1991_Signetics_IC013_Data_Communication_Products 1991 Signetics IC013 Data Communication Products
User Manual: 1991_Signetics_IC013_Data_Communication_Products
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Signetics
Philips Components
PHILIPS
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PHILIPS
Data Communication
Products
Philips Components
PHILIPS
Signetics reserves the right to make changes, without notice, in the products, including
circuits, standard cells, and/orsoftware, described or contained herein in order to improve
design andlor performance. Signetics assumes no responsibility or liability for the use
of any of these products, conveys no license or title under any patent, copyright, or mask
work rightto these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise
specified. Applications that are described herein for any of these products are forillustrative purposes only. Signetics makes no representation or warranty that such applications
will be suitable for the specified use without further testing or modification.
LIFE SUPPORT APPLICATIONS
Signetics Products are not designed for use in life support appliances, devices, or
systems where malfunction of a Signetics Product can reasonably be expected to result
in a personal injury. Signetics customers using or selling Signetics Products for use in
such applications do so at their own risk and agree to fully indemnify Signetics for any
damages resulting from such improper use or sale.
Signetics registers eligible circuits under
the Semiconductor Chip Protection Act.
© Copyright 1991 NAPC.
All rights reserved.
Philips Components-Signetics
Preface
Data Communication Products
Applications for our data communications products continue to grow as the microprocessor-based systems prolnerate. In addition to servicing the traditional function. ~
recognize the need to offer improved features and performance while at the same time
we retain a cost-effective product. To achieve this goal we have installed manufacturing
capabilitythattakes advantage of our technology development effort particularly in the
CMOS arena. The new products resulting from this activity will not only complement
the existing family. but will also allow the designer to enhance the system capabilities
and performance very economically.
Our entire focus in Data Communications is to continue to playa major role in the market through constant attention to performance and economics using innovation and
technology development.
January 1991
iii
Philips Components-Signetics
Product Status
Data Communication Products
DEFINITIONS
Data Sheet
Identification
Product Status
Definition
This dala sheet contains the design target or goal
Objective Specification
Formative or In Design
Preliminary Specificalion
Preproduction Product
This data sheet contains preliminary data and
supplementary data will be published at a later date.
Signetics reserves the right to make changes at any lime
without notice In order to irrprove design and supplylhe best
possible product.
Product Specification
Full Production
reserves the right to make changes at anytime without notice
specHications for product development. Specifications may
change In any manner without notice.
This data sheet contains Final Specifications. Signetics
January 1991
iv
in order to irrprove design and supply the best possible
product.
Philips Components-Signetics
Ordering
Information
Data Communication Products
DATA COMMUNICATION PRODUCTS PART NUMBERING SYSTEM
Example:
Mno __
~,"
•••"
Identifier - Always SC
seN
~ ~ 4
Jj
Jt
ProcesS/Power Variation
N = N - Channel
C=C-MOS
B = Bipolar
C 6 N 4 8
~""="'
14, 16,20,24,28,40,48, etc.
Package
A = Plastic Leaded Chip Carrier (PLCC)
F = Hermetic Cerdip
I = Hermetic Ceramic DIP
Basic Part Number
See individual data sheets
Temperature
C = OOC to 70°C
(Commercial)
A = -40°C to +80oC
(Automotive)
M = -55°C to +125°C
(Military)
P = -20°C to +70°C
(Philips)
Example:
Timing Variation
Spd Sym
Spd Sym
01 1
21 1
02 2
22 2
03 3
23 3
04 4
24 4
05 5
25 5
06 6
26 6
27 7
07 7
08 8
28 8
29 9
09 9
10 A
30 0
11 B
31 1
12 C
32 2
13 D
33 3
14 E
34 4
15 F
35 5
16 6
36 6
17 7
37 7
18 8
38 8
19 9
39 9
20 0
40 0
Unless otherwise noted.
NE 553 7N
- -,- T'-_____
Package Description:
A
Plastic Leaded Chip Carriers (PLCC)
D
Plastic SO Packages
F
Hermetic Cerdip
G
Hermetic Chip Carriers - Leadless
H
Headers
N
Plastic DIL
P
Pin Grid Array - Hermetic
W = Hermetic Cerpac
Y = Hermetic Chip Carrier - Leaded Square (Cerpac)
Device Number
Device
NE
SE
SA =
January 1991
Family and Temperature Range Prefix
0 to +70 oC
-55°C to +125°C
-40°C to +80oC
v
N = Plastic DIL
P = Pin Grid Array Hermetic
Spd
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
Sym
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
Philips Components-Signetics
Contents
Data Communication Products
Preface ............................................................................................. iii
Product Status .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. iv
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Section 1 - Quality and Reliability
Quality and Reliability ........ : ........................... , ........................................ 3
Section 2 - Digital Data Communication Products
SCN2651
Programmable Communications Interface (PCI) ..................................... 9
SCN26521SCN68652
Multi-Protocol Communications Controller (MPCC) ................................. 25
Enhanced Programmable Communications Interface (EPCI) .......................... 45
SCN2661/68661
SCN2681
Dual Asynchronous ReceiverfTransmitter (DUART) ., ............................... 65
SCN2681T
Dual Asynchronous ReceiverfTransmitter (DUART) ................................. 84
Dual Asynchronous ReceiverfTransmitter (DUART) ................................. 96
SCN68681
SCC2691
Universal Asynchronous ReceiverfTransmitter (UART) .............................. 116
Dual Asynchronous ReceiverfTransmitter (DUART) ................................ 132
SCC2692
Dual Asynchronous ReceiverfTransmitter (DUART) ................................ 154
SC26C92
SCC68692
Dl,lal Asynchronous ReceiverfTransmitter (DUART) ................................ 178
Dual Asynchronous ReceiverfTransmitter (DUART) ................................ 199
SC68C92
Quad Universal Asynchronous ReceiverfTransmitter (QUART) ....................... 221
SC26C941SC68C94
Enhanced Octal Universal Asynchronous ReceiverfTransmitter (Octal UART) ............ 247
SCC2698B
Dual Universal Serial Communications Controller (DUSCC) .......................... 267
SCN26562
Dual Universal Serial Communications Controller (DUSCC) .......................... 283
SC26C562/SC68C562
SCN68562
Dual Universal Serial Communications Controller (DUSCC) .......................... 297
Input/Output Processor (lOP) ................................................. 348
SC26C460
Section 3 - Wired Data Communication Products
AM26LS30
Dual Differential RS-422 Party Line/Quad Single-Ended RS-423 Line Driver .............
AM26LS31
Quad High-Speed Differential Line Driver ........................................
AM26LS32/AM26LS33
Quad High-Speed Differential Line Receivers .....................................
AM26LS32B
Quad High-Speed Differential Line Receivers .....................................
MC145406
EIA-232-DN.28 Driver/Receiver ...............................................
MC1488
Quad Line Driver ...........................................................
MC1489/1489A
Quad Line Receivers ........................................................
NE5080
High-Speed FSK Modem Transmitter ...........................................
NE5081
High-Speed FSK Modem Receiver .............................................
NE5170
Octal Line Driver .................... '" ....................................
NE5180/5181
Octal Differential Line Receivers .......................... , ....................
371
378
381
385
388
393
397
400
404
408
414
Section 4 - Local Area Network Products
NE502A
Ethernet EncoderlDecoder ................................................... 421
NE8392A
Coaxial Transceiver Interface for EthernetlThin Ethernet ............................ 437
EtherStart™ Ethernet Controller ............................................... 446
NE86950
Section 5 - Package Outlines
Package Outlines ............................................................................... 479
Section 6 - Sales Representatives and Distributor Offices
Office Listing ................................................................................... 493
January 1991
vi
Philips Components-Signetics
Data Communication Products
Section 1
Quality and Reliability
Philips Components-Signetics
Quality and Reliability
Data Communication Products
SIGNETICS QUALITY
Signetics has put together winning processes
for manufacturing. Our standard is zero
defects, and current customer quality
statistics demonstrate our commitment to this
goal.
The data communications produced in the
Standard Products Group must meet rigid
criteria as defined by our design rules and as
evaluated with a thorough product
characterization and quality process. The
capabilities of our manufacturing process are
measured and the results evaluated and
reported through our corporate-wide QAOS
data base system. The SURE (Systematic
Uniform Reliability Evaluation) program
monitors the performance of our product in a
variety of accelerated environmental stress
conditions. All of these programs and
systems are intended to prevent
product-related problems and to inform our
customers and employees of our progress in
achieving zero defects.
RELIABILITY BEGINS WITH THE
DESIGN
Quality and reliability must begin with design.
No amount of extra testing or inspection will
produce reliable ICs from a design that is
inherently unreliable. Signetics follows very
strict design and layout practices with its
circuits. To eliminate the possibility of metal
migration, current density in any path cannot
exceed 2 x 105 ampslcm 2 . Layout rules are
followed to minimize the possibility of shorts,
circuit anomalies, and SCR type latch-up
effects. Numerous ground-to-substrate
connections are required to ensure that the
entire chip is at the same ground potential,
thereby precluding internal noise problems.
PRODUCT CHARACTERIZATION
Before a new design is released, the
characterization phase is completed to insure
that the distribution of parameters resulting
from lot-to-Iot variations is well within
specified limits. Such extensive
January 1991
characterization data also provides a basis
for identifying unique application-related
problems which are not part of normal
data sheet guarantees. Characterization
takes place from -5S oC to + 125°C and at ±
10% supply Voltage.
monitor. Samples are selected that represent
all generic product groups in all wafer
fabrication and assembly locations.
THE LONG-TERM AUDIT
One-hundred devices from each generic
family are subjected to each of the following
stresses every eight weeks:
QUALIFICATION
Formal qualification procedures are required
for all new or changed products, processes
and facilities. These procedures ensure the
high level of product reliability our customers
expect. New facilities are qualified by
corporate groups as well as by the quality
organizations of specific units that will
operate in the facility. After qualification,
products manufactured by the new facility are
subjected to highly accelerated environmental
stresses to ensure that they can meet
rigorous failure rate requirements. New or
changed processes are similarly qualified.
• High Temperature Operating Ufe:
T J = 150°C, 1000 hours, static biased or
dynamic operation, as appropriate (worst
case bias configuration is chosen)
QA05 - QUALITY DATA BASE
REPORTING SYSTEM
THE SHORT-TERM MONITOR
The QAOS data reporting system collects the
results of product assurance testing on all
finished lots and feeds this data back to
concerned organizations where appropriate
action can be taken. The QAOS reports EPQ
(Estimated Process Quality) and AOO
(Average Outgoing Quality) results for
electrical, visual/mechanical, hermeticity, and
documentation audits. Data from this system
is available upon request.
THE SURE PROGRAM
The SURE (Systematic Uniform Reliability
Evaluation) program audits/monitors products
from all Signetics' divisions under a variety of
accelerated environmental stress conditions.
This program, first introduced in 1964, has
evolved to suit changing product complexities
and performance requirements.
The SURE program has two major functions:
Long-term accelerated stress performance
audit and a short-term accelerated stress
3
• High Temperature Storage: T J = 150°C,
1000 hours
• Temperature Humidity Biased Life: 85°C,
85% relative humidity, 1000 hours,
static biased
• Temperature Cycling (Air-to-Air): -5S O C to
+lS0°C, 1000 cycles
Every other week a 50-piece sample from
each generic family is run to 168 hours of
pressure pot (lSpsig, 121°C, 100% saturated
steam).
In addition, each Signetics assembly plant
performs SURE product monitor stresses
weekly on each generic family and molded
package by pin count and frame type.
Fifty-piece samples are run on each stress,
pressure pot to 96 hours.
SURE REPORTS
The data from these test matrices provides a
basic understanding of product capability, an
indication of major failure mechanisms and
an estimated failure rate resulting from each
stress. This data is compiled periodically and
is available to customers upon request.
Many customers use this information in lieu
of running their own qualification tests,
thereby eliminating time-consuming and
costly additional testing.
Philips Components-Signetics Data Communication Products
Quality and Reliability
RELIABILITY ENGINEERING
In addition to the product performance
monitors encompassed in the Data
Communication SURE program, Signetics'
Corporate and Division Reliability
Engineering departments sustain a broad
range of evaluation and qualification
activities.
Those of you who invest in cosUy test
equipment and engineering to assure that
incoming products meet your specifications
have a special understanding of the cost of
ownership. And your cost does not end there;
you are also burdened with inflated
inventories, lengthened lead times and more
rework.
Included in the engineering process are:
• Evaluation and qualification of new or
changed materials, assemblylwafer-fab
processes and equipment, product
designs, facilities and subcontractors
• Device or generic group failure rate studies
• Advanced environmental stress
development
• Failure mechanism characterization and
corrective action/prevention reporting
The environmental stresses utilized in the
engineering programs are similar to those
utilized for the SURE monitor; however, more
highly-accelerated conditions and extended
durations typily the engineering projects.
Additional stress systems such as biased
pressure pot, power-temperature cycling, and
cycle-biased temperature-humidity, are also
included in the evaluation programs.
SIGNETICS UNDERSTANDS
CUSTOMERS'NEEDS
Signetics has long had an organization of
quality professionals, inside all operating
units, coordinated by a corporate quality
department. This broad decentralized
organization provides leadership, feedback,
and direction fo achieving a high level of
quality. Special programs are targeted on
specific quality issues. For example, in 1978
a program to reduce electrically defective
units for a major automotive manufacturer
improved outgoing quality levels by an order
of magnitude.
In 1980 we recognized that in order to
achieve outgoing levels on the order of
100ppm (parts per million), down from an
industry practice of 10,OOOppm, we needed to
supplement our traditional quality programs
with one that encompassed all activities and
all levels of the company. Such
unprecedented low defect levels could only
be achieved by contributions from all
employees, from the Rand D laboratory to
the shipping dock. In short, from a program
that would effect a total cultural change within
Signetics in oUf'attitude toward quality.
QUALITY PAYS OFF FOR OUR
CUSTOMERS
Signetics' dedicated programs in product
quality improvement, supplemented by close
working relationships with many of our
customers, have improved outgoing product
quality more than twenty-fOld since 1980,
Today, many major customers no longer test
Signetics circuits, Incoming product moves
directly from the receiving dock to the
production line, greaUy accelerating
throughput and reducing inventories. Other
customers have pared significantly the
amount of sampling done on our products.
Others are beginning to adopt these
cost-saving practices.
We closely monitor the electrical, visual, and
mechanical quality of all our products and
review each return to find and correct the
cause. Since 1981, over 90% of our
customers report a significant improvement in
overall quality (see Figure 1).
FAILURE ANALYSIS
The SURE Program and the Reliability
Engineering Program both include failure
analysis activities and are complemented by
corporate, divisional and plant failure analysis
departments. These engineering units
provide a service to our customers who
desire detailed failure analysis support, who
in turn provide Signetics with the technical
understanding of the failure modes and
mechanisms actually experienced in service.
This information is essential in our ongoing
effort to accelerate and improve our
understanding of product failure mechanisms
and their prevention.
Goal
-i":n~H'7'7";~+ 125
ZERO DEFECTS PROGRAM
In recent years, United States industry has
increaSingly demanded improved product
qUality. We at Signetics believe that the
customer has every right to expect quality
products from a supplier. The benefits which
are derived from quality products can be
summed up in the words, lower cos! of
_
ELECTRICAL EPQ
~ MECHANICAL EPa
ownership.
Figure 1. Signetics Quality Performance
January 1991
4
Philips Components--{)ignetics Data Communication Products
Quality and Reliability
ONGOING QUALITY PROGRAM
The quality improvement program at
Signetics is based on "Do It Right the First
lime" The intent of this innovative program is
to change the perception of Signetics'
employees that somehow quality is solely a
manufacturing issue where some level of
defects is inevitable. This attitude has been
replaced by one of acceptance of the fact that
all errors and defects are preventable, a point
of view shared by all technical and
administrative functions equally.
This program extends into every area of the
company, and more than 40 quality
improvement teams throughout the
organization drive its ongoing refinement and
progress.
Key components of the program are the
Quality College, the "Make Certain" Program,
Corrective Action Teams, and the Error
Cause Removal System.
The core concepts of doing it right the first
time are embodied in the four absolutes of
quality:
1. The definition of quality is conformance to
requirements.
2. The system to achieve quality
improvement is prevention.
3. The performance standard is zero
defects.
4. The measurement system is continuous
improvement.
QUALITY COLLEGE
Almost continously in session, Quality
College is a prerequisite for all employees.
The intensive curriculum is built around the
four absolutes of quality; colleges are
conducted at company facilities throughout
the world.
"MAKING CERTAIN" ADMINISTRATIVE QUALITY
IMPROVEMENT
Signetics' experience has shown that the
largest source of errors affecting product and
service quality is found in paperwork and in
other administrative functions. The "Make
Certain" program focuses the attention of
management and administrative personnel on
error prevention, beginning with each
employee's own actions.
This program promotes defect prevention in
three ways: by educating employees as to
the impact and cost of administrative errors,
by changing attitudes from accepting
occasional errors to one of accepting a
personal work standard of zero defects, and
January 1991
by providing a formal mechanism for the
prevention of errors.
CORRECTIVE ACTION TEAMS
Employees with the perspective, knowledge,
and necessary skills to solve a problem are
formed into ad hoc groups called Corrective
Action Teams. These teams, a major force
within the company for quality improvement,
resolve administrative, technical and
manufacturing issues.
QUALITY AND RELIABILITY
ORGANIZATION
Quality and reliability professionals at the
divisional level are involved with all aspects
of the product, from design through every
step in the manufacturing process, and
provide product assurance testing of outgoing
product. A separate corporate-level group
provides direction and common facilities.
Quality and Reliability Functions:
• Manufacturing quality control
• Product assurance testing and qualification
ECR SYSTEM (ERROR CAUSE
REMOVAL)
• Laboratory facilities - failure analysis,
chemical, metallurgy, thin film, oxides
The ECR System permits employees to
report to management any impediments to
doing the job right the first time. Once such
an impediment is reported, management is
obliged to respond promptly with a corrective
program. Doing it right the first time in all
company activities produces lower cost of
ownership through defect prevention.
• Environmental stress testing
PRODUCT QUALITY PROGRAM
To reduce defects in outgoing products, we
created the Product Quality Program. This is
managed by the Product Engineering
Council, composed of the top product
engineering and test professionals in the
company. This group:
1. Sets aggressive product quality
improvement goals:
• Quality and reliability engineering
• Customer liaison
COMMUNICATING WITH EACH
OTHER
For information on Signetics' quality
programs or for any question concerning
product quality, the field salesperson in your
area will provide you with the quickest access
to answers. Or, write on your letterhead
directly to the corporate VP of quality at the
corporate address shown at the back of this
manual.
2. provides corporate-level visibility and
focus on problem areas:
We are dedicated to preventing defects.
When product problems do occur, we want to
know about them so we can eliminate their
causes. Here are some ways we can help
each other:
3. serves as a corporate resource for any
group requiring assistance in quality
improvement; and
• Provide us with one informed contact within
your organization. This will establish
continuity and build confidence levels.
4. drives quality improvement projects.
• Periodic face-to-face exchanges of data
and quality improvement ideas between
your engineers and ours can help prevent
problems before they occur.
As a result of this aggressive program, every
major customer who reports back to us on
product performance is reporting significant
progress.
VENDOR CERTIFICATION
PROGRAM
Our vendors are taking ownership of their
own product quality by establishing improved
process control and inspection systems. They
subscribe to the zero defects philosophy.
Progress has been excellent.
Through intensive work with vendors, we
have improved our lot acceptance rate on
incoming materials as shown in Figure 2.
Simultaneously, waivers of incoming material
have been eliminated.
5
• Test correlation data is very useful.
line-pull information and field failure
reports also help us improve product
performance.
• Provide us with as much specific data on
the problem as soon as possible to speed
analysis and enable us to take corrective
action.
• An advance sample of the devices in
question can start us on the problem
resolution before physical return of
shipment.
This teamwork with you will allow us to
achieve our mutual goal of improved product
quality.
Philips Components-Signetics Data Communication Products
Quality and Reliability
LOT ACCEPTANCE RATE
*1986 Decline - New lead frame supplier
NOTE: Water. Included ttwough 1987.
Figure 2, Incoming Direct Materials Quality
MANUFACTURING: DOING IT
RIGHT THE FIRST TIME
In dealing with the standard manufacturing
flows, it was recognized that significant
improvement would be achieved by "doing
every job right the first time", a key concept of
the quality improvement program, Key
changes included such things as
January 1991
implementing 100% temperature testing on
all products as well as upgrading test
handlers to insure 100% pOSitive binning.
Some of the other changes and additions
were to tighten the outgoing QA lot
acceptance criteria to the tightest in the
industry, with zero defect lot acceptance
sampling across all three temperatures.
6
The achievements resulting from the
improved process flow have helped Signetics
to be recognized as the leading quality
supplier of data communications. These
achievements have also led to our
participation in several Ship-to-Stock
programs, which our customers use to
eliminate incoming inspection. Such
programs reduce the user cost of ownership
by saving both time and money.
Philips Components-Signetics
Section 2
Digital Data
Communication Products
Data Communication Products
INDEX
Programmable Communications Interface (PCI)
Multi-Protocol Communications Controller (MPCC) ....
Enhanced Programmable Communications Interface (EPCI) .
Dual Asynchronous ReceiverlTransmitter (DUART)
Dual Asynchronous ReceiverlTransmitter (DUART) .. .
Dual Asynchronous ReceiverlTransmitter (DUART) ... .
Universal Asynchronous ReceiverlTransmitter (UART)
Dual Asynchronous ReceiverlTransmitter (DUART) .
Dual Asynchronous ReceiverlTransmitter (DUART)
Dual Asynchronous ReceiverlTransmitter (DUART) .
Dual Asynchronous ReceiverlTransmitter (DUART) .
Quad Universal Asynchronous ReceiverlTransmitter (QUART) .
Enhanced Octal Universal Asynchronous Receiver/Transmitter
(Octal UART)
................ .
Dual Universal Serial Communications Controller (DUSCC)
SCN26562
SC26C5621SC68C562 Dual Universal Serial Communications Controller (DUSCC)
Dual Universal Serial Communications Controller (DUSCC)
SCN68562
SC26C460
Input/Output Processor (lOP)
SCN2651
SCN26521SCN68652
SCN2661/SCN68661
SCN2681
SCN2681T
SCN68681
SCC2691
SCC2692
SC26C92
SCC68692
SC68C92
SC26C94/SC66C94
SCC2698B
9
25
45
65
84
96
116
132
154
178
199
221
247
267
283
297
348
Philips Components-5ignetics
Document No.
853-{)083
ECN No.
77351
Date of Issue
February 20, 1985
Status
Product Specification
SCN2651
Programmable
communications interface (PCI)
Data Communication Products
DESCRIPTION
The Signetics SCN2651 PCI is a
universal synchronous/asynchronous
data communications controller chip
designed for microcomputer systems. It
interfaces directly to the Signetics
SCN2650 microprocessor and may be
used in a polled or interrupt driven
system environment. The SCN2651
accepts programmed instructions from
the microprocessor and supports many
serial data communication disciplines,
synchronous and asynchronous, in the
full or half-duplex mode.
The PCI serializes parallel data
characters received from the
microprocessor for transm ission.
Simultaneously, it can receive serial
data and convert it into parallel data
characters for input to the
microcomputer.
The SCN2651 contains a baud rate
generator which can be programmed to
either accept an external clock or to
generate internal transmit or receive
clocks. Sixteen different baud rates can
be selected under program control when
operating in the internal clock mode.
- Automatic SYN or DLE-SYN
insertion
- SYN or DLE stripping
- Odd,
even, or no parity
- Local or remote maintenance
loopback mode
- Baud rate: DC to 1Mbps (1Xclock)
• Asynchronous operation
- 1, 1-112 or 2 stop bits
• Computer to computer links
• Serial peripherals
PIN CONFIGURATIONS
01
DO
- Line break detection and
generation
VCC
RxC
- False start bit detection
OTR
- Automatic serial echo mode
RTS
- Local or remote maintenance
loopback mode
OSR
RESET
- Baud rate: DC to 1Mbps
(1X clock)
DC to 62.5kbps (16X clock)
DC to 15.625kbps
(64X clock)
BRCLK
AD
OTHER FEATURES
• Full or half duplex operation
• Synchronous operation
• TIL compatible inputs and outputs
- Transparent or non-transparent
mode
• Remote data concentrators
- Parity, overrun and framing error
detection
FEATURES
- Internal character synchronization
• Front-end processors
- Odd, even, or no parity
• Internal or external baud rate clock
- Single or double SYN operation
• Network processors
- 5- to 8-bit characters
The PCI is constructed using Signetics
n-channel silicon gate depletion load
technology and is packaged in a 28-pin
DIP.
- 5- to 8-bit characters
APPLICATIONS
• Intelligent terminals
• 16 internal rates - 50 to 19,200 baud
• Double buffered transmitter and
receiver
• Single 5V power supply
• No system clock required
• 28-pin dual in-line package
9
RIW
TOP VIEW
Product Specification
Philips Components-Signetics Data Communication Products
Programmable communications interface (PCI)
SCN2651
ORDERING CODE
Vcc=5V ±5%
PACKAGES
Commercial
Automotive
D"C to +7D"C
-4D"C to +85"C
CERDIP
SCN2651CC1 F28
SCN2651CA1F28
Plastic DIP
SCN2651CC1N28
Not available
Plastic LCC
SCN2651CC1A28
Not available
BLOCK DIAGRAM
t--
DATA BUS
IlO-O7
(27,28, I, 2,
5,6,7,8)
RE SET
A"
A,
RIW
t:E
(21)
(12)
(Ill)
(13)
(11)
v
t--
DATA BUS
BUFFER
MODE REGISTER 1
Til:
~
~
"
STATUS REGISTER
-
BAUD RATE
GENERATOR
AND
CLOCK CONTROL
I--
f--
CTS
February 20, 1985
(22)
(23)
(24)
(19)
TxD
MODEM
CONTROL
i
RECEIVER
~
(16)
_1m
+
~
(25)
!ITS"
IJTR
15
TRANSMIT DATA
HOLDING REGISTER
TRANSMIT
SHIFT REGISTER
KX
DllR
TRANSMITTER
,-
(20)
(0)
DLE REGISTER
y--
v
BRCLK
SYN 2 REGISTER
/"-
MODE REGISTER 2
COMMAND REGISTER
SYN 1 REGISTER
I
I
t
OPERATION CONTROL
SYNIDLE CONTROL
v
2J
18
10
I
I
(14)
Rxl!DV
RECEIVE
SHIFT REGISTER
RECEIVE DATA
HOLDING REGISTER
~
RxD
Product Specification
Philips Components-Signetics Data Communication Products
Programmable communications interface (PCI)
SCN2651
ABSOLUTE MAXIMUM RATINGS1
PARAMETER
Operating ambient temperature 2
Storage temperature
All voltages with respect to ground3
RATING
UNIT
Note 4
-65 to +150
-0.5 to +6.0
°C
°C
V
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on + 150°C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effect of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range
and operating supply range.
DC ELECTRICAL CHARACTERISTICS1, 2, 3
LIMITS
SYMBOL
PARAMETER
Min
TEST CONDITIONS
Typ
Max
UNIT
0.8
V
V
0.4
V
V
Input voltage
Low
High
V,L
V,H
2.0
Output voltage
Low
High
VOL
VOH
Input leakage current
I'L
3·State output feakage current
IOL = 1.6mA
IOH = -100fIA
2.4
V,N = 0 to 5.25V
-10
10
fIA
Vo =4.0V
Vo =0.45V
-10
-10
10
10
fIA
fIA
Data bus high
Data bus low
ILH
ILL
Power supply current
150
mA
Icc
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range
and operating supply range.
2. All voltage measurements are referenced to ground. All time measurements are at the 50% level for inputs (except tBAH and tBAd and at
0.8V and 2.0V for outputs. Input levels for testing are 0.45V and 2.4V.
3. Typical values are at +25°C, typical supply voltages and typical processing parameters.
CAPACITANCE TA = 25°C, Vee = OV
SYMBOL
I
Capacitance
C,N
COUT
C,,o
I
Input
Output
Input/Output
February 20, 1985
PARAMETER
I
I
TEST CONDITIONS
fe = 1MHz
Unmeasured pins tied to ground
11
I
I
I
LIMITS
Min
I
I
Typ
I
I
Max
20
20
20
J
I
I
UNIT
pF
pF
pF
Product Specilication
Philips Components-Signetics Data Communication Products
Programmable communications interface (PCI)
SCN2651
AC ELECTRICAL CHARACTERISTICS1, 2, 3
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
UNIT
Pulse width
tREs
leE
Reset
Chip enable
1000
300
ns
ns
20
20
ns
ns
ns
ns
ns
ns
ns
ns
Set-up and hold time
tAS
tAH
les
leH
los
tOH
tRXS
tRxH
Address setup
Address hold
RIW control setup
RIW control hold
Data setup lor write
Data hold lor write
RX data setup
RX data hold
too
tOF
icED
"CE to "CE delay
20
20
225
0
300
350
Data delay time lor read
Data bus Iloating time lor read
Cl = 100pF
Cl = 100pF
250
150
ns
ns
ns
5.0736
1.0
MHz
MHz
700
Input clock frequency
IBR~
Baud rate generator
!xCor"RXC
1.0
dc
leR{
leRl
tRITH
tRITl6
Baud rate high
Baud rate low
!xC or"RXC high
!xC or"RXC low
70
70
500
500
tTxO
tTes
TxD delay Irom lalling edge of !xC
Skew between TxD changing and lalling edge
01 !xC output"
fRIT
5.0666
Clock width
Cl = 100pF
CL = 100pF
ns
ns
ns
ns
650
0
ns
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specilied. See ordering code table lor applicable temperature range
and operating supply range.
2. All voltage measurements are relerenced to ground. All time measurements are at the 50% level lor inputs (except leRH and tBRd and at
0.6Vand 2.0V lor outputs. Input levels lor testing are 0.45V and 2.4V.
3. Typical values are at +25°C, typical supply voltages and typical processing parameters.
4. Parameter applies when internal transmitter clock is used.
5. Under test conditions 01 5.0666MHz, IBRG, leRH, and tBRl measured at VIH and Vil respectively.
6. tRIT and tR/TL shown lor all modes except localloopback. For localloopback mode IRIT = 0.7MHz and tRiTl = 700ns min.
February 20, 1985
12
Product Specification
Philips Components-Signetics Data Communication Products
SCN2651
Programmable communications interface (PCI)
PIN DESCRIPTION
PIN NO.
27, 28, 1, 2, 5-<3
21
12,10
13
11
22
24
23
17
16
18
9
25
19
3
15
14
20
26
4
Table 1.
BAUD RATE
SYMBOL
NAME AND FUNCTION
TYPE
00-0 7
8-bit data bus
Reset
Internal register select lines
Read or write command
Chip enable input
Data set ready
Data terminal ready
Request to send
Clear to send
Data carrier detected
Transmitter empty or data set change
Transmitter clock
Receiver clock
Transmitter data
Receiver data
Transmitter ready
Receiver ready
Baud rate generator clock
+5V supply
Ground
1/0
I
I
I
I
I
RESET
Ao-A,
row
IT
1JSR
DTR
"RTS
CTS
lYCU
TXE'mIUSCR"G
TXC
J:1xC
TxD
RxD
TXROY
RXRlJ'i'
BRCLK
Vee
GND
0
0
I
I
0
1/0
1/0
0
I
0
0
I
I
I
Baud Rate Generator Characteristics Crystal
Frequency = 5.0688MHz
THEORETICAL
FREQUENCY
16XCLOCK
ACTUAL
FREQUENCY
16XCLOCK
PERCENT
ERROR
0.8KHz
1.2
1.76
2.152
2.4
4.8
9.6
19.2
28.8
32.0
38.4
57.6
76.8
115.2
153.6
307.2
0.8KHz
1.2
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8
-
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200'
and generates appropriate signals to various internal sections to control the overall device operation.
It contains read and write circuits to permit communications with the microprocessor via the data bus
and contains mode registers 1 and 2, the command
register, and the status register. Details of register
addressing and protocol are presented in the PCI
programming section of this data sheet.
Timing
The PCI contains a baud rate generator (BRG)
which is programmable to accept external transmit
or receive clocks or to divide an external clock to
perlorm data communications. The unit can generate 16 commonly used baud rates, anyone of
which can be selected for full-duplex operation.
See Table 1.
Receiver
The receiver accepts serial data on the RxO pin,
converts this serial input to parallel format, checks
for bits or characters that are unique to the communication technique and sends an "assembled"
character to the CPU.
Transmitter
DIVISOR
6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16
0.016
-
0.253
-
-
-
3.125
NOTE:
'Error at 19200 can be reduced to zero by using crystal frequency 4.9152MHz.
16X clock is used in asynchronous mode. In synchronous mode, clock multiplier is lX.
The transmitter accepts parallel data from the
CPU, converts it to a serial bit stream, inserts the
appropriate characters or bits (based on the communication technique) and outputs acomposite serial stream of data on the TxD output pin.
Modem Control
The modem control section provides interfacing for
three input signals and three output signals used
for "handshaking" and status indication between
the CPU and a modem.
SYN/DLE Control
This section contains control circuitry and three
8-bit registers storing the SYN 1, SYN2, and OLE
characters provided by the CPU. These registers
are used in the synchronous mode of operation to
provide the characters required for synchronization, idle fill and data transparency.
INTERFACE SIGNALS
BLOCK DIAGRAM
The PCI consists of six major sections.
These are the transmitter, receiver, timing,
operation control, modem control and SYNI
OLE control. These sections communicate
with each other via an internal data bus and
February 20,1985
an internal control bus. The internal data
bus interlaces to the microprocessor data
bus via a data bus buffer.
Operation Control
This functional block stores configuration
and operation commands from the CPU
13
The PCI interlace signals can be grouped into two
types: the CPU-related signals (shown in Table 2),
which interface the SCN2651 to the microprocessor system, and the device-related signals (shown
in Table 3), which are used to interlace to the communications device or system.
Philips Components-Signetics Data Communication Products
Product Specification
Programmable communications interface (PCI)
Table 2.
SCN2651
CPU-Related Signals
PIN NAME
PIN NO.
INPUT/OUTPUT
Vee
26
I
+5V supply input
GND
4
I
Ground
RESET
21
I
A high on this input performs a master reset on the SCN2651. This signal asynchronously
terminates any device activity and clears the mode, command and status registers. The
device assumes the idle state and remains there until initialized with the appropriate control
words.
A,-Ao
10,12
13
11
I
I
I
D7- DO
8,7,6,5
2,1,28,27
110
TXRO'i"
15
0
RX110Y
14
0
TXE'F1T/
18
0
Address lines used to select internal PCI registers.
Read command when low, write command when high.
Chip enable command. When low, indicates that control and data lines to the PCI are valid
and that the operation specified by the 'RW, A, and Ao inputs should be performed. When
high, places the Do-D7 lines in the 3-State condition.
8-bit, three-state data bus used to transfer commands, data and status between PCI and
the CPU. Do is the least significant bit, 0 7 the most significant bit.
This output is the complement of status register bit SRO. When low, it indicates that the
transmit data holding register (THR) is ready to accept a data character from the CPU. It
goes high when the data character is loaded. This output is valid only when the transmitter
is enabled. It is an open drain output which can be used as an interrupt to the CPU.
This output is the complement of status register bit SR 1. When low, it indicates that the
receive data holding register(RHR) has a character ready for inputto the CPU. Itgoes high
when the RHR is read by the CPU, and also when the receiver is disabled. It is an open
drain output which can be used as an interrupt to the CPU.
This output is the complement of status register bit SR2. When low, it indicates that the
transmitter has completed serialization of the last character loaded by the CPU, or that a
change of state of the DSR or UCU inputs has occurred. This output goes high when the
status register is read by the CPU, if the TxEMT condition does not exist. Otherwise, the
THR must be loaded by the CPU for this line to go high. It is an open drain output which
can be used as an interrupt to the CPU.
RIW
CE
US'CHG
OPERATION
The lunctional operation of the SCN2651 is programmed by a set of control words supplied by
the CPU. These control words specify items
such as synchronous or asynchronous mode,
baud rate, number of bits per character, etc.
The programming procedure is described in the
PCI programming section of the data sheet.
After programming, the PCI is ready to perform
the desired communications functions. The receiver performs serial to parallel conversion of
data received from a modem or equivalent device. The transmitter converts parallel data received from the CPU to a serial bit stream.
These actions are accomplished within the
framework specified by the control words.
Receiver
The SCN2651 is conditioned to receive data
when the UCU input is low and the RxEN bit in
the command register is true. In the asynchronous mode, the receiver looks for a high to low
transition of the start bit on the RxO input line.
If a transition is detected, the state of the RxO
line is sampled again after a delay of one-half
of a bit-time. If RxO is now high, the search for
February 20, 1985
FUNCTION
a valid start bit is begun again. If RxO is still low,
a valid start bit is assumed and the receiver
continues to sample the input line at one bit time
intervals until the proper number of data bits,
the parity bit, and one stop bit(s) have been assembled. The data is then transferred to the receive data holding register, the RxROY bit in the
status register is set, and the RX110Y output is
asserted. If the character length is less than 8
bits, the high order unused bits in the holding
register are set to zero. The parity error, framing error, and overrun error status bits are
strobed into the status register on the poSitive
going edge of ~ corresponding to the received character boundary. If a break condition
is detected (RxO is low for the entire character
as well as the stop bit[s]), only one character
consisting of all zeros (with the FE status bit
set) will be transferred to the holding register.
The RxO input must return to a high condition
before a search for the next start bit begins.
When the PCI is initialized into the synclironous
mode, the receiver first enters the hunt mode on
a 0 to 1 transition of RxEN (CR2). In this mode,
as data is shifted into the receiver shift register
a bit at a time, the contents of the register are
14
compared to the contents of the SYN 1 register.
If the two are not equal, the next bit is shifted in
and the comparison is repeated. When the two
registers match, the hunt mode is terminated
and character assembly mode begins. If single
SYN operation is programmed, the SYN detect
status bit is sel. If double SYN operation is programmed, the first character assembled after
SYN 1 must be SYN2 in order for the SYN detect bit to be set. Otherwise, the PCI returns to
the hunt mode. (Note that the sequence
SYN1-SYN1-SYN2 will not achieve synchronization.) When synchronization has been
achieved, the PCI continues to assemble characters and transfer them to the holding register,
setting the RxROY status bit and asserting the
RX110Y output each time a character is transferred. The PE and OE status bits are set as appropriate. Further receipt of the appropriate
SYN sequence sets the SYN detect status bit.
If the SYN stripping mode is commanded, SYN
characters are not transferred to the Holding
Register. Note that the SYN characters used
to establish initial synchronization are not
transferred to the holding register in any case.
Philips Components-Signetics Data Communication Products
Product Specification
SCN2651
Programmable communications interface (PCI)
Table 3.
Device-Related Signals
PIN NAME
BRCLK
PIN NO.
INPUT/OUTPUT
20
FUNCTION
5.06SSMHz clock input to the internal baud rate generator. Not required if external receiver
and transmitter clocks are used.
25
I/O
Receiver clock. If external receiver clock is programmed, this input controls the rate at
which the character is to be received. Its frequency is 1X, 16X or 64X the baud rate, as
programmed by mode register 1. Data are sampled on the rising edge olthe clock. If internal receiver clock is programmed, this pin becomes an output at 1X the programmed baud
rate ..
9
110
Transmitter clock. If external transmitter clock is programmed, this input controls the rate
at which the character is transmitted. Its frequency is 1X, 16X or64X the baud rate, as programmed by mode register 1. Thetransmitted data changes on the falling edge olthe clock.
If internal transmitter clock is programmed, the pin beccmes an output at IX the programmed baud rate ..
RxD
3
I
TxD
19
0
Serial dataoutputfrom the transmitter. "Mark" is high, "space" is low. Held in mark condition
when the transmitter is disabled.
OSR
22
I
General purpose input which can be used for data set ready orring indicator condition. Its
complement appears as status register bit SR7. Causes a low output on TXEMTIOSCHG
when its state changes.
ucu
16
I
Data carrier detect input. Must be low in order for the receiver to operate. Its complement
appears as status register bit SR6. Causes a low output on TXEMTIDS"CHG when its state
changes.
"CTS
17
I
Clear to send input. Must be low in order for the transmitter to operate. If it goes high during
transmission, the character in the transmit shift register will be transmitted before termination.
DTR
24
0
General purpose output which is the complement of command register bit CR 1. Normally
used to indicate data terminal ready.
fITS
23
0
General purpose output which is the complement of command register bit CR5. Normally
used to indicate request to send.
Serial data input to the receiver. "Mark" is high, "Space" is low.
NOTE.
'RXC and TXC outputs have short circuit protection max. CL = l00pF
Transmitter
The PCI is conditioned to transmit data when
the"CTS input is Low and the TxEN command
register bit is set. The SCN2651 indicates to
the CPU that it can accept a character for transmission by setting the TxRDY status bit and asserting the TXRIJV output. When the CPU
writes a character into the transmit data holding
register, these conditions are negated. Data is
transferred from the holding register to the
transmit shift registerwhen it is idle or has completed transmission of the previous character.
The TxRDY ccnditions are then asserted
again. Thus, one full character time of buffering
is provided.
In the asynchronous mode, the transmitter automatically sends a start bit followed by the programmed number of data bits, the least
significant bit being sent first. It then appends
an optional odd or even parity bit and the programmed number of stop bits. If, following
transmission of the data bits, a new character
is not available in the transmit holding register,
the TxD output remains in the marking (high)
condition and the TXEMTIDS"CHG output and
February 20, 19S5
its ccrresponding status bit are asserted.
Transmission resumes when the CPU loads a
new character into the holding register. The
transmitter can be forced to output a continuous low (BREAK) condition by setting the send
break command bit high.
available in the transmit data holding register.
If the send DLE bit in the command register is
true, the DLE character is automatically transmitted prior to transmission of the message
character in the THR.
In the synchronous mode, when the SCN2651
is initially conditioned to transmit, the TxD output remains high and the TxRDY condition is
asserted until the first character to be transmitted (usually a SYN character) is loaded by
the CPU. Subsequent to this, a continuous
stream of characters is transmitted. No extra
bits (other than parity, if commanded) are generated by the PCI unless the CPU fails to send
a new character to the PC I by the time the transmitter has ccmpleted sending the previous
character.
PCI PROGRAMMING
Since synchronous communication does not
allow gaps between characters, the PCI asserts T xEMT and automatically "fills" the gap by
transmitting SYN 1s, SYN I-SYN2 doublets, or
DLE-SYN 1 doublets, depending on the state of
MR16 and MRI7. Normal transmission of the
message resumes when a new character is
15
Prior to initiating data communications, the
SCN2651 operational mode must be programmed by performing write operations to the
mode and command registers. In addition, if
synchronous operation is programmed, the appropriate SYN/DLE registers must be loaded.
The PCI can be reconfigured atany time during
program execution. However, ifthechangehas
an effect on the reception of a character the receiver should be disabled. Altematively if the
change is made 11/2 RxC periods after RxRDY
goes active it will affect the next character assembly. A flowchart of the initialization process
appears in Figure 1.
The internal registers of the PCI are accessed
by applying specific signals to the cr, "RIW, A,
and Ao inputs. The conditions necessary to address each register are shown in table 4.
Product Specification
Philips Components-8ignetics Data Communication Products
Programmable communications interface (PCI)
INITIAL RESET
NOTE,
Mode Register 1 must be written
before 2 can be written. Mode Register 2
need not be programmed it external
clocks are used.
SCN2651
The SYNI. SYN2, and OLE registers are accessed
by performing write operations with the conditions
A l : 0, Ao : 1, and RIW : 1. The first operation
loads the SYN 1 register. The next loads the SYN2
register, and the third loads the OLE register.
Reading or loading the mode registers is done in a
similar manner. The first write (or read) operation
addresses mode register 1, and a subsequent operationaddresses mode register 2. If more than the
required number of accesses are made, the internal sequencer recycles to point at the first register.
The pointers are reset to SYN 1 register and mode
register 1 by a RESET input or by performing a
"read command register" operation, but are unaffected by any other read or write operation.
The SCN2651 register formats are summarized in
Tables 5, 6, 7 and B. Mode registers 1 and 2 define
the general operational characteristics of the PCI,
while the command register controls the operation
within this basic framework. The PCI indicates its
status in the status register. These registers are
cleared when a RESET input is applied.
Mode Register 1 (MR1)
Table 5 illustrates mode register 1. Bits MR11 and
MR10 select the communication format and baud
rate multiplier. 00 specifies synchronous mode and
lXmultiplier. IX, 16X, and 64X multipliers are programmable for asynchronous formal. However,
the multiplier in asynchronous format applies only
if the external clock input option is selected by
MR24 or MR25.
MR13 and MR12 select a character length of 5, 6,
7, or B bits. The character length does not include
the parity bit, if programmed, and does not include
the start and stop bits in asynchronous mode.
MR 14 controls parity generation. If enabled, a parity bit is added to the transmitted character and the
receiver performs a parity check on incoming data.
MR15 selects odd or even parity when parity is enabled by MRI4.
Figure 1. SCN2651 Initialization Flowchart
Table 4.
~
1
0
0
0
0
0
0
0
0
SCN2651 Register Addressing
A,
Ao
'R/W
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
FUNCTION
3-State data bus
Read receive holding register
Write transmit holding register
Read status register
Write SYN IISYN2IOLE registers
Read mode registers 112
Write mode registers 112
Read command register
Write command register
NOTE:
See AC Characteristics section for timing requirements.
February 20. 1985
16
In asynchronous mode, MR17 and MR16 select
character framing of 1, 1.5, or 2 stop bits. (If 1X
baud rate is programmed, 1.5 stop bits default to 1
stop bit on transmit) In synchronous mode, MR17
controls the number of SYN characters used to establish synchronization and for character fill when
the transmitter is idle. SYN 1 alone is used if MR17
: 1, and SYNI-SYN2 is used when MRI7: O. If
the transparent mode is specified by MRI6, OLESYN 1 is used for character fill and SYN detect, but
he normal synchronization sequence is used. Also
OLE stripping and OLE detect (with MRI4: 0) are
enabled.
Product Specification
Philips Components-Signetics Data Communication Products
Programmable communications interface (PCI)
Mode Register 2 (MR2)
Table 6 illustrates mode register 2. MR23,
MR22, MR21, and MR20controi the frequency
of the internal baud rate generator (BRG). Sixteen rates are selectable. When driven by a
5.0688MHz input at the BRCLK input (pin 20),
Table 5.
SCN2651
tively. If the BRG clock is selected, the baud
rate factor in asynchronous mode is 16X regardless of the factor selected by MRll and
MR10. In addition, the corresponding clock pin
provides an output at 1X the baud rate.
the BRG output has zero error except at 134.5
2000, and 19,200 baud, which have errors of
+0.016%, +0.235%, and +3.125%respectively.
MR25 and MR24 select either the BRG or the
eexternal inputs !xC" and 11xC" as the clock
source for the transmitter and receiver, respec-
Mode Register 1 (MR1)
MR17
MR16
Async: Stop bit length
00 = Invalid
01 = 1 Stop bit
10 = 1 1/2 Stop bits
11 = 2 Stop bits
Sync:
Transparency
control
a = Double SYN
O=Normal
1 = Transparent
1 = Single SYN
MR13
MR12
MR11
I
MR10
MR14
Parity Control
Character Length
Mode and Baud Rate Factor
o = Odd
0= Disabled
1 = Enabled
00 = 5 Bits
01 = 6 Bits
10 = 7 Bits
11 = 8 Bits
00 = Synchronous 1X rate
01 = Asynchronous 1X rate
10 = Asynchronous 16X rate
11 = Asynchronous 64X rate
1 = Even
Sync:
Number of SYN
char
I
MR15
Parity Type
NOTE:
Baud rate factor in asynchronous applies only if external clock is selected. Factor is 16X if internal clock is selected. Mode must be selected
(MRll, MR10) in any case.
Table 6.
MR27
Mode Register 2 (MR2)
I
MR26
MR25
MR24
Transmitter
Clock
Receiver
Clock
a = External
Not used
1 = Internal
Table 7.
CR7
MR23
I
MR22
I
MR21
r
MR20
Baud Rate Selection
0= External
1 = Internal
0000 = 50 Baud
0001 = 75
0010 = 110
0011 = 134.5
0100 = 150
0101 = 300
0110 = 600
0111 = 1200
1000 = 1800 Baud
1001 = 2000
1010 = 2400
1011 =3600
1100 = 4800
1101 =7200
1110 = 9600
1111 = 19,200
Command Register (CR)
I
CR6
Operating Mode
00 = Normal operation
01 = Async: automatic
echo mode
Sync: SYN andlor OLE
stripping mode
1a = Local Loopback
11 = Remote Loopback
February 20, 1985
CR5
Request
to Send
o = Force F!TS
output high
1 = Force F!TS
output low
CR4
CR3
CR2
Receive
Control
(RxEN)
Reset Error
0= Normal
1 = Reset
error flag
in status reg
(FE,OE,
PE/DLE
DETECT)
17
Async:
Force Break
a = Normal
1 = Force break
Sync
Send OLE
a = Normal
1 = Send OLE
CR1
CRO
Data Terminal
Ready
Transmit
Control
(TxEN)
a = Disable
a = Force IITR a = Disable
1 = Enable
output high
1 = Force IITR
output low
1 = Enable
Product Specification
Philips Components-signetics Data Communication Products
Programmable communications interface (PCI)
TableS.
SCN2651
Status Register (SR)
SR7
SR6
SRS
DataSet
Ready
Data Carrier
Deleet
FEISYN
Detect
0= USRinput
is high
1 = USRinput
is low
0= OCUinput
is high
1 = OCUinput
is low
Async:
0= Normal
1 = Framing
ERROR
Sync:
0= Normal
1 = SYN char
detected
Command Register (CR)
Table? illustrates the command register. Bits
CRO (TxEN) and CR2 (RxEN) enable or disable
the transmitter and receiver respectively. A 0
to 1 transition of CR2 forces start bit search
(async mode) or hunt mode (sync mode) on the
secondRXC' rising edge. Disabling the receiver
causes RXROY to go high (inactive). If the
transmitter is disabled, it will complete the
transmission of the character in the transmit
shift register (if any) prior to terminating operation. The TxD output will then remain in the
marking state (high) while TXRDY and TXEMT
will go high (inactive). If the receiver is disabled, it will terminate operation immediately.
Any character being assembled will be neglected.
Bits CR1 (DTR) and CRS (RTS) control the
SR4
SR3
SR2
SR1
SRO
Overrun
PEiDLE
Detect
TxEMTI
DSCHG
RxRDY
TxRDY
Async:
0= Normal
1 = Parity error
0= Normal
1 = Change in
OSRor
OCU,or
transmit
shift
register is
empty
0= Normal
1 = Overrun
error
Sync:
0= Normal
1 = Parity
error or
DLEchar
received
regenerated received data are automatically directed to the TxD line while normal receiveroperation continues. The receiver must be
enabled (CR2 = 1), but the transmitter need not
be enabled. CPU to receiver communications
continues normally, but the CPU to transmitter
link is disabled. Only the first character of a
break condition is echoed. The TxD output will
go high until the next valid start is detected.
The following conditions are true while in automatic echo mode:
1. Data assembled by the receiver are automatically placed in the transmit holding
register and retransmitted by the transmitter on the TxD output.
2. The transmitter is clocked by the receive
clock.
DTR and RTS outputs. Data at the outputs is
3. TXRDV output = 1.
the logical complement of the register data.
4. The I xEM TlDSCHG pin will reflect only
In asynchronous mode, setting CR3 will force
and hold the TxD output low (spacing condition)
at the end of the current transmitted character.
Normal operation resumes when CR3 is
cleared. The TxD line will go high for at least
one bit time before beginning transmission of
the next character in the transmit data holding
register. In synchronous mode, setting CR3
causes the transmission of the OLE register
contents prior to sending the character in the
transmit data holding register. CR3 should be
reset in response to the next TxRDY.
Setting CR4 causes the error flags in the status
register (SR3. SR4. and SRS) to be cleared.
This is a one time command. There is no internallatch for this bit.
The PCI can operate in one of four submodes
within each major mode (synchronous or
asynchronous). The operational submode is
determinedbyCR7andCR6. CR?-CR6=OO
is the normal mode, with the transmitter and receiver operating independen~y in accordance
with the mode and status register instructions.
In asynchronous mode, CR? -CR6 = 01 places
the PCI in the automatic echo mode. Clocked,
February 20, 1985
the data set change condition.
5. The TxEN command (CRO) is ignored.
In synchronous mode, CR? - CR6 = 01 places
the PCI in the automatic SYN/DLE stripping
mode. The exact action taken depends on the
setting of bits MR17 and MRI6:
1. In the non-transparent, single SYN mode
(MR1? - MR16 = 10), characters in the
data stream matching SYN 1 are not
transferred to the receive data holding
register (RHR).
2. In the non-transparent, double SYN mode
(MR17 - MR16 = 00), characters in the
data stream matching SYN 1, or SYN2 if
immediately preceded by SYN 1, are not
transferred the RHR. However, only the
firstSYNI ofanSYNI-SYNI pair is
stripped.
3. In transparent mode (MRI6 = I), character in the data stream matching OLE, or
SYNI if immediately preceded by OLE,
are not transferred to the RHR. However,
only the first OLE of a DLE-DLE pair is
stripped.
18
0= Receive
holding
register
empty
1 = Receive
holding
register
has data
0= Transmit
holding
register
busy
1 = Transmit
holding
register
empty
Note thatautomaticstripping mode does not affect the setting of the OLE detect and SYN detect status bits (SR3 and SR5).
Two diagnostic submodes can also be configured. In localloopback mode (CR? - CR6 =
10), the following loops are connected
internally:
1. The transmitter output is connected to the
receiver input.
2. OTR is connected to OCU and RTS is
connected to 'CTS.
3. The receiver is clocked by the transmit
clock.
4. The DTR, RTS and TXD outputs are held
high.
5. The 'CTS, OCU, OSR and RxD inputs are
ignored.
Additional requirements to operate in the local
loopback mode are that CRO (TxEN), CRI
(DTR), and CR5 (RTS) must be set to 1. CR2
(RxEN) is ignored by the PCI.
The second diagnostic mode is the remote
loopback mode (CR? - CR6 = 11). In this
mode:
1. Data assembled by the receiver are automatically placed in the transmit holding
register and retransmitted by the transmitter on the TxD output.
2. The transmitter is clocked by the receive
clock.
3. No data is sent to the local CPU. but he
error status conditions (PE, OE, FE) are
set.
4. The RXROY, TXRDV. and TXEMTI
USCRG outputs are held high.
5. CRO (TxEN) is ignored.
6. All other signals operate normally.
Philips Components~ignetics Data Communication Products
Product Specification
Programmable communications interface (PC I)
Status Register
The data contained in the status registar (as
shown in Table 8) indicate receiver and transmitter conditions and modem/data set status.
SROis the transmitterready(TxROY) status bit.
It, and its corresponding output, are valid only
when the transmitter is enabled. If equal to 0,
it indicates that the transmit data holding register has been loaded by the CPU and the data
has not been transferred to the transmit shift
register. If set equal to I, it indicates that the
Holding Register is ready to accept data from
the CPU. This bit is initially set when the transmitter is enabled by CRO, unless a character
has previously been loaded into the holding
register. It is not set when the automatic echo
or remote loopback modes are programmed.
When this bit is set, the IxROY output pin is
low. In the automatic echo and remote loopback modes, the output is held high.
SRI, the receiver ready (RxROY) status bit, indicates the condition of the receive data holding
register. If set, it indicates that a character has
been loaded into the holding register trom the
receive shift register and is ready to be read by
the CPU. If equal to zero, there is no new character in the holding register. This bit is cleared
when the CPU reads the receive data holding
February 20, 1985
register or when the receiver is disabled by
CR2. When set, the lixRDY output is low.
The TxEMT/OSCHG bit, SR2, when set, indicates either a change of state of the tm"R" or
OCU inputs or that the transmit shift register
has completed transmission of a character and
no new character has been loaded into the
transmit data holding register. Note thatin synchronous mode this bit will be set even though
the appropriate "fill" character is transmitted.
T xE MT will not go active until at least one character has been transmitted. It is cleared by
loading the transmit data holding register. The
OSCHG condition is enabled when TxEN = I or
RxEN = I. If the status register is read twice
and SR2 = I while SR6 and SRl remain unchanged, then a TxEMT condition exists. It is
cleared when the status register is read by the
CPU. When SR2 is set, the 'Ti-
TiEMT
"CE FOR
WRITE
OFTHR
DATA 2
DATA'
- D - A I ' I 2 13
I
TKO
w
8::E
..
TxEN
~
TiRIlV
~
~
DATA a
14 151 B
DATA'
c
I
DATA 4
I 2 13 14
AI'
151 B
DATA 2
c
I
A
I'
I 2 13
14
DATA a
i 51
B
c- D -
I
I
I
I
:z:
.!il
~
TiEMT
"CEFOR
WRITE
OFTHR
DATA'
DATA 2
DATA a
NOTES:
A _ Start bit
B_Stopbn t
C _ Stop bit 2
o _ TxD marking condition
TxEMT goes low at the beginning of the last data bit. or, if parity is enabled. at the beginnjng ot
February 20, 1985
21
the parity bit.
DATA
4
I I'
A
I 2
DATA
15
4
Product Specification
Philips Components-Signetics Data Communication Products
SCN2651
Programmable communications interface (PCI)
TIMING DIAGRAMS (Continued)
RxRDY (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode])
RiC
!
II
RxD
w
2
!
3
!
SYNI
4
I 5 II
I 2 !3 !4
I 2 13 ! 4
r
I 2 ! 3 14
IS
DATA 2
DATA 1
DATA 3
0
i
IGNORED
"'
:>
RxEN
~
li!l:
~
SYNDET
STATUS BIT
"'
IIXIIIlV
CEFOR
READ
II
U
READ
STATUS
READ
STATUS
READ RHR
(DATAl)
READ RHR
(DATA 2)
READ RHR
(DATA 3)
READ RHR
(DATA 3)
RxD
RxEN
OVERRUN
STATUS~~T
________________________
~
+-____________________________ __
____
~
~
CEFOR------------------------~ ~----------------------------~~----~ n~---READ
READRHR
(DATAl)
READ RHR
(DATA 3)
NOTES,
A-Startb,
B -Stopb, 1
C. S10p bil2
o ., TxD marking condition
February 20, 1985
22
Product Specification
Philips Components-Signetics Data Communication Products
SCN2651
Programmable communications interface (PCI)
TYPICAL APPLICATIONS
ASYNCHRONOUS INTERFACE TO CRT TERMINAL
ADDRESS BUS
CONTROL BUS
DATA BUS
r-----'
RxD
TxD
t
ElA TO TTL
CONVERT
(OPT)
L. _ _ _ _ _ .J
SCN2651
BRCLK
5.0688MHz
OSCILLATOR
ZS!J)
CRT
TERMINAL
ASYNCHRONOUS INTERFACE TO TELEPHONE LINES
PHONE
UNE
INTERFACE
t
TELEPHONE
UNE
February 20, 1985
23
Phmps Componen~ignetics Data Communication Products
Product Specification
SCN2651
Programmable communications interface (PCI)
TYPICAL APPLICATIONS (Continued)
SYNCHRONOUS INTERFACE TO TERMINAL OR PERIPHERAL DEVICE
ADDRESS BUS
I
I
1
CONTROl BUS
I
_I
DATA BUS
JU~
RxD
SCN2651
TxD
RiC
TiC
SYNCHRONOUS
TERMiNAL OR
PERIPHERAL
DEVICE
SYNCHRONOUS INTERFACE TO TELEPHONE UNES
PHONE
UNE
INTERFACE
SYNC
MODEM
TELEPHONE
UNE
FebrualY 20, 1985
24
Philips Components-Signetics
Document No.
853-1068
ECN No.
00927
Date of Issue
November 5, 1990
Status
Product Specification
SCN2652/SCN68652
Multi-protocol communications
controller (M PCC)
Data Communication Products
DESCRIPTION
APPLICATIONS
The SCN2652/68652 Multi-Protocol
Communications Controller (MPCC) is a
monolithic n-channel MOS LSI circuit
that formats, transmits and receives
synchronous serial data while
supporting bit-oriented or byte control
protocols. The chip is TTL compatible,
operates from a single +5V supply, and
can interface to a processor with an 8 or
16-bit bidirectional data bus.
• Intelligent terminals
FEATURES
• Line controllers
• Network processors
• Front end communications
• Remote data concentrators
• Communication test equipment
• Computer to computer links
PIN CONFIGURATION
• DC to 1Mbps or 2Mbps data rate
INDEX
CORNER
• Bit-oriented protocols (BOP):
SDLC, ADCCP, HDLC
MM
rxc
• Byte-control protocols (BCP):
DDCMP, BISYNC (external CRC)
rxsa
rxE
• Programmable operation
rxu
- 8 or 16-bit tri-state data bus
TxBE
- Error control- CRC or VRC or none
rxA
- Character length - 1 to 8 bits for
BOP or 5 to 8 bits for BCP
RESEr
- Idle transmission of SYNC/FLAG or
MARK for BCP-BOP
• Automatic detection and generation of
special BOP control sequences, i.e.,
FLAG, ABORT, GA
• Zero insertion and deletion for BOP
• Short character detection for last BOP
data character
• SYNC generation, detection, and
stripping for BCP
rOPVIEW
Vee
- SYNC or secondary station address
comparison for BCP-BOP
Pin Function
OBOO
1
2
3
4
5
6
7
8
9
10
OBol
0810
OBo2
DB11
OBo3
OB12
0B04
0813
OBoS
OB14
OBo6
0815
OBo7
lIiW
OBEN
A2
BYTE
Al
AO
11
NC
CE
RxC
RxSI
SlF
RxA
RxDA
RxSA
RxE
GNO
DB08
NC
DB09
OB10
0811
0812
DB13
DB14
OBIS
12
13
14
15
16
17
18
19
20 !WI
21 A2
22 Al
• Maintenance mode for self-testing
Pin Function
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NC
AD
BYTE
DBEN
DB07
DB06
DB05
DB04
OB03
DB02
OBOI
NC
DBOO
VCC
RESET
TxA
TxBE
TxU
TxE
TxSQ
TxC
MM
NOTE: 00 is least significant bit. highest number
• TTL compatible
(that is.
• Single +5V supply
25
DB1~
A2) i. most significant bit.
Philips Components-Signetics Data Communication Products
Product Specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
ORDERING CODE
Vcc =5V :1:.5%
PACKAGES
Commercia.
Automotive
Extended
DOC to +7DoC
-4D"C to +85°C
-55"C to + 125°C
SCN2652AM2F40
Ceramic DIP
2MHz
SCN2652AC2F40
SCN2652AA2F40
Plastic DIP
2MHz
SCN2652AC2N40
Contact Factory
Not Available
PlasticLCC
2MHz
SCN2652AC2A44
Contact Factory
Not Available
NOTE:
SCN68652 is identical to SCN2652. Order using part numbers shown above.
BLOCK DIAGRAM
..J\.
('DBOO
DBIS-
-v
'f"
DATA
BUS
BUFFER
~
~
""
-
~8BlTS_..
1681T9-------
PARAMETER CONTROL
SYNC/ADDRESS
REGISTER
- - - vcc
PCSAR
PARAMETER
CONTROL
REGISTER
PCR
- 4 - - GND
f
16
J
REC8VER
DATAISTATUS
REGISTER
RESET
RDSA
TRANSMITTER
DATA/STATUS
REGISTER
MM
_INTERNAL
BUS
A2- A O _
i-' 16
r
i-' 16
BYTE_
RIW_
CE_
READ/
WRITE
LOGIC
AND
CONTROL
DBEN_
~
SlF
R.E
AKA
RxDA
REC8VER
LOGIC AND
CONTROL
I
,I
T.E
T.A
T.BE
T.U
November 5, 1990
I
II
Rxe RxSf
RxSA
26
TRANSMITTER
LOGIC AND
CONTROL
I!
TxC TxSO
TOSR
Philips Components-Signetics Data Communication Products
Product Specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
PIN DESCRIPTION
MNEMONIC
PIN NO,
TYPE
DBl5-D800
17-10
I/O
24-{31
NAME AND FUNCTION
Data Bus: D807-DBOO contain bidirectional data while DBl5-DB08 contain control and status
information to or from the processor. Corresponding bits of the high and low order bytes can be wire
OR'ed onto an 8-bit bus. The data bus is floating if either CE or DBEN are low.
A2-AO
19-21
I
Address Bus: A2-AO select internal registers. The four 16-bit registers can be addressed on a word or
byte basis. See Register Address section.
BYTE
22
I
Byte: Single byte (8-bit) data bus transfers are specified when this input is high. A low level specifies
16-bit data bus transfers.
CE
1
I
Chip Enable: A high input permits a data bus operation when DBEN is activated.
l'1!W
18
I
ReadlWrite: row controls the direction of data bus transfer. When high, the data is to be loaded into the
addressed register. A low input causes the contents of the addressed register to be presented on the
data bus.
DBEN
23
I
Data Bus Enable: After A2-AO, CE, BYTE and RIW are set up, DBEN may be strobed. During a read,
the 3-state data bus (DB) is enabled with information for the processor. During a write, the stable data is
loaded into the addressed register and TxBE will be reset if TDSR was addressed.
RESET
33
I
Reset: A high level initializes all internal registers (to zero) and timing.
MM
40
I
Maintenance Mode: MM internally gates TxSO back to RxSI and TxC to RxC for off line diagnostic
purposes. The RxC and RxSI inputs are disabled and TxSO is high when MM is asserted.
RxE
8
I
Receiver Enable: A high level input permits the processing of RxSI data. A low level disables the
receiver logic and initializes all receiver registers and timing.
RxA
5
0
Receiver Active: RxA is asserted when the first data character of a message is ready for the processor.
In the BOP mode this character is the address. The received address must match the secondary station
address if the MPCC is a secondary station. In BCP mode, if strip-SYNC (PCSAR I3) is set, the first
non-SYNC character is the first data character; if strip-SYNC is zero, the character following the second
SYNC is the first data character. In the BOP mode, the closing FLAG resets RxA. In the BCP mode, RxA
is reset by a low level at RxE.
RxDA'
6
0
Receiver Data Available: RxDA is asserted when an assembled character is in RDSR L and is ready to
be presented to the processor. This output is reset when RDSR L is read.
RxC
2
I
s/F
4
0
SYNC/FLAG: s/F is asserted for one RxC clock time when a SYNC or FLAG character is detected.
RxSN
7
0
Receiver Status Available: RxSA is asserted when there is a zero to one transition of any bit in RDSR H
except for RSOM. It is cleared when RDSRH is read.
Receiver Clock: RxC (1 X) provides timing for the receiver logic. The positive going edge shifts serial
data into the RxSR from RxSI.
='1', space ='0'.
RxSI
3
I
Receiver Serial Input: RxSI is the received serial data. Mark
TxE
37
I
Transmitter Enable: A high level input enables the transmitter data path between TDSR L and TxSO. At
the end of a message, a low level input causes TxSO = 1(mark) and TxA =0 after the closing FLAG
(BOP) or last character (BCP) is output on TxSO.
TxA
34
0
Transmitter Active: TxA is asserted after TSOM (TDSRs) is set and TxE is raised. This output will reset
when TxE is low and the closing FLAG (BOP) or last character (BCP) has been output on TxSO.
TxBE'
35
0
Transmitter Buffer Empty: TxBE is asserted when the TDSR is ready to be loaded with new control
information or data. The processor should respond by loading theTDSR which resets TxBE.
TxU'
36
0
Transmitter Underrun: TxU is asserted during a transmit sequence when the service of TxBE has been
delayed for one character time. This indicates the processor is not keeping up with the transmitter. Line
fill depends on PCSAR 11 . TxU is reset by RESET or setting of TSOM (TDSRs), synchronized by the
falling edge of TxC.
TxC
39
I
Transmitter Clock: TxC (1 X) provides timing for the transmitter logic. The positive going edge shifts
data out of the TxSR to TxSO.
TxSO
38
0
Vee
32
I
GND
9
I
Indicates possible Interrupt signal
November 5, 1990
Transmitter Serial Output: TxSO is the transmitted serial data. Mark = '1', space
+5V: Power supply.
Ground: OV reference ground.
27
='0'.
Product Specification
Philips Components-Signetics Data Communication Products
SCN2652/SCN68652
Multi-protocol communications controller (MPCC)
Table 1.
Glossary
REGISTERS
NO. OF BITS
DESCRIPTION'
16
PCR
Parameter control syncl
address register
Parameter control register
PCSARH and PCR contain parameters common to the
receiver and transmitter. PCSAR L contains a
programmable SYNC character (BCP) or secondary
station address (BOP).
RDSR
Receive data/status register
16
RDSR H contains receiver status information.
RDSRL = RxDB contains the received assembled
character.
TDSR
Transmit data/status register
16
TDSRH contains transmitter command and status
information. TDSRL = TxDB contains the character to be
transmitted
Internal
CCSR
HSR
Control character shift register
Holding shift register
8
16
These registers are used for character assembly
(CSSR, HSR. RxSR), disassembly (TxSR), and
CRC accumulation/generation (RxCRC, TxCRC).
Addressable
PCSAR
RxSR
TxSR
RxCRC
8
Receiver shift register
Transmitter shift register
Receiver CRC accumulation
register
Transmitter CRC generation
register
TxCRC
8
8
16
16
NOTES:
+H = High byte - bits 15-8
L = Low byte - bits 7...{J
FUNCTIONAL DESCRIPTION
The MPCC can be functionally partitioned into
receiver logic, transmitter logic, registers that
can be read or loaded by the processor, and
data bus control circuitry. The register bit
formats are shown in Figure 1 while the receiver
and transmitter data paths are depicted in
Figures 2 and 3.
Table 2.
Error Control
CHARACTER
FCS
BCC
Table 3.
Special Characters
OPERATION
BITPATIERN
BOP
FLAG
ABORT
01111110
1 1 1 1 1 1 1 1 generation
01111111 detection
01111111
GA
Address
BCP
SYNC
Block check character is
transmitted/received as
two successive characters
following the last data character of a BCP message.
The polynomial is CRC-16
(X'S + X'5 + X2 + l)or
CRC-CCITI with dividend
preset to O's (as specified
by ECM). The true remainder is transmitted as the
BCC.
Frame message
Terminate communication
Terminate loop mode
repeater function
Secondary station address
(PCSARLl'
(PCSARLl or (TxDBj2
generation
DESCRIPTION
Frame check sequence is
transmitted/received as 16
bits following the last data
character of a BOP message. The divisor is usually
CRC-CCITI (X'6 + X'2 +
X· + 1) with dividend preset
to 1's but can be other wise
determined by ECM. The
inverted remainder is transmitter as the FCS.
FUNCTION
Character synchronization
NOTES:
1. ( ) = contents of.
2. For IDLE = 0 or 1 respectively.
PCSAR
PCR
I
,5
APA
'4
"
RERR
TDSR
TERR
'5
13
'4
TxCL
15
RDSR
'2
'3
"
14
14
"
ITXCLEIRXCLEI
13
12
ABC
I
12
13
'2
11
'0
I ROR I
~BI
11
10
8
'0
ECM
I PROTO I SSiGA I SAM I IDLE I
I
10
8
RxCL
8
7 &
I
NOTE:
Refer to Register Formats tor mnemonics and description.
28
RxDB
8
NOT DEFINED I TGA I TABORT ITEaM I TSOM I
Figure 1, Short Form Register Bit Formats
NovemberS, 1990
3 2 ,
StAR
8
IREOMIRSOMI
8
5 4
TxDB
0
Philips Components~ignetics Data Communication Products
Product Specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
Rx51
HSR('.)
ZERO
DELEllON
CONTROL
MM
S/F
- - - - - - - - j - - - -..
CRC-•• (BCP) OR
CCRC-CCITT
(BOP)
BCP
RESET
RxE
RICA
RxDA
RxSA
RxC
NOTES:
1. Detected in SYNC FF and 7 MS bits of CCSR.
2. In BOP rrode, a mini room of two data characters must be received to turn the receiver active.
Figure 2. M pec Receiver Data Path
RESET
TxE
TxA
TxBE
TRANS.
MITTER
CONTROL
LOGIC
!8-TXSO
TxSR (8)
1 BIT
DELAY
TxU
TxCRC ACC ('.)
CRC-•• OR CRC-CCITT
BOP
ZERO
INSERTION
LOGIC
BCP
PARITY
GENERAllON
TxC
CONTROL
CHARACTER
GENERATOR
FLAG ABORT
GA
NOTES:
1. TxCRC selected if TEOM • 1 and the last data character has been shifted oul ofTxSR.
2. In BCP parity selected will be generated after each character is shifted out of TxSR.
Figure 3. MPee Transmitter Data Path
November 5, 1990
29
ZERO
INSERllON
CONTROL
Product Specification
Philips Components-Signetics Data Communication Products
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
RECEIVER OPERATION
General
"""::";;=T-===--.--10
PROCESSOR
After initializing the parameter control registers
(PCSAR and PCR), the RxE input must be set
high to enable the receiver data path. The serial
data on the RxSI is synchronized and shifted
into an 8-bit Control Character Shift Register
(CCSR) on the rising edge of RxC. A
comparison between CCSR contents and the
FLAG (BOP) or SYNC (BCP) character is made
until a match is found. At that time, the s/F
output is asserted for one RxC time and the
IS-bit Holding Shift Register (HSR) is enabled.
The receiver then operates as described below.
BOP Operation
A flowchart of receiver operation in BOP mode
appears in Figure 4. Zero deletion (after five
ones are received) is implemented on the
received serial data so that a data character will
not be interpreted as a FLAG, ABORT, or GA.
Bits following the FLAG are shifted through the
CCSR, HSR, and into the Receiver Shift
Register (RxSR). A character will be assembled
in the RxSR and transferred to the RDSRL for
presentation to the processor. At that time the
RxDA output will be asserted and the processor
must take the character no later than one RxC
time after the next character is assembled in the
RxSR. If not, an overrun (RDSR l1 = 1) will occur
and succeeding characters will be lost.
The first character following the FLAG is the
secondary station address. If the MPCC is a
secondary station (PCSAR l 2 = I), the contents
of RxSR are compared with the address stored
in PCSARL. A match indicates the forthcoming
message is intended for the station; the RxA
output is asserted, the character is loaded into
RDSRL, RxDA is asserted and the Receive
Start of Message bit (RSOM) is set. No match
indicates that another station is being addressed and the receiver searches for the next
FLAG.
If the MPCC is a primary station, (PCSAR12 = 0),
no secondary address check is made; RxA is
asserted and RSOM is set once the first
non-FLAG character has been loaded into
RDSRL and RxDA has been asserted.
Extended address field can be supported by
software if PCSAR12 = O.
When the 8 bits following the address character
have been loaded into RDSRL and RxDA has
been asserted, RSOM will be cleared. The
processor should read this 8-bit character and
interpret it as the Control field.
Received serial data that follows is read and
interpreted as the information field by the
processor. It will be assembled into character
lengths as specified by PCAs-lO. As before,
RxDA is asserted each time a character has
been transferred into RDSRL and is cleared
November 5, 1990
C-
TEST MADE EVERiI
RxCTIME
J
SlF=11"
FOR ONE RxC
BIT TIME
..
~~---- t~~-----------r~
(1) OVERRUN (ROVRN)
CAUSES LOSS OF
SUBSEQUENT
CHARACTERS
START OF
MESSAGE
RxA=l
RSOM= 1
FOR ONE
CHARACTER
----+----1...-.....:::----'-----'
TIME
RxDA = 1 - - - - - - '
(PROCESSOR
SHOULD
READ RxDB)
RXSA = 1
(PROCESSOR
SHOULD~
..f - - ; - - - - -
EXAMINE~
READ AND
RDSAH - REOM, RABlGA,
ROVRN, ABC, RERR)
~
t
SIF=1FOR ONERXC
BIT TIME
REOM=l,RxA=O
YES
FLAG
INCCSR-
~~N~O---------"
? YES-END OF MESSAGE
Figure 4. BOP Receive
when RDSRL is read by the processor.
RDSRH should only be read when RxSA is
asserted. This occurs on a zero to one
transition of any bit in RDSRH except for
RSOM. RxSA and all bits in RDSRH except
RSOM are cleared when RDSRH is read. The
processor should check RDSRs-15 each time
RxSA is asserted. If RDSR9 is set, then
RDSRl2-15 should be examined.
30
Receiver character length may be changed
dynamically in response to RxDA: read the
character in RxDB and write the new character
length into RxCL. The character length will be
changed on the next receiver character
boundary. A received residual (short) character will be transferred into RxDB after the
previouscharacterin RxDB has been read, i.e.
there will not be an overrun. In general the last
two characters are protected from overrun.
Philips Components-Signetics Oata Communication Products
Product Specification
Multi-protocol communications controller (MPCC)
The CRC-CCITT, if specified by PCSARs-10, is
accumulated in RxCRC on each character
following the FLAG. When the closing FLAG is
detected in the CCSR, the received CRC is in
the 16-bit HSR. At thattime, the Receive End of
Message bit (REOM) will be set; RxSA and
RxOA will be asserted. The processor should
read the last data character in ROSRL and the
receiver status in ROSR9-15. If ROSR 15 = 1,
there has been a transmission error; the
accumulated CRC-CCITT is incorrect. If
ROSR12_14 " 0, last data character is not of
prescribed length. Neither the received CRC
nor closing FLAG are presented to the
processor. The processor may drop RxE or
leave it active at the end of the received
message.
SCN2652/SCN68652
INITIALIZE PCSAR, PCR
PROCESSOR
NO
SIF = 1 FOR ONE
R.CBITTIME
NO
BCP Operation
The operation of the receiver in BCP mode is
shown in Figure 5. The receiver initially
searches for two successive SYNC characters,
of length specified by PCRS-10, that match the
contents of PCSAR L. The next non-SYNC
character or next SYNC character, if stripping is
not specified (PCSAR 13 = 0), causes RxA to be
asserted and enables the receiver data path.
Once enabled, all characters are assembled in
RxSR and loaded into ROSRL. RxOA is active
when a character is available in ROSR L. RxSA
is active on a 0 to 1 transition of any bit in
ROSRH. The signals are cleared when ROSRI
or ROSRH are read respectively.
If CRC-16 error control is specified by
PCSARs-1O, the processor must determine the
last character received prior to the CRC field.
When that character is loaded into ROSRL and
RxOA is asserted, the received CRC will be in
CCSR and HSRL. To check for a transmission
error, the processor must read the receiver
status (ROSRH) and examine ROSR 15 . This bit
will be set for one character time if an error free
message has been received. If ROSR15 = 0, the
CRC-16 isin error. The state of ROSR 15in BCP
CRC mode does not set RxSA. Note that this bit
should be examined only at the end of a
message. The accumulated CRC will include all
characters starting with the first non-SYNC
character if PCSAR 13 = 1, or the character after
the opening two SYNCs if PCSAR 13 = O. This
necessitates extemal CRC generation/checking when supporting IBM's BISYNC. This can
be accomplished using the Signetics SCN2653
Polynomial Generator/Checker. See Typical
Applications.
IfVRC has been selected for error control, parity
(odd or even) is regenerated on each character
and checked when the parity bit is received. A
discrepancy causes ROSR 15 to be set and
RxSA to be asserted. This must be sensed by
the processor. The received parity bit is stripped
before the character is presented to the
processor.
November 5,1990
t------
RxA = 1 ....
(1) SYNC. ARE ASSEMBLED
(2) OVERRUN (ROVRN) CAUSES
LOSS OF SUBSEaUENT
CHARACTERS
RxDA = 1
(PROCESSOR _ _
SHOULD READ
L...!=~==.J
RxOB)
R.SA = 1 ....t - - - - (PROCESSOR SHOULD
READ AND EXAMNE
RDSRH - ROVRN,
RERR(IFVRC
SPECIRED)
NO
RxE= 0
WHEN LAST
CHARACTER HAS
BEEN SERVICED
0
NOTES:
1. Test made every Axe time.
2. Test made on Rx character boundary.
Figure 5. BCP Receive
When the processor has read the last
character ot the message, it should drop RxE
which disables the receiver logic and
initializes all receiver registers and timing.
TRANSMITTER OPERATION
General
After the parameter control registers (PCSAR
and PCR) have been initialized, TxSO is held
at mark until TSOM (TOSRs) is set and TxE is
raised. Then, transmitter operation depends
on protocol mode.
31
BOP Operation
Transmitter operation tor BOP is shown in
Figure 6. A FLAG is sent after the processor
sets the TransmitStartof Message bit (TSOM)
and raises TxE. The FLAG is used to
synchronize the message that follows. TxA
will also be asserted. When TxBE is asserted
by the MPCC, the processor should load
TOSRLwith the first character ofthe message.
TSOM should be cleared at the same time
TOSRL is loaded (16-bit data bus) or
immediately thereafter (S-bit data bus).
FLAGS are sent as long as TSOM = 1. For
counting the number of FLAGs, the processor
Product Specification
Philips Components-8ignetics Data Communication Products
Multi-protocol communications controller (MPCC)
(PROCESSOR MUST CLEAR
,,~~:INI:::TI:::A:::U:::Z:::E:::P:::C~SAtR,~PC~R~'~TDS:R~H~~~TA~B~O~R~TIG~A~IN~R:E:S=PO:NS:E~----,
TO T,BE = ')
A.l
TS.:!~::
- - - - 1...
I---=-;==.r==;
-
TxA =1 .....
TxBE= 1
PROCESSOR
SHO~~g~~~g ~
TSOM=~
~--------~
(PROCESSOR MAY
SET TABORT, TGA, AS REQUIRED)
,---------1
T,SO = ABORT: 11111111 IF IDLE = 0
FLAG = 01111110 IF IDLE =.
ON UNDERRUN:
T,U=., TERR=.
(PROCESSOR - - SHOULD
SETTSOM)
TxBE: •
(PROCESSOR - - SHOULD LOAD
TxOB WITH NEXT ---...
DATA CHAR)
SERIAUZE DATA CHARACTER
IN TxDB, ZERO INSERTION,
ACCUMULATE CRC IF
SPECIRED BY ECM,
TRANSMT ON TxSO
®
NO
lxBE=1 . . . -
NO
(PROCESSOR SHOULD
RESET TEOM AND SET
TSOM OR DROP TxE)
SCN2652/SCN68652
character is serialized in TxSR and transmitted
on TxSO.lntemal zero insertion logic stuffs a "0"
into the serial bit stream after five successive
"I s" are sent. This insures a data character will
not match a FLAG, ABORT, or GA reserved
control character. As each character is
transmitted, the Frame Check
Sequence
(FCS) is generated as specified by Error
Control Mode (PCSARs-l0). The FCS should be
the CRC-CCITT polynomial (XIS + X12 + X5 +
1) preset to ls.lfan underrun occurs (processor
is not keeping up with the transmitter), TxU and
TERR (TDSR I5) will be asserted with ABORTor
FLAG used as the TxSO line fill depending on
the state of IDLE (PCSARl1)' The processor
must set T50M to reset the underrun condition.
To retransmit the message, the processor
should proceed with the normal start of
message sequence.
A residual character of 1 to 7 bits may be
transmitted at the end of the information field. In
response to TxBE, write the residual character
length into TxCL and load TxDB with the
residual character. Dynamic alteration of
character length should be done in exactly the
same sequence. The character length will be
changed on the next transmit character
boundary.
After the last data character has been loaded
into TDSRL and sent to TxSR (TxBE = 1), the
processor should set TEOM (TDSRg). The
MPCC will finish transmitting the last character
followed by the FCS and the closing FLAG. The
processor should clear TEOM and drop TxE
when the next TxBE is asserted. This
corresponds to the start of closing FLAG
transmission. When TxE has been dropped.
TxA will be low 1 1/2 bit times after the last bit
of the closing FLAG has been transmitted.
TxSOwili be marked afterthe closing FLAG has
been transmitted.
If TxE and TEOM are high, the transmitter
continues to send FLAGs. The processor may
initiate the next message by resetting TEOM
and setting T50M, or by loading TDSRL with a
data character and then simply resetting TSOM
(without setting TSOM).
BCP Operation
YES
T,A
=0
....I----~-
°GA will be transmitted if TOA is set together with TEOM.
Figure 6, BOP Transmit
should reassert TSOM in response to the
assertion of TxBE.
November 5, 1990
All succeeding characters are loaded into
TDSR L by the processor when TxBE = 1. Each
32
Transmitteroperation for BCP mode is shown in
Figure 7. TxA will be asserted after TSOM = 1
andTxE is raised. Atthattime SYNC characters
are sent from PCSARL or TDSRL (IDLE = 0 or
1) as long as TSOM = 1. TxBE is asserted at the
start of transmission of the first SYNC character.
For counting the number of SYNCs, the
processor should reassertTSOM in response to
the assertion of TxBE. When TSOM = 0
transmission is from TDSRL, which must be
loaded with characters from the processor each
time TxBE is asserted. If this loading is delayed
for more than one character time, an underrun
results: TxU and TERR are asserted and the
Product Specification
Philips Components--Signetics Data Communication Products
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
Special Case
The capability to transmit 16 spaces is provided
for line turnaround in half duplex mode or for a
control recovery situation. This is achieved by
setting TSOM and TEaM, clearing TEaM when
TxBE = 1, and proceeding as required.
INiTlAUZE PCSAR, PCR, TDSRH
PROCESSOR
TSOM= 1
TxE = 1
TxA
=1
TxBE
=1
PROGRAMMING
..= = - - - - - - - . - - { I B
~"I-------l
AFT~A~NgI~k ~~~~~~~
IN TxDB AND TSOM
=D
--.-J
TxBE= 1
(PROCESSOR
SHOULD LOAD TxDB)
The default value for all registers is zero. This
corresponds to BOP, primary station mode,
S-bit character length, FCS = CRC-CCITI
preset to 1s.
(~~~~~s,.?:TS~.?~~ --.1.----+/
For BOP mode the character length register
(PCR) may be set to the desired values during
system initialization. The address and control
fields will automatically be S-bits. If a residual
character is to be transmitted, TxCL should be
changed to the residual character length priorto
transmission of that character.
MESSAGE IF CRC
SPECIAED)
TxU = 1, TERR = 1
(PROCESSOR SHOULD
SETTSOM= 1)
TxBE = 1
(PROCESSOR
SHOULD CLEAR
TEOM AND DROP
~.I------
DATA BUS CONTROL
The processor must set up the MPCC register
address (A2-AO), chip enable (CE), byte select
(BYTE), and readlwrite (R/W) inputs before
each data bus transfer operation.
TxE) - - -___
TxA
=0
....1 - - - - - -
Figure 7. BCP Transmit
TxSO line fill depend on IDLE (PCSARll)' The
processor must set TSOM and retransmit the
message to recover. This is not compatible
with IBM's BISYNC, so that the user must not
underrun when supporting that protocol,
CRC-16, if specified by PCSAR8-1D, is
generated on each character transmitted from
TDSR L when TSOM =0. The processor must
set TEaM = 1 after the last data character has
been sent to TxSR (TxBE = I), The MPCC will
finish transmitting the last data character and
the CRC-16 field before sending SYNC
characters which are transmitted as long as
November 5, 1990
Priorto initiating data transmission orreception,
PCSAR and PCR must be loaded with control
information from the processor. The contents of
these registers (see Register Format section)
will configure the MPCC for the user's specific
data communication environment. These regis·
ters should be loaded during power-on
initialization and after a reset operation. They
can be changed at any time that the respective
transmitter or receiver is disabled.
TEaM = 1. II SYNCs are not desired after
CRC-16 transmission, the processor should
clear TEaM and lower TxE when the TxBE
corresponding to the start of CRC-16
transmission is asserted. When TEaM = 0, the
line is marked and a new message may be
initiated by setting TSOM and raising TxE.
IIVRC is specified, itis generated on each data
character and the data character length must
not exceed 7 bits. For software LRC or CRC,
TEaM should be set only if SYNC's are
required at the end of the message block.
33
During a read operation (R/W = 0), the leading
edge of DBEN will initiate an MPCC read cycle.
The addressed register will place its contents on
the data bus. If BYTE = I, theS-bitbyte is placed
on DBI5-{)Sor DB07-{)Odepending on the H/L
status of the register addressed. Unused bits in
RDSRL are zero. If BYTE = 0, all 16 bits
(DBI5-{)0) contain MPCC information. The
trailing edge of DBEN will reset RxDA andlor
RxSA if RDSRL or RDSR H is addressed
respectively.
DBEN acts as the enable and strobe so that the
MPCC will not begin its internal read cycle until
DBEN is asserted.
During a write operation (R/W = 1), data must be
stable on DB,~ andior DB07-OO prior to the
leading edge of DBEN. The stable data is
strobed into the addressed register by DBEN.
TxBE will be cleared if the addressed register
was TDSR H or TDSRL.
Product Specification
Philips Components-Signetics Data Communication Products
Multi-protocol communications controller (MPCC)
Table 4.
SCN2652/SCN68652
MPCC Register Addressing
A2
BYTE = 0
A1
16-BIT DATA BUS
= DB15 -
0
0
1
1
BYTE = 1
AO
REGISTER
X
X
X
X
RDSR
TDSR
PCSAR
PCR"
0
1
0
1
0
1
0
1
RDSRL
RDSRH
TDSRL
TDSRH
PCSARL
PCSARH
PCRL"
PCRH
DBoo
0
1
0
1
8-BIT DATA BUS = DB7-4 or DB,~"
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
NOTES:
" PCR lower byte does not exist. It will be all ··O"s when read.
"" Corresponding high and low order pins must be tied together.
Table 5.
Parameter Control Register (PCR)-(R/w)
BIT
NAME
00"{)7
Not Defined
08-10
RxCl
MODE
FUNCTION
BOP/BCP
Receiver character length is loaded by the processor when RxClE = o. The character length
is valid after transmission of single byte address and control fields have been received.
10
0
0
0
0
1
1
1
1
!!
8
Char length (bits)
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
1
2
3
4
5
6
7
11
RxClE
BOP/BCP
Receiver character length enable should be zero when the processor loads RxCL. The
remaining bits of PCR are not affected during loading. Always 0 when read.
12
TxCLE
BOP/BCP
Transmitter character length enable should be zero when the processor loads TxCL. The
remaining bits of PCR are not affected during loading. Always 0 when read.
13-15
TxCl
BOP/BCP
Transmitter character length is loaded by the processor when TxCLe = O. Character bit length
specification format is identical to RxCL. It is valid after transmission of single byte address and
control fields.
November 5, 1990
34
Product Specification
Philips Components-$ignetics Data Communication Products
SCN2652/SCN68652
Multi-protocol communications controller (MPCC)
Table 6.
Parameter Control SYNC/Address Register (PCSARHR/W)
BIT
NAME
MODE
FUNCTION
00--07
s/AR
BOP
SYNC/address register. Contains the secondary station address if the MPCC is a secondary
station. The contents of this register is compared with the first received non-FLAG character to
determine if the message is meant for this station.
BCP
SYNC character is loaded into this register by the processor. It is used for receive and transmit
bit synchronization with bit length specified by RxCl and TxCL.
08-10
ECM
BOP/BCP
Em!! Cllol[1I1 MQde
111
II
II
Sl!ggll!lld Mllde
Cbl![ leoglb
CRC-CCITI preset to l's 0
1-8
BOP
0
0
CRC-CCITI preset to D's 0
0
1
BCP
8
Not used
0
1
0
BCP
8
CRC-16 preset to O's
0
1
1
5-7
0
VRC odd
BCP
0
1
VRC even
1
BCP
5--7
1
0
Not used
0
1
1
BCP/BOP
No error control
5-8
1
1
1
ECM should be loaded by the processor during initialization or when both data paths are idle.
11
IDLE
12
SAM
13
SS/GA
14
Determines line fill character to be used if transmitter underrun occurs (TxU asserted and TERR
set) and transmission of special characters for BOP/BCP.
BOP
IDLE: 0, transmit ABORT characters during underrun and when TABORT : 1.
IDLE: 1, transmit FLAG characters during underrun and when TASORT : 1.
BCP
IDLE: 0 transmit initial SYNC characters and underrun line fill characters from theS/AR.
IDLE: 1 transmit initial SYNC characters from TxDB and marks TxSO during underrun.
BOP
Secondary Address Mode: 1 if the MPCC is a secondary station. This facilitates automatic
recognition of the received secondary station address. When transmitting, the processor must
load the secondary address into TxDB.
SAM: 0 inhibits the received secondary address comparison which serves to activate the
receiver after the first non-FLAG character has been received.
Strip SYNC/Go Ahead. Operation depends on mode.
BOP
SS/GA: 1 is used for loop mode only and enables GA detection. When a GA is detected as
a closing character, REaM and RABIGA will be set and the processor should terminate the
repeater function. SS/GA : 0 is the normal mode which enables ABORT detection. It causes
the receiver to terminate the frame upon detection of an ABORT or FLAG.
BCP
SS/GA: 1, causes the receiver to strip SYNC's immediately following the first two SYNC's
detected. SYNC's in the middle of a message will not be stripped. SS/GA : 0, presents any
SYNC's after the initial two SYNC's to the processor.
BOP
BCP
PROTO: 0
PROTO: 1
BOP
All parties address. If this bit is set, the receiver data path is enabled by an address field of
'11111111' as well as the normal secondary station address.
PROTO
15
November 5, 1990
APA
Determines MPCC Protocol mode
35
Product Specification
Philips Components-Signetics Data Communication Products
Multi~protocol
Table 7,
Transmit Data/Status Register (TDSR) (RIW except TDSR15)
BIT
NAME
MODE
OO"'()7
TxDB
BOP/BCP.
08
TSOM
09
SCN2652/SCN68652
communications controller (MPCC)
FUNCTION
Transmit data buffer. Contains processor loaded characters to be serialized in TxSR and
transmitted on TxSO.
Transmitter start of message. Set by the processor to initiate message transmission provided
TxE = 1.
a
BOP
·T80M'; 1 generates FLAGs. When T80M = transmission is from TxDB and FCS generation
(if s'pecified) begins. FCS, as specified by PCSAR8-10, should be CRC~CCITT preset to l's.
BCP
TSOM = 1 generates SYNCs from PCSARL or transmits from TxDB for IDLE = or 1
respectively. When T80M = transmission is from TxDB and CRC generation (if specified)
begins.
TEaM
a
a
Transmit end of message. Used to terminate a transmitted message.
BOP
TEaM = 1 causes the FCS and the closing FLAG to be transmitted following the transmission
of the data character in TxSR. FLAGs are transmitted until TEaM = o. ABORT or GA are
transmitted if TABORT or TGA are set when TEaM = 1.
BCP
TEaM = 1 causes CRC-16 to be transmitted (if selected) followed by SYNCs from PCSAR L
or TxDB (IDLE = or 1). Clearing TEaM prior to the end of CRC-16 transmission (when
TxBE = 1) causes TxSO to be marked following the CRC-16. TxE must be dropped before a
new message can be initiated. If CRC is not selected, TEaM should not be sel.
a
10
TABORT
BOP
Transmitter abort = 1 will cause ABORT or FLAG to be sent (IDLE
character is transmitted. (ABORT = 11111111)
11
TGA
BOP
Transmit go ahead (GA) instead of FLAG when TEaM
in loop mode. (GA = 01111111)
12-14
Not Defined
15
TERR
Read
only
Transmitter error = 1 indicates the TxDB has not been loaded in time (one character time-1/2
TxC period after TxBE is asserted) to maintain continuous transmission. TxU will be asserted
to inform the processor of this condition. TERR is cleared by setting TSOM. See timing diagram.
November 5, 1990
BOP
ABORT's or FLAG's are sent as fill characters (IDLE
BCP
SYNC's or MARK's are serit as fill characters (IDLE
before underrun is not valid.
36
= 1 or 1) after the current
= 1. This facilitates repeater termination
= a or 1)
= a or 1). For IDLE = 1 the last character
Product Specification
Philips Components-Signetics Data Communication Products
Multi-protocol communications controller (MPCC)
Table 8.
SCN2652/SCN68652
Receiver Data/Status Register (RDSR)-(Read Only)
BIT
NAME
MODE
FUNCTION
00-07
RxDB
BOP/BCP
Receiver data buffer. Contains assembled characters from the RxSR. If VRC is specified, the
parity bit is stripped.
08
RSOM
BOP
Receiver start of message = 1 when a FLAG followed by a non-FLAG has been received and
the latter character matches the secondary station if SAM = 1. RxA will be asserted when RSOM
= 1. RSOM resets itself after one character time and has no affect on RxSA.
09
REOM
BOP
Receiver end of message = 1 when the closing FLAG is detected and the last data charaater
is loaded into RxDB or when an ABORT/GA character is received. REOM is cleared on reading
RDSRH, reset operation, or dropping of RxE.
10
RAB/GA
BOP
Received ABORT or GA character = 1 when the receiver senses an ABORT character if SS/GA
=0 or a GA character if SSlGA = 1. RAB/GA is cleared on reading RDSR H, reset operation, or
dropping of RxE. A received abort does not set RxDA.
11
ROR
BOP/BCP
Receiver overrun = 1 indicates the processor has not read last character in the RxDB within one
character time + 1/2 RxC period after RxDA is asserted. Subsequent characters will be lost. ROR
is cleared on reading RDSR H, reset operation, or dropping of RxE.
12-14
ABC
BOP
Assembled bit count. Specifies the number of bits in the last received data character of a message and should be examined by the processor when REOM = 1(RxDA and RxSA asserted).
ABC = 0 indicates the message was terminated (by a flag or GA) on a character boundary as
specified by PCRS-10. Otherwise, ABC =number of bits in the last data character. ABC is cleared
when RDSR H is read, reset operation, or dropping RxE. The residual character is right justified
inRDSR L·
15
RERR
BOP/BCP
Receiver error indicator should be examined by the processor when REOm = 1 in BOP, or when
the processor determines the last data character of the message in BCP with CRC or when
RxSA is set in BCP with VRC.
CRC-CCID preset to l's/O's as specified by PCSARs-lO:
RERR = 1 indicates FCS error (CRC '" FOBS or '" 0)
RERR = 0 indicates FCS received correctly (CRC = FOB8 or = 0)
CRC-16 preset to O's on 8-bit characters specified by PSCARs-lO:
RERR = 1 indicates CRC-16 received correctly (CRC = 0).
RERR = 0 indicates CRC-16 error (CRC~)
VRC specified by PCSARs-,o:
RERR = 1 indicates VRC error
RERR = 0 indicates VRC is correct.
ABSOLUTE MAXIMUM RATINGS'
PARAMETER
RATING
UNIT
TA
Operating ambient temperature 2
Note 4
°C
TSTG
Storage temperature
-65 to +150
°C
Input or output voltages with respect to GND3
--{).3to +15
V
With respect to GND
--{).3 to+7
V
Vee
NOTES:
1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operation sections of this specification is not
implied.
2. For operating at elevated temperatures the device must be derated based on +150°C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging eHects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range
and operating supply range.
November 5, 1990
37
Product Specification
Philips Components-Signetics Data Communication Products
SCN2652/SCN68652
Multi-protocol communications controller (MPCC)
DC ELECTRICAL CHARACTERISTICS1, 2
LIMITS
PARAMETER
TEST CONDITIONS
Min
Input voltage
Low
Vil
High
VIH
Power supply current
Max
UNIT
V
0.8
2.0
V
Output voltage
Low
VOL
-VOH
High
Icc
Typ
IOl = 1.6mA
IOH =-1001lA
Vcc
0.4
2.4
=5.25V, TA =ODC
150
Leakage current
Input
III
Output
IOl
VIN =0 to 5.25V
VOUT =0 to 5.25V
10
10
Capacitance
C IN
Input
Output
COUT
VIN =OV, I = 1MHz
VOUT =OV, I = 1MHz
20
rnA
itA
pF
20
AC ELECTRICAL CHARACTERISTlCS1, 2, 3
1 MHz CLOCK VERSION
PARAMETER
Min
Set-up and hold time
Address/control set-up
tACS
Address/control hold
tACH
Data bus set-up (write)
tos
Data bus hold (write)
tOH
Receiver
serial data set-up
tRXS
Receiver serial data hold
tRxH
50
0
50
0
150
150
Pulse width
RESET
tRES
DBEN
tOBEN
250
250
Delay Time
Data bus (read)
IoD
Transmit serial data
tTxO
DBEN to DBEN delay
IoBENO
Max
Typ
2MHz CLOCK VERSION
Min
Typ
Max
UNIT
ns
50
0
50
0
150
150
ns
m4
250
250
m4
ns
170
250
200
325
200
200
IoF
Data bus Iloat time (read)
150
150
ns
I
Clock (RxC, TxC) frequency
1.0
2.0
MHz
Clock high (MM = 0)
340
ns
165
tclKl
Clock high (MM = 1)
490
240
tclK2
Clock low
490
240
tclKo
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specilied. See ordering code table for applicable temperature range
and operating supply range.
2. All voltage measurements are referenced to ground. All time measurements are at 0.8V or 2.0V. Input voltage levels for testing are O.4V and
2.4V.
3. Output load Cl = 100pF.
4. m = TxC low and applies to writing to TDSRH only.
November 5, 1990
38
Product Specification
Philips Components-Signetics Data Communication Products
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TIMING DIAGRAMS
RESET
RESET AND WRITE DATA BUS
DBEN
-----1--
IDBEN----I'-------
'ACS
R~ET-t= IRES~--
'ACH
CEo RIW, --""""',-+------+-.....~
BnE _ _ _~_~
'ACS
+_~-----
Oo-D,5 ------~"'"',,....:;;::.:..-w---+--w-"'Fl-:o""'An"'N.,.,G,-
(READ) -;,.:;,;;;..;;,.;;~-::"'-:"=:'I'-.....:.c:::;:-t--'I'::--7,D:;;F;..;;,.;;.;..:;..-
Do-D,S
---w---i------+--w-----
(WRITE) --...Jf'.--1------+-~----
'DH
'DS
CLOCK
TxSO
I
ir------------r---------------
!
*'------.-------
I- TXo--.!
I
I
RxC
---)
~
'eLKO
I
RxSI
______
--i~1
f
---+- --I'
'eLK.
'RxS
I
'RxH
I
-...J~. T f'--------I
November 5, 1990
39
PhilipsComponents--Signetics Data Communication Products
Product Specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TIMING DIAGRAMS (Continued)
TRANSMIT - START OF MESSAGE
--------'
TxA
NOTES:
1. SYNC may be 5 to 8 bits and will contain parity bit as specified.
2. TxA goes high relative to TxC rising edge after TSOM has been set and TxE has been raised.
3.
TxBE 9086 low relative to DBEN falling edge on the first write transfer into TOSA. It is reasserted 1 TxC time before the first bit of the transmitted SYNC/FLAG. TxBE then goes
low relative 10 OBEN falling edge when writing Into TDSR H and/or roSR l • It is reasserted on the rising edge of the TxC that corresponds 10 the transmission of the last bit of each
character. except In BOP mode when the CRe is to be sent as the next character (see Transmit Timing-End of Message).
TRANSMIT - END OF BOP MESSAGE
TxSO
NEXT TO LAST CHAR
TxBE1
DBEN
NOTES:
1. TxBE goes low relative to the failing edge d OBEN corresponding 10 loading TOSF\n. It goes high one TxC before character transmission begins and also when TxA has been
dropped.
2. TxE can be dropped before resetting TEOM if Tl(BE (corresponding to the closing FLAG) is high. Alternatively TxE can remain high and a new message Initiated.
3. TxA goes low after TxE has been dropped and 1 112 TxC's after the last bit of the closing FLAG has been transmitted.
November 5, 1990
40
Product Specification
Philips Components-Signetics Data Communication Products
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TIMING DIAGRAMS Continued)
TRANSMIT TIMING - END OF BCP MESSAGE
TxSO
NEXT TO LAST CHAR
LAST CHAR
CRC'
MARK
TxBE
LOAD LAST CHAR
DBEN~
SET TEOM
-Jr1
RES~~TE_O_M
_____________________________
__________
TxE
TxA
NOTE:
1. When SCN2652 generated CRe Is not required. TEOM should only be set if SYNCs are to foltowthe message blocK. In that case, TxE should be dropped in response to TxBE
(which corresponds to the start of transmission of the last character). When CRe is required, TxE must be dropped before CAe transmission is complete. Otherwise, the contents of TxDB will be shifted out on Tx50. This facilitates transmission of contiguous rressages.
TRANSMIT UNDERRUN
L
DBE~
_ _____________
~SETTSOM
~
NOTES:
1.
TxU goes active relative to Txe falling edge it TxBE has not been serviced after n-l/2 TxC times (where n = transmit character length). TxU is reset on the Txe falling edge
2.
An underrun will occur a1tha next charader boundary H TEOM is reset and the transmitter remains enabled, unless the T50M command is asserted or a character is loaded into
the TxDB.
following assertion of the T50M command.
November 5, 1990
41
Product Specification
Philips Components-Signetics Data Communication Products
Multi·protocolcommunications controller (MPCC)
SCN2652/SCN68652
RECEIVE - START OF MESSAGE
'''C~::~~~_r-:lRXOA2_ _ _ _ _ _--I
___-,
2nd CHAR READY
TO BE REAO-
OBEN
sp~~
_______________________________
RXEJ
NOTES:
1. AxA goes high relative to failing edge of Rxe when RxE is high and: a. A data character following two SYNC's is ;n RxDB (BCP mode). b. Character following FLAG Is In RxDB
(BOP primary station mode). c. Character following FLAG is in RxDB and character matches the secondary station address or all parties address (BOP secondary station mode).
2. RxOA goes high on Axe falling edge when a character in, RxDB is ready to be read. It comes up before RxSA and goes low on the failing edge of DBEN when RxDB Is read.
3. s/F goes high relative to rising edge of Axe anytime a SYNC (BCP) or FLAG (BOP) is detected.
RECEIVE END OF MESSAGE
RxC
RxOA
RoSA' _ _ _ _---1
OBEN
(8-BlT)---------'
~F~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
1-------------------------,
I
NOTES:
1. At Ihe end of a BOP message. RxSA goes high when FlAG detection ($IF 1) forces REOm to be set. Processor should read the last data character (ROSRd and status (ROSRHl
which resets RxDA and RxSA respectively. For BCP end of message, RxSA may not be set and S/F _ O. The processor should read the last data character and status.
2. RxE must be dropped for 9CP with non-contiguous messages. It may be left on at the end of a BOP message (see BOP Receive Operation).
3. RxA is reset relative to the falling edge of RxC after the closing FLAG of a BOP message (REOM ., 1 and RxSA active.) or when RxE is dropped.
November 5, 1990
42
Philips Components-Signetics Data Communication Products
Product Specification
SCN2652/SCN68652
Multi-protocol communications controller (MPCC)
TYPICAL APPLICATIONS
SCN2652 MPCC MICROPROCESSOR INTERFACE
RESET
TxC
DATA BUS
RxC
8-BIT
MPCC
SCN2652
~P
ADDRESS CONTROL
SYNCHRONOUS
A2-AO, RIW OBEN CE
TxSO
MODEM
RxSI
MODEM
CONTROL
lOGIC
RxE
TxE
DCD
CTS
RTS, CTS,
DTR, DSR,
DCD
NOTES,
1.
2.
3.
4.
5.
Possible lAP interrupt requests are: RxDA RxSA TxBE TxU
Other SCN2652 status signals and possible uses are S F line Idle Indicator, frame delimiter. RxA handshake on RxE, line turn around control. TxA handshake on TxE, IlnEl turn
around control.
Line drivers/receivers (LD/LR) convert EIA to TTL vOltages and vice-versa.
RTS should be dropped alter the CRe (BCP) or FLAG (BOP) has been transmrtted. ThiS lorces CTS low and TxE low.
Corresponding high and low ofder bits 01 DB must be OR lied.
DMA/PROCESSOR INTERFACE
DATA BUS
1
WORD COUNT
RDREO
S OR 16 BITS
n
RxA
TxBE
RxSA
TxA
ADDRESS PTR
RIWCONTROl
DB15--DBOO
PROCESSOR (PI
AND
SUPPORT LOGIC:
1. INITlAUZES
SCN2652
2. SETS/RESETS
TSOM, TEOM
3. RESPONDS
TO RxSA
TxE
DMA
CONTROllER
SCN2652
ADDRESS AND
CONTROL
ADDRESS
I1IW CONTROLS
SCN2652
TxU
SIF
A2-AO
BYTE
I1IW
CE
DBEN
RESET
_
RxDA
f--
TxBE
I1IW
MEMORY
MM
ADDRESS. HIW,
CONTROL
RxC TxC RxSI TxSO
iii
~
MODEM OR DCE
SYSTEM ADDRESS AND CONTROL BUS
For non·DMA operation TxBE and RxDA are set to the processor which then loads or reads data characters as required.
November 5, 1990
DATA BUS
RxE
TO PRotESSOA
WRREot
n
J
0815--0800
RxDA
43
ADDRESS,
CE, RIW
Philips Components-Signetics Data Communication Products
Product Specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TYPICAL APPLICATIONS (Continued)
CHANNEL INTERFACE
COMPUTER
MPCC
SCN.65.
OR
TERMINAL
COMPUTER
OR
TERMINAL
MPCC
SCN2652
RxSI
No Modem - DC Baseband Transmission
SCN2652/SCN2653 INTERFACE TYPICAL PROTOCOLS:
BISYNC, OOCMP, SOLC, HOLC
INTERRUPTS
l~
TxBE TxU RxDA., RxSA
II
087-080
MPCC
SCN.55.
A.
A1
AO
r---
TxD
I---
RxD
I-- TxC
RIW
I---
DBEN
CE
RxC
DBnDO
CPU
L----{)
CEO
PGC
SCN2653
A1
RIW
AO
CEf
i
November 5, 1990
!
44
\lIT
(OPEN DRAIN)
5V
I
Philips Components-Signetics
Document No.
853"'{)086
ECN No.
83082
Date of Issue
April 4, t 986
Status
Product Specification
SCN2661/SCN68661
Enhanced programmable
communications interface (EPCI)
Data Communication Products
DESCRIPTION
FEATURES
OTHER FEATURES
The Signetics SCN2661 EPCI is a
universal synchronous/asynchronous
data communications controller chip that
is an enhanced version of the SCN2651.
It interfaces easily to all a-bit and 16-bit
microprocessors and may be used in a
polled or interrupt driven system
environment. The SCN2661 accepts
programmed instructions from the
microprocessor while supporting many
serial data communications disciplines
--synchronous and asynchronous - in
the full- or half-duplex mode. Special
support for BISYNC is provided.
• Synchronous operation
• Internal or external baud rate clock
The EPCI serializes parallel data
characters received from the
microprocessor for transmission.
Simultaneously, it can receive serial
data and convert it into parallel data
characters for input to the
microcomputer.
The SCN2661 contains a baud rate
generator which can be programmed to
either accept an external clock or to
generate internal transmit or receive
clocks. Sixteen different baud rates can
be selected under program control when
operating in the internal clock mode.
Each version of the EPCI (A, B, C) has a
different set of baud rates.
- 5- to a-bit characters plus parity
- Single or double SYN operation
- Internal or external character
synchronization
- Transparent or non-transparent
mode
- Transparent mode DLE stuffing (Tx)
and detection (Rx)
- Automatic SYN or DLE-SYN
insertion SYN, DLE and DLESYN
stripping
• 3 baud rate sets
• 16 internal rates for each set
• Double-buffered transmitter and
receiver
• Dynamic character length switching
• Full- or half-duplex operation
• TTL compatible inputs and outputs
• RxC and TxC pins are short-circuit
protected
- Odd, even, or no parity
• Single +5V power supply
- Local or remote maintenance
loopback mode
• No system clock required
- Baud rate: DC to 1Mbps (lX clock)
APPLICATIONS
• Asynchronous operation
- 5- to a-bit characters plus parity
- 1, 1-1/2 or 2 stop bits transmitted
- Odd, even, or no parity
- Parity, overrun and framing error
detection
• Intelligent terminals
• Network processors
• Front-end processors
• Remote data concentrators
• Computer-to-computer links
- Line break detection and
generation
• Serial peripherals
- False start bit detection
• BISYNC adaptors
- Automatic serial echo mode
(echoplex)
- Local or remote maintenance
loopback mode
- Baud rate: DC to 1Mbps
(lX clock)
DC to 62.5kbps (16X clock)
DC to 15.625kbps
(64X clock)
45
Philips Components-Signetics Data Communication Products
Product Specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
PIN CONFIGURATIONS
DI
INDEX
CORNER
DO
vcc
RiC/BKDET
om
!ITS"
IlSI!
RESET
BRCLK
AI
TOPYIEW
TxD
NOTE:
Pin Functions the same as 2S-pin DIP.
TiEJ.\T1IlSCI«l
AD
CTS
lIJW
IlCD
TiI!DV
ORDERING CODE
Vee
PACKAGES
= +5V +5%
Commercial
Automotive
Military
DOC to +70°C
-40°C to +85°C
·55OC to +125°C
Ceramic DIP
28-Pin
0.6" Wide
SCN2661ACI F28
SCN2661BC1F28
SCN2661CCI F28
SCN2661AA1F28
SCN2661BA1F28
SCN2661CA1F28
SCN2661AMI F28
SCN2661 BMI F28
SCN2661CM1F28
Plastic DIP
28-Pin
0.6" Wide
SCN2661ACI N28
SCN2661BC1N28
SCN2661CC1N28
Contact Factory
Not Available
PlasticLCC
SCN2661AC1A28
SCN2661 BC1A28
SCN2661CC1A28
Contact Factory
Not Available
April 4, 1986
46
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
BLOCK DIAGRAM
A
DATA BUS
DO-D7
"
DATA BUS
/1
BUFFER
J--
SNE/DLE CONTROL
v
SYN 1 REGISTER
t
J
SYN 2 REGISTER
DLE REGISTER
RESET
OPERATION CONTROL
,..
MODE REGISTER 1
MODE REGISTER 2
A,
RIW
COMMAND REGISTER
~
~
t---
t----
STATUS REGISTER
"CE
J--
BAUD RATE
GENERATOR
AND
CLOCK CONTROL
TiC"ISYNC
~l-
t----
t-
MODEM
CONTROL
TRANSMIT DATA ~
HOLDING REGISTER
~
I
I
r------
~
NOTES:
• Open-draln output pin.
47
TxD
T
RECEIVER
'RiCfBKDET
.
TRANSMITIER
TRANSMIT
SHIFT REGISTER
.----
BRCLK
April 4, 1986
~
RxRllY'
RECEIVE DATA ~
HOLDING REGISTER
REcaVE
SHIFT REGISTER
I
J r-----
RxD
Philips COll1ponen~ignetics Data Communication Products
. Product Specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
ABSOLUTE MAXIMUM RATINGS1
PARAMETER
Operating ambient temperature2
Storage temperature
All voltages with respect to grouncf!
RATING
UNIT
Note 4
-65 to +150
-0.5 to +6.0
DC
DC
V
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on + 150DC maximum function temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effect of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Over recommended free-air operating temperature range and supply voltage range unless otherwise specified. For conditions shown as MIN
or MAX, use the appropriate. value specified under recommended operating conditions.
DC ELECTRICAL CHARACTERISTICS1, 2, 3
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
UNIT
0.8
V
V
0.4
V
V
10
"A
10
10
"A
"A
150
mA
Input voltage
V il
VIH
Low
High
2.0
Output voltage
IOl =2.2mA
IOH = -400"A
VOL
VOH 4
Low
High
III
Input leakage current
VIN
2.4
=0 to 5.5V
3-State output leakage current
IlH
III
Data bus high
Data bus low
Icc
Power supply current
Vo =4.0V
Vo= 0.45V
NOTES:
1. Over recommended tree-air operating temperature range and supply voltage range unless otherwise specified. For conditions shown as MIN
or MAX, use the appropriate value specified under recommended operating conditions.
2. All voltages measurements are referenced to ground. All time measurements are at the 50% level for inputs (except tBRH and IeRd and at
0.8Vand 2.0V for outputs. Input levels swing between 0.4V and 2.4V, with a transition time of oS 20ns maximum.
3. Typical values are at +25 DC, typical supply voltages and typical processing parameters.
4. lNTR, TXRIlY, RXROY and TXEfiilTIDSCF!G outputs are open-drain.
CAPACITANCE TA = 25 o C, Vcc = OV
SYMBOL.
I
Capacitance
CIN
COUT
ClIO
April 4,1986
I
Input
Output
Input/Output
PARAMETER
I
I
TEST CONDITIONS
fc = 1MHz
Unmeasured pins tied to ground
48
I
I
I
LIMITS
Min
I
I
Typ
I
I
Max
20
20
20
I
I
I
UNIT
pF
pF
pF
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
AC ELECTRICAL CHARACTERISTICS', 2, 3
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
UNIT
Pulse width
tRES
teE
Reset
Chip enable
1000
250
ns
ns
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
Setup and hold time
tAS
tAH
tes
teH
tos
tOH
tRXS
tRXH
too
toF 7
teED
Address setup
Address hold
control setup
control hold
Data setup for write
Data hold for write
RX data setup
RX data hold
row
row
150
10
300
350
Data delay time for read
Data bus floating time for read
CE to CE delay
Cl = 150pF
C l = 150pF
200
100
ns
ns
ns
4.9202
5.0738
1.0
MHz
MHz
MHz
600
Input clock frequency
fBRG
fBR~
fRfT
!xC orRXC
Baud rate generator (2661A, B)
Baud rate generator (2661 C)
1.0
1.0
dc
Baud rate High (2661 A, B)
Baud rate High (2661 C)
Baud rate Low (2661A, B)
Baud rate Low (2661 C)
!xC or RXC High
!xC or RXC Low
75
70
75
70
480
480
4.9152
5.0688
Clock width
tBRH 5
tBRH 5
tBRL 5
tBRl 5
tR/TH
tRfTl 6
tTXO
tTes
TxD delay from falling edge of !xC
Skew between TxD changing and falling edge
of !xC output"
Cl = 150pF
Cl = 150pF
ns
ns
ns
ns
ns
ns
650
0
ns
ns
NOTES:
1. Over recommended free-air operating temperature range and supply voltage range unless otherwise specified. For conditions shown as MIN
or MAX, use the appropriate value specified under recommended operating conditions.
2. All voltages measurements are referenced to ground. All time measurements are at the 50% level for inputs (except tBRH and tBRLl and at
0.8V and 2.0V for outputs. Input levels swing between 0.4V and 2.4V, with a transition time of.$ 20ns maximum.
3. Typical values are at +25'C, typical supply voltages and typical processing parameters.
4. Parameter applies when internal transmitter clock is used.
5. Under test conditions of 5.0688MHz fBRG (68661) and 4.9152MHz fBRG (68661A, B), tBRH and tBRl measured at V,H and V,L, respectively.
6. In asynchronous local loop back mode, using 1X clock, the following parameters apply: fAIT = 0.83MHz max and tRITL = 700ns min.
7. See AC load conditions.
April 4, 1986
49
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced programmable communications
interface (EPCI)
BLOCK DIAGRAM
Timing
The EPCI consists of six major sections. These
are the transmitter, receiver, timing, operation
control, modem control and SYN/DLE control.
These sections communicate with each other
via an internal data bus and an internal control
bus. The internal data bus interfaces to the microprocessor data bus via a data bus buffer.
The EPCI contains a Baud Rate Generator
(BRG) which is programmable to accept external transmit orreceive clocks orlo divide an external clock to perform data communications.
The unit can generate 16 commonly used baud
rates, anyone of which can be selected for
full-duplex operation. See Table 1.
Operation Control
Receiver
This functional block stores configuration and
operation commands from the CPU andgenerates appropriate signals to various internal sections to control the overall device operation. It
The receiver accepts serial data on the RxD
pin, converts this serial input to parallel format,
checks for bits or characters that are unique to
the communication technique and sends an
"assembled" character to the CPU.
contains read and write circuits to permit com-
munications with the microprocessor via the
data bus and contains mode registers 1 and 2,
the command register, and the status register.
Details of register addressing and protocol are
presented in the EPCI programming section of
this data sheet.
Table 1.
Transmitter
The transmitter accepts parallel data from the
CPU, converts it to a serial bit stream, inserts
SCN2661/SCN68661
the appropriate characters orbits (based on the
communication technique) and outputs a composite serial stream of data on the TxD output
pin.
Modem Control
The modem control section provides interfacing for three input signals and three outputsignals used lor "handshaking" and status
indication between the CPU and a modem.
SYN/DLE Control
This section contains control circuitry and three
8-bit registers storing the SYN1, SYN2, and
DLE characters provided by the CPU. These
registers are used in the synchronous mode of
operation to provide the characters required for
synchronization, idle fill and data transparency.
Baud Rate Generator Characteristics
68661A (BRCLK
=4 9152MHz)
MR23-20
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
68661 B (BRCLK
50
75
110
134.5
150
200
300
600
1050
1200
1800
2000
2400
4800
9600
19200
1110
1111
April 4, 1986
ACTUAL FREQUENCY
16X CLOCK
0.8kHz
1.2
1.7598
2.152
2.4
3.2
4.8
9.6
16.8329
19.2
28.7438
31.9168
38.4
76.8
153.6
307.2
PERCENT
ERROR
-{l.01
-
0.196
-{l.19
-{l.26
-
-
DIVISOR
6144
4096
2793
2284
2048
1536
1024
512
292
256
171
154
128
64
32
16
=4.9152MHz)
MR23-20
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
BAUD RATE
BAUD RATE
45.5
50
75
110
134.5
150
300
600
1200
1800
2000
2400
4800
9600
19200
38400
ACTUAL FREQUENCY
16X CLOCK
0.7279kHz
0.8
1.2
1.7598
2.152
2.4
4.8
9.6
19.2
28.7438
31.9168
38.4
76.8
153.6
307.2
614.4
50
PERCENT
ERROR
0.005
-{l.01
-
-{l.19
-{l.26
-
DIVISOR
6752
6144
4096
2793
2284
2048
1024
512
256
171
154
128
64
32
16
8
Philips Components-Signetics Data Communication Products
Product Specification
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
68661C (BRCLK = 5.0688MHz)
MR23-20
0000.
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
BAUD RATE
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
ACTUAL FREQUENCY
16XCLOCK
0.8kHz
1.2
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8
PERCENT
ERROR
0.016
-
0.253
-
3.125
DIVISOR
6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16
NOTE:
16X clock is used in asynchronous mode. In synchronous mode, clock multiplier is IX and BRG can be used only for TxC.
OPERATION
The functional operation of the 68661 is programmed by a set of control words supplied by
the CPU. These control words specify items
such as synchronous or asynchronous mode,
baud rate, number of bits per character, etc.
The programming procedure is described in the
EPCI programming section of the data sheet.
After programming, the EPCI is ready to perform the desired communications functions.
The receiver performs serial to parallel conversion of data received from a modem or equivalent device. The transmiller converts parallel
data received from the CPU to a serial bit
stream. These actions are accomplished within the framework specified by the control words.
Receiver
The 68661 is conditioned to receiver data when
the lJCO input is Low and the RxEN bit in the
commands register is true. In the asynchronous ~ode, the receiver looks for High-ta-Low
(mark to space) transition of the start bit on the
RxD input line. If a transition is detected, the
state of the RxD line is sampled again after a
delay of one-half of a bit-time. If RxD is now
high, the search for a valid start bit is begun
again. If RxD is still Low, a valid start bit is assumed and the receiver continues to sample
the input line at one bit time intervals until the
proper number of data bits, the parity bit, and
one stop bit have been assembled. The data
are then transferred to the receive data holding
register, the RxRDY bit in the status register is
set, and the l1xROY output is asserted. If the
character length is less than 8 bits, the High or-
April 4, 1986
der unused bits in the holding register are set
to zero. The parity error, framing error, and
overrun error status bits are strobed into the
status register on the poSitive going edge of
RXC' corresponding to the received character
boundary. If the stop bit is present, the receiver
will immediately begin its search for the next
start bit. If the stop bit is absent (framing error),
the receiver will interpret a space as a start bit
if it persists into the next bit timer interval. If a
break condition is detected (RxD is Low for the
entire character as well as the stop bit), only
one character consisting of ali zeros (with the
FE status bit SR5 set) will be transferred to the
holding register. The RxD input must return to
a High condition before a search for the next
start bit begins.
Pin 25 can be programmed to be a break detect
output by appropriate setting of MR27-MR24.
If so, a detected break will cause that pin to go
High. When RxD returns to mark for one RxC
time, pin 25 will go low. Refer to the Break Detection Timing Diagram.
When the EPCI is initialized into the synchronous mode, the receiver first enters the hunt
mode on a 0 to 1 transition of RxEN (CR2). In
this mode, as data are shifted into the receiver
shift register a bitata time, the contents of the
register are compared to the contents of the
SYN 1 register. If the two are not equal, the next
bit is shifted in and the comparison is repeated.
When the two registers match, the hunt mode
is terminated and character assembly mode
begins.
If single SYN operation is pro-
51
grammed, the SYN DETECT status bit is set.
If double SYN operation is programmed, the
first character assembled after SYNI must bo
SYN2 in order for the SYN DETECT bit to bo
set. Otherwise, the EPCI returns to tho hunt
mode.
(Note
that
the
sequence
SYN I-SYN 1-5YN2 will not achieve synchronization.) When synchronization has been
achieved, the EPCI continues to assemble
characters and transler then to the holding register, setting the RxRDY status bit and asserting the l1xROY output each time a character is
transferred. The PE andOE status bits are set
as appropriate. Further receipt of the appropriate SYN sequence sets the SYN DETECT status bit.
If the SYN stripping mode is
commanded, SYN characters are not transferred to the holding register. Note that the SYN
characters used to establish initial synchronization are nOllransferred to the holding register
in any case.
External jam synchronization can be achieved
via pin 9 by appropriate selling of MR27-MR24.
When pin 9 is an XSYNC input, the internal
SYN1, SYNI-SYN2, and DLE-SYNI detection is disabled. Each positive going signal on
XSYNC will cause the receiver to establish synchronization on th!3 rising edge of the next RxC
pulse. Character assembly will start with the
RxD input at this edge. XSYNC may be loweredon the next rising edge of RxD. Thisexternal synchronization will cause the SYN
DETECT status bit to be set until the status register is read. Refer to XSYNC timing diagram.
Product Specification
Phili'ps Components-Signetics Data Communication Products
Enhanced programmable communications
interface (EPCI)
Table 2.
PIN NAME
SCN2661/SCN68661
CPU-Related Signals
INPUTI
OUTPUT
PIN NO.
,
FUNCTION
I
A High on this input performs a master reset on the 68661. This signal asynchronously termi·
nates any device activity and clears the mode, command and status registers. The device assumes the idle state and remains there until initialized with the appropriate control words.
12,10
13
11
I
I
I
00-07
27,28,1,2,5-8
I/O
TXRUY
15
0
RXRDY
14
0
TXEMTI
18
0
Address lines used to select internal EPCI registers.
Read command when Low, write command when High.
Chip enable command. When Low, indicates that control and data lines to the EPCI are valid
and that the operation specified by the RW, Aland AO inputs should be performed. When High,
places the 00-07 lines in the 3-State condition.
8-bit, 3-State data bus used to transfer commands, data and status between EPCI and the CPU.
DO is the least significant bit, 07 the most significant bit.
Thisoutput is the complement of status registerbitSRO, When Low, it indicates thatthe transmit
data holding register(THR) is ready to accept a data character from the CPU. It goes High when
the data character is loaded. This output is valid only when the transmitter is enabled. It is an
open-drain output which can be used as an interrupt to the CPU.
This output is the complement of status register bit SRI. When Low, it indicates that the receive
data holding register (RHR) has a ch~acter ready for input to the CPU. It goes High when the
RH R is read by the CPU, and also when the receiver is disabled. It is an open-drain outputwhich
can be used as an interrupt to the CPU.
This output is the complement of status register bit SR2. When Low, it indicates that the transmitter has completed serialization of the last character loaded by the CPU, or that a change of
state of the USR or rrcu inputs has occurred. This output goes High when the status register
is ready by the CPU, ilthe TxEMT condition does not exist. Otherwise, the THR must be loaded
by the CPU for this line to go high. It is an open-drain output which can be used as an interrupt
to the CPU. See Status Register (SR2) for details.
RESET
21
AO,Al
row
cr
USCRG
Table 3.
Device-Related Signals
PIN NO.
INPUT!
OUTPUT
BRCLK
20
I
Clock input to the internal baud rate generator (see Table 1). Not required if external receiver
and transmitter clocks are used,
'RXC'/BKDET
25
I/O
"TXCIXSYNC
9
I/O
RxD
TxD
3
19
0
USR
22
I
mm
16
I
Receiver clock. If external receiver clock is progr"lmmed, this input controls the rate at which
the character is to be received. Its frequency is 1X, 16X or 64X the baud rate, as programmed
by mode register 1. Data are sampled on the rising edge of the clock. If internal receiver clock
is programmed, this pin can be a lX116X clock or a break detect output pin.
Transmitter clock, If external transmitter clock is programmed, this input controls the rate at
which the character is transmitted, Its frequency is 1X, 16X or 64X the baud rate, as programmed by mode register 1, The transmitted data changes on the falling edge of the clock.
If internal transmitter clock is programmed, this pin can be a 1Xl16X clock output or an external
jam synchronization input.
Serial data input to the receiver. "Mark" is High, "space" is ·Low.
Serial data output from the transmitter. "Mark" is High, "Space" is Low. Held in mark condition
when the transmitter is disabled.
General purpose input which can be used for data set ready or ring indicator condition. Its complement appears as status register bit SR7. Causes a Low output on TXEIiilT/Dsmm: when
its state changes if CR2 or CRO = 1.
Data carrier detect input. Must be Low in order for the receiver to operate. Its complement appears as status register bit SR6. Causes a Low output on TXEIiilTtUSCIlG when its state
changes if CR2 or CRO =1. If rrcu goes High while receiving, the RxC is internally inhibited.
CTS
17
I
Clear to send input. Must be Low in order for the transmitter to operate. If it goes High during
transmission, the character in the transmit shift register will be transmitted before termination.
UTR
24
0
ms
23
0
General purpose output which is the complement of command register bit CRI. Normally used
to indicate data terminal ready.
General purpose output which is the complement of command register bit CRS. Normally used
to indicate request to send. See Command Register (CR5) for details.
PIN NAME
April 4, 1986
I
FUNCTION
52
Product Specification
Philips Components-Signetics Oata Communication Products
Enhanced programmable communications
interface (EPCI)
Transmitter
The EPCI is conditioned to transmit data when
the CTS input is Low and the TxEN command
register bit is set. The 68661 indicates to the
CPU that itcan accept a character for transmission by setting the TxROY status bit and asserting the TXF!lJ'I' output. When the CPU writes
a character into the transmit data holding register, these conditions are negated. Oata are
transferred from the holding register to the
transmit shift registerwhen it is idle or has completed transmission of the previous character.
The TxROY conditions are then asserted
again. Thus, one full character time of buffering
is provided.
In the asynchronous mode, the transmitter automatically sends a start bit followed by the programmed number of data bits, the least
significant bit being sent first. It then appends
an optional odd or even parity bit and the programmed number of stop bits. If, following
transmission of the data bits, a new character
is not available in the transmit holding register,
the TxO output remains in the marking (High)
condition and the TXEliiIT~ output and
its corresponding status bit are asserted.
Transmission resumes when the CPU loads a
new character into the holding register. The
transmitter can be forced to output a continuous Low (BREAK) condition by setting the send
break command bit (CR3) High.
In the synchronous mode, when the 68661 is
initially conditioned to transmit, the TxO output
remains High and the TxROY condition is asserted until the first character to be transmitted
(usually a SYN character) is loaded by the
CPU. Subsequentto this, a continuous stream
of characters is transmitted. No extra bits (other than parity, if commanded) are generated by
the EPCI unless the CPU fails to send a new
character to the EPCI by the time the transmitter has completed sending the previous character. Since synchronous communication does
not allow gaps between characters, the EPCI
asserts TxEMTand automatically "fills" the gap
by transmitting SYN 1s, SYN 1-SYN2 doublets,
or OLE-SYN 1 doubles, depending on the state
of MR16 and MR17. Normal transmission of
the message resumes when a new character is
available in the transmit data holding register.
If the send OLE bit in the commands register is
true, the DLE character is automatically trans-
April 4, 1986
SCN2661/SCN68661
mitted prior to transmission of the message
character in the TH R.
clude the parity bit, if programmed, and does
not include the start and stop bits in asynchronous mode.
EPCI PROGRAMMING
MR14 controls parity generation. If enabled, a
parity bit is added to the transmitted character
and the receiver performs a parity check on incoming data. MR15 selects odd or even parity
when parity is enabled by MR14. In asynchronous mode, MR17and MR16 select character
framing of 1, 1.5, or 2 stop bits. (If 2X baud rate
is programmed, 1.5 stop bits defaults to 1 stop
bits on transmit.) In synchronous mode, MR17
controls the number of SYN characters used to
establish synchronization and for character fill
when the transmitter is idle. SYN 1 alone is used
if MR17 = 1, and SYN1-SYN2 is used when
MR17 = O. If the transparent mode is specified
by MR16, OLE-SYNl is used forcharacterfill
and SYN detect, but the normal synchronization sequence is used to establish character
sync. When transmitting, a OLE character in
the transmit holding register will cause a second OLE character to be transmitted. This OLE
stuffing eliminates the software OLE compare
and stuff on each transparent mode data character. If the send OLE command (CR3) is active
when a OLE is loaded into THR, only one additional OLE will be transmitted. Also, OLE stripping and OLE detect (with MR 14 = 0) are
enabled.
Prior to initiating data communications, the
68661 operational mode must be programmed
by performing write operations to the mode and
command registers. In addition, if synchronous
operation is programmed, the appropriate
SYN/OLE registers must be loaded. The EPCI
can be reconfigured atany time during program
execution. A flowchart of the initialization process appears in Figure 1.
The internal registers of the EPCI are accessed
by applying specific signals to the CE, 'RIW, A 1
and AO inputs. The conditions necessary to address each register are shown in Table 4.
The SYN1, SYN2, and OLE registers are accessed by performing write operations with the
conditionsAl =O,AO=l,andRIW=1. Thefirst
operation loads the SYNl register. The next
loads the OLE register. Reading or loading the
mode registers is done in a similar manner. The
first write (or read) operation addresses mode
register 1, and a subsequent operation addresses mode register 2. If more than the required number of accesses are made, the
intemal sequencer recycles to point at the first
register. The pointers are reset to SYN 1 register and mode register 1 by a RESET input or
by performing a read command register operation, but are unaffected by any other read or
write operation.
The 68661 register formats are summarized in
Tables 5, 6, 7 and 8. Mode registers 1 and 2 define the general operational characteristics of
the EPCI, while the command register controls
the operation within this basic framework. The
EPCI indicates its status in the status register.
These registers are cleared when a RESET input is applied.
Mode Register 1 (MR1)
Table 5 illustrates mode register 1. Bits MRll
and MR10 select the communication format
and baud rate multiplier. 00 specifies synchronous format. However, the multiplierin asynchronous format applies only if the external clock
input option is selected by MR24 or MR25.
MR 13 and MR 12 select a character length of 5,
6,7 or 8 bits. The character length does not inc-
53
The bits in the mode register affecting character
assembly and disassembly (MR12-MR16) can
be changed dynamically (during active receive/
transmit operation). The character mode register affects both the transmitter and receiver;
therefore in synchronous mode, changes
should be made only in half-duplex mode
(RxEN = 1 or TxEN = 1, but not both simultaneously = 1). In asynchronous mode, character
changes should be made when RxEN and
TxEN =Oorwhen TxEN = 1 and the transmitter
is marking in half-duplex mode (RxEN = 0).
To effect assembly/disassembly of the next received/transmitted character, MR 12 - 15 must
be changed within n bittimes of the active going
state of RXAU"i'rrxRlJ'i'. Transparent and
non-transparent mode changes (MR16) must
occur within n-l bit times of the character to be
affected when the receiver or transmitter is active. (n - smaller of the new and old character
lengths.)
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced programmable communications
interface CEPCI)
Table 4
68661 Register Addressing
CE
A,
Ao
'R/W
1
X
0
0
0
0
X
0
0
X
0
1
1
0
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
SCN2661/SCN68661
-
1
1
1
1
FUNCTION
3-State data bus
Read receive holding register
Write transmit holding register
Read status register
Write SYN1/SYN2IDLE registers
Read mode register 1/2
Write mode register 1/2
Read command register
Write command register
INI11ALRESET
NOTE:
Mode Register 1 must be wrinen
before 2 can be written. Mode Register 2
need not be programmed if external
clocks are used.
NOTE:
SYN 1 Register must be written
before SYN2 can be wrinen. and
SYN2 belore DLE can be wrinen.
Figure 1. 68661 Initialization Flowchart
April 4, 1986
54
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced programmable communications
interface (EPCI)
Table 5.
SCN2661/SCN68661
Mode Register 1 (MR1)
MR17
MR16
Sync/Async
MR15
MR14
Parity Type
Parity Control
O=Odd
1 = Even
0= Disabled
1 = Enabled
Async: Stop bit length
MR11
MR12
I
MR10
Character Length
Mode and Baud Rate Factor
00 = 5 bits
01 = 6 bits
10=7bits
11 =8 bits
00 = Synchronous tX rate
01 = Asynchronous IX rate
10 = Asynchronous 16X rate
11 = Asynchronous 64X rate
,
00 = invalid
01 = 1 stop bit
10 = 1 1/2 stop bits
11 = 2 stop bits
Sync:
Number of
SYN char
Sync:
Transparency
control
o = Double SYN
0= Normal
1 = Transparent
1 = Single SYN
1
MR13
..
NOTE: Baud rate factor In asynchronous applies only If external clock IS selected. Factor IS 16X If Internal clock IS selected. Mode must be
selected (MRll, MR10) in any case.
Table 6.
Mode Register 2 (MR2)
MR23-MR20
MR27-MR24
0000
0001
0010
0011
0100
0101
0110
0111
TxC
RxC
Pin 9
Pin 25
E
E
I
I
E
E
I
I
E
I
E
I
E
I
E
I
TxC
TxC
IX
IX
TxC
TxC
16X
16X
RxC
IX
RxC
IX
RxC
16X
RxC
16X
TxC
RxC
Pin 9
Pin 25
Mode
Baud Rate
Selection
E
E
I
I
E
E
I
I
E
I
E
I
E
I
E
I
XSYNC'
TxC
XSYNC'
IX
XSYNC'
TXC
XSYNC"
16X
RXC/TxC
BKDET
RxC
BKDET
RxC/TxC
BKDET
RxC
BKDET
sync
async
sync
async
sync
async
sync
async
See baud rates
in Table 1.
1000
1001
1010
1011
1100
1101
1110
1111
NOTES:
• When pin 9 is programmed as XSYNC input, SYN1, SYNI-SYN2, and DLE-SYNI detection is disabled.
E = External clock
I = Internal clock (BRG)
IX and 16X are clock outputs.
Table 7.
CR7
Command Register (CR)
I
CR6
Operating Mode
00 = Normal operation
01 = Async:
Automatic
Echo mode
Sync: SYN andlor DLE
stripping mode
10 = Localloopback
11 = Remote loopback
April 4, 1986
CR5
Request
to Send
o = Force l=ITS
Output High
one clock
time after
TxSR
serialization
1 = Force l=ITS
output Low
CR4
Reset Error
0= Normal
1 = Reset error
flags in
status reg.
(FE,OE,PEI
DLE detect.)
CR3
CR2
CR1
CRO
Sync/Async
Receive
Control
(RxEN)
Data Terminal
Ready
Transmit
Control
(TxEN)
Async:
0= Disable
Force Break
1 = Enable
0= Normal
1 = Force break
0= Force OTR
output High
1 = Force OTR
output Low
Sync
Send OLE
a = Normal
1 = Send DLE
55
Not applicable
in
0= Disable
1 = Enable
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced programmable communications
interface (EPCI)
TableS.
Status Register (SR)
SR7
SR6
SR5
DataSet
Ready
Data Carrier
Detect
FEISYN
Detect
0= OSRinput
is High
1 = OSRinput
is Low
0= UCUinput
is High
1 = UCUinput
is Low
Async:
0= Normal
1 = Framing
error
SR4
SR3
SR2
Overrun
PEiDLE
Detect
TxEMT
DSCHG
Async:
0= Normal
1 = Parity error
0= Normal
1 = Change in
OSRor
m;u,or
transmit
shift
register is
empty
0= Normal
1 = Overrun
error
Sync:
0= Normal
1 = SYN
detected
Mode Register 2 (MR2)
Table 6 illustrates mode regisier 2. MR23,
MR22, MR21 and MR20 control the frequency
of the internal baud rate generator (BRG). Sixteen rates are selectable for each EPCI version
(-1,-2,-3).
Versions 1 and 2 specify a
4.9152MHz TTL input at BRCLK (pin 20); version 3 specifies a 5.0688MHz input which is
identical 10 the Signetics 2651. MR23 - 20 are
don't cares' if external clocks are selected
(MR25 - MR24 = 0). The individual rates are
given in Table 1.
MR24 - MR27 select the receive and transmit
clock source (either the BRG or an external input) and the function at pins 9 and 25. Reter to
Table 6.
Command Register (CR)
Table 7 illustrates the command register. Bits
CRO (TxEN) and CR2 (RxEN) enable ordisable
the transmitter and receiver respectively. A 0to-l transition ot CR2 torces start bit search
(asyncmode) orhuntmode (sync mode) on the
secondRXC rising edge. Disabling the receiver
causes flXFlDV' to go High (inactive). If the
transmitter is disabled, it will complete the
transmission of the character in the transmit
shift register (it any) prior to terminating operation. The TxD output will then remain in the
marking state (High) while TXl'lPY and Ti(Ef;iIT
will go High (inactive). If the receiver is disabled, it will terminate operation immediately.
Any character being assembled will be neglected. A 0-10-1 transition of CR2 will initiate
start bit search (async) or hunt mode (sync).
Bits CRI (DTR) and CR5 (RTS) control the
Data at the outputs are
the logical complement of the register data.
om and RTS outputs.
In asynchronous mode, setting CR3 will force
and hold the TxD output Low (spacing condition) at the end of the current transmitted character. Normal operation resumes when CR3 is
cleared. The TxD line will go High for at least
one bit time before beginning transmission of
the next character in the transmit data holding
register. In synchronous mode, setting CR3
causes the transmission of the DLE register
April 4, 1986
SCN2661/SCN68661
Sync:
0= Normal
1 = Parity error
orDLE
received
contents prior to sending the charact'1r in the
transmit data holding register. Since this is a
one time command, CR3 does not have to be
reset by software. CR3 should be set when entering and exiting transparent mode and for all
DLE-non-DLE character sequences.
Setting CR4 causes the error flags in the status
register (SR3, SR4, and SR5) to be cleared;
this is a one time command. There is no internallatch for this bit.
When CRS (RTS) is set, the RTS pin is forced
Low. A 1-to--{) transition ofCR5wili causeRTS
to go High (inactive) one TxC time afterthe last
serial bit has been transmitted. If a I-to--{) transition of CRS occurs while data is being transmitted, RTS will remain Low (active) until both
the THR and the transmit shift register are
empty and then go High (inactive) one TxC time
later.
The EPCI can operate in one of four sub modes
within each major mode (synchronous or
asynchronous). The operational sub-mode is
determined by CR7 and CR6. CR7 - CR6 = 00
is the normal mode, with the transmitter and receive operating independently in accordance
with the mode and status register instructions.
In asynchronous mode, CR7 -CR6 = 01 places
the EPCI in the automatic echo mode.
Clocked, regenerated received data are automatically directed to the TxD line while normal
receiver operation continues. The receiver
must be enabled (CR2 = 1), but the transmitter
need not be enabled. CPU to receiver communication continues normally, but the CPU to
transmitter link is disabled. Only the first character of a break condition is echoed.
The TxD output will go High until the next valid
start is detected. The following conditions are
true while in automatic echo mode:
1. Data assembled by the receiver are automatically placed in the transmit holding
register and retransmitted by the transmitter on the TxD output.
2. The transmitter is clocked by the receive
clock.
56
3.
SRI
RxRDY
0= Receive
holding
register
empty
1 = Receive
holding
register
has data
SRO
TxRDY
0= Transmit
holding
register
busy
1 = Transmit
holding
register
empty
IxfID'i' output = 1.
4. The I xEM IIDSCRG pin will reflect only
the data set change condition.
5. The TxEN command (CRO) is ignored.
In synchronous mode, CR7 - CR6 = 01 places
the EPCI in the automatic SYN/DLE stripping
mode. The exact action taken depends on the
setting of bits MR17 and MRI6:
1. In the non-transparent, single SYN mode
(MR17 - MR16 = 10), characters in the
data stream matching SYN 1 are not
transferred to the Receive Data Holding
register (RHR).
2. In the non-transparent, double SYN mode
(MR17 - MR16 = 00), character in the
data stream matching SYN1, or SYN2 if
immediately preceded by SYN I, are not
transferred the RHR.
3. In transparent mode (MRI6 = I), character in the data stream matching DLE, or
SYNI if immediately preceded by DLE,
are not transferred to the RHA. However,
only the first DLE of a DLE-DLE pair is
stripped.
Note that automatic stripping mode does notaffectthe setting of the DLE detect and SYN detect status bits (SR3 and SR5).
Two diagnostic sub-modes can also be configured. In localloopback mode (CR7 - CR6 =
10), the following loops are connected
internally:
1. The transmitter output is connected 10 the
receiver input.
2.
om
is connected to UCU and RTS is
connected to "CTS.
3. The receiver is clocked by the transmit
clock.
4. The om, RTS and !xU outputs are held
High.
5. The"CTS, m;u, OSR and RxD inputs are
ignored.
Philips Components-Signetics Data Communication Products
Product Specification
Enhanced programmable communications
interface (EPCI)
Additional requirements to operate in the local
loopback mode are that CRO (T~EN), CRI
(DTR) and CR5 (RTS) must be set to 1. CR2
(RxEN) is ignored by the EPCI.
The second diagnostic mode is the remote
loopback mode (CR7 - CR6 = 11). In this
mode:
1. Data assembled by the receiver are automatically placed in the transmit holding
register and retransmitted by the transmitter on the TxD output.
2. The transmitter is clocked by the receiver
clock.
3. No data are sent to the local CPU, but he
error status conditions (PE, FE) are set.
4. The RXRlJ'I', TXRlJ'/', and TXEliIT/
mmFm: outputs are held High.
S. CRO (TxEN) is ignored ..
6. All other signals operate normally.
Status Register
The data contained in the status register (as
shown in Table 8) indicates receiver and transmitter conditions and modem/data set status.
SRO is the transmitter ready (TxRDY) status bit.
It, and its corresponding output, are valid only
when the transmitter is enabled. If equal to 0-,
it indicates that the transmit data holding register has been loaded by the CPU and the data
has not been transferred to the transmit register. If set equal to 1, it indicates that the holding
register is ready to accept data from the CPU.
This bitis initially set when the transmitterisenabled by CRO, unless a character has previous-
April 4, 1986
Iy been loaded into the holding register. It is not
set when the automatic echo or remote loopback modes are programmed. When this bit is
set, the TXRlJ'/' output pin is Low. In the automatic echo and remote loopback modes, the
output is held High.
SRI, the receiver ready (RxRDY) status bit, indicates the condition of the receive data holding
register. If set, it indicates that a character has
been loaded into the holding register from the
receive shift register and is ready to be read by
the CPU. If equal to zero, there is no new character in the holding register. This bit is cleared
when the CPU reads the receive data holding
register or when the receiver is disabled by
CR2. When set, the RXRlJ'I' output is Low.
The TxEMT/DSCHG bit, SR2, when set, indicates either a change of state of the USR" or
inputs (when CR2 or CRO = 1) or that the
transmit shift register has completed transmission of a character and no new character has
been loaded into the transmit data holding register. Note that in synchronous mode this bit will
be set even though the appropriate "fill" character is transmitted. TxEMTwili notgo active until
at least one character has been transmitted. It
is cleared by loading the transmit data holding
register. The DSCHG conditions is enabled
when TxEN = 1 or RxEN = 1. It is cleared when
the status register is read by the CPU. If the status reg ister is read twice and SR2 - 1 whi Ie SR6
and SR7 remain unchanged, then a TxEMT
condition exists. When SR2 is set, the TXEliIT/
DS"CHG output is Low.
rrcu
SR3, when set, indicates a received parity error
when parity is enabled by MRI4. In synchro-
57
SCN2661/SCN68661
nous transparent mode (MRI6 = 1), with parity
disabled, it indicates that a character matching
OLE register was received and the present
character is neither SYN2 or OLE. This bit is
cleared when the next character following the
above sequence is loaded into RHR, when the
receiver is disabled, or by a reset error command,CR4.
The overrun error status bit, SR4, indicates that
the previous character loaded into the receive
holding register was not ready the CPU at the
time of new received character was transferred
into it. This bit is cleared when the receiver is
disabled or by the reset error command, CR4.
In asynchronous mode, bit SRS signifies that
the received character was not framed by a
stop bit; i.e., only the first stop bit is checked.
If RHR = 0 when SR5 = 1, a break condition is
present.
In synchronous non-transparent
mode (MRI6 = 0), it indicates receipt of the
SYN 1 character in single SYN mode or the
SYNI - SYN2 pair in double SYN mode. In
synchronous transparent mode (MRI6 = 1),
this bit is set upon detection of the initial synchronizing characters (SYN or SYN 1 - SYN2)
and, after synchronization has been achieved,
when a DLE-SYN 1 pair is received. The bit is
reset when the receiver is disabled, when the
reset error command is given in asynchronous
mode, or when the status register is read by the
CP U in the synchronous mode.
rrcu
SR6 and SR7 reflect the conditions of the
andUSR"inputs, respectively. A Low input sets
its corresponding status bit, and a High input
clears it.
Philips Components-Signetics Oata Communication Products
Product Specification
Enhanced programmable communications
interface (EPCI)
Table 9
SCN2661/SCN68661
68661 EPCI VS 2651 PCI
FEATURE
PCI
EPCI
1. MR2BIT6,7
Control pins 9, 25
Not used
2. OLE detect - SR3
SR3 = 0 for OLE-OLE, OLE - SYN 1
SR3 = 1 for OLE-OLE, OLE - SYNl
3. Reset of SR3, OLE detect
Second character after OLE, or receiver disable, or CR4 = 1
Receiver disable, or CR4 = 1
4. Send OLE - CR3
One time command
Reset via CR3 on next TXRO'i'
5. OLE stuffing in transparent mode
Automatic OLE stuffing when OLE is loaded
except if CR3 = 1
None
6. SYN 1 stripping in double sync non-transparent mode
AIISYNl
First SYN 1 of pair
7. Baud rate versions
Three
8. Terminate ASYNC transmission (drop
RTS),
Reset CR5 in response to
from 1 toO
One
TXEMT changing
Reset CRO when TXEMT goes from 1 to
Then reset CR5 when TXEMT goes from
1 toO
9. Break detect
Pin 25'
FE and null character
10. Stop bit searched
One
Two
11. External jam sync
Pin9""
No
12. Oata bus timing
Improved over 2651
-
13. Oata bus drivers
Sink 2.2mA
Source 400f'A
Sink 1.6mA
Source 100f'A
NOTES:
Internal BRG used for RxC.
•• Internal BRG use.? for TxC.
AC LOAD CONDITIONS
.sv
2.2V
I 2~
L~n
OUTq
OUT=-±
r
r
CL=l~pF
NOTES:
Open-drain outputs.
CL" Load capacitance includes JIG and probe capacitance.
April 4, 1986
58
CL=~pF
o.
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
TIMING DIAGRAMS
RESET
CLOCK
'BRL
'RITL
BRCLK,
TxC, Rxe
1 - - - - MRIT - - - . ,
TRANSMIT
RECEIVE
1 BIT TIME
(1. 16. OR 64 CLOCK PERIODS4
TiC
(INPUT)
TxD
TiC
(OUTPUT)
CE _ ______
READ AND WRITE
Ao,A,
Do-OJ
(WRITE) _ _ _ _
April 4. 1986
59
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
TIMING DIAGRAMS (Continued)
TxRDY,
Tx~MT (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode])
Til:" ('X)
TxD
...
Q
i
'"
TxEN
::>
~
TiRDV
:z:
~
..'"
TiEIIT
t:E FOR
WRITE
OFTHR
DATA.
DATA 2
-D-AI'
I
T.o
w
~
~'"
0
TxEN
I 2 13
DATA 3
14 151 B
DATA.
c
DATA 4
I I'
A
I 2 13 14
DATA2
151 B
c
I
AI'
I 2 13
14
DATA 3
i 51
B
c-
D-
---.J
TiRDV
a:
:z:
~
..'"
c
TiEIIT
CEFOR
WRITE
OFTHR
DATA.
DATA 2
DATA 3
NOTES:
A .. Stan bit
B-Stopb! t
C _ Stop bit2
o .. TxO marking condition
TxEMT goes low al the beginning of the last data bit, or, if parity is enabled. at the beginning of the parity bit.
April 4, 1986
60
DATA
4
I I'
A
I2
DATA
15
4
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
TIMING DIAGRAMS (Continued)
EXTERNAL SYNCHRONIZATION WITH XSYNC
1X RxC
~
~.-1
XSYNC
I
I
I
I
I
Ie. = XSYNC SETUP TIME = 3OOno
tH
'"
=XSYNC HOLD TIME =ONE RxC
~
I
RxO
V
CHARACTER ASSEMBLY
BREAK DETECTION TIMING
Rx CHARACTER
=5 BITS, NO PARITY
Rxe + 16 0064
RxO
I
LOOK FOR START BIT
=LOW ~F RxD IS HIGH, LOOK FOR HIGH TO LOW TRANSITION)
MISSING STOP BIT DETECTED, SET FE BIT.
0--> RHR, ACTIVATE RxROY. SET BKDET PIN
RxD ~ INPUT RxSA UNTIL A MARK TO SPACE
TRANSITION OCCURS.
NOTE:
• If the stop bit is present, the start b~ search will commence immediately.
April 4, 1986
61
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
TIMING DIAGRAMS (Continued)
RxRDY (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous model)
RxD
SVNl
IGNORED
RxEN
SVNDET
STATUS"-Bl=T_--,.._ _ _ _----'
~-----------, M-------~~ r~------~~ r~--~~~
CEFOR
READ
r------' rl-----II
U
READ
STATUS
I
READ
STATUS
READ RHR
(DATAl)
READ RHR
(DATA 2)
READ RHR
(DATA 3)
READRHR
(DATA 3)
RxEN
til
i
:.:
>~[f
OVERRUN
SnTUS~B~IT_ _ _ _ _ _ _ _ _ _~--_r--------------~
CEFOR:-------------~ rf------------------~~--,
READ
READ RHR
(DATAl)
READ RHR
(DATA 3)
NOTES:
A-Slanbh
B_Stopbh t
c _ Stop bl12
0- TxD marklng condition
Only one stop bit is detected
April 4, 1986
r,r-----
62
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced programmable communications
interface (EPCI)
SCN2661/SCN68661
TYPICAL APPLICATIONS
ASYNCHRONOUS INTERFACE TO CRT TERMINAL
ADDRESS BUS
CONTROL BUS
DATA BUS
r-----'
SCN2661f68661 ~::f---~L_~~~_~M!«E----i-----'ay
BRCLKI4----j
BAUD RATE CLOCK
OSCILLATOR
CRT
TERMINAL
ASYNCHRONOUS INTERFACE TO TELEPHONE LINES
PHONE
UNE
INTERFACE
i
TELEPHONE
UNE
April 4. 1986
63
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced programmable communications
interface (EPCI)
TYPICAL APPLICATIONS (Continued)
SCN2661/SCN68661
.
SYNCHRONOUS INTERFACE TO TERMINAL OR PERIPHERAL DEVICE
ADDRESS BUS
I
CONTROL BUS
~
-'
J
I
DATA BUS
J
Ja~
R.D
T.D
SCN2661168661 RiC
TiC
SYNCHRONOUS
TERMINAL OR
PERIPHERAL
DEVICE
SYNCHRONOUS INTERFACE TO TELEPHONE LINES
PHONE
UNE
INTERFACE
SYNC
MODEM
i
TELEPHONE
UNE
ApriI4.1986
64
Philips Components-Signetics
Document No.
853-1077
ECN No.
00932
Date of Issue
November 5, 1990
Status
Product Specification
SCN2681
Dual asynchronous
receiver/transmitter (DUART)
Data Communication Products
DESCRIPTION
FEATURES
The Signetics SCN2681 Dual Universal
Asynchronous Receiverffransmitter
(DUART) is a single-chip MaS-LSI
communications device that provides
two independent full-duplex
asynchronous receiverltransmitter
channels in a single package. It
interfaces directly with microprocessors
and may be used in a polled or interrupt
driven system.
• Dual full-duplex asynchronous
receiverltransmilter
The operating mode and data format of
each channel can be programmed
independently. Additionally, each
receiver and transmitter can select its
operating speed as one of eighteen
fixed baud rates, a 16X clock derived
from a programmable counterltimer, or
an external 1X or 16X clock. The baud
rate generator and counterltimer can
operate directly from a crystal or from
external clock inputs. The ability to
independently program the operating
speed of the receiver and transmitter
make the DUART particularly attractive
for dual-speed channel applications
such as clustered terminal systems.
Each receiver is quadruply buffered to
minimize the potential of receiver
over-run or to reduce interrupt overhead
in interrupt driven systems. In addition,
a flow control capability is provided to
disable a remote DUART transmitter
when the. buffer of the receiving device
is full.
• Quadruple buffered receiver data
registers
• Programmable data format
- 5 to 8 data bits plus parity
- Odd, even, no parity orforce parity
- 1, 1.5 or 2 stop bits programmable
in 1/16-bit increments
• Programmable baud rate for each
receiver and transmitter selectable
from:
- 18 fixed rates: 50 to 38.4k baud
• Multi-function 7-bit input port
- Can serve as clock or control inputs
- Change of state detection on four
inputs
• Multi-function 8-bit output port
- Individual bit set/reset capability
- Outputs can be programmed to be
status/interrupt signals
• Versatile interrupt system
- Single interrupt output with eight
maskable interrupting conditions
- Output port can be configured to
provide a total of up to six separate
wire-aRable interrupt outputs
- One user-defined rate derived from
programmable timer/counter
• Maximum data transfer:
IX-1MB/sec, 16X-125kB/sec
- External 1X or 16X clock
• Automatic wake-up mode for multidrop
applications
• Parity, framing, and overrun error
detection
• False start bit detection
• Line break detection and generation
• Programmable channel mode
- Normal (full-duplex)
• Start-end break interrupt/status
• Detects break which originates in the
middle of a character
• On-chip crystal oscillator
• Single +5V power supply
- Automatic echo
- Local loopback
• Commercial and industrial temperatu re ranges available
- Remote loopback
• DIP and PLCC packages
• Multi-function programmable 16-bit
counter/timer
65
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
SCN2681
PIN CONFIGURATIONS
Vcc
IP4
IPS
IP&
Vee
IP2
1P2
CEN
RESET
AO
CEN
Vee
RESET
CEN
X2
X2
RESET
Xl/CLK
Xl/ClK
Xl/ClK
RXDA
RXDA
RXDA
TXDA
TXDA
TXDA
OPI
01'0
OPO
0P3
0P2
OPS
0P4
0P1
OP&
RXDa
Dl
DO
D3
D2
DS
D4
DO
D7
D3
D2
GND
DS
D4
Dl
D7
DO
D2
D6
DS
D4
D7
D6
GND
INTRN
INTRN
D6
GND
INTRN
PlNfFUNCUON
INDEX
CORNER
1
2
3
4
s
6
7
8
9
10
11
12
13
14
15
16
17
TOP VIEW
16
19
Also provided on the SCN2681 are a multipurpose 7-bit input port and a mUltipurpose
8-bit output port. These can be used as
general purpose 110 ports or can be assigned specific functions (such as clock inputs or statuslinterrupt outputs) under program control.
PIN/FUNCTION
NC
AO
IP3
A1
IP1
A2
A3
IPO
WRN
RON
RXDB
NC
TXDB
OP1
OP3
OP5
OP7
01
NC
24 INTRN
25 06
23
26 D4
27 02
28 DO
29 DP6
30 OP4
31 OP2
32 OPO
33 TXDA
34 NC
35 RXDA
36 X1ICLK
37 X2
36 RESET
3. CEN
40 IP2
41 IP&
42 IPs
43 IP4
44 VCC
D3
05
21 07
22 GND
20
The SCN2681 is available in three package
versions: 40-pin and 28-pin, both 0.6" wide
DIPs; a compact 24-pin 0.4" wide DIP; and
a 44-pin PLCC.
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
24-Pln 1
Ceramic DIP
Plastic DIP
Vcc
= +5V ±10%, TA = -40°C 10 +85°C
44-Pin
40-Pin2
44-Pln
Not available
SCN2681AE1F40
Not available
Not available
SCN2681AC1F28
SCN2681AC1F40
SCN2681AC1N24
SCN2681ACI N28
SCN2681AC1N40
Nol available
SCN2681AE1N40
Not available
Not available
Not available
SCN2681AC1A44
Not available
SC2681AE1A44
PlasticLCC
NOTES:
1. 400mil-wide DIP
2. 600mil-wide DIP
November 5, 1990
Vcc = +5V ±5%, TA = OOC 10 +70OC
28-Pln2
4D-Pln 2
Nol available
68
Philips Components-Signetics Oata Communication Products
Product Specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681
PIN DESCRIPTION
SYMBOL
APPUCABlE
TYPE
NAME AND FUNCTION
40/44
28
24
00-07
X
X
X
I/O
CEN
X
X
X
I
Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the
OUART are enabled on 00-07 as controlled by the WRN, RON and AO-A3 inputs. When
High, places the 00-07 lines in the 3-State condition.
WRN
X
X
X
I
Write Strobe: When Low and CEN is also Low, the contents of the data bus is loaded into
the addressed register. The transfer occurs on the rising edge of the signal.
RON
X
X
X
I
Read Strobe: When Low and CEN is also Low, causes the contents of the addressed register to be presented on the data bus. The read cycle begins on the falling edge of RON.
AO--A3
X
X
X
I
Address Inputs: Select the OUART internal registers and ports for read/write operations.
RESET
X
X
X
I
Reset: A High level dears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts
OPO-OP7 in the High state, stops the counter/timer, and puts Channels A and B in the inactive state, with the TxOA and TxOB outputs in the mark (High) state.
INTRN
X
X
X
0
Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more
of the eight maskable interrupting conditions are true.
Xl/ClK
X
X
X
I
Crystal I: Crystal or external clock input. A crystal or clock of the specified limits must be
supplied at all times. When a crystal is used, a capacitor must be connected from this pin to
ground (see Figure 5).
X2
X
X
I
Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must
be connected from this pin to ground (see Figure 5).
RxOA
X
X
X
I
Channel A Recefver Serial Data Input: The least significant bit is received first. "Mark" is
High, "space" is Low.
RxOB
X
X
X
I
Channel B Receive Serial Data Input: The least significant bit is received first. "Mark" is
High, "space" is Low.
TxOA
X
X
X
0
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first.
This output is held in the "mark" condition when the transmitter is disabled, idle or when operating in localloopback mode. "Mark" is High, 'space" is Low.
TxOB
X
X
X
0
Channel B Transmitter Serial Data Output: General purpose output or Channel A request
to send (RTSAN, active-Low). Can be deactivated automatically on receive or transmit.
OPO
X
X
0
Output 0: General purpose output or Channel B request to send (RTSBN, active-Low). Can
be deactivated automatically on receive or transmit.
OPI
X
X
0
Output I : General purpose output or Channel A transmitter 1X or 16X clock output, or Channel A receiver 1X clock output.
OP2
X
0
Output 2: General purpose output or open-drain, active-Low counter/timer output, or Channel B transmitter 1X clock output, or Channel B receiver 1X clock output.
OP3
X
0
Output3: General purpose output or open-drain. active-Low counterltimer output or Channel
B transmitter IX clock output, or Channel B receiver IX clock output.
OP4
X
0
Output4: General purpose output or Channel A open-drain, active-Low, RxROYA/FFULLA
output.
OP5
X
0
OutputS: General purpose output or Channel B open-drain, active-Low, RxROYB/FFULLB
output.
OP6
X
0
Output6: General purpose output or Channel A open-drain, active-Low, TxROYA output.
OP7
X
0
Output 7: General purpose output or Channel B open-drain, active-Low, TxROYB output.
IPO
X
I
Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN).
IPI
X
I
Input I : General purpose input or Channel B clear to send active-Low input(CTSBN).
IP2
X
IP3
X
November 5, 1990
X
Data Bus: Bidirectional3-State data bus used to transfer commands, data and status between the OUART and the CPU. 00 is the least significant bit.
I
Input 2: General purpose input or counterltimer external clock input.
I
Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When
the external clock is used by the transmitter, the transmitted data is clocked on the falling
edge of the clock.
67
Philips Components-Signetics Data Communication Products
Product Specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681
PIN DESCRIPTION (Continued)
SYMBOL
APPUCABLE
28
40/44
TYPE
NAME AND FUNCTION
24
IP4
X
I
Input 4: General purpose input or Channel B receiver external clock input (RxCA). When the
external clock is used by the receiver, the received data is sampled on the rising edge of the
clock.
IP5
X
I
Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When
the external cioqk is used by the transmitter, the transmitted data is clocked on the falling
edge of the clock.
IP6
X
I
Input 6: General purpose input or Channel B receiver external clock input (RxCB). When the
external ciock is used by the receiver, the received data is sampled on the rising edge of the
clock.
.
Vee
X
X
I
Power Supply: +5V supply input.
GND
X
X
I
Ground
ABSOLUTE MAXIMUM RATINGS'
SYMBOL
RATING
UNIT
TA
Operating ambient temperature range 2
PARAMETER
See Note 4
°C
TSTG
Storage temperature range
-65 to +150
°C
All voltages with respect to ground3
-{l.5 to +6.0
V
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
.
~~
2. For operating at' elevated temperatures, the device must be derated based on + 150°C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge.
Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and Vee
supply range.
.
DC ELECTRICAL CHARACTERISTICS', 2, 3
UMITS
SYMBOL
TEST CONDITIONS
PARAMETER
Vil
VIH
VIH
VIH
VOL
VOH
VOH
Input low voltage
Input high voltage (except Xl/CLK)5
Input high voltage (except XlICLK)4
Input high voltage (XlICLK)
Output low voltage
Output high voltage (except o.d. oUtputS)5
Output high voltage (except o.d. outputS)4
III
III
IXll
Input leakage current
Data bus 3-stage leakage current
XlICLK low input current
IX1H
XlICLK high input current
IX2l
IX2H
lac
lace
X2 low input current
X2 high input current
Open-{)ollector output leakage current
Power supply current
O°C to +70°C version
-40°C to +85°C version
Min
Typ
Max
UNIT
0.8
V
V
V
V
V
V
V
2
IOL =2.4mA
IOH = -4001lA
IOH = -4001JA
VIN =0 to Vee
Vo = 0.4 to Vee
VIN = 0, X2 grounded
VIN = 0, X2 floated
VIN = Vee, X2 grounded
VIN = Vee, X2 floated
VIN = 0, X lICLK floated
VIN = Vee, XlICLK floated
Vo = 0.4 to Vee
2.5
4
0.4
2.4
2.9
-10
-10
-4
-3
-1
0
-100
0
-10
-2
-1.5
0.2
3.5
-30
+30
10
10
0
0
1
10
0
100
10
150
175
IJA
IJA
mA
mA
mA
mA
IJA
IJA
IJA
mA
mA
NOTES:
1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and Vee
supply range.
2. All voltage measurements are referenced to ground (GNO). For testing, all inputs except XlICLK swing between O.4V and 2.4V with a transition time of 20ns maximum. For XlICLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of
0.8V and 2.0V as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. TA ~
BAUD RATE
GENERATOR
XlICLK
X2
I
CLOCK
SELECTORS
I
COUNTER!
TIMER
I
XTALOSC
!i~i
I
I
--
,/l
~ ...
CHANGE OF
STATE
DETECTORS (4)
"-
I
7
/
v
I
~ f--
IPCR
ACR
IPO-iP6
I
I--<
r--.
OUTPUT PORT
~
.1'-
I'-
FUNCTION
SELECT LOGIC
8
OPO-OP7
v
I
I
CSRA
CSRB
ACR
OPCR
OPR
I
CT~
CTLR
November 5, 1990
70
~
VCC
oil
GND
Philips Components-Signetics Data Communication Products
Product Specification
Dual asynchronous receiver/transmitter (DUART)
BLOCK DIAGRAM
The SCN2681 DUART consists of the following
eight major sections: data bus buffer, operation
control, interrupt control, timing, communications Channels A and B, input port and output
port. Refer to the block diagram.
Data Bus Buffer
The data bus buffer provides the interface between the external and internal data buses. It is
controlled by the operation control block to allow read and write operations to take place between the controlling CPU and the DUART.
Operation Control
The operation control logic receives operation
commands from the CPU and generates appropriate signals to internal sections to control
device operation. It contains address decoding
and read and write circuits to permit communications with the microprocessor via the data
bus buffer.
Interrupt Control
A single active-Low interrupt output (INTRN) is
provided which is activated upon the occurrence of any of eight internal events. Associated with the interrupt system are the
Interrupt Mask Register (IMR) and the Interrupt
Status Register (ISR). The IMR may be programmed to select only certain conditions to
cause INTRN to be asserted. The ISR can be
read by the CPU to detenmine all currently active interrupting conditions.
Outputs OP3-0P7 can be programmed to provide discrete interrupt outputs for the transmitter, receivers, and counter/timer.
Timing Circuits
The timing block consists of a crystal oscillator,
a baud rate generator, a programmable 1&-bit
counter/timer, and four clock selectors. The
crystal oscillator operates directly from a
3.6864MHz crystal connected across the
X1/CLK and X2 inputs. If an external clock of
the appropriate frequency is available, it may
be connected to X1/CLK. The clock serves as
the basic timing reference for the Baud Rate
Generator (BRG), the counterltimer, and other
internal circuits. A clock signal within the limits
specified in the specifications section of this
data sheet must always be supplied to the
DUART.
If an external is used instead of a crystal, both
X1 and X2 should be driven using a configuration similar to the one in Figure 5.
The baud rate generator operates from the oscillator or external clock input and is capable of
generating 18 commonly used data communications baud rates ranging from 50 to 38.4k
baud. The clock outputs from the BRG are at
16X the actual baud rate. The counterltimer
can be used as a timer to produce a 16X clock
November 5, 1990
for any other baud rate by counting down the
crystal clock or an external clock. The four
clock selectors allow the independent selection, for each receiver and transmitter, of any of
these baud rates or external timing signal.
SCN2681
port change register. The bits are cleared
when the register is read by the CPU. Any
change-of-state can also be programmed to
generate an interrupt to the CPU.
Output Port
The Countermmer (CIT) can be programmed
to use one of several timing sources as its input.
The output of the CIT is available to the the
clock selectors and can also be programmed to
be outputatOP3.lnthecountermode, the contents of the CIT can be read by the CPU and
it can be stopped and started under program
control. In the timer mode, the CIT acts as a
programmable divider.
The 8-bit multipurpose port can be used as a
general purpose output port, in which case the
outputs are the complements of the Output Port
OPR(n) = 1 results in
Register (OPR).
OP(n) = Low and vice versa. Bits of the OPR
can be individually set and reset. A bit is set by
performing a write operation at address E 16
with the accompanying data specifying the bits
to be set (1 = set, 0 = no change).
Communications
Channels A and B
Likewise, a bit is reset by a write at address F16
with the accompanying data specifying the bits
to be reset (1 = reset, 0 = no change).
Each communications channel of the
SCN2681 comprises a full-duplex asynchronous receiver/transmitter (UART). The operating frequency for each receiver and transmitter
can be selected independently from the baud
rate generator, the counter timer, orfrom an external input.
The transmitter accepts parallel data from the
CPU, converts it to a serial bit stream, inserts
the appropriate start, stop, and optional parity
bits and outputs a composite serial stream of
data on the TxD output pin. The receiver accepts serial data on the RxD pin, converts this
serial input to parallel format, checks for. start
bit, stop bit, parity bit (if any), or break condition
and sends an assembled character to the CPU.
The input port pulse detection circuitry uses a
38.4kHz sampling clock derived from one olthe
baud rate generator taps. This results in a sampling period of slightly more than 25j.1s (this assumes that the clock input is 3.6864MHz). The
detection circuitry, in order to guarantee that a
true change in level has occurred, requires two
successive samples at the new logic level be
observed. As a consequence, the minimum
duration of the signal change is 25j.1s if the
transition occurs 'coincident with the first sample pulse". The 50j.ls time refers to the situation
in which the change-of-state is 'just missed"
and the firstchange-of-state is not detected until 25j.1s later.
Input Port
The inputs to this unlatched 7-bit port can be
read by the CPU by perfonming a read operation at address D16. A High input results in a
logic 1 while a Low input results in a logic O. D7
will always read as a logic 1. The pins of this
port can also serve as auxiliary inputs to certain portions fo the DUART logic.
Four change-of-state detectors are provided
which are associated with inputs IP3, IP2, IP1
and I PO. A High-to-Low or Low-to-High transition of these inputs lasting longer than 25 50j.ls, will set the corresponding bit in the input
71
Outputs can be also individually assigned specific functions by appropriate programming of
the Channel A mode registers (MRI A, MR2A),
the Channel B mode registers (MRt B, MR2B),
and the Output Port Configuration Register
(OPCR).
.
OPERATION
Transmitter
The SCN2681 is conditioned to transmit data
when the transmitter is enabled through the
command register. The SCN2681 indicates to
the CPU that it is ready to accept a character by
setting the TxRDY bit in the status register.
This condition can be programmed to generate
an interrupt requestatOP60rOP7 and INTRN.
When a character is loaded into the Transmit
Holding Register (THR), the above conditions
are negated. Data is transferred from the holding register to transmit shift register when it is
idle or has completed transmission of the previous character. The TxRDY conditions are
then asserted again which means one full character time of buffering is provided. Characters
cannot be loaded into the THR while the transmitter is disabled.
The transmitter converts the parallel data from
the CPU to a serial bit stream on the TxD output
pin. It automatically sends a start bit followed
by the programmed number of data bits, an optional parity bit, and the programmed number of
stop bits. The least significant bit is sent first.
Following the transmission of the stop bits, if a
new character is not available in the THR, the
TxD output remains High and the TxEMT bit in
the Status Register (SR) will be set to 1. Transmission resumes and the TxEMT bit is cleared
when the CPU loads a new character into the
THR.
If the transmitter is disabled, it continues operating until the character currently being transmitted is completely sent out. The transmitter
Philips Components-Signetics Data Communication Products
Product Specification
Dual asynchronous receiver/transmitter (DUART)
can be forced to send a continuous Low condition by issuing a send break command.
Thetransmittercan be reset through a software
command. If it is reset, operation ceases immediately and the transmitter must be enabled
through the command register before resuming
operation. If CTS operation is enable, ·the
CTSN input must be Low in order for the
character to be transmitted. If it goes High in
the middle of a transmission, the character in
the shift register is transmitted and TxDA then
remains in the marking state until CTSN goes
Low. The transmitter can also control the deactivation of the RTSN output. If programmed,
the RTSN output will be reset one bit time after
the character in the transmit shift register and
transmit holding register (if any) are completely
transmitted, if the transmitter has been disabled.
Receiver
The SCN2681 is conditioned to receive data
when enabled through the command register.
The receiver looks for a High-to-Low
(mark-to-space) transition of the start bit on the
RxD input pin. If a transition is detected, the
state of the RxD pin is sampled each 16X clock
for71/2clocks (16Xclock mode) oralthe next
rising edge of the bit time clock (1 X clock
mode). If RxD is sampled High, the start bit is
invalid and the search for a valid start bit begins
again. If RxD is still Low,a valid start bit is assumed and the receiver continues to sample
the input atone bit time intervals at the theoretical center of the bit, until the proper number of
data bits and parity bit (if any) have been assembled, and one stop bit has been detected.
The least .significant bit is received first. The
data is then transferred to the Receive Holding
Register (RHR) and the RxRDY bit in the SR is
set to a 1. Thi s concjition can be programmed
to generate an interrupt at OP4 or OP5 and
Table 1 ..
A2'
A1
AO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
.1
1
0
0
0
1
0
1
1
1
1
After the stop bit is detected, the receiver will
immediately look for the next start bit. However, if a non-zero character was received without
a stop bit (framing error) and RxD remains Low
for one half of the bit period after the stop bit
was sampled, then the receiver operates as if
a new start bit transition had been detected at
thatpoint(one-half bit time after the stop bitwas
sampled).
The parity error, framing error, overrun error
and received break state (if any) are strobed
into the SR at the received character boundary,
before the RxRDY status bit is set. If a break
condition is detected (RxD is Low for the entire
character including the stop bit), a character
consisting of all zeros will be loaded into the
RH R and the received break bit in the SR is set
to 1. The RxD input must return to a High
condition for at least one-half bit time before a
search for the next start bit begins.
TheRHRconsistsofaFirst-ln-First-Out(FIFO)
stack with a capacity of three characters. Data
is loaded from the receive shift register into the
topmost empty position of the FIFO. The
RxRDY bit in the staius register is set whenever
one or more characters are available to be
read, and a FFULL status bit is set if all three
stack positions are filled with data. Either of
these bits can be selected to cause an interrupt.
A read of the RHR outputs the data at the top
olthe FIFO. After the read cycle, the data FIFO
and its associated status bits (see below) are
'popped' thus emptying a FIFO position for new
data.
In addition to the data word, three status bits
(parity error, framing error, and received break)'
are also appended to each data character in the
FIFO (overrun is not). Status can be provided
in two ways, as programmed by the error mode
control bit in the mode register. In the 'character' mode, status is provided on a character-by-character basis; the status applies only
to the character at the top of the FIFO..In the
'block' mode, the status provided in the SR for
these three bits is the logical-OR of the status
for all characters coming to the top of the FIFO
since the last 'reset error' command was issued. In either mode reading the SR does not
affect the FIFO. The FIFO is 'popped' only
when the RHR is read. Therefore the status register should be read prior to reading the FIFO.
If the FIFO is full when a new character is received, that character is held in the receive shift
register until a FIFO position is available. If an
additional character is received while this state
exits, the contents of the FIFO are not affected;
the character previously in the shift register is
lost and the overrun error status bit (SR[4] will
be set-upon receipt of the start bit of the new
(overrunning) character).
The receiver can control the deactivation of
RTS. If programmed to operate in this mode,
the RTSN output will be negated when a valid
start bit was received and the FIFO is full.
When a FIFO position becomes available, the
RTSN output will be re-assertedautomatically.
This feature can be used to prevent an overrun,
in the receiver, by connecting the RTSN output
to the CTSN input of the transmitting device.
If the receiver is disabled, the FIFO characters
can be read. However, no additional characters
can be received until the receiver is enabled
again. If the receiver is reset, the FIFO and all
of the receiver status, and the corresponding
output ports and interrupt are reset. No additional characters can be received until the receiver is enabled again.
SCN2681 Register AddreSsing
A3
1
1
1
1
INTRN. If the character length is less than eight
bits, the most significant unused bits in the RHR
are set to zero.
SCN2681
1
1
1
1
0
0
0
0
1
1
1
1
November 5, 1990
1
1
1
0
1
1
0
0
1
1
0
0
0
,
1
0
1
0
1
1
0
1
1
READ (RON
= 0)
Mode Register A (MRI A, MR2A)
Status Register A (SRA)
'Reserved'
Rx Holding Register A'(RHRA)
Input Port Change Register (IPCR)
Interrupt Status Register (ISR)
Countermmer Upper (CTU)
Countermmer Lower (CTJ._)
Mode Register B (MRI B; 'MR2B)
Status Register (SRB)
'Reserved'
Rx Holding Register B (RHRB)
'Reserved'
Input Port
Start Counter Command
Stop Counter Command
a
72
WRITE (WRN
= 0)
Mode Register A (MR1A, MR2A)
Clock Select Register A (CSRA)
Command Register A (CRA)
Tx Holding Register A (THRA)
Aux. Control Register (ACR)
Interrupt Mask Register (IMR)
CIT Upper Register (CRUR)
CIT Lower Register (CTLR)
Mode Register B (MRI B, MR2B)
Clock Select Register B (CSRB)
Command Register B (CRB)
Tx Holding Register B (THRB)
'Reserved'
Output Port Conf. Register (OPCR)
Set Output Port Bits Command
Reset Output Port Bits Command
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
Multidrop Mode
The DUART is equipped with a wake up mode
for multidrop applications. This mode is selected by programming bits MRIA[4:3] or
MRI 8[4:3] to 'II' forChannelsAand B, respectively. In this mode of operation, a 'master' station transmits an address character followed by
data characters for the addressed 'slave' station. The slave stations, with receivers that are
normally disabled, examine the received data
stream and 'wakeup' the CPU (by setting
RxRDY) only upon receipt of an address character. The CPU compares the received address to its station address and enables the
receiver if it wishes to receive the subsequent
data characters. Upon receipt of another address character, the CPU may disable the receiver to initiate the process again.
A transmitted character consists of a start bit
the programmed number of data bits, and Ad:
dresslData (AID) bit, and the programmed
number of stop bits. The polarity of the
transmitted AID bit is selected by the CPU by
programming
bit
MRIA[2]/MRI8[2].
MRIA[2]/MRI8[2] = 0 transmits a zero in the
AID bit position, which identifies the corresponding
data bits
as
data
while
MRIA[2]/MRI 8[2] = I transmits aone in the AI
D bit position, which identifies the corresponding data bits as an address. The CPU should
program the mode register prior to loading the
corresponding data bits into the THR.
In this mode, the receiver continuously looks at
the received data stream, whether it is enabled
or disabled. If disabled, it sets the RxRDY status bit and loads the character into the RHR
FIFO if the received AID bit is a one (address
tag), but discards the received character if the
received AID bit is a zero (data tag). If enabled,
all received characters are transferred to the
CPU via the RHR. In either case, the data bits
are loaded into the data FIFO while the AID bit
is loaded into the status FI FO position normally
used for parity error (SRA[5] or SR8[5]). Framing error, overrun error, and break detect operate normally whether or not the receive is
enabled.
PROGRAMMING
The operation of the DUART is programmed by
writing control words into the appropriate regis-
November5,1990
ters. Operational feedback is provided via status registers which can be read by the CPU.
The addressing of the registers is described in
Table I.
The contents of certain control registers are initialized to zero on RESET. Care should be exercised if the contents of a register are changed
during operation, since certain changes may
cause operational problems.
For example, changing the number of bits per
character while the transmitter is active may
cause the transmission of an incorrect character. In general, the contents of the MR, the
CSR, and the OPCR should only be changed
while the receiver(s) and transmitter(s) are not
enabled, and certain changes to the ACR
should only be made while the CIT is stopped.
Mode registers I and 2 of each channel are accessed via independent auxiliary pointers. The
pointer is set to MRtx by RESET or by issuing
a 'reset pointer' command via the corresponding command register. Any read or write of the
mode register while the pointer is at MRI x,
switches the pointer to MR2x. The pointer then
remains at MR2x, so that subsequent accesses
are always to MR2x unless the pointer is reset
to MR I x as described above.
Mode, command, clock select, and status registers are duplicated for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions.
The reserved registers at addresses H'02' and
H'OA' should never be read during normal operation since they are reserved for internal
diagnostics.
MR1A - Channel A Mode
Register 1
MRI A is accessed when the Channel A MR
pointer points to MRI. Thepointeris setto MRI
by RESET or by a 'set pointer' command
applied via CRA. After reading or writing
MRI A, the pointer will point to MR2A.
MR1A[7] - Channel A Receiver
Request-to-Send Control
This bit controls the deactivation of the RTSAN
output(OPO) by the receiver. This output is normally asserted by setting OPR[O] and negated
by resetting OPR[O]. MRIA[7] = I causes
RTSAN to be negated upon receipt of a valid
73
SCN2681
start bit if the Channel A FIFO is lull. However,
OPR[O] is not reset and RTSAN will be asserted
again when an empty FIFO position is available. This feature can be used for flow control
to prevent overrun in the receiver by using the
RTSAN output signal to control the CTSN input
01 the transmitting device.
MR1A[6]- Channel A Receiver
Interrupt Select
This bit selects either the Channel A receiver
ready status (RxRDY) or the Channel A FIFO
lull status (FFULL) to be used lor CPU interrupts. Italso causes the selected bit to be output on OP4 if it is programmed as an interrupt
output via the OPCR.
MR1A[5]-ChanneJ A
Error Mode Select
This bit select the operating mode 01 the three
FIFOed status bits (FE, PE, received break) lor
Channel A. In the 'character' mode, status is
provided on a character-by-character basis;
the status applies only to the character at the
top 01 the FIFO. In the 'block" mode, the status
provided in the SR for these bits is the ace\1mulation (logical-OR) of the status lor all characters coming to the top 01 the FIFO since the last
'reset error' command lor Channel A was issued.
MR1A[4:31- Channel A Parity Mode Select
If 'with parity' or 'force parity' is selected a parity
bit is added to the transmitted character and the
receiver performs a parity check on incoming
dataMRIA[4;3] + II selects Channel Ato operate in the special multidrop mode described in
the Operation section.
MR1A[2]- Channel A Parity Type Select
This bit selects the parity type (odd or even) il
the 'with parity' mode is programmed by
MRIA[4;3], and the polarity of the forced parity
bit if the 'force parity' mode is programmed. It
has no effect il the 'no parity' mode is programmed. In the special multidrop mode it selects the polarity of the AID bit.
MRI A[1 :D]- Channel A Bita Per Character
Select
This field selects the number of data bits per
character to be transmitted and received. The
character length does not include the start, parity, and stop bits,
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
Table 2.
.SCN2681
Register Bit Formats
MR1A
MR1B
BIT 7
BIT6
BITS
RxRTS
CONTROL
RxlNT
SELECT
ERROR
MODE
o =No
O=RxRDV
1= FFULL
O=Char
1 = Block
1 =Ves
BIT7
BIT6
CHANNEL MODE
00 = Normal
01 = Auto-Echo
10 = Local loop
11 = Remote loop
MR2A
MR2B
BIT 4
BIT 3
BIT 2
PARITY MODE
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multidrop Mode
BITS PER
CHARACTER
0= Even
1 = Odd
00 =5
01 =6
10 = 7
11 =8
BIT 3
BITS
BIT 4
TxRTS
CONTROL
CTS
ENABLETx
0= No
1 = Ves
O=No
1 =Ves
BITO
BITl
PARITY
TYPE
BIT 2
BIT 0
BIT 1
STOP BIT LENGTH'
0=0.563
1 = 0.625
2 = 0.688
3 = 0.750
4 = 0.813
5 = 0.875
6 = 0.938
7 = 1.000
8 = 1.563
9 = 1.625
A = 1.688
B = 1.750
C = 1.813
D=I.875
E=I.938
F = 2.000
NOTE:
"Add 0.5 to values shown for 0 - 7 if channel is programmed for 5 bitS/char.
BIT7
BIT6
CRA
CRB
BIT3
BIT 2
BITI
BITO
See Text
See Text
BIT6
BIT3
BIT2
BITI
BITO
MISCELLANEOUS COMMANDS
BITS
DISABLETx
ENABLETx
DISABLERx
ENABLE Rx
See Text
0= No
1 = Yes
0= No
1 = Ves
0= No
1 = Ves
0= No
1 = Yes
Not usedmust be 0
SRA
SRB
BIT4
TRANSMITTER CLOCK SELECT
CSRA
CSRB
BIT7
BITS
RECEIVER CLOCK SELECT
BIT4
BIT 7
BIT6
BITS
BIT4
BIT3
BIT2
BITI
BIT 0
RECEIVED
BREAK"
FRAMING
ERROR"
PARITY
ERROR"
OVERRUN
ERROR
TxEMT
TxRDY
FFULL
RxRDY
0= No
1 = Ves
0= No
1 = Ves
0= No
1 = Ves
0= No
1 = Ves
0= No
1 = Ves
0= No
1 = Ves
0= No
1 = Ves
0= No
1 = Ves
NOTE:
" These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from
the top of the FIFO together with bits (4:0). These bits are cleared by a "reset error status" command. In character mode they are discarded
when the corresponding data character is read from the FIFO.
OPCR
BfT7
BIT6
BITS
BIT4
OP7
OP6
OPS
OP4
o =OPR[7]
1 = TxRDVB
0=OPR[6j
1 = TxRDVA
0=OPR[5j
1 = RxRDVI
FFULLB
0= OPR[4j
1 = RxRDYI
FFULLA
BIT 7
BIT 6
BITS
BIT 4
ACR
November5,1990
BRGSET
SELECT
COUNTERITIMER
MODE AND SOURCE
O=set 1
1 =set2
See Table 4
74
BIT 2
BIT3
BIT 0
BIT 1
OP3
OP2
00=OPR[3j
01 = CIT OUTPUT
10 = TxCB(lx)
11 = RxCB(lx)
11 =OPR[2j
01 = TxCA(16x)
10 = TxCA(lxl
11 = RxCA(1 xl
BIT3
BIT2
BIT 1
BITO
DELTA
IP31NT
DELTA
IP21NT
DELTA
IPllNT
DELTA
IPOINT
0= Off
1 =On
0=011
1 =On
O=Off
1 =On
0=011
1 =On
Philips Components-Signetics Data Communication Products
Product Specification
Dual asynchronous receiver/transmitter (DUART)
Table 2.
SCN2681
Register Bit Formats {Continued)
IPCR
ISR
IMR
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
BITl
BITO
DELTA
IP3
DELTA
IP2
DELTA
IP 1
DELTA
IPO
IP3
IP 2
IP 1
IPO
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= Low
1 = High
0= Low
1 = High
O=Low
1 = High
0= Low
1 = High
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
BITl
BITO
INPUT
PORT
CHANGE
DELTA
BREAK B
RxRDYI
FFULLB
TxRDYB
COUNTER
READY
DELTA
BREAK A
RxRDYI
FFULLA
TxRDYA
0= No
1 = Yes
O=No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
O=No
1 = Yes
0= No
1 = Yes
O=No
1 = Yes
0= No
1 = Yes
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
BITl
BITO
IN. PORT
CHANGE
INT
DELTA
BREAK B
INT
RxRDYI
FFULLB
INT
TxRDYB
INT
COUNTER
READY
INT
. DELTA
BREAK A
INT
RxRDYI
FFULLA
INT
TxRDYA
INT
O=Off
1 =On
O=Off
1 =On
0= Off
1 =On
O=Off
1 =On
o = Off
1 =On
O=Off
1 =On
O=Off
1 =On
o = Off
1 =On
BIT7
BIT6
BITS
BIT4
BIT 3
BIT2
BITl
BITO
CIT[l5)
CIT[14]
C/T[13]
C/T[12]
CIT[ll]
CIT[10]
CIT[9]
C/T[S]
CTUR
BIT7
BIT6
BIT 5
BIT4
BIT3
BIT2
BITl
BITO
CIT[7]
CIT[6]
CfT[5]
CIT[4]
CIT[3]
CIT[2]
CfT[l]
C/T[O]
CTLR
MR2A - Channel A Mode
Register 2
4. The Channel A TxRDY and TxEMT status
bits are inactive.
5. The transmitter must be enabled, but the
receiver need not be enabled.
MR2A is accessed when the Channel A MR
pointer points to MR2, which occurs after any
access to MR1A. Accesses to MR2A do not
change the pointer.
5. The received parity is checked, but is not
regenerated for transmission, i.e. transmitted parity bit is as received.
6. CPU to transmitter and receiver communications continue normally.
6. Character framing is checked, but the
stop bits are retransmitted as received.
MR2A[7:6]- Channel A Mode
Select
Each channel of the DUART can operate in one
of four modes. MR2A[7:6] = 00 is the normal
mode, with the transmitter and receiver operating independently. MR2A[7:6] = 01 places the
channel in the automatic echo mode, which automatically retransmits the received data. The
following conditions are true while in automatic
echo mode:
1. Received data is reclocked and retransmitted on the TxDA output
Two diagnostic modes can also be configured.
MR2A[7:6] = 10 selects local loopback mode.
In this mode:
1. The transmitter output is internally connected to the receiver input
2. The receive clock is used for the
transmitter.
2. The transmit clock is used for the
receiver.
3. The receiver must be enabled, but the
transmitter need not be enabled.
3. The TxDA output is held High.
November 5, 1990
7. A received break is echoed as received
until the next valid start bit is detected.
B. CPU to receiver communication continues
normally, but the CPU to transmitter link is
disabled.
4. The RxDA input is ignored.
75
The second diagnostic mode is the remote
loopback mode, selected by MR2A[7:6] = 11.
In this mode:
1. Received data is reclocked and retransmitted on the TxDA output
2. The receive clock is used for the
transmitter.
3. Received data is not sent to the local
CPU, and the error status conditions are
inactive.
4. The received parity is not checked and is
not regenerated for transmission, Le.,
transmitted parity is as received.
5. The receiver must be enabled.
6. Character framing is not checked and the
stop bits are retransmitted as received.
7. A received break is echoed as received
until the next valid start bit is detected.
Philips Components-Signetics Data Communication Products
Product Specification
Dual'asynchronous receiver/transmitter (DUART)
The user must exercise care when switching
into and out of the various modes. The selected mode will be activated immediately upon
mode selection, even if this occurs in the middle
of a received or transmitted character. Likewise, if a mode is deselected the device will
switch outof the mode immediately. An exception to this is switching out of autoecho or remote loopback modes: if the deselection
occurs just after the receiver has sampled the
stop bit (indicated in autoecho by assertion of
RxRDY), and the transmitter is .enabled, the
transmitter will remain in autoecho mode until
the entire stop has been retransmitted.
MR2A(5]-Channel A Transmitter Request-to-Send Control
This bit controls the deactivation of the RTSAN
output (OPO) by the transmitter. This output is
normally asserted by setting OPR[O] and negated by resetting OPR[O). MR2A[5] = 1
. caused OPR[O] to be reset automatically one
bit time after the characters in the Channel A
transmit shift register and in the THR, if any, are
completely transmitted including the programmed number of stop bits, if the transmitter
is not enabled. This feature can be used to automatically terminate the transmission of a
message as follows:
1. Program auto-reset mode: MR2A[5] = 1.
2. Enable transmitter.
3. Asset RTSAN: OPR[O] = 1.
4. Send message.
5. Verify the message is sent by waiting until
the transmit ready .status (TxRDY) is asserted. Disable transmitter after the last
character is loaded into the Channel A
THR.
6. The last character will be transmitted and
OPR[O] will be reset one bit time after
the last stop bit, causing RTSAN to be
negated.
MR2A[4]- Channel A.Clear-to-Send Control
IfthisbitisO, CTSAN has no effect on thetrans-'
mitter. If this bit is aI, the transmitter checks
the state of CTSAN (IPO) each time it is ready
to send a character. If IPO is asserted (Law),
the character is transmitted. If it is negated.
(High), the TxDA output remains in the marking
state and the transmission is delayed until
CTSAN goes Low. Changes in CTSAN while
a character is being .transmitted do not affect
the transmission of that character..
MR2A[3:0]- Channel A Stop Bit Length
Select
Thisfield programs the length of the stop bitappended to the transmitted character. Stop bit
lengths of .563 TO 1 AND .563 to 2 bits. In in-
November5,1990
crements of 0.625 bit, can be programmed for
character lengths of 6, 7,andSbits. Forachar·
acter lengths of 5 bits, 1.0625 to 2 stop bits can
be programmed in increments of .0625 bit.
The receiver only checks for a 'mark' condition
althe center of the first stop bit position (one bit
time after the last data bit, or after the parity bit
is enabled) in all cases.
" an external 1X clock is used for the transmitter, MR2A[3] = 0 selects one stop bit and
MR2A[3] = 1 selects two stop bits to be trans·
mitted.
SCN2681
The receiverclockis always a 16Xclockexcept
for CSRA[7] = 1111.
CSRA(3:0]- Channel A Transmitter Clock
Select
This field selects the baud rate clock for the
Channel A transmitter. The field definition is as
per CSR[7:4] except as follows:
CSRA(3:0]
1110
0111
ACR(7] = 0
IP3-16X
IP3-1X
Baud Rate
ACR[7] = 1
IP3-16X
IP3-1 X
MR1 B - Channel B Mode
Register 1
The transmitter clock is always a 16X clockex·
cepltor CSR[3:0] = 1111.
MRI B is accessed when the Channel B MR
pointer points to MRI. ThepointerissetloMRl
by RESET or by a 'set pointer' command
applied via CRB. After reading or writing
MRI B, the pointer will point to MR2B .
CSRB - Channel B Clock Select
Register
MR2B - Channel B Mode
Register 2
MR2B is accessed when the Channel B MR
pointer points to MR2, which occurs after any
access to MRI B. Accesses to MR2B do not
. change the pointer.
The bit definitions for mode registers 1 and 2
are identical to the bit definitions for.MRA and
MR2A except that all control actions apply to
the Channel B receiver and transmitter and the
corresponding inputs and outputs.
CSRA -Channel A Clock Select
Register
CSRA[7:4]- Channel A Receiver Clock
Select
This field selects the baud rate clock for the
Channel A receiver as follows:
CSRA[7:4]
ACR[7] =0
Baud Rate
ACR[7] = 1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
50
110
134.5
200
300
600
1,200
1,050
2,400
4,SOO
75
110
134.5
150
300
600
1,200
2,000
2,400
4,SOO
CS!lA[7:4]
ACR[7] =0
Baud Rate
ACR[7] = 1
7,200
9,600
3S.4k
limer
IP4-16X
IP4-1X
I,SOO
9,600
19.2k
limer
IP4-16X
IP4-1X
1010
1011
1100
1101
1110
1111
76
CSRB(7:4]- Channel B Receiver Clock
Select
This field selects the baud rate clock for the
Channel B receiver. The field definition is as
per CSRA[7:4] excepras follow~:
CSRB[7:4]
1110
0111
ACR(7] = 0
IPS-16X
lPG-IX
Baud Rate
ACR(7] = 1
IP6-16X
IPG-l'X
The receiver clock is always a 16Xclockexcept
for CSRB[7:4] = 1111.
CSRB(3:0]- Channel B Transmitter Clock
Select
This field selects the baud rate clock for the
Channel B transmitter. The field definition is as
per CSRA[7:4] except as follows:
CSRB(3:4]
1110
0111
ACR(7] = 0
Baud Rate
ACR(7] = 1
IPS-16X
IPS-IX
IPS-16X
. IPS-IX
The transmitter clock is always a 16X clock except for CSRB[3:0] = 1111.
CRA - Channel A Command
Register
CRA is a register used to supply commands to
Channel A. Multiple commands can be speci'fied in a single write to CRA as long as the commands are non-conflicting, e.g., the 'enable
transmitter' and 'reset transmitter' commands
cannot be specified in a single command word.
CRA[6:4]- Channel A Miscellaneous
Command
The encoded value of this field may be used to
specify a single command as follows:
CRA[6:4]
COMMAND
000 No command.
001
Reset MR pointer. Causes the Channel
A MR pointer to point to MRI.
Philips Components--Signetics Data Communication Products
Product Specification
Dual asynchronous receiver/transmitter (DUART)
010
011
100
101
110
111
Reset receiver. Resets the Channel A
receiver as if a hardware reset had been
applied. The receiver is disabled and
the FIFO is flushed.
Reset transmitter. Resets the Channel
A transmitter as if a hardware reset had
been applied.
Reset error status. Clears the Channel
A Received Break, Parity Error, and
Overrun Error bits in the status register
(SRA[7:4]). Used in character mode to
clear OE status (although RB, PE and
FE bits will also be cleared) and in block
mode to clear all error status after a
block of data has been receiVed.
Reset Channel A break change interrupt. Causes the Channel A break detect change bit in the interrupt status
register (ISR[2]) to be cleared to zero.
Start break. Forces the TxDA output
Low (spacing). If the transmitter is
emptythestartofthebreakconditionwill
be delayed up to two bit times. If the
transmitter is active the break begins
when transmission of the character is
completed. If a character is in the THR,
the start of the break will be delayed until
that character, or any other loaded
subsequently are transmitted.
The
transmitter must be enabled for this
command to be accepted.
Stop break. The TxDA line will go High
(marking) within two bit times. TxDAwili
remain High for one bit time before the
next character, if any, is transmitted.
CRA[3) - Disable Channel A
Transmitter
This command terminates transmitter operation and reset the TxDRY and TxEMT status
bits. However, if a character is being transmitted or if a character is in the THR when the
transmitter is disabled, the transmission of the
character(s) is completed before assuming the
inactive state.
CRA[2)- Enable Channel A
Transmitter
Enablesoperation of the Channel A transmitter.
The TxRDY status bit will be asserted.
CRA[1)- Disable Channel A Receiver
This command terminates operation of the receiver immediately - a character being receivedwill be lost. The command has no effect
on the receiver status bits or any other control
registers. If the special multidrop mode is programmed, the receiver operates even ifitisdisabled. See Operation section.
CRA[O)- Enable Channel A Receiver
Enables operation of the Channel A receiver.
If not in the special wakeup mode, this also
November 5, 1990
forces the receiver into the search for start-bit
state.
CRB - Channel B Command
Register
CRB is a register used to supply commands to
Channel B. Multiple commands can be specified in a single write to CRB as long as the commands are non-conflicting, e.g., the 'enable
transmitter' and 'reset transmitter' commands
cannot be specified in a single command word.
The bit definitions for this register are identical
to the bit definitions forCRA, except that all control actions apply to the Channel B receiver and
transmitter and the corresponding inputs and
outputs.
SRA - Channel A Status
Register
SRA[7] - Channel A Received Break
This bit indicates that an all zero character of
the programmed length has been received
without a stop bit. Only a single FIFO position
is occupied when a break is received: further
entries to the FIFO are inhibited until the RxDA
line to the marking state for at least one-half a
bit time (two successive edges olthe internal or
external 1X clock).
When this bit is set, the Channel A 'change in
break' bit in the ISR (ISR[2]) is set. ISR[2) is
also set when the end of the break condition, as
defined above, is detected.
The break detect circuitry can detect breaks
that originate in the middle of a received character. However, if a break begins in the middle
of a character, it must persist until at least the
end of the next character time in order for it to
be detected.
SRA[6)-Channel A Framing Error
This bit, when set, indicates that a stop bit was
not detected when the corresponding data
character in the FIFO was received. The stop
bit check is made in the middle of the first bit position.
SRA[S)- Channel A Parity Error
This bit is set when the 'with parity' or 'force parity' mode is programmed and the corresponding character in the FIFO was received with
incorrect parity.
In the special multidrop mode the parity error bit
stores the receive AID bit.
SRA[4) - Channel A Overrun Error
This bit, when set indicates that one or more
characters in the received data stream have
77
SCN2681
been lost. Itis set upon receipt of anew character when the FI FO is full and a character is already in the receive shift register waiting for an
empty FIFO position. When this occurs, the
character in the receive shift register (and its
break detect, parity error and framing error status, if any) is lost.
This bit is cleared by a 'reset error status' command.
SRA[3) - Channel A Transmitter Empty
(TxEMTA)
This bit will be set when the Channel A transmitter underruns; i.e., both the Transmit Holding
Register (THR) and the transmit shift register
are empty. It is set after transmission of the last
stop bit of a character.il no character is in the
THRawaiting transmission: Itis reset when the
THR is loaded by the CPU or when the transmitter is disabled.
SRA[2)- Channel A Transmitter Ready
(TxRDYA)
This bit, when set, indicates that the THR is
empty and ready to be loaded with a character.
This bit is cleared when the THR is loaded by
the CPU and is set when the character is transferred to the transmit shift register. TxRDY is
reset when the transmitter is disabled and is set
when the transmitter is first enabled, viz., characters loaded into the THR while the transmitter
is disabled will not be transmitted.
SRA[1)- Channel A FIFO Full (FFULLA)
This bit is set when a character is transferred
from the receive shift register to the receive
FIFO and the transfer causes the FIFO to become full, i.e., all three FIFO positions areoccupied. It is reset when the CPU reads the RHR.
If a character is waiting in the receive shift register because the FIFO is full, FFULL will not be
reset when the CPU reads the RHR.
SRA[O)- Channel A Receiver Ready
(RxRDYA)
This bit indicates that a character has bee'; received and is waiting in the FIFO to be read by
the CPU. It is set when the character is transferred from the receive shift to the FIFO and reset when the CPU reads the RHR, if after this
read there are not more characters still in the
FIFO.
SRB - Channel B Status
Register
The bit definitions for this register are identical
to the bit definitions for SRA, except that all status applies to the Channel B receiver and transmitter and the corresponding inputs and
outputs.
Philips Components--Signetics Data Communication Products
Product Specification
Dual asynchronous receiver/transmitter (DUART)
OPCR - Output pon
Configuration Register
OPCR[7) - OP7 Output Select
This bit programs the OP7 output to provide
one of the following:
- The complement of OPR[7).
- The Channel 8 transmitter interrupt output
which is the complement of TxRDY8.
When in this mode OP7 acts as an OpenCollector output. Note that this output is
not masked by the contents of the IMR.
OPCR[6]- OP6 Output Select
This bit programs the OP6 output to provide
one of the following:
- The complement of OPR[6].
- The Channel A transmitter interrupt output
which is the complement of TxRDYA.
When in this mode OP6 acts as an OpenCollector output. Note that this output is
not masked by the contents of the IMR.
OPCR[S]- OPS Output Select
This bit programs the OP5 output to provide
one of the following:
- The complement of OPR[5].
- The Channel 8 transmitter interrupt output
which is the complement of ISR[5]. When
in this mode OP5 acts as an Open-Collector output. Note that this output is not
masked by the contents of the IMR.
OPCR[4]- OP4 Output Select
This field programs the OP4 output to provide
one of the following:
- The complement of OPR[4].
ceived data. If data is not being received,
a free running 1X clock is output.
OPCR[1 :0]- OP2 Output Select
This field programs the OP2 output to provide
one of the following:
- The complement of OPR[2].
- The 16X clock for the Channel A transmitter. This is the clock selected by
CSRA[3:0], and will be a 1X clock if
CSRA[3:0] = 1111.
- The IX clock for the Channel A transmitter,
which is the clock that shifts the transmitted data. If data is not being transmitted, a free running 1X clock is output.
- The 1X clock for the Channel A receiver,
which is the clock that samples the received data. If data is not being received,
a free running 1X clock is output.
ACR - Auxiliary Control
Register
ACR[7) - 8aud Rate Generator Set Select
This bit selects one of two sets of baud rates to
be generated by the 8RG:
Set 1:
Set 2:
50, 110, 134.5,200,300,600,
1.05k, 1.2k, 2.4k, 4.8k, 7.2k, 9.Sk,
and 3B.4k baud.
75,110,134.5,150,300, SOD, l.2k,
1.8k, 2.0k, 2.4k, 4.Bk, 9.Sk, and
19.2kbaud.
The selected set of rates is available for use by
the Channel A and 8 receivers and transmitters
as described in CSRA and CSR8. 8aud rate
generator characteristics are given in Table 3.
- The Channel 8 transmitter interrupt output
which is the complement of ISR[I]. When
in this mode OP4 acts as an Open-Collector output. Note that this output is not
masked by the contents of the IMR.
ACR[6:4]- Countermmer Mode And
Clock Source Select
this field selects the operating mode of the
counterltimer and its clock source as shown in
Table 4.
OPCR[3:2]- OP3 Output Select
This bit programs the OP3 output to provide
one of the following:
- The complement of OPR[3].
ACR[3:0]-IP3, IP2,IP1, IPO
Change-of-State Interrupt Enable
This field selects which bits of the input port
change register (IPCR) cause the input change
bit in the interrupt status register (ISR[7]) to be
set. If a bit is in the 'on' state the setting of the
corresponding bit in the IPCR will also result in
the setting of ISR[7), which results in the generation of an interrupt output if IMR[?] = 1. If a bit
is in the 'off' state, the setting of that bit in the
IPCR has no effect on ISR[?].
- The counter/timer output, in which case
OP3 acts as an Open-Collector output. In
the timer mode, this output is a square
wave at the programmed frequency: In the
counter mode, the output remains High until terminal count is reached, at which time
it goes Low. The output returns to the High
state when the counter is stopped by a
stop counter command. Note that this out,
put is not masked by the contents of the
IMR.
- The IX clock for the Channel 8 transmitter,
which is the clock that shifts the transmitted data. If data is not being transmitted, a free running IX clock is output.
- The IX clock for the Channel 8 receiver,
which is the clock that samples the raNovember 5, 1990
IPCR - Input Pon Change
Register
IPCR[7:4j-IP3, IP2, IP1, IPO
Change-of-State
These bits are'set when a change-of-state, as
defined in the input port section of this data
sheet, occurs at the respective input pins. They
are cleared when the IPCRis read by the CPU.
78
SCN2681
A read of the IPCR also clears ISR[7], the input
change bit in the interrupt status register. The
setting of these bits can be programmed to
generate an interrupt to the CPU.
IPCR[3:0j-IP3, IP2,IP1, IPO
Current State
These bits provide the current state of the respective inputs. The information is unlatched
and reflects the state of the input pins at the
time the IPCR is read.
ISR - Interrupt Status Register
This register provides the status of all potential
interrupt sources. The contents of this register
are masked by the Interrupt Mask Register
(IMR). If a bit in the ISR is a '1' and the corresponding bit in the IMR is also a '1', the INTRN
output will be asserted. If the corresponding bit
in the IMR is a zero, the state of the bit in the
ISR has no effect on the INTRN output. Note
that the I MR does not mask the reading of the
ISR -the true status will be provided regardless
of the contents of the I MR. The contents of this
register are initialized to 00 ,6 when the DUART
is reset.
ISR(7) -Input Port Change Status
This bit is a '1' when a change-of-state has occurred at the IPO, IP 1, IP2, or IP3 inputs and
that event has been selected to cause an interrupt by the programming of ACR[3:0]. The bit
is cleared when the CPU reads the IPCR.
ISR[6] - Channel B Change In Break
This bit, when set, indicates that the Channel 8 .
receiver has detected the beginning or the end
of a received break. It is reset when the CPU
issues a Channel 8 'reset break change interrupl' command.
ISR[S]- Channel B Receiver Ready
or FIFO Full
The function of this bit is programmed by
MRI8[S]. If programmed as receiver ready, it
indicates that a character has been received in
Channel 8 and is waiting in the FIFO to be read
by the CPU. It is set when the character is
transferred from the receive shift register to the
FIFO and reset when the CPU reads the RHR.
If after this read there are more characters still
in the FIFO the bit will be set again after the
FIFO is 'popped'. If programmed as FIFO full,
itis set when a character is transferred from the
receive holding register to the receive FIFO and
the transfer caused the Channel 8 FIFO to become full; i.e., all three FIFO positions are occupied. It is reset when the CPU reads the RHR.
If a character is waiting in the receive shift register because the FIFO is full, the bit will be set
again when the waiting character is loaded into
the FIFO.
ISR[4]- Channel B Transmitter Ready
This bit is a duplicate of TxRDY8 (SR8[2]).
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
ISR[3]- Counter Ready,
In the counter mode, this bit is set when the
counter reaches terminal count and is reset
when the counter is stopped by a stop counter
command.
In the timer mode, this bit is set once each cycle
of the generated square wave (every other time
thatthe counter/timerreaches zero count). The
bit is reset by a stop counter command. The
command, however, does not stop the counterl
timer.
ISR[2)- Channel A Change in Break
This bit, when set, indicates that the Channel A
receiver has detected the beginning or the end
of a received break. It is reset when the CPU
issues a Channel A 'reset break change interrupt' command.
ISR[l)- Channel A Receiver Ready Or
FIFO Full
The function of this bit is programmed by
MRl A[6]. If programmed as receiver ready, it
indicates that a character has been received in
Channel A and is waiting in the FIFO to be read
by the CPU. It is set when the character is
transferred from the receive shift register to the
FIFO and reset when the CPU read the RHR.
IF afterthis read there are more characters still
in the FIFO the bit will be set again after the
FIFO is 'popped'. If programmed as FIFO full,
it is set when a character is transferred from the
receive holding registerto the receive FIFOand
the transfer caused the Channel A FIFO to become full; i.e., all three FIFO positions are occupied. Itis reset when the CPU reads the RHR.
If a character is waiting in the receive shift register because the FIFO is full, the bit will be set
again when the ISR[O) and IMR waiting character is loaded into the FIFO.
IMR - Interrupt Mask Register
The programming of this register selects which
bits in the ISR causes an interrupt output. If a
bit in the ISR is a '1' and the corresponding bit
in the IMR is also a '1' the INTRN output will be
asserted. If the corresponding bitin the IMR is
a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR
does not mask the programmable interrupt outputs OP3-OP7 or the reading of the ISR.
CTUR and CTLR - Counter/Timer
Registers
The CTUR and CTlR hold the eight MSBs and
eight lSBs, respectively, of the value to be
used by the counter/timer in either the counter
or timer modes of operation. The minimum value which may be loaded into the CTURlCTlR
registers is 0002,6, Note that these registers
are write-only and cannot be read by the CPU.
In the timer (programmable divider) mode, the
CT generates a square wave with a period of
twice the value (in clock periods) of the CTUR
and CTlR.
If the value in CTURand CTlRis changed, the
current half-period will not be affected, but subsequent half periods will be. In this mode the
CIT runs continuously. Receipt of a start counter command (read with A3-AO = 1110) causes
the counter to terminate the currenttiming cycle
and to begin a new cycle using the values in
CTUR and CTlR.
The counterready status bit (ISR[3]) is set once
each cycle of the square wave. The bit is reset
by a stop counter command (read with A3-AO
= 1111). The command however, does not stop
the CIT. The generated square wave is output
on OP3 if it is programmed to be the CIT
output.
SCN2681
On power up and after reset, the timer/counter
runs in timer mode and can only be restarted.
Because it cannot be shut off or stopped, and
runs continuously in timer mode, it is recommended that at initialization, the output port
(OP3) should be masked off through the
OPCR[3:2] = 00 until the TIC is programmed to
the desired operational state.
In the counter mode, the CIT counts down the
numberof pulses loaded into CTUR and CTlR
by the CPU. Counting begins upon receipt of
a counter command. Upon reaching terminal
count (0000,6), the counter ready interrupt bit
(ISR[3]) is set. The counter continues counting
past the terminal count until stopped by the
CPU. If OP3 is programmed to be the output
of the CIT, the output remains High until terminal count is reached, atwhich time it goes low.
The output returns to the High state and ISR[3]
is cleared when the counter is stopped by a stop
counter command. The CPU may change the
values of CTUR and CTlR at any time, but the
new count becomes effective only on the next
start counter command. If new values have not
been loaded, the previous countvalues are preserved and used for the next count cycle.
Inthecountermode, the current value of the upper and lower 8 bits of the counter (CTU, CTl)
may be read by the CPU.
It is recommended that the counter be stopped
when reading to prevent potential problems
which may occur if a carry from the lower 8 bits
to the upper 8 bits occurs between the times
that both halves of the counter are read. However, note that a subsequent start counter command will cause the counter to begin a new
count cycle using the values in CTUR and
CTlR.
ISR[O)-Channel A Transmitter Ready
This bit is a duplicate of TxRDYA (SRA[2]).
Tab[e 3.
Bit Rate Generator Characteristics Crystal or Clock -- 3 6864MHz
NORMAL RATE (BAUD)
50
75
110
134.5
150
200
300
600
1050
1200
1aOO
2000
2400
4800
7200
9600
19.2k
38.4k
ACTUAL 16x CLOCK (kHz)
ERROR(%)
0.8
1.2
1.759
2.153
2.4
3.2
4.8
9.6
16.756
19.2
28.8
32.056
38.4
76.8
115.2
153.6
307.2
614.4
0
0
-0.069
0.059
0
0
0
NOTE, Duty cycle of 16x clock IS 500Yo ± 10Yo.
November 5, 1990
79
0
-0.260
0
0
0.175
0
0
0
0
0
0
Philips Components-Signetics Data Communication Products
Product Specification
SCN2681
Dual asynchronous receiver/transmitter (DUART)
Table 4.
ACR 6:4 Field Definition
ACR6:4
MODE
CLOCK SOURCE
000
001
010
011
100
101
110
111
Counter
Counter
Counter
Counter
TImer
TImer
TImer
TImer
External (IP2)
TxCA - 1x clock of Channel A transmitter
TxCB - 1x clock of Channel B transmitter
Crystal or external clock (x1/CLK) divided by 16
External (IP2)
External (IP2) divided by 16
Crystal or external clock (x1/CLK)
Crystal or external clock (x1/CLK) divided by 16
TIMING DIAGRAMS
RESET
rf.----
----J
~_
'RES
-.J '
Figure 1. Reset Timing
CEN
'RWDRDN
IlO-D7
(READ)
FLOAT
----t-'
'RWD-l
WDN
f
'DS-
~~'DH------
_ _ _ _ _. _
(Wo::rro~
------
X
VAUD
Figure 2. Bus Timing
November 5, 1990
80
Philips Components-5ignetics Data Communication Products
Product Specification
Dual asynchronous receiver/transmitter (DUART)
---------
WRN
SCN2681
J
--------------,.\V~-------Vo.
OPO-OP7
v.}!\.
OLD DATA
NEW DATA
' - - - - - - - - - vo,
v.. =1.SV
Figure 3. Port TIming
Rg~~
...t
w."
'. ~
~R
VOL
INTERRUPT'
OUTPUT
+O.5V
_____ VOL
NOTES:
1. INTRN or OP3 - OP7 when used as interrupt outputs.
2. The test for open-drain outputs Is intended to guarantee switching of the output transistor. Measurement or this response is referenced from themidpoinl of the switching signal. Vu. 10 a
point O.5V above Va.. This point represents noise margin that assures true switching has occurred. Beyond this level. the effects of external circuitry and test environment are pronounced
and can greatly,affect the resultant msasurement.
Figure 4. Interrupt TIming
R1: 10aK - 1Meg (See design note)
+5V
C1 _ C2: Q.-5pF + (STRAY < 5pF)
DRIVING FROM
EXTERNAL SOURCE
>.>--e_-
.sV
X'ICLK
CTCLK
RxC
TxC
,Kn
X,
0--"-------1 X,
SCN2681
X2
X2
3.6864MHz
CRYSTAL SERIES RESISTANCE3 SHOULD
BE LESS THAN ,son
Figure 5. Clock Timing
November 5. 1990
81
CLOCK
TO OTHER
CHIPS
Product Specification
Philips Components-$ignetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
T'C~ (1 o:.~:Jl.~KS)
~I
. . . 't=
SCN2681
.
'L
-
~'ljo---~
~
j-f.-
(IX O U T P U T ) - - - - - - - ~
/
Figure 6. Transmit
Figure 7. Receive
T.D
TRANSMITTER
ENABLED
TxRDY
(SR2)
WRN
CTSN'
(IPO) _ _ _.J
I
n
RTSN'~
(oPO)
( ' ' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1. ( . ' - -_ __
OPR(O)
=1
OPR(O)= 1
NOTES:
1. liming shown for MR2(4} • 1.
2. lining shown for MR2(5) _ 1.
Figure 8. Transmitter Timing
November 5. 1990
82
Philips Components-5ignetics Data Communication Products
Product Specification
SCN2681
Dual asynchronous receiver/transmitter (DUART)
RxD
RECEIVER
ENABLED
RxRDY
(SRa) _ _ _ _ _ _---'
FFULL
(SR.) _ _ _ _ _ _ _ _ _ _~--------~
RxRDYI - - - - - - - - - ,
FFULL
(OPS)'
RDN - - - - - - - . ,
OVERRUN
(SR4) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~-~~
RTS' - - - -(-',
' -_ _ _ _ _ _ _ _ _ _ _ _ _----'
(oPO)
OPR(O)= •
NOTES:
1. TilTing shown for MA1{7),., 1.
2. Shown for OPCR(4) ... 1 and MR(6) .. O.
Figure 9. Receiver Timing
MASTER STAllON
I,'
",~
BIT9 I ,--Tr-!O I ~'l-('
_ _ _ _ _ _ _T./r--J'--...L....JIL..;Ac;:Dc;:D;;.:.2:..! I ~r--
BIT9
I ADD"!
TxD
BIT9
.1
DO
I
.:..J'
I
TRANSMITTER~
ENABLED
I
I
I
T(~:~
I
-----:;)--li1...~-...JI'1
,r-'
,
_ _ _ _ _ _ _ _~\,
~
WRN
MR.(...... ) = 11
MR.(2)=.
ADD#1 MR'(2) = 0
L'_ _ _ _ _ _ _ _ _ _ _ __
( < -
DO
MR. (2) =. ADD..
PERIPHERAL STAllON
r-_-rB~ITr9:.,
I
BIT 9
I
d Ii
BIT 9
.',h
"
~
I
I
:/-:_ _ _ _ _ _
AOOfl
'l-
I
L----
~~,~
STATUS DATA,
STATUS DATA,
DO
ADD.2
Figure 10. Wake-Up Mode
NovemberS. 1990
BIH
II
I
I
RD~:-lJ-~~~=========-:.-=-+--,r--~---'
MR1(4-3) = 11
BIT 9
DO=-::::~o~lll~~~~=======:,~'i---J=~~I~A~DD~I2~!~.~11~1::=~::::0I ~l-
RxD - - - - - ,
;0
I
ADDI.;
RECEIVER
I _ _ rENABUD _ _ _ _ _ _ _ _ _ _ _ _rl
83
Philips Components-Signetics
Document No.
853-1002
ECN No.
00930
Date of Issue
November 5, 1990
Status
Product Specification
SCN2681T
Dual asynchronous
receiver/transmitter (DUART)
Data Communication Products
DESCRIPTION
The Signetics SCN2681 Dual Universal
Asynchronous Receiverrrransmitter
(DUART) is a single-chip MOS-LSI
communications device that provides
two independent full-duplex
asynchronous receiverltransmitter
channels in a single package. The
SCN2681T features a faster bus cycle
time than the standard SCN2681. The
quick bus cycle eliminates or reduces
the need for wait states with fast CPUs
and permits high throughput in I/O
intensive systems. Higher external
clock rates may be used with the
transmitter, receiver and counter timer
which in turn provide greater versatility
in baud rate generation. The
SCN2681 T interfaces directly with
microprocessors and may be used in a
polled or interrupt driven system.
disable a remote DUART transmitter
. when the receiver buffer is full.
Also provided on the SCN2681T are a
multipurpose 7-bit input port and a
mUltipurpose 8-bit output port. These
can be used as general purpose I/O
ports or can be assigned specffic
functions (such as clock inputs or
status/interrupt outputs) under program
control.
For a complete functional description
and programming information for the
SCN2681T. refer to the SCN2681
product specffication.
FEATURES
• Fast bus cycle times reduce or
eliminate CPU wah states
• Dual full-duplex asynchronous
receiverltransmitters
The operating mode and data format of
each channel can be programmed
independently. Additionally, each
receiver and transmitter Can select its
operating speed as one of eighteen
fixed baud rates, a 16X clock derived
from a programmable counterltimer, or
an external 1X or 16X clock. The baud
rate generator and counterltimer can
operate directly from a crystal or from
external clock inputs. The ability to
independently program the operating
speed of the receiver and transmitter
make the DUART particularly attractive
for dual-speed channel applications
such as clustered terminal systems.
• Quadruple buffered receiver data
registers
Each receiver is quadruple buffered to
minimize the potential of receiver ~
over-run or to reduce interrupt overhead
in interrupt driven systems. In addition,
a flow control capability is provided to
• Parity, framing, and overrun error
detection
- Normal (full-duplex)
- Automatic echo
- Local loopback
- Remote loopback
• Multi-function programmable 16-bit
counterltimer
• Multi-function 7-bh input port
- Can serve as clock or control inputs
- Change of state detection on four
inputs
• Multi-function 8-bit output port
- Individual bit set/reset capability
- Outputs can be programmed to be
status/interrupt signals
• Versatile interrupt system
- Single interrupt output with eight
maskable interrupting conditions
- Output port can be configured to
provide a total of up to six separate
wire-ORable interrupt outputs
- Odd, even, no parity or force parity
• Maximum data transfer rates:
1X-I MB/sec transmitter and
receiver; 16X - 500kB/sec receiver
and 250kB/sec transmitter
- I, 1.5 or 2 stop bits programmable
in 1/16-bit increments
• Automatic wake-up mode for multidrop
applications
• Programmable data format
- 5 to 8 data bits plus parity
• Programmable baud rate for each
receiver and transmitter selectable
from:
- 18 fixed rates: 50 to 38.4k baud
- One user-defined rate derived from
programmable counterltimer
- External 1X or 16X clock
• False start bit detection
• Line break detection and generation
• Programmable channel mode
84
• Start-end break interrupt/status
• Detects"break which originates in the
middle of a character
• On-chip crystal oscillator
• Single +5V power supply
• Commercial and industrial
temperature ranges available
Product Specification
Philips Components-Signetics Data Communication Products
SCN2681T
Dual asynchronous receiver/transmitter (DUART)
PIN CONFIGURATIONS
INDEX
CORNER
Vcc
IP'
IPS
IP6
IP2
CEN
RESET
TOP VIEW
X2
X1IClK
RxDB
RxDA
TxOB
TxOA
OP1
oPO
OP3
OP2
oPS
OP.
OP7
OPS
D1
DO
D3
D2
DS
D.
D7
D6
GND
PI~/EUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
INTRN
ORDERING INFORMATION
DESCRIPTION
Vcc
= +5V +10%, TA = O'C to +70'C
40-Pin Plastic DIP (600mil-wide DIP)
SCN2681TC 1N40A
44-Pin Plastic LCC
SCN2681TC 1A44A
November 5, 1990
85
NC
AD
IP3
A1
IP1
A2
A3
IPO
WRN
RDN
RxDB
PlNfFUNCnON
23
24
25
26
27
28
29
30
31
32
33
NC
INTAN
D6
D4
D2
DO
OP6
OP4
OP2
OPO
TxDA
TxDB
34 NC
35 RxDA
OP1
OP3
OP5
OP7
D1
D3
D5
D7
GND
36
37
38
39
40
41
42
43
44
NC
X1/CLK
X2
RESET
CEN
IP2
IPS
IP5
IP4
VCC
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
BLOCK DIAGRAM
/I
00-07
8,
Z
~
"BUS BUFFER
CHANNEL A
~
TRANSMIT
HOLDING REG
f--
TRANSMIT
SHIFT REGISTER
TxDA
OPERAlION CONTROL
RDN
WRN
eEN
AD-A3
RESET
,.-
4
I
I
ADDRESS
DECODE
I
RlWCONmOL
I
:--+
I
A
j..
"
"
RECEIVE
HOLDING REG (3)
RxOA
RECEIVE
SHIFT REGISTER
f--
I
MRA1,2
CRA
SRA
INTERRUPT CONmOL
INTRN
I
IMII
ISR
~
.11
I "
-v
"
.,::>
i'!
'c"
....
6a: ~I-'~"
...z
i
0
1=
~
'"
"
-
TxDB
CHANNElB
(AS ABOVE)
RxDB
II)
liMING
INPUT PORT
CHANGE OF
STATE
DETECTORS (4)
.11
BAUD RATE
GENERATOR
v
I
I--
I
CLOCK
SELECTORS
I
I-f--
X,lClK
X2
I
COUNTERI
lIMER
I
XTAlOSC
I
I
-
IPCR
ACR
7
I
~
OUTPUT PORT
-
/I
"-
"-
."
Vt..--
v
FUNCTION
SELECT lOGIC
I
eSRA
eSRB
ACR
CTIoIl
eTlR
OPCR
OPR
8
.
86
OPO-OP7
I
..
NovemberS, 1990
IPO~P6
Vee
GND
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
PIN DESCRIPTION
MNEMONIC
TYPE
DO-D7
I/O
NAME AND FUNCTION
CEN
I
Chip Enable: Active low input signal. When low, data transfers between the CPU and the DUART are enabled on DO-D7
as controlled by the WRN, RDN, andAO-A3 inputs. When CEN is high, the DUART places the DO-D71ines in the threestate condition.
WRN
I
Write Strobe: When low and CEN is also low, the contents of the data bus is loaded into the addressed register. The
transfer occurs on the rising edge of the signal.
RDN
I
Read Strobe: When low and CEN is also low, causes the contents of the addressed register to be presented on the
data bus. The read cycle begins on the falling edge of RDN.
AO-A3
I
Address Inputs: Select the DUART internal registers and ports for read/write operations.
RESET
I
Reset: A high level clears internal registers (SRA, SRB, iMR, ISR, aPR, OPCR), puts OPO--OP7 in the high state, stops
the counter/timer, and puts channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark (high)
state.
INTRN
a
Interrupt Request: Active-low, open-drain output which signals the CPU that one or more of the eight maskable interrupting conditions are true.
XI/ClK
I
Crystal I : Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When
a crystal is used, a capacitor must be connected from this pin to ground (see Figure 5).
X2
I
Crystal 2: Connection for other side of crystal. When a crystal is used, a capacitor must be connected from this pin to
ground (see Figure 5). If XI/ClK is driven from an external source, this pin should be grounded.
RxDA
I
Channel A Receiver Serial Data Input: The least significant bit is received first. 'Mark' is high, 'space' is low.
RxDB
I
Channel B Receiver Serial Data Input: The least significant bit is received first. 'Mark' is high, 'space' is low.
TxDA
a
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. Thisoutput is held in the 'mark'
condition when the transmitter is disabled, idle, or when operating in localloopback mode. 'Mark' is high, 'space' is low.
TxDB
a
Channel B Transmitter Serial Data Output: The least significant bitis transmitted first. Thisoutput is held in the 'mark'
condition when the transmitter is disabled, idle, or when operating in localloopback mode. 'Mark' is high, 'space' is low.
OPO
a
Output 0: General purpose output, orchannel A requesllo send (RTSAN, active-low). Can be deactivated automatically
on receive or transmit.
OPI
a
Output I : General purpose output, orchannel B requesllo send (RTSBN, active-low). Can be deactivated automatically
on receive or transmit.
OP2
a
Output 2: General purpose output, or channel A transmitter I X or 16X clock output, or channel A receiver I X clock
output.
OP3
a
Output 3: General purpose output, or open-drain, active-low counter/timer output, or channel B transmitter I X clock
output, or channel B receiver I X clock output.
OP4
a
Output 4: General purpose output, or channel A open-drain, active-low, RxRDYA/FFUlLA output.
OP5
a
OutputS: General purpose output, or channel B open-drain, active-low, RxRDYBIFFUllB output.
OP6
a
Output 6: General purpose output, or channel A open-drain, active-low, TxRDYA output.
OP7
a
Output 7: General purpose output, or channel B open-drain, active-low TxRDYB output.
Data Bus: Bidirectional three-state data bus used to transfer commands, data and status between
the DUART and the CPU. DO is the least significant bit.
IPO
I
Input 0: General purpose input, or channel A clear to send active-low input (CTSAN).
IPI
I
Input 1 : General purpose input, or channel B clear to send active-low input (CTSBN).
IP2
I
Input 2: General purpose input, or counterltimer external clock input.
IP3
I
Input3: General purpose input, or channel A transmitter external clock input (TxCA). When the external clock is used
by the transmitter, the transmitted data is clocked on the falling edge of the clock.
IP4
I
Input 4: General purpose input, or channel A receiver extemal clock input (RxCA). When the external clock is used by
the receiver, the received data is sampled on the rising edge of the clock.
November 5, 1990
87
Product Specification
Philips Components-Signetics Data Communication Products
SCN2681T
Dual asynchronous receiver/transmitter (DUART)
PIN DESCRIPTION (Continued)
MNEMONIC
TYPE
NAME AND FUNCTION
IPS
I
InputS: General purpose input, or channel B transmitter external clock input (TxCB). When the external clock is used
by the transmitter, the transmitted data is clocked on the falling edge of the clock.
IP6
I
InputS: General purpose input, or channel B receiver external clock input (RxCB). When the external clock is used by
the receiver, the received data is sampled on the rising edge of the clock.
Vee
I
Power Supply: +5V supply input.
GND
I
Ground
ABSOLUTE MAXIMUM RATINGSl
SYMBOL
PARAMETER
o to +70
UNIT
,DC
Storage temperature range
-65 to "" 150
DC
All voltages with respect to GND 3
-0.5 to +6.0
Operating ambient temperature range 2
TA
TSTG
RATING
V
NOTES:
1. Stresses above those listed underApsolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on + 150 DC maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge.
Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
DC ELECTRICAL CHARACTERISTICS1, 2, 3
LIMITS
SYMBOL
TEST CONDITIONS
PARAMETER
VIL
V IH
V IH
Input low voltage
Input high voltage (except Xl/ClK)
Input high voltage (Xl/ClK)
Val
VOH
Output low voltage
Output high voltage (except o.c. outputS)4
IlL
III
Input leakage current
Data bus 3-state leakage current
IXll
Xl/ClK low input current
IX1H
Xl/ClK high input current
IX2l
IX2H
X2 low input current
X2 high input current
lac
Open-collector output leakage current
Icc
Power supply currentS
ODC to + 70 DC version
Min
Typ
Max
UNIT
0.8
V
V
V
0.4
V
V
10
10
flA
flA
0
0
1
10
0
100
mA
mA
mA
mA
flA
flA
10
flA
150
mA
2.0
3.5
IOl = 2.4mA
IOH = -400flA
2.4
VIN = 0 to Vee
Va = 0.4 to Vee
-10
-10
VIN = 0, X2 grounded
VIN = 0, X2 floated
VIN = Vee, X2 = grounded
VIN = Vee, X2 floated
VIN = 0, Xl/ClK floated
VIN = Vee, X l/ClK floated
-4
-3
-1
0
-100
0
Va = 0.4 to Vee
-10
-2
-1.5
0.2
3.5
-30
+30
NOTES:
1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and Vee
supply range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except Xl/ClK swing between 0.4V and 2.4V with a transition time of 20ns maximum. For Xl/ClK this swing is between O.4V and 4.0V. All time measurements are referenced at input voltages of
0.8V and 2.0V and output voltages of O.SV and 2.0V as appropriate.
3. Typical values are at +25 DC, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: Cl = 150pF, except interrupt outputs. Test conditions for interrupt outputs: C l = 50pF, Rl = 2.7kQ to Vee·
5. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle
and the signal negated first terminates the cycle.
November 5, 1990
88
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
AC ELECTRICAL CHARACTERISTICS1, 2, 3,4
Figure 1. Reset Timing
NOTES:
t. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and Vee
supply range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except XI/ClK swing between O.4V and 2.4V with a transition time of 20ns maximum. For XI/ClK this swing is between 0.4V and 4.0V. All time measurements are referenced at input voltages of
0.8V and 2.0V and output voltages of 0.8V and 2.0V as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7kQ to Vee.
LIMITS
SYMBOL
tRES
November 5, 1990
PARAMETER
Reset pulse width
Min
1.0
89
I
I
Max
UNIT
fLs
Product Specification
Philips Components-Signetics Data Communication Products
SCN2681T
Dual asynchronous receiver/transmitter (DUART)
AG-A3
f----+f-- tELAX
CEN
(READ)
RDN
00-07
(READ)
FLOAT
FLOAT
------1--'"'1
CEN
(WRITE)
WRN
DO-D7
(WRITE) _ _ _ _ _ _J
Figure 2. Bus Timing
LIMITS
SYMBOL
tAVEl
tElAX
tRlRH
tEHEl
tRlOA
tRlOV
tRHOI
tRHOF
tWLWH
tOVWH
tWHOI
PARAMETER'
Min
AO-A3 setup to RDN and CEN. or WRN and CEN low
RDN and CEN, or WRN and CEN low to AO-A7 invalid
RDN and CEN low to RDN or CEN high
CEN high to CEN low2. 3
CEN and RDN low to data outputs active
CEN and RDN low to data valid
CEN or RDN high to data invalid
CEN or RDN high to data outputs floating
WRN and CEN low to WRN or CEN high
Data input valid to WRN or CEN high
WRN or CEN high to data invalid
Max
UNIT
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
100
120
110
15
10
65
75
35
15
NOTES:
1. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle
and the signal negated first terminates the cycle.
2. If CEN is used as the 'strobing' input, the parameter defines the minimum high times between one CEN and the next. The RDN signal must
be negated for IEHEl to guarantee that any status register changes are valid. As a consequence, this minimum time must be met for the RDN
input even if the CEN is used as the strobing signal for bus operations.
3. Consecutive write operations to the same command register require at least three rising edges of the XI clock between writes.
NovemberS, 1990
90
Philips Components-Signetics Data Communication Products
Product Specification
Dual asynchronous receiver/transmitter (DUART)
~
SCN2681T
_. ==x~r:=_:'.jk_tPHRON
)'
(a) INPUT PINS
WRN~
r
_ '----_-_'~4~tPD_
oPO-OP7
OLD DATA
,
'
NEW DATA
(b) OUTPUT PINS
Figure 3. Port Timing
LIMITS
SYMBOL
!Ps
!PH
!PD
PARAMETER'
Min
Port input setup time before RDN low
Port input hold time after RDN high
Port output valid after WRN high
Max
UNIT
200
ns
ns
ns
0
0
NOTE:
1, For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle
and the signal negated first terminates the cycle.
""~;; "_: : : : : : : ~ ~R-J~
______
______
NOTES:
,. INTRN or OP3-0P7 when used as interrupt outputs.
2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoinl of the switching
signal, VIlA. to a point O.5V above Voc. This point represents noise margin that assures true sw~ching has occurred. Beyond this level. the effects of external circuitry and
test environment are pronounced and can greatly affect the resultant measurement.
Figure 4. Interrupt Timing
LIMITS
SYMBOL
tfR
November 5, 1990
PARAMETER
Min
INTRN (or OP3-0P7 when used as interrupts) negated from:
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
Reset command (delta break interrupt)
Stop CIT command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
91
Max
UNIT
200
200
200
200
200
200
ns
ns
ns
ns
ns
ns
Philips Components-Signetics Data Communication Products
Product Specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
DRIVING FROM
EXTERNAL SOURCE
+5V
lK
Xl
lK
X2
X>---+X1iCLKY
CTCLK
RxC
TxC
,---~----t----1Xl
SCN2681T
c==J
Rl
X2
Rl: lOOK -lMeg
C1 = C2: o-spF + (STRAY
<
3.6864MHz
5pF)
CRYSTAL SERIES RESISTANCE3 SHOULD
BE LESS THAN loon
Figure 5. Clock Timing
LIMITS
SYMBOL
!elK
felK
!eTe
feTe
tRX
fRx
tTX
fTX
PARAMETER
Xl/ClK high or low time
Xl/ClK frequency
CTClK (IP2) high or low time
CTClK (IP2) frequency 1
RxC high or low time
RxC frequency (16X{,
(lX)
TxC high or low time
TxC frequency (16X)'
(lX)'
Min
90
2
55
Typ
Max
3.686
4
4
0
8
55
8
1
0
0
110
0
0
4
1
NOTE:
1. Minimum frequencies are not tested but are guaranteed by design.
November 5, 1990
92
UNIT
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
CLOCK
TO OTHER
CHIPS
Product Specification
Philips Components-Signetics Data Communication Products
SCN2681T
Dual asynchronous receiver/transmitter (DUART)
1 BlTTIME
(1 OR 16 CLOCKS)
--1
--L.
TxC
(INPUT)
TxO
trcs
TxC - - - - - - - - - - , . .
(1X OUTPUT)
Figure 6. Transmit
LIMITS
SYMBOL
tTXD
tTCS
PARAMETER
TxD output delay from TxC low
Output delay from TxC low to TxD data output
(1XINPRJ~----'"
RXo---->t
Min
Max
UNIT
0
300
100
ns
ns
-T
,,'-_____
'"~~ ~-'~=t---Figure 7. Receive
LIMITS
SYMBOL
tRXS
tRXH
PARAMETER
RxD data setup time to RxC high
RxD data hold time from RxC high
November 5, 1990
Min
200
25
93
Max
UNIT
ns
ns
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
TxD
TlIANSMITTER
ENABLED
TxRDY
(SR2)
WRN
CTSN1
(IPO) _ _ _..J
~b:;~L
_________________________________________
~I?L-
OPR(D)= •
NOTES:
1. 11m1ng shown for MR2(4). 1.
_____
OPR(D) =.
2., Timing shown for M R2(S) ., 1.
Figure 8. Transmitter Timing
RaD
RECEIVER
ENABLED
RaRDY
(SAO) _ _ _ _ _ _--1
FFULL
(SR')
------------'f---------'
RaRDYI - - - - - - - ,
FFULL
(OPS)'
RON - - - - - - - ,
S= STATUS
0= DATA
I
I
I
D.
02
03
04
OVERRUN
liDS W I L L ) o . , . - - - + - - - - - , RESET BY
(SR4) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.,.=B::.E.:.LO"'S:..:T...J
COMMAND
RTS'--'
(OPO)
rTL----------------'
OPR(D)
=•
NOTES:
1. Timing shown for MR1(7) '"' 1.
2. Shown for OPCA(4) _ 1 and MA1(6). D.
Figure 9. Receiver Timing
November 5, 1990
94
Product Specification
Philips Components-Signetics Data Communication Products
SCN2681T
Dual asynchronous receiver/transmitter (DUART)
MASTER STATION
BIT 9
I ADIlN.!. I
I
I
I
I
TRANSMlnER~
ENABLED
I
I
T~:
------~:~r'
MR'(4-3) = 11
MR.(2)=.
ADD., MR'(2) = 0 DO
PERIPHERAL STATION
BtT9
:0 I I I
ENAB~D
MR'(2) = •
BIT 9
ADD.,!.
RECEIVER
________________
---1:'~I...---~-----J~l
BtT9
IIi
DO
-+II____
____________________
ADDn
~
I
rt\'
:011I Lt,
\
L
I
I
I
I
I
~~-------------------~--, ~~~-S-=-S-T-AT-U-S------~~'~
MR'(4-3)= 11
L...,.-J
AOD,1
DO
Figure 10. Wake-Up Mode
November 5, 1990
95
0= DATA
ADDn
Philips Components-5lgnetics
Document No.
853-1OS3
ECN No.
00933
Date of Issue
NovemberS, 1990
Status
Product Specification
SCN68681
Dual asynchronous
receiver/transmitter (DUART)
Data Communication Products
DESCRIPTION
FEATURES
The Signetics SCN68681 Dual Universal
Asynchronous ReceiverfTransmitter
(DUART) is a single-chip MOS-LSI
communications device that provides
two independent full-duplex
asynchronous receiverltransmitter
channels in a single package. It is
compatible wnh other S68000 family
devices, and can also interface easily
with other microprocessors. The
DUART can be used in polled or
interrupt driven systems.
• S68000 bus compatible
- Can serve as clock or control inputs
• Dual full-duplex asynchronous
receiverltransmitter
- Change-of-state detection on four
inputs
The operating mode and data format of
each channel can be programmed
independently. Additionally, each
receiver and transmitter can select its
operating speed as one of eighteen
fixed baud rates, a 16X clock derived
from a programmable counterltimer, or
an external 1X or l6X clock. The baud
rate generator and counterltimer can
operate directly from a crystal or from
external clock inputs. The ability to
independently program the operating
speed of the receiver and transmitter
make the DUART particularly attractive
for dual-speed channel applications
such as clustered terminal systems.
• Programmable baud rate for each
receiver arid transmitter selectable
from:
• Multi-function 6-bit input port
• Quadruple buffered receiver data
registers
• Programmable data format
- S to 8 data bits plus parity
- Odd, even, no parity or force parity
- 1, I.S or 2 stop bits programmable
in l/l6-bit increments
- 18 fixed rates: SO to 38.4k baud
- One user-defined rate derived from
programmable counterltimer
- External 1X or 16X clock
• Multi-function 8-bit output port
- Individual bit set/reset capability
- Outputs can be programmed to be
status/interrupt signals
• Versatile interrupt system
- Single interrupt output with eight
maskable interrupting conditions
- Interrupt vector output on interrupt
acknowledge
- Output port can be configured to
provide a total of up to six separate
wire-ORable interrupt outputs
• Maximum data transfer rates:
1X - 1MB/sec, 16X - 12SkB/sec
• Parity, framing, and overrun error
detection
• Automatic wake-up mode for multidrop
applications
• False start bit detection
• Start-end break interrupt/status
• Line break detection and generation
• Detects break which originates in the
middle of a character
• Programmable channel mode
- Normal (full-duplex)
• On-chip crystal oscillator
- Automatic echo
• Single +SV power supply
- Local loopback
• Commercial and industrial temperature ranges available
- Remote Ioopback
• Multi-function programmable 16-bit
counter/timer
96
• DIP and PLCC packages
Product Specification
Philips Components-Signetics Data Communication Products
SCN68681
Dual asynchronous receiver/transmitter (DUART)
Vcc
IP'
IPS
IACKN
IP.
CSN
RESETN
X2
XI/ClK
RxDB
RxDA
TxOB
TxDA
OPl
OPO
OP3
OP.
OPS
OP'
OP7
OPS
01
D.
~HlELlNCDQN
1
2
3
4
5
6
7
8
9
10
11
12
NC
Al
IP3
A2
IPl
A3
A4
IPO
R/WN
DTACKN
AxDB
NC
DO
13 TxDB
D.
14 OPl
15 OP3
OS
D4
07
os
16 OP5
17 OP7
18
19
20
21
22
23
24
25
26
27
28
29
30
Dl
D3
D5
D7
GND
NC
INTRN
D6
D4
D2
DO
OPS
OP4
INTRN
GNO
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
Vcc
= +5V +5%, TA = DOC to +7D'C
Vcc = +5V +10%, TA
=40°C to +85'C
40-Pin Ceramic DIP
SCN68681C1 F40
SCN68681E1F40
40-Pin Plastic DIP
SCN68681C1N40
SCN68681 E1 N40
44-Pin Plastic LCC
SCN68681CIA44
SCN68681E1A44
November 5, 1990
97
31 OP2
32 OPO
33 TxDA
34 NC
35 RxDA
36 XllCLK
37 X2
38 RESETN
39 CSN
40 IP2
41 IACKN
42 IP5
43 IP4
44 VCC
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
SCN68681
BLOCK DIAGRAM
r-8
OO-D7
"
X "v
~
BUS BUFFER
CHANNEL A
~
~
DTACKN
A1-A4
RESETN
TxDA
TRANStilT
SHIFT REGISTER
-
OPERAnoN CONTROL
RlWN
CSN
TRANStilT
HOlDING REG
4
I
ADDRESS
DECODE
I
RlWCONTROI.
I
A
--.
I
"v
RECEIVE
HOLDING REG (3)
RxDA
RECEIVE
SHIFT REGISTER
>--
MR1.2
CRA
SRA
INTERRUPT CONTROL
INTRN
IMII
IACKN
I
ISR
IVR
I
~
"
A
v
"
"v
TxDB
CHANNELB
(AS ABOVE)
RxDB
.".
II>
;!:
INPUT PORT
D
g a~~a:
nMiNG
I-
z
0
u
BAUD RATE
GENERATOR
Z
~
:i
;!;
1=
A
I
~ I-CLOCK
SELECTORS
CHANGE OF
STATE
DETECTORS (4)
"v
IPCR
ACR
6
IPO~P5
I
~ f--<
I-- ~
XlICLK
X2
I
COUNTERI
nMER
I
XTALOSC
I
I
OUTPUT PORT
>--
A
"
"
"
FUNCnON
SELECT LOGIC
8
OPO-OP7
v
I
CSRA
OPCR
OPR
I
CSRB
ACR
CTI6I
•
CTLR
•
NovemberS, 1990
98
VCC
GND
Philips Components--Signetics Data Communication Products
Product Specification
Dual asynchronous receiver/transmitter (DUART)
SCN68681
PIN DESCRIPTION
SYMBOL
TYPE
NAME AND FUNCTION
110
Data Bus: Bidirectional3-State data bus used to transfer commands, data and status between the OUART and the
CPU. 00 is the least significant bit.
CSN
I
Chip Select: Active-Low input signal. When low, data transfers between the CPU and the OUART are enabled on
00-07 as controlled by the RlWN, RON and A l-A4 inputs. When High, places the 00-07 lines in the 3-State condition.
RlWN
I
Read/Write: A High input indicates a read cycle and a low input indicates a write cycle, when a cycle is initiated by
assertion of the CSN input.
Al-A4
I
Address Inputs: Select the OUART internal registers and ports for read/write operations.
RESETN
I
Reset: A low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the IVR to hex OF, puts
OPO-OP7 in the High state, stops the coutner/timer, and puts Channel A and B in the inactive state, with the TxOA
and TxOB outputs in the mark (High) state.
OTACKN
0
Data Transfer Acknowledge: Three-state active Low output asserted in write, read, or interrupt cycles to indicate
proper transfer of data between the CPU and the OUART.
INTRN
0
. Interrupt Request: Active-low, open-drain, output which signals the CPU that one or more of the eight maskable
interrupting conditions are true.
IACKN
I
Interrupt Acknowledge: Active-low input indicating an interrupt acknowledge cycle. In response, the OUART will
place the interrupt vector on the data bus and will assert OTACKN if it has an interrupt pending.
Xl/ClK
I
Crystal 1 : Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. If a
crystal is used, a capacitor must be connected from this pin to ground (see Figure 7).
X2
I
Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this
pin to ground (see Figure 7). If an external clock is used, this pin should be grounded.
RxOA
I
Channel A Receiver Serial Data Input: The least significant bit is received first. "Mark" is High, "space" is low.
RxOB
I
Channel B Receiver Serial Data Input: The least significant bit is received first. "Mark" is High, "space" is low.
TxOA
0
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the
"mark" condition when the transmitter is disabled, idle or when operating in localloopback mode. "Mark" is High,
"space" is low.
TxOB
0
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the
'mark' condition when the transmitter is disabled, idle, or when operating in localloopback mode. 'Mark' is High,
'space' is low.
OPO
0
Output 0: General purpose output or Channel A request to send (RTSAN, active-low). Can be deactivated automaiically on receive or transmit.
OPI
0
Output 1 : General purpose output or Channel B request to send (RTSBN, active-lOW). Can be deactivated automatically on receive or transmit.
OP2
0
Output 2: General purpose output, or Channel A transmitter IX or 16X clock output, or Channel A receiver IX clock
output.
OP3
0
Output 3: General purpose output or open-drain, active-low counter/timer output or Channel B transmitter IX clock
output, or Channel B receiver 1X clock output.
OP4
Output 4: General purpose output or Channel A open-drain, active-Low, RxROYA/FFUlLA output.
OP7
0
0
0
0
IPO
I
IPI
I
Input 1 : General purpose input or Channel B clear to send active-low input (CTSBN).
IP2
I
Input2: General purpose input, or Channel B receiver extemal clock input (RxCB), or counter/timer external clock
input. When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock.
IP3
I
Input3: General purpose input or Channel A transmitter external clock input (TxCA). When the external clock is
used by the transmitter, the transmitted data is clocked on the falling edge of the clock.
IP4
I
Input4: General purpose input or Channel A receiver external clock input (RxCA). When the external clock is used
by the receiver, the received data is sampled on the rising edge of the clock.
IPS
I
Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external clock is
used by the transmitter, the transmitted data is clocked on the falling edge of the clock.
Vcc
GNO
I
Power Supply: +5V supply input.
I
Ground:
00-07
OP5
OP6
November 5, 1990
Output 5: General purpose output or Channel B open-drain, active-low, RxROYB/FFUllB output.
Output6: General purpose output or Channel A open-drain, active-low, TxROYA output.
Output 7: General purpose output, or Channel B open-drain, active-low, TxROYB output.
Input 0: General purpose input or Channel A clear to send active-low input (CTSAN).
99
Philips Components-Signetics Data Communication Products
Product Specification
Dual asynchronous receiver/transmitter (DUART)
SCN68681
ABSOLUTE MAXIMUM RATINGS1 ,
SYMBOL
PARAMETER
UNIT
RATING
TA
Operating ambient temperature range 2
See Note 4
°C
TSTG
Storage temperature range
-65 to +150
°C
All voltages with respect to ground3
-0.5 to +6.0
V
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on + 150°C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge.
Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and Vee
supply range.
DC ELECTRICAL CHARACTERISTICS1, 2, 3
LlMfTS
SYMBOL
PARAMETER
Vll
VIH
VIH
VIH
Input low voltage
Input high voltage (except X1/C~K)5
Input high voltage (except XlIClK)4
Input high voltage (X1/ClK)
VOL
VOH
VOH
Output low voltage
'
Output high voltage (except o.d. outputS)5
Output high voltage (except o.d. outputS)4
III
III
Input leakage current
Data bus 3-State leakage current
IXll
X1/ClK low input current
IX1H
X1/ClK high input current
IX2l
IX2H
X2 low input current
X2 high input current
loe
lee
Open-collector output leakage current
Power supply current
O°C to +70°C version
-40°C to +85°C version
TEST CONDITIONS
Min
Typ
Max
UNIT
0.8
V
V
V
V
0.4
V
V
V
10
10
!1A
!1A
0
0
1
10
0
100
rnA
rnA
rnA
rnA
!1A
!1A
2
2.5
4
IOl = 2.4mA
IOH = -400!1A
IOH = -400!1A
2.4
2.9
VIN = 0 to Vee
Vo = 0.4 to Vee
-10
-10
VIN = 0, X2 grounded
VIN = 0, X2 floated
VIN = Vee, X2 grounded
VIN = Vee, X2 floated
VIN = 0, X1/ClK floated
VIN = Vee, XlIClK floated
-4
-3
-1
0
-100
0
Va = 0.4 to Vee
-10
-2
-1.5
0.2
3.5
-30
+30
10
!1A
150
175
rnA
rnA
NOTES:
1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and Vee
supply range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except Xt/ClK swing between O.4V and 2.4V with a transition time of 20ns maximum. For X1lClK this swing is between O.4V and 4.4V. All time measurements are referenced at input voltages of
0.8Vand 2.0V as appropriate.
3. Typicaf values are at +25°C, typical supply voltages, and typical processing parameters.
4. TA-- f--
r--
--
INPUT PIN
A
"-
"
v
'---
I
A
"
v"-
117
I
v
I
CHANGE OF
STATE
DETECTOR
UPI
I
OUTPUT PIN
FUNcnON
SELECT LOGIC
I
ACR
I
UPO
....> - - - - - -
Vee
....>-----',---
GND
Product Specification
Philips Components-Signetics Data Communication Products
Universal asynchronous receiver/transmitter (UART)
SCC2691
PIN DESCRIPTION
MNEMONIC
TYPE
NAME AND FUNCTION
DIP
22-15
PLCC
27,25,
24,
22-18
I
Data Bus: Active-high 8-bit bidirectional3-State data bus. Bit 0 is the LSB and bit 7 is the MSB.
All data, command, and status transfers between the CPU and the UART take place over this
bus. The direction of the transfer is controlled by the WRN and RDN inputs when the CEN input
is low. When the CEN input is high, the data bus is in the 3-State condition.
CEN
14
17
I
Chip Enable: Active-low input. When low, data transfers between the CPU and the UART are
enabled on DO-D7 as controlled by the WRN, RDN and AO-A2 inputs. When CEN is high, the
UART is effectively isolated from the data bus and DO-D7 are placed in the 3-State condition.
WRN
28
28
I
Write Strobe: Active-low input. A low on this pin while CEN is low causes the contents of the
data bus to be transferred to the register selected by AO-A2. The transfer occurs on the trailing
(rising) edge of the signal.
RON
1
2
I
Read Strobe: Active-low input. A low on this pin while CEN is low causes the contents of the
register selected by AO-A2 to be placed on the data bus. The read cycle begins on the leading
(falling) edge of RDN.
AO-A2
8-6
11-9
I
Address Inputs: Active-high address inputs to select the UART registers for readlwrite operations.
RESET
11
14
I
Reset: Master reset. A high on this pin clears the status register (SR), the interrupt mask register
(IMR), and the interrupt status register(ISR), sets the mode register pointer to MR1, and places
the receiver and transmitter in the inactive state causing the TxD output to go to the marking
(high) state.
INTRN
13
16
0
Interrupt Request: This active-low output is asserted upon occurrence of one or more of seven
maskable interrupting conditions. The CPU can read the interrupt status register to determine
the interrupting condition(s). This open-drain output requires a pull-up resistor.
Xl/CLK
9
12
I
Crystal 1 : Crystal or external clock input. When using the crystal oscillator, this pin serves as
the connection for one side of the crystal. If a crystal is not used, an external clock is supplied
at this input. An external clock (or c()'stal) is required even if the internal baud rate generator is
not utilized. This clock is used to drive the internal baud rate generator, as an optional input to
the timer/counter, and to provide other clocking signals required by the chip.
X2
10
13
I
Crystal 2: Connection for other side of crystal. If an external source is used instead of a crystal,
this connection should be open.
RxD
2
3
I
Receiver Serial Data Input: The least significant bit is received first. If external receiver clock
is specified, this input is sampled on the rising edge of the clock.
TxD
3
4
0
Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held
in the marking (high) condition when the transmitter is idle or disabled and when the UART is
operating in localloopback mode. If external transmitter is specified, the data is shifted on the
falling edge of the transmitter clock.
MPO
4
5
0
Multi-Purpose Output: One of the following functions can be selected for this output pin by programming the auxiliary control register:
RTSN - Request to send active-low output. This output is asserted and negated via the command register. By appropriate programming of the mode registers, RTSN can be programmed
to be automatically reset after the character in the transmitter is completely shifted or when the
receiver FIFO and shift register are full.
ClTO - The counter/timer output.
TxCl X - The 1X clock for the transmitter.
TxC16X - The 16X clock for the transmitter.
R]!Cl X - The 1X clock for the receiver.
RxC16X - The 16X clock for the receiver.
TxRDY - The lra(\smitter holding register empty signal. Active-low output.
RxRDY/FFULL - The receiver FIFO not empty/full signal. Active-low output.
MPI
5
6
I
MultI-Purpose Input: This pin can serve as an input for one of the following functions:
GPI- General purpose input. The current state of the pin can be determined by reading the ISR.
CTSN - Clear-to-send active-low input.
CTCLK - Counter/timer external clock input.
RTCLK - Receiver andlor transmitter external clock input. This may be a IX or 16X clock as
programmed by CSR[3:0] or CSR[7:4].
Vee
24
1
I
Power Supply: +5V supply input.
GND
12
15
I
Ground
DO-D7
November 5, 1990
PIN NO.
118
Product Specification
Philips Components--Signetics Data Communication Products
Universal asynchronous receiver/transmitter (UART)
SCC2691
ABSOLUTE MAXIMUM RATINGsl
SYMBOL
RATING
PARAMETER
TA
Operating ambient temperature range 2
T STG
Storage temperature range
Vee
Voltage from Vee to GND3
Vs
Voltage from any pin to ground3
PD
Power Dissipation
UNIT
Note 4
°C
-65 to +150
°C
--{l.5 to + 7.0
V
--{l.5 to Vcc ±10%
V
300
mW
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not implied.
2. For operating at elevated temperature, the device must be derated based on + 150°C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge.
Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range. See Ordering Information table for applicable operating temperature and Vee supply
range.
.'
DC ELECTRICAL CHARACTERISTICS1, 2, 3
UMITS
SYMBOL
V IL
V IH
PARAMETER
TEST CONDITIONS
Typ
Input low voltage
Input high voltage
All except Xl/ClK
Xl/ClK
VOL
VOH'
Min
2
0.8Vee
Output low voltage
Output high voltage
(except open drain outputs)
IOL= 2.4mA
Max
UNIT
0.8
V
Vee
V
V
0.4
10H =-400~
2.4
VIN =
to Vee
Va = 0.4 to Vee
Va = 0.4 to Vee
a
-10
-10
-10
IlL
ILL
laD
Input leakage current
Data bus 3-State leakage current
Open-drain output leakage curent
IXIL
Xl/ClK low input current
VIN = 0, X2 floated
-100
~o
a
IXIH
Xl/ClK high input current
VIN = Vee, X2 floated
a
30
100
IX2L
X2 low output current
VOUT = 0, Xl/ClK = Vee
-100
IX2H
X2 high output current
VOUT = Vee, Xl/ClK = OV
leeA
Power supply current, active
O°C to +70°C
-40°C to +85°C
Power down current
Iceo
,
V
V
10
10
10
~
~
!LA
~
~
~
0.8
1.0
100
~
2.0
2.5
mA
mA
sao
~
NOTES:
1. Parameters are valid over specified temperature range. See Ordering Information table for applicable operating temperature and Vcc supply
range.
2. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between OV and 2.8V with a transition time of
20ns max. For X l/ClK, this swing is between 0.4 V and 4.0V. All time measurements are referenced at input voltages of O.BV and 2V and output
voltages of O.BV and 2V as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test condition for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7kohms to Vce.
November 5, 1990
119
Product Specification
Philips Components-$ignetics Data Communication Products
Universal asynchronous receiver/transmitter (UART)
SCC2691
AC ELECTRICAL CHARACTERISTICS 1, 2, 3, 4
UMITS
Min
PARAMETER
SYMBOL
Typ
Max
UNIT
Reset timing (Figure 1)
Reset pulse width
tRES
Bus timing (Figure 2)5
lAs
IAH
les
IeH
IRw
100
toF
tos
tOH
tRWO
AO-A2 setup time to RON, WRN low
AO-A2 hold time from RON, WRN high
CEN setup time to RON, WRN low
CEN hold time from RON, WRN high
WRN, RON· pulse width
Data valid after RON low
Data bus floating after RON high
Data setup time before WRN high
Data hold time after WRN high
TIme between reads andior writes 6 , 7
100
ns
10
0
0
0
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
125
110
50
30
150
MPI and MPO timing (Figure 3)5
MPI input setup time before RON low
tps
MI input hold time after RON low
tpH
MPO output valid after WRN high
\Po
Interrupt timing (Figure 4)
tlR
370
ns
ns
ns
370
370
370
370
370
270
ns
ns
ns
.ns
ns
ms
30
30
INTRN negated
Read RHR (RxROY/FFUll interrupt)
Write THR (TxROY, TxEMT interrupt)
Reset command (break change interrupt)
Reset command (MPI change interrupt)
Stop CIT command (counter interrupt)
Write IMR (clear of interrupt mask bit)
Clock timing (Figure 5)
IelK
fClK
IeTC
feTe
tRX
fRX
tTx
fTX
Xl/ClK high or low time
Xl/ClK frequency
Counterltimer clock high or low time
Counterltimer clock frequency
RxC high or low time
RxC frequency (16X)
RxC frequency (1 X)
TxC high or low time
TxC frequency (16X)
TxC frequency (1 X)
100
2.0
100
0"
220
0"
0"
220
0"
0"
3.6864
2.0M
1.0M
ns
MHz
ns
Hz
ns
Hz
Hz
ns
Hz
Hz
350
150
ns
ns
4.0
4.0M
2.0M
1.0M
Transmitter timing (Figure 6)
trxD
tres
TxO output delay from TxC low
TxC output delay from TxO output data
0
Receiver timing (Figure 7)
RxO data setup time to RxC high
100
ns
tRXS
RxO data hold time from RxC high
100
ns
tRXH
NOTES:
1. Parameters are valid over specified temperature range. See Ordering Information table for applicable operating temperature and Vee supply
range.
2. All voltage measurements are referenced to ground (GNO). For testing, all input signals swing between OV and 2.8V with a transition time of
20ns max. For Xl/ClK, this swing is between 0.4V and 4.0V. All time measurements are referenced at input voltages of 0.8V and 2V and output
voltages of 0.8V and 2V as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test condition for outputs: Cl = 150pF, except interrupt outputs. Test conditions for interrupt outputs: Cl = 50pF, Rl = 2.7kohms to Vee.
5. TIming is illustrated and referenced to the WRN and RON inputs. The device may also be operated with CEN as the 'strobing' input. In this case,
all timing specifications apply referenced to the falling and rising edges of CEN. CEN and RON (also CEN and WRN) are ORed internally. As
a consequence, this signal asserted last initiates the cycle and the signal negated first terminates the cycle.
S. If CEN is used as the 'strobing' input, this parameter defines the minimum high time between one CEN and the next. The RON signal must be
negated for IRwp guarantee that any status register changes are valid.
7. Consecutive wnte operations to the command register require at least three rising edges of the X 1 clock between writes.
November 5, 1990
120
Product Specification
Philips Components-Signetics Data Communication Products
Universal asynchronous receiver/transmitter (UART)
BLOCK DIAGRAM
As shown in the block diagram, the UART consists of: data bus buffer, interrupt control, operation control, timing, receiver and transmitter.
Table 1.
A2 A1
Data Bus Buffer
a
0
0
I
I
The data bus buffer provides the interface between the external and internaf data busses. It
is controlled by the operation control block to allow read and write operations to take place between the controlling CPU and UART.
1
I
1
I
I
Interrupt Control
A single interrupt output (INTRN) is provided
which may be asserted upon occurrence of any
of the following internal events:
- Transmit holding register ready
- Transmit shift register empty
- Receive holding register ready or FIFO full
- Change in break received status
0
0
0
Register Addressing
AO
0
1
0
1
I
a a
a 1
1 a
READ
(RON =0)
MRI, MR2
SR
Reserved'
RHR
Reserved'
ISR
CTU
CTl
WRITE
(WRN =0)
MRI, MR2
CSR
CR
THR
ACR
IMR
CTUR
CTlR
NOTE;
'Reserved registers should never be read
during operation since they are reserved for
internal diagnostics.
ACR = Auxiliary control register
CR = Command register
CSR = Clock select register
CTl = Counter/timer lower
CTlR = Counter/timer lower register
CTU = Counter/timer upper
CTUR = Counter/timer upper register
MR = Mode register A
SR = Status register
THR = Tx holding register
- Counter reached terminal count
- Change in MPI input
- Assertion of MPI input
Associated with the interrupt system are the interrupt mask register (IMR) and the interrupt
status register (ISR). The IMR can be programmed to select only certain of the above
conditions to cause INTRN to be asserted. The
ISR can be read by the CPU to determine all
currently active interrupting conditions. However, the bits of the ISR are not masked by the
IMR.
Operation Control
The operation control logic receives operation
commands from the CPU and generates appropriate signals to internaf sections to control
device operation. It contains address decoding
and read and write circuits to permit communications with the microprocessor via the data
bus buffer. The functions performed by the CPU
read and write operations are shown in Table 1.
Mode registers I and 2 are accessed via an
auxiliary pointer. The pointer is set to MRI by
RESET or by issuing a reset pointer command
via the command register. Any read or write of
the mode register while the pointer is at MRI
switches the pointer to MR2. the pointer then
remains at MR2 so that subsequent accesses
are to MR2, unless the pointer is reset to MR1
as described above.
November 5, 1990
Timing Circuits
The timing block consists of a crystal oscillator,
a baud rate generator, a programmable 16-bit
counter/timer, and two clock selectors.
The crystal oscillator operates directly from a
3.6864MHz crystal connected across the XI/
ClK and X2 inputs with a minimum of external
components. If an external clock of the appropriate frequency is available, it may be connected to XI/ClK. If an external clock is used
instead of a crystal, XI/ClK is driven using a
configuration similar to the one in Figure 5. In
this case, the input high-voltage must be capable of attaining the voltage specified in the DC
Electrical Characteristics. The clock serves as
the basic timing reference for the baud rate
generator (BRG), the counter/timer, and other
internaf circuits. A clock frequency, within the
limits specified in the electrical specifications,
mustbe supplied if the internal BRG isnotused.
SCC2691
The CIT operation is programmed by ACR[6:4].
One of eight timing sources can be used as the
input to the crr. The output of the crr is available to the clock selectors and can be programmed by ACR[2:0] to be output on the MPO
pin.
In the timer mode, the crr generates a square
wave whose period is twice the number of clock
periods loaded into the crr upper and lower
registers. The counterready bit in the ISR is set
once each cycleofthe square wave. If the value
in CTUR or CTlR is changed, the current halfperiod will not be affected, but subsequent halfperiods will be affected. In this mode the crr
runs continuously and does not recognize the
stop counter command (the command only resets the counter ready bit in the ISR). Receipt
of a start CIT command causes the counter to
terminate the current timing cycle and to begin
a new cycle using the values in CTUR and
CTlR.
In the counter mode, the crr counts down the
number of pulses loaded into CTUR and CTlR.
Counting begins upon receipt of a start crr
command. Upon reaching terminal count, the
counter ready bit in the ISR is set. The counter
continues counting past the terminal count until
stopped by the CPU. If MPO is programmed to
be the output of the crr, the output remains high
until terminaf count is reached, at which time it
goes low. The output returns to the high state
and the counter ready bit is cleared when the
counter is stopped by a stop counter command.
the CPU may change the values of CTUR and
CTlR at any time, but the new count becomes
effective only on the next start counter command following a stop counter command. If
new values have not been loaded, the previous
count values are preserved and used for the
next count cycle.
In the counter mode, the current value ofthe upper and lower eight bits of the counter may be
read by the CPU. It is recommended that the
counter be stopped when reading to prevent
potential problems which may occur if a carry
from the lower eight bits to the upper eight bits
occurs between the times that both halves of
the counter are read. However, a subsequent
start counter command causes the counter to
begin a new count cycle using the values in
CTUR and CTlA.
The baud rate generator operates from the oscillatoror external clock input and is capable of
generating 18 commonly used data communications baud rates ranging from 50 to 38.4K
baud. Thirteen of these are available simultaneously for use by the receiver and transmitter.
Receiver and TransmItter
Eight are fixed, and one of two sets of five can
The UART is a full-duplex asynchronous rebe selected by programmingACR[7). The clock
ceiver/transmitter. The operating frequency for
outputs from the BRG are at '16X the actual
the receiver and transmitter can be selected inbaud rate. The counter/timer can be used as a
timer to produce a 16X clock for any other baud . dependently from the baud rate generator, the
counter/timer, or from an external input. Regisrate by counting down the crystal clock or an exters associated with tlje communications chanternal clock. The clock selectors allow the indenel are: the mode registers (MRI and MR2), the
pendent selection by the receiver and er of any
of these baud rates or an external timing signal.
clock select register (CSR), the command reg-
121
Product Specification
Philips Components-Signetics Data Communication Products
Universal asynchronous receiver/transmitter (UART)
ister (CR), the status register (SR), the transmit
holding register (THR), and the receive holding
register (RHR).
Tr,ansmltter
The transmitter accepts parallel data from the
CPU and converts ilia a serial bit stream on the
TxD output pin. It automatically sends a start bit
followed by the programmed number of data
bits, an optional parity bit, and the programmed
number of stop bits. The least significant bit is
sentfirst. Following the transmission of the stop
bits, if a new character is not available in the
THR, the TxD output remains high and the
TxEMT bit in the SR will be set to 1. Transmission resumes and the TxEMT bit is cleared
when the CPU loads a new character in the
THR. In the 16X clock mode, this also resynchronizes the internal 1X transmitter clock so
that transmission of the new character begins
with minimum delay.
The transmitter can be forced to ~end a break
. (continuous low condition) by issuing a start
break command via the CA. The break is terminated by a stop break command.
If the transmitter is disabled, it continues operating until the character currently being transmitted and the character in the THR, if any, are
completely sent out. Characters cannot be
loaded in the'THR while the transmitter is disabled.
Receiver
The receiver accepts serial data on the RxD
pin, converts the serial input to parallel format,
checks for start bit, stop bit, parity bit (if any), or
break condition, and presents the assembled
character to the CPU. The receiver looks for a
high-to-Iow (mark-to-space) transition of the
start bit on the RxDinputpin.lfa transition isdetected, the state of the RxD pin is sampled
again each 16X clock for 7-1/2 clocks (16X
clock mode) or at the next rising edge of the bit
time clock (1X clock mode). If RxD is sampled
high, the start bit is invalid and the search for a
valid start bit begins again. If RxD is still low, a
valid start bit is assumed and the receiver continues to sample the input at one bit time intervals at the theoretical center of the bit, until the
proper number of data bits and the parity bit (if
any) have been assembled, and one sop bit has
been detected. The data is then ,transferred to
the RHR and the RxRDY bit in the SR is set to
a 1.lf the character length is less than eight bits,
the most significant unused bits in the RHR are
set to zero.
After the stop bit is detected, the receiver will
immediately look for the next start bit. However,
if a non-zero character Was received without a
stop bit (Le. framing error) and RxD remains low
for one-half of the bit period after the stop bit
was sampled, then the receiver operates as if
a new start bit transition had been detected at
NovemberS, 1990
that point(one-half bit time after the stop bit was
sampled). The parity error, framing error and
overrun error (if any) are strobed into the SR at
the reCeiVed character boundary, before the
RxRDY status bit is set.
I! a break condition is detected (RxD is low for
the entire character including the stop bit), only
one character consisting of all zeros will be
loaded in the FIFO and the received break bit
in the SR is set to 1. The RxD input must return
to a high condition for two successive clock
edges of the 1X clock (internal or external) before a search for the next start bit begins.
RECEIVER FIFO
The RHR consists of a first-in-first-out (FIFO)
queue with a capacity of three characters. Data
is loaded from the receive shift register into the
top-most empty position of the FIFO. The
RxRDY bit in the status register (SR) is set
whenever one ormore characters are available
to be read, and a FFULL status bit is set if all
three queue positions are filled with data. Either
of these bits can be selected to cause an interrupt: A read of the RHR outputs the data at the
top of the FIFO. After the read cycle, the data
FIFO and its associated status bits are 'popped'
thus emptying a FIFO position for new data,
In addition to the data word, three status bits
(parity error, framing error, and received break)
are appended to each data character in the
FIFO. Status can be provided in two ways, as
programmed by the error mode control bit in
mode register 1. In the character mode, status
is provided on a character-by-character basis:
the status applies only to the character at the
top of the FIFO. In the block mode, the status
provided in the SR for these three bits is the logical-OR of the status for all characters coming
to the top of the FIFO since the last reset error
command was issued. In either mode, reading
the SR does not affect the FI FO. The FIFO is
'popped'onlywhen the RHR is read. Therefore,
the SR should be read prior to reading the corresponding data character.
SCC2691
In this mode of operation, a 'master' station
transmits an address character followed by
data characters for the addressed 'slave' station. The slave stations, whose receivers are
normally disabled, examine the received data
stream and 'wake-up' the CPU [by setting
RxRDY) only upon receipt of an address character. The CPU compares the received address to its station address and enables the
receiver if it wishes to receive the subsequent
data characters. Upon receipt of another address character, the CPU may disable the receiver to initiate the process again.
A transmitted character consists of a start bit,
the programmed number of data bits, an addressldata (AID) bit, and the programmed number of stop bits. The polarity of the transmitted
AID bit is selected by the CPU by programming
bit MRl [2]. MR1 [2] = 0 transmits a zero in the
AID bit position which identifies the corresponding data bits as data, while MR1[2] = 1
transmits a one in the AID bit position which
identifies the corresponding data bits as an address. The CPU should program the mode register prior to loading the corresponding data bits
in the THR.
While in this mode, the receiver continuously
looks at the received data stream, whether it is
enabled or disabled. If disabled, it sets the
RxRDY status bit and loads thecharacterin the
RHR FIFO if the received AID bit is a one, but
discards the received character if the received
AID bit is a zero. Ifenabled, all received characters are thim transferred to the CPU via the
RHA. In either case, the data bits are loaded in
the data FIFO while the AID bit is loaded in the
status FIFO position normally used for parity error (SR[S]). Framing error, overrun error, and
break detect operate normally whether OLnot
the receiver is enabled.
.
MULTI-PURPOSE INPUT PIN
WAKE-UP MODE
The MPI pin can be programmed as an input to
one of several UART circuits. The function of
the pin is selected by programming the appropriate control register(MR2[4]), ACR[6:4], CSR
[7:4,3:0]). Only one of the functions may be selected at any given time. If CTS or GPI is selected, a change of state detector provided with
the pin is activated. A high-to-Iow orlow-to-high
transition of the inputs lasting longer than
25-50fLs sets the MPI change-of-state bit in the
interrupt status register. The bit is cleared via a
command. The change-of-state can be programmed to generate an interrupt to the CPU
by setting the corresponding bit in the interrupt
mask register.
In addition to the normal transmitter and receiver operation described ab(Jve, the UART incorporates a special mode which provides
automatic wake-up of the receiver through address frame recognition for multi-processor'
communications. This mode is selected by programming bits MR1[4:3] to'11'.
The input port pulse detection circuitry uses a
38AkHz sampling clock derived from one of the
baud rate generator taps. This produces a sampling period of slightly more than 2SI1s (assuming a 3.6864MHz oscillator input). The detection circuitry, in order to guarantee that a true
change in level has occurred, requires two
I! the FIFO is full when a new character is received, that character is held in the receive shift
register until a FIFO position is available. If an
additional character is received while this state
exists, the contents of the FIFO are not affected: the character previously in the shift register is lost and the overrun error status bit
(SR[4]) will be set upon receipt of the start bit
of the new (overrunning) character.
122
Product Specification
Philips Components-Signetics Data Communication Products
Universal asynchronous receiver/transmitter (UART)
successive samples at the new logic level be
observed. As aconsequence, the minimum duration of the signal change is 25~ if the transition occurs coincident with the first sample
pulse. The 50~ time refers to the condition
where the change of state is just missed and the
first change of state is not detected until after an
additional 25f!s.
MULT-PURPOSE OUTPUT PIN
This pin can be programmed to serve as a request-to-send output, the counter/timer output,
the output for the 1X or 16X transmitter or receiverclocks, the TxRDY output or the RxRDY/
FFULL output (see ACR[2:0] - MPO Output
Select).
REGISTERS
The operation of the UART is programmed by
writing control words in the appropriate registers. Operational feedback is provided via status registers which can be read by the CPU.
Addressing of the registers is as described in
Table 1.
The contents of certain control registers are initialized to zero on reset (see RESET pin description). Care should be exercised if the
contents of a register are changed during operation, since certain changes may cause operational problems. For example, changing the
number of bits percharacterwhile the transmitter is active may cause the transmission of an
incorrect character. Thecontentsofthe MR, the
CSR, and the ACR should only be changed
while the receiver and transmitter are disabled,
and certain changes to the ACR should only be
made while the CIT is stopped. The bit formats
of the UART are'shown in Table 2.
MR1 - Mode Register 1
MRI is accessed when the MR pointer points
to MRI. The pointer is setto MRI by RESET or
by a set pointer command applied via the CR.
After reading or writing MR1, the pointers are
set at MR2.
MR1[7] - Receiver Request-to-Send Control
The bit controls the deactivation of the RTSN
output (MPO) by the receiver. This output is
normally asserted and negated by commands
applied via the command register. MR1[7] = 1
causes RTSN to be automatically negated
upon receipt of a valid start bit if the receiver
FIFO is full. RTSN is reasserted when an empty
FIFO position is available. This feature can be
used to prevent overrun in the receiver by using
the RTSN output signal to control the CTS input
of the transmitting device.
MR1[6) - Receiver Interrupt Select
This bit selects either the receiver ready status
(RxRDY) or the FIFO full status (FFULL) to be
used for CPU interrupts.
November 5, 1990
MR1 [5]- Error Mode Select
This bit selects the operating mode of the three
FIFOed status bits (FE, PE, received break). In
the character mode, status is provided on a
character-by-character basis. The status applies only to the character at the top of the FI FO.
Inthe block mode, the status provided in the SR
for these bits is the accumulation (logicaJ-OR)
of the status for all characters coming to the top
of the FIFO since the last reset error command
was issued.
MR1[4:3]- Parity Mode Select
If with parity or force parity is selected, a parity
bit is added to the transmitted character and the
receiver performs a parity check on incoming
data. MR![4:3] = 11 selects the channel tooperate in the special wake-up mode.
MR1[2) - Parity Type Select
This bit selects the parity type (odd or even) if
the with parity mode is programmed by
MRI [4:3), and the polarity of the forced parity
bit if the force parity mode is programmed. It
has no effect if the no parity mode is programmed. In the special wake-up mode, it selects the polarity of the transmitted AID bit.
MR1[1:0) - Bits Per Character Select
This field selects the number of data bits per
character to be transmitted and received. The
character length does not include the start, parity, and steip bits.
MR2 - Mode Register 2
MR2 is accessed when the channel MR pointer
points to MR2, which occurs after any access
to MRI. Accesses to MR2 do not change the
pointer.
MR2[7:6]- Mode Select
The UART can operate in one of four modes.
MR2[7:6) = 00 is the normal mode, with the
transmitter and receiver operating independently. MR2[7:6) = 01 places the channel in the
automatic echo mode, which automatically retransmits the received data. The following conditions are true while in automatic echo mode:
1. Received data is reclocked and retransmitted on the TxD output.
2. The receive clock is used for the transmitter.
3. The receiver must be enabled, but the
transmitter need not be enabled.
4. The TxRDY and TxEMT status bits are inactive.
5. The received parity is checked, but is not regenerated for transmission, i.e., transmitted
parity bit is as received.
6. Character framing is checked, but the stop
bits are retransmitted as received.
7. A received break is echoed as received until
the next valid start bit is detected.
123
SCC2691
8. CPU-to-receiver communication continues
normally, but the CPU-to-transmitter link is
disabled.
Two diagnostic modes can also be selected.
MR2[7:6) = 10 selects local loopback mode. In
this mode:
1. The transmitter output is internally connected to the receiver input.
2. The transmit clock is used for the receiver.
3. The TxD output is held high.
4. The RxD input is ignored.
5. The transmitter must be enabled, but the receiver need not be enabled.
6. CPU to transmitter and receiver communications continue normally.
The second diagnostic mode is the remote
loopback mode, selected by MR2[7:6) = 11. In
this mode:
1. Received data is reclocked and retransmitted on the TxD output.
2. The receive clock is used for the transmitter.
3. Received data is not sent to the local CPU,
and the error status conditions are inactive.
4. The received parity is not checked and is
not regenerated for transmission, i.e., the
transmitted parity bit is as received.
5. The receiver must be enabled, but the
transmitter need not be enabled.
6. Character framing is not chllcked, and the
stop bits are retransmitted as received.
7. A received break is echoed as received until
the next valid start bit is detected.
When switching in and out of the various
modes, the selected mode is activated immediately upon mode selection, even if this occurs
in the middle of a received or transmitted character. Likewise,'if a mode is deselected, the device will switch out of the mode immediately. An
exception to this is switching out of auto-echo
or remote loopback modes; if the deselection
occurs just after the receiver has sampled the
stop bit (indicated in auto-echo by assertion 0
fRxRDY), and the transmitter is enabled, the
transmitter is enabled, the transmitter will remain in auto-echo mode until one full stop bit
has been retransmitted.
MR2[5) - Transmitter Request-to-Send
Control
This bit controls the deactivation of the RTSN
output (MPO) by the transmitter. This output is
normally'asserted and negated by appropriate
commands issued via the command register.
MR2[5] = 1 causes RTSN to be reset automatically one bit time after the characters in the
transmit shift register and in the THR (ifany)are
completely transmitted (including the programmed number of stop bits) if the transmitter
is not enabled. This feature can be used to automatically terminate the transmission as follows:
Product Specification
Philips Components-Signetics Data Communication Products
Universal asynchronous receiver/transmitter (UART)
1. Program auto-reset mode: MR2[51 = 1.
2. Enable transmitter.
3. Assert RTSN via command.
Table 2.
4. Send message.
5. Disable transmitter after the last character
of the message is loaded in the THR.
SCC2691
6. The last character will be transmitted and
RTSN will be reset one bit time after the last
stop bit.
Register Bit Formats
Bit 7
Blt6
Blt5
Blt4
Bit3
Bit 0
Bit 1
Bit2
MR1 (Mode Register 1)
RxRT Control
RxlNT Select
Error Mode
0= no
1 = yes
0= RxRDY
1 = FFULL
0= Char
1 = Block
Parity Mode
00 = With parity
01 = Force parity
10 = No parity
11= Special mode
Parity Type
Bits per C--
RDN
CHANNEL A
r-A
4/
I
I
RIWCONTROL
I r--I
TxDA
TRANSIilT
SHIFT REGISTER
"
r--
"
RECEIVE
HOLDING REG (3)
v
RxDA
RECEIVE
SHIFT REGISTER
L
MRA1,2
J
CRA
SRA
INTERRUPT CONTROL
INTRN
I
IMII
ISR
~
[v--r-v'
A
~
I
.."
hOB
CHANNELB
(AS ABOVE)
"
RxDB
EO
~
INPUT PORT
c
5a:
....z
TIMING
0
BAUD RATE
GENERATOR
CLOCK
SELECTORS
I
X,ICLK
X2
I
XTALOSC
I
~ffi'L-i
"
1=
-
>--
-
COUNTER!
TIMER
~
A
I "
~
-
"
CHANGE OF
STATE
DETECTORS (4)
v
I
IPCR
ACR
7/
I
cf-;o
OUTPUT PORT
-
"
"
VL--
v
FUNCTION
SELECT LOGIC
I
CSRA
CSRB
ACR
CTLI!
CTLR
OPCR
OPR
8
.
134
OPO-OP7
I
..
November 5,1990
IPO~P6
VCC
GND
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
SCC2692
PIN DESCRIPTION
SYMBOL
APPLICABLE
TYPE
NAME AND FUNCTION
X
1/0
Data Bus: Bidirectional3-State data bus used to transfer commands, data and status between the
DUART and the CPU. DO is the least significant bit.
X
X
I
Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the
DUART are enabled on DO-D7 as controlled by the WRN, RDN and AO-A3 inputs. When High,
places the DO-D7 lines in the 3-State condition.
WRN
X
X
I
Write Strobe: When Low and CEN is also Low, the contents of the data bus are loaded into the
addressed register. The transfer occurs on the rising edge of the signal.
RDN
X
X
I
Read Strobe: When Low and CEN is also Low, causes the contents of the addressed register to
be presented on the data bus. The read cycle begins on the falling edge of RDN.
AO-A3
X
X
I
Address Inputs: Select the DUART internal registers and ports for readlwrite operations.
RESET
X
X
I
Reset: A High level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OPO-OP7
in the High state, stops the counter/timer, and puts Channels A and B in the inactive state, with the
TxDA and TxDB outputs in the mark (High) state.
INTRN
X
X
0
Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the
eight maskable interrupting conditions are true.
Xl/CLK
X
X
I
Crystal': Crystal or external clock input. A crystal or clock of the specified limits must be
supplied af all times. When a crystal is used, a capacitor must be connected from this pin to
ground (sea Figure 5).
X2
X
X
I
Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be
connected from this pin to ground (see Figure 5). It Xl/CLK is driven from an external source, this
pin can be left open or connected to ground.
RxDA
X
X
I
Channel A Receiver Serial Data Input: The least significant bit is received first. "Mark" is High,
"space" is Low.
RxDB
X
X
I
Channel B Receiver Serial Data Input: The least significant bit is received first. "Mark" is High,
"space" is Low.
TxDA
X
X
0
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This
output is held in the "mark" condition when the transmitter is disabled, idle or when operating in
localloopback mode. "Mark" is High, "space" is Low.
TxDB
X
X
0
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This
output is held in the 'mark' condition when the transmitter is disabled, idle, or when operating in
localloopback mode. 'Mark' is High, 'space' is Low,
OPO
X
X
0
Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be
deactivated automatically on receive or transmit.
OPI
X
X
0
Output,: General purpose output or Channel B request to send (RTSBN, active-Low). Can be
deactivated automatically on receive or transmit.
OP2
X
0
Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A
receiver 1X clock output.
OP3
X
0
Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B
transmitter IX clock output, or Channel B receiver IX clock output.
OP4
X
0
Output 4: General purpose output or Channel A open-drain, active-Low, RxRDYAN/FFULLAN
output.
OP5
X
0
Output 5: General purpose output or Channel B open-drain, active-Low, RxRDYBN/FFULLBN
output.
Output 6: General purpose output or Channel A open-drain, active-Low, TxRDYAN output.
40,44
28
DO-D7
X
CEN
OP6
X
OP7
X
0
0
IPO
X
I
Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN).
IPI
X
I'
Input,: General purpose input or Channel B clear to send active-Low input (CTSBN).
IP2
X
IP3
X
November 5, 1990
X
Output 7: General purpose output, or Channel B open-drain, active-Low, TxRDYBN output.
I
Input 2: General purpose input or counter/timer external clock input.
I
Input3: General purpose input or Channel A transmitter external clock input (TxCA). When the
external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the
clock.
135
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
SCC2692
PIN DESCRIPTION (Continued)
SYMBOL
APPUCABLE
40,44
TYPE
NAME AND FUNCTION
28
IP4
X
I
Input4: General purpose input or Channel A receiver external clock input (RxCA). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock.
IPS
X
I
Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the
external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the
clock.
IP6
X
I
Input 6: General purpose input or Channel B receiver external clock input (RxCB). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock.
Vcc
GND
X
X
X
X
I
Power Supply: +5V supply input.
I
Ground
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
RATING
UNIT
Note 4
°C
Storage temperature range
-65 to +150
°C
Vcc
Voltage from Vcc to GND3
-0.5 to +7.0
V
Vs
Voltage from any pin to GND3
-0.5 to IIcc +0.5
V
TA
Operating ambient temperature range 2
TSTG
Power dissipation
Po
750
mW
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device." This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied.
.
2. For operating at elevated temperatures, the device must be derated b,!sed on + 150°C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection.of its internal devices from damaging effects of excessive static charge.
Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
.
4. Parameters are valid over specified temperature range.
November 5, 1990
136
Product Specification
Philips Components-Signetics Data Communication Products
SCC2692
Dual asynchronous receiver/transmitter (DUART)
DC ELECTRICAL CHARACTERISTICS1, 2, 3
LIMITS
SY"!BOL
TEST CONDITIONS
PARAMETER
Min
VIL
VIH
VIH
VIH
Input low voltage
Input high voltage (except Xl/ClK)6
Input high voltage (except Xl/ClK)7
Input high voltage (Xl/ClK)
VOL
VOH
Output low voltage
Output high voltage (except 00 outputS)4
IOH = -400fJA
Vee-O· 5
IIX1PO
IILXl
IIHXl
Xl/ClK input current - power down
Xl/ClK input low current - operating
Xl/ClK input high current - operating
VIN = 0 to Vee
V IN = 0
VIN = Vee
IOHx2
IOHx2s
IOLx2
IOLx2s
X2 output high current - operating
X2 output high short circuit current - operating
X2 output low current - operating
X2 output low short circuit current - operating and
power down
II
Typ
2.0
2.5
0.8 Vee
Max
0.8
UNIT
V
V
V
V
0.4
V
V
-10
-75
0
+10
0
75
fJA
fJA
fJA
VOUT = Vee, Xl = 0
Vour= 0, Xl = 0
VOUT = 0, Xl = Vee
VOUT = Vee, Xl = Vee
0
-10
-75
1
+75
-1
0
10
fJA
rnA
VIN = 0 to Vee
VIN = 0 to Vee
-10
-20
+10
+10
fJA
fJA
10
-10
fJA
fJA
IOL = 2.4mA
Input leakage current:
All except input port pins
Input port pins
loZH
IOZL
Output off current high, 3-state data bus
Output off current low, 3-state data bus
VIN = Vee
VIN =OV
looL
IOOH
Open-drain output low current in off-state
Open-drain output high current in off-state
V IN = 0
VIN = Vee
Power supply current 5
Operating mode
-10
TTL input levels
CMOS input levels
TTL input levels
CMOS input levels
Icc
Power down mode
fJA
rnA
10
fJA
fJA
10
10
3.0
2.0
rnA
rnA
rnA
rnA
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between O.4V and 2.4V with a transition time of 5ns
maximum. For Xl/ClK this swing is between O.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of O.BV and 2.0V, as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7KQ to Vee.
5. All outputs are disconnected. Inputs are switching between TTL levels of 2.4V and 0.4V or CMOS levels of Vee -0.2V and Vss + 0.2V.
6. TA"O°C
7. TA 70°C.
November5,1990
138
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
BLOCK DIAGRAM
The SCC2692 DUART consists of the following
eight major sections: data bus buffer, operation
control, interrupt control, timing, communications Channels A and B, input port and output
port. Refer to the Block Diagram.
Data Bus Buffer
The data bus buffer provides the interface between the external and internal data buses. It
is controlled by the operation control block to allow read and write operations to take place between the controlling CPU and the DUART.
Operation Control
The operation control logic receives operation
commands from the CPU and generates appropriate signals to internal sections to control
device operation. It contains address decoding
ard read and write circuits to permit communications with the microprocessor via the data
bus buffer.
Interrupt Control
A single active-low interrupt output (INTRN) is
provided which is activated upon the occurrence of any of eight internal events. Associated with the interrupt system are the
Interrupt Mask Register (IMR) and the Interrupt
Status Register (ISR). The IMR can be programmed to select only certain conditions to
cause INTRN to be asserted. The ISR can be
read by the CPU to determine all currently active interrupting conditions.
Outputs OP3-0P7 can be programmed to provide discrete interrupt outputs for the transmitter, receivers, and counter/timer.
Timing Circuits
The timing block consists of a crystal oscillator,
a baud rate generator, a programmable 16-bit
counter/timer, and four clock selectors. The
crystal oscillatoroperates directly from a crystal
connected across the XI/ClK and X2 inputs.
If an external clock of the appropriate frequency
is available, it may be connected to XI/ClK.
The clock serves as the basic timing reference
for the Baud Rate Generator (BRG), the counter/timer, and other internal circuits. A clock
signal within the limits specified in the specifications section of this data sheet must always be
supplied to the DUART.
If an external clock is used instead of a crystal,
XI should be driven using a configuration similar to the one in Figure 5.
The baud rate generator operates from the oscillator or external clock input and is capable of
generating 18 commonly used data communications baud rates ranging from 50 to 38.4K
baud. A 3.6864MHz crystal or external clock
mustbeusedtogetthe standard baud rate. The
clock outputs from the BRG are at 16X the actual baud rate. The counter/timer can be used
November 5, 1990
SCC2692
as a timer to produce a 16X clock for any other
baud rate by counting down the crystal clock or
an external clock. The four clock selectors allow the independent selection, for each receiver and transmitter, of any of these baud rates or
external timing signal.
transition occurs "coincident with the first sample pulse". The 50f!s time refers to the situation
in which the change-of-state is "just missed"
and the first change-of-state is not detected until 25f!s later.
The Countermmer (C/T) can be programmed
to use one of several timing sources as its input.
The output of the CIT is available to the the
clock selectors and can also be programmed to
be output at OP3. In the counter mode, the contents of the CIT can be read by the CPU and
it can be stopped and started under program
control. In the timer mode, the CIT acts as a
programmable divider.
The 8-bitmultipurpose output port can be used
as a general purpose output port, in which case
the outputs are the complements of the Output
Port Register (OPR). OPR(n) = 1 results in
OP(n) = low and vice versa. Bits of the OPR
can be individually set and reset. A bit is set by
performing a write operation at address irE'
with the accompanying data specifying the bits
to be reset (I = set, 0 = no change). Likewise,
a bit is reset by a write at address H'F' with the
accompanying data specifying the bits to be reset (1 = reset, 0 = no change).
Communications
Channels A and B
Each communications channel of the
SCC2692 comprises a full-duplex asynchronous receiver/transmitter (UART). The operating frequency for each receiver and transmitter
can be selected independently from the baud
rate generator, the counter/timer, or from an external input.
The transmitter accepts parallel data from the
CPU, converts it to a serial bit stream, inserts
the appropriate start, stop, and optional parity
bits and outputs a composite serial stream of
data on the TxD output pin. The receiver accepts serial data on the RxD pin, converts this
serial input to parallel format, checks for start
bit, stop bit, parity bit (if any), or break condition
and sends an assembled characterto the CPU.
Input Port
The inputs to this unlatched 7-bit port can be
read by the CPU by performing a read operation at address H'D'. A High input results in a
logic 1 while a low input results in a logic O. D7
will always read as a logic 1. The pins of this
port can also serve as auxiliary inputs to certain portions fo the DUART logic.
Four change-of-state detectors are provided
which are associated with inputs IP3, IP2, IPI
and I PO. A High-to-low or low-to-High transition of these inputs, lasting longer than 25 50f!s, will set the corresponding bit in the input
port change register. The bits are cleared
when the register is read by the CPU. Any
change-of-state can also be programmed to
generate an interrupt to the CPU.
The input port pulse detection circuitry uses a
38.4KHz sampling clock derived from one of
the baud rate generator taps. This results in a
sampling period of slightly more than 25f!s (this
assumes that the clock input is 3.6864MHz).
The detection circuitry, in order to guarantee
that a true change in level has occurred, requires two successive samples at the new logic
level be observed. As a consequence, the minimum duration of the signal change is 25f!s if the
139
Output Port
Outputs can be also individually assigned specific functions by appropriate programming of
the Channel A mode registers (MR1A, MR2A),
the Channel B mode registers (MRIB, MR2B),
and the Output Port Configuration Register
(OPCR).
OPERATION
Transmitter
The SCC2692 is conditioned to transmit data
when the transmitter is enabled through the
command register. The SCC2692 indicates to
the CPU that ilis ready to accept a character by
setting the TxRDY bit in the status register.
This condition can be programmed to generate
an interruptrequestatOP60rOP7and INTRN.
When a character is loaded into the Transmit
Holding Register (THR), the above conditions
are negated. Data is transferred from the holding register to transmit shift register when it is
idle or has completed transmission of the previous character. The TxRDY conditions are
then asserted again which means one full character time of buffering is provided. Characters
cannot be loaded into the THR while the transmitter is disabled.
The transmitter converts the parallel data from
the CPU toa serial bit stream on the TxD output
pin. It automatically sends a start bit followed
by the programmed number of data bits, an op,
tional parity bit, and the programmed number of
stop bits. The least significant bit is sent first.
Following the transmission of the stop bits, if a
new character is not available in the THR, the
TxD output remains High and the TxEMT bit in
the Status Register (SR) will be set to I. Transmission resumes and the TxEMT bit is cleared
when the CPU loads a new character into the
THR.
If the transmitter is disabled, it continues operating until the character currently being trans-
Product Specification
Philips Components-Signetics Data Communication Products
SCC2692
Dual asynchronous receiver/transmitter (DUART)
mitted is completely sent out. The transmitter
can be forced to send a continuous Low condition by issuing a send break command.
INTRN. I! the character length is less than 8
bits, the most significant unused bits in the RHR
are set to zero.
The transmitter can be reset through a software
command. If it is reset, operation ceases immediately and the transmitter must be enabled
through the command register before resuming
operation. If CTS operation is enable, the
CTSN input must be Low in order for the
character to be transmitted. If it goes High in
the middle of a transmission, the character in
the shift register is transmitted and TxDA then
remains in the marking state until CTSN goes
Low. The transmitter can also control the deactivation of the RTSN output. If programmed,
the RTSN output will be reset one bit time after
the character in the transmit shift register and
transmit holding register (if any) are completely
transmitted, if the transmitter has been disabled.
After the stop bit is detected, the receiver will
immediately look for the next start bit. However, if a non-zero character was received without
a stop bit (framing error) and RxD remains Low
for one half of the bit period after the stop bit
was sampled, then the receiver operates as if
a new start bit transition had been detected at
that point (one-hal! bittime after the stop bit was
sampled).
Receiver
The SCC2692 is conditioned to receive data
when enabled through the command register.
The receiver looks for a High-to-Low
(mark-to-space) transition of the start bit on the
RxD input pin. If a transition is detected, the
state of the RxD pin is sampled each 16X clock
for 7-1/2 clocks (16Xclock mode) or at the next
rising edge of the bit time clock (IX clock
mode). I! RxD is sampled High, the start bit is
invalid and the search for a valid start bit begins
again. I! RxD is still Low, a valid start bit is assumed and the receiver continues to sample
the input at one bit time intervals at the theoreticaf center of the bit, until the proper number of
data bits and parity bit (if any) have been assembled, and one stop bit has been detected.
The least significant bit is received first. The
data is then transferred to the Receive Holding
Register (RHR) and the RxRDY bit in the SR is
set to a 1. This condition can be programmed
to generate an interrupt at OP4 or OP5 and
Table 1.
A2
AI
AO
0
0
0
0
0
0
0
0
0
·1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
1
1
1
1
1
The RHRconsists of a First-In-First-Out (FIFO)
stack with a capacity of three characters. Data
is loaded from the receive shift register into the
topmost empty position of the FIFO. The
RxRDY bit in the status register is set whenever
one or more characters are available to be
read, and a FFULL status bit is set if all three
stack positions are filled with data. Either of
these bits can be selected to cause an interrupt.
A read of the RHR outputs the data at the top
of the FIFO. After the read cycle, the data FIFO
and its associated status bits (see below) are
'popped' thus emptying a FIFO position for new
data.
In addition to the data word, three status bits
(parity error, framing error, and received break)
are also appended to each data character in the
If the FIFO is full when a new character is received, that character is held in the receive shift
register until a FIFO position is available. If an
additional character is received while this state
exits, the contents of the FIFO are not affected;
the character previously in the shift register is
lost and the overrun error status bit (SR[4] will
be set-upon receipt of the start bit of the new
(overrunning) character.
The receiver can control the deactivation of
RTS. If programmed to operate in this mode,
the RTSN output will be negated when a valid
start bit was received and the FIFO is full.
When a FIFO position becomes available, the
RTSN output will be ra-asserted automatically.
This feature can be used to prevent an overrun,
in the receiver, by connecting the RTSN output
to the CTSN input of the transmitting device.
If the receiver is disabled, the FIFO characters
can be read. However, no additional characters
can be received until the receiver is enabled
again. If the receiver is reset, the FIFO and all
of the receiver status, and the corresponding
output ports and interrupt are reset. No additional characters can be received until the receiver is enabled again.
SCC2692 Register Addressing
A3
0
The parity error, framing error, and overrun error (if any) are strobed into the SR at the received character boundary, before the RxRDY
status bit is set. I! a break condition is detected
(RxD is Low for the entire character including
the stop bit), a character consisting of all zeros
will be loaded into the RHR and the received
break bit in the SR is set to 1. The RxD input
must return to a High condition for at least
one-hal! bit time before a search for the next
start bit begins.
FIFO (overrun is not). Status can be provided
in two ways, as programmed by the error mode
control bit in the mode register. In the 'character' mode, status is provided on a character-by-character basis; the status applies only
to the character at the top of the FIFO. In the
'block' mode, the status provided in the SR for
these three bits is the logical-OR of the status
for all characters coming to the top of the FIFO
since the last 'reset error' command was issued. In either mode reading the SR does not
affect the FIFO. The FIFO is 'popped'. only
when the RHR is read. Therefore the status register should be read prior to reading the FIFO.
November 5, 1990
0
1
0
1
READ (RDN
=0)
Mode Register A (MR1A, MR2A)
Status Register A (SRA)
Reserved
Rx Holding Register A (RHRA)
Input Port Change Register (IPCR)
Interrupt Status Register (ISR)
Countermmer Upper (CTU)
Countermmer lower (CTL)
Mode Register B (MRI B, MR2B)
Status Register B (SRB)
Reserved
Rx Holding Register B (RHRB)
Reserved·
Input Port (IPR)
Start Counter Command
Stop CouJlter Command
140
WRITE (WRN
= 0)
Mode Register A (MR1A, MR2A)
Clock Select Register A (CSRA)
Command Register A (CRA)
Tx Holding Register A (THRA)
Aux. Control Register (ACR)
Interrupt Mask Register (IMR)
CIT Upper Register (CRUR)
CIT lower Register (CTlR)
Mode Register B (MRI B, MR2B)
Clock Select Register B (CSRB)
Command Register B (CRB)
Tx Holding Register B (THRB)
Reserved
Output Port Conf. Register (OPCR)
Set Output.Port Bits Command
Reset Output Port Bits Command
Philips Components--$ignetics Data Communication Products
Product Specification
Dual asynchronous receiver/transmitter (DUART)
Timeout Mode
The timeout mode uses the received data
stream to control the counter. Each time a received character is transferred from the shift
register to the RH R, the counter is restarted.
If a new character is not received before the
counter reaches zero count, the counter ready
bit is set, and an interrupt can be generated.
This mode can be used to indicate when data
has been left in the Rx FIFO for more than the
programmed time limit. Otherwise, if the receiver has been programmed to interrupt the
CPU when the receive FIFO is full, and the
message ends before the FIFO is full, the CPU
may not know there is data left in the FIFO. The
CTU and CTl value would be programmed for
just over one character time, so that the CPU
would be interrupted as soon as it has stopped
receiving continuous data. This mode can also
be used to indicate when the serial line has
been marking for longer than the programmed
time limit. In this case, the CPU has read all of
the characters from the FIFO, but the last charac;ter received has started the count. If there is
no new data during the programmed time interval, the counter ready bit will get set, and an interrupt can be generated.
This mode is enabled by writing the appropriate
'command to the command register. Writing an
'Ax' to CRA or CRB will invoke the timeout
mode for that channel. Writing a 'Cx' to CRA or
CRB will disable the timeout mode. The timeout mode should only be used by one channel
at once, since it uses the CfT. CTU and CTl
muSt be loaded with a value greater than the
normal receive character period. The timeout
mode disables the regular START/STOP
Counter commands and puts the CfT into
counter mode under the control of the received
data stream. Each time a received character is
transferred from the shift register to the RHR,
the CfT is stopped after I CIT clock, reloaded
with the value in CTU and CTl and then restarted on the next CfT clock. If the CfT is allowed to end the count before a new character
has been received, the counter ready bit,
ISR[3], will be set. If I MR[3] is set, this will generate an interrupt. Since receiving a character
after the CfT has timed out will clear the counter
ready bit, ISR[3], and the interrupt. Invoking the
'Set Timeout Mode On' command, CRx = 'Ax',
will also clear the counter ready bit and stop the
counter until the next character is received.
Multidrop Mode
The DUART is equipped with a wake up mode
for multidrop applications. This mode is selected by programming bits MRIA[4:3] or
MRI B[4:3]to'II'forChannels Aand B, respectively. In this mode of operation, a 'master' station transmits an address character followed by
data characters for the addressed 'slave' station. The slave stations, with receivers that are
normally disabled, examine the received data
November 5, 1990
SCC2692
stream and 'wakeup' the CPU (by setting
RxRDY) only upon receipt of an address character. The CPU compares the received address to its station address and enables the
receiver if it wishes to receive the subsequent
data characters. Upon receipt of another address character, the CPU may disable the receiver to initiate the process again.
pointer is set to MRI X by RESET or by issuing
a 'reset pointer' command via the corresponding command register. Any read or write of the
mode register while the pointer is at MRIX,
switches the pointer to MR2X. The pointer then
remains at MR2X, sO that subsequent accesses are always to MR2X unless the pointer
.
is reset to MR I X as described above.
A transmitted character consists of a start bit,
the programmed number of data bits, and AddresslData (AID) bit, and the programmed
number of stop bits. The polarity of the
transmitted AID bit is selected by the CPU by
programming
bit
MRIA[2]/MRI B[2].
MR I A[2]/MR I B[2] = 0 transmits a zero in the
AID bit position, which identifies the corresponding data bits as data
while
MR I A[2]/MR I B[2] = I transmits a one in the
AID bit position, which identifies the corresponding data bits as an address. The CPU
should program the mode register prior to loading the corresponding data bits into the THR.
Mode, command, clock select, and status registers are duplicated for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions.
The reserved registers at addresses H'02' and
H'OA' should never be read during normal operation since they are reserved for internal
diagnostics.
In this mode, the receiver continuously looks at
the received data stream, whether it is enabled
or disabled. If disabled, it sets the RxRDY status bit and loads the character into the RHR
FIFO if the received.AlD bit is one (address
tag), but discards the received character if the
received AID bit is a zero (data tag). If enabled,
all received characters are transferred to the
CPU via the RHR. In either case, the data bits
are loaded into the data FI FO while the AID bit
is loaded into the status FIFO position normally
used for parity error (SRA[5] or SRB[5]). Framing error, overrun error, and break detect operate normally whether or not the receive is
enabled.
a
PROGRAMMING
The operation of the DUART is programmed by
writing control words into the appropriate registers. Operational feedback is provided via status registers which can be read by the CPU.
The addressing of the registers is described in
Table 1.
The contents of certain control registers are initialized to zero on RESET. Care should be exercised if the contents of a register are changed
during operation, since certain changes may
cause operational problems.
For example, changing the number of bits per
character while the transmitter is active may
cause the transmission of an incorrect character. In general, the contents of the MR, the
CSR, and the OPCR should only be changed
while the receiver{s) and transmitter{s) are not
enabled, and certain changes to the ACR
should only be made while the CfT is stopped.
Mode registers I and 2 of each channel are accessed via independent auxiliary pointers. The
141
MR1 A - Channel A Mode
Register 1
MR I A is accessed when the Channel A MR
pointer points to MRI. The pointer is setto MRI
by RESET or by a 'set pointer' command
applied via CRA. After reading or writing
MR I A, the pointer will point to MR2A.
MRIA[7] - Channel A Receiver
Request-to-Send Control
This bit controls the deactivation of the RTSAN
output{OPO) by the receiver. This output is normally asserted by setting OPR[O] and negated
by resetting OPR[O]. MRIA[7] = I causes
RTSAN to be negated upon receipt of a valid
start bit if the Channel A FIFO is full. However;
OP R[O] is not reset and RTSAN will be asserted
again when an empty FI FO position is available. This feature can be used for flow control
to prevent overrun in the receiver by using the
RTSAN output signal to control the CTSN input
of the transmitting device.
MR1A[6]- Channel A Receiver
Interrupt Select
This bit selects either the Channel A receiver
ready status (RxRDY) or the Channel A FIFO
full status (FFUll) to be used for CPU interrupts. It also causes the selected bit to be output on OP4 if it is programmed as an interrupt
output via the OPCR.
MR1A[5]- Channel A
Error Mode Select
This bit selects the operating mode of the three
FIFOed status bits (FE, PE, received break) for
Channel A. In the 'character' mode, status is
provided on a character-by-character basis:
the status applies only to the character at the
top of the FIFO. In the 'block' mode, the status
provided in the SR for these bits is the accumulation (logical-OR) of the status for all characters coming to the top of the FIFO since the last
'reset error' command for Channel A was issued.
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
MR1A[4:31- Channel A Parity Mode Select
If 'with parity' or 'force parity' is selected a parity
bit is added to the transmitted character and the
receiver performs a parity check on incoming
dataMR1A[4:3]= 11 selects ChannelAtooperate in the special multidrop mode described in
the Operation section.
MR1A[2]- Channel A Parlly Type Select
This bit selects the parity type (odd or even) if
the 'with parity' mode is programmed by
MR1A[4:3], and the polarity olthe forced parity
bit if the 'force parity' mode is programmed. It
has no effect if the 'no parity' mode is programmed. In the special multidrop mode it selects the polarity of the AID bit.
MR1A[I:0]-Channel A Bits Per Character
Select
This field selects the number of data bits per
character to be transmitted and received. The
character length does not include the start, parity, and stop bits.
MR2A - Channel A Mode
Register 2
MR2A is accessed when the Channel A MR
pointer points to MR2, which occurs after any
access to MRI A. Accesses to MR2A do not
change the pointer.
MR2A[7:6]- Channel A Mode
Select
Each channel of the DUART can operate in one
of four modes. MR2A[7:6] = 00 is the normal
mode, with the transmitter and receiver operating independently. MR2A[7:6] = Ql places the
channel in the automatic echo mode, which automatically retransmits the received data. The
following conditions are true while in automatic
echo mode:
1. Received data is reclocked and retransmitted on the TxDA output.
2. The receive clock is used for the transmitter.
3. The receiver must be enabled, but the
transmitter need not be enabled.
4. The Channel A TxRDY and TxEMT status
bits are inactive.
5. The received parity is checked, but is not
regenerated for transmission, i.e. transmitted parity bit is as received.
6. Character framing is checked, but the
stop bits are retransmitted as received.
7. A received break is echoed as received
until the next valid start bit is detected.
November 5, 1990
8. CPU to receiver communication continues
normally, but the CPU to transmitter link is
disabled.
Two diagnostic modes can also be configured.
MR2A[7:6] = 10 selects local loopback mode.
In this mode:
1. The transmitter output is internally connected to the receiver input.
2. The transmit clock is used for the receiver.
3. The TxDA output is held High.
4. The RxDA input is ignored.
5. The transmitter must be enabled, but the
receiver need not be enabled.
6. CPU to transmitter and receiver communications continue normally.
The second diagnostic mode is the remote
loopback mode, selected by MR2A[7:6] = 11.
In this mode:
1. Received data is reclocked and retransmitted on the TxDA output.
2. The receive clock is used for the transmitter.
3. Received data is not sent to the local
CPU, and the error status conditions are
inactive.
4. The received parity is not checked and is
not regenerated for transmission, i.e.,
transmitted parity is as received.
5. The receiver must be enabled.
6. Character framing is not checked, and the
stop bits are retransmitted as received.
7. A received break is echoed as received
until the next valid start bit is detected.
The user must exercise care when switching
into and out of the various modes. The selected mode will be activated immediately upon
mode selection, even ilthis occurs in the middle
of a received or transmitted character. Ukewise, if a mode is deselected the device will
switch out of the mode immediately. An exception to this is switching out of autoecho or remote loopback modes: if the de-selection
occurs just after the receiver has sampled the
stop bit (indicated in autoecho by assertion of
RxRDY), and the transmitter is enabled, the
transmitter will remain in autoecho mode until
the entire stop has been re-transmitted.
142
SCC2692
M R2A[S] - Channel A Transmitter
Request-to-Send Control
This bit controls the deactivation of the RTSAN
output (OPO) by the transmitter. This output is
normally asserted by setting OPR[O] and negated by resetting OPR[O]. MR2A[5] = 1
causes OPR[O] to be reset automatically one bit
time after the characters in the Channel A transmit shift register and in the THR, if any, are completely transmitted including the programmed
number of stop bits, if the transmitter is not enabled. This feature can be used to automatically terminate the transmission of a message as
follows:
1. Program auto-reset mode: MR2A[S] = 1.
2. Enable transmitter.
3. Assert RTSAN: OPR[O] = 1.
4. Send message.
5. Disable transmitter after the last character
is loaded into the Channel A THR.
6. The last character will be transmitted and
OPR[O] will be reset one bit time after the
last stop bit, causing RTSAN to be negated.
MR2A[4]- Channel A Clear-to-Send
Control
II this bit is 0, CTSAN has no effect on the transmitter. If this bit is aI, the transmitter checks
the state of CTSAN (IPO) each time it is ready
to send a character. If IPO is asserted (Low),
the character is transmitted. II it is negated
(High), the TxDA output remains in the marking
state and the transmission is delayed until
CTSAN goes low. Changes in CTSAN while a
character is being transmitted do not affect the
transmission of that character..
MR2A[3:0]- Channel A Stop Bit Length
Select
This field programs the length olthe stop bit appended to the transmitted character. Stop bit
lengths of 9/ 16 to 1 and 1-9/16 to 2 bits, in increments 011/16 bit, can be programmed for character lengths 016, 7, and 8 bits. For a character
lengthsofSbits, 1-1/16t02 stop bits can be programmed in increments of 1/16 bit. In all cases,
the receiver only checks for a 'mark' condition
at the center of the first stop bit position (one bit
time after the last data bit, or after the parity bit
is enabled).
If an external 1X clock is used for the transmitter, MR2A[3] = 0 selects one stop bit and
MR2A[3] = 1 selects two stop bits to be
transmitted.
Product Specification
Philips Components-Signetics Data Communication Products
SCC2692·
Dual asynchronous receiver/transmitter (DUART)
Table 2.
Register Bit Formats
MR1A
MR1B
BIT 7
BIT6
BITS
RxRTS
CONTROL
RxlNT
SELECT
ERROR
MODE
0= No
1 = Yes
0= RxRDY
1 = FFULL
0= Char
1 = Block
BIT7
BIT6
CHANNEL MODE
00 = Normal
01 = Auto-Echo
10 = Local loop
11 = Remote loop
MR2A
MR2B
BIT4
BIT 3
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multidrop Mode
BITS
BIT 4
TxRTS
CONTROL
CTS
ENABLE Tx
0= No
1 = Yes
0= No
1 = Yes
BIT1
BIT 2
BITO
BITS PER
CHARACTER
PARITY
TYPE
PARITY MODE
0= Even
1 = Odd
BIT 3
00
01
10
11
BIT 2
=5
=6
=7
=8
BIT 0
BIT 1
STOP BIT LENGTH'
0=0.563
1 = 0.625
2 = 0.688
3 = 0.750
4 = 0.813
5 = 0.875
6 = 0.938
7= 1.000
C = 1.813
D = 1.875
E = 1.938
F = 2.000
8=1.563
9 = 1.625
A= 1.688
B= 1.750
NOTE:
'Add 0.5 to values shown for 0 -7 if channel is programmed for 5 bits/char.
BIT7
BIT 6
BIT 3
BIT 2
BIT 1
BITO
See Text
See Text
BIT3
BIT 2
BIT1
BITO
MISCELLANEOUS COMMANDS
BIT6
DISABLE Tx
ENABLE Tx
DISABLE Rx
ENABLE Rx
See Text
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
CRA
CRB
SRA
SRB
BIT4
TRANSMITTER CLOCK SELECT
CSRA
CSRB
BIT7
BITS
RECEIVER CLOCK SELECT
BIT S
BIT4
BIT 7
BIT6
BITS
BIT4
BIT3
BIT2
BIT1
BITO
RECEIVED
BREAK'
FRAMING
ERROR'
PARITY
ERROR'
OVERRUN
ERROR
TxEMT
TxRDY
FFULL
RxRDY
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
NOTE:
, These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from
the top of the FIFO together with bits (4:0). These bits are cleared by a "reset error status" command. In character mode they are discarded
when the corresponding data character is read from the FIFO.
OPCR
BIT7
BIT6
BITS
BIT4
OP7
OP6
OPS
OP4
0= OPR[?]
1 = TxRDYB
o =OPR[6]
1 = TxRDYA
0= OPR[5]
1 = RxRDY/
FFULLB
0= OPR[4]
1 = RxRDY/
FFULLA
BIT 7
BIT6
BIT S
BIT4
ACR
November 5, 1990
BRGSET
SELECT
COUNTERITIMER
MODE AND SOURCE
0= set 1
1 = set 2
See Table 4
143
BIT3
BIT 2
BIT 1
OP3
BITO
OP2
00 = OPR[3]
01 = CIT OUTPUT
10 = TxCB(IX)
11 = RxCB(IX)
11 =OPR[2]
01 = TxCA(16X)
10 = TxCA(IX)
11 = RxCA(IX)
BIT3
BIT 2
BIT 1
BITO
DELTA
IP31NT
DELTA
IP21NT
DELTA
IP 11NT
DELTA
IPO INT
0= Off
1 =On
o = Off
O=Off
1 =On
O=Off
1 =On
1 =On
Product Specification
Philips Components-Signetics Data Communication Products
Dualasynchronous receiver/transmitter (OUART)
Table 2.
SCC2692
Register Bit Formats (Continued)
IPCR
ISR
,
IMR
BIT 7
BIT6
BITS
BIT4
BIT 3
BIT2
BITl
BIT 0
DELTA
IP3
DELTA
IP2
DELTA
IP 1
DELTA
IPO
IP3
IP2
IPl
IPO
0= No
1 = Yes
O=No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= Low
1 = High
0= Low
1 = High
O=Low
1 = High
o = Low
1 = High
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
BITl
BITO
INPUT
PORT
CHANGE
DELTA
BREAK B
RxRDYI
FFULLB
TxRDYB
COUNTER
READY
DELTA
BREAK A
RxRDYI
FFULLA
TxRDYA
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
a = No
1 = Yes
o =No
1 = Yes
0= No
1 = Yes
o =No
1 = Yes
O=No
1 = Yes
BIT7
BIT6
BITS
BIT 4
BIT3
BIT2
BITl
BIT 0
IN. PORT
CHANGE
INT
DELTA
BREAK B
INT
RxRDYI
FFULLB
INT
TxRDYB
INT
COUNTER
READY
INT
DELTA
BREAK A
INT
RxRDYI
FFULLA
INT
TxRDYA
INT
0=011
1 =On
0=011
1 =On
0=011
1 =On
0=011
1 =On
0=011
1 =On
0=011
1 =On
o = Off
1 =On
0=011
1 =On
BIT 7
BIT6
BITS
BIT4
BIT3
BIT2
BITl
BITO
CIT[l5)
CIT[14]
C/T[13]
C/T{12]
CIT[II]
CIT[10]
CIT[9]
C/T[8]
CTUR
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
BITI
BITO
CIT[7]
CIT[6]
CIT[S]
CIT[4)
CIT[3]
CIT[2)
CIT[I]
C/T[O)
CTLR
MR1 B - Channel B Mode'
Register 1
CSRA - Channel A Clock Select
Register·
MRI B is accessed when the Channel B MR
pointer points to MR 1. The pointer is selto MR 1
by RESET or by a 'set pointer' command
applied via CRB. After reading or writing
MRI B, the pointer will point to MR2B ..
CSRA[7:4)- Channel A Receiver Clock
Select
This field selects the baud rate clock for the
Channel A transmitter. The field definition is
shown in Table 3.
The bit definitions for this registar are identical
to MR1A, except that all control actions apply
to the Channel B receiver and transmitter and
th'e corresponding inputs and outputs.
MR2B - Channel B Mode
Register 2
MR2B is accessed y.ohen the Channel B MR
pointer points to MR2, which occurs after any
access to MR 1B. Accesses to MR2B do not
change the pointer.
CSRA[3:0)- Channel A Transmitter Clock
Select
This field selects the baud rate clock for the
Channel A transmitter. The field definition is as
shown in Table 3, except as follows:
CSRA[3:0)
1110
1111
ACR[7] = 0
IP3-16X
IP3-1X
IP3-16X
IP3-1X
The transmitter clock is always a 16X clock except for CSRA[3:0) = 1111.
The bit definitions for mode register are identi·
cal to the bit definitions for MR2A, except that
all control actions apply to the Channel B receiver and transmitter and the corresponding
inputs and outputs.
November 5, 1990
ACR[7] = 1
144
Table 3. Baud Rate
CSRA[7:4]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
,0,',
1100
1101
1110
1111
ACR[7] =0
ACR[7] = 1
50
110
134.5
200
300
600
1,2()0
1,050
2,400
4,000
7,2()0
9,600
38.4K
Timer
IP4-16X
IP4-1X
75
110
134.5
150
300
600
1,200
2,000
2,400
4,800
1,800
9,600
19.2K
Timer
IP4-16X
IP4-1X
NOTE: The receiver clock IS always a 16X
clock except for CSRA[7:4] = 1111.
Philips Components...signetics Data Communication Products
Product Specification
Dual asynchronous receiver/transmitter (DUART)
CSRB - Channel B Clock Select
Register
CSRB[7:4]- Channel B Receiver Clock
Select
This field selects the baud rate clock for the
Channel B receiver. The field definition is as
shown in Table 3, except as follows:
CSRB[7:4]
ACR[7]
1110
1111
=0
IP6-16X
IP6-1X
ACR[7]
=1
0111
IP6-16X
IP6-1X
1000
The receiver clock is always a 16X clock except
for CSRB[7:4] = 1111.
CSRB[3:0]- Channel B Transmitter Clock
Select
This field selects the baud rate clock for the
Channel B transmitter. The field definition is as
shown in Table 3, except as follows:
CSRB[3:0]
ACR[7]
1110
1111
=0
IPS-16X
IPS-IX
ACR[7]
1001
1010
=1
IP5-16X
IP5-1X
1011
1100
The transmitter clock is always a 16X clock exceptfor CSRB[3:0] = 1111.
CRA - Channel A Command
Register
CRA is a register used to supply commands to
Channel A. Multiple commands can be specified in a single write to CRA as long as the commands are non-conflicting, e.g., the 'enable
transmitter' and 'reset transmitter' commands
cannot be specified in a single command word.
1101
1110
CRA[7:4]- Miscellaneous Commands
The encoded value of this field may be used to
specify a single command as follows:
COMMAND
CRA[6:4]
0000 No command.
0001 Reset MR pointer. Causes the Channel
A MR pointer to point to MRI.
0010 Reset receiver. Resets the Channel A
receiver as if a hardware reset had been
applied. The receiver is disabled and
the FIFO is flushed.
0011 Reset transmitter. Resets the Channel
A transmitter as if a hardware reset had
been applied.
0100 Reset error status. Clears the Channel
A Received Break, Parity Error, and
Overrun Error bits in the status register
(SRA[7:4]). Used in character mode to
clear OE status (although RB, PE and
FE bits will also be cleared) and in block
mode to clear all error status after a
block of data has been received.
0101 Reset Channel A break change interrupt. Causes the Channel A break detect change bit in the interrupt status
register (lSR[2]) to be cleared to zero.
0110 Start break. Forces the TxDA output
low (spacing). I! the transmitter is
emptythestartofthebreakconditionwill
November 5, 1990
1111
be delayed up to two bit times. If the
transmitter is active the break begins
when transmission of the character is
completed. If a character is in the THR,
the start of the break will be delayed until
that character, or any other loaded
subsequently are transmitted.
The
transmitter must be enabled for this
command to be accepted.
Stop break. The TxDA line will go High
(marking)within two bit times. TxDA will
remain High for one bit time before the
next character, if any, is transmitted.
AssertRTSN. Causes the RTSNoutput
to be asserted (Low).
Negate RTSN. Causes the RTSN output to be negated (High).
Set TImeout Mode On. The receiver in
this channel will restart the CfT as each
receive character is tran sferred from the
shift register to the RHR. The CIT is
placed in the counter mode, the STARTI
STOP counter commands are disabled,
the counter is stopped, and the Counter
Ready Bit, ISR[3]. is reset.
Not used.
Disable TImeout Mode. This command
returns control of the CIT to the regular
START/STOP counter commands. It
does not stop the counter, or clear any
pending interrupts. After disabling the
timeout mode, a 'Stop Counter· command should be issued
Not used.
Power Down Mode On. In this mode,
the DUART oscillator is stopped and all
functions requiring this clock are suspended. The execution of commands
other than disable power down mode
(1111) requires a Xl/ClK. While in the
power down mode, do not issue any
commands to the CR exceptthe disable
power down mode command. The contents of all registers will be saved while
in this mode.. It is recommended that
the transmitter and receiver be disabled
prior to placing the DUART into power
down mode. This command is in CRA
only.
Disable Power Down Mode. This command restarts the oscillator. After invoking this command, wait for the oscillator
to start up before writing further commands to the CR. This command is in
CRA only.
CRA[3]- Disable Channel A
Transmitter
This command terminates transmitter operation and resets the TxDRY and TxEMT status
bits. However, if a character is being transmitted or if a character is in the TH R when the
transmitter is disabled, the transmission of the
character(s) is completed before assuming the
inactive state.
145
SCC2692
CRA[2]- Enable Channel A
Transmitter
Enablesoperation of the Channel A transmitter.
The TxRDY status bit will be asserted.
CRA[l]- Disable Channel A Receiver
This command terminates operation of the receiver immediately - a character being received will be lost. The command has no effect
on the receiver status bits or any other control
registers. I! the special multidrop mode is programmed, the receiver operates even if it is disabled. See Operation section.
CRA[O] - Enable Channei A Receiver
Enables operation of the Channel A receiver.
I! not in the special wakeup mode, this also
forces the receiver into the search for start bit
state.
CRB - Channel B Command
Register
CRB is a register used to supply commands to
Channel B. Multiple commands can be specified in a single write to CRB as long as the commands are non-conflicting, e.g., the 'enable
transmitter' and 'reset transmitter' commands
cannot be specified in a single command word.
The bit definitions for this register are identical
to the bit definitions for CRA, with the exception
of comamnds "Ex" and "Fx" which are used for
power downmode. These two commands are
not used in CRB. All other control actions that
apply to CRA also apply to CRB.
SRA - Channel A Status
Register
SRA[7] - Channel A Received Break
This bit indicates that an all zero character of
the programmed length has been received
without a stop bit. Only a single FIFO position
is occupied when a break is received: further
entries to the FIFO are inhibited until the RxDA
line to the marking state for at least one-hal! a
bit time (two successive edges of the internal or
external 1X clock).
When this bit is set, the Channel A 'change in
break· bit in the ISR (ISR[2)) is set. ISR[2] is
also set when the end of the break condition, as
defined above, is detected.
The break detect circuitry can detect breaks
that originate in the middle of a received character. However, if a break begins in the middle
of a character, it must persist until at least the
end of the next character time in order for it to
be detected.
Philips Components-Signetics Data Communication Products
Product Specification
Dual asynchronous receiver/transmitter (DUART)
SRA(6)- Channel A Framing Error
This bit, when set, indicates that a stop bit was
not detected when the corresponding data
character in the FIFO was received. The stop
bit check is made in the middle of the first stop
bit position.
SRA(5) - Channel A Parity Error
This bit is set when the 'with parity' or 'force parity' mode is programmed and the corresponding character in the FIFO was received with
incorrect parity.
'In the special multidrop mode the parity error bit
stores the receive AID bit.
SRA[4)- Channel A Overrun Error
This bit, when set, indicates that one or more
characters in the received data stream have
been lost. It is set upon receipt of a new character when the FIFO is full and a character is already in the receive shift register waiting for an
empty FIFO position. When this occurs, the
character in the receive shift register (and its
break detect, parity error and framing error status, if any) is lost.
This bit is cleared by a 'reset error status' command.
SRA[3) - Channel A Transmitter Empty
(TxEMTA)
This bit will be set when the Channel A transmitter underruns; i.e., both the Transmit Holding
Register (THR) and the transmit shift register
are empty. It is set after transmission of the last
stop bit of a character if no character is in the
THRawaiting transmission. liis reset when the
THRis loaded by the CPU orwhen the transmitter is disabled.
SRA[2)- Channel A Transmitter Ready
(TxRDVA)
This bit, when set, indicates that the THR is
empty and ready to be loaded with a character.
This bit is cleared when the THR is loaded by
the CPU and is set when the character is transferred to the transmit shift register. TxRDY is
reset when the transmitter is disabled and is set
when the transmitter is first enabled, e.g., characters loaded into the THRwhile the transmitter
is disabled will not be transmitted.
SRA[1) - Channel A FIFO Full (FFULLA)
This bit is set when a character is transferred
from the receive shift register to the receive
FIFO and the transfer causes the FIFO to become lull, i.e., all three FI FO pOSitions are occupied. It is reset when the CPU reads the RHR.
If a character is waiting in the receive Shift register because the FIFO is lull, FFULL will not be
reset when the CPU reads the RHR.·
November 5, 1990
SRA[O)- Channel A Receiver Ready
(RxRDVA)
This bit indicates that a character has been received and is waiting in the FIFO to be read by
the CPU. It is set when the character is transferred from the receive shift to the FI FO and reset when the CPU reads ttie RHR, if after this
read there are not more characters still in the
FIFO.
SRB - Channel B Status
Register
The bit delinitions for this register are identical
to the bit definitions lor SRA, except that all status applies to the Channel B receiverand transmitter and the corresponding inputs and
outputs.
OPCR - Output Port
Configuration Register
OPCR[7) - OP7 Output Select
This bit programs the OP7 output to provide
one of the following:
- The complement of OPR[?).
- The Channel B transmitter interrupt output
which is the complement of TxRDYB.
When in this mode OPT acts as an opendrain output. Note that this output is not
masked by the contents 01 the IMR.
OPCR[6) - OP6 Output Select
This bit programs the OPS output to provide
one of the iollowing:
- The complement of OPR[S).
- The Channel A transmitter interrupt output
which is the complement of TxRDYA.
When in this mode OPS acts as an opendrain output. Note that this output is not
masked by the contents of the IMR.
OPCR[S]- OPS Output Select
This bit programs the OP5 output to provide
one of the following:
- The complement of OPR[5).
- The Channel B transmitter interrupt output
which is the complement of ISR[5). When
in this mode OP5 acts as an open-drain
output. Note that this output is not masked
by the contents of the I MR.
SCC2692
output. Note that this output is not
masked by the contents of the IMR.
OPCR[3:2].,. OP3 Output Select
This bit programs the OP3 output to provide
one of the following:
- The complement of OPR[3].
- The counterllimer output, in which case
OP3 acts as an open-drain output. In the
timer mode, this output is a square wave at
the programmed frequency. In the counter
mode, the output remains High until terminal count is reached, at which time it goes
Low. The output returns to the High state
when the counter is stopped by a stop
counter command. Note that this output is
not masked by the contents of the IMR.
- The 1X clock for the Channel B transmitter,
which is the clock that shifts the transmitted data. If data is not being transmitted, a free running 1X clock is output.
- The 1X clock for the Channel B receiver,
which is the clock that samples the received data. If data is not being received,
a free running lX clock is output.
OPCR[1 :0] - OP2 Output Select
This field programs the OP2 output to provide
one of the following:
- The complement of OPR(2).
- The ISX clock for the Channel A transmitter. This is the clock selected by
CSRA[3:0), and will be a 1X clock if
CSRA[3:0) = 1111.
- The IX clock'for the Channel A transmitter,
which is the clock that shifts the transmitted data. If data is not being transmitted, a free running 1X clock is output.
- The IX clock for the Channel A receiver,
which is the clock that samples the received data. If data is not being received,
a free running 1X clock is output.
ACR - Auxiliary Control
Register
ACR[7) - Baud Rate Generator Set Select
This bit selects one of two sets of baud rates to
be generated by the BRG:
Set 1:
OPCR[4]- OP4 Output Select
This field programs the OP4 output to provide
. one of the following:
- The complement of OPR[4).
- The Channel A receiver interrupt output
which is the complement oIISR[l]. When
in this mode OP4 acts as an open-drain
146
Set 2:
SO, 110, 134.5,200,300, SOO,
1.05K, 1.2K, 2.4K, 4.8K, 7.2K,
9.SK, and 38.4K baud.
75,110,134.5, ISO, 300, SOO,
1.2K, l.aK, 2.0K, 2.4K, 4.aK, 9.SK,
and 19.2K baud.
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
The selected set of rates is available for use by
the Channel A and B receivers and transmitters
as described in CSRA and CSRB. Baud rate
generator characteristics are given in Table 4.
Table 4.
Bit Rate Generator
Characteristics
Crystal or Clock =
3.6864MHz
NORMAL
RATE
(BAUD)
ACTUAL
16XCLOCK
(kHz)
50
75
110
134.5
150
200
300
600
1050
1200
1BOO
2000
2400
4BOO
7200
9600
19.2K
3B.4K
ERROR(%)
O.B
1.2
1.759
2.153
2.4
3.2
4.B
9.6
16.756
19.2
2B.B
32.056
3B.4
76.B
115.2
153.6
307.2
614.4
0
0
-0.069
0.059
0
0
0
0
-0.260
0
0
0.175
0
0
0
0
0
0
NOTE:
Duty cycle of 16X clock is 50% ± 1%.
ACR[6:4)- CounterlTimer Mode And
Clock Source Select
This field selects the operating mode of the
counter/timer and its clock source as shown in
Table 5.
Table 5.
ACR 6:4 Field
Definition
ACR
6:4
MODE
CLOCK SOURCE
000
001
Counter
Counter
010
Counter
011
Counter
100
101
TImer
TImer
110
TImer
111
TImer
External (IP2)
TxCA - IX clock of
Channel A transmitter
TxCB -IX clock of
Channel B transmitter
Crystal or external clock
(Xl/ClK) divided by 16
External (IP2)
External (IP2) divided
by 16
Crystal or external clock
(Xl/ClK)
Crystal or external clock
(Xl/ClK) divided by 16
ACR[3:0)-IP3, IP2, IP1, IPO
Change-al·State Interrupt Enable
This field selects which bits of the input port
change register (IPCR) cause the input change
bit in the interrupt siatus register (ISR[7)) to be
November 5, 1990
set. If a bit is in the 'on' state the setting of the
corresponding bit in the IPCR will also result in
the setting of ISR[?), which results in the generation of an interrupt output if IMR[?) = 1. If a bit
is in the 'off' state, the setting of that bit in the
IPCR has no effect on ISR[?).
IPCR - Input Port Change
Register
IPCR[7:4)-IP3, IP2, IP1, IPO
Change-aI-State
These bits are set when a change-of-state, as
defined in the input port section of this data
sheet, occurs at the respective input pins. They
are cleared when the IPCR is read by the CPU.
A read of the IPCR also clears ISR[7), the input
change bit in the interrupt status register. The
setting of these bits can be programmed to
generate'an interrupt to the CPU.
IPCR[3:0)-IP3, IP2, IP1, IPO
Change-aI-State
These bits provide the current state of the respective inputs. The information is unlatched
and reflects the state of the input pins at the
time the IPCR is read.
ISR - Interrupt Status Register
This register provides the status of all potential
interrupt sources. The contents of this register
are masked by the Interrupt Mask Register
(IMR). If a bit in the ISR is a 'I' and the corresponding bit in the IMR is also a 'I', the INTRN
output will be asserted (low). If the corresponding bit in the IMR is a zero, the state of
the bit in the ISR has no effect on the INTRN
output. Note·that the IMR does not mask the
reading of the ISR - the true status will be provided regardless of the contents of the IMR.
The contents of this register are initialized to
00,6 when the DUART is reset.
ISR[7)-lnput Port Change Status
This bit is a '1' when a change-of-state has occurred at the IPO, IP1, IP2, or IP3 inputs and
that event has been selected to cause an interrupt by the programming of ACR[3:0]. The bit
is cleared when the CPU reads the IPCR.
ISR(6)- Channel B Change In Break
This bit, when set, indicates that the Channel B
receiver has detected the beginning or the end
of a received break. It is reset when the CPU
issues a Channel B 'reset break change interrupt' command.
ISR[S) - Channel B Receiver Ready
or FIFO Full
The function of this bit is programmed by
MR 1B[6). If programmed as receiver ready, it
indicates that a character has been received in
Channel B and is waiting in the FIFO to be read
by the CPU. It is set when the character is
transferred from the receive shift register to the
FIFO and reset when the CPU reads the RHR.
147
SCC2692
If after this read there are more characters stili
in the FIFO the bit will be set again after the
FIFO is 'popped'. If programmed as FIFO full,
it is set when a character is transferred from the
receive holding register to the receive FI FO and
the transfer caused the Channel B FIFO to becomefull; i.e., all three FIFO positions are oceupied. It is reset when the CPU reads the RHR.
If a character is waiting in the receive shift register because the FIFO is full, the bit will be set
again when the waiting character is loaded into
the FIFO.
ISR(4)- Channel B Transmitter Ready
This bit is a duplicate of TxRDYB (SRB[2)).
ISR[3)- Counter Ready.
In the counter mode, this bit is set when the
counter reaches terminal count and is reset
when the counter is stopped by a stop counter
command.
In the timer mode, this bitis set once each cycle
of the generated square wave (every other time
thatthe counter/timer reaches zero count). The
bit is reset by a stop counter command. The
.command, however, does not stop the counter/
timer.
ISR[2) - Channel A Change in Break
This bit, when set, ;ndicates that the Channel A
receiver has detected the beginning or the end
of a received break. It is reset when the CPU
issues a Channel A 'reset break change interrupt' command.
ISR[1) - Channel A Receiver Ready Or
FIFO Full
The function of this bit is programmed by
MR1A[6]. If programmed as receiver ready, it
indicates that a character has been received in
Channel A and is waiting in the FIFO to be read
by the CPU. It is set when the character is
transferred from the receive shift register to the
FIFO and reset when the CPU reads the RHR.
If after this read there are more characters still
in the FIFO the bit will be set again after the
FIFO is 'popped'. If programmed as FIFO full,
it is set when a character is transferred from the
receive holding register to the receive FIFO and
the transfer caused the Channel A FIFO to becomefull; i.e., all three FIFO positions areoceupied. Itis reset when theCPU reads the RHR.
If a character is waiting in the receive shift register because the FIFO is full, the bit will be set
again when the ISR[O] and IMR waiting character is loaded into the FIFO.
ISR[O)- Channel A Transmitter Ready
This bit is a duplicate of TxRDYA (SRA[2]).
IMR - Interrupt Mask Register
The programming of this register selects which
bits in the ISR causes an interrupt output. If a
bit in the ISR is a 'I' and the corresponding bit
in the IMR is also a 'I' the INTRN output will be
Product Specification
Philips Components-Signetics Data Communication Products
SCC2692
Dual asynchronous receiver/transmitter (DUART)
asserted. If the corresponding bit in the IMR is
a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR
does not mask the programmable interrupt outputs OP3-0P7 or the reading of the ISR.
CTUR and CTLR - CounterlTimer
Registers
The CTUR and CTlR hold the eight MSBs and
eight lSBs, respectively, of the value to be
used by the counterltimer in either the counter
or timer modes of operation. The minimum value which may be loaded into the CTURlCTlR
registers is H'0002'. Note that these registers
are write-only and cannot be read by the CPU.
In the timer (programmable divider) mode, the
CIT generates a square wave with a period of
twice the value (in clock periods) of the CTUR
and CTlR. If the value in CTUR and CTlR is
changed, the current half-period will not be affected, but subsequent half periods will be. The
CIT will not be running until it receives an initial
'Start Counter' command (read at address
A3-AO ; 11(0). After this, while in timer mode,
the CIT will run continuously. Receipt of a start
counter command (read with A3-AO ; (110)
causes the counter to terminate the currenttiming cycle and to begin a new cycle using the values in CTUR and CTlR.
The counter ready status bit(ISR[3)) is set once
each cycle of the square wave. The bit is reset
by a stop counter command (read with A3-AO
; H'F'). The command however, does not stop
the CIT. The generated square wave is output
on OP3 if it is programmed to be the CIT
output.
In the counter mode, the CIT counts down the
number of pulses loaded into CTUR and CTlR
by the CPU. Counting begins upon receipt of
a start counter command. Upon reaching terminal count H'OOOO', the counter ready interrupt bit (ISR[3)) is set. The counter continues
counting past the terminal count until stopped
by the CPU. If OP3 is programmed to be the
output of the CIT, the output remains High until
terminal count is reached, at which time it goes
low. The output returns to the High state and
ISR[3] is cleared when the counter is stopped
by a stop counter command. The CPU may
change the values of CTUR and CTlR at any
time, but the new count becomes effective only
on the next start counter commands. If new values have not been loaded, the previous count
values are preserved and used for the next
count cycle
In the counter mode, the current value olthe upper and lower 8 bits of the counter eCTU, CTL)
may be read by the CPU. It is recommended
that the counter be stopped when reading to
prevent potential problems which may occur if
a carry from the lower 8 bits to the upper 8 bits
occurs between the times that both halves of
the counter are read. However, note thata subsequent start counter command will cause the
counter to begin a newcountcycle using the values in CTUR and CTlR.
A----i
RESETN
-J~ 'RES~~
Figure 1. Reset Timing
M-A3
CEN
'RWD---~
RON
DO-D7
(READ)
flOAT
-----+-1
'RWD-I
WON
(W~,.o~
f
'DS-
_. _
---------------
VAUD
r:'DH
X
~-------------------
Figure 2. Bus Timing
November 5, 1990
148
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
SCC2692
""'~
I~P6
(a) INPUT PINS
WRN
/
OPO-OP1_ _ _ OLD
DATA
_
__
)<
~
NEW DATA
t . . _ __
__
(b) OUTPUT PINS
Figure 3. Port Timing
,~~ '_: : : : : : :~ qR-I~
___
____
NOTES:
1. INTRN or QP3·0P7 when used as interrupt outputs.
2. The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching
signal. Vu• to a point O.5V above Va... This point represents noise margin that assures true sw~ching has occurred. Beyond this level, the effects of external circuitry and
test environment are pronounced and can greatly affect the resultant measurement.
Figure 4. Interrupt Timing
November 5. 1990
149
Product Specification
Philips Components-Signetics Data Communication Products
SCC2692
Dual asynchronous receiver/transmitter (DUART)
tell(
teTC
4700
XliClK
CTClK
R.C
ClK
T.C
In.
"NOTE: X2 CAN BE lEFT OPEN OR
GROUNDED WHEN XI IS DRIVEN.
tr.
CI
=C2 - 24pF FOR C
L
tr--~~--------~ XI
= 20pF
SCC2682
XI
1
r---'1
=
C2
d=::;;;;
T
~
X2
3.6B64MHz
TYPICAL CRYSTAL SPECIACATION
2-4 MHz
12-32 pF
FREOUENCY
lOAD CAPACITANCE (Cel
TYPE OF OPERATION
,
PARALLEL RESONANT, FUNDAMENTAL MODE
Figure 5. Clock Timing
--t
o
(IO~~:~~KS)
~
T.C
(INPUT)
hO
-1
~
_~tTCS~
T.C
(IX OUTPUT)
,
/
Figure '6. Transmitter External Clocks
November 5, 1990
150
\
~
X2"
Product Specification
Philips Components-Signetics Data Communication Products
SCC2692
Dual asynchronous receiver/transmitter (DUART)
(1X
INP'::~
\
rr-
RXD--~f-JL
Figure 7. Receiver External Clock
TxD
TRANSMITTER
ENABLED
neRDY
(SR2)
WRN
CTSN'
(IPO) _ _ _.J
RTSN'
(OPO)
A
n
( ' ' - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _, ( '_ _ __
OPR(O)= 1
OPR(O)= 1
NOTES,
1. Timing shown for MR2(4) '" 1.
2. Timing shown for MR2(5) .. 1.
Figure 8. Transmitter Timing
November 5. 1990
151
Product Specification
Philips GompOnents-Signetics Data Communication Products
SCC2692
Dual asynchronous receiver/transmitter (DUART)
RxD
RECEIVER
ENABLED
.RxRDY ____________
(s~)
~
-+________________--1
FFULL
(SR1) ____________________
RxRDYI ---------------,
FFULL
(OPS)'
RDN ---------------,
OVERRUN
(SR4) ________________________________________
~~~~
RTS'
(CPO)
OPR(O) = 1
NOTES:
1. T1mingshownforMR1(7)_1.
2. Shown for OPCR(4) ~ 1 and MR(6) .. O.
Figure 9. Receiver TIming
MASTER STAnON
BIT9
BIT 9
I ADD"! 1 I
TxD
I
l',~
"
~','
______________-rI• ______
-L_I~AD~D~~~!~11
---c(""
BIT9
~~
~.
TRANSMlnER~
ENABLED
I
I
.
i~~~
I
I
,/-'----:;):~~'~l4__-----Ir(
_ ______________
MR1(4-3) = 11
MR'(2)='
L'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
~\
~
WRN
c
(
MR1 (2) = 1 ADO~
ADDN1 MR1(2) = 0 DO
PERIPHERAL STAnON
.--__.;:B::.:ITr=9,
BIT 9
BIT9
/'
RxD - - - ,
0
ADD..
DO:O II
RECEIVER
1
I -R
ENABLED ______________________""'If--__-'
I
I
:I I I
.',/----'
BIT 9
BITS
oI
L')-:--------f.~~--'-J..I!:!AD~Dl!!#2;i..:'wlllL.....J_--'-!:W
!d II
I
l
I
'~
tl...
L-
I
\\
I
I
~-------.,
RDN::-U-r----------------~---, ~,<--~------r~~
RxRDY
MR1(4-3) = 11
ADD.,
STATUS DATA,
STATUS DATA,
DO
ADD#2
Figure 10. Wake·Up Mode
November 5. 1.990
152
Philips Components-Signetics Data Communication Products
Product Specification
SCC2692
Dual asynchronous receiver/transmitter (DUART)
2.7K
INTRN
'\IV'
O~-------1>----~
1
I
o +5V
50pF
=
7500:
D(}-D7
TxDAlB
2.15V
OPO-{)P7
=
Figure 11. Test Conditions on Outputs
November5,1990
153
Philips Components-Signetics
Document 11/0., ,
ECN No.
Date of Issue
November 12, 1990
Status
Preliminary Specification
SC26C92
Oualasynchronbus
receiver/transmitter (OUART)
Data Communlcallon Products
DESCRIPTION
The SC26C92 is a pin and function
replac~ment for the 2692 with added
features and deeper f~os. Its
configuration on power up is that of the
2692. Its differences from the 2692 are:
8 character receiver, 8 character
transmit fifos, receiver watch dog timer,
mode register 0 is added, extended
baud rate and overall faster speeds,
programmable receiver and transmitter
interrupts.
The Signetics SC26C92 Dual Universal
Asynchronous ReceiverITransmitter
(DUART) is a single-chip CMOS-LSI
communications device that provides
two full-duplex asynchronous
receiverltransmitter channels in a single
package. It interfaces directly with
microprocessors and may be used in a
polled or interrupt driven system.
The operating mode and data format of
each channel can be programmed
independently. Additionally, each
receiver and transmitter can select its
operating speed as one of eighteen
fixed baud rates, a 16X clock derived
from a programmable counterltimer, or
an external I X or 16X clock. The baud .
rate generator and counterltimer can
operate directly from a crystal or from
external clock inputs. The ability to
independently program the operating
speed of the receiver and transmitter
make the DUART particularly attractive
for dual-speE;!d channel applications
such as clustered terminal systems.
Each receiver is buffered by eight
character fifos to minimize the potential
of receiver over-run or to reduce
interrupt overhead in interrupt driven
systems. In addition, a flow control
capability is provided to disable a
remote transmitter when the receiver
buffer is full.
Also provided on the SC26C92 are a
mUltipurpose 7-bit input port and a
mUltipurpose 8-bit output port. These
can be used as general purpose 110
ports or can be assigned specific
functions (such as clock inputs or
status/interrupt outputs) under program
control.
The SC26C92 is available in three
package versions: 40-pin and 28-pin,
0.6" wide, DIPs and a 44-pin PLCC.
FEATURES
• Dual full-duplex independent asynchronous receiver/transmitters
• 8 character Fifos for each receiver and
transmitter
• Programmable data forinat
- 5 to 8 data bits plus parity
- Odd, even, no parity or force parity
- I, 1.5 or 2 stop bits programmable
in 1/16-bit increments
• Programmable baud rate for each
receiver and transmitter selectable
from:
- 18 fixed rates: 50 to 38.4k baud
- Other baud rates to 230.4k baud at
16X
- Programmable user-defined rates
derived from a programmable
counterltimer
- External 1X or 16X clock
• Parity, framing, and overrun error
detection
• False start bit detection
• Line break detection and generation
154
• Programmable channel mode
- Normal (full-duplex)
- Automatic echo
- Local loopback
- Remote loopback
• Multi-function 7-bit input port
- Can serve as clock or control inputs
- Change of state detection on four
inputs
• Multi-function 8-bit output port
- Individual bit set/reset capability
- Outputs can be programmed to be
status/interrupt signals
• Versatile interrupt system
- Single interrupt output with eight
maskable interrupting conditions
- Output port can be configured to
provide a total of up to six separate
wire-aRable interrupt outputs
- Each fifo can be programmed for
four different interrupt levels
- Watch dog timer for each receiver
• Maximum data transfer rates:
I X-I MB/sec, 16X - 1Mb/sec
• Automatic wake-up mode for multidrop
applications
• Start-end break interrupt/status
• Detects break which originates in the
middle of a character
• On-chip crystal oscillator
• Power down mode
". Receiver timeout mode
• Commercial, industrial and military
temperature range versions
• TIL compatible
• Single +5V power supply
Preliminary Specification
Philips Components-Signetics Oata Communication Products
SC26C92
Dual asynchronous receiver/transmitter (DUART)
PIN CONFIGURATIONS
INDEX
CORNER
vcc
IP'
IPS
IP6
Vo<
IP2
1P2
CEN
CEN
RESET
RESET
X2
X2
XlICLK
X1/CLK
OPl
OP3
TxOA
TxDA
OPO
OPO
0P2
OPS
0P4
0P7
OPS
01
OS
07
03
02
GNO
OS
0'
07
06
GNO
DO
02
DO
01
TOP VIEW
RxOA
RxDA
RxDB
04
06
INTRN
INTRN
PIN/FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
ORDERING INFORMATION
DESCRIPTION
Vcc
= +5V ±5%, TA = 0 to +70°C
Vcc
= +5V ±10%, TA = -40 to +85°C
40-Pin Cerdip
SC26C92AC1 F40
28-Pin Cerdip
SC26C92AC 1F28
SC26C92AA t F28
40-Pin Plastic 01 P
SC26C92ACl N40
SC26C92AA 1N40
28-Pin Plastic 01 P
SC26C92AC1 N28
SC26C92AA 1N28
44-Pin Plastic LCC
SC26C92AC 1A44
SC26C92AA 1A44
November 12, 1990
SC26C92AA 1F40
155
NC
NJ
IP3
AI
IPI
A2
A3
IPO
WRN
RDN
RXDS
NC
TXDB
OPI
OP3
OP5
OP7
Dl
D3
D5
D7
GND
PIN/FUNCTION
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NC
INTRN
DB
D4
D2
DO
OP6
OP4
OP2
OPO
TXDA
NC
RXDA
Xl/eLK
X2
RESET
CEN
IP2
IP6
IP5
IP4
VCC
P'l'liminary Specification
Philips Components-Signetics Data Communication Products
SC26C92
Oualasynchronousreceiver/transmitter (OUART)
BLOCK DIAGRAM
~
8
IlO-D7
~
r-..
f
BUS BUfFER
CHANNEL A
,.--:..
8 BYTE mANSMIT
AFO
TRANSMIT
SHIFT REGISTER
f-- r--OPERATION CONTROL
RDN
WRN
CEN
AG-A3
RESET
4
I
ADDRESS
DECODE
I
I
R/WCONTROL
I
--
TxDA
"-
8 BYTE REcaVE
AFO
v
WATCH DOG TIMER
RECEIVE SHIFT
REGISTER
r---
RxOA
URAD,I,2
CRA
SRA
INTERRUPT CONTROL
INTRN
I
IMR
ISR
~
"-
I
"-
v
'"
TxDB
CHANNELB
(AS ABOVE)
v
RxDB
III
::>
III
~
TIMING
CLOCK
SELECTORS
XlICLK
X2
eOUNTERI
TIMER
I
XTALose
!if--
(,)
1=
--
I
0::
§
BAUD RATE
GENERATOR
I
I
/1
"
:E
~
~
05
CHANGE OF
STATE
DETECTORS (4)
"v
I
f-- r------
IPCR
ACR
,
7
IPO~P6
I
r---<
f--.
OUTPUT PORT
'--
r-..
r-..
FUNCTION
SELECT LOGIC
v
~
CSRA
eSRB
ACR
eTI.\!
eTLR
November 12, 1990
INPUT PORT
0
....
0
156
I
OPCR
OPR
8/
OPO-OP7
I
~
Vce
"
GND
Preliminary Specification
Philips Components-$ignetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
SC26C92
PIN DESCRIPTION
SYMBOL
APPLICABLE
TYPE
NAME AND FUNCTION
X
I/O
Data Bus: Bidirectional3-State data bus used to transfer commands, data and status between the
DUART and the CPU. 00 is the least significant bit.
X
X
I
Chip Enable: Active-low input signal. When low, data transfers between the CPU and the
DUART are enabled on 00-07 as controlled by the WRN, RON and AO-A3 inputs. Whep High,
places the 00-07 lines in the 3-State condition.
WRN
X
X
I
Write Strobe: When low and CEN is also low, the contents of the data bus is loaded into the
addressed register. The transfer occurs on the rising edge of the signal.
RON
X
X
I
Read Strobe: When low and CEN is also low, causes the contents of the addressed register to
be presented on the data bus. The read cycle begins on the falling edge of RON.
AO-A3
X
X
I
Address Inputs: Select the DUART internal registers and ports for readlwrite operations.
RESET
X
X
I
Reset: A High level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OPO-OP7
in the High state, stops the counter/timer, and puts Channels A and B in the inactive state, with the
TxDA and TxDB oUlputs in the mark (High) state.
INTRN
X
X
0
Interrupt Request: Active-low, open-drain, output which signals the CPU that one or more of the
eight maskable interrupting conditions are true.
Xl/ClK
X
X
I
Crystal 1 : Crystal or external clock input. A crystal or clock of the specified limits must be
supplied at all times. When a crystal is used, a capacitor must be connected from this pin to
ground (see Figure 5).
X2
X
X
I
Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be
connected from this pin to ground (see Figure 5). If Xl/ClK is driven from an external source, this
pin can be left open or connected to ground.
RxDA
X
X
I
Channel A Receiver Serial Data Input: The least significant bit is received first. "Mark" is High,
'space" is low.
RxDB
X
X
I
Channel B Receiver Serial Data Input: The least significant bit is received first. "Mark" is High,
·space" is Low.
TxDA
X
X
0
Channel A Transmitter Serial Data Output: The least significanl bit is transmitted first. This
output is held in the "mark" condition when the transmitter is disabled, idle or when operating in
localloopback mode. "Mark" is High, "space" is low.
TxDB
X
X
0
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This
output is held in the 'mark' condition when the transmitter is disabled, idle, or when operating in
localloopback mode. 'Mark' is High, 'space' is low.
OPO
X
X
0
Output 0: General purpose output or Channel A request to send (RTSAN, active-low). Can be
deactivated automatically on receive or transmit.
OPI
X
X
0
Output 1 : General purpose output or Channel B request to send (RTSBN, active-low). Can be
deactivated automatically on receive or transmit.
OP2
X
0
Output 2: General purpose output, or Channel A transmitter I X or 16X clock output, or Channel A
receiver 1X clock output.
OP3
X
0
Output 3: General purpose output or open-drain, active-low counter/timer output or Channel B
transmitter IX clock oulput, or Channel B receiver IX clock output.
OP4
X
0
Output 4: General purpose output or Channel A open-drain, active-low, RxRDYAN/FFUlLAN
output.
OP5
X
0
Output 5: General purpose output or Channel B open-drain, active-Low, RxRDYBN/FFUllBN
output.
OP6
X
X
0
0
Output 6: General purpose output or Channel A open-drain, active-Low, TxRDYAN oulput.
OP7
IPO
X
I
Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN).
IPI
X
I
Input 1: General purpose input or Channel B clear to send active-low input (CTSBN).
IP2
X
IP3
X
40,44
28
00-07
X
CEN
November 12,1990
X
Output 7: General purpose oulput, or Channel B open-drain, active-Low, TxROYBN output.
I
Input 2: General purpose input or counter/timer external clock input.
I
Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the
external ciock is used by the transmitter, the transmitted data is clocked on the falling edge of the
clock.
157
Preliminary Specification
Philips Components-$ignetics Data Communication Products
Dual asynchronous
receiv~r/transmitter
(DUART)
SC26C92
PIN DESCRIPTION (Continued)
SYMBOL
APPUCABLE
40,44
TYPE
NAME AND FUNCTION
28
IP4
X
I
Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock.
IPS
X
I
Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the
external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the
clock.
IPS
X
I
Input 6: General purpose input or Channel B receiver external clock input (RxCB). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock.
Vee
X
X
GND
X
X
I
"
I
Power Supply: +5V supply input.
'Ground
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
TA
Operating ambient temperature range 2
TSTG
Storage temperature range
Vee
Voltage from Vee t6 GND3
Vs
Voltage from any pin to GND3
Po
Power dissipation 5
"
RATING
UNIT
Note 4
DC
-65 to + 150
DC
-0.5 to +7.0
V
-0.5 to Vee +0.5
V
750
mW
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied.
.
2. For operating at elevated temperatures, the device must be derated based on + 150DCmaximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge.
Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range.
5. Maximum power dissipation of the chip when outputs are loaded externally. For operating current, see DC Electrical Characteristics.
November 12, 1990
158
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
SC26C92
DC ELECTRICAL CHARACTERISTICS1, 2, 3
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
V IL
V IH
V IH
Input low voltage
Input high voltage (except X1/CLK)
Input high voltage (X lIC LK)
VOL
VOH
Output low voltage
Output high voltage (except OD outputs)'
IOH = -4001lA
Vee-0 .5
IIX1PD
IILX1
IIHX1
X 1/CLK input current - power down
X1/CLK input low current - operating
X1/CLK input high current - operating
VIN = 0 to Vee
VIN = 0
VIN = Vee
IOHx2
IOHx2s
IOLx2
IOLX2S
X2 output high current - operating
X2 output high short circuit current - operating
X2 output low current - operating
X2 output low short circuit current - operating and
power down
II
Max
O.S
2.0
O.S Vee
UNIT
V
V
V
OA
V
V
-10
-75
0
+10
0
75
VOUT = Vee, X1 = 0
VOUT = 0, X1 = 0
VOUT = 0, X1 = Vee
VOUT = Vee, X1 = Vee
0
-10
-75
1
+75
-1
0
10
IlA
IlA
IlA
IlA
VIN = 0 to Vee
VIN=OtoVee
-10
-20
+10
+10
-10
IOL = 2AmA
Input leakage current:
All except input port pins
Input port pins
IOZL
Output off current high, 3-State data bus
Output off current low, 3-State data bus
VIN = Vee
VIN = OV
IODL
IODH
Open-drain output low current in off-state
Open-drain output high current in off-state
VIN = 0
VIN = Vee
10ZH
Typ
Power supply currentS
Operating mode
10
-10
10
TTL input levels
CMOS input levels
TTL input levels
CMOS input levels
lee
Power down mode
10
10
3.0
TBD
rnA
IlA
rnA
IlA
IlA
IlA
IlA
IlA
IlA
rnA
rnA
rnA
IlA
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, ali inputs swing between OAV and 2.4V with a transition time of 5ns
maximum. For X1/CLK this swing is between OAV and 4AV. Ali time measurements are referenced at input voltages of O.SV and 2.0V and
output voltages of O.SV and 2.0V, as appropriate.
3. Typical values are at +25'C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: C L = 50pF, RL = 2.7KQ to Vee.
5. Ali outputs are disconnected. Inputs are switching between TTL levels of 2AV and OAV or CMOS levels of Vee -0.2V and Vss + 0.2V.
AC CHARACTERISTICS1, 2, 4
LIMITS
SYMBOL
PARAMETER
Min
Typ3
Max
UNIT
Reset Timing (See Figure 1)
tRES
RESET pulse width
1.0
fLs
10
30
0
0
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bus TimingS (See Figure 2)
tAS
tAH
les
leH
tRW
tDD
tDA
tDF
tDI
tDs
tDH
tRWD
AO-A3 setup time to RDN, WRN Low
AO-A3 hold time from RDN, WRN Low
CEN setup time to RDN, WRN Low
CEN hold time from RDN, WRN High
WRN, RDN pulse width
Data valid after RDN Low
RDN Low to data bus active 7
Data bus floating after RDN High
RDN High to data bus invalid7
Data setup time before WRN High
Data hold time after WRN High
High time between reads and/or writes s, 6
November 12, 1990
20
75
0
55
159
110
110
45
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (OUART)
SC26C92
AC CHARACTERISTICS1, 2, 4 (Continued)
UMITS
SYMBOL
PARAMETER
Min
Typ3
Max
UNIT
110
ns
ns
ns
100
100
100
100
100
100
ns
ns
ns
ns
ns
ns
Port TimingS (See Figure 3)
Ips
tpH
IpD
Port input setup time before RON low
Port input hold time after RON High
OP n output valid from WRN High
0
0
Interrupt TIming (See Figure 4)
tlR
INTRN (or OP3-OP7 when used as interrupts) negated from:
Read RHR (RxRDY/FFUll interrupt)
Write THR (TxRDY interrupt)
Reset command (break change interrupt)
Stop CIT command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
Clock TIming (See Figure 5)
!eLK
fCLK
!eTC
fCTC
tRX
fRX
tTX
fTX
BO
2
60
Xl/ClK High or low time
Xl/ClK frequency
CTClK (IP2) High or low time
CTClK (IP2) frequencyB
RxC High or low time
RxC frequency {16X)B
{IX)B,9
TxC I-jigh or low time
TxC frequency {16X)B
{IX)B,9
a
220
0
0
220
0
0
3.6864
2
1
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
120
50
ns
ns
4
B
2
1
Transmitter Timing (See Figure 6)
tTXD
tTCS
TxD output delay from TxC low
Output delay from TxC low to TxD data output
a
Receiver Timing (See Figure 7)
tRXS
tRXH
RxD data setup time to RxC High
RxD data hold time from RxC High
100
100
ns
ns
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between O.4V and 2.4V with a transition time of 5ns
maximum. For Xl/ClK this swing is between O.4V and 4.4V. All time measurements are referenced at input voltages of O.BV and 2.0V and
output voltages of O.BV and 2.0V, as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL =50pF, RL = 2.7KQ to Vcc.
5. TIming is illustrated and referenced to the WRN and RON inputs. The device may also be operated with CEN as the 'strobing' input. CEN
and RON (also CEN and WRN) are ORed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.
6. If CEN is used as the 'strobing' input, the parameter defines the minimum High times between one CEN and the next. The RON signal must
be negated for tRWD to guarantee that any status register changes are valid.
7. Guaranteed by characterization of sample units.
8. Minimum frequencies are not tested but are guaranteed by design.
9. Clocks for 1X mode should be symetrical.
November 12,1990
160
Philips Components-Signetics Data Communication Products
Preliminary Specification
Dual asynchronous receiver/transmitter (DUART)
BLOCK DIAGRAM
The SC26C92 DUART consists of the following
eight major sections: data bus buffer. operation
control. interrupt control. timing. communications Channels A and B. input port and output
port. Refer to the Block Diagram.
Data Bus Buffer
The data bus buffer provides the interface between the external and internal data buses. It
is controlled by the operation control block to allow read and write operations to take place between the controlling CPU and the DUART.
Operation Control
The operation control logic receives operation
commands from the CPU and generates appropriate signals to internal sections to control
device operation. It contains address decoding
and read and write circuits to permit communications with the microprocessor via the data
bus buffer.
Interrupt Control
A single active-low interrupt output (INTRN) is
provided which is activated upon the occurrence of any of eight internal events. Associated with the interrupt system are the
Interrupt Mask Register (IMR) and the Interrupt
Status Register (ISR). The IMR can be programmed to select only certain conditions to
cause INTRN to be asserted. The ISR can be
read by the CPU to determine all currently active interrupting conditions.
Outputs OP3-0P7 can be programmed to provide discrete interrupt outputs for the transmitter. receivers. and counter/timer.
When OP3 to OP7 are programmed as interrupts. their output buffers are changed to the
open drain active low configuration.
Timing Circuits
The timing block consists of a crystal oscillator.
a baud rate generator. a programmable 16-bit
counter/timer. and four clock selectors. The
crystal oscillator operates directly from acrystal
connected across the Xl/ClK and X2 inputs.
If an external clock of the appropriate frequency
is available. it may be connected to Xl/ClK.
The clock serves as the basic timing reference
for the Baud Rate Generator (BRG). the counter/timer. and other internal circuits. A clock
signal wi thin the limits specified in the specifications section of this data sheet must always be
supplied to the DUART.
If an external is used instead of a crystal. Xl
should be driven using a configuration similar
to the one in Figure 5.
The baud rate generator operates from the oscillator or external clock input and is capable of
generating 18 commonly used data communications baud rates ranging from 50 to 38.4K
November 12. 1990
baud. Programming bit 0 of MRO to a "1" gives
additional baud rates of 57.6kB. 115.2kB and
230.4kB. These will be in the 16X mode. A
3.6864MHz crystal or external ciock must be
used to get the standard baud rate. The clock
outputs from the BRG are at 16X the actual
baud rate. The counter/timer can be used as a
timer to produce a 16X clock for any other baud
rate by counting down the crystal clock or an external clock. The four clock selectors allow the
independent selection. for each receiver and
transmitter. of any of these baud rates or external timing signal.
The Countermmer (C/I) can be programmed
to use one of several timing sources as its input.
The output of the CIT is available to the the
clock selectors and can also be programmed to
be output at OP3. In the counter mode. the contents of the CIT can be read by the CPU and
it can be stopped and started under program
control. In the timer mode, the CIT acts as a
programmable divider.
Communications
Channels A and B
Each communications channel of the
SC26C92 comprises a full-duplex asynchronous receiver/transmitter (UART). The operating frequency for each receiver and transmitter
can be selected independently from the baud
rate generator. the counter/timer. or from an external input.
SC26C92
The input port pulse detection circuitry uses a
38.4KHz sampling clock derived from one of
the baud rate generator taps. This results in a
sampling period of slightly more than 25J.ls (this
assumes that the clock input is 3.6864MHz).
The detection circuitry, in order to guarantee
that a true change in level has occurred. requires two successive samples at the new logic
level be observed. Asa consequence. the minimum duration olthe signal change is 25J.ls if the
transition occurs "coincident with the first sample pulse". The 50J.ls time refers to the situation
in which the change-of-state is "just missed"
and the first change-of-state is not detected until 25J.ls later.
Output Pan
This 8-bit output port is a general purpose output and is controlled by the OPR and the OPCR
registers. The OPR register is set and reset by
writing to the SOPR and ROPR addresses.
(See the description of the SOPR and ROPR
registers). The output pins will drive the inverse
data polarity of the OPR registers. The OPCR
register conditions these output to be controlled
by the OPR or by other signals in the chip.
OPERATION
Transmitter
The inputs to this unlatched 7-bit port can be
read by the CPU by performing a read operation at address H '0'. A High input results in a
logic 1 while a low input results in a logic O. D7
will always read as a logic 1. The pins of this
port can also serve as auxiliary inputs to certain portions fa the DUART logic.
The SC26C92 is conditioned to transmit data
when the transmitter is enabled through the
command register. The SC26C92 indicates to
the CPU that it is ready to accept a character by
setting the TxRDY bit in the status register.
This condition can be programmed to generate
an interrupt requestatOP60rOP7 and INTRN.
When the transmitter is initially enabled the
TxRDYand TxEMPTY bits will be set in the status register. When a character is loaded to the
transmitfifo the TxEMPTY bit will be reset. The
TxEMPTY will not set until: 1) the transmit fifo
is empty and the transmit shift register has finished transmitting the stop bitolthe lastcharacter written to the transmit fifo. or 2) the
transmitter is disabled and then re-enabled.
The TxRDY bit is set whenever the transmitter
is enabled and the TxFIFO is not full. Data is
transferred from the holding register to transmit
shift register when it is idle or has completed
transmission of the previous character. Characters cannot be loaded into the THR while the
transmitter is disabled.
Four change-of-state detectors are provided
which are associated with inputs IP3. IP2. IPl
and I PO. A High-to-low or low-to-High transition of these inputs. lasting longer than 25 50J.ls. will set the corresponding bit in the input
port change register. The bits are cleared
when the register is read by the CPU. Any
change-of-state can also be programmed to
generate an interrupt to the CPU.
The transmitter converts the parallel data from
the CPU to a serial bit stream on the TxD output
pin. It automatically sends a start bit followed
by the programmed number of data bits. an optional parity bit. and the programmed numberof
stop bits. The least significant bit is sent first.
Following the transmission of the stop bits. if a
new character is not available in the THR. the
TxD output remains High and the TxEMT bit in
The transmitter accepts parallel data from the
CPU. converts it to a serial bit stream. inserts
the appropriate start. stop. and optional parity
bits and outputs a composite serial stream of
data on the TxD output pin. The receiver accepts serial data on the RxD pin. converts this
serial input to parallel format. checks for start
bit. stop bit, parity bit (if any). or break condition
and sends an assembled character to the CPU
via the receive FIFO. Three status bits (Break,
Framing and Parity Errors) are also FIFOed
with each data character.
Input Pan
161
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
the Status Register (SR) will be set to t. Transmission resumes and the TxEMT bit is cleared
when the CPU loads a new character into the
THR.
If the transmitter is disabled, it continues operating until the character currendy being transmitted is completely sent out. The transmitter
can be forced to send a continuous low condition by issuing a send break command.
The transmitter can be reset through a software
command. If it is reset, operation ceases immediately and the transmitter must be enabled
through the command register before resuming
operation. If CTS operation is enable. the
CTSN input must be low in order for the
character to be transmitted. If it goes High in
the middle of a transmission, the character in
the shift register is transmitted and TxDA then
remains in the marking state until CTSN goes
low. The transmitter can also control the deactivation of the RTSN output. If programmed,
the RTSN output will be reset one bit time after
the character in the transmit shift register and
transmit holding register (if any) are completely
transmitted, if the transmitter has been disabled.
Receiver
The SC26C92 is conditioned to receive data
when enabled through the command register.
The receiver looks for a High-to-low
(mark-te-space) transition of the start bit on the
RxD input pin. If a transition is detected, the
state of the RxD pin is sampled each 16X clock
for 7-1/2 clocks (16X clock mode) or at the next
rising edge of the bit time clock (1 X clock
mode). If RxD is sampled High, the start bit is
invalid and the search for a valid start bit begins
again. If RxD is still low, a valid start bit is assumed and the receiver continues to sample
the input at one bit time intervals at the theoretical center of the bit, until the proper number of
data bits and parity bit (if any) have been assembled, and one stop bit has been detected.
The least significant bit is received first. The
data is then transferred to the Receive Holding
Register (RHR) and the RxRDY bit in the SR is
set to a 1. This condition can be programmed
to generate an interrupt at OP4 or OP5 and
INTRN. If the character length is less than 8
bits, the most significant unused bits in the RHR
are set to zero.
After the stop bit is detected, the receiver will
immediately look for the next start bit. However, if a non-zero character was received without
a stop bit (framing error) and RxD remains low
for one half of the bit period after the stop bit
was sampled, then the receiver operates as if
a new start bit transition had been detected at
thatpoint(one-halfbit time after the stop bitwas
sampled).
November 12, 1990
The parity error, framing error, and overrun error (if any) are strobed into the SR at the received character boundary, before the RxRDY
status bit is set. If a break condition is detected
(RxD is low for the entire character including
the stop bit), a character consisting of all zeros
will be loaded into the RHR and the received
break bit in the SR is set to 1. The RxD input
must return to a High condition for at least
one-half bit time before a search for the next
start bit begins.
The RHR consists of aFirst-ln-First-Out (FIFO)
stack with a capacity of eight characters. Data
is loaded from the receive shift register into the
topmost empty position of the FIFO. The
RxRDY bit in the status register is set whenever
one or more characters are available to be
read, and a FFUll status bit is set if all eight
stack positions are filled with data. Either of
these bits can be selected to cause an interrupt.
A read of the RHR outputs the data at the top
of the FIFO. After the read cycle, the data FIFO
and its associated status bits (see below) are
'popped' thus emptying a FIFO position for new
data.
In addition to the data word, three status bits
(parity error, framing error, and received break)
are also appended to each data character in the
FIFO (overrun is not). Status can be provided
in two ways, as programmed by the error mode
control bit in the mode register. In the 'character' mode, status is provided on a character-by-character basis; the status applies only
to the character at the top of the FIFO. In the
'block' mode, the status provided in the SR for
these three bits is the logical..QR of the status
for all characters coming to the top of the FIFO
since the last 'reset error' command was issued. In either mode reading the SR does not
affect the FIFO. The FIFO is 'popped' only
when the RHR is read. Therefore the status register should be read prior to reading the FIFO.
If the FIFO is full when a new character is received, that character is held in the receive shift
register until a FIFO position is available. If an
additional character is received while this state
exits, the contents of the FIFO are not affected;
the character previously in the shift register is
lost and the overrun error status bit (SR[4] will
be set-upon receipt of the start bit of the new
(overrunning) character).
The receiver can control the deactivation of
RTS. If programmed to operate in this mode,
the RTSN output will be negated when a valid
start bit. was received and the FIFO is full.
When a FiFO position becomes available, the
RTSN output will be re-asserted automatically.
This feature can be used to prevent an overrun,
in the receiver, by connecting the RTSN output
to the CTSN input of the transmitting device.
162
SC26C92
If the receiver is disabled, the FIFO characters
can be read. However, noadditionalcharacters
can be received until the receiver is enabled
again. If the receiver is reset, the FIFO and all
of the receiver status, and the .corresponding
output ports and interrupt are reset. No additional characters can be received until the receiver is enabled again.
Timeout Mode
In addition to the watch dog timer described in
the receiver section, the counterltimer may be
used for a similar function. Its programmability,
of course, allows much greater precision of
time out intervals.
The timeout mode uses the received data
stream to control the counter. Each time a received character is transferred from the shift
register to the RHR, the counter is restarted.
If a new character is not received before the
counter reaches zero count, the counter ready
bit is set, and an interrupt can be gElnerated.
This mode can be used to indicate when data
has been left in the Rx FIFO for more than the
programmed time limit. Otherwise, if the receiver has been programmed to interrupt the
CPU when the receive FIFO is full, and the
message ends before the FIFO is full, the CPU
may not know there is data left in the FI FO. The
CTU and CTl value would be programmed for
just over one character time, so that the CPU
would be interrupted as soon as it has stopped
receiving continuous data. This mode can also
be used to indicate when the serial line has
been marking for longer than the programmed
time limit. In this case, the CPU has read all of
the characters from the FIFO, but the last character received has started the count. If there is
no new data during the programmed time interval, the counter ready bit will get set, and an interrupt can be generated.
This mode is enabled by writing the appropriate
command to the command register. Writing an
'Ax' to CRA or CRB will invoke the timeout
mode for that channel. Writing a 'Cx'to CRA or
CRB will disable the timeout mode. The timeout mode should only be used by one channel
at once, since it uses the CIT. CTU and CTl
must be loaded with a value greater than the
normal receive character period. The timeout
mode disables the regular STARTISTOP
Counter commands and puts the CIT into
counter mode under the control of the received
data stream. Each time a received character is
transferred from the shift register to the RHR,
the CIT is stopped after 1 CIT clock, reloaded
with the value in CTU and CTl and ther restarted on the next CIT clock. If the CIT is allowed to end the count before a new character
has been received, the counter ready bit,
ISR[3], will be set. If IMR[3] is set, this will gen-
Philips Components-Signetics Data Communication Products
Preliminary Specification
Dual asynchronous receiver/transmitter (DUART)
erate an interrupt. Since receiving a character
afterthe CfT has timed out will clear thecounter
ready bit, ISR[3J, and the interrupt. Invoking the
'Set TImeout Mode On' command, CRx = 'Ax',
will also clear the counter ready bit and stop the
counter until the next character is received.
acter. The CPU compares the received address to its station address and enables the
receiver if it wishes to receive the subsequent
data characters. Upon receipt of another address character, the CPU may disable the receiver to initiate the process again.
Multidrop Mode
A transmitted character consists of a start bit,
the programmed number of data bits, and AddresslData (AID) bit, and the programmed
number of stop bits. The polarity of the
transmitted AID bit is selected by the CPU by
programming
bit
MR1A[2J/MR1B[2].
MR1 A[2]/MR1 B[2J = 0 transmits a zero in the
AID bit position, which identifies the corresponding data bits as data
while
MR1A[2]/MR1B[2] = 1 transmits a one in the
AID bit position, which identifies the corresponding data bits as an address. The CPU
The DUART is equipped with a wake up mode
for multidrop applications. This mode is selected by programming bits MR1A[4:3] or
MR1 B[4:3]to'11' for Channels A and B, respectively. In this mode of operation, a 'master' station transmits an address character followed by
data characters for the addressed 'slave' station. The slave stations, with receivers that are
normally disabled, examine the received data
stream and 'wakeup' the CPU (by setting
RxRDY) only upon receipt of an address char-
November 12, 1990
163
SC26C92
should program the mode register prior to load-'
ing the corresponding data bits into the THR.
In this mode, the receiver continuously looks at
the received data stream, whether it is enabled
or disabled. If disabled, it sets tlie RxRDY status bit and loads the character into the RHR
FIFO if the received AID bit is a one (address
tag), but discards the received character if the
received AID bit is a zero (data tag). If enabled,
all received characters are transferred to the
CPU via the RHR. In either case, the data bits
are loaded into the data FI FO while the AID bit
is loaded into the status FIFO position normally
used for parity error (SRA[5J or SRB[5]). Framing error, overrun error, and break detect operate normally whether or not the receive is
enabled.
Preliminary Specification
PhilipsComponents-Signetics Data Communication Products
Dual asynchronous receive.r/transmitter (DUART)
PROGRAMMING
The operation of the DUARTis programmed by
writing control words into the appropriate registers. Operational feedback is provided via status registers which can be read by the CPU.
The addressing of the registers is described in
Table 1.
The contents of certain control registers are initialized to zero on RESET. Care should be exercised if the contents of a register are changed
during operation, since certain changes may
cause operational problems.
For example, changing the number of bits per
character while the transmitter is active may
cause the transmission of an incorrect character. In general, the contents of the MR, the
CSR, and the OPCR should only be changed
while the receiver(s) and transmitter(s) are not
enabled, and certain changes to the ACR
should only be made while the CIT is stopped.
Each channel has 3 more registers (MRO, 1,2)
which control the basic configuration of the
channel. Access to these registers is controlled
by independent MR address pointers. These
pointers are set to 0 or 1 by MR control commands in the command register "Miscellaneous Commands". Each time the MR
registers are accessed the MR pointer incre-
SC26C92
ments, stopping at MR2. It remains pointing to
MR2 until set to 0 or 1 via the miscellaneous
commands of the command register. The pointer is set to 1 on reset for compatibility with the
SC26C92.
Mode, command, clock select, and status registers are duplicated for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions.
The resenied registers at addresses H'02' and
H'OA' should never be read during normal operation since they are reserved for internal
diagnostics.
Table 1, SC26C92 RegIster Addressing
A3
A2
At
AD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
READ (RON
= 0)
WRITE (WRN
Mode Register A (MROA, MR1A, MR2A)
Status Register A (SRA)
Reserved
Rx Holding Register A (RHRA)
Input Port Change Register (IPCR)
Interrupt Status Register (ISR)
Countermmer Upper (CTU)
Countermmer Lower (CTL)
Mode Register B (MROB, MRl B, MR2B)
Status Register B (SRB)
Reserved
Rx Holding Register B (RHRB)
Reserved
Input Port (IPR)
Start Counter Command
Stop Counter Command
= 0)
Mode Register A (MROA, MR1A, MR2A)
Clock Select Register A (CSRA)
Command Register A (CRA)
Tx Holding Register A (THRA)
Aux. Control Register (ACR)
Interrupt Mask Register (IMR)
CIT Upper Register (CRUR)
CIT Lower Register (CTLR)
Mode Register B (MROB, MRl B, MR2B)
Clock Select Register B (CSRB)
Command Register B (CRB)
Tx Holding Register B (THRB)
Reserved
Output Port Conf. Register (OPCR)
Set Output Port Bits Command
Reset Output Port Bits Command
NOTE:
.The three MR Registers are accessed via the MR Pointer and Commands Ixh and dxh. (Where 'x" represents receiver and transmitter enable!
disable control)
The following named registers are the same for Channels
A and B.
Mode Register
Status Register
Clock Select
Command Register
Receiver Fifo
Transmitter Fifo
November 12,1990
MRnA
SRA
CSRA
CRA
RHRA
THRA
MRnB
SRB
CSRB
CRB
RHRB
THRB
These registers control the functions which service both
Channels.
RIW
Input Port Change Register
Auxiliary Control Register
Interrupt Status Register
Interrupt Mask Register
Counter TImer Upper Value
Counter TImer Lower Value
Counter TImer Preset Upper
Counter TImer Preset Lower
Input Port Register
Output Configuration Register
Set Output Port Bits
Reset Output Port Bits
Ronly
Wonly
Wonly
Ronly
Wonly
164
IPCR
ACR
ISR
IMR
CTU
CTL
CRUR
CRLR
IPR
OPCR
SOPR
ROPR
R
W
R
W
R
R
W
W
R
W
W
W
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
Table 2,
MROA
MROB
SC26C92
Register Bit Formats
BIT7
BIT 6
RxWATCH
DOG
0= Disable
1 = Enable
RxINT(2)
BITS
BIT4
TxINT (1:0)
BIT 3
BIT2
BIT 1
BITO
DON'T
CARE
Set toO
TEST 1
TEST 2
Set to 0
SettoO
BAUD RATE
EXTEND
0= Normal
1 = Extend
NOTE:
MROB[3:0] are not implemented. When writing to MROB set them to o. A read of MROB[3:0] returns 1111.
BIT 7
BIT6
BITS
RxCONTROLS
RTS
Rx INT
BIT 1
ERROR
MODE
0= No
1 = Yes
0= RxRDY
1 = FFULL
0= Char
1 = Block
MR1A
MR1B
BIT7
BIT 6
CHANNEL MODE
00 = Normal
01 = Auto-Echo
10 = Local loop
11 = Remote loop
MR2A
MR2B
BIT4
BIT3
BIT2
PARITY MODE
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multidrop Mode
BIT 5
BIT4
Tx CONTROLS
RTS
CTS
ENABLETx
0= No
1 = Yes
0= No
1 = Yes
BITO
BITl
PARITY
TYPE
BITS PER
CHARACTER
0= Even
1 = Odd
00 =5
01 =6
10 = 7
11 = 8
BIT 3
BIT 1
BIT 2
BIT 0
STOP BIT LENGTH'
4 = 0.813
5 = 0.875
6 = 0.938
7 = 1.000
0=0.563
1 = 0.625
2 = 0.688
3 = 0.750
8 = 1.563
9 = 1.625
A = 1.688
B= 1.750
C = 1.813
D = 1.875
E=1.938
F = 2.000
NOTE:
'Add 0.5 to values shown for 0 - 7 if channel is programmed for 5 bits/char.
BIT7
BIT 6
BIT4
BIT3
BIT2
BITO
BITl
TRANSMITTER CLOCK SELECT
See Text
See Text
CSRA
CSRB
BIT7
BITS
RECEIVER CLOCK SELECT
BIT3
BIT2
BIT 1
BITO
MISCELLANEOUS COMMANDS
BIT6
DISABLETx
ENABLETx
DISABLE Rx
ENABLE Rx
See Text
0= No
1 = Yes
0= No
1 = Yes
·0 = No
1 = Yes
0= No
1 = Yes
CRA
CRB
BITS
BIT4
BIT7
BIT 6
BITS
BIT4
BIT3
BIT2
BITl
BITO
RECEIVED
BREAK'
FRAMING
ERROR'
PARITY
ERROR'
OVERRUN
ERROR
TxEMT
TxRDY
FFULL
RxRDY
0= No
1 = Yes
0= No
1 = Yes
O=No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
SRA
SRB
NOTE:
, These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from
the top of the FIFO together with bits (4:0). These bits are cleared by a "reset error status" command. In character mode they are discarded
when the corresponding data character is read from the FIFO.
OPCR
BIT7
BIT6
BIT 5
BIT4
OP7
OP6
OPS
OP4
0=OPR[7]
1 = TxRDYB
o =OPR[6]
0= OPR[5]
1 = RxRDY/
FFULLB
0= OPR[4]
1 = RxRDY/
FFULLA
November 12, 1990
1 = TxRDYA
165
BIT3
BIT2
OP3
00 = OPR[3]
01 = CIT OUTPUT
10 = TxCB(1X)
11 = RxCB(1X)
BITO
BIT 1
OP2
11 =OPR[2]
01 = TxCA(16X)
10 = TxCA(1X)
11 = RxCA(1X)
Preliminary SpecificatiOn
Philips C<;>mponents-Signetics Data Communication Products
SC26C92
Dual asynchronous receiver/transmitter (DUART)
Table 2.
Register Bit Formats (Continued)
BIT7
SOPR
0= No Change
1 = Set
ROPR
0= No Change
1 = Reset
BIT7
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
BIT1
BIT 0
BIT 6
BITS
BIT 4
BIT3
BIT 2
BIT 1
BITO
BIT6
BITS
BRGSET
SELECT
COUNTERrnMER
MODE AND SOURCE
o = set 1
See Table 4
ACR
1 = set 2
IPCR
BIT 4
BIT3
BIT2
BIT 1
BITO
DELTA
IP31NT
DELTA
IP21NT
DELTA
IP liNT
DELTA
IPOINT
0= Off
1 =On
0=011
1 =On
0=011
1 =On
0=011
1 =On
BIT3
BIT2
BITI
BITO
BIT7
BIT6
BITS
BIT4
DELTA
IP3
DELTA
IP 2
DELTA
IP 1
DELTA
IP 0
IP3
IP2
IP 1
IP 0
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= Low
1 = High
0= Low.
1 = High
0= Low
1 = High
0= Low
1 = High
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
BIT 1
BITO
INPUT
PORT
CHANGE
DELTA
BREAK B
RxRDYI
FFULLB
TxRDYB
COUNTER
READY
DELTA
BREAK A
RxRDYI
FFULLA
TxRDYA
0- No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
O=No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
ISR
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
BIT1
BITO
IN. PORT
CHANGE.
INT
DELTA
BREAK B
INT
RxRDYI
FFULLB
INT
TxRDYB
INT
COUNTER
READY
INT
DELTA
BREAK A
INT
RxRDYI
FFULLA
INT
TxRDYA
INT
0=011
1 =On
0=011
1 =On
0=011
1 =On
0=011
1 =On
0=011
1 =On
IMR
0=011
1 =On
0=011
1 =On
0=011
1 =On
BIT7
BIT6
BITS
BIT 4
BIT 3
BIT2
BIT 1
BITO
Crr[l5]
Crr[14]
C/T[13]
C/T[12]
Crr[11]
Crr[10]
Crr19]
CIT[S]
CTUR
BIT 7
BIT6
BITS
BIT4
BIT3
BIT2
BIT 1
BITO
Crr(7]
Crr(6]
Crr[S]
Crr(4]
Crr(3]
Crr(2]
Crr[l]
C/T(O]
CTLR
November 12,1990
166
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (OUART)
REGISTER DESCRIPTIONS
Mode Registers
MRO is accessed by setting the MR pointer to
a via the command register command D.
MROA
MRO[7] - This bit controls the receiver watch
dog timer. = disable, 1 = able. When enabled,
the watch dog timer will generate a receiver interrupt if the receiver FIFO has not been accessed within 64 bit times of the receiver IX
clock. This is used to alert the control processor
that data is in the RHR that has not been read.
This situation may occur when the last part of
a message is not large enough to generate an
interrupt.
a
URO[S] - Bit 2 of receiver FI FO interrupt level.
This bit along with Bit6 of MRI sets the fill level
of the 8 byte FIFO that generates the receiver
interrupt.
MRO[6]
MR1[S]
a
a
a
1
a
1
1
1
Interrupt Condition
1 or more bytes in FI FO
(Rx RDY)
3 or more bytes in FIFO
6 or more bytes in FIFO
8 or more bytes in FIFO
(Rx FULL)
MRO[S:4]- Tx interrupt fill level.
MRO[S]
MRO[4]
a
a
a
1
a
1
1
1
Interrupt Condition
8 bytes empty
(Tx EMPTY)
4 or more bytes empty
6 or more bytes empty
1 or more bytes empty
(TxRDY)
MRO[3]- Not used. Should be set to O.
MRO[2:1]- Test 1 and Test 2. Used for factory
test. Set to
a
a
MRO[O]- Baud rate extend. = Normal baud
rates. 1 = Extend baud rate. 57.6kB, 115.2kB,
230.4kB.
Note: MRO[3:0] are not used in channel B. They
should be set to O.
MR1A
MR1A is accessed when the Channel A MR
pointer points to MR 1. The pointer is sello MR 1
by RESET or by a 'set pointer' command
applied via CR command 1. After reading or
writing MR1A, the pointer will point to MR2A.
MR1A[7] - Channel A Receiver
Request-to-Send Control
This bit controls the deactivation of the RTSAN
output (OPO) by the receiver. This output is normally asserted by selling OPR[O] and negated
by resetting OPR[O]. MR1A[7] = 1 causes
RTSAN to be negated upon receipt of a valid
November 12, 1990
start bit if the Channel A FIFO is full. However,
OPR[O] is notresetandRTSANwili be asserted
again when an empty FIFO position is available. This feature can be used for flow control
to prevent overrun in the receiver by using the
RTSAN output signal to control the CTSN input
of the transmitting device.
MR1[6]- Bitl of the receiver interrupt control.
See description under MRO[6].
MR1A[S]-Channel A
Error Mode Select
This bit select the operating mode of the three
FIFOed status bits (FE, PE, received break) for
Channel A. In the 'character' mode, status is
provided on a character-by-character basis;
the status applies only to the character at the
top of the FIFO. In the 'block' mode, the status
provided in the SR for these bits is the accumulation (logical-OR) of the status for all characters coming to the top of the FIFO since the last
'reset error' command for Channel A was issu9d.
MR1A[4:31- Channel A Parity Mode Select
If 'with parity'or'force parity' is selected a parity
bit is added to the transmitted character and the
receiver performs a parity check on incoming
data MR1A[4:3] = 11 selectsChannelAtooperate in the special multidrop mode described in
the Operation section.
MRl A[2] - Channel A Parity Type Select
This bit selects the parity type (odd or even) if
the 'with parity' mode is programmed by
MRI A[4:3], and the polarity of the forced parity
bit if the 'force parity' mode is programmed. It
has no effect if the 'no parity' mode is programmed. In the special multidrop mode it selects the polarity of the AID bit.
MR1A[1 :0]- Channel A Bits Per Character
Select
This field selects the number of data bits per
character to be transmitted and received. The
character length does not include the start, parity, and stop bits.
MR2A - Channel A Mode
Register 2
MR2A is accessed when the Channel A MR
pointer points to MR2, which occurs after any
access to MR 1A. Accesses to MR2A do not
change the pointer.
MR2A[7:6]- Channel A Mode
Select
Each channel of the DUART can operate in one
of four modes. MR2A[7:6] = 00 is the normal
mode, with the transmitter and receiver operating independently. MR2A[7:6] = 01 places the
channel in the automatic echo mode, which automatically retransmits the received data. The
167
SC26C92
following conditions are true while in automatic
echo mode:
1. Received data is reclocked and retransmitted on the TxDA output.
2. The receive clock is used for the transmitter.
3. The receiver must be enabled, but the
transmitter need not be enabled.
4. The Channel A TxRDY and TxEMT status
bits are inactive.
5. The received parity is checked, but is not
regenerated for transmission, i.e. transmitted parity bit is as received.
6. Character framing is checked, but the
stop bits are retransmitted as received.
7. A received break is echoed as received
until the next valid start bit is detected.
8. CPU to receiver communication continues
normally, but the CPU to transmitter link is
disabled.
Two diagnostic modes can also be configured.
MR2A[7:6] = 10 selects localloopback mode.
In this mode:
1. The transmitter output is internally connected tO,the receiver input.
2. The transmit clock is used for the receiver.
3. The TxDA output is held High.
4. The RxDA input is ignored.
5. The transmitter must be enabled, but the
receiver need not be enabled.
6. CPU to transmitter and receiver communications continue normally.
The second diagnostic mode is the remoie
loopback mode, selected by MR2A[7:6] = 11.
In this mode:
1. Received data is reclocked and retransmitted on the TxDA output.
2. The receive clock is used for the transmitter.
3. Received data is not sent to the local
CPU, and the error status conditions are
inactive.
4. The received parity is not checked and is
not regenerated for transmission, i.e.,
transmitted parity is as received.
5. The receiver must be enabled.
6. Character framing is not checked, and the
stop bits are retransmitted as received.
7. A received break is echoed as received
until the next valid start bit is detected.
Preliminary Specification
Philips Compon!lnts-Signetics Data Communication Products
SC26C92
Oualasynchronous receiver/transmitter (OUART)
The user must exercise care when switching
into and out of the various modes.· The selected mode will be activated immediately upon
mode selection, even if this occurs in the middle
of a received or transmitted· character. Likewise, if a mode is deselected the device will
switch out of the mode immediately. An exception to this is switching out of autoecho or remote loopback modes: if the de-selection
occurs just after the receiver has sampled the
stop bit (indicated in autoecho by assertion of
RxRDY), and the transmitter is enabled, the
transmitter will remain in autoecho mode until
the entire stop has been re-transmitted.
MR2A[5)- Channel A Transmitter
Request-to-Send Control
This bit controls the deactivation of the RTSAN
output (OPO) by the transmitter. This output is
normally asserted by setting OPR[O] and negated by resetting OPR[O]. MR2A[S] = 1
caused OPR[O] to be reset automatically one
bit time after the characters in the Channel A
transmit shift register and in the THR: if any, are
completely transmitted including the programmed number of stop bits, if the transmitter
is not enabled. This feature can be used to automatically terminate the transmission of a
message as follows:
1. Program auto-reset mode: MR2A[S] = 1.
MR2A[4)- Channel A Clear-to-Send
Control
If this bit is 0, CTSAN has no effect on the transmitt.er. If this bit is a I, the transmitter .checks
the state of CTSAN (IPO) each time it is ready
to send a character. If IPO is asserted (Low),
the character is transmitted. If it is negated
(High), the TxDA output remains in the marking
state and the transmission is delayed until
CTSAN goes low. Changes in CTSAN while a
character is being transmitted do not affect the
transmission of that character..
MR2A[3:0)- Channel A Stop Bit Length
Select
This field programs the length of the stop bit appended to the transmitted character. Stop bit
lengths of9116 to 1 and 1-9116 to 2 bits, in increments of 1116 bit, can be programmed for character lengths of 6, 7, and 8 bits. For a character
lengths of S bits, 1-1116 to 2 stop bits can be programmed in increments of 1116 bit. In all cases,
the receiver only checks for a 'mark' condition
althe center of the first stop bit position (one bit
time after the last data bit, or after the parity bit
is enabled).
If an external 1X clock is used for the transmitter, MR2A[3] = 0 selects one stop bit and
MR2A[3] = 1 selects two stop bits to be
transmitted.
2. Enable transmitter.
3. Asset RTSAN: OPR[O] = 1.
4. Send message.
S. Disable transmitter after the last character
is loaded into the Channel A THR.
6. The last character will be transmitted and
OPR[O] will be reset one bit time after the
last stop bit, causing RTSAN to be negated.
MRDB - Channel B Mode
Register 1
MROB is accessed when the Channel B MR
pointer points to MRI. The pointer is selto MRO
by RESET or by a 'set pointer' command
applied via CRB. After reading or writing
MROB, the pointer will point to MRI B.
The bit definitions for this register are identical
to MROA, except that all control actions apply
to the Channel B receiver and transmitter and
the corresponding inputs and outputs.
MR1 B - Channel B Mode
Register 1
MRI B is' accessed when the Channel B MR
pointer points to MR 1. The pointeris setto MRI
by RESET or by a 'set pointer' command
applied via CRB. After reading or writing
MRI B, the pointer will point to MR2B.
The bit definitions for this register are identical
to MR1A, except that all control actions apply
to the Channel B receiver and transmitter and
the corresponding inputs and outputs.
MR2B - Channel B Mode
Register 2
MR2B is accessed when the Channel B MR
pointer points to MR2, which occurs after any
access to MRI B. Accesses to MR2B do not
change the pointer.
The bi't definitions for mode register are identical to the bit definitions for MR2A, except that
all control actions apply to the Channel B receiver and transmitter and the corresponding
inputs and outputs.
CSRA - Channel A Clock Select
Register
CSRA[7:4)- Channel A Receiver Clock
Select
This field selects the baud rate clock for the
Channel A transmitter. The field definition is
shown in Table 3.
CSRA[3:0)- Channel A Transmitter Clock
Select
This field selects the baud rate clock for the
Channel A transmitter. The field definition is as
shown in Table 3, except as follows:
CSRA[3:0]
1110
1111
ACR[7]
=0
IP3-16X
IP3-1X
ACR[7]
=1
IP3-16X
IP3-1X
The transmitter clock is always a 16X clock exceptlor CSR[3:0] = 1111.
November 12,1990
168
Philips Components-Signetics Data Communication Products
Preliminary Specification
Dual asynchronous receiver/transmitter (DUART)
Table 3.
SC26C92
Baud Rate
MRO[O]
CSRA[7:4]
ACR[7]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
=0
50
110
134.5
200
300
600
1,200
1,050
2,400
4,BOO
7,200
9,600
3B.4K
Timer
IP4-16X
IP4-1X
=0
MRO[O]
ACR[7]
=1
ACR[7]
75
110
134.5
150
300
600
1,200
2,000
2,400
4 ,BOO
I.BOO
9,600
19.2K
Timer
IP4-16X
IP4-1X
=0
50
110
134.5
200
1800
3600
7200
1,050
14.4K
2B.BK
7,200
S7.6K
23O.4K
Timer
IP4-16X
IP4-1X
=1
ACR[7]
=1
450
110
230.4K
900
1BOO
3600
7,200
2,000
14.4K
2B.BK
1,BOO
S7.6K
lIS.2K
Timer
IP4-16X
IP4-1X
NOTE: The receiver clock IS always a 16X clock except for CSRA[7:4] = 11".
CSRB - Channel B Clock Select
Register
CSRB[7:4] - Channel B Receiver Cfock
Select
This field selects the baud rate cloclk for the
Channel B transmitter. The field definition is as
shown in Table 3, except as follows:
CSRB[7:4]
1110
1111
ACR[7]
=0
IP6-16X
IP6-1X
ACR[7]
=1
IP6-16X
IP6-1X
The transmitter clOCk is always a 16X clock except for CSRB[7:4] = 1111.
CSRB[3:0)- Channel B Transmitter Clock
Selecl
This field selects the baud rate clock for the
Channel B transmitter. The field definition is as
shown in Table 3, except as follows:
CSRB[3:4)
1110
1111
ACR[7]
=0
IPS-16X
IPS-IX
ACR[7]
=1
IP5-16X
IP5-1X
The transmitter clock is always a 16X clock exceptfar CSRB[3:0] = 1111.
CRA - Channel A Command
Register
CRA is a register used to supply commands to
Channel A. Multiple commands can be specified in a single write to CRA as long as the cammands are non-conflicting, e.g., the 'enable
transmitter' and 'reset transmitter' commands
cannot be specified in a single command word.
CRA[7:4)- Miscelfaneous Commands
The encoded value of this field may be used to
specify a single command as follows:
CRA[6:4]
COMMAND
0000 No command.
November 12, 1990
0001 Reset MR pointer. Causes the Channel
A MR pointer to point 10 MR 1.
0010 Reset receiver. Resets the Channel A
receiver as if a hardware reset had been
applied. The receiver is disabled and
the FIFO is flushed.
0011 Reset transmitter. Re'sets the Channel
A transmitter as if a hardware reset had
been applied.
0100 Reset error status. Clears Ihe Channel
A Received Break, Parity Error, and
Overrun Error bits in the status register
(SRA[7:4]). Used in character .mode· to
clear DE status (although RB, PE and
FE bits will also be cleared) and in block
mode to clear all error status after a
block of data has been received.
0101 Reset Channel A break change interrupt. Causes the Channel A break de-'
tect change' bit in the interrupt status
register (ISR[2]) to be cleared to zero.
0110 Start break. Forces the TxDA output
Low (spacing). If the transmitter is
empty the startofthe break condition will
be delayed up to two bit times. If the
transmitter is active the break begins
when transmission of the character is
completed. If a character is in the THR, .
the start of the break will be delayed until
that character, or any other loaded
subsequently are transmitted.
The
transmitter must be enabled for this
command to be accepted.
0111 Stop break. The TxDA line will go High
(marking) within two bit times. TxDA will
remain High for one bit time before the
next character, if any, is transmitted.
1000 Assert RTSN. Causes the RTSN output
to be asserted (Low).
1001 Negate RTSN. Causes the RTSN output to be negated (High).
1010 Set Timeout Mode On. The receiver in
this channel will restart the CfT as each
receive character is transferred from the
shift register to the RH R. The CIT is
placed in the counter mode, the STARTI
169
1011
1100
1101
1110
1111
STOP counter commands are disabled,
the counter is stopped, and the Counter
Ready Bit, ISR[3], is reset.
Not used.
Disable Timeout Mode. This command
returns control of the CIT to the regular
STARTISTOP counter commands. It
does not stop the counter, or clear any
pending interrupts. After disabling the
timeout mode, a 'Stop Counter' command should be issued
Set MR pointer to "0".
Power Down Mode On. In this mode,
the DUART oscillator is stopped and all
functions requiring this clock are suspended. The execution of commands
other than disable power down mode
(1111) requires aXIICLK. While in the
power down mode, do not issue any
commands to the CR except the disable
power down mode command. The contents of all registers will be saved while
in this mode. It is recommended that
the transmitter and receiver be disabled
prior to placing the DUART into power
down mode. This command is in CRA
only.
Disable Power Down Mode. This commandrestarts theoscillator. Afterinvoking this command, wait for the oscillator
to start up before writing further commands to the CR. This command is in
CRAonly.
CRA[3)- Disable Channel A
Transmitter
This command terminates transmitter operation and reset the TxDRY and TxEMT status
bits. However, if a character is being transmitted or if a character is in the THR when the
transmitter is disabled, the transmission of the
character(s) is completed before assuming the
inactive state.
Pl\ili~~\lfTIponents-Signetics Data Communication Products
Preliminary Specification
Dual asynchronous receiver/transmitter (OUART)
CRA{2] ~ Enable Channel A
Transmitter
EAablesoperation of the Channel A transmitter.
The TxRDY status bit will be asserted.
CRAI1]- Disable Channel A Receiver
This command terminates operation of the receiver immediately - a character being receivedwill be.108t. The command has no effect
on the receiver status bits or any other control
registers. If the special multidrop mode is programmed, the receiver operates eve~ if it is disabled. See Operation section.
CRAIO) _ Enable Channel A Receiver
Enables operation of the Channel A receiver.
If not in the special wakeup mode, this ·also
forces the receiver into the search for start-bit
state.
SRAIS) - Channel A Parity Error
This bit is set when the 'With parity' or 'Iorce Parity' mode is programmed and the corresponding character in the FIFO w~s received with
incorrect parity.
In the special multidrop mode the parity error bit
stores the receive AID bit.
SRA(4) - Channef A Overrun Error
This bit, when set, indicates that one or more
characters in the rece.ived data stream have
been lost. It is set upon receipt of a new character when the FIFO is lull and a character is already in the receive shift register waiting for an
empty FIFO position. When this occurs, the
character in the receive shift register (and its
break detect, pariiy error and Iraming error status, il any) is lost.
CRB ..:. Channel B Command
Register
This bit is cleared by a 'reset error status' command.
CRB is a register used to supply commands to
Channel B. Multiple commands can be specified in a single write to CRB as long asthe commands are non-conflicting, e.g., the 'enable
transmitter' and 'reset transmitter' commands
cannotb.e specified in a single command word.
SRA(3) - Channel A Transmitter Empty
(TxEMTA)
This bit will be set when the Channel A transmitter underruns; I.e., both the Transmit Holding
Register (THR) and the transmit shift register
are empty. It is set alter transmission of the last
stop bit 01 a character il no character is in the
THR awaiting transmission. It is resetwhen the
THR is loaded by the CPU orwhen the transmitter is disabled or reset.
The bit definitions for this register are identical
to the bit definitions for CRA, with the exception
of comamnds "Ex" and "Fx" which are used lor
power downmode. These two commands are
not used in CRB. All other control actions that
apply to CRA also apply to CRB.
SRA - Channel A Status
Register
SRA(7) - Channel A Received Break
This bit indicates that an all zero character of
the programmed length has been received
without a stop bit. Only a single FIFO position
is occupied when a break is received: lurther
entries to the FIFO are inhibited until the RxDA
linll to the marking state for at least one-hall a
bit time (two successive edges of the internal or
external 1X clock).
SRA(2) - Channel A Transmitter Ready
(TxRDYA)
This bit, when set, indicates that the transmit
FIFO is not full and ready to be loaded with
another character. This bit is cleared when the
transmit FIFO is loaded by the CPU and there
are (after this load) no more empty locations in
the FIFO. It is set when a character is transferred to the transmit shift register. TxRDYA is
reset when the transmitter is disabled and is set
when the transmitter is first enabled, VIZ., characters loaded into the transmit FIFO while the
transmitteris disabled or reset will not be transmitted. This bit has different meaning from
ISRO.O
.
SC26C92
ferred from the receive shift register to the FIFO
and reset when the CPU reads the receive
FIFO, only if (after this read) there are no more
characters in the FIFO.
SRB - Channel B Status
Register
The bit definitions for this register are identical
to the bit definitions lor SRA, except that all status applies to the Channel B receiver and transmitter and the corresponding inputs and
outputs.
OPCR - Output Port
Configuration Register
OPCR(7) - OP7 Output Select
This bit programs the OP7 output to provide
one of the following:
- The complement ot OPR[7].
- The Channel B transmitter interrupt output
.
which is the complement of TxRDYB.
When in this mode OP7 acts as an opendrain output. Note that this output is not
masked by the contents 01 the IMR.
OPCR[S) - OPS Output Select
This bit programs the OP6 output to provide
one 01 the following:
- The complement 01 OPRIS],
- The Channel A transmitter interrupt output
which is the complement ot TxRDYA.
When in this mode OP6 acts as an opendrain output. Note that this output is not
masked by the contents of the IMR.
OPCR[5) - OPS Output Select
This bit programs the OPS output to provide
one of the following:
- The complement 01 OPRIS[.
- The Channel B transmitter interrupt output
which is the complement 01ISRI5]. When
in this mode OP5 acts as an open-drain
output. Note that this output is not masked
by the contents of the IMR.
OPCR(4) - OP4 Output Select
This lield programs the OP4 output to provide
SRA(1) - Channel A FIFO Full (FFULLA)
one of the following:
This. bit is set when a character is transferred
- The complement of OPR[4].
Irom the receive shift register to the receive
. - The Channel A receiver interrupt output
FIFO and the transfer causes the FIFO to bewhich is the complement ollSRll). When
The break detect circuitry can detect breaks
come full, i.e., all eightFIFOpositionsareoccuin this mode OP4 acts as an open-drain
that originate in the middle 01 a received charpied. It is reset when the CPU reads the receive
output. Note that this output is not
acter. "However, if a blllak begins'in the middle
FIFO .. If a charaClerk;. waiting in the receive
masked by the contents of the I MR.
01 a character, it must persist until at least the . shift register because the FIFO is lull, FFULLA
end of the next character time in order lor it to
will not be reset when the CPU reads the reOPCR[3:2) - OP3 Output Select
be detected.
ceive AFO. This bit has different meaning from
This bit programs the OP3 output to provide
ISAl when ~Rl 6 is programmed to;1'I'.
'One of the following:
SRA(6) - Channel A Framing Error
- The complement 01 OPR(3).
This bit, when set, indicates that a stop bit was
SRAIO) - Channel A Receiver Ready
- The counter/timer output, in which case
not detected when the corresponding data (RxRDYA)
OP3 acts as an open-drain output. In the
character in the FI FO was receiVed. The stop
This bit indicates that a character has been retimer mode, this output is a square wave at
bit check is made in the middle of the lirst stop
ceived and is waiting in the FIFO to be read by
the programmed frequency.- In the counter
bit position.
the CPU. It is set when the character is trans-
When this bit is set, the Channel A 'change in
break' bit in the ISR (ISRI2]) is set. ISR(2) is
also set when the end oHhe break condition, as
delined above, is detected.
November 12, 1990
170
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
mode, the output remains High until terminal count is reached, at which time it goes
low. The output returns to the High state
when the counter is stopped by a stop
counter command. Note that this output is
not masked by the contents of the IMR.
- The 1X clock for the Channel B transmitter,
which is the clock that shifts the transmitted data. If data is not being transmitted, a free running 1X clock is output.
- The 1X clock for the Channel B receiver,
which is the clock that samples the received data. If data is not being received,
a free running IX clock is output.
OPCR[1 :0]- OP2 Output Select
This field programs the OP2 output to provide
one of the following:
- The complement of OPR[2].
- The 16X clock for the Channel A transmitter. This is the clock selected by
CSRA[3:0j, and will be a 1X clock if
CSRA[3:0j = 1111.
- The 1X clock for the Channel A transmitter,
which is the clock that shifts the transmitted data. If data is not being transmitted, a free running 1X clock is output.
- The 1X clock for the Channel A receiver,
which is the clock that samples the received data. If data is not being received,
a free running 1X clock is output.
SOPR - Set the Output Port Bits
(OPR)
SOPR[7:0j - Ones in the byte written to this
register will cause the corresponding bit positions in the OPR to set to 1. Zeros have no
effect.
ROPR - Reset Output Port Bits
(OPR)
Table 4.
Bit Rate Generator
Characteristics
Crystal or Clock =
3.6864MHz
NORMAL
RATE
(BAUD)
ACTUAL
16XCLOCK
(kHz)
50
75
110
134.5
150
200
300
600
1050
1200
1BOO
2000
2400
4800
7200
9600
19.2K
3B.4K
0.8
1.2
1.759
2.153
2.4
3.2
4.8
9.6
16.756
19.2
28.8
32.056
38.4
76.8
115.2
153.6
307.2
614.4
ACR[6:4j- CounterlTlmer Mode And
Clock Source Select
This field selects the operating mode of the
counterltimer and its clock source as shown in
Table 5.
Table 5.
ACR 6:4 Field
Definition
ACR
6:4
MODE
CLOCK SOURCE
000
001
Counter
Counter
External (IP2)
TxCA - 1X clock of
Channel A transmitter
TxCB - 1X clock of
Channel B transmitter
Crystal or external clock
(Xl/ClK) divided by 16
External (IP2)
External (I P2) divided
by 16
Crystal or external clock
(Xl/ClK)
Crystal or external clock
(XlIClK) divided by 16
010
Counter
011
Counter
100
101
Timer
Timer
ACR - Auxiliary Control
Register
110
Timer
111
Timer
Set 1:
Set 2:
50, 110, 134.5,200,300,600,
1.05K, 1.2K, 2.4K, 4.8K, 7.2K,
9.6K, and 3B.4K baud.
75,110,134.5,150,300,600,
1.2K, 1.8K, 2.0K, 2.4K, 4.8K, 9.6K,
and 19.2K baud.
The selected set of rates is available for use by
the Channel A and B receivers and transmitters
as described in CSRA and CSRB. Baud rate
generator characteristics are given in Table 4.
November 12, 1990
0
0
-0.069
0.059
0
0
0
0
-0.260
0
0
0.175
0
0
0
0
0
0
NOTE:
Duty cycle of 16X clock is 50% ± 1%.
ROPR[7:0j - Ones in the byte written to the
ROPR will cause the corresponding bit positions in the OPR to set to O. Zeros have no
effect.
ACR[7] - Baud Rate Generator Set Select
This bit selects one of two sets of baud rates to
be generated by the BRG:
ERROR(%)
ACR[3:0]-IP3, IP2, IP1,IPO
Change·ol·State Interrupt Enable
This field selects which bits of the input port
change register(IPCR) cause the input change
bit in the interrupt status register (ISR[7]) to be
set. If a bit is in the 'on' state the setting of the
corresponding bit in the IPCR will also result in
the setting of ISR[7], which results in the generation of an interrupt output if IMR[7] = 1. If a bit
171
SC26C92
is in the 'off' state, the setting of that bit in the
IPCR has no effect on ISR[7].
IPCR - Input Port Change
Register
IPCR[7:4j-IP3,IP2, IP1, IPO
Change·ol-State
These bits are set when a change-of-state, as
defined in the input port section of this data
sheet, occurs at the respective input pins. They
are cleared when the IPCR is read by the CPU.
A read of the IPCRalsoclears ISR[7j, the input
change bit in the interrupt status register. The
setting of these bits can be programmed to
generate an interrupt to the CPU.
IPCR[3:0j-IP3,IP2,IP1,IPO
Change-ol-State
These bits provide the current state of the respective inputs. The information is unlatched
and reflects the state of the input pins at the
time the IPCR is read.
ISR - Interrupt Status Register
This register provides the status of all potential
interrupt sources. The contents of this register
are masked by the Interrupt Mask Register
(IMR). If a bit in the ISR is a '1' and the corresponding bit in the IMR is also a '1', the INTRN
output will be asserted (low). If the corresponding bit in the IMR is a zero, the state of
the bit in the ISR has no effect on the INTRN
output. Note that the IMR does not mask the
reading of the ISR - the true status will be provided regardless of the contents of the IMR.
The contents of this register are initialized to
00'6 when the DUART is reset.
ISR[7] -Input Port Change Status
This bit is a '1' when a change-of-state has occurred at the IPO, IP 1, IP2, or IP3 inputs and
that event has been selected to cause an interrupt by the programming of ACR[3:0j. The bit
is cleared when the CPU reads the IPCR.
ISR[6]- Channel B Change In Break
This bit, when set, indicates that the Channel B
receiver has detected the beginning or the end
of a received break. It is reset when the CPU
issues a Channel B 'reset break change interrupt' command.
ISR[5j- Rx ROY/FULL
This bit indicates that the channel B receiver is
interrupting according to the fill level programmed by the MRO and MR1 registers. This
bit has a different meaning than the receiver
readylfull bit in the status register.
ISR[4j- Tx ROY/FULL
This bit indicates that the channel B transmitter
is interrupting according to the interrupt level
programmed in the MRO[5:4] bits. This bit has
Philips Components-Signetics Data Communication Products
Preliminary Specification
Dual asynchronous receiver/transmitter (DUART)
a different meaning than the Tx RDY bit in the
status register.
. ISR[3) - Counter Ready.
In the counter mode, this bit is set when the
counter reaches terminal count and is reset
when the counter is stopped by a stop counter
command.
In the timer mode, this bit is set once each cycle
of the generated square wave (every other time
thatthe counterltimerreaches zero count). The
bit is reset by a stop counter command. The
command, however, does not stop the counterl
timer.
ISR[2) - Channet A Change in Break
This bit, when set, indicates that the Channel A
receiver has detected the beginning or the end
of a received break. It is reset when the CPU
issues a Channel A 'reset break change interrupt' command.
ISR[1) - Rx ROYIFULL
This bit indicates that the channel A receiver is
interrupting according to the fill level programmed by the MRO and MR1 registers. This
bit has a different meaning than the receiver
ready/lull bit in the status register.
ISR[O) - Tx ROY/FULL
This bit indicates that the channel A transmitter
is interrupting according to the interrupt level
programmed in the MRO[S:4] bits. This bit has
a different meaning than the Tx RDY bit in the
status register.
bit in the ISR is a '1' and the corresponding bit
in the IMR is also a '1' the INTRN output will be
asserted. Ifthecorresponding bitin the IMRis
a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR
does not mask the programmable interrupt outputs OP3-0P7 or the reading of the ISR.
CTUR and CTLR -' CounterlTimer
Registers
The CTUR and CTLR hold the eight MSBs and
eight LSBs, respectively, of the value to be
used by the counterltimer in either the counter
or timer modes of operation. The minimum value which may be loaded into the CTURlCTLR
registers is H'0002'. Note that these registers
are write-only and cannot be read by the CPU.
In the timer (programmable divider) mode, the
CIT generates a square wave with a period of
twice the value (in clock periods) of the CTUR
and CTLR. I! the value in CTUR and CTLR is
changed, the c·urrent half-period will not be affected, but subsequent hal! periods will be. The
CIT will not be running until it receives an initial
'Start Counter' command (read at address
A3-AO = 1110). After this, while in timer mode,
the CIT will run continuously. Receipt of a start
counter command (read with A3-AO = 1110)
causes the counter to terminate the current timing cyde and to begin a new cycle using the values in CTUR and CTLR.
The counterready status bit(ISR[3]) is set once
each cycle of the square wave. The bit is reset
by a stop counter command (read with A3-AO
IMR - Interrupt Mask Register
The programming of this register selects which
bits in the ISR causes an interrupt output. I! a
RESETN
~
-J~ tRES~~
Figure 1. Reset Timing
November 12,1990
172
SC26C92
= H'P). The command however, does not stop
the CIT The generated square wave is output
on OP3 if it is programmed to be the CIT
output.
In the counter mode, the CIT counts down the
number of pulses loaded into CTURand CTLR
by the CPU. Counting begins upon receipt of
a start counter command. Upon reaching terminal count H'OOOO', the counter ready interrupt bit (ISR[3]) is set. The counter continues
counting past the terminal count until stopped
by the CPU. If OP3 is programmed to be the
output of the CIT, the output remains High until
terminal count is reached, at which time it goes
Low. The output returns to the High state and
ISR[3] is cleared when the counter is stopped
by a stop counter command. The CPU may
change the values of CTUR and CTLR at any
time, but the new count becomes effective only
on the next start counter commands. I! new values have not been loaded, the previous count
values are preserved and used for the next
count cycle
In the counter mode, the current value of the upper and lower 8 bits of the counter (CTU, CTL)
may be read by the CPU. It is recommended
that the counter be stopped when reading to
prevent potential problems which may occur if
a carry from the lower 8 bits to the upper 8 bits
occurs between the times that both halves of
the counter are read. However, note thata subsequent start counter command will cause the
counterto begin anew count cycle using the values in CTUR and CTLR.
Philips Components-Signetics Data Communication Products
Preliminary Specification
Dual asynchronous receiver/transmitter (DUART)
CEN
RON
00-07
(READ)
FLOAT
-----1-/
tRWD-1
WON
00-07
(WRITE)
VAUD
---------'
Figure 2. Bus Timing
""'~
IPO-IP6
(a) INPUT PINS
WRN
J
OLD DATA
'v
NEW DATA
----------11'11-------
OPO-OP7
(b) OUTPUT PINS
Figure 3. Port Timing
November 12, 1990
173
SC26C92
Preliminary Specification
Philips Components-$ignetics Data Communication Products
SC26C92
Dual-asynchronous receiver/transmitter (OUART)
/
,
WRN
INTEJl~~:J;
_I
,,'---------""
/
~R..JXOl_~.5~
______________
VOl
NOTES:
1. INTRN or OP3·0P7 when used as Interrupt outputs.
2. The test for open-drain outputs Is intended to guarantee switching of the output transistor. Measurement 01 this response is referenced from the midpoint of the switching
Signal, VIA. to a point O.5V above Va.. This point represents noise margin that assures true switching has occurred. Beyond this level. the effects of external circuitry and
tast environment are pronounced and can greatly affect the resultanlmeasurement. .
Figure 4. Interrupt Timing
+5V
:!~iTOR
REQUIRED
FQR TIL INPUT.
X,ICLK
CTClK
RxC
TxC
tTx
C,
= C2 -
24pF FOR CL
=20pF
470Q
ClK
x,
'NOTE: X2 SHOULD BE LEFT OPEN OR
GROUNDED WHEN X, IS DRIVEN.
X2'
SC26C92
x,
~CJ
..,
C2
X2
3.6864MHz
TYPICAL CRYSTAL SPEClACAnON
FREQUENCY
lOAD CAPACITANCE (CLl
TYPE OF OPERAnON
2-4 MHz
,2-32pF
PARALLEL RESONANT, FUNDAMENTAL MODE
Figure 5. Clock TIming
November 12,1990
174
Preliminary Specification
Philips Components-Signetics Data Communication Products
SC26C92
Dual asynchronous receiver/transmitter (DUART)
-t
(lo~~~ciL~KS)
~
TxC
(INPUT)
.
-1l----~
~CS~
1
-/
TxC
(IX OUTPUT)
Figure 6. Transmitter External Clocks
\'----~"1~
Figure 7. Receiver External Clock
TxD
TRANSMITTER
ENABLED
TxRDY
(SR2)
WRN
CTSN 1
(IPO) _ _ _..J
I
('1..______________________n
. !.L-___
RTSN'--:l
(OPO)
OPR(D)_ 1
OPR(D)_ 1
NOTES:
1. Tirringshown1orMR2(4).1.
2. Timing shown fOl' MR2(5) _ 1.
Figure 8. Transmitter Timing
November 12,1990
175
Preliminary Specification
Philips Components-Signetics Data Communication Products
Oual
~synchronous
receiver/transmitter (OUART)
SC26C92
RxD
RECEIVER
ENABLED
RxRDY
(SAO) _ _ _ _ _ _- '
-r_______________
FFULL
(SR') _ _ _ _ _ _ _ _ _ _
~
RxRDYI - - - - - - - - - - - - - ,
FFULL
(OPS)'
RON - - - - - - - - - - - - - ,
~
~
~
______________________________
~
~
0,
OVERRUN
(SR4) _______
RTS'~
(CPO)
( '...._ _ _ _ _ _ _ _ _ _ _----'
OPR(O). ,
NOTES:
1. TIrringshownforMR1(7)_1.
2. Shown for OpeR(4) • , and MR(6) = O.
Figure 9. Receiver TIming
MASTER STATION
BIT9
1 ADD#'! ,I
TxD
I
I
-~::~~1~1-------:;)-'--f(I~""""_--Jrl
, _______________
~
WRN
MR'(4-3).11
MR'(')"
ADD#, MR'(')' 0 DO
PERIPHERAL STA!lON
BIT9
RXD~
~'
:01
-------------------------
,~,
C-
MR'(')., ADD#2
BIT.
IIADD#,:,ld
RECEIVER
ENABLED _______________________
(
i
BIT 9
00
~I-----J
II
,:0 I I 1(,
L>,
,--u
I
I
I
I
RD:::-IJ-;~~~=========~-~...,-~-.'~r-------I~~
--',
MR'(4-3) = 11
ADD#,
. STATUS DATA,
STATUS DATA,
DO
ADD#2
Figure 10. Wake-Up Mode
November 12, 1990
176
Preliminary Specification
Philips Components-$ignetics Data Communication Products
SC26C92
Dual asynchronous receiver/transmitter (DUART)
2.7K
INTRN
o>------I....----~'\IV'~--~o
"J"
DO-D7
TxDAlB
50pF
~
+5V
1= S.3mA VOL
1=400jlA VOH
OP(},,()P7
1
150PF
Figure 11. Test Conditions on Outputs
November 12, 1990
177
+5V
Philips Components-Signetics
_SCC68692
Document No.
853-{)977
ECN No.
00928
Dual asynchronous
Date of Issue
November 5, 1990
receiver/transmitt-er (DUART)
Status
Product Specification
Data Communication Products
DESCRIPTION
The Signetics SCC68692 Dual Universal
Asynchronous Receiverrrransmitter
(DUART) is a single-chip CMOS-LSI
communications device that provides
two full-duplex asynchronous
receiverltransmitter channels in a single
package. It is compatible with other
S68000 family devices and can also
interface easily with other
microprocessors. The DUART can be
used in a polled or interrupt driven
systems.
The operating mode and data format of
each channel can be programmed
independently. Additionally, each
receiver and transmitter can select its
operating speed as one of eighteen
fixed baud rates, a 16X clock derived
from· a programmable counterltimer, or
an external 1X or 16X clock. The baud
rate generator and counterltimer can
operate directly from a crystal or from
external clock inputs. The ability to
independently program the operating
speed of the receive~ and transmitter
make the DUART particularly attractive
for dual-speed channel applications
such as clustered terminal systems.
Each receiver is quadruple buffered to
minimize the potential of receiver
over-run or to reduce interrupt overhead
in interrupt driven systems. In addition,
a flow control capability is provided to
disable a remote DUART transmitter
when the receiver buffer is full.
Also provided on the SCC68692 are a
munipurpose 6-bit input port and a
munipurpose 8-bit output port. These
can be used as general purpose I/O
Ports or can be assigned specffic
functions (such as clock inputs or
status/interrupt outputs) under program
control.
• Multi-function 8-bit output port
- Individual bit set/reset cap~bility
- Outputs can be programmed to be
status/interrupt signals
FEATURES
• S68000 bus compatible
• Dual full-duplex asynchronous
receiverltransmitters
• Versatile interrupt system
- Single interrupt output with eight
maskable interrupting conditions
• Quadruple buffered receiver data
register
- Interrupt vector output on interrupt
acknowledge
• Programmable data for.mat:
- S to 8 data bits plus parity
- Output port can be configured to
provide a total of up to six separate
wire-aRable interrupt outputs
- Odd, even, no parity or force parity
- 1, 1.S or 2 stop bits programmable
in 1/16-bit increments
• Programmable baud rate for each
receiver and transmitter selectable
from:
- 18 fixed rates: SO to 38.4k baud
- One user-defined rate derived from
programmable counterltimer
- External 1X or 16X clock
• Parity, framing, and overrun error
detection
• False start bit detection
• Line break detection and generation
• Programmable channel mode
- Normal (full-duplex)
- Automatic echo
- Local loopback
- Remote loopback
• Multi-function 6-bit input port
- Can serve as clock or control inputs
- Change of state detection on four
inputs
178
• Maximum data transfer rates:
1X - 1MB/sec, 16X - 12SkB/sec
• Automatic wake-up mode for multidrop
applications
• Start-end break interrupt/status
• Detects break which originates in the
middle of a character
• On-chip crystal oscillator
• Power down mode
• Receiver timeout mode
• Commercial and Industrial temperature range versions
• TTL compatible
• Single +SV power supply
Product Specification
Philips Components-Signetics Data Communication Products
SCC68692
Dual asynchronous receiver/transmitter (DUART)
PIN CONFIGURATIONS
INDEX
CORNER
Vee
1P4
IPS
IACKN
1P2
CSN
RESETN
X2
TOP VIEW
X,/CLK
RxoS
RxDA
TxOS
ixCA
op,
OPO
OP3
OP2
OPS
OP4
OP7
0P6
0,
DO
03
02
05
D4
07
PlNlfUNCDON
,
2
3
4
5
6
7
8
9
'0
A2
IP'
A3
A4
IPO
R1WN
OTACKN
11 RxOB
'2 NC
'3 TxDB
'4 op,
'5 OP3
'6 OP5
17 OP7
'8 0'
03
20 05
2' 07
22 GNO
,"
06
GND
NC
A'
IP3
INTRN
ORDERING INFORMATION
DESCRIPTION
Vce
= +5V.t.5%, TA =0 to +70°C
Vcc
= +5V .t.10%, TA = ·40 to +85°C
40-Pin Cerdip
SCC68692C 1F40
SCC68692E 1F40
40-Pin Plastic DIP
SCC68692C t N40
SCC68692E 1N40
44-Pin Plastic LCC
SCC68692C1A44
SCC68692E1 A44
November5,1990
179
E!lH!EU~CnQH
23
24
25
26
27
28
29
3/l
3'
32
33
34
35
36
37
38
39
40
4'
42
43
NC
INTRN
os
D4
02
DO
OPS
OP4
OP2
OPO
TxOA
NC
RxOA
X,/ClK
X2
RESET
CSN
IP2
IACKN
IP5
IP4
44 VCC
Philips Components-Signetics Data Communication Products
Product Specification
Dual asynchronous receiver/transmitter (OUART)
SCC68692
BLOCK DIAGRAM
A
00-07
"
~
8
Z "v
BUS BUFFER
CHANNEL A
~
TRANSMIT
HOLDING REG
>-- I - -
OPERATION CONTROL
RIWN
DTACKN
CSN
A.-A4
RESETN
A
4,
I
ADDRESS
DECODE
I
t
RIWCONTROl
I
I----
"
"
RECEIVE
HOLDING REG (3)
RxDA
RECEIVE
SHIFT REGISTER
I--
I
I
INTERRUPT CONTROL
INTRN
IACKN
TxDA
TRANSMIT
SHIFT REGISTER
IlIA
I
ISR
IVR
I
~
"
A
-r--~
MRA1,2
CRA
SRA
I
I
TxDB
CHANNElB
(AS ABOVE)
RxDB
"
..'"~
::>
INPUT PORT
0
6
i
TIMING
BAUD RATE
GENERATOR
·1
XlICLK
X2
CLOCK
SELECTORS
I
COUNTER!
TIMER
I
XTAlOSC
I
I
I"
I
~-~I!!
!I
.,
1---
I--
r--
~-
CHANGE OF
STATE
DETECTORS (0)
"
"
~-------
6
/
I
IPO~P5
IPCR
~ACR
1
,.
~
OUTPUT PORT
.~~
"-
"
v
VL.--
FUNCTION
SELECT lOGIC
180
8,
OPO.OP7
OPCR
1
CSRA
CSRB
ACR
CTioR·
CTlR
November 5, 1990
A
i!i
OPR
1
~
VCC
~
GND
Philips Component!h':>ignetics Data Communication Products
Product Specification
Dual asynchronous receiver/transmitter (DUART)
SCC68692
PIN DESCRIPTION
SYMBOL
DO-D7
PIN NO.
25,16,24, t7
23,18,22,19
TYPE
CSN
35
I
Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART are
enabled on DO-D7 as controlled by the RlWN and Al-A4 inputs. When CEN is High, the DUART places
the DO--D71ines in the 3-State condition.
RlWN
8
I
ReadlWrite: A High input indicates a read cycle and a low input indicates a write cycle, when a cycle is
initiated by assertion of the CSN input.
Al-A4
RESETN
1,2,5,6
34
I
I
Address Inputs: Selectthe DUART internal registers and ports for readlwrite operations.
Reset: A Low level clears internal registers (SRA, SRB, IMR, ISR, aPR, OPCR), initializes the IVR to
hex OF, puts OPO-OP7 in the High state, stops the counter/timer, and puts Channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark (High) state.
DTACKN
9
a
Data Transfer Acknowledge: 3-State active-Low output asserted in write, read, or interrupt cycles to
indicate proper transfer of data between the CPU and the DUART.
INTRN
21
a
Interrupt Request: Active-Low, open-drain output which signals the CPU that one or more of the eight
maskable interrupting conditions are true.
IACKN
37
I
Interrupt Acknowledge: Active-Low input indicating an interrupt acknowledge cycle. In response, the
DUART will place the interrupt vector on the data bus and will assert DTACKN if it has an interrupt pending.
Xl/CLK
32
I
Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all
times. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 7).
X2
33
I
Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 7). If Xl/CLK is driven from an external source, this pin can be
left open.
RxDA
31
I
Channel A Receiver Serial Data Input: The least significant bit is received first. "Mark" is High, "space"
is Low.
RxDB
10
I
Channel B Receive Serial Data Input: The least significant bit is received first. "Mark" is High, "space"
is low.
TxDA
30
a
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is
held in the "mark" condition when the transmitter is disabled, idle or when operating in localloopback
mode. "Mark" is High, "space" is low.
TxDB
11
a
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is
held in the 'mark' condition when the transmitter is disabled, idle, or when operating in localloopback
mode. 'Mark' is High, 'space' is Low.
OPO
29
a
Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be deactivated automatically on receive or transmit.
OPI
12
a
Output 1 : General purpose output or Channel B request to send (RTSBN, active-low). Can be deactivated automatically on receive or transmit.
OP2
28
a
Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A receiver 1X clock output.
OP3
13
a
Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B transmit- .
ter 1X clock output, or Channel B receiver 1X clock output.
OP4
27
14
a
Output 4: General purpose output or Channel A open-drain, active-low, RxRDYAN/FFULlAN output.
OutputS: General purpose output or Channel B open-drain, active-low, RxRDYBN/FFUllBN output.
OP5
OP6
110
NAME AND FUNCTION
Data Bus: Bidirectional3-State data bus used to transfer commands, data and status between the
DUART and the CPU. DO is the least significant bit.
26
a
a
OP7
IPO
IPI
15
7
a
I
4
IP2
36
I
I
IP3
2
I
Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock.
IP4
39
I
Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock.
IP5
38
I
Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock.
Vee
GND
40
20
I
I
Power Supply: +5V supply input.
Ground
November 5, 1990
Output6: General purpose output or Channel A open-drain, active-low, TxRDYAN output.
Output 7: General purpose output or Channel B open-drain, active-low, TxRDYBN output.
Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN).
Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN).
Input 2: General purpose input or Channel B receiver external clock input (RxCB), or counter/timer external clock input. When external clock is used by the receiver, the received data is sampled on the rising
edge of the dock.
181
Product Speci.fication
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
SCC68692
ABSOLUTE MAXIMUM RATINGs1
SYMBOL
PARAMETER
RATING
UNIT
Note 4
°C
Storage temperature range
~5to+150
-C
Vee
Voltage from Vee to GND3
~.5to+7.0
V
Vs
Voltage from any pin to GND3
~.5 to Vee +0.5
V
TA
Operating ambient temperature range 2
Tsm
Power dissipation
750
mW
Po
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on + 150°C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its intemal devices from damaging effects of excessive static charge.
Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range.
DC ELECTRICAL CHARACTERISTICS1, 2, 3
LIMITS
SYMBOL
PARAMETER
Max
UNIT
0.8
V
V
V
V
0.4
V
V
-10
-75
0
+10
0
75
J.LA
J.LA
J.LA
VOUT = Vee, Xl = 0
VOUT = 0, Xl = 0
VOUT = 0, Xl = Vee
VOUT = Vee, Xl = Vee
0
-10
-75
1
+75
-1
0
10
J.LA
mA
J.LA
mA
V IN = 0 to Vee
V IN = 0 to Vee
-10
-20
+10
+10
J.LA
J.LA
10
-10
J.LA
J.LA
TEST CONDITIONS
Min
Vil
VIH
VIH
VIH
Input low voltage
Input high voltage (except Xl/CLK)6
Input high voltage (except Xl/CLKj1
Input high voltage (Xl/CLK)
VOL
VOH
Output low voltage
Output high voltage (except 00 outputs)4
IOl = 2.4mA
IOH =-400J.LA
Vee~·5
IIX1PO
IllXl
IIHXl
XlICLK input current - power down
Xl/CLK input low current - operating
Xl/CLK input high current - operating
VIN = Oto Vee
VIN = 0
VIN = Vee
IOHX2
IOHX2S
IOlx2
IOlX2S
X2 output high current - operating
X2 output high short circuit current - operating
X2 output low current - operating
X2 output low short circuit current - operating and
power down
II
Typ
2.0
2.5
0.8Vee
Input leakage current:
All except input port pins
Input port pins
IOZH
IOZl
Output off current high, 3-State data bus
Output off current low, 3-State data bus
VIN = Vee
VIN = OV
IOOl
looH
Open-drain output low 'current in off State
Open-drain output high current in off State
VIN = 0
VIN = Vec
. Power supply currentS
Operating mode
TTL input levels
CMOS input levels
TTL input levels
CMOS input levels
lee
Power down mode
-10
10
10·
10
3.0
2.0
J.LA
J.LA
mA
mA
mA
mA
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between OAV and 2.4V with a transition time of 5ns
maximum. For Xl/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V, as appropriate.
3. Typical values are at +25°C, typical supply' voltages, and typical processing parameters.
4. Test conditions for outputs: Cl = 150pF, except interrupt outputs. Test condition for interrO'pt outputs: Cl = 50pF, RL = 2.7kn to Vee·
5. All outputs are disconnected. Inputs are switching between TTL levels of 2.4V and 0.4V or CMOS levels of Vee ~.2V and Vss + 0.2V.
6. TA~O°C
.
7. TA. 70°C.
BLOCK DIAGRAM
Timing Circuits
The SCC68692 DUART consists of the following eight major sections: data bus buffer, opera'·
tion control, interrupt control, timing,
communications Channels A and B, input port
and output port. Refer.to the Block Diagram.
The timing block consists of a crystal oscillator,
a baud rate generator, a programmable IS-bit
counterltimer, and four clock selectors. The
crystal oscillator operates directly from a crystal
connected across the X I/ClK and X2 inputs.
If an external clock of theappropriatefrequency
Data Bus Bufj!!r
is available, it may be connected to Xl/ClK.
The data bus buffer provides the interface be- , The clock serves as the basic timing reference
tween the external and internal data buses. It
for the Baud Rate Generator (BRG), the counis controlled by the operation control block to alter/timer, and other internal circuits. A clock
low read and write operations to take place besignal within the limits specified in the specificatween the controlling CPU and the DUART.
tions section of this data sheet must always be
supplied to the DUART.
Operation Control
The operation control logic receives operation
commands from the CPU and generates appropriate signals to internal sections to control
device operation. It contains address decoding
and read and write circuits to permit communications with the microprocessor via the data
bus buffer. The DTACKN output is asserted
during write and read cycles to indicate to the
CPU that data has been latched on a write
cycle, or that valid data is presenton the bus on
a read cycle.
Interrupt Control
A single active-low interrupt output (INTRN) is
provided which is activated upon the occurrence of any of eight internal events. Associated with the interrupt system are the
Interrupt Mask Register (IMR) and the Interrupt
Status Register (ISR), the Auxiliary Control
Register (ACR), and the Interrupt Vector Register.(IVR). The IMR may be programmed to select only certain conditions to cause INTRN to
be a~serted. The ISR can be read by the CPU
to determine all currently active interrupting
conditions. When IACKN is asserted, and the
DUART has an interrupt pending, the DUART
responds by placing the contents of the IVR
register on the data bus and asserting
DTACKN.
Outputs OP3--0P7 can be programmed to previde discrete interrupt outputs for the transmitter, receivers, and counterltimer.
November 5, 1990
If an external is used instead of a crystal, XI
should be driven using a configuration similar
to the one in Figure 7.
If an external clock is used instead of a crystal,
XI should be driven using a configuration similar to the one in Figure 5.
The baud rate generator operates from the oscillator or externa:! clock input and is capable of
generating 18 commonly used data communications baud rates ranging from 50 to 38.4K
baud. A 3.6864MHz crystal or external clock
mustbe usedtogetthe standard baud rate. The
clock outputs from the BRG are at ISX the actual baud rate. The counterltimer can be used
as a timer to produce a ISX clock for any other
baud rate by counting down the crystal clock or
an external clock. The four clock selectors allow the independent selection, for each receiver and transmitter, of any of these baud rates or
external timing signal.
The Countermmer (C/T) can be programmed
to use one of several timing sources as its input.
The output of the CIT is available to the the
clock selectors and can also be programmed to
be outputatOP3.ln the counter mode, the contents of the CIT can be read by the CPU and
it can be stopped and started under program
control. In the timer mode, the CIT acts as a
programmable divider.
184
Communications
Channels A and B
Each communications channel of· the
SCCS8692 comprises a full-duplex asynchronous receiverltransmitter (UART). The operating frequency for each receiver and transmitter
can be selected independently from the baud
rate generator, the counter timer, or from an external input.
The transmitter accepts parallel data from the
CPU, converts it to a serial bit stream, inserts
the appropriate start, stop, and optional parity
bits and outputs a composite serial stream of
data on the TxD output pin. The receiver accepts serial data on the RxD pin, converts this
serial input to parallel format, checks for start
bit, stop bit, parity bit (if any), or break condition
and sends an assembled characterto the CPU.
Input pon
The inputs to this unlatched S-bit port can be
read by the CPU by performing a read operation at address H·D'. A High input results in a
logic 1 while a low input results in a logic o. D7
will always be read as a logic 1 and DS will reflect the level of IACKN. The pins of thi.port
can also serve as auxiliary inputs to certain portions fo the DUART logic.
Four change-of-state detectors are provided
which are associated with inputs IP3, IP2, IPI
and IPO. A High-to-low or low-te-High transition of these inputs, lasting longer than 25 50fLS, will set the corresponding bit in the input
port change register. The bits ·are cleared
when the register is read by the CPU. Any
change-of-state can also be programmed to
generate an interrupt to the CPU.
The input port pulse detection circuitry uses a
38.4kHz sampling clock derived from one of the
baud rate generator taps. This results ina sampling period of slightly more than 25f1s (this assumes that the clock input is 3.S864MHz). The
detection cirCUitry, in order to guarantee that a
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
true change in level has occurred, requires two
successive samples at the new logic level be
observed. As a consequence, the minimum
duration of the signal change is 25ltS if the
transition occurs "coincident with the first sample pulse". The 50lts time refers to the situation
in which the change-of-state is "just missed"
and the first change-of-state is not detected until 25lts later.
Output Port
The 8-bit mUltipurpose output port can be used
as a general purpose output port, in which case
the outputs are the complements of the Output
Port Register (OPR). OPR(n) = 1 results in
OP(n) = Low and vice versa. Bits of the OPR
can be individually set and reset. A bit is set by
performing a write operation at address H'E'
with the accompanying data specifying the bits
to be reset (1 = set, 0 = no change). Likewise,
a bit is reset by a write at address H'F' with the
accompanying data specifying the bits to be reset (1 = reset, 0 = no change).
Outputs can be also be individually assigned
specific functions by appropriate programming
of the Channel A mode registers (MR1A,
MR2A), the Channel B mode registers (MRI B,
MR2B), and the Output Port Configuration
Register (OPCR).
OPERATION
Transmitter
The SCC68692 is conditioned to transmit data
when the transmitter is enabled through the
command register. The SCC68692 indicates
to the CPU that it is ready to accept a character
by setting the TxRDY bit in the status register.
This condition can be programmed to generate
an interruptrequestatOP60rOP7 and INTRN.
When a character is loaded into the Transmit
Holding Register (THR), the above conditions
are negated. Data is transferred from the holding register to transmit shift register when it is
idle or has completed transmission of the previous character. The TxRDY conditions are
then asserted again which means one full character time of buffering is provided. Characters
cannot be loaded into the THR while the transmitter is disabled.
The transmitter converts the parallel data from
the CPU to a serial bit stream on the TxD output
pin. It automatically sends a start bit followed
by the programmed number of data bits, an optional parity bit, and the programmed numberof
stop bits. The least significant bit is sent first.
Following the transmission of the stop bits, if a
new character is not available in the THR, the
TxD output remains High and the TxEMT bit in
the Status Register (SR) will be set to 1. Transmission resumes and the TxEMT bit is cleared
when the CPU loads a new character into the
THR. If the transmitter is disabled, it continues
November 5, 1990
operating until the character currently being
transmitted is completely sent out. The transmittercan be forced to send a continuous Low
condition by issuing a send break command.
The transmitter can be reset through a software
command. If it is reset, operation ceases immediately and the transmitter must be enabled
through the command register before resuming
operation. If CTS operation is enable, the
CTSN input must be Low in order for the
character to be transmitted. If it goes High in
the middle of a transmission, the character in
the shift register is transmitted and TxDA then
remains in the marking state until CTSN goes
Low. The transmitter can al so control the deactivation of the RTSN output. If programmed,
the RTSN output will be reset one bit time after
the character in the transmit shift register and
transmit holding register (if any) are completely
transmitted, if the transmitter has been disabled.
Receiver
The SCC68692 is conditioned to receive data
when enabled through the command register.
The receiver looks for a High-to-Low
(mark-to-space) transition of the start bit on the
RxD input pin. If a transition is detected, the
state of the RxD pin is sampled each 16X clock
for 7-112 clocks (16X clock mode) or at the next
rising edge of the bit time clock (1 X clock
mode). If RxD is sampled High, the start bit is
invalid and the search for a valid start bit begins
again. If RxD is still Low, a valid start bit is assumed and the receiver continues to sample
the input at one bit time intervals at the theoretical center of the bit, until the proper number of
data bits and parity bit (if any) have been assembled, and one stop bit has been detected.
The least significant bit is received first. The
data is then transferred to the Receive Holding
Register (RHR) and the RxROY bit in the SR is
set to a 1. This condition can be programmed
to generate an interrupt at OP4 or OP5 and
INTRN. If the character length is less than 8
bits, the most significant unused bits in the RHR
are set to zero.
After the stop bit is detected, the receiver will
immediately look for the next start bit. However, if a non-zero character was received without
a stop bit (framing error) and RxD remains Low
for one half of the bit period after the stop bit
was sampled, then the receiver operates as if
a new start bit transition had been detected at
that point (one-half billime after the stop bit was
sampled).
The parity error, framing error, and overrun error (if any) are strobed into the SR at the received character boundary, before the RxRDY
status bit is set. If a break condition is detected
(RxD is Low for the entire character including
the stop bit), a character consisting of all zeros
185
SCC68692
will be loaded into the RHR and the received
break bit in the SR is set to 1. The RxD input
must return to a High condition for at least
one-half bit time before a search for the next
start bit begins.
The RHRconsists ofa First-ln-First-Out(FIFO)
stack with a capacity of three characters. Data
is loaded from the receive shift register into the
topmost empty position of the FIFO. The
RxRDY bit in the status register is set whenever
one or more characters are available to be
read, and a FFULL status bit is set if all three
stack positions are filled with data. Either of
these bits can be selected to cause an interrupt.
A read of the RH R outputs the data at the top
of the FIFO. After the read cycle, the data FIFO
and its associated status bits (see below) are
'popped' thus emptying a FIFO position for new
data.
In addition to the data word, three status bits
(parity error, framing error, and received break)
are also appended to each data character in the
FIFO (overrun is not). Status can be provided
in two ways, as programmed by the error mode
control bit in the mode register. In the 'character' mode, status is provided on a character-by-character basis; the status applies only
to the character at the top of the FIFO. In the
'block' mode, the status provided in the SR for
these three bits is the logical-OR of the status
for all characters coming to the top of the FIFO
since the last 'reset error' command was issued. In either mode reading the SR does not
affect the FIFO. The FIFO is 'popped' only
when the RHR is read. Therefore the status register should be read prior to reading the FIFO.
If the FIFO is full when a new character is received, that character is held in the receive shift
register until a FIFO position is available. If an
additional character is received while this state
exits, the contents of the FIFO are not affected;
the character previously in the shift register is
lost and the overrun error status bit (SR[4] will
be set-upon receipt of the start bit of the new
(overrunning) character.
The receiver can control the deactivation of
RTS. If programmed to operate in this mode,
the RTSN output will be negated when a valid
start bit was received and the FIFO is full.
When a FIFO position becomes available, the
RTSN output will be re-asserted automatically.
This feature can be used to preventan overrun,
in the receiver, by connecting the RTSN output
to the CTSN input of the transmitting device.
If the receiver is disabled, the FIFO characters
can be read. However, no additional characters
can be received until the receiver is enabled
again. If the receiver is reset, the FIFO and all
of the receiver status, and the corresponding
output ports and interrupt are reset. No addi-
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
tional characters can be received until the receiVer is enabled again.
Timeout Mode
The timeout mode uses the received data
stream to control"lhe counter. Eacih time a received character is transferred from the shift
'register to the RHR, the counter is restarted.
If a new ciharacter is not received before the
counter reaches zero count, the counter ready
bit is set, and an interrupt can be generated.
This mode can be used to indicate when data
has been left in the Rx FIFO for more than the
programmed time limit. Otherwise, if the receiver has been programmed to interrupt the
CPU when the receive FIFO is full, and the
message ends before the FIFO is full, the CPU
may not know there is data left in the FIFO. The
CTU and CTL value would be programmed for
just over one character time, so that the CPU
would be interrupted as soon as it has stopped
receiving continuous data. This mode can also
be used to indicate when the serial line has
been marking for longer than the programmed
time limit. In this case, the CPU has read all of
the characters from the FIFO, but the last ciharacter received has started the count. If there is
no new data during the programmed time interval, the counter ready bit will get set, and an interrupt can be generated.
This mode is enabled by writing the appropriate
command to the command register. Writing an
'Ax' to CRA or CRB will invoke the timeout
mode for that cihanne1. Writing a 'Cx' to CRA or
CRB will disable the timeout mode. The timeout mode should only be used by one channel
at once, since it uses the CfT. CTU and CTL
must be loaded with a value greater than the
normal receive character period. The timeout
mode disables the regular START/STOP
Counter commands and puts the CfT into
counter mode under the control of the received
data stream. Eacih time a received ciharacter is
transferred from the shift register to the RHR,
the CfT is stopped after 1 CIT clock, reloaded
with the value in CTU and CTL and then restarted on the next CfT clock. If the CfT is allowed to end the count before a new ciharacter
has been received, the counter ready bit,
November 5, 1990
ISR[3]. will be set. If IMR[3] is set, this will generate an interrupt. Since receiving a ciharacter
after the CfT has timed outwill clear the counter
ready bit, ISR[3], and the.interrupt. Invoking the
'Set Timeout Mode On' command, CRx = 'Ax',
will also clear the counter ready bit and stop the
counter until the next ciharacter is receiVed.
Multidrop Mode
The DUART is equipped with a wake up mode
for multidrop applications. This mode is selected by programming bitsMR1A[4:3] or
MRI B[4:3]to '11 'for Channels Aand B, respectively. In this mode of operation, a 'master' station transmits an address character followed by
data characters for the addressed 'slave' station. The slave stations, with receivers that are
normally disabled, examioe the received data
stream and 'wakeup" the CPU (by setting
RxRDY) only upon receipt of an address ciharacter. The CPU compares the received address to its statlon address and enables the
receiver if it wis,hes to receive the subsequent
data characters. Upon receipt of another address character, the CPU may disable the receiver to initiate the process again.
A transmitted character consists of a start bit,
the programmed number of data bits, and Address/Data (A/D) bit, and the programmed
number of stop bits. The polarity of the'
transmitted AID bit is selected by the CPU by
programming
bit
MR1A[2yMR1B[2] ....
MR1A[2YMRI B[2] = 0 transmits a zero in the
A/D bit position, which identifies the corresponding data bits as data
while
MR1A[2YMR1B[2] = 1 transmits a one in the
A/D bit position, which identifies the corresponding data bits as an address. The CPU
should program the mode register prior to loading the corresponding data bits into the THR.
In this mode, the receiver continuously looks at
the received data stream, whether it is enabled
or disabled. If disabled, it sets the RxRDY status bit and loads the character into the RHR
FIFO if the receiVed AID bit is a one (address
tag), but discards. the reCeiVed character if the
received A/D bit is a zero (data tag). If enabled,
all received characters are transferred to the
186
SCC68692
CPU via the RHR. In either case, the data bits
are loaded into the data FIFO while the AID bit
is loaded into the status FI FO position normally
used for parity error (SRA[5] or SRB[5]). Framing error, overrun error, and break detect operate normally whether or not the receive is
enabled.
PROGRAMMING
The operation of the DUART is programmed by
writing control words into the appropriate registers. Operational feedback is provided via status registers which can be read by the CPU.
The addressing of the registers is described in
Table 1.
The contents of certain control registers are initialized to zero on RESET. Care should be ex- ,,,'
ercised if the contents of a register arechanged
during operation, since certain changes may
cause operational problems. For example,
changing the numberof bits per character while
the transmitter is active may cause the transmission of an incorrect character. In general,
the contents of the MR, the CSR, and the
OPC'R should only be changed while the receiver(s) and transmitter(s) are not enabled,
and certain changes to the ACR should only be
made while the CfT is stopped.
Mode registers 1 and 2 of each channel are accessed via independent auxiliary pointers. The.
pointer is set to MRI x by RESET or by issuing
a 'reset pointer' command via the corresponding command register. Any read or write of the'
mode register while the pointer is at MR 1x,
switches the pointer to MR2x. The pointer then
remains at MR2x, so that subsequent accesses
are always to MR2x unless the pointer is reset
to MRlx as described above.
Mode, command, clock ~elect, and status registers are duplicated for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions.
The reserved registers at addresses H'02' and
H'OA' should never be read during normal operation since they are reserved for internal diagnostics.
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
Table 1.
Register Addressing
A3
A2
Al
AO
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SCC68692
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MR1 A - Channel A Mode
Register 1
MR1A is accessed when the Channel A MR
pointer points to MR1. The pointer is setto MRl
by RESET or by a 'set pointer' command
applied via CRA. After reading or writing
MRl A, the pointer will pointto MR2A.
MR1A[7] - Channel A Receiver
Request-to-Send Control
This bit controls the deactivation of the RTSAN
output(OPO) by the receiver. This outputis normally asserted by setting OPR[O] and negated
by resetting OPR[O]. MR1A[7] = 1 causes
RTSAN to be negated upon receipt of a valid
start bit if the Channel A FIFO is full. However,
OPR[O] is not reset and RTSAN will be asserted
again when an empty FIFO position is available. This feature can be used for flow control
to prevent overrun in the receiver by using the
RTSAN output signal to control the CTSN input
of the transmitting device.
MRl A[6]- Channel A Receiver
Interrupt Select
This bit selects either the Channel A receiver
ready status (RxRDY) or the Channel A FIFO
full status (FFULL) to be used for CPU interrupts. It also causes the selected bit to be output on OP4 if it is programmed as an interrupt
output via the OPCR.
MR1A[5] - Channel A
Error Mode Select
This bit selects the operating mode of the three
FIFOed status bits (FE, PE, received break) for
Channel A. In the 'character' mode, status is
provided on a character-by-character basis;
the status applies only to the character at the
top of the FIFO. In the 'block" mode, the status
provided in the SR for these bits is the accumulation (logical-OR) of the status for all characters coming to the top of the FIFO since the last
'reset error' command for Channel A was issued.
November 5, 1990
READ (RON
= 0)
Mode Register A (MR1A. MR2A)
Status Register A (SRA)
Reserved
Rx Holding Register A (RHRA)
Input Port Change Register (IPCR)
Interrupt Status Register (ISR)
CounterlTimer Upper (CTU)
CounterlTimer Lower (CTL)
Mode Register B (MRl B, MR2B)
Status Register B (SRB)
Reserved
Rx Holding Register B (RHRB)
Reserved
Input Port
Start Counter Command
Stop Counter Command
MRl A[4:31- Channel A Parity Mode Select
If 'with parity· or 'force parity' is selected a parity
bit is added to the transmitted character and the
receiver performs a parity check on incoming
dataMR1A[4:3]= 11 selects Channel A tooperate in the special multidrop mode described in
the Operation section.
MRl A[2]- Channel A Parity Type Select
This bit selects the parity type (odd Dr even) if
the 'with parity' mode is programmed by
MRl A[4:3], and the polarity of the forced parity
bit if the 'force parity' mode is programmed. It
has no effect if the 'no parity' mode is programmed. In the special multidrop mode it selects the polarity of the AID bit.
WRITE (WRN
= 0)
Mode Register A (MR1A, MR2A)
Clock Select Register A (CSRA)
Command Register A (CRA)
Tx Holding Register A (THRA)
Aux. Control Register (ACR)
Interrupt Mask Register (IMR)
CIT Upper Register (CRUR)
CIT Lower Register (CTLR)
Mode Register B (MR1B, MR2B)
Clock Select Register B (CSRB)
Command Register B (CRB)
Tx Holding Register B (THRB)
Interrupt Vector Register (IVR)
Output Port Conf. Register (OPCR)
Set Output Port Bits Command
Reset Output Port Bits Command
3. The receiver must be enabled, but the
transmitter need not be enabled.
4. The Channel A TxRDY and TxEMT status
bits are inactive.
5. The received parity is checked, but is not
regenerated for transmission, i.e. transmitted parity bit is as received.
6. Character framing is checked, but the
stop bits are retransmitted as received.
7. A received break is echoed as received
until the next valid start bit is detected.
8. CPU to receiver communication continues
normally, but the CPU to transmitter link is
disabled.
M Rl A[l :0] - Channel A Bits Per Character
Select
This field selects the number of data bits per
character to be transmitted and received. The
character length does not include the start, parity, and stop bits.
Two diagnostic modes can also be configured.
MR2A[7:6] = 10 selects local loop back mode.
In this mode:
1. The transmitter output is internally connected to the receiver input.
MR2A - Channel A Mode
Register 2
2. The transmit clock is used for the receiver.
MR2A is accessed when the Channel A MR
pointer points to MR2, which occurs after any
access to MRl A. Accesses to MR2A do not
change the pointer.
3. The TxDA output is held High.
MR2A[7:6]- Channel A Mode
Select
Each channel of the DUART can operate in one
of four modes. MR2A[7:6] = 00 is the normal
mode, with the transmitter and receiver operating independently. MR2A[7:6] = 01 places the
channel in the automatic echo mode, which automatically retransmits the received data. The
following conditions are true while in automatic
echo mode:
1. Received data is reclocked and retransmitted on the TxDA output.
2. The receive clock is used for the transmitter.
187
4. The RxDA input is ignored.
5. The transmitter must be enabled, but the
receiver need not be enabled.
6. CPU to transmitter and receiver communications continue normally.
The second diagnostic mode is the remote
loopback mode, selected by MR2A[7:6] = 11.
In this mode:
1. Received data is reclocked and retransmitted on the TxDA output.
2. The receive clock is used for the transmitter.
Product Specification
Philips Components-Signetics Data Communication Products
SCC68692
Dual asynchronous receiver/transmitter (DUART)
3. Received data is not sent to the local
CPU, and the error status conditions are
inactive.
4. The received parity is not checked and is
not regenerated for transmission, i.e.,
transmitted parity is as received.
5. The receiver must be enabled.
6. Character framing is not checked, and the
stop bits are retransmitted as received.
wise. if a mode is deselected the device will
switch out of the mode immediately. An exception to this is switching out of autoecho or remote loopback modes: if the de-selection
occurs just after the receiver has sampled the
stop bit (indicated in 'autoecho by assertion of
RxRDY), and the transmitter is enabled, the
transmitter will remain in autoecho mode until
the entire stop has been retransmitted.
7. A received break is echoed as received
until the next valid start bit is detected.
The user must exercise care when switching
into and out of the various modes. The selected mode will be activated immediately upon
mode selection, even if this occurs in the middle
of a received or transmitted character. Like-
Table 2.
MR2A[5] - Channel A Transmitter Request-to-Send Control
This bit controls the deactivation of the RTSAN
output (OPO) by the transmitter. This output is
normally asserted by setting OPR[O) and negated by resetting OPR[O!. MR2A[5! = 1
caused OPR[O] to be reset automatically one
bit time after the characters in the Channel A
transmit shilt register and in the THR, if any, are
completely transmitted including the' programmed number of stop bits, if the transmitter
is not enabled. This feature can be used to automatically terminate the transmission of a
message as follows:
1. Program auto-reset mode: MR2A[5) = 1.
2. Enable transmitter.
3. Assert RTSAN: OPRIO) = 1.
4. Send message.
5. Disable transmitter after the last character
is loaded into the Channel A THR.
6. The last character will be transmitted and
OPRIO] will be reset one bit time after the
last stop bit, causing RTSAN to be
negated.
Register Bit Formats
MR1A
MR1B
BIT 7
BIT6
BIT5
RxRTS
CONTROL
RxlNT
SELECT
ERROR
MODE
0= No
1 = Yes
0= RxRDY
1 = FFULL
0= Char
1 = Block
BIT7
BIT6
CHANNEL MODE
MR2A
MR2B
00 = Normal
01 = Auto-Echo
10 = Local loop
11 = Remote loop
BIT3
BIT4
BIT 2
PARITY MODE
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multidrop Mode
BITS
BIT 4
TxRTS
CONTROL
CTS
ENABLETx
0= No
1 = Yes
0= No
1 = Yes
BITl
BITO
PARITY
TYPE
BITS PER
CHARACTER
0= Even
1 = Odd
00 = 5
01 =6
10 = 7
11 = 8
BIT 3
BIT 2
BIT 1
BIT 0
STOP BIT LENGTH'
0=0.563
1 = 0.625
2 = 0.688
3 = 0.750
4 = 0.813
5 = 0.875
6 = 0.938
7 = 1.000
8 = 1.563
9 = 1.625
A = 1.688
B= 1.750
C= 1.813
0=1.875
E = 1.938
F = 2.000
NOTE:
• Add 0.5 to values shown for 0 - 7 if channel is programmed for 5 bits/char.
BIT7
BIT6
BITl
BIT2
BITO
See Text
See Text
BIT3
BIT2
BITl
BITO
MISCELLANEOUS COMMANDS
BIT6
DISABLETx
ENABLETx
DISABLE Rx
ENABLE Rx
See Text
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
CRA
CRB
SRA
SRB
BIT 3
BIT4
TRANSMITTER CLOCK SELECT
CSRA
CSRB
BIT7
BIT5
RECEIVER CLOCK SELECT
BITS
BIT4
BIT7
BIT6
BITS
BIT4
BIT3
BI12
BITl
BITO
RECEIVED
BREAK'
FRAMING
ERROR'
PARITY
ERROR'
OVERRUN
ERROR
TxEMT
TxRDY
FFULL
RxRDY
0= No
1 = Yes
0= No
1 = Yes
O=No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
O=No
1 = Yes
NOTE:
• These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from
the top of the FIFO together with bits (4:0). These bits are cleared by a "reset error status" command. In character mode they are discarded
when the corresponding data character is read from the FIFO.
November 5, 1990
188
Philips Components-Signetics Data Communication Products
Product Specification
Dual asynchronous receiver/transmitter {DUART}
Table 2.
OPCR
SCC68692
Register Bit Formats (Continued)
BIT 7
BIT6
BITS
BIT4
OP7
OP6
OPS
OP4
0= OPR[l]
1 = TxRDYB
0= OPR[6]
1 = TxRDYA
0= OPR[5]
1 = RxRDYI
FFULLB
0= OPR[4]
1 = RxRDYI
FFULLA
BIT7
BIT6
BITS
BIT4
ACR
IPCR
ISR
IMR
BRGSET
SELECT
COUNTERITIMER
MODE AND SOURCE
0= set 1
1 =set2
See Table 4
BIT3
BIT 2
BITO
BITl
OP2
OP3
00= OPR[3]
01 = CIT OUTPUT
10 = TxCB(lx)
11 = RxCB(lx)
11 =OPR[2]
01 = TxCA(16x)
10 = TxCA(lx)
11 = RxCA(lx)
BIT3
BIT2
BIT 1
BITO
DELTA
IP31NT
DELTA
IP21NT
DELTA
IPllNT
DELTA
IPOINT
0=011
1 =On
0=011
1 =On
0=011
1 =On
0=011
1 =On
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
BITl
BITO
DELTA
IP3
DELTA
IP2
DELTA
IPl
DELTA
IPO
IP3
IP2
IPl
IPO
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= Low
1 = High
0= Low
1 = High
0= Low
1 = High
0= Low
1 = High
BIT 7
BIT6
BITS
BIT4
BIT 3
BIT2
BIT 1
BITO
IN PORT
CHANGE
DELTA
BREAK B
RxRDYI
FFULLB
TxRDYB
COUNTER
READY
DELTA
BREAK A
RxRDYI
FFULLA
TxRDYA
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
BIT7
BIT6
BIT 5
BIT4
BIT3
BIT2
BIT 1
BITO
IN PORT
CHANGE
INT
DELTA
BREAK B
INT
RxRDYI
FFULLB
INT
TxRDYB
INT
COUNTER
READY
INT
DELTA
BREAK A
INT
RxRDYI
FFULLA
INT
TxRDYA
INT
0=011
1 =On
0=011
1 =On
0=011
1 =On
0=011
1 =On
0=011
1 =On
0=011
1 =On
0=011
1 =On
0=011
1 =On
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
BITl
BITO
CIT[l5]
CIT[14]
Cm13]
C/T[12]
CIT[11]
CIT[10]
CIT[9]
C/T[S)
CTUR
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
BIT 1
BITO
CIT[7]
CIT[6)
C/T[S)
CIT[4)
CIT[3)
CIT[2)
CIT[l)
C/T[O)
CTLR
BIT7
BIT6
BITS
BIT4
BIT 3
BIT2
BITl
BIT 0
IVR[7]
IVR[6]
IVR[S)
IVR[4)
IVR[3)
IVR(2)
IVR[l)
IVR[O)
IVR
November 5, 1990
169
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
MR2A[4]- Channel A Clear-to-Send
Control
If this bit is 0, CTSAN has no effect on the transmitter. If this bit is aI, the transmitter checks
the state of CTSAN (IPO) each time it is ready
to send a character. If IPO is asserted (Low),
the character is transmitted. If it is negated
(High), the TxDA output remains in the marking
state and the transmission is delayed until
CTSAN goes low. Changes in CTSAN while a
character is being transmitted do not affect the
transmission of that character.
MR2A[3:0]- Channel A Stop Bit Length
Select
This field programs the length of the stop bit appended to the transmitted character. Stop bit
lengths of 9/16 to 1 and 1-9/16 to 2 bits, in increments of 1/16 bit, can be programmed for
characterlengthsof6, 7,and8bits. Foracharacter lengths of 5 bits, 1-1/16 to 2 stop bits can
be programmed in increments of 1/16 bit. In all
cases, the receiver only checks for a 'mark'
condition at the center of the first stop bit position (one bit time after the last data bit, or after
the parity bit is enabled).
If an external 1X clock is used for the transmitter, MR2A[3] = a selects one stop bit and
MR2A[3] = 1 selects two stop bits to be
transmitted.
MR1 B - Channel B Mode
Register 1
MRI B is accessed when the Channel B MR
pointerpointsto MRI. The pointer is setto MRI
by RESET or by a 'set pointer' command
applied via CRB. After reading or writing
MRI B, the pointer will point to MR2B.
The bit definitions for this register are identical
to MR 1A, except that all control actions apply
to the Channel B receiver and transmitter and
the corresponding inputs and outputs.
MR2B - Channel B Mode
Register 2
MR2B is accessed when the Channel B MR
pointer points to MR2, which occurs after any
access to MRI B. Accesses to MR2B do not
change the pointer.
The bit definitions for mode register are identical to the bit definitions for MR2A, except that
all control actions apply to the Channel B receiver and transmitter and the corresponding
inputs and outputs.
CSRA - Channel A Clock Select
Register
CSRA[7:4]- Channel A Receiver Clock
Select
This field selects the baud rate clock for the
Channel A transmitter, The field definition is
shown in Table 3.
November 5, 1990
CSRA[:i:O]- Channel A Transmitter Clock
Select
This field selects the baud rate clock for the
Channel A transmitter. The field definition is as
shown in Table 3, except as follows:
CSRA[3:0]
1110
1111
ACR[7]
=0
IP3-16X
IP3-1X
Baud Rate
ACR[7] 1
=
IP3-16X
IP3-1X
The transmitter clock is always a 16X clock except for CSRA[3:0] = 1111.
Table 3.
CSRA[7:4]
Baud Rate
ACR[7]
=0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
50
110
134.5
200
300
600
1,200
1,050
2,400
4,800
1010
1011
1100
1101
1110
1111
7,200
9,600
38.4k
Timer
IP4-16X
IP4-1X
Baud Rate
ACR[7] 1
=
75
110
134.5
150
300
600
1,200
2,000
2,400
4,800
1,800
9,600
19.2k
Timer
IP4-16X
IP4-1X
NOTE: The receiver clock IS always a 16X
clock except for CSRA[7:4] = 1111
CSRB - Channel B Clock Select
Register
CSRB[7:4] - Channel B Receiver Clock
Select
This field selects the baud rate clock for the
Channel B receiver. The field definition is as
shown in Table 3, except as follows:
CSRB[7:4]
1110
1111
ACR[7]
=0
IP6--16X
IP6--1X
Baud Rate
ACR[7] = 1
IP6-16X
IP6-1X
The receiver clock is always a 16X clock except
for CSRB[7:4] = 1111.
CSRB[3:0]- Channel B Transmitter Clock
Select
This field selects the baud rate clock for the
Channel B transmitter. The field definition is as
shown in Table 3, except as follows:
CSRB[3:0]
1110
1111
=0
Baud Rate
ACR[7] 1
IP5--16X
IP5--1 X
IP5--16X
IP5--1 X
ACR[7]
=
The transmitter clock is always a 16X clock except for CSRB[3:0] = 1111.
190
SCC68692
CRA - Channel A Command
Register
CRA is a register used to supply commands to
Channel A. Multiple commands can be specified in a single write to CRA as long as the commands are non-conflicting, e.g., the 'enable
transmitter' and 'reset transmitter' commands
cannot be specified in a single command word.
CRA[7:4]- Miscellaneous Commands
The encoded value of this field may be used to
specify a single command as follows:
0000 No command.
0001 Reset MR pointer. Causes the Channel
A MR pointer to point to MRI.
0010 Reset receiver. Resets the Channel A
receiver as if a hardware reset had been
applied. The receiver is disabled and
the FIFO is flushed.
0011 Reset transmitter. Resets the Channel
A transmitter as if a hardware reset had
been applied.
0100 Reset error status. Clears the Channel
A Received Break, Parity Error, and
Overrun Error bits in the status register
(SRA[7:4]). Used in character mode to
clear OE status (although RB, PE and
FE bits will also be cleared) and in block
mode to clear all error status after a
block of data has been received.
0101 Reset Channel A break change interrupl. Causes the Channel A break detect change bit in the interrupt status
register (ISR[2]) to be cleared to zero.
0110 Start break. Forces the TxDA output
Low (spacing). If the transmitter is
empty the start of the break condition will
be delayed up to two bit times. If the
transmitter is active the break begins
when transmission of the character is
completed. If a character is in the THR,
the start of the break will be delayed until
that character, or any other loaded
subsequently are transmitted.
The
transmitter must be enabled for this
command to be accepted.
0111 Stop break. The TxDA line will go High
(marking)within two bittimes. TxDAwili
remain High for one bit time before the
next character, if any, is transmitted.
1000 Assert RTSN. Causes the RTSN output
to be asserted (Low).
1001 Negate RTSN. Causes the RTSN output to be negated (High).
1010 Set Timeout Mode On. The receiver in
this channel will restart the CIT as each
receive character is transferred from the
shift register to the RHR. The CIT is
placed in the counter mode, the STARTI
STOP counter commands are disabled,
the counter is stopped, and the Counter
Ready Bit, ISR[3], is reset.
1011 Not used.
1100 Disable Timeout Mode. This command
returns control of the CIT to the regular
START/STOP counter commands. It
does not stop the counter, or clear any
pending interrupts. After disabling the
Product Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
timeout mode, a 'Stop Counter' command should be issued
1101 Not used.
1110 Power Down Mode On. In this mode,
the DUART oscillator is stopped and all
functions requiring this clock are suspended. The execution of commands
other than disable power down mode
(1111) requires a Xl/CLK. While in the
power down mode, do not issue any
commands to the CR except the disable
power down mode command. It is recommended that the transmitter and receiver be disabled prior to placing the
DUART into power down mode. This
command is in CRA only. Design Note:
The part will not output DTACKN while
in power down mode. Use automatic
DTACKN generation.
1111 Disable Power Down Mode. This command restarts the oscillator. After invoking this command, wait for the oscillator
to start up before writing further commands to the CR. This command is in
CRAonly.
CRA[3]- Disable Channel A
Transmitter
This command terminates transmitter operation and reset the TxDRY and TxEMT status
bits. However, if a character is being transmitted or if a character is in the THR when the
transmitter is disabled, the transmission of the
character(s) is completed before assuming the
inactive state.
CRA[2]- Enable Channel A
Transmitter
Enablesoperation oftheChannel A transmitter.
The TxRDY status bit will be asserted.
CRA[l]- Disab!e Channel A Receiver
This command terminates operation of the receiver immediately - a character being received will be lost. The command has no effect
on the receiver status bits or any other control
registers. If the special multidrop mode is programmed, the receiver operates even if it is disabled. See Operation section.
CRA[O]- Enable Channel A Receiver
Enables operation of the Channel A receiver.
If not in the special wakeup mode, this also
forces the receiver into the search for start bit
state.
CRB - Channel B Command
Register
CRB is a register used to supply commands to
Channel B. Multiple commands can be specified in a single write to CRB as long as the commands are non-conflicting, e.g., the 'enable
transmitter' and 'reset transmitter' commands
cannot be specified in a single command word.
The bit definitions for this register are identical
to the bit definitions for CRA, with the exception
of comamnds "Ex" and "Fx" which are used for
November 5, 1990
power downmode. These two commands are
not used in CRB. All other control actions that
apply to CRA also apply to CRB.
SRA - Channel A Status
Register
SRA[7] - Channel A Received Break
This bit indicates that an all zero character of
the programmed length has been received
without a stop bit. Only a single FIFO position
is occupied when a break is received: further
entries to the FIFO are inhibited until the RxDA
line to the marking state for at least one-half a
bit time (two successive edges of the internal or
external 1X clock).
When this bit is set, the Channel A 'change in
break' bit in the ISR (ISR[2]) is set. ISR[2] is
also set when the end of the break condition, as
defined above, is detected.
The break detect circuitry can detect breaks
that originate in the middle of a received character. However, if a break begins in the middle
of a character, it must persist until at least the
end of the next character time in order for it to
be detected.
SRA[6] - Channel A Framing Error
This bit, when set, indicates that a stop bit was
not detected when the corresponding data
character in the FIFO was received. The stop
bit check is made in the middle of the firsl stop
bit position.
SRA[5]- Channel A Parity Error
This bit is set when the 'with parity' or 'force parity' mode is programmed and the corresponding character in the FIFO was received with
incorrect parity. In the special multidrop mode,
the parity error bit stores the received AID bit.
SRA[4] - Channel A Overrun Error
This bit, when set, indicates that one or more
characters in the received data stream have
been lost. Itis setupon receipt of anew character when the FI FO is full and a character is already in the receive shift register waiting for an
empty FIFO position. When this occurs, the
character in the receive shift register (and its
break detect, parity error and framing error status, if any) is lost. This bit is cleared by a 'reset
error status' command.
SRA[3]-Channel A Transmitter Empty
(TxEMTA)
This bitwill be set when the Channel A transmitter underruns; i.e., both the Transmit Holding
Register (THR) and the transmit shift register
are empty. It is set after transmission of the last
stop bit of a character if no character is in the
THR awaiting transmission. It is reset when the
THR is loaded by the CPU orwhen the transmitter is disabled.
191
SCC68692
SRA[2] - Channel A Transmitter Ready
(TxRDYA)
This bit, when set, indicates that the THR is
empty and ready to be loaded with a character.
This bit is cleared when the THR is loaded by
the CPU and is set when the character is transferred to the transmit shift register. TxRDY is
resetwhen the transmitter is disabled and is set
when the transmitter is first enabled, e.g., characters loaded into the THR while the transmitter
is disabled will not be transmitted.
SRA[l] - Channel A FIFO Full (FFULLA)
This bit is set when a character is transferred
from the receive shift register to the receive
FIFO and the transfer causes the FIFO to become full, i.e., all three FIFO positions areoccupied. It is reset when the CPU reads the RHR.
If acharacter is waiting in the receive shift register because the FIFO is full, FFULL will not be
reset when the CPU reads the RHR.
SRA[O]- Channel A Receiver Ready
(RxRDYA)
This bit indicates that a character has been received and is waiting in the FIFO to be read by
the CPU. It is set when the character is transferred from the receive shift to the FIFO and reset when the CPU reads the RHR, if after this
read there are not more characters still in the
FIFO.
SRB - Channel B Status
Register
The bit definitions for this register are identical
to the bit definitions for SRA, except that all status applies to the Channel B receiver and transmitter and the corresponding inputs and
outputs.
OPCR - Output Port
Configuration Register
OPCR[7] - OP7 Output Select
This bit programs the OP7 output to provide
one of the following:
- The complement of OPR[7].
- The Channel B transmitter interrupt output
which is the complement of TxRDYB.
When in this mode OP7 acts as an
open-drain output. Note that this output is
not masked by the contents of the IMR.
OPCR[6] - OP6 Output Select
This bit programs the OPS output to provide
one of the following:
- The complement of OPR[S].
- The Channel A transmitter interrupt output
which is the complement of TxRDYA.
When in this mode OPS acts as an
open-drain output. Note that this output is
not masked by the contents of the IMR.
Philips Components-Signetics Data Communication Products
Product Specification
Dual asynchronous receiver/transmitter (OUART)
OPCR[S] - OPS Output Select
This bit programs the OPS output to provide
one of the following:
- The complement of OPR[S).
- The Channel B transmitter interrupt output
which is the complement of ISR(5). When
in this mode OP5 acts as an open-,OMMAND
Product Specification
Philips Components-Signetics Data Communication Products
SCC68692
Dual asynchronous receiver/transmitter (DUART)
MASTER STATION
BIT 9
I ADD.. : 1 I
TxD
I
"
BIT 9
I
!0 I ~:r'
DO
I
_______
TRANSMITTER~
ENABLED
:
TxRDY
:
,
MR1(4+3) = 11
MR1(2)=1
(
ADD#1 MR1(2) = 0 DO
PERIPHERAL STATION
BIT 9
:0 I
I
L' _ _ _ _ _ _ _ _ _ _ __
(-
MR1(2) = 1 ADD#2
BIT9
II 00
:
RECEIVER
ENABLED _ _ _ _ _ _ _ _ _ _ _-+-----'
1
RxD - - - - ,
,-Tr-LL.,r--
I
'-'>r--....
_ _ _ _ _ _ _~\,
~
BIT 9
r-'
:;)'~
,
\I----------~\
(SR2)
CSN
(WRITE)
t',~
Tll,>---l'---'-....I...;A.;:D.;;.D•.;:2...: 1....1
I ADD.. : 1 I
BIT 9
\\
,:0 I I il(
~,
,'(
I
I
I
I
R::_~--;~~~~~~======~-~~--~--~:r:------------~~~
MR1(4:3) = 11
ADDII
STATUS DATA,
STATUS DATA,
DO
ADD.2
Figure 12. Wake-Up Mode
2.7K
INTRN
~----I----'VV'----O
I
.5V
50pF
7500
00-07
TxDNB
OP(},{)P7
2.15V
Figure 13. Test Conditions on Outputs
November 5. 1990
198
Philips Components-Signetics
Document No.
ECN No.
Date of Issue
November 12, 1990
Status
Preliminary Specification
SC68C92
Dual asynchronous
receiver/transmitter (DUART)
Data Communication Products
DESCRIPTION
The SC68C92 is a pin and function
replacement for the SCC68692 with
added features and deeper fifos, Its
configuration on power up is that of the
SCC68692. Its differences from the
SCC68692 are: 8 character receiver,
8 character transmit fifos, receiver watch
dog timer, mode register 0 is added,
extended baud rate and overall faster
speeds, programmable receiver and
transmitter interrupts.
The Signetics SC68C92 Dual Universal
Asynchronous Receiverrrransmitter
(DUART) is a single-chip CMOS-LSI
communications device that provides
two full-duplex asynchronous
receiverltransmitter channels in a single
package. It interfaces directly with
microprocessors and may be used in a
polled or interrupt driven system.
The operating mode and data format of
each channel can be programmed
independently. Additionally, each
receiver and transmitter can select its
operating speed as one of eighteen
fixed baud rates, a 16X clock derived
from a programmable counterllimer, or
an external 1X or 16X clock. The baud
rate generator and counter/timer can
operate directly from a crystal or from
external clock inputs. The ability to
independently program the operating
speed of the receiver and transmitter
make the DUART particularly attractive
for dual-speed channel applications
such as clustered terminal systems.
Each receiver is buffered by eight
character fifos to minimize the potential
of receiver over-run or to reduce
interrupt overhead in interrupt driven
systems. In addition, a flow control
capability is provided to disable a
remote transmitter when the receiver
buffer is full.
Also provided on the SC68C92 are a
mUltipurpose 7-bit input port and a
mUltipurpose 8-bit output port. These
can be used as general purpose I/O
ports or can be assigned specific
functions (such as clock inputs or
status/interrupt outputs) under program
control.
The SC68C92 is available in three
package versions: 40-pin and 28-pin,
0.6" wide, DIPs and a 44-pin PLCC.
FEATURES
• S6800 bus compatible
• Dual full-duplex independent
asynchronous receiverltransmitters
• 8 character fifos for each receiver and
transmitter
• Programmable data format
- 5 to 8 data bits plus parity
- Odd, even, no parity or force parity
- 1, 1.5 or 2 stop bits programmable
in 1/16-bit increments
• Programmable baud rate for each
receiver and transmitter selectable
from:
- 18 fixed rates: 50 to 38.4k baud
- Other baud rates to 230.4k baud at
16X
- Programmable user-defined rates
derived from a programmable
counterltimer
- External 1X or 16X clock
• Parity, framing, and overrun error
detection
• False starl bit detection
• Line break detection and generation
199
• Programmable channel mode
- Normal (full-duplex)
- Automatic echo
- Local loopback
- Remote loopback
• Multi-function 7-bit input port
- Can serve as clock or control inputs
- Change of state detection on four
inputs
• Multi-function 8-bit output port
- Individual bit sel/reset capability
- Outputs can be programmed to be
status/interrupt signals
• Versatile interrupt system
- Single interrupt output with eight
maskable interrupting conditions
- Output port can be configured to
provide a total of up to six separate
wire-aRable interrupt outputs
- Each fifo can be programmed for
four different interrupt levels
- Watch dog timer for each receiver
• Maximum data transfer rates:
1X-I MB/sec, 16X - 1Mb/sec
• Automatic wake-up mode for multidrop
applications
• Start-end break interrupt/status
• Detects break which originates in the
middle of a character
• On-chip crystal oscillator
• Power down mode
• Receiver timeout mode
• Commercial, industrial and military
temperature range versions
• TIL compatible
• Single +5V power supply
Philips Components-Signetics Data Communication Products
Preliminary Specification
SC68C92
Dual asynchronous receiver/transmitter (DUART)
PIN CONFIGURATIONS
INDEX
CORNER
Vee
1P4
IPS
IACKN
1P2
eSN
RESETN
X2
TOP VIEW
X1ICLK
RxDB
RxOA
TxDB
TxOA
OPI
OPO
OP3
OP2
OPS
OP4
OP7
OP6
01
DO
03
02
os
D4
07
PIN/FUNCTION
1
2
3
4
5
6
7
8
g
10
11
12
13
14
15
16
17
18
19
20
21
22
06
GNO
INTRN
NC
Al
IP3
A2
IPI
A3
A4
IPO
RIWN
DTACKN
R,DB
NC
TxDB
OPI
OP3
OP5
OP7
01
03
05
07
GNO
ORDERING INFORMATION
DESCRfPTION
Vee
= +5V .±10%, TA = 0 to +70°C
Vec
= +5V .±10%, TA = ·40 to +85°C
40-Pin Cerdip
SC68C92C 1F40
SC68C92E1F40
40-Pin Plastic DIP
SC68C92C 1N40
SC68C92E 1N40
44-Pin Plastic lCC
SC68C92C1A44
SC68C92E1A44
November 12. 1990
200
~NlEUNCIlQN
23
24
25
26
27
26
29
30
31
32
33
34
35
36
37
NC
INTRN
os
D4
D2
DO
OP6
OP4
OP2
OPO
T,DA
NC
RxDA
XlICLK
X2
38 RESET
39 CSN
40 1P2
41
IACKN
42 IP5
43 IP4
44
VCC
Preliminary Specification
Philips Components-Signetics Data Communication Products
SC68C92
Dual asynchronous receiver/transmitter (DUART)
BLOCK DIAGRAM
8
7-
~
r-.
BUS BUFFER
v
CHANNel A
~
OPERATION CONTROL
RlWN
DTACKN
CSN
Al-A4
RESETN
OW;SO
DECODE
4
f
I
RIWCONTROl
I
-
,--
8 BYTE TRANSMIT
AFO
I----
TRANSIilT
SHIFT REGISTER
"-
8 BYTE RECEIVE
AFO
v
WATCH DOG TIMER
TxOA
RxDA
RECEIVE SHIFT
REGISTER
I----
MRAO,1,2
CRA
SRA
INTERRUPT CONTROL
INTRN
IMR
IACKN
I
ISR
IVR
I
7
"
r-.
v
"-
"
RxDB
j!!
c
cj
IX
~
!<
:iii
0
BAUD RATE
GENERATOR
I
CLOCK
SELECTORS
"
I
-
I
COUNTER!
TIMER
I
XliCLK
X2
I
XTALOSC
I
~
INPUT PORT
..J
2!
ffiA
!<
1=
hOB
CHANNEL B
(AS ABOVE)
v
..."'"
TIMING
I
-
~ f--
"
CHANGE OF
STATE
DETECTORS (4)
J-,.
v
I
IPCR
ACR
6L
IPO~P5
I
I-----<
~
OUTPUT PORT
'----
"-
_J\.
v
v
FUNCTION
SELECT LOGIC
I
CSRA
OPCR
OPR
8
OPO-OP7
I
CSRB
ACR
CTLI'I
CTLR
November 12, 1990
201
c
VCC
C
GND
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
SC68C92
PIN DESCRIPTION
SYMBOL
DO-07
PIN NO.
25,16.24,17
23,18,22,19
TYPE
I/O
35
I
Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART are
enabled on DO-D7 as controlled by the RlWN and Al-A4 inputs. When CEN is High, the DUART places
the DO--D71ines in the 3-State condition.
RlWN
8
I
ReadlWrite: A High input indicates a read cycle and a low input indicates a write cycle, when a cycle is
initiated by assertion of the CSN input.
Al-A4
Address Inputs: Select the DUART internal registers and ports for readlwrite operations.
Reset: A Low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the IVR to
hex OF, puts OPO-OP7 in the High state, stops the counter/timer, and puts Channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark (High) state.
CSN
NAME AND FUNCTION
Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between the
DUART and the CPU. DO is the least significant bit.
1,2,5,6
I
RESETN
34
I
DTACKN
9
0
Data Transfer Acknowledge: 3-State active-Low output asserted in write, read, or interrupt cycles to
indicate proper transfer of data between the CPU and the DUART.
INTRN
21
0
Interrupt Request: Active-Low, open-drain output which signals the CPU that one or more of the eight
maskable interrupting conditions are true.
IACKN
37
I
Interrupt Acknowledge: Active-Low input indicating an interrupt acknowledge cycle. In response, the
DUART will place the interrupt vector on the data bus and will assert DTACKN if it has an interrupt pending.
Xl/CLK
32
I
Crystal 1 : Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all
times. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 7).
X2
33
I
Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 7). If Xl/CLK is driven from an external source, this pin can be
leltopen.
RxDA
31
I
Channel A Receiver Serial Data Input: The least significant bit is received first. "Mark" is High, "space"
is Low.
RxDB
10
I
Channel B Receive Serial Data Input: The least significant bit is received first. "Mark" is High, "space"
is Low.
TxDA
30
0
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is
held in the "mark" condition when the transmitter is disabled, idle or when operating in localloopback
mode. "Mark" is High, "space" is Low.
TxDB
11
0
Channel B Transmiller Serial Data Output: The least significant bit is transmitted first. This output is
held in the 'mark' condition when the transmitter is disabled, idle, or when operating in localloopback
mode. 'Mark' is High, 'space' is Low.
OPO
29
0
Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be deactivatedautomatically on receive or transmit.
OPI
12
0
Outputt: General purpose output or Channel B request to send (RTSBN, active-Low). Can be deactivated automatically on receive or transmit.
OP2
28
0
Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A receiver 1X clock output.
OP3
13
0
Output3: General purpose output or open-drain, active-Low counterllimer output or Channel B transmitter 1X clock output, or Channel B receiver 1X clock output.
OP4
OPS
27
14
Output4: General purpose output or Channel A open-drain, active-Low, RxRDYAN/FFULLAN output.
OP6
26
OP7
IPO
IPI
IP2
15
7
0
0
0
0
4
36
IP3
2
I
Input3: General purpose input or Channel A transmitter external clock input (TxCA). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock.
IP4
39
I
Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock.
IPS
38
I
Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock.
Vee
GND
40
20
I
I
Power Supply: +5V supply input.
Ground
November 12,1990
I
I
I
Output5: General purpose output or Channel B open. 70"C.
BLOCK DIAGRAM
Timing Circuits
The SC68C92 DUART consists of the following
eight major sections: data bus buffer, operation
control, interrupt control, timing, communications Channels A and B, input port and output
port. Refer to the Block Diagram.
The timing block consists of a crystal oscillator,
a baud rate generator, a programmable 16-bit
counter/timer, and four clock selectors. The
crystal oscillator operates directly from a crystal
connected across the Xl/ClK and X2 inputs.
If an external clock of the appropriate frequency
is available, it may be connected to Xl/CLK.
The clock serves as the basic timing reference
for the Baud Rate Generator (BRG), the counter/timer, and other internal circuits. A clock
signal within the limits specified in the specifications section of this data sheet must always be
supplied to the DUART.
Data Bus Buffer
The data bus buffer provides the interface between the external and intemal data buses. It
is controlled by the operation control block to allow read and write operations to take place between the controlling CPU and the DUART.
Operation Control
The operation control logic receives operation
commands from the CPU and generates appropriate signals to internal sections to control
device operation. It contains address decoding
and read and write circuits to permit communications with the microprocessor via the data
bus buffer. The DTACKN output is asserted
during write and read cycles to indicate to the
CPU that data has been latched on a write
cycle, or that valid data is present on the bus on
a read cycle.
Interrupt Control
A single active-Low interrupt output (INTRN) is
provided which is activated upon the occurrence of any of eight internal events. Associated with the interrupt system are the
Interrupt Mask Register (IMR) and the Interrupt
Status Register (ISR), the Auxiliary Control
Register(ACR), and the Interrupt Vector Register (IVR). The IMR may be programmed to select only certain conditions to cause INTRN to
be asserted. The ISR can be read by the CPU
to determine all currently active interrupting
conditions. When IACKN is asserted, and the
DUART has an interrupt pending, the DUART
responds by placing the contents of the IVR
register on the data bus and asserting
DTACKN.
Outputs OP3-0P7 can be programmed to provide discrete interrupt outputs for the transmitter, receivers, and counter/timer.
November 12,1990
If an external is used instead of a crystal, Xl
should be driven using a configuration similar
to the one in Figure 7.
If an external clock is used instead of a crystal,
X 1 should be driven using a configuration similar to the one in Figure 5.
The baud rate generator operates from the oscillator or external clock input and is capable of
generating 18 commonly used data communications baud rates ranging from 50 to 38.4K
baud. Programming bitO of MROto a "1 " gives
additional baud rates of 57.6kB, 115.2kB and
230.4kB. These will be in the 16X mode. A
3.6864MHz crystal or external clock must be
used to get the standard baud rate. The clock
outputs from the BRG are at 16X the actual
baud rate. The counter/timer can be used as a
timer to produce a 16X clock for any other baud
rate by counting down the crystal clock or an external clock. The four clock selectors allow the
independent selection, for each receiver and
transmitter, of any of these baud rates or external timing signal.
The CounterlTimer (CIT) can be programmed
to use one of several timing sources as its input.
The output of the CIT is available to the the
clockselectors and can also be programmed to
be output at OP3.ln the counter mode, the contents of the CIT can be read by the CPU and
it can be stopped and started under program
205
control. In the timer mode, the CIT acts as a
programmable divider.
Communications
Channels A and B
Each communications channel of the
SC68C92 comprises a full-duplex asynchronous receiver/transmitter (UART). The operating frequency for each receiver and transmitter
can be selected independently from the baud
rate generator, the counter timer, or from an external input.
The transmitter accepts parallel data from the
CPU, converts it to a serial bit stream, inserts
the appropriate start, stop, and optional parity
bits and outputs a composite serial stream of
data on the TxD output pin. The receiver accepts serial data on the RxD pin, converts this
serial input to parallel format, checks for start
bit, stop bit, parity bit (if any), or break condition
and sends an assembled character to the CPU.
Input Port
The inputs to this unlatched 6-bit port can be
read by the CPU by performing a read operation at address H'D'. A High input results in a
logic 1 while a low input results in a logic o. 07
will always be read as a logic 1 and 06 will reflect the level of IACKN. The pins of this port
can also serve as auxiliary inputs to certain portions fa the DUART logic.
Four change-of-state detectors are provided
which are associated with inputs IP3, IP2, IPI
and IPO. A High-to-Low or low-to-High transition of these inputs, lasting longer than 25 50~s, will set the corresponding bit in the input
port change register. The bits are cleared
when the register is read by the CPU. Any
change-of-state can also be programmed to
generate an interrupt to the CPU.
The input port pulse detection circuitry uses a
38.4kHz sampling clock derived from one of the
baud rate generator taps. This results in a sampling period of slightly more than 25~s (this assumes that the clock input is 3.6864MHz). The
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
detection circuitry, in order to guarantee that a
true change in level has occurred, requires two
successive samples at the new logic level be
observed. As a consequence, the minimum
duration of the signal change is 2511S if the
transition occurs 'coincident with the first sample pulse". The 50l1s time refers to the situation
in which the change-of-state is "just missed"
and the first change-of-state is not detected until 2511S later.
Output Port
The 8-bit multipurpose output port can be used
as a general purpose output port, in which case
the outputs are the complements of the Output
Port Register (OPR). OPR(n) = 1 results in
OP(n) = Low and vice versa. Bits of the OPR
can be individually set and reset. A bit is set by
performing a write operation at address H'E'
with the accompanying data specifying the bits
to be reset (1 = set, 0 = no change). Likewise,
a bit is reset by a write at address H'P with the
accompanying data specifying the bits to be reset (1 = reset, 0 = no change).
Outputs can be also be individually assigned
specific functions by appropriate programming
of the Channel A mode registers (MR1A,
MR2A), the Channel B mode registers (MR1B,
MR2B), and the Output Port Configuration
Register (OPCR).
OPERATION
Transmitter
The SC68C92 is conditioned to transmit data
when the transmitter is enabled through the
command register. The SC68C92 indicates
to the CPU that it is ready to accept a character
by setting the TxRDY bit in the status register.
This condition can be programmed to generate
an interrupt requestatOP6 orOP7 and INTRN.
When the transmitter is initially enabled the
TxRDYand TxEMPTYbitswili be set in the status register. When a character is loaded to the
transmitfifo the TxEMPTY bit will be reset. The
TxEMPTY will not set until: 1) the transmit fifo
is empty and the transmit shift register has finishedtransmitting the stop bitof the lastcharacter written to the transmit fifo, or 2) the
transmitter is disabled and then re-enabled.
The TxRDY bit is set whenever the transmitter
is enabled and the TxFIFO is not full. Data is
transferred from the holding register to transmit
shift register when it is idle or has completed
transmission of the previous character. Characters cannot be loaded into the THR while the
transmitter is disabled.
The transmitter converts the parallel data from
the CPU to a serial bit stream on the TxD output
pin. It automatically sends a start bit followed
by the programmed number of data bits, an optional parity bit, and the programmed number of
stop bits. The least significant bit is sent first.
November 12,1990
SC68C92
Following the transmission of the stop bits, if a
new character is not available in the THR, the
TxD output remains High and the TxEMT bit in
the Status Register (SR) will be set to 1. Transmission resumes and the TxEMT bit is cleared
when the CPU loads a new character into the
THR. If the transmitter is disabled, it continues
operating until the character currenUy being
transmitted is completely sent out. The transmitter can be forced to send a continuous Low
condition by issuing a send break command.
The parity error, framing error, and overrun error (if any) are strobed into the SR at the received character boundary, before the RxRDY
status bit is set. If a break condition is detected
(RxD is Low for the entire character including
the stop bit), a character consisting of all zeros
will be loaded into the RHR and the received
break bit in the SR is set to 1. The RxD input
must return to a High condition for at least
one-half bit time before a search for the next
start bit begins.
The transmitter can be resetthrough a software
command. If it is reset, operation ceases immediately and the transmitter must be enabled
through the command register before resuming
operation. If CTS operation is enable, the
CTSN input must be Low in order for the
character to be transmitted. If it goes High in
the middle of a transmission, the character in
the shift register is transmitted and TxDA then
remains in the marking state until CTSN goes
Low. The transmitter can also control the deactivation of the RTSN output. If programmed,
the RTSN output will be reset one bit time after
the character in the transmit shift register and
transmit holding register (if any) are completely
transmitted, if the transmitter has been disabled.
The RHR consists of a First-In-First-Out (FIFO)
stack with a capacity of eight characters. Data
is loaded from the receive shift register into the
topmost empty position of the FIFO. The
RxRDY bit in the status register is set whenever
one or more characters are available to be
read, and a FFULL status bit is set if all eight
stack positions are filled with data. Either of
these bits can be selected to cause an interrupt.
A read of the RH R outputs the data at the top
olthe FIFO. After the read cycle, the data FIFO
and its associated status bits (see below) are
'popped' thus emptying a FIFO position for new
data.
Receiver
The SC68C92 is conditioned to receive data
when enabled through the command register.
The receiver looks for a High-to-Low
(mark-to-space) transition of the start bit on the
RxD input pin. If a transition is detected, the
state of the RxD pin is sampled each 16X clock
for7-1/2 clocks (16X clock mode) or at the next
rising edge of the bit time clock (1 X clock
mode). If RxD is sampled High, the start bit is
invalid and the search for a valid start bit begins
again. If RxD is still Low, a valid start bit is assumed and the receiver continues to sample
the input at one bit time intervals at the theoretical center of the bit, until the proper number of
data bits and parity bit (if any) have been assembled, and one stop bit has been detected.
The least significant bit is received first. The
data is then transferred to the Receive Holding
Register (RHR) and the RxRDY bit in the SR is
set to a 1. This condition can be programmed
to generate an interrupt at OP4 or OP5 and
INTRN. If the character length is less than 8
bits, the most significant unused bits in the RHR
are set to zero.
After the stop bit is detected, the receiver will
immediately look for the next start bit. However, if a non-zero character was received without
a stop bit (framing error) and RxD remains Low
for one half of the bit period after the stop bit
was sampled, then the receiver operates as if
a new start bit transition had been detected at
that point (one-half bit time after the stop bit was
sampled).
206
In addition to the data word, three status bits
(parity error, framing error, and received break)
are also appended to each data character in the
FIFO (overrun is not). Status can be provided
in two ways, as programmed by the error mode
control bit in the mode register. In the 'character' mode, status is provided on a character-by-character basis; the status applies only
to the character at the top of the FIFO. In the
'block' mode, the status provided in the SR for
these three bits is the logical-OR of the status
for all characters coming to the top of the FIFO
since the last 'reset error' command was issued. In either mode reading the SR does not
affect the FIFO. The FIFO is 'popped' only
when the RHR is read. Therefore the status register should be read prior to reading the FIFO.
If the FIFO is full when a new character is received, that character is held in the receive shift
register until a FIFO position is available. If an
additional character is received while this state
exits, the contents of the FIFO are not affected;
the character previously in the shift register is
lost and the overrun error status bit (SR[4] will
be set-upon receipt of the start bit of the new
(overrunning) character.
The receiver can control the deactivation of
RTS. If programmed to operate in this mode,
the RTSN output will be negated when a valid
start bit was received and the FIFO is full.
When a FIFO position becomes available, the
RTSN output will be re-asserted automatically.
This feature can be used to prevent an overrun,
in the receiver, by connecting the RTSN output
to the CTSN input of the transmitting device.
Preliminary Specification
Philips Components-Signetics Data Communication Products
SC68C92
Dual asynchronous receiver/transmitter (DUART)
If the receiver is disabled, the FIFO characters
can be read. However, no additional characters
can be received until the receiver is enabled
again. If the receiver is reset, the FIFO and all
of the receiver status, and the corresponding
output ports and interrupt are reset. No additional characters can be received until the receiver is enabled again.
Timeout Mode
The timeout mode uses the received data
stream to control the counter. Each time a received character is transferred from the shift
register to the RH R, the counter is restarted.
If a new character is not received before the
counter reaches zero count, the counter ready
bit is set, and an interrupt can be generated.
This mode can be used to indicate when data
has been left in the Rx FIFO for more than the
programmed time limit. Otherwise, if the receiver has been programmed to interrupt the
CPU when the receive FIFO is full, and the
message ends before the FIFO is full, the CPU
may not know there is data left in the FI FO. The
CTU and CTL value would be programmed for
just over one character time, so that the CPU
would be interrupted as soon as it has stopped
receiving continuous data. This mode can also
be used to indicate when the serial line has
been marking for longer than the programmed
time limit. In this case, the CPU has read all of
the characters from the FIFO, but the last character received has started the count. If there is
no new data during the programmed time interval, the counterready bit will get set, and an interrupt can be generated.
This mode is enabled by writing the appropriate
command to the command register. Writing an
'Ax' to CRA or CRB will invoke the timeout
mode for that channel. Writing a 'Cx' to CRA or
CRB will disable the timeout mode. The timeout mode should only be used by one channel
at once, since it uses the CfT. CTU and CTL
must be loaded with a value greater than the
normal receive character period. The timeout
mode disables the regular START/STOP
Counter commands and puts the CfT into
counter mode under the control of the received
data stream. Each time a received character is
transferred from the shift register to the RHR,
the CfT is stopped after 1 CIT clock, reloaded
November 12, 1990
with the value in CTU and CTL and then restarted on the next CfT clock. If the CfT is allowed to end the count before a new character
has been received, the counter ready bit,
ISR[3]. will be set. If IMR[3] is set, this will generate an interrupt. Since receiving a character
after the CfT has timed outwill clear the counter
ready bit, ISR[3], and the interrupt. Invoking the
'Set Timeout Mode On' command, CRx = 'Ax',
will also clear the counter ready bit and stop the
counter until the next character is received.
receivedA/D bit is azero (data tag). Ifenabled,
all received characters are transferred to the
CPU via the RHR. In either case, the data bits
are loaded into the data FIFO while the AID bit
is loaded into the status FI FO position normally
used for parity error (SRA[5] or SRB[5]). Framing error, overrun error, and break detect operate normally whether or not the receive is
enabled.
Multidrop Mode
The operation of the DUART is programmed by
writing control words into the appropriate registers. Operational feedback is provided via status registers which can be read by the CPU.
The addressing of the registers is described in
Table 1.
The DUART is equipped with a wake up mode
for multidrop applications. This mode is selected by programming bits MR1A[4:3] or
MRI B[4:3]to '11 'forChannels AandB, respectively. In this mode of operation, a 'master' station transmits an address character followed by
data characters for the addressed 'slave' station. The slave stations, with receivers that are
normally disabled, examine the received data
stream and 'wakeup' the CPU (by setting
RxRDY) only upon receipt of an address character. The CPU compares the received address to its station address and enables the
receiver if it wishes to receive the subsequent
data characters. Upon receipt of another address character, the CPU may disable the receiver to initiate the process again.
A transmitted character consists of a start bit,
the programmed number of data bits, and Address/Data (A/D) bit, and the programmed
number of stop bits. The polarity of the
transmitted AID bit is selected by the CPU by
programming
bit
MR1A[2]/MR1B[2].
MR1A[2VMR1B[2] = 0 transmits a zero in the
A/D bit position, which identifies the corresponding data bits as data
while
MR1A[2VMR1B[2] = 1 transmits a one in the
A/D bit position, which identifies the corresponding data bits as an address. The CPU
should program the mode register prior to loading the corresponding data bits into the THR.
In this mode, the receiver continuously looks at
the received data stream, whether it is enabled
or disabled. If disabled, it sets the RxRDY status bit and loads the character into the RHR
FIFO if the received AID bit is a one (address
tag), but discards the received character if the
207
PROGRAMMING
The contents of certain control registers are initialized to zero on RESET. Care should be exercised if the contents of a register are changed
during operation, since certain changes may
cause operational problems. For example,
changing the number of bits percharacterwhile
the transmitter is active may cause the transmission of an incorrect character. In general,
the contents of the MR, the CSR, and the
OPCR should only be changed while the receiver(s) and transmitter(s) are not enabled,
and certain changes to the ACR should only be
made while the CfT is stopped.
Mode registers 1 and 2 of each channel are accessed via independent auxiliary pointers. The
pointer is setto MRI x by RESET or by issuing
a 'reset pointer' command via the corresponding command register. Any read or write of the
mode register while the pointer is at MRlx,
switches the pointer to MR2x. The pointer then
remains at MR2x, so thatsubsequentaccesses
are always to MR2x unless the pointer is reset
to MRlx as described above.
Mode, command, clock select, and status registers are duplicated for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions.
The reserved registers at addresses H'02' and
H'OA' should never be read during normal operation since they are reserved for internal diagnostics.
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
Table 1.
SC68C92
Register Addressing
= 0)
A4
A3
A2
AI
READ (RON
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
Mode Register A (MROA, MR1A, MR2A)
Status Register A (SRA)
Reserved
Rx Holding Register A (RHRA)
Input Port Change Register (IPCR)
Interrupt Status Register (ISR)
Countermmer Upper (CTU)
Countermmer lower (CTl)
Mode Register B (MROB, MRI B, MR2B)
Status Register B (SRB)
Reserved
Rx Holding Register B (RHRB)
Reserved
Input Port
Start Counter Command
Stop Counter Command
1
1
0
a
1
1
1
1
1
1
1
1
1
0
1
a
1
a
1
0
0
0
1
1
0
1
1
WRITE (WRN
= 0)
Mode Register A (MROA, MR1A, MR2A)
Clock Select Register A (CSRA)
Command Register A (CRA)
Tx Holding Register A (THRA)
Aux. Control Register (ACR)
Interrupt Mask Register (I MR)
CIT Upper Register (CRUR)
CIT lower Register (CTlR)
Mode Register B (MROB, MR 1B, MR2B)
Clock Select Register B (CSRB)
Command Register B (CRB)
Tx Holding Register B (THRB)
Interrupt Vector Register (IVR)
Output Port Conf. Register (OPCR)
Set Output Port Bits Command
Reset Output Port Bits Command
REGISTER DESCRIPTIONS
Mode Registers
Note: MRO[3:0]are not used in channel B. They
should be set to O.
'reset error' command for Channel A was issued.
MRO is accessed by setting the MR pointer to
MR1 A - Channel A Mode
Register 1
MROA
MR 1A is accessed when the Channel A MR
pointer points to MR 1. The pointer is selto MR 1
by RESET or by a 'set pointer' command
applied via CRA. After reading or writing
MRI A, the pointer will point to MR2A.
MR1A[4:3\- Channef A Parity Mode Sefect
If 'with parity' or 'force parity' is selected a parity
bit is added to the transmitted character and the
receiver performs a parity check on incoming
dataMR1A[4:3] = 11 selectsChannelAtooperate in the special multidrop mode described in
the Operation section.
ovia the command register command D.
MRO[7] - This bit controls the receiver watch
dog timer. = disable, 1 = able. When enabled,
the watch dog timer will generate a receiver interrupt if the receiver FIFO has not been accessed within 64 bit times of the receiver 1X
clock. This is used to alert the control processor
that data is in the RHR that has not been read.
This situation may occur when the last part of
a message is not large enough to generate an
interrupt.
a
MRO[6]- Bit 2 of receiver FIFO interrupt level.
This bit along with Bit6 of MRI sets the fill level
of the 8 byte FIFO that generates the receiver
interrupt.
MRO[6]
MR1[6]
a
a
a
1
0
1
1
1
Interrupt Condition
1 or more bytes in FI FO
(Rx ROY)
3 or more bytes in FI FO
6 or more bytes in FIFO
8 or more bytes in FIFO
(Rx FUll)
MRO[5:4]- Tx interrupt fill level.
MRO[5]
MRO[4]
a
a
a
1
1
1
a
1
Interrupt Condition
8 bytes empty
(Tx EMPTY)
4 or more bytes empty
6 or more bytes empty
1 or more bytes empty
(TxRDY)
MRO[3]- Not used. Should be set to O.
MRO[2:1]- Test 1 and Test 2. Used for factory
test. Set to 0
MRO[O]- Baud rate extend. 0 = Normal baud
rates. 1 = Extend baud rate. S7.6kB, IIS.2kB,
230.4kB.
November 12,1990
MR1A[7] - Channel A Receiver
Request-to-Send Control
This bit controls the deactivation of the RTSAN
output(OPO) by the receiver. Thisoutputisnormally asserted by setting OPR[O] and negated
by resetting OPR[O]. MR1A[7] = 1 causes
RTSAN to be negated upon receipt of a valid
start bit if the Channel A FIFO is full. However,
OPR[O] isnotresetand RTSANwili be asserted
again when an empty FIFO position is available. This feature can be used for flow control
to prevent overrun in the receiver by using the
RTSAN output signal to control the CTSN input
of the transmitting device.
MR1A[6]-Channel A Receiver
Interrupt Select
This bit selects either the Channel A receiver
ready status (RxRDY) or the Channel A FIFO
full status (FFUll) to be used for CPU interrupts. It also causes the selected bit to be output on OP4 if it is programmed as an interrupt
output via the OPCR.
MR1A[5] - Channel A
Error Mode Select
This bit selects the operating mode of the three
FIFOed status bits (FE, PE, received break) for
Channel A. In the 'character' mode, status is
provided on a character-by-character basis;
the status applies only to the character at the
top of the FIFO. In the 'block" mode, the status
provided in the SR for these bits is the accumulation (logical-OR) of the status for all characters coming to the top of the FIFO since the last
208
MR1A[2]-Charinel A Parity Type Select
This bit selects the parity type (odd Dr even) if
the 'with parity' mode is programmed by
MR1A[4 :3], and the polarity of the forced parity
bit if the 'force parity' mode is programmed. It
has no effect if the 'no parity' mode is programmed. In the special multidrop mode it selects the polarity of the AID bit.
MR1A[1 :0]- Channef A Bits Per Character
Select
This field selects the number of data bits per
character to be transmitted and received. The
character length does not include the start, parity, and stop bits.
MR2A - Channel A Mode
Register 2
MR2A is accessed when the Channel A MR
pointer points to MR2, which occurs after any
access to MRIA. Accesses to MR2A do not
change the pointer.
MR2A[7:6]- Channef A Mode
Select
Each channel of the OUART can operate in one
01 four modes. MR2A[7:6] = 00 is the normal
mode, with the transmitter and receiveroperating independently. MR2A[7:6] = 01 places the
channel in the automatic echo mode, which automatically retransmits the received data. The
following conditions are true while in automatic
echo mode:
1. Received data is reclocked and retransmitted on the TxDA output.
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
2. The receive clock is used for the transmitter.
6. CPU to transmitter and receiver communications continue normally.
3. The receiver must be enabled, but the
transmitter need not be enabled.
4. The Channel A TxRDY and TxEMT status
bits are inactive.
5. The received parity is checked, but is not
regenerated for transmission, i.e. transmitted parity bit is as received.
6. Character framing is checked, but the
stop bits are retransmitted as received.
8. CPU to receiver communication continues
normally, but the CPU to transmitter link is
disabled.
Two diagnostic modes can also be configured.
MR2A[7:6] = to selects localloopback mode.
In this mode:
t. The transmitter output is internally connected to the receiver input.
2. The transmit clock is used for the receiver.
3. The TxDA output is held High.
4. The RxDA input is ignored.
5. The transmitter must be enabled, but the
receiver need not be enabled.
MROA
MROB
2. The receive clock is used for the transmitter.
3. Received data is not sent to the local
CPU, and the error status conditions are
inactive.
7. A received break is echoed as received
until the next valid start bit is detected.
Tab[e 2.
The second diagnostic mode is the remote
loopback mode, selected by MR2A[7:6] = 11.
In this mode:
1. Received data is reclocked and retransmitted on the TxDA output.
4. The received parity is not checked and is
not regenerated for transmission, i.e.,
transmitted parity is as received.
5. The receiver must be enabled.
6. Character framing is not checked, and the
stop bits are retransmitted as received.
7. A received break is echoed as received
until the next valid start bit is detected.
SC68C92
mote loopback modes: if the de-selection
occurs just after the receiver has sampled the
stop bit (indicated in autoecho by assertion of
RxRDY), and the transmitter is enabled, the
transmitter will remain in autoecho mode until
the entire stop has been retransmitted.
MR2A[5]- Channel A Transmitter Requesl-lo·Send Conlrol
This bit controls the deactivation of the RTSAN
output (OPO) by the transmitter. This output is
normally asserted by setting OPR[O) and negated by resetting OPR[O). MR2A[5) = 1
caused OPR[O) to be reset automatically one
bit time after the characters in the Channel A
transmitshilt register and in the THR, if any, are
completely transmitted including the programmed number of stop bits, if the transmitter
is not enabled. This feature can be used to automatically terminate the transmission of a
message as follows:
1 Program auto-reset mode: MR2A[5) = 1.
2. Enable transmitter.
3. Assert RTSAN: OPR[O) = 1.
The user must exercise care when switching
into and out of the various modes. The selected mode will be activated immediately upon
mode selection, even if this occurs in the middle
of a received or transmitted character. likewise, if a mode is deselected the device will
switch outofthe mode immediately. An exception to this is switching out of autoecho or re-
4. Send message.
5. Disable transmitter after the last character
is loaded into the Channel A THR.
6. The last character will be transmitted and
OPR[O) will be reset one bit time after the
last stop bit, causing RTSAN to be
negated.
Register Bit Formats
BIT7
BIT6
RxWATCH
DOG
0= Disable
1 = Enable
RxINT(2)
BIT 5
BIT4
TxINT(I:0)
BIT3
BIT2
BIT 1
BITO
DON'T
CARE
Setto 0
TEST 1
TEST 2
Set to 0
Setto 0
BAUD RATE
EXTEND
0= Normal
1 = Extend
NOTE.
MROB[3:0) are not implemented. When writing to MROB set them to O. A read of MROB[3:0) returns 1111.
BIT7
BIT6
BITS
RxRTS
CONTROL
RxlNT
SELECT
ERROR
MODE
0= No
1 = Yes
0= RxRDY
1 = FFULL
MRIA
MRIB
BIT7
BIT 6
CHANNEL MODE
MR2A
MR2B
00 = Normal
01 = Auto-Echo
10 = Locallocp
11 = Remote loop
BIT4
PARITY MODE
0= Char
1 = Block
BIT5
BIT4
TxRTS
CONTROL
CTS
ENABLETx
O=No
1 = Yes
0= No
1 = Yes
209
BIT2
PARITY
TYPE
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multidrop Mode
NOTE:
•Add 0.5 to values shown for 0 - 7 if channel is programmed for 5 bits/char.
November 12, 1990
BIT 3
BIT 3
BITI
0= Even
1 = Odd
BIT 2
BIT 0
BITS PER
CHARACTER
00
01
10
11
BIT 1
=5
=6
=7
=8
BIT 0
STOP BIT LENGTH'
0=0.563
1 = 0.625
2 = 0.688
3 = 0.750
4=0.813
5 = 0.875
6 = 0.938
7 = 1.000
8 = 1.563
9 = 1.625
A = 1.688
B = 1.750
C = 1.813
D = 1.875
E = 1.938
F = 2.000
Philips Components--$ignetics Data Communication Products
Preliminary Specification
Dual asynchronous receiver/transmitter (DUART)
Table 2.
SC68C92
Register Bit Formats (Continued)
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
BITl
BITO
RECEIVER CLOCK SELECT
TRANSMITTER CLOCK SELECT
See Text
See Text
CSRA
CSRB
BIT 3
BIT 2
BITl
BITO
MISCELLANEOUS COMMANDS
BIT 6
DISABLETx
ENABLETx
DISABLERx
ENABLE Rx
See Text
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
BIT7
CRA
CRB
BITS
BIT4
BIT7
BIT 6
BITS
BIT 4
BIT3
BIT 2
BITl
BIT 0
RECEIVED
BREAK'
FRAMING
ERROR'
PARITY
ERROR'
OVERRUN
ERROR
TxEMT
TxRDY
FFULL
RxRDY
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
SRA
SRB
NOTE •
• These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from
the top of the FIFO together with bits (4:0). These bits are cleared by a "reset error status" command. In character mode they are discarded
when the corresponding data character is read from the FIFO.
OPCR
BIT 7
BIT6
BITS
BIT4
OP7
OP6
OPS
OP4
0= OPR[7]
1 = TxRDYB
o =OPR[6]
0=OPR[5]
1 = RxRDYI
FFULLB
o =OPR[4]
1 = TxRDYA
BIT7
BIT 6
BITS
BIT4
1 = RxRDYI
FFULLA
BRGSET
SELECT
COUNTERfTlMER
MODE AND SOURCE
o = set 1
See Table 4
ACR
1 =set2
IPCR
BIT 2
BIT3
BITO
BIT 1
OP3
OP2
00 = OPR[3]
01 = CfT OUTPUT
10 = TxCB(lx)
11 = RxCB(1x)
11 =OPR[2]
01 = TxCA(16x)
10 = TxCA(lx)
11 = RxCA(lx)
BIT3
BIT2
BITl
BITO
DELTA
IP31NT
DELTA
IP21NT
DELTA
IPllNT
DELTA
IPOINT
0= Off
1 =On
0=011
1 =On
0=011
1 =On
0=011
1 =On
BIT7
BIT6
BITS
BIT 4
BIT3
BIT2
BITl
BITO
DELTA
IP3
DELTA
IP2
DELTA
IPl
DELTA
IPO
IP3
IP2
IPI
IPO
0= No
1 = Yes
O=No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
O=Low
1 = High
0= Low
1 = High
0= Low
1 = High
O=Low
1 = High
BIT7
BIT 6
BITS
BIT4
BIT3
BIT2
BITI
BITO
IN PORT
CHANGE
DELTA
BREAK B
RxRDYI
FFULLB
TxRDYB
COUNTER
READY
DELTA
BREAK A
RxRDYI
FFULLA
TxRDYA
0= No
1 = Yes
0= No
1 = Yes
O=No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
O=No
1 = Yes
ISR
0= No
1 = Yes
o =No
1 = Yes
BIT 7
BIT6
BITS
BIT4
BIT3
BIT2
BITI
BITO
IN PORT
CHANGE
INT
DELTA
BREAK B
INT
RxRDYI
FFULLB
INT
TxRDYB
INT
COUNTER
READY
INT
DELTA
BREAK A
INT
RxRDYI
FFULLA
INT
TxRDYA
INT
0=011
1 =On
0=011
1 =On
0=011
1 =On
0=011
1 =On
IMR
November 12, 1990
0=011
1 =On
0=011
1 =On
210
0=011
1 =On
0=011
1 =On
Philips Components-Signetics Data Communication Products
Preliminary Specification
Dual asynchronous receiver/transmitter (DUART)
Table 2.
SC68C92
Register Bit Formats (Continued)
BIT7
BIT6
BITS
BIT4
BIT3
BIT 2
BIT1
BITO
CfT[1S]
CfT[14]
C/T[13]
C/T[12]
CfT[11]
CfT[10]
CfT[9]
C/T[S]
CTUR
BIT7
BIT6
BITS
BIT4
BIT3
BIT 2
BIT1
BIT 0
CfT[7]
CfT[6]
CfT[S]
CfT[4]
CfT[3]
CfT[2]
CfT[1]
C/T[O]
CTlR
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
BIT1
BITO
IVR[7]
IVR[6]
IVR[S]
IVR[4]
IVR[3]
IVR[2]
IVR[1]
IVR[O]
IVR
MR2A[4]- Channel A Clear-to-Send
Control
If this bit is 0, CTSAN has no effect on the transmitter. If this bit is a 1, the transmitter checks
the state of CTSAN (IPO) each time it is ready
to send a character. If IPO is asserted (Low),
the character is transmitted. If it is negated
(High), the TxDA output remains in the marking
state and the transmission is delayed until
CTSAN goes low. Changes in CTSAN while a
character is being transmitted do not affect the
transmission of that character..
MR2A[3:0]- Channel A Stop Bit Length
Select
This field programs the length of the stop bitappended to the transmitted character. Stop bit
lengths of 9/16 to 1 and 1-9/16 to 2 bits, in increments of 1/16 bit, can be programmed for
character lengths of 6,7, and 8 bits. For a character lengths of 5 bits, 1-1/16to 2 stop bits can
be programmed in increments of 1/16 bit. In all
cases, the receiver only checks for a 'mark'
condition at the center of the first stop bit position (one bit time after the last data bit, or after
the parity bit is enabled).
Table 3.
If an external 1X clock is used for the transmitter, MR2A[3] = 0 selects one stop bit and
MR2A[3] = 1 selects two stop bits to be
transmitted.
MR1 B - Channel B Mode
Register 1
MR 1B is accessed when the Channel B MR
pointer points to MR 1. The pointer is setto MR 1
by RESET or by a 'set pointer' command
applied via CRB. After reading or writing
MR 1B, the pointer will point to MR2B.
The bit definitions for this register are identical
to MR1A, except that all control actions apply
to the Channel B receiver and transmitter and
the corresponding inputs and outputs.
MR2B - Channel B Mode
Register 2
MR2B is accessed when the Channel B MR
pointer points to MR2, which occurs after any
access to MR1 B. Accesses to MR2B do not
change the pointer.
all control actions apply to the Channel B receiver and transmitter and the corresponding
inputs and outputs.
CSRA - Channel A Clock Select
Register
CSRA[7:4]- Channel A Receiver Clock
Select
This field selects the baud rate clock for the
Channel A transmitter. The field definition is
shown in Table 3.
CSRA[3:0]- Channel A Transmitter Clock
Select
This field selects the baud rate clock for the
Channel A transmitter. The field definition is as
shown in Table 3, except as. follows:
CSRA[3:0]
1110
1111
ACR[7] = 0
IP3-16X
IP3-1X
Baud Rate
ACR[7] = 1
IP3-16X
IP3-1X
The transmitter clock is always a 16X clock except for CSRA[3:0] = 1111.
The bit definitions for mode register are identical to the bit definitions for MR2A, except that
Baud Rate
MRO[O] =0
MRO[O] = 1
CSRA[7:4]
ACR[7) =0
ACR[7] = 1
ACR[7] = 0
ACR[7] = 1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
50
110
134.5
200
300
600
1,200
1,050
2,400
4,800
7,200
9,600
38.4K
Timer
IP4-16X
IP4-1X
75
110
134.5
150
300
600
1,200
2,000
2,400
4,800
1,800
9,600
19.2K
Timer
IP4-16X
IP4-1X
50
110
134.5
200
1800
3600
7200
1,050
14.4K
28.8K
7,200
57.6K
230.4K
Timer
IP4-16X
IP4-1X
450
110
230.4K
900
1800
3600
7,200
2,000
14.4K
2B.BK
1,800
57.6K
115.2K
Timer
IP4-16X
IP4-1X
NOTE: The receiver clock is always a 16X clock except for CSRA[7:4]
November 12, 1990
= 1111.
211
Philips Components:-Signetics Data Communication Products
Preliminary Specification
Dual asynchronous receiver/transmitter (DUART)
CSRB - Channel B Clock Select
Register
CSRB[7:4]- Channel B Receiver Clock
Select
This field selects the baud rate clock for the
Channel B receiver. The field definition is as
shown in Table 3, except as follows:
CSRB[7:4)
1110
1111
ACR[7)
=0
IP6-16X
IP6-1 X
Baud Rate
ACR[7) = 1
IP6-16X
IP6-1X
The receiver clock is always a 16X clock except
forCSRB[7:41 = 1111.
CSRB[3:0)- Channel B Transmitter Clock
Select
This field selects the baud rate clock for the
Channel B transmitter. The field definition is as
shown in Table 3, except as follows:
CSRB[3:0)
1110
1111
=0
Baud Rate
ACR[7) = 1
IP5-16X
IPS-IX
IPS-16X
IPS-IX
ACR[7)
The transmitter clock is always a 16X dock except for CSRB[3:01 = 1111.
CRA - Channel A Command
Register
CRA is a register used to supply commands to
Channel A. Multiple commands can be specified in a single write to C RA as long as the commands are non-conflicting, e.g., the 'enable
transmitter' and 'reset transmitter' commands
cannot be specified in a single command word.
CRA[7:4)- Miscellaneous Commands
The encoded value of this field may be used to
specify a single command as follows:
0000 No command.
0001 Reset MR pointer. Causes the Channel
A MR pointer to point to MRI.
0010 Reset receiver. Resets the Channel A
receiver as if a hardware reset had been
applied. The receiver is disabled and
the FIFO is flushed.
0011 Reset transmitter. Resets the Channel
A transmitter as if a hardware reset had
been applied.
0100 Reset error status. Clears the Channel
A Received Break, Parity Error, and
Overrun Error bits in the status register
(SRA[7:4]). Used in character mode to
clear OE status (although RB, PE and
FE bits will also be cleared) and in block
mode to clear all error status after a
block of data has been received.
0101 Reset Channel A break change interrupt. Causes the Channel A break detect change bit in the interrupt status
register (ISR[2]) to be cleared to zero.
November 12, 1990
0110 Start break. Forces the TxDA output
low (spacing). If the transmitter is
empty the startofthe break condition will
be delayed up to two bit times. If the
transmitter is active the break begins
when transmission of the character is
completed. If a character is in the THR,
the start of the break will be delayed until
that character, or any other loaded
subsequenUy are transmitted.
The
transmitter must be enabled for this
command to be accepted.
0111 Stop break. The TxDA line will go High
(marking) within two bit times. TxDA will
remain High for one bit time before the
next character, if any, is transmitted.
1000 Assert RTSN. Causes the RTSN output
to be asserted (low).
1001 Negate RTSN. Causes the RTSN output to be negated (High).
1010 Set TImeout Mode On. The receiver in
this channel will restart the CIT as each
receive character is transferred from the
shift register to the RHR. The CIT is
placed in the counter mode, the START/
STOP counter commands are disabled,
the counter is stopped, and the Counter
Ready Bit, ISR[3], is reset.
1011 Set MR pointerto O.
1100 Disable TImeout Mode. This command
returns control of the CIT to the regular
START/STOP counter commands. It
does not stop the counter, or clear any
pending interrupts. After disabling the
timeout mode, a 'Stop Counter' command should be issued
1101 Not used.
1110 Power Down Mode On. In this mode,
the DUART oscillator is stopped and all
functions requiring this clock are suspended. The execution of commands
other than disable power down mode
(1111) requires a Xl/ClK. While in the
power down mode, do not issue any
commands to the CR except the disable
power down mode command. It is recommended that the transmitter and receiver be disabled prior to placing the
DUART into power down mode. This
command is in CRA only. Design Note:
The part will not output DTACKN while
in power down mode. Use automatic
DTACKN generation.
1111 Disable Power Down Mode. This command restarts the oscillator. After invoking this command, wait for the oscillator
to start up before writing further commands to the CR. This command is in
CRAonly.
CRA[3]- Disable Channel A
Transmitter
This command terminates transmitter operation and reset the TxDRY and TxEMT status
bits. However, if a character is being transmitted or if a character is in the THR when the
transmitter is disabled,the transmission of the
212
SC68C92
character(s) is completed before assuming the
inactive state.
CRA[2) - Enable Channel A
Transmitter
Enables operation of the Channel A transmitter.
The TxRDY status bit will be asserted.
CRA[l) - Disable Channel A Receiver
This command terminates operation of the receiver immediately - a character being receivedwill be lost. The command has no effect
on the receiver status bits or any other control
registers. If the special multidrop mode is programmed, the receiver operates even ifit is disabled. See Operation section.
CRA[O) - Enable Channel A Receiver
Enables operation of the Channel A receiver.
If not in the special wakeup mode, this also
forces the receiver into the search for start bit
state.
CRB - Channel B Command
Register
CRB is a register used to supply commands to
Channel B. Multiple commands can be specified in a single write to CRB as long as the commands are non-conflicting, e.g., the 'enable
transmitter' and 'reset transmitter' commands
cannot be specified in a single command word.
The bit definitions for this register are identical
to the bit definitions for CRA. with the exception
of comamnds "Ex" and "Fx" which are used for
power downmode. These two commands are
not used in CRB. All other control actions that
apply to CRA also apply to CRB.
SRA - Channel A Status
Register
SRA[7) - Channel A Received Break
This bit indicates that an all zero character of
the programmed length has been received
without a stop bit. Only a single FIFO position
is occupied when a break is received: further
entries to the FIFO are inhibited until the RxDA
line to the marking state for at least one-half a
bit time (two successive edges of the internal or
external 1X clock).
When this bit is set, the Channel A 'change in
break' bit in the ISR (ISR[2]) is set. ISR[2] is
also set when the end of the break condition, as
defined above, is detected.
The break detect circuitry can detect breaks
that originate in the middle of a received character. However, if a break begins in the middle
of a character, it must persist until al least the
end of the next character time in order for it to
be detected.
Philips Components-Signetics Data Communication Products
Preliminary Specification
SC68C92
Dual asynchronous receiver/transmitter (DUART)
SRA[6)- Channel A Framing Error
This bit, when set, indicates that a stop bit was
not detected when the corresponding data
character in the FI FO was received. The stop
bit check is made in the middle of the first stop
bit position.
SRA[S) - Channel A Parity Error
This bit is set when the 'with parity' or 'force parity' mode is programmed and the corresponding character in the FIFO was received with
incorrect parity. In the special multidrop mode,
the parity error bit stores the received AID bit.
SRA[4)- Channel A Overrun Error
This bit, when set, indicates that one or more
characters in the received data stream have
been lost. It is set upon receipt of a new character when the FIFO is full and a character is already in the receive shift register waiting for an
empty FIFO position. When this occurs, the
character in the receive shift register (and its
break detect, parity error and framing error status, if any) is lost. This bit is cleared by a 'reset
error status' command.
SRA[3) - Channel A Transmitter Empty
(TxEMTA)
This bitwill be set when the Channel A transmitter underruns; i.e., both the Transmit Holding
Register (THR) and the transmit shift register
are empty. It is set after transmission of the last
stop bit of a character if no character is in the
THR awaiting transmission. Itis reset when the
THR is loaded by the CPU orwhen the transmitter is disabled.
SRA[2) - Channel A Transmitter Ready
(TxRDYA)
This bit, when set, indicates that the THR is
empty and ready to be loaded with a character.
This bit is cleared when the THR is loaded by
the CPU and is set when the character is transferred to the transmit shift register. TxRDY is
resetwhen the transmitteris disabled and is set
when the transmitter is first enabled, e.g., characters loaded into the THR while the transm itter
is disabled will not be transmitted.
SRA[1)- Channel A FIFO Full (FFULLA)
This bit is set when a character is transferred
from the receive shift register to the receive
FIFO and the transfer causes the FIFO to become full, i.e., all eight FIFO positions are occupied. It is reset when the CPU reads the RHR.
If a character is waiting in the receive shift regi ster because the FIFO is full, FFULL will not be
reset when the CPU reads the RHR.
SRA[O]- Channel A Receiver Ready
(RxRDYA)
This bit indicates that a character has been received and is waiting in the FIFO to be read by
the CPU. It is set when the character is transferred from the receive shift to the FIFO and reset when the CPU reads the RHR, if after this
November 12,1990
read there are not more characters still in the
FIFO.
SRB - Channel B Status
Register
The bit definitions for this register are identical
to the bit definitions for SRA, except that all status applies to the Channel B receiver and transmitter and the corresponding inputs and
outputs.
OPCR - Output pon
Configuration Register
OPCR[7] - OP7 Output Select
This bit programs the OP7 output to provide
one of the following:
- The complement of OPR[7].
- The Channel B transmitter interrupt output
which is the complement of TxRDYB.
When in this mode OP7 acts as an
open-drain output. Note that this output is
not masked by the contents of the IMR.
OPCR[6] - OP6 Output Select
This bit programs the OPS output to provide
one of the following:
- The complement of OPR[S).
- The Channel A transmitter interrupt output
which is the complement of TxRDYA.
When in this mode OPS acts as an
open-drain output. Note that this output is
not masked by the contents of the IMR.
Low. The output returns to the High state
when the counter is stopped by a stop
counter command. Note that this output is
not masked by the contents of the IMR.
- The I X clock for the Channel B transmitter,
which is the clock that shifts the transmitted data. If data is not being transmitted, a free running I X clock is output.
- The I X clock for the Channel B receiver,
which is the clock that samples the received data. If data is not being received,
a free running IX clock is output.
OPCR[1 :0)- OP2 Output Select
This field programs the OP2 output to provide
one of the following:
- The complement of OPR[2).
- The 1SX clock for the Channel A transmitter. This is the clock selected by
CSRA[3 :0), and will be a I X clock if
CSRA[3:0) = 11'1
- The I X clock for the Channel A transmitter,
which is the clock that shifts the transmitted data. If data is not being transmitted, a free running I X clock is output.
- The I X clock for the Channel A receiver,
which is the clock that samples the received data. If data is not being received,
a free running I X clock is output.
SOPR - Set the Output pon Bits
(OPR)
OPCR[S) - OPS Output Select
This bit programs the OP5 output to provide
one of the following:
- The complement of OPR[5).
SOPR[7:0) - Ones in the byte written to this
register will cause the corresponding bit positions in the OPR to set to 1. Zeros have no
effect.
- The Channel B transmitter interrupt output
which is the complement of ISR[5). When
in this mode OP5 acts as an open-drain
output. Note that this output is not masked
by the contents of the I MR.
ROPR - Reset Output pon Bits
(OPR)
OPCR[4)- OP4 Output Select
This field programs the OP4 output to provide
one of the following:
- The complement of OPR[4).
- The Channel A receiver interrupt output
which is the complement of ISR[1). When
in this mode OP4 acts as an open-drain
output. Note that this output is not
masked by the contents of the I MR.
OPCR[3:2]- OP3 Output Select
This bit programs the OP3 output to provide
one of the following:
- The complement of OPR[3).
- The counter/timer output, in which case
OP3 acts as an open-drain output. In the
timer mode, this output is a square wave at
the programmed frequency. In the counter
mode, the output remains High until terminal count is reached, at which time it goes
213
ROPR[7:0) - Ones in the byte written to the
ROPR will cause the corresponding bit positions in the OPR to set to o. Zeros have no
effect.
ACR - Auxiliary Control
Register
ACR[7] - Baud Rate Generator Set Select
This bit selects one of two sets of baud rates to
be generated by the BRG.
Set 1:
Set 2:
50,110,134.5,200,300, SOO,
1.05k, I .2k, 2.4k, 4.8k, 7.2k, 9.6k,
and 38.4k baud.
75,110,134.5,150,300,600, 1.2k,
I .8k, 2.0k, 2.4k, 4.8k, 9.Sk, and
19.2k baud.
The selected set of rates is available for use by
the Channel A and B receivers and transmitters
as described in CSRA and CSRB. Baud rate
generator characteristics are given in Table 4.
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
Table 4.
Bit Rate Generator
Characteristics
Crystal or Clock =
3.6864MHz
NORMAL
BAUD
RATE
ACTUAL
l6xClOCK
(kHz)
50
75
tl0
134.5
150
200
300
600
1050
1200
1800
2000
2400
4800
7200
9600
19.2k
38.4k
ERROR(%)
0.8
1.2
1.759
2.153
2.4
3.2
4.8
9.6
16.756
19.2
28.8
32.056
38.4
76.8
115.2
153.6
307.2
614.4
0
0
-{).069
0.059
0
0
0
0
-{).260
0
0
0.175
0
0
0
0
0
0
NOTE:
Duty cycle of 16x clock is 50% ± 1%.
ACR[6:4] - CounterlTlmer Mode And
Clock Source Select
This field selects the operating mode of the
counter/timer and its clock source as shown in
Table 5.
Table 5.
ACR [6:4] Field
Definition
[6:4]
MODE
CLOCK SOURCE
000
001
Counter
Counter
010
Counter
011
Counter
100
101
TImer
TImer
110
TImer
111
TImer
External (IP2)
TxCA -Ix clock of
Channel A transmitter
TxCB - IX clock of
Channel B transmitter
Crystal or external clock
(xl/ClK) divided by 16
External (IP2)
External (IP2) divided
by 16
Crystal or external clock
(XlIClK)
Crystal or external clock
(Xl/ClK) divided by 16
ACR[3:0] -IP3, IP2, IP1, IPO
Change-oloState Interrupt Enable
This field selects which bits of the input port
change register (IPCR) cause the input change
bit in the interrupt status register (ISR[7]) to be
set. II a bit is in the 'on' state the setting of the
corresponding bit in the IPCR will also result in
the setting of ISR[7], which results in the generation 01 an interrupt output if IMR[7] = 1. If a bit
is in the 'off' state, the setting of that bit in the
IPCR has no effect on ISR[7].
November 12, 1990
IPCR - Input Port Change
Register
IPCR[7:4]-IP3, IP2,IP1, IPO
Change-ol-State
These bits are set when a change-of-state, as
defined in the input port section of this data
sheet, occurs althe respective input pins. They
are cleared when the IPCR is read by the CPU.
A read of the IPCR also clears ISR[7], the input
change bit in the interrupt status register. The
setting of these bits can be programmed to
generate an interrupt to the CPU.
IPCR[3:0]-IP3,IP2, IPt, IPO
Change-ol-State
These bits provide the current state of the respective inputs. The information is unlatched
and reflects the state of the input pins at the
time the IPCR is read.
ISR - Interrupt Status Register
This register provides the status of all potential
interrupt sources. The contents of this register
are masked by the Interrupt Mask Register
(IMR). If a bit in the ISR is a '1' and the corresponding bit in the IMR is also a '1', the INTRN
output will be asserted (low). If the corresponding bit in the IMR is a zero, the state of
the bit in the ISR has no effect on the INTRN
output. Note that the IMR does not mask the
reading of the ISR - the true status will be provided regardless of the contents of the IMR.
The contents of this register are initialized to
00'6 when the DUART is reset.
ISR[7]-lnput Port Change Status
This bit is a '1' when a change-of-state has occurred at the IPO, IP1, IP2, or IP3 inputs and
that event has been selected to cause an interrupt by the programming of ACR[3:0). The bit
is cleared when the CPU reads the IPCA.
ISR[6]- Channel B Change In Break
This bit, when set, indicates that the Channel B
receiver has detected the beginning or the end
of a received break. It is reset when the CPU
issues a Channel B 'reset break change interrupt' command.
ISR[5] - Channel B Receiver Ready
or FIFO Full
The function of this bit is programmed by
MRI B[6[. If programmed as receiver ready, it
indicates that a character has been received in
Channel B and is waiting in the FIFO to be read
by the CPU. It is set when the character is
transferred from the receive shift register to the
FIFO and reset when the CPU reads the RHA.
II alter this read there are more characters still
in the FIFO the bit will be set again after the
FIFO is 'popped'. If programmed as FIFO full,
it is set when a character is translerred from the
receive holding register to the receive FIFO and
the transfer caused the Channel B FIFO to be214
SC68C92
come full; i.e., all three FIFO positions areoccupied. It is reset when the CPU reads the RHR.
If a character is waiting in the receive shift register because the FIFO is full, the bit will be set
again when the waiting character is loaded into
the FIFO.
ISR[4]- Channel B Transmitter Ready
This bit is a duplicate of TxRDYB (SRB[2]).
ISR[3]- Counter Ready.
In the counter mode, this bit is set when the
counter reaches terminal count and is reset
when the counter is stopped by a stop counter
command.
In the timer mode, this bitis set once each cycle
of the generated square wave (every othertime
that the counter/timer reaches zero count). The
bit is reset by a stop counter command. The
command, however, does not stop the counter/
timer.
ISR[2]- Channel A Change In Break
This bit, when set, indicates that the Channel A
receiver has detected the beginning or the end
of a received break. It is reset when the CPU
issues a Channel A 'reset break change interrupt' command.
ISR[I]- Channel A Receiver Ready Or
FIFO Full
The function of this bit is programmed by
MR1A[6]. If programmed as receiver ready, it
indicates that a character has been received in
Channel A and is waiting in the FIFO to be read
by the CPU. It is set when the character is
transferred from the receive shift register to the
FIFO and reset when the CPU reads the RHR.
If after this read there are more characters still
in the FIFO the bit will be set again after the
FIFO is 'popped'. If programmed as FIFO full,
it is set when a character is transferred from the
receive holding reg ister to the receive FIFO and
the transfer caused the Channel A FIFO to becomefull; i.e., all three FIFO positions are occupied. It is reset when the CPU reads the RHR.
If a character is waiting in the receive shift register because the FIFO is full, the bit will be set
again when the ISR[O] and IMR waiting character is loaded into the FIFO.
ISR[O] - Channel A Transmitter Ready
This bit is a duplicate of TxRDYA (SRA[2]).
IMR - Interrupt Mask Register
The programming of this register selects which
bits in the ISR causes an interrupt output. If a
bit in the ISR is a '1' and the corresponding bit
in the IMR is also a 't' the INTRN output will be
asserted. If the corresponding bit in the IMR is
a zero, the state of the bit in the ISR has no effect on the INTRN output. Note .that the IMR
does not mask the programmableinterruptoutputs OP3-OP7 or the reading of the ISR.
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
CTUR and CTlR - Counter/Timer
Registers
The CTUR and CTlR hold the eight MSBs and
eight lSBs, respectively, of the value to be
used by the counterltimer in either the counter
or timer modes of operation. The minimum value which may be loaded into the CTURlCTlR
registers is H'0002'. Note that these registers
are write-only and cannot be read by the CPU.
In the timer (programmable divider) mode, the
CIT generates a square wave with a period of
twice the value (in clock periods) of the CTUR
and CTlA. If the value in CTUR and CTlR is
changed, the current half-period will not be affected, but subsequent half periods will be. The
CIT will not be running until it receives an initial
'Start Counter' command (read at address
A3-AO = 1110). After this, while in timer mode
the CIT will run continuously. Receipt of a start
counter command (read with A3-AO = 1110)
causes the counter to terminate the current timing cycle and to begin a new cycle using the values in CTUR and CTlR.
The counter ready status bit (ISR[3]) is set once
each cycle of the square wave. The bit is reset
by a stop counter command (read with A3-AO
= H'F'). The command however, does not stop
the CIT. The generated square wave is output
on OP3 if it is programmed to be the CIT
output.
In the counter mode, the CIT counts down the
number of pulses loaded into CTUR and CTlR
by the CPU. Counting begins upon receipt of
a start counter command. Upon reaching terminal count H'OOOO', the counter ready interrupt bit (ISR[3]) is set. The counter continues
counting past the terminal count until stopped
by the CPU. If OP3 is programmed to be the
output of the CIT, the output remains High until
terminal count is reached, at which time it goes
low. The output returns to the High state and
ISR[3] is cleared when the counter is stopped
by a stop counter command. The CPU may
change the values of CTUR and CTlR at any
time, but the new count becomes effective only
on the next start counter commands. If new val-
RESET
Figure 1. Reset Timing
XllCLK:-------....j..I
Al-A4
RWN
CSN-----_.
DO-D7'----~~
DTACKN!-----------F~--~~~~
Figure 2, Bus Timing (Read Cycle)
November 12, 1990
215
SC68C92
ues have not been loaded, the previous count
values are preserved and used for the next
count cycle
In the counter mode, the current value of the upper and lower 8 bits of the counter (CTU, CTl)
may be read by the CPU. It is recommended
that the counter be stopped when reading to
prevent potential problems which may occur if
a carry from the lower 8 bits to the upper 8 bits
occurs between the times that both halves of
the counter are read. However, note that a subsequent start counter command will cause the
counter to begin a new count cycle using the values in CTUR and CTlR.
IVR -Interrupt Vector Register
This register contains the interrupt vector. The
register is initialized to H'OF' by RESET. The
contents of the register are placed on the data
bus when the DUART responds to a valid interrupt acknowledge cycle.
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
Xl/ClK----t'
Al-A4
RWN
CSN-----,.
DO-D7-~===t==n>-----+_.,.I
DTACKN _ _ _ _ _ _ _ _ _
Figure 3. Bus liming (Write Cycle)
Xl/ClK
INTRN
~~----+--~~------~I
IACKN - - - - . . , .
DO-D7
DTACKN
-----------------~--_t----------_t-V~--------------
----------------------+..,.
Figure 4. Interrupt Cycle Timing
November 12, 1990
216
SC68C92
Preliminary Specification
Philips Components-Signetics Data Communication Products
SC68C92
Dual asynchronous receiver/transmitter (DUART)
CSN------~~r--------------------~j
~.~+
~t~
CSN - - " " " ' \ . i I.
__
_ _ _ _ _ _ _ _ _~-J~
OPl>-OP7 _ _ _ _ _ _ _ _ _ _ _
OLD
DATA
NEW DATA
IPD~
-
Figure 5. Port Timing
'. i
CSN'----f
.\:~:::
I
~R
VOL ..o.SV
INTERRUPTI
OUTPUT
_____ VOL
NOTES:
1. INTRN or OP3 - OP7 when used as interrupt outputs.
2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from themidpoinl of the switching signal. V~, to a
point O.5vo~s above Voc_This poinl represents noise margin thai assures true switching has occurred. Beyond this level, the effects afexternal circu~ry and leslenvironmenl are pronounced
and can greatly affect the resu~ant measurement.
Figure 6. Interrupt Timing
November 12, 1990
217
Philips Components-5ignetics Data Communication Products
Preliminary Specification
Dual asynchronous receiver/transmitter (DUART)
SC68C92
+5V
~~~~~OR
REQUIRED
FOR TIL INPUT.
XIICLK
CTCLK
RxC
TxC
elK
-
'CLK
'CTC
'Rx
IT,
SC68C92
X2
3.6864MHz
TYPICAL CRYSTAL SPECIFICATION
Frequency
2-4 MHz
12 - 32pF
Load Capacitance (ell
Type of Operation
Parallel resonant, fundamental mode
Figure 7. Clock Timing
T'C--t(I~~~~KS) ~I
L
(INPUT)
,~
~')j----~
j~'~
i
/
(IX O U T P U T ) - - - - - - -
Figure 8. Transmit TIming
\,
7
November 12,1990
X1
X2'
NOTE:' X2 SHOULD BE LEFT OPEN OR
GROUNDED WHEN XI IS DRIVEN.
XI
..
~ 470Q_~
-0-..----- ._-
218
Preliminary Specification
Philips Components-Bignetics Data Communication Products
SC68C92
Dual asynchronous receiver/transmitter (DUART)
\'-----
~J('_____
Figure 9. Receive Timing
TxD
TRANSMITTER
ENABLED
TxRDY
(SR2)
CSN
(WRITE)
CTSN'
(IPO) _ _ _.J
I
RTSN 2
(OPO)
----;l
rJ
('-------------------------.
r·----
OPR(O) = 1
OPR(O) = 1
NOTES:
1. Timing shown for MR2(4) .1.
2. Timing shown for MR2(5) SI 1.
Figure 10. Transmitter Timing
RxD
RECEIVER
ENABLED
RxRDY
(SAO) _ _ _ _ _ _ _.J
-+________________--J
FFULL
(SR1) ____________________
RxRDYI - - - - - - - - - - - - - - ,
FFULL
(OP')'
CSN--------------,
(READ)
01
OVERRUN
(SR') ________________________________________
~~~~
RTS' - - - - ,
(OPO)
( ' ' -_ _ _ _ _ _ _ _ _ _ _ _---1
OPR(O)= 1
NOTES:
1. TimingshownforMR1(7) .. "
2. Shown for OPCR(4) and MR1(6) "" O.
Figure 11. Receiver Timing
November 12. 1990
219
U~i.ULI.¥°MMAND
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual asynchronous receiver/transmitter (DUART)
MASTER STAll0H
BIT 9
I ADD.. ! 11
I
TxD
BIT9
,n
DO!O 1 L,,~~
1
SC68C92
.',~
BIT 9
______~,,(l---lI-...J......JIL...:A.::D.::DI2;.:.r..;!1",1
I
~'------
~~
I
TRANSMlnER~
ENABLED
I
I
Ti:~~
I
I
,
----~---r~~~----JI'l
---------------T',(
~
CSN
(WRITE)
MR1(4+3) = 11
MR1(2)=1
AD()jf1 MR1(2) = 0
PERIPHERAL STAll0N
BIT 9
RxD
'l-l
~
DO
BIT9
:01 I
,~'-----------------------<-
MR1(2) = 1 AD()jf2
BIT 9
I ADD..: I II
"
,~h
1
RECEIVER
:
ENABLED _____________________If-_...J
I
I
.--__.y:B",IT,.;.9.,
BIT 9
I
I
I
~
RxRDV
'(-
I ADDI2:' III'-...JL..._"';';:0::. 11 ~(-
(::~-IJ-~:::::::::===~~-., ~:r--:-----I;"~
MR1(4:3)= 11
ADDt1
STATUS DATA
STATUS DATA,
DO
ADDI2
Figure 12. Wake,Up Mode
2.7K
INTRN
~----I-.----~'VV'----O
50pF
'J"
00-07
T,DAlB
~
+5V
1= 5.3mA VOL
1= 4OO1tA VOH
OPO-OP7
I
'50PF
Figure 13. Test Conditions on Outputs
November 12, 1990
220
+5V
Philips Components-Signetics
Document No.
ECN No.
Date of Issue
November 12, 1990
Status
Preliminary Specification
SC26C94/SC68C94
Quad universal asynchronous
receiver/transmitter (QUART)
Data Communication Products
PIN CONFIGURATIONS
DESCRIPTION
FEATURES
The SC26C94/SC68C94 quad universal
asynchronous receiverltransmitter
(QUART) combines four enhanced
Signetics industry-standard UARTs with
an innovative interrupt scheme that can
vastly minimize host processor
overhead. It is implemented using
Signetics' high-speed CMOS process
that combines small die size and cost
with low power consumption.
• Four Signetics industry-standard
UARTs
The operating speed of each receiver
and transmitter can be selected
independently at one of eighteen fixed
baud rates, a 16X clock derived from a
programmable counterltimer, or an
external 1X or 16X clock. The baud rate
generator and counterltimer can operate
directly from a crystal or from external
clock inputs. The ability to independently
program the operating speed of the
receiver and transmitter make the Octal
UART particularly attractive for
dual-speed channel applications such as
clustered terminal systems.
Each receiver is buffered with eight
character FIFOs (first-in-first-out
memories) and one shift register to
minimize the potential for receiver
overrun and to reduce interrupt
overhead in interrupt driven systems. In
addition, a handshaking capability is
provided to disable a remote UART
transmitter when the receiver buffer is
full. (RTS control)
The SC26C941SC68C94 provides a
power-down mode in which the oscillator
is stopped and the register contents are
stored. This results in reduced power
consumption on the order of several
magnitudes. The Octal UART is fully
TIL compatible and operates from a
single +5V power supply.
• Eight byte receive FIFOs for each
UART
• Programmable data format:
- 5 to 8 data bits plus parity
- Odd, even, no parity or force parity
- 1, 1.5 or 2 stop bits programmable
in 1/IS-bit increments
• Baud rate for the receiver and
transmitter selectable from:
- 18 fixed rates: 50 to 38.4K baud
Non-standard rates to 230.4K baud
- User-defined rates from the
programmable counterltimer
associated with each block
- External 1X or 16X clock
• Parity, framing, and overrun error
detection
• False start bit detection
• Line break detection and generation
VCC
AIS,O]
CEN
RON
WRN
OACKN
IACKN
OIHl
RON
RESET
Xl/eLK
IOOa-d
101a-" >
"
z
a:
;=
~
:;:
~
~
:
1020
AS
1010
IRON
lOOD
I02C
AD
WRN
November 12, 1990
RXDD
os
TXDD
IOlC
lOOC
VSS
VCC
CEN
lOOA
lOlA
D2
RON
102A
103B
OACKN
100B
IACKN
1018
TXOB
I02B
RXOB
07
TXOA
RXOA
06
DO
05
01
D4
02
03
Vss
Xl/CLK
D4
VSS
X2
D3
VSS
1030
Vss
RESET
TXDC
01
RXOC
DO
1020
RXDA
1010
TXOA
.. .. ..§
1;1 §
222
'"2 1;1'" §'" §'" >'"'" § §" "1;1 "2
0
§
Preliminary Specification
Philips Components Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
(QUART)
SC26C94/SC68C94
BLOCK DIAGRAM
INTERNAL DATA
~S
0[700]
~
r
v
I
I
CONTROL~r--
I
RESET
ADDRESS
DECODE
I
~
'-===t==;t-,
f.I
A-T
>--
~
I
I
l~====~II
CRYSTAL
OSCILLATOR
Xl/elK
>--
"J"
10[300]C
CSR Rx
I
CSR Tx
::t 1'\
~-~--:-.c;
II
J
r---!
I
.VSS2
.VSS3
f-I-----.,:~::::::--~I I~
v
.VSS4
November 12, 1990
I
OPCR
II
RxDB
it
100
AB
100
10[300]B
I
4
f--"--r'--'--
i
10[300]A
II
TIMING
I
i:
INTERRU PT CONTROL
JI
I
FUNCTION SELECT
LOGIC
II
~
['v I IV
LOGIC
GLOBAL
REGISTERS
OUTPUT PORT
'\
r-~
6
IACKN
.VSS1
I
;::
~
j
BLOCK B
(SAME AS A)
I
-VCC
IPCR
=~=A=CR=~~-
I
I
hOB
DUART
COMMON
+..l
STATE
DETECTORS (4)
f----+---Ir--t
INTERRUP ARBITRATION
IRON
~
IL
I
I
TXDC
10[300]0
SR
I
CHANNEL B
DUARTCD
RXDD
MR1,2
CR
I
I/
RXDC
I
- - - - - RxDA
l'J: -+ (AS ABOVE)
J
1-,!lllr~==::=§~~::=:~-,
INPUT PORT
~
i i
CHANGE-OFI
, - - - - - - - , 18
BAUD RATE
GENERATOR
TXDD
RECEIVE SHIFT
REGISTER
/L
POWER UP-DOWN
LOGIC
X2
I
L~J!~~~======~~
'~
1----_
r-
TxDA
RECEIVE HOLD
REGISTER (3)
v
I
I
DACKN . _ - - - - - - - '
f------
TRANSMIT SHIFT
REGISTER
~
1
I RIWCONTROL I
----"1L,..~====~~
llMING
CHANNEL A
TRANSMIT HOLD
REGISTER
f-- -
OPERATION CONTROL
BLOCK A
I
,-
----<1
TIMING
RON _ _ _ _~
I
"-..,-----,/
BUS BUFFER
L..._ _ _ _ _.....r
WRN
CEN --6--~
A[500] --7"----1
DUARTAB
r--------------------,
8
l'-. /
...-------, A
CLOCK
SELECTORS
I
C~~~~RI
I
I
ACR
CTUR
r
CTLR
II
I
I i
I
I
:
I
I
I
I
I
I
I
I
I
II
I ___________ ..JI
L
II
L ____________________ ..J
223
Preliminary Specification
Philips Components-Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
(QUART)
SC26C94/SC68C94
PIN DESCRIPTION
MNEMONIC
CEN
TYPE
NAME AND FUNCTION
I
Chip Select: Active low input that, in conjunction with RON or WRN, indicates that the control processor is trying
to access a OUART register.
A5:0
I
07:0
1/0
RON
I
Read Strobe: Active low input. When this line is asserted simultaneously with CEN, the SC26C94/SC68C94 places
the contents of the register selected by A[5:0] on the 0[7:0] lines.
WRN
I
Write Strobe: Active low input. When this line is asserted simultaneously with CEN, the SC26C94/SC68C94 writes
the data on 0[7:0] into the register selected by A[5:0].
OACKN
0
Data ACKnowledge: Active low, open-drain output to the control processor, which is asserted subsequent to a read
or write operation. For a read operation, assertion of OACKN indicates that register data is valid on 0[7:0]. For a
write operation, it indicates that the data on 0[7:0J has been captured into the indicated register. This signal
corresponds to READYN on 80x86 processors and OTACKN on 680xO processors.
IRON
0
Interrupt Request: This active low open-drain outputto the control processor indicating that one or more of the UART
channels has reached an interrupt value which exceeds that pre-programmed by host software. The IRON can be
used directly as a 680xO processor input; it must be inverted for use as an 80x86 interrupt input. This signal requires
an extemal pull-up resistor.
IACKN
I
Interrupt ACKnOWledge: Active low input indicating that the control processor is acknowledging an interrupt requested by this device. The SC26C94/SC68C94 responds to the assertion of this signal by placing an interrupt vector
on 0[7:0J and asserting OACKN.
TDa-d
0
ROa-d
I
I/OOa-d
1/0
Input/Output 0: A multi-use input or output signal for each UART. These pins can be used as general purpose inputs,
Clear to Send inputs, lX or 16X Transmit Clock outputs or general purpose outputs. Change-of-state detection is
provided for these pins.
I/0la-d
I/O
Input/Output 1 : A multi-use input or output signal for each UART. These pins can be used as general purpose or
1X or 16X transmit clock inputs, or general purpose 1X or 16X receive clock outputs. Change-of-state detection is
provided for these pins. In addition, 1101 a and 1101 c can be used as Countermmer inputs and 1101 band 1/01 d can
be used as Countermmer outputs.
1/02a-d
1/0
Input/Output 2: A multi-use input or output signal for each UART. These pins can be used as general purpose inputs,
lX or 16X receive clock inputs, general purpose outputs, RTS output or lX or 16X receive clock outputs.
1/03a-d
1/0
Input/Output 3: A multi-use input or output signal for each UART. These pins can be used as general purpose inputs,
lX or 16X transmit clock inputs, general purpose outputs, or 1X or 16X transmit clock outputs.
RESET
I
Master Reset: Active high reset for the SC26C94/SC68C94 logic. Must be asserted at power-up, may be asserted
at other times that the system is to be reset and restarted. Registers reset. MR pointer, CIR, IRON, OTACKN, IVR
Interrupt Vector, Power Oown, Test registers, FIFO pointers, Baud rate generator, Error Status, Watch Oog Timers,
IMR, Change of State detectors, counterltimer to timer, Transmitter and Receiver controilers.
Xl/ClK
I
Crystal 1 or Communication Clock: This pin can be connected toone side of a3.6864MHz or a 7.3728MHz crystal,
or can be connected to a TIL-level clock with the same frequency.
0
Crystal 2: If a crystal is used, this pin should be connected to its other terminal. If a TTL-level ciock is applied to
Xl, this pin should be left unconnected.
X2
Address Lines: These inputs select a SC26C94/SC68C94 register to be read or written by the control processor.
B-bit Bidirectional Data Bus: Used by the control processor to read and write SC26C941SC68C94 registers.
Transmit Data: Serial outputs from the four UARTs.
Receive Data: Serial inputs to the four UARTs/
BLOCK A
BUS
INTERFACE
'-rl
I
A[5:01 - D[7:OI~
I
INTERRUPT CONTROL
I
t
f-- ~
f--H
j.- f----
UARTSAIB
+
H
DACKN IACKN - -
COUNTER/TIMER
110 PORT CONTROL
BLOCKB
UARTS C/D
I/O CONTROL
I/O PORT CONTROL
r
l-
f----
f--
Figure 1. Channel Architecture
November 12, 1990
224
BAUD
RATE
GENERATOR
Preliminary Specification
Philips Components-Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
(QUART)
Table 1.
QUART Registers
A5:O
READ (RON
Reg~ter
=Low)
a (MRca. MRta. MR2a)
WRITE (WRN
=Low)
Mode Register a (MROa. MRIa. MR2a)
00000o
Mode
OOOOOt
Status Register a (SRa)
Clock Select Register a (CSRa)
ooootO
Reserved
Command Register a (eRa)
OOOtOO
Receive Holding Register a (RxFIFOa)
Transmit Holding Register a (TxFIFOa)
OOtOOO
Input Port Change Reg ab (IPCRab)
Auxiliary Control Reg ab (ACRab)
000101
Interrupt Statue Reg ab (ISRab)
Interrupt Mask Reg ab (IMRab)
000110
CounterlTimer Upper ab (ClUab)
Coun1ermlTJ9r Upper Reg ab (CTURabl
Counterllimer Lower Reg ab (CTlRab)
000111
CounterlTimer Lower ab (CTLab)
OOtOOO
Mode Register b (MROb. MRlb. MR2b)
Mode Reglsterb (MROb. MRlb. MR2b)
001001
Status Register b (SRlb, SR2b)
Clock Select Register b (CSRb. CS Rb)
001010
Reserved
Corrmand Register b (CAb)
001011
Receive Holding Register b (RxFIFOb)
Transmit Holding Register b (TxFIFOb)
001100
Output Port Register ab (OPRab)
Output Port Register ab (OPRab)
001101
Input Pon Register all (IPRab)
va Port Register a (IOPRa)
001110
Start Counter ab
110 Port Register b (KlPRb)
001111
Stop Counter ab
Reserved
010000
Mode Register e (MRDe, MR1e. MR2e)
Mode Register e (MROc., MR1e. MR2e)
010001
Status Register e (SRe)
Clock Select Register c (CSRe)
010010
Reserved
Command Register e (CRe)
010011
Receive Holding Register c (AxFIFOe)
Transmit Holding Register e (TxFIFOc)
010100
Input Port Change Reg cd (IPCRcd)
Auxiliary Control Reg cd (ACRed)
010101
InterruJ,:i Status Reg ed (IS Red)
Interrupt Mask Reg ed (lMRcd)
010110
CounterlTimer Upper ed (CTUed)
Countermmer Upper Reg ed (CTURed)
010111
CounterlTlmer Lower ed (CTLcd)
CounterlTimer L0'N9r Reg ed (CTLRcd)
011000
Mode Register d (MROd, MRld. MR2d)
Mode Registerd (MROd, MAid. MR2d)
011001
Status Register d (SRd)
Clock Select
011010
Reserved
Command Register d (CRd)
Reg~ter d
(CSRd)
011011
Receive Holding Register d (RxFIFOd)
Transmit Holding Register d (TxFIFOd)
011100
Output Port Register cd (OPRcd)
Output Port Register cd (OP Red)
011101
Input Port Register ed (IPRcd)
011110
Start Counter cd
va Port Register e (IOPRe)
va Port Register d (IOPRd)
011111
Stop Counter cd
Reserved
100000
Bidding Control Register a (BCRa)
Bidding Control Register a (BCRa)
100001
Bidding Control Register b (BCRb)
Bidding Control Register b (BCRb)
100010
Bidding Control Register c (BCRe)
Bidding Control Register e (SCRe)
100011
Bidding Control Register d (BCAd)
Bidding Control Register d (BCRd)
100100
Reserved
Power Down
100101
Reserved
Power Up
100110
Reserved
D~able
100111
Reserved
Enable DACKN
101000
Current Interrupt Register (CIR)
Reserved
101001
Global Interrupt Channel Reg (GICA)
Interrupt Vector Register (IVR)
101010
G_llnt Byte Count Reg (GIBCR)
UpdateCIR
101011
Global Receive Holding Reg (GRxFIFO)
Global Transmit Holding Reg (GTxFIFO)
101100
Interrupt Control Register (ICA)
Interrupt Control Register (ICRl
101101
Reserved
Test 3
101101
Reserved
Set XI/ClK Normal
101111
Reserved
Set XI/ClK 10 divide by two
11 0000-111 000
Reserved
ReselVed
111001
Tesl Mode
Test Mode
111010-111111
Reserved
Reserved
November 12,1990
225
DACKN
SC26C94/SC68C94
Philips Components-Signetics Data Communication Products
Preliminary Specification
Quad universal asynchronous receiver/transmitter
(QUART)
FUNCTIONAL BLOCKS
The QUART is composed of four Signetics
industry-standard UARTs, each having a
separate transmit and receive channel.
The Basic UART cells in the QUART are
configured with 8-byte Receive FIFOs and
8-byte Transmit FIFOs. Hardware supports
interrupt priority arbitration based on the
number of bytes available in the transmit and
receive FIFOs. Attempts to push a full FIFO
or pop an empty FIFO do not affect the count.
Baud Rate Generator
The baud rate generator used in the QUART
is the same as that used in other Signetics
industry standard UARTs. It provides 18
basic Baud rates from 50 baud to 38,400
baud. It has been enhanced to provide to
provide other baud rates up to 230,400 baud
based on a 3.6364MHz clock. With a
7.272800MHz clock 460,800 baud is
available.
BLOCK DIAGRAM
As shown in the block diagram, the QUART
consists of: data bus buffer, interrupt control,
operation control, timing, and four receiver
and transmitter channels. The four channels
are divided into two different blocks, each
block independent of the other (see Figure 1).
Channel Blocks
There are two blocks (Figure 1), each
containing two sets of receiver/transmitters.
In the following discussion, the description
applies to Block A which contains channels a
and b. However, the same information
applies to all channel blocks.
Data Bus Buffer
The data bus buffer provides the 'interface
between the external and internal data buses.
It is controlled by the operation control block
to allow read and write operations to take
place between the controlling CPU and the
QUART.
Operation Control
The operation control logic receives operation
commands from the CPU and generates
appropriate signals to internal sections to
control device operation. It contains address
decoding and read and write circuits to permit
communications with the oontrol processor
via the data bus buffer. The functions
performed by the CPU read and write
operations are shown in Table 1.
Mode registers (MR) 0, 1 and 2 are accessed
via an address counter. This counter is set to
one (1) by reset for compatibility with other
Signetics UARTs. It is set to 0 via a
command to the Command Register (CR).
The address counter is incremented with
each access to the MR until it reaches 2 at
November 12, 1990
which time it remains at 2. All subsequent
accesses to the MR will be to MR2 until the
MR counter changed by a reset or an MR
counter command.
The Mode Registers control the basic
configuration of the UART channels. There is
one for each UART. (Transmitter/receiver
pair)
Timing Circuits
The timing block consists of a crystal
oscillator, a baud rate generator, a
programmable 16-bit counter/timer for each
block, and two clock selectors.
Oscillator
The crystal oscillator operates directly from a
3.6864MHz crystal connected across the XI/
ClK and X2 inputs with a minimum of
external components. "an external clock of
the appropriate frequency is available, it may
be connected to Xl/ClK. "an external clock
is used instead of a crystal, XI must be
driven and X2 left floating as shown in Figure
8. The clock serves as the basic timing
reference for the baud rate generator (BRG),
the oounter/timer, and other internal circuits.
A clock frequency, within the limits specified
in the electrical specifications, must be
supptied even if the internal BRG is not used.
Baud Rate Generator
The baud rate generator operates from the
oscillator or external clock input and is
capable of generating 18 commonly used
data oommunications baud rates ranging
from 50 to 38.4K baud. Thirteen of these are
available simultaneously for use by the
receiver and transmitter. Eight are fixed, and
one of two sets of five can be selected by
programming ACR[71. The clock outputs from
the BRG are at 16X the actual baud rate. The
counter/timer can be used as a timer to
produce a 16X clock for any other baud rate
by counting down the crystal clock or an
external clock. The clock selectors allow the
independent selection, by the receiver and
transmitter, of any of these baud rates or an
external timing signal.
Counter/Timer (CIT)
The counter timer is a 16-bit programmable
divider that operates in one of three modes:
counter, timer, time out. In the timer mode it
generates a square wave. In the counter
mode it generates a time delay. In the time
out mode it monitors the time between
received characters. In this mode it is acting
as a programmable watch dog timer.
The CfT uses the numbers loaded into the
Countermmer lower Register (CTlR) and
the Countermmer Upper Register (CTUR) as
its divisor.
226
SC26C94/SC68C94
There are two counter/timers in the QUART;
one for each DUART. The counter/timer
clock source and mode of operation (counter
or timer) is selected by the Auxiliary Control
Register bits 6 to 4 (ACR[6:4]). The output of
the counterltimer may be used for a baud
rate andlor may be output to the I/O pins for
some external function that may be totally
unrelated to data transmission. The
counter/timer also sets the oounter/timer
ready bit in the Interrupt Status Register
(ISR) when its output transitions from 1 to O.
A register read address is reserved to start
counter/timer command and a second
register read address is reserved to issue a
stop command. The START command
always toads the contents of CTUR, CTlR, to
the counting registers. The STOP command
always resets the ISR[31 bit in the interrupt
status registers. See Table 1.
TfmerMode
In the timer mode a symmetrical square wave
is generated whose l!a!l..Qeri.QQ is equal in
time to division of the selected counter/timer
clock frequency by the 16-bit number loaded
in the CTlR CTUR. Thus, the frequency of
the counter/timer output will be equal to the
counter/timer clock frequency divided by
twice the value of the CTUR CTlR. While in
the timer mode the ISR bit 3 (ISR[3]) will be
set each time the oounter/timer transitions
from 1 to O. (High to low) This continues
regardless of issuance of the stop counter
command. ISR[3] is reset by the stop
counter command. NOTE: Reading of the
CTU and CTl registers in the timer mode is
not meaningful.
Counter Mode
In the counter mode the counter/timer oounts
the value of the CTlR CTUR down to zero
and then sets the ISR[3] bit and sets the
counter/timer output from 1 to O. It then rolls
over to 65,365 and continues counting with
no further observable effect.
Reading the CIT in the oounter mode outputs
the present state of the CfT. "the CfT is not
stopped, a read of the CfT may result in
changing data on the data bus.
Timeout Mode
The timeout mode uses the received data
stream to control the counter. Each time a
received character is transferred from the
shift register to the RxFIFO, the counter is
restarted. " a new character is not received
before the counter reaches zero count, the
counter ready bit is set, and an interrupt can
be generated. This mode can be used to
indicate when data has been left in the Rx
FIFO for more than the programmed time
limit. "the receiver has been programmed to
interrupt the CPU when the receive FIFO is
full, and the message ends before the FIFO
Preliminary Specification
Philips Components-Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
(QUART)
is full, the CPU will not be interrupted for the
remaining characters in the RxFIFO.
By programming the CIT such that it would
time out in just over one character time, the
above situation could be avoided. The
processor would be interrupted any time the
data stream had stopped for more than one
character time. NOTE: This is very similar to
the watch dog timer controlled by MRO. The
difference is in the programmability of the
delay time.
This mode is enabled by writing the
appropriate command to the command
register. Writing an 'Ax' to CRA or CRB will
invoke the timeout mode for that channel.
Writing a 'Cx' to CRA or CRB will disable the
timeout mode. The timeout mode should only
be used by one channel at a time.
The timeout mode disables the regular
START/STOP counter commands and puts
the CIT into counter mode under the control
of the received data stream. Each time a
received character is transferred from the
shift register to the RxFIFO, the CIT is
stopped after one CIT clock, reloaded with
the value in CTUR and CTLR and then
restarted on the next CfT clock. If the CfT is
allowed to end the count before a new
character has been received, the counter
ready bit, ISR[3], will be set. If IMR]3] is set,
this will generate an interrupt. Since receiving
a character restarts the CIT, the receipt of a
character after the CfT has timed out will
clear the counter ready bit, ISR[3], and the
interrupt. Invoking the 'Set Timeout Mode On'
command, CRx='Ax', will also clear the
counter ready bit and stop the counter until
the next character is received.
The counter timer is controlled with six
commands: Start/Stop CfT, Read/Write
Counterffimer lower register and Read/Write
Counterffimer upper register. These
commands have slight differences depending
on the mode of operation. Please see the
detail of the commands under the CTLR
CTUR Register descriptions.
Receiver and Transmitter
The QUART has four full-duplex
asynchronous receiveritransmitters. The
operating frequency for the receiver and
transmitter can be selected independenUy
from the baud rate generator, the
counterltimer, or from an external input.
Registers associated with the
communications channel are the mode
registers (MRO, MRl and MR2) Clock Select
Register (CSR), Command Register (CR),
Status Register (SR), Transmit FIFO
(TxFIFO), and the Receive FIFO (RxFIFO).
The transmit and receive FIFOs are each
November 12, 1990
eight characters deep. The receive FIFO
also stores three status bits with each
character.
Transmitter
The transmitter accepts parallel data from the
CPU and converts it to a serial bit stream on
the TxD output pin. It automatically sends a
start bit followed by the programmed number
of data bits, an optional parity bit, and the
programmed number of stop bits. The least
significant bit is sent first. Following the
transmission of the stop bits, if a new
character is not available in the TxFIFO, the
TxD output remains high and the TxEMT bit
in the SR will be set to 1. Transmission
resumes and the TxEMT bit is cleared when
the CPU loads a new character in the
TxFIFO. In the 16X clock mode, this also resynchronizes the internal 1X transmitter clock
so that transmission of the new character
begins with minimum delay.
The transmitter can be forced to send a break
(continuous Low condition) by issuing a start
break command via the CR. The break is
terminated by a stop break command. If the
transmitter is disabled, it continues operating
until the characters currently being
transmitted and the character in the TxFIFO,
if any, are completely sent out. Characters
cannot be loaded in the TxFI FO while the
transmitter is disabled.
Receiver
The receiver accepts serial data on the RxD
pin, converts the serial input to parallel
format, checks for start bit, stop bit, parity bit
(if any), or break condition, and presents the
assembled character to the CPU. The
receiver looks for a High-to-Low
(mark-to-space) transition of the start bit on
the RxD input pin. If a transition is detected,
the state of the RxD pin is sampled again
each 16X clock for 7-112 clocks (16X clock
mode) or at the next rising edge of the bit
time clock (lX clock mode).
If RxD is sampled High, the start bit is invalid
and the search for a valid start bit begins
again. If RxD is still Low, a valid start bit is
assumed and the receiver samples the input.
This continues at one bit time intervals, at the
theoretical center of the bit, until the proper
number of data bits and the parity bit (if any)
have been assembled, and one stop bit has
been detected. The data is then transferred
to the RxFIFO and the RxRDY bit in the SR
is set to a one. If the character length is less
than eight bits, the most significant unused
bits in the RxFI FO are set to zero.
After the stop bit is detected, the receiver will
immediately look for the next start bit.
However, if a non-zero character was
received without a stop bit (i.e. framing error)
227
SC26C94/SC68C94
and RxD remains low for one-half of the bit
period after the stop bit was sampled, then
the receiver operates as if a new start bit
transition had been detected at that point
(one-half bit time after the stop bit was
sampled). The parity error, framing error and
overrun error (if any) are strobed into the SR
at the received character boundary, before
the RxRDY status bit is set.
If a break condition is detected (RxD is low
for the entire character including the stop bit),
only one character consisting of all zeros will
be loaded in the FIFO and the received break
bit in the SR is set to 1. The RxD input must
return to a high condition for two successive
clock edges of the 1X clock (internal or
external) before a search for the next start bit
begins.
RECEIVER FIFO
The RxFIFO consists of a first-in-first-out
(FIFO) with a capacity of eight characters.
Data is loaded from the receive shift register
into the top-most empty position of the FIFO.
The RxRDY bit in the status register (SR) is
set whenever one or more characters are
available to be read, and a FFULL status bit
is set if all eight stack positions are filled with
data. The number of filled positions is
encoded into a 3-bit value. This value is sent
to the interrupt bidding logic where it is used
to generate an interrupt. A read of the
RxFIFO, outputs the data at the top of the
FIFO. After the read cycle, the data FIFO and
its associated status bits are 'popped' thus
emptying a FIFO pOSition for new data.
NOTE: The number of filled positions in the RxFtFO is
coded as one (1) less than the actual number. Thus, three
filled positions is coded as two, B filled is coded as 7. etc.
In addition to the data word, three status bits
(parity error, framing error, and received
break) are appended to each data character
in the FIFO. Status can be provided in two
ways, as programmed by the error mode
control bit in the mode register. In the
'character' mode, status is provided on a
character-by-character basis: the status
applies only to the character at the top of the
FIFO. In the 'block' mode, the status provided
in the SR for these three bits is the logical
OR of the status for all characters coming to
the top of the FIFO since the last reset error
command was issued. In either mode,
reading the SR does not affect the FI FO. The
FIFO is 'popped' only when the RxFIFO is
read. Therefore, the SR should be read prior
to reading the corresponding data character.
If the FIFO is full when a new character is
received, that character is held in the receive
shift register until a FIFO position is available.
If an additional character is received while
this state exists, the contents of the FIFO are
not affected: the character previously in the
Preliminary Specification
Philips Components--Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
SC26C94/SC68C94
(QUART)
shift register is lost and the overrun error
status bit, SR[4J, will be set upon receipt of
the start bit of the new (overrunning)
character.
A "watch dog" timer is associated with lllIch
re~iver. Its interrupt is enabled by MRO[7j.·
The purpose of this timer to alert the control
processor that characters are in the RxFIFO
which have not been read. This situation
may occur at the end of a transmission when
the last few characters received are not
sufficient to cause an interrupt.
This counter times out after 64 bit times. It is
reset each time a character is transferred
from the Receive shift register to the RxFIFO.
WAKE-UP MODE
In addition to the normal transmitter and
receiver operation described above, the
OUART incorporates a special mode which
provides automatic "wakeup" of a receiver
through address frame (or character)
recognition for multi-processor or
multi-station communications. This mode is
selected by programming MR1[4:3J to '11'.
In this mode of operation a 'master' station
transmits an address character to the several
'slave' stations on the line. The address
character is identified by setting its parity bit
to 1. The slave stations will usually have
their receivers partially enabled as a result of
setting MR1[4:3J to 11. When the receivers
see a parity bit.set to one they will load that
character to the RxFIFO and set the RxRbY
bit in the status register. The user would usually set the receiver interrupt to occur on
RxRDY as well. (All characters whose parity
bits are set to 0 will be ignored). The local
processor at the slave station will read the
'address' character just received. The master
will normally follow an address character(s)
with data characters. Since the data characters transmitted by the master will have their
parity bits set to zero, stations other than the
addressed one(s) will ignore the data.
A transmitted character consists of a start bit,
the programmed number of data and stop bits
and an "address/data" bit. The parity bit is used
as the address or data indicator. The polarity
of the AID bit is selected by setting MRI [2J to
zero or one; zero indicates that the current byte
is data, while one indicates that the current byte
is addresses. The desired polarity of the AID bit
(parity) should be programmed l2.el2rl! the
TxFIFO is loaded.
While in this mode, the receiver continuously
looks at the received data stream, whether it
is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character in
the RxFIFO if the received AID bit is a one,
but discards the received character if the
November 12,1990
received AID bit is a zero. If enabled, all
received characters are then transferred to
the CPU via the RxFIFO. In either case, the
data bits are loaded in the data FIFO while
the AID bit is loaded in the status FIFO
position normally used for parity error (SR[5J).
Framing error, overrun error, and break detect
operate normally whether or not the receiver
is enabled.
INPUT OUTPUT (1/0) PINS
There are 16 multi-use pins; four for each
UART. These pins are accessed and controlled
via the Input Port Register (IPR), I/O Port
Control Register (IOPCR), Input Port Change
Register (IPCR), and Output Port Register
(OPR). They may be individually programmed
to be inputs or outputs.
I/OOx and I/Olx pins have change of state
detectors. The change of state detectors
sample the input ports every 26.04f1s and set
the change bit in the IPCR if the pin has
changed since it was last read. Whether the
pins are programmed as inputs or outputs the
change detectors still operation and report
changes accordingly. See the register
descriptions of the I/O ports for the detailed
use of these features.
Interrupt Priority Logic
The interrupt logic compares all active
interrupts in the OUART, periodically
selecting the highest priority interrupt for
comparison to an Interrupt Threshold value.
User programmable register fields allow the
system programmer to tailor which interrupt
conditions are more important than others.
Programmable interrupt priorities allow timely
response to critical interrupts or simply allow
a single CPU to service a greater number of
interrupt situations than it could using more
conventional methods.
(IMR) bit as Signetics UARTs have always
been (the receiver timequt function is enabled
by a bit in the new MRO register). Those
interrupt sources that are enabled provide the
interrupt priority logic with an 8 bit value,
considered as an unsigned integer for
purposes of this discussion. Those interrupt
sources that are disabled do not provide a
value to the arbitration logic. This can be
accomplished by forcing an all zero value of
by inhibiting the EVAL signal, described
below, in the disabled interrupt sources.
This integer (called a "bid" since each
interrupt is vying for attention) is a
concatenation of fixed fields and user
programmable fields. The fixed fields are
channel number, interrupt type and (for
receiver and transmitter types) byte count
values. During the "bid arbitration" process,
all the bids from enabled sources are
presented, simultaneously, to an internal
Interrupt Bus. The bidding system and
formats are discussed in more detail in the
following sections.
The interrupt arbitration logic insures that the
interrupt with the numerically largest "bid"
value will be the only source driving the
Interrupt Bus at the end of the arbitration
period. The winner must continue to drive
the Interrupt Bus long enough to insure
capture by the Interrupt Bus Latches. At the
beginning of the next arbitration' cycle, all
"enabled bidders" drive their current values
onto the Interrupt Bus.
The value of the winning bid is compared to
the Interrupt Threshold field of the Interrupt
Control register which determines if an
interrupt should be generated by asserting
IRON. Winning bids with values below the
interrupt threshold do not generate an
interrupt.
Priority Arbitration and Bidding
Overview
The interrupt logic produces a numeric code
that identifies the highest priority interrupt
condition currently pending. This code is
compared against a programmable Interrupt
Threshold register which determines whether
the IRON pin is asserted. If the code is
currently greater than the programmed value,
I RON is asserted. In the OUART there are
18 interrupt sources:
1. Four receiver data transfer/space filled
functions
2. Four receiver break detected conditions
3. Four transmitter FIFO space available
events
4. Two counter timer interrupts
5. Four change of state detectors
Each interrupt source is enabled or disabled
by the appropriate Interrupt Mas.k Register
228
Each of the five "types" of interrupts has
slightiy different "bid" value, as follows:
Receivers
# rcv'd
rEr
3
1
Transmitters
0
# avail
3
I Chan # I
I
2
I I
Break Detect
Programmable
3
Change of State
I
I Programmable
0
2
10
I 0 I Chan # I
2
0 10
I I Chan # I
3
CounterlTimer
IProgrammable I 0 I
2
I Chan # I
2
10 1
I Chan # I
2
Philips Components-Signetics Data Communication Products
Preliminary Specification
Quad universal asynchronous receiver/transmitter
(QUART)
Bits shown above as '0' or '1' are hard-wired
inputs to the arbitration logic. Their presence
allows determination of the interrupt type and
they insure that no bid will have a value of all
zeros (a condition that is indistinguishable
from not bidding at all). They also serve to
set a default priority among the
non-receive/transmit types when the
programmable fields are all zeros.
The channel number always occupies the two
LSBs. Inclusion of the channel number
insures that a bid value generated will be
unique and that a single ''winner'' will drive
the Interrupt Bus at the end of the arbitration
interval. The channel number portion of each
UARTs bid is hard-wired with UARTa being
channel number 0 and so forth.
As can be seen above, bits 4:2 of the winning
bid value can be used to identify the type of
interrupt, including whether data was
received correctly or not. Like the Channel
number field, these bits are hard-wired for
each interrupt source.
The "# rcv'd" and "# avail" fields indicate the
number of bytes present in the receiver FI FO
and the number of empty bytes in the
transmitter FIFO, respectively. For both
these fields, the count is one less than the
actual number of bytes available.
NOTE: When there are zero bytes in the
receiver'S FIFO, it does NOT bid. Similarly, a
full transmitter FIFO makes NO bid. In the
case where all bids have been disabled by
the Interrupt Mask Register or as a result of
their byte counts, the active-low Interrupt Bus
will return FFh. This value always indicates
no interrupt source is active and IRON should
be negated.
The high order bit of the transmitter "bid" is
always zero. An empty transmit FIFO is,
therefore, fixed at a lower interrupt priority
than a 5/8 full receive FIFO. Bit 4 of a
receiver bid is the Receiver Error Bit (RER).
The RER is the OR of the parity, framing and
overrun error conditions. The RER does little
to modify the priority of receiver interrupts vs.
transmitter interrupts. It is output to the
Interrupt Bus to allow inclusion of good data
vs. problem data information in the Current
Interrupt Register.
The high order bits of bids for received break,
CoS (Change of State) and Countermmer
events are all programmable. By
programming ones in these fields, the
associated interrupt source can be made
more significant than most receiver and all
transmitter interrupts. Values near zero in
these fields makes them lower priority
classes of interrupt.
November 12, lGG0
As shown in Figure 2, the bid arbitration
process is controlled by the EVAUHOLDN
signal derived from the oscillator clock.
Receipt of an IACKN signal from the control
processor latches the latest ''winning bid"
from the latched Interrupt Bus into the
Current Interrupt Register (CIR). This logic is
diagrammed in Figure 3.
If the IACKN falling edge of Figure 1 occurs
during EVAL time, the result from the last
arbitration (captured by the Interrupt Bus
latches) is stored in CIR. Otherwise, the next
EVAL pulse is inhibited and the value in the
Interrupt Bus Latches is stored in CIR.
SC26C94/SC68C94
low, but the result on the interrupt bus line
was low, the logic disables less significant
bits, if any, from driving the interrupt bus. In
effect, the logic of all the active interrupt
sources acts together as a combinatorial
network to determine the highest priority
active interrupt. This network is best
understood as acting from the most
significant bit of the interrupt bus, in
sequence down to the least significant bit.
After a suitable settling time, the value on the
interrupt bus reflects the numerically highest
bid value among the active interrupt sources.
However, while the overall logic network is
settling, the logic at what what proves to be
the final winning interrupt source may find
itself temporarily losing at some of the less
significant bits.
Clearing the Interrupt
Activities which change the state of the ISR
will cause the IRON to assert or negate. In
addition, the accessing of a global or local
RxFIFO or TxFIFO reduces the associated
byte count for transmitter and receiver data
interrupts. If the byte count falls below the
threshold value, the interrupt request is
withdrawn. Other interrupt conditions are
cleared as on previous Signetics UARTs.
Once the interrupts is cleared or its byte
count value is reduced by one of the methods
listed above, a different bidder (or no bidder
at all) will win the on-going arbitration. When
the winning bid drops below the Interrupt
Threshold Register's value, the IRON pin will
negate.
Interrupt Priority Arbitration
Hardware
The hardware that resolves which interrupt
has the highest priority is shown conceptually
in Figure 3. The rising edge of the EVAL
signal begins an arbitration. All interrupt
sources drive their "bid" onto the active-low
Interrupt Bus. An open drain buffer is
employed at each bit position. Interrupt
sources that are not participating in the
arbitration, i.e., those that are disabled, do
not assert their Interrupt Bus drivers.
Each interrupt source in the OUART has its
own arbitration logic like that shown in Figure
3. Note that a one in a bit of a bid value
corresponds to a low on the Interrupt Bus line
to low (1 ), the result is a low (1) on that
Interrupt Bus bit regardless of what the other
interrupt sources are doing with respect to
that line. Thus each line acts as a wired OR.
At each bit position, the arbitration logic
compares the value of that bit of its bid value
against the OR'd result on that bit of the
Interrupt Bus. If it did not drive the line to
229
The winning value is captured on the trailing
edge of EVAL; the pulse with of EVAL must
be long enough for a worst-case combination
of bid values to resolve.
Arbitration" Aftermath
At the end of the arbitration, i.e., the falling
edge of EVAL, the winning interrupt source is
driving its Channel number, number of bytes
(if applicable) and interrupt type onto the
Interrupt Bus. These values are captured
into a latch by the trailing edge of EVAL. The
output of this latch is used by the Interrupt
Threshold comparator; the winning value is
captured into another set of latches called the
Current Interrupt Register (CIR) at the time of
an Interrupt Acknowledge cycle.
The Current Interrupt Register and
associated read logic is shown in Figure 3.
Interrupting channel number and the three bit
interrupt type code are readable via the
Internal Data Bus.
The contents of the appropriate receiver or
transmitter byte "counter", as captured at the
time of IACKN assertion, make up bits 7:5 of
the CIR. If the interrupt type stored in the
Current Interrupt Register is not a receiver or
transmitter data transfer type, the CIR[7:5]
field is read as the programmable fields of
their respective bid formats.
The buffers driving the CIR to the DBUS also
provide the means of implementing the
Global Interrupting Channel and Global Byte
Count Registers, described in a later section.
The winning bid channel number and
interrupt type fields can also be used to
generate part of the Interrupt Acknowledge
(lACK) Vector, as defined by the Interrupt
Control Register.
Preliminary Specification
Philips Components-Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
(QUART)
Interrupt Context
The channel number of the winning "bid" is
used by the address decoders to provide
data from the interrupting UART channel via
a set of Global pseudo-registers. The
interrupt Global pseudo-registers are:
1.
2.
3.
4.
Global Interrupting Byte Count
Global Interrupting Channel
Global Receive Holding Register
Global Transmit Holding Register
The first two Global "registers" are provided
by Current Interrupt Register fields as shown
in Figure 3. The interrupting channel number
latched in CIR modifies address decoding so
that the Receive or Transmit Holding
Register for the interrupting channel is
accessed during I/O involving the Global
Receive and Transmit Holding Registers.
Similarly, for data interrupts from the
transmitter and receiver, the number of
characters available for transfer to the CPU
or the number of transmit FIFO positions
open is available by reading the Global
Interrupt Byte Count Register. For non-data
interrupts, a read of the Global Interrupt Byte
Count Register yields an undefined value.
In effect, once latched by an lACK, the
winning interrupt channel number determines
the contents of the global registers. All
Global registers will provide data from the
interrupting UART channel.
Interrupt Threshold Calculation
The state of IRQN is determined by
comparison of the winning "bid" value to the
Interrupt Threshold field of the Interrupt
Control Register.
The logic of the bidding circuit is such that
when no interrupt source has a value greater
than the interrupt threshold then the interrupt
is not asserted and the CIR (Current Interrupt
Register) is set to all ones. When one or
more of the 18 interrupt sources which are
enabled via the IMR (Interrupt Mask Register)
exceed the threshold then the interrupt
threshold is effectively disconnected from the
bidding operation while the 18 sources now
bid against each other. The final result is that
the highest bidding source will disable all
others and its value will be loaded to the CIR
and the IRQN pin asserted low. This all
occurs during each cycle of the Xl,X2 crystal
clock.
Interrupt Note on 26C94.
For the receivers and transmitters, the
bidding of any particular unit may be held off
unless one of four FIFO fill levels is attained ..
This is done by setting the RxlNT and TxlNT
November 12, 1990
REGISTERS
bits in MRO and MRI to non-zero values.
This may be used to prevent a receiver or
transmitter from generating an interrupt
eventhough it is filled above the bid
threshold. Although this is not in agreement
with the idea that each enabled interrupt
source bid withe qual authority, it does allow
the flexibility of giving particular receiver or
transmitters more interrupt importance than
others.
The operation olthe QUART is programmed by
writing control words into the appropriate
registers. Operational feedback is provided via
status registers which can be read by the CPU.
Addressing of the registers is described in
Table 1.
The bit formats of the QUART registers are
depicted in Table 2.
Receiver interrupt fill level.
MRO[6]
MR1[6]
o
o
0
1
1
0
1
1
MRO - Mode Register 0
Mode Register 0 (MRO) is part of the UART
configuration registers. It controls the watch
dog timer and the encoding of the number of
characters received in the RxFIFO. The
lower four bits of this register are not
implemented in the hardware of the chip.
MRO should be set to only~. A
read of this register will return 1111 (Fh) in the
lower four bits. See note in Interrupt
Threshold Calculation.
Interrupl Condition
1 or more bytes in FIFO
(Rx ROY) default
3 or more bytes in FIFO
6 or more bytes in FIFO
8 or more bytes in FIFO
(Rx FULL)
MRO[5:4]- Tx interrupt filileve!.
MRO[5]
MRO[4]
o
o
0
1
1
0
1
1
The MRO register is accessed by setting the
MR Pointer to zero (0) via the command
register command 1011 (Bh).
Interrupt Condition
8 bytes empty
(Tx EMPTY) default
4 or more bytes empty
6 or more bytes empty
1 or more bytes empty
(Tx ROY)
Vectored Interrupts
The QUART responds to an Interrupt
Acknowledge (lACK) initiated by the host
MCU by providing an Interrupt Acknowledge
Vector on 07:0. The interrupt acknowledge
cycle is terminated with a OACKN pulse. The
vector provided by the QUART can have one
of the three forms under control of the IVC
control field (bits 1:0 of the Interrupt Control
Register):
With IVC
I
= 00 (lVR only)
IVR7:0
8
With IVC
I
= 01 (channel number)
IVR7:2
I Chan #
6
With IVC
I
2
= 10 (type & channel number)
I
I
IVR7:5
Type
Chan #
3 3 2
I
A code of 11 in the Interrupt Vector Control
Field of the ICR results in NO interrupt vector
being generatec;l. The extemal data bus will
be held in a high impedance state throughout
the lACK cycle. A OACKN will be generated
normally for the lACK cycle, however.
230
SC26C94/SC68C94
MRO[7]: This bit enables or disables the
RxFIFO watch dog timer.
MRO[7] = 1 enable timer
MRO[7] = 0 disable timer
MRO[6:4]: These bits should always be set to
zero.
MRO[3:0]: These bits are not implemented in
the chip. They could be used to control
hardware external to the chip.
MR1 - Mode Register 1
MRI is accessed when the MR pointer points
to MRI. The pointer is set to MRI by RESET
or by a set pointer command applied via the
CR. After reading or writing MR1, the pointers
are set at MR2.
MR1[7J - Receiver Request-Io-Send
Conlrol
This bit controls the deactivation of the RTSN
output (MPO) by the receiver. This output is
manually asserted and negated by
commands applied via the command register.
MR1[7] = 1 causes RTSN to be automatically
negated upon receipt of a valid start bit if the
receiver FIFO is full. RTSN is re-asserted
when an empty FIFO position is available.
This feature can be used to prevent overrun
in the receiver by using the RTSN output
signal to control the CTS input of the
transmitting device.
MR1[6] - Receiver Interrupt Selecll
This bit is reserved and should be set to O.
See note in Interrupt Threshold Calculation.
Philips Components-Signetics Data Communication Products
Preliminary Specification
Quad universal asynchronous receiver/transmitter
SC26C94/SC68C94
(QUART)
MR1[5] - Error Mode Select
This bit selects the operating mode 01 the
three FIFOed status bits (FE, PE, received
break). In the character mode, status is provided on a character-by-character basis; the
status applies only to the character at the top
olthe FIFO. In the block mode, the status provided in the SR lor these bits is the accumulation (Iogical-OR) 01 the status lor all characters coming to the top 01 the FIFO since the
last reset error command was issued.
MR1[4:3]- Parity Mode Select
II 'with parity' or 'Iorce parity' is selected, a
parity bitis added to the transmitted character
and the receiver performs a parity check on
incoming data. MR1[4:3] = 11 selects the
channel to operate in the special wake-up
mode.
MRl [2]- Parity Type Select
This bit selects the parity type (odd or even)
il the 'with parity' mode is programmed by
MRI [4:3], and the polarity 01 the lorced parity
bit il the 'foroe parity' mode is programmed.
It has no ellect il the 'no parity' mode is programmed. In the special 'wake-up' mode, it
selects the polarity 01 the transmitted AID bit.
MRl [1 :0]- Bits Per Character Select
This lield selects the number 01 data bits per
character to be transmitted and received. The
character length does not include the start,
parity, and stop bits.
Table 2.
I
Bit 7
I
Register Bit Formats
Rx
Watch·
dog
Timer
0=011
1 = on
RxlNT2
bit
1. Received data is re-clocked and
retransmitted on the TxD output.
2. The receive clock is used lor the transmitter.
3. The receiver must be enabled, but the
transmitter need not be enabled.
4. The TxRDY and TxEMT status bits are inactive.
5. The received parity is checked, but is not
regenerated lor transmission, i.e., transmitted parity bit is as received.
November 12, 1ggO
I
Bit4
TxlNT Control
These bits should be set to 0
I
Bit 3
I
IBit 2
I
Bitl
BitO
These bits not implemented. May be
used lor external control
(Reserved for future upgrades)
x
J
I
x
I
x
x
MRl (Mode Register 1)
RxRTS
Control
0= No
1 = Yes
RxINT1
Select
Error
Mode
Always
settoO
0= Char
1 = Block
Parity Mode
00 = With parity
01 = Force parity
10 = No parity
11 = Special mode
Parity
Type
Bits per Character
0= Even
1 = Odd
00 =5
01 =6
10 = 7
11 = 8
MR2 (Mode Register 2)
TxRTS
Conrol
Channel Mode
00 = Normal
01 = Auto-echo
10 = local loop
11 = Remote loop
O=No
1 = Yes
CTS
Enable Tx
0= No
1 = Yes
Stop Bit length'
0=0.5634 =0.813
1 = 0.625 5 = 0.875
2 = 0.688 6 = 0.938
3 = 0.7507 = 1.000
8 = 1.563 C = 1.813
9 = 1.625 D = 1.875
A = 1.688 E = 1.938
B = 1.750 F = 2.000
NOTE:
Add 0.5 to values shown above lor 0-7, if channel is programmed lor 5 bits/char.
CSR (Clock Select Register)
Receiver Clock Select
Transmitter Clock Select
See text
See text
CR (Command Register)
Disable
Tx
Miscellaneous Commands
0= No
1 = Yes
See text
MR2[7:6]- Mode Select
The QUART can operate in one 01 four
modes. MR2[7:6] = 00 is the normal mode,
with the transmitter and receiver operating independenlly. MR2[7:6] = 01 places the channel in the aulomatic echo mode, which automatically retransmits the received data. The
lollowing conditions are true while in automatic echo mode:
BitS
MRO (Mode Register 0)
MR2 - Mode Register 2
MR2 is accessed when the channel MR pointer points 10 MR2, which occurs after any access to MR 1. Accesses 10 MR2 do not
change the pointer.
I
Blt6
Enable
Tx
0= No
1 = Yes
Disable
Rx
0= No
1 = Yes
Enable
Rx
0= No
1 = Yes
SR (Status Register)
Rec'd.
Break
Framing
Error
Parity
Error
Overrun
Error
TxEMT
TxRDY
FFUll
RxRDY
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
O=No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
O=No
1 = Yes
0= No
1 = Yes
,
.
.
NOTE:
These status bits are appended to the corresponding data character in the receive FIFO. A read
01 the status register provides these bits [7:5] Irom the top 01 the FIFO Iogether with bits [4:0].
These bits are cleared by a reset error status command. In character mode, they must be reset
when the corresponding data character is read Irom the FIFO.
231
Preliminary Specification
Philips Components-Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
(QUART)
Two diagnostic modes can also be selected.
MR2[7:6] = 10 selects localloopback mode.
In this mode:
1. The transmitter output is internally connected to the receiver input.
2. Thetransmitclockis usedforthe receiver.
3. The TxD output is held high.
4. The RxD input is ignored.
5. The transmitter must be enabled, but the
receiver need not be enabled.
6. CPU to transmitter and receiver communications continue normally.
The second diagnostic mode is the remote
loopback mode, selected by MR2[7:6] = 11.
In this mode:
1. Received data is re-clocked and
retransmitted on the TXD output.
2. The receive clock is used for the
transmitter.
3. Received data is not sent to the local
CPU, and the error status conditions are
inactive.
4. The received parity is not checked and is
not regenerated for transmission, i.e., the
transmitted parity bit is as received.
5. The receiver must be enabled, but the
transmitter need not be enabled.
6. Character framing is not checked, and the
stop bits are retransmitted as received.
7. A received break is echoed as received
until the next valid start bit is detected.
When switching in and out of the various
modes, the selected mode is activated at the
completion of all transmitted and received
characters. Likewise, if a mode is deselected,
the device will switch out of the mode at the
completion of all transmit and/or receive
characters.
MR2[S]- Transmitter Request-to-Send
Control
Thi s bit controls the deactivation of the RTSN
output (MPO) by the transmitter. This output is
manually asserted and negated by appropriate
commands issued via the command register.
MR2[5] = 1 causes RTSN to be reset automatically one bit time after the characters in the
transmitshiflregister and in the TxFIFO (if any)
are completely transmitted (includes the programmed number of stop bits if the transmitter
is notenabled). This feature can be used to automatically terminate the transmission as fol,
lows:
1.
2.
3.
4.
5.
Program auto-reset mode: MR2[5] = 1.
Enable transmitter.
Assert RTSN via command.
Send message.
Verify the next to last character of the message is being sent by waiting until transmitter ready is asserted. Disable transmitter
after the last character of the message is
loaded in the TxFIFO.
November 12, 1990
Table 2_
I
Bit7
I
SC26C94/SC68C94
Register Bit Formats (Continued)
I
Bit 6
BitS
I
Blt4
I
Bit3
I
Bit2
I
Bit1
I
BltO
ACR (Auxiliary Control Register)
BRGSet
Select
CounterlTImer
Mode and Source
Delta
101b
Delta
lOOb
Delta
lOla
Delta
100.
0= set 1
1 = set 2
See text
0=011
1 =on
0=011
1 =on
0=011
1 = on
0=011
1 =on
IPCR (Input Port Change Register)
Delta
101b
Delta
100b
Delta
lOla
Delta
100a
101b
100b
lOla
100a
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
O=Low
1 = High
O=Low
I = High
0= Low
1 = High
o = Low
I = High
ISR (Interrupt Status Register)
10 Port
Change
o
=No
I = Yes
Delta
BREAKb
RxRDYI
FFULLb
TxRDYb
Counter
Ready
Delta
BREAKa
RxRDYI
FFUlLa
TxRDYa
0= No
I = Yes
0= No
I = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
I = Yes
0= No
1 = Yes
0= No
I = Yes
IMR (Interrupt Mask Register)
10 Port
Change
INT
Delta
BREAKb
INT
RxRDYI
FFUllb
INT
TxRDYb
INT
Counter
Ready
INT
Delta
BREAKa
INT
RxRDYI
FFULLa
INT
TxRDYa
INT
0=011
I =on
0=011
I =on
0= off
I =on
0=011
I = on
0=011
I =on
0=011
I =on
0=011
I = on
0=011
I =on
CllR (CounterlTimer lower Register)
IPR (Input Port Register)
103b
102b
103a
102a
101b
100b
lOla
100a
0= Low
1 = High
o = Low
0= Low
1 = High
0= Low
1 = High
0= Low
1 = High
0= Low
1 = High
0= Low
1 = High
0= Low
1 = High
1 = High
6. The last character will be transmitted and
RTSN will be reset one bit time after the last
stop bit.
MR2[4]- Clear-to-Send Control
The sate of this bit determines if the CTSN input
(10) controls the operation of the transmitter. If
this bit is 0, CTSN has no effect on the transmitter. If this bit is aI, the transmitter checks the
sate of CTSN each time it is ready to send a
character. If it is asserted (Low), the character
is transmitted. If it is negated (High), the TxD
output remains in the marking state and the
transmission is delayed until CTSN goes Low.
Changes in CTSN, while a character is being
transmitted do not affect the transmission of
that character. This feature can be used to prevent overrun of a remote receiver.
232
MR2[3:0]- Stop Bit Length Select
This field programs the length olthe stop bit appended to the transmitted' character. Stop bit
lengthsol9/16to 1 and 1-9/16 to 2bits, inincrements of 1/16 bit, can be programmed for character lengths of 6, 7, and 8 bits. For a character
length of 5 bits, 1-1I16to 2 stop bits can be programmed in increments of 1/16 bit. In all cases,
the receiver only checks for a mark condition at
the center of the first stop bit position (one bit
time after the last data bit, or after the parity bit
if parity is enabled). If an external IX clock is
used for the transmitter, MR2[3] = 0 selects one
stop bit and MR2[3] = 1 selects two stop bits to
be transmitted.
Preliminary Specification
Philips Components-Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
(QUART)
CSR - Clock Select Register
CSR(7:4)- Receiver Clock Selecl
When using a 3.6B64MHz crystal or external
clock input, this field selects Ihe baud rate clock
for the receiver as shown in Table 3.
Table 3.
The receiver clock is always a 16X clock, exceptforCSR[7:4] = 1111. 102x is external input.
CSR(3:0)- Transmitter Clock Selecl
This field selects the baud rate clock for the
transmitter. The field definition is as shown in
0101
Tesl3 = 1
ACR(7) = 1
ACR(7) =0
ACR(7) = 1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
50
110
134.5
200
300
600
1,200
1,050
2,400
4,BOO
7,200
9,600
3B.4K
Timer
102-16X
102-1X
75
110
3B.4K
150
300
600
1,200
2,000
2,400
4,BOO
1,BOO
9,600
19.2K
Timer
102-16X
102-1X
50
110
134.5
200
1BOO
3,600
7,200
1,050
14.4K
2B.BK
7,200
57.6K
230.4K
Timer
102-16X
102-1X
450
110
230.4K
900
1,BOO
3,600
7,200
2,000
14.4K
2B.BK
1,BOO
57.6K
115.2K
Timer
102-16X
102-1X
0110
CR(7:4)- Miscellaneous Commands
The encoded value of this field can be used to
specify a single command as follows:
0100
ACR(7) = 1
103x -16X
103x-1X
ACR(7) =0
CR is used to write commands to the Octal
UART.
0011
ACR(7) = 0
103x -16X
103x -IX
CSR(7:4)
CR - Command Register
0010
Table 3, except as follows:
CSR(3:0)
1110
1111
Baud Rate
Tesl3 =0
0000
0001
SC26C94/SC68C94
No command.
Reset MR pointer. Causes the MR
pointerto pointto MRI.
Reset receiver. Resets the receiver as if a hardware reset had been
applied. The receiver is disabled
and the FIFO pointer is reset to the
first location.
Reset transmitter. Resets the
transmitter as if a hardware reset
had been applied.
Reset error status. Clears the
received break, parity error,
framing error, and overrun error
bits in the status register(SR(7:4]}.
Used in character mode to clear
OE status (although RB, PE, and
FE bits will also be cleared), and in
block mode to clear all error status
after a block of data has been
received.
Reset break change interrupt.
Causes the break detect change
bit in the interrupt status register
(lSR[2 or 6]) to be cleared to zero.
November 12, 1990
0111
1000
1001
1010
Start break. Forces the TxD output
low (spacing). If the transmitter is
empty, the start of the break condition will be delayed up to two bit
times. If the transmitter is active,
the break begins when transmission of the character is completed.
If a character is in the TxFIFO, the
start of break is delayed until that
character or any others loaded after it have been transmitted
(TxEMT must be true before break
begins). The transmitter must be
enabled to start a break
Stop break. The TxD line will go
high (marking) within two bittimes.
TxD will remain high for one bit
time before the next character, if
any, is transmitted.
Assert RTSN. Causes the RTSN
output to be asserted (Low).
Negate RTSN. Causes the RTSN
output to be negated (High).
Set Timeout Mode On. The register in this channel will restart the CI
T as each receive character is
transferred from the shift register
to the RxFIFO. The CIT is placed
in the counter mode, the STARTI
STOP counter commands are disabled, the counter is stopped, and
the Counter Ready Bit, ISR[3]. is
reset
1011
Reserved.
233
1100
1101
111 x
Disable Timeout Mode. This command returns control of the CIT to
the regular START/STOP counter
commands. It does not stop the
counter, or clear any pending interrupts. After disabling the timeout
mode, a 'Stop Counter' command
should be issued.
Set MR pointer to O.
Reserved fortesting.
CR(3)- Disable Transmitter
This command terminates transmitter operation and resets the TxRDY and TxEMT status
bits. However, il a character is being transmitted or if a character is in the TxFIFO when
the transmitter is disabled, the transmission 01
the character(s) is completed before assuming
the inactive state.
CR(2)- Enable Transmitter
Enables operation of the transmitter. The
TxRDY status bit will be asserted.
CR(1)- Disable Receiver
This command terminates operation of the
receiver immediately - a character being
received will be lost. The command has no
effect on the receiver status bits or any other
control registers. If the special wake-up mode
is programmed, the receiver operates even if it
is disabled (see Wake-up Mode).
Preliminary Specification
Philips Components-Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
(QUART)
CR[O]- Enable Receiver
Enables operation of the receiver. If not in the
special wake-up mode, this also forces the
receiver into the search for start bit state.
SR - Channel Status Register
SR[7] - Received Break
This bit indicates that an all zero character of
the programmed length has been received
without a stop bit. Only a single FIFO position
is occupied when a break is received; further
entries to the FIFO are inhibited until the RxDA
line returns to the marking state for at least
one-half bit time (two successive edges of the
internal or external 1x clock).
When this bit is set, the change in break bit in
the ISR (ISR[S or 2]) is set. ISR[6 or 2] is also
set when the end of the break condition, as
defined above, is detected. The break detect
circuitry is capable of detecting breaks that
originate in the middle of a received character.
However, if a break begins in the middle of a
character, it must last until the end of the next
character in order for it to be detected.
SR[6] - Framing Error (FE)
This bit, when set, indicates that a stop bit was
not detected when the corresponding data
character in the FIFO was received. The stop
bit check is made in the middle of the first stop
bit position.
SR[S]- Parity Error (PE)
This bit is set when the 'with parity' or 'force
parity' mode is programmed and the
corresponding character in the FIFO was
received with incorrect parity. In special
'wake-up mode', the parity error bit stores the
received AID bit.
SR[4]- Overrun Error (OE)
This bit, when set, indicates that one or more
characters in the received data stream have
been lost. It is set upon receipt of a new
character when the FIFO is full and a character
is already in the receive shift register waiting for
an empty FIFO position. When this occurs, the
character in the receive shift register (and its
break detect, parity error and framing error
status, if any) is lost. This bit is cleared by a
reset error status command.
SR[3]- Transmitter Empty (TxEMlj
This bit will be set when the transmitter underruns, i.e., both the transmit holding register and
the transmit shift register are empty. This bit
and TxRDY are set when transmitter is first enabled after a disable transmitter command or
reset.
November 12, 1990
It is set after transmission of the last stop bit of
a character, if no character is in the TxFIFO
awaiting transmission.ltis reset when the TxFIFO is loaded by the CPU, or when the transmitter is disabled.
SR[2] - Transmitter Ready (TxRDY)
This bit, when set, indicates that the TxFIFO is
ready to be loaded with a character. This bit is
cleared when the TxFIFO is full and is set when
the character is transferred to the transmit shift
register. TxRDY is reset when the transmitter is
disabled and is set when the transmitter is first
enabled, e.g., characters loaded in the TxFIFO
while the transmitter is disabled will not be
transmitted.
SR[I]- FIFO Full (FFULL)
This bit is set when a character is transferred
from the receive shift register to the receive
FIFO and the transfer causes the FIFO to becomefull, i.e., all eight FIFO positions areoccupied. It is reset when the CPU reads the FIFO
and there is no character in the receive shift
register. If a character is waiting in the receive
shift register because the FI FO is full, FFUll is
not reset after reading the FIFO once.
SR[O]- Receiver Ready (RxRDY)
This bit indicates that a character has been received and is waiting in the FIFO to be read by
the CPU. It is set when the character is transferred from the receive shift registerto the FIFO
and reset when the CPU reads the RxFIFO,
and no more characters are in the FIFO.
ACR - Auxiliary Control Register
ACR[7] - Baud Rate Generator Set Select
This bit selects one of two sets of baud rates
generated by the BRG.
Set 1:
50, 110, 134.5, 200, 300, 600,
1.0Sk, 1.2k, 2.4k, 4.Bk, 7.2k, 9.6k,
and 3B.4k baud.
Set 2:
75, 110, 150,300,600, 1.2k, I.Bk,
2.0k, 2.4k, 4.Bk, 9.6k, 19.2k, and
3B.4kbaud.
SC26C94/SC68C94
Table 4,
ACR[6:4] CIT Clock
and Mode Select
[6:4]
Mode
Clock Source
oa a
aa I
a10
oI I
Counter
Counter
Counter
1 00
1
I
I I 0
a
TImer
TImer
TImer
I I I
TImer
10 pin
10 pin divided by 16
TxC-l X clock of the
transmitter A or C
Crystal or external
clock (Xl/ClK)
divided by 16
10 pin
10 pin divided by 16
Crystal or external
clock (XI/ClK)
Crystal or external
clock (XI/ClK)
divided by 16
Counter
ACR[3:0]-IOlb, 100b, lOla, 100a
Change-of-State Interrupt Enable
This field selects which bits of the input port
change register (IPCR) cause the input change
bit in the interrupt status register, ISR[7], to be
set. If a bit is in the 'on' state, the setting of the
corresponding bit in the IPCR will also result in
Ihe setting of ISR[7], which results in the generation of an inlerrupt output if I MR[7] = 1. If a bit
is in the 'off' state, the setting of that bit in the
IPCR has no effect on ISR[7].
IPCR - Input pon Change
Register
IPCR[7:4]-IOlb, 100b, lOla, 100a
Change-ol-State
These bits are set when a change of state, as
defined in the Input Port section of this data
sheet, occurs at the respective pins. They are
cleared when the IPCR is read by Ihe CPU. A
read of the IPCR also clears ISR[7], the input
change bit in the interrupt status register. The
setting ofthese bits can be programmed to generate an interrupt to Ihe CPU.
IPCR[3:0]-IOlb, 100b, lOla, 100a
Change-ol-State
These bits provide the current state of the respective inputs. The information is unlatched
and reflects the state of the inputs pins at the
time the IPCR is read.
ISR - Interrupt Status Register
The selected set of rates is available for use by
the receiver and transmitter.
ACR[6:4]- CounterlTimer Mode and Clock
Source Select
This field selects the operating mode of the
counter/timer and ils clock source (see Table
4).
234
This register provides the status of all potential
interrupt sources. The contents of this register
are masked by the interrupt mask register
(IMR). If a bit in the ISR is a 'I' and the corresponding bit in the IMR is also a 'I', the INTRN
output is asserted (low). If the corresponding
bit in the IMR is a zero, the state of the bit in the
ISR has no effect on the INTRN output. Note
that the IMR does not mask the reading of the
ISR; the true status is provided regardless of
the contents of the IMR.
Preliminary Specification
Philips Components-Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
SC26C94/SC68C94
(QUART)
ISR[7] - 10 Change-ol-State
This bit is set when a change-of-state occurs at
the 101 b, 100b, 101 a, 100a input pins. It is reset
when the CPU reads the IPCR.
ISR[6) - Channel b Change In Break
This bit, when set, indicates that the receiver
has detected the beginning or the end of a
receivedbreak.ltis reset when the CPU issues
a reset break change interrupt command.
ISR[S) - Receiver Ready or FIFO Full
Channelb
The function of this bit is programmed by
MRl [6). If programmed as receiver ready, it indicates that a character has been received and
is waiting in the FIFO to be read by the CPU. It
is set when the character is transferred from the
receive shift register to the FIFO and reset
when the CPU reads the receiver FIFO. If the
FIFO contains more characters, the bit will be
set again after the FI FO is read.
If programmed as FIFO full, it is set when a
character is transferred from the receive holding register to the receive FIFO and the transfer
causes the FIFO to become full, i.e., all three
FIFO positions are occupied. It is reset when
FIFO is read and there is no character in the receiver shift register. If there is a character waiting in the receive shift register because the
FIFO is full, the bit is set again when the waiting
character is transferred into the FIFO.
ISR[4) - Transmitter Ready Channel b
This bit is a duplicate of TxRDY (SR[2)).
ISR[3) - Counter Ready
In the counter mode of operation, this bit is set
when the counter reaches terminal count and
is reset when the counter is stopped by a stop
counter command. Itis initialized to '0' when the
chip is reset.
In the timer mode, this bit is set once each cycle
of the generated square wave (every other time
the CIT reaches zero count). The bit is reset by
a stop counter command. The command, however, does not stop the CIT.
ISR[2) - Channel a Change In Break
This bit, when set, indicates that the receiver
has detected the beginning or the end of a received break. It is reset when the CPU issues
a reset break change interrupt command.
ISR[l) - Receiver Ready or FIFO Full
Channel a
The function of this bit is programmed by
MRl [6). If programmed as receiver ready, it indicates that a character has been received and
is waiting in the FIFO to be ready by the CPU.
It is set when the character is transferred from
the receive shift register to the FIFO and reset
when the CPU reads the receiver FIFO. If the
FIFO contains more characters, the bit will be
set again after the FIFO is read. If programmed
November 12, 1990
as FIFO full, it is set when a character is transferred from the receive holding register to the
receive FIFO and the transfer causes the FIFO
to become full, i.e., all three FIFO positions are
occupied. It is reset when FIFO is read and
there is no character in the receiver shift register. If there is a character waiting in the receive
shift register because the FIFO is full, the bit is
set again when the waiting character is transferred into the FIFO.
ISR[O) - Transmitter Ready Channel a
This bit is a duplicate of TxRDY (SR[2)).
IMR - Interrupt Mask Register
The programming of this register selects which
bits in the ISR cause an interrupt output. If a bit
in the ISR is a .,. and the corresponding bit in
the IMR is a '1', the INTRN output is asserted
(low). If the corresponding bit in the IMR is a
zero, the state of the bit in the ISR has no effect
on the INTRN output. Note that the IMR does
not mask reading of the ISR.
CTUR and CTlR - Counter/Timer
Registers
The CTUR and CTlR hold the eight MSBs and
eightlSBs, respectively, olthe value to be used
by the counter/timer in either the counter or
timer modes of operation. The minimum value
which may be loaded into the CTURlCTlR
registers is H'0002'. Note that these registers
are write-only and cannot be read by the CPU.
In the timer (programmable divider) mode, the
CIT generates a square wave with a period of
twice the value (in clock periods) of the CTUR
and CTlR. If the value in CTUR or CTlR is
changed, the current half-period will not be
affected, but subsequent half-periods will be.
The CIT will not be running until it receives an
initial 'Start Counter' command (read at
address A3-AO = 1110). After this, while in
timer mode, the CIT will run continuously.
Receipt of a subsequent start counter
command causes the CiT to terminate the
current timing cycle and to begin a new cycle
using the values in the CTU Rand CTlR.
The counter ready status bit (ISR[3)) is set once
each cycle of the square wave. The bit is reset
by a stop counter command read with AS-AO =
H'P). The command, however, does not stop
the CIT. The generated square wave is output
on an 10 pin if it is programmed to be the CIT
output.
In the counter mode, the CIT counts down the
number of pulses loaded in CTURand CTlR by
the CPU. Counting begins upon receipt of a
start counter command. Upon reaching the
terminal count H'OOOO', the counter ready
interrupt bit (ISR[3)) is set. The counter
continues counting past the terminal count until
stopped by the CPU. If 10 is programmed to be
235
the output of the CIT, the output remains High
until the terminal count is reached, at which
time it goes low. The output returns to the High
state and ISR[3) is cleared when the counter is
stopped bya stop counter command. TheCPU
may change the values of CTUR and CTlR at
any time, but the new count becomes effective
only on the next start counter command. If new
values have not been loaded, the previous
values are preserved and used for the next
count cycle.
In the counter mode, the current value of the
upper and lower eight bits of the counter (CTU,
CTL) may be read by the CPU. It is
recommended that the counter be stopped
when reading to prevent potential problems
which may occur if a carry from the lower eight
bits to the upper eight bits occurs between the
times that both halves of the counter is read.
However, note that a subsequent start counter
command will cause the counter to begin a new
count cycle using the values in CTUR and
CTlR.
I/O lOGIC
Another difference between the QUART and
most other Signetics UART products is that
the QUART has four pins for each channel
which can be inputs or outputs, while
previous Signetics UART devices have
varying number of fixed-direction input pins
and output pins.
IPR (for DUART ab)
I 3b I 2b I 3a I 2a I 1blOb I la I Oa I
1
1
1
1
1
1
1
1
The state of all eight pins for each DUART
can always be read via the IPR.
IPCR (lor DUART ab)
la
1
1
1
1
1
I Oa I
1
IPR and IPCR are analogous to registers of
the same name in the SCC2698.
10PCR (for DUART ab)
1I03X use
2
I 102x use 1101 x use 1I00x use I
2
2
2
The configuration of I/O pins as inputs or
outputs in each UART channel is controlled
by a register called 10PCR (I/O Port Control
Register). This register generally replaces
the OPCR (Output Port Control Register) of
previous Signetics UARTs. The coding of the
10PCR control fields is shown in Figure 4.
OPR (for DUART ab)
I 3b I 2b I 3a I 2a I 1blOb I la I Oa I
1
1
1
1
1
1
1
1
For I/O pins that are selected for output port
control in 10PCR, this register controls their
Preliminary Specification
Philips Components-Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
SC26C94/SC68C94
(QUART)
state. The OPRs are readlwrite at address
OCh and 1Ch. Readlwrite output registers
optimize the changing of some bits without
affecting the state of other bits in the register.
generation by change of state of these inputs.
ACR[O] enables change of state interrupt on
100a, ACR[I] on lOla, ACR[2] on 100b and
ACR[3] on 101b.
to be inputs upon reset. Each UART channel
has two inputs, 100 and 101, that are
equipped with change detection. The ACR
(Auxiliary Control Register) controls interrupt
Each of a channel's 4 1/0 lines are configured
10PCR Control of 103:0 Pins for Each Channel
10PCR?
IOPCR6
IOPCR5
103x Control
00 = GPI or TxC in
01 = OPR3 out
10 = TxC16X out
11 =TxC1Xout
IOPCR4
IOPCR3
102x Control
00 = GPI or RxC in
01 = OPR2 (Note 1)
10 = RxC1X out
11 = RxC16X out
10PCRI
IOPCR2
101 x Control
00 = (Note 2)
01 = OPRI out
10 = (Note 3)
11 = RxC1Xout
10PCRO
100x Control
00 = GPI or CTS in
01 = OPROout
10 = TxC1X out
11 = TxC16X out
Note1: Bit 2 of the OPR is the Request to Send function that is affected by the Assert and Negate RTS commands
in CRA or CRB, and by the TxRTS feature if MR2x5 is 1, as well as by writing OPR. The RxRTS function, which is
activated if MRlx? is 1, does not affect OPR2 but merely blocks the output signal whenever the Rx FIFO is full.
Note 2: As for the other three pins, a 00 value in this field makes the 101 pin an input. 101 can always be used as
a General Purpose Input (GPI). lOla and 10Ic can be used as CTI depending on how ACR6:4 is programmed. If
OPCR?:6 is not 00, 101 can be used as TxC depending on how CSRx3:0 is programmed.
Note 3: A 10 value in this field makes 10Ib and 10Id outputthe CTO signal, and makes lOla and 10Ic output
RxC16x.
QUART REGISTERS vs 26988
As shown in Table 1, registers present in the
SCC2698's first four channels are present in
the QUART. Furthermore, they retain the
same addresses and functionally that they
possess in the 2698. Thus, the QUART is
compatible with existing software except for
the mUlti-purpose 1/0 and some interrupt
related functions.
100 Receiver break change
101 Countermmer
111 Receive available, wlerrors
With Type = XII, the # Bytes field indicates
the count of received bytes available for
reading, while with Type = xl0 it indicates the
number of bytes that can be written to the
transmit FIFO. With Type = xOx, the # Bytes
field is undefined.
The CIR is Read only at address 28H.
Similar to the GRxFIFO, no physical register
implementation exists. The byte is pushed
into the correct transmitter'S FIFO based on
the interrupting channel field of the Current
Interrupt Register.
If a transmitter is not the cause of the current
interrupt, a write to the Global TxFIFO has no
effect.
The GTxFIFO is Write only at address 2BH.
Revised Formats for Existing
Registers
Global Interrupt Byte Count (GIBC)
I
The function of bit 6 of the MR 1 register
(RxINT Select) has been superseded by the
new interrupt priority logic. This bit is now
reserved.
The ACR has analogous but slightly different
functions for bits 3:0 as described in the 1/0
Logic section.
The new format of the 10PCR, shown above,
does not provide for the power down bit. The
power down function is now set by a write to
QUART address 24H; power up is a write to
address 25H.
New Registers Required
Current Interrupt Register (CIR)
I
# Bytes
I
3
Type
3
I
Chan #
2
The Channel # field indicates which of the
four UARTs has the highest priority interrupt
currently outstanding, while the Type field
indicates its source within the UART. The
Type field is encoded as follows:
000 No Interrupt
001 Change of State
xl0 Transmit available
a11 Receive available, no error
November 12, 1990
I
I
00000
5
# Bytes
3
8
Like the GIBC" no physical register
implementation exists. The correct receiver's
FIFO is popped based on the value of the
interrupting channel field of the Current
Interrupt Register.
.
If a receiver is not the cause of the current
interrupt, a read of the Global RxFIFO will
yield a byte containing all ones and NONE of
the UART channels' receive FIFOs will be
popped. (IMPORTANT)
The GRxFIFO is Read only at address 2BH.
Global Transmit Holding Register (GTHR)
236
Chan #
2
Interrupt Control (ICR)
I
Received Data
8
I
Like the other Global pseudo-registers no
hardware register exists. The Channel
number field of the Current Interrupt Register
padded with leading zeros is output as the
GICR. The GICR is Read only at address
29H.
Global Interrupt Byte Count (GIBC)
Data to be Sent
000000
6
The GIBC is not an actual register but simply
outputs the interrupting UART's transmit or
receive byte counter value. The count,
accurate at the time IACKN asserts, is
captured in the CIR. The high order 5 bits
are read as '0'. The GIBC is read only at
address 2AH.
I
Global Interrupting Channel (GICR)
I
Threshold
IVC
6
2
The Threshold Field is used by the interrupt
comparator to determine if a winning interrupt
"bid" should result in interrupting the control
processor. This field resets to 3Fh.
The IVC field controls what kind of vector the
QUART returns to the control processor
during an Interrupt Acknowledge cycle:
00 Output contents of Interrupt Vector
Register
01 Output 6 MSBs of IVR and Channel
number as 2 LSBs
10 Output 3 MSBs of IVR and Channel
number and Interrupt Type
11 Disable generation of vector during
lACK cycle
This field reset to 00 and is readlWrite at
address 2CH.
Preliminary Specification
Philips Components-Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
SC26C94/SC68C94
(QUART)
Bidding Control Registers (BCRs)
[Rc~;dB;~-~k
State Change
crr ~
3
3
2
The 3 MSBs determine the priority of
Received Break Interrupts; they are reset to
001
Bits 4:2 determine the priority of Change of
Input State interrupts, and are reset to 00.
There is one BCR per UART channel; they
I
I
can be read or written at addresses 20-23H.
Interrupt Vector (IVR)
interrupt type code andlor Channel code bits
The IVR is write only at address 29H.
I Always Used I with IVC = Ox I wllVC > 001
3 3 2
Holds the constant bits of the interrupt
acknowledge vector. As shown, the three
MSBs are always used, while the less
significant bits can be replaced by the
OPEN ISSUES
This specification is Preliminary. Final
performance values will follow
characterization. AC parameters have been
taken from first fabrication lots.
ABSOLUTE MAXIMUM RATlNGS1
SYMBOL
PARAMETER
TA
Operating ambient temperature range 2
T STG
Storage temperature range
Vee
Voltage from Voo to GND3
Vs
Voltage from any pin to ground 3
Po
Power dissipation
UNIT
RATING
Note 4
"C
-£5 to +150
"C
-D.5 to +7.0
V
-D.5 to Vee +0.5
V
1
w
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not implied.
2. For operating at elevated temperatures, the device must be derated based on + 150°C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge
Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating supply
range.
DC ELECTRICAL CHARACTERISTICS1, 2, 3
LIMITS
SYMBOL
PARAMETER
V,L
V,H
V,H
Input low voltage
Input high voltage (except Xl /ClK)
Input high voltage (Xl/ClK)
VOL
VOH
Output low voltage
Output High voltage (except OD outputs)
I,L
I'H
Input current low, I/O ports
Input current High, I/O ports
TEST CONDITIONS
IOL = 4.0mA
IOH = -400flA
Y,N = 0
Y,N = Vee
UNIT
0.8
V
V
V
0.4
V
V
V
-10
V,N=OtoVee
-1
-100
Xl/ClK input low current
Xl/ClK input High current
IOZH
IOZL
Output off current High, 3-State data bus
Output off current low, 3-State data bus
V,N = Vee
Y,N = 0
IODL
IODH
Open-drain output low current in off state: IRON
Open-drain output low current in off state: IRON
V,N = Vcc
V,N = 0
Operating mode
Max
O.BVec
0.9Vec
Y,N = GND, X2 = open
Y'N = Vcc , X2 = open
Input leakage current
I,LX1
I,HX1
Icc
Typ
2.0
O.BVec
I,
Power supply current
Min
TIL input levels 25"C
with Xl = 4MHz
Power down mode
-1
1
flA
flA
1
flA
100
flA
flA
10
1
flA
1
flA
50
mA
-10
TBD
flA
NOTES:
1. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating supply
range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between OAV and 2.4V with a transition time of 20ns
maximum. For Xl/ClK this swing is between O.4Vand 4.4V. All time measurements are referenced at input voltages OfV ,L and V,H , as appropriate.
3. Typical values are at +25"C, typical supply voltages, and typical processing parameters.
November 12, 1990
237
Preliminary Specification
Philips Components-Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
SC26C94/SC68C94
(QUART)
AC ELECTRICAL CHARACTERISTICS', 2, 3, 4 TA = 2O"C; Vee = 5V ± 10"10, unless othelWise specified.
LIMITS
SYMBOL
FIGURE
Min
PARAMETER
Typ
Max
UNIT
Reset timing
tRES
5
Reset pulse width
200
ns
10 Port timingS
tps
6
10 input setup time before RON low
0
ns
tpH
6
10 input hold time after RON High
0
ns
7
INTRN negated or 10 output High from:
Read RHR (RxRDY/FFUll interrupt)
Write THR (TxRDY interrupt)
Reset command (break change interrupt)
Reset command (10 change interrupt)
Stop CIT command (counter interrupt)
Write IMR (clear of interrupt mask bit)
Interrupt timing
tlR
}
With respect to a
3.68S4MHz clock on
pin Xl/ClK
100
100
100
100
100
100
ns
ns
ns
ns
ns
ns
4.0
MHz
8
MHz
16
1.0
MHz
MHz
16
1.0
MHz
MHz
120
ns
50
ns
Clock timing
!eLK
8
XlIClK low timelhigh time
!eLK
8
XlIClK frequency
!eTC
8
Counter/timer clock high or low time
60
feTe
8
Counter/timer clock frequency
0 11
tRX
8
RxC high or low time
30
8
RxC frequency (16X)
RxC frequency (1 X)
0 11
0"
tTX
8
TxC high or low time
200
fTX
8
TxC frequency (16X)
TxC frequency (IX)
0 11
0"
fRX
1251100
2.0
ns
3.6864
ns
ns
ns
Transmitter timing
tTXO
9
TxD output delay from TxC low 16X
tTes
9
TxD output delay from TxC output
0
Receiver timing
tRXS
10
RxD data setup time to RxC high
100
ns
tRXH
10
RxD data hold time from RxC high
100
ns
NOTES:
1. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating supply
range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 20ns
maximum. For XlIClK this swing is between 0.4 V and 4.4V. All time measurements are referenced at input voltages OfVIL and VIH, as appropriate.
3. Typical values are at +25"C, typical supply voltages, and typical processing parameters.
4. Test condition for interrupt and 10 outputs: C L = 50pF, forced current for VOL = 5.3mA; forced current for VOH = 4oo~, RL = 2.7kQ to Vee. Test
conditions for rest of outputs: CL = 150pF.
November 12,1990
238
Preliminary Specification
Philips Components-Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
(QUART)
AC ELECTRICAL CHARACTERISTICS (PRELlMINARy)4
SC26C94/SC68C94
TA = 20°C; Vcc = 5V ± 10%, unless otherwise specified.
LIMITS
NO,
FIGURE
1
la
Setup: A[5:0] valid to CEN low
10
2
la
Hold: A[5:0] valid after CEN low
30
3
la
Access: Later of CEN low and RDN low, to Dnn valid (read)
CHARACTERISTIC
Min
Max
Typ
UNIT
ns
ns
110
Later of CEN low and (RDN or WRN as applicable) low, to DACKN low
Normal Operation:
ns
70 + 2
XI edges
ns
150
ns
From Power Down:
4
la
5
la
Earlier of CEN high or RDN high, to Dnn released (read)'
0
45
ns
6
la
Earlier of CEN high or (RDN or WRN as applicable) high, to DACKN released
0
30
ns
7
la
Earlier of CEN high or (RDN or WRN as applicable) high, in one cycle, to later
of CEN low and (RDN or WRN as applicable) low, for the next cycle
55
ns
8
la
Setup, Dnn valid (write) to later of CEN low and WRN low2
--30
ns
9
la
Later of CEN low and WRN low, to earlier of CEN high or WRN high
110
ns
10
la
Hold: Dnn valid (write) after DACKN low, CEN high or WRN high 3
0
ns
NOTES:
1. The minimum time indicates that read data will remain valid until the bus master drives CEN andlor RDN to high.
2. The fact that this parameter is negative means that the Dnn line may actually become valid after CEN and WRN are both low.
3. In a Write operation, the bus master must hold the write data valid either until drives CEN andlor WRN to high, or until the QUART drives
DACKN to low, whichever comes first.
4. Test condition for interrupt and 10 outputs: CL = 5OpF, forced current for VOL = 5.3mA; forced current for VOH = 400pA, RL = 2.7kn to Vce.
Test conditions for rest of outputs: CL = 150pF.
REAOCYCLE
A[S:OI
WRITE CYCLE
~1- ~2~
~f-1
___
4-2---K
9
7
CEN
9-
7
RON
9-c.
7
WRN
7
'-f-3 -+
!--3--
~
0[7:01
'-1--- 4
14-OACKN
4
9 ------,
-. 4-.-
.r-sI-s--
.t:=}
f.- ,0-'
• ,0-~
'0-
+-- I-- 4
I.---
4 -
Figure 1a. A Read Cycle Followed by a Write Cycle Ylli1!! DACKN
November 12, 1990
239
~f-6
1.---6
Preliminary Specification
Philips Components-Signetics Oata Communication Products
Quad universal asynchronous receiver/transmitter
SC26C94/SC68C94
(QUART)
AC ELECTRICAL CHARACTERISTICS (PRELlMINARy)1
TA
= O°C; Vee = 5V ± 10%, unless otherwise specified.
LIMITS
Min
Typ
Max
UNIT
NO.
FIGURE
1
lb
A[5:0] Setup time to RON WRN Low
10
ns
2
lb
A[5:0] Hold time from RON WRN Low
30
ns
3
lb
CEN Setup time to RON WRN Low 2
0
ns
4
lb
CEN Hold time from RON WRN High2
0
ns
5
lb
RON WRN Pulse width Low
6
lb
0[7:0] Oata Valid after CEN and RON Low
110
ns
7
lb
0[7:0] Oata bus floating after RON or CEN High
45
ns
8
lb
0[7:0] Oata bus setup time before WRN or CEN High
75
9
lb
0[7:0] Hold time after WRN or CEN High
0
ns
10
lb
Time between Reads andior Writes 3
55
ns
CHARACTERISTIC
ns
110
ns
NOTES:
1. Timing is illustrated and referenced to the WRN and RON inputs. The device may also be operated with CEN as the 'strobing' input. CEN and
RON (also CEN and WRN) are ANOed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first lerminates the cycle.
2. The RON signal must be negated for tRWD guarantee that any status register changes are valid.
3. Consecutive write operations to the command register require at least three rising edges of the Xl clock between writes.
WRITE CYCLE
READ CYCLE
A15"'1
~1 _
_
2~
~1_ '-2~
-
CEN
:'-3~
10
4
RON
~
WRN
I6
5 _______
fc- 9-"
-7-
~5-,
1--8-----'
Ir--
0[7"'1
Figure 1 b. A Read Cycle Followed by a Write Cycle .lIIlitIJ2J.!1 OACKN
November 12, 1990
240
Preliminary Specification
Philips Components-Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
(QUART)
AC ELECTRICAL CHARACTERISTICS (PRELIMINARY) TA = O'C; Vee
=
SC26C94/SC68C94
5V ± 10%, unless otherwise specified.
LIMITS
NO.
FIGURE
1
lc
Typ
Max
UNIT
D[7:0] Valid after IACKN Low
110
ns
10 + 2
XI edges
ns
Min
CHARACTERISTIC
2
lc
DACKN Low after IACKN Low
3
lc
D[7:0] floating after IACKN High
45
ns
4
lc
DACKN High after IACKN High
45
ns
\~
INTRN
30
__________________~/~r_-_-_-_-_-_-_-~/
\
IACKN
J
~
1
1+-3--00
0[7"'1
2
j-.-'--.
OACKN
V
Figure 1c, Interrupt Knowledge (IACKN) Timing
OSCIN
EVAUHOLD
IACKN
\\\\\\
I!/lll
CIR __________________________L)(~_V~A~lU~E~F~OR~T~H~IS~IN~T~ER_R_U_PT______________________
Figure 2. Interrupt Bid Arbitration Timing.
November 12, 1990
241
Preliminary Specification
Philips Components-Signetics Data Communication Products
Quad universal asynchronousreceiver/transmitter
SC26C94/SC68C94
(QUART)
INTBUSN7:O
HOLD
EN
INVERTING LATCHES
BYTE COUNT CORRECTION LOGIC
lACK
BYTE COUNT
CURRENT
INTERRUPT
REGISTER
CHANNEL
REAOGIBC
REAOCIR
READGICR
07
06
05
D4
02
03
01
DO
Figure 3. Current Interrupt Register Logic
INTRAN-INTRDN,
MPP1a-MPP1h.
MPP2a-MPP2h
2. 7K
o>-----I
.....---'\IV'vr-----o
I
60pF
~
+5V
00-07.
TxDa-TxDh.
MPOa-MPOh
I
1=5.3mAVOL
I =400J'A VOH
'5OpF
Figure 4. Test Conditions on Outputs
November 12.1990
242
+5V
Preliminary Specification
Philips Components-Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
SC26C94/SC68C94
(QUART)
Figure 5. Reset Timing
I
'------------~~
WRN
10.e Output
tpD
'v
OLD DATA
NEW DATA
----------------------~~I~-----------
Figure 6. 10 Port TIming
Vu ~R
INT~~TU::;
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.L.. _
~o~...,~VVOL
~; Pfol:I-~===========--~-R------Jf,,"",,~
NOTES:
1. Includes 10 when used as TxRDY or RxDY/FFULL outputs as well as INTRN.
2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced trom the midpoint 01 the switching signal.
Vw• 10 a point O.SV above Va... This Point Represents Noise Margin That Assures True Switching Has Occurred. Beyond this level. the effects 01 external circu~ry and tesl
environment are pronounced and can greatly affect the resultant measurement.
Figure 7. Interrupt TIming
November 12, 1990
243
Preliminary Specification
Philips Compon/lnts-Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
SC26C94/SC68C94
(QUART)
teLK
teTC
+5V
NOTE:
RESISTOR REQUIRED
FQR TTL INPUT
I
~----L--NC-~
X,ICLK
CTCLK
RxC
TxC
C,
= c. = 24pF FOR C, = 20PF
'K
SCz&C94fSC68C94
x,
=
'--____*--___-"X2=-+_ _---r____---~-... TO INTERNAL CLOCK DRIVERS
3.6864MHz
1
4PF
NOTE:
C1 and C2 should be baaed on manufacturer'. specification.
Xl and X2 parasitic capacitance ia 1.2pF and 3-SpF, respectively.
TYP1CAL CRYSTAL SPEC1RCAnON
FREQUENCY:
• -4MHZ
,. - 32pF
LOAD CAPACITANCE (C,):
TYPE OF OPERATION:
PARALLEL RESONANT, FUNDAMENTAL MODE
Figure 8. Clock Timing
Txe
(INPUT)
TxD
TxC
('X OUTPUT)
Figure 9. Transmit Timing
November 12,1990
244
:
Preliminary Specification
Philips Components-Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
(QUART)
SC26C94/SC68C94
RxC
(1X INPUT)
RxO
Figure 10. Receive Timing
TxO
WRN
CTSN 1
(1/00) _ _ _ _- '
(1102)
RTSN27L
l-J
______________________________I
CR[7:']
=1000
CR[7:']
NOTES:
1. Timing shown for MR2[4] = 1.
2. Timing shown for M R2[5] .. 1.
Figure 11. Transmitter Timing
November 12, 1990
(~
245
=1000
Preliminary Specification
Philips Components-Signetics Data Communication Products
Quad universal asynchronous receiver/transmitter
SC26C94/SC68C94
(QUART)
I
RxD
I: I
D.
~~~~~:~r---------~:--------~-------------------r+-----~------_,
I
RxRDV
(SAO)
FFULL
(~')---------T------------~------------------~
RDN
S= STATUS
D=DATA
RESET BY
COMMAND
+ __________________________________-;-..::..:.;=::.:.:...=:::1
OVERRUN
(SR4) ________
NOTES,
1. Timing shown for MR1[7] _ 1.
Figure 12. Receiver Timing
MASTER STATION
BIT 9
BIT S
BIT9
I I
DO
TxD
:;
::
0
II
TxROY
(SR2)
CSN
(WRITEI
MR. [4:3] = 11 ADD#'
MR. 121= •
MR' [2] = 0
DO
MR. [21 =.
ADD.2
PERIPHERAL STATION
I
RxD
RECEIVER
ENABLED
RxRDY
(SAO)
RDNIW;-U
MR. [4:3] = 11
BITS
!I
0
I
BITS
ADD••
BITS
!. I: I
DO
: 0
I:I
I
I
I
I
I
I
~
I
:
ri :
Figure 13. Wake-Up Mode
246
BITS
!. I : I
!I
I
0
I
I
DO
November 12. 1990
BIT9
ADD..
I
~
ADD,1
:
I
S = STATUS
D = DATA
:
~
~
ADD..
I '.'-
L.>r-
Philips Components-Signetics
Document No.
853-t127
ECN No.
000341
Date of Issue
November 12, 1990
Status
Product Specification
SCC26988
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
Data Communication Products
DESCRIPTION
The SCC2698B Enhanced Octal
Universal Asynchronous
ReceiverfTransmitter (Octal UART) is a
single chip MOS-LSI communications
device that provides eight full-duplex
asynchronous receiverltransmitter
channels in a single package. It is
fabricated with CMOS technology which
combines the benefits of high density
and low power consumption.
The operating speed of each receiver
and transmitter can be selected
independently as one of eighteen fixed
baud rates, a 16X clock derived from a
programmable counterltimer, or an
external 1X or 16X clock. The baud rate
generator and counterltimer can operate
directly from a crystal or from external
clock inputs. The ability to independently
program the operating speed of the
receiver and transmitter make the Octal
UART particularly attractive for
dual-speed channel applications such as
clustered terminal systems.
The receiver is quadruple buffered to
minimize the potential of receiver
overrun or to reduce interrupt overhead
in interrupt driven systems. In addition, a
handshaking capability is provided to
disable a remote UARTtransmitter
when the receiver buffer is full.
The UART provides a power-down
mode in which the oscillator is frozen but
the register contents are stored. This
results in reduced power consumption
on the order of several magnitudes. The
Octal UART is fully TIL compatible and
operates from a single +5V power
supply.
• Baud rate for the receiver and
transmitter selectable from:
- 18 fixed rates: 50 to 38.4K baud
Non-standard rates to 115.2K baud
- User-defined rates from the
programmable counterltimer
associated with each of four blocks
- External 1x or 1 6x clock
The SCC2698B is an upwardly
compatible version of the 2698A Octal
UART. In PLCC packaging, it is
enhanced by the addition of receiver
ready or FIFO full status outputs, and
transmitter empty status outputs for
each channel on 16 multipurpose I/O
pins. The multipurpose I/O pins of the
SCC2698B were inputs only on the
SCC2698A.
• Parity, framing, and overrun error
detection
• False start bit detection
• Line break detection and generation
• Programmable channel mode
- Normal (full-duplex), automatic
echo, local loop back, remote
loopback
FEATURES
• Eight full-duplex asynchronous
receiverltransmitters
• Quadruple buffered receiver data
register
• Programmable data format:
- 5 to 8 data bits plus parity
- Odd, even, no parity or force parity
- 1, 1.5 or 2 stop bits programmable
in 1/16-bit increments
• Four multi-function programmable
16-bit counterltimers
• Four interrupt outputs with eight
maskable interrupting conditions for
each output
• Receiver ready/FIFO full and
transmitter ready status available on
16 multi-function pins in PLCC
package
• On-chip crystal oscillator
• TIL compatible
• Single +5V power supply with low
power mode
ORDERING INFORMATION
PACKAGES
Plastic DIP
Vcc = +5V ±5%, TA = DoC to +70°C
Vcc = +5V ±5%, TA =-40°C to +85°C
SCC2698BC 1N64
SCC2698BA 1N64
Plastic Leaded Chip Carrier
SCC2698BC1A84
NOTE:
Pin Grid Array (PGA) package version is available from Philips Components Military Division.
247
SCC2698BA 1A84
Philips Components--Signetics Data Communication Products
Product Specification
SCC26988
Enhanced octal universal asynchronous receiver/transmitter
PIN CONFIGURATIONS
RxDs
TxD.
RxDe
TxDc
R.De
MP10h
MP1Qg
RxDg
T.De
D4
TxOg
Pin
NC
MPO.
1
2
3
4
5
6
7
8
9
10
DS
MPOc
RESET
MPOe
D6
MPOg
D7
CEN
MP10f
WRN
MP10e
GND
RxCh
RDN
RxDf
AD
R.Dd
A1
RxDb
A2
TxOh
A3
MPOh
A4
Test Input
AS
MPOf
MP10a
MP10b
MPOd
T.Dd
INTRBN
INTRDN
MP10c
INTRCN
T.Db
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
TxO.
INTRAN
MP10d
November 12, 1990
GND
VCC
MPOb
248
Function
Pin
Function
Pin
Function
TxDa
29
30
31
32
33
A3
MPP2b
57
MPP2g
RxDa
MPP2h
Vee
X2
58
RxDd
RxD!
X1ICLK
34
A1
MPP1b
A2
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
MPP2a
56
DO
D1
D2
D3
D4
D5
MPlla
RESET
D6
D7
CEN
WRN
GND
MPI1b
RDN
AO
MPPla
A4
59
RxDh
A5
MPIOa
MPIOb
INTRAN
INTRSN
60
MPlle
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
MPIOe
MPI1f
MPIOc
MPllc
MPIOd
MPI1d
TxDb
MPPlc
MPOb
MPP1d
Vee
INTRCN
INTRDN
MPP2c
TxDd
MPP2d
MPOd
TxD!
MPOf
MPOh
77
TxDh
78
79
80
81
82
83
RxDb
84
MPIOf
MPPle
GND
MPP1f
MP09
MPP2e
MPOe
MPP2f
MPOc
MPOa
TxOg
TxDe
RxDg
MPIOg
MPIOh
MPI1g
RxOe
MPlh
TxDc
MPP1g
RxDc
MPP1h
Product Specification
Philips Components-Signetics Data Communication Products
SCC26988
Enhanced octal universal asynchronous receiver/transmitter
BLOCK DIAGRAM
INTERNAL DATA
BUS
8
/I
Z
00-07
r-..
I
BUS BUFFER
I
~
~
RON
WRN
CEN
AD-AS
RESET
6
--r-
I
I
I
RlWCONTROL
I
TIMING
XIICLK
X2
I
/I
I
CRYSTAL
OSCILLATOR
I
POWER-ON
LOGIC
~
I r-:::
I
>--
TxDA
TRANSMIT SHIFT
REGISTER
r-..
RECEIVE HOLD
REGISTER (3)
RxDA
:
RECEIVE SHIFT
REGISTER
I
I
I
I
I
I
T
MR1,2
CR
SR
CSR Rx
CSRTx
~
"
"
>-/I
CHANNELB
(ASABOYE)
V
I
I
INPUT PORT
i
CHANGE-OFSTATE
DETECTORS (4)
~
i
I
v
II
BLOCKC
(SAME AS A)
:
I
I
I
n
MPlb
4
I
MPP'
4
2
MPP2
MPO
TIMING
~"=~ ~ I
I
:
~
I "
I
I
L " L ___________________
J
CLOCK
SELECTORS
I
~
r-..
v
COUNTER!
TIMER
I
I
I
ACR
CTUR
CTLR
I
I
INTERRUPT CONTROL
/I
IMR
v
'"'-
November 12, 1990
I
OPCR
MPIO
:
I
I
I
I
I
I
I
I
I
I
I
I
I
4
FUNCTION SELECT
LOGIC
I
~r--r-'.
BLOCK 0
(SAME ASA)
4
OUTPUT PORT
"-
RxDb
/
ACR
:
T
TxDb
I
IPCR
I
BLOCK B
(SAME AS A)
I
I
TRANSMIT HOLD
REGISTER
II
~
OPERATION CONTROL
ADDRESS
DECODE
BLOCK A
CHANNEL A
I
TIIIINGCONTROL-
r----------------- ---,I
I
I
249
I
ISR
INTRAN :
I
Philips Components-5ignetics Data Communication Products
Product Specification
Enhanced octal universal asynchronous receiver/transmitter
SCC2698B
PIN DESCRIPTION
MNEMONIC
PIN NO.
TYPE
NAME AND FUNCTION
8-13,
16,17
I/O
16
18
I
Data Bus: Active-High B-bit bidirectional3-State data bus. BitO is the LSB and bit 7 is the MSB.
All data, command, and status transfers between the CPU and the Octal UART take place over
this bus. The direction of the transfer is controlled by the WRN and RON inputs when the CEN
input is low. When the CEN input is High, the data bus is in the 3-State condition.
Chip Enable: Active-Low input. When Low, data transfers between the CPU and the Octal
UART are enabled on 00-07 as controlled by the WRN, RON and AO-A5 inputs. When CEN
is High, the Octal UART is effectively isolated from the data bus and 00-07 are placed in the
3-State condition.
WRN
17
19
I
Write Strobe: Active-Low input. A Low on this pin while CEN is Low causes the contents of the
data bus to be transferred to the register selected by AO-A5. The transfer occurs on the trailing
(rising) edge of the signal.
RDN
19
22
I
Read Strobe: Active-Low input. A Low on this pin while CEN is Low causes the contents of the
register selected by AO-A5to be placed on the data bus. The read cycle begins on the leading
(falling) edge of RDN.
AO-A5
20-25
23,25,
27,29,
31,32
I
Address Inputs: Active-High address inputs to select the Octal UART registers for readiwrile
operations.
RESET
13
15
I
Reset: Master reset. A High on this pin clears the status register (SR), clears the interrupt mask
register (IMR), clears the interrupt status register (ISR), clears the output port configuration register (OPCR), places the receiver and transmitter in the inactive state causing the TxD output
to go to the marking (High) state, and stops the counter/timer. Clears power-down mode and
interrupts.
28,29,
35,36
35,36,
46,47
0
Interrupt Request: This active-Low open drain output is asserted on occurrence of one or more
of eight maskable interrupting conditions. The CPU can read the interrupt status register to determine the interrupting condition(s).
XI/ClK
3
7
I
Crystal 1: Crystal or external clock input. When using the crystal oscillator, this pin serves as
the connection for one side of the crystal. If a crystal is not used, an external clock is supplied
at this input. An external clock (or crystal) is required even if the internal baud rate generator is
not utilized. This clock is used to drive the internal baud rate generator, as an optional input to
the timer/counter, and to provide other clocking signals required by the chip.
X2
2
6
I
Crystal 2: Connection for other side of crystal. If an external source is used instead of a crystal,
this connection should be left open (see Figure 7).
64,44,
62,45,
60,46,
57,47
3,56,
83,57,
I
Receiver Serial Data Input: The least significant bit is received first. If external receiver clock
is specified, this input is sampled 00 the rising edge of the clock. If internal clock is used, the
RxO input is sampled on the rising edge of the RxC I x signal as seen on the MPO pin.
DIP
lDCC
4-6.8,
10,12,
14, 15
CEN
00-07
INTRANINTRDN
RxDa-RxOh
79,58,
75,59
TxDa-TxDh
63,32,
61,37,
56,39,
55,43
1,41,
Bl,49,
74,52,
73,55
0
Transmitter Serial Data Output: The least significant bit is transmitted first. This outputis held
in the marking (High) condition when the transmitter is idle or disabled and when the Octal UART
is operating in localloopback mode. If external transmitter is specified, the data is shifted on the
falling edge of the transmitter clock. If internal clock is used, the TxD output changes on the failing edge of the TxClx signal as seen on the MPO pin.
MPOa-MPOh
54,33,
53,38,
52,40,
51,42
72,43,
71,51,
69,53,
67,54
0
Multi-Purpose Output: Each of the four DUARTS has two MPO pins. One of the following eight
functions can be selected for this output pin by programming the OPCR (output port configuration register). Note that reset conditions MPO pins to RTSN.
RTSN - Request to send active-Low output. This output is asserted and negated via the command register. By appropriate programming of the mode registers, RTSN can be programmed
to be automatically reset after the character in the transmitter is completely shifted or when the
receiver FIFO and shift register are full. RTSN is an internal signal which normally represents
the condition of the receiver FIFO not full, i.e., the receiver can request more data to be sent.
However, it can also be controlled by the transmitter empty and the commands 8h and 9h written
to the CR (command register).
CtTO - The counter/timer output.
TxC1X - The IX clock for the transmitter.
TxC16X - The 16X clock for the transmitter.
RxCI X - The 1X clock for the receiver.
RxC16X - The 16X clock for the receiver.
TxRDY - Transmitter holding register empty signal.
RxRDYIFFUll - Receiver FIFO not emptylfull signal.
MPIOa-MPIOh
26,27,
30,31,
48,49,
58,59
33,34,
37,39,
61,63,
76,77
I
Multi-Purpose Input 0: This pin (one in each UART) is programmable. Its state can always be
read through the IPCR bit 0, or the IPR bit O.
CTSN: By programming MR2[4J to a I, this input will also control the clear-to-send functions.
It is active low. This pin is provided with a change-of-state detector.
November 12,1990
250
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced octal universal asynchronous receiver/transmitter
SCC26988
PIN DESCRIPTION (Continued)
MNEMONIC
PIN NO.
TYPE
NAME AND FUNCTION
14,21,
38,40,
GO,62,
78,80
I
Multi-Purpose Inpull: This pin (one for each unit) is programmable. Its state can always be
determined by reading the IPCR bit 1 or IPR bit 1.
CITCLK - By programming MR2[5[ to ai, this input will serve as the external clock lor the coun·
ter/timer 2. This occurs only lor channels a, c, e, and g since there is one counter/timer 2 lor each
DUART block. This pin is provided with a change-ol-state detector.
24,26,
42,44,
I/O
Multi-Purpose Pin 1: This pin (one for each UART) is programmed to be an input or an output
according to the state 01 OPCR[7]. (0 = input, 1 = output). The state of the multi-purpose pin can
always be determined by reading the IPR. When programmed as an input, it will be the transmitter clock (TxClK). It will be IX or 16x according to the clock select registers (CSR[3.0]). When
programmed as an output, it will be the status register TxRDY bit. As an output, it will be an open
drain.
DIP
LDCC
MPlla-MPllh
NC
MPPla-MPPlh
NC
64,66,
82,84
MPP2a-MPP2h
NC
28,30,
48, SO,
68,70,
2,4
I/O
Multi-Purpose Pin 2: This pin (one for each UART) is programmed to be an input or an output
according to the state oIOPCR[7]. (0 = input, 1 = output). The state 01 the multi-purpose pin can
always be determined by reading the I PRo When programmed as an input, it will be the receiver
clock (RxClK). It will be Ix or 16x according to the clock select registers (CSR[7:4). When programmedas an output, it will be the status register RxRDY/FIFO full bit. As an output, it will be
an open drain.
Test Input
41
-
I
Tesllnpul: This pin is used as an inpul for test purposes at the lactory while in test mode. This
pin can be treated as 'N/C' by the user. It can be tied high, tied low, or left open.
Vcc
1,34
5,45
I
Power Supply: +5V supply input.
GND
18,50
20,65
I
Ground
BLOCK DIAGRAM
Interrupt Control
As shown in the block diagram, the Octal UART
consists of: data bus buffer, interrupt control,
operation control, timing, and eight receiver
and transmitter channels. The eight channels
are divided into four different blocks, each block
independent of each other (see Figure 1).
A single interrupt output per block (INTRN) is
provided which is asserted on occurrence of
any of the following internal events:
-Transmit holding register ready for each
channel
BLOCK A
CHANNELS a, b
BLOCKC
CHANNELS e, f
BLOCKB
CHANNELS c, d
BLOCKD
CHANNELS g, h
-Receive holding register ready or FIFO full
for each channel
-Change in break received status for each
channel
-Counter reached terminal count
Figure 1. Channel Architecture
Channel Blocks
There are four blocks (Figure 1), each containing two sets of receiverltransmitters. In the following discussion, the description applies to
Block A which contains channels a and b. However, the same information applies to all channel blocks.
Data Bus Buffer
The data bus buffer provides the interface between the external and internal data buses. It is
controlled by the operation control block to allow read and write operations to take place between the controlling CPU and the Octal UART.
November 12, 1990
-Change in MPI input
Associated with the interrupt system are the interrupt mask register (IMR) and the interrupt
status register (ISR). The IMR can be programmed to select only certain conditions, of
the above, to cause INTRN to be asserted. The
ISR can be read by the CPU to determine all
currently active interrupting conditions. However, the bits of the ISR are not masked by the
IMR. The transmitter ready status and the receiverready or FIFO full status can be provided
on MPPla, MPPlb, MPP2a, and MPP2b by
setting OPCR[7]. these outputs are not masked
byiMR.
Operation Control
The operation control logic receives operation
commands from the CPU and generates appropriate signals to internal sections to control
device operation. It contains address decoding
and read and write circuits to permit communi-
251
cations with the microprocessor via the data
bus buffer. The functions performed by the CPU
read and write operations are shown in Table 1.
Mode registers 1 and 2 are accessed via an
auxiliary pointer. The pointer is set to MR 1 by
RESET or by issuing a reset pointer command
via the command register. Any read or write of
the mode register while the pointer is at MRI
switches the pointer to MR2. The pointer then
remains at MR2 so that subsequent accesses
are to MR2, unless the pointer is reset to MR 1
as already described.
Timing Circuits
The timing block consists of a crystal oscillator,
a baud rate generator, a programmable 16-bit
counterltimer for each block, and two clock
selectors.
The crystal oscillator operates directly from a
3.6864MHz crystal connected across the XI/
ClK and X2 inputs with a minimum of external
components. If an external clock of the appropriate frequency is available, it may be connected to Xl/ClK. If an external clock is used
instead of a crystal, XI must be driven and X2
left floating as shown in Figure 7. The clock
serves as the basic timing reference for the
baud rate generator (BRG), the counterltimer,
and other internal circuits. A clock frequency,
within the limits specified in the electrical specifications, must be supplied even if the internal
BRG is not used.
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced octal universal asynchronous receiver/transmitter
Register Addressing
Table 1.
Units Eand F
Units Aand B
AS
A4
A3
A2
Al
AO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
READ (RDN=O)
MRla, MR2a
SRa
Reserved;
RHRa
IPCRA
ISRA
CTUA
CTLA
MRlb,MR2b
SRb
Reserved'
RHRb
Reserved'
Input portA
Start CfT A
StopC/TA
WRITE (WRN=O)
MRla, MR2a
CSRa
CRa
THRa
ACRA
IMRA
CTURA
CTlRA
MRlb, MR2b
CSRb
CRb
THRb
Reserved'
OPCRA
Reserved'
Reserved'
AS
A4
A3
A2
Al
AO
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
UnltsCandD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SCC26988
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
1
0
1
0
0
1
1
1
0
0
0
1
0
1
1
1
0
1
MRlc, MR2c
SRc
Reserved'
RHRc
IPCRB
ISRB
CTUB
CTlB
MRld,MR2d
SRd
Reserved'
RHRd
Reserved'
Input port B
StartCfT B
Stop CfTB
November 12,1990
1
1
1
1
1
MRle, MR2e
SRe
Reserved'
RHRe
IPCRC
ISRC
CTUC
CTlC
MR1I, MR2f
SRI
Reserved'
RHRI
Reserved'
Input port C
StartCfTC
Stop CfT C
WRITE (WRN=O)
MRle, MR2e
CSRe
CRe
THRe
ACRC
IMRC
CTURC
CTlRC
MR1I, MR2f
CSRI
CRI
THRf
Reserved'
OPCRC
Reserved'
Reserved'
UnltsG and H
MRlc, MR2c
CSRc
CRc
THRc
ACRB
IMRS
CTURB
CTlRB
MRld, MR2d
CSRd
CRd
THRd
Reserved'
OPCRB
Reserved'
Reserved'
NOTE:
'Reserved registers should never be read during normal operation
ACR
Auxiliary control register
CR
Command register
CSR = Clock select register
CTl = Counterltimer lower
CTlR = Counter/timer lower register
CTU = Counterltimer upper
CTUR = Counterltimer upper register
MR
Mode register
The baud rate generator operates from the oscillator or external clock input and is capable 01
generating 18 commonly used data communications baud rates ranging Irom 50 to 38.4K
baud. Thirteen 01 these are available simUltaneously lor use by the receiver and transmitter.
Eight are fixed, and one 01 two sets 01 live can
be selected by programming ACR[7]. The clock
outputs from the BRG are at 16X the actual
baud rate. The counterltirner can be used as a
timer to produce a 16X clock for any other baud
rate by counting down the crystal clockor an external clock. The clock selectors allow the independent selection, by the receiver and
1
READ (RDN=O)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
0
0
1
1
0
0
1
0
0
1
1
1
1
0
1
0
1
1
1
1
0
0
0
0
1
0
1
1
1
1
MRlg, MR2g
SRg
Reserved'
RHRg
IPCRO
ISRO
CTUD
CTlD
MRlh, MR2h
SRh
Reserved'
RHRh
Reserved'
Input port D
Start CfT 0
Stop CfT 0
MRlg, MR2g
CSRg
CRg
THRg
ACRO
IMRD
CTURD
CTlRD
MRlh, MR2h
CSRh
CRh
THRh
Reserved'
OPCRD
Reserved'
Reserved'
since they are reserved lor internal diagnostics.
SR
Status Register
THR
Tx holding register
RHR
Rx holding register
IPCR
Input port change register
ISR
Interrupt status register
IMR = Interrupt mask register
OPCR= Output port configuration registerr
transmitter, 01 any 01 these baud rates or an
external timing signal.
There are lour ClTs in the Octal UART, one for
each block. The CIT operation is programmed
by ACR[6:4]. One of eight timing sources can
be used as the input to the CIT. The output of
the CIT is available to the clock selectors and
can also be programmed by OPCR[2:0] for
channel a and OPCR[6:4] for channel b, to be
outPyt on the MPOa or MPOb pin respectively.
A register read address is reserved to issue a
start counter/timer command and a second
register read address is reserved to issue a
252
stop counter/timer command for each timer.
For example, to issue a stop counter command
for the counter-timer in block B, a read of address '1 F' must be performed. See Table 1 for
register addressing.
In the timer mode, the. CfT generates a square
wave whose period is twice the numberof clock
periods loaded into the CfT upper and lower
registers. The counterready bit in the ISR is set
once each cycle of the square wave. If the value
in CTUR or CTlR is changed, the current halfperiod will not be affected, butsubsequenthalfperiods will be affected. I n this mode the CfT
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced octal universal asynchronous receiver/transmitter
runs continuously and does not recognize the
stop CIT command (the command only resets
the counter ready bit in the ISR). Receipt of a
start CIT command causes the counter to terminate the current timing cycle and to begin a
new cycle using the values in CTUR and CTlA.
In the counter mode, the CIT counts down the
number of pulses loaded into CTUR and CTlA.
Counting begins upon receipt of a start counter
command. Upon reaching terminal count, the
counter ready bit in the ISR is set. The counter
continues counting pastthe terminal count until
stopped by the CPU. I! MPO is programmed to
be the output of the CIT, the output remains
High until terminal count is reached, at which
time it goes low. The output returns to the High
state and the counter ready bit is cleared when
the counter is stopped by a stop counter command. The CPU may change the values of
CTUR and CTlR at any time, butthe new count
becomes effective only on the next start counter command following a stop counter command. If new values have not been loaded, the
previous count values are preserved and used
for the next count cycle.
In the counter mode, the current value ofthe upper and lower eight bits of the counter may be
read by the CPU. It is recommended that the
counter be stopped when reading to prevent
potential problems which may occur if a carry
from the lower eight bits to the upper eight bits
occurs between the times that both halves of
the counter are read. However, a subsequent
start counter command causes the counter to
begin a new count cycle using the values in
CTUR and CTlR.
Receiver and Transmitter
The Octal UART has eight full-duplex asynchronous receiver/transmitters. The operating
frequency for the receiver and transmitter can
be selected independently from the baud rate
generator, the counter/timer, or from an external input.
Registers associated with the communications
channel are the mode registers (MRI and
MR2), the clock select register(CSR), the command register (CR), the status register (SR),
the transmit holding register (THR), and the receive holding register (RHR).
Transmitter
The transmitter accepts parallel data from the
CPU and converts itto a serial bit stream on the
TxD output pin. It automatically sends a start bit
followed by the programmed number of data
bits, an optional parity bit, and the programmed
number of stop bits. The least significant bit is
sent first. Following the transmission of the stop
bits, if a new character is not available in the
THR, the TxD output remains high and the
TxEMT bit in the SR will be set to 1. Transmission resumes and the TxEMT bit is cleared
November 12, 1990
when the CPU loads a new character in the
THA. In the 16X clock mode, this also resynchronizes the internal 1X transmitter clock so
that transmission of the new character begins
with minimum delay.
The transmitter can be forced to send a break
(continuous low condition) by issuing a start
break command via the CA. The break is termi·
nated by a stop break command. I! the transmitter is disabled, it continues operating until the
characters currently being transmitted and the
character in the THR, if any, are completely
sent out. Characters cannot be loaded in the
THR while the transmitter is disabled.
Receiver
The receiver accepts serial data on the RxD
pin, converts the serial input to parallel format,
checks for start bit, stop bit, parity bit (if any), or
break condition, and presents the assembled
character to the CPU. The receiver looks for a
High-to-low (mark-to-space) transition of the
start bit on the RxD input pin. I! a transition is detected, the state of the RxD pin is sampled
again each 16X clock for 7-1/2 clocks (16X
clock mode) or at the next rising edge of the bit
time clock (IX clock mode).
If RxD is sampled High, the start bit is invalid
and the search for a valid start bit begins again.
If RxD is still low, a valid start bit is assumed
and the receiver samples the input. This continues at one bit time intervals, at the theoretical
centerof the bit, until the proper number of data
bits and the parity bit (if any) have been assembled, and one stop bit has been detected.
The data is then transferred to the RHR and the
RxRDY bit in the SR is set to a one. If the character length is less than eight bits, the most significant unused bits in the RHR are set to zero.
After the stop bit is detected, the receiver will
immediately look for the next start bit. However,
if a non-zero character was received without a
stopbit(Le. framing error) and RxD remains low
for one-half of the bit period after the stop bit
was sampled, then the receiver operates as if
a new start bit transition had been detected at
that point (one-hal! bit time after the stop bit was
sampled). The parity error, framing error and
overrun error (if any) are strobed into the SR at
the received character boundary, before the
RxRDY status bit is set.
If a break condition is detected (RxD is low for
the entire character including the stop bit), only
one character consisting of all zeros will be
loaded in the FI FO and the received break bit
in the SR is set to 1. The RxD input must return
to a high condition for two successive clock
edges of the 1X clock (internal or external) before a search for the next start bit begins.
253
SCC26988
TIMEOUT MODE
The timeout mode uses the received data
stream to control the counter. Each time a received character is transferred from the shift
register to the RHR, the counter is restarted. If
a new character is not received before the
counter reaches zero count, the counter ready
bit is set, and an interrupt can be generated.
This mode can be used to indicate when data
has been left in the Rx FIFO for more than the
programmed time limit. Otherwise, if the receiver has been programmed to interrupt the CPU
when the receive FIFO is full, and the message
ends before the FIFO is full, the CPU may not
know when there is data left in the FIFO, The
CTU and CTl value would be programmed for
just over one character time, so that the CPU
would be interrupted as soon as it has stopped
receiving continuous data. This mode can also
be used to indicate when the serial line has
been marking for longer than the programmed
time limit. In this case, the CPU has read all of
the characters from the FIFO, but the last character received has started the count. I! there is
no new data during the programmed time interval, the counter ready bit will get set, and an interrupt can be generated.
This mode is enabled by writing the appropriate
command to the command register. Writing an
'Ax' to CRA or CRB will invoke the timeout
mode for that channel. Writing a 'Cx' to CRA or
CRB will disable the timeout mode. The timeout
mode should only be used by one channel at
once, since it uses the CIT. CTU and CTl must
be loaded with a value greater than the normal
receive character period. The timeout mode
disables the regular START/STOP counter
commands and puts the CIT into counter mode
under the control of the received data stream.
Each time a received character is transferred
from the shift register to the RHR, the CIT is
stopped after one CIT clock, reloaded with the
value in CTU and CTl and then restarted on the
next CIT clock. If the CIT is allowed to end the
count before a new character has been received, the counter ready bit, ISR[3], will be set.
If IMR[3] is set, this will generate an interrupt.
Since receiving a character restarts the CIT, the
receipt of a character after the CIT has timed
out will clear the counter ready bit, ISR[3], and
the interrupt. Invoking the 'Setlimeout Mode
On' command, CRx='Ax', will also clear the
counter ready bit and stop the counter until the
next character is received.
RECEIVER FIFO
The RHR consists of a first-in-first-out (FIFO)
with a capacity of three characters. Data is
loaded from the receive shift register into the
top-most empty position of the FIFO. The
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced octal universal asynchronous receiver/transmitter
RxRDY bit in the status register (SR) is set
whenever one or more characters are available
to be read, and a .FFULL status bit is set if all
three stack positions are filled with data. Either
of these bits can be selected to cause an interrupt. A read of the RHR, outputs the data at the
top of the FIFO. After the read cycle, the data
FI FO and its associated status bits are 'popped'
thus emptying a FIFO position for new data.
In addition to the data word, three status bits
(parity error, framing error, and received break)
are appended to each data character in the
FIFO. Status can be provided in two ways, as
programmed by the error mode control bit in the
mode register. In the 'character' mode, status
is provided on a character-by-character basis:
the status applies only to the character at the
top of the FIFO. In the 'block' mode, the status
providedin the SR for these three bits is the logical OR of the status for all characters coming
to the top of the FIFO since the last reset error
command was issued. In either mode, reading
the SR does not aHect the FIFO. The FIFO is
'popped' only when the RHR is read. Therefore,
the SR should be read prior to reading the corresponding data character.
If the FIFO is full when a new character is received, that character is held in the receive shift
register until a FIFO position is available. If an
additional character is received while this state
exists, the contents of the FIFO are not affected: the character previously in the shift register is lost and the overrun error status bit,
SR[4], will be set upon receipt of the start bit of
the new (overrunning) character.
WAKE·UP MODE
In addition to the normal transmitter and receiver operation described above, the Octal UART
incorporates a special mode which provides
automatic wake-up. of the receiver through address frame recognition for multiprocessor
communications. This mode is selected by programming bits MR1[4:3] to'II'.
In this mode of operation, a 'master' station
transmits an address character followed by
data characters for the addressed 'slave' station. The slave stations, whose receivers are
normally disabled. examine the received data
stream and 'wake-up' the CPU [by setting
RxRDY) only upon receipt of an address character. The CPU compares the received address to its station address and enables the
receiver if it wishes to receive the subsequent
data characters. Upon receipt of another address character, the CPU may disable the receiver to initiate the process again.
A transmitted character consists of a start bit,
the programmed number of data bits, an address/data (AID) bit, and the programmed number of stop bits. The polarity of the transmitted
November 12,1990
AID bit is selected by the CPU by programming
bit MR 1[2]; MR 1[2] = 0 transmits a zero in the
AID bit position which identifies the corresponding data bits as data; MR1[2] = 1 transmits a one in the AID bit position which identifies
the corresponding data bits as an address. The
CPU should program the mode register prior to
loading the corresponding data bits in the THR.
While in this mode, the receiver continuously
looks at the received data stream, whether it is
enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character in the
RH R FIFO if the received AID bit is a one, but
discards the received character if the received
AID bit is a zero. If enabled, all received characters are then transferred to the CPU via the
RH R. In either case, the data bits are loaded in
the data FIFO while the AID bit is loaded in the
status FIFO position normally used for parity error (SR[5J). Framing error, overrun error, and
break detect operate normally whether or not
the receiver is enabled.
MULTI·PURPOSE INPUT PIN AND
MULTI·PURPOSE 1/0 PINS
The inputs to this unlatched 8-bit port for each
block can be read by the CPU, by performing a
read operation as shown in Table 1. A High input results in a logic one, while a Low input results in a logic zero. When the input port pins
are read on the 84-pin LLCC, they will appear
on the data bus in alternating pairs (i.e., DBO =
MP10a, OBI = MPlla, DB2 = MPIOb, DB3 =
MPllb, DB4 = MPPla, DB5 = MPP2a, DB6 =
MPP 1b, DB7 = MPP2b. Although this example
is shown for input port 'A', all ports will have a
similar order).
The MPI pin can be programmed as an input to
one of several Octal UART circuits. The function of the pin is selected by programming the
appropriate control register. Change-of-state
detectors are provided for MPIO and MPII for
each channel in each block. A High-to-Low or
Low-to-High transition of the inputs lasting
longer than 25 to 50l's sets the MPI change-ofstate bit in the interrupt status register. The bit
is cleared via a command. The change-of-state
can be programmed to generate an interrupt to
the CPU by setting the corresponding bit in the
interrupt mask register.
The input port pulse detection circuitry uses a
38.4KHz sampling clock, derived from one of
the baud rate generator taps. This produces a
sampling period of slightly more than 251'S (assuming a 3.6864MHz oscillator input). The detection circuitry, in order to guarantee thata true
change in level has occurred, requires two
successive samples be observed at the new
logic level. As a consequence, the minimum
duration of the signal change is 251's if the tran-
254
SCC26988
sition occurs coincident with the first sample
pulse. (The 50l'S time refers to the condition
where the change-of-state is just missed and
the first change of state is not detected until after an additional 25I's.)
The multi-purpose pins can be programmed as
inputs or outputs using OPCR[7]. When programmed as inputs, the functions of the pins
are selected by programming the appropriate
control registers. When programmed as outputs, the two MPPI pins (per block) will provide
the transmitter ready (TxRDY) status for each
channel and the MPP2 pins will provide the receiver ready or FIFO full (RxRDY/FFULL) status for each channel.
MULTI·PURPOSE OUTPUT PIN
This pin can be programmed to serve as a request-to-send output, the counterltimer output,
the output for the 1X or 16X transmitter or receiverclocks, the TxRDYoutputorthe RxRDYI
FFULLoutput(seeOPCR[2:0]andOPCR[6:4]
- MPO Output Select).
REGISTERS
The operation of the Octal UART is programmed by writing control words into the appropriate registers. Operational feedback is
provided via status registers which can be read
by the CPU. Addressing of the registers is described in Table 1.
The bit formats of the Octal UART registers are
depicted in Table 2. These are shown for block
A. The bit format for the other blocks is the
same.
MR1 - Mode Register 1
MR 1 is accessed when the MR pointer points
toMR1. The pointer is set to MRI by RESET or
by a set pointer command applied via the CR.
After reading or writing MR1, the pointers are
set at MR2.
MR1 [7] - Receiver Request.te-Send
Control
This bit controls the deactivation of the RTSN
output (MPO) by the receiver. This output is
manually asserted and negated by commands
applied via the command register. MR1[7J = 1
causes RTSN to be automatically negated
upon receipt of a valid start bit if the receiver
FIFOis full. RTSN is reasserted when an empty
FIFO position is available. This feature can be
used to prevent overrun in the receiver by using
the RTSN output signal to control the CTS input
of the transmitting device.
M R1 [6) - Receiver Interrupt Select
This bit selects either the receiver ready status
(RxRDY) or the FIFO full status (FFULL) to be
used for CPU interrupts.
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced octal universal asynchronous receiver/transmitter
MR1 (5)- Error Mode Select
This bit selects the operating mode of the
three FIFOed status bits (FE, PE, received
break). In the character mode, status is provided on a character-by-oharacter basis; the
status applies only to the character at the top
of the FIFO. In the block mode, the status provided in the SR for these bits is the accumulation (logical-OR) of the status for all characters coming to the top of the FIFO since the
last reset error command was issued.
Table 2.
I
Register Bit Formats
I Bit 6
Bit 7
I BitS
IBII4
I
Bit3
SCC2698B
I
I
I
Bit2
Bit1
BitO
MR1 (Mode Register 1)
RxRTS
Control
0= No
1 = Yes
RxlNT
Select
Error
Mode
0=
RxRDY
1=
FFULL
0= Char
1 = Block
Parity
Type
Parity Mode
Bits per Character
0= Even
1 = Odd
00 = With parity
01 = Force parity
10 = No parity
11 = Special mode
00 = 5
01 = 6
10 = 7
11 = 8
MR1 [4:3]- Parity Mode Select
If 'with parity' or 'force parity' is seiected, a
parity bit is added to the transmitted character
and the receiver performs a parity check on
incoming data. MR1[4:3] = 11 selects the
channel to operate in the special wake-up
mode.
MR2 (Mode Register 2)
MR1[2]- Parity Type Select
This bit selects the parity type (odd or even)
if the 'with parity' mode is programmed by
MRI [4:3], and the polarity of the forced parity
bit if the 'force parity' mode is programmed.
It has no effect if the 'no parity' mode is programmed. In the special 'wake-up' mode, it
selects the polarity of the transmitted AID bit.
NOTE:
"Add 0.5 to values shown above for 0--7, if channel is programmed for 5 bitslchar.
MR1 [1 :0]- Bits Per Character Select
This field selects the number of data bits per
character to be transmitted and received. The
character length does not include the start,
parity, and stop bits.
MR2 - Mode Reg]ster 2
MR2 is accessed when the channel MR pointer points to MR2, whioh occurs after any access to MRI. Accesses to MR2 do not
change the pointer.
MR2[7:6]- Mode Select
The Octal UART can operate in one of four
modes. MR2[7:6] = 00 is the normal mode,
with the transmitter and receiver operating independendy. MR2[7:6) = 01 places the channel in the automatic echo mode, which automatically retransmits the received data. The
following conditions aretruewhilein automatic echo mode:
1. Received data is reclocked ,lnd retransmitted on the TxD output.
2. The receive clock is used for the transmitter.
3. The receiver must be enabled, but the
transmitter need not be enabled.
4. The TxRDYand TxEMTstatus bits are inactive.
5. The received parity is checked, but is not
regenerated for transmission, i.e., transmitted parity bit is as received.
6. Character framing is checked, but the stop
bits are retransmitted as received.
November 12, 1990
TxRTS
Conrol
Channel Mode
CTS
Enable Tx
00 = Normal
01 = Auto-echo
10 = Local loop
11 = Remote loop
0= No
1 = Yes
0= No
1 = Yes
Stop Bit Length'
0= 0.5634
1 = 0.625 5
2 = 0.688 6
3 = 0.7507
= 0.813 8 = 1.563 C = 1.813
= 0.875 9 = 1.625 C = 1.875
= 0.938 A = 1.688 E = 1.938
= 1.000 B = 1.750 F = 2.000
CSR (Ctock Select Register)
Receiver Clock Select
Transmiller Clock Select
See text
See text
CR (Command Register)
Disable
Tx
Miscellaneous Commands
0= No
1 = Yes
See text
Enable
Tx
0= No
1 = Yes
Disable
Rx
0= No
1 = Yes
Enable
Rx
0= No
1 = Yes
SR (Status Register)
Reo'd,
Break
Framing
Error
Parity
Error
Overrun
Error
Tx,EMT
TxRDY
FFULL
RxRDY
0= No
1 = Yes
"
0= No
1 = Yes
0= No
1 = Yes
"
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
"
NOTE:
"These status bits are appended to the corresponding data character in the receive FI FO. A read
of the status register provides these bits [7:5] from the top of the FIFO together with bits [4:0]
These bits are cleared by a reset error status command. In character mode, they must be reset
when the corresponding data character is read from the FIFO.
OPCR (Output Port Configuration Register)
MPP
Function
Select
a
= input
1 = output
MPOb Pin Function Select
000= RTSN
001 = CITO
010 = TxC (IX)
011 = TxC (16X)
100 = RxC (IX)
101 = RxC (16X)
110 = TxRDY
111 = RxRDY/FF
PowerDown
Mode
0=011
1= On
"
MPOa Pin Function Select
000 = RTSN
001 =C/TO
010 = TxC (IX)
011 = TxC (16X)
100 = RxC (IX)
101 = RxC (16X)
110 = TxRDY
111 = RxRDY/FF
NOTE:
"Only OPCR[3] in block A controls the power-down mode.
7. A received break is echoed as received until
the next valid start bit is detected.
255
8. CPU-to-receiver communication continues
normally, but the CPU-to-transmitter link is
disabled.
Product Specification
Philips·Componerits-Signetics Data Communication Products
SCC26988
Enhanced octal universal asynchronous receiver/transmitter
Two diagnostic modes can also be selected.
MR2[7:6] = 10 selects localloopback mode.
In this mode:
1. The transmitter output is internally connected to the receiver input.
2. The transmit clock is usedforthe receiver.
3. The TxD output is held high.
4. The RxD input is ignored.
5. The transmitter must be enabled, but the
receiver need not be enabled.
6. CPU to transmitter and receiver communications continue normally.
The second diagnostic mode is the remote
loopback mode, selected by MR2[7:6] = 11.
I n this mode:
1. Received data is reclocked and retransmitted on the TXD output.
2. The receive clock is used forthe transmitter.
3. Received data is not sent to the local
CPU, and the error status conditions are
inactive.
4. The received parity is not checked and is
notregeneratedfortransmission, i.e., the
transmitted parity bit is as received.
5. The receiver must be enabled, but the
transmitter need not be enabled.
6. Characterframing is not checked, and the
stop bits are retransmitted as received.
7. A received break is echoed as received
until the next valid start bit is detected.
When switching in and out of the various
modes, the selected mode is activated at the
completion of all transmitted and received
characters. Likewise, if a mode is deselected,
the device will switch out of the mode at the
completion of all transmit andlor receive
characters.
MR2[5]- Transmitter Request-to-Send
Control
This bit controls the deactivation of the RTSN
output (MPO) by the transmitter. This output is
manually asserted and negated by appropriate
commands issued via the command register.
MR2[5] = 1 causes RTSN to be reset automatically one bit time after the characters in the
transmit shift register and in the THR (if any)
are completely transmitted (includes the programmed number of stop bits if the transmitter
is notenabled). This feature can be used to automatically terminate the transmission as follows:
1.
2.
3.
4.
5.
Program auto-reset mode: MR2[5] = 1.
Enable transmitter.
Assert RTSN via command.
Send message.
Verify the next to last character of the message is being sent by waiting until transmitter ready is asserted. Disable transmitter
after the last character of the message is
loaded in the THR.
November 12,1990
Table 2.
IBit 7
I
Register Bit Formats (Continued)
I
Blt6
BitS
I
Bit 4
I
Bit3
I
Bit2
I
Bit 1
I
BitO
ACR (Auxiliary Control Register)
BRGSet
Setect
Counter/Timer
Mode and Source
Delta
MPllblNT
Delta
MPIOblNT
Delta
MPllalNT
Delta
MPIOalNT
0= set 1
1 =set2
See text
O=off
1 =on
0= off
1 = on
o = off
1 = on
O=off
1 =on
IPCR (Input Port Change Register)
Delta
MPllb
Delta
MPIOb
Delta
MPlla
Delta
MPIOa
MPllb
MPIOb
MPlla
MPIOa
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= Low
1 = High
O=Low
1 = High
0= Low
1 =High
O=Low
1 = High
ISR (Interrupt Status Register)
MPIPort
Change
Delta
BREAKb
RxRDY/
FFULLb
TxRDYb
Counter
Ready
Delta
BREAKa
RxRDY/
FFULLa
TxRDYa
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
0= No
1 = Yes
IMR (Interrupt Mask Register)
MPIPort
Change
INT
Delta
BREAKb
INT
RxRDY/
FFULLb
INT
TxRDYb
INT
Counter
Ready
INT
Delta
BREAKa
INT
RxRDY/
FFULLa
INT
TxRDYa
INT
o = off
1 = on
0= off
1 =on
0= off
1 =on
o = off
1 = on
0= off
1 =on
0= off
1 = on
0=011
1 = on
0=011
1 =on
CTUR (Countermmer Lower Register)
IPR (Input Port Register)
MPP2b
MPPlb
MPP2a
MPPla
MPllb
MPIOb
MPlla
MPIOa
0= Low
1 = High
0= Low
1 = High
o = Low
0= Low
1 = High
0= Low
1 = High
0= Low
1 = High
O=Low
1 = High
O=Low
1 = High
1 = High
6. The last character will be transmitted and
RTSN will be reset one bit time after the last
stop bit.
MR2[4)- Clear-to-Send Control
The sate of this bit determines ilthe CTSN input
(MPI) controls the operation of the transmitter.
"this bit is 0, CTSN has no ellect on the transmitter. If this bit is aI, the transmitter checks the
sate of CTSN each time it is ready to send a
character. "it is asserted (Low), the character
is transmitted. If it is negated (High), the TxD
output remains in the marking state and the
transmission is delayed until CTSN goes Low.
Changes in CTSN, while a character is being
transmitted do not affect the transmission of
256
that character. This feature can be used to prevent overrun of a remote receiver.
MR2[3:0)- Stop Bit Length Select
This field programs the length olthe stop bit appended to the transmitted character. Stop bit
lengthsof9116to 1 and 1-9116 t02 bits,inincrements of 1116 bit, can be programmed for character lengths of 6, 7, and 8 bits. For a character
length of 5 bits, 1-1116 to 2 stop bits can be programmed in increments of 1116 bit. In all cases,
the receiver only checks for a mark condition at
the center of the first stop bit position (one bit
time after the last data bit, or after the parity bit
if parity is enabled). If an external 1X clock is
used for the transmitter, MR2[3] = 0 selects one
Philips Components-Signetics Data Communication Products
Product Specification
Enhanced octal universal asynchronous receiver/transmitter
stop bit and MR2(3] = 1 selects two stop bits to
be transmimed.
0100
CSR - Clock Select Register
CSR[7:4]- Receiver Clock Select
When using a 3.6864MHz crystal or external
clock input, this field selects the baud rate clock
for the receiver as shown in Table 3.
Table 3.
CSR[7:4]
Baud Rate
ACR[7] = 0
0000
0001
00 10
00 t 1
a 10 a
a 10 1
01 10
011 1
1000
100 1
1010
1011
1100
1101
1110
1111
50
110
134.5
200
300
600
1,200
1,050
2,400
4,800
7,200
9,600
38.4k
TImer
MP2 -16X
MP2-1X
ACR[7]
=1
75
110
38.4k
150
300
600
1,200
2,000
2,400
4,800
1,800
9,600
19.2k
Timer
MP2-16X
MP2-1X
The receiver clock is always a 16X clock, except for CSR[7:4] = 1111. When MPP2 is selected as the input, MPP2a is for channel a and
MPP2b is for channel b.
CSR[3:] - Transmitter Clock Select
This field selects the baud rate clock for the
transmitter. The field definition is as shown in
Table 3, except as follows:
CSR[3:0]
1 1 1a
1111
ACR[7] = 0
MPPI - 16X
MPPI - IX
0101
0110
0111
1000
1001
1010
ACR[7] = 1
MPP1-16X
MPP1-1X
When MPPI is selected as the input, MPPI a is
for channel a and MPP 1b is for channel b.
CR - Command Register
1011
1100
CR is used to write commands to the Octal
UART.
CR[7:4]- Miscellaneous Commands
The encoded value of this field can be used to
specify a single command as follows:
0000
0001
0010
0011
No command.
Reset MR pointer. Causes the MR
pointer to point to MRI.
Reset receiver. Resets the receiver as if a hardware reset had been
applied. The receiver is disabled
and the FIFO pointer is reset to the
first location.
Reset transmitter. Resets the
transmitter as if a hardware reset
had been applied.
November 12, 1990
1101
l11x
Reset error status. Clears the received break, parity error, framing
error, and overrun error bits in the
status register (SR(7:411. Used in
character mode to clear OE status
(although RB, PE, and FE bits will
also be cleared), and in block
mode to clear all error status after
a block of data has been received.
Reset break change interrupt.
Causes the break detect change
bit in the interrupt status register
(ISR(2 or 6]) to be cleared to zero.
Start break. Forces the TxD output
low (spacing). If the transmitter is
empty, the start of the break condition will be delayed up to two bit
times. II the transmitter is active,
the break begins when transmission of the character is completed.
If a character is in the THR, the
start of break is delayed until that
character or any others loaded after it have been transmitted
(TxEMT must be true before break
begins). The transmitter must be
enabled to start a break
Stop break. The TxD line will go
high (marking) within two bit times.
TxD will remain high for one bit
time before the next character, if
any, is transmitted.
Assert RTSN. Causes the RTSN
output to be asserted (Low).
Negate RTSN. Causes the RTSN
output to be negated (High).
Set TImeout Mode On. The register in this channel will restart the C/
T as each receive character is
transferred from the shift register
to the RHR. The CIT is placed in
the counter mode, the START/
STOP counter commands are disabled, the counter is stopped, and
the Counter Ready Bit, ISR(3], is
reset.
Reserved.
Disable Timeout Mode. This command returns control of the CIT to
the regular START/STOP counter
commands. It does not stop the
counter, or clear any pending interrupts. After disabling the timeout
mode, a 'Stop Counter' command
should be issued.
Reserved.
Reserved for testing.
CR[3]- Disable Transmitter
This command terminates transmitter operation and resets the TxRDY and TxEMT status
bits. However, if a character is being transmitted or if a character is in the TH R when the
transmitter is disabled, the transmission of the
character(s) is completed before assuming the
inactive state.
257
SCC26988
CR[2]- Enable Transmitter
Enables operation of the transmitter. The
TxRDY status bit will be asserted.
CR[1]- Disable Receiver
This command terminates operation of the receiver immediately - a character being received will be lost. The command has no effect
on the receiver status bits or any other control
registers. If the special wake-up mode is programmed, the receiver operates even if it is disabled (see Wake-up Mode).
CR[O]- Enable Receiver
Enables operation of the receiver. If not in the
special wake-up mode, this also forces the receiver into the search for start bit state.
SR - Channel Status Register
SR[7] - Received Break
This bit indicates that an all zero character of
the programmed length has been received
without a stop bit. Only a single FIFO position
is occupied when a break is received: further
entries to the FIFO are inhibited until the RxDA
line returns to the marking state for at least onehalf bit time (two successive edges of the internal or external 1x clock).
When this bit is set, the change in break bit in
the ISR (ISR(6 or 2]) is set. ISR(6 or 2] is also
set when the end of the break condition, as defined above, is detected. The break detect circuitry is capable of detecting breaks that
originate in the middle of a received character.
However, if a break begins in the middle of a
character, it must last until the end of the next
character in order for it to be detected.
SR[6]- Framing Error (FE)
This bit, when set, indicates that a stop bit was
not detected when the corresponding data
character in the FIFO was received. The stop
bit check is made in the middle of the first stop
bit position.
SR[5]- Parity Error (PE)
This bit is set when the 'with parity' or 'force parity' mode is programmed and the corresponding character in the FIFO was received with
incorrect parity. In special 'wake-up mode', the
parity error bit stores the received AID bit.
SR[4]- Overrun Error (OE)
This bit, when set, indicates that one or more
characters in the received data stream have
been lost. It is set upon receipt of a new character when the FI FO is full and a character is already in the receive shift register waiting for an
empty FIFO position. When this occurs, the
character in the receive shift register (and its
break detect, parity error and framing error status, if any) is lost. This bit is cleared by a reset
error status command.
Philips Components-Signetics Data Communication Products
Product Specification
Enhanced octal universal asynchronous receiver/transmitter
SR[3]- Transmitter Empty (TxEMT)
This bit will be set when the transmitter underruns, i.e., both the transmit holding register and
the transmit shift register are empty. It is set after transmission of the last stop bit of a character, If no character is in the THR awaiting
transmission. It is reset when the THR is loaded
by the CPU, or when the transmitter is disabled.
SR[2]- Transmitter Ready (TxRDY)
This bit, when set, indicates that the THR is
empty and ready to be loaded with a character.
This bit is cleared when the THR is loaded by
the CPU and is set when the character is transferredto the transmit shift register. TxRDY is reset when the transmitter is disabled and is set
when the transmitter is first enabled, e.g., characters loaded in the THR while the transmitter
is disabled will not be transmitted.
SR[l]- FIFO Full (FFULL)
This bit is set when a character is transferred
from the receive shift register to the receive
FIFO and the transfer causes the FIFO to be-.
comefull, i.e., all three FIFOpositionsareoccupied. It is reset when the CPU reads the FIFO
and there is no character in the receive shift
register. If a character is waiting in the receive
shift register because the FIFO is full, FFUllis
not reset after reading the FIFO once.
SR[O]- Receiver Ready (RxROY)
This bit indicates that a character has been received and is waiting in the FIFO to be read by
the CPU. It is set when the character is transferredfrom the receive shift register to the FIFO
and reset when the CPU reads the RHR, and
no more characters are in the FIFO.
OPCR - Output Port
Configuration Register
OPCR[7] - MPP Function Select
When this bit is a zero, the MPP pins function
as inputs, to be used as general purpose inputs
or as receiver or transmitter external clock inputs. When this bit is set, the MPP pins function
as outputs. MPPl will be a TxROY indicator,
and MPP2 will be an RxROY/FFUll indicator.
OPCR[6:4]- MPOb Output Select
This field programs the MPOb output pin to provide one of the following:
Request-to-send active-low out000
put (RTSN). This output is asserted and negated via the command register. Mode RTSN can be
programmed to be automatically
reset after the character in the
transmitter is completely shifted
out or when the receiver FIFO and
receiver shift register are full using
MR2[S] and MR 1[7], respectively.
November 12, 1990
001
The counter/timer output. In the
timer mode, this output is a square
wave with a period of twice the value (in clock periods) of the contents of the CTUR and CTlR. In
the counter mode, the output remains high until the terminal count
is reached, at which time it goes
low. The output returns to the High
state when the counter is stopped
by a stop counter command.
010
The lX clock for the transmitter,
which is the clock that shifts the
transmitted data. If data is not being transmitted, a non-synchronized 1X clock is output.
011
The 16X clock for the transmitter.
This is the clock selected by
CSR[3:0], and is a 1X clock if
CSR[3:0] = 1111.
100
The 1X clock for the receiver,
which is the clock that samples the
received data. If data is not being
received, a non-synchronized 1X
clock is output.
101
The 16X clock for the receiver. This
is the clock selected by CSR[7:4],
and is a IX clock if CSR[7:4] =
1111.
110
The transmitter register empty signal, which is the same as SR[3].
111
The receiver ready or FIFO full signal.
OPCR[3]- Power Down Mode Select
This bit, when set, selects the power-down
mode. In this mode, the 26989 oscillator is
stopped and all functions requiring this clock
are suspended. The contents of all registers are
saved. It is recommended that the transmitter
and receiver be disabled prior to placing the
26989 in this mode. This bit is reset with RESET asserted. Note that this bit must be set to
a logic 1 after power up. Only OPCR[3] in block
A controls the power-down mode.
OPCR[2:0]- MPOa Output Select
This field programs the MPOa output pin to provide one of the same functions as described in
OPCR[6:4].
ACR - Auxiliary Control Register
ACR[7J - Baud Rate Generator Set Select
This bit selects one of two sets of baud rates
generated by the 9RG.
258
SCC2698B
Set 1:
50, 110, 134.S, 200, 300, 600,
1.0Sk, 1.2k, 2.4k, 4.8k, 7.2k, 9.6k,
and 38.4k baud.
Set 2:
7S, 110, ISO, 300, 600, 1.2k, 1.8k,
2.0k, 2.4k, 4.8k, 9.6k, 19.2k, and
38.4kbaud.
The selected set of rates is available for use by
the receiver and transmitter.
ACR[6:4] - CounterlTimer Mode and Clock
Source Select
This field selects the operating mode of the
counter/timer and its clock source (see Table
4).
The MPI pin available as the clock source is
MPI a,c,e, and g only.
Table 4.
[6:4)
o0
o0
o1
o1
ACR[6:4] Operating
Mode
Mode
Clock Source
0
1
0
Counter
Counter
Counter
1
Counter
MPI pin
MPI pin divided by 16
TxC-1XA clock of
the transmitter
Crystal or external
clock (Xl/ClK)
divided by 16
MPI pin
MPI pin divided by 16
Crystal or extemal
clock (Xl/ClK)
Crystal or external
clock (Xl/ClK)
divided by 16
1 0 0
1 0 1
1 1 0
Timer
Timer
Timer
111
Timer
ACR[3:0]- MPII b, MPIOb, MPlla, MPIOa
Change-of-State Interrupt Enable
This field selects which bits of the input port
change register (IPCR) cause the input change
bit in the interrupt status register, ISR[7], to be
set. If a bit is in the 'on' state, the setting of the
corresponding bit in the IPCR will also result in
the setting of ISR[7), which results in the generation of an interrupt output if I MR[7] = 1. If a bit
is in the 'off' state, the setting of that bit in the
IPCR has no effect on ISR[7].
IPCR - Input Port Change
Register
IPCR[7:4)- MPllb, MPIOb, MPlla, MPIOa
Change-of-State
These bits are set when a change of state, as
defined in the Input Port section of this data
Philips Components-Signetics Data Communication Products
Product Specification
Enhanced octal universal asynchronous receiver/transmitter
sheet. occurs at the respective pins. They are
cleared when the IPCR is read by the CPU. A
read of the IPCR also clears ISR[7], the input
change bit in the interrupt status register. The
setting of these bits can be programmed to generate an interrupt to the CPU.
ISR[3] - Counter Ready
In the counter mode of operation, this bit is set
when the counter reaches terminal count and
is reset when the counter is stopped by a stop
counter command. It is initialized to '0' when the
chip is reset.
IPCR[3:0]- MPI1b, MPIOb, MPI1a, MPIOa
Change-ol-State
These bits provide the current state of the respective inputs. The information is unlatched
and reflects the state of the inputs pins during
the time the IPCR is read.
In the timer mode, this bit is set once each cycle
althe generated square wave (every other time
the CIT reaches zero count). The bit is reset by
a stop counter command. The command, however, does not stop the CIT.
ISR - Interrupt Status Register
This register provides the status of all potential
interrupt sources. The contents of this register
are masked by the interrupt mask register
(IMR). II a bit in the ISR is a '1' and the corresponding bit in the IMR is also a '1', the INTRN
output is asserted (Low). If the corresponding
bit in the IMR is a zero, the state of the bit in the
ISR has no effect on the INTRN output. Note
that the IMR does not mask the reading of the
ISR; the true status is provided regardless of
the contents of the IMR.
ISR[7] - MPI Change-ol-State
This bit is set when a change-of-state occurs at
the MPllb, MPIOb, MPlla, MPIOainputpins.lt
is reset when the CPU reads the IPCR.
ISR[6]- Channel b Change In Break
This bit, when set, indicates that the receiver
has detected the beginning or the end of a received break. It is reset when the CPU issues
a reset break change interrupt command.
ISR[S]- Receiver Ready or FIFO Full
Channel b
The function of this bit is programmed by
MRI [6]. II programmed as receiver ready, it indicates that a character has been received and
is waiting in the FIFO to be read by the CPU. It
is set when the character is transferred from the
receive shift register to the FIFO and reset
when the CPU reads the receiver FIFO. If the
FIFO contains more characters, the bit will be
set again after the FIFO is read.
II programmed as FIFO full, it is set when a
character is transferred from the receive holding register to the receive FIFOandthetransfer
causes the FIFO to become full, i.e., all three
FIFO positions are occupied. It is reset when
FIFO is read and there is no character in the receiver shift register. If there is a character waiting in the receive shift register because the
FIFO is full, the bit is set again when the waiting
character is transferred into the FIFO.
ISR[2]- Channel a Change in Break
This bit, when set, indicates that the receiver
has detected the beginning or the end 01 a received break. It is reset when the CPU issues
a reset break change interrupt command.
ISR[1]- Receiver Ready or FIFO Full
Channel a
The function of this bit is programmed by
MR 1[6]. If programmed as receiver ready, it indicates that a character has been received and
is waiting in the FIFO to be ready by the CPU.
It is set when the character is transferred from
the receive shift register to the FIFO and reset
when the CPU reads the receiver FIFO. If the
FIFO contains more characters, the bit will be
set again after the FIFO is read. If programmed
as FIFO full, it is set when a character is transferred from the receive holding register to the
receive FIFO and the transfer causes the FIFO
to become full, i.e., all three FIFO positions are
occupied. It is reset when FIFO is read and
there is no character in the receiver shift register. II there is a character waiting in the receive
shift register because the FIFO is full, the bit is
set again when the waiting character is transferred into the FIFO.
ISR[O]- Transmitter Ready Channel a
This bit is a duplicate of TxRDY (SR[2]).
IMR - Interrupt Mask Register
The programming of this register selects which
bits in the ISRcause an interrupt output. II a bit
in the ISR is a '1' and the corresponding bit in
the IMR is a '1', the INTRN output is asserted
(Low). If the corresponding bit in the IMR is a
zero, the state 01 the bit in the ISR has no effect
on the INTRN output. Note that the IMR does
not mask reading of the ISR.
CTUR and CTLR - Counter/Timer
Registers
The CTUR and CTLR hold the eight MSBs and
eight LSBs, respectively, of the value to be used
by the counterltimer in either the counter or tim-
ISR[4]- Transmitter Ready Channel b
This bit is a duplicate of TxRDY (SR[2]).
November 12, 1990
259
SCC26988
er modes 01 operation. The minimum value
which may be loaded into the CTURlCTLR registers is H'OO02'. Note that these registers are
write-only and cannot be read by the CPU.
In the timer (programmable divider) mode, the
CIT generates a square wave with a period of
twice the value (in clock periods) of the CTUR
and CTLR. If the value in CTUR or CTLA is
changed, the current half-period will not be affected, but subsequent half-periods will be. The
CIT will not be running until it receives an initial
'Start Counter' command (read at adddress
A3-AO = 1110). Afterthis, while in timer mode,
the CIT will run continuously. Aeceipt of a subsequent sttart counter command causes the CI
T to terminate the current timing cycle and to
begin a new cycle using the values in the CTUA
andCTLR
The counter ready status bit (ISR[3]) is set once
each cycle of the square wave. The bit is reset
by a stop counter command read with A3-AO =
H'F'). The command. however. does not stop
the CIT. The generated square wave is output
on MPO if it is programmed to be the CIT output.
In the counter mode, the CIT counts down the
number of pulses loaded in CTUAand CTLRby
the CPU. Counting begins upon receipt of a
start counter command. Upon reaching the terminal count H'OOOO', the counter ready interrupt bit (ISA[3]) is set. The counter continues
counting past the terminal count until stopped
by the CPU. If MPO is programmed to be the
output of the CIT, the output remains High until
the terminal count is reached, at which time it
goes Low. The output returns to the High state
and ISA[3] is cleared when the counter is
stopped by a stop counter command. The CPU
may change the values of CTUR and CTLA at
any time, but the new count becomes effective
only on the next start counter command. If new
values have not been loaded, the previous values are preserved and used for the next count
cycle.
In the counter mode, the current value of the upper and lower eight bits of the counter (CTU,
CTL) may be read by the CPU. It is recommended that the counter be stopped when
reading to prevent potential problems which
may occur if a carry from the lower eight bits to
the upper eight bits occurs between the times
that both halves of the counter is read. However, note that a subsequent start counter command will cause the counter to begin a new
count cycle using the values in CTUA and
CTLA.
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced octal universal asynchronous receiver/transmitter
SCC2698B
ABSOLUTE MAXIMUM RATINGSl
SYMBOL
PARAMETER
TA
Operating ambient temperature range2
TSTG
Storage temperature range
Vee
Voltage from Voo to GN03
Vs
Voltage from any pin to ground3
Po
Power dissipation
UNIT
RATING
Note 4
°C
--65 to +150
°C
--{l.5 to +7.0
V
--{l.S to Vee +0.5
V
I
W
NOTES:
I. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and lunctional operation of the device at these or any other condition above those indicated in the operation section of this specification is not implied.
2. For operating at elevated temperatures, the device must be derated based on + 150°C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge.
Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating supply
range.
DC ELECTRICAL CHARACTERISTICS1, 2, 3
LIMITS
SYMBOL
PARAMETER
VIL
VIH
VIH
Input low voltage
Input high voltage (except X I/ClK)
Input high voltage (XI/ClK)
VOL
VOH
Output low voltage
Output High voltage (except 00 outputs)
IlL
IIH
Input current low, MPI and MPP pins
Input current High, MPI and MPP pins
TEST CONDITIONS
Min
Typ
Max
UNIT
O.S
V
V
V
0.4
V
V
V
2.0
O.SVee
IOL= 2.4mA
IOH = -400JlA
IOH = -100JlA
VIN = 0
VIN = Vee
II
Input leakage current
ilLXl
IIHXl
XI/ClK input low current
Xl/ClK input High current
IOZH
IOZL
Output off current High, 3-State data bus
Output off current low, 3-State data bus
VIN = Vee
VIN = 0
IOOL
IOOH
Open-drain output low current in off state: IRON
Open-drain output low current in off state: IRON
VIN = Vee
VIN = 0
Icc
Power supply current
Operating mode
O.SVee
0.9Vee
-50
VIN =OtoVee
-10
VIN = GND, X2 = open
VIN = Vee, X2 = open
-100
Power down mode
20
JlA
JlA
10
JlA
tOO
JlA
JlA
10
-10
JlA
-10
10
JlA
30
mA
2.0
mA
NOTES:
I. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating supply
range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 20ns
maximum. For XI/ClK this swing is between 0.4 V and4.4V. All time measurements are referenced at input voltages of VIL and VIH, as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test condition for interrupt and MPP outputs: CL = 5OpF, RL = 2.7k!l to Vee. Test conditions for rest of outputs: CL = ISOpF.
5. Timing is illustrated and referenced to the WRN and RON inputs. The device may also be operated with CEN as the 'strobing' input. CEN and
RON (also CEN and WRN) are AN Oed intemally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle.
6. If CEN is used as the 'strobing' input, the parameter defines the minimum high times between one CEN and the next. The RON signal must be
negated for tRWO guarantee that any status register changes are valid.
7. Consecutive write operations to the command register require at least three rising edges of the XI clock between writes.
S. This value is not tested, but is guaranteed by design.
November 12, 1990
260
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced octal universal asynchronous receiver/transmitter
AC ELECTRICAL CHARACTERISTICS1,
SCC26988
2, 3, 4
LIMITS
SYMBOL
FIGURE
Min
PARAMETER
Typ
Max
UNIT
Reset timing
3
Reset pulse width
tREs
4
AD-A5 setup time to RON, WRN Low
tRES
4
AD-A5 hold time from RON, WRN High
tes6
4
teH6
tRES
200
ns
Bus timingS
10
ns
100
ns
CEN setup time to RON, WRN Low
0
ns
4
CEN hold time from RON, WRN High
0
ns
tRW
4
WRN, RON pulse width Low
225
ns
too
4
Oata valid after RON Low
200
ns
tOF
4
Data bus floating after ROI>J High
80
ns
tos
4
Data setup time before WRN High
toH
4
tRwo7
4
100
ns
Data hold time after WRN High
10
ns
TIme between reads and/or writes
100
ns
MPI and MPO timing 5
tps
5
MPI or MPP input setup time before RON low
0
ns
tpH
5
MPI or MPP input hold time after RON High
0
ns
tpo
5
MPO output valid from
WRN High
RON Low
250
250
ns
ns
INTRN negated or MPP output High from:
Read RHR (RxROY/FFULl interrupt)
Write THR (TxROY interrupt)
Reset command (break change interrupt)
Reset command (MPI change interrupt)
Stop
command (counter interrupt)
Write IMR (clear of interrupt mask bit)
270
270
270
270
270
270
ns
ns
ns
ns
ns
ns
4.0
MHz
4.0
MHz
2.0
1.0
MHz
MHz
2.0
1.0
MHz
MHz
350
ns
150
ns
Interrupt timing
tlR
6
crr
Clock timing
!eLK
!eLK
7
Xl/ClK high or low time
120
7
Xl/ClK frequency
2.0
teTe
7
Counter/timer clock high or low time
120
feTe
7
Counter/timer clock frequency
08
tRX
7
RxC high or low time
200
fRx
7
RxC frequency (16X)
RxC frequency (1 X)
08
08
tTx
7
TxC high or low time
200
fTX
7
TxC frequency (16X)
TxC frequency (1 X)
08
08
ns
3.6864
ns
ns
ns
Transmitter timing
tTXO
8
TxD output delay from TxC low
tTes
8
TxC output delay from TxO output data
tRxs
9
RxO data setup time to RxC high
50
ns
tRXH
9
RxD data hold time from RxC high
100
ns
0
Receiver timing
November 12,1990
261
Proc;luct·Specification
Philips Comp$nents-Signetics D.ata Communication Products
Enhanced octa.1 universaJasynchronousrecei.ver/transmitt.er
2.7K
INTRAII-INTRDN,
MPPt.~MPPlh,.
MPi"2a-MPP2h
0
f~
'VV'v
o
+5V
+5V
-
1.61(
00-1)7,
TxDa-Tx-Dh.
MPOa-MPOh
&K
l50pF
FillJolre 2. Test Conditions Qn Ou·tpuls
Figure 3. Reset Timing
_A5
RDN
DO-D7
FLOAT
(ReAD)
waN
DO-D7
(WRITE)
Figure 4. Bus Timing
November 12, 1990
262
SCC2698B
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced octal universal asynchronous receiver/transmitter
SCC26988
WRN
RON
tpo
---------+1
~ ________________________
~~
~
-J~I~
NEW DATA
__________
__
Figure S. Port TIming
WRN
INTE;:~:UTT'
~'--
--//Vv;,;-
___
I--
~R
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _L
_
~O~~VVOl
...;: Pfo:C--::::::::::=--~-R--------------------.J-f~_~ .~
NOTES:
1. INCLUDES MPP WHEN USED AS T,RDY or R,DYtFFULL OUTPUTS AS WELL AS INTRN.
2. THE TEST FOROPEN DRAIN OUTPUTS IS INTENDED TO GUARANTEE SWITCHING OF THE OUTPUT TRANSISTOR. MEASUREMENT Of: THIS RESPONSE IS REF-
ERENCED FROM THE MIDPOINT OF THE SWITCHING SIGNAL. VM. TO A POINTO.5V ABOVE VOL. THIS POINT REPRESENTS NOISE MARGIN THAT ASSURES TRUE
SWITCHING HAS OCCURRED. BEYOND THIS LEVEL. THE EFFECTS OF EXTERNAL CIRCUITRY AND TEST ENVIRONMENT ARE PRONOUNCED AND CAN GREATLY
AFFECT THE RESULTANT MEASUREMENT.
Figure 6. Interrupt TIming
November 12. 1990
263
Product Specification
Philips Components'-Signetics Data Communication Products
Enhanced octal universal asynchronous receiver/transmitter
SCC26988
teLK
teTC
X1fCLK
CTCLK
R.C
-D
T.C
C1
=C2 =24pF FOR C, =20PF
SCC2698B
X1
=
' -_ _ _ _ _ _---~X~2-1---.-----'~-----L_TO INTERNAL CLOCK DRIVERS
3.6864MHz
1
4pF
NOTE:
C1 AND C2 SHOULD BE BASED ON MANUFACTURER'S SPECIFICATION,
TYPICAL CRYSTAL SPECIFICATION
FREQUENCY:
2 -4MHZ
LOAD CAPACITANCE (C,):
12 - 32pF
PARAllEL RESONANT, FUNDAMENTAL MODE
TYPE OF OPERATION:
Figure 7, Clock Timing
T.C
(INPUT)
T.D
T.C
(1XOUTPUT)
Figure 8, Transmit Timing
R.C
('XINPUT)
R.D
Figure g, Receive Timing
November 12, 1990
264
Product Specification
Philips Components-Signetics Data Communication Products
Enhanced octal universal asynchronous receiver/transmitter
SCC26988
TxD
TxRDV
(SR2)
WRN
CTSN
(MPIO ' _ _ _ _- - '
7,
RTSN 2
(MPO)
b
- - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _,
CR[7:4]
0
1010
(.~
CR[7:4]
0
1010
NOTES:
1. TIMING SHOWN FOR MA2[4] = 1.
2. TIMING SHOWN FaA MA215] _1.
Figure 10. Transmitter Timing
RxD
~~~~~:~r------+-----~-----------4-+---~---~
RxRDY
(SRO)
D2
FFULL
(SR1) _ _ _ _ _ _ _ _ _ _ _ _ _
-+________________J
RxROYI
FFULL
MP02
RDN
So STATUS
Do DATA
~
Dl
OVERRUN
(SR4) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
--!-___...:.:;;;;;;J
MPO
=1 (CR[7:4] =1010)
NOTES;
1. T1MINGSHOWNFORMR1[7]_1.
2. SHOWN FOR OPCR [6:4. 2:0]- 111 AND MA1[61_
o.
Figure 11. Receiver Timing
November 12,1990
265
RESET BY
COMMAND
Philips Components-Signetics Data Communication Products
Product Specification
Enhanced octal universal asynchronous receiver/transmitter
MASTER STAnON
BITo
I
TxD
IADD"I'I
BITO
I
DO
I 0
I
I I
-"~ESJ
~~=
CSN
(WRITE]
MRI [2]=0 DO
PERIPHERAL STAnON
BI19
RxD
I
I
RECEIVER
ENABLED
R.RDY
(SOO)
RDNIW;-U
MRI [4:3] = 11
1
0 I
MRI[2]= I
BITo
BITo
I
:
I I
:
'I I I
IADD"I'I:
I
I
I
I
I
DO
i
0 I :
I
I
~
I
ADD12
:
:
BITo
I
I ADDM211 I
ri :
~
ADD.1
Figure 12. Wake-Up Mode
266
BITO
I
I 0 I
I
I
I
I
I
i
I
I
DO
November 12, 1990
BIT.
ADDI2I
:~ :
(SR2)
MRI [4:3] = 11 ADDMI
MRI [2]= I
:
SCC26988
S = STATUS
0= DATA
:
~
~
ADDM2
I
II-
4-
Philips Components-Signetics
Document No.
853--
(
4-tRDLRR
,,
/
H
tRDHEOZ
/1
® The RxFIFO is addressed during this read cycle.
Figure 11. Receive Dual Address DMA Timing
LIMITS
SYMBOL
PARAMETER
SCN26562C4
Min
tRDlRRH
tRDlEOl
tRDHEOZ
October 30, 1990
RON low to Rx DMA REQN high
RON low to EOPN output low
RON high to EOPN output high impedance
Max
320
300
225
278
SCN26562C2
Min
UNIT
Max
320
300
225
ns
ns
ns
Product Specification
Philips Components--Signetics Data Communication Products
Dual universal serial communications controller
(DUSCC)
SCN26562
AC ELECTRICAL CHARACTERISTICS (Continued)
TIRQN
l)
I-- trAHTAL
TxDAKN
~
"
V
tTALTAH
WRN
MEMRN
trALTRH
)'
~
--------
~---
"'--@-..../
--~I----
/
------"
'----_..../
/
----
~--
'TAHEI1H
I--- 'EILTAH
,
EOPN
(INPUT)
CtwOVTAH
07-00
T
.i'TAHWDI
"k:
/'
"
"
--
tTAHEOF
r----EOPN
'TALEOL
"-
(OUTPUT)
-
NOTES:
® Ignored by the DUSCC since CEN is not asserted, but it can be used externally to qual~y TxDAKN.
® Memory read signal; not seen by DUSCC.
Figure 12. DMA-Transmit Single Address Mode
LIMITS
SYMBOL
PARAMETER
SCN26562C4
Min
tTAHTAl
tTALTAH
tTALTRH
tWDVTAH
tTAHWDI
tTALEOL
tTAHEOF
tEILTAH
tTAHEIH
October 30, 1990
Transmit DMA ACKN high to low time
Transmit DMA ACKN low to high time
Tx DMA ACKN low to Tx DMA REQN high
Write data valid to Tx DMA ACKN high
Tx DMA ACKN high to write data invalid
Tx DMA ACKN low to EOPN output low
Tx DMA ACKN high to EOPN output float
EOPN input low to Tx DMA ACKN high
Tx DMA ACKN high to EOPN input high
Max
SCN26562C2
Min
100
250
100
250
250
250
90
30
90
30
170
200
170
200
50
50
279
50
50
UNIT
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
Product Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller
SCN26562
(DUSCC)
AC ELECTRICAL CHARACTERISTICS (Continued)
RxDRQN
RxDAKN
"
tRALRRH
'RAHRAL
~
/
tRALRAH
~
RON
MEMWN
---
---
,'--@-..../ ,---- ---cr---/
---
,'-----_..../
.-
EOPN
(OUTPUT)
-
07-00
'RALDDV
----
;--/
tRAHEOF
tRALEOL
1--+
'"
f---
~
>-
-1tRAHDDI
/
1"'
"
I tRAHOOF
NOTES:
® Ignored by the DUSCC bit; it can be used to qualify RxOAKN.
® Memory read signal; not seen by DUSCC.
Figure 13. DMA-Receive Single Address Mode
LIMITS
SYMBOL
PARAMETER
SCN26562C4
Min
tRAHRAL
tRALRAH
tRALRRH
tRALEOL
tRAHEOF
tRALDDV
tRAHDDI
tRAHDDF
October 30. 1990
Receive DMA ACKN high to low time
Receive DMAACKN low to high time
Rx DMA ACKN low to Rx DMA REQN high
Rx DMA ACKN low to EOPN output low
Rx DMA ACKN high to EOPN output float
Rx DMA ACKN low to read data valid
Rx DMA ACKN high to read data invalid
Rx DMA ACKNhigh to data bus float
Max
160
250
SCN26562C2
Min
160
250
320
200
225
225
10
280
320
200
225
225
10
125
UNIT
Max
125
ns
ns
ns
ns
ns
ns
ns
ns
Product Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller
(DUSCC)
SCN26562
AC ELECTRICAL CHARACTERISTICS (Continued)
"'---------tR-W-H~'&~.
RDNlWRN
IRON _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
---'u
_
VOL
Figure 14. Interrupt Timing
LIMITS
SYMBOL
PARAMETER
SCN26562C4
Min
tRWHIRH
RDNIWRN high to IRON high for:
Read RxFIFO (RxRDY interrupt)
Write TxFIFO (TxRDY interrupt)
Write RSR (Rx condition interrupt)
Write TRSR (RxlTx interrupt)
Write ICTSR (counter/timer interrupt)
450
450
400
400
400
X1/ClK
WRN~
COMMAND
VAUD
Figure 15. Command Timing
October 30. 1990
Max
281
SCN26562C2
Min
UNIT
Max
450
450
400
400
400
ns
ns
ns
ns
ns
Product Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller
(DUSCC)
SCN26562
RxC
Rxe
LCN
e. Loop Control Output Assertion
RxC
Rxe
LCN
______________________________________________________- - J
b. Loop Control Output Negation
Figure 16. Relationship Between Received Data and the Loop Control Output
2.7K
IRON •
I
I
=
"IN
• Vee
SOpF
82110
RDYN •
II
"IN
• +s.OV
150pF
1K
EOPN •
I
I
"IN
• Vee
50PF
.....
ALL OTHER
OUTPUTS
710
v
~
150PF:i
=
~
~r:
-=
~r:
~~
:-
NOTE,
All Cl includes 50pF stray capacitance,
Le .• Cl '" 15ClJF '" 1OOpF discrete +5OpF stray.
Figure 17. Test Conditions for Outputs
October 30. 1990
282
..s.OV
Philips Components-5ignetics
Document No.
ECN No.
Date of Issue
NovemberS, 1990
Status
Preliminary Specification
Data Communication Products
DESCRIPTION
The Signetics Dual Universal Serial
Communications Controller (DUSCC)
is a single-chip CMOS-LSI
communications device that provides
two independent, multi-protocol,
full-duplex receiver/transmitter channels
in a single package. It supports
bit-oriented and character-oriented (byte
count and byte control) synchronous
data link controls as well as
asynchronous protocols. The new
CMOS device (SC26C562/SC68C562)
will be pin hardware and software
compatible with the present SCN26562
and SCN68562. All design variances in
the NMOS device had been corrected.
However after power up the CMOS
DUSCC will be configured to operate as
the NMOS DUSCC.
The operating mode and data format of
each channel can be programmed
independently. Each channel consists of
a receiver, a transmitter, a 16-bit
multifunction counterltimer, a digital
phase locked loop (DPLL), a parity/CRC
generator and checker, and associated
control circuits. The two channels share
a common bit rate generator (BRG),
operating directly from a crystal or an
external clock, which provides sixteen
common bit rates simultaneously. The
operating rate for the receiver and
transmitter of each channel can be
independently selected from the BRG,
the DPLL, the counterltimer, or from an
external 1X or 16X clock, making the
DUSCC well suited for dual-speed
channel applications. Data rates up to
4.0Mbits per second are supported.
SC26C562/SC68C562
Dual universal serial
communications controller (DUSCC)
Preliminary Features and Additions between
NMOS and CMOS devices.
Familiarity with the DUSCC users guide is assumed.
receiver status bits. This permits reading
and writing of up to sixteen characters at
a time, minimizing the potential of
receiver overrun or transmitter underrun,
and reducing interrupt or DMA
overhead. In addition, a flow control
capability is provided to disable a
remote transmitter when the FIFO of the
local receiving device is full.
Two modem control inputs (DCD and
CTS) and three modem control outputs
(RTS and two general purpose) are
provided. Because the modem control
inputs and outputs are general purpose
in nature, they can be optionally
programmed for other functions.
Two versions of the DUSCC are
available. The SC26C562 is optimized
to interface with processors using a
synchronous bus interface, such as the
8086, 80186 and 80286. The SC68C562
is optimized to interface with processors
using an asynchronous bus interface,
such as the 68000 and 68010. Both
versions are capable of program-polled,
interrupt-driven, block-move or DMA
data transfers. The contents of this
manual apply to both versions of the
DUSCC, unless explicitly noted
otherwise.
FEATURES
General Features
• Multi-protocol operation
• Sixteen character receiver and
transmitter FIFOs. Nine status bits
fifoed with each byte received.
• 0 to 10Mbit/sec. data rate
• Programmable bit rate for each
receiver and transmitter
• Parity and FCS (frame check
sequence LRC or CRC) generation
and checking
• Programmable data
encoding/decoding: NRZ, NRZI, FMO,
FM1, Manchester
• Programmable channel mode: full- or
half-duplex, auto-echo, or local
loopback
• Programmable data transfer mode:
polled, interrupt, DMA, wait
• Single- or dual-address DMA transfers
• Two multi-function programmable
16-bit counter/timers
• On-chip oscillator for crystal
Asynchronous Mode
• Character length: 5 to 8 bits
• Odd or even parity, no parity, or force
parity
• Up to two stop bits programmable in
1/16-bit increments
• Break generation with handshake for
counting break characters
• Detection of start and end of received
break
• Character compare with optional
interrupt on match
• Transmit up to 4.0Mbps and receive
up to 2.0Mbps data rates
The transmitter and receiver each
contain a sixteen characters FIFOs with
appended transmitter command and
283
Philips Components-Signetics Data Communication Products
Preliminary Specification
Dual universal serial communications controller
(DUSCC)
FEATURES (Continued)
• Idle in MARK or SYNs
Character-Oriented Protocols
• BISYNC submode
• Character length: 5 to 8 bits
Bit-Oriented Protocol
• Odd or even parity, no parity, or force parity
• Character length: 5 to 8 bits
• LRC or CRC generation and checking
• Optional opening PAD transmission
• Detection and transmission of residual
character: 0-7 bits
• One or two SYN characters
• Optional opening PAD transmission
• SYN detection and optional stripping
• Detection and generation of FLAG,
ABORT, and IDLE bit patterns
• SYN or MARK linefill or underrun
November 8, 1990
SC26C562/SC68C562
• ABORT, ABORT-FLAGs, or FCS-FLAGs
linefill on underrun
• Idle in MARK or FLAGs
284
• Secondary address recognition including
group and global address
• Single- or dual-octet secondary address
• CRC generation and checking
• SDLC loop mode capability
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller
(DUSCC)
BLOCK DIAGRAM -
SC26C562/SC68C562
SC68C562
['1
OO-D7
BUs
BUFFER
CHANNEL MODE
AND TIMING AlB
~
/1
~_
~
DPll eLK
MUXA/S
DPLl AlB
INTERFACE!
OPERATION
CONTROL
I
DTACKN
RWN
Al-A6
~
-.
CSN = :
RESETN
RTxDRQANlGP01AN
RTxDRQBN/GP01BN
TxDRQAN/GP02AN
TxDRQBN/GP02BN
TRxCA/B
RTxCA/B
RTSBN/SYNOUTBN
RTSAN/SYNOUTAN
elSA/BN
INTERFACE
I
I
I--
R1W
DECODE
DMA
CONTROL
ceRA/S
t--->
:=
:=
RTxDAKAN/GPI1AN ---I
RTxDAKBNfGPll BN ---I
TxDAKANIGPI2AN
lxOAKBN/GPI2BN = :
DTCN
DONEN
MPU
ADDRESS
DECODE
peRA/B
RSRAIB
I
J
~
r--
CTHAIB
CTLAfB
..'"
=>
....
CMR1AIB
r------
OMRAIB
a:
w
li!:
I
TRANS elK
MUX
I
TPAA/B
TIRAfB
~
~
:=:
:=
TRANSt.lTAIB
z
GSR
CMR2A/B
:=:
CTPRHA/B
CTPRLAIB
l/L-~
I"r-f'/'
ICTSRA/B
I--
CIT ClK
MUX AlB
CTCRAfB
I
TRSRAIB
DMA INTERFACE
I
COUNTER!
TIMER AlB
Vt--A
I~
BRG
J
SPECIAL
FUNCTION
PINS
I--
TX SHIFT
REG
r---
TxD AlB
I--
RxDA/B
TRANSMIT
40Eep
AFO
CRC
GEN
CONTROL
SPEC CHAR
GENlOGIC
DCDBNtSYNIBNI = :
DCDAN/SVNIAN1---1
RECEIVER AlB
INTERRRUPT
CONTROL
IRON
IACKN
----->
ICRAIB
IERA/S
IVR
I
---
r
~
Vt--A
"
~
DUSCC
LOGIC
Xl/eLK
November 8, 1990
~
OSCILLATOR
I
RPRAfB
IVRM
X2~DCN
RCVR ClK
MUX
~
~
L--
RTRAIB
SlRA/B
S2RA/B
RCVR
SHIFT REG
RECEIVER
4 DEEP
AFO
CRC
ACCUM
BISYNC
COMPARE
lOGIC
285
Philips Components~ignetics Data Communication Products
Preliminary Specification
Dual universal serial communications controller
(DUSCC)
BLOCK DIAGRAM
SC26C562/SC68C562
SC26C562
CHANNEL
MODE AND
TIMNG AlB
~
DPLLCLK
MUXA/B
~ ~----~~
~D7
v
~~F~R I~'.~·'------------------------------v
_____________________---' v
DPLLA/B
I~
BRG
INTERFACEI
OPERATION
CONTROL
ADDRESS
DECODE
RDYN
Rm
DECODE
*--------1
I
WRN - - - - - - . .
RDN - - - - - - . .
A1-AS
--------i
MPU
INTERFACE
I+---
CEN ----~
DMA
CONTROL
I
I
r-..
COUNTER
TIMER AlB
v
CIT CLK
MUXA/B
I+---
CTCRA/B
>-----
CTPRHAIB
CTPRLA/B
I
CTHAIB
CllA/B
CCRA/B
PCRAIB
RESETN -------..
TRANSMIT
AlB
RSRA/B
'"
'"-"~
TRSRA/B
::>
ICTSRA/B
RTxDROANIGP01AN
*--------1
RTxDROBNlGP01BN
*--------1
GSR
CMRIA/B
CMR2A/B
T.DROAN/GP02AN + - - - - j
TxDRQBN/GP02BN
TRANSCLK
MUX
a:
TPRA/B
w
r---~
TTRA/B
TX SHIFT
REG
OMRAIB
+-------1
RT.DAKAN/GPIIAN -------..
"
RTxDAKBN/GPllBN ------~
v
r-----
TxD AlB
~==~
!C--RCVR
R.D AlB
TRANSMIT
4 DEEP
FIFO
TxDAKANIGPI2AN -------..
TxDAKBNIGPl2BN ------"*I
EOPN +------j
CRC
GENERATOR
SPEC CHAR
GEN LOGIC
TllxCA/B
RTxCAIB
CTSAN/LCAN
CTSBNlLCBN - - - - - .
DCDBN/SYNIBN
SPECIAL
FUNCTION
PINS
~
RECEIVER
AlB
RCVRCLK
MUX
DCDANiSYNIAN
RTSBNiSYNOUTBN
RTSAN/SYNOUTAN
RPRA/B
RTRAIB
SlRA/B
INTERRUPT
CONTROL
IRON
IACKN
ICRAIB
A
IERA/B
rv
IVR
IVRM
S2RA/B
iC---------------~
v
DUSCC
LOGIC
XM:~~==l
November 8, 1990
OSCILlATOR
SHIFT REG
RECEIVER
4 DEEP
FIFO
CRC
ACCUM
~
BISYNC
COMPARE
LOGIC
286
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller
SC26C562/SC68C562
(DUSCC)
PIN CONFIGURATIONS -
SC66C562
N PACKAGE
INDEX
CORNER
A PACKAGE
IACKN
A4
AS
A6
5
RTxDAKANI
GPI1AN
IRON
6
XlICLK
RESETN
7
X2J1DCN
RTSBNI
8
RTSANI
SVNOUTAN
RTxDAKBNI
GPllBN
SVNOUTBN
Pin Function
TRxCA
RTxCB
RTxCA
OCDBNI
DCDAN/
SVNlAN
SVNIBN
IACKN
A3
A2
Al
RTxDAKBNI
GPI1BN
IRON
NC
RESETN
Rxde
RxDa
TxDA
lxDO
TxDAKANI
TxDAKBNI
RTSBNI
GPI2AN
RTxDROANI
GPOIAN
TxDROAN/
GP02ANlRTSAN
GPl2BN
RTxDRQBNI
GPOIBN
TxDRQBN/
GP02BN/RTSBN
CTSBN/LCBN
SYNOUTBN
10 TRxCa
11 RTxCS
12 DCDBN/
SYNIBN
13 NC
14 RxDB
15 TxDB
16 TxDAKBNI
GPI2BN
17 RTxDRQBNI
GP01BN
18 TxDRQBNI
GP02BN/RTSBN
19 CTSBN/LCBN
20 D7
21 D6
22 D5
23 D4
24 DTACKN
25 DTCN
26 GND
CTSANILCAN
07
DO
06
01
05
02
04
03
DTACKN
DONEN
DTCN
RiWN
GND
CSN
TOP VIEW
November 8,1990
287
Pin Function
27 CSN
28 RNiN
29 DONEN
30 D3
31 D2
32 D1
33 DO
34 NC
35 CTSAN/LCAN
36 TxDROANI
GP02AN/RTSAN
37 RTxDROAN/
GP01AN
38 TxDAKANI
GPI2AN
39
40
41
42
43
44
45
TxDA
RxDA
NC
DCDANi
SYNIAN
RTxCA
TRxCA
RTSANi
SVNOUTAN
X2IIDCN
X1JCLK
46
47
48 RTxDAKANI
GPI1AN
49 AS
50 AS
51 A4
52 VDD
Preliminary Specification
Philips Components--Signetics Data Communication Products
Dual universal serial communications controller
SC26C562/SC68C562
(DUSCC)
PIN CONFIGURATIONS - SC26C562
N PACKAGE
IACKN
A PACKAGE
INDEX
CORNER
•
A4
A.
A.
4
A6
RTxDAKBNI
Gpt.BN
5
RTxDAKANI
GPI.AN
IRON
6
XlICLK
RDYN
7
X2
RTSBNI
SYNOUTBN
8
RTSANI
SYNOUTAN
PIN FUNCTION
mxCA
RTxCA
DCDAN/
SYNIAN
RxDA
TxDA
6
7
TxDAKANI
8
•
GPI2AN
RTxDROAN/
GP01AN
TxDROAN/
GP02ANlRTSAN
.0 TRxCB
11 AlxCB
.2 DCDBNI
SYNIBN
.3 NC
.4 RxDB
CTSANILCAN
••••
DO
lxDB
TxDAKBNI
PIN FUNCTION
.7 CEN
28 WRN
2. EOPN
30 D3
3. D2
32 D'
33 DO
34 NC
35 CTSANILCAN
36 TxORQANI
GP02ANIRTSAN
37 RTxDRQAN/
GPO.AN
38 TxDAKANI
GPl2AN
3. TxDA
40 RxDA
4. NC
42 DCDANI
SYNIAN
17 RTxDRQBNI
43 RTxCA
GPO.BN
44 TRxCA
.8 TxDROBN/
4. RTSAN/
GP02BNIRTSBN
SVNOUTAN
CTSBN/LCBN
46 X2
20 07
47 X.ICLK
2. 06
48 RTxDAKANI
2. 05
GPI1AN
23 D4
4. A6
24 RON
50 AS
25 RESETN
5. A4
GND
52 VCC
D.
O.
03
••
EOPN
WRN
CEN
••
November 8, 1990
IACKN
A3
A2
A.
RTxDAKBNI
GPI.BN
IRON
NC
RDVN
RTSBNI
SYNOUTBN
288
GPl2BN
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller
(DUSCC)
SC26C562/SC68C562
PIN DESCRIPTION
In this document, signals are discussed using the terms 'active' and 'inactive' or 'asserted' and 'negated' independent of whether the signal is active
in the High (logic 1) or low (logic 0) state. N at the end of a pin name signifies the signal associated with the pin is Active-low (see individual pin
description for the definition of the active level of each signaL) Pins which are provided for both channels are designated by AlB after the name of
the pin and the Active-low state indicalor, N, if applicable. A similar method is used for registers provided for both channels; these are designated
by either an underline or by AlB after the name.
MNEMONIC
APPLIES TO
TYPE
NAME AND FUNCTION
26C562 68C562
AI-AS
X
X
I
Address Unes: Active-high. Address inputs which specify which of the internal registers is
accessed for readiwrite operation.
DO-D7
X
X
I/O
Bidirectional Data Bus: Active-high, 3-State. Bit 0 is the lSB and bit 7 is the MSB. All data,
command and status transfers between the CPU and the DUSCC take place over this bus.
The data bus is enabled when CSN (CEN) is low and during interrupt acknowledge cycles and
single address DMA acknowledge cycles.
RlWN
X
I
ReadlWrite: A high input indicates a read cycle and a low input indicates a write cycle when
a cycle is initiated by assertion of the CSN input.
CSN
X
I
Chip Select: Active-low input. When low, data transfers between the CPU and the DUSCC
are enabled on DO--D7 as controlled by the RIWN and A I-AS inputs. When CSN is high, the
DUSCC is isolated from the data bus (except during interrupt acknowledge cycles and single
address DMA transfers) and DO-D7 are placed in the 3-State condition.
DTACKN
X
0
Data Transfer Acknowledge: Active-low, 3-State. DTACKN is asserted on a write cycle to
indicate that the data on the bus has been latched, and on a read cycle or interrupt acknowledge cycle to indicate valid data is on the bus. In a write bus cycle, input data is latched by
the assertion (falling edge) of DTACKN or by the negation (rising edge) of CSN, whicheveroccurs first. The signal is negated when completion of the cycle is indicated by negation of CSN
or IACKN input, and returns to the inactive state (3-State) a short period after it is negated.
In a single address DMA mode, input data is latched by the assertion (falling edge) of DTCN
or by the negation (rising edge) of the DMA acknowledge input, whichever occurs first. DTACK
is negated when completion of the cycle is indicated by the assertion of DTCN or negation of
DMA acknowledge inputs (whichever occurs first), and returns to the inactive state (3-State)
a short period after it is negated. When inactive, DTACKN requires an external pull-up resistor.
RDN
X
I
Read Strobe: Active-low input. When active and CEN is also active, causes the content of
the addressed register to be present on the data bus. RDN is ignored unless CEN is active.
WRN
X
I
Write Strobe: Active-low input. When active and CEN is also active, the content of the data
bus is loaded into the addressed register. The transfer occurs on the rising edge of WRN. WRN
is ignored unless CEN is active.
CEN
X
I
Chip Enable: Active-low input. When active, data transfers between the CPU and the DUSCC
are enabled on D7-DO as controlled by RDN or WRN, and AS-A 1. When CEN is high, the
data lines are placed in the 3-State condition (except if IACKN is asserted or during a ddMA
acknowledge cycle).
RDYN
X
0
Ready: Active-low, open drain. Used to synchronize data transfers between the master and
the DUSCC. It is valid only during read and write cycles where the DUSCC is configured in
'wait on Rx', 'wait on Tx' or 'wait on Tx or Rx' modes, otherwise it is always inactive. RDYN
becomes active 0 n the leading edge of RDN and WRN if the requested operation cannot be
performed (viz, no data in RxFIFO in the case of a read or no room in the TxFIFO in the case
of a write).
IRON
X
X
0
Interrupt Request: Active-low, open-drain. This output is asserted upon occurrence of any
enabled interrupting condition. The CPU can read the general status registerto determine the
interrupting condition(s), or can respond with an interrupt acknowledge cycle to cause the
DUSCC to output an interrupt vector on the data bus.
X
I
Interrupt Acknowledge: Active-low. When IACKN is asserted, the DUSCC responds by
placing the contents of the interrupt vector register (modified or unmodified by status) on the
data bus and asserting DTACKN. If no active interrupt is pending, DTACKN is not asserted.
I
Interrupt Acknowledge: Active-low. When IACKN is asserted, the DUSCC responds by eitherforcing the bus into high-impedance, placing a vector number, call instruction or zero on
the data bus. The vector number can be modified or unmodified by the status. If no interrupt
is pending, IACKN is ignored and the data bus placed in high-impedance.
I
Crystal or External Clock: When using the crystal oscillator, the crystal is connected between pins XI and X2. If a crystal is not used, an external clock is supplied at this input. This
clock is used to drive the internal bit rate generator, as an optional input to the counter/timer
or DPll, and to provide other required clocking signals. When a crystal is used, a capacitor
must be connected from this pin to ground.
IACKN
IACKN
X
Xl/ClK
X
November 8,1990
X
289
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller
(DUSCC)
SC26C562/SC68C562
PIN DESCRIPTION (Continued)
MNEMONIC
APPLIES TO
26C562
X2IIDCN
TYPE
NAME AND FUNCTION
I/O
Crystal or Interrupt Daisy Chain: When a crystal is used as the timing source, the crystal
is connected between pins X 1 and X2. This pin can be programmed to provide an interrupt
daisy chain active-low output which propagates the IACKN signal to lower priority devices, if
no active interrupt is pending. This pin should be grounded when an external clock is used
on Xl and X2 is not used as an interrupt daisy chain output. When a crystal is used, a capacitor
must be connected from this pin to ground.
I
Crystal 2: Connection for other side of crystal. When a crystal is used, a capacitor must be
connected from this pin to ground. If an external clock is used on Xl, this pin must be grounded.
68C562
X
X2
X
RESETN
X
X
I
Master Reset: Active-low. A low on this pin resets the transmitters and receivers and resets
the registers shown in Table 1. Reset is asynchronous, i.e., no clock is required.
RxDA,RxDB
X
X
I
Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If external receiver clock is specified for the channel, the input is sampled on the rising edge of the
clock.
TxDA, TxDB
X
X
0
Channel A (B) Transmitter Serial Data Output: The least signifiicant bit is transmitted first.
This output is in the marking condition when the transmitter is disabled or when the channel
is operating in localloopback mode. If external transmitter clock is specified for the channel,
the data is shifted on the falling edge of the clock.
RTxCA, RTxCB
X
X
I/O
Channel A (B) RecelverlTransmflter Clock: As an input, it can be programmed to supply
the receiver, transmitter, counterltimer, or DPLL clock. As an output, can supply the counter/
timer output, the transmitter shift clock (1 X), or the receiver sampling clock (1 X).
TRxCA, TRxCB
X
X
I/O
Channel A (B) Transmitter/Receiver Clock: As an input, itcan supply the receiver, transmitter, counterltimer, or DPLLciock. As an output, itcan supply the counter/timer output, the DPLL
output, the transmitter shift clock (1 X), the receiver sampling clock (1 X), the transmitter BRG
clock (16X), The receiver BRG clock (16X), or the internal system clock (Xl/2).
CTSAlBN,
LCAIBN
X
X
I/O
Channel A (B) Clear-to-Send Input or Loop Control Output: Active-low. The signal can
be programmed to act as an enable for the transmitter when not in loop mode. The DUSCC
detects logic level transitions on this input and can be programmed to generate an interrupt
when a transition occurs. When operating in the BOP loop mode, this pin becomes a loop control output which is asserted and negated by DUSCC commands. This output provides the
means of controlling external loop interface hardware to go on-line and off-line without disturbing operation of the loop.
DCDAlBN,
SYNIAIBN
X
X
I
Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is
programmable. As a DCD active-low input, it acts as an enable for the receiver or can be used
as a general purpose input. For the DCD function, the DUSCC detects logic level transitions
on this pin and can be programmed to generate an interrupt when a transition occurs. As an
active-low external sync input, it is used in COP mode to obtain character synchronization for
the receiver without receipt of a SYN character. This mode can be used in disc or tape can troller
applications.
RTxDROAlBN,
GP01AiBN
X
X
0
Channel A (B) RecelverlTransmitter DMA Service Request or General Purpose Output:
Active-low. For half-duplex DMA operation, this output indicates to the DMA controller that one
or more characters are available in the receiver FIFO (when the receiver is enabled) or that
the transmit FIFO is not full (when the transmitter is enabled). For full-duplex DMA operation,
this output indicates to the DMA controller that data is available in the receiver FIFO. In
non-DMA mode, this pin is a general purpose output that can be asserted and negated under
program control.
TxDROAlBN,
GP02A1BN,
RTSA/BN
X
X
0
Channel A (B) Transmitter DMA Service Request, General Purpose Output, or Request-to-Send: Active-low. For full-duplex DMA operation, this output indicates to the DMA
controller that the transmit FIFO is not full and can accept more data. When not in full-duplex
DMA mode, this pin can be programmed as a general purpose or a Request-to-Send output,
which can be asserted and negated under program control (see Detailed Operation).
RTxDAKAlBN,
GPllAiBN
X
X
I
Channel A (B) RecelverlTransmflter DMA Acknowledge or General Purpose Input: Active-Iow. For half-duplex single address operation, this input indicates to the DUSCC that the
DMA controller has acquired the bus and that the requested bus cycle (read receiver FIFO
when the receiver is enabled orload transmitter FI FO when the transmitter is enabled) is beginning. For full-duplex single address DMA operation, this input indicates to the DUSCC that
the DMA controller has acquired the bus and that the requested read receiver FIFO bus cycle
is beginning. Because the state of this input can be read under program control, it can be used
as a general purpose input when not in single address DMA mode.
NovemberS, 1990
290
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller
(DUSCC)
SC26C562/SC68C562
PIN DESCRIPTION (Continued)
TYPE
NAME AND FUNCTION
X
I
Channel A (B) Transmitter DMA Acknowledge or General Purpose Input: Active-low.
When the channel is programmed for full-duplex single address DMA operation, this input is
asserted to indicate to the DUSCC that the DMA controller has acquired the bus and that the
requested load transmitter FIFO bus cycle is beginning. Because the state of this input can
be read under program control, it can be used as a general purpose input when not in full-duplex single address DMA mode.
DTCN
X
I
Device Transfer Complete: Active-low. DTCN is asser1ed by the DMA controller to indicate
that the requested data transfer is complete.
DONEN
X
I/O
Done: Active-low, open-drain. DONEN can be used and is active in both DMA and non-DMA
modes. See Detailed Operation for a description of the function of this pin.
I/O
Done (EOP): Active-low, open-drain. EOPN can be used and is active in both DMA and nonDMA modes. See Detailed Operation for a description of the lunction of this pin.
Channel A (8) Sync Detect or Request-to-Send: Active-low. II programmed as a sync output, it is asserted one bit time after the specified sync character (COP or BISYNC modes) or
a FLAG (BOP modes) is detected by the receiver. As a Request-to-Send modem control signal, it functions as described previously for the TxDRQN/RTSN pin.
MNEMONIC
TxDAKAlBN,
GPI2A1BN
APPLIES TO
26C562
68C562
X
EOPN
X
RTSA/BN,
SYNOUTAIBN
X
X
0
VDD
X
X
I
+5V Power Input
GND
X
X
I
Signal and Power Ground Input
November 8,1990
291
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller
SC26C562/SC68C562
(DUSCC)
Table 1.
DUSCC RegIster Address Map
(Present NMOS DUSCC and new CMOS DUSCC)
REGISTER NAME
ADDRESS BITS'
MODE
AFFECTED
BY RESET
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
Yes-OO
ACRONYMS
6
5
4
3
2
1
c
0
0
0
0
0
CMRI
Channel mode register I
c
0
0
0
0
I
CMR2
Channel mode register 2
c
0
0
0
I
0
SIR
SYN I/secondary address I register
c
0
0
0
I
I
S2R
SYN 21secondary address 2 register
c
0
0
0
0
TPR
Transmitter parameter register
0
1
ITR
Transmitter timing register
I
0
RPR
Receiver parameter register
Yes-OO
No
No
Yes -00
c
0
0
1
1
c
0
0
1
c
0
0
I
I
I
RTR
Receiver timing register
c
0
1
0
0
0
CTPRH
Counter/timer preset register high
c
0
1
0
0
I
CTPRL
Counter/timer preset register low
c
0
0
1
0
CTCR
c
0
1
1
0
1
1
OMR
c
0
1
1
0
0
CTH
Counter/timer high
R
No
c
0
1
1
0
1
CTL
Counter/timer low
R
No
c
0
1
0
PCR
I
1
1
CCR
c
I
0
0
0
I
R
No
c
1
1
X
X
TxFIFO
c
X
X
RIW
RIW
W
Yes-OO
0
1
1
1
c
1
0
0
0
RSR
c
1
0
0
1
TRSR
c
0
I
0
ICTSR
d
1
1
1
1
1
0
1
1
c
1
1
1
0
0
c
1
1
1
0
1
..
..
RxFIFO
Counter/timer control register
Output and miscellaneous register
Pin configuration register
Channel command register
Transmitter FIFO
..
..
..
Receiver FI FO
No
Yes -00
No
No
No
Yes -00
Yes -00
No
No
Receiver status register
RlW2
Yes -00
Transmitter and receiver status register
RlW2
Yes -00
Input and counter/timer status register
RlW2
Yes
GSR
General status register
RlW2
Yes -00
IER
Interrupt enable register
RIW
Yes -00
RIW
Yes-OF
R
Yes - FF
RIW
RIW
Yes -00
Not used
0
1
1
1
1
0
IVR
1
1
0
IVRM
1
1
1
1
0
1
1
1
1
ICR
1
1
1
1
1
13
MRR
Interrupt vector register - unmodified
..
Interrupt vector register - modified
Interrupt control register
Yes3
NOTES:
1. c =0 for channel A, c = 1 for channel B.
d = don't care - register may be accessed as either channel.
x = don't care - FI FOs are addressable at any of four adjacent addresses to allow them to be addressed as byte/word/long word.
2. A write to this register can perform a status resetting operation.
3. SC26C562 only. See Master Reset Register section for description of operation. Not used for SC6SC562.
4. n/a = Not applicable
5 .•• These registers are EDGE TRIGGERED. Others are read only or level triggered. Level triggered registers should not be changed while
channel is active. NOTE: ICTSR for bits 6, 5, 4 only.
REGISTERS
The addressable registers of the DUSCC are
shown in Table 1. The following rules apply to
all registers:
1. A read from a reserved location in the
map results in a read from the 'null register'. The null register returns all ones for
data and results in a normal bus cycle. A
write to one of these locations results in a
normal bus cycle without a write being
performed.
NovemberS, 1990
Master reset register
2. Unused bits of a defined register are read
as zeros, unless ones have been loaded
after master reset.
3. Bits that are unused in the chosen mode
but are used in others are readable and
writable but their contents are ignored in
the chosen mode.
4. All registers are addressable as B-bit
quantities. Addresses are ordered such
292
that certain sets of registers may also be
accessed as words or long words.
The operation of the DUSCC is programmmed
by writing control words into the appropriate registers. Operational feedback is provided via
status registers which can be read by the CPU.
The contents of certain control registers are initialized on RESET. Care should be exercised
if the contents of a register are changed during
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller
SC26C562/SC68C562
(DUSCC)
operation, since certain changes may cause
operational problems, e.g., changing the channel mode at an inappropriate time may cause
the reception or transmission of an incorrect
character. In general, the contents of registers
which control transmitter or receiver operation,
or the counterltimer, should be changed only
when they are not enabled.
The DUSCC registers can be separated into
five groups to describe their usage:
1. Channel mode configuration and pin description registers.
CMOS DUSCC OBJECTIVE SPEC
The CMOS DUSCC is a single-chip communication device that is a fully software compatible
with Signetics' DUSCC chip with 16 deep FIFO,
individual interrupt enable bits. It is implemented using high speed CMOS process and
faster data bus timing.
Key Features
• Fully software and hardware compatible
with NMOS DUSCC
• 8 bit data bus with 160ns bus cycle
• 0 to 1OMbit per second
2. Transmitter and receiver parameter and
timing registers.
• Rx FIFO
- 16 x 8 data FIFO
- RxRDY triggered by programmable filled
level of FIFO
- Watch dog timer
3. Counter/timer control and value registers.
4. Interrupt control and status registers.
5. Command register.
CMOS DUSCC Register Address Map
- Status bits for the filled level of Rx FIFO
- FIFO all of the error status bits
- Provide DMA frame status byte
• Tx FIFO
- 16 x 8 data FIFO
- TxRDY triggered by programmable filled
level of FIFO
- Status bits for the empty level of Tx
FIFO
• Baud Rate Generator-from 50bps up to
64Kbps
• Interrupt control
- Individual interrupt enable bits
- Support interrupt Daisy Chain-RDYN
(DTACKN) is provided
• Support X.21 pattern recognition
• Lower power consumption
(New registers available by setting internal A7 bit.)
ADDRESS BITS
REGISTER NAME
MODE
AFFECTED
BY RESET
ACRONYM
7
6
5
4
3
2
1
1
c
0
0
0
1
0
IERl
Interrupt enable register 1
RlW
Yes - 00
1
c
0
0
0
1
1
IER2
Interrupt enable register 2
RlW
Yes - 00
1
c
0
0
1
0
1
IER3
Interrupt enable register 3
RlW
Yes - 00
1
c
0
0
1
1
1
RCR
Rx command register
RlW
Yes - 00
1
c
0
1
1
1
0
RFLR
RxFIFO tilled level register
1
c
1
1
1
0
0
FTLR
1
c
1
1
1
1
0
1
c
1
1
1
1
1
x
0
1
1
1
0
x
1
1
1
1
x
0
1
1
1
R
Yes - 00
FIFO threshold level register
RlW
Yes - C3
TRMR
Tx/Rx misc register
RlW
Yes -00
TFLR
TxFIFO filled level register
R
Yes -10
1
REA
Reset internal A 7 to 0
W
A7= 0
0
1
SEA
Set internal A7 to 1
W
A7= 0
0
1
CID
Chip identification
R
A7 = 0
Register map - The internal A7 affects the
following registers and all other registers are
not affected by A7.
A7=O
A7 = 1
SlR
S2R
TIR
RTR
PCR
IER
IVRlIVRM
ICRlMRR
IERl
IER2
IER3
RCR
RFLR
FTLR
TRMR
TELR
TTR - Transmitter Timing
Register
[3210]- This field selects an output from bit rate
generator to be used by the transmitter circuits.
Three extra bit rate are provided if new bit rates
is chosen by RCR.
NovemberS, 1990
[3210]- Bit Rates
[5] Overrun
0000
[4] Reserved
0001
0010
50/14.4K. If RCR[l] is set, TIR[3:0] =
[0000] chooses 14.4Kbps. If RCR[l]
is reset, then it will switch back to default value, 5Obps.
[3] BRK End
[2] BRK Start
75/56K. If RCR[l] is set, TTR[3:0] =
[0001] chooses 56Kbps. If RCR[l] is
reset, then it will switch back to default
value, 75bps.
[1] Frame Error
110/64K. If RCR[l] is set, TIR[3:0] =
[0010] chooses 64Kbps. If RCR[l] is
reset, then it will switch back to default
value, 11 Obps.
[7] EOM Detect
IERl -Interrupt Enable Register 1.
This registeris active only when individual interrupt enable mode is selected.
[0] Parity Error
In COP mode:
[6] PAD error
[5] Overrun
[4] Reserved
[3] Reserved
[2] SYN detect
In ASYNC mode:
[7] Character Comparison
[1] CRC/LRC Error
[0] Parity Error
[6] RTS Negated
293
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller
SC26C562/SC68C562
(DUSCC)
In BOP/BOP LOOP modes:
[7] EOM Detect
[6] ABORT/EOP detect
[5] Overrun
[6] TxRDY Interrupt Enable Bit.
This bit is ignored while original IER is being
used.
o
Interrupt not enabled
Interrupt generated if TxRDY is asserted.
[4] Short frame
[3] IdlelTurnaround Detect
[5] RxRDY fnterrupt Enable Bit.
[2] Flag detect
This bit is ignored while original IER is being
used.
[1] CRC Error
[0] RCL not zero
IER2 - Interrupt Enable Register 2.
This register is active only when individual
interrupt enable mode is selected.
In ASYNC mode:
[7] Tx path empty
[6] Reserved
[5] Tx Underrun
[4] CTS Underrun
[3] Send BRK ACK
[2] DPLL error
[1] Delta CTS detect
[0] Delta DCD detect
In COP mode:
o
Interrupt generated if no data is loaded into
RxFIFO within 128 consecutive bit times after
command is issued.
[1] Delta CTS detectlLC detect
[0] Delta DCD detect
In BOP and BOP LOOP modes:
[7] Tx path empty
[6] Tx Frame Complete
[5] Tx Underrun
[4] CTS Underrun/Loop Sending
[3] Send SOM ACK
[2] DPLL error
[1] Delta CTS/LC detect
[0] Delta DCD detect
IER3 - Interrupt Enable Register 3.
This register is active only when individual
interrupt enable mode is selected.
[7] Channel Master Interrupt Enable Bit.
This bit is used as ICR[I] or ICR[O] while
A7 = 1. This bit is ignored when A7.= O.
November 8, 1990
This bit is set when the last bit of the data is
being shifted out of TxD while no more characler in the FIFO or in the whole transmitter data
path. A '1' written to this bit can clearthe status
bit. This bit is also cleared if the Tx RESET or
Master RESET is issued.
[3] Pattern 0 Status Bit.
This bit is set when Rx receives 16 contiguous
O's after pattern recognition is enabled. A '1'
written to this bit can clear the status bit. This
bit is also cleared if the Rx RESET or Master
RESET is iSSUed.
[2] Pattern 1 Status Bit.
This bit is set when Rx receives 16 contiguous
1's after pattern recognition is enabled. A '1'
written to this bit can clear the status bit. This
bit is also cleared if the Rx RESET or Master
RESET is issued.
[1] Pattern Alternating 01 Status Bit.
This bit is set when Rx receives 16 contiguous
alternating 01 or 10 after pattern recognition is
enabled. A 'l'written to this bit can c.lear the status bit. This bit is also cleared if the Rx RESET
or Master RESET is issued.
[0] WTD Status Bit.
This bit is set whenever the WTD is time out.
294
Disable DMA status byte. See detail
in DFSB.
Disable Pattern Recognition all O's.
Enable Pattern Recognition all O·s.
This command will have the receiver
start to hunt 16 consecutive O's.
Disable Pattern Recognition all 1'so
Enable Pattern Recognition all l's.
This command will have the receiver
start to hunt 16 consecutive l's. The
status bit is shown in TRMR.
[0] Reserved
[7:5] Reserved
[2] DPLL error
[5] - 0
[4]- 0
TRMR - Transmitter/Receiver Misc. Register. This register provides pattern recognition
status bits and Tx path empty status bit.
Disable Watch Dog TImer.
Enable DMA status byte. The status
byte for the whole frame is fifoed
following last byte of frame while DMA
is in progress.
[1] Reserved
[4] Tx Path Empty Status Bit.
[3] Send SOM ACK
[6]- 0
[3] Pattern Recognition Interrupt Enable BIt.
Interrupt generated if any of the pattern recognitions is set.
[2] Reserved
Rx Command Register.
Enable Watch Dog TImer. WTD status
is set if no data is loaded into RxFIFO
within 128 consecutive bit limes after
command is issued.
[4] Watch Dog Timer Interrupt Enable Bit.
[6] Tx Frame complete
[4] CTS underrun
RCR -
[7] - 0
Interrupt not enabled
Interrupt generated if RxRDY is asserted.
[7] Tx path empty
[5] Tx Underrun
This bitis ORed together with RxRDY status bit
in the GSA. A '1' written to this bit can clear the
status bit. This bit is also cleared if the Rx
RESET or Master RESET is issued.
[3]- 0
Disable Pattern Recognition alternating 01.
Enable Pattern Recognition alternating 01. This command will have the receiver start to hunt 16 contiguous
alternating 01 or 10. The status bit is
shown in TRMR.
[2]- 0
Default mode. No individual interrupt
enable mode.
Enable individual interrupt enable
mode. In this mode, IERI and IER2
are used and originallER is ignored.
[1]-0
Defaultmode. Nonew bit rates can be
selected.
Three additional new bit rates, 14.4k,
56k, and 64k can be chosen through
TIR[3:0]. See TIR[3:0] for further
information.
[0]
Reserved
TELR - TxFIFO Empty Level Register.
This register indicates the TxFIFO empty level.
A read from this register can tell the current
available space(s} for the TxFIFO.
[7:5] Reserved
[4:0] This field selects the available location(s)
for the TxFIFO.
00000 - 0
00001 - 1
bytes empty
(implies TxFIFO full)
byte empty
Philips Components-Signetics Data Communication Products
Preliminary Specification
Dual universal serial communications controller
(DUSCC)
00010- 2
00011 - 3
00100- 4
bytes empty
bytes empty
bytes empty
00101- 5 bytes empty
00110 - 6 bytes empty
00111 - 7 bytes empty
01000- 8 bytes empty
01001- 9 bytes empty
01010- 10 bytes empty
01011- 11 bytes empty
01100 - 12 bytes empty
01101 - 13 bytes empty
01110 - 14 bytes empty
01111 - 15 bytes empty
10000- 16 bytes empty
(implies TxFI FO empty)
RFlR - RxFIFO Filled level Register.
This register indicates the RxFIFO filled level.
Nine status bits are fifoed with each byte
received. A read from this register can tell the
current FIFO filled level.
[7:5] Reserved
[4:0] This field selects the RxFIFO filled level.
00000 - 0
00001 - 1
00010 - 2
00011 - 3
byte filled
(implies RxFI FO empty)
bytes filled
bytes filled
bytes filled
00100- 4
00101 - 5
bytes filled
bytes filled
0011 0 - 6
00111 - 7
bytes filled
bytes filled
01000 - 8
01001 - 9
bytes filled
bytes filled
0101001011 0110001101 01110 -
bytes filled
bytes filled
bytes filled
bytes filled
bytes filled
10
11
12
13
14
01111 - 15 bytes filled
10000 - 16 bytes filled (implies RxFIFO full)
FTlR - FIFO Threshold level Register.
This register indicates both TxFIFO and
RxFIFO interrupt threshold level.
[7:5] This field selects Ihe TxFIFO Threshold level. To use threshold level to generate
interrupt request, TxRDY activate bit on OMR
could be set to 'I' (FIFO empty). The default
threshold level is 4 byte locations available.
TxRDY does not clear until the TxFIFO is full or
transmitter is disabled.
November 8, 1990
0000 - 1
0001
0010
0011
0100
0101
-
2
3
4
5
6
0110 - 7
0111 - 8
SC26C562/SC68C562
byte empty
(only one space available)
ters can be accessed. Data is ignored during
the write cycle.
bytes empty
bytes empty
bytes empty (default mode)
CID - Chip Identification.
A read operation provides software signature
which can tell the part version.
bytes empty
bytes empty
bytes empty
bytes empty
1000 - 9 bytes empty
1001 - 10 bytes empty
1010 - 11 bytes empty
1011 - 12 bytes empty
1100 - 13 bytes empty
1101 - 14 bytes empty
1110-15 bytes empty
1111 - 16 bytes empty (TxFIFO empty)
[4:0] This field selects Ihe RxFIFO threshold
level. To generate RxRDY interrupt or DMA
request, the RxFIFO filled level must be equal
or greater than the threshold level.
To use the threshold level to generate interrupt
request, RxRDY activate bit on OMR could be
setto 'I' (FIFO full). The default threshold level
is 4 characters. RxROY is set when more than
one byte is in the FIFO. It resets when the
receiver FI FO is ready or the receiver is
disabled.
DATA OUTPUT
PART VERSION
FFH
NMOS DUSCC
EFH
CMOS OUSCC Rev. A
DFSB - DMA Frame Status Byte.
In RxDMA cycle, this status byte can be attached to the FI FO following last byte of frame
(last byte means data with EOM status bit set).
This byte is updated frame by frame by logical
'OR-ing' of prior status bytes with the present
status byte of the frame and only used for COP
or BOP/BOPl modes while OMA transfers are
in progress. The DONEN (EOPN)wili not be set
until this byte pops to the top of the FIFO.
To enable this mode user has to send the command through CCR. ("ABORT does NOT reset DFSB but RxReset does")
COP mode
[7] Reserved
[6] Reserved
[5] Reserved
[4] PAD ERROR
0000 - 1
0001 - 2
0010 - 3
byte filled
bytes filled
bytes filled
0011 - 4
0100 - 5
0101 - 6
bytes filled (default mode)
bytes filled
bytes filled
[I] BCC ERROR
0110 - 7
bytes filled
BOP/BOPl mode
0111 - 8
1000 - 9
bytes filled
bytes filled
[7:5] Residual character length. Same as
TRSR[2:0]
1001 1010 1011 11 00 -
bytes filled
bytes filled
bytes filled
bytes-filled
[4] ABORT
10
11
12
13
11 01 - 14 bytes filled
1110 - 15 bytes filled
1111 - 16 bytes filled (Rx FIFO full)
REA - Resellnlernal A 710 O.
A write to this address set the address bit to 6
bits. This is the default mode. No new registers
can be accessed. Data is ignored during the
write cycle.
SEA - Set Internal A 7 to 1.
A write to this register automatically extend
address bit to 7 bits. Therefore all the new regis-
295
[3] DPLL error
[2] Overrun
[0] Parity error
[3] DP LL error
[2] Overrun
[1]CRCerror
[0] Short Frame
CCR - Channel Command Register.
76543210
01xxOl00
01xxOl0l
Default mode. Disable
new fifeed status bits.
Enable new fifoed status bits. In
this mode all of the following
status bits in RSRlTRSR reflect
the status of the current character
at the top of the RxFIFO.
Preliminary Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller
SC26C562/SC68C562
(DUSCC)
ASYNC:
#
#
#
COP
#
#
#
BOP/BOPL:
#
#
#
#
:
Since abort detect and short frame may not
have data byte to attach, a dummy byte is provided for status attachment. This dummy byte
includes the current data in the shift register.
Therefore, whenever the abort or short frame
occurs, the status bit is always attached to this
dummy byte.
"NOTE" In BOP/BOPL mode, TRSR[2:0J is
always fifoed no matter what kind of command
is issued.
GSR - General Status Register.
This register remain almost same as NMOS
DUSCC's GSR except RxRDY and RxlTx status bits. For RxRDY status bit, it combines Rx
WDT status bit with original Rx Ready together
RSR[7J
RSR[SJ
RSR[2J
RSR[IJ
RSR[OJ
Character Compare
Overrun
BRKStart
FE
PE
RSR[7J
RSR[6J
RSR[SJ
RSR[IJ
RSR[OJ
EOM
Pad Error
Overrun
RSR[7J
RSR[6J
RSR[SJ
RSR[4J
RSR[IJ
RSR[OJ
EOM
ABORT/EOP
Overrun
Short frame
CRC CRC error
RCL not zero
LRC/CRC error
PE
Fifoed status bits in NMOS DUSCC.
if Rx WDT is enabled. For the Tx/Rx status bit,
it combines original Receiver/transmitter status
bits with pattern recognition status bits and Tx
path empty bit together if those functions are individuallyenabled.
[7] CH.B External or CIT status.
[6J CH.B RxlTx status. This bit is set whenever
one of the following status bits is set. RSR[7:0J,
TRSR[7:3J, Tx path empty, Pattern recognitions. The Tx path empty and Pattern recognitions can affect GSR[6J only if those functions
are enabled individually.
[4J CH.B RxRDY. This bit is set either when
Receiver Ready is active or when WDT status
bit is set if the WDT is enabled.
[3J CH.A External or CIT status.
[2J CH.A RxlTx status. This bit is set whenever
one of the following status bits is set. RSR[7:0J,
TRSR[7:3J, Tx path empty, Pattern recognitions. The Tx path empty and Pattern recognitions can affect GSR[6J only if those functions
are enabled individually.
[IJ CH. A TxRDY.
[OJ CH.A RxRDY. This bit is set either when
Receiver Ready is active or when WDT status
bit is set if the WDT is enabled.
[SJ CH.B TxRDY.
BISYNC control:
CMR1 [5]
CMR [4:3]
0
00
EBCDIC, NO parity, 8 bit data, 8 bit CTRL character.
1
00
ASCII, NO parity, 8 bit data, 8 bit CTRL character. Odd parity bit is generated by users. It's same
as NMOS DUSCC. Receiver check the parity bit by loop-up table. If an LRC BCC is selected in
CMR[2:0] then LRC-8 is used (the MSB of the LRC is the logical XOR of all MSBs in the frame.)
1
01
ASCII, No parity, 8 bit data, 8 bitCTRLcharacter. The receiver only check 7 bits forthe CTRLcharacter and ignore the MSB of each character. If an LRC BCC is selected in CMR[2:0J then LRC-7
is used (the MSB of the LRC is 0).
1
10
ASCII, ODD parity, 7 bit data + 1 odd parity bit, 7 bit CTRL char+ 1 odd parity bit. Parity bit is generated/checked by DUSCC. Any CTRL character as parity error will not be treated as a CTRL character.
If an LRC BCC is selected in CMR[2:0J then LRC-7 is used. The MSB of the LRC will be the ODD
PARITY value computed from the 7 other bits that comprise the LRC.
1
11
ASCII, EVEN parity. Similar to CMR[4:3J = 10 except parity bit is even.
November 8, 1990
296
Philips Components-Signetics
Document No.
B53-{)B31
ECN No.
95721
Date of Issue
October 30, 1990
Status
Product Specification
SCN68562
Dual universal serial
communications controller (DUSCC)
Data Communication Products
DESCRIPTION
The Signetics SCN68562 Dual Universal
Serial Communications Controller
(DUSCC) is a single-chip MaS-LSI
communications device that provides
two independent, multi-protocol,
full-duplex receiverltransmitter channels
in a single package. It supports
bit-oriented and character-oriented (byte
count and byte control) synchronous
data link controls as well as
asynchronous protocols. The
SCN68562 interfaces to the 68000
MPUs via asynchronous bus control
signals and is capable of
program-polled, interrupt driven,
block-move or DMA data transfers.
The operating mode and data format of
each channel can be programmed
independently. Each channel consists of
a receiver, a transmitter, a 16-bit
multifunction counterltimer, a digital
phase-locked loop (DPll), a parity/CRC
generator and checker, and associated
control circuits. The two channels share
a common bit rate generator (BRG),
operating directly from a crystal or an
external clock, which provides 16
common bit rates simultaneously. The
operating rate for the receiver and
transmitter of each channel can be
independently selected from the BRG,
the DPLL, the counterltimer, or from an
external IX or 16X clock, making the
DUSCC well suited for dual-speed
channel applications. Data rates up to
4Mbits per second are supported.
The transmitter and receiver each
contain a four-deep FIFO with appended
transmitter command and receiver
status bits and a shift register. This
permits reading and writing of up to four
PIN CONFIGURATIONS
N PACKAGE
INDEX
A PACKAGE
CORNER
A4
AS
A6
RTxOAKBN'
5
GPl1BN
RTxOAKANI
GPI1AN
IRON
6
Xl/eLK
RESETN
7
X2nOCN
RTSBNI
SVNOUTBN
8
RTSANI
SVNOUTAN
TRxCA
RTxCB
RTxCA
ceOON!
SVNlBN
DCDANI
SVNIAN
RxDa
Rxda
TxDB
TxDA
TxOAKANI
GPI2AN
RTxORQAN!
GP01AN
TxDRQAN!
TxOAKBNI
GPl2BN
RTxCRQBN!
GPOIBN
TxoRaSHI
GP02ANlRTSAN
GP02BNfRTSBN
CTSBNlLCBN
CTSANILCAN
07
DO
06
01
05
02
D4
03
DONEN
OTACKN
RlWN
OTCN
CSN
GNO
characters at a time, minimizing the
potential of receiver overrun or
transmitter underrun, and reducing
interrupt or DMA overhead. In addition,
a flow control capability is provided to
disable a remote transmitter when the
FIFO of the local receiving device is full.
297
Pin Functlon
IACKN
A3
A2
Al
RTxDAKBNI
GPllBN
IRON
NC
RESETN
RTSBNI
SYNOUTBN
10 TRxCe
11 RTxCB
12 DCDBNI
SVNIBN
13 NC
14 RxDB
15 TxOB
16 TxDAKBNI
GPI2BN
17 RTxOROBNI
GPOIBN
18 TxDROBNI
GP02BNlRTSBN
19 CTSBNILCBN
20 07
21 D6
22 D5
23 D4
24 DTACKN
25 DTCN
26 GNO
Pin Function
27 CSN
28 R/WN
29 OONEN
30 03
31 02
32 Dl
33 DO
34 NC
35 CTSANILCAN
36 TxDROANI
GP02AN/RTSAN
37
RTxDRQANI
GPOIAN
38 TxDAKANI
GPI2AN
3. TxDA
40 RxDA
41 NC
42 DCDANI
SYNIAN
43 RTxCA
44 TRxCA
45 RTSANI
SVNOUTAN
46 X21IDCN
47 XlICLK
48 RTxDAKANI
GPI1AN
49 AS
50 A5
51 A4
52 VDD
Two modem control inputs (DCD and
CTS) and three modem control outputs
(RTS and two general purpose) are
provided. Because the modem control
inputs and outputs are general purpose
in nature, they can be optionally
programmed for other functions.
Product Specification
Philips Components-Signetics Data Communication Products
SCN68562
Dual universal serial communications controller (DUSCC)
FEATURES
- Count received or transmitted
characters
- Delay generator
- Automatic bit length measurement
General Features
• Dual full-duplex synchronous!
asynchronous receiver and transmitter
• Multiprotocoloperation
- BOP: HDLC/ADCCP, SDLC, SDLC loop,
X.25 or X.75 link level, etc.
- COP: BISYNC, DDCMP
- ASYNC: 5-8 bits plus optional parity
• Modem controls
- RTS, CTS, DCD, and up 10 four general
I/O pins per channel
- CTS and DCD programmable
ruJloenabies for Tx and Rx
- Programmable interrupt on change of
CTS orDCD
• Four character receiver and transmitter
FIFOs
• On-chip oscillator for crystal
• 0 to 4MHz data rate
• TTL compatible
• Programmable bit rale for each receiver
and transmitter selectable from:
- 16 fixed rates: 50 to 38.4k baud
- One user-defined rate derived from
programmable counter/timer
- External 1X or 16X clock
- Digital phase-locked loop
• Single +5V power supply
Asynchronous Mode Features
• SYN or MARK linefill on underrun
• Idle in MARK or SYNs
• Parity, FCS, overrun, and underrun error
detection
BISYNC Features
- EBCDIC or ASCfI header, text and
control messages
- SYN, DLE stripping
- EOM (end of message) detection and
transmission
- Auto transparent mode switching
- Auto hunt after receipt of EOM sequence
(with dosing PAD check after EOT or
NAK)
- Control chamcter sequence detection for
both transparent and normal text
• Character length: 5 to 8 bits
• Odd or even parity, no parity, or force parity
• Up 10 two stop bits programmable in
1/16-bit increments
• Parity and FCS (frame check sequence
LRC or CRC) generation and checking
• 1X or 16X Rx and T x dock faclors
Bit-Oriented Protocol Features
• Character length: 5 to 8 bits
• Detection and transmission of residual
character: 0-7 bits
• Automatic switch
length for 1 field
to programmed character
• Programmable data encoding/decoding:
NRZ, NAZI, FMC, FM1, Manchester
• Parity, overrun, and framing error detection
• Programmable channel mode: full- and
half-duplex, auto-echo, or local loopback
• Start bit searoh 1I2-bitlime after framing
error detection
• Programmable data transfer mode: pC/lied,
interrupt, DMA, wait
• Break generation with handshake for
counting break characters
• Detection and generation of FLAG,
ABORT, and I DLE bit patterns
• DMA interface
- Compatible with the Signetics
SCB68430 Direct Memory Access
Interface (DMAI) and other DMA
controllers
- Single- or dual-address dual transfers
- Half- or full-duplex operation
- Automatic frame termination on
counter/timer terminal count or DMA
DONE
• Detection of start and end of received
break
• Detection and generation of shared (single)
FLAG between frames
• Character compare with optional interrupt
on match
• Detection of overlapping (shared zero)
FLAGs
• Transmits up to 4Mbs and receive up te
2Mbps data rates
• ABORT, ABORT-FLAGs, or FCS FLAGs
/inefill on underrun
• False start bit detection
• Optional opening PAD Iransmission
• Idle in MARK or FLAGs
• Interrupt capabilities
- Daisy chain option
- Vector output (fixed or modified by
status)
- Programmable internal priorities
- Maskable interrupt conditions
• Multi-function programmable 16-bit
counter/timer
- Bit rate generator
- Event counter
Character-Oriented Protocol
Features
• Secondary address recognition indudin§
group and global address
• Character length: 5 10 e bits
• Single- or dual-octet secondary address
• Odd or even partty, no parity, or force parity
• Extended address and control fields
• LRC or CRe generation and checking
• Short frame rejection for receiver
• Optional opening PAD transmission
• One or two SYN characters
• Detection and notification of received end
of message
• External sync capability
• CRC generation and checking
• SYN detection and optional stripping
• SOLC loop mode capabmty
ORDERING INFORMATION
Vcc
=+5V ±5%, TA =O°Clo +70ac
=
Serial Dala Rale =
DESCRIPTION
Serial Dala Rate
2.5Mbps Maximum
4Mpbs Maximum
48-Pin Plastic DIP
SCN68562C2N48
SCN68562C4N4S
52-Pin PLCC
SCN68562C2A52
SCN68562C4A52
October 30, 1990
• Zero insertion and deletion
298
Product Specification
Philips Components-Signetics Data Communication Products
SCN68562
Dual universal serial communications controller (DUSCC)
BLOCK DIAGRAM
r-
9
BUS
BUFFER
~
--
----
--
-
>
----
CHANNEL MODE
AND TIMING AlB
I
I
INTERFACE!
OPERATION
CONTROL
I
DTACKN
RWN
Al·A6
CSN
RESETN
~
=:
MPU
INTERFACE
f.---
---->
ADDRESS
DECODE
I
RIW
DECODE
I
CONTROL
DMA
ceRA/8
RTxDROANIGPOl AN
RTxDRQSN/GP018N
TxDRQAN/GP02AN
TxDRQBN/GP02BN
RTxDAKAN/GPI1AN
RTxDAKBN/GPllBN
TxDAKAN/GPI2AN
:=
--=:
~
f--
DMA INTERFACE
f.---
RTxCA/B
RTSBNtSYNOUTBN
RTSAN/SYNOUTAN
eISA/BN
OCDBN/SVNIBN
DCOAN/SYNIAN
I
I~
=:
-
BRG
I
TIMER AlB
CfT ClK
MUXA/S
CTCRA!8
I
f---
CTPRHAfB
CTPRLA/B
A-~
CTHAIB
'y----v
CTLAt8
al
GSR
'"zwa:
TRANS .... T AlB
~
I
0-
:!;
CMR2A/B
TRANSClK
MUX
I
~
OMRAIB
TPRA/B
-
TTRAf8
~
TX SHIFT
REG
~----v
:=:
:=..
=:
MUX AlB
DPLl AlB
COUNTERI
k;=>
CMR1A/8
TxDAKBN/GPI2BN
DTCN
DONEN +---*
TRxCA/B
peRA/B
RSRA/B
I
OPll eLK
SPECIAL
FUNCTION
PINS
f.---
TRANSMIT
40EEP
RFO
TxD AlB
CRC
GEN
CONTROL
SPEC CHAR
GENlOGIC
RECEIVER AlB
INTERRRUPT
CONTROL
IRON
IACKN
--
-«-
ICRA/B
IERA/S
IVR
/'V
I
-
XlfClK
RTRAIB
-
-----
------- - - - -
-~
v
SlRA/S
~
v--v
--- ----
IVRM
October 30, 1990
~
S2RA/B
RCVR
SHin REG
DUSCC
OSCILLATOR
I
RPRA/8
LOGIC
X2llDCN
RCVR ClK
MUX
~
~
RECEIVER
4 DEEP
RFO
CRC
ACCUM
BISYNC
COMPARE
lOGIC
299
---
RxD AlB
Product Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller (DUSCC)
SCN68562
PIN DESCRIPTION
In this data sheet, signals are discussed using the terms 'active' and 'inactive' or 'asserted' and 'negated' independent of whether the signal is active
in the High (logic 1) or Low (logic 0) state. N at the end of a pin name signifies the signal associated with the pin is active-Low (see individual pin
description for the definition of the active level of each signaL) Pins which are provided for both channels are designated by AlB after the name of
the pin and the active-Low state indicator, N, if applicable. A similar method is used for registers provided for both channels: these are designated
by either an underline or by AlB after the name.
MNEMONIC
DIP
PIN NO.
TYPE
NAME AND FUNCTION
Al-A6
4-2,
45-47
I
Address Lines: Active-High. Address inputs which specify which of the internal registers
is accessed for readlwrite operation.
DO-D7
31-28,
21-18
I/O
Bidirectional Data Bus: Active High, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All
data, command, and status transfers between the CPU and the DUSCC take place over
this bus. The data bus is enabled when CSN is Low, during interrupt acknowledge cycles
and single-address DMA acknowledge cycles.
RlWN
26
I
ReadlWrlle: A High input indicates a read cycle and a Low input indicates a write cycle
when a cycle is initiated by assertion of the CSN input.
CSN
25
I
Chip Select: Active-Low input. When Low, data transfers between the CPU and the
DUSCC are enabled on DO - D7 as controlled by the RlWN and AI - A6 inputs. When
CSN is High, the DUSCC is isolated from the data bus (except during interrupt acknowledge cycles and single-address DMA transfers) and DO - D7 are placed in the 3-State
condition.
DTACKN
22
0
Data Transfer Acknowledge: Active-Low, 3-State. DTACKN is asserted on a write cycle
to indicate that the data on the bus has been latched, and on a read cycle or interrupt acknowledge cycle to indicate valid data is on the bus. The signal is negated when completion of the cycle is indicated by negation of the CSN or IACKN input, and returns to the
inactive state (3-State) a short period after it is negated. In a single address DMA mode,
data is latched with the falling edge of DTCN. DTACKN is negated when completion of the
cycle is indicated by the assertion of DTCN or negation of DMA acknowledge inputs (whichever occurs first). and returns to the inactive state (3-State) a short period after it is negated. When negated, DTACKN becomes an open-drain output and requires an external
pull-up resistor.
IRON
6
0
Interrupt Request: Active-Low, open-drain. This output is asserted upon occurrence of
any enabled interrupting condition. The CPU can read the general status register to determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle to
cause the DUSCC to output an interrupt vector on the data bus.
IACKN
1
I
Interrupt Acknowledge: Active-Low. When IACKN is asserted, the DUSCC responds by
placing the contents of the interrupt vector register (modified or unmodified by status) on
the data bus and asserting DTACKN. If no active interrupt is pending, DTACKN is not
asserted.
Xl/CLK
43
I
Crystal or External Clock: When using the crystal oscillator, the crystal is connected
between pins X 1 and X2. If a crystal is not used, and external clock is supplied at this
input. This clock is used to drive the internal bit rate generator. as an optional input to the
counter/timer or DPLL, and to provide other required clocking signals.
X2IIDCN
42
I/O
RESETN
7
I
Master Reset: Active-Low. A low on this pin resets the transmitters and receivers and
resets the registers shown in Table 1. Reset in asynchronous, I.e., no clock is required.
RxDA, RxDB
37,12
I
Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If
external receiver clock is specified for the channel, the input is sampled on the rising edge
of the clock.
TxDA, TxDB
36,13
0
Channel A (B) Transmitter Serial Data Output: The least signifiicant bit is transmitted
first. This output is held in the marking (High) condition when the transmitter is disabled or
when the channel is operating in localloopback mode. If external transmitter clock is specified for the channel, the data is shifted on the falling edge of the clock.
RTxCA, RTxCB
39, 10
I/O
Channel A (B) ReceiverlTransmiUer Clock: As an input, it can be programmed to supply
the receiver, transmitter, counter/timer, or DPLL clock. As an output, can supply the counter/timer output, the transmitter shift clock (1 X), or the receiver sampling clock (1 X). The
maximum external receiver/transmitter clock frequency is 4MHz.
October 30, 1990
Crystal or Interrupt Daisy Chain: When a crystal is used as the timing source, the crystal is connected between pins XI and X2. This pin can be programmed to provide and
interrupt daisy chain active-Low output which propagates the IACKN signal to lower priority
devices, if no active interrupt is pending. This pin should be grounded when an external
clock is used on X 1 and X2, is not used as an interrupt daisy chain output.
300
Product Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller (DUSCC)
SCN68562
PIN DESCRIPTION (Continued)
MNEMONIC
DIP
PIN NO.
NAME AND FUNCTION
TYPE
TRxCA. TRxCB
40.9
I/O
Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver,
transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer
output, the DPLL output, the transmitter shift clock (1X), the receiver sampling clock (1X),
the transmitter BRG clock (16X), The receiver BRG clock (16X), or the internal system
clock (X1/2). The maximum external receiver/transmitter clock frequency is 4MHz.
CTSAlBN, LCAI
BN
32,17
I/O
Channel A (B) Clear-To-Send Input or Loop Control Output: Active-Low. The signal
can be programmed to act as an enable for the transmitter when not in loop mode. The
DUSCC detects logic level transitions on this input and can be programmed to generate an
interrupt when a transition occurs. When operating in the COP loop mode, this pin becomes a loop control output which is asserted and negated by DUSCC commands. This
output provides the means of controlling external loop interface hardware to go on-line and
off-line without disturbing operation of the loop.
DCDAlBN,
SYNIAIBN
38,11
I
Channel A (8) Data Carrier Detected or External Sync Input: The function of this pin is
programmable. As a DCD active-Low input, it acts as an enable for the receiver or can be
used as a general purpose input for the DCD function, the DUSCC detects logic level
transitions on this input and can be programmed to generate an interrupt when a transition
occurs. As an active-Low external sync input, it is used in COP modes to obtain character
synchronization without receipt of a SYN character. This mode can be used in disc or
tape controller applications or for the optional byte timing lead in X.21.
RTxDROAlBN,
GP01A1BN
34,15
0
Channel A (8) ReceiverlTransmltter DMA Service Request or General Purpose
Output: Active-Low. For half-duplex DMA operation, this output indicates to the DMA
controller that one or more characters are available in the receiver FIFO (when the receiver
is enabled) or that the transmit FIFO is not full (when the transmitter is enabled). For
full-duplex DMA operation, this output indicates to the DMA controller that data is available
in the receiver FIFO. In non-DMA mode, this pin is a general purpose output that can be
asserted and negated under program control.
TxDROA/BN,
GP02A1BN,
RTSA/BN
33,16
0
Channel A (8) Transmitter DMA Service Request, General Purpose Output, or Request-to-Send: Active-Low. For full-duplex DMA operation, this output indicates to the
DMA controller that the transmit FIFO is not full and can accept more data. When not in
full-duplex DMA mode, this pin can be programmed as a general purpose or a Request-to
-Send output, which can be asserted and negated under program control (see Detailed
Operation).
RTxDAKA/BN,
GPI1A/BN
44,5
I
Channef A (8) ReceiverlTransmil1er DMA Acknowledge or Generaf Purpose Input:
Active-Low. For half-duplex single address DMA operation, this input indicates to the
DUSCC that the DMA controller has acquired the bus and that the requested bus cycle
(read receiver FIFO or load transmitter FIFO) is beginning. For full-duplex single address
DMA operation, this input indicates to the DUSCC that the DMA controller has acquired the
bus and that the requested read receiver FIFO bus cycle is beginning. Because the state
of this input can be read under program control, it can be used as a general purpose input
when not in single address DMA mode.
TxDAKAlBN,
GP12A1BN
35,14
I
Channel A (8) Transmitter DMA Acknowledge or General Purpose Input: Active-Low.
When the channel is programmed for full-duplex single address DMA operation, this input
is asserted to indicate to the DUSCC that the DMA controller has acquired the bus and that
the requested load transmitter FIFO bus cycle is beginning. Because the state of this input
can be read under program control, it can be used as a general purpose input when not in
full-duplex single address DMA mode.
DTCN
23
I
Device Transfer Complete: Active-Low. DTCN is asserted by the DMA controller to indicate that the requested data transfer is complete.
DONEN
27
I/O
Done: Active-Low, open-drain. See Detailed Operation for a description of the function of
this pin.
RTSAlBN,
SYNOUTAIBN
41,8
0
Channel A (8) Sync Detect or Request-to-Send: Active-Low. If programmed as a sync
output, it is asserted one bit time after the specified sync character (COP or BISYNC
modes) or a FLAG (BOP modes) is detected by the receiver. As a Request-te-Send modem control signal, it functions as described previously for the TxDRON/RTSN pin.
Voo
48
I
+5V ± 10% power input.
GND
24
I
Signal and power ground input.
October 30, 1990
301
Product Specification
Philips Components-Signetics Data Communication Products
SCN68562
Dual universal serial communications controller (DUSCC)
ABSOLUTE MAXIMUM RATINGS1
RATING
UNIT
o to +70
°C
Storage Temperature
-65 to +150
°C
Voltage from Vee to GND3
-0.5 to +7.0
V
SYMBOL
PARAMETER
TA
Operating ambient temperature2
TSTG
Vee
V
Voltage from any pin to ground3
-0.5 to Vec +0.5
Vs
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on + 150°C maximum junction temperature and thermal resistance of 40°CIW for plastic DIP and 42°CIW for PLCC.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge.
Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
DC ELECTRICAL CHARACTERISTICS1, 2, 5 TA = 0 to +70°C, Vee = 5.0V -+ 5%
LIMITS
SYMBOL
Vil
VIH
PARAMETER
Input low voltage:
All except XIIClK
XI/ClK
Input high voltage:
All except XIIClK
XI/ClK
TEST CONDITIONS
Min
2.0
2.4
VOH
Output low voltage:
All except IRON, DONEN
IRON, DONEN
Output high voltage:
(Except open drain outputs)
IOH = -4001JA
IllXl
IIHXl
Xl/CLK input low current4
XI/CLK input high current4
VIN = 0, X2 = GND
VIN = Vee, X2 = GND
IllX2
IIHX2
X2 input low current4
X2 input high current4
VIN =0, XI = open
VIN = Vee, XI = open
-100
III
Input low current
DTCN, TxDAKAlBN, RTxDAKAIBN
Il
Input leakage current
IOZH
lozl
IODl
Output off current high, 3-State data bus
Output off current low, 3-State data bus
VOL
IODH
lee
IOl = 5.3mA
IOl = 8.8mA
VIN =0
-40
VIN=OtoVee
-5
VIN = Vee
VIN = 0
-5
Open drain output low current in off
state:
DONEN
IRON, DTACKN
Open drain output high current in off
state:
DON EN, IRON, DTACKN
Power supply current
Input capacitance3
Output capacitance3
Input/output capacitance 3
2.4
-5.5
Typ
Max
UNIT
0.8
0.4
V
V
Vee
V
V
0.5
0.5
V
V
0.0
1.0
rnA
rnA
100
IJA
IJA
V
5
5
IJA
IJA
IJA
IJA
VIN =0
-120
-5
-25
VIN = Vee
Vo = 0 to Vee
Vee = GND = 0
Vee = GND = 0
Vee = GND = 0
IJA
IJA
5
IJA
275
10
15
20
rnA
pF
pF
pF
CIN
COUT
CIK>
NOTES:
I. Parameters are valid over specified temperature and voltage range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except XI/ClK swing between O.4V and 2.4V with a transition time of 20ns maximum. For XI/ClK, this swing is between OV and 2.8V. All time measurements are referenced at input voltages of O.BV
and 2.0V and output voltages of O·.BV and 2.0V, as appropriate.
3. These values were not explicitly tested; they are guaranteed by design and characterization data.
4. XI/CLK and X2 are not tested with a crystal installed.
5. This specification applies to revision C, revision E and later revisions.
October 30, 1990
302
Product Specification
Philips Components-Signetics Data Communication Products
SCN68562
Dual universal serial communications controller (DUSCC)
AC ELECTRICAL CHARACTERISTICS1, 2, 3, 4 TA = -55 to + 110°c, Vee = 5V -+ 10%
LIMITS
NO_
FIGURE
PARAMETER
Min
Typ
Max
UNIT
1
12
RESETN pulse width
1.2
I'S
2
3
4
5
6
7
7A
8
9
10
11
12
12A
13
14
15
13,15
13.15
13,15
13,15
13,15
13,16
16
13,16
13
15
13,16
13,15
15
13,15
13,15
16
AI - A6 set-up time to CSN Low
AI - A6 hold time from CSN High
RWN set-up time to CSN Low
RWN hold time to CSN High
CSN High pulse width'
CSN or IACKN High from DTACKN Low
IACKN High to DTACKN High
Data valid from CSN or IACKN Low
Data bus floating from CSN High 7
Data hold time from DTACKN LowS
DTACKN Low from read data ready
DTACKN Low from CSN Low
CSN Low to write data valid
DTACKN High from CSN High
DTACKN high impedance from CSN High
DTACKN Low from IACKN Low
10
560
50
150
185
550
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
16
17
18
17
17
GPI input set-up time to CSN Low
GPI input hold time from CSN Low
GPO output valid from DTACKN Low
300
nS
nS
nS
19
18
450
450
400
400
400
nS
nS
nS
nS
nS
20
17
19
a
a
a
160
30
200
300
100
a
a
20
100
IRON High from:
Read RxFIFO (RxRDY interrupt~
Write TxFIFO (TxRDY interrupt)
Write RSR (Rx condition interrupt)"
Write TRSR (RxfTx interrupt)B
Write ICTSR (port change and CT in!.)B
25
2.0
100
X1ICLK High or Low time
Xl/CLK frequency
CTCLK High or Low time
CTCLK frequency
RxC High or Low time
RxC frequency (16X or lX)9
TxC High or Low time
TxC frequency (16X or IX)
a
110
a
110
a
14.745
6
4
nS
MHz
nS
MHz
nS
MHz
nS
MHz
240
435
50
nS
nS
nS
16
4
4
21
20
22
20
TxD output from TxC input Low (IX)
(16X)
TxD output from TxC output Low
23
24
21
21
RxD data set-up time to RxC High
RxD data hold time from RxC High
25
22
IACKN Low to daisy chain Low
200
nS
26
Data valid from receive DMA ACKN
DTCNwidth
RDYN Low to DTCN Low
Data bus float from DTCN Low7
DMA ACKN Low to RDYN (DTACKN) Low
RDYN High from DTCN Low
RDYN High impedance from DTCN Low
Receive DMA REON High from DMA ACKN Low
Receive DMA ACKN width
Receive DMA ACKN Low to DONEN Low
Data set-up to DTCN Low
Data hold from DTCN Low6
Transmit DMA REON High from ACKN Low
Transmit DMA ACKN width
Transmit DMA ACKN Low to DONEN Low output
DTCN Low DONEN output High
300
27
28
29
30
31
32
33
34
35
36
37
38
39
40
40A
24
23,24
23,24
24
23,24
23,24
23,24
24
24
23,24
23
23
23
23
23
23
250
260
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
41
42
43
44
25
25
25
25
CSN
CSN
CSN
CSN
300
400
300
400
nS
nS
nS
nS
October 30, 1990
50
50
Low to transmit DONEN Low output
Low to transmit DMA REO negated
Low to receive DONEN Low
Low to receive DMA REO negated
303
nS
nS
100
80
200
360
230
250
325
150
250
50
50
340
150
Philips Components-Signetics Data Communication Products
Product Specification
Dual universal serial communications controller (DUSCC)
SCN68562
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For D.C. and functional testing, all inputs except Xl/ClK swing between 0.4V
and 2.4V with a transition time of 20ns maximum. For Xl/ClK, this swing is between 0.4V and 4.4V All time measurements are referenced
at input voltages of 0.2V and 2.4V for all inputs. Output levels are referenced at I.SV.
3. Test conditions for outputs: CL ~ 150pF, except open-drain outputs. Test condition for open-drain outputs: CL ~ SOpF to GND, RL ~ 2.7fill to
Vee except DTACKN whose Rl - 820n to Vee and CL ~ 150pF to GND and DONEN which requires CL ~ 50pF to GND and Rl ~ Ifill to
Vee·
4. This specification will impose maximum 68000 CPU ClK to 6MHz. Higher CPU ClK can be used if repeating bus cycles are not performed.
5. Execution of the valid command (after it is latched) requires three falling edges of XI (see Figure 14).
6. In single address DMA mode write operation, data is latched by the falling edge of DTCN.
7. These values were not explicitly tested, they are guaranteed by design and characterization data.
8. These timings are from the falling edge of DTACKN (not CSN rising).
9. Xl/ClK frequency must be at least four times the receiver serial data rate.
REGISTERS
3. Counter/timer control and value registers.
The addressable registers of the DUSCC are
shown in Table 1. The following rules apply to
all registers:
4. Interrupt control and status registers.
1. A read from a reserved location in the
map results in a read from the 'null register'. The null register returns all ones for
data and results in a normal bus cycle. A
write to one of these locations results in a
normal bus cycle without a write being
performed.
This arrangement is used in the following description of the DUSCC registers.
2. Unused bits of a defined register are read
as zeros, unless ones have been loaded
after master reset.
3. Bits that are unused in the chosen mode
but are used in others are readable and
writable but their contents are ignored in
the chosen mode.
4. All registers are addressable as 8-bit
quantities. To facilitate operation with the
68000 MOVEP instruction, addresses are
ordered such that certain sets of registers
may also be accessed as words or long
words.
The operation of the DUSCC is programmmed
by writing control words into the appropriate registers. Operational feedback is provided via
status registers which can be read by the CPU.
The contents of certain control registers are initialized on RESET. Care should be exercised
if the contents of a register are changed during
operation, since certain changes may cause
operational problems, e.g., changing the channel mode at an inappropriate time may cause
the reception or transmission of an incorrect
character. In general, the contents of registers
which control transmitter or receiver operation,
or the counter/timer, should be changed only
when they are not enabled.
The DUSCC registers can be separated into
five groups to facilitate their usage:
1. Channel mode configuration and pin description registers.
2. Transmitter and receiver parameter and
timing registers.
October 30, 1990
acter comparisons are made using
EBCDIC coding.
Odd parity if with parity is selected by
[4:3] or a 1 in the parity bit position if
force parity is selected by [4:3[. In BISYNC protocol mode, intemal character comparisons are made using
7-bit plus odd parity ASCII coding.
(Note: The receiver should be programmed for 7 -bit characters,
RPR[1 :0] ~ 11, with no parity,
CMR1[4:3] ~ 00.)
5. Command register.
Channel Mode Configuration and
Pin Description Registers
There are five registers in this group for each
channel. The bitformatforeach of these registers is contained in Table 2. The primary function of these registers is to define configuration
of the channels and the function of the programmable pins. A channel cannot be dynamically
reconfigured. Do not write to CMRI or CMR2
if the receiver or transmitter is enabled.
Channel Mode Register 1
(CMR1A, CMR1 B)
[1:6] Data Encoding - These bits select the
data encoding for the received and transmitted
data:
00
[4:3] Address Mode (BOP) - This field controls whether a single octet or multiple octets
follow the opening FLAG(s) for both the receiver and the transmitter. This field is activated by
selection of BOP secondary mode through the
channel protocol mode bits CMR1[2:0] (see
Detailed Operation).
00
Single-octet address.
01
Extended address.
10
Dual-octet address.
11
Dual-octet address with group.
If the DPll is set to NRZI mode (see
DPll commands), it selects positive
10gic(1 ~ High, 0 ~ low). If the DPll
is set to FM mode (see DPll commands), Manchester (bi-phase level)
encoding is selected.
[4:3] Pairty Mode(COP/ASYNC)- This field
selects the parity mode for both the receiver
and the transmitter. A parity bit is added to the
programed character length if with parity or
force parity is selected:
01
NRZr. Non-return-to-zero inverted.
00
10
FMO. Bi-phase space.
11
FM1. Bi-phase mark.
[5] Extended Control (BOP)o
No. A one-octet control field follows
the address field.
Yes. A two-octet control field follows
the address field.
[5] Parity (COP/ASYNC), Code Select
(BISYNC)-
o
Even parity if with parity is selected by
[4:3] or a 0 in the parity bit position if
force parity is selected by [4:3]. In BISYNC protocol mode, internal char-
304
No pairty. Required when BISYNC
protocol mode is programmed.
01
Reserved.
10
With parity. Odd or even parity is selected by [5].
11
Force parity. The parity bit is forced to
the state selected by [5].
[2:0] Channel Protocol Mode - This field selects the operational protocol and submode for
both the receiver and transmitter:
000
BOP Primary. No address comparison is performed. For receive, all
characters received after the opening
FLAG(s) are transferred to the FIFO.
Product Specification
Philips Components-Signetics Data Communication Products
SCN68562
Dual universal serial communications controller (DUSCC)
001
010
BOP Secondary. This mode activates the address modes selected by
[4:3]. Exceptin the case of extended
address ([4:3] = 01), and address
comparison is pertormed to determine if a frame should be received.
Referto Detailed Operation for details
of the various addressing modes. If a
valid comparison occurs, the receiver
is activated and the address octets
and all subsequent received charactersofthe frame are transferred to the
receive FIFO.
commands are used to cause the
DUSCC to go on and off the loop.
Normally, the TxD output echos the
RxD input with a two-bit time delay. If
the transmitter is enabled and the 'go
active on poll' command has been asserted, the transmitter will begin
sending when an EOP sequence consisting of a zero followed by seven
ones is detected.
The DUSCC
changes the last one of the EOP to
zero, making it another FLAG, and
then operates as described in the Detailed Operation section. The loop
sending status bit (TRSR[6L is asserted concurrent with the beginning
of transmission. The frame should
BOP Loop. The DUSCC acts as a
secondary station in a loop. The
GO-ON-LOOP and GO-OFF-LooP
Table 1.
normally be terminated with an EOM
followed by an echo of the marking
RxD line so that secondary stations
further down the loop can append
their messages to the messages from
up-loop stations by the same process.
If the 'go active on poll' command is
not asserted, the transmitter remains
inactive (other than echoing the received data) even when the EOP sequence is received.
011
BOP Loop without address comparison. Same as normal loop mode except that address field comparisons
are disabled. All received frames are
transmitted to the CPU.
DUSCC Register Address Map
ADDRESS BITS'
654321
cOOOOO
cOOOOl
cOO010
cOO 0 11
c00100
c0010l
cO 0110
cOO 111
cOl000
cOl00l
cO 1 010
cO 1 01 1
cO 11 00
cO 11 0 1
cO 111 0
cO 1111
cl00XX
cl01XX
c 11000
ell 00 1
c 11010
d 11011
c 111 00
ell 101
011110
111110
011111
111111
ACRONYM
CMRl
CMR2
SlR
S2R
TPR
ITR
RPR
RTR
CTPRH
CTPRL
CTCR
OMR
CTH
CTL
PCR
CCR
TxFIFO
RxFIFO
RSR
TRSR
ICTSR
GSR
IER
IVR
IVRM
ICR
REGSITER NAME
MODE
Channel Mode Register 1
Channel Mode Register 2
SYN 1/Secondary Address 1 Register
SYN 2/Secondary Address 2 Register
Transmitter Parameter Register
Transmitter TIming Register
Receiver Parameter Register
Receiver TIming Register
Counter/limer Preset Register High
Countermmer Preset Register Low
Counter/limer Control Register
Output and Miscellaneous Register
Counter/limer High
Counter/limer Low
Pin Configuration Register
Channel Command Register
Transmitter FIFO
Receiver FIFO
Receiver Status Register
Transmitter and Receiver Status Register
Input and Counter/Timer Status Register
General Status Register
Interrupt Enable Register
Not used
Interrupt Vector Register- Unmodified
Interrupt Vector Register- Modified
Interrupt Control Register
Not used
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
R
R
RIW
RIW
W
R
RIW"
RIW"
RIW"
RIW"
RIW
RIW
R
RlW
AFFECTED
BY
RESET
Yes-OO
Yes-OO
No
No
Yes-OO
No
Yes-OO
No
No
No
Yes-OO
Yes-OO
No
No
Yes-OO
No
No
No
Yes-OO
Yes-OO
Yes
Yes-OO
Yes-OO
Yes-OF
Yes-OF
Yes-OO
NOTES:
, c = 0 for Channel A, c = 1 for Channel B.
d = don't care - register may be accessed as either channel.
x = don't care - FIFOs are addressable at any of four adjacent addresses to allow them to be addressed as bytelword/long word with the
68000 MOVEP instruction .
.. A write to this register may pertorm a status resetting operation.
100
101
COP Dual SYN. Character sync is
achieved upon receipt of a bit sequence matching the contents of the
appropriate bits of Sl Rand S2R
(SYN 1-SYN2), including parity bits if
any.
COP Dual SYN (BISYNC). Character
sync is achieved upon receipt of a bit
sequence matching the contents of
the appropriate bits of S 1Rand S2R
(SYN1-SYN2). In this mode, special
transmitter and receive logic is acti-
October 30, 1990
110
vated. Transmitter and receiver character length must be programmed to
8 bits and no parity (see Detailed Operation).
Channel Mode Register 2
(CMR2A, CMR2B)
COP Single SYN. Character sync is
achieved upon receipt of a bit sequence matching the contents of the
appropriate bits of SlR (SYN1), including parity bit if any. This mode is
required when the external sync
mode is selected (see description of
RPR[4], BOP/COP).
[7:6) Channel Connection - This field selects the mode of operation of the channel. The
user must exercise care when switching into
and out of the various modes. The selected
mode will be activated immediately upon mode
selection, even if this occurs in the middle of a
received or transmitted character.
305
111
Asynchronous. Start/stop format.
Product Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller (DUSCC)
00
Normal mode. The transmitter and
receiver operate independently in either half- or full-duplex, controlled by
the respective enable commands.
01
Automatic echo mode. Automatically
retransmits the received data with a
half-bit time delay (ASYNC, 16X clock
mode) or a two-bit time delay (all other
modes). The following conditions are
true while in automatic echo mode:
1. Received data is reclocked and
retransmitted on the TxD output.
2. The receiver clock is used for the
transmitter for ASYNC 16X clock
mode. For other modes the
transmitter clock must be
supplied.
[5:3] Data Transfer Interface- This field specifies the type of data transfer between the
DUSCC's Rx andTxFIFOs and the CPU. All interrupt and status functions operate normally
regardless of the data transfer interface programmed. Refer to Detailed Operation for details of the various DMA transfer interfaces.
000
Half-duplex single address DMA.
001
Half-duplex dual address DMA.
000
No frame check sequence.
010
Full-duplex single address DMA.
001
Reserved
011
Full-duplex dual address DMA.
010
100
Wait on receive only. In this mode a
read of a non-empty receive FIFO resuits in a normal bus cycle. However,
if the receive FIFO of the channel is
empty when a read Rx FIFO cycle is
initiated, the DTACKN output remains
negated until a character is received
and loaded into the FIFO. DTACKN
is then asserted and the cycle is completed normally.
LRCS: Divsior = x8 + I, dividend preset to' zeros. The Tx sends the calculated LRC non-inverted. The Rx
indicates and error if the computed
LRC is not equal to O. Valid for COP
modes only.
011
LRCS: Divisor = x8 + I, dividend preset to ones. The Tx sends the calculated LRC non-inverted. The Rx
indicates an error if the computed
LRC is not equal to O. Valid for COP
modes only.
100
. CRCI6: Divisor - X16 + X15 + x2 + I,
dividend preset to zeros. The Tx
sends the calculated CRC non-inverted. The Rx indicates an error if
the comuted CRC is not equal to O.
Not valid for ASYNC mode.
101
CRCI6: Divisor = X 16 + X15 + X2 + I,
dividend preset to ones. The Tx
sends the calculated CRC non-inverted. The Rx indicates an error if
the computed CRC is not equal to O.
Not valid for ASYNC mode.
110
CRC-CCITT: Divisor = X 16 + X12 + X5
+ I, dividend preset to zeros. The Tx
sends the calculated CRC non-inverted. The Rx indicates an error if
the com puted C RC is not equal to O.
Not valid for ASYNC mode.
111
CRC-CCITT: Divisor = X 16 + X12 + x5
+ I, dividend preset to ones. The Tx
sends the calculated CRC inverted.
The Rx indicates an error if the computed CRC is not equal to H'FOBS·.
Not valid for ASYNC mode.
4. The TxRDY and underrun status
bits are inactive.
10
Wait on transmit only. In this mode a
write to a non-full transmit FIFO resuits in a normal bus cycle. However,
if the transmit FIFO of the channel is
full when a write TxFIFO cycle is initiated, the DTACKN output remains negated until a FIFO position becomes
available for the new character.
DTACKN is then asserted and the
cycle is completed normally.
110
7. CPU to receiver communication
continues normally, but the CPU
to transmitter link is disabled.
Wait on transmit and receive. As
above for both wail on receive and
transmit operations.
111
Polled or interrupt. DMA and wait
function of the channel are not activated. Data transfers to the Rx and
TxFIFOs are via normal bus read and
write cycles in response to polling of
the status registers and/or interrupts.
1. The transmitter data output and
clock are intemally connected to
the receiver.
2. The transmit clock is used for the
receiver if NRZI or NRZ encoding
is used. For FM or Manchester
encoding because the receiver
clock is derived from the DPLL,
the DPLL source clock must be
maintained.
[2:0] Frame Check Sequence Select - This
field selects the optional frame check sequence
(FCS) to be appended at the end of a transmitted frame. When CRC is selected in COP,
then no pairty and S-bit character length must
be used. The selected FCS is transmitted as
follows:
3. The TxD output is held High.
1. Following transmission of a FIFOed char-
4. The RxD input is ignored.
5. The receiver and transmitter
must be enabled.
6. CPU to transmitter and receiver
communications continue normally.
11
101
6. In ASYNC mode, character framing is checked, but the stop bits
are retransmitted as received. A
received break is echoed as received.
Localloopback mode. In this mode:
acter tagged with the 'send EOM' command.
2. If underrun control (TPR[7:6J) is programmed for TEaM, upon occurrence of
an underrun.
3. If TEaM on zero count or done (TPR[4J)
is asserted and the counter/timer is count-
Reserved.
October 30, 1990
ing transmitted characters, after transmission of the character which causes the
counter to reach zero cOunt.
4. In DMA mode with TEaM on zero count
or done (TPR[4J) set, after transmission of
a character if DONEN is asserted when
that character was loaded into the TxFIFO
by the DMA controller.
3. The receiver must be enabled,
but the transmitter need not be
enabled.
5. The received parity and/or FCS
are checked if required, but are
not regenerated for transmission,
i.e., transmitted parity and/or
FCS are as received.
SCN68562
306
SYN1/Secondary Address 1
Register (S1RA, S1RB)
[7:0} Character Compare-In ASYNC mode
this register holds a 5- to B-bit long bit pattern
which is ocmpared with received characters. if
a match occurs, the character compare status
bit (RSR[7J) is set. This field is ignored if the receiver is in a break condition.
Product Specification
Philips Components-Signetics Data Communication Products
SCN68562
Dual universal serial communications controller (DUSCC)
SYN2/Secondary Address 2
Register (S2RA, S2RB)
In COP modes, this register contains the 5- to
a-bit SYNI bit pattern, right justified. Parity bit
need not be included in the value placed in the
registereven is parity is specified in CMRI [4:3].
However, a character received with parity error,
when parity is specified, will not match. In
ASYNC, or COP modes, if parity is specified,
then any unused bits in this register must be
programmed to zeros. In BOP secondary
mode it contains the address used to compare
the first received address octet. The register is
not used in BOP primary mode or secondary
modes where address comparisons are not
made, such as when extended addressing is
specified.
Table 2.
the partial address used to compare the second
received address octet.
Pin Configuration Register
(PCRA, PCRB)
[7:0] - This register is not used in ASYNC,
COP single SYN, BOP primary modes, BOP
secondary modes with single address field, and
BOP secondary modes where address comparisons are not made, such as when extended
addressing is specified.
This register selects the functions for mUltipurpose 110 pins.
[7] X2I1DC - This bit is defined only for PCRA.
It is not used in PCRB.
In COP dual SYN modes, it contains the 5- to
a-bit SYN2 bit pattern, right justified, Parity bit
need not be included in the value placed in the
register even if parity is specified in CMR1[4:3].
However, a character received with parity error,
when parity is specified, will not match. If parity
is specified, then any unused bits in this register
mustbe programmed to zeros. In BOP secondary mode using two address octets, it contains
o
TheX2IIDCN pin is used as a crystal
connection.
The X2IIDCN pin is the interrupt daisy
chain output.
[6] GP02/RTS- The function of this pin isprogrammable only when not operating in full-duplex DMA mode.
Channel Configuration/Pin Definition Registers Bit Formats
CHANNEL MODE REGISTER 1
BIT7
I
BIT6
BITS
Data Encoding
00 - NRZlManchester
(CMRIA.
CMR1B)
BIT 4
Extended
Control
BIT2
BIT3
01 - extended address
10-16-bit
11-16-bitw/group
11~FMl
Parity'
I
BITI
I
BITO
Channef Protocol
Mode
Address Mode (BOP)
~O-a-bit
BOP only
O-no
I-yes
01-NRZI
10-FMO
I
000 001 010 011 -
BOP primary
BOP secondary
BOP loop
BOP loop - no adr. compo
Parity Mode (COP/ASYNC)
~O-no
O-even
I-odd
parity
01 - reserved
10 - with parity
11 - force parity
100 - COP dual SYN
101 - COP dual SYN (BISYNC)
110 - COP single SYN
111 - asynchronous
NOTE:
• In BISYNC protocol mode, 0 = EBCDIC, 1 = ASCII coding.
CHANNEL MODE REGISTER
BIT 7
I
BIT6
BfTS
Channel Connection
(CMR2A.
CMR2B)
I
BIT4
I
BIT 3
BIT2
OO-normal
01 - auto echo
10 - local loop
11 - reserved
I
BITI
I
BITO
Frame Check Sequence Select
Data Transfer Interface
000 - half-duplex single address DMA
00 1 - half -du plex dual address D MA
010 - full-duplex single address DMA
all - full-duplex dual address DMA
100 - wait on Rx only
101-waitonTxonly
110 -wait on Rx orTx
l11-polledorinterrupt
ODD-none
00 1 - reserved
010 - LRCa preset as
all - LRCa preset Is
100 - CRC 16 preset Os
101-CRC 16 preset Is
110 - CRC CCITT preset Os
111 - CRC CCITT preset Is
SYNl/SECONDARY ADDRESS REGISTER 1
BIT 7
(SlRA.
SlRB)
October 30, 1990
I
BIT6
I
BITS
1
BIT 4
J
BIT3
I
ASYNC - Character compare (5 - a bits)
COP - SYNI (5 - a bits)
BOP - First address octet
307
BIT 2
I
BITI
I
BITO
Product Specification
Philips Components--Signetics Data Communication Products
SCN68562
Dual universal serial communications controller (DUSCC)
Table 2.
Channel Configuration/Pin Definition Registers Bit Formats (Continued)
SYN2ISECONDARY ADDRESS REGfSTER 2
BfT7
I
BIT6
I
I
BITS
I
BIT 4
BIT3
I
BIT 2
I
BIT 1
I
BITO
ASYNC - not used
COP - SYN2 (5 - 8 bits)
BOP - Second address octet
(S2RA,
S2RB)
PIN CONFIGURATION REGISTER
BIT7
.
X2IIDS
(PCRA,
PCRB)
0-X2
I-IDC
BIT 6
BITS
GP02/RTS
SYNOUT/RTS
O-GP02
I-RTS
I
BIT4
O-SYNOUT
I-RTS
BIT3
BIT2
RTxC Pin
OO-input
Ol-CIT
10-TxCLK IX
11- RxCLK IX
I
BITt
I
BITO
TRxCPln
OOO-input
001 -XTAU2
OIO-DPLL
OIl-CIT
tOO - TxCLK 16X
101 - RxCLK 16X
110- TxCLK IX
III - RxCLK IX
NOTE:
• PCRA only. Not used in PCRB.
o
The TxDRQN/GP02N/RTSN pin is a
general purpose output. It is Low
when OMR[2] is a I and High when
OMR[2] is a o.
The pin is a request-to-send output
(see Detailed Operation). The logical
state of the pin is controlled by
OMR[O]. When OMR[O] is set, the
output is Low.
l a T h e pin is an output for the transmitter
shift register clock.
Transmitter and Receiver Parameter and Timing Registers
II
This set of five registers contains the information which controls the operation of the transmitter and receiver for each channel. Table 3
shows the bit map format for each of these registers. The registers of this group are:
[2:0] TRxC000
[S] SYNOUT/RTS ·0
The SYNOUTN/RTSN pin is an active-Low output which is asserted one
bit time after a SYN pattern (COP
modes) in HSRH/HSRL or FLAG
(BOP modes) is detected in CCSR.
The output remains asserted for one
receiver clock period. See Figure 1
for receiver data path.
The pin is a request-to-send output
(see Detailed Operation). The logical
state of the pin is controlled by
OMR[O] when OMR[O] is set, the outputis Low.
[4:31 RTxC00
aI
The pin is an input. It must be programmed for input when used as the
input for the receiver or transmitter
clock, the DPLL, or the CIT.
The pin is an output for the receiver
shift register clock.
The pin is an input. It must be programmed for input when used as the
input for the receiver or transmitter
clock, the DPLL, or the CIT.
ters (TPRAIB and TTRA/B)
001
The pin is an output from the crystal
oscillator divided by two.
2. Receiver parameter and timing registers
ala
The pin is an output for the DPLL output clock.
3. Output and miscellaneous register
(OMRA/B).
all
The pin is an output for the counterl
timer. Refer to CTCRAIB description.
100
The pin is an output for the transmitter
BRG at 16X the rate selected by TTR
[3:0].
101
The pin is an output for the receiver
BRG at 16X the rate selected by RTR
[3:0].
lID
The pin is an output for the transmitter
shift register clock.
The first and second group of registers define
the transmitter and receiver parameters and
timing. Included in the receiver timing registers
are the programming parameters for the DPLL.
The last register of the group, OMR contains
additional transmitter and receiver information
and controls the logical state of the output pins
when they are not used as a part of the channel
configuration.
III
The pin is an output for the receiver
shift register clock.
The pin is an output for the counterl
timer. Referto CTCRA/B description.
October 30, 1990
1. Transmitter parameter and timing regis-
308
(RPRA/B and RTRA/B)
A channel cannot be dynamically reconfigured.
Do not write to the RPR if the receiver is enabled, and do not write to the TPR if the transmitter is enabled.
Product Specification
Philips Components-Signetics Data Communication Products
SCN68562
Dual universal serial communications controller (DUSCC)
Table 3.
Transmitter and Receiver Parameter and Timing Register Bit Format
TRANSMITIER PARAMETER REGISTER
BIT 6
BIT 7
I
(TPRA,
TPRB)
COP
Underrun Control
00 - FCS-idle
01 - reserved
10-MARKs
II-SYNs
00 01 10 II -
BIT 4
BIT 3
BIT 2
Idle
TEOMon
Zero Cnt
or Done
TxRTS
Control
CTS
Enable Tx
O-MARKs
I-SYNs
Underrun Control
BOP
BITS
O-no
I-yes
O-MARKs
I-FLAGs
O-no
I-yes
I
BIT 0
Tx Character Length
OO-Sbits
01-6 bits
10-7 bits
II-Sbits
TEOMon
ZeroCnt
or Done
Idle
FCS-FLAG-idle
reserved
ABORT-MARKs
ABORT-FLAGs
O-no
I-yes
BIT 1
O-no
I-yes
Stop Bits Per Character
9/16 to I, 17/16 to 1.5, 25116 to 2
programmable in 1/16-bit increments
ASYNC
TRANSMITIER TIMING REGISTER
BIT7
(TIRA,
TIRB)
0- RTxC
I-TRxC
I
BIT6
External
Source
BITS
I
BIT4
BIT 3
Transmitter Clock Select
I
BIT2
I
BIT1
I
BITO
I
BITO
Bit Rate Select
000 - I X external
001 -16X external
OIO-DPLL
Oll-BRG
100 - 2X other channel CIT
101 - 32X other channel CfT
110 - 2X own channel CIT
III - 32X own channel CfT
one 01 sixteen rates Irom BRG
RECEIVER PARAMETER REGISTER
(RPRA,
RPRB)
BIT7
BIT6
BITS
BIT4
BIT3
BIT 2
not used
not used
not used
RxRTS
Control
Strip
Parity
DCD
Enable Rx
Rx Character Length
O-no
I-yes
O-no
I-yes
O-no
I-yes
00- Sbits
01-6bits
Ext Sync
Strip
Parity
ASYNC
COP
BOP
October 30. 1990
SYNStrlp
FCSto
FIFO
& Pad Chk
O-no
I-yes
O-no
I-yes
O-no
I-yes
O-no
I-yes
O-no
I-yes
not used
FCSto
FIFO
Overrun
Mode
not used
All Parity
Address
O-no
I-yes
O-hunt
I-cont
Auto Hunt
O-no
I-yes
309
BIT1
10-7bits
11 -S bits
Philips Components-Signetics Data Communication Products
Product Specification
SCN68562
Dual universal serial communications controller (DUSCC)
Table 3.
Transmitter and Receiver Parameter and Timing Register Bit Format (Continued)
RECEIVER TIMING REGISTER
BIT7
(RTRA,
RTRB)
I
BIT 6
External
Source
I
BITS
BIT3
BIT 4
Receiver Clock Select
O-RTxC
1-TRxC
I
BIT 2
I
BIT1
I
BITO
Bit Rate Select
000-IX external
001 -16X external
ASYNC
010-BRG
protocol
011 - CIT of channel
mode only
100 - DPLL, source = 64X Xl/CLK
101 - DPLL, source = 32X External
110 - DPLL, source = 32X BRG
111 - DPLL, source = 32X CIT
one of sixteen rates from BRG
I
OUTPUT AND MISC REGISTER
BIT7
(OMRA,
OMRB)
I
BIT6
I
BITS
Tx Residual Character Length
000-1 bit
001-2 bits
010-3bits
011-4bits
100-5 bits
101-6 bits
110-7bits
111 -same as TPR[I:01
Transmitter Parameter Register
(TPRA, TPRB)
[7:6) Underrun Control- In BOP and COP
modes, this field selects the transmitter response in the event of an underrun (I.e., the
TxFIFO is empty).
00
Normal end of message termination.
In BOP, thetransmittersends the FCS
(if selected by CMR2[2:0)) followed by
a FLAG and then either MARKs or
FLAGs, as specified by [5]. In COP,
the transmitter sends the FCS (if selected by CMR2[2:0)) and then either
MARKs or SYNs, as specified by [5].
01
Reserved.
10
In BOP, the transmitter sends an
ABORT (11111111) and then places
the TxD output in a marking condition
until receipt of further instructions. In
COP, the transmitter places the TxD
output in a marking condition until receipt of further instructions.
11
In BOP, the transmitter sends an
ABORT (11111111) and then sends
FLAGs until receipt of further instruction. In COP, the transmitter sends
SYNs until receipt of further instructions.
October 30, 1990
BIT4
BIT 3
BIT 2
BIT 1
BITO
TxRDY
Activate
RxRDY
Activate
OUT2
OUT 1
RTS
O-FIFO
not full
I-FIFO
empty
O-FIFO
not empty
I-FIFO
full
[5) Idle -In BOP and COP modes, this bit selects the transmitter output during idle. Idle is
defined as the state following a normal end of
message until receipt of the next transmitter
command.
o
Idle in marking condition.
Idle sending SYNs (COP) or FLAGs
(BOP).
[4) Transmit EOM on Zero Count or DoneIn BOP and COP modes,the assertion of this
bit causes the end of message (FCS in COP,
FCS-FLAG in BOP) to be transmitted upon the
following events:
1. If the counterltimer is counting transmitted
characters, after transmission of the character which causes the counter to reach
zero count. (DONEN is also asserted as
an output if the channel is in a DMA operation.)
2. If the channel is operating in DMA mode,
after transmission of a character if DONEN was asserted when that character
was loaded into the TxFIFO by the DMA
controller.
[7:4) Stop Bits per character - In ASYNC
mode, this field programs the length of the stop
bit appended to the transmitted character as
shown in Table 4.
310
Bit Pin
O-H
1-L
Table 4.
Bit Pin
O-H
1-L
Bit Pin
O-H
1-L
Stop BltsTransmitted Character
[7:4)
SBITSI
CHAR
6,7 or 8
BITS/CHAR
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1.063
1.125
1.188
1.250
1.313
1.375
1.438
1.500
1.563
1.625
1.688
1.750
1.813
1.875
1.938
2.000
0.563
0.625
0.688
0.750
0.813
0.875
0.938
1.000
1.563
1.625
1.688
1.750
1.813
1.675
1.938
2.000
Stop bit lengths of 9/16 to 1 and 1-9/16 to 2 bits,
in increments of 1/16-bit, can be programmed
for character lengths of G, 7, and 8 bits. For a
character length of 5 bits, 1-1116 to 2 stop bits
can be programmed in increments of l/1G-bit.
The receiver only checks for a 'mark' condition
atthe center of the first stop bit position (one bit
time after the last data bit, Qr after the parity bit
if parity is enabled) in all cases.
Product Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller (DUSCC)
If an external 1X clock (or a 2X clock for counter/timer) is used for the transmitter, [7] = 0 selects one stop bit and [7) = 1 selects two stop
bits to be transmitted. If Manchester, NRZI, or
FM data encoding is selected, only integral stop
bit lengths should be used.
[3) Transmitter Request-to-Send ControlThis bit controls the deactivation of the RTSN
output by the transmitter (see Detailed Operation).
o
RTSN is not affected by status of
transmitter.
010
011
Internal clock from the bit rate generator at 32X the shift rate. The clock signal is divided by two before use in the
transmitter which operates at 16X the
baud rate. Rate selected by [3:0).
100
Internal clock from counter/timer of
other channel. The CIT should be
programmed to produce a clock at 2X
the shift rate.
RTSN changes state as a function of
transmitter status.
[2) Clear-to-Send Enable Transmitter - The
state of this bit determines if the CTSN input
controls the operation olthe channel's transmitter (see Detailed Operation). The duration of
CTS level change is described in the discussion of ICTSR[4).
o
CTSN has no affect on the transmitter.
101
Transmitter Timing Register
(TTRA, TTRB)
[7) External Source - This bit selects the
RTxC pin or the TRxC pin of the channel as the
transmitter clock input when [6:4) specifies external. When used for input, the selected pin
must be programmed as an input in the PCR
[4:3) or [2:0).
o
External input form RTxC pin.
Internal clock from counterltimer of
other channel. The CIT should be
programmed to produce a clock at
32X the shift rate.
110
Internal clock from the counterltimer
of own channel. The CIT should be
programmed to produce a clock at 2X
the shift rate.
111
Internal clock from the counter/timer
of own channel. The CIT should be
programmed to produce a clock at
32X the shift rate.
CTSN affects the state of the transmitter.
[1 :0) Transmitted Bits per Character - This
field selects the number of data bits per character to be transmitted. The character length
does not includes the start, parity, and stop bits
in ASYNC or the parity bit in COP. In BOP
modes the character length for the address and
control field is always 8 bits, and the value of
this field only applies to the information (I) field,
except for the last character of the I field, whose
length is specified by OMR[7:5}.
Internal clock from the phase-lOCked
loop at lX the bit rate. It should be
used only in half-duplex operation
since the DPLL will periodically resync itself to the received data if in
full-duplex operation.
Table 5.
[3:0)
Receiver/Transmitter
Baud Rates
BIT RATE
0000
0001
0010
0011
0100
0101
0110
0111
50
75
110
134.5
150
001
Extemal clock from TRXC or RTxC at
16X the shift rate.
October 30, 1990
[3:0)
1000
1001
1010
1011
1100
1101
1110
1111
200
300
600
External input from TRxC pin.
External clock from TRxC or RTXC at
lX the shift (baud) rate.
(7) SYN Stripping - This bit controls the
DUSCC processing in COP modes of SYN
'character patterns' that occur after the initial
character synchronization. Refer to Detailed
Operation of the receiver for details and definition of SYN 'patterns', and their accumulation
of FCS.
o
BIT RATE
Strip only leading SYN 'patterns' (i.e.
before a message).
Strip all SYN 'patterns' (including all
odd DLE's in BISYNC transparent
mode).
[6) Transfer Received FCS to FIFO - In BISYNC and BOP modes, the assertion ofthis bit
causes the received FCS to be loaded into the
RxFIFO. When this bit is set, BOP mode operates correctly only if a minimum of two extra
FLAGs (without shared zeros) are appended to
the frame. If the FCS is specified to be transferred to the FI FO, the EOM status bit will be
tagged onto the last byte of the FCS instead of
to the last character of the message.
o
Do not transfer FCS to RxFIFO.
Transfer FCS to RxFIFO.
[5) Auto-Hunt and Pad Check (BISYNC) -In
BISYNC mode, the assertion of this bit causes
the receiver to go into hunt for character sync
mode after detecting certain End-Of-Message
(EOM) characters. These are defined in the
Detailed Operations section for COP receiver
operation. After the EOT and NAK sequences,
the receiver also does a check for a closing
PAD of four 1s.
o
Disable auto-hunt and PAD check.
Enable auto-hunt and PAD check.
[6:4) Transmitter Clock Select - This field
selects the clock for the transmitter.
000
Receiver Parameter Resgister
(RPRA, RPRB)
[3:0) Bit Rate Select -
This field selects an
output from the bit rate generator to be used by
the transmitter circuits. The actual frequency
output from the BRG is 32X the bit rate shown
in Table 5. With a crystal or external ciock of
14.7456MHz the bit rates are as given in Table
5 (this input is divided by two before being
applied to the oscillator circuit).
SCN68562
311
1050
1200
2000
2400
4800
9600
19.2K
38.4K
(5) Overrun Mode (BOP) - The state of this
control bit determines the operation of the receiver in the event of a data overrun, i.e., when
a character is received while the RxFIFO and
the Rx shift register are both full.
Product Specification
Philips Components-$ignetics Data Communication Products
Dual universal serial communications controller (DUSCC)
o
The receiver terminates receiving the
current frame and goes into hunt
phase, looking for a FLAG to be received.
The receiver continues receiving the
currentframe. The overrunning character is lost. (The five characters already assembled in the RxFIFO and
Rx shift register are protected).
[4] Receiver Request-to-Send Control
(ASYNC) - See Detailed Operation.
o
Receiver does not control RTSN output.
Receiver can negate RTSN output.
[4] External Sync (COP) In COP single
SYN mode, the assertion of this bit enables external character synchronization and receipt of
SYN patterns is not required. In order to use
this feature, the DUSCC must be programmed
to COP single SYN mode, CMR 1[2:0] = 110,
which is used to set up the internal data paths.
In all other respects, however, the external
sync mode operation is protocol transparent.
A negative signal on the DCDN/SYNIN pin will
cause the receiver to establish synchronization
on the next rising edge of the receiver clock.
Character assembly will start at this edge with
the RxD input pin considered to have the second bit of data. The sync signal can then be negated. Receipt of the Active-High external sync
input causes the SYN detect status bit (RSR[2])
to be set and the SYN BOUTN pin to be asserted for one bit time. When this mode is enable, the internal SYN (COP mode) detection
and special character recognition (e.g., IDLE,
STX, ETX, etc.) circuits are disabled. Character assembly begins as if in the I-field with character length as programmed in RPR[1 :)J.
Incoming COP frames with parity specified optionally can have it stripped by programming
RPR[3]. The user must wait at least eight bit
times after Rx is enabled before applying the
SYNIN signal. This time is required to flush the
internal data paths. The receiver remains in
this mode and further external sync pulses are
ignored until the receiver is disabled and then
reenabled to resynchronize or to retum to normal mode. See Figure 2.
o
External sync not enabled.
1
External sync enabled.
Note that EXT SYNC and DCD ENABLE Rx
cannot be asserted simultaneously since they
use the same pin.
October 30, 1990
[3] Strip Parity - In COP and ASYNC modes
with parity enabled, this bit controls whether the
received parity bit is stripped from the data
placed in the receiver FIFO. It is valid ony for
programmed character lengths of 5, 6, and 7
bits. If the bit is stripped, the corresponding bit
in the received data is set to zero.
o
Transfer parity bit as received.
Stop parity bit from data.
[3] All Parties Address - In BOP secondary
modes, the assertion of this bit causes the receiver to 'wake-up' upon receipt of the address
H'FF' or H'FF, FF', for single- and dual-octet address modes, respectively, in addition to its normal station address. This feature allows all
stations to receive a message.
o
Recognize all parties address.
o
Receiver Timing Register (RTRA,
RTRB)
[7] External Source -
This bit selects the
RTxC pin or the TRxC pin of the channel as the
receiver or DPLL clock input, when [6:4J specifiesexternal. When used for input, the selected
pin must be programmed as an inputinthePCR
[4:3J or [2:0J.
o
[6:4] Receiver Clock Select- This field selects the clock for the receiver.
000
External clock from TRxC or RTxC at
1X the shift (baud) rate.
001
External clock fromTRxC or RTxC at
16X the shift rate. Used for ASYNC
mode only.
010
Internal clock from the bit rate generator at 32X the shift rate. Clock is divided by two before used by the
receiver logic, which operates at 16X
the baud rate. Rate selected by [3:0J.
Used for ASYNC mode only.
011
Internal clock from counterltimer of
own channel. The CIT should be programmed to produce a clock at 32X
the shift rate. Clock is divided by two
before use in the receiver logic. Used
for ASYNC mode only.
100
Internal clock from the digital phaselocked loop. The clock for the OPLL
is a 64X clock from the crystal oscillator or system clock input. (The input
to the oscillator is divided by two).
101
Internal clock from the digital phaselocked loop. The clock for the DPLL is
an external32X clock from the RTxC
or TRxC pin, as selected by [7).
110
Internal clock from the digital phaselocked loop. The clock for the OPLL
is a 32X clock from the BRG. The frequency is programmed by [3:0J.
111
Internal clock from the digital phaselocked loop. The clock for the OPLL
is a 32X clock from the counterltimer
of the channel.
DCD not used to enabled receiver.
DCO used to enabled receiver.
EXT SYNC and OCD ENABLE Rx cannot be
asserted simultaneously since they use the
same pin.
[1 :0] Received Bits per Character This
field selects the number of data bits per character to be assembled by the receiver. The character length does not include the start, parity,
and stop bits in the ASYNC or the parity bit in
COP. In BOP modes, the character length for
the address and control field is always 8 bits,
and the value of this field only applies to the information field. If the number of bits assembled
for the last character of the I-field is less than
the value programmed in this field, RCL not
zero (RSR[O]) is asserted and the actual number of bits received is given in TRSR[2:0].
312
External input form RTxC pin.
External input form TRxC pin.
Don't recognize all parties address.
[2] DCD Enable Receiver - If this bit is asserted, the DCDN/SYNIN input must be Low in
order for the receiver to operate. If the input is
negated (goes High) while a character is being
received, the receiver terminates receipt of the
current message (this action in effect disables
the receiver). If OCO is subsequently asserted,
the receiver will search for the start bit, SYN
pattern, or FLAG, depending on the channel
protocol. (Note that the change of input can be
programmed to generate an interrupt; the duration of the OCD level change is described in the
discussion of the input and counterltimer status
register (CTSR[5]).
SCN68562
[3:0] Bit Rate Select- This field selects an
output from the bit rate generator to be used by
the receiver circuits. The actual frequency output from the BRG is 32X the bit rate shown in
Table 5.
Philips Components-Signetics Data Communication Products
Product Specification
Dual universal serial communications controller (DUSCC)
Output and Miscellaneous Register (aMRA, OMRB)
The RxRDY status bit will also be asserted, regardless 01 the receiver
FIFO lull condition, when an
end-ol-message character is loaded
in the RxFIFO (BOP/BISYNC), when
a BREAK condition (ASYNC mode) is
detected in RSR[2], or when the counter/timer is programmed to count received characters and the character
which causes it to reach zero is
loaded in the FIFO (all modes). (Refer to the Detailed Operation of the receiver.)
[7:5] Transmitted Residual Character
Length - In BOP modes, this field determines
the number of bits transmitted for the last character in the information field. This length applies to:
- The character in the transmit FIFO accompanied by the FIFOed TEOM command.
- The character loaded into the FIFO by the
DMA controller if DONEN is simultaneously
asserted and TPR[4} is asserted.
If reset by the CPU, the RxRDY status
bit will remain negated, regardless of
the current state of the receiver FIFO,
until it is asserted again due to one of
the above conditions.
- The character loaded into the FIFO which
causes the counter to reach zero count
when TPR[4] is asserted.
The length of all other characters in the frame's
information field is selected by TPR[l :0]. If this
field is Ill, the number of bits in the lastcharacter is the same as programmed in TPR[l :0].
[4] TxRDY Activate Mode-
o
FIFO not full. The channel's TxRDY
status bit is asserted each time a
character is transferred from the
transmit FIFO to the transmit shift register. If not reset by the CPU, TxRDY
remains asserted until the FIFO is full,
at which time it is automatically negated.
FIFO empty. The channel's TxRDY
status bit is asserted when a character transfer from the transmit FIFO to
the transmit shift register causes the
FIFO to become empty. If not reset
by the CPU, TxRDY remains asserted until the FIFO is full, at which
time it is negated.
If the TxRDY status bit is reset by the
CPU, it will remain negated regardless of the current state olthe transmit
FIFO, until it is asserted again due to
the occurrence of one of the above
conditions.
[3] RxRDY Activate Mode -
o
FIFO not empty.
The channel's
RxRDY status bit is asserted each
time a character is transferred Irom
the receive shiftregisterto the receive
FIFO. If not reset by the CPU, RxRDY
remains asserted until the receive
FIFO is empty, atwhich time it is automatically negated.
FIFO full. The channel's RxRDY status bit is asserted when a character
transfer from the receive shift register
to the receive FIFO causes the FIFO
to become full. If not reset by the
CPU, RxRDY ream ins asserted until
the FIFO is empty, at which time it is
negated.
October 30, t990
[2] General PurposeOutput2- This general
purpose bit is used to control the TxDRON/
GP02lRTSN pin, when it is used as an output.
The output is High when the bit is a 0 and is Low
when the bit is a 1.
[1] General Purpose Output 1 - This bit is
used to control the RTxDRON/GPOI N output,
which is a general purpose output when the
channel is not in DMA mode. The output is High
when the bit is a 0 and is Low when the bit is a
I.
[0] Request-to-Send Output- This bit controls the TxDRON/GP02N/RTSN and SYNOUTN/RTSN pin, when eitheris usedas aRTS
output. The output is High when the bit is a 0
and is Low when the bit is a 1.
Counter/Timer Control and Value
Registers
There are five registers in this set consisting of
the following:
o
3. Counter/timer (current value) High and
Low registers (CTHAlB, CTLA/B)
[6] Zero Detect Control- This bit determines
the action of the counter upon reaching zero
count.
o
[5] CounterlTimer Output Control- This bit
selects the output waveform when the counter/
timer is selected to be output on TRxC or RTxC.
The output is a single clock positive
width pulse each time the CIT reaches zero count. (The duration of this
pulse is one clock period.)
o
The output toggles each time the CIT
reaches zero count. The output is
cleared to Low by either of the preset
counter/timer commands.
[4:3] Clock Select- This field selects whether
the clock selected by [2 :0] is pre scaled prior to
being applied to the input of the CIT.
00
No prescaling.
01
Divide clock by 16.
10
Divide clock by 32.
11
Divide clock by 64.
[2:0] Clock Source - This field selects the
clock source for the counter/timer.
000
RTxC pin. Pin must be programmed
as input.
001
TRxC pin. Pin must be programmed
as input.
010
Source is the crystal oscillator or system clock input divided by four.
011
This selects a special mode of operation. In this mode the counter, after receiving the 'start CIT' command,
delays the start of counting until the
RxD input goes Low. It continues
counting until the RxD input goes
High, then stops and sets the CIT zero
count status bit. The CPU can use the
value in the CIT to determine the bit
rate of the incoming data. The clock
is the crystal oscillator or system clock
input divided by four.
100
Source is the 32X BRG output selected by RTR[3:0] of own channel.
101
Source is the 32X BRG output selected by TIR[3:0] of own channel.
Counter/Timer Control Register
(CTCRA/CTCRB)
313
The counter/timer is preset to the value contained in the counter/timer preset registers (CTPRL, CTPRH) at the
next clock edge.
The counter/timer continues counting
without preset. The value at the next
clock edge will be H'FFFF'.
The format of each 01 the registers of this set is
contained in Table 6. The control register contains the operational information for the counter/timer. The preset registers contain the
count which is loaded into thecounter/timercircuits. The third group contains the current value of the counter/timer as it operates.
[7] Zero Delect Interrupt - This bit determines whether the assertion of the CIT ZERO
COUNT status bit (ICTSR[6]) causes an interrupt to be generated.
Interrupt disabled.
Interrupt enabled if master interrupt
enabled (ICR[I] or ICR[O]) is asserted.
I. Counterltimer control register (CTCRAlB).
2. Counter/timer preset Highland Low registers (CTPRHAlB, CTPRLA/B).
SCN68562
/
Product Specification
Philips Components-Signetics Data Communication Products
SCN68562
Dual universal serial communications controller (DUSCC)
110
Table 6_
on zero count or done control bit
(TPR[4]) is asserted, the FIFOed
send EOM command will be automatically asserted when the character
which causes the count to go to zero
is loaded into the transmit FIFO.
causes the count to go to zero is
loaded into the receive FIFO.
Source is the internal signal which
loads received characters from the receive shift register into the receiver
FIFO. When operating in this mode,
the FIFOed EOM status bit (RSR[7])
shall be set when the character which
Source is the internal signal which
transfers characters from the data
bus into the transmit FIFO. When operating in this mode, and if the TEOM
111
CounterlTlmer Control and Value Register Bit Formats
COUNTERITIMER CONTROL REGISTER
BIT7
BITS
BIT S
Zero
Detect
Interrupt
Zero
Detect
Control
Output
Control
O-disable
I-enabled
O-preset
I-continue
(CTCRA,
CTCRB)
O-square
1 -pulse
BIT 4
I
BIT2
BIT 3
I
BITt
I
BITO
Clock Source
Prescaler
00-1
01-16
10-32
11-64
000 - RTxC pin
001 - TRxC pin
010 - XI/eLK divided by 4
011 - XI/eLK divided by 4 gated by RxD
l00-RxBRG
101 - Tx BRG
110- Rx characters
111 - Tx characters
COUNTERITIMER PRESET REGISTER HIGH
BIT7
I
BITS
(CTPRHA,
CTPRHB) ,
I
BITS
I
BIT4
I
BIT 3
1
I
BITt
I
BITO
I
BITt
I
BITO
BIT2
I
BITt
I
BITO
BIT 2
I
BITt
I
BITO
BIT2
Most significant bits of counter/timer preset value.
COUNTERITIMER PRESET REGISTER LOW
BIT7
(CTPRLA,
CTPRLB)
I
BITS
I
BITS
I
BIT4
I
BIT3
I
BIT2
Least significant bits of counter/timer preset value.
COUNTERITIMER REGISTER HIGH
BIT7
I
BITS
I
BITS
(CTHA,
CTHB)
I
BIT4
I
BIT3
I
Most significant bits of counter/timer.
COUNTERITIMER REGISTER LOW
BIT7
I
BIT6
(CTLA,
CTLB)
I
BITS
I
BIT4
I
BIT 3
I
Least significant bits of counter/timer.
CounterlTimer Preset High Register (CTPRHA, CTPRHB)
Counter/Timer Preset Low Register (CTPRLA, CTPRLB)
Counter/Timer High Register
(CTHA, CTHB)
[7:0] MSB - This regsiter contains the eight
most significant bits of the value loaded into the
counter/timer upon receipt of the load crr from
preset regsiter command or when the counter/
timer reaches zero count and the zero detect
control bit (CTCR[6]) is negated. The minimum
16-bit counter/timer preset value is H'0002'.
[7:0] LSB - This register contains the eight
least significant bits of the value loaded into the
counter/timer upon receipt of the load err from
preset register command or when the counter/
timer reaches zero count and the zero detect
control bit (eTCR[6]) is negated. The minimum
16-bit counter/timer preset value is H'0002'.
[7:0] MSB - A read of this 'register' provides
the eight most significant bits of the current value of the counterltimer. It is recommended that
the err be stopped via a stop counter command before it is read in order to prevent errors
which may occur due to the read being performed while the crr is changing. This count
may be continued after the register is read.
October SO, 1990
314
Product Specification
Philips Components-Signetics Data Communication Products
SCN68562
Dual universal serial communications controller (DUSCC)
Counter/Timer Low Register
(CTLA, CTLB)
5. Interrupt Vector Register (IVR) and Modified Interrupt Vector Register (lVRM).
[7:0] LSB - A read of this 'register' provides
the eight least significant bits of the current value of the counter/timer. It is recommended that
the CfT be stopped via a stop counter command before it is read, in order to prevent errors
which may occur due to the read being performed while the CIT is changing. This count
may be continued after the register is read.
Interrupt Control and Status Registers
This group of registers define mechanisms for
communications between the DUSCC and the
processor and contain the device status information. Four registers, available for each channel, and four common device registers
comprise this group which consists of the following:
3. Transmitter and Receiver Status Register
(TRSRAlB).
Interrupt generated if bits 7, 6, 5, 4 or
3 of the TRSR are asserted.
7. General status register (GSR)
See Table 7 for bit formats and Figure 3 for table
[4] RxRDY-
relationships.
o
Interrupt not enabled.
Interrupt Enable Register (IERA,
IERB)
This register controls whether the assertion of
bits in the channel's status registers causes an
interrupt to be generated. An additional condition for an interrupt to be generated is that the
channel's master interrupt enabled bit, ICR[O]
or ICR[I], be asserted.
Interrupt generated if RxRDY
(GSRIO] or GSR[4] for Channels A
and B, respectively) is asserted.
[3] RSR 76-
o
Interrupt not enabled.
Interrupt generated if bits 7 or 6 of the
RSR are asserted.
[7] DCD/CTS -
[2] RSR54-
o
o
Interrupt not enabled.
Interrupt not enabled.
Interrupt generated if bits 5 or 4 of the
RSR are asserted.
Interrupt generated if ICTSR[4] or
ICTSR[5] are asserted.
[6] TxRDY-
[1] RSR 32-
o
0
Interrupt not enabled.
Interrupt not enabled.
Interrupt generated if bits 3 or 2 of the
RSR are asserted.
~nterrupt
generated if TxRDY
(GSR[I] or GSR[5] for Channels A
and B, respectively) is asserted.
4. Input and CoutnerfTimer Status Register
(ICTSRAlB).
Table 7.
Interrupt not enabled.
6. Interrupt control register (lCR).
I. Interrupt Enable Register (IERAlB).
2. Receiver Status Register (RSRAlB).
[5] TRSR73-
o
Interrupt Control and Status Register Bit Format
RECEIVER STATUS REGISTER
'BIT 7
BfT6
BIT5
BIT4
BIT3
BIT2
BfTl
BITO
(RSRA, RSRB)
ASYNC
# Char
compare
RTS
negated
Overrun
error
not
used
BRKend
detect
BRK start
detect
# Framing
error
# Parity
error
COP
#EOM
detect +
PAD
error +
Overrun
error
not
used
not
used
Syn
detect
#CRC
error
# Parity
error
BOP
#EOM
detect
Abort
detect
Overrun
error
Short
frame detect
Idle
detect
Flag
detect
#CRC
error
# RCLnot
zero
LOOP
#EOM
detect
Abort/EOP
detect
Overrun
error
Short
frame detect
Turn-around
detect
Flag
detect
#CRC
error
# RCL not
zero
NOTES:
# Status bit is FIFOed.
+ COP BISYNC mode only
• All modes indicate charaeter count complete.
TRANSMITTER AND RECEIVER STATUS REGISTER
BIT 7
BIT6
BIT5
BIT4
81T3
BIT 2
BIT I
BITO
(TRSRA, TRSRB)
ASYNC
Transmitter
empty
CTS
underrun
not
used
Send
break ack
DPLL
error
not
used
not
used
not
used
COP
Transmitter
empty
CTS
underrun
Frame
complete
SendSOM
ack
DPLL
error
not
used
Rx hunt
mode
Rx xpnt
mode
Rx Residual Character Length
CTS
underrun
BOP
Transmitter
empty
Loop
sending'
Frame
complete
Send SOM!
abortack
NOTE:
• Loop mode only.
October 30, 1990
315
DPLL
error
000-0 bit
001 - I bits
DID - 2 bits
011-3bits
100-4bits
101-5bits
110-6bits
111-7bits
Product Specification
Philips Gomponents--Signetics Data Communication Products
SCN68562
Dual universal serial communications controller (DUSCC)
Table 7.
Interrupt Control and Status Register Bit Format (Continued)
INPUT AND GOUNTERITIMER STATUS REGISTER
(ICTSRA,
ICTSRB)
BIT7
BIT 6
BITS
BIT4
BIT3
BIT2
BITl
BIT 0
CIT
CIT zero
running
count
Delta
DCD
Delta
CTSILC
DCD
CTS/LC
GPI2
GPl1
INTERRUPT ENABLE REGISTER
(I ERA, IERB)
BIT 7
BIT6
BITS
BIT4
BIT3
BIT2
BIT 1
BITO
DCD/CTS
TxRDY
TRSR [7:3]
RxRDY
RSR[7:6]
RSR [S:4]
RSR [3:2]
RSR [1:0]
O-no
1-yes
O-no
1-yes
O-no
1-yes
O-no
1-yes
O-no
1-yes
O-no
1-yes
O-no
1-yes
O-no
1-yes
(IVR,IVRM)
GENERAL STATUS REGISTER
BIT7
I
BIT6
(GSR)
I
BIT S
I
BIT4
BIT3
I
BIT2
Channel B
External
or CIT
Status
I
RxlTx
status
I
I
BITl
I
BIT 0
I
RxRDY
Channel A
TxRDY
I
RxRDY
BITS
I
BIT 4
External
orC/T
status
I
RxlTx
status
I
TxRDY
INTERRUPT CONTROL REGISTER
BIT7
(ICR)
I
BIT 6
Channel AlB
Interrupt Priority
00 - Channel A
01 - Channel S
10- interleaved A
11 - interleaved B
[0] RSR 10-
o
Interrupt not enabled.
Interrupt generated if bits 1 orOofthe
RSR are asserted.
Receiver Status Register (RSRA,
RSRB)
This register informs the CPU of receiver status. Bits indicated as 'not used' in a particular
mode will read as zero. The logical OR of these
bits is presented in GSR(2) or GSR[6) (ORed
with the bits of TRSR) for Channels A and S, re-
October 30. 1990
BIT3
BIT2
BITl
BITO
Vector Mode
Bits to
Modify
Vector
Includes
Status
Channel A
Master Int
Enable
ChannelB
Master Int
Enable
00 - vectored
01 - vectored
10- vectored
11 - non vectored
0-2:0
1-4:2
spectively. Unless otherwise indicated, asserted status bits are reset only be performing
a write operation to the status register with the
bits to be reset being ones in the accompanying
data word, or when the RESETN input is asserted, or when a 'reset receiver' command is
issued.
Certain status bits are specified as being FIFOed. This means that they occupy positions
in a status FIFO that correspond to the data
FIFO. As the data is brought to the top of the
FIFO (the position read when the RxFIFO is
316
O-no
1-yes
O-no
1-yes
O-no
1-yes
read), the FIFOed status bits are logically
ORed with the previous contents of the corresponding bits in the status register. This permits the user to obtain status either character
by character or on a block basis. For character
by character status, the SR bits should be read
and then cleared before reading the character
data from RxFIFO. For block status, the status
register is initially cleared and then read after
the message is received. Asserted status bits
can be programmed to generate an interrupt
(see Interrupt Enable Register).
Product Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller (DUSCC)
[7] Character Count Complete (All Modes),
until it is empty and determine if any
valid characters from a previous
frame are in the FIFO. IIno character
with a tagged EOM detect ([7]) is
found, all characters are from the current frame and should be discarded
along with any previously read by the
CPU. An ABORT detect causes the
receiver to automatically go into
search for FLAG state. An abort during a valid frame does not cause the
CRC to reset; this will occur when the
next frame begins.
Character compare (ASYNC), EOM (BISYNC/BOP/LOOP) - If the counterltimer is
programmed to count received characters, this
bit is asserted when the character which
causes the count to go to zero is loaded into the
receive FI FO. It is also asserted to indicate the
following conditions:
ASYNC The character currently at the top of
RxFIFO matched the contents of
SlR. A character will not compare if
it is received with parity error even if
the data portion matches.
LOOP
BISYNC The character currently at the top of
the FIFO was either a text message
terminator or a control sequence re-
ceived outside of a text or header
field. See Detailed Operation of COP
Receiver. If transfer FCS to FIFO
(RPR[6]) is set, the EOM will instead
be tagged onto the last byte of the
FCS. Note that if an overrun occurs
during receipt of a message, the EOM
character may be lost, but this status
bitwill still be asserted to indicate that
an EOM was received. For 2 byte
EOM comparisons, only the second
byte is tagged (assuming the CRC is
not transferred to the FIFO).
BOP,
LOOP
The character currently at the top
of the FIFO was the last character of
the frame. If trnasfer FCS to FIFO
(RPR[6]) is asserted, the EOM will be
tagged instead onto the last byte of
the FCS. Note that if an overrun occurs, the EOM character may be lost,
but this status bit will still be asserted
to indicate that an EOM was received.
This bit will not be set when an abort
is received.
Performs the ABORT detect function
as described for BOP without the restriction that the pattern be detected
during an active frame. A zero followed by seven ones is the
end-of-poll sequence which allows
the transmitter to go active if the 'go
active on poll' command has been invoked.
[5] Overrun Error (All Modes) - A new character was received while the receive FIFO was
full and a character was already waiting in the
receive shift register to be transferred to the
FIFO. the DUSCC protects the five characters
previously assembled (four in RxFIFO, one in
the Rx shift register) and discards the overrunning character(s). After the CPU reads the
FIFO, the character waiting in the RxSR will be
loaded into the available FIFO position. This releases the RxSR and a new character assembly will start at the next character boundary. In
this way, only valid characters will be assembled, i.e., no partial character assembly will
occur regardless of when the RxSR became
available during the incoming data stream.
[4] Short Frame (BOP/LooP)-
[6] RTS Negated (ASYNC), PAD Error (BISYNC), ABORT (BOP)-
ASYNC Not used
COP
Not used
ASYNC The RTSN output was negated due to
receiving the start bitof a new character while the RxFIFO was full (see
RPR[4]).
BOP,
LOOP
A closing flag was received with
missing fields in the frame. See detailed operation for BOP receiver.
BISYNC PAD error detected (see RPR[5]).
LOOP An ABORT sequence consisting of a
zero followed by seven ones was received after receiptof the first address
octet but before receipt of the closing
FLAG. The user should read RxFIFO
[3] BREAK End Detect (ASYNC), IDLE
(BOP), Turnaround (LOOP)-
October 30, 1990
ASYNC 1X clock mode: The RxD input has returned to the marking state for at least
one period of the 1X receiver clock after detecting a BREAK.
317
SCN68562
16X clock mode: The RxD input has
returned to the marking (High) state
lor a least one-half bit time after detecting a BREAK. A half-bitlime is defined as eight clock cycles of the t 6X
receiver clock.
COP
Not used.
BOP
An IDLE sequence conSisting of a
zero followed by fifteen ones was received. During a valid frame, an abort
must precede an idle. However, outside of a valid frame, an idle is recognized and abort is no!.
LOOP
A turnaround sequence consisting of
eight contiguous zeros was detected
outside of an active frame. This
should normally be used to terminate
transmitter operation and return the
system to the 'echoing RxD' mode.
[2] BREAK Start Detect (ASYNC), SYN Detect (COP), FLAG Detect (BOP/LOOP)ASYNC An all zero character, including parity
(if specified) and first stop bit, was received. The receiver shall be capable
of detecting breaks which begin in the
middle of a previous character. Only
a single all-zero character shall be put
into the FIFO when a break is detected. Additional entries to the FIFO
are inhibited until the end of break has
been detected (see above) and a new
character is received.
COP
A SYN pattern was received. Refer
to Detailed Operation for definition of
SYN patterns. Set one bit time after
detection of SYN pattern in HSRH,
HSRL. See Figure 1 for receiver data
path.
BOP,
LOOP
A FLAG frequency (01111110) was
received. Set one bit time after FLAG
is detected in CCSR. See Figure 1 for
receiver data path.
[1] Framing Error (ASYNC), CRC Error
(COP/BOP/LOOP) ASYNC At the first stop bit position the RxD input was in the Low (space) state. The
receiver only checks for framing error
at the nominal center of the first stop
bit regardless of the number of stop
bits programmed in TPR[7:4]. This bit
is not set for BREAKS.
Philips Components-$ignetics Data Communication Products
Product Specification
Dual universal serial communications controller (DUSCC)
COP-SINGLE SYN.
OUAlSYN,
I
I
rr"'''''T""T~~''''''''''T""T"'T""'1 BlSYN
I
RxD
r=:==:-1INTERNAL I
RxD(NRZ}
INTERNAL TxD
L.........,.......-'
1x RCVRCLCK
SCN68562
[FLAGDETECT]
--1-~ II p§S~ I I I
I
l~
~
::
I~
Y ...
~ ... hmslll
~~s~111
1
::1
;HSS*RR:L: :
BOP WITHOUT CRC
~ (ZERO DELETE)
I
I
I
I
I
I...I.........................J...J BOP WITH CRC
f-r I[stliOJ]
~ II ~t~111
~I~';III
ASYNC
Figure 1. Receiver Data Path
COP
In BISYNC COP mode. this bit is set
upon receipt of the BCC byte(s). if
any. to indicate that the received BCC
was in error. The bit is normally FIFOed with the last byte of the frame
(the character preceding the first BCC
byte). However. if transfer FCS to
FIFO (RPR[6]) is asserted. this bit is
FIFOed with the last BCC byte. The
value of this bit should be ignored for
non-test messages or if the received
frame was aborted via an ENQ. In
non-BISYNC COP modes. the bit is
set with each received character ifthe
current value of the CRC checker is
not equal to the non-error value (see
CMR2[2:0]).
October 30, 1990
BOP.
LOOP
This bit is set upon receipt of the
FCS byte(s). if any. to indicatethatthe
received FCS was in error. The bit is
normally FIFOed with the last byte of
the I field (the character preceding the
first FCS byte). However, if transfer
FCS to FIFO (RPR[6]) is asserted,
this bit is FIFOed with the last FCS
byte.
[0) Parity Error (ASYNC/COP). RCL Not Zero
(BOP/LOOP) ASYNC The parity bit of the received characterwas notas expected. A parity error
does not affect the parity bit put into
318
the FIFO as part of the character
when strip parity (RPR[3]) is negated.
COP
The parity bit of the received characterwas not as expected. A parity error
does not affect the parity bit put into
the FIFO as part of the character
when strip parity (RPR[3]) is negated.
A SYN or other character received
with parity error is treated as a data
character. Thus, a SYN with parity error received while in SYN search state
will not establish character sync.
Characters received with parity error
while in the SYN search state will not
set the error bit.
Philips Components-Signetics Data Communication Products
Product Specification
Dual universal serial communications controller (DUSCC)
BOP,
LOOP
The last character of the I field did not
have the character length specified in
RPR[I :0]. The actual received character length of this byte can be read in
TRSR[2:0]. This bit is FIFOed with
the EOM character but TRSR[2:0] is
not. An exception occurs if the command to transfer the FCS to the FIFO
isactive. Inthiscase, the bit will be FIFOed with the last byte of the FCS,
i.e., with REOM. In the event that residual characters from two consecutive frames are received and are both
in the FI FO, the length in TRSR[2:0]
applies to the last received residual
character.
[6) CTS Underrun (ASYNC/COP/BOP), Loop
sending (LOOP)ASYNC, This bit is set only if CTS enable Tx
COP,
(TPR[2]) is asserted. It indicates
BOP
that the transmit shift register was
ready to begin serializing a character
and found the CTSN input negated.
In ASYNC mode, this bit will be reasserted if cleared by the CPU while the
CTSN input is negated.
LOOP
Transmitter/Receiver Status
Register (TRSRA, TRSRB)
This register informs the CPU of transmitter
and receiver status. Bits indicated as not used
in a paritcular mode will read as zero, except for
bits [2:0], which may not be zero. The logical-OR of bits [7:3] is presented in GSR[2] or
GSR[6] (ORed with the bits of RSR) for channels A and B, respectively. Unless otherwise indicated, asserted status bits are reset only:
t. By performing a write operation to the status register with the bits to be reset being
ones in the accompanying data word
[7:3].
2. When the RESETN input is asserted.
3. For [7:4], when a 'reset transmitter' command is issued.
4. For [3:0], when a 'reset receiver' command is issued.
5. For [2:0], see description in BOP mode.
Asserted status bits in [7:3] can be programmed to generate an interrupt. See IER.
[7] Transmitter Empty - Indicates that the
transmit shift register has completed serializing
a character and found no other character to serialize in the TxFIFO. The bit is not set until at
least one character from the transmit FIFO (not
including PAD characters in synchronous
modes) has been serialized. The transmitter
action after transmitter empty depends on operating mode:
ASYNC The TxD output is held in the MARK
state until another character is loaded
into the TxFIFO. Normal operation
then continues.
COP
Action is specified by TPR[7:6].
BOP,
LOOP
Action is specified by TPR[7:6].
October 30, 1990
ASYNC Not used.
COP
BOP
COP
Set when the transmitter begins
transmission of a SYN pattern in response to the TSOM or TSOMP command. If the command is reinvoked,
the bit will be set again at the beginning of the next transmitted SYN pattern. The user can control the number
of SYNs which are sent through this
mechanism.
BOP
Set when the transmitter begins
transmission of a FLAG/ABORT in response to the TSOM or TSOMP or
TABRK command. If the command is
reinvoked, the bit will be set again at
the beginning of the next transmitted
FLAG/ABORT. The user can control
the numberof FLAGs/ABORTs which
are sent through this mechanism.
Asserted when the go active on poll
command has been invoked and an
EOP sequence has been invoked and
an EOP sequence has been detected, causing the transmitter to go
active by changing the EOP to a
FLAG (see Detailed Operation of
transmitter).
[5) Frame Complete (COP/BOP)-
Assertedatthe beginning oftransmission of the end of message sequence
invoked by which is either a TEOM
command, or when TPR[4] = I, or
TPR[7:6] = 00. The CPU can invoke
the TSOM command after this bit is
set to control the number of SYNs between transmitted frames.
Assertedatthe beginning oftransmission of the end of message sequence
which is invoked by either a TEOM
command, or when TPR[4] = I, or
TPR[7:6] = 00. The CPU can invoke
the TSOM command after this bit is
set to control the number of FLAGs
between transmitted frames.
In COP/BOP modes, the frame complete status bit is set during the
next-to-Iast bit (on TxD pin) of the last
characterin the data/information field.
In BOP mode, if a I-bit residual character is selected through OMR[7:5],
then this bit is set during the
next-to-Iast bit (on TxD pin) of the last
full length character olthe information
field.
[3) DPLL Error-SetwhiletheDPLLisoperating in FM mode to indicate that a data transition
was not detected within the detection window
for two consecutive bits and that the DPLL was
forced into search mode. This feature is disabled when the DPLL is specified as the clock
source for the transmitter via TIR[6:4].
[2:0) Received Residual Character Length
(BOP)BOP
319
This field should be examined to determine the length of the last characterofthe I field (charactertaggedwith
REOM status bit) if RSR[O] is set to indicate that the length was not equal to
the character length specified in
RPR[I :0]. This field is negated when
a reset receiver or disabled receiver
command is issued, or when the first
control character for the next frame of
data is in HSRL (see Figure I). Care
must be taken to read TRSR[2:0] before these bits are cleared.
[I) Receiver in Hunt Mode (COP)COP
[4] Send Break Ack (ASYNC)/Send SaM
ACK (COP)/Send SOM·Aborl Ack (BOP ASYNC Set when the transmitter begins
transmission of a break in response to
the send break command. If the command is reinvoked, the bit will be set
again at the beginning of the next
character time. The user can control
the length of the break by counting
character times through this mechanism.
SCN68562
This bit is asserted after the receiver
is reset or disabled. It indicates that
the receiver is in the hunt mode,
searching the data stream for a SYN
sequence to establish character synchronization, The bit is negated automatically when character sync is
achieved.
[0) Receiver in Transparent Mode (BISYNC)
COP
Indicates that a DLE-STX sequence
was received and the receiver is operating in BISYNC transparent mode.
Set two bit times after detection of
STX in HSRL. See Figure I for receiver data path. Transparent mode
Product Specification
· Philips Components--$ignetics Data Communication Products
SCN68562
Dual universal serial communications controller (DUSCC)
operation is terminated and the bit is
negated automatically when one of
the terminators for transparent text
mode is received (DlE-ETXlETBI
ITBlENO).
Input and Counter/Timer Status
Register (ICTSRA, ICTSRB)
This register informs the CPU of status of the
counterllimer and inputs. The logical-OR of
bits [S:4] is presented in GSR[3] or GSR[?] for
Channels A and B, respectively. Unless otherwise specified, bits of this register are reset
only:
1. By performing a write operation to the status register with the bits to be reset (ones
in the accompanying data word for bits
[S :4] only).
2. When the RESETN input is asserted (bits
[7:4]) only.
[7] CounterlTImlng Running - Set when the
CIT is started by start CIT command and reset
when it is stopped by a stop CIT command.
[6] CounterlTlmer Zero Detect - Set when
the counterllimer reaches zero count, or when
the bit length measurement is enabled (CTCR
[2:0] = all) and the RxD input has returned
High. The assertion of this bit causes an interrupt to be generated if ICTCR[?] and the channel's master interrupt enable (ICR[ 1] or ICR[O])
are asserted.
[5] DellaDCD- The DCDinputis sampledapproximately every S.8~s using the 32X, 4800
baud output from the BRG. After synchronizing
with the sampling clock, at least two consecutive samples at the same level are required to
establish the level. As a consequence, a
change of state at the DCD input, lasting at
least 1?~s, will set this bit. The reset circuitry
initializes the sampling circuits so that a change
is not falsely indicated at power on time. The
assertion of this bit causes an interrupt to be
generated if IER[?] and the channel's master interrupt enable (ICR[1 Jor ICR[O]) are asserted.
[4J Della CTSllC - When not in loop mode,
the CTS input is sampled approximately every
6.8~s using the 32X, 4800 baud outpulforrn the
BRG. After synchronizing with the sampling
clock, at least two consecutive samples at the
same level are required to establish the level.
As a consequenc;e, a change of state at the
CTS input, lasting atleast17~, will seith is bit.
The reset circuitry initializes the sampling circuits so that a change is not falsely indicated at
power on time. The assertion of this bit causes
an interrupt to be generated if IER[?] and the
channel's master interrupt enable (ICR[IJ or
ICR[O]) are asserted.
October 30, 1990
In SDlC loop mode, this bit is set upon transitions of the lC output. lC is asserted in response to the 'go on-loop' command when the
receiver detects azerofollowed by seven ones,
and negated in response to the 'go off-loop'
command when the receiver detects a sequence of eight ones.
[3:2J State of DCD and CTS -ICTSRx[3J reflects the state of the DCDxN input pin, while
ICTSRx[2] reflects the state of CTSxN. When
the bits are 0, the inputs are High, when they
are 1, the pins are Low.
[1:0J Current State of GPI2 and GPII These fields provide the current state of the
channels general purpose input pins. The bits
valve are latched at the beginning of the read
cycle.
Interrupt Vector Register (IVR)
and Modified Vector Register
(IVRM)
[7:0] Register Content - If ICR[2J = 0, the
content of IVR register is output on the data bus
when the DUSCC has issued an interrupt request and the responding interrupt acknowledge (IACKN) is received. The value in the IVR
is initialized to H'OF' on master reset. If 'vector
includes status' is specified by ICR[2J = I, bit
[2:0) or [4:2J (depending on ICR[3]), of the vector are modified as shown in Table 9 to indicate
the highest priority interrupt currently active.
The priority is programmable through the ICA.
This modified vector is stored in the IVRM.
When ICR[2J= I, thecontentofthelVRMisoutput on to the data bus on the interrupt acknowledge. The vector is not modified, regardless of
the value of ICR[2J, if the CPU has not written
an initial vector into this register.
Either the modified or unmodified vector can
also be read by the CPU via a normal bus read
cycle (see Table 1). The vector value is locked
at the beginning of the lACK or read cycle until
the cycle is completed. If no interrupt is pending, an H'FF' is output when reading the IVRM
or the IVR.
Interrupt Control Register (ICR)
[7:6J Channel AlB Interrupt Priority Selects the relative priority between Channels
A and B. The state of this bit determines the value of the interrupt vector (see Interrupt Vector
Register). The priority within each channel,
from highest to lowest, is as follows:
320
o
Receiver ready.
1
Transmitter ready
2
RxlTx status.
3
External or CIT status.
00
Channel A has the highest priority.
The DUSCC interrupt priorities from
highest to lowest are as follows: A(O),
A( 1), A(2), A(3), B(O), 8(1), 8(2), 8(3).
01
Channel 8 has the highest priority.
the DUSCC interrupt priorities from
highest to lowest are as follows: 8(0),
8(1),8(2),8(3), A(O), A(I), A(2), A(3).
10
Priorities are interleaved between
channels, but Channel A has the highest priority between events of equal
channel priority. The DUSCC interrupt priorities from highest to lowest
are as follows: A(O), 8(0), A(1), 8(1),
A(2), 8(2), A(3), 8(3)
11
Priorities are interleaved between
channels, but Channel 8 has the highest priority between events of equal
channel priority. The DUSCC interrupt priorities from highest to lowest
are as follows: 8(0), A(O), 8(1), A(I),
8(2), A(2), 8(3), A(3).
Table 8,
IVRM
[2:0]1
[4:2J
000
001
010
011
100
101
110
111
Interrupt Status
Encoding
HIGHEST PRIORITY
INTERRUPT CONDITION
Channel A receiver ready
Channel A transmitter ready
Channel A RxlTx status
Channel A external or CIT status
Channel 8 receiver ready
Channel 8 transmitter ready
Channel 8 RxlTx status
Channel 8 external or CIT status
[5 :4] Vector Mode - The value of this field determines the response of the DUSCC when the
interrupt acknowledge (IACKN) is received
from the CPU.
00
or
01
or
10
Vectored mode. Upon interrupt
acknowledge, the DUSCC locks its
current interrupt status until the end
of the acknowledge cycle. If it has an
active interrupt pending, it responds
with the appropriate vector and then
asserts DTACKN. If it does not have
Product Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller (DUSCC)
an interrupt, it propagates the acknowledge through its X2IIDCN output if this function is programmed in
PCRA[7]. Otherwise, the IACKN is ignored. Locking the interrupt status at
the leading edge of IACKN prevents
a device at High position in the interrupt daisy chain from responding to
an lACK issued for a lower priority device while the acknowledge is being
propagated to that device.
11
Non-vectored mode. The DUSCC ignores an lACK if one is received; the
interrupt vector is not placed on the
data bus. The internal interrupt status
is locked when a read of the IVR or
IVRM is performed. Except forthe absence of the vector on the bus, the
DUSCC performs as it does in vectored mode - the vector is prioritized
and modified if programmed.
[3) Vector 8its to Modify - Selects which bits
of the vector stored in the IVR are to be modified
to indicate the highest priority interrupt pending
in the DUSCC. See Interrupt Vector Register.
a
Modify bits 2:0 of the vector.
Modify bits 4:2 of the vector.
(2) Vector fncludes Status - Selects whether the modified (includes status) (IVRM) or unmodified vector (IVR) is output in response to
an interrupt acknowledge (see Interrupt Vector
Register).
a
Unmodified vector.
Modified vector.
[1) Channel A Master Interrupt Enable-
a
Channel A interrupts are disabled.
Channel A interrupts are enabled.
(0) Channel 8 Master Interrupt Enable -
a
Channel B interrupts are disabled.
Channel B interrupts are enabled.
General Status Register (GSR)
This register provides a 'quick look' althe overall status of both channels of the DUSCC. A
write to this register with 1s at the corresponding bit positions causes TxRDY (bits 5 and 1)
and/or RxRDY (bits 4 and 0) to be reset. The
other status bits can be reset only by resetting
the individual status bits that they point to.
(7) Channel 8 Externaf or Coutnermmer
Status - This bit indicates that one of the following status bits is asserted: ICTSRB[6:4].
October 30, 1990
state. Also clears the transmitter status bits (TRSR[7:4]) and resets the
TxRDY status bit (GSR[l) or GSR[5]
for Channels A and B, respectively).
The counterltimer and other registers
are not affected.
(6) Channel 8 Receiver or Transmitter
Status - This bit indicates that one of the following status bits is asserted: RSRB[7:»),
TRSRB[7:3].
(5) Channel 8 Transmitter Ready - The assertion of this bit indicates that one or more
characters may be loaded into the Channel B
transmitter FIFO to be serialized by the transmit
shift register. See description of OMR[4]. This
bit can be asserted only when the transmitter is
enabled. Disabling or resetting the transmitter
negates TxRDY.
[4] Channel 8 Receiver Ready - The assertion of this bit indicates that one or more characters are available in the Channel B receiver
FIFO to be read by the CPU. See description
of OMR[3J. RxRDY is initially reset (negated)
by a chip reset or when a 'reset Channel B receiver' command is invoked.
0001
ResesttransmitCRC. Thiscommand
is appended to and FIFOed along with
the next character loaded into the
transmit FIFO. It causes the transmitterCRC generator to be reset to its initial
state prior to beginning
transm ission of the appended character.
0010
Enabletransmitter. Enables transmitter operation , conditioned by the state
of the CTS ENABLE Tx bit, TPR[2J.
Has no effect if invoked when the
transmitter has previously been enabled.
0011
Disable transmitter. Terminates transmitter operation and places the TxD
output in the marking state at the next
occurrence of a transmit FIFO empty
condition. All characters currently in
the FI FO, or any loaded subsequently
prior to attaining an empty condition,
will be transmitted.
0100
Transmit start of message. Used in
COP and BOP modes to initiate transmission of a frame after the transmitter is first enabled, prior to sending the
contents of the FIFO. Can also be
used to precisely control the number
of SYN/FLAGs at the beginning of
transmission or in between frames.
[3) Channel A External or CounterrTimer
Status - This bit indicates that one of the following status bits is asserted: ICTSRA[6:4].
(2) Channel A Receiver or Transmitter Status- This bit indicates that one of the following
is
asserted:
RSRA[7:0],
status
bits
TRSRA[7:3].
[1) Channel A Transmitter Ready - The assertion of this bit indicates that one or more
characters may be loaded into the Channel A
transmitter FI FO to be serialized by the transmit
shift register. See description of OMR[4J. This
bit can be asserted only when the transmitter is
enabled. Disabling or resetting the transmitter
negates TxRDY.
[0] Channel A Receiver Ready - The assertion of this bit indicates that one or more characters are available in the Channel A receiver
FIFO to be read by the CPU. See description
of OMR[3J. RxRDY is initially reset (negated)
by a chip reset or when a 'reset Channel A receiver' command is invoked.
Channel
Command Register (CCRA,
CCRB) - Commands to the DUSCC are entered through the channel command register.
The format of that register is shown in Table 9.
A read of this register returns the last invoked
command (with bits 4 and 5 set to 1).
Transmitter Commands
0000
Reset transmitter. Causes the transmitter to cease operation immediately. The transmit FI FO is cleared and
the TxD output goes into the marking
321
SCN68562
When the transmitter is first enabled,
transmission will not begin untill this
command (or the transmit SOM with
PAD command, see below) is issued.
The command causes the SYN
(COP) or FLAG (BOP) pattern to be
SEND SOM ACK
transmitted.
(TRSR[4]) is set when transmission of
the SYN/FLAG begins. The CPU
may then reinvoke the command if
multiple SYN/FLAGs are to be transmitted. Transmission of the FIFO
characters begin when the command
is no longer invoked. If the FI FO is
empty, SYN/FLAGs continue to be
transmitted until a character is loaded
into the FIFO, but the status bit
(TRSR[4]) is not set. Insertion of
SYN/FLAGs between frames can be
accomplished by invoking this command afterthe frame complete status
bit (TRSR[5]) has been asserted in re-
Product Specification
Philips Compsnent&-Signetics Data Communication Products
Dual universal serial communications controller (DUSCC)
sponse to transmission of the end~f
message sequence.
0101
Transmit start of message with opsning PAD. Used in COP and BOP
modes after the transmitter is first enabled to send a bit pattern for DPLL
synchronization prior to transmitting
the opening SYN (COP) or FLAG
(BOP). the SYN/FLAG is sent at the
next occurrence of a transmit FIFO
empty condition. All characters currently in the FIFO, or any loaded subsequently prior to attaining an empty
condition, will be transmitted. While
the PAD characters are transmitted,
the character length is set to 8 bits,
(regardless of the programmed
length), and parity generation (COP),
zero insertion (BOP) and LRC/CRC
accumulation are disabled. SEND
SOM ACK (TRSR[4]) is set when
transmission of the SYN/FLAG bagins. The CPU may then invoke the
transmit SOM command if multiple
SYN/FLAGs are to be transmitted.
be repeated. This can be used to
send the idle sequence. The 'transmit
SOM' command must be used to initiate transmission of a new message.
In either mode, invoking this command causes the transmit FIFO to be
flushed (characters are not transmitted).
In ASYNC mode, causes a break
(spaee) to be tr!lnsmitted after transmission of the character currently in
the shift register is completed. Send
break ack (TRSR[4]) is set when the
transmission olthe break begins. The
transmitter keeps track of character
times. If the command is reasserted,
send break ack will be set again at the
beginning of the next character time.
The user can use this mechanism to
control the length of the break in character time multiples. Transmission of
the break is terminated by issuing a
'reset Tx' or 'disableTx' command.
1000
The TSOMITSOMP commands, dascribed above, are sampled by the
controller in alternate bit times of the
transmitter clock. As a consequence,
the first bit time of a COP/BOP frame
will be transmitted on the TxD pin, after a maximum of three bit times, after
the command is issued. (The additional 1-bit delay in the data path is
due to the data encoding logic.)
0110
0111
Transmitend-of-message. This command is appended to the nextcharacter loaded into the transmit FIFO. It
causes the transmitter to send the
end-of message sequence (selected
FCS in COP modes, FCS-FLAG in
BOP modes) after the appended
character is transmitted. Frame complete (TRSR[5]) is set when transmission of the FCS begins.
This
command is also asserted automatically ilthe TEOM on zero count or one
control bit (TPR[4]) is asserted, and
the counter/timer is programmed to
count transmitted characters when
the character which causes the count
togo to zero is loaded into the transmit
FIFO. TEOM is not recognized if the
transmitter FIFO is full.
Transmit Abort BOPlTransmit Break
ASYNC. In BOP modes, causes an
abort (eight ones) to be transmitted
after transmission of the character
currently in the shift register is completed. The transmitter then sends
MARKs or FLAGs depending on the
state of underrun control (TPR[7:S]).
Send SOMiabort ack (TRSR[4]) is set
when the transmission of the abort
begins. If the command is reasserted
before transmission of the previous
ABORT is completed, the process will
October 30, 1990
1001
Transmit DLE. Used in COP modes
only. This command is appended to
and FIFOed with the next character
loaded into the transmitter FIFO. It
causes the transmitterto send a OLE,
(EBCDIC H'10', ASCII H'10') prior to
transmitting the appended character.
If the transmitter is operating in BISYNC transparent mode, the transmitter control logic automatically
causes a second DLE to be transmitted whenever a DLE is detected at
the top of the FIFO. tn this case, the
TOLE command should not be invoked. An exIra (third) OLE, however,
will not be sent if the transmit DLE
command is invoked.
Go active on poll. Used in BOP loop
mode only. Causes the transmitter, if
it is enabled, to begin sending when
an EOP sequence consisting of a
zero followed by seven ones is detected. The last one of the EOP is
changed to zero, making it another
FLAG, and then the transmitter operates as described in the detailed operation section. The loop sending
status bit (TRSR[S]) is asserted concurrent with the beginning of transmission.
1010
Reset go active on poll. Clears the
stored 'go active on poll' command.
1011
Go on-loop. Used in BOP loop mode
to control the assertion of the LCN
output. This output provides the
means 01 controlling external loop interface hardware to go on-loop and
off-loop. When the command is asserted, the DUSCC will look for the receipt of a zero followed by seven
ones, at which time it will assert the
LCN output and selthe delta DCD/LC
status "'it (ICTSR[4]). This allows the
322
SCN68562
OUSCC te break into the loop without
affecting loop operation. This command must be used to initiate loop
mode operation.
1100
Go oil-loop. Used in BOP loop mode
to control the negation of the LCN output. This output provides the means
of controlling external loop interface
hardware to go on-loop and off-loop.
When the command is asserted, the
DUSCcwililooklorthereceiptofeight
contiguous ones, at which time it will
negate the LCN output and set the
delta OCOILC status bit (ICTSR[4]).
This allows the OUSCC to get off the
loop operation. This£ommandisnormally used to terminate loop mode
operation.
1101
Exclude from CRC. This command is
appended to and FIFOed along w;th
the next character loaded into the
transmit FIFO. It causes the transmitter CRC generator to be disabled
while the appended character is baing
transmitted. Thus, that character is
not included in the CRC aCGumulation.
Receiver Commands
0000
Reset Re<;:eiver. Causes the receiver
to cease operation, clears the receiver FIFO, clears the data path, and
clears the receiver status (RSR[7:0j,
TRSR[3:0j, and either GSR[Oj or
GSR[4j for Channels A and B, respectively). The counter/timer and other
registers are not affected.
0001
Reserved.
0010
Enable receiver. Causesreceiveroperation to begin, conditioned by the
state of the OCO ENABlED Rx bit,
RPR[2j. Receiver goes inlo START,
SYN, or FLAG search mode depending on channel protocol mode. Has no
effect il invoked when the receiver
has previously been enabled.
0011
Disable receiver. Terminates operalion of the receiver. Any character
currently being assembledwill be lost.
Does not affect FIFO or any status.
While in COP mode, disabling the receiver does not clear the data path; in
all other cases, it does.
Counter/Timer Commands
0000
Start. Starts the oounterltimer and
prescaler.
0001
Stop. Stops the counter/timer and
prescaler. Since the command may
be asynchronous with the selected
clock source, !he counter/timer and!
or prescaler may count one or more
additional cycles before stepping.
Product Specification
Philips Components-Bignetics Data Communication Products
SCN68562
Dual universal serial communications controller (DUSCC)
0010
0011
the value 15 and the clock output will
be forced Low. The counter will be
disabled until a transition on the data
line is detected, at which point it will
start incrementing. After the counter
reaches a count of 31, it will reset to
zero and cause the clock output to go
from Low to High. The DPLL will then
continue normal operaton. This allows theDPLL to be locked onto the
data without pre-frame transitions.
This command should not be used if
the DPLL is programmed to supply
the clock for the transmitter is active.
Preset to FFFF. Presets the counter
timer to H'FFFF' and the prescaler to
its initial value.
This command
causes the CfT output to go Low.
Preset from CTPRH/CTPRL. Transfers the current value in the counter/
timer preset registers to the
counter/timer and presets the prescaler to its initial value. This command causes the CfT output to go
Low.
Digital Phase-Locked Loop
Commands
0000
0001
Disable DPLL. Disables operation of
the DPLL.
0010
Set FM Mode. Sets the DPLL to the
FM mode of operation, used when
FMO, FM1, or Manchester (NMRZ) is
selected by CMRI [7:6].
0011
Set NRZI Mode. Sets the DPLLto the
NRZI mode of operation, used when
NRZ or NRZI is selected by
CMR1[7:6).
0100
Reserved for test.
0101
Reserved for test.
Enter Search Mode. This command
causes the DPLL counter to be set to
Table 9,
Command Register Bit Format
CHANNEL COMMAND REGISTER
BIT7
I
BITe
BIT 5
BIT4
BIT3
I
BIT2
I
BIT1
I
00 =
Transmitter CMD
don't
care
don't
care
00000001001000110100010101100111 100010011010101111001101-
resetTx
reset TxCRC'
enable Tx
disable Tx
transmit SOM (TSOM)
transmit SOM with PAD (TSOMP)
transmit EOM (TEOM)"
transmit ABORT/BREAK (TABRK)
transmit DLE (TDLE)"
go active on poll
reset go active on poll
go on-loop
go off-loop
exclude form CRC'
don't
care
0000000100100011-
reset Rx
reserved
enable Rx
disable Rx
don't
care
0000000100100011-
start
stop
preset to FFFF
preset from CTPRH/CTPRL
0000-
enter search mode
disable DPLL
set FMmode
set NRZI mode
reserved for test
reserved for test
Receiver Command
01 =
Receiver CMD
don't
care
Countermmer Command
10 =
CfTCMD
don't
care
DPLL Command
11 =
DPLLCMD
October 30, 1990
BIT 0
Transmitter Command
(CCRA, CCRB)
don't
care
don't
care
323
00010010001101000101-
Philips Components--Signetics Data Communication Products
Product Specification
Dual universal serial communications controller (DUSCC)
DETAILED OPERATION
Interrupt Control
A single interrupt output (IRON) is provided
which is activated upon the occurrence of any
of the following conditions:
Channel A external or CIT special condition
Channel B extemal or CIT special condition
Channel A RxlTx error or special condition
Channel B RxlTx error or special condition
Channel A TxRDY
Channel B TxRDY
Channel A RxRDY
Channel B RxRDY
Each of the above conditions occupies a bit in
the General Status Register (GSR). If ICR[2J
is set, the eight conditions are encoded into
three bits which are inserted into bits [2:0J or
[4:2J of the interrupt vector register. This forms
the content of the IVRM during an interrupt acknowledge cycle. Unmodified and modified
vectors can read directly through specified registers. Two of the conditions are the inclusive
OR of several other maskable conditions:
- External or CIT special condition: Delta
DCD, Delta CTS or CIT zero count
(ICTSR[6:4J).
- RxlTx error or special condition: any condition in the Receiver Status Register
(RSR[7:0J) or a transmitter or DPLL condition in the Transmitter and Receiver Status
Register (TRSR[7:3J).
The TxRDY and RxRDY conditions are defined
by OMR[4J and OMR[3J, respectively. Also associated with the interrupt system are the Interrupt Enable Register (IER), one bit in the
Countermmer Control Register (CTCR), and
the Interrupt Control Register (lCR).
The IER is programmed to enable specified
conditions or groups of conditions to cause an
interrupt by asserting the corresponding bit. A
negated bit prevents an interrupt from occurring when the condition is active and hence
masks the interrupt. In addition to the IER,
CTCR[7J could be programmed to enable or
disable an interrupt upon the CIT zero count
condition. The interrupt priorities within achannel are fixed. Priority between channels is controlled by ICR[7:6J. Refer to Table 8 and
ICR[7:6].
The ICR contains the master interrupt enables
for each channel (ICR[lJ andICR[OJ) which
must be set if the corresponding channel is to
cause an interrupt. The CPU vector mode is
specified by ICR[5:4J which selects either vectored or non-vectored operation. If vectored
mode is selected, the content of the IVR or
IVRM is placed on the data bus when lACK is
October 30, 1990
activated. If ICR[2J is set, the content of IVRM
is output which contains the content of IVR and
the encoded status of the interrupting condition.
Upon receiving an interrupt acknowledge, the
DUSCC locks its current interrupt status until
the end of the acknowledge cycle. If it has an
active interrupt pending, it responds with the
appropriate vector and then asserts DTACKN.
Ifitdoes not have an interrupt, it propagates the
acknowledge through its X2/1DCN output if this
function is programmed in PCRA[7]; otherwise,
the IACKN is ignored. Locking the interruptstatus althe leading edge of IACKN prevents a device at a High position in the interrupt daisy
chain from responding to an lACK issued for a
lower priority device while the acknowledge is
being propagated to that device.
DMA Control
The DMA control section provides the interface
to allow the DUSCC to operate with an external
DMA controller. One of four modes of DMA can
be programmed for each channel independently via CMR2[5:3J:
- Half-duplex single address. In this mode, a
single pin provides both DMA read and
write requests. Acknowledgement of the
requests is via a single DMA acknkowledge
pin. The data transfer is accomplished in a
single bus cycle - the DMA controller
places the memory address of the source
or destination of the data on the address
bus and then issues the acknowledge signal, which causes the DUSCC to either
write the data into its transmit FIFO (write
request) or to output the contents of the top
of the recieve FIFO (read request). The
cycle is completed when the DTCN input is
asserted by the DMA controller. This mode
can be used when channel operation is
half-duplex (e.g., BISYNC) and allows a
single DMA channel to service the receiver
and transmitter. The receiver and transmitter should not be enabled at the same
time when half-duplex mode is programmed.
- Half-duplex dual address. In this mode, a
single pin provides both DMA read and
write requests. Acknowledgement of the
requests is via normal bus read and write
cycles. The data transfer requires two bus
cycles - the DMA controller acquires the
data from the source (memory for a Tx
DMA or DUSCC for a Rx DMA) on the first
cycle and deposits it at the destination
(DUSCC for a Tx DMA or memory for a Rx
DMA) on the second bus cycle. This mode
is used when channel operation is half-duplex (e.g., BISYNC) and allows a single
DMA channel to service the receiver and
transmitter.
324
SCN68562
- Full-duplex single address. This mode is
similar to half-duplex single address mode
but provides separate request and acknowledge pins for the receiver and transmitter.
- Full-duplex dual address. This mode is
similar to half-duplex dual address mode
but provides duplex dual address mode
and provides separate request pins for the
receiver and transmitter
Figures 4 through 7 describe operation of the
DUSCC in the various DMA environments.
Table 10 summarizes pins used for the DMA request and acknowledge function for the transmitter and receiver for the different DMA
modes.
The DMA request signals are functionally identical to the TxRDY and RxRDY status signals
for each serial channel except that the DMA request signals are negated on the leading edge
of the acknowledge signal when the subsequent transfer causes the FIFO to become full
(transmitter request) or empty (receiver request).
In non-DMA operation TxRDY and RxRDY signals are automatically negated only after the
transfer is completed. The DMA read request
can be programmed through OMR[3J be asserted either when any character is in the receive FIFO or only when the receive FIFO is
full. Likewise, the DMA write request can be
programmed through OMR[4J to be asserted
either when the transmit FIFO is not full or only
when the transmit FIFO is empty (The transmitter must be enabled for a DMA requesllo be asserted). The request signals are automatically
negated when the respective data transfer
cycle is completed and the FIFO becomes full
(transmitter request) or empty (receiver request). If a transfer is completed and the FIFO
is not left full (transmitter) or empty (receiver),
the request stays Low. The request may be negated by the CPU with a status reset write
cycle. (Although DONEN terminates all DMA
transfers, it has no effect on the requests. The
requests are a function of the FIFO status, but
they can be negated by writing into the GSR.)
When the serial channel is not operating in
DMA mode, the request and acknowledge pins
for the channel can be programmed for other
functions (see Pin Descriptions).
DMA DON EN Operation
As an input, DONEN is asserted by the DMA
controller concurrent with the corresponding
DMA acknowledge to indicate to the DUSCC
that the character being transferred into the
TxFIFO is the last character of the transmission
frame. In synchronous modes, the DUSCC can
be programmed through TPR[4J to automati-
Product Specification
Philips Components-Signetics Data Communication Products
SCN68562
Dual universal serial communications controller (DUSCC)
mitted characters and the terminal count
has occurred.
cally transmit the frame termination sequence
(e.g., FCS-FLAG in BOP mode) upon receipt of
this signal.
As an output, DONEN is asserted by the
DUSCC under the following conditions:
a. In response to the DMA acknowledge for
a receiver DMA request if the FI FOed RECEIVED EOM status bit (RSR[7]) is set
for the character being transferred.
b. In response to the DMA acknowledge for
a receiver DMA request if the counterltimer has been programmed to count trans-
Table 10.
Block Transfers Using DTACK
The DTACKN line may be used to synchronize
data transfers to and from the DUSCC utilizing
a 'wait' state. Either the receive or the transmitter or both may be programmed for this mode
of operation, independently for each channel,
via CMR2[5:3j.
In this mode, if the CPU attempts a write to the
transmit FIFO and an empty FIFO position is
not available, the DTACKN line will remain negated until a position empties. The data will
then be written into the FIFO and DTACKN will
be asserted to signify that the transfer is complete.
Similarly, a read of an empty receive FI FO will
be held off until data is available to be transferred. Potentially, this mode can cause the microcomputer system to hang up if, for example,
a read request was made and no further data
was available.
DMA REO and ACK Pins for Operational Modes
FUNCTION
RCVR REO
TRAN REO
RCVRACK
TRAN ACK
HALF DUPLEX
SINGLEADDR
DMA
RTxDRON
Same as RCVR REO
RTxDAKN
Same as RCVR ACK
Timing Circuits
The timing block for each channel consists of a
crystal oscillator, a Bit Rate Generator (BRG),
a Digital Phase-Locked Loop (DPLL) and a
16-bit Counterrrimer (CIT) (see Figure 8).
Crystal Oscillator
The crystal oscillator operates directly from a
crystal (normally 14.7456MHz if the internal
BRG is to be used) connected across the
X1/CLK and X2/1DCN pins with a minimum of
external components. If an external clock of the
appropriate frequency is available, it may be
connected to the X1/CLK pin. This signal is divided by two to provide the internal system
ciock.
Bit Rate Generator
The BRG operates from the osciliator or external clock and is capable of generating 16-bit
rates. These are available to the receiver,
transmiller, DPLL, and CIT. The BRG output is
at 32X the base bit rate. Since all sixteen rates
are generated simultaneously, each receiver
and transmitter may select its bit rate independently. The transmitter and receiver timing registers include a 4-bit field for this purpose
(TTR[3:0j, RTR[3:0]).
Digital Phase· Locked Loop
Each channel of the DUSCC includes a DPLL
used in synchronous modes to recover clock information from a received data stream. The
DPLL is driven by a clock at nominally 32 times
the data rate. This clock can be programmed,
via RTR[7:4j, to be supplied from an external input, from the receiver BRG, from the crr, or directly from the crystal oscillator.
The DPLL uses this clock, along with the data
stream to construct a data ciock which may
October 30, 1990
HALF DUPLEX
DUALADDR
DMA
RTxDRON
Same as RCVR REO
Normal read RCVR FIFO
Normal write TRAN FIFO
RTxDRON
TxDRON
RTxDAKN
TxDAKN
then be used as the DUSCC receive clock,
transmitciock, or both. The output olthe DPLL
is a square wave at 1X the data rate. The
derived clock can also be programmed to be
output on a DUSCC pin: only the DPLL receiver
output clock is available at the TRxC pin. Four
commands are associated with DPLL operation: Enter search mode, set FM mode, set
NRZI mode, and disable DPLL. The commands are described in the Command Register
Description. Waveforms associated with the
DPLL are illustrated in Figure 9.
DPLL NRZI Mode Operation - This mode is
used with NRZ and NRZI data encoding. With
this type of encoding, the transitions of the data
stream occur at the beginning of the bit cell.
The DPLL has a six-bit counter which is incremented by a 32X ciock. The first edge detected
during search mode sets the counter to 16 and
begins operation. The DPLL output clock then
rises at a count of 0 and falls at 16. Data is
sampled on the rising edge of the clock. When
a transition in the data stream is detected, the
count length is adjusted by one or two counts,
depending on the counter value when the transitionoccurs (see Table 11). A transition detection at the roll-over point (third column in Figure
11) is treated as a transition occurring at zero
count.
The count length adjustments cause the rising
edge of the DPLL output block to converge to
the nominal center of the bit cell. In the worst
case, which occurs when a DPLL pulse is coincidentwith the data edge, the DPLLconverges
after 12 data transitions.
For NRZ encoded data, a stream of alternating
ones and zeros should be used as a synchro-
325
FULL DUPLEX
DUALADDR
DMA
FULL DUPLEX
SINGLEADDR
DMA
RTxDRON
TxDRON
Normal read RCVR FIFO
Normal write TRAN FIFO
nizing pattern. For NRZI encoded data, a
stream of zeros should be used.
Table 11.
NRZI Mode Count
Length
COUNT WHEN
TRANSITION
DETECTED
COUNT
LENGTH
ADJUST·
MENT
COUNTER
RESET
AFTER
COUNT
REACHES
0-7
8-15
16-23
24-30
None detected
-2
-1
+1
+2
0
29
30
32
33
31
DPLL FM Mode Operation - FM operation is
used with FMO, FM1, and Manchester data encoding. With this type of encoding, transitions
in the data stream always occur at the beginning of the bit cell for FMO and FM1, or at the
center of the bit cell for Manchester. The DPLL
6-bit counter is incremented by a 32X clock.
The first edge detected during search mode
sets the counter to 16 and begins operation.
The DPLL receiver clock then rises on a count
of 8 and falls on 24. (The DPLL transmitter
ciock output falls on a count of 16. it rises on
a count of 0 if a transition has been detected between count of 16 and 23. For other cases, it
rises 1/2 count of the 32X input clock sooner.)
This provides a 1X clock with edges poSitioned
at the nominal centers of the two halves of the
bit cell. The transition detection circuit is enabled between counts of 8 and 23, inclusive.
When a transition is detected, the count length
is adjusted by one, depending on when the
transition occurs (see Table 12).
Philips Components-Signetics Data Communication Products
Product Specification
Dual universal serial communications controller (DUSCC)
RSR2S STATUS BIT
SCN68562
(STATUS BIT
RSR2SET)
PINSYNOUTN
U(SYNOUT)
(SUBSEQUENT
SYNC INPUTS
IGNORED)
(SYNC INPUT COINCIDENT
WITH SECOND BIT OF
ARST CHARACTER)
PINCDCDISYNIN
PINRxD
(IX Rx CLOCK)
Figure 2. External Sync Mode
If a transition is not detected for two consecutive data bits, the DPLL is forced into search
mode and the DPLL error status bit (TRSR[3])
is asserted. This feature is disabled when the
DPLL output is used only as the transmitter
clock.
To prevent the DPLL from locking on the wrong
edges of the data stream, an opening PAD sequence should be transmitted. For FMO, a
stream of at least 16 ones should be sent initially. For FM1, a minimum stream of 16 zeros
should be sent and for Manchester encoding
the initial data stream should consist of alternating ones and zeros.
Table 12.
FM Mode Count
Length
COUNT WHEN
TRANSITION
DETECTED
COUNT
LENGTH
ADJUST·
MENT
8-15
16-23
24-7
None detected
-1
+1
Disabled
0
COUNTER
RESET
AFTER
COUNT
REACHES
30
32
31
CounterlTimer
Each channel of the DUSCC contains a Countermmer (CIT) conSisting of a 16-bit down
counter, a IS-bit preset register, and associated control circuits. Operation of the counter/timer is programmed via the Countermmer
Control Register (CTCR). There are also four
commands associated with CIT operation, as
described in the Command Description section.
October 30, 1990
The CIT clock sou rce, clock prescali ng, and operating mode are programmed via CTCR[2:0],
CTCR[4:3], and CTCR[6], respectively. The
preset register is loaded with minimum of 2 by
the CPU and its contents can be transferred
into the down counter by a command, or automatically upon reaching terminal count if
CTCR[6] is negated. Commands are also
available to stop and start the CIT and to preset
it to an initial value of FFFF. Counting is triggered by the falling edge of the clocking input.
The CIT zero count status bit, ICTSR[6], is set
when the CfT reaches the terminal count of
zero and ICTSR[7] indicates whether the
counter is currently enabled or not.
An interrupt is generated upon reaching zero
count if CTCR[7] and the channel's master interrupt enable are asserted. The output of the
CIT can be programmed to be output on the
channel's RTxC or TRxC pin (via PCR[4:0]) as
either a single pulse or a square wave, as programmed in CTCR[5]. The contents of the CfT
can be read at any time by the CPU, butthe CfT
should normally be stopped before this is done.
Several CfT operating modes can be selected
by programming of the counter/timer control
register. Typical applications include:
1. Programmable divider. The selected
clock source, optionally prescaled, is divided by the contents of the preset register. The counter automatically reloads
itself each time the terminal count is
reached. In this mode, the CfT may be
programmed to be used as the Rx or Tx
bit rate generator, as the input to the
DPLL, or it may be output on a pin as ei-
326
ther a pulse or a square wave. The CfT
interrupt should be disabled in this mode.
2. Periodic interrupt generator. This mode is
similar to the programmable divider mode,
except that the CfT interrupt is enabled,
resulting in a periodic interrupt to the
CPU.
3. Delay timer. The counter is preset from
the preset register and a clock source,
optionally prescaled, is selected. An interrupt is generated upon reaching terminal count. The CfT continues counting
without reloading itself and its contents
may be read by the CPU to allow additional delay past the zero count to be determined.
4. Character counter. The counter is preset
to FFFF by command and the clock
source becomes the internal signal used
to control loading of the Rx or Tx characters. This operation is selected by
CTCR[2:0]. The CIT counts characters
loaded into the RxFIFO by the receiver or
loaded into the transmit FIFO by the CPU,
respectively. The current character count
can be determined by the CPU by reading
the contents of the CfT and taking its
ones complement. Optionally, a preset
number may be loaded into the counter
and an interrupt generated when the
count is exhausted. When counting Tx
characters, the terminal count condition
can be programmed through TPR[4] to
cause an end of message sequence to be
transmitted. When counting received
Product Specification
Philips Components-Signetics Data Communication Products
Dual universal serial communications controller (DUSCC)
charactgrs, the FIFOed EOM status bit is
asserted when the character which
causes the count to go to zero is loaded
into the receive FIFO. The channel's 'reset lx' or 'reset Rx' commands have no
effect on the operation of the CIT.
5. External event counter. The counter is
preset to FFFFF by command and an external clock source is selected. The current count can be determined by the CPU
by reading the contents of the CIT and
taking its ones complement. Optionally, a
preset number may be loaded into the
the input data. Normally thiS function is
used for asynchronous operation.
counter and an interrupt generated when
the count is exhausted.
6. Bit length measurement. The counter is
preset to FFFF by command and the
X1/CLKl4 clock input gated by RxD mode
(optionally prescaled) is programmed.
The CIT starts counting when RxD goes
Low and stops counting when RxD goes
High. At this time, ICTSR[6] is set and an
interrupt (if enabled) is generated. The
resulting count in the counter can be read
by the CPU to determine the bit rate of
SCN68562
Communication Channels A
and 8
Each communication channel of the DUSCC is
a full-duplex receiver and transmitter that supports ASYNC, COP, and BOP transmission formats. The bit rate clock for each receiver and
transmitter can be selected independently to
come from the bit rate generator, CIT, DPLL, or
an external input (such as a modem generated
clock).
TRANSMITTER AND RECEIVER STATUS REGISTER A (TSRSRA)
INPUT AND CIT STATUS REGISTER A (ICTSRA)
~SHORTI
I OVR
ERROFRAME
I. I.I. I
. PROTOCOL DEPENDENT
GENERAL STATUS REGISTER
~~~~~~~~...
IRON TO CPU
-------
MASTER CHANNEL INTERRUPT
76543210
IIIIIIII
INTERRUPT VECTOR REGISTER (IVR)
-~~~~~-
Figure 3. Interrupt Control and Status Register
October 30, 1990
327
I·-~
~-
IACKN FROM CPU
Philips Components-8ignetics Data Communication Products
Product Specification
Dual universal serial communications controller (DUSCC)
DMAC
MEMORY
DMAC
SCN68562
MEMORY
DUSCC
t
DUSCC
t
Initiate Request
1. Assert RxORON
I
lniti ... Request
1. Assert T,ORON
•t
I
Acquire BUB
•t
Acquire IIuo
Addrese Memory
1. Set AWN to write
2. Place address on bus
Addre.. Memory
1. Set RWN 10 read
2. Place addraaa on bus
3. Assert ASN
3. AssartASN
4. Assert RTxDAI lines of the bus.
In this case, the peripheral appears to host
software and lOP channel programs as occupying every other byte within its address
range. The relationship between AO, and
the data lines to which the peripheral is connected is as shown in Table 2. This method
has the advantage 01 hardware simplicity
but the disadvantage is thatthe 6-bit "device
displacement" values in the lOP instructions can only span 32 register bytes.
2. Or, a peripheral's 8-bit bus can be interfaced
to the 16-bit data bus using two octal transceivers, and its AO--An inputs can be connected to the AO-An lines on the bus (if AO
exists, otherwise A 1-An' sig·nals). In this
case, the peripheral appears to the host
software or lOP channel program as a contiguous set of bytes as described in its data
sheet. 8-bit "device displacement" values in
the lOP instructions can span 64 byte location.
In this case, one of the two transceivers is
enabled according to AO (see Table 2).
Byte and Word Ordering for lOP
For a Byte Cycle With:
lOP Takes Data From: .
For a Word Cycle With:
lOP Accesses:
AO=O
AO=1
07-00
015-08
A1 =0
A1 = 1
LS 16 bits (bits 15-0)
MS 16 bits (bits 31-16)
Table 2.
8-Blt Peripheral Attachment for the lOP
If an 8-Bit Peripheral Is Connected to:
Then the lOP addresses the peripheral with:
II an 8-Blt Peripheral is Connected to Both Halves 01 the
Data Bus, then lor a Cycle
With:
Intel System Enables the Trans·
ceivers on:
015-08
07-00
Odd addresses
Even addresses
AO=O
AO= 1
07--00
015-08
8- and 16-Blt Devices
and Memories
The lOP requires a 16 (or 32) bit memory for its
channel programs and decision tables, but can
transfer data to and from memory either 8 or 16
bits at a time. It can also handle peripheral devices that transfer 8 or 16 bits of data at a time.
the only exception to this facility is that only 8
bits of data can be interpreted at a time using
a decision table. Several types of transfer sequences are possible during INPUT and OUTPUT instructions.
November 1989
1. 8-bit device, 8-b~ memory transfers. Each
byte is read' from the source (device or
memory), placed in the CHAR register, optionally interpreted through a decision table.
and then written to the destination (memory
or device).
2. 16-bit device, 16-bit memory transfers. Each
16-bit word is read from the source, placed
in CHAR and the SST entry for the channel,
and then written to the destination.' Either
one olthe two bytes in the word can be interpreted as part of the INPUT or OUTPUT
354
command. If both bytes need to be interpreted, multiple i,nstructlons are needed.
3. 8-bit device. 16-bit memory transfers, INPUT instruction. In general, bytes destined
for even-addressed memory locations are
stored in the byte store table until the byte
for the following odd-addressed location is
available from the device. The composite
16-bitword is then written to memory. Each
byte can be interpreted just after being read
from the device.
Preliminary Specification
Philips Components-Signetics Data Communication Products
1/0 Processor (lOP)
4. 8-bit device, 16-bit memory transfers, OUTPUT instruction. In general, 16-bit words
are read from memory. Each word's evenaddressed byte is immediately sent to the
device, while the odd-addressed byte is
saved in the BST until the device is ready for
it. Each byte can be interpreted just before
it is sent to the device.
The BST and BSTO flags are included in the
lOP to allow it to handle cases 3 and 4 above.
While this adds on-Chip RAM, operation in this
mode is advantageous because it reduces the
total number of cycles used on the bus.
CTRL Register
This register is programmable by the host processor to control the basic operation of the lOP
(See Figure 4). Note that the contents of the
CTRl register represents system-level constants that are intended to be programmed
once, at system initialization time. The only bit
that can be re-programmed thereafter is dE.
BuS Time-Out Facility
Whenever the lOP is accessing external
memory or peripheral, it waits for DAcKN to be
asserted. In case of certain system malfunctions, this response may never occur. Therefore, the lOP includes a time-out counter that
operates whenever it is waiting for DACKN (but
not when it is waiting for BGN). The time-out
field of the TOCTRl register should be programmed to the host MPU before the lOP operation is enabled, to reflect a time-out longer
than the longest valid DACKN response time
that is possible in the system. The lOP will wait
for DACKN for 2'+7 ClK periods, where t is the
value olthe 3-bit time-out field. Thus, a time-out
field value of 0 will cause the lOP to wait up to
128 ClK periods. A 1 designates waiting 256
ClK periods, and so forth through the maximum time-out value of 7 which will cause the
lOP to waitup to 16,384 ClKperiods.AtaClK
frequency of 16MHz, these correspond to a
range of 8 microseconds to 1 millisecond.
If the time-out value is exceeded, the lOP internally simulates an INT instruction, using the
higher priority level if there are two levels, using
the vector field of the TOCTRl register as the
vector value. Thus, it asserts the IRaN pin if it
had not been asserted previously. After doing
this, it clears the dE bit in the CTRl register so
thatit no longer responds to any furtherrequest
signals. The vector from TDCTRl should
cause the host MPU to investigate the problem
and take appropriate corrective action.
November 1989
SC26C460
Typical Execution
The next section describes the lOP instructions. Forthe instructions, the following general
rules apply for channel program execution.
1. A peripheral device asserts its "interrupt request" output. This signal is either directly
connected to one of the lOP's Ran inputs,
or is encoded externally to make the value
on R04-ROO.
2. The request is serviced when no higherpriority peripheral is making a request.
3. The lOP begins service for this peripheral
by transferring the encoded channel number to the CHAN and TCHAN registers, and
then loads the value in the corresponding
entry from the PCT RAM into its program
counter (PC). It then executes the "channel
program" that starts at the location in external memory.
Note that the PCT entry for a channel is initially loaded by the host MPU, and can be
changed by a channel program thereafter,
in response to changing status of the peripheral device.
4. A channel program will typically start with an
INTERP instruction that reads a status register on the peripheral and then uses the
status byte as an index to read a word from
a "decision table" in memory.
5. The contents of the word from the decision
table may cause the lOP to do either, both,
or neither of two things: change (add to) the
value in the CHAN register, andlor branch,
i.e. reload the PC with a value in the decision table word or from PCT [new CHAN].
The two actions above correspond to the
kinds of information that a peripheral status
byte may convey: in a multi-channel peripheral device, it identifies which channel
needs service, andlor it identifies any exceptionalconditions (e.g. errors) involved in
its "interrupt request".
For example, in a peripheral with separate
input and output channels, the decision
table words cOrresponding to an "output request" might be coded to add 2 to (CHAN)
and branch, while those corresponding to
an "input request" might do neither of those
things.
355
Note that a priority between such input and
output channels is determined by coding of
words corresponding to "both requests".
Also that while the decision table mechanism might be considered wasteful in
memory, it improves performance by processing a whole status bye "in parallel" to
make a decision that an MPU interrupt service routine might make by means of a series of "bit test" and "branch" instructions.
6. With some peripheral devices, several status registers may have to be read to determine what is to be done. For example, with
the 2698 each DUART has an individual interrupt request line, but within each one,
each UART has its own status register. In
such cases, the channel program might begin with several consecutive I NTERP instructions, one for each status register. The
decision table words could be set up to:
a. if the status register value indicates there is
something to be done, branch to a routine
to do it, or
b. if there is nothing to be done, increment
CHAN to the value that corresponds to the
next status register, and don't branch.
7. After the INTERP instruction(s) have routed
control to the appropriate branch of the
channel program based on the peripheral
status, a branch that transfers data will use
an INPUT or OUTPUT instruction to transfer data between memory and (one of) the
peripheral's data register(s).
8. INPUT and OUTPUT instructions can also
use the decision table structure, for applications in which data byte values affect what
is to be done. Forexample, in receiving from
a datacomm line, reception of a carriage return (CR) character might mean that the
current input buffer in memory is 'complete"
and that the host MPU should be notified.
Decision table processing for INPUT and
OUTPUT instructions is slightly different
from that for INTERP. As with INTERP, certain data characters can cause a branch,
but instead of CHAN adjustment, decision
table words for data are coded to control
whether the byte is transferred to the destination (to memory for INPUT, to the device
for OUTPUT).
Preliminary Specification
Philips Components-5ignetics Data Communication Products
SC26C460
110 Processor (lOP)
MAXON
MIN OFF
UPri
dE
This bit enable the overall operation of the lOP. H it is zero, the lOP ignores the ROn lines. dE resets to zero; host MPU
software should set up the various registers and RAM locations in the lOP before programming this bit to 1.
rE
This bit indicates how the RQ lines are interpreted by the lOP and how the starting CHAN value for service Is derived from
them. " the request code on RQ4-AOO is externally encoded. then rE should be programmed 10 O. in which case thalO?
treats the Ran lines as carrying a channel nurroer. If (5 or less) devices "interrupt request- signals are directly connected
to the RO lines, then rE should be programmed to 1, in which case the lOP encodes the state of R04-RQO to obtain a
channel nurrber. In this encoding. R04 has the highest priority and ROO the lowest A table In the request logic sed ion
indicates the starting CH~N value for each of the five devices (RO lines) when rE is 1.
Max On, Min Off
These fields are used only in single-bus applications. Max On control.s the maximum length ot timethe lOP will retain control
of the bus alter being granted it, while Min Off controls the length of time for which the lOP will refrain from requesting the
bus again. after it has given it up. Together, these two values constitute a "throttle" control on hOW' rruch of the overall bus
bandwidth an lOP will use. These times are measured In terms of the elK input divided by 4. Max On .. 0 indicates that
the lOP will run only one bus cycle per grant. Note that in dual·bus application, the lOP will always give up control of the
system bus alter using it for one cycle, so that these values do not apply.
UP,I
UPri assigns the starting channel number for each Ran input in the internal encoded mode (rE .. 1). In this assignment,
the lower the starling channel, the higher the priority. The effect of UPri "on starting channel numbers is as follows:
_ _ STARTING CHANNEL NUMBER-+
INTERNALLY ENCODED RQ'.
nl
UPri
RD<
RQ3
RQ2
RQl
ROO
000
001
010
011
100
101
8
12
12
4
4
4
4
16
16
16
20
20
20
20
12
12
24
24
24
24
24
,6
0
0
0
0
0
8
8
B
This bit controls how the interrupt FIFO Is Configured. If nl is 0, it is treated as a single FIFO 01 32 entries, which ~re all
~ the same level of priority. If nL is 1, it is divided into 2 FIFOs each having 16 entries, representing two priority \9veis.
Figure 4. CTRL Register
9. An INPUT and OUTPUT instruction will typically be written so that it ends servicing for
the channel unless a decision table causes
a branch, or the byte count for the I/O buffer
in memory is decremented to zero.
10. When an 110 buffer is completed, the channel program will typically interrupt the host
MPU. Such interrupts are stored in a queue
on the lOP, so that the host MPU is interrupted once for each time any lOP channel
program posts an interrupt.·
11. In addition to interrupting the host when an
I/O buffer is completed, the channel program can either use a RELOAD instruction
to get another I/O buffer from a circular list
of such buffers, or send a command byte to
the device to teli it to stop asserting its "interrupt request" line for this channel, until the
host MPU responds to the interrupt posted
by the channel program.
November 1989
INSTRUCTION SET
INTERP
0100
I I
0
OecTabM
Is I
devdiap
4
1
4
1
6
This instruction is used fro examining status bytes and similar data.
1. If devdisp is not "ali ones", data is read from
an external device at the address formed as
follows:
A23--0 (DAT[CHAN] XOR devdisp
Bit 15 of MCT[CHAN] determines the size
of data read from the device:
a. If this bit indicates a 16-bit peripheral, a
word is read from the device. The units bit
of the address has no effect on the cycle
with the device, but rather serves to identify
which byte of the word is interpreted. The
byte selected by the units bit of the address
356
is placed in CHAR and the other byte is
placed in BST[CHAN]. The units bit of the
address is saved in the internal SVAO flag
in case the word needs to be reconstituted
later.
IftheSbitofthe instruction is 1,the selected
byte is also stored in the internal SVCHAR
register, and the other byte is stored in the
internal SVBST register, lor later retrieval
and reinterpretation.
b. IF bit 15 of MCT[CHAN] indicates an 8-bit
peripheral, a byte is read and placed in
CHAR. If the S bit of the instruction is 1, the
byte is also stored in the SVCHAR register,
for later retrieval and reinterpretation.
2. If devdisp = ali ones, (CHAR) from a previous· instruction is used in the following
steps, and the S bit of the instruction has no
effect.
Philips Components-Signetics Data Communication Products
Preliminary Specification
I/O Processor (lOP)
3. A word is read from a decision table at the
address formed as follows:
A23-13:
A12-9:
A8-1
AO:
(DTBR)
DecTab#
(CHAR)
0 for word access.
SC26C460
2. "devdisp = all ones, (CHAR), and (BST
(CHANJ) if applicable, from a previous instruction are use in the following steps, and
the S bit of the instruction has no effect.
3. "DecTab#>O, awordis read from a decision
table at the address formed as follows:
A23-13: (DTBR)
A 12-9: DecTab#
A8-1:
(CHAR)
AO:
0 for word access.
This word is interpreted as follows:
This word is interpreted as follows:
Is I DellaCHAN I
New PC
ro
1
Note that this is the only instruction that can use
DecTab#O.
4. The Delta CHAN value is added to (CHAN),
the result being new contents for the CHAN
register.
5. If B = 1, the lOP tests whether the new PC
value is "aU ones". If so, it loads
(PCT[CHANJ) into the PC, otherwise it
loads the New PC value in the decision
table word into the PC. In either case, the
lOP executes its next instruction from the
new location. "B = 0, the next instruction is
performed.
INPUT
0101
4
I E I Decla"" IS I
1
4
1
devdiap
6
This instruction provides the basic data transfer
mechanism from devices to memory areas.
1. "devdisp is not "all ones·, data is read from
an external device at the address formed as
follows:
A23-0: (DAT[CHANJ) XOR devdisp.
I slwl
1
a. "this bit indicates a IS-bit peripheral, a
word is read from the device. The units bit
of the address has no effect on the cycle
with the device, but rather serves to identify
which byte of the word is interpreted in the
next phase of instruction operation. The
byte selected by the units bit of the address
is placed in CHAR and the other byte is
placed in BST[CHAN]. The units bit of ihe
address is saved in the SVAO flag in case
the word needs to be reconstituted later.
lithe S bitolthe instruction is 1, the selected
byte is also stored in the SVCHAR register,
and the other byte is stored in the SVBST
register, for later retrieval and reinterpretation.
b. II bit 15 of MCT(CHAN) indicates an 8-bit
peripheral, a byte is read and placed in
CHAR." the S bit of the instruction is 1, the
byte is also stored in the SVCHAR register,
for later retrieval and reinterpretation.
November 1989
New PC
4
10
II DecTab# = 0, the lOP performs the following
steps as if B = 0 and W = 1.
4. " the W bit is 1, bits 15 and 14 of MCT
(CHAN] determine how the data is transferred to memory:
a. "these bits indicate an 8-bit peripheral and
8-bit memory transfers, the byte in CHAR is
written to memory at the address in
MAT[CHAN). The address is incremented
by 1, and the count in MCT[CHAN] is decremented by 1.
b. II MCT/CHAN) bits 15-14 indicate a lS-bit
peripheral and lS-bit memory (SVAO) so
that the word is written in the same way it
was read from the device. The address is incremented by 2, and the count in
MCT(CHAN] is decremented by 2.
c. If MCT(CHAN] bits 15-14 indicate an 8-bit
peripheral and lS-bit memory transfers:
i.
Bit 15 of MCT[CHAN) determines the size
of data read from the device.
1
If the address in MAT(CHAN) is not 0001,
the byte in CHAR is placed in BST[CHAN),
and the BSTO[CHAN) flag is set.
ii. It the address is even and the count is 000 1,
(CHAR) is written to memory as a byte.
iii. It the address is odd and the BSTO[CHAN]
. flag is set, a word is written to memory. Its
even-addressed byte is obtained from BST
[CHAN) and its odd-addressed byte is obtained from CHAR.
iv. lithe address is odd and the BSTO[CHAN]
flag is not set, (CHAR) is written to memory.
This will only occur for the first byte in a buffer that starts at an odd address.
Regardless of how (CHAR) is handled, the address in MAT/CHAN) is decremented by 1, and
the count in MCT[CHAN) is decremented by 1.
5. II the B bit is 1 and the "new PC" value is all
ones, (PCT(CHANJ) is loaded in the PC,
and execution continues from that address.
"B is 1 and the "new PC" is not all ones, the
"new PC" is loaded into the PC, and execution continues from that address.
357
6. It the count was not decremented to 0 in step
5, and B is 0, and E is 1, the service for this
device is completed.
7. " the count was decremented to 0 in step
5 or (B is 0 and E is 0), execution continues
at the next instruction.
OUTPUT
I 011 IR I E I Declo"" IS I
3
1
1
4
devdiep
1
The instruction provides the basic data transfer
mechanism from memory areas to devices.
1. "R= 1,bits 15and 14 of MCT[CHAN] determine how memory data is obtained for
transfer to the peripheral:
a. II these bits indicate an 8-bit peripheral and
8-bit memory transfers, a byte is read from
memory at the address in MAT[CHAN] and
is placed in the CHAR register. The address
in MAT[CHAN) is incremented by 1, and the
count in MCT(CHANII is decremented by 1.
" the S bit of the instruction is 1, the byte
placed in CHAR is also stored in the
SVCHAR register, for later retrieval and reinterpretation.
b. II MCT[CHAN) bits 15 and 14 indicate a
lS-bit peripheral and IS-bit memory transfers, a word is read from memory at the address in MAT[CHAN). The units bit of the
address has no effect on the memory cycle
but rather serves to select which byte can
be interpreted in the next phase of instruction operation. The byte selected by the
units bit of the address is placed in CHAR,
the other byte is placed in BST[CHAN], and
the units bits is saved in the SVAO bit so the
word can be reconstituted later. The address in MAT/CHAN) is incremented by 2,
and the count in MCT/CHAN) is decremented by 2.
II the S bit of the instruction is 1, the byte
placed in CHAR is also stored in the
SVCHAR register, and the other byte is
stored in the SVBST register, for later retrieval and reinterpretation.
c. It MCT[CHAN) bits 15 and 14 indicate an
8-bit peripheral and lS-bit memory transfers, a byte is obtained in one of the following'ways and is placed in CHAR:
II the address in MAT(CHAN) is even and
(MCT(CHANJ) is not 0001, a word is read
from that address. Its even-addressed byte
is placed in CHAR, its odd-addressed byte
is placed in BST[CHAN), and the
BSTO[CHAN] flag is set.
ii. If the address is even and the count in
MCT(CHAN] is0001, a byte is read from the
address.
Preliminary Specification
Philips Components-Signetics Data Communication Products
SC26C460
I/O Processor (lOP)
iii. If the address is odd and the BSTO[CHAN]
flag is set, the byte in BST[CHAN] is transferred to CHAR.
7. It. the count was decremented to 0, or (B
is and E is 0), execution continues at the
next instruction.
iv. If the address is odd and the BSTO[CHAN]
flag is not set, a byte is read from the address. This will only occur for the first byte
in a buffer that starts at an odd address.
Note that an OUTPUT instruction with R = 0,
DecTab# = 0, devdisp = 1111111, (MCT) > 0,
and E = 1 does nothing other than completing
the current service. Same conditions with E =
o can be used as NOP instructions.
Regardless of how the byte is obtained, the address in MAT[CHAN] is incremented by 1, and
the count in MCT[CHAN] is decremented by 1.
It the S bit of the instruction is 1, the byte placed
in CHAR is also stored in the SVCHAR register,
for later retrieval and reinterpretation.
2. If R = 0, (CHAR) and (BST[CHAN]) from a
previous instruction are used in the following steps, and the S bit of the instruction has
no effect.
3. Unless DecTab# = 0, a word is read from a
decision table at the address formed as follows:
A23-13: (DTBR)
A12-9: DecTab#
AS-l:
(CHAR)
AO:
for word access.
This word is interpreted as follows:
°
I Blwl
1
1
New pc
4
10
If DecTab# = 0, the lOP performs the following
steps as if B = and W = 1.
°
4. It devdisp is not "all ones" and the W-bit is 1,
data is sent to an external device at the address formed as follows:
A23-0: (DAT[CHAN]) XOR devdisp
Bit 15 of MCT[CHAN] determines how
much data is sent:
a. It this "it indicates a 16-bit peripheral, a
word is sent to the device. The data is comprised of (BST[CHAN]) and (CHAR), arranged according to (SVAO) so that the
word is written in the same way it was read
from memory.
b. It bit 15 of MCT[CHAN] indicate an S-bit peripheral, (CHAR) is sent to the device
5. If the B bit is 1 and the "new PC" value is all
ones, (PCT[CHAN]) is loaded in the PC,
and execution continues from that address.
If B is 1 and the "new PC" is not all ones,
(PCT[CHAN]) is loaded into the PC, and execution continues from that address.
°
INT
1011
4
IEIFILlol
1
1
1
1
vecto,
8
When the command is executed, the following
steps are performed:
1. If the F bit is 1 and the BSTO[CHAN] flag
is set, then the current buffer is "closed" as
follows:
a. (BST[CHAN]) is written to memory at the
address in MAT[CHAN] minus one. (The
address in MAT[CHAN] is always odd when
BSTO is set, so this is accomplished by simply forcing AO to 0.) The operation is actually
a word write, with the data written to the
odd-addressed byte being undelined.
Since the byte in BST[CHAN] would not
have been placed there if MCT[CHAN] indicated it was destined for the last byte available in the buffer, a word write is always
permissible.
b. The address in MAT[CHAN] in not incremented, and the count in MCT[CHAN] is not
decremented (these two operation s already
occurred for this byte when it was placed in
BST).
c. The BSTO[CHAN] Ilag is cleared.
2. 'vector' and (CHAN) are written into the interruptFIFO.llnLin the CTRLregisteris 1 and
Lis 0, they are placed in the lower-priority
queues. If nL in the CTRL register is 1 and
L is 1, they are placed in the higher-priority
queue. If nL is 0, there is only one 32-entry
queue, and the L bit is ignored.
4. The selected FIFO is "popped", that is, its
top entry is removed.
5. IF nL is 1 and both FIFOs are now empty,
or nL is 0 and the (single) FIFO is now
empty, the IRON pin is negated.
By the mechanism described above, the lOP
maintains two internal interrupt priority levels at
which a channel program can post an interrupt
to the host MPU. All interrupts with L = 1 have
a higher priority than any interrupts with L = 0,
but within each level interrupts are presented to
the host MPU in the orderthatthey were posted
by the channel program(s). Forexample, forexternal UARTs, all "receive" and "error" interrupts
mightbe posted at level 1 while "transmit" interrupts are posted at level O.
JCD
1001
00
4
2
New pc
10
If the count in MCT[CHAN] is zero, then the value "new PC" is loaded in the PC and these becomes the address 01 the next instruction
executed. Otherwise, the next instruction is executed.
JNCD
1001
01
4
2
New PC
10
lIthe count in MCT[CHAN] is zero, then the value "new PC" is loaded in the PC and thus becomes the address of the next instruction
executed. Otherwise, the next instruction is executed.
JUMP
1001
I
New pc
11
2
4
10
3. The IRON pin is asserted (if it was not already asserted).
The value "new PC" is unconditionally loaded
in the PC and thus becomes the address of the
next instruction executed.
4. It E is 1, s~rvice for this channel is con-
LOPCT
cluded; otherwise the next instruction is performed.
1010
When the host processor responds byasserting the IACKN pin, or by polling the INTRD register, the following steps are performed:
It B is 1 and the "new PC" is not all ones, the
"new PC" is loaded in the PC, and execution
continues from that address .•
1. If nL is 1 and there is at least one entry in
the higher-priority FIFO, the higher-priority
FIFO is selected. If nL is 1 and the higherpriority FIFO is empty, the lower-priority
FIFO is selected. If nL is 0, the single
·32-entry FIFO is selected.
6. It the·count was not decrementedtoOand
B is 0, and E is 1, the service for this device
is completed.
2. The vector byte from the top entry in the selected FI FO is placed on the external data
pins (07-00), and DACKN is asserted.
November 19S9
3. The channel number for the top entry in the
selected FIFO is copied to the INTCHN register, from which it can be read by the host
MPU.
358
4
10
1
Ic I
1
New PC
10
The value "New PC" is loaded in a PC entry and
thus becomes the starting point for execution
lor future device service. I! C is 0, the vale is
loaded in PCT[TCHAN], where TCHAN is the
channel number at which execution was
started for the current device (i.e., the request
code 01 ihe current device). I! C is 1, the value
is loaded in PCT[CHAN]. Note that CHAN may
have been changed by INTERP instructions
since tile start of execution.
The TCHAN register is also used by the RELOAD instruction. I! both a RELOAD instruction
Preliminary Specification
Philips Components-Signetics Data Communication Products
110 Processor (lOP)
and a LCPCT instruction with C = 0 are to be
done during the same execution, the LDPCT
must be executed first.
SC26C460
structions. Careful examination of the procedure described above, and the description for
INPUT, will clarify the various possibilities.
SEND2DEV
I 00 I
1
value
divdiap
1
·value" is sent to an external device at the address
A23-O: (DAT[CHAN]) XOR devdisp.
This instruction is useful for sending fixed byte
values (e.g., commands) to devices. (CHAR) is
not used or changed by this instruction. for
SEND2DEV, devdisp may not be all ones, because this value identifies the instruction as
SEND2MEM.
SEND2MEM
I 00 I
1
value
1
8
111111
6
The ·value" byte is written to memory as if it had
been received from the device in an INPUT in. struction. Bit 14 of MCTlCHAN] determines
how the data is transferred to memory.
1. If MCT[CHAN]14 =0, indicating8-bitmemory transfers, "value" is written as a byte at
the address in MAT[CHAN].
2. If MCT[CHAN]14 = I, indicating 16-bitmemory transfers, the lOP proceeds as follows:
a. If the address in MAT[CHAN] is even and
the count in MCT[CHAN] is not 000 I, "value" is placed in BST[CHAN], and the
BSTO[CHAN] flag is set.
b. Ifthe address iseven andthecountis0001,
"value" is written to memory as a byte.
c. If the address is odd and the BSTO[CHAN]
flag is set, a word is written to memory. Its
even-addressed byte is obtained from
BST[CHAN] and its odd-addressed byte is
"value".
d. If the address is odd and the BSTO[CHAN]
flag is not set, "value" is written to memory
as a byte.
Regardless of the memory width and how ·value" is handled, the address in MAT[CHAN] is incremented by I, and the count in MCT[CHAN]
is decremented by 1.
An example of use of this instruction is to substitute an error code when a character with a parity error is received from a comm link.
If device data is also 16 bits wide, SEND2MEM
instructions should be done in pairs so as to
store 16-bit values in memory. If a single
SEND2MEM is performed during service for a
channel for a 16-bitdevice, its data byte may be
written to memory immediately, or the byte may
be lost, or the byte may be written to memory
after intervening words stored by INPUT inNovember 1989
LDCHAR
1001
op
00
4
2
2
value
8
"value" is loaded into CHAR andlor SVCHAR
depending on "op" as follows:
op
Operation
00 CHAR: = value
01
SVCHAR, CHAR: = value
IF MCT[CHAN]15 = I,
BST[CHAN]: = (SVBST)
10 BST[CHAN]: = (CHAR);
CHAR: = value. SVAO: = 0
11
as 10 except SVAO: = 1
With op = 00, the 8-bit immediate value is simply placed in CHAR for use by subsequent instructions. With op = 01, the value is placed in
both SVCHAR and CHAR, and if the channel
involves a 16-bit peripheral, the contents of
SVBST are retrieved and placed in BST
[CHAN]. the latter characteristic of operation
with op = 0 1 is by symmetry with the next group
of (logic) instructions. No specific application of
this characteristic is foreseen.
With op = 1x, the previous contents of CHAR
are sent to BST[CHAN], the new value is
placed in CHAR, and the SVAO flag is set as indicated. As noted in a subsequent section, one
LDCHAR with op = 00 can be followed by one
with op = 1x to set up to a "16-bit immediate value" that can then be sent to a 16-bit device in
one operation by an OUTPUT command.
ORCHAR,ANDCHAR,XORCHAR
1100 I
op
I
LL
I
value
••
•
The logical combination indicated by LL, between "value" and (CHAR), (SVCHAR), or
(BST[CHAN]), is formed and then placed in
CHAR andlor SVCHAR. LL values are as follows:
LL Function
01
ANDCHAR
10 ORCHAR
11
XORCHAR
while "op" values are as follows:
op
Operation
00 CHAR: = value LL CHAR
01
SVCHAR, CHAR: = value LL SVCHAR;
IF MCT[CHAN] 15 = I,
BST[CHAN]: = (SVBST)
10 tmp: = value LL BST[CHAN];
BWT[CHAN]: = (CHAR);
CHAR: = tmp; SVAO: = 0
11
same as 10 except SVAO: = 1
359
These instructions, with op = 00, can be used
by a channel program to produce a "command"
value from a "status" value from a peripheral. In
particular, commandlstatus bytes for some peripherals include a collection of information for
multiple sub-devices/channels. In such cases,
it is necessary to modify certain bits in the byte
value while preserving other bits "as is".
With op = 01, these instructions can be used to
retrieve (SVCHAR), potentially modified, back
into CHAR for use by a subsequent INTERP instruction having an all ones "devdisp" field. If a
status register contains multiple event flags,
this facility can be used to handle the events
one by one. If the channel involves a 16-bit peripheral, BST[CHAN] is also retrieved from
SVBST
With op = 1x, the instructions can be used to
more or less exchange (BST[CHAN]) and
(CHAR), with modification, which may be useful in conjunction with handling 16-bit data or
status values for 16-bit devices.
Note that ORCHAR with value = 0 comprises a
"move" operation.
RELOAD
1101 10iFIoi
4
1
1
1
0000
4
Delta CHAN
5
1. If the F bit is 1 and the BSTO[CHAN] flag is
set, then the current bufferis "closed" as follows:
a. (BST[CHAN]) is written to memory at the
address in MAT[CHAN] minus one. (The
address in MAT[CHAN] is always odd when
BSTO is set, so this is accomplished by simply forcing AO to 0). The operation is actually
a word write, with the data written to the
odd-addressed byte being undefined.
Since the byte in BST[CHAN] would not
have been placed there if MCT[CHAN] indicated it was destined for the last byte available in the buffer, a word write is always
permissible.
b. The address in MAT[CHAN] is not incremented, and the count in MCT[CHAN] ,s'not
decremented (these two operations already
occurred for this byte when it was placed in
BST).
c. The BSTO[CHAN] flag is cleared.
2. The sum (CHAN) + Delta CHAN is formed
and placed in the TCHAN register. A second
lOP channel is selected by (TCHAN). The
24-bit contents of MAT[CHAN], with 8 highorder zeros, are written into memory by
means of two consecutive 16-bit writes
starting at the address in MAT[TCHAN], followed by one 16-bit write of 0000.
MAT[TCHAN} is incremented and MCT
[TCHAN] is decremented as these words
are written, fora total increment/decrement
of 6 (bytes).
Preliminary Spe.cification
Philips Components-Signetics Data Communication Products
SC26C460
1/0 Processor (lOP)
3. If MCT[TCHAN] is zero at the conclusion of
these writes, then the contents of OAT
[TCHAN] are copied into MATITCHAN],
and the contents of PCT[TCHAN] are copied into the 10 LSBsof MCT[TCHAN]. This
feature allows a wraparound "ring" of buffer
addresses and counts, containing OAT
[TCHAN]! 6 entries.
Note that while PC entries contain less bits than
MCT entries, 10 bit are more than enough to
contain the length of the buffer address table
used for reloading.
4. Whether or not such a wraparound occurs,
the lOP saves (MAT[TCHAN], then reads
two words from memory at the new address
in MAT[TCHAN] and places the contents in
MAT[CHAN], and then read the next word
and places its contents in MCT[CHAN]. Finally it restores MATITCHAN] to the saved
i/
Y
MAT[7J I- - BUFFER 1 ADDR.. -MCT(7]
MAT[O)
BUFFER 1 LENGTH -
r.:.---
MCT[9}
/
- -
If there are only a few buffers in the "ring (e.g. 2),
and the processor takes a long time from servicing interrupts, it is possible that ali the buffers
in the ring may be exhausted. This can be
tested by a JCO or JNCO instruction following
the RELOAD.
The count loaded in the MCT and PCT entries,
for an lOP channel that is used for reloading,
must be a multiple of 6.
Figure 5 shows the effect of two different executions of a RELOAD instruction with CHAN ~. 7
and Delta CHAN ~ 2. Channel 7 has a ring of
three 110 buffers and is reloaded via channel g.
The first RELOAD is issued after"n" bytes have
been transferred from or to buffer area 1', at
which time the host MPU is "Current" in that it
has provided the addresses and counts of buffers 2 and 3. The other RELOAD is executed
some time later; "m" bytes have been trans-
In analyzing the contents of a buffer that was
"prematurely terminated" because of interpreting a status or data byte, system software does
not have access to the residual count for the
buffer. However, since" the address in a MAT
entry is always incremented whenever the
count in the corresponding MCT entry is decremented, the stored address conveys the
same information in a slightly less convenient
form.
BUFFER 1 ADDR - -
r -
- - BUFFER 1 ADDR +n
BUFFER 2 LENGTH
MCT(7]
BUFFER 2 ADDR - -
MATI9}
-
- -
BUFFER 3 ADDR - -
B~FFER
MAT[O)
- - - - 101210--~
MeT[9}
1006,0
DAT[O] 1 - - - -
,000,0----
PCT[9}
1018,0
MAT(7] I- -
BUFFER 1 LENGTH
MCT[7J
BUFFER 1 ADDR - BUFFER 1 LENGTH /
MAT[9} 1 - - - -
1000,0 - - - -
0000
MeT[O]
1018,0
I- - BUFFER 3 ADDR - -
DAT[9]
- - - - '000'0 - - - -
BUFFER 3 LENGTH
PCT[O]
1018,0
BEFORE THIRD RELOAD
--
BUFFER, ADDR +n .-
0000
360
- -
BUFFER 2 ADDR - BUFFER 2 LENGTH
- -
BUFFER 3 ADDR - BUFFER 3 LENGTH
AFTER THIRD RELOAD
Figure 5. Effects of Two RELOAD 2 Instructions with (CHAN)
November 1989
/
/
I- - BUFFER 2 ADDR + k .-
.~
BUFFER 3 ADDR - -
AFTER ARST RELOAD
I- - BUFFER 1 ADDR - -
3 LENGTH - m
--
BUFFER 3 LENGTH
BEFORE ARST RELOAD
MeT(7]
BUFFER 2 ADDR
BUFFER 2 LENGTH
1012,0
BUFFER 3 LENGTH
MAT[7J -- BUFFER3ADDR+n .-
--
0000
--_. 1006 ,0 .--=-:::= ~ -
MCT[9}
BUFFER 2 LENGTH
1018 10
Host Software Constraints
MAT(7] - - BUFFER 2 ADDR - -
BUFFER, LENGTH
_. -
,000,0----
fimed from or to buffer 3, and the host MPU is
a little "behind" in that it has refreshed the address and count for buffer 1 but has not yet done
sO for buffer 2.
.
value, so that it once again points to the first
word of the address in memory.
=7
Preliminary Specification
Philips Components-$ignetics Data Communication Products
1/0 Processor (lOP)
Some Applications
This section provides a few examples of how
various lOP instructions can be combined.
Sending a Word to a Device
SEND2DEVonly send an 8-bitbyte to a device.
If a l6-bit word must be sent to a l6-bit device
in a single write operation, a sequence like the
following can be used:
LDCHAR valuel
LDCHAR value2, op=l x
OUTPUT R = 0, decTab#=O
Interpreting a 16-Blt Status Value
To interpret both bytes in a status value from a
l6-bit device, without re-reading the word:
INTERP TAB1,statreg_offset
ORO,op=lx
INTERP TAB2, X"3F'
Interpreting a 16-Bit Data Value
As the previous example, but the 16-bit value
should be written to memory ifboth bytes "pass"
interpretation:
INTERP TABA,datareg_offset
November 1989
SC26C460
OR 0, op=1x
INPUT TABB, X"3F'
Additional Notes
Since the lOP maintains its addresses and bUller length in on-chip RAM, it can service any of
its channels without having to fetch this data
from external memory.
The best-case service time for a channel is
when its channel program consists of a single
INPUT or OUTPUT instruction, with neither
status no.data interpretation. In this case, servicing the channel takes three bus cycles: one
to fetch the instruction, one to read the memory
or peripheral, and one to write to the peripheral
or memory.
Perhaps more typical is the case when peripheral status needs to be interpreted. In this case,
an instruction read, a status read and adecision
table read are added before the transfer instruction is read, for a total fa six bus cycles.
In the 2698 OCTART handler shown in Listing
1, there are tow separate status registers that
361
may need to be read. Thus, a single character
can be handled in either six or nine bus cycles,
or an average of 7.5. However, when the receive FIFO is full, the handler uses the 2698's
flag indication to process 4 received characters
in 18 or 21 cycles, an average of 4.875 bus
cycles per character. Similarly, when the transmitter is completely empty, the handler processes 2 transmitted characters in 10 or 13 bus
cycles, an average of 5.75 bus cycles per character.
If data is to interpreted as well as status, anotherdecision table read is performed between the
data read and write cycles, for a total of (at
least) seven bus cycles.
All of these figures assume that decision table
reads do not indicate any exceptional action
such as buffer termination or error handling,
and that the buffer count does not expire. Such
(rare) occurrences may add substantially to the
number of cycles and the time to service a
channel.
Preliminary Specification
Philips Components-Signetics Data Communication Products
SC26C460
1/0 Processor (lOP)
Listing 1 .. Sample of lOP Service Routine for a 2698
0000
IOPC HANDLER FOR 2698
BEGIN_PROG
00000002
00000004
00000006
00000006
0000
0000
0000
0000
00000008
0000
OFFSETS OF 2698 REGISTERS, TIMES 2 FOR BYTE DEVICE
2
STATUS
SR
4
COMMAND
CR
RECEIVE DATA
RlIR
6
TIlR
6
TRANSMIT DATA
; COMMAND CODE IN CR
DTX
8
DISABLE TX
00000000
0000
; DECISION TABLE FORWARD REFERENCES
SRTAB
0
0000
0002
2698 CHANNEL PROGRAM STARTS HERE
(HOST PUTS STRT98 IN 4 PCT ENTRIES
THE FOLLOWING INTERPS BRANCH IF THE SR OF A UART IS NON-ZERO,
OTHERWISE THEY STEP CHAN +2 AND CONTINUE TO THE NEXT INSTRUCTION
SR,SRTAB
; TEST UART #1 STATUS
STRT98: INTERP
INTERP
SR, SRTAB
; TEST UART #2 STATUS
B8l6
0004
ERROR:
BOTH STATUS REGS ZERO,
FFULL WITHOUT RXRDY,
TXEMT WITHOUT TXRDY
FLGERR: INT
22, END
; 22 IS VECTOR FOR WEIRD THINGS
5006
900A'
5006
900A'
5006
900A'
0006
0008
OOOA
OOOC
OOOE
0010
; RECEIVE 4 CHARACTERS (INTERP BRANCHES HERE IF FFULL)
RCV4
INPUT
RlIR
ONE
JCO
RCVEND
INPUT
RlIR
TWO
JCO
RCVEND
INPUT
RlIR
THREE
JCO
RCVEND
5806
B8l8
0012
0014
RECEIVE 1 CHARACTER (INTERP BRANCHES HERE IF RXRDY, NO FFULL)
RCV:
INPUT
RlIR, ,END
; READ RlIR, WRITE MEMORY
RCVEND INT
24, END
7006
900E'
0016
; TRANSMIT 2 CHARACTERS (INTERP BRANCHES HERE IF TXEMT, NO RXRDY)
XMIT
OUTPUT
TIlR
ONE
JCO
XMITEND
7·806
0204
B8l9
OOlA
OOlC
OOlE
TRANSMIT 1 CHARACTER (INTERP COMES HERE IF TXRDY, NO RXRDY NOR TXEMT)
XMIT:
OUTPUT
TIlR, END
READ MEMORY, WRITE TIlR
XMITENC SEND2DEV CR, DTX
; DISABLE THE TRANSMITTER
INT
25, END
B8l7
0020
; RECEIVER ERROR(S) (INTERP BRANCHES HERE IF ANY OF 4 HIGH SR BITS)
RCVERR: INT
23, END
4002
4002
FLAG
0022
0000
0800
8009
8002
8003
840D
8009
8002
8003
8002'
840B
8009
8002
8003
8010'
8010'
(ETC.
.)
November 1989
0000
0002
0004
0006
0008
OOOA
OOOC
OOOE
0010
0018
OOlA
OOlC
OOlE
0020
0028
DECISION TABLE
DTAB
IDTE
IDTE
IDTE
IDTE
IDTE
IDTE
IDTE
IDTE
IDTE
IDTE
IDTE
IDTE
IDTE
IDTE
FOR 2698 SR
SRTAB
,2
RCV
FLGERR
RCV4
XMIT,l
RCV
FLGERR
RCV4
FLGERR,,4
XMIT2, 1
RCV
FLGERR
RCV4
RCVERR, ,240
362
IF STATUS = 0, NO BRANCH, STEP CHAN +2
RXRDY
FFULL, NO RXRDY IS IMPOSSIBLE
FFULL, RXRDY
TXRDY (STEP CHAN +1)
TXRDY, RXRDY
FFULL, NO RXRDY IS IMPOSSIBLE
TXRDY, FFULL, RXRDY
TXEMT, ·NO TXRDY IS IMPOSSIBLE
TXEMT, TXRDY (STEP CHAN +1)
TXEMT, TXRDY, RXRDY
FFULL, NO RXRDY IS IMPOSSIBLE
TXEMT, TXRDY, FFULL, RXRDY
RECEIVE ERRORS
Preliminary Specification
Philips Components-Signetics Data Communication Products
SC26C460
1/0 Processor (lOP)
ABSOLUTE MAXIMUM RATINGS1, 2, 3
RATING
PARAMETER
UNIT
o to +70
'C
Storage temperature range
-65 to +150
'C
Supply voltage to ground
-0.5 to +6.5
V
Operating ambient temperature range
Power dissipation
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not implied.
2. For operating at elevated temperature, the device must be derated based on + 150'C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge.
Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
DC ELECTRICAL CHARACTERISTICS TA = O'C to +70'C,
Vcc = 5V±10%
TENTATIVE LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
V IL
Input low voltage
V IH
Input high voltage
VOL
Output low voltage
VOH
Output high voltage (except open-drain outputs)
IlL
Input leakage current
ILL
Data bus 3-State leakage current
Min
Max
UNIT
O.B
V
2.0
= 2.4mA
IOH = -400fIA
VIN = 0 to Vcc
VIN = 0 to Vcc
V
0.4
IOL
V
V
2.4
10
10
fIA
10
10
fIA
AC ELECTRICAL CHARACTERISTICS TA = O'C to +70'C, Vcc = 5V ±10%'
TENTATIVE LIMITS
NO.
FIGURE
1
2
3
4
6
6
6
6
PARAMETER
BCLK period (tSCLK)
BCLK width high
BCLK width low
RESETN width low
Min
Max
UNIT
60
25
25
1000
600
ns
ns
ns
ns
50
ns
ns
ns
ns
ns
ns
ns
Master Arbitration
5
6
7'
B
9
10
11
12'
7
7
7
7
7
7
7
7
BCLK high to BRN low
BRN low to BGN low
Setup, BGN low to BCLK low
BCLK high to drivers enabled
BCLK high to BRN high
BRN high to drivers disabled
BRN high to BGN high
Setup, BGN high to BCLK low
0
10
2
0
0
10
50
20
Master Operation
20
21
22
23
24
25
26
27
2B'
29
30
31
32
34
35
36
37
3B
B,9
B,9
B,9
B,9
B,9
B,9
B,9
B
B,9
B,9
B,9
B
B,9
9
9
9
9
9
November 19B9
BCLK high to A23:1 change
BCLK high to A23:1 valid
BCLK high to RWC valid
BCLK high to MIlO valid
A23:1. RWC. and MilO valid to ASN low
BCLK high to ASN low
BCLK high to DHIEN andlor DLDEN low
D15:0 valid (read) to DACKN low
Setup, DACKN low to BCLK high
BCLK low to ASN high
BCLK low to DHIEN and DLDEN high
Hold, read data valid after DHIEN and DLDEN high
DHIEN and DLDEN high to DACKN high (to avoid acknowledging next cycle)
BCLK high to data bus drivers enabled (write)
BCLK high to write data valid
Write data valid to DHIEN andlor DLDEN low
Hold, write data valid after BCLK high
BCLK high to data bus released (end of write)
363
0
0
0
20
4
4
0
10
50
50
50
45
45
50
50
0
\eCLK
0
60
10
10
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Preliminary Specification
Philips Components-Signetics Oata Communication Products
. 1/0 Processor (lOP)
SC26C460
AC ELECTRICAL CHARACTERISTICS (Continued)
TENTATIVE LIMITS
NO.
FIGURE
PARAMETER
Min
Max
UNIT
Slave Arbitration (Two Bus System)
39'
40
41
42
43'
44
45
10
10
10
10
10
10
10
10
Setup, LBRN low to BCLK low
BCLK high to LBGN low
BCLK high to lOP drivers disabled
LBGN low to lOP drivers disabled
Setup, LBRN high to BCLK low
LBRN high to LBGN high
BCLK high to lOP drivers enabled
45
30
20
10
40
10
ns
ns
ns
ns
ni;
ns
ns
Slave Operation
47
48
49
50'
51 3
53
54
55
56
57
58
59
60
61
62
63
64'
65
66
67'
68
69.
70
11,12
11,12
11,12
12,13
11,12,13
11,12
11,12,13
11,12
11
11
11,12
11,12
11,12
11,12
12
13
13
13
13
13
13
13
13
Setup, AS:l valid to CSN low
Setup, RWC valid to CSN low
Setup, OHIEN and/or OLOEN low to CSN low
Setup, CSN low to BCLK low
lOP response latency
BCLK low to data bus valid (read or lACK)
BCLK low to OACKN low
OACKN low to CSN high or (OHIEN and OLOEN high)
Hold, data bus valid after CSN high or (OIEHN and OLOEN high)
CSN high or (OHIEN and OLOEN high) to data bus released
CSN high or (OHIEN and CLOEN high) to OACKN released
Hold, A8:1 valid after CSN high or (OHIEN and OLOEN high)
Hold, RWC valid after CSN high or (OHIEN and OLOEN high)
CSN width high (intercycle)
Setup, data bus valid (write) to CSN low
Hold, write data valid after CSN high or (OHIEN and DLOEN high)
Setup, IACKN low to BCLK low
BCLK low to IRON released
DACKN low to IACKN high
Setup, IACKN high to BCLK low
Hold, data bus valid after IACKN high
IACKN high to data bus released
IACKN high to DACKN released
0
0
0
10
3tBClK
111sclK
65
40
0
10
30
25
0
0
IsClK
0
0
10
0
10
10
50
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
NOTES:
1. If the subject input signal meets this setup time, the lOP is guaranteed to recognize its new state at the subject edge of BCLK. If this setup
time is not met, recognition may occur at the subject clock edge, or one BCLK later.
2. The maximum rating of this parameter should be as short as is consistent with device characterization, so as to maximize the compatibility of
the lOP with processors that re-arbitrate and re-grant if BR is kept low after a first grant.
3. This parameter defines the number of clock cycles (wait states) between the BCLK falling edge at which CSN or IACKN is sampled and the
falling edge from which the lOP responds with DACKN low, which is a function of the lOP's internal state and activity. For accesses to DMA
processor registers when the lOP is idle, 3 BCLK cycles are required. For accesses to DUART registers when the lOP is idle,S BCLK cycles
are required. If the lOP is internally active at the same time CSN or IACKN goes low, up to 11 BCLK cycles may be needed.
BCLK_~
.amp
OJ
Figure 6. Clock and Reset Timing
November 1989
364
q
Preliminary Specification
Philips Components-Signetics Data Communication Products
SC26C460
110 Processor (lOP)
BCLK
BRN
BGN
A.3:., ASN,
RWC, MIlO,
OHIEN, OLOEN
:i,_ _---<~I[
----------~~
~~~~;--------
Figure 7. Two Wire Master Arbitration
BCLK
+_.11 I'___+ ____?~----+------+--+_-..A
A.3:. _ _
ASN
RWC
--+-~---_1-+_--~~----~-----_4--_+~~~~--
M~O
OHlEN, OLOEN
D'5~ -------------~~~r---_r-------_r-~:=~--OACKN
Figure 8. lOP Read From External Peripheral or Memory
November 1989
365
Preliminary Specification
Philips Components-$ignetics Data Communication Products
SC26C460
1/0 Processor (lOP)
BCLK
-+-_'" 1'----+------4--,')--+-------I---I--...f"'--...:.-
A23:1 _ _
ASN
RWC
MIlO
D15:O
----------t-~~--1--l~-1------j--i-t~._--
DHlEN, DLOEN
DACKN
Figure 9. lOP Write to External Peripheral or Memory
BCLK
LBRN
LBGN
A23, ASN,
RWl, MIlO,
DHlEN, DLOEN
Figure 10. Dual Bus ''Slave'' Arbitration
November 1989
366
Preliminary Specification
Philips Components-Signetics Data Communication Products
1/0 Processor (lOP)
SC26C460
BCLK
D15~----------j--------TI------------------~~
____~________~~--+-~
51
DACKN----------r-------~I~----------------------~~----~
CSN
AS:1
RWC
--~~~----------_l~------------------------------------~,~--+_~~------
DHiEN. CLOEN
Figure 11. Host MPU Read from lOP
BCLK
015:0
CSN
DACKN
AS:1
--,~--~----------l~----------------------------------~~--+_~'------
RWC
--~~~----------_l~------------------------------------~,~_4--~~------
DHlEN, CLOEN
Figure 12. Host MPU Write to lOP
November 1989
367
Preliminary Specification
Philips Components-Signetics Data Communication Products
1/0 Processor (lOP)
SC26C460
BCLK
IRaN
~
~
51
IACKN
@
07:0
4\.'
N
OACKN
Figure 13. Interrupt Acknowledge Cycle by Host MPU
November 1989
368
Philips Components-Signetics
Section 3
Wired Data
Communication Products
Data Communication Products
INDEX
AM26LS30
Dual Differential RS-422 Party Line/Quad Single-Ended
RS-423 Line Driver .............................
AM26LS31
Quad High-Speed Differential Line Driver. . . . . . . . . . . . . .
AM26LS32/AM26LS33 Quad High-Speed Differential Line Receivers .................
AM26LS328
Quad High-Speed Differential Line Receivers
. . . ..
MC145406
EIA-232-DIV.28 Driver/Receiver. .
MC1488
Quad Line Driver. . . . . . . . . . . . . . . . .
MC1489/MC1489A
Quad Line Receivers .....
NE5080
High-Speed FSK Modem Transmitter.
...........
NE5081
High-Speed FSK Modem Receiver.
NE5170
Octal Line Driver.
NE5180/NE5181
Octal Differential Line Receivers.
371
378
381
385
388
393
397
400
404
408
414
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Philips Components-Signetics
Document No.
853-0091
ECN No.
98211
Date of Issue
November 29, 1989
Status
Product Specification
AM26LS30
Dual differential RS-422
party line/quad single-ended RS-423
line driver
Data Communication Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The AM26LS30 is a line driver designed
for digital data transmission. A mode
control input provides a choice of
operation either as two differential line
drivers which meet all the requirements
of EIA Standard RS-422 or as four
independent single-ended RS-423 line
drivers.
• Dual RS-422 line driver or quad
RS-423 line driver
In the differential mode, the outputs
have individual3-State controls. In the
high impedance state, these outputs will
not clamp the line over a common mode
transmission line voltage of ± 1OV. A
typical full duplex system consists of the
AM26LS30 differential line driver and up
to twelve AM26LS32 line receivers, or
the AM26LS32 line receiver and up to
thrity-two AM26LS30 differential drivers.
• RS-422 differential mode: 35mWI
driver typ
A slew control pin allows the use of an
external capacitor to control slew rate for
suppression of near-end cross-talk to
receivers in the cable.
The AM26LS30 is constructed using
.
high speed oxide isolated bipolar
processing.
o and N PACKAGE
SLEW RATE
CONTROL A
• Driver outputs do not clamp line with
power off or in high impedance state
• Individual3-State controls when used
in differential mode
OUTPUTA
OUTPUTB
ENABLE B
SLEW RATE
CONTROlB
SLEW RATE
CQNTROlC
• Low Icc and lEE power consumption
• RS-423 single-ended mode: 26mWI
drivertyp
INPUTI
ENABLE C
6
11
OUTPUTD
INPUT D
L-._ _--' 9
A PACKAGE
w<
tc(...J .0;(
• son transmission line drive capability
(RS-422 into virtual ground)
a:~ ~
<
t-
::J
• Low current PNP inputs compatible
with TTL, MOS and CMOS
• High capacitive load drive capability
• Exact replacement for DS16/3691
• High speed oxide isolated bipolar
processing
o.
~
EN~~~~~
3
MODE
4
>8
C)
z
;:tWZ
...JO
cnU
0.
t0
:J
INPUTI 7
ENABLE C
13
w
w
U wD D
Z
~o 5
::~ g:
~8 5
ORDERING INFORMATION
TEMPERATURE RANGE
ORDER CODE
16-Pin Plastic DIP
O°C to +70°C
AM26LS30CN
16-Pin Plastic SO .
O°C to +70°C
AM26LS30CD
16-Pin Plastic DIP
-40°C to +85°C
AM26LS30IN
16-Pin Plastic SO
-40°C to +85°C
AM26LS30ID
O°C to +70°C
AM26LS30CA
20-Pin PLCC
~b~l'fttZ5
• Individual slew rate control for each
output
>
DESCRIPTION
OUTPUTC
371
SLEW RATE
CONTROle
OUTPUTC
Product Specification
Philips Components-Signetics Data Communication Products
Dual differential RS-422 partylline
quad single-ended RS-423 line driver
AM26LS30
FUNCTION TABLE
INPUTS
OUTPUTS
MODE
A(O)
8(C)
A(O)
0
0
0
0
1
0
0
Z
Z
8(C)
0
1
1
0
1
0
0
1
1
Z
Z
1
1
0
0
0
0
0
1
0
1
1
1
0
1
0
1
1
1
1
1
BLOCK DIAGRAM
LOGIC FOR AM26LS30 WITH
MODE CONTROL LOW (RS-<422)
_
~ SRCONTROLA
INPUT A ~ OUTPUT A
ENABLEB
, - - - _ ' SRCONTROLA
......... . , . - - - OUTPUTA
_
INPUT A
~ SRCONTROLB
/f$:--_
OUTPUT B
'-~-- SR CONTROl. B
, INPUTB ~ OUTPUTB
_
~ SRCONTROLC
INPUTC ~ OUTPUTC
, - - - - SR CONTROl. C
-"""'Ir---e OUTPUT C
INPUTD
_
/,~--e OUTPUT D
~ SRCONTROLD
' - - - - - SR CONTROL D
INPUTD ~ OUTPUTD
VCC ,GND-
VCC MODE
CONTROL
GND-'-
VEE -
MODE
CONTROL
VEE -
LD09460S
November 29, 1989
372
Product Specification
Philips Components-Signetics Data Communication Products
Dual differential RS-422 party/line
quad single-ended RS-423 line driver
ABSOLUTE MAXIMUM RATINGS
SYMBOL
(Above which the useful life may be impaired.)
PARAMETER
Vee
Supply voltage
V+
VEE
V-
VIN
Input voltage
VOUT
Output voltage (Power Off)
TA
Ambient temperature range
AM26LS30
UNIT
RATING
6
V
-6
V
~.5VtoVcc
V
±13.5
V
AM26LS30C
o to +70
"C
AM26Ls301
-40 to +B5
"C
TSTG
Storage temperature range
TSOLD
Lead soldering temperature (IOsec.)
8JA
Thermal impedance
-65 to +150
"C
300
"C
"CIW
PACKAGE POWER DISSIPATION DERATING TABLE
PACKAGE
POWER DISSIPATION AT TA = 25"C DERATING FACTOR
ABOVE TA
N
I,4BSmW
11.9mW/"C
D
1,262mW
10.lmWI"C
DC ELECTRICAL CHARACTERISTICS
Over the operating temperature range. The following conditions apply unless otherwise
specified: AM26LS30C, T A = 0 to 70"C, Vce = 5.0V ±5%, VEE = GND; AM26LS301,
TA = -40 to +B5"C, Vec = 5.0V ±5%, VEE = GND, RS-423 Connection Mode Voltage
<20V
LIMITS
SYMBOL2
PARAMETER
Vo
Differential output
va
Voltage, VA,B
TEST CONDITIONS3
RL = 00
UNIT
TVpl
Max
VIN = 2.0V
3.6
6.0
V
VIN =O.BV
-3.6
-6.0
V
Min
VT
Differential output
VI
Voltage, VA,B
Vos, VOs
Common mode offset voltage
RL = loon
2.5
3.0
V
tVTt - tVIt
Difference in common mode output
voltage
RL = loon
0.005
0.4
V
tVost - tVOst
Difference in common mode offset
voltage
RL = lOon
0.005
0.4
V
Vss
tVT-VIt
RL = loon
4.0
VeMR
Output voltage common
range
VENABLE = 2.4V
±IO
IXA
Output leakage current
RL = loon
mode
lox
ISA,lsB
Off-state (hi-Z) output current
Off-state (hi-Z) output current
Output short circuit current
2.4
-2.0
-2.4
V
V
V
4.B
V
VCMR = 10V
0.5
20
)lA
~.5
-20
)lA
VCMA < tOV
0.5
20
)lA
VCMR >-IOV
~.5
-20
)lA
VCMA .$ 5V
0.03
I
)lA
VCMA >-5V
~.03
1
)lA
VOA = OV
-75
-ISO
mA
Voe = 6V
100
150
mA
VOA = OV
100
150
mA
Voe= 6V
-75
-ISO
mA
Vee = MAX
Vee = MAX
VIN = 2.4V
VIN = 0.4V
November 29, 19B9
2.0
V 1N = O.SV
VeMR = 10V
Vec = OV
,1XB
lox
V1N = 2.0V
373
Product Specification
Philips Components--Signetics Data Communication Products
Dual differential RS-422 partylline
quad single-ended RS-423 line driver
AM26LS30
DC ELECTRICAL CHARACTERISTICS (Continued)
UMITS
SYMBOL2
TEST CONDITIONS3
PARAMETER
Min
Tvpl
Max
UNIT
18
30
mA
Icc
Supply current
V IH
High level input voltage
V IL
Low level input voltage
IIH
High level input current
VIN = 2.4V
VINS Vcc
0.3
100
IlL
Low level input current
VIN =0.4V
-10
V
2.0
V
40
-200
iJA
iJA
iJA
-1.5
V
0.3
Input clamp voltage
VI
IIN=-12mA
NOTES:
1. Typical limits are at Vee = 5V, V •• = GND, 25"C ambient and maximum loading.
2. Symbols and definitions correspond to EIA RS-422 where applicable.
3. Rl connected between each output and its complement.
AC ELECTRICAL CHARACTERISTICS
0.8
EIA RS-423 Connection, Vce = 5.0V, V.E = -5V, Mode = 2.4V, T A = 25"C.
UMITS
SYMBOL"
PARAMETER
TEST CONDITIONS3
Min
tR
Rise time
tF
Fall time
tpOH
Output propagation delay
tpOL
Output propagation delay
= lOOn, CL = SOOpF, Figure 1
RL = lOOn, C L = 500pF, Figure 1
RL = lOOn, CL = SOOpF, Figure 1
RL = lOOn, CL = SOOpF, Figure 1
tpLZ
Output enable to output
RL = 450n, CL = SOOpF, Figure 2
RL
tpHZ
tPZL
Output enable to output
RL
= 450n, CL '" SOOpF, Figure 2
tpZH
UNIT
Tvpl
Max
80
200
ns
110
200
ns
90
200
ns
95
200
ns
·0.8
ns
60
350
ns
140
350
ns
120
300
ns
NOTES:
1. Typical limits are at Vee = 5V, VEE = GND, 25"C ambient and maximum loading.
2. Symbols and definitions correspond to EIA RS-422 where applicable.
3. RL connected between each output and its complement.
r-------,
vCC~
, . . - - - - - " " " \ - - - - - 3.0V
1
1
1
INPUT
'-'----ov
INPUT
I
1'5
>-~T--'
21
1
~
OUTPUT
=
1
1
1
vEE ---4L _ _ _ _
OUT
_ _ _ J1
8
NOTE:
'TEK CTR
CURRENT TRANSF.
OR EQUIVALENT
'Current probe is the easiest way to display a differential waveform.
TC23010S
Figure 1, Switching Time Waveforms and AC Test Circuits for EIA RS-422 Connection
November 29, 1989
374
Product Specification
Philips Components-Signetics Data Communication Products
Dual differential RS-422 partylline
quad single-ended RS-423 line driver
r-----,'----
AM26LS30
3.0V
INPUT A
INPUT B
"TEK CTR
CURRENT TRANSF.
OR EQUIVALENT
TC32020S
Fi ure 2. 3-State Dela s
DC ELECTRICAL CHARACTERISTICS
Over the operating temperature range. The following conditions apply unless otherwise
specified: AM26LS30C. T A = 0 to 70°C. Vee = 5.0V ±5%, VEE = GND; AM26LS301,
TA = -40 to +85°C, Vee = 5.0V ±5%, VEE = GND, RS-422 Connection Mode Voltage
<08V
LIMITS
SYMBOL2
Vo
PARAMETER
Output voltage
va
VT
Output voltage
TEST CONDITIONS
Min
TVpl
Max
UNIT
RL = 003
IVeci = IVEEI
Y'N = 2.4V
4.0
4.1
6.0
V
= 4.75V
Y,N = O.4V
-4.0
-4.2
---+"'--4--.~~..----<>
1
1
1
1
1
1
1
1
1
1
1
I
~
-::-
8
OUTPUT
1
VEE+--"JL _ _ _
OUT_ _ _ JI
TC23030S
Figure 3. Switching Time Waveforms and AC Test Circuits for EIA RS-423 Connection
SLEW RATE (RISE or FALL TIME)
vo EXTERNAL CAPACITOR
10k
u:
.s
w
)
lk
"i!z
~
/
~ 100
1.
/
SUPPLY CURRENT
va SUPPLY VOLTAGE
/
«g
,
!Zw
V
a:
a:
/
1
10
100
RISE TIME ( Jls)
32
TA= 25°C
2B
24
"
20
~
16
0.
12
"
I
0
-"
RS-422 .JI' II"
8
4
•o
V
A
1--
RS-423
I
Figure 4.
0.7 1.4 2.1 2.8 3.54.2 4.9 5.6 6.37.0
FigureS.
376
I
I I I
Vee -SUPPLY VOLTAGE (V)
OP20760S
November 29.1989
lLL iNPJTS ~PE~ orlGR~UN~E~ I I I
0
If)
1000
40
36
OP2aB10S
Product Specification
Philips Components-Signetics Data Communication Products
Dual differential RS-422 partylline
quad single-ended RS-423 line driver
AM26LS30
HIGH-LEVEL OUTPUT VOLTAGE
va OUTPUT CURRENT
4.50
'--
4.05
'-
-----
'-...
~ 3.60
:---
w
"~
g
3.15
I-
::>
"-
50
....w
>
2.70
2.25
:I:
I I
1.80
4.05
~'OVI""""""
r- VC~:4.5~
5 1 .35
Vcc: 5.5V
"-
Vee= s.ov
Vee =4.SV
3.60
0.90
3.15
TA:250C
2.70
o
o
\
1\
\
1\
\
\ \
I
0.45
"-
r\ \
i'-
I
>
TA=2SoC
~V
4.50
w
....
":;:
--
I--.
0
-4
..a
-12
-16
-10
-20
-30
-40
-so
-60
\
\
\
-80
-70
-90
-100
IOH - HIGH-LEVEl OUTPUT CURRENT (rnA)
OP2079QS
FigureS.
LOW-LEVEL OUTPUT VOLTAGE
.s OUTPUT CURRENT
-4.50
I'-
-4.05
r----
~
-3.60
I'-.
g
-3.15
"~
.......
............
..............
I-
::>
"-
I-
-2.70
::>
a
Ld
~O,!.
;:0.
....
-4.05
r--r---
-3.60
r----
-2.25
-4.50
-1.80
I
6
>
-1.35
-----
TA = 25°C
r-r-....
r-...
.............. ~5.5VI
r-- ~5.0~
r-- ~:4.~
-
'\
Vee ~ 5.5V
'""""-
Vec: 5.0V
T-
-r--
Vcc: 4.5V
-<>.90
-3.15
TA = 25°C
-<>.45
0
I
4
8
12
16
12
24
36
48
60
-2.70
o
o
72
84
96
108
120
IOL-LOW-LEVEL OUTPUT CURRENT (rnA)
OP20800S
Figure 7.
November 29, 1989
377
Philips Components-Signetics
Document No.
853-1272
ECN No.
93196
Date of Issue
May 5,1988
Status
Product Specification
AM26LS31
Quad high-speed differential
line driver
Data Communication Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The AM26LS31 is a quad differential line
driver, designed for digital data
transmission over balanced lines. The
AM26LS31 meets all the requirements
of EIA standard RS-422 and Federal
standard 1020. It is designed to provide
unipolar differential drive to twisted-pair
or parallel-wire transmission lines. The
circuit provides an enable and disable
function common to all four drivers. The
AM26LS31 features 3-State outputs and
logical ORed complementary enable
inputs. The inputs are all LS compatible
and are all one unit load.
• Output skew of 2.0ns typical
The AM26LS31 is constructed using
advanced Low Power Schottky
processing.
• Operation from single +5V
• 16-pin DIP and SO packages
• Four line drivers in one package
• Output short-circuit protection
• Complementary outputs
• Meets EIA standard RS-422
• High output drive capability for 1000.
terminated transmission lines
• Available in military and commercial
temperature range
• Advanced low power Schottky
processing
TOP VIEW
FUNCTION TABLE (Each Driver)
INPUT
ENABLES
OUTPUTS
'A
A
G
G
A
• Outputs won't load line when
Vee = OV
H
H
X
H
L
L
H
X
L
H
APPLICATIONS
H
X
L
H
L
• Data communications equipment
L
X
L
L
H
Z
Z
• Computer peripherals
• Workstations
• Automatic test equipment
ORDERING INFORMATION
DESCRIPTION
0, F, and N Packages
• Input to output delay: 12ns
TEMPERATURE RANGE
ORDER CODE
IS-Pin Plastic DIP
O°C to +70°C
AM26LS31CN
16-Pin SO
O"C to +70"C
AM26LS31CD
16-Pin Plastic DIP
-40"C to +85"C
AM26LS311N
16-PinSO
-40"C to +85"C
AM26LS311D
16-Pin Plastic DIP
-55°C to + 125°C
AM26LS31MN
378
L
H
X
NOTES:
H = High level
L,,; Low level
X = Irrelevant
Z = High-impedance (OFF)
Product Specification
Philips Components-Signetics Data Communication Products
AM26LS31
Quad high-speed differential line driver
DC AND AC ELECTRICAL CHARACTERISTICS
Vee~ SV ±10%, TA ~ -55 to +125"C forAM26LS31MF and AM26LS31MN;
Vee ~ SV ±S%, TA ~ -40 to +85°C for AM26LS31IN and AM26LS31ID;
Vee ~ SV ±S%, TA ~ 0 to +70"C for AM26LS31 CN and AM26LS31 CD,
unless otherwise specified
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typl
2.S
3.0
VOH
Output High voltage
Vee ~ Min.,
10H ~ -20mA
VOL
Output Low voltage
Vee ~ Min.,
IOL ~ 20m A
V,H
Input High voltage
Vee ~ Min.
V,L
Input Low voltage
Vee ~ Max.
Input Low current
Vee ~ Max.,
V ,N ~ 0.4V
I'H
Input High current
Vee ~ Max.,
V,N ~ 2.7V
I,
Input reverse current
Vee
V,N
10
OFF-state (high-impedance)
output current
Vee ~ Max,
Vo ~ 5.5V
Vo ~ 0.5V
V,
Input clamp voltage
Vee~ Min.,
liN ~ -18mA
Ise
Output short-circuit current
Vee ~ Max.
I,L
~
~
~
0.3
Max
V
O.S
V
V
2.0
Max.,
7.0V
UNIT
0.8
V
-0.26
-0.36
rnA
0.001
20
~
0.001
0.1
rnA
0.6
-0.050
20
-20
~
~
-0.8
-30
-l.S
V
-lS0
mA
Icc
Power supply current
40
80
rnA
tpLH
Input to output
TA ~
25"C, load 2
9
20
ns
tpHL
Input to output
TA ~
2S"C, load 2
9
20
ns
SKEW
Output to output
TA ~
2S"C, load 2
2
6
ns
tLZ
Enable to output
TA ~
25"C, CL ~ 10pF
17
35
ns
tHZ
Enable to output
TA ~
25°C, CL
12
30
ns
tZL
Enable to output
TA ~
25"C, load 2
14
45
ns
tZH
Enable to output
TA ~
25°C, load 2
12
40
ns
NOTES:
1. All typical values are TA ~ +2S"C; Vee ~ 5.0V.
2 CL ~ 30pF; V,N ~ 1.3V to VOUT ~ 1.3V; VPULSE
May S, 1988
Vee
~
Max; all outputs disabled
OV to 3 Ov.
379
~
lOpF
Product Specification
Philips Components-Signeties Data Communication Products
AM26LS31
Quad high-speed differential line driver
TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage vs
Data Input Voltage
Output Voltage vs
Data Input Voltage
6.00
€
Vec· 5.OV
NO LOAD
5.00
""~5OC
w
"i3~
'.00
_55°C
> 3.00
....
"
I!:
"00
I
l
+l!5°e
2.00
> 1.00
-3.00
~"
2.SO
>
....
2.00
w
0
0
>
2
I
I
r-
J1
--55°C
I.SO
~
/ :IJ
i/ III
/
1.00
O.SO
0.5
1
1.5
~
Vee = '.sv
2.00 I--t--t--H-t--+--j
I.SO I--t--+--+-Ir--+--+--I
1.00 I--'--.l--.l-I-+--+--I
TA=2S"C
0.00 LOAD =.7QQ TO Vee
2
2.5
0.5
VI ENABLE G INPUT VOLTAGE (V)
"~
'"g
IOH=-20mA
10----
10H·-4OmA
-
~
....
".......
".....0
~
.....
0.00
-75
0
25
50
75
100 125
TA AMBIENT TEMPERATURE (OC)
MayS, 1988
3.SO
~
2.SO
1.5
~
g 3.00
~
1.00
2.5
a
0.5
2.5
1.5
VI ENABLE GINPUT VOLTAGE (V)
Low Level Output Voltage
vs Ambient Temperature
'Vce' s.SV
I',.
,
,
I',. 1',.'
0.40
....
I!:
0.30
"o
~
~,
~
i'..'
5
>
-10 -20 -30-40-50-60 -10-80 -90-100
10H HIGH LEVEL OUTPUT eURRENT (rnA)
380
"~
g
Vee' '.SV
o
I
o
>
::>
I
1.SO
25"C
+l!soe
-S5°e
g 2.00
0.00
2
~
Vee,5.0V~ t'""
2.00
2.5
I
,... rl t
4.00
~ 0.50
.......
.......
3.00
::c
!2 1.00
::c
5 O.SO
> 0.00
-50 -25
Vee· 5V
LOAD. lk,no Vee
w
w
-.....
-
'.00
2
\.
TA·2soe
w '.SO
I
~
5.00
1.5
5.00
High Level Output Voltage
vs Output Current
€
Vee' SV
1
1
Output Voltage vs
Enable G Input Voltage
VI ENABLE GINPUT VOLTAGE (V)
High Level Output Voltage
vs Ambient Temperature
~ 5.00
0.5
VI ENABLE G INPUT VOLTAGE (V)
€
::: I--t--+--.J+-+--+--I
O.SO
-t-
6.00
vec· s.sv
Vee·S.OV
!::
Output Voltage vs
Enable G Input Voltage
6.00
5.SO TA .2SOC
LOAD =470" TO GROU ND
5.00
'.SO
Vee' 5.5V
'.00
3.SO
Vee .s.OV
3.00
Vee ,'.SV
2.SO
2.00
I.SO
1.00
O.SO
0.00
'3
!; 2.SO I--t--t--+t-t--+--j
I!:
5
i3>
....
".......
0
~ 4.00 I--t--+---l---+--+--I
I I
I II
"~
>
~:
~
€
w
"0
2.5
+25"C
+125 C/
a
Vee' s.OV
Vee' '.SV
Output Voltage vs
Enable G Input Voltage
1.5
0
0.00
'.00
3.SO
0
> 3.00
....
2.SO
I!: 2.00
0
0 I.SO
> 1.00
O.SO
0.00
"~
Output Voltage vs
Enable G Input Voltage
0
...."...
::>
Vee = 5.SV
0.5
1.5
1
2
2.5
VI DATA INPUT VOLTAGE (V)
1
Vee· 5.OV
LOAD ••7O5 to +150
°C
DISSIPATION OPERATING TABLE
PACKAGE
POWER DISSIPATION
DERATING
FACTOR
ABOVE
TA
F
1,524mW
12.19mW/oC
25°C
N
1,275mW
10.2mW/oC
25°C
D'
1,262W
10.lmWf'C
25"C
DC AND AC ELECTRICAL CHARACTERISTICS
Vee =5.0V ±10% for AM26LS32133MX, Vee =5.0V ±5% for AM26LS32/33CX
and AM26LS32/331X over operating temperature range unless otherwise
specified
LIMITS
SYMBOL
PARAMETER
AM 26LS32/33
TEST CONDITIONS
UNIT
Min
Typl
Max
VOUT = VOL or VOH
AM26LS32, -7V ,. VeM ,. +7V
--{l.2
0,06
0.2
0.5
VTH
Differential input voltage
AM26LS33, -15V < VeM S +15V
--{l.5
0.06
RIN
Input resistance
-15VsVeMs+15V
(One input AC ground)
6.0
9.8
liN
Input current
(under test)
VIN =+15V
Other input -10V S VIN S + 15V
2.3
rnA
liN
Input current
(under test)
VIN = -15V
Other input + 10V S VIN S -15V
-2.8
rnA
VOH
Output HIGH voltage
VOL
Output LOW voltage
Vee = Min., 10H = --440flA
~VIN = +1.0V
VENABLE = 0.8V
Vee = Min.,
VENABLE = 0.8V
~VIN = +1.0V
Com'l
2.7
Mil
2,5
IOL = 8.0mA
V IL
Enable LOW voltage
V IH
Enable HIGH voltage
VI
Enable clamp voltage
10
Off state (high impedance)
output current
November 15, 1990
V
V
3,4
0.4
V
0.45
V
0.8
V
2.0
382
V
-1.5
V
Vo = 2.4V
20
flA
Vo = O.4V
-20
flA
' Vee = Min., liN = -18mA
Vee = Max.
V
kQ
3.4
0.3
10L = 4.0mA
V
Product Specification
Philips Components--Signetics Data Communication Products
Quad high-speed differential line receivers
DC AND AC ELECTRICAL CHARACTERISTICS (Continued)
AM26LS321 AM26LS33
vee = 5.0V ±10% for AM26LS32/33MX, Vee = 5.0V ±5%
for AM26LS32133CX and AM26LS321331X over operating
temperature range unless otherwise specified
LIMITS
SYMBOL
Min
IlL
Enable LOW current
IIH
Enable HIGH current
I;
Enable input HIGH current
Ise
Output short circuit current
Icc
Power supply current
UNIT
AM26LS32/33
TEST CONDITIONS
PARAMETER
Typ'
Max
VIN
--{).2
--{).36
mA
VIN
0.5
20
1
100
f1A
f1A
-BO
--85
mA
52
70
mA
= O.4V
= 2.7V
VIN = 5.5V
Vee = Max.,
,WIN = +IV, VOUT = OV
Vee = Max.; All VIN = GND outputs
-15
disabled
VHYST
Input hysteresis
Vee
tpLH
Input to output
tpHL
Input to output
tLZ
Enable to output
TA = 25'C,
= 5.0V, VeM = OV
TA = 25'C, Vee
AM26LS32
120
AM26LS33
120
= 5.0V
mV
mV
10
25
ns
TA = 25'C, Vee = 5.0V
CL = 15pF (see test condition)
10
25
ns
= 25'C, Vee = 5.0V
= 5pF (see test condition)
TA = 25'C, Vee = 5.0V
C L = 5pF (see test condition)
TA = 25'C, Vee = 5.0V
CL = 15pF (see test oondition)
TA = 25'C, Vee = 5.0V
CL = 15pF
15
30
ns
12
22
ns
8
22
ns
9
22
ns
CL = 15pF (see test oondition)
TA
CL
tHZ
Enable to output
tZl
Enable to output
tZH
Enable to output
NOTE:
1. All typical values are TA = 25'C, Vee = 5.0V.
FUNCTION TABLE (EACH RECEIVER)
DIFFERENTIAL
INPUT
ENABLES
OUTPUT
E
E
Vlo ~ VTH
H
X
X
L
H
H
VTL " VIO " VTH
H
X
X
L
?
?
V IO " V TL
X
H
L
X
L
X
X
L
H
Z
NOTES:
H = High level, L = Low level, X = Irrelevant
Z = High impedance (off), ? = Indeterminate
E = Enable, E' = Eii"ii6Ie
November 15, 1990
383
. Product Specification
Philips Components-Signetics Data Communication Products
Quad high-speed differential line receivers
CllNClUDES
PROBE AND JIG
CAPACITANCE
I
-=
,----3.0V
ENl'JILE
;f5~\
VCC
FROI/IOUTPUT _~~~__~__o--S1~.~
UNDER TEST
AM26LS321AM26LS33
INPUT
All DIODES
l~~~OR
OUTPUT -+--,.-!NORlllAllY
lOW
~
-1.5V
Load Test Circuit for 3-State Outputs
O.5V
Enable and Disable Tmes 2 • 3. 4
VOH
- - - 1.3V
~=\t.'"~~'
OUTPUT
~~~~f
TRANSITION
---
----
.
-,2.5V
Propagation Delay 1.4
NOTES:
1.
2.
3.
4.
Diagram shown for 'E'iiID5Tii Low.
Enable is tested with Ena'6li High; 'EffiiI5li is tested with Enable Low.
S1 and ~ of Load Circuit are closed except where shown.
Pulse Generator for An Pulses: Rates. 1.0MHz; Zo '" son; Ir S. 15n5; If .s.6.0ns.
November 15. 1990
OV
384
Philips Components-Signetics
AM26LS328
Document No.
Quad high-speed differential
line receivers
ECN No.
Date of Issue
July 20, 1990
Status
Preliminary Specification
Data Communication Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The AM26LS32B is a quad line receiver
designed to meet all of the requirements
of RS-422 and RS-423, CCID V.l 0 and
V.l1 and Federal Standards 1020 and
1030 for balanced and unbalanced
digital data transmission.
• ±1 OOmV sensitivity over the input
range of OV to 5V
The AM26LS32B features an input
sensitivity of ±1 OOm V over the common
mode input voltage range of OV to +5V
and ±200mV over the common mode
input voltage range of -7V to + 12V.
The AM26LS32B guarantees a
minimum hysteresis and propagation
delay skew resulting in a higher noise
margin and better system performance.
• ±200mV sensitivity over the VCM range
Vcc
• Typical input voltage hysteresis of
120mV
INPUT B
• 3V maximum open circuit voltage
OUTPUT B
• All AC and DC parameters guaranteed
over operating temp range
• Single +5V supply
• Advance low-power Schottky
processing
ORDERING INFORMATION
DESCRIPTION
16-Pin SO
TEMPERATURE RANGE
ORDER CODE
DOC to +7DoC
AM26LS32BCN
DOC to +7DoC
AM26LS32BCD
16-Pin Plastic DIP
-40°C to +85°C
AM26LS32BIN
16-Pin SO
-40°C to +85°C
AM26LS32BID
-55°C to +125°C
AM26LS32BMN
16-Pin Plastic DIP
INPUT!!
• Three state outputs disabled power up
and power down
The AM26LS32B provides an enable
and disable function common to all four
receivers. It features 3-State outputs
with 24mA sink capability and
incorporates a fail-safe input-output
relationship which keeps the outputs
high when the inputs are open.
16-Pin Plastic DIP
o and N PACKAGE
385
INPUTC
Preliminary Specification
Philips Components-Signetics Data Communication Products
Quad
high-~peed
differential line receivers
AM26LS32B
ABSOLUTE MAXIMUM RATINGS (Above which the usefullile may be impaired.)
SYMBOL
Vee
VIN
UNIT
V
RATING
PARAMETER
Enable voltage
7
7
Output sink current
50
mA
V
Power supply
V
Common mode range
±25
VTH
Differential input voltage
±30
V
TSTG
Storage temperature range
-55 to +150
°C
TsoLD
Lead soldering temperature (10sec.)
8JA
Thermal impedance
300
°C
°CIW
PACKAGE POWER DISSIPATION DERATING TABLE
PACKAGE
POWER DISSIPATION AT TA
= 25°C
DERATING FACTOR ABOVE TA
N
1,275mW
10.2mWI"C
0
1,262mW
10.lmWI"C
DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V ± 10% for AM26LS32BMX, Vee = 5.0V ±5% for AM26LS32BCX over operating temperature range unless otherwise specified.
LIMITS
SYMBOL
VTH
PARAMETER
Differential input voltage
TEST CONDITIONS
VOUT = VOL
orVOH
OV5. VCM 5.5V
Min
-100
-7V 5. VCM :5 +12V
-200
-15V:5 VCM 5. +15V
(one input AC ground)
RIN
Input resistance
liN
Input current (under test)
VIN = +15V
Other input -15V :5 VIN :5 +15V
liN
Input current (under test)
VIN = -15V
Other input +15V ,; VIN 5. -15V
VOH
Output HIGH voltage
VOL
Output LOW voltage
Max
+100
UNIT
+200
mV
6.0
mV
k.Q
2.3
rnA
-2.B
rnA
Vee = min.,
t.V IN = +1.0V
10H = -12mA
2.0
V
\fEN = O.BV
10H=-lmA
2.4
V
Vee = min.,
t.VIN = -1.0V
10H = 16mA
0.4
V
\fEN = O.BV
10H = 24mA
0.5
V
0.8
V
VIL
Enable LOW voltage
VIH
Enable HIGH voltage
VI
Enable clamp voltage
10
Off state (high impedance) output current
IlL
Enable LOW current
VIN = 0.4V
IIH
Enable HIGH current
II
Enable input HIGH current
Vee = max
2.0
Vee = min, liN = -I,BmA
Vcc= max
Vo= 2.4V
V
-1.5
V
20
flA
-20
IIA
-{).36
rnA
VIN =2.7V
20
VIN = 5.5V
100
IIA
IIA
Vo=0.4V
July 20, 1990
Tvp
386
Preliminary Specification
Philips Components--Signetics Data Communication Products
AM26LS32B
Quad high-speed differential line receivers
DC ELECTRICAL CHARACTERISTICS (Continued)
LIMITS
SYMBOL
TEST CONDITIONS
PARAMETER
Ise
Output short circuit current
Icc
Power supply current
Vee
Max
UNIT
-120
mA
70
mA
80
200
mV
1
3
V
Tvp
Min
-30
= max, ,WIN = +1V, VOUT = GND
Vee = max, all VIN = GND
outputs disabled
VHYST
Input hysteresis
Vloe
Open circuit input voltage
Vee
= 5.0V, VeM = OV
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
ROOM
TEMPERATURE2
TEST CONDITIONS
Typ
tpLH
Propagation delay, input to output
tSKEW
Propagation delay skew, tpLH - tpHl
Output enable time, EN to OUTPUT
= 50pF
Cl
(see test circuit)
tZH
tlZ
Output disable time, EN to OUTPUT
Cl
= 5pF
(see test circuit)
tHZ
Typ
Max
tpHL
tZl
COMMERCIAU
MILITARY'
UNIT
Max
21
26
ns
21
26
ns
3.0
4.0
ns
22
33
ns
16
22
ns
18
27
ns
18
27
ns
NOTES:
1. AC performance over the operating temperature range is guaranteed by testing defined in Group A, Subgroup 9.
2. Vce = 5V
~
TEST
~_P~0~IN~T~~__~_S_'~280QVCC
FROM OUTPUT _
ENABlE_
CL INCLUDES
PROBE AND JIG
NORMALLY
ALL DIODES
lN916 OR
'ZH
-l.SV
10PEN
-
1.3V'
-OV
'HZ
~
OUTPUT
-==1----------\=
;::::::::.-L
.
I
OPPOSITE
'
'PLH
~~~~~=\
TRANSITION
r-=:=:
'PHL
VOH
'3V
VOL
OV
~+"ov
~
-1.0V
PROPAGATION DELAY
1. Diagram fhovm tor Enable LOW.
2. 8, and 52 of load Circu~ are closed except where shown
3. Pulse Generator for All Pulses: Rate ~ 1.0MHz; Zo .. son; Ir .:; 2.5ns; If -.; 2.5ns
(Notes 1 and 3)
Figure 1.
387
YOH
~-1.5V
ENABLE AND DISABLE TIMES
(Notes 2 and 3)
SWITCHING TEST CIRCUIT
FOR THREE STATE OUTPUTS
13V
~ VOL
OUTPUT~~;......--l.-
NORMALLY
HIGH
July 20, 1990
1.3V
LOW S2 OPEN
lN3064
CAPACITANCE
NOTES,
~
tzL ~LZ 'ov
-- -4.SV
O.SV
INPUT
OUTPUT
UNDER TEST
l3.0V
O.SV
Philips Components-Signetics
Document No.
853-1430
MC145406
ECN No.
99588
EIA-232-D/V.28 driver/receiver
Date of Issue
May IS, 1990
Status
Product Specification
Data Communication Products
DESCRIPTION
The MC145406 is a silicon-gate CMOS
IC that combines 3 drivers and 3
receivers to fulfill the electrical
specifications of standards EIA-232-D
and CCITT V.28. The drivers feature
true TTL input compatibility, slew-rate
limited output, 300(1 power-off source
impedance, and output typically
switching to within 25% of the supply
rails. The receivers can handle up to
±25V while presenting 3 to 7kn
impedance. Hysteresis in the receiver
aids reception of noisy signals. By
combining both drivers and receivers in
a single CMOS chip, the MC145406
provides efficient, low-power solutions
for EIA-232-D and V.28 applications.
PIN CONFIGURATION
FEATURES
Drivers
• 300(1 power-off source impedance
Vcc
• Output current limiting
DOl
• TTL compatible
011
DO'
• Maximum slew rate = 30V/IJ.S
DI2
Receivers
• ±25V input voltage range over the full
supply range
• 3 to 7k(1 input impedance
• Hystersis on input switchpoint
R", Receiver
• Very low supply currents for long
battery life
APpLIcATIONS
• Modem interface
• Voice/data telephone interface
• Lap-top computers
• UART interface
ORDERING INFORMATION
TEMPERATURE RANGE
NOTE:
D_ Driver
General
• Operation is independent of power
supply sequencing
DESCRIPTION
o and N Packages
• ±5 to ± 12V supply range
ORDER CODE
16-Pin Plastic DIP
O°C to +70'C
MC145406N
16-Pin SOL
O°C to +70°C
MC145406D
388
Product Specification
Philips Components-Signetics Oata Communication Products
MC145406
EIA-232-DIV.28 driver/receiver
BLOCK DIAGRAM
'5k
RX
DO
5.4k
=
VSS
=
1.0V
1.BV
DRIVER
HYSTERESIS
300
01
LEVEL
TX
SHIFT
1.4V
=
Vss
PIN NO.
SYMBOL
1
Voo
PIN DESCRIPTION
Positive power supply. The most positive power supply pin, which is typically 5 to 12 volts.
8
Vss
Negative power supply. The most negative power supply pin, which is typically -5 to -12 volts.
16
Vee
Digital power supply. The digital supply pin, which is connected to the logic power supply (maximum +5.5V).
9
GNO
Ground. Ground return pin is typically connected to the signal ground pin of the EIA-232-0 connector (Pin 7)
as well as to the logic power supply ground.
2,4,6
RX" RX2, RX 3
Receive Data Input. These are the EIA-232-0 receive signal inputs whose voltages can range from +25 to
-25V. A voltage between +3 and +25 is decoded as a space and causes the corresponding 00 pin to swing
to ground (OV); a voltage between -3 and -25V is decoded as a mark and causes the 00 pin to swing up to
Vee. The actual turn-on input switchpoint is typically biased at 1.8V above ground, and includes 800mV of
hysteresis for noise rejeclion. The nominal input impedance is 5kU. An open or grounded input pin is interpreted
as a mark, forcing the 00 pin to Vee.
11,13,15
001,002,003
Data Output. These are the receiver digital output pins, which swing from Vee to GNO. A space on the RX
pin causes 00 to produce a logic zero; a mark produces a logic one. Each output pin is capable of driving one
LSTIL input load.
10,12.. 14
011,012,013
Data Input. These are the high-impedance digital input pins to the drivers. TIL compatibility is accomplished
by biasing the input switchpoint at 1.4V above ground. However, 5V CMOS compatibility is maintained as well.
Input voltage levels on these pins must be between Vee and GNO.
3,5,7
TX1, TX2, TX3
Transmit Data Output. These are the EIA-232-0 transmit signal output pins, which swing toward Voo and Vss.
A logic one ata 01 input causes the corresponding TX outputto swing toward Vss. A logic zero causes the output
to swing toward Voo (the output voltages will be slightly less than Voo or Vss depending upon the output load).
Output slew rates are limited to a maximum of30V/lls. When the MC145406 is off (Voo = Vss = Vee = GNO),
the minimum output impedance is 300U.
May 15,1990
389
Product Specification
Philips Components-Signetics Data Communication Products
MC145406
EIA·232·DIV.28 driver/receiver
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
Vee
Supply voltage
-0.5 to +6.0
V
Voo
Supply voltage
-0.5 to +13.5
V
Vss
Supply voltage
+0.5 to -13.5
V
VIR
Input voltage range
RX l -3 inputs
Dl l -3 inputs
(Vss -15) to (Voo + 15)
-0.5 to (Vee + 0.5)
V
±100
rnA
DC current per pin
Po
Power dissipation (package)
1.0
W
TA
Operating temperature range
o to +70
·C
TSTG
Storage temperature range
--S5 to +150
·C
Thermal impedance
N package
80
·C/W
"JA
D package
105
NOTE: This deVice contains protection circuitry to protectlhe Inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper
operation, it is recommended that the voltages at the DI and DO pins be constrained to the range GND,S VOI,S Voo and GND,S Voo,S Vee. Also,
the voltage at the RX pin should be constrained to ±25V, and TX should be constrained to Vss,S V TXl-3's Voo. Unused inputs must always be tied
to an appropriate logic voltage level (e.g., GND or Vee for DI, and Vss or Voo for RX).
DC ELECTRICAL CHARACTERISTICS Typical values are at TA = 0 to 70·C· GND= OV, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
UNIT
DC supply voltage
Voo
4.5
5to 12
13.2
V
Vss
-4.5
-5to-12
-13.2
V
Vee
4.5
5.0
5.5
V
Quiescent supply current (outputs unloaded, inputs low)
100
Voo=+12V
20
400
jJA
Iss
Vss =-12V
280
600
)lA
Icc
Vee = +5V
260
450
jJA
RECEIVER ELECTRICAL CHARACTERISTICS
Typical values are at TA = 0 to 70·C; GND = OV; Voo = +5 to + 12V; Vss = -5 to
-12V' Vee
= +5V -+5%
unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
UNIT
1.35
1.80
2.35
V
0.75
1.00
1.25
V
7.0
k!l
VON
Input turn-on threshold
RX l _3
VOFF
Input turn-off threshold
RX l _3
=VOL, Vee =5.0V ±5%
VOOl- 3 =VOH, Vee =5.0V ±5%
VON-VOFF
Input threshold hysteresis
RX l _3
Vee = 5.0V ±5%
0.6
0.8
RIN
Input resistance
RX l _3
(Vss-15V),S VRXl-3's (Voo+15V)
3.0.
5.0
VOH
High level output voltage
D01-3
IOH = -20jJA, Vee
4.9
5.0
V
IOH
3.8
4.4
V
VRXl-3
=--3V to (Vss-15V)1
Low level output voltage
VOL
VRXl - 3
=+3V to (Voo+15V)1
DOl - 3
VOOl-3
=+5.0V
=-lmA, Vee =+5.0V
IOL = +20jJA, Vee = +5.0V
0.005
0.1
V
IOL =+2mA, Vee
0.15
0.5
V
0.3
0.7
V
=+5.0V
IOL =+4mA, Vee = +5.0V
.
~~
1. This is the range of input voltages as specified by EIA-232-D to cause a receiver to be in the high or low logic state.
May 15, 1990
V
390
Product Specification
Philips Components-Signetics Data Communication Products
MC145406
EIA-232-DIV.28 driver/receiver
DRIVER ELECTRICAL CHARACTERISTICS
Typical values are at TA = 0 to 70°C; GND = OV; Vee = +5V ±5%, unless otherwise
specified.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
VIL
Digital input voltage
DI , - 3
Logic 0
V IH
Digital input voltage
DI ,- 3
Logic 1
liN
VOH
Input current
DI , -3
Vel 1-3 = Vee
Output high voltage
TX ,- 3
Vee = +5.0V, Vss = -5.0V
V e11 - 3 = Logic 0, RL = 3.0k!!
Output low voltage 1
VOL
Ise
TX ,_3
Vel1 - 3 = Logic 0, RL = 3.0kO
Off source resistance
Figure 1
TX ,_3
Output short-circuit current
TX ,_3
Min
Typ
Max
0.8
V
V
2.0
4.1
~
V
V
±1.0
3.5
UNIT
Vee = +6.0V, Vss = ~.OV
4.3
5.0
Vee = + 12.0V, Vss = -12.0V
9.2
10.4
V
Vee = +S.OV, Vss = -S.OV
-4.0
-4.3
V
Vee = +6.0V, Vss = ~.OV
-4.5
-S.2
V
Vee = + 12.0V, Vss = -12.0V
-10.0
-10.3
V
Voe = Vss = GND = OV, VW-3 = ±2.0V
300
TX, _3 shorted to GND2
0
±22
.60
mA
TX, _3 shorted to ± 15.0V3
mA
+100
Vee = + 12.0V, Vss = -12.0V
+60
NOTE:
1. The voltage specifications are in terms of absolute values.
2. Specification is for one TX output pin to be shorted at a time. Should all three driver outputs be shorted simultaneously, device power dissipation limits will be exceeded.
3. This condition could exceed package limitations.
SWITCHING CHARACTERISTICS
Typical values are at TA = 0 to 70°C; Vee = +5V ±S%, unless otherwise specified.
(See Figures 2 and 3)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
UNIT
ns
Drivers
tpLH
Propagation delay time
TX, -3
Low-to-High RL = 3kQ, C L = 50pF
300
500
IpHL
Propagation delay time
TX,_3
High-to-Low RL = 3kQ, C L = SOpF
300
SOO
ns
TX,_3
SR
Output slew rate
(minimum load)
RL = 7kO, CL = OpF,
Vee = 6 to 12.0V, Vss =~ to-12V
±6
±30
V/!'s
Output slew rate
(maximum load)
TX ,_3
RL = 7kQ, C L = 2500pF,
Vee = 12V, Vss=-12V
±3.0
V/!'s
Receivers (eL = 50pF)
tpLH
Propagation delay time
D01-3
Low-to-High
ISO
42S
ns
IpHL
Propagation delay time
DO, _3
High-to-Low
150
425
ns
tR
Output rise time
DO,_3
120
400
ns
IF
Output fall time
DO,_3
40
100
ns
May 15,1990
391
Product Specification
· Philips Components-Signetics Data Communication Products
EIA-232-DIV.28 driver/receiver
Vcc
'4
DI,
TX,
DI.
'0 DI3
ROUT
.!!tl.
I
=
3V
1'-----oV
IpLH
R~EEIVERS
50%
-
+3V
RX,-3
OV
t HL
tpLH
VOH
VOL
Figure 2. Switching Characteristics
DRIVERS
~
v
3V
TX,-3
-3
.
tSLH
SLEW RATE (SRI
-3V
tsHL
=-3V -3V
tSLH
3V - (-3V)
OR
tsHL
Figure 3. Slew Rate Characterization
May 15, 1990
APPLICATIONS INFORMATION
RECEIVERS
The MC 145406 has been designed to meet the
electrical
specifications
of
standards
EIA-232-D/CCITI V.2S and as such, defines
the elctrical and' physical interface between
Data Communication Equipment (DCE) and
Data Terminal Equipment (DTE). A DCE is
connected to a DTE using a cable that typically
carries up to 25 leads, which allow the transfer
of timing, data, control, and test signals. The
MC 145406 provides the necessary level
shifting between the TIUCMOS logic levels
and the high voltage levels of EIA-232-D
(ranging from ±3 to ±25V).
The job of an EIA-232-D receiver is to level-shift
voltages in the range of -25 to +25V down to
TIUCMOS logic levels (0 to +5V). A voltage of
between -3 and -25V on RX, is defined as a
mark and produces a logic one at DO,. A
voltage between +3 and +25V is a space and
produces a logic zero. While receiving these
signals, the RX inputs must present a
resistance between 3 and 7kQ. Nominally, the
input resistance of the RX,_3 inputs is 5.0kn.
DRIVERS
Figure 1. Power-Off Source Resistance
(Drivers)
tPHL
MC145406
As defined by the specification, an EIA-232-D
driver presents a voltage of between ±5 to ± 15V
into a load of between 3 to 7kn. A logic one at
the driver input results in a voltage of between
-5 to -15V. A logic zero results in a voltage
between ±5to ± 151/. When operating at ±7 to
±12V, the MC145406 meets this requirement.
When operating at ±5V. the MC145406 drivers
produce less than ±5V at the output (when
terminated). which does not meet the
EIA-232-D specification. However, the output
voltages when using a ±5V power supply are
high enough (around ±4V) to permit proper
reception by an EIA-232-D receiver. and can be
used in applications where strict compliance to
EIA-232-0 is not required.
Another requirement of the MC 145406 drivers
is that they withstand a short to another driver
in the EIA-232-D cable. The worst-case
condition that is permitted by EIA-232-D is a
± 15V source that is current limited to 500mA.
The MC 145406 drivers can withstand this
condition momentarily. In most short circuit
conditions the source driver will have a series
300n output impedance needed to satisfy the
EIA-232-D driver requirements.
This will
reduce the short circuit current to under 40mA
which is an acceptable level for the MC 145406
to withstand.
Unlike some other drivers, the MC 145406
drivers feature an internally-limited output slew
rate that does not exceed 30V/IlS.
392
The input threshold of the RX'_3 inputs is
typically biased at 1.SV above ground (GNO)
with typically 800mV of hysteresis included to
improve noise immunity. The 1.SV bias forces
the appropriate DO pin to a logic one when its
RX input is open or grounded as called for in
EIA-232-D specification. Notice that TIL logic
levels can be applied to the RX inputs in lieu of
normal EIA-232-D signal levels. This might be
helpful in situations where access to the
modem or computer through the EIA-232-D
connector is necessary with TIL devices.
However, it is important hot to' connect the
EIA-232-D outputs (TX,) to TIL inputs since
TIL operates off +.5V only, and may be
damaged by the high output voltage of the
MC145406.
The DO outputs are to be connected to a TTL
or CMOS input (such as an input to a modem
chip). These outputs will swing from Vee to
ground, allowing the designer to operate the
00 and 01 pins from the digital power supply.
The TX and RX sections are independently
powered by VDD and Vss so that one may run
logic at +5V and the EIA-232-D signals at± 12V.
POWER SUPPLY
CONSIDERATIONS
The Signetics MC 145406 is not sensitive to
power supply sequencing and does not require
the special protection circuitry of other designs.
Philips Components-Signetics
Document No.
853-- V IN :> 7.0
V
±15
V
SYMBOL
Vee
PARAMETER
V IN
Input voltage
VO UT
Output voltage
PD
Maximum power dissipation, T A ~ 25°C
(still-air}l
F package
1190
mW
N package
1420
mW
1040
mW
D package
TA
Operating ambient temperature range
TSTG
Storage temperature range
TSOLD
Lead soldering temperature (10see max)
o to +75
°C
--65 to + 150
°C
300
°C
NOTE:
1. Derate above 25°C, at the following rates:
F package at 9.SmW/oC.
N package at 11.4mWI"C.
D package at 8.3mW/oC.
November 14, 1986
394
Product Specification
Philips Components--Signetics Data Communication Products
MC1488
Quad line driver
DC AND AC ELECTRICAL CHARACTERISTICS
V+ = +9.0V ±1%, V- = -9.0V ±1%, TA = O°C to +75°C, unless otherwise
specifed All typicals are tor V+ = 9 OV V- = -9.0V and T A = 25°C'
LIMITS
SYMBOL
V 1H
VIL
PARAMETER
TEST CONDITIONS
Logic "0" input current
Logic "1" input current
VIN=OV
VIN = +5.0V
RL = 3.0k.(2
VOH
High level output voltage
VIN=0.8V
V+ = 9.0V
V-=-9.0V
V+ = 13.2V
V- = -13.2V
RL = 3.0kn
VOL
Low level output voltage
Min
VIN= 1.9V
V+ = 9.0V
V-=-9.0V
V+ = 13.2V
V- = -13.2V
Typ
Max
UNIT
-1.0
0.005
-1.6
10.0
mA
f1A
6.0
7.0
V
9.0
10.5
V
~.O
~.8
V
-9.0
-10.5
V
Isc+
High level output
short-circuit current
VOUT= OV
V 1N =0.8V
~.O
-10.0
-12.0
mA
Isc-
Low level output
short-circuit current
VOUT = OV
VIN = 1.9V
5.0
10.0
12.0
mA
ROUT
Output resistance
V+ = V- = OV
VOUT= ±2V
300
1+
Positive supply current
(output open)
1-
Po
Negative supply current
(output open)
Q
VIN=1.9V
V+ = 9.0V, V- = -9.0V
V+ = 12V, V- = -12V
V+ = 15V, V- = -15V
15.0
19.0
25.0
20.0
25.0
34.0
mA
mA
mA
V1N =0.8V
V+ = 9.0V, V- = -9.0V
V+ = 12V, V-=-12V
V+ = 15V, V- = -15V
4.5
5.5
8.0
6.0
7.0
12.0
mA
mA
mA
VIN= 1.9V
V+ = 9.0V, V- = -9.0V
V+ = 12V, V- = -12V
V+=15V,V-=-15V
-13.0
-18.0
-25.0
-17.0
-23.0
--34.0
mA
mA
mA
V1N = 0.8V
V+ = 9.0V, V- = -9.0V
V+ = 12V, V- = -12V
V+ = 15V, V- = -15V
-1
-1
-0.01
-15
-15
-2.5
mA
1190
1420
1040
mW
mW
mW
Maximum power dissipation, T A = 25°C (still--air)2
F package
N package
D package
f1A
f1A
tpo,
Propagation delay to "1"
RL = 3.0k.(2, C L = 15pF, T A = 25°C
275
560
ns
tpoo
Propagation delay to "0"
RL = 3.0k.(2, CL = 15pF, TA = 25°C
70
175
ns
tR
Rise time
RL = 3.0k.(2, CL = 15pF, TA = 25°C
75
100
ns
tF
Fall time
RL = 3.0kO, CL = 15pF, TA = 25°C
40
75
ns
NOTES:
1. Voltage values shown are with respect to network ground terminal. Positive current is defined as current into the referenced pin.
2. Derate above 25°C, at the following rates:
F package at 9.5mW/oC.
N package at 11.4mWFC.
D package at 8.3mWFC.
November 14, 1986
395
Product Specification
Philips Components-Signetics Data Communication Products
Quad line driver
MC1488
TYPICAL PERFORMANCE CHARACTERISTICS
1:
15
12
....
z
I I
~
\
MC.489A
t
1\
W
It:
It:
V+ ~9V'\
V- = -9V
\ \
:::>
<>
~
1/4MC14891
V+ =12V
V-=-12V
-3
!; -8
~ -9
0- '2
- -15
\
\
'\
\
\ 1\
T'UDTL
-:::r-p.-_
--L_
INTERCONNECTING
CABLE
,,
\
\ \
..l
~11b.
-
-16 -12 -8 -4
INTERNAL DATA
\
a
12
TERMINAL
EQUIPIIENT
MODEll
16
Vo OUTPUT VOLTAGE (V)
NOTE:
·Optional for noise filtering
Output Voltage and Current·Llmiting
Characteristics
AC LOAD CIRCUIT
APPLICATIONS
VIN~VOUT
3K
-=-
RS·232C Data Transmission
J'5pP
NOTE:
·CL includes probe and jig capacitance.
SWITCHING WAVEFORMS
TYPICAL APPLICATIONS
By connecting a capacitor to each driver output
the slew rate can be controlled utilizing the output current-limiting characteristics 01 the
MC 1488. For a set slew rate the appropriatecapacitor value may be calculated using the following relationship
+12V
IIOS
OUTPUT
V--,o-"V'-1o-u-'OV TO
~.4V
.K
C = Isc(t.T/t.V)
.OK
where C is the required capacitor, Isc is the
short-circuit current value, and t.V/t.T is the
slew rate.
-.2V
-=-
-.2V
DTLlTTL·to·MOS Translator
RS-232C specifies that the output slew rate
must not exceed 30V/,s. Using the worst-case
output shorH:ircuit current of 12mA in the
above equation, calculations result in a required capacitor of 400pF connected to each
output.
+12V
p---.---{;
-12V
HTL
OUTPUT
-O.7VTO
•• OY
-=-
DTLlTTL·to·HTL Translator
NOTE:
"" and l,: are measured between 10% and 90% of
the output waveform.
+1.2V
RTL
P--1~-"--{) ~UJt'~~
+3.7V
-'2V
+3.0V
-=-
DTLlTTL·to·RTL Translator
November 14, 1986
396
Philips Components-Signetics
853--0934
MC1489/MC1489A
ECN No.
91023
Quad line receivers
Date of Issue
October 20, 1987
Status
Product Specification
Document No.
Data Communication Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The MC1489/MC1489A are quad line
receivers designed to interface data
terminal equipment with data
communications equipment. They are
constructed on a single monolithic
silicon chip. These devices satisfy the
specifications of EIA standard
No. RS-232C.
• Four totally separate receivers per
package
0, F, N Package
• Programmable threshold
• Built-in input threshold hysteresis
• "Fail safe" operating mode
INPUT 1
1
VCC
RESPONSE
CONTROL 1
2
INPUT4
•
RESPONSE
CONTROL 4
OUTPUT 1
• Inputs withstand ±30V
RESPONSE
CONTROL 2
APPLICATIONS
INPUT.
RESPONSE
CONTROL.
• Computer port inputs
• Modems
• Eliminating noise in digital circuitry
• MOS-to-TrUDTL translation
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
14-Pin Plastic DIP
O°C to +70°C
MC1489N
14-Pin Plastic DIP
O°C to +70°C
MC1489AN
14-Pin Cerdip
O°C to +70°C
MC1489F
14-Pin Cerdip
O°C to +70°C
MC1489AF
14-Pin Plastic SO
O°C to +70°C
MC1489D
14-Pin Plastic SO
O°C to +70°C
MC1489AD
EQUIVALENT SCHEMATIC
r--._--.--o vcc
(114 OF UNIT SHOWN)
9K
5K
2K
10K
NOTES:
1. MC1489: RF" 10kn
2. MC"89A: RF = 2kn
L--~-~-~-~~-oGND
397
TOP VIEW
Product Specification
Philips Components-Signetics Data Communication Products
Quad line receivers
MC1489/MC1489A
VOLTAGE WAVEFORMS
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Power supply voltage
Vee
RATING
10
UNIT
V
VIN
Input voltage range
±30
V
lOUT
Output load current
20
rnA
Po
Maximum power dissipation,
T A = 25°C (still-air) 1
F package
N package
D package
1190
1420
1040
mW
mW
mW
o to +75
°C
-65 to +150
°C
TA
Operating temperature range
TSTG
Storage temperature range
NOTE:
1. Derate above 25°C, at the following rates:
F package at9.5mW/oC
N package at 11.4mW/oC
D package at8.3mW/oC
DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V ± 1%, O°C -< TA -< +75°C, unless otherwise specified. 1.2
MC1489
SYMBOL
MC1489A
PARAMETER
TEST CONDITIONS
Min
VIH
Input high threshold voltage
TA = 25°C, VOUT S 0.45V,
lOUT = lOrnA
1.0
VIL
Input low threshold voltage
TA = 25°C, VOUT« 2.5V,
lOUT = -O.5mA
0.75
VIN = +25V
VIN = -25V
VIN = +3V
VIN=-3V
+3.6
-3.6
+0.43
-0.43
+5.6
-S.6
+0.53
-0.53
VIN = 0.7SV, lOUT = -O.5mA
Input = Open, lOUT = -O.SmA
VIN = 3.0V, lOUT = lOrnA
2.6
2.6
3.8
3.8
0.33
5.0
5.0
0.45
,
liN
Input current
VOH
Output high voltage
VOL
Output low voltage
Ise
Output short-circuit current
lee
Supply current
Typ
V IN = 0.7SV
3.0
VIN = 5.0V
20
Max
Min
Typ
Max
UNIT
1.5
1.75
2.25
V
1.25
0.75
+8.3
-6.3
+3.6
-3.6
+0.43
-0.43
+5.6
-5.6
+0.S3
-O.S3
+8.3
-6.3
1.25
V
2.6
2.6
3.8
3.8
0.33
5.0
5.0
0.45
3.0
26
PARAMETER
TEST CONDITIONS
Min
MC1489A
Typ
Max
25
85
Min
Typ
Max
UNIT
25
85
ns
20
50
ns
110
175
ns
20
ns
Ip01
Input to output "high"
Propagation delay
RL = 3.9kn (AC test circuit)
tpOD
Input to output "low"
Propagation delay
RL = 3900 (AC test circuit)
20
50
tR
Output rise time
RL = 3.9kn (AC test circuit)
110
175
IF
Output fall time
RL = 3900 (AC test circuit)
9
20
9
NOTES:
1. Voltage values shown are with respect to network ground terminal. Positive current is defined as current into the referenced pin.
2. These specifications apply for response control pin = open.
October 20,1987
rnA
mW
Vee = 5.0V ± 1%, TA = 25°C, unless otherwise specified. 1, 2
MC1489
SYMBOL
V
V
V
rnA
26
20
Power dissipation
100
130
130
Po
V IN = 5.0V
100
NOTES:
1. Voltage values shown are with respect to network ground terminal. Positive current is defined as current into the referenced pin.
2. These specifications apply for response control pin = open.
AC ELECTRICAL CHARACTERISTICS
rnA
398
Product Specification
Philips Components-Signetics Data Communication Products
MC1489/MC1489A
Quad line receivers
AC TEST CIRCUIT
RESPONSE
CoNTROL
• OPEN
OUTPUT
I
VCC
15pF
INCLUDING
JIG AND PROBE
TYPICAL APPLICATIONS
lf4 MCl489!
TUDll
--r==L~)o-
114 MCl488
MCl489A
TUDlL
---r-
-=L~»--
i
INTERCONNECTING
CABLE
0-
I---+-------'L---+--<>I
TUDTL
INTERNAL DATA
TERr.tNAL
EQUIPMENT
I
=
-"1--
-<>(_ ~
114 MC1488
r----'J"" ~,
MOSLOGIC
I
L. _ _ _ _ .J
-II:>
I
114 MC14891
MC1489A
I.,..
I
6
MODEM
NOTE:
'Optional for noise filtering
RS-232C Data Transmission
October 20, 1987
~J"->
MOS-to-TTUDTL Translator
399
L~
Philips Components-5ignetics
NE5080
Document No.
High-speed FSK modem
transmitter
ECN No.
Date of Issue
December 1988
Status
Preliminary Specification,
Data Communication Products
DESCRIPTION
FEATURES,
The NE5080 is the transmitter chip, of a
two-chip set, designed to be the heart of
an FSK modem. (The NE5081 is the
receiver chip.) The chips are compatible
with the IEEE 802.4 standard for a
"Single-Channel" Phase-ContinuousFSK Token Bus." The specifications
shown in this data sheet are those
guaranteed when the transmitter is
tuned for the frequencies given in the
802 standard. However, both the
NE5080 and the NE5081 may be used
at other frequencies. The ratio of logic
high to logic low frequencies is normally
at 1.67 to 1.00 at any center frequency;
however, it can be varied externally.
(See AN1950.)
• Meets IEEE 802.4 standard
PIN CONFIGURATION
N Package
• Data rates to several Megabaud
• Half- or full-duplex operation
• ,Jabber function on-chip
JABBER FLAG 2
C~~~:~
APPLICATIONS
• Local Area Networks
• Point-to-point communications
15
3
VCC1 4
TRANSMIT 5
GATE
FSK OUTPUT 6
CABLEGND 7
• Factory automation
• Process control
TOP VIEW
• Office automation
ORDERING CODE
DESCRIPTION
TEMPERATURE
RANGE
ORDER CODE
16-Pin Plastic DIP
NE5080N
BLOCK DIAGRAM
R1
2.1K
C1
1~~~~o-:l..:.4/-1--1
r-::::-l----~-<>
JABBER FLAG
C4
L ____--to.r-;;;;:;;;-l-_~~6_~
TRANSMITTER
7 I
FSK OUTPUT
r-~~~~~~-j
11
400
-=-
CABLEGND
:~~~TO
Philips Components-Signetics Data Communication Products
Preliminary Specification
High-speed FSK modem transmitter
GENERAL DESCRIPTION
The NE5080 is designed to transmit high frequency asynchronous data on coaxial cable, at
rates from DC to 2M baud (see Note 1). The
chip accepts serial data and transmits it as a
periodic signal whose frequency depends on
whether the data is high or low.
The device is meant to operate at a frequency
of 6.25MHz for a logic high and 3.75MHz for a
logic low (see Note 2). The frequency is set up
by external trimming components; however,
the ratio of the high and low frequencies is set
internally and cannot be altered.
The FSK output can be turned off by use of the
transmit gate pin. When turned off, the transmitter has a high output impedance and the oscillator is disabled.
The length of time a transmitter can transmit
can be controlled by the use of the Jabber control pin (see description of Jabber Control Pin).
NE5080
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
VCC1
VCC2
Supply Voltage
V 1N
Input voltage range (Data, Gate)
PD
Power dissipation
TA
Operating temperature range
TJ
Maximum junction temperature
Tsm
Storage temperature range
TsoLD
Lead temperature (soldering, 10sec)
RATING
UNIT
+6
V
-0.3 to Vcc
V
800
mW
o to +70
"C
+150
"C
--<35 to +150
"C
300
"C
NE5080 PIN FUNCTION
PIN
FUNCTION
1
OSC 1: One end of the external capacitor used to set the carrier frequency.
2
Jabber Flag: This pin goes to a logic high if the transmitter attempts to
transmit for a longer time than allowed by the Jabber control function.
Jabber Control Pin
3
Jabber Control: Used to control transmit time. See note on Jabber function.
During the time the transmitter is transmitting,
this pin sources a current. This current can be
used to set the maximum time thatthe transmitter can be on. There are three options that can
be used:
1. Use the current to charge a capacitor.
When the voltage across the cap gets to
approximately 1.4 V, the transmitter will
turn off. A logic low applied to Pin 3 will
reset the Jabber function; an open collector output should be used for this purpose. A logic high applied to the pin will
disable the transmitter.
4
VCC1 : Voltage supply.
5
Transmit Gate: A logic flow on this pin will enable the transmitter; a logic
high will disable it.
2. Use to externally sense the current and
have external circuitry to control the
length of time the transmitter is on.
3. The pin can be tied to ground and is
then not active. Transmission is then controlled solely by the signal at the transmit
gate pin.
Jabber Flag Pin
6
Transmitter FSK Output
7
Cable Ground: The shield of the coax cable should be connected to this pin
and to Pin 11.
B
VCC2 : Connect to Pin 4 close to device.
9
No Connection
10
No Connection
11
Ground 2: Connect to Analog ground close to device.
12
OSC 3: A variable resistor between this point and ground is used to set the
carrier frequencies.
13
Ground 1: Connect to Analog close to device.
14
Data Input
15
Regulator Bypass: A bypass capacitor between this pin and VCC1 is
required for the internal voltage regulator function.
16
OSC 2: One end of a capacitor that is between Pin 1 and Pin 16 and
is used to set the carrier frequency.
This pin will go to a logic high when the Jabber
Control pin is used to shut off the transmitter. It
will latch and can be reset by applying a logic
low to the Jabber Control pin.
NOTES:
1. The NE5080 is capable of transmitting up
to 1M baud of differential Manchester
code at a center frequency of 5MHz.
2. Although the chip is designed to meet the
requirements of IEEE standard 802.4 (Token-Passing Single-Channel Phase-Continuous-FSK Bus), it can be used at other
frequencies.
December 1988
401
Preliminary Specification
Philips CompOlients-Signetics Data Communication Products
NE5080
High-speed FSK modem transmitter
DC ELECTRICAL CHARACTERISTICS V~1
2 = 4 75-5 25V TA = O°C to +70°C.
LIMITS
SYMBOL
Typ
Max
UNIT
f1
Output frequency (Logic high)
Data input >2.OV (See Note 1)
6:17
6.25
6.33
MHz
fa
Output frequency (Logic low)
Data input <0.8V (See Note 1)
3.67
3.75
3.83
MHz
1.0
VRMS
PARAMETER
TEST CONDITIONS
Min
Data input ?2.OV or ;$0.8V
Output Load = 37.50
0.5
100
Vo
Output amplitude
ROFF
Output impedance (gated off)
Transmit gate ;,2.OV
RON
Output impedance (gated'on)
Transmit gate sO.8V
37.5
Q
Transmit gate ;,2.OV or sO.8V
10
pF
Transmit gate ;,2.OV
2.OMHz sq. wave (TIL levels) input
1
mVRMS
'C o
Output capacitance
kQ
VF
Feedthrough
IJ
Jabber current
Transmit gate sO.8V
Input ;,2.OV or sO.8V
1.25
Icc
Supply current
V CC 1 connected to VCC2
75
f.lA
100
mA
0.8
40
-1.6
V
V
j.lA
mA
0.8
40
-1.6
V
V
j.lA
mA
0.4
V
V
0.8
V
V
Logic levels
Input high voltage
Input low voltage
VIN = 2.4V
VIN = O.4V
2.0
VIL
IIH
IlL
Data Input
Logic high
Logic low
Input current
Input current
VIH
V IL
IIH
IlL
Transmit gate
Logic high
Logic low
Input current
Input current
Input high voltage
Input low voltage
VG = 2AV
VG = OAV
2.0
IOH = -400j.lA
IOL = 4.0mA
2.4
Input high voltage
Input low voltage
2.0
VIH
VOL
Jabber flag
Logic high
Logic low
VIH
VIL
Jabber control
Logic high
Logic low
VOH
NOTE:
1. Tuned per instructions in AN 195.
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TO
FROM
TEST CONDITIONS
Min
Typ
2
0.1
Is
Setup time
Data in
Gate on
Figure 1
tA
Delay time
Output Ireq.
change
Data transition
Figure 2
ts
Delay time
Output
disabled
Gate off
Figure 3
Ie
Delay time
Output
disabled
Jabber control
Figure 4
Delay time
Jabber flag
Jabber control
Figure 5
to
Jabber control reset
Pulse width (Logic low)
December 1988
OA
UNIT
f.ls
150
ns
2
f.ls
100
ns
100
100
402
Max
ns
ns
Preliminary Specification
Philips Components-Signetics Data Communication Products
NE5080
High-speedFSK modem transmitter
TRANSMITIER - - - - - - . . . . ,
GATE
Ii.-
-:l.....Jfer-
JABBER CONTRO_l_ _ _ _
ts-i
I
I
VAUD DATA
Ln,----
DATA INPUT
=J fA~
I _ _=:I
_
-J
L.·........
I
"
fA
JABBER CONTROl_ _ _ _....J
I~I
I
I
JABBERFLAG~
I
I
OUTPUT
I
'0
"
Figure 5. Delay TIme, to
Figure 2. Delay Time, tA
Figure 3. Delay Time, tB
December 1988
1\f\f\}-
Figure 4. Delay TIme, te
Figure 1. Setup TIme, ts
DATA INPUT
OUTPUT
403
Philips Components-Signetics
Document No:
NE5081
High-speed FSK modem receiver
ECN No.
Date of Issue
December 1988
Status
Preliminary Specification
Data Communication Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The NE5081 is the receiver chip of a
two-chip set designed to operate as an
FSK modem (the NE5080 is the
transmitter chip). The chips are
compatible with the IEEE 802.4
standard for a "Single-Channel PhaseContinuous- FSK Token Bus." The
specifications given in this data sheet
are those guaranteed when the
receiver is tuned to the frequencies
given in the 802 standard. Ho\Vever. the
receiver will work at other frequencies.
• Meets IEEE 802.4 standard
N Package
• Data rates to several Megabaud
• Half- or full-duplex operation
• Low bit rate error (10- 12 typical)
18 INPUT BYPASS
APPLICATIONS
17 ANALOG GND
• Local Area Networks
16
15
• Point-to-point communications
VCC2 9
INPUT
LEVEL 10
FLAG
• Office automation
ORDERING INFORMATION
DESCRIPTION
11 DATA OUTPUT
TOP VIEW
TEMPERATURE RANGE
20-Pin Plastic DIP
~:T~~nON TIMING
14 ~N:v~~ DETECTION
13 INPUT LEVEL
DETECT
• Factory automation
• Process control
g':~E~TION TIMING
ORDER CODE
O'C to +70'C
NE5081N
BLOCK DIAGRAM
Note: Either
L1 orC7 is
variable,
14
~
lK
...
13
....-!:I------o
OUTPUT DATA
~~~------~'-~~~-I~~--~INPUT
DIGITAL GND
LEVEL FLAG
12
404
Preliminary Specification
Philips Components-Signetics Data Communication Products
NE5081
High-speed FSK modem receiver
ABSOLUTE MAXIMUM RATINGS
SYMBOL
Vcc ,
VCC2
TA
= 25"C
PARAMETER
Supply voltage
V,N
Input voltage range
100
Output (Data, Level detect)
Max sink current
Po
Maximum power dissipation, TA = 25"C, (still-air)'
N package
UNIT
+6
V
--{).3 to +Vcc
V
20
mA
1690
mW
o to +70
"C
-65 to +150
"C
Lead soldering temperature (10 sec. max)
300
"C
Max differential voltage between
analog and digital grounds
100
mV
TA
Operating temperature range
Tsm
Storage temperature range
T SOLO
RATING
NOTE:
1. Derate above 25"C as foHows:
N package at 13.5mWI"C.
DC ELECTRICAL CHARACTERISTICS
Vcc " 2 = 4.75-5.25V. External LC circuit tuned to 5MHz. Input level detect set at 16mVRMS,
TA = O"C +70"C
LIMITS
Max
Logic Low Frequency
External LC tuned to 5MHz
3.67
3.75
3.83
MHz
f,
Logic High Frequency
External LC tuned to 5MHz
6.17
6.25
6.33
MHz
INoL
Minimum Input Detect Level
Minimum input level that is detected as
carrier (See Note 2 in General Description)
5
50
mVRMS
VOL
VOH
VOH
Logic Levels:
Data Output
Data Output
Data Output
0.4
V
V
V
0.4
V
V
50
mA
PARAMETER
Icc
Supply Current
BER
Bit Error Rate
December 1988
Min
IOL = 4.0mA V,N" 16mVRMs Freq = fa
IOH = -4001JA V,N ,. 16mVRMS Freq = f,
IOH = -400!'A V,N < 5mVRMS Freq = fa
2.4
2.4
IOL = 4.0mA V'N = OVRMS
IOH = -4001JA V'N" 16mV
2.4
Input Detect Flag
VOL
VOH
TEST CONDITIONS
UNIT
Typ
fa
SYMBOL
Vcc
= 5.25V (Vcc, connected to VCC2)
V'N = 1.0VRMS Freq = f, or fo
Input Signal > 16mVRMs
maximum in-band noise = 1.6mVRMS
10-12
10-9
Preliminary Specification
Philips Components-Signetics Data Communication Products
High-speed FSK modem receiver
NE5081
AC ELECTRICAL CHARACTERISTICS (AN195 Figure 5 with a 100KHz lVp- p)
LIMITS
TO
FROM
TEST CONDITIONS
Delay TIme
Input Level
Detect Flag
Input On
Figure 1
Delay TIme
Input Level
Detect Flag
Input Off
Figure 1
tD
Delay TIme
Output
Enabled
Input On
Figure 2
tE
Delay TIme
Output
Disabled
Input Off
Figure 2
Required Delay
Carrier
Turn Off
Valid Data
End
SYMBOL
tB
Ie
PARAMETER
GENERAL DESCRIPTION
The N ES081 will accept an FSK-encoded signal
and provide the demodulated digital data at the
output. It is optimized to work at frequencies
specified in IEEE 802.4-Token-Passing Single-Channel Phase-Continuous-FSK Bus-(i.e.,
3. 75MHz and 6.25MHz). However, it will work at
other frequencies. 1
Its normal acceptable input signal level range is
from 16mVRMsto lVRMS. This can beadjusted. 3
The receiver will yield an undetected 'Bit Error
Rate" of 1(J1I or lower when receiving signals
with a 20dB signal-to-noise ratio. It has a maximum output Jitter of ± 40ns. 3
NOTES:
1. The receiver can be tuned to accept different frequencies by adjustment of the LC
circuit shown in Figure 7. However, the external components have been optimized
for 3. 75MHz and 6.25MHz. See 'Determining Component Values" for use at other
frequencies.
.
2. Input Level Detect
This is a method of turning off the output of
the receiver when the input signal falls beIowan acceptable level. This level is adjustable within the range given in the electrical specification section. The purpose of
this function is to minimize the effect of
noise on receiver performance and to indicate when there is an acceptable signal
present at the input. All specifications given in this data sheet are with the input level detection set at 16mVRMS.
3. Jitter (Definition)
This is a measure of the ability of the receiver to accurately reproduce the timing of
its FSK-coded digital input. The spec indicates the error band in the timing of a logic
level change.
December 1988
MIn
Typ
Max
UNIT
0.05
1
ILs
1.5
2.5
ILs
2
ILs
2.S
ILs
0.5
0.5
I.S
2
ILs
NE5081 PIN FUNCTION
PIN
FUNCTION
1
Vc c ,: Should be connected to the SV supply and Pin 9.
2
CT: One end of an external capacitor tthat is used to tune the receiver.
3
LT: One end of an indicator that is used to tune the receiver.
4
MT: The junction of the capacitor and inductor used for tuning the receiver.
S
6
7
8
F2}
F1 Pins 5, 6, 7, 8 are used for a low-pass filter to remove carrier
F3 harmonics from the data output.
F4
9
VCC2 : Connect to Pin 1 (see Pin 1 function) close to the device.
10
Input Level Flag: This pin is used to indicate when there is a signal at the
input that is greater than the level set by the input level detection circuitry.
A logic high indicates an input greater than the set level.
11
Data Output: Supplies I2L level data that corresponds to the FSK input
received.
12
13 and
14
Digital Ground: Should be connected to digital ground.
Input Level Detect: These pins are used to set the level of input signal
that the device will accept as valid.
15
Input Detection Timing: An external capacitor between this pin and ground
is used to determine the time from carrier turn-off to output disable.
16
Input Detection Timing: Same as Pin 15, except that a resistor goes
between this pin and ground. The values of the C and R depend on the
carrier frequency. The values given in this data sheet are for a SMHz carrier
center frequency.
17
Analog Ground: Connect to analog ground close to the device.
18
Input Bypass: A capacitor between this pin and ground is used to bypass
the input bias circuitry.
19
Input: The FSK signal from the cable goes to this pin.
20
No Connection.
406
Preliminary Specification
Philips Components-Signetics Data Communication Products
NE5081
High-speed FSK modem receiver
Fo. Fl
16mVRMS
INPUT_--Illlllllllllllllllillt--- 10-~
INPUTOUTPUT
LEVEL ____
DETECT
II
~
Figure 1. Delay TIme, 10, Ie
Fa. Fl
16mVRMS
INPUT---IIIIIIIIIIIIIIIIIIIIt--1- ---1 IIE ---1 lt
VAUO
DATA
-:li----DATA OUTPUT
10
Figure 2. Delay TIme, 10,
December 1988
IE
407
Philips. Components-Signetics
NE5170
Document No.
Octal line driver
ECN No.
Date of Issue
February 1987
Status
Preliminary Specification
Data Communication Products
PIN DESCRIPTION
DESCRIPTION
FEATURES
The NESll0 is an octal line driver which
is designed for digital communications
with data rates up to 100kb/s. This
device meets all the requirements of
EIA standards RS-232C/RS-423A and
CCITI recommendations V.l 01X.26.
Three programmable features:
(I) output slew rate, (2)·output voltage
level, and (3) three-state control (highimpedance) are provided so that output
characteristics may be modified to meet
the requirements of specific
applications.
• Meets EIA RS-232C/423A and CCITI
V.l0/X.26
N Package
He
• Simple slew rate programming with a
single external resistor
.0.1 to 1OV/!!S slew rate range
HJ
GI
Go
FO
FI
BO
• Highliow programmable voltage
output modes
EJ
Eo
01
• TIL compatible inputs
VCC
DO
ERlIBLE ,0
+MOOE
APPLICATIONS
GND
-MODE
NC
NC
• High-speed modems
• High-speed parallel communications
• Computer I/O ports
TOP VIEW
• Logic·level translation
FUNCTION TABLE
91
A Package
AI AO NC He HI GI
OUTPUT VOLTAGE (V)
ERl(B[E
RS-423A'
L
L
510.6V
5106V
? 9V
L
H
-5lo...f3V
-5lo--6V
5-9V
H
X
High-Z
High-Z
High-Z
Low Output Mode'
GO
Fo
FI
90
RS-232C
LOGIC
INPUT
High Oulput Mode'
Co
CI
EO
Vce
DO 9
ERlIBLE ,
---'1::rr.rr:rt"dr:l"1r:::n-:;f-
+MOOE
NOTES:
I. Vcc=+10VandVEE=-10V;RL=3kQ
2. Vee = +12V and VEE = -12V; RL = (3kQ
o Package
ORDERING CODE
TEMPERATURE RANGE
ORDER CODE
28-Pin Plaslic DIP
O·C to +70·C
NE5170N
28-Pin PLCC
O·C 10 +70·C
NE5170A
28-Pin SO package
O·C 10 +70·C
NE5170D
DESCRIPTION
NC
Ho
AO
Hj
At
GI
Go
FO
FI
Ilj
BO
Co
CI
OJ
EJ
Eo
8
VCC
+MODE
GND
-MODE
TOP VIEW
408
Preliminary Specification
Philips Components-Signetics Data Communication Products
NE5170
Octal line driver
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
Vee
Supply voltage and + MODE
15
V
VEE
Supply voltage and - MODE
-15
V
lOUT
Output current'
±150
mA
-1.5 to +7
V
Y'N
Input voltage (EiiBI5Ie, Data)
VOUT
Output voltage2
Minimum slew resistof!
±15
V
1
kO
Power dissipation
1200
mW
Po
NOTES:
1. Maximum current per driver. Do not exceed maximum power dissipation if more than one output is on.
2. High impedance mode.
3. Minimum value of the resistor used to set the slew rate.
DC ELECTRICAL CHARACTERISTICS
Vee = 10V ±10%; VEE = -10V ±10%; ±MODES = OV; RSL = 2kO, O°C" TA" 70°C, unless
otherwise specified.
UMITS
SYMBOL
VOH
VOL
PARAMETER
TEST CONDITIONS
Min
Max
V IN = 0.8V
RL= 3kQ2
5
6
RL= 45002
4.5
6
RL = 3kQ3, CL = 2500pF
Vee-3
VIN=2.0V
RL = 3kQ2
~
-5
RL ;' 45002
~
-4.5
Output high voltage
Output low voltage
RL = 3kQ3, CL = 2500pF
You
Output unbalance voltage
leE x
Output leakage current
V
V
VEE+3
Vee = IVEEI, RL = 45002
IVai = 6V, ENABLE = 2V or Vee = VEE ~ OV
UNIT
-100
0.4
V
100
flA
V,H
Input high voltage
V,L
Input low voltage
I,L
Logic "0" input current
Y'N = O.4V
I'H
Logic "1" input current
Y'N = 2.4V
0
los
Output short circuit current'
Vo=OV
-150
VeL
Input clamp voltage
I'N=-15mA
-1.5
Icc
Supply current
35
mA
-400
NO LOAD
NO LOAD
lEE
NOTES:
1. Maximum current per driver. Do not exceed maximum power dissipation if more than one output is on.
2. VOH, VOL at RL = 4500 will be ~ 90% of VoH, VOL at RL = 00.
3. High Output Mode; +MODE pin = Vee; -MODE pin = VEE; 9V S Vee S 13V; -9V ~ VEE ~-13V.
February 1987
V
2.0
409
-45
0.8
V
0
40
flA
flA
150
mA
V
mA
Preliminary Specification
Philips Components-Signetics Data Communication Products
Octal line driver
NE5170
AC ELECTRICAL CHARACTERISTICS Vee - + lOY- VEE - -10V' Mode - GND O°C';; TA';; 70°C
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Max
UNIT
5
Ils
tpHZ
Propagation delay output high to high impedance
RL = 450, CL = SOpF
or
RL = 3k; CL = 2500pF
tpLZ
Propagation delay output low to high impedanCe
RL =450, CL = 50pF
or
RL = 3k, CL = 2500pF
5
Ils
tPZH
Propagation delay high impedance to high output
RSL = 200k
RL = 450, CL = 50pF
or
RL = 3k, CL = 2500pF
150
I!S
tpZL
Propagation delay high impedance to low output
RSL= 200k
RL = 450, CL = 50pF
or
RL = 3k, CL = 2S00pF
150
Ils
SR
.'
RSL = 2k
8
12
RSL = 20k
0.8
1.2
RSL = 200k
0.06
0.14
Output slew rate'
NOTE:
SR: Load condition. (A) For RSL < 4k.Q. use RI. = 450Q; CL = 50pF: (8) for RSL > 4kQ use either RL = 450Q, CL = 50pF or RL = 3k.Q,
CL = 2S00pF.
AC PARAMETER TEST CIRCUIT AND WAVEFORMS
+1DY
Vcc
VOUTI----..--....---o OUTPUT
RSL
RSL
=
-10V
=
V~
3V~..
:
1
1
1
1
1
1-'
VOl
1 1Y I
1
VOUT
VOl -
-
-
1
VOl
1-, 'T----t-t
1
-+j
1
1
I
t-
--I
1pZL
NOTES:
1. See A{; electrical characteristics table for values of AS&... F\. and Ct.
2. V1Npulse: Frequency_ 1kHz, duty cycle .. 50%. Zou-r- 5O.Q, t,.-tt.s 10ns.
February 1987
410
I-
'PlH
I-
'PHl
V/lls
Preliminary Specification
Philips Components--Signetics Data Communication Products
NE5170
Octal line driver
length and data rate found in EIA standard
RS-423A. Approximations for cable length and
data rate are given by:
Max. data rate (in kbls) = 300/t
SLEW RATE PROGRAMMING
Slew rate for the NE5170 is set using a single
external resistor connected between the RSL
pin and ground. Adjustment is made according
to the formula:
RSL (in k.Q) =
Cable length (in feet) = 100xt
where t is the rise time in microseconds. The
absolute maximum data rate is 100kb/s and the
absolute maximum cable length is 4000 feet.
20
Slew Rate
where the slew rate is in V/jJ.s. The slew resistor
can vary between 2 and 200kn which gives a
slew rate range of 10 to O.IV/jJ.s. This adjustment of the slew rate allows tailoring output
characteristics to recommendations for cable
OUTPUT MODE PROGRAMMING
The NE5170 has two programmable output
modes which provide different output voltage
levels ..The low output mode meets the specifications of EIA standards RS-423A and
RS-232C. The high output mode meets the
specifications of RS-232C only, since higher
output voltages result from programming this
mode. The high output mode provides the
greater output voltages where higher attenuation levels must be tolerated. Programming the
high output mode is accomplished by connecting the +MODE pin to Vee and the -MODE pin
to VEE. The low output mode results when both
of these pins are connected to ground.
APPLICATION
1'"-----------,
1'"-----------,
+vl
-v
r
LJ
I
I 'TIE TO GROUND FOR
I RS232C
-L
=
'MODE PINS CONNECTED FOR
PROPER OUTPUT LEVEL
Figure 1. RS·232C/RS·423A Data Transmission
VCC
INPUTo-.---IoI__-4"'---IIf--~~
Figure 2. Input Stage Schematic
February 1987
411
Preliminary Specification
Philips Components-Signetics Data Communication Products
Octal line driver
NE5170
,---------If---II--.----II-o OUTPUT
Figure 3. Output Stage Schematic
February 1987
412
Philips Components-Signetics Data Communication Products
Preliminary Specification
Octal line driver
45
;(
.1 -
I-
g
I-
I••
z
c
l - f-
-20
-15
29 -
o·c
Icc
'=
~11
:10
::t12
-4OO~
g
'"
- l - - vE.-D·SV
-600 _,
Vee AND VEEM
Figure 4. Typical Icc and lEE vs Supply
Voltages
o
-4
0
-200
1
-400
LJ
I
6.0
50
-12
Figure 5. Typical Input Current vs Input
Voltage
800
;];~~~tlV; 1
I
I
T.-2S·C;
RL JkQ!,NPUT=2V
-
f-
I- f-I-
I- (:.I-
~J
100
e
70 G
c-
o
o
10
15
V+MODEM
Figure 6. Typical +MODE Current vs
+MODE Voltage
February 1987
20
-50
.l..lRL -450Q
, 4.0
50
70
Figure 11. Typical Output High Voltage
vs Temperature
10
r
VOl "iV' 1V'I LDjM,DE
I I I I I
T. =2S·C;'R... '=2~Q; I~PU~ =o1v
,-40
NO~
--
Vs· sOY, HlGH MODE
I
I
I
v~= ~9V;'RSl ~2~.t.6W~O~E-t
13
I I I I I
Vcc +O.5V
70
HGHMODE I- ' -
Va = ±13V, HIGH MODE
800
1
V~= 001311;
Figure 8. Typical Output Low Voltage
vs Load Current
(V~. ~1OJ.~ .2~Q)
'INOrAi- f-
4.5
I
-10
I-
Figure 10. Typical Output Low Voltage
vs Temperature
5.5
Vs. ::t9V,
-8 HIGH MOD.
-2
RL =-=4500-
-5.5
-1000
-2
200
~
50
'O\.(mAj
20
30
10
o
~-5.0
-6.0
Figure 7. Typical-MODE Current vs
-MODE Voltage
v I~ ~lOJ.o.J.TA~70lc
2kll.LDW MODE_ f-
-800
(Yo·
:!:13
....
-4.5
:10J. R~ =2l,,)
1 J I'j I
25
V~. ;9V;~
-200
I
70~C
::1:9
0.0
7O'·C
L
.9
0
~~
I
'1'
I
I
I
()
-5
I
I f
ooc
37
33
~
-10
701c
0
-4.0
V_MODEM
~~D~~~~~~Ir==2::lDAD
41
Jl
NE5170
-30
-20
-10
0
o
'OH(mA)
figure 9. Typical Output High Voltage
vs Load Current
413
0.1 !-i.l.J.Ll.LlJ.IlLJ..J..LlJ.I..J.1.WI...J.:>c.U
1
10
100
RSL(kQ)
Figure 12. Typical Slew Rate vs RSL
Philips Components-Signetics
Document No.
NE5180/NE5181
ECN No.
Octal differential line receivers
Date of Issue
February 1987
Status
Preliminary Specification
Data Communication Products
PIN DESCRIPTION
DESCRIPTION
FEATURES
the NE5l80 and NE5l8l are octal line
receivers designed to interface data
terminal equipment with data
communications equipment. These
devices meet the requirements of EIA
standards RS-232C. RS-423A.
RS-422A. and CCITT V.l O. V.ll. V.28.
X~26 and X.27. The NE5l80 is intended
for use where the data transmission rate
is up to 200 kb/s. The NE5l8l covers
the entire range of data rates up to
10 Mb/s. The difference in data rates for
the two devices results from the input
filtering of the NE5l80. These devices
also provide a failsafe feature which
protects against certain input fault
conditions.
• Meets EIA RS-232C/423A1422A and
CCITT V.l0. V.ll. V.28
N Package
• Single +5V supply-TTL compatible
outputs
Vec
HO
• Differential inputs withstand ±25V
H+
H-
• Failsafe feature
• Input noise filter (NE5l80 only)
B+
Go
BO
G+
G-
• Internal hysteresis
FS2
• Available in SMD PLCC
FO
F+
APPLICATIONS
'"---"'.-......J F-
• High-speed modems
• High-speed parallel communications
• Computer I/O ports
0+
Eo
DO
GND
E+
ETOP VIEW
• Logic level translation
FUNCTION TABLE
A Package
INPUT
V 10 > 200mV 1
V10 < -200mVl
FAILSAFE
INPUT
LOGIC
OUTPUT
X
H
X
L
OV
L
Vee
H
B- AO A+ A- vcc
He
H+
0+ DO GND E- E+
Eo
F-
Both inputs open or grounded
NOTE:
1. V10 is defined as the non-inverting terminal input voltage minus the inverting terminal input
voltage.
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
TOP VIEW
28-Pin Plastic DIP
O°C to +70°C
NE5180N
28-Pin Plastic DIP
O°C to+70°C
NE5181N
28-Pin PLCC
O°C to +70°C
NE5180A
28-Pin PLCC
··O°C to + 70·oC
NE5181A
414
Preliminary Specification
Philips Components-Signetics Data Communication Products
NE5180/NE5181
Octal differential line receivers
ABSOLUTE MAXIMUM RATINGS TA = +25°C
SYMBOL
PD
RATING
PARAMETER
Power dissipation
UNIT
800
mW
7
V
Vee
Supply voltage
VeM
Common-mode range
±15
V
VID
Differential input voltage
±25
V
FS.Vec
-- r-r-
ISINK
Output sink current
Failsafe voltage
IDS
Output short-circuit time
DC ELECTRICAL CHARACTERISTICS
50
mA
-0.3 to Vee
V
1
sec
,
,
VHl -.
VFS
VOUT
FS.GND
I-
_.+
-Figure 1. Vu. Vth • V H Definitions
-
Vee = +5V +5% DoC -< TA -< +70°C input common-mode range -+ 7V
NE5181
NE5180
SYMBOL
"'- VH2
PARAMETER
TEST CONDITIONS
Min
Max
Min
Max
UNIT
3
7
3
7
!ill
0.45
V
V
AIN
DC input resistance
3V "IVINI" 25V
V OFS
Failsafe output voltage
Inputs open or
shorted to GND
V TH
Differential input high4
threshold
VouT?2.7V,
10uT= -440flA
VII
Differential input low'
threshold
VOUT" 0.45V,
lOUT = 8mA
VH
Hysteresis4
FS = OV or Vee (See Figure 1 )
Vloe
Open-circuit input voltage
2
2
V
CI
Input capacitance
30
30
pF
VOH
High level output voltage
V ID = 1V, lOUT = -440flA
VOL
Low level output voltage
VID = -IV
I
0.45
0 " lOUT "SmA, Vlailsale = OV
I 0> louT> -400flA, Vlailsale = Vee
2.7
2.7
Rs=O'
0.2
0.2
Rs = 500'
0.4
0.4
As= 0'
-0.2
As = 500'
-0.4
50
-0.4
140
2.7
los
Short-circuit output current
VID = IV, Note 3
lee
Supply current
4.75V " Vee ,,5.25V, VID = -1 V; FS = OV
liN
Input current
Other inputs grounded
V
-0.2
140
50
V
2.7
10UT= 4mA2
0.4
0.4
10UT= 8mA2
0.45
0.45
20
100
20
100
TVIN = +10V
VIN = -10V
3.25
-3.25
mV
V
100
mA
100
mA
3.25
mA
--3.25
NOTES:
1. Rs is a resistor in series with each input.
'2. Measured after lOOms warm-up (at ODC).
3. Only 1 output may be shorted at a time and then only for a maximum of 1 second.
4. See Figure 1 for threshold and hysteresis definitions.
AC ELECTRICAL CHARACTERISTICS
Vee = +5V ±5% O°C" T A < +70°C
-
NE5180
SYMBOL
PARAMETER
TEST CONDITIONS
Max
UNIT
Propagation delay-low to high
CL =50pF, VID=±IV
500
100
ns
tpHL
Propagation delay-high to low
CL = 50pF, VID = ±IV
500
100
ns
fa
Acceptable input frequency
Unused input grounded, VID = ±200mV'
0.1
5.0
MHz
fr
Rejectable input frequency
Unused input grounded, VID = +500mV
February 1987
415
5.5
Max
NE5181
tpLH
NOTE:
1. VID = ±IV for NE5181.
Min
Min
NA
MHz
Preliminary Specification
Philips Components-Signetics Data Communication Products
Octal differential line receivers
FAILSAFE OPERATION
These devices provide 'a failsafe operating
mode to guard against input fault conditions as
defined in RS-422A and RS-423A standards.
These fault conditions are (1) driver in power-
NE5180/NE5181
off condition, (2) receiver not interconnected
with driver, (3) open-circuited interconnecting
cable, and (4) short-circuited interconnecting
cable. If one of these four fault conditions occurs at the inputs of a receiver, then the output
of that reCeiver is driven to a known logic level.
The receiver is programmed by connecting the
failsafe input to Vee or ground. A connection to
APPLICATIONS
VCC
+vU
-v
- --0 VFAILSAFE
'TIE TO GROUND
FOR RS-232C
RS-,232C/RS-423C Data Transmission
VCC
+Vl
-v
r
VFAILSAFE
LJ
RS-422A Data Transmission
AC TEST CIRCUIT
+IV
VOLTAGE WAVEFORMS
1------)--~
n
-,v.J
February 1987
L
416
Philips Components-8ignetics Data Communication Products
Preliminary Specification
Octal differential line receivers
Vee provides a logic "I" output under fault
conditions. while a connection to ground provides a logic "0". There are two failsafe pins
(FSI and FS2) on the NESI80 or NESI81
where each provides common failsafe control
for four receivers.
NE5180/NE5181
Vcc
INPUT
0----,
OUTPUT
Vee
=,1.4V
RI
R2
RS-232 FAILSAFING
The internal failsafe circuitry works by providing a small input offset voltage which can be
polarity-switched by using the failsafe control
pins. This offset is kept small (approximately
80mV) to avoid degradation of the ±200mV
input threshold for RS-423 or RS-422 operation. If the positive and negative inputs to any
receiver are both shorted to ground or open
circuited. the internal offset drives that output
to the programmed failsafe state. If only one
input open circuits (as may be the case for
RS-232 operation). that input will rise to the
"input open circuit voltage" (approximately
700mV). Since this is much greater than the
200mV threshold. the output will be driven to
a state that is independent of the failsafe programming. Failsafe programming can be
achieved for non-inverting single-ended
applications by raising or lowering the unused
input bias voltage as shown in Figure 2. For
VSIAS '" 1.4. an open (or grounded) INPUT
line will be approximately 700mV (OV) and the
output will failsafe low. If the resistor divider is
not used and VSIAS is connected to ground.
the output will failsafe high due to the internal
failsafe offset for the IN PUT grounded and the
700mV "open circuit input voltage" for the INPUT open circuited. Similar operation holds
for an inverting configuration. with VSIAS
applied to the positive input and VFS = ground.
NOTE:
Two silicon diodes may be used in place of A2.
Figure 2. Single-Input Failsafe Programming
Vcc
Figure 3. Differential Input Stage
Vcc
Vcc
INPUT FILTERING (NES180)
75
The NESI80 has input filtering for additional
noise rejection. This filtering is a function of
both signal level and frequency. Forthe specified input (S.SMHz at±SOOm V) the input stage
filter attenuates the signal such thatlhe output
stage threshold levels are not exceeded and
no change of state occurs at theoutpul. As the
signal amplitude decreases (increases) the
rejected frequency decreases (increases).
VOUT
'---~--<>---
0.50
0.58
--
I-I--
...-:- ~
~
~
"1
I-
1.0
~
~
~
~
VC~·t25~
0.9
0.8
I'A ~
1
70 C_
25'C
0.7
1
0.8
0.3
0.54
0.2
0.52
0.1
0.50
o
4.75
5.25
5.5
. f-
W
0.5
l.a r'-o.c r- f-
.$.6.4
0.58
4.5
'This graph applies for all receiver inputs,
provided that the opposite polarity input of
the amplifier being measured is grounded.
olc
...;.r:~
l- I-"
~
Figure 8. Typical Low Level Output
Voltage vs Output Current
Figure 7. Typical High Level Output
Voltage vs Output Current
0.70
~
'oLemA)
'OH(rnA)
Figure-6. Typical Supply Current vs
Supply Voltage
J...-:: ::::::::
P:::: /: V
25'C
~ 0.4
·\·c
o·C
'.75
1
0.5
'.0
I--: ~
.....l:S; I::::::
'-"""
V1o -1V.
V1D =lV
7O~C
25:,.c
1
_~cc=4.75V
VCC ·4.75V
~!I':~~
lY
II
J,
-1
0
"
1
2
3
4
5
5
7
8
Figure 11. Typical FS Input Current
FS Applied Voltage
Figure 10. Typical V,oc vs Vcc
9
VFSM
vS
Figure 9. Input Current vs Input
Applied Voltage'
~§"=~~V,
vcc· sv.
FS=OV.
f=lOOkHz,
f=lOOkHz,
°
<'TA <70 DC,
~L =~PF
o,,'TA< 70°C,
c~ -50pF
-
v l1v r- f,D ...
\
15V
H,. .
VOL
\ \
~
-
l-
YOOiV -
t-
/~500;"V
I
I
L \
I-
=500m~- I-
=1oolv -
V ID - =1V
1\ \
1.5 V
\
1
1 1
200
400
600
BOO
",HLln.)
Figure 12. NE5180: Propagation Delay
at Various Input Amplitudes
February 1987
418
200
400
600
BOO
tPlH (ns)
Figure 13. NE5180: Propagation Delay
at Various Input Amplitude
Philips Components-Signetics
Section 4
Local Area Network
Products
Data Communication Products
INDEX
NE502A
NE8392A
NE86950
Ethernet Encoder/Decoder
Coaxial Transceiver Interface for Ethernet/Thin Ethernet.
EtherStar™ Ethernet Controller .. . .
. ......... .
421
437
446
Philips Components-Signetics
Document No.
853-1449
NE502A
ECN No.
99960
Ethernet encoder/decoder
Date of Issue
July 11, 1990
Status
Product Specification
Data Communication Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The NE502A is an EtherneF"
encoder/decoder designed to meet all
the requirements of the IEEE 802.3 and
EthernetlThin Ethernet specification and
fabricated with high-speed ECl and
Schottky TTL technology.
• Full Ethernet II, IEEE 802.3 10base5
and 1Obase2 compatibility
The encoder converts serial binary data
into complementary Manchester code.
The decoder ccnverts Manchester code
into binary data and synchronous clock
signals. The decoding method is a
digital phase locked loop with dual
bandwidth which allows both fast lockon and low jitter. Typical acquisition is
eight bits or better. A key feature of the
decoder design is its capability to
recover distorted input signals. The
NE502A is packaged in a standard
24-pin ceramic DIP.
• Carrier detection
The NE502A is normally part of a 3-chip
set that implements a complete
Ethernel/Thin Ethernet interface for a
DTE. The other chips are an Ethernet
Data Link Controller (EDlC) such as the
NE86950 and a coaxial transceiver
interface (CTI) such as the NE8392A.
• Manchester encode and decode
v,e
• level conversion: transceiver level
tolfrom TTL level
COL-
TXDATA+
RXDATA-
• Dual bandwidth phase locked loop:
allows fast acquisition
• loopback "CONFIDENCE" test
feature
RXDATA+
OCIJNK
LBC
TCKN
• Built-in clock generator
• Small external parts count:
• High-speed ECl and Schottky TTL
technology
• Single power supply: +5V
• Low power dissipation: 750mW typo
• 24-pin standard dual in-line ceramic
package
APPLICATION
• Terminals
• File servers
• Print servers
ORDERING INFORMATION
DESCRIPTION
COL+
• large distortion recovery: ±20ns
• Workstations
TEMPERATURE RANGE
24-Pin Ceramic DIP
F Package
ORDER CODE
NE502AF
'Ethernet™ is a Trade Mark of Xerox Corp., USA
421
XCD
XCOL
GND
RCKN
Product SpecifiCation
Philips Components-Signetics Data Communication Products
NE502A
Ethernet encoder/decoder
BLOCK DIAGRAM
r----------------------------------------j
I COLLISION LEVEL CONVERTER
I
1
I
I
1
2
I COL.±
I
I
I
-----r~NCODER
,..
LEVEL
CONVERTER
(RECEIVER)
XCOL
1
1
f.-
----------
1
1
- - - - - - - - - - - - - - - - - - - - - - -I
I
1
I
I
TCKN
TXDATA..
I
I
I
I
I
I
2
f--
TXD
ENCODER
=f~
TEN
I+-
r------i------------
I
RC
I
I
I
I
C
I
f-- - - - - - I DECODER
I
I
I
I
I
I
LEVEL
CONVERTER
(DRIVER)
OSC.OUT
1
100 MHz
OSCILLATOR
I
...
2
I
~
1
RCKN
DIGITAL
PLL
NC
1
1
RXDATA±
OSC.REF
5~
=i= -~
-L------i------------
I
1
1
OSC.lN
-
1
---------
LEVEL
CONVERTER
(RECEIVER)
I+-
RXD
DECODER
I+--
1
1
1
1
I
I
-.
XCD
STATE
REGISTER
1
1
1L
__
-----
---------
--------------------LBC
.
lJClJI'IK
0
July 11, 1990
422
_I
r-:;b. 1
1 OSCILLATOR
1
1
1
1
1
1
1
1
1
I
1
I
I
Product Specification
Philips Components-Signetics Data Communication Products
NE502A
Ethernet encoder/decoder
PIN ASSIGNMENT TABLE
PIN NO.
SYMBOL
PIN NAME
1/0
FUNCTION
LEVEL
Power Group
12
GND
Power supply
I
-
Ground
24
Vee
Power supply
I
-
+5V DC power Supply
Cable Group
18
19
RXDATA+
RXDATA-
Receive data pair
I
I
ECl
differential
Interfacing to receive pair of the transceiver.
20
21
TXDATA+
TXDATA-
Transmit data pair
0
0
ECl
differential
Interfacing to transmit pair of the transceiver.
22
23
COl+
COl-
Collision presence pair
I
I
ECl
differential
Interfacing to collision presence pair of the transceiver.
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
EDlC Group
8
TEN
Transmit encode enable
I
9
TXD
Transmit serial data
I
10
TCKN
Transmit data clock
0
11
RXD
Receive serial data
0
13
RCKN
Receive data clock
0
14
XCOl
Collision presence
0
15
XCD
Receive carrier detect
0
16
lBC
loopback command
I
Input for encoding and TXDATA± enable.
Input for transmit data to be encoded onto the Ethernet coax.
Stable 10MHz clock output for transmit bit stream.
Output of received and decoded bit stream.
Clock output to strobe RXD.
Duplication of the collision presence pair (COl±).
Carrier detect function of the decoder.
Input to command the NE502A to operate in loopback mode.
Oscillator Group
4
5
6
OSC.OUT
OSC.IN
OSC.REF
0
Oscillator pins
I
ECl
Pins for direct connection of discrete oscillator components.
-
ECl
Pins for direct connection of a capacitor.
0
Others
1
2
RC
C
3
NC
Non-connection (Pll
test)
0
ECl
7
RESET
FF test
I
TTL
Input pin to initialize flip-flops for testing purpose only.
I
TTL
Input to select DC/AC coupling of transceiver cable pairs.
17
DCLINK
July II, 1990
Capacitor pins
DC/AC coupling select
for tran sceiver pairs
-
Output pin for Pll testing purpose only.
423
Philips
Components~ignetics
Product Specification
Data Communication Products
NE502A
Ethernet encoder/decoder
ABSOLUTE MAXIMUM RATINGS'
RATING
UNIT
Vee
Supply Voltage
~.3t07.0
V
VITIL
TIL Level Input Voltage
~.3t07.0·
V
VIR
Receiver Input Voltage
VODV
Driver Output Voltage
Vee (max)
V
IODV
Driver Output Current
-40.0 to 0
rnA
Vlose
Oscillator Input Voltage
Vec-4 to Vee and < -0.3
V
loose
Oscillator Output Current
-2O.0toO
rnA
Top
Operating Temperature
-25 to 100
°C
TSTG
Storage Temperature
-65 to 125
°C
SYMBOL
PARAMETER
~.3to
Vee + 0.3
V
NOTE:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
Vee
Supply Voltage
RATING
IOH
TIL High Level Output Current
~.4mAtoOmA
1m
TTL Low Level Output Current
OmA to SmA
VIR
Receiver Input Voltage
RLD
Driver Terminator
RDLD
Differential Load
RLOse
Oscillator Terminator
330n and 33pF parallei1
100MHz ± 0.01%2
OV to Vee
270n
7sn
fXTAL
Crystal for Oscillator
CTX
Capacitor placed between C and RC pins
Lose
LC Tank Constant
Case
UNIT
5.0V±5%
I
I
OoC to +700 C
470pF
Inductance
0. 151lH
Capacitance
33pFl
NOTES:
1. The values of the oscillator capacitors may have to be tuned for a particular components layout. Both capacitors should be adjusted for
maximum voltage at OSC.IN. However, once the correct values are determined for that layout, any more tuning will not be necessary for·
each board.
2. 5th overtone series resonant.
July 11, 1990
424
Product Specification
Philips Components-Signetics Data Communication Products
NE502A
Ethernet encoder/decoder
DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
VALUE
SYMBOL
PARAMETER
Vcc (V)
Min
Typ
Max
UNIT
V
2.0
V IH
High level input voltage'
V IL
Low level input voltage'
VIC
Input clamp voltage'
IIL=-IBmA
4.75
-1.5
VOH
High level output vOltage2
10H = --{).4mA
4.75
2.7
VOL
Low level output voltage 2
10L = BmA
4.75
0.5
V
IIH
High level input current'
V IH = 2.7V
5.25
20
~
IlL
Low level input current'
VIL = 0.4V
5.25
-100
los
Output short current'!
Vo=OV
5.25
-100
-20
~
mA
V IHD
High level differential input voltage3
VIR+ - VIR-, ONINK = OV
VILD
Low level differential input voltage 3
VIR+ - VIR-, ONINK = OV
--{).2
V
V IHD
High level differential input voltage4
VIR+ - VIR_, ONINK = 4.5V
V ILD
Low level differential input voltage 4
VIR+ - VIR-, ONINK = 4.5V
--{).4
V
VIHD
High level differential input voltage5
VIR+ - VIR-, UClJ1iIK = 4.5V
VILD
Low level differential input voltage 5
VIR+ - VIR-, ONINK = 4.5V
IIHR
High level input current!
VIR = 5.25V,
O.B
UClJ1iIK = OV
VIR = OV, UClJ1iIK = OV
V
V
0.2
--{).05
V
V
0.2
5.25
Low level input current!
VOHTX
High level output voltage6
5.0
4.1
VOLTX
Low level output voltage 6
5.0
3.3
VOHD
High level differential output voltageS
Vo+ - Yo-; ONINK = OV
Vo+ - Vo-, ONINK = OV
5.25
V
0.7
mA
mA
0.55"
V
V
1.0
VOLD
Low level differential output voltage6
V BB
Oscillator reference voltage7
IIHO
High level input currentB
VIH = 4.1V
5.0
VOHO
High level output voltage9
OSC.IN is open
5.0
4.15
YOLO
Low level output voltage 9
V IOSC = 4.1V
5.0
3.3
RRC
RC internal resistor
VRC = 0.5V
0.5
Icc
Power supply current
All signal pins are open.
5.25
to
to
to
to
to
--{).2
-1.5
-1.0
5.0
--{).55
V
3.7
150
25
50
V
100
kn
220
rnA
TTL input pins. (TEN, TXD, LBC, ONINK and RESET)
TTL output pins. (TCKN, RXD, RCKN, XCOL and XCD)
COli and RXDATA±.
RXDATA± while XCD output is low (idle state) and Cali.
RXDATA± while XCD output is high.
425
~
V
Applicable to TXDATA±. These pins are connected to ground through 270n resistors. A 7Bn resistor is placed between these pins.
Applicable to OSC.REF.
Applicable to OSC.IN.
Applicable to OSC.OUT. This pin is connected to ground through a 330n resistor.
July II, 1990
V
V
IILR
NOTES:
1. Applicable
2. Applicable
3. Applicable
4. Applicable
5. Applicable
6.
7.
B.
9.
CONDITION
Product. Specification
Philips Componenls-Signetics Data Communication Products
NE502A
Ethernet encoder/decoder
AC CHARACTERISTICS
Recommended operating conditions unless otherwise noted. Vee = S.OV. Transmit Timing (Figure 22)
VALUE
SYMBOL
PARAMETER
CONDITION
Min
Typ
Max
UNIT
100.01
ns
Transmit timing (Figure 1)
lcnc
TCKN cycle time
(Figures 2,3)
99.99
100.00
IWlTC
TCKN low time
(Figures 2,3)
40
50
IWHTC
TCKN high lime
(Figures 2,3)
40
50
ns
IpDTX
TXDATA± encode time
(Figures 2,3)
95
ns
ns
ns
tRTX
TXDATA± output rise lime
(Figures 5,6)
2.0
IFTX
TADATA± oulpul fall lime
(Figures 5,6)
2.0
ns
tnx
TXDATA-Iow level hold time
3
jls
IRlTX
TXDATA- idling rise time
= 470pF lJCOlIlK = Vee (Figures 5,6)
CTX = 470pF, (20% - 80%), lJCOlIlK = Vcc
0.8
jls
\sUTX
TXD, TEN setup time
(Figures 4)
20
ns
IHDTX
TXD, TEN hold time
(Figures 4)
0
ns
CTX
(Figures 5,6)
Receive timing (Figures 2, 3)
100.01
teTRC
RCKN cycle time in idle
(Figures 2,3)
99.99
100.00
IWlRC
RCKN low time
(Figures 2,3)
35
50
tWHRC
RCKN high lime
(Figures 2,3)
35
50
ns
tpHlRC
RCKN delay lime
(Figures 2,3,7)
120
ns
IplHCD
XCD ON delay time
(Figures 2,3,7)
80
IpHlCD
XCD OFF delay time
(Figures 2,3,7)
230
ns
IHDlCD
XCD low hold lime
(Figures 2,3)
10
ns
IHDHCD
XCD high hold time
(Figures 2,3)
120
ns
\sUlCD
XCD Low selup lime
(Figures 2,3)
80
ns
tSURXD
RXD setup lime
(Figures 2,3)
20
60
ns
IHDRXD
RXD hold time
(Figures 2,3)
10
20
ns
0
ns
ns
110
ns
Loopback timing' (Figure 4)
IpGlBC
LBC receiving data purge time
(Figures 2,3,4)
230
ns
tAcLBC:
LBC receiving data accept lime
(Figures 2,3,4)
80
ns
IpHlTRu
DATA Ihrough lime
(Figures 2,3,4)
280
ns
IWTEN
TEN wail lime
(Figures 2,3,4)
0
ns
Collision timing (Figure 5)
IplH
COL 10 XCOL Propagation Delay Time
IpHl
COL 10 XCOL Propagation Delay Time
lJCOlIlK = OV, (Figures 2,3,7)
lJCOlIlK = OV, (Figures 2,3,7)
9
30
ns
11
30
ns
NOTE:
1. In Loopback mode operation, COL± and RXDATA± inputs are ignored, TXDATA+ and XCOL are high level, and XCD, RCKN and RXD
lunctions are in Ihe same manner as a normal receive operation.
July 11, 1990
426
Product Specification
Philips Components---Signetics Data Communication Products
NE502A
Ethernet encoder/decoder
FUNCTIONAL DESCRIPTION
SIGNAL PIN DESCRIPTION
The NE502A has five major functions:
encode, decode, collision signal conversion,
master clock generation and loopback.
Cable Group
Encode
The encoder section of the NE502A is a
simple circuit which performs an appropriate
exclusive-OR between the transmit clock and
transmit data using latches to reduce the
skew of TXDATA± outputs. The encoder
sends the transmit clock (TCKN) to an
Ethernet Data Link controller (EDLC) such as
the NE86950. An encode enable signal
(TEN) and data (TXD) are then returned from
the EDLC.
Decode
The decoder performs three functions. First,
it decodes data arriving at the RXDATA±
inputs and passes it to the EDLC via the RXD
output. Second, it signals to the EDLC that
receive carrier is present by asserting the
XCD output. Third, the receive clock is
recovered and passed to the EDLC via the
RCKN output. The RCKN is inhibited for 6 or
7 cycles during PLL acquisition, but, upon
restarting, has the correct phase relationship
with the recovered data.
The decoder PLL is a digital phase locked
loop with excellent distortion handling
capability. It is designed to recover data from
±20ns of jitter.
Collision
In the event of a collision, the 10MHz collision
signal sent from the transceiver to the COL+
inputs is converted to a TTL 10MHz signal at
the XCOL pin. The latching and timing functions for this signal are provided in the EDLC
(NES6950).
Master Clock Generation
The oscillator generates a 100MHz master
clock for the encoder and decoder.
Discrete oscillator components and a crystal
are directly connected to the provided
oscillator pins. The oscillation frequency
must be 1OOMHz with a tolerance of less than
±0.01 % to meet the IEEE S02.3 specification
because one tenth of the oscillation
frequency is the transmit bit rate.
Loopback
A loopback input (LSC) is provided to allow
all encoding and decoding functions to be
exercised without using the transceiver cable.
During loopback operation, the encoded data
is routed internally to the decoder, while
transmit outputs remain idle and the receive
and collision inputs are ignored.
July 11, 1990
RXDATA± (receive serial data pair, inputs):
These are the inputs to the decoder. They
receive Manchester coded signals from the
transceiver. The input circuit is a differential
receiver and with a common mode voltage
range of 0 to Vee. The differential receiver
has two modes of operation: DC coupled
operation and AC coupled operation, which
are selected by the UClJIiIR: input.
In DC coupled operation (UClJIiIR: is low), the
differential squelch threshold is typically -OV.
In AC coupled operation (lJCOliIK is high),
the differential squelch threshold is typically
-O.2V. This is the operating mode for coaxial
Ethernet where an isolation transformer is
used between the encoder/decoder and the
transceiver.
In both DC and AC coupled operation, the
differential zero crossing threshold for the
received signal is OV in order to minimize
receive distortion. When RXDATA± are idle,
the RXD output is a TIL high.
TXDATA± (transmit data pair, outputs):
These are the outputs of the encoder. They
transmit Manchester coded signals to the
transceiver.
The driver output circuits are emitter followers
and require pull-down resistors of 270Q.
They can drive a transceiver cable with
differential impedance of 7SQ.
The differential transmitter outputs TXDATA±
are normally connected directly to the primary
of an isolating pulse transformer. In idle state
they have a low offset voltage in order to
minimize DC current through the transformer.
When entering the idle state, at the end of a
transmit packet, the transmitter outputs
gradually return to a differential voltage of OV
across the transformer primary in order to
prevent undershoot glitches at the
transformer secondary. The returning time
constant is determined by an external
capacitor connected between the RC and C
pins.
COL± (collision presence pair, inputs): This
pair of inputs receive a 10MHz signal from
the transceiver when a collision is detected.
The input circuit has the same common mode
voltage range as the RXDATA± inputs. It
also operates in DC or AC coupled modes,
depending on whether UClJIiIR: is low or high
respectively, with the same differential
squelch thresholds of OV or -O.2V,
respectively.
427
Unlike the RXDATA± inputs, the zero
crossing threshold is -O.2V even when COL±
are receiving a collision present signal.
When COL± are idle, the XCOL output is a
TIL high.
EDLC Group
TEN (transmit encode enable, input): This is
an input to the on-chip Manchester encoder
and enables the TXDATA± pair. An input
high enables the TXDATA± pair; an input low
makes the TXDATA± pair idle (high).
TXD (transmit serial data, input): This is an
input to the on-chip Manchester encoder and
provides the data to be encoded.
Serial binary data must be supplied to this
input synchronously with the falling edge of
TCKN (transmit data clock).
This input is enabled when TEN (transmit
encode enable) is high.
TCKN (transmit data clock, output): A
1OMHz clock output for the transmit serial
binary data. This is a stable clock of onetenth of the master clock frequency. See
TXD (transmit serial data) description.
RXD (receive serial data, output): This is an
output of the on-chip Manchester decoder
and provides decoded data to the EDLC.
This output is synchronous with the falling
edge of RCKN (receive data clock).
RCKN (receive data clock, output): Clock
output to strobe RXD (receive serial data).
See RXD (receive serial data) description.
At the beginning of a packet, RCKN is
inhibited for 6 or 7 clock cycles to allow the
PLL to gain acquisition. At the end of a
packet, RCKN is inhibited for 1 clock cycle.
During idle state, this output generates a
10MHz clock signal.
XCOL (collision presence, output): This is a
TIL duplication of the collision signal at
COL±. The transceiver connected to the
Ethernet coax supplies a high level or
differential voltage of OV to COL± when a
collision is not present on the coax. It
supplies a 1OMHz square wave signal to
COL± when a collision is detected.
Accordingly, XCOL outputs a high level when
collision is not see and outputs a 10MHz
square wave signal during collision presence.
xeD (receive carrier detect, output): This
output provides the carrier detect function of
the Manchester decoder. This signal is used
by the receive section of the Data Link
controller as a data acquisition enable signal
and by the transmit section as transmission
permission information.
Output is low when the Ethernet coax is idle.
Product Specification
Philips Components-Signetics Data Communication Products
Ethernet encoder/decoder
LBC (Ioopback command, input): A high
level input to this pin dictates loopback mode
operation. During the loopback mode
operation, XCOL output is a high level,
TXDATA± outputs are high level, RXDATA±
inputs are ignored. The data supplied to TXD
(transmit serial data) when TEN (transmit
encode enable) is high is encoded, intemally
routed back to the Manchester decoder and
output from RXD (receive serial data), RCKN
(receive data clock) and XCD (receive carrier
detect).
Oscillator Group
OSC.OUT, OSC.IN, and OSC.REF (oscillator
pins): A 100MHz crystal is placed between
OSC.IN and OSC.OUT.
An LC tank circuit is placed between OSC.IN
and OSC. REF to assure start-up at the
proper harmonic of the crystal.
OSC.OUT is an emitter-follower output and
NE502A
requires a pull-down resistor (3300 typ.). A
phase adjusting capacitor is placed in parallel
with the pull-down resistor to make the delay
through the oscillator close to IOns to
increase the efficiency of the crystal.
As a design recommendation, connection
wires should be as short as possible.
Others
RC and C (capacitor pins): A capacitor
placed between these pins provides the
timing for the active-to-idle time of the
TXDATA± pair.
In AC coupled operation (UClJIiIK is high),
after data transmission, TXDATA- goes high
with rise time determined by the timeconstant of the internal resistor and the
connected capacitor. When a 470pF
capacitor is connected, the rise time of
TXDATA- is typically 0.81-'s (20% to 80%).
(START OF PACKET)
(END OF PACKET)
TEN
TXD
TCKN
TXDATA+
TXDATA-
TXDATA
(DIFFERENTIAL)
LAST BIT. 0
TXDATA
(DIFFERENTIAL)
LAST BIT- 1
RC
NOTE: -
-
-
-
tx:tJI'lR. L
Figure 1. Transmit Tlmfng Diagram
July 11, 1990
428
Because pin C is connected to Vcc on chip,
DC voltage must never be supplied to this
pin.
lJCIJ"RT{ (DC/AC coupling select for
transceiver pair): This input is to select
DC/AC coupling of the transceiver cable
pairs. A low level selects DC coupling: a high
level selects AC coupling and makes both
TXDATA± high during idle state to prevent
the transformer core from saturating. See
CABLE GROUP description.
This pin must be connected to a TTL high or
low. It may be connected directly to Vee or
ground.
"RESET (FF testing purpose only):
This input
pin is used to initialize flip-flops for testing
purposes only and must be connected to Vcc
or a TTL high level in a normal operation.
NC (non-connection): This output pin is for
testing purposes only and must be left open
in a normal operation.
Product Specification
Philips Components-Signetics Data Communication Products
NE502A
Ethernet encoder/decoder
(START OF PACKET)
lslEDGE ' \
DIFFERENTIAL +
RXDATA 0
(IDEAL)
-
\I"
(0)
(1)
(1)
(0)
(1)
(0)
(0)
DIFFERENTIAL
RXDATA 0
(DISTORTEO)
XCD
RCKN
RXD
NOTE:
. --
THRESHOLD MANIPULATION IN AC COUPLED OPERATION
_ _ _ _ _ _ DC COUPLED OPERATION
Figure 2. Receive liming Diagram, Start of Packet
(END OF PACKET)
(1)
(1)
(0)
DIFFERENTIAL
RXDATA
(IDEAL)
DIFFERENTIAL +
RXDATA 0
(DISTORTED)
XCD
RCKN
RXD
o
NOTE:
0
THRESHOLD MANIPULATION IN AC COUPLED OPERATION
DC COUPLED OPERATION
Figure 3. Receive liming Diagram, End of Packet
July 11, 1990
429
(1)
(0)
Product Specification
Philips Components-Signetics Data Communication Products
NE502A
Ethernet encoder/decoder
LBC
--C
tPGLBC
TEN
TXD
TCKN
XCD
7
'~
'NOTE t
RXO
'NOTE 2
'tf.XttQ///WI
NOTE t: WHEN RXDATA±ARE RECEIVING A PACKET AlLBC RISING. THE RECEIVED DATA IS NOT COMPLETE.
NOTE 2: WHEN RXDATA± ARE RECEIVING AT LBC FALLING. THE PACKET MAY NOT BE DECODED CORRECTLY.
Figure 4. Loopback Timing Diagram
DIFFERENTIAL
COL 0
XCOL
NOTE:
- - - - - THRESHOLD MANIPULATION IN AC COUPLED OPERATION
_ _ _ _ _ _ DC COUPLED OPERATION
Figure 5. Collision Timing Diagram
July 11, 1990
430
Product Specification
Philips Components-Signetics Data Communication Products
NE502A
Ethernet encoder/decoder
lN3064x4
(OR EQUIVALENT)
TIL OUTPUT
RL - 2kn
RL" lSpF
(INCLUDING JIG CAPACITANCE)
Figure 6. TTL Output Load Circuit
VOH----""""
VOL----.J
'w
-------<
ICT
THRESHOLD VOLTAGE", 1.5V
Figure 7. TTL Output Waveform
V,H - - - - -
1.5V
V,L - - - - . . . . /
VtH .. 3V. VIL '" OV
tr
_t, '" 10ns
THRESHOLD VOLTAGE", 1.5V
Figure 8. TTL Input Waveform
July 11. 1990
431
Product Specification
Philips Component&-Signetics Data Communication Products
NE502A
Ethernet encoder/decoder
RT
TXDATA+;L=l
RL
TXDATA-
RT
-=
RL-7Bn
Rp27Cln
Figure 9. TXDATA± Output
Load Circuit
VOH----'
VOL - - - - -
tw
----'---I~----- tw----~
~----------- ~T ----------~
Figure 10. TXDATA± Output Waveform
]1R-
~
F-
80%
VIL _ _ _ _ _ 2.5V
80%
'-20%
________2_0....
%
2.5V
VIH - 3.5V. VIL - t.5V
tR .. IF - 2.0ns
RXDATA-. COL-INPUT VOLTAGE. 2.5V (DC)
llCOflK • OV (DC COUPLING)
Figure 11. RXDATA+, COL+ Input Waveform
July 11, 1990
432
Product Specification
Philips Components-Signetics Data Communication Products
NE502A
Ethernet encoder/decoder
TYPICAL TIMING CHARACTERISTICS
-0.6
0.8
TA-2S0C
Vee - 0 V (Shifted)
~
-1.0
}
_H-
~
V
0
<5
>
:i
0
>
/
0.4
VGNO - -4.5 V
.sE
I--
-2.2
-tiO
"5
-0.2
~
-0.4
~
A ~
-0.8
VIN Input Vohage (V)
Figure 13. RXDATA±, COL±
Input Current vs Input Voltage
~
~
&: ~
:;.r
~
"5
~
a
16
~
~
Vee
«
=
5V
I
II
12
.s
Vee _4.5 V
Vee - 5 V
Vee- 5.5V
~
8
I-- -
"5
..j%
a
-tiO
~
~
I
I
~
.0>
I
I
I
TA .. 2S0C
A~
8
-
-40
TA-2S0C
-40
llCillIK - 0 V
I
10 Output Current (mA)
.s
~
~
~
-0.6
Figure 12. TXDATA±
Output Voltage vs Output Current
«
,~ ~
llCillIK. Vee
~
---
.-
0.2
0
I-- I,......-'
VOL lit. '-"" I-"
-1.8
V -"I ~ ~ I-" ~
i--"'" .-.J. ~
ver5VI
VOH
V, VGNO-5 V
VGNO- -5.5 V
-1.4
TA·2S0C
0.6
f-'""
«
g
i
~
-120
~
.9
o
/
o
0.2
VOH High Level Output Voltage (V)
0.4
0.6
Figure 15. TTL·OUTPUT
Low Level Output Current vs
Low Level Output Voltage
Figure 14. TTL·OUTPUT
High Level Output Current vs
High Level Output Voltage
80
TA-2S0c
TA=2S0C
i.,...--:
«
:::;
~
-10
!
-20
8
Vee
V/J
=
5V
40
«
'\.
'\'
i'vee = 4.5 V
Vee = 5 V
I'vee. 5.5 V
;;l,
I
E
f--
~
8
i
~
~
-40
-30
-80
July 11, 1990
0.8
VOL Low Level Output Voltage (V)
I
VIN Input Vohage (V)
VIN Input Voltage (V)
Figure 16. TTL·INPUT
Input Current vs Input Voltage
Figure 17. OSC.IN
Input Current vs Input Voltage
433
Philips Components-Signetics Data Communication Products
Product Specification
Ethernet encoder/decoder
NE502A
TYPICAL TIMING CHARACTERISTICS
TA = 25bC
RL = 5 kn to GND
U'C[J'fJK = 0 V
6
~
.,
N'
g
5
90
"
~
.,
4
'\
-'\("
2
TA = 25b C
RL = 5 kn to GND
U'C[J'fJK = Vee
6
~
N'
4
5
90
~
2
g
Vcc=4.5V
Vee = 5 V
Vee = 5.5 V
"
~Vcc=5.5V
'\ Vee=5V Vee = 4.5 V
0
0
Vdiff = VeoL. - VeoL-
Vdiff = VeoL. - VeoL-
-0.4
o
o
-0.4
-0.2
0.2
0.4
Vdiff Differential Input Voltage (V)
Figure 18. COli to XCOL TRANSFER
(Receiver Threshold) Output Voltage vs
Differential Input Voltage
-0.2
0.2
0.4
Vdiff Differential Input Voltage (V)
Figure 19. COli to XCOL TRANSFER
(Receiver Threshold) Output Voltage vs
Differential Input Voltage
,
-0.6
~\
~ -1.0
\\\
J
1\ \ ~
~
o
~
-
\
~ -1.4
:r:
TA = 25°C
Vee = 0 V (Shifted) RL = SOOn to VGND
LBC = VGND
OCONR:=OV
/ VGND = -4.5 V
VGND = --5 V
' / VGND = --5.5 V
V-
1\ \ /
-1.8
>-
4.2
-2.2
-1.8
4.6
5
5.4
5.8
Vee Power Supply Voltage (V)
40
TA = 25d C
Vee =5 V
U'C[J'fJK = Vee
.,
E
F
lux
V
/'
L.
-",
V
./
-0.2
30
CL = 15pF
RL=2kn
OCONR:=OV
V
Vee = 4.75 V
lI,.,/cc=5V
,t1 Vee = 5.25 V
20
f- IpHL
./
j
t,iT!- ~
l - t--
10
I- IpLH
o
400
BOO
1200
1600
CTX RC Capacitance (pF)
Figure 22. TXDATA- LOW LEVEL HOLD TIME
TXDATA- Low Level Hold Time
TXDATA-Idllng Rise Time vs RC Capacitance
July 11, 1990
-1.0
-0.6
VRC RC Input Voltage (V)
Figure 21. RC to TXDATA- TRANSFER
Output Voltage vs RC Input Voltage
Figure 20. TTL·INPUT THRESHOLD
TTL Input Threshold vs Power Supply Voltage
16
-1.4
//
~
"'"'"
'1
o
20
40
60
TA Ambient Temperature (oC)
80
Figure 23. COli to XCOL PROPAGATION
DELAY TIME Propagation Delay Time vs
Ambient Temperature
434
Product Specification
Philips Components-Signetics Data Communication Products
Ethernet encoder/decoder
NE502A
Vcc (+S.OV)
NES02A
C .. 33pF
4 OSC.OUT
7 RES'ET
TEN--J..---------1
TXO---r----------~
TCKN---+------------~
TCKN
I
I
EOLC
NEB6950
RXO---+
1 ------------1
:+~lllr~
~':: I'---_~___=__====="____'
LBC
i
I
Note: 39n resistors must be balanced less than 1%
Figure 24. Typical Application Circuit
July 11, 1990
435
Product Specification
Philips Components-Signetics Data Communication Products
NE502A
Ethernet encoder/decoder
1-1II
SIP
RESISTER
39n
SIP
RESISTER
2700
COL-
COL+
TXDATA-
I
:
0
'----+_-{
TXDATA+
I
___L-_-_-_....--l--g :EF
000
0000
00
00
00
00
RXDATA-
RXDATA+
C)
TEN
LBC
EDLC
NE86950
(PLCC)
0
rl
1
NOTE: THE TRACESG AND
Figure 25. Typical Component Layout (Top View).
July 11, 1990
C)
C)
436
~ MUST BE AS SHORT AS POSSIBLE.
Philips Components-Signetics
Document No.
853-1482
ECN No.
00665
Date of Issue
October9,1990
Status
Product Specification
NE8392A
Coaxial transceiver interface for
Ethernet/Thin Ethernet
Data Communication Products
DESCRIPTION
The NE8392A Coaxial Transceiver
Interface (CTI) is a coaxial line
driver/receiver for Ethernet (10base5)
and Thin Ethernet (10base2) local area
networks. The CTI is connected
between the coaxial cable and the Data
Terminal Equipment (DTE) and consists
of a receiver, transmitter, collision
detector, heartbeat generator and jabber
timer (see Block Diagram). The
transmitter output connects directly to a
doubly terminated 50n cable, while the
receiver output, collision detector output
and transmitter input are connected to
the DTE through isolation transformers.
Isolation between the CTI and the DTE
is an IEEE 802.3 requirement that can
be met on signal lines by using a set of
pulse transformers normally available in
a standard 16-pin DIP. Power isolation
for the CTI is achieved using DC-to-DC
conversion through a power transformer
(see Figure 1, Connection Diagram).
During transmission the jabber timer is
initiated to disable the CTI transmitter in
the event of a longer than legal length
data packet. Collision detection circuitry
monitors the signals on the coaxial cable
to determine the presence of colliding
packets and signals the DTE in the
event of a collision. At the end of every
transmission the heartbeat generator
creates a pseudo collision for a short
time to ensure that the collision circuitry
is functioning correctly. The heartbeat
function can be disabled for repeater
applications.
a Serial Network Interface (SNI) and a
Network Interface Controller (NIC). The
SNI provides Manchester Encoding and
Decoding while the NIC handles the
media access protocol and buffer
management tasks.
PIN CONFIGURATION
N PACKAGE
FEATURES
• Compatible with Ethernet II, IEEE
802.3 10base5 and 10base2, and ISO
8802/3 interface specifications
• Integrates all transceiver electronics
except signal and power isolation
• Only one external resistor required for
setting coaxial signaling current
• Jabber timer function integrated on
chip
• Heartbeat generator can be externally
disabled for operation as IEEE 802.3
compatible repeaters
• On-chip precision voltage reference
for receive mode collision detection
• Squelch circuitry on all signal inputs
rejects noise
• Full ESD protection
• Standard 16-pin DIP with special lead
frame minimizes the operating die
temperature
• Power-on reset prevents glitches on
coaxial cable during power up.
The CTI is normally part of a three chip
set that implements a complete
Ethernet! Thin Ethernet network
interface for a DTE (see Figure 2,
Interlace Diagram). The other chips are
437
A PACKAGE
Product Specification
Philips Components-Signetics Data Communication Products
Coaxial transceiver interface for Ethernet/Thin Ethernet
NE8392A
ORDERING INFORMATION
TEMPERATURE RANGE
ORDER CODE
16-Pin Plastic DIP
DESCRIPTION
O·C to +70·C
NE8392AN
28-Pin PLCC
O·C to +70·C
NE8392AA
BLOCK DIAGRAM
DTE
INTERFACE
COAX
CABLE
RlCI
4-POLE BESSEL
LOW PASS ALTER
RECEIVER
AC-DC SQUELCH
TXO
CDS
HEARTBEAT ENABLE
October 9,1990
438
Product Specification
Philips Components-Signetics Data Communication Products
Coaxial transceiver interface for Ethernet/Thin Ethernet
NE8392A
PIN DESCRIPTIONS
PIN NO.
NPKG
PIN NO.
PLCC
SYMBOL
DESCRIPTION
1
2
2
3
CD+
CD-
Collision Outputs. Balanced differential line driver outputs which send a 10MHz oscillation signal to the DTE in the event of a collision. jabber interrupt or heartbeattest.
3
6
4
12
RX+
RX-
Receiver Outputs. Balanced differential line driver outputs which send the received
signal to the DTE.
7
8
13
14
TX+
TX-
Transmitter Inputs. Balanced differential line receiver inputs which accept the transmission signal from the DTE and apply it to the coaxial cable at TXO.
9
15
HBE
Heartbeat Enable. The heartbeat function is disabled when this pin is connected to
VEE and enabled when connected to GND or left floating.
11
12
18
19
RR+
RR-
External Resistor. A 1k.Q (1%) resistor connected between these pins establishes
the signaling current at TXO. RR- is internally connected to VEE.
14
26
RXI
Receiver Input. This pin is connected directly to the coaxial cable. Received signals
are equalized, amplified, and sent to the DTE through the RX± pins.
15
28
TXO
Transmitter Output. This pin is connected directly (Thin Ethernet) or through an
external isolating diode (Ethernet) to the coaxial cable.
16
1
CDS
Collision Detect Sense. Ground sense connection for the collision detection circuitry.
This pin should be directly connected to the coaxial cable shield to prevent ground
drops affecting the collision threshold voltage.
GND
Positive Supply Pin.
16
10
17
4
5
13
5to 11
20 to 25
VEE
Negative supply pins. These pins also serve as a low thermal resistance path forextracting heatfrom the die. They should, therefore, be connected to a large metal area
on the PC board.
NOTE:
1. The IEEE 802.3 name for CD is CI; for RX is DI; for TX is DO.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
VEE
Supply voltage'
V1N
Voltage at any input'
TSTG
Storage temperature range
RATING
UNIT
-12
V
Oto-12
V
-05 to +150
·C
TSOLD
Lead soldering temperature (10sec.)
+300
·C
TJ
Recommended max junction temperature 2
+130
·C
BJA
Thermal impedance (N and A packages)
60
·CfW
NOTES:
1. 100% measured in production.
2. The junction temperature is calculated from the following expression:
TJ ~ TA + OJA [VEE (0.075 + n x 0.051100) + 8(VEE -2) I RI
where
TA ~ Ambient temperature in ·C.
OJA ~ Thermal resistance of package.
VEE ~ Normal operating supply voltage in volts.
n
Percentage transmitter duty cycle.
R
Pull down resistors on the RX and CD pins in n.
The N package is specially designed to have a low OJA by directly connecting the four center Pins 4. 5, 12, and 13 to the die attachment
area. These four pins then provide a conductive heat flow path from the die to the PCB where they should be soldered to a large area VEE
track. For the A package, Pins 5 to 11 and 19 to 25 should similarly be soldered to a large area VEE and rack.
October 9, 1990
439
Product Specification
Philips Components-$ignetics Data Communication Products
NE8392A
Coaxial transceiver interface for Ethernet/Thin Ethernet
ELECTRICAL CHARACTERISTICS
VEE = -9V ±5%; TA = O°C to +70°C unless otherwise specified 1,2. No external isolation diode on
TXO.
LIMITS
SYMBOL
VPOR
lEE
PARAMETER
TEST CONDITIONS
Min
Power~n
reset voltage. Transmitter disabled
for IVEEI < IVpORI
Typ
Max
UNIT
V
-6.5
Supply current non-transmitting
-60
-130
mA
Supply current transmitting
-125
-180
mA
+25
fIA
fIA
I.Rxl
Receive input. bias current
VRXI = OV
ICDS
Cable sense input bias current
Vcos=OV
VIH
HBE input HIGH voltage
V IL
HBE input LOW voltage
IIH
HBE input HIGH current
V HBE = OV
HBE input LOW current
VHBE = VEE
-2
+2
+6
V
VEE +1.4
VEE +0.4
V
250
500
--SOO
-1000
fIA
fIA
lroc
Transmit output DC current level3
-37
-45
mA
ITAc
Transmit output AC current level 3
±28
±Iroc
mA
ITX10
Transmit current
-250
+250
fIA
IlL
VTCOM
VTXO = -10V
Transmitter output voltage oompliance4
Veo
Collision threshold5
Voo
Differential output voltage - non idle at RX± and
CD±6
VOB
Differential ourut voltage imbalance - idle at
RX±andCD±
Voc
Output common mode voltage at RX± and CD±
VRS
Receiver squelch threshold
Measured by applying
DC voltage at RXI
-1450
-1530
±600
-3.7
V
-1580
mV
±1200
mV
±40
mV
-1.5
-2
-2.5
V
VRXI average DC
-130
-250
-370
mV
(VTX. - VTX-) peak
-175
-225
-300
mV
VTS
Transmitter squelch threshold
RRXI
Shunt resistance at RXI non-transmitting
CRXI
Input capacitance at RXI
2
pF
RTXO
Shunt resistance at TXO transmitting
10
kQ
100
kQ
NOTES:
1. Currents flowing into device pins are positive. All voltages are referenced to ground unless otherwise specified. For ease of interpreiation,
the parameter limit that appears in the MAX column is the largest value of the parameter, irrespective of sign. Similarly, the value in the MIN
column is the smallest value of the parameter, irrespective of sign.
2. All typicals are for VEE = -9V and TA = 27°C.
3. lroc is measured as (VMAX + VMIN)/(2 x 25) where VMAX and VMIN are the max and min voltages at TXO with a 25Q load between TXO and
GND. ITAC is measured as (VMAX - VMIN)/(2 x 25).
4. The TXO pin shall oontinue to sink at least lroc min when the idle (no signal) voltage on this pin is -3.7Y.
5. Collision threshold for an AC signal is within 10% of Vco.
6. Measured on secondary side of isolation transformer (see Connection Diagram, Figure 1). The transformer has a 1:1 turns ratio with an
inductance between 30 and 100..H at 5MHz.
7. Measured as the voltage difference between the RX pins or the CD pins with the transformer removed.
October 9,1990
440
Product Specification
Philips Components-$ignetics Data Communication Products
NE8392A
Coaxial transceiver interface for Ethernet/Thin Ethernet
TIMING CHARACTERISTICS
VEE = -9V ±5%' TA = 0 to 70°C unless otherwise specified'. No external isolation diode on TXO.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
tAON
Receiver start up delay RXI to RX± (Figure 3)
First received bit on RX+
V AXI = -2V peak
Min
Typ
First validly timed bit on RX±
35
UNIT
5
bits
tAON +2
bits
50
ns
tAD
Receiver prop. delay RXlto RX±
tAA
Differential output rise time on RX± and CD±2.3
5
ns
tAF
Differential output fall time on RX± and CD+2.3
5
ns
los
Differential output settling time on RX±and CD±
to VOB = 40mV2 (see Figure 5)
1
Il s
tAJ
Receiver and cable total jitter
tAHI
Receiver high to idle time
tAM
Rise and fall time matching on RX± and CD±
Transmitter start-up delay TX± to TXO
(Figure 4)
tTST
VAXI = -2V peak
Max
Measured to +210mV
850
150
V Tx±=-1Vpeak
1
First validly timed bit
tTo
tTA
Transmitter rise time 10% to 90% (see Figure 4)
ns
ns
0.4
tAF -tAA
First transmitted bit on TXO
Transmitter prop delay TX± to TXO
(see Figure 4)
ns
±3
35
VTX± = 1V peak
2
bits
tTST + 2
bits
50
ns
25
ns
tTF
Transmitter fall time 10% to 90% (see Figure 4)
25
ns
tTM
tTF -tTA mismatch
±2
ns
tTS
Transmitter added skew'
±2
tTON
Transmitter tum on pulse width (see Figure 4)
VTX± = 1V peak
10
tTOFF
Transmitter tum off pulse width (see Figure 4)
VTX± = 1V peak
150
icON
Collision tum on delay (see Figure 6)
OV to -2V step at RXI
lcoFF
Collision turn off delay (see Figure 6)
-2V to OV step at RXI
IcHI
Collision high to idle time (see Figure 6)
Measured to +210mV
fco
Collision frequency (see Figure 6)
tcp
250
150
8.0
ns
40
10
ns
340
ns
13
bits
16
bits
850
ns
12.5
MHz
Collision signal pulse width (see Figure 6)
35
70
ns
Heartbeat turn on delay (see Figure 7)
0.6
1.6
Ils
IHw
Heartbeat test duration (see Figure 7)
0.5
1.5
Il s
tJA
Jabber activation delay measured from TX± to
CD± (see Figure 8)
20
60
ms
tJA
Jabber reset delay measured from TX± to CD±
(see Figure 8)
250
750
ms
tHON
NOTES:
1. All typicals are for VEE = -9V and TA = 27°C.
2. Measured on secondary side of isolation transformer (see Figure 1. Connection Diagram). The transformer has a 1:1 turn ratio with an
inductance between 30 and 100llH at5MHz.
3. The rise and fall times are measured as the time required for the differential voltage to change from -225mV to +225mV, or +225mV to
-225mV, respectively.
4. Difference in propagation delay between rising and falling edges at TXO.
October 9, 1990
441
Product Specification
Philips Components-Signetics Data Communication Products
Coaxial transceiver interface for Ethernet/Thin Ethernet
NE8392A
FUNCTIONAL DESCRIPTION
The NE8392A contains four main functional
blocks (see Block Diagram). These are:
a. The receiver which takes data from the
coaxial cable and sends it to the DTE.
b. The transmitter which receives data from
the DTE and sends it onto the coaxial
cable.
c. The collision detection and heartbeat
generation circuitry which indicates to the
OTE any collision on the coaxial cable
and tests for collision circuitry functionality
at the end of every transmission.
d. The jabber timer which disables the
transmitter in the event of a longer than
legal length data packet.
Receiver Functions
The receiver consists of an input buffer, a
cable equalizer, a 4-pole Bessel low pass
filter, a squelch circuit and a differential line
driver.
The buffer provides high input resistance and
low input capacitance to minimize loading
and reflections on the coaxial cable.
The equalizer is a high pass filter that
compensates for the low pass effect of the
coaxial cable and results in a flatband
response over all signal frequencies to
minimize signal distortion.
The 4-pole Bessel low pass filter extracts the
average DC voltage level on the coaxial cable
for use by the receiver squelch and collision
detection circuits.
The receiver squelch circuit prevents noise
on the coaxial cable from falsely triggering
the receiver in the absence of a true signal.
At the beginning of a packet, the receiver
turns on when the DC level from the low pass
filter is lower than the DC squelch threshold.
For normal signal levels this will take less
than SOOns, or S bits. However, at the end of
a packet, a fast receiver tum off is neeefed to
reject both dribble bits on the coaxial cable
and spurious responses due to settling of the
on-<:hip bandpass filter. This is accomplished
by an AC timing circuit that disables the
receiver if the signal level on the coaxial
cable remains high for typically 250ns and
only enables the receiver again after approximately IllS. Figures 3 and S illustrate receiver
timing.
The differential line driver provides typically
±900mV signals to the DTE with less than
7ns rise and fall times. When in idle state (no
received signal) its outputs provide <20m V
differential voltage offset to minimize DC
standing current in the isolation transformer.
The line driver outputs are emitter followers
October 9, 1990
and, for Ethernet applications where they
drive a 78n transmission line, require a soon
pull-down resistor to VEE. For Thin Ethernet
applications where the AUI cable is not used,
the pull-down resistor can be increased to
I.Skn to save power consumption.
Transmitter Functions
The transmitter has differential inputs and an
open collector current driver output. The
differential input common mode voltage is
established by the CTI and should not be
altered by external circuitry. Controlled rise
and fall times of 2Sns (±Sns) minimize higher
harmonic components in the transmitted
spectrum, while matching of these rise and
fall times to typically 2ns minimizes signal
jitter. The drive current levels of the CTI are
set by an on-chip bandgap voltage reference
and an external I % resistor. An on-chip
isotation diode is provided to reduce the
transmitter'S coaxial cable load capacitance.
For Thin Ethernet applications, no further
external isolation diode is required, since the
NE8392A meets the capacitive loading
specifications. For Ethernet applications a
further external diode should be added to
reduce loading capacitance.
The transmitter squelch circuit ensures that
the transmitter can only be enabled by
negative-going differential signals of typically
greater than 225mV in magnitude and 15ns in
duration. The transmitter will be disabled at
the end of a packet if there are no negative
going signals of greater than 225mV for more
than typically 250ns. Figure 4 illustrates
transmitter timing.
Collision Functions
The collision detection scheme implemented
in the NE8392A is receive mode detection,
which detects a collision between any two
stations on the network with certainty at all
times, irrespective of whether or not the local
DTE is producing one of the colliding signals.
This is the only detection scheme allowed by
the IEEE 802.3 standard for both repeater
and non-repeater nodes.
The collision circuitry consists of the 4-pole
Bassellow pass filter, a comparator, a
precision voltage reference that sets up the
collision threshold, a heartbeat generator, a
I OM Hz oscillator, and a differential line driver.
The collision comparator monitors the DC
level at the output of the low pass filter and
enables the line driver if it is more negative
than the collision threshold. A collision
condition is indicated to the DTE by a 10MHz
oscillation signal at the CD outputs and
typically occurs within 700ns of the onset of
the collision. The collision signal begins with
442
a negative-going pulse and ends with a continuous high-to-idle state longer than 170ns.
Figure 6 illustrates collision timing.
At the end of every transmission, the
heartbeat generator creates a pseudo
collision to ensure that the collision circuitry is
properly functioning. This pseudo collision
consists of a IllS burst of I OMHz oscillation
at the line driver outputs approximately IllS
after the end of the transmission. The
heartbeat function can.be disabled externally
by connecting the HBE (heartbeat enable) to
VEE. This allows the CTI to be used in
repeater applications. Figure 7 illustrates
heartbeat timing.
As with the receiver outputs, the collision
outputs also require a pull down resistor to
VEE and maintain <20mV differential voltage
offset in the idle state to minimize DC
standing current in the isolation transformers.
Jabber Functions
The jabber timer monitors the transmitter and
inhibits transmission if it is active for longer
than typically 30ms. The jabber circuit then
enables the collision outputs for the
remainder of the data packet and for typically
4S0ns (unjab time) after it has ended. At this
point the transmitter becomes uninhibited.
Figure 6 illustrates jabber timing.
Detection of Coaxial Cable Faults
In the NE8392A there is no internalloopback
path from the TX inputs to the RX outputs.
This means that, when the local DTE is
transmitting, the signal will only be present at
the receiver outputs RX+ and RX- if it
appears on the coaxial cable and is larger
than the receiver squelch threshold VRS. If a
short circuit fault condition occurs at the cable
connector to the CTI, then no signal will
appear at the receiver outputs. An intelligent
OTE can, therefore, detect this fault. If the
fault is an open circuit, then a continuous
collision signal will be sent to the OTE,
provided the average DC voltage at the RXI
pin is greater than the typical collision
threshold of -1.S3Y.
If a short or open circuit occurs elsewhere on
the coaxial cable, the resulting reflections can
result in an impedance at the CTI of any
value between a short circuit and son,
depending on the distance of the CTI from
the fault. The upper limit of son results from
the fact that the coaxial cable is terminated in
son at both ends. Faults on the cable itself
are, therefore, not guaranteed to be detected
by simply monitoring the RX and CD pins
when in the transmit mode, and more
sophisticated schemes may be necessary.
Product Specification
Philips Components-Signetics Data Communication Products
NE8392A
Coaxial transceiver interface for Ethernet/Thin Ethernet
AUI
CABLE
12T015VDC
COLUSION
PAIR
700
•
.
,
- ,
,
,
,
,
,
r -
,
,
,
,
,
+
DC TO DC
CONVERTER
9V (ISOLATED)
-
sooo
16
1
,
,
,
•
II
I
I.
500il
~
13
CD+
RECEIVE
PAIR
700
,
TRANSMIT
PAIR
,
,
,
,
I.
1
,
,
II
•
7
~
__ J
CD-
I.
RX+
~
,
,
,
,
---
500il
T1 (NOTE 1)
4
~
SOOO
8
Ifn
~
RX-
"
3
NE8392A 14
4
13
6
700
TX-
8
RXI
"
11
10
•
RR+
HOE
--:--
Figure 1. Connection Diagram
SERIAL
NETWORK
INTERFACE
NETWORK
INTERFACE
CONTROLLER
DTE
MAU = Medium Attachment Unit
AUI Cable = Attachment Unit Interface Cable (not used in Thin Ethernet applications)
Figure 2. Interface Diagram for EthernetlThin Ethernet Local Area Network
October 9, 1990
443
I
,
,
NOTES:
(OPTIONAl)
,K1%
GND
1. T11a a 1:1 pulse tranaformer, with an inductance of 30 to l00~H.
2. IN916 or equivalent for Ethernet. not required for Thin Ethernet
(AUI CABLE)
I
VEE3
RR-
CTI
TX+
7
(NOTE')
TXO
•
•
f---.----
CDS
Product Specification
Philips Components-Signetics Data Communication Products
NE8392A
Coaxial transceiver interface for Ethernet/Thin Ethernet
.__--.JI
RXI
RX±
1.
4
10
7:
51
'...- - - - - IJION+2 -;.----.> ,
Figure 3. Receiver Timing
1- ,oono-..j
TX+
TXO
10
Figure 4. Transmitter Timing
RXI
RX±
Figure 5. Receiver End-ol-Packet TIming
RXI
~:~L
__________________
-J
r- ~ONl
r-i
1iFeD
Figure 6. Collision TIming
October 9, 1990
444
11
11
Product Specification
Philips Components-Signetics Data Communication Products
Coaxial transceiver interface for Ethernet/Thin Ethernet
TX±
NE8392A
~_ _ _ _ _ _ _ _ _ _ _ _ _ __
;,4--.- - tHON - - - ' ' ; ' - , .- - 'Hw - - - - - : . ,
Figure 7. Heartbeat TIming
TX±
-lllllllllllllllllll-I- - - - - - - - - :.
j'-.:
TXO
CD±
IJA
:
)0,
~~----IJR-----·'
-lllllllillt-I-------~---11111111111111111111111111111111111111111111111111---1- - Figure 8. Jabber Timing
October 9, 1990
445
Philips Components-Signetics
Document No.
853-1450
NE86950
ECN No.
00014
EtherStar™ Ethernet controller
Date of Issue
July 23, 1990
Status
Product Specification
Data Communication Products
PIN CONFIGURATION
DESCRIPTION
FEATURES
The NE86950 ElherStarT" is a highly
integrated, local area network controller
that supports both IEEE 802.3
CSMAlCD 10Mbls Ethernet and 1Mb/s
StarLANT" protocols. Configurable for
8- or 16-bit wide bus interfaces, it links a
host system bus to the local area
network (LAN) transceiver or drivers in
cost sensitive network applications such
as personal computers, terminals,
workstations, and other resourcesharing controllers with the minimum
amount of controlling software and host
system EtherStar interaction. Its design
enables the controller to be connected
directly on the main system bus without
contention with the host CPU for the
bus. Also, there is no need for a
dedicated local CPU to handle data
transfers.
• IEEE802.3 CSMA/CD EthernetlThin
Ethernet and StarLAN compatibility
EtherStar is normally part of a three chip
set that forms a complete EthernetlThin
Ethernet interface for a Data Terminal
Equipment. The EtherStar is the
Network Interface Controller (NIC) and
the other chips are a Serial Network
Interface (SNI), such as the NE502A,
and a Coaxial Transceiver Interface
(CTI), such as the NE8392A. The SNI
provides Manchester encoding and
decoding while the CTI provides the
physical attachment to the coaxial
medium.
• Configurable for 8-bit or 16-bit data
path widths
• Unique buffer management
architecture arbitrates all dedicated
SRAM or DRAM memory data
accesses and automatically allocates
buffer memory area for incoming data
frames
12~
84-PIN
PLASTIC LEADED
CHIP CARRIER
(PLCC)
o
u----_,..,r
uP 54
32 -.....,-
33
TOP VIEW
• Allows simultaneous transfer of data
frames tolfrom host system and
transmission/reception of data frames
tolfrom LAN media
53
64
• Allows automatic retransmission of
data packets during collisions, thus
saving bus bandwidth
• Keeps track of all buffer memory area
pointers internally in hardware to
reduce software overhead
• Supports data transfers at up to 3.3
Mbytes or Mwords per second to the
host system
• Addresses 8, 16, 32, or 64 Kbytes of
dedicated SRAM or DRAM buffer
memory. Dedicated buffer memory
architecture allows data packet
reception without using bus bandwidth
• Supports DMA transfers
• Available in 84-pin plastic J-bend
PLCC or BO-pin plastic quad flat pack
• Dual metal, CMOS technology
• 25mA typical Icc current
ORDERING INFORMATION
DESCRIPTION
Packages
TEMPERATURE RANGE
ORDER CODE
BO-Pin Plastic Quad Flat Pack
O·Cto +7()OC
NEB6950BB
B4-Pin Plastic Leaded Chip Carrier
O·C to +7()OC
NEB6950BA
446
24 -"-rT""--rr~41
25
40
TOP VIEW
APPLICATIONS
• Workstations
• Terminals
• File servers
• Print servers
Product Specification
Philips Components-Signetics Data Communication Products
NE86950
EtherStar™ Ethernet controller
ETHERSTAR BLOCK DIAGRAM
INTERNAL DATA BUS
DATAUNK
CONTROLLER
TXDITXDS
TEN
INTERNAL
ADDRESS BUS
lBC
DATAUNK
CONTROllER
REGISTERS
RXD/RXDS
RCKN
XCD
HOST
SYSTEM
INTERFACE
XCOl
TM
CONTRO
BUFFER
MANAGER
BUFFER
MANAGER
PORT
REGISTERS
TCKNlTCKNS
TCKP
SYSTEM
CONAGURE
STARLAN
MANCHESTER
ENCODER/DECODER
DRAM
CONTROllER
800-8015
BAO-BA7
PIN ASSIGNMENTS - PQFP
PIN
NO.
PIN NAME
PIN
NO.
PIN NAME
PIN
NO.
PIN NAME
PIN
NO.
PIN NAME
PIN
NO.
PIN NAME
PIN
NO.
PIN NAME
1
ETiSTAR'
15
RESET
29
EOP
43
SD10
57
BA3
71
BD8
2
8IW
16
SD7
30
SA3
44
SDll
58
BA4
72
PRES
3
BSO
17
SD6
31
SA2
45
SD12
59
BA5
73
VCC2
4
881
18
SD5
32
TM
46
SD13
60
BA6
74
BD9
5
TEN
19
SD4
33
VCC1
47
SD14
61
BA7
75
BD10
6
LBC
20
SD3
34
SAl
48
SD15
62
rn::
76
BDll
7
XCD
21
SD2
35
SAO
49
WE
63
BDO
77
BD12
8
JtOO[
22
SDI
36
BHE
50
RJ\SO
64
BDI
78
BD13
9
TXDITXDS
23
SDO
37
fID
51
RAST
65
BD2
79
BD14
10
TCKP
24
FID"7
38
WAr
52
GND2
66
BD3
80
BD15
11
TCKNITCKNS
25
TINT
39
~
53
"CAS
67
BD4
12
GNDI
26
RlNT
40
BREQ
54
BAD
68
BDS
13
RCKN
27
!mE[
41
SD8
55
BAI
69
BD6
14
RXD/RXDS
28
USE[
42
SD9
56
BA2
70
BD7
July 23. 1990
447
Philips Components-Signetics Data Communication Products
Product Specification
EtherStar™ Ethernet controller
NE86950
PIN ASSIGNMENTS - PLCC
PIN
NO.
PIN NAME
PIN
NO.
PIN NAME
PIN
NO.
PIN NAME
PIN
NO.
PIN NAME
PIN
NO.
PIN NAME
PIN
NO.
PIN NAME
B014
1
GNOI
15
R1NT
29
~
43
GN03
57
B03
71
2
RCKN
16
'RSE[
30
BREO
44
~
58
B04
72
B015
3
RXO/RXOS
17
USE[
31
S08
45
BAO
59
B05
73
ETiSlAR
BIW
4
RESET
18
EOP
32
S09
46
BAI
60
B06
74
5
S07
19
SA3
33
SOlO
47
BA2
61
B07
75
BSO
6
S06
20
SA2
34
SOil
48
BA3
62
B08
76
BSI
TEN
7
S05
21
VCC1
35
S012
49
BA4
63
VCC2
77
8
S04
22
GN02
36
S013
50
BA5
64
GN04
78
LBC
9
S03
23
TM
37
S014
51
BA6
65
PRES
79
xeD
10
S02
24
SAl
38
S015
52
BA7
66
B09
80
xcm:
11
SOl
25
SAO
39
WE
53
erE
67
BOlO
81
TXOITXOS
12
SOO
26
BFIE
40
RASO
54
BOO
68
BOil
82
TCKP
13
ROY
27
RU
41
WiST
55
BOI
69
B012
83
TCKNITCKNS
14
TINT
28
WAr
42
NC
56
B02
70
B013
84
NC
PIN DESCRIPTIONS
PIN NO.
PLCC
PQFP
SYMBOL
TYPE
DESCRIPTION
Device Configuration Pins
73
1
ETiSlAR
I
NETWORK CONFIGURATION: configures EtherStar for Ethernet (ETiSlAR = 1) or StarLAN (ET/
STAR=O)
74
2
BIW
I
BYTElWORD SELECT: BIW = 1 configures EtherStar for an -bit data bus, BIW = 0 configures
EtherStar to a 16-bit data bus.
I
BUFFER SIZE SELECT LINES: These inputs, together with BIW, determine the size of the buffer
memory supported by EtherStar. For word transfers, BRE should be asserted. Refer to the BRE
signal description for more details.
BSl BSO
BIW=l
BIW=O
0
0
8KB
4KW
0
1
16KB
8KW
1
0
32KB
16KW
1
1
64KB
32KW
75,76
3,4
BS1, BSO
Network Interface Pins
77
5
TEN
0
TRANSMIT ENABLE: This pin becomes active when the first bit of the outgoing packet is valid and
is held stable during transmission of data from the TXOITXOS pin. This pin goes low after the last bit
of the packet is clocked out. The TEN pin interfaces directly with the TEN pin of the Ethernet
encoder/decoder, such as Signetics NE502A, in Ethernet configuration only.
78
6
LBC
0
LOOPBACK CONTROL: When LBC = 1, indicates that EtherStar is in the loopback mode. In
Ethernet configurations, this pin connects to LBC on the encoder/decoder, and instructs it not to send
data 10 the Ethernet medium but to send the original data packet back to EtherStar for validation. In
StarLAN configurations, this also occurs but loopback occurs on-chip.
79
7
XCO
I
CARRIER DETECT: This signal is provided by the encoder/decoder. It indicates the presence of a
carrier on the network media.
80
8
xcrn:
I
COLLISION DETECT: This active low input indicates that a collision has been detected on the network media. Signal is provided by the encoder/decoder for Ethernet configurations or as an optional
pin for StarLAN configurations.
81
9
TXOITXDS
0
TRANSMIT DATA (Ethernet)ITRANSMIT DATA (StarLAN): This pin is a dual function pin. In an
Ethernet configuration, (ETiSlAR = 1), TXOITXOS is the serial data output to the encoder/decoder.
In a StarLAN configuration (ETiSlAR = 0). TXO/TXOS transmits Manchester encoded data to an
RS-422 type transceiver.
July 23, 1990
448
Product Specification
Philips Components-Signetics Data Communication Products
NE86950
EtherStar™ Ethernet controller
PIN DESCRIPTIONS (Continued)
PIN NO.
PLCC
PQFP
SYMBOL
TYPE
DESCRIPTION
Network Interface Pins (Continued)
82
10
TCKP
0
CRYSTAL OUTPUT: This is the 1OMHz output pin required if a crystal is used. It is available for
StarLAN configurations only. The multiplexed pin TCKNfTCKNS is used as the OSCIN input in
conjunction with the TCKP signal pin if a crystal is used.
83
11
TCKN/
TCKNS
I
TRANSMIT CLOCK {Ethernet)/StarLAN CLOCK (StarLAN): This pin is a dual function pin. In an
Ethernet configuration, (ETISTAR = 1), TCKN/TCKNS is the input clock. Typically this clock is 10MHz
and is generated by the external encoder/decoder. In a StarLAN configuration (ETiSTAR = 0), TCKN/
TCKNS is a 10MHz clock required by the on-chip Manchester encoder/decoder.
2
13
RCKN
I
RECEIVE DATA CLOCK: This is the 10MHz synchronous receive data clock signal supplied by the
encoder/decoder. Not used in StarLAN configurations.
3
14
RXD/
RXDS
I
RECEIVE DATA {Ethernet)/RECEIVE DATA (StarLAN): This pin is a dual function pin. In an
Ethernet configuration, RXD/RXDS is the serial data input line from the external encoder/decoder. In a
StarLAN configuration, RXD/RXDS is the input line that receives the asynchronous 1MHz Manchester
encoded data from the LAN network.
System Interface Pins
4
15
RESET
I
HARDWARE RESET: Active high. A minimum pulse of 211S in duration is required. This pin resets
EtherStar's internal pointers and registers to the appropriate state.
5-12
31-.'3B
16-23
41-4B
SD7-S00
SOB-SOlS
I/O
SYSTEM DATA BUS: All data, command and status transfers between the host system and
EtherStar take place over this bidirectional, 3-state bus. The direction of the transfer is controlled by
RIT and WRT. The type of transaction which is occuring is controlled by F!SE[, OSE[, and llJI:CK.
The portion of the data bus over which the transaction occurs is controlled by BIW, BRE, and SAO.
13
24
ROY
0
READY: Active low. This output is asserted to indicate to the host system that EtherStar is ready to
complete the requested read or write operation. It will also be asserted if the device is unable to respond to the request for a read or write within 2.4l1s. In that case, EtherStar will also assert RlNT and
the bus read error status bit (OLCR2, bit 6) or TJliIT and the bus write error status bit (OLCRO, bit 0).
14
25
TJliIT
0
TRANSMIT INTERRUPT: Active low. Indicates that EtherStar requires host system attention after
successful transmission of a packet or if an error occurs during transmission. This interrupt is
maskable and can be cleared by writing to OLCRI.
15
26
RlNT
0
RECEIVE INTERRUPT: Active low. Indicates that EtherStar requires host system attention after
successful reception of a packet or during reception should any error conditions occur. This signal is
maskable and can be cleared by writing to OLCR3.
16
27
F!SE[
I
REGISTER SELECT: Active low. Enables reacllwrite operations between the 16 data link control
registers (OLCRO-15) and the host system.
17
2B
USE[
I
DATA SELECT: Active low. Enables read/write operation between the host system and EtherStar's
buffer memory port (BMPRO) and buffer manager registers (BMPR2-4).
lB
29
EOP
I
END OF PROCESS: Indicates that an entire packet has been transferred between the buffer memory
and the host system. When the OMA controller asserts EOP, further assertions of EtherStar's bus
request output, BREQ, will be discontinued.
19,20
24,25
30,31
34,35
SA3,SA2
SA1,SAO
I
23
32
TM
0
SYSTEM ADDRESS LINES: Specifies which of the internal registers or ports of EtherStar is selected
for read/write operations.
TEST MODE: The signal on this pin is the complement of the value of the
used to control external functions.
TIiiI bit (DLCR4, bit 2). It is
BYTE HIGH ENABLE: Active low. This pin is the byte/word control line. It is used only when EtherStar is configured for a 16-bit data bus (BIW = 0). It allows word, upper byte only or lower byte only
transfers. The address select pin SAO is used with BRE for byte or word transfers as follows:
26
36
BRE
I
BIW
BHE
0
0
0
0
1
1
SAO
0
1
0
1
1
X
X
0
0
July 23, 1990
449
FUNCTION
Word transfer {BMPRO, BMPR2-3, 4 onl~;>Byte transfer on upper half of data bus ( 015-S0B)
Byte transfer on lower half of data bus (S07-S00)
Reserved
Byte (S07-S00)
Product Specification
Philips Components-Signetics Data Communication Products
EtherStar™ Ethernet controller
NE86950
PIN DESCRIPTIONS (Continued)
PIN NO.
PlCC
PQFP
SYMBOL
TYPE
DESCRIPTION
System Interface Pins (Continued)
27
37
"RO
I
READ: Active low input which specifies that the current transfer between EtherStar and the host system is a read from one of EtherStar's internal registers or its data port.
28
38
WRT
I
WRITE: Active low input which specifies that the current transfer between EtherStar and the host
system is a write to one of EtherStar's internal registers or its data port.
29
39
mmR
I
BUS ACKNOWLEDGE: Active low. Indicates that the DMA controller is ready to transfer data between the host system and EtherStar's buffer memory.
30
40
BREQ
0
BUS REQUEST: Issued to the DMA controller to indicate that EtherStar has data available to be read
in its receive buffer, or is ready to accept data into its transmit buffer.
65
72
PRES
0
PACKET RESET: This signal pin follows the RMT RST bit (DLCR2, bit 4) that indicates a complete
special data packet with the data length field 0900H has been received. This is intended to be used
as a hardware control function from other nodes in the network.
Buffer Memory Control Pins
39
49
WE
0
WRITE ENABLE: Active low. This output enables the DRAM memory buffer for write operations.
40
41
50
51
~
0
ROW ADDRESS STROBE: Active low. Outputs to the DRAM buffer memory.
~
44
53
~
54-61
BAO-BA7
0
0
COLUMN ADDRESS STROBE: Active low. DRAM buffer memory column address strobe.
45-52
53
62
OE
0
OUTPUT ENABLE: Active low. Used to enable the buffer memory during read operations.
54-62
66-72
63-71
74-80
BDO-BD8
BD9-BD15
I/O
BUFFER MEMORY DATA: Data lines between the DRAM buffer memory and EtherStar. This 3-state
data bus is configurable for an B-bit or 16-bit data size by the BIW input.
BUFFER MEMORY ADDRESS: These eight lines can address 64 Kbytes of DRAM buffer memory.
Device Power Pins
1
22
43
64
12
52
-
GND1
GND2
GND3
GND4
21
63
33
73
VCC1
VCC2
July 23, 1990
SYSTEM GROUND
POWER SUPPLY: A nominal +5VDC supply is required.
450
Product Specification
Philips Components-Signetics Data Communication Products
NE86950
EtherStar™ Ethernet controller
ABSOLUTE MAXIMUM RATINGS1,4
RATING
UNIT
-0.3 to 6.0
V
DC input voltage2
-{l.3 to Vee + 0.3
V
VOUT
DC output voltage
-{l.3 to Vee + 0.3
V
TSTG
Storage temperature range
-40 to +150
DC
TJ
Maximum recommended junction temperature
PD
Power dissipation
500
mW
SYMBOL
PARAMETER
Vee
Supply voltage
V IN
Thermal impedance
8JA
DC
A package
B package
DCIW
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not implied.
Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
2. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge.
Nonetheless, it is recommended that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
3. Parameters are valid over specified temperature range and supply voltage range unless otherwise noted.
4. All voltage measurements are referenced to ground (GND). All time measurements are referenced at input and output levels of 1.5V. For testing,
all inputs swing between 0.4V and 2.4V. See Figure 13.
DC ELECTRICAL CHARACTERISTICS1, 2 TA = 0 to 70DC; Vee = 5V ±5%, unless otherwise stated.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
UNIT
V IL
Low level input voltage
0
0.8
V
VIH
High level input voltage
2.2
Vee
V
VOL
Low level output voltage
All except BREa
BREa
IOL = 3.2mA
IOL = 12.8mA
0
0
0.4
0.4
V
V
High level output voltage
All except BREa
BREa
IOL = -{l.4mA
IOL = -10.0mA
4.2
4.2
Vee
Vee
V
V
VI
= 0 or Vee
= 0 or Vee
No output load; TCKN = 10MHz;
RCKN = 10MHz
All inputs static; VI = 0 or Vee
-10
10
Vo
-10
10
flA
flA
40
mA
VOH
III
Input leakage current
ILZ
Thre-state output leakage current
lee3
Operating Vee supply current
25
Static Vee supply current
100
Ices
flA
NOTES:
1. Parameters are valid over specified temperature range and supply voltage range unless otherwise noted.
2. All voltage measurements are referenced to ground (GND). All time measurements are referenced at input and output levels of 1.5V. For testing,
all inputs swing between 0.4V and 2.4V. See Figure 13.
3. Limited functional test patterns are performed during device testing for this parameter.
July 23, 1990
451
Product Specification
Philips Components-Signetics Data Communication Products
EtherStar™ Ethernet controller
NE86950
AC ELECTRICAL CHARACTERISTICS1, 2, 3 TA - 0 to 70"C' Vee -- 5V -+5% unless otherwise stated
LIMITS
Min
Typ
Max
UNIT
SYMBOL
FIGURE
tAvRL
14, tl
Address, select control valid to read low
10
ns
tRHAI
14, t2
Read high to address, select and control invalid
10
ns
tRLRL
14, t3
Read low to ROY low'
35
ns
tRHRH
14,14
Read high 10 ROY high
35
ns
tRLDV
14,15
ROY low 10 data valid
22
ns
IRHDT
14,16
Read high 10 data Ihree state
12
45
ns
PARAMETER
ns
tRDW
14,17
Read pulse width
35
IAVWL
15,11
Address, selecl and control valid to write low
10
ns
IWHAI
15, t2
Write high to address, selecl and control invalid
10
ns
tWRw
15, t3
Write pulse widlh
35
tDs
15,14
Write low 10 dala valid
IoH
15, t5
Wrile high 10 data invalid
IWLRL
15,16
Write low 10 ROY low5
35
ns
tWHRH
15, t7
Write high 10 ROY high
35
ns
tWHBRH
16, tl
Write high to bus request high
23
62
ns
tBALEH
16, t2
Bus acknowledge low 10 end of process
10
ns
IEpw
16, t3
End of process pulse width
20
ns
10
ns
5
30
IELBAH
16, t4
End of process low to bus acknowledge high
IBALBRL
17,11
Bus acknowledge low to bus request low
tBAHBRH
17,12
Bus acknowledge high to bus request high 6
8
ns
ns
ns
35
ns
50
ns
laAWS
17,13
Bus acknowledge low 10 read/write low
10
ns
IBAWH
17,14
Readlwrite high to bus acknowledge high
10
ns
IRWLRL
17,15
Readiwrile low to ROY low
35
ns
IRWLRH
17,16
Readlwrite high 10 ROY high
35
ns
tLBcD
18,11
Loopback conlrol delay
30
90
ns
ITMD
18,12
Tesl mode signal delay
30
80
ns
IINTO
18,13
Inlerrupl signal mask/clear delay
30
80
tTEND
18,14
Transmit enable dealy7
ns
2.3
iJ-s
ns
teyC
19
TCKN cycle
100
IRC
19
Random readlwrite cycle
300
tRAC
19
Access time from Rl\S
150
ns
teAC
19
Access time from CAS
100
ns
toEA
19
Access time from DE
90
ns
IDBC
19
Data hold before CAS high
-8
ns
tRP
19
100
ns
IRAS
19
Rl\S precharge time
Rl\S pulse widlh
165
ns
tePN
19
CAS precharge lime
100
ns
teAS
19
CAS pulse widlh
160
ns
tAsR
19
Row address setup time
45
ns
ns
tRAH
19
Row address hold time
23
ns
tAse
19
Column address setup lime
11
ns
leAH
19
Column address hold lime
166
ns
Iwcs
19
Wrile command setup time
50
ns
IWCH
19
Wrile command hold time
108
ns
July 23, 1990
452
Product Specification
Philips Components-Signetics Data Communication Products
NE86950
EtherStar™ Ethernet controller
AC ELECTRICAL CHARACTERISTICS1, 2, 3 (Continued)
LIMITS
SYMBOL
FIGURE
PARAMETER
Min
Typ
Max
UNIT
twp
19
Write command pulse width
185
ns
tos
19
Data to CAS setup time
55
ns
tOH
19
Data from CAS hold time
120
ns
toES
19
DE to RAS inactive setup time
80
tRCO
19
RAS to CAS delay time
50
toEc
19
DE to CAS high
6
teRS
19
"CAS" to RAS setup time
tRHC
20, t15
Refresh cycle
tRAS
20, t16
RAS pulse width
165
ns
tASR
20, t17
Row address setup time
45
ns
tRAH
20, t18
Row address hold time
150
tTCL
21-24, tl
Transmit clock low width
35
50
tTCH
21-24, t2
Transmit clock high width
35
50
tTED
21-24, t3
TCKN low to transmit enable
tTOH
21-24, t4
Transmit data hold
12
tTEH
21-24, t5
Transmit enable hold
13
tTINT
21-24, t6
Transmit interrupt to transmit enable low
teOLw
21-24, t7
Collision detect width
teaLs
21-24, t8
Collision inactive spacing
!caLL
21-24, t9
Minimum collision length
ns
68
ns
ns
ns
55
15.5
~s
ns
ns
ns
52
ns
ns
ns
TCKN
cycles
1
ns
20
200
520
ns
ns
tJAM
21-24, tl0
Jam periods
32
TCKN
cycles
tlNTP
21-24, tllp
Transmit interrupt when collision at preamble
5
TCKN
cycles
tlNTA
21-24, tlla
Transmit interrupt when collision at data field
16
TCKN
cycles
teJ
21-24, t12
Collision to first jam bit
tTDS
21-24, t13
Transmit data setup
40
tRCL
25, tl
Receive clock low width
35
50
ns
tRCH
25, t2
Receive clock high width
35
50
ns
tRDS
25, t3
Receive data setup
10
ns
tRDH
25, t4
Receive data hold
10
ns
tRCSS
25, t5
Receive carrier sense setup
10
ns
12
ns
RCKN
cycles
4
12
TCKN
cycles
ns
tRCSH
25, t6
Receive carrier sense hold
tRINTG
25, t7
Last bit of good packet received to interrupt
40
RCKN
cycles
tRINTE
25, t8
Receive interrupt after bad packet
15
RCKN
cycles
tTxs
26, tl
Transmit width short
4.95
5.05
TCKN
cycles
tTXL
26, t2
Transmit width long
9.95
10.05
TCKN
cycles
tRXS
26, t3
Receive width short
4.1
5.9
TCKN
cycles
July 23, 1990
7
453
Philips Components~ignetics Data Communication Products
Product Specification
EtherStar™ Ethernet controller
NE86950
AC ELECTRICAL CHARACTERISTICS1, 2, 3 (Continued)
LIMITS
SYMBOL
FIGURE
Min
PARAMETER
Typ
9.1
Max
UNIT
10.9
TCKN
cycles
tRXL
2S,t4
Receive width long
IcLTE
2S,tS
TCKN low to transmit enable
tTAFM
2S,tS
TEN active to first bit Manchester code
10
TCKN
cycles
tTWL
2S, t7
Transmit width length
10
TCKN
cycles
tTILM
2S, t8
TEN inactive to last bit Manchester code
15
TCKN
cycles
50
ns
NOTES:
1. Parameters are valid over specified temperature range and supply voltage range unless otherwise noted.
2. All voltage measurements are referenced to ground (GNO). All time measurements are referenced at input and output levels of 1.5V. Forlesting,
all inputs swing between O.4V and 2.4V. See Figure 13.
3. AC test condition: for bidirectional busses (SOO-SOI5, BOO-BOI5) CL = 85pF, for all other outputs C L = 6OpF. See Figure 13.
4. When reading from the buffer memory port, BMPRO, a worst case time of 2.25!,s may occur if the buffer manager is required to service simultaneous access requests from the system, the refresh controller, and the network (operating in loopback mode). The worst case time is 2.4!,s if
the system attempts to read an empty receive buffer memory. A BUS_RO_ERR will occur in the latter case.
5. When writing to the buffer memory pori, BMPRO, a worst case time of 2. 25!,s may occur if the buffer manager is required to service simultaneous
access requests from the system, the refresh controller, and the network (operating in loopback mode.) The worst case time is 2.4!'S ifthe system
attempts to write to a full transmit buffer memory. A BUS_WR_ERR will occur in the latter case.
S. A worst case time of 2.2S!,s may occur if the buffer manager is required to service simultaneous access requests from the system, the refresh
controller, and the network (operating in loopback mode).
7. This timing assumes that the network is free.
8. The 32 jam bits include eight data bits and 24 '0' bits.
MAIN OR LOCAL
SYSTEM BUS
NE89650
ETHERSTAR
'NOT NEEDED IN STARLAN
CONAGURATIONS
Figure 1, Typical System Configuration
July 23, 1990
454
LAN
NETWORK
MEDIA
Product Specification
Philips Components-Signetics Data Communication Products
EtherStar™ Ethernet controller
GENERAL DESCRIPTION
The NE86950 EtherStar is a highly
integrated, local area network controller that
supports both IEEE 802.3 CSMAlCD 10Mbls
Ethernet and 1Mbls StarLAN protocols.
Configurable for 8- or IS-bit wide bus
interfaces, it links a host system bus to the
local area network (LAN) transceiver or
drivers in cost sensitive network applications
such as personal computers, terminals,
workstations, and other resource-sharing
controllers with the minimum amount of
controlling software and host systemEtherStar interaction. Its design enables the
controller to be connected directly on the
main system bus without contention with the
host CPU for the bus. Also, there is no need
for a dedicated local CPU to handle data
transfers.
EtherStar arbitrates access to a dedicated
DRAM or SRAM buffer memory of up to 64
Kbytes in size. The transfer of data frames
to/from the host system and the transmission/
reception of data frames tolfrom the network
media can occur simultaneously. EtherStar
supports transfers tolfrom the system using
programmed I/O or DMA. EtherStar integrates a data link controller (DLC), a 1Mb/s
Manchester encoder/decoder, a dynamic
memory controller (DMC), and a buffer manager to arbitrate simultaneous access to the
buffer memory by the host system CPU and
the data frames from the LAN media. The
DLC block provides for automatic generation
and stripping of the 64-bit preamble, 32-bit
CRC generation/checking, serial and parallel
data conversions, automatic retransmission,
contention resolution by binary exponential
back-off, and address recognition for 10Mb/s
Ethemet and 1Mbls StarLAN supporting
IEEE 802.3 CSMAlCD specifications.
SYSTEM CONFIGURATION
A typical system configuration for the
NE86950 EtherStar is shown in Figure 1. On
the host side, EtherStar interfaces to the
system bus to obtain configuration
information for its internal control registers, to
provide receive and transmit status
information from its internal status registers,
to move data packets to be transmitted from
the host memory to EtherStar's dedicated
buffer memory, and to deliver received data
packets from the dedicated buffer memory to
the host system. The network side
connection depends on the protocol mode of
operation. For Ethernet mode, EtherStar
connects to the LAN media via an external
Manchester encoder/decoder (such as
Signetics' NE502A) and an Ethernet
transceiver (such as the Signetics NE8392A).
In StarLAN mode, the encoding/decoding
function is performed internally, and EtherStar
July 23, 1990
NE86950
attaches to the LAN media via appropriate
RS-422 drivers and receivers.
BUFFER MEMORY
As described above, the NE86950 uses a
dedicated buffer memory for intermediate
storage of data frames to be transmitted and
of data frames received from the network.
The BSO and BSI input pins configure
EtherStar to operate with 8, 16,32 or 64
Kbytes of buffer. This memory is partitioned
into two separate address spaces: the first
four Kbytes are reserved for transmit buffers,
while the remainder of the memory is used
for a receive buffer (see Figure 2).
n
TRANSMIT BUFFER 1
(2KAXEO)
BUFFER
-------- TRANSMIT
RING
U
TRANSMIT BUFFER 2
(2K AXED)
4K
RECEIVED PACKET n+3
(LAST PART)
CURRENTLY AVAILABLE
FREE BUFFER AREA
RECEIVED PACKET n
n
RECEJVE BUFFER
RING
(60KBYTES MAlt)
RECEIVED PACKET n+ 1
RECEIVED PACKET n+2
RECEIVED PACKET n+3
(ARSTPART)
jJ
NOTES:
1. L = 8, 16, 32 OR 64 Kbytea
2. Packets are aligned on an eight byte
boundary
3. each received packet i. preceded by •
~o;:~ ~~,.~~~~t~n:::r 8. follows:
Byte 1 - Not Used
Byte 2 - Packet Size lSBa
Byte 3 - Packet Size MS8.
Figure 2. Buffer Memory Organization
EtherStar supports both programmed I/O and
DMA transfers between the buffer memory
and the host system. The host accesses the
buffer memory by reading from or writing to
EtherStar's buffer memory port register,
designated BMPRO. The ROY signal
synchronizes these transfers to
accommodate other internal buffer access
requests.
Access to the transmit and receive buffers is
completely managed by EtherStar. As
required, it updates its internal pointers to
these buffers for the tasks of transmission,
retransmission, reception, rejection of bad
frames, and data transfers to and from the
host. Thus, the host is relieved of these buffer
455
management functions, making EtherStar
extremely easy to operate and reducing
firmware requirements substantially.
Transmit Buffer
The transmit buffer space is divided to form a
ring structure of two transmit buffers, each
two Kbytes in length. These function in a
'ping-pong' manner to permit one of the
buffers to be loaded by the host while the
contents of a previously loaded data frame
are being transmitted to the network.
Internal pointers, managed by EtherStar,
control which of the two buffers is selected for
access by the host and which bytelword of
that buffer is written to. At reset, the pointers
are initialized to point to the beginning of one
of the transmit buffers. Each time the host
writes data to the buffer via BMPRO, an
internal pointer is advanced to the next
memory location within the transmit buffer.
Once a data byte/word is written it cannot be
read, and the internal pointer cannot be
reversed. When the host has completed
loading an outbound data packet into the
buffer by successive writes to BMPRO, it
initiates transmission of that data packet to
the network by writing the length of the
outbound packet to the packet length register
within EtherStar. The internal pointers are
then automatically set to point to the
beginning of the second transmit buffer; that
buffer is then available to be loaded with the
next outbound packet. When the contents of
the first data buffer are successfully
transmitted, it again becomes available for
use by the host.
Receive Buffer
Buffer memory from 4K through the end of
memory is used for receiving packets from
the network. This portion of the buffer is not
partitioned into fixed length buffers, but is
dynamically allocated as packets are
received. Each received packet is preceded
by a four byte header which provides packet
status and the length of that data packet. All
receive buffers are aligned on an eight byte
boundary and are linked by internal pointers
to form a ring structure.
A status bit in one of EtherStar·s internal
registers informs the host when one or more
packets are resident in the receive buffer
memory and available to be read. The host
retrieves these packets from the buffer
memory by successive reads of BMPRO.
Once a data bytelword is read from the buffer
memory, internal pointers are advanced and
that memory becomes available for reception
of new packets.
If EtherStar detects a bad incoming packet
(CRC error, etc.), it releases the buffer space
in which that packet is contained and resets
Philips Components-Signetics Data Communication Products
Product Specification
EtherStar™ Ethernet controller
NE86950
its internal pointers so as to use that space
for the next incoming packet. If an incoming
packet requires more space than remains
available in the buffer, that packet is
automatically rejected.
I
HOST CPU SYSTEM INTERFACE
TRANSMIT
AND
SIMULTANEOUSLY
RECEIVE·
READ
NE86950 FUNCTIONAL
DESCRIPTION
OR
WRITE
As illustrated in the block diagram, the
NE869S0 consists of five major functional
blocks: system interface, buffer manager,
DRAM controller, data link controller, and
StarLAN encoder/decoder. The operation of
these blocks is described below.
System Interface
The system interface block provides the
connection between EtherStar and the host
CPU. EtherStar supports both 8- and 16-bit
bus architectures and byte or word transfers.
It may be operated in I/O-mapped, memory
mapped, or DMA modes. Two interrupt
outputs, TfIIIT and RmT, are provided which
may be programmed by the user to alert the
host CPU of transmitter and receiver status
conditions requiring host intervention.
Two sets of user accessible registers are
contained within EtherStar: the data link
control register set and the buffer memory
port register set. Address decoding circuits
within the system interface block select the
appropriate register within the NE86950 for
read and write transactions. All registers are
accessible as bytes. Additionally, when the
interface is configured for word mode (BiW =
0), the registers in the BMPR set can be
accessed as bytes or as words.
Buffer Manager
The buffer manager automatically arbitrates,
prioritizes and services requests for access to
the buffer memory from the data link
controller, the refresh timer within the DRAM
controller, and the host system, in that order.
It updates all buffer memory pointers,
allocates memory space for incoming data
packets, and controls pertinent bits within the
status registers.
The arbitration mechanism interleaves the
buffer memory accesses without loss of data,
so that operation appears to be
'simultaneous': data can be written to or read
from the buffer memory by the host via
BMPRO while data frames are retrieved for
transmission andlor provided for storage by
the data link controller. Thus, the buffer
manager supports all the cases of
'simultaneous' access to the buffer memory,
as conveyed in Figure 3 and as follows:
July 23, 1990
ETHERSTAR
BUFFER
MANAGER
t
I
I
NETWORK
MEDIA
-
INTERLEAVE
DATA
DEDICATED
BUFFER MEMORY
I
·RECEIVER IS ALWAYS ON
TRANSMIT WHILE SIMULTANEOUSLY RECEIVING
OCCURS IN LOOPBACK OR BROADCAST MODE.
Figure 3. Simultaneous Operations
Possible with EtherStar
1. The host can transfer a packet to a
transmit buffer while data from the network is
stored in a receive buffer.
2. The host can retrieve a packet from a
receive buffer while data from a transmit
buffer is obtained by the data link controller.
3. The data link controller can obtain data
from a transmit buffer while the host loads the
next packet into the second transmit buffer.
4. The data from the network is stored in a
receive buffer while the host reads the data in
another receive buffer.
5. The host retrieves a packet from a receive
buffer while the network side stores data in a
different receive buffer and obtains data from
a transmit buffer (e.g., in loopback or
broadcast address modes).
6. The host delivers a packet to a transmit
buffer while the network side obtains data
from the second transmit buffer and stores
data in a receive buffer (e.g., in loopback or
broadcast address modes).
DRAM Controller
The DRAM controller provides address
multiplexing, timing and automatic refreshing
for a DRAM dedicated buffer memory. In 8-bit
bus mode (BiW = 1) EtherStar supports a
memory of up to 64Kx8. In 16-bit bus mode
(BIW = 0), a memory of up to 32Kx16 can be
used.
Data Link Controller
The data link controller (DLC) fully
implements the IEEE 802.3 CSMNCD
specification for 10Mb/s Ethernet and 1Mb/s
StarLAN. It assembles data packets for
456
transmission and disassembles received da.ta
packets. The DLC provides for automatic
generation and stripping of the 64-bit
preamble, 32- bit CRC generation and
checking, contention resolution by binary
exponential back-off, several modes of
address recognition, and serial/parallel and
paralleVserial conversions.
Receiver
The receiver includes a receive state
machine, serial to parallel converter,
preamble recognition circuitry, address
comparison logic for the various modes of
address recognition, CRC checker and a
FIFO.
The receiver state machine provides
sequencing of events for the receiver,
including idle, address recognition, data, CRC
check and hold. It detects various receive
error conditions and sets appropriate bits
within the DLC registers.
A six byte receive data FIFO provides a small
elastic buffer for synchronization with the
buffer manager timing, and to hold data in the
event that the buffer manager is serviCing
another buffer memory access reques!.
All received bytes are delayed by four bytes
so that the last four bytes of the packet can
be trapped and checked for correct CRC.
These CRC bytes are not transferred to the
receive buffer.
During reception, Pllckets are automatically
rejected if space in the receive buffer is
insufficient to hold the entire received frame
or if certain error conditions are detected.
Status bits in the receive status register are
set to indicate these occurrences.
Transmitter
Circuits within the transmitter include a
transmitter state machine, a FIFO, preamble
generator, GRG generator, parallel to serial
converter, back-off generator and a time
domain reflectometer (TOR) counter.
The transmitter state machine provides
sequencing of events for the transmitter,
including idle, preamble, data, GRG,
interframe gap, jam and back-off. It detects
various transmit error conditions and sets
appropriate bits within the DLG registers.
The two-byte FIFO provides a small amount
of elastic buffering that the buffer manager
can load with data to be transmitted. The
GRG generator produces the standard
Ethernet 32-bit GRC that is appended to the
end of the packet data field.
A 17-bit pseudo-random number generator
provides for the back-off function. This is
clocked at the bit rate so that distances
between stations become part of the
Philips Components-Signetics Data Communication Products
Product Specification
EtherStar™ Ethernet controller
randomizing function. It is sampled at the
time of collision and counted down at the slottime rate (512 bits) defined in the Ethernet
specification, which provides a binary
exponential back-off from collisions.
The TOR function is provided by a 14-bit
counter that counts the actual number of bits
transmitted for each packet before a fault
condition occurs. See DLCR7 and DLCR15
description for full details of operation.
If EtherStar detects a collision during
transmission (XCOI: input asserted in
Ethernet mode, internal detection in StarLAN
mode), it will automatically try to re-transmit
the packet until sixteen attempts have been
made. Status bits in the transmit status
register are set in case of a collision and
sixteen consecutive collisions.
Starlan Encoder/Decoder
This unit is operational when the NE86950 is
set for StarLAN mode by tying the ETiSTAR
configuration pin LOW.
When transmitting data, the encoder section
converts the 1Mbls serial NRZ stream from
the DLC to Manchester code and detects
collisions. EtherStar monitors its receive input
during transmission and assumes a collision
has occurred if the received Manchester
encoded data is not valid (i.e., anything but
valid Manchester). However, this received
data is not transferred to the data buffer
unless the loopback mode has been enabled.
When receiving, a digital phase locked loop
within the decoder section extracts a
synchronized clock from the received data
stream, while simultaneously converting the
Manchester encoded data to NRZ form. The
synchronized clock and data are then passed
to the data link controller.
REGISTERS
The operation of the NEB6950 is
programmed prior to beginning operation by
writing control words into appropriate
registers within the device. Operational
feedback is provided by status registers
which can be read by the CPU. Certain bits
in the control registers can also be
manipulated during operation to change the
device's operation, e.g., which status bits are
enabled to cause interrupts. The user
accessible registers within EtherStar are
divided into two sets: the data link control
register set and the buffer memory port
register set. Table 1 defines the address
decoding for these registers.
The data link control register set, consisting
of the 16 registers DLCRO-OLCRI5, contains
transmit control and status registers, receive
control and status registers, transmit and
July 23,1990
NE86950
receive interrupt masks, and node 10
registers. The registers within this set are
byte aligned and byte accessible. The node
10 registers (DLCRB--DLCRI3) are protected;
their contents can only be changed when the
data link controller is disabled by setting the
enable data link controller bit, DLCR6<7>, to
a '1', or immediately after device reset.
The buffer memory port register set provides
the host with the mechanism to access the
transmit and receive buffers, as well as
controlling DMA operation. This set contains
the buffer memory port register (BMPRO),
transmit packet length registers
(BMPR2-BMPR3), and a DMA control
register (BMPR4). These registers are word
aligned and byte or word accessible. When
the host reads from or writes to BMPRO, the
RlJ'i' output synchronizes the data transfer,
since there may be higher priority requests
for access to the buffer memory pending from
the data link controller andlor from the DRAM
refresh controller. If the buffer manager
cannot respond to the host's access request
within 2.4f!s, it sets an appropriate status bit
(bus read error or bus write error) and then
asserts RlJ'i' while simultaneously asserting
the corresponding interrupt line (RTl'IT or
TINT). This will not typically occur during
normal operation, but only if the host
attempts to read from an empty receive buffer
or to write to a full transmit buffer.
Reset
A reset pulse with a minimum duration of 2f!s
is applied to the RESET input after power on,
or at any other time, to reset the internal
pointers and other logic within the NE86950.
Reset disables the data link controller
(effectively setting DLCR6<7> to a '1'), sets
DLCR5<6>, BUF_EMP, to a '1', and clears
the following bits:
DLCRO
DLCRI
DLCR2
DLCR3
DLCR5
BMPR4
5,6,7
0,4,6
4,7
5,6
5
0, 1,2,3
The state of all other bits within the registers
after reset is indeterminate.
Initialization
Initialization is performed by software to place
EtherStar into a known functional state. This
includes setting the transmit and receive
interrupt conditions, transmission and
reception modes, and the node address that
EtherStar responds to. A flow chart of the
initialization process is shown in Figure 4.
In byte mode (EliW = 1), all registers are
accessed as bytes. Note that when accessing
the buffer memory in byte mode, successive
bytes are read or written from BMPRO. When
the interface is config ured for word mode
(BIW = 0), all transactions to the buffer
memory port must be word transactions;
successive words are read or written from
BMPRO. The other registers in the BMPR set
can be accessed as bytes or as words,
depending on the state of the BFfE and SAO
inputs, as described in the Pin Descriptions
table.
Tables 2 and 3 provide an overview of the
contents and functions of each register in the
DLCR set and the BMPR set, respectively.
Detailed descriptions of the registers are given in tables 4 and 5.
OPERATION
The operation of the NE86950 can be
considered in four major operational phases:
reset, initialization, packet transmission, and
packet reception. Although described
separately here, packet transmission and
reception can be performed concurrently in
actual operation. In the sections that follow,
interrupt-driven operation is assumed.
457
Figure 4. NE86950 Initialization
Before any initialization begins, EtherStar
should be disabled by writing a value of H'80'
to DLCR6. This disables the data link
controller and enables access to the node 10
Product Specification
Philips Components-Signetics Data Communication Products
EtherStar™ Ethernet controller
registers (DLCRS through DLCRI3). The
DLCR register set is then initialized, in any
order, based on the communication
requirements. The basic programming is as
follows:
DLCRO-Transmit Status: A value of H'OF' is
written to clear all transmit errors.
NE86950
Transmit Initiation
The first phase is illustrated in Figure 5. To
transmit a packet, the host loads the
outbound packet into a transmit buffer,
initiates transmission, waits for EtherStar to
clear the TMT_OK bit, sets a transmit
pending flag, and sets the transmit interrupt
masks.
OLCR1-Transmlt Interrupt Masks: The
transmit interrupts are disabled by writing a
value of H'OO' at initialization. Desired
interrupts should be enabled prior to a packet
transmission.
Packet Transmission
July 23, 1990
2 BYTES
DATA
MINIMUM
DATA LENGTH
IS 46 BYTES
FOR IEEE 802.3
Figure 6. Transmit Packet Format
(with the TMST bit set) to the packet length
register (BMPR3:BMPR2). Note that the
packet length value is in bytes regardless of
whether the NE86950 is configured in word
mode or in byte mode. If operating in word
mode, and the packet length is an odd value,
the MS byte of the last word sent to the buffer
will not be transmitted.
OLCR5-Recelve Mode: A value is written per
system requirements to enable/disable CRC
testing, set the address size, enable/disable
short packet reception, enable/disable remote
reset packet reception, and to set the
address recognition mode.
An outbound packet is transmitted in two
phases. In phase one, the packet is
transferred from host memory to a transmit
buffer in EtherStar and the transmission is
initiated. In phase two, a transmit interrupt is
used to report successful transmission or a
transmit error condition.
6 BYTES
DATA LENGTH
TOTAL LENGTH ALLOWED BY THE NE86950 IS
BETWEEN SIX BYTES AND 2KBYTES.
OLCR4-Transmit Mode: Normally, a value of
H'02' is written to disable chip test, test mode
and loop back, and to enable carrier detect.
When this initialization is completed, the data
link controller is enabled by writing H'OO' to
DLCR6. A delay of 1511S, the time needed by
EtherStar to complete internal initialization,
must be guaranteed between the trailing
edge of reset and clearing of DLCR6. In
StarLAN mode only, an additional delay of
120!,s after the OLC is enabled is required
before EtherStar is ready to begin transmit or
receive operations.
SOURCE ADDRESS
TOTAL LENGTH ALLOWED BY IEEE802.3IS
BETWEEN 64 BYTES AND 1.518 BYTES,
INCLUDING THE FOUR BYTE CRC WHICH IS
GENERATED AND APPENDED BY THE NEil6950.
OLCR3-Recelve Interrupt Masks: Required
receive interrupts are enabled by writing the
appropriate value. These may be changed
during operation, based on reception criteria.
If this initialization is part of an error recovery
procedure, BMPRO should be read twice to
assure that certain internal pipeline registers
are cleared. If a BUS_RD_ERR results from
these read operations, it should be ignored.
GBYTES
PAD
(IF DATA ts LESS
THAN 46 BYTES)
OLCR2-Receive Status: The value H'CF' is
written to clear all receive errors.
OLCR8 to OLCR13-Node 10 Registers: The
six byte address programmed into these
registers must be unique. It is used in
conjunction with the address match mode bits
(DLCR5<1 :0» for packet reception.
DESTINATION ADDRESS
Figure 5, Transmit Initiation
A transmit packet, Figure 6, contains a six
byte Destination Address, a six byte Source
Address, a two byte Data Length, and data.
EtherStar is capable of transmitting packets
with a total packet length of six to 2,048
bytes, depending on the configuration set at
initialization. (Software conforming to the
IEEE 802.3 specification must guarantee that
the total packet length is in the range of 64 to
1,518 bytes including the four-byte CRC,
which is calculated by EtherStar and
appended to the packet when it is
transmitted.)
The packet is loaded into a transmit buffer
using the buffer memory port register
(BMPRO). At initialization or the initiation of a
transmission, EtherStar's internal pointers are
advanced to the beginning of the next
available transmit buffer. The packet is
transferred from the host to a transmit buffer
by successive writes of data, starting at the
beginning of the packet, to BMPRO. The
internal pointers manage the placement of
the data into the current transmit buffer.
When the entire packet has been loaded,
EtherStar is requested to send the packet by
writing the total length of the transmit packet
458
When the network is free and EtherStar
actually begins transmitting the packet to the
LAN, it will clear the TMT_OK bit. The
TMT_OK_MSK bit must not be set until
TMT_OK is cleared to prevent an erroneous
transmit interrupt from being generated. The
host can load the next packet into the second
transmit buffer immediately after it sets TMST
for the previous packet, but the TMST bit
cannot be set for that second packet until the
lirst packet has been successfully transmitted
to the LAN.
When using a common interrupt service
routine (ISR) to handle both transmit and
receive interrupts, a transmit pending flag is
required within the driver to distinguish
whether TMT_OK was set to indicate the
completion of a pending transmission or is
the residue of a previous transmission, since
the software does not have the ability to clear
TMT_OK after completion of a pending
transmission.
Once the transmit has been initiated and the
TMT_ OK bit is cleared by EtherStar, the
transmit interrupt masks are set. Typically, a
value of H'82' is written to the transmit masks
register (DLCR1) to enable transmission
interrupts based on transmit complete, and
16-collision error. The COL and underflow
error interrupts may optionally be enabled.
Philips Components-Signetics Data Communication Products
Product Specification
EtherStar™ Ethernet controller
NE86950
Transmit Interrupt Routine
When a packet is successfully transmitted or
a transmit error condition occurs which has
its corresponding transmit interrupt mask set
in DLCR1, a transmit interrupt (TfliIT), is
generated, A typical transmit interrupt service
routine (ISR) to service this interrupt is shown
in Figure 7,
collision counter wraps around to 0, 16_COL
is set and EtherStar will not retransmit If
COL is set and 16_COL is not set, the
collision counter will contain the number of
collisions encountered on that transmission.
Recovery is accomplished by clearing the
On entering the ISR, the transmit interrupt
masks are cleared by writing H'OO' to DLCR1,
to prevent nested interrupts. These masks
may need to be saved and rewritten prior to
exiting the ISR. If the transmit pending flag is
set, the status of TMT_OK is checked, If it is
set, the packet has been successfully
transmitted; the routine clears the transmit
pending flag and takes any other driver
specific action, This may include signaling
successful transmission to the upper layer
network soltware and/or initiating another
transmission.
Prior to exiting the ISR, the transmit pending
flag is checked to see if there is an
outstanding transmission. If set, then the
transmit interrupt masks, which were cleared
on entering the ISR, must be written back to
DLCR1 to interrupt when the transmission
completes,
The major error conditions which must be
handled by the ISR are bus write error and
16~collision error. BUS_WRT _ERR is not the
result of a transmission by the DLC, but
indicates that an attempt was made to
transfer data to a transmit buffer and the
transmit buffer was full. The ISR clears the
bit, increments a bus write error counter in
the driver for diagnostic purposes, and
performs any other driver specific recovery
action. 16_COL indicates that sixteen
collisions have occurred in the transmission
of a single packet and that EtherStar has
aborted attempting to transmit that packet
This error is handled by clearing the error bit,
incrementing a 16~collision error counter in
the driver for diagnostic purposes, and
performing any driver specific recovery
algorithms,
Note: If, after 16 collisions have occurred, the
host wishes to attempt to transmit the same
packet again, it must reload that packet into
one of EtherStars' transmit buffers.
UDR_FLO will not occur during normal
operation, but may be the result of some
other error condition. This error is handled in
a manner similar to 16_COL
Setting of the collision error status bit, COL,
indicates that at least one collision occurred
in the transmission of a single packet
EtherStar will continue to re~transmit the
packet up to sixteen times, Each time the
packet fails to transmit due to colliSion, a
collision counter in the transmit mode register
(DLCR4<7:4» is incremented, When the
July 23, 1990
COL bit and incrementing a collision error
counter if desired,
Packet Reception
Incoming packets are examined for a match
in the destination address field of the
Ethernet header. Reception is based on the
address match mode bits and the ADD_SZE
bit in the receive mode register IDLCR5) and
the node ID IDLCR8 through DLCR13).
When a packet matches the defined
reception critena, it is copied into a receive
buffer and checked for overflow, CRC,
alignment or short packet errors If no errors
are detected, PKT_RDY in the receive status
register IDLCR2) is set and BUF_EMP in the
receive mode register IDLCR5) is cleared if
not already cleared, If an error is
encountered, the packet is discarded, making
the buffer memory occupied by that packet
available for reception of another packet, and
the appropriate error bits are set in DLCR2,
Addressing Modes
In addition to the normal single address
match mode, where the incoming address is
compared to the programmed node ID, the
NE86950 supports three special receiver
address match modes: promiscuous receive,
multicast address, and multicast group
address, These modes are enabled by setting
the address match mode bits in the receive
mode register appropriately, and may be
changed by the driver at any time. It is also
possible to set the transmit mode for
loopback, so that transmitted packets are not
sent the network, but are simply fed back into
the receiver.
In promiscuous receive mode, all good
incoming packets on the LAN are received
into buffer memory. No matching is done on
the destination address field of the packet.
This can be useful for network monitoring
applications and debugging.
459
A multicast address is identified by a value of
'1' in the least significant bit of the destination
address. Using multicast address mode will
cause all packets having a multicast address
to be received, Note that in this mode
EtherStar does not provide any hashing on
the multicast address and simply receives all
multicast packets.
When multicast group address mode is set,
packets will be received if the three least
significant bytes of the address match the
address in the node ID registers and the least
significant bit of the destination address is '1'
Receive Packet Structure
When a packet is successfully stored in the
receive buffer memory, EtherStar attaches a
four byte header in the front of the packet
The first byte is a copy of the receive status
register IDLCR2) in which bit 5 is set and the
PKT_RDY bit is invalid, The second byte is
reserved. The third and fourth bytes contain
the LS and MS bytes of the length of the
packet, respectively, Note that the packet
length value is in bytes regardless of whether
EtherStar is configured in word mode or in
byte mode
Receive Interrupt Routine
A receive interrupt IRJNT) is generated when
a packet is successfully stored in the receive
buffer memory or a receive error condition
occurs which has its corresponding interrupt
mask set in DLCR3. A typical receive
interrupt service routine (ISR) to service this
interrupt is shown in Figure 8.
On entering the ISR, the receive interrupt
masks are cleared by writing H'OO' to DLCR3,
to prevent nested interrupts, These masks
may need to be saved and rewritten prior to
exiting the ISR. If BUF_EMP is cleared, there
is at least one valid packet in the receive
buffer memory, and the ISR proceeds to
transfer that packet to the host. First,
PKT_RDY is cleared, Then, the receive
status byte and reserved bytes are read from
the buffer memory via BMPRO, lin this
model, these bytes are unused, but must be
read to advance internal pointers used to
control the extraction of received packets,)
The packet length is then extracted to
determine the size of the actual received
packet, and that packet is copied to host
memory by successive reads of BMPRO. The
ISR then checks BUF_EMP again to see if
additional packets remain in the receive
buffer memory and, if so, the steps described
above are repeated until all available packets
have been copied to the host
Philips Components~ignetics Data Communication Products
Product Specification
EtherStar™ Ethernet controller
NE86950
Figure 7. Transmit ISR
Note: Reading more than the specified
number of bytes extracts a portion of the next
receive packet or causes a BUS_RD_ERR.
Reading less than the specified number of
bytes leaves garbage at the beginning of the
next receive packet. These conditions can
generate a fatal error condition.
July 23,1990
Figure 8. Receive ISR
Note: If operating in word mode, and the
indicated packet length is an odd value, an
extra byte of invalid data will be read out of
the buffer on the last word read and should
be ignored. There is no danger of reading the
first byte of the next packet in this case
because the packets in the buffer memory
are aligned to start on an eight byte/four word
boundary.
460
Note: When a packet has been completely
read out of the buffer, EtherStar will re-assert
PKT_ROY if any packets remain in the
receive buffer. This feature can be used to
cause an interrupt to be generated for each
valid packet received and stored in the buffer.
Product Specification
Philips Components-Signetics Data Communication Products
EtherStar™ Ethernet controller
NE86950
BIW= 1
j
(BYTE CONAGURATION)
llllSlJ
DATA~B
aKB
aKW
16KW
16KB
(16K x 4) x 2 CHIPS
(16K x 4) x 4 CHIPS
a
' -___"7''-a--''DATA LSB
Q[
lIlISIJ32KW
32KB
(64K x 4) x 4 CHIPS
(16K x 4) x 4 CHIPS
a DATA LSB
Figure 9. Buffer Memory Implementation with DRAM
RAS1
SRAM
8K x 8
OR
32Kx8
The receive error conditions which can be
programmed to cause an interrupt are bus
read error, overflow, CRC error, alignment
error, and short packet. All except the first do
not require host intervention other than
tallying the error for diagnostic purposes;
EtherStar will automatically reject any packet
in which any of these error conditions is
detected.
the ENA_SRT_PKT bit in DLCR5 is set. six
bytes. For these errors, the sample ISR takes
no action other than clearing the error
condition and incrementing a corresponding
error counter.
BUS_RD_ERR indicates that an attempt was
made to transfer data from a receive buffer to
the host when the receive buffers are empty.
This should be considered a fatal error, where
the hardware or software is faulty. To recover,
the ISR clears the BUS_RD_ERR bit,
increments a bus read error counter, and
performs any other driver specific recovery
routine.
The NEB6950 supports DMA operation for
transfers of data between the host system
and the dedicated buffer memory. The BREO
and BliCK signals are used for handshaking
between the external DMA controller and
EtherStar.
Prior to exiting the ISR, the receive interrupt
masks are restored to enable future receive
interrupts.
DMA OPERATION
BIW=o
(WORD CONAGURATION)
o IHIrr
BA7
Q
ADDRESS
C LATCH
SRAM
SKxS
OR
32K x8
RlISl
DATA LSBS"7''-----'
SRAM
8K x 8
OR
32Kx8
DATA MSBS a
=r--------L~
Figure 10. Buffer Memory
Implementation with SRAM
July 23. 1990
OVR_FLO denotes that an incoming packet
from the LAN media was rejected because it
was longer than the amount of free memory
available in the receive buffer area.
CRC_ERR indicates that the incoming
packet's CRC did not match that calculated
by EtherStar. ALG_ERR signifies that the
incoming packet has a bad CRC at the last
octet boundary and the number of bits were
not divisible by eight. SRT_PKT indicates that
the iricoming packet does not meet the
minimum length requirement of 60 bytes, or if
461
DMA Write (Transmit)
TENA, BMPR4<0>, is set to a '\' to enable
DMA write operation for transfers of data
packets from the host memory to EtherStar's
transmit data buffer. When it is ready to
begin to accept data from the host, EtherStar
will assert its Bus Request output, BREO.
The host responds by asserting BliCK
followed by WAr and placing the data on the
data bus. EtherStar will negate BREO and
will assert its ROY' output when it is ready to
complete the current data transfer cycle.
When the host negates BliCK and WAr,
EtherStar accepts that data byte/word, moves
its internal pointer to point to the next
Philips·Components-Signetics Data Communication Products
Product Specification
EtherStar™ Ethernet controller
bytelWord, and then re-asserts BREa to
repeat the process. The DMA controller must
assert the End of Process input, EOP,
concurrent with the last byteIWord data
transfer to indicate that the entire packet has
been transferred. EtherStar will then
discontinue making further data requests.
To cause the 'packet to be transmitted, the
host must load its packet length into
BMPR3:BMPR2, asserting the TMST bit
when the MS byte is loaded into BMPR3.
TENA must be cleared when the packet
transfer is completed, and set again when the
host desires to begin loading another packet
into the transmit buffer using DMA.
NE86950
data requests. RENA must be cleared when
the packet transfer is completed, and set
again when the host desires to begin reading
another packet from the receive buffer using
DMA.
When EOP is asserted by the external DMA
controller, the EOP status bit, BMPR4<2>,
will be set to a '1' and will cause RINT to be
. asserted if BMPR4<3>, EOP-'NT_MSK, is
set. This interrupt can be used by the host to
clear RENA. The interrupt is cleared by
writing to BMPR4 with bit 2 set, which can be
done at the same time as RENA is cleared.
BUFFER MEMORY
IMPLEMENTATION
When EOP is asserted by the external DMA
controller, the EOP status bit, BMPR4<2>,
will be set to a '1' and will cause RINT to be
asserted if BMPR4<3>, EOP_INT_MSK, is
set. This interrupt can be used by the host to
initiate the actions described in the paragraph
above. The interrupt is cleared by writing to
BMPR4 with bit 2 set, which can be done at
the same time as TENA is cleared.
EtherStar is configured via the BSO and BSI
inputs to support buffer memory sizes of 8,
16, 32 or 64 ·Kbytes. Figures 9 and 10
illustrate the typical implementation of the
buffer memory for these options in both byte
and word modes using industry standard
DRAMs and SRAMs, respectively. Table 6
describes the relationship between the
internal address lines A 15:AO and the
multiplexed buffer addresses BA7:BAO.
DMA Read (Receive)
Although not neces~ary for operation~1
purposes, it is useful for debugging and
diagnostic purposes to describe how the
network side and the system side access the
buffer.
Prior to beginning the transfer of a data
packet from EtherStar's receive buffer
memory to the host memory via DMA, the
host must read the four-byte packet header to
determine the number of bytes/words in the
packet and should load that number into the
counter in the external DMA controller.
RENA, BMPR4<1>, is then set to a '1' to
enable DMA read operation to transfer the
actual packet tQ the host memory. When it is
ready to begin, EtherStar will assert its Bus
Request output, BREa. The host responds
by asserting BACK followed by mJ. EtherStar
will negate BREa and will assert its 1mY
output when it has placed the byte/word on
the data bus and is ready to'complete the
data transfer cycle. When the host negates
BACK and mJ, EtherStar moves its internal
pointer to point to the next byte/word, and
then re-asserts BREa to repeat the process.
The DMA controller must assert the End of
Process input, EOP, concurrent with the last
byte/ word data transfer to indicate that the
entire packet has been transferred.
EtherStar will then discontinue making further
July 23, 1990
Network Access'
The network side always transfers a byte at a
time to or from the buffer.
In word mode (BIW = 0), RAS'O is asserted
for each LS byte transferred to or from the
buffer and ~ is asserted for each MS
byte transferred to or from the buffer.'
In byte mode (B/W = 1), for 8, 16 or 64 Kbyte
configurations, RAS'O is asserted for every
byte transferred to or from the buffer. For 32
Kbyte configuration, RAS'O is asserted during
even byte transfers (AO = 0), while ~ is
asserted during odd byte transfers {AO = 1).
System Access
The system side transfers either a byte at a
time or a word at a time to or from the buffer,
depending on the mode selected.
462
In word mode (BIW = 0, both ~ and
~ are asserted for each word transferred
to or from the buffer. It is not possible to
address the bytes separately for this mode.
In byte mode (BIW = 1), for 8, 16 or 64 Kbyte
configurations, ~ is asserted for every
byte transferred to or from the buffer. For 32
Kbyte configuration, RAS'O is asserted during
even byte transfers (AO = 0): while ~ is
asserted during odd byte transfers (AO = 1).
LOOPBACK
A loopback capability is provided to allow
operation of EtherStar to be exercised
without sending signals onto the LAN media.
The loopback function is invoked by clearing
the J:'E!C bit, DLCR4<1 >, to a zero. The
complement of this bit appears at the
Loopback output, LBC. Operation is
illustrated in Figure 11.
STARLAN CONFIGURAllON
ETHERSTAR
I
TXOS •
RXOS
•
t
I
NO SIGNALS
AT
APPEAR
OUTPUT PINS
NO SIGNALS
APPEAR AT
OUTPUT PINS
Figure 11. Loopback Operation
In StarLAN mode, the TXDS output is
internally tied back to the RXDS input. The
transmit data' is blocked from appearing at
the TXDS pin, and the RXDS and XCO[
inputs ale ignored. Data is routed from the
tran.smit buffer, through the transmit section
of the DLC, through the internal Manchester
encoder, back to the Manchester decoder,
through the receive section of the DLC, and
is then stored in a receive buffer.
In Ethernet mode, operation is similar, except
that the data is output on TXD and received
at RXD. The external Manchester
encoder/decoder, such as the NE502A,
should respond to assertion of its LBC input
by looping its transmitter output to its receiver
input internally, and should block the transmit
data from appearing at its output pin.
Product Specification
Philips Components-Signetics Data Communication Products
EtherStar™ Ethernet controller
NE86950
O~1.5VTESTPOlNT~
==--"L------ 2AV
~ 1.SV TEST POINT
O.4V
RO
'------'h J
'------'h J
OUTPUT PIN
RECOMMENDED VALUES:
CRYSTAL OSCILLATOR
The NEB6950 requires a precise 10MHz
clock source for proper operation. In
Ethernet mode. this signal is normally
supplied from the external encoder/decoder.
In StarLAN mode. the signal may be supplied
externally, or may be generated from a crystal
by connecting the crystal as shown in Figure
12.
CL=60pF
BUS PIN
W-L,rkOMHz
RO=17on
CL
=85pF
=
C' 2DpF
C2 = 2DpF
Figure 13. Test Conditions
Figure 12. Crystal Connection
for StarlAN Mode
Table 1.
Internal Register Address Map
BYTE!
WORD
~
BYTE
1
1
0
0
0
0
0
DLCRO
Transmit Status
BYTE
1
1
0
0
0
0
1
DLCR1
Transmit Masks
BYTE
1
1
0
0
0
1
0
DLCR2
Receive Status
BYTE
1
1
0
0
0
1
1
DLCR3
Receive Masks
BYTE
1
1
0
0
1
0
0
DLCR4
Transmit Mode
BYTE
1
1
0
0
1
0
1
DLCR5
Receive Mode
BYTE
1
1
0
0
1
1
0
DLCR6
Software Reset
BYTE
1
1
0
0
1
1
1
DLCR?
TDR(LSB)
BYTE
1
1
0
1
0
0
0
DLCRB
Node IDO
BYTE
1
1
0
1
0
0
1
DLCR9
Node ID1
BYTE
1
1
0
1
0
1
0
DLCR10
Node ID2
BYTE
1
1
0
1
0
1
1
DLCR11
Node ID3
DSEI:
RSE[
SA3
SA2
SAl
SAO
DESCRIPTION
ADDRESS
BYTE
1
1
0
1
1
0
0
DLCR12
Node ID4
BYTE
1
1
0
1
1
0
1
DLCR13
Node 1D5
BYTE
1
1
0
1
1
1
0
DLCR14
Reserved
BYTE
1
1
0
1
1
1
1
DLCR15
TDR(MSB)
BOTH
1
0
1
0
0
0
0
BMPRO
Buffer Memory Port
BOTH
1
0
1
0
0
1
0
BMPR2
Packet Length LSB
BOTH
1
0
1
0
0
1
1
BMPR3
Packet Length MSB
BOTH
1
0
1
0
1
0
0
BMPR4
DMA Enable/Control
BOTH
0
1
1
X
X
X
X
BMPRO
Buffer Memory Port
July 23, 1990
463
Product SpeCification
Philips Components-Signetics Oata Communication Products
EtherStar™ Ethernet controller
Table 2.
Data Link Controller
OLeR
"""n"",,"
0
Transmit
Status
1
Transmit
I nterrupt Masks
NE86950
Set Summary
RD/WR
BIT7
REAO
I~!I~;IIII:
BIT6
BIT5
BIT4
BIT3
BIT 2
NETBSY
TMT
REC
SRTPKT
UORFLO
COL
WRITE
2
Receive
Status
3
Receive
Interrupt Masks
REAO
I!,r.:'
WRITE
I:'~IB
Transmit
Mode
5
Receive
Mode
T~~~C
CLR
-
CLR
CLR
-
MASK
UOR FLO
MASK
COL
MASK
16COL
-
-
MASK
UORFLO
MASK
COL
MASK
16COL
-
RMTRST
SRT PKT
ALG ERR
CRC ERR
CLR
CLR
CLR
MASK
SRTPKT
MASK
ALGERR
MASK
MASK
MASK
OVR FLO
'0"
REAO
~II~
-
-
WRITE
;~~~I~
-
-
MASK
RMTRST
MASK
SRT PKT
MASK
ALGERR
MASK
CRCERR
COLCTR
0
CHPTST
Tfii'I
me
me
REAO
COLCTR
COLCTR
2
COLCTR
1
WRITE
CHPTST
Tfii'I
REAO
ENA
SRTPKT
ENA
REMRST
ENA
ENA
Enable Oata
Link Controller
TST
TST
-
BUF FUL
BITO
.>i 1111~
MASK
RMTRST
WRITE
6
-
:·ij~~lij:··• :
REAO
WRITE
4
-
MASK
TMTREC
BIT1
AOOSIZE
OSC
OSC
AM1
AMO
AM1
AMO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AOO SIZE
WRITE
ONLY
ENA"lJ[C
TOR7
TOR6
TOR5
TOR4
TOR3
TOR2
TOR1
TORO
7
TOR (LSB)
REAO
ONLY
8
Node ID
RE~O
107
106
105
104
103
102
101
100'
9
Node ID
REAO
WRITE
1015
1014
1013
1012
1011
1010
109
108
10
Node 10
REAO
WRITE
1023
1022
1021
1020
1019
1018
1017
1016
11
Node 10
REAO
WRITE
1031
1030
1029
1028
1027
1026
1027
1028
12
Node 10
READ
WRITE
1039
1038
1037
1036
1035
1034
1033
1032
13
Node 10
REAO
WRITE
1047
1046
1045
1044
1043
1042
1041
1040
14
Reserved
15
TOR (MSB)
TOR13
TOR12
TOR11
TOR10
TOR9
TOR8
REAO
ONLY
-
-
NOTES:
1. • A '1' should never be written into these bits.
2. The shaded bits indicate those that should be closely monitored/controlled by the host. Other status bits in OLCR2 and OLCR4 are automatically
handled by EtherStar and are for information only, so thus may normally be masked.
July 23, ,1990
464
Product Specification
Philips Components-Signetics Data Communication Products
NE86950
EtherStar™ Ethernet controller
Table 3.
BMPR
0
Buffer Memory Port Register Set Summary
REGISTER
Buffer
Memory Port
ROIWR
BIT7
READ
IN BYTE MODE, CONSECUTIVE BYTES ARE READ FROM OR WRITTEN TO THE BUFFER
MEMORY BY READINGIWRITING BMPRO, IN WORD MODE, CONSECUTIVE WORDS ARE
READ FROM OR WRITTEN TO THE BUFFER MEMORY BY READINGIWRITING BMPRO.
WRITE
Packet
Length LSB
2
WRITE
ONLY
Packet
Length MSB
3
4
PL7
-
WRITE
ONLY
DMA
Enable/Status
-
-
TMST
BIT6
BITS
BIT3
BIT4
BIT2
BIT1
BITO
-
-
-
-
-
-
PL5
PL4
PL3
PL2
PL1
PLO
-
-
-
-
-
-
-
-
-
-
-
PL6
PL10
READ
-
-
-
-
EOP INT
MASK'
EOP'
WRITE
-
-
-
-
EOP INT
MASK'
CLR EOP
STATUS'
PL9
RENA
PL8
TENA
NOTE:
1.• These bits are not implemented in the NE86950A version of EtherStar
Table 4.
Data Link Controller Register Descriptions
DLCRO -Transmit Status, ReadlWrite
This register provides transmit status to the host. The user may program the assertion of bits 7, 5, 3, 2 and 1 of this register to cause the
assertion of the Transmit interrupt output (TINT =0) by setting the corresponding bits in DLCRI Assertion of bit 0 of this register will cause
assertion of TINT -this bit is not maskable.
Bits <3:0> may be cleared individually or in any combination by writing a '1' to those bits. The state of bits written with a '0' is not affected.
Bit <7:4> are cleared automatically as described below.
RDIWR
BIT7
BIT6
BIT S
BIT 4
BIT3
BIT 2
BIT 1
BITO
READ
TMTOK
NETBSY
TMTREC
SRT PKT
UDR FLO
COL
16 COL
BUS
WR ERR
CLR
CLR
CLR
CLR
WRITE
-
-
-
-
BIT
SYMBOL
DESCRIPTION
0
BUSWR ERR
BUS WRITE ERROR: This error condition occurs if a fIDY response cannot be issued within 2.4l.1s after the WRT
signal is asserted by the host system when writing to the buffer memory port register, BMPRO. Occurs when the
transmit buffer memory is full. This should not happen during normal operation.
1
16 COL
2
COL
COLLISION: This bit is set if a collision occurs during transmission of a data packet. The buffer manager will
automatically attempt to transmit the current packet up to 16 times. The user may determine the number of
consecutive collisions by reading the collision counter, DCLR4<7:4>.
3
UDR FLO
UNDERFLOW: This register is set when data from the transmit section of buffer memory is not available for serial
transmission. EtherStar will continue to send out this data frame. This should not occur during normal operation.
4
SRTPKT
SHORT PACKET: Set if the Received Carrier Detect input (XCD) is negated during a packet transmission. This can
be caused by a collision or a shorted LAN media. Automatically cleared as each transmission begins.
5
TMTREC
TRANSMIT RECEIVED: Indicates that a good packet was received by the receiver shortly after transmission was
completed. This is used to indicate seif-{8ception of the packet. This allows the software to take advantage of the
hardware address matching even in systems which are designed for half duplex operation. This bit is cleared as each
transmission begins.
6
NETBSY
NET BUSY: This is a copy of XCD, the Receive Carrier Detect pin.
7
TMTOK
TRANSMIT OKAY: This bit is set when a data packet is successfully transmitted. EtherStar clears this bit
automatically as each transmission begins and sets it automatically at the finish of each data packet transmission.
July 23, 1990
16 COLLISION: This bit is set after the sixteenth unsuccessful transmission of the same packet.
465
Product Specification
Philips Components-Signetics Data Communication Products
NE86950
EtherStar™ Ethernet controller
Table 4.
Data Link Controller Register Descriptions (Continued)
DLCR1 -Transmit Interrupt Masks, ReadlWrite
Bits 7, 5, 3, 2, 1 are the transmit interrupt masks. They can be set individually depending on system requirements. Setting a bit to a '1' causes
the assertion of the corresponding bit in DLCRO to assert 11fIT.
RD/WR
BIT 7
READ
WRITE
MASK
TMTOK
BIT6
-
BITS
BIT 4
MASK
TMTREC
-
BIT3
BIT2
BIT 1
MASK
UDRFLO
MASK
COL
MASK
16COL
BITO
-
DLCR2 -Receive Status, ReadlWrite
This register provides receive status to the host. The user may program the assertion of bits 7 and <4:0> of this register to cause the assertion
of the Receive Interrupt output (RmT = 0) by setting the corresponding bits in DLCR3. Assertion of bit 6 of this register will cause assertion
of RmT -this bit is not maskable.
Bits <7:6> and <3:0> may be cleared individually or in any combination by writing a '1' to those bits. The state of bits written with a '0' is not
affected. Bit 4 is cleared automatically as described below.
RD/WR
BIT7
BIT 6
READ
PKTRDY
BUS
RDERR
WRITE
CLR
CLR
BIT4
BIT3
BIT2
BIT1
BITO
RMTRST
SRTPKT
ALG ERR
CRC ERR
OVR FLO
CLR
CLR
CLR
CLR
BITS
-
-
'0'
BIT
SYMBOL
DESCRIPTION
0
OVRFLO
OVERFLOW: This bit is asserted if a received packet is discarded because there is insufficient memory space in the
receive buffer memory to accommodate the complete data packet. The space remaining is made available for shorter
data packets.
1
CRC ERR
CRC ERROR: This bit is set when the calculated CRC does not match the CRC at the end of the received packet.
2
ALG ERR
AUGNMENT ERROR: Set if a packet has bad CRC at the last octet boundary and the number of bits are not divisible
by eight.
3
SRT PKT
SHORT PACKET: Set if a data packet does not meet the minimum length requirements of 60 bytes or 6 bytes when
the enable short packet bit, DLCR5<3>, is on.
4
RMTRST
REMOTE RESET: This bit will be set when the ENA RMT RST bit, DLCR5<2>, is on and a receive packet with the
special data length 0900H is successfully received. The RMT RST bit, when set, will assert the PRES pin. The bit
is cleared at the beginning of the next packet reception. This bit is set only if the node ID matches, not on multicast
or broadcast addresses, in any address match mode (see DLCR5<1 :0».
-
S
6
BUS RD ERR
7
PKTRDY
RESERVED: Never write a "1" into this bit.
BUS READ ERROR: This error condition occurs if a Jm'i' response cannot be issued within 2. 41's after the rID signal
is asserted by the system when reading the buffer memory port register, BMPRO. Occurs when trying to read when
the receive buffer memory is empty.
PACKET READY: Set after the successful reception of packet data into the receive buffer memory.
DLCR3 -Receive Masks, ReadlWrite
Bits 7and <4:0> are the receive interrupt masks. Setting a bit to a '1 ; causes the assertion of the corresponding bit in DLCR2 to assert RmT.
July 23, 1990
RD/WR
BIT7
READ
WRITE
MASK
PKTRDY
BIT6
-
BITS
-
BIT4
BIT3
MASK
RMTRST
MASK
SRTPKT
466
BIT2
MASK
ALG ERR
BIT1
BITO
MASK
CRC ERR
MASK
OVR FLO
Product Specification
Philips Components-Signetics Data Communication Products
EtherStar™ Ethernet controller
Table 4.
NE86950
Data Link Controller Registers Descriptions (Continued)
DLCR4 -Transmit Mode, ReadlWrlte
This register controls certain transmit functions and provides the count of successive collisions on transmission attempts.
RD/WR
BIT7
BIT6
BIT 5
BIT 4
BIT3
READ
COLCTR
COLCTR
COLCTR
3
2
COLCTR
1
a
CHPTST
-
-
CHPTST
WRITE
BIT
SYMBOL
0
DSC
1
am
2
m
-
-
BIT2
BITl
BITO
m
m
am
am
DSC
DSC
DESCRIPTION
DISABLE CARRIER DETECT: When this bit is set the transmitter disregards XCD, the Carrier Detect signal.
LOOPBACK CONTROL: This bit controls the loopback function of the external encoder/decoder in Ethernet mode,
and the internalloopback function in StarLAN mode. The LBC pin signal value is the complement of the value of this
bit, '0' = Loopback, '1' =No Loopback.
TEST MODE: A bit whose complement is available as singal pin TM. Used for controlling power to the transceiver
or any other function external to the chip.
3
CHPTST
CHIP TEST: Signetics internal use. Always write a '0' to this bit for normal operation.
<7:4>
COLCTR
COLLISION COUNTER: Bits <7:4> keep track of the number of consecutive collisions during transmission of a data
packet.
July 23, 1990
467
Product Specification
Philips Components-Signetics Data Communication Products
NE86950
EtherStar™ Ethernet controller
Table 4.
Data Link Controller Register Descriptions (Continued)
DLCRS -Receive Mode, ReadlWrlte
This register controls certain receive functions and provides receive buffer memory status.
RD/WR
BIT 7
BITS
BITS
BIT 4
BIT3
READ
TST
BUF EMP
BUF FUL
ADDSZE
ENA
SRTPKT
WRITE
TST
-
-
ADDSZE
ENA
SRTPKT
BIT
SYMBOL
<1:0>
AM1,AMO
BIT 1
BITO
ENA
REMRST
AMI
AMO
ENA
REM RST
AMI
AMO
BIT2
DESCRIPTION
ADDRESS MATCH MODE: These two bits control address recognition and matching.
Bit 1
BitO
0
0
0
1
1
0
1
1
Function
Accept no packets.
Acce~t ~hysical address, multicast-ijroup addresses which
matc t e first three bytes, and broaacast address.
Accept physical address, all multicast addresses, and
broadcast address.
Accept all packets (promiscuous mode).
2
ENA
RMTRST
ENABLE REMOTE RESET: This bit is used to enable/disable the receipt of packets with the special data length
0900H. See DLCR2<4>.
3
ENASRTPKT
ENABLE SHORT PACKET: When set to "I", the receive section will receive packets as short as six bytes. When
reset to "0", the receive section of buffer memory will receive between 60 bytes and two Kbytes.
4
ADDSZE
ADDRESS SIZE: When set, this bit reduces the node 10 address match to five bytes rather than the normal six bytes.
This is used where the node is used to perform some multiplex function on the least significant byte of the destination
address.
5
BUF FUL
BUFFER FULL: This bit provides real-time status of the receive buffer memory. As a packet is being loaded into the
buffer memory from the data link controller, this bit will be set if the empty space remaining becomes equal to or less
than eight bytes. This bit ytjlf automatically clear when the space remaining becomes more than eight bytes due to
a) the packet being rejected and sufficient memory freed by the buffer manager or b) the host reading enough data
from the buffer.
6
BUFEMP
BUFFER EMPTY: Indicates thalthe buffer memory is empty. A "O"indicates,thalthere is at least one good data packet
in the receive seCtion. A "I" indicates that the receive section is empty. This bit gives the host software an indication
to continue reading additional data frames from the receive buffer after successful reading of a packet.
7
TST
TEST: This bit is used for testing purposes. When EtherStar is in the receive mode, this bit set to "1" fixes four bytes
olthe CRC to C7, 04, DO, 7B. This value is shifted into the CRC register and checked without being modified. When
EtherStar is transmitting, the back-
7
July 23, 1990
RD/WR
BIT 7
BIT6
WRITE
ONLY
El'JAO[C
-
BITS
-
BIT 4
-
SYMBOL
El'JAO[C
BIT 3
-
BIT2
-
BIT 1
-
BITO
-
DESCRIPTION
Not used.
ENABLE DATA LINK CONTROLLER: This bit must be cleared by writing a "0" into the location after the other OLC
registers have been programmed. After this bins cleared, EtherStar is ready to traAsmit and receive. At least 15J.1s
must elapse between the end of the hardware reset pulse falling edge and the writing of El'JAO[C. ·1" will relel\se
EtherStar from any activity on the network. Node 10 registers -DLCR8-13 readlwrite only when thi!, bit is "I".
468
Product Specification
Philips Components-Signetics Data Communication Products
EtherStar™ Ethernet controller
Table 4.
NE86950
Data Link Controller Register Descriptions (Continued)
OLCR7 -TOR Register LSBs, Read Only, OLCR15 - TOR Registers MSBs, Read Only
A Time Domain Reflectometer (TDR) function is provided by this 14-bit counter that counts the number of bits successfully transmtted for
each packet. The purpose of this function is to provide a rough measure of the distance of the unit on the network to same media fault, either
a short or an open.
The counter is cleared at the beginning of each transmission and counts bits from that time until the Carrier Detect input (XCD) negates or
acollision is detected. The counter is also cleared after each successful data packet transmission. The LSBs are read from OLCR7, the MSBs
from DLCRI5.
ROIWR
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
BIT1
BITO
OLCR7
READ
ONLY
TOR7
TOR6
TOR5
TOR4
TOR3
TOR2
TORI
TORO
OLCR15
READ
ONLY
TOR13
TOR12
TORll
TDR10
TOR9
TOR8
-
-
OLCR8 :OLCR13 -Node 10 Registers, ReadIWrite
The node ID is comprised of the six bytes contained in DLCR8 through OLCRI3. EtherStar compares this node 10 with the destination field
of all packets on the LAN media to determine if there is a match. If the two addresses match, and the address match mode in OLCR5<1 :0>
allows reception, the packet is received into buffer memory. OLCR8 is the LS byte and OLCR13 is the MS byte of the node 10. The node
ID is reduced to the five MS bytes (DLCR9 to DLCRI3) if DLCR5<4> is set to a 'I '.
These registers are accessible for read/write operation only when the data link controller has been disabled via DLCR6<7> or immediately
after reset.
BIT 1
BIT 0
102
101
IDO"
1011
ID10
109
108
1020
1019
ID18
ID17
ID16
ID29
ID28
1027
1026
1025
1024
ID38
ID37
1036
1035
1034
1033
1032
1046
1045
1044
1043
1042
1041
ID40
RO/WR
BIT7
BIT6
BITS
BIT4
BIT3
DLCR8
READ
WRITE
107
106
ID5
104
103
OLCR9
READ
WRITE
ID15
1014
1013
1012
DLCR10
READ
WRITE
1023
ID22
1021
OLCRll
READ
WRITE
1031
ID30
DLCR12
READ
WRITE
1039
OLCR13
READ
WRITE
1047
BIT2
"Do not program to 'I'.
Table 5.
Buffer Manager Port/Register Descriptions
OMPRO -Buffer Memory Port Register, ReadIWrlte
This register provides the host access to the buffer memory. Writing a bytelword to this port transfers that data to the currently addressed
location in the transmit buffer and increments the transmit buffer pointer to point to the next bytelword. Reading a bytelword from this port
transfers the contents of the currently addressed location in the receive buffer to the host and increments the receive buffer pointer to point
to the next byte/word. See DLCRO, DLCR2<6>, OLCRS and OLCRS<6> for additional information.
This register is byte access only in byte mode and word access only in word mode (the upper and lower bytes cannot be accessed
independently in word mode).
Word Access ---------------------------~
1 ...<--------- Byte Access
READ
WRITE
July 23, 1990
469
-------.
I
Philips Components-Signetics Data Communication Products
. Product Specification
EtherStar™ Ethernet controller
NE86950
Table 5.
Buffer Manager Port/Register Descriptions (Continued)
BMPR3:BMPR2 -Packet length Registers, Write Only
The host writes to these registers to define the length of the packet which was loaded for-transmission into the curren~y addressed transmit
buffer. The LS byte is in the BMPR2, the MS bits are in BMPR3. The transmit start bit, TMST in BMPR3, is set when BMPR3 is written to
inform the buffer manager that the data and packet length have been provided and that it should initiate transmission of that packet via the
data link controller.
In byte access mode, the LS byte must be written lirst, followed by the MS bits and TMST in BMPR3.
RD/WR
BIT7
BIT6
BITS
BIT4
BIT3
BMPR2
WRITE
ONLY
PL7
PL6
PL5
PL4
PL3
BMPR3
WRITE
ONLY
TMST
.-
-
-
-
BIT2
BIT1
BITO
PL2
PLl
PLO
PL10
PL9
PL8
BIT 1
BITO
BMPR4 -DMA Control and Status Register, ReadIWrite
This register enables/disables DMA operation for accessing the buffer memory, and provides DMA status.
RDIWR
BIT7
BIT6
BITS
BIT 4
BIT3
BIT2
EOP
CLR EOP
BMPR2
READ
-
-
-
-
EOPINT
MASK
BMPR3
WRITE
-
-
-
-
EOPINT
MASK
RENA
TENA
,
BIT
SYMBOL
DESCRIPTION
0
TENA
TRANSMIT DMA ENABLE: A' l' enables DMA write operation between the host and the buffer memory. A '0' disables
DMA write operation between the host and the buffer memory. Write only.
1
RENA
RECEIVE DMA ENABLE: A '1' enables DMA read operation between the host and the buffer memory. A '0' disables
DMA read operation between the host and the buller memory. Write only.
2
EOP
END OF PROCESS: Indicates that an entire packet has been transferred between the buller memory and the host.
Set to a '1' when the external DMA controller asserts the EOP input. The host should respond by clearing RENA or
TENA. When this bit is set, the Receive Interrupt output, RINT, will be asserted if this action has been enabled by
setting bit 3 of this register. Writing a '1' to this bit clears the status bit, writing a '0' has no effect .. Readlwrite.
NOTE: This function is not implemented in the NE86950A version of EtherStar.
3
EOP INT
MASK
EOP fNTERRUPT MASK: Writing a '1' to this bit will cause RlNTto be asserted when the EOP status bit, bit 2 of this
register, is also set. Writing a '0' to this register masks RINT from being asserted by that condition. Read/write.
NOTE: This function is not implemented in the NEB6950A version of EtherStar.
<7:4>
July 23, 1990
-
Not used,
470
Product Specification
Philips Components-Signetics Data Communication Products
NE86950
EtherStar™ Ethernet controller
Table 6.
Address Multiplexing on Buffer Address Outputs
~I
Internal
BA7
BAS
BA5
BA4
BA3
BA2
BA1
BAD
RASADDRESS
A13
A12
All
Al0
A9
AS
A7
AS
CAS ADDRESS
A15
A5
A4
A3
A2
AI
AO
A14
SA3-
tePN
tAse.... I---tR~
teAH
)
BA7:O
--tWCS
WE
+- .ASC
~
---
tWCH
.WP
I
tOH
tOS - - - .
*
BD1S-1iDO
(OUTPUTTo DRAM)
.
OE
-
- - _.
--
.OEA-
'CAC.RAe
BD1S-1iDO
DRAM)
"
<
I
~NPUT FROM
Figure 19. DRAM Interface Timing
Figure 20. DRAM Refresh Timing
July 23, 1990
...J0E~
• OES .----......
473
tDBC~
+-
Product Specification
Philips Components-Signetics Data Communication Products
EtherStar™ Ethernet controller
NE86950
TCKN
TEN
---If-'I
TXD
lINT
(IF IT IS NOT MASKED)
Figure 21. Transmit In Ethernet Configuration
Figure 22. Collision Timing
TEN
TXD
J
~l
r--- PREAMBLE--ISTAR~"""
-----
JmM
JAM
-ll1P-·L
-----l
lINT
l~-------------Figure 23. Collision at the Preamble Field
TEN
110
1-- 112 - \ "
-,
JAM
/\
Xl:OC
-------------------------t~_______
I.
lINT
\
\
TXD
---~
tna
Figure 24. Collision at the Data Field
July 23, 1990
474
Product Specification
Philips Components-Signetics Data Communication Products
EtherStar™ Ethernet controller
RCKN
NE86950
_---l..+_'
XCD
mm
-----------------------------------+------~
(IF ITiS NOT MASKED)
Figure 25. Receive in Ethernet Configuration
TCKN
TXDS
RXDS
TCKN
TEN
.
7--
.. I
18
~
'~
NEXT TO LAST BIT
BIT
Figure 26. StarLAN Transmit and Receive Timing
July 23, 1990
475
.
"j
--
LAST BIT
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Philips Components-Signetics
Data Communication Products
Section 5
Package Outlines
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Philips Components-Signetics
Package Outlines
Data Communication Products
28-PIN PLASTIC LEADED CHIP CARRIER
__ -m-H~~~+_-t___l ..tl2ioo~'I'£:"~8~'~'TIA~®W::e-IGlill®
1
PACKAGE DIMENSIONS CONFORM TO JEDEC SPECli=ICA liON
300<7621
MO-O'7-AB FOR PLASTIC LEADED (HIP CARRIER 28 LEADS
050 INCH LEAD SPACING. SQUARE (ISSUE A. 101J1I8'(J
01~~XO~5 1 - ,
~00710181 S
B@O-E s
CONTROLLING DIMENSIONS INCHES METRIC DIMENSIONS IN mm
ARE SHOWN IN PARENTHESES
2
3 PLACES
3
DIMENSIONING AND TOLERAN(ING PER ANSI
~
y"
5M-1982
DATUM PLANEEB]LOCATED AT THE TOP OF MOLD PARTING
LINE ANO COINCIDENT WITH TOP OF LEAD WHERE LEAD EXITS
495,'2571
485Ti232T
I
&.
LOCATION TO DATUMWANO[JEjTO BE DETERMINED AT PLANE
c:BJ
THESE DATUMS 00 NOT INCLUDE MOLD FLASH MOLO FLASH
PROTRUSION SHALL NOT EXCEED 006' lO 15 mm) ON ANY SIDE
&.
.. 007 I 018 I@ AS F-G S
002 IN f IN
DATUM~ANDBARE
DETERMINED WHERE THESE CENTER
LE.ADS EXIT FROM THE BODY AT PLANE8E]
7
PIN NUMBERS CONTINUE COUNTERCLOCKWISE TO PIN 28 nOP
8
SIGNETICS ORDER CODE FOR PRODUCT PACKAGED IN A PLCC IS
THE SUFFIX 'A' AFTER THE PRODUCT NUMBER
A
-B-&
~
APPLICABLE TO PACKAGES WITH PEDESTAL ONLY
~
-c~
II
SEATING
PLANE
1+1015 I 038
I®IF G"®J
853-0401 93885
January 1991
4301 1092
3901991)
&
g~;: ~.;: ~ ~020
PEDESTAL
CLEARANCE
I 05 I MIN]
CLEARANCE WID
PEDESTAL
-+/ S~t::~G
I ~I~=*:
&~ ~~: i;;: i
-
&,
1*1010 I 025 1(9!A®!B®!
J_JI___il.HI:Qi"[SD"j]3'[8Il)®ml[£D-~E:l\1J®1
AQ1
479
Philips Components-Signetics Data Communication Products
Package Outlines
44·PIN PLASTIC LEADED CHIP CARRIER
.. 007(0181@BS O-E
002 IN liN
e
s
695 ( 1765 1 _ _ _+-_---.13[:0220[7I:;(Q[il~':OJ:11'I!A~ItF-:QGcg®21
-A_ " ,
68S(1740)
010(025)
MAX R
3 PLACES
007 I 0.18 1
B
s
O-E
1.
PACKAGE OIMENSIONS CONFORM TO JEOEC SPECIFICATION
MO-047-Al FOR PLASTIC LEADED (HIP CARRIER 44 LEADS. 050
2
CONTROLLING DIMENSIONS. INCHES METRIC DIMENSIONS IN mrn .
::I
DIMENSIONING AND TOLERANCING PER ANSI Y145M-1982
®
INCH LEAO SPACING, SQUARE. (ISSUE A, 10/31184)
ARE SHOWN IN PARENTHESES
656/1666)
~
6
DATUM PLANE~LO(ATEO AT THE TOP OF MOLD PARTING LINE
AND COINc!DENT WITH TOP OF LEAD. WHERE LEAD EXITS
PLASTIC BODY
.&
LOCATION TO OATUMWANOrnTO BE DETERMINED AT PLANE
8.8.
THESE DATUMS DO NOT INCLUDE MOLD FLASH MOLD FLASH
PROTRUSION SHAll NOT EXCEED 006' !O 15 mml ON ANY SIDE .
.t!
DATUM
m:£] AND ~ ARE
DETERMINED WHERE THESE CENTER
LEADS EXIT FROl1 THE BOOY AT PLANEBE
7
PIN NUMBERS CONTINUE COUNTERCLOCKWISE TO PIN 44
nop
VIEWI
~~OO~7~J
~O.,~.tiJ~'pA~'~F-C[GM_+-_ _
~ 0021NiiN A
-B-
&.
",
GB~------------J
SEATING
PLANE
6.
656 I 1666 )
&
r---------~(----~----L
I
1.1007 I 0.16 I@ID-E® F-G®I
44 PLACES
:gi~ ~ ri.~441IR
11+1.015(0.361~
853·0403 93885
January 1991
SIGNETICS ORDER CODE FOR PRODUCT PACKAGED IN A PLCC IS
THE SUFFIX 'A' AFTER THE PROQUCT NUMBER
~
APPLICABLE TO PACKAGES WITH PEDESTAL ONLY
", g;; ~ ~i: : [1i~~R~~dE":I~
ic~~r~~: SEA,,:'EOEST"
_
I
~I
.630 ( 1600 I
590114.991
1",1
1
~ .~~~ : ~.~~ \
!
PLANE
&.
\.\010 ( 0.25 J(Q\A®IB®I
1.10151 0.36 I %>!D-E ®I
AXl
480
Philips Components-Signetics Data Communication Products
Package Outlines
52-PIN PLASTIC LEADED CHIP CARRIER
.. . , (6.11) @;
a$ D-E$
NOTES:
1. Package dimensions conform to JEDEC specification
MO·047·AD for plastk: leaded chip carrier 52 leads,
.050 inch lead spacing, square. (issue A. 10/31/84) .
2. Controlling dimensions: inches. Metric dimensions in
mm are shown in parentheses.
3. Dimensioning and tolerancing per ANSI Y14.5M·1982.
4. Dalum plane "H" located at the top of mold parting
line and coincident with top 01 lead, where lead exits
plastiC body.
5. Location to datum "A" and "8" to be determined al
plane "H". ThJSe oalums do not include mold flash.
Mold flash protrusion shall not exceed .006~ (0.15
mm) on any side.
6. Datum "o-E" and "F·G" are determined where these
center leads exit from the body at plane "H".
7. Pin numbers continue counterclockwise to pin #52
(top view).
8. Signetics order code 101' product packaged in a PLCC
is the suffix "A" after the product number.
9. Applicable to packages with pedestal only.
..... -~o
ir-;;;r,...,
\J~---r
---'
-
. . _.M)
:Q!..!iM~8EATINII
~
IILANE
U PLACE.
::~:\
..
AA1
853-0397 93885
January 1991
481
Philips Components-Signetics Data Communication Products
Package Outlines
84·PIN SQUARE PLASTIC LEADED CHIP CARRIER
... , ..
f:!J&
.....
•
.....
-''''",
.......
NOTES,
N
1. Package dimensions conform to JEDEC specihcalion
MQ·047·AF fa( plastic leaded chIP camer 84 leads.
.050 Inch lead spacmg. square. (issue A. 10/31/84).
2. Controlling dimenSions: inches. Mabie dimensions in
mm are shown in parentheses.
3. Dimensioning and Ioktranclng per ANSI Y14.5M·1982.
4. Datum plane "H" located at the top of mold parting
line and cotncident with top of lead, where lead exits
plastiC body
5 location to datum "A" and "B" to be determined al
plane "H". These Datums do not include mold flash.
Mold flash protruSIOn shall not exceed .006" (0.15
mm) on any SIde.
6. Datum "D-E" and "F-G" are determined where these
center leads eX11 from the body at plane "H",
7. Pin numbef's continue counterclockwise to pin #84
(top view).
8. Signelics ordef code for product packaged in a PLCC
IS the suffix "A" after Ihe product number.
9. Applicable 10 packages with pedestal only.
'
I
1._"""1
1·.'
.... 1
I
I
o
I
I
I~
,
~3-0399
93885
January 1991
AC1
482
Philips Components-Signetics Data Communication Products
Package Outlines
24·PIN PLASTIC SOL
NOTES:
I
10.62 (.418)
7.60 (.299)
10.21 (.402)
7.40 (.291)
ftIE®I·25 1.010) ® I
1
ED
1. Package dimensions conform to JEDEC specification
MS-OI3-AO for standard small outline (SO) package. 24
leads, 7.50mm (.300") body width (issue A, June 1985),
2. Controlling dimensions are in mm. Inch dimensions in
parentheses.
:t Dimensions and lolerancing per ANSI YI4.SM- 1982.
4. "T". "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .ISmm (.006") on
any side,
5. Pin numbers stan with pin # 1 and continue
counterclockwise to pin #24 when viewed from top.
6. Signetics ordering code for a product packaged in a
plastic small outline (SO) package Is the suffix Dafter
the product number.
-~ !:n=;::;==;=;=:;:::;:::::;::;===;::;::::;::;:::;::;::~
-o-·~----+-----------
lr
15.60 (.614)
·75 (.030) X4S'
.50 (.020)
15.20 (.59B)
~
I
2.65 (.104)
§
.10(.004)1
I
-----J
L
2.35 (.093)
I
.34 59 (.019)
.
(.014)
-1.1 TIE 10 ®I .25 (.010)@1
.301·0'2)
.10 (.004)
.834 (.003)
.559 (.022)
ON2
853·0173 82949
January 1991
.32 (.013)
.23 1.009)
483
Philips Components-Signetics Data Communication Products
Package Outlines
24·PIN PLASTIC SOL (EIAJ TYPE II OUTLINE)
l CONTROLLING DIMENSIONS ARE IN MILLIMETERS Imm)
DIMENSIONS IN PARENTHESES ARE IN INCHES
2. PIN NUMBERS START WITH PIN ttl AND CONTINUE
COUNTERCLOCKWISE TO PIN '24 WHEN VIEWED
FROM TOP.
~
I 307 t.OI2)
0.2iOI
-.LI~I
• THIS IS NOT A JEDEC OUTLINE
FOR JEDEC SO 24 OUTLINE
DRAWINGS53-0173
see
EIAJ Type II Outline
DNB
853-1460 000238
January 1991
484
Philips Components-Signetics Data Communication Products
Package Outlines
28-PIN CERAMIC DIP (600 MILS WIDE)
I
f---
I
098 (2.49)
.040 (1.02)
[ S E E NOTE
~
I
r
098 (2.49)
.D40 (102)
AAAAAA{AAl
NOTES:
1 Controlling dimension: inches. MIllimeters are shown in
parentheses.
2. Dimensions and teleranclng per ANSI Y14.SM - 1982.
3. "T", "0", and HE" are reference datums on the body
and include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.
4 These dimenSions measured with the leads constrained
to be perpendicular to plane T.
5. Pin numbers start with pin # 1 and conllnue
counterclockwise to pin #28 when viewed from the top.
6. Denotes window Jocation for EPROM products (see FA
package).
.620 (15.75)J
590 (14.99)
(NOTE 4)
,
'
~
t-
600 ('5.24)
esc
(NOTE 4)
.695 (17.65)
,600 (1524)
FQ3
853-05B9 84000
January 1991
485
Philips Components-8ignetics Data Communication Products
Package Outlines
40·PIN CERAMIC DIP (600 MILS WIDE)
SEE
r
NOTE
S
lr~m~~
!!~~'2AS'
.o40TT:lr'2'l
,
~~~~~~~~~
m~
f
~~
~'iL' .100'2,4,.se
ERJ
mmml
l~~o:l.m
~
c..!..:r"--_
EATING
PLANE
JL
m-d.""
MILLIMETERS ARE SHOWN IN PARENTHESIS
2. DIMENSION MDTOlERANCtNGPER ANSIYU.5M,'9S2.
3.
4.
"","0". AND "E" ARE Ref't:FlANCE DATUMS ON THE
BOOY AND INCLUDE ALLOWANCE FOR GLASS OVERRUN
AND MENISCUS ON me SEAL LINE. AND LID TO BAse
MISMATCH.
'rn'ESE DIMENSIONS MEASURED W1TH THE LfADS
CONSTRAtNED TO BE peRPENDICULAR TO PLANE T
5.
PINNUMBERSSTARTwtTHPIN"ANOCONTINU'E
COUNTERCLOCKWISE TO PIN,.O WHEN VIEWED FROM
THE TOP.
S.
DENOTES WINDOW LOCATM)H FOR EPROM PROOUCTS.
~AX.
BfHUl-RlllilE 10®1.0IOI.2.4' @I
::J~Hl
853-0590 95528
January 1991
NOTES:
t. CONTROlLING DIMENSION: INCHES.
Ii,
C.24'J
lSOO.'SI
(NOTE 4J
Utl-m-~~
FW3
486
Philips Components-Signetics Data Communication Products
Package Outlines
24-PIN PLASTIC DIP (300 MILS WIDE)
caNTRoLl I NG
2.
3.
4.
0 I MENS ION: INCHES
METRIC ARE SHOWN IN PARENTHESES.
PACKAGE DIMENSIONS CONFORM TO
JEDEC SPECIFICATION MS-OQI-AF
FOR STANDARO [JUAL
IN~LINE(OIP)
PACKAGE .300 I NCH ROW SPAC I NG
(PLASTIC) 2.4 LEAOS(ISSUE 8.7/8S)
DIMENSION AND TOLERANCING PER
ANSI
YI4.SM-19B2.
"T","Q",AND
"E"
ARE
REFERENCE
GATEMS ON THE MOLDED BODY AND
NOT I NCLUO[ MOLD FLASH OR
PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED.OIO
INCHl2SMM10N ANY SIDE.
THESE DIMENSIONS MEASURED WITH
THE LEADS CONSTRAINED TO BE
PERPENDICULAR TO PLANE T.
PIN NUMBERS START WITH PIN.!
AND CONTINUE COUNTERCLOCKWISE
TO PIN#24 WHEN VIEWED FROM
DO
S.
6.
THE
TOP.
~.~J
.31IT1 CTG 2)
[tJOTE
.:~
853·04109B727
January 1991
S)
:--:
NN1
487
Philips Components-Signetics Data Communication Products
Package Outlines
24-PIN PLASTIC DIP (400 MILS WIDE)
Iflo@!.OO4
(.'0)
I
NOTES:
1. Controlling dimension: inches. Metric are shown in
parentheses.
I
LL.,oo
.370 (9.40)
2. Dimensions and tolerancing per ANSI Y14. 5M·1982.
3. "T", "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .010 inch (.25mm)
on any side.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin #24 when viewed from the top.
(2.54) BSC
1.205 (30.61)
1.190 (30.23)
.042 (1.07)
.064 (1.63)
.034 ( .86)
.045 (1.14)
.190 (4.83)
.422 (10.72)
.145 (a.S6)
.035
.138 (3.51)
:~~ ::::~
.120 (3.05)
-f+iTleID®l.61o
(.25)
@l
853·0411 81237
January 1991
.400 (10.16)
(NOTE 4)
.155 (3.94)
('8~9)
if
.020 (.51)
~_
BSC
.400 (10.16)
j\\
---I
(NOTE 4)
.015 (.38)
.010 (.25)
.495 (12.57)
.400 (10.16)
NN2
488
Philips Components-Signetics Data Communication Products
Package Outlines
28-PIN PLASTIC DIP (600 MILS WIDE)
NOTES:
1 Controlling dimension: Inches. MetriC are shown In
parentheses.
2. Package dimenSions conform to JEDEC specification
MS-011-AB for standard dual in-line (DIP) package .600
inch fOW spacing (PLASTIC) 28 leads (issue 8. 7 J85)
3. DimenSions and tolerancing per ANSI Y14. 5M-1982.
4. "T", "0" and "E" are reference datums on the molded
body and do not Include mold flash r;or protrusions. Mold
flash or protrusions shall not exceed .010 inch (.25mm)
on any side.
5. These dimenSions measured with the leads constramed
to be perpendicular to plane T.
6. Pin numbers start with pin #. 1 and continue
counterclockwise to pin # 28 when viewed from the top.
.155 (3.94)
.145{3.68\
rt4--------------------------'----.
.200 (5.081
ED--
PLANE
~
120 (3.05)
:~~ ;::~
015(.311)
t+\TlEI[)(S)I.010 (,25) @I
600 (1524)
853·0413 84099
January 1991
NQ3
489
Philips Components-Signetics Data Communication Products
Package Outlines
40·PIN PLASTIC DIP (600 MILS WIDE)
.555 (14.10)
.545 (13.84)
~I~T"T'T'T'T'T'T"I
~
NOTES:
1. ControUing dimension: inches. Metric are shown in
parentheses.
2. Package dimensions conform to JEOEC specification
M&-ol1-AC for standard dual in-line (DIP) package .600
inch row spacing (PlASTIC) 40 leads (issue B. 7185)
3. Dimensions and tolerancing per ANSI Y14. SMM1982.
4. "T". "0" and "E" are reference datums on the molded
body and do not Include mold flash or protrusions. MoJd
flash or protrusions shaH not exceed .010 inch (.25mm)
on any side.
5. These dimensions measured with the teeds constrained
to be perpendicular to plane T.
6. Pin numbers start with pin # 1 and continue
counterctockwiSe to pin #40 when viewed from the top.
U-.'00 (2.54) esc
i=lf'l--+----------~: :~:::----------I
.620 (16.76)
.200 (5.08)
.155 (3.94)
~
.145 (3.68)
.045 (1.14)
.138 (3.51)
:: !::-ftIrlElO@1
.120 (3.05)
.010 (.25)
II
(NOTE 5)
.015 (.38)
t~
h
(.6~)
.010(.25)
853-041584971
January 1991
.020
.600 (15.24)
.600 (15.24)
esc:=:J
. (NOTE 5)
.695 (17.65)
~
NW3
490
Philips Componehts-Signetics Data Communication Products
Package Outlines
48-PIN PLASTIC DIP
lei ......) lGool
NOTES:
1. Controlling dimensions: Inches. Metric afe shown in
parentheses.
2. Oimensions and torMencing per ANSI Y145M.1982.
3. "T", "0", and "E" are reference OaIUfnS on the
I
~
~~;n;;rvt;;n;;nJ~~IJ~)
molded bedy and do not include mold flash or
protrusions. Mold flash or prolrUsions Shall not
exceed .010 inch (25mm) on any side.
4. These dimensiona measured with the leads
constrained to be perpendtcular to plane 'T'.
5. Pin numbers start with # 1 and continue counte,clockwise to pin -48 when viewed "om the top.
~
E!3--+---------------------:::::
=
-ill .nc.) II TIl! ID
Cli
1IS34<18_
January 1991
NY3
491
Philips Components-Signetics Data Communication Products
Package Outlines
64-PIN PLASTIC DIP
NOTES:
l
1. Controlling dimensions: Inches. Metric are shown in
parentheses.
2. Dimensioning and toIerancing per ANSI Y14.SM-1982.
3. liT", "0", and "E" are reference Qatu~ on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shan not exceed .010 inch (25mm)
on any side.
4. These dimensions measured with the leads constrained
to be perpendicular to !)Jane 'T'.
5. Pin numbers start with # 1 and continue counterclockwise to pin #64 when viewed from the top.
NS4
853·041493945
January 1991
492
Philips Components-Signetics
Data Communication Products
Section 6
Sales Offices,
Representatives &
Distributors
Philips Components-Signetics
Sales Offices,
Representatives &
Distributors
Data Communication Products
SIGNETICS
HEADQUARTERS
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, CA 94088-3409
Phone: (408) 991-2000
TENNESSEE
Greeneville
Phone: (615) 639-0251
ALABAMA
Huntsville
Phone: (205) 830-4082
Richardson
Phone: (214) 644-1610
CALIFORNIA
Calabasas
Phone: (818) 880-6304
Irvine
Phone: ~14) 833-8980
TEXAS
Austin
Phone: (512) 339-9945
CANADA
SIGNETICS CANADA, LTD.
Etobicoke, Ontario
Phone: (416) 626-6676
Sunnyvale
Phone: (408) 991-3737
COLORADO
En~lewood
hone: (303) 792-9011
GEORGIA
Atlanta
Phone: (404) 594-1392
ILLINOIS
Itasca
Phone: (708) 250-0050
INDIANA
Kokomo
Phone: (317) 459-5355
MASSACHUSETTS
Westford
Phone: (508) 692-6211
MICHIGAN
Farmington Hills
Phone: (313) 553-6070
NEW JERSEY
Parsippany
Phone: (201) 334-4405
Toms River
Phone: (201) 505-1200
NEW YORK
Wappingers Falls
Phone: (914) 297-4074
OHIO
Columbus
Phone: (614) 888-7143
OREGON
Beaverton
Phone: (503) 627-0110
PENNSYLVANIA
Plymouth Meeting
Phone: (215) 825-4404
JanuarY 1991
PENNSYLVANIA
Hatboro
Delta Technical Sales, Inc.
Phone: (215) 957-0600
MASSACHUSETTS
Chelmsford
JEBCO
- Phone: (508) 256-5800
TEXAS
Austin
Synergistic Sales, Inc.
Phone: (512) 346-2122
MICHIGAN
Brighton
AP Associates, Inc.
Phone: (313) 229-6550
Houston
Synergistic Sales, Inc.
Phone: (713) 937-1990
MINNESOTA
Eden Prairie
High Technology Sales
Phone: (612) 944-7274
Ne~ean,
Ontario
hone: (613) 225-5467
( 14) 752-2780
San Diego
Phone: (619) 560-0242
MARYLAND
Columbia
Third Wave Solutions, Inc.
Phone: (301) 290-5990
REPRESENTATIVES
MISSOURI
Bridgeton
Centech, Inc.
Phone: (314) 291-4230
ALABAMA
Huntsville
Elcom, Inc.
Phone: (205) 830-4001
Raytown
Centech, Inc.
Phone: (816) 358-8100
ARIZONA
Scottsdale
Thorn Luke Sales, Inc.
Phone: (602) 941-1901
NEW MEXICO
Albuquerque
F.P. Sales
Phone: (505) 345-5553
CALIFORNIA
Folsom
Webster Associates
Phone: (916) 989-0843
NEW YORK
Ithaca
Bob Dean, Inc.
Phone: (607) 257-1111
COLORADO
En~wood
. om Luke Sales, Inc.
Phone: (303) 649-9717
Rockville Centre
S-J Associates
Phone: (516) 536-4242
CONNECTICUT
Wallingford
JEBCO
Phone: (203) 265-1318
Richardson
Synergistic Sales, Inc.
Phone: (214) 644-3500
UTAH
Salt Lake City
Electrodyne
Phone: (801 ) 264-8050
WASHINGTON
Bellevue
Western Technical Sales
Phone: (206) 641-3900
Spokane
Western Technical Sales
Phone: (509) 922-7600
WISCONSIN
Waukesha
Micro-Tex, Inc.
Phone: (414) 542-5352
CANADA
Alberta
ech-Trek, Ltd.
Phone: (403) 241-1719
Ca~ary,
Mississauga, Ontario
Tech-Trek, Ltd.
Phone: (416) 238-0366
Wa~Pin8ers Falls
Ne~ean,
FLORIDA
Oviedo
Conley and Assoc., Inc.
Phone: (407) 365-3283
NORTH CAROLINA
Smithfield
ADI
Phone: (919) 934-8136
Richmond, B.C.
Tech-Trek, Ltd.
Phone: (604) 276-8735
GEORGIA
Norcross
Elcom, Inc.
Phone: (404) 447-8200
OHIO
Aurora
InterActive Technical Sales,
Inc.
Phone: (216) 562-2050
ILLINOIS
Hoffman Estates
Micro-Tex, Inc.
Phone: (708) 382-3001
Columbus
InterActive Technical Sales,
Inc.
Phone: (614) 888-1256
INDIANA
Indianapolis
Mohrfield Marketing, Inc.
Phone: (317) 546-6969
Dayton
InterActive Technical Sales,
Inc.
Phone: (513) 436-2230
IOWA
Cedar Rapids
J.R. Sales
Phone: (319) 393-2232
OREGON
Beaverton
Western Technical Sales
Phone: (503) 644-8860
ob ean, Inc.
Phone: (914) 297-6406
495
Ontario
ech-Trek, Ltd.
Phone: (613) 225-5161
Ville St. Laurent, Quebec
Tech-Trek, Ltd.
Phone: (514) 337-7540
PUERTO RICO
Santurce
Mectron Group
Phone: (809) 728-3280
DISTRIBUTORS
Contact one of our
local distributors:
Anthem Electronics
Falcon Electronics, Inc.
Gerber Electronics
Hamiiton/Avnet Electronics
Marshall Industries
Lex Electronics
Wyle/LEMG
Zentronics, Ltd.
11/9190
DA T A HANDBOOK SYSTEM
Jl
--------------------
------------------------------------------------------DA T A HANDBOOK SYSTEM
Our Data Handbook System comprises more than 60 books with specifications on electronic
-components, subassemblies and materials: It is made up of six series of handbooks:
INTEGRATED CIRCUITS
DISCRETE SEMICONDUCTORS
DISPLAY COMPONENTS
PASSIVE COMPONENTS*
PROFESSIONAL COMPONENTS**
MATERIALS*
The contents of each series are listed on pages iii to viii.
The data handbooks contain all pertinent data available at the time of publication, and each is revised
and reissued periodically.
When ratings or specifications differ from those published in the preceding edition they are indicated
with arrows in the page margin. Where application is given it is advisory and does not form part of the
product specification.
Condensed data on the preferred products of Philips Components is given in our Preferred Type Range
catalogue (issued annually).
Information on current Data Handbooks and how to obtain a subscription for future issues is
available from any of the Organizations listed on the back cover.
Product specialists are at your service and enquiries will be answered promptly.
* Will replace the Components and materials (green) series of handbooks.
** Will replace the Electron tubes (blue) series of handbooks.
ii
November
19881 (
_ _ _Jl__
INTEGRATED CIRCUITS
This series of handbooks comprises:
code
handbook title
ICOl
Radio. audio and associated systems
Bipolar, MOS
Video and associated systems
Bipolar, MOS
ICs for Telecom
Bipolar, MOS
Subscriber sets. Cordless Telephones
HE4000B logic family
CMOS
Advanced low-power Schottky (AlSI logic Series
High-speed CMOS; PC74HC/HCT/HCU
Logic family
IC02a/b
IC03
IC04
ICOS
IC06
IC07
Icoa
IC09N
IC10
Advanced CMOS logic (AClI
ECl 10K and lOOK logic families
TTL logic series
ICll
IC12
IC13
Linear Products
12 C-bus compatible ICs
IC14
IC1S
Supplement
to IC1S
IC16
IC17
ICla
IC19
Memories
MOS, TTL, ECl
Semi-custom
Programmable logic Devices (PlDI
Microcontrollers
NMOS, CMOS
FAST TTL logic series
FAST TTL logic series
CMOS integrated circuits for clocks and watches
ICs for Telecom
Bipolar. MOS
Radio pagers
Mobile telephones
ISDN
Microprocessors and peripherals
Data communication products
1
(June 1989
iii
__Jl_ __
DISCRETE SEMICONDUCTORS
This series of data handbooks comprises:
current new
handbook title
code
code
Sl
SCOl
S2a
SC02*
Power diodes
S2b
SC03*
Thyristors and triacs
Small-signal transistors
Diodes
High-voltage tripler units
53
SC04
54a
SC05
Low-frequency power transistors and hybrid IC power modules
54b
SC06
High-voltage and switching power transistors
S5
SC07
Small-signal field-effect transistors
S6
SCOS
SC09
R F power transistors
RF power modules
S7
SC10
SCll·
Surface mounted semiconductors
Light emitting diodes
SC12
SC13*
Optocouplers
$11
SC14
SC15
Wideband transistors and wideband hybrid IC modules
Microwave transistors
S15**
SC16
Laser diodes
S13
SC17
SC1S*
Semiconductor sensors
S8a
S8b
S9
S,10
S14
PowerMOS transistors
Liquid crystal displays and driver ICs for LCDs
• Not yet issued with the new code in this series of handbooks.'
•• New handbook in this series; wi" be issued shortly.
iv
June 19891 (
_ _ _Jl__
DISPLAY COMPONENTS
This series of data handbooks comprises:
current
code
new
code
T8
DC01
Colour display components
T16
DC02
Monochrome monitor tubes and deflection units
C2
DC03
Television tuners, coaxial aerial input assemblies
C3
DC04*
Loudspeakers
C20
DC05
Flyback transformers, mains transformers and
general-purpose FXC assemblies
handbook title
* These handbooks are currently issued in another series; they are not yet
issued in the Display Components series of handbooks.
1(
October 1989
v
Jl
--------------------'
'-----------------------------------------------------PASSIVE COMPONENTS
This series of data handbooks comprises:
current
code
new
code
handbook title
C14
PAOl
Electrolytic capacitors; solid and non-solid
Cll
PA02
Varistors, thermistors and sensors
C12
C7
PA03
PA04
Variable capacitors
C22
PA05*
Film capacitors
C15
PA06*
Ceramic capacitors
C9
PA07*
C13
PAOB
Piezoelectric quartz devices
Fixed resistors
Potentiometers and switches
* Not yet issued with the new code in this series of handbooks.
vi
October 19891 (
_ _ _Jl_
PROFESSIONAL COMPONENTS
This series of data handbooks comprises:
current new
handbook title
code
code
T4
.
.
.
PC01*"
.
T5
PC02*"
Cathode-ray tubes
Geiger-Mii lIer tubes
T1
T2a
T2b
T3
Power tubes for RF heating and communications
Transmitting tubes for communications, glass types
Transmitting tubes for communications, ceramic types
High-power klystrons
Magnetrons for microwave heating
T6
PC03*"
T9
PC04*"
Photo and electron multipliers
T10
PC05
Plumbicon camera tubes and accessories
T11
PC06
Circulators and Isolators
T12
T13
PC07
Vidicon and Newvicon camera tubes and deflection units
PCOS
Image intensifiers
T15
PC09**
Dry reed switches
CS
PC10
PC11
Variable mains transformers; annular fixed transformers
Solid state image sensors and peripheral integrated circuits
.. These handbooks will not be reissued .
.... Not yet issued with the new code in this series of handbooks.
1
(May 1989
vii
__Jl____
MATERIALS
This series of data handbooks comprises:
current
code
new
code
handbook title
~}
MA01*
Soft Fe"ites
C16
MA02** Permanent magnet materials
C19
MA03** Piezoelectric ceramics
• Handbooks C4 and C5 will be reissued as one handbook having the new code
MA01 .
• * Not yet issued with the new code in this series of handbooks.
viii
November
19881 (
Philips Components - a worldwide Company
ArgeMlna: PHILIPS ARGENTINA SA. DIY Philips Components. VedIC! 3892,
1430 BUENOS AJlES, T~ (01 ) (;41-4261 .
Australia: PHILIPS COMPOt.ENT~ "TV ltd, 11 Waltham Str9&t,
ARTARMON, N.S.W 2064, TEl. (02)4393322.
Austria: OSTERREICHISCHE PHILIPS INOUSTRIE G.m b,H ,
UB Bauelemente, Tnestef Sir. 54, 1101 WIEN Tel. (02221 60 101 -820
Belgium: N.V. PHILIPS PROF SYST("'~S - Components Dill"
80 Rue Des Deux Gares, 8-1070 BRUXElLES, Tel. (02) 5256111
Brazil: PHlPS COMPONENTS (Actrve DeVICeS)
Av. das Nac:oes UnIClas, 12495-SAO PAUlO·SP, CEP 04578, PO Box 7383,
T~. (011) 534·2211
PHILIPS COMPONENTS (PassIVe Dew::es & Malena~5)
All Franosco Monteiro, 702 - QIBEIRAO PIRES·SP, CEP 09400,
T~.(011)45g.8211
Canada: PHILIPS ELECTRONICS LTD., Philips Components,
601 Milner Ave., SCARBOROUCH, Onraoo. MIS 1M8
T~. (416) 292·5161 .
(IC Products) SIGNETIC$ CANADA LTD., 1 Eva Road, Sol18 433,
ETOBICOKE. Ontano, M9C 4ZS, Tel. (416) 626-6676.
Chile: PHILIPS CHLENAS.A., Av Sanra Mana 0760, SANTIAGO,
T~. (02) m816.
Colombia: IPRELENSO LTDA., Carrera 21 No 56-17, BOGOTA, 0 E .
PO. Box 77621. Tel. (01) 2497624.
Denmark: PHILIPS COMPONENTS AIS. Prags Boulevard eo. PB1919. DK·2300
COPENHAGEN S, Tel, 01·541133.
Finland: PHILPS COMPONENTS. SlOlkalhonlie 3. SF·2630 ESPOO
Tel. 358.0-50261 .
France: PHILIPS COMPOSANTS, 117 DUal du PreSident Roosevel~
92134ISSY·LEs..MOUlINEAUXCeOex, Tel (01) 40938:00
Germany(Fed. Republic): PHILIPS COMPONENTS UBder PhlhpsG m b.H .
Burchardsn'aSse 19. 0·2 HAMBURG I, Tel. (040) 3296-0
Greece: PHLIPS HEUENIOUE SA, Components DMSIOI1,
No 15. 25th Mardl Street. GR 1m8 TAVROS, Tel (01) 4894339148949It
Hong Kong: PHILIPS HONG KONG l.: Components DIy.
l5IF Philips Ind. Bldg.• 24·28 Kung Yip St. KWAI CHUNG, Tel (0)·4245121
India: PEK:.O ELECTRONICS & ELECTqlCAlS LTD., Components Dept .
Band Box BUilding, 254·0 Dr Annie Besant Rd ,BOMBAY - 400025,
Tel (022)493031114~90.
Indonesi.: P.l PHIlIPs..RAUN ELECTRON ICS. Components DIY..
Sehabulll1 Buildmg, 6th Fl., Jalan H R. Rasuna Srud (P.O Box 2231KBY)
Kuningan, JAKARTA 12910. Tel. (021) 517'995
Ireland: PHLPS ELECTRONK:.S (IREL WD) LTD • Components DIVISIOn,
Newslead , Cionskeagh, DUBlJN 14, Tel. (OI) 693355
Ilaly: PHILPS S.p.A., Philips Components, Piazza IV Novembre 3,
1·20124 MIlANO, Tel. (02) 6752.1
Japan: PHLIPS JAPAN LTD., Components DIVISIOn. Philips Bldg 13·37.
Kohr"an 2·chome. Mmato·ku. TOKYO (lOS), Tel (03) 7405028
Korea (R.pu~ic 01): PHILIPS ELECTRONICS (KOREA) LID" Compooen.
OMS/on. Ph~lps House, 260-19912 'Woo--dong. Yongsan·ku. SEOUL,
T~. (02) 194·5011
Malaysia: PHILIPS MAlAYSIA SON BHD. Components DIY .
3 Jalan SSI512ASUBANG. 47500 PETAUNG JAYA. Tel (03) ]3.l.5511
Mnk::o: PHILPS COMPONENTS, Paseo Tnunlo dJ Ia RepublICa., No 215
LocalS, Cd ..k.larez CHIHUAt-IJA 32340 MEXICO, Tel jI6j18·67·01 m
Netherlands: PHILIPS NEDERlAND B.V., Marklgroep Ptulips Components.
Poslbus 9OClSO. 5600 PB EINDHOVEN. Tel (040) 78374g
New Zealand: PHILIPS NEW ZEALAND LTD., Components DIYISlon, •
110 Mt Eden Road, C.P.O. Box 1041. AUCKLAND. Tel (09)6Q5.914
Norway: NORSK AIS PHILIPS. Ph~IP' ComponenlS. Box 1. Manglerud 0612.
OSLO, T~. (02) 680200.
Paklsl.n: PHLIPS ELECTRICAl CO OF PAKISTAN LTD.. Philip' MaI1w.
M.A. Jlnnah Rd .• KARACHI·3. Tel (021 ) 725772
Peru: CAOESA. Carretera Centra! 6500, LIMA 3, Apartado 5612,
Tel. 51 ·1 4·350059.
Philippines: PHILIPS ELECTRICAL LAMPS INC .. Components Diy., 106 Valero
St Salcado Village, MAKATI. P.O. Box 911. METRO MANIlA.
Tel. (63·2) 810-0161
Portugll : PHILPS PORTUGUESA S A.R L . Ay. Eng Duane Pacheco 6.
l009l1SBOA Codex, Tel. (019) 683121
Singapore: PHILPS SINGAPORE. PTE LTD . Components DIY .lorong 1.
Toa Payoh. SINGAPORE 1231 . Tel. 3502000
South Alriea: SA PHLIPS PTY LTD • Components DIYISIon,
JOHANNESBURG 2000. PO. 8ox7430.
Spain: PHILIPS COMPONENTS, Balmes 22, 08007 BARCELONA.
Tel. (03) 3016312.
Sweden: PHIlPS COMPONENTS. A B . Tegeluddsyagen 1.
S·l1584 STOCKHOlM. Tel (0)8·7821000
Swilzer1and: PHI.IPS A.G. ComponenlS Dept. A1lmendstrasse 140·142,
CH·S027 ZURICH. Tel. (01) 488221 1
Taiwan: PHILPS TAIWAN LTD , 581 Mln Sheflg East Road. PO 80x 22978
TAIPEI 10446, T8JWan. Tel 886-2-509·7666
Thailand: PHl.iPS ELECTRK:.Al CO OF THAILAND LTD .• 283 SIIom Road.
PO. Box 961 , BANGKOK. Tel (02) 233·63:J)·9
Tul1tey: TURK PHILIPS nCARET A.S., PhihP6 Components.
Talatpasa Cad. No 5.80640 LEVENT/LSTANBUl, Tel. (01) 1792770
United Kingdom: PHILIPS COMPONENTS LTD .. Mullard House.
TOrTIngton Place. LONDON WC1E 7HD, Tel. (01) 5806633.
United States: (ColOI' PICture Tubes· Monochrome & Colour Display TU~ I
PHLIPS DISPLAY COMPONENTS COMPANY, 1600 Huron Parkway.
PO Box 963. ANN ARBOR. MlChlgSn 48106. Tel. (313) 996-9400
(e Products) SIGNETICS COMPANY. 811 East Atques Avenue.
SUNNYVAlE. CA 94088·3409. Tel (4OS) 991·2000
(PasSive Components, Dlsaele SemlCOnducDtS. Mateoals and ProfesSIonal
Components) PHILIPS COMPONENTS. Orscrele Products DMSlOn.
2001 West Blue Heron Blvd, PO Box 10330. RIVIERA BEACH. •
Ronda 33404, Tel. (407) 881 ·3200
Uruguay; PHILIPS COMPONENTS, Coronel Mora 433. MONTEVIDEO.
Tel. (02) 7Q.4044
V.nezuela: MAGNETK:.A SA. Calle 6. Ed. las Tres ..Iotas. CARACAS 1074A,
App Pos\. 78117. Tel(02)2417509
Zimbabwe : PHiLIPS elECTRICAL (PVT) LTD . 62 Mutare Road. HARARE.
PO Box 994, Tel. 47211
For all other countries apply to: PhihP6 Compol'I8nlS OMSIOll, Straleg~
Accounts and International Sales. P.O Box 218. 5600 MO EINDHOVEN. The
NOIhertands. Telex 35000 phlCnl. Fax 23753
ASeo 08110190 f>PhillpsExportBV 1990
Ali nghls are reserved Reproducuon 1(1 whole or In part IS proMlited wI!houtlh9
pnor wnnen consent of !he copr,'l'Ighl owner
The Information presented 11'1 thIS document does nollorm part or a1Y qUOlatlon 0'
contrac~ IS belIeVed to be acctJrate and reliable and may be changed Without
nollce No IIaDltty Will be accepted by the publISher lor any consequence 01 Its use.
PublicatIOn thereol does not convey nor Imply any license under patent- Of
Industnal OI'm!ellec!uaJ property nghls
Copynght1990 NAPe Pnnted In USA
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