1991_TI_MOS_Memory_Data_Book 1991 TI MOS Memory Data Book
User Manual: 1991_TI_MOS_Memory_Data_Book
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TEXAS
INSTRUMENTS
MOSMemory
Commercial and Military Specifications
1991
MOSMemory
DafaBook
Commercial and Military
Specifications
'TEXAS
INSTRUMENTS
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to or to discontinue any
semiconductor product or service identified in this publication without notice. TI
advises its customers to obtain the latest version of the relevant information to
verify, before placing orders, that the information being relied upon is current.
TI warrants performance of its semiconductor products to current specifications
in accordance with TI's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty.
Unless mandated by government requirements, specific testing of all parameters
of each device is not necessarily performed.
TI assumes no liability for TI applications assistance, customer product design,
software performance, or infringement of patents or services described herein.
Nor does TI warrant or represent that license, either express or implied, is granted
under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Texas Instruments products are not intended for use in life-support appliances,
devices, or systems. Use of a TI product in such applications without the written
consent of the appropriate TI officer is prohibited.
Copyright © 1991, Texas Instruments Incorporated
INTRODUCTION
The 1991 MOS Memory Data Book from Texas Instruments includes complete detailed
specifications on the expanding MOS Memory product line including Dynamic Random-Access
Memories (DRAMs), Single-In-Line Package DRAM Memory Modules (SIPs), Erasable
Programmable Read-Only Memories (EPROMs), One-Time Programmable Read-Only
Memories (OTP PROMs), Electrically Erasable Programmable Read-Only Memories (Flash
EEPROMs), and Application Specific Memories (ASMs). Also included are military specifications
for DRAMs, EPROMs, and ASMs, as well as specifications for the Datapath VLSI Memory
Management products.
The data book is divided into 14 chapters. Below you will find a brief description of each chapter.
Chapter 1. General Information - Includes an alphanumeric index for quickly finding device
numbers, a part number guide with ordering information, and an Ie Line-up chart for a quick
overview.
Chapter 2. Selection Guide - An easy-to-use reference guide that includes specific device
information. Page numbers are also shown for easy access to the detailed specifications.
Chapter 3. Alternate Source Directory - Lists alternate vendor part numbering examples in
addition to alternate sources for TI devices (based on published data).
Chapter 4. GlossaryfTiming Conventions/Data Sheet Structure - Defines terms and standards
used throughout the data book.
Chapters 5 - 10. Product specifications for over 100 devices can be found in these sections.
Chapter 11. Logic Symbols -Includes an explanation and examples of the IEEE standard.
Chapter 12. Quality and Reliability - Details selected processes and the philosophies of Texas
Instruments that are used to ensure high quality standards.
Chapter 13. Electrostatic Discharge Guidelines - Because all MOS Memory devices are ESDsensitive, handling guidelines are included.
Chapter 14. Mechanical Data - Detailed package drawings and specifications are shown in this
section.
Additional and/or updated information on these products is available from:
Texas Instruments
Customer Response Center
P.O. Box 809066
Dallas, Texas 75380-9066
1-800-232-3200
For ordering information or further assistance please contact your nearest Texas Instruments
Sales Office or Distributor as listed in the back of this book.
Table of Contents
CHAPTER 1.
GENERAL INFORMATION
Alphanumeric Index .......................................................... 1-1
Ordering.lnformation ......................................................... 1-2
DR~MNRAM/FMEM ..................................................... 1-2
DRAM Module ........................................................... 1-4
EPROM/OTP PROM/Flash EEPROM ...................................... 1-6
MOS Memory IC Line-up ..................................................... 1-7
Military IC Line-up ........................................................... 1-8
CHAPTER 2.
SELECTION GUIDE
DRAM .. ; .................................................................. 2-1
DRAM Module .............................................................. 2-4
EPROM/FLASH EEPROM .................................................... 2-6
OTP PROM ................................................................. 2-9
Application Specific Memories ................................................ 2-11
CHAPTER 3.
ALTERNATE SOURCE DIRECTORY
DRAM ...................................................................... 3-1
DRAM Module .............................................................. 3-4
EPROM/FLASH EEPROM/OTP PROM ........................................ 3-7
Application Specific Memories ................................................ 3-11
CHAPTER 4.
GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTURE
General Concept and Type of Memories ........................................ 4-1
Operating Conditions and Characteristics ....................................... 4-5
Timing Diagrams Conventions ................................................ 4-10
Basic Data Sheet Structure .................................................. 4-10
CHAPTER 5.
TMS44C256
TMS4C1024
TMS4C1025
TMS4C1027
TMS48C128
TMS48C138
TMS44100
TMS44101
TMS44400
TMS44410
DYNAMIC RAMS
1 048 576-bit
1 048 576-bit
1 048 576-bit
1 048 576-bit
1 048 576-bit
1 048 576-bit
4 194 304-bit
4 194 304-bit
4 194 304-bit
4 194 304-bit
(256K x 4) Enhanced Page Mode .......... 5-1
(1 024K x'1) Enhanced Page Mode ........ 5-23
(1 024K x 1) Nibble Mode ................ 5-23
(1 024K x 1) Static Column Decode Mode .. 5-23
(128K x 8) Enhanced Page Mode ......... 5-63
(128K x 8) Write-Per-Bit Operation ........ 5-63
(4096K x 1) Enhanced Page Mode ........ 5-87
(4096K x 1) Nibble Mode ............... 5-107
(1 024K x 4) Enhanced Page Mode ....... 5-125
(1 024K x 4) Write-Per-Bit Operation ...... 5-145
TMS416100
TMS416400
CHAPTER 6.
16 777 216-bit
16 777 216-bit
(16 384K x 1) Enhanced Page Mode ..... 5-165
(4096K x 4) Enhanced Page Mode ....... 5-187
DYNAMIC RAM MODULES
TM256GU9C
2359 296-bit
(256K x 9) Single-Sided .................. 6-1
TM024GAD8
8 388 608-bit
(1 024K x 8) Single-Sided ................. 6-7
TM124GU8A
8 388 608-bit
(1 024K x 8) Single-Sided ........... -. . . .. 6-13
TM256BBK32
8 388 608-bit
(256K x 32) Single-Sided ................ 6-21
TM024EAD9
9 437 184-bit
(1 024K x 9) Single-Sided ................ 6-31
TM124EAD9B
9 437 184-bit
(1 024K x 9) Single-Sided ................ 6-37
TM 124EAD9C
9 437 184-bit .
(1 024K x 9) Single-Sided ................ 6-37
TM256KBK36B
9 437 184-bit
(256K x 36) Single-Sided ................ 6-45
TM256KBK36C
9 437 184-bit
(256K x 36) Single-Sided ................ 6-55
TM512CBK32
16 777 216-bit
(512K x 32) Double-Sided ............... 6-21
TM512LBK36B 18874 368-bit
(512K x 36) Double-Sided ............... 6-45
TM512LBK36C 18 874 368-bit
(512K x 36) Double-Sided .. ' ............. 6-55
TM4100GBD8
33 554 432-bit
(4096K x 8) Single-Sided ................ 6-65
TM124BBK32
33554 432-bit
(1 024K x 32) Single-Sided ............... 6-73
TM4100EBD9
37748 736-bit
(4096K x 9) Single-Sided ................ 6-81
TM124MBK36A 37 748 736-bit
(1 024K x 36) Double-Sided .............. 6-89
TM124MBK36B 37748 736-bit
(1024K x 36) Single-Sided ............... 6-97
Memory Card Overview .................................................... 6-105
CHAPTER 7.
EPROM/OTP PROM/FLASH EEPROM
(16K x 8) CMOS EPROM ................. 7-1
131 072-bit
TMS27C128
131 072-bit
(16K x 8) CMOS OTP PROM ............. 7-1
TMS27PC128
TMS27C256
262144-bit
(32K x 8) CMOS EPROM ................ 7-15
TMS27PC256
262144-bit
(32K x 8) CMOS OTP PROM ............ 7-15
TMS29F256
262144-bit
(32K x 8) 5-V Flash EEPROM ............ 7-27
(32K x 8) 5-V Flash EEPROM ............ 7-27
TMS29F258
262144-bit
TMS29F259
262 144-bit
(32K x 8) 5-V Flash EEPROM ............ 7-27
TMS29F259 Package Addendum ............................................. 7-45
TMS87C257
262 144-bit
(32K x 8) CMOS Latched EPROM ....... . 7-47
(64K x 8) CMOS EPROM ............... . 7-57
TMS27C510
524 288-bit
(64K x 8) CMOS OTP PROM ........... . 7-57
TMS27PC510
524 288-bit
- TMS27C512
524 288-bit
(64K x 8) CMOS EPROM ............... . 7-69
(64K x 8) CMOS OTP PROM ...........,. 7-69
TMS27PC512
524288-bit
TMS29F512
524 288-bit
(64K x 8) 5-V Flash EEPROM ........... . 7-81
TMS29F512 Package Addendum
7-83
TMS27C010A
1 048 576-bit
(128K x 8) CMOS EPROM ............... 7-85
TMS27PC010A
1 048 576-bit
(128K x 8) CMOS OTP PROM ... '. . . . . . .. 7-85
TMS29F010
1 048 576-bit
(128K x 8) 5-V Flash EEPROM ........... 7-95
TMS29F010 Package Addendum ............................................ 7-117
TMS27C210A
1 048576-bit
(64K x 16) CMOS EPROM .............. 7-119
TMS27PC210A
TMS27C020
TMS27C040
TMS27PC040
TMS27C240
TMS27PC240
CHAPTER 8.
(64K x 16) CMOS OTP PROM ..........
(256K x 8) CMOS EPROM ..............
(512K x 8} CMOS EPROM ..............
(512K x 8) CMOS EPROM ..............
(256K x 16) CMOS EPROM
(256K x 16) CMOS OTP PROM
•••••••••
••
I
I
••
••••••
7-119
7-129
7-139
7-139
7-149
7-149
APPLICATION SPECIFIC MEMORIES
TMS29F816
TMS44C250
TMS44C251
TMS44C260
TMS48C121
TMS4C1050
TMS4C1060
TMS4C1070
TMS44460
CHAPTER 9.
1 048 576-bit
2 097 152-bit
4 194 304-bit
4 194 304-bit
4 194 304-bit
4 194 304-bit
16384-bit
1 048 576-bit
1 048 576-bit
1 048 576-bit
1 048 576-bit
1 048 576-bit
1 048 576-bit
1 048 576-bit
4 197 304-bit
(2K x 8) SCOPE Diary .................. 8-1
(256K x 4) Multipart Video RAM ........... 8-3
(256K x 4) Mulitport Video RAM .......... 8-31
(256K x 4) Parity DRAM ................. 8-73
(128K x 8) Multipart Video RAM .......... 8-91
(256K x 4) Field Memory ............... 8-125
(256K x 4) Field Memory ............... 8-125
(256K x 4) Field Memory ............... 8-141
(1024K x 4) Parity DRAM ............... 8-155
T
'"
MILITARY PRODUCTS
Military Introduction .......................................................... 9-1
DYNAMIC RAMS
. SMJ44C256
SMJ4C1024
SMJ44100
SMJ44400
1 048 576-bit
1 048 576-bit
4 197 304-bit
4 197 304-bit
(256K x 4) Enhanced Page Mode .......... 9-3
(1 024K x 1) Enhanced Page Mode ........ 9-23
(4096K x 1) Enhanced Page Mode ........ 9-41
(1 024K x 4) Enhanced Page Mode ........ 9-61
131 072-bit
262144-bit
524288-bit
1 048 576-bit
1 048 576-bit
(16K x 8) CMOS EPROM ................ 9-81
(32K x 8) CMOS EPROM ................ 9-91
(64K x 8) CMOS EPROM ............... 9-101
(128K x 8) CMOS EPROM .............. 9-113
(64K x 16) CMOS EPROM .............. 9-115
EPROMS
SMJ27C128
SMJ27C256
SMJ27C512
SMJ27C010
SMJ27C210
APPLICATION SPECIFIC MEMORIES
SMJ44C250
SMJ44C251
SMJ44C251A
CHAPTER 10.
1 048 576-bit
1 048 576-bit
1 048 576-bit
(256K x 4) Multipart Video RAM
(256K x 4) Multipart Video RAM
(256K x 4) Mulitport Video RAM
9-117
9-147
9-149
DATAPATH VLSI PRODUCTS
CACHE ADDRESS COMPARATORS/DATA RAMS
SN74ACT2140A
SN74ACT2150A
TMS2150A
SN74ACT2151
SN74ACT2153
4K x 18/8K x 18
512 x 8
512 x 8
1K x 11
1K x 11
10-1
10-3
10-5
10-7
10-7
iii
SN74ACT2152A
SN74ACT2154A
SN74ACT2155
SN74ACT2156
SN74ACT2157
SN74ACT2158
SN74ACT2159
SN74ACT2160
SN74ACT2163
SN74ACT2164
SN74BCT2160
SN74BCT2141
SN74BCT2163
SN74BCT2164
SN74BCT2166
SN74BCT2165
2K x 8
2Kx 8
2K x 8
16K x 4
2K x 16
8K x 9
8K x 9
8K x 4
16K x 5
16K x 5
8K x 4
8K x 18
16K x 5
16Kx5
16Kx5
8K x 4
· ....................................... 10-9
· ...................................... 10-9
· . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-11
10-13
10-15
10-17
10-17
10-19
..................................... . 10-21
..................................... . 10-21
..................................... . 10-23
..................................... . 10-25
..................................... . 10-27
..................................... . 10-27
..................................... . 10-27
..................................... . 10-:29
DYNAMIC MEMORY SUPPORT PRODUCTS
TMS4500A
THCT4502B
SN7 4ACT4503
SN74ALS6300
SN74ALS6310A
SN74ALS6311A
SN74BCT2423A
SN74BCT2424A
SN74LS610
SN74LS612
Dynamic RAM Controller ............................. .
Dynamic RAM Controller ............................. .
Dynamic RAM Controller ............................. .
Input-Selectable Refresh Timer ....................... .
Static Column and Page Mode Access Detector ...... , .. .
Static Column and Page Mode Access Detector ......... .
16-bit Latched Multiplexer/Demultiplexer Bus Transceiver .
16-bit Latched Multiplexer/Demultiplexer Bus Transceiver .
Memory Mapper .................................... .
Memory Mapper .................................... .
10-31
10-33
10-35
10-37
10-39
10-39
10-41
10-41
10-43
10-43
ERROR DETECTION AND CORRECTION (EDAC) PRODUCTS
SN74ALS632B
SN74AS632
SN74AS632A
SN74AS6364
CHAPTER 11.
32-bit
32-bit
32-bit
64-bit
Parallel Circuit ..................................
Parallel Circuit .................................
Flow-Thru Circuit .... "...........................
Flow-Thru Circuit ...............................
10-45
10-45
10-47
10-49
LOGIC SYMBOLS
Explanation of IEEE/l EC Logic Symbols for Memories ........................... 11-1
CHAPTER 12.
QUALITY AND RELIABILITY
MOS Memory Products Division Quality and Reliability Information ................ 12-1
CHAPTER 13.
ELECTROSTATIC DISCHARGE GUIDELINES
Guidelines for Handling Electrostatic-Discharge Devices and Assemblies .......... 13-1
CHAPTER 14.
MECHANICAL DATA
MOS Memory Products MOS Memory Products iv
Commercial ......................................... 14-1
Military ........................................... 14-21
General Information
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _G_e_n_e_ra_I_I_n_fo_r_m_a_ti_o_n___----'
General Information
Alphanumeric Index
SMJ27C010 ............ 9-113
SMJ27C128 ............ 9-81
SMJ27C210 ............ 9-115
SMJ27C256 ............ 9-91
SMJ27C512 ............ 9-101
SMJ44100 ............. 9-41
SMJ44400 ............. 9-61
SMJ44C250 ............ 9-117
SMJ44C251 ............ 9-147
SMJ44C251A ........... 9-149
SMJ44C256 ............ 9-3
SMJ4C1024 ............ 9-23
SN74ACT2140A ........ 10-1
SN74ACT2150A ........ 10-3
SN74ACT2151 ......... 10-7
SN74ACT2152A ........ 10-9
SN74ACT2153 ......... 10-7
SN74ACT2154A ........ 10-9
SN74ACT2155 · ........ 10-11
SN74ACT2156 · ........ 10-13
SN74ACT2157 · ........ 10-15
SN74ACT2158 · ........ 10-17
SN74ACT2159 · ........ 10-17
SN74ACT2160 · ........ 10-19
SN74ACT2163 ......... 10-21
SN74ACT2164 ......... 10-21
SN74ACT4503 ......... 10-35
SN74ALS6300 .......... 10-37
SN7 4ALS631 OA ........ 10-39
SN74ALS6311A ........ 10-39
SN74ALS632B ......... 10-45
SN74AS6364 ..... , ..... 10-49
SN74AS632 ............ 10-45
SN74AS632A ........... 10-47
SN74BCT2141 ......... 10-25
SN74BCT2160 ......... 10-23
SN74BCT2163 ......... 10-27
SN74BCT2164 ......... 10-27
SN74BCT2165 ......... 10-29
SN74BCT2166 ......... 10-27
SN74BCT2423A ........ 10-41
SN74BCT2424A ........ 10-41
SN74LS610 ............ 10-43
SN74LS612 ............ 10-43
THCT 4502B ............ 10-33
TM024EAD9 ........... 6-31
TM024GAD8 ........... 6-7
TM124BBK32 .......... 6-73
TM124EAD9B .......... 6-37
TM 124EAD9C .......... 6-37
TM124GU8A ........... 6-13
TM124MBK36A ......... 6-89
TM124MBK36B ......... 6-97
TM256BBK32 .......... 6-21
TM256GU9C ........... 6-1
TM256KBK36B ......... 6-45
TM256KBK36C ......... 6-55
TM4100EBD9 .......... 6-81
TM4100GBD8 .......... 6-65
TM512CBK32 .......... 6-21
TM512LBK36B ......... 6-45
TM512LBK36C ......... 6-55
TMS2150A ............. 10-5
TMS27C010A .......... 7-85
TMS27C020 ............ 7-129
TMS27C040 ., .......... 7-139
TMS27C128 ............ 7-1
TMS27C210A .......... 7-119
TMS27C240 ............ 7-149
TMS27C256 ............ 7-15
TMS27C510 ............ 7-57
TMS27C512 ............ 7-69
TMS27PC010A . . . . ..
TMS27PC040 .......
TMS27PC128 .......
TMS27PC210A ......
TMS27PC240 .......
TMS27PC256 .......
TMS27PC510 .......
TMS27PC512 .......
TMS29F010 .........
TMS29F256 .........
TMS29F258 .........
TMS29F259 . . . . . . . ..
TMS29F512 .........
TMS29F816 .........
TMS416100 .........
TMS416400 .........
TMS44100 ..........
TMS44101 ..........
TMS44400 ..........
TMS44410 ..........
TMS44460 ..........
TMS44C250 . . . . . . . ..
TMS44C251 .........
TMS44C256 . . . . . . . ..
TMS44C260 .........
TMS4500A ..........
TMS48C121 .........
TMS48C128 .........
TMS48C138 . . . . . . . ..
TMS4C1024 .........
TMS4C1025 .........
TMS4C1027 .........
TMS4C1050 .........
TMS4C1060 .........
TMS4C1070 .........
TMS87C257 .........
7-85
7-139
7-1
7-119
7-149
7-15
7-57
7-69
7-95
7-27
7-27
7-27
7-81
8-1
5-165
5-187
5-87
5-107
5-125
5-145
8-155
8-3
8-31
5-1
8-73
10-31
8-91
5-63
5-63
5-23
5-23
5-23
8-125
8-125
8-141
7-47
TEXAS ~
INSlRUMENlS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
1-1
General Information
DRAMNRAM/FMEM Ordering Information
Factory orders for 1 Meg DRAMs, VRAMs, and FMEMs described in this book should include an eight-part type
number as explained in the following example:
TMS
4
I
1. Prefix:
TMS
Commerical MOS
Military MOS
SMJ
2. Product Family: _ _ _ _ _ _ _ _ _ _ _ _ _ _..J
4
4
C
256
-10
DJ
DRAMNRAM/FMEM
3. Word Width:
1
Blank
Blank
4
xl
x 1 (256K and 1 Meg x 1 DRAM only)
x 4 (1 Meg FMEM only)
x4
x8
8
4. Technology: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-1
Blank
C
NMOS
CMOS
---------------------------1
5. Density:
121
1 Meg Parity DRAM (,44C260)
1 Meg VRAM (,48C121)
260
1 Meg DRAM (,4Cl024)
128
1 Meg DRAM ('48C128)
1024
138
1 Meg DRAM (,48C138)
1 Meg DRAM ('4Cl025)
1025
1 Meg DRAM (,4Cl027)
1027
250
1 Meg VRAM (,44C250)
1 Meg FMEM (,4Cl050)
251
1 Meg VRAM (,44C251)
1050
1 Meg FMEM (,4Cl060)
251A 1 Meg VRAM (' 44C251 A)
1060
256
1 Meg DRAM ('44C256)
1 Meg FMEM ('4Cl070)
1070
6. Speed Designator: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----J
DRAMsNRAMs
- 60
60 ns
-70
70 ns
- 80
80 ns
-10
100 ns
- 12
120 ns
- 15
150 ns
- 20
200 ns
FMEMs
- 30
25 ns
- 40
30 ns
- 60
50 ns
7. Package: - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
Commercial (Plastic)
Military (Ceramic)
FQ
OJ
Small-Outline J-Lead (SOJ)
Small-Outline Leadless Chip Carrier (SOLCC)
FV
Leadless Chip Carrier (CLCC)
ON
Thin Small-Outline J-Lead (ThinSOJ)
HJ
DZ
Small-Outline J-Lead (SOJ)
Small-Outline J-Lead (SOJ)
. HK
Flatpack
SO
Zig-Zag In-Line (ZIP)
N
Dual-In-Line (DIP)
JD
Dual-In-Line (DIP)
8. Temperature Range: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....J
Commerical
L
DoC to 70°C
Blank DOC to 70°C
Military
M
TEXAS
- 55°C to 125°C
l!1
INSlRUMENTS
1-2
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
General Information
DRAM Ordering Information
Factory orders for the 4 Meg and 16 Meg DRAMs described in this book should include an eight-part type number
as explained in the following example:
TMS
4
I
1. Prefix:
Commerical MOS
TMS
Military MOS
SMJ
2. Product Family: _ _ _ _ _ _ _ _ _ _ _ _ _ _....
4
3. Density: -
4
00
-80
OM
DRAM
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....
4
4 Meg
16 Meg
16
4. Word Width:
x1
4
x4
5. Mode of Operation: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
00
01
10
60
Enhanced Page Mode
Nibble Mode
Write-Per-Bit Operation
Parity
6. Speed Designator:
60 ns
- 60
- 70
70 ns
- 80
80 ns
-10
100 ns
-12
120 ns
- 15
150 ns
7. Package:
Commercial (Plastic)
OJ
Small-Outline J-lead (SOJ)
OM
Small-Outline J-lead (SOJ)
ON
Thin Small-Outline J-lead (ThinS OJ)
DZ
Small-Outline J-lead (SOJ)
SO
Zig-Zag In-Line (ZIP)
Military
HM
HJ
HR
JD
(Ceramic)
Small-Outline leadless Chip Carrier (SOlCC)
Small-Outline J-lead (SOJ)
Flatpack
Side-Brazed Dual-In-Line
--------------------------------1
8. Temperature Range:
Commercial
Blank O°C to 70°C
Military
M - 55°C to 125°C
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
1-3
General Information
Standard DRAM Module Ordering Information
Factory orders for the standard DRAM Modules described in this book should include a seven-part type number as
explained in the following example:
TM
I
AD
. TEXAS -1.!1
INSTRUMENTS
1-4
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9
-10
General Information
Differentiated DRAM Module Ordering Information
Factory orders for the mixed DRAM Modules described in this book should include an eight-part type number as
explained in the following example:
TM
1. Prefix: _ _ _ _ _ _ _ _ _ _ _ _ _......1
TM
2. Density:
256
512
124
256
K
BK
36
A
-10
Commerical TI MOS Module
256K
512K
1 Meg
3. Pinout Configuration: - - - - - - - - - - - - - - - - - '
B
K
C
L
E
M
G
4. Board Dimensions: _ _ _-'-_ _ _ _ _ _ _ _ _ _ _ _ _ _-...J
U
AD
BK
5. Word Width Output:
8
x8
9
x9
32
x 32
36
x 36
6. Devices Used:
Blank 8 - '44C256s ('256BBK32)
Blank 16 - '44C256s (,512CBK32)
Blank 8 - '44400s ('124BBK32)
A
2 - '44C256s ('124GU8A)
A
8 - '44400s + 4 - '4C1024s ('124MBK36A)
B
2 - '44400s + 1 - '4C1024 (,124EAD9B)
B
8 - '44C256s + 1 - '44C260 (,256KBK36B)
B
16 - '44C256s + 2 - '44C260s ('512LBK36B)
B
8 - '44400s + 1 - '44460 ('124MBK36B)
C
2 - '44C256s + 1 - '4C1024 ('256GU9C)
C
2 - '44400s + 1 - '44100 ('124EAD9C)
C
8 - '44C256s + 2 - '44C260s (,256KBK36C)
C
16 - '44C256s + 4 - '44C260s ('512LBK36C)
7. Speed Designator: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1
-6
-7
-8
- 100
60 ns
70 ns
80 ns
100 ns
- 60
-70
- 80
-10
60 ns
70 ns
80 ns
100 ns
8. Temperature Range:
Blank O°C to 70°C
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
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HOUSTON. TEXAS 77001
1-5
General Information
EPROM/OTP PROM/Flash EEPROM Ordering Information
Factory orders for EPROMs, OTPs, and Flash EEPROMs described in this book should include a nine-part type
number as explained in the following example:
TMS
1. Prefix: _ _ _ _ _ _ _ _ _ _ _ _ _--'1
TMS
SMJ
27
P
C
512
-10
FM
L
Commerical MOS
Military MOS
---------------1
2. Product Family:
27
EPROM/OTP
29
Flash EEPROM
87
Latched EPROM
3. Erasability: - - - - - - - - - - - - - - - - - -....
P
Non-erasable
Blank
Erasable
4. Technology: - - - - - - - - - - - - - - - - - - - - '
C
CMOS
F
CMOS Flash EEPROM
5. Density: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
-1, -17, -170
80 ns
- 8, - 80
170 ns
100 ns
-10, -100
200 ns
- 2, - 20, - 200
Blank, - 20, - 200
120 ns
-12, - 120
250 ns
150 ns
- 1, - 15, - 150
300 ns
- 30, - 300
7. Package: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
OTPs (Plastic)
N
Dual-In-Line (DIP)
FM Chip Carrier
Flash EEPROMs
Ceramic Dual-In-Line (DIP)
N
Plastic Dual-In-Line (DIP)
FM Plastic Chip Carrier
8. Temperature Range: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
Commerical
L
O°C to 70°C
E
- 40°C to 85°C
Q
- 40°C to '125°C
9. 168 Hour Burn-in Option:
Commerical
4
168 Hour Burn-in
Blank No Burn-in
EPROMs (Ceramic)
Dual-In-Line (DIP)
~
512
816
16K
512K
128
128K
010A 1 Meg
210A 1 Meg
256
256K
020
257
256K
2 Meg
040
258
256K
4 Meg
240
259
256K
4 Meg
512K
510
6. Speed Designator: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....J
J
J
Military
M
- 55°C to 125°C
Military
Blank
5004 Processing
TEXAS
lJ1
INSTRUMENTS
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POST OFFICE BOX 1443
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HOUSTON, TEXAS 77001
4
General Information
MOS Memory
Ie Line-up
DRAMs- CMOS
1024Kl1024K x 1 TMS4C1024 -TMS4C1025- TMS4C1027
256K x 4 1 TMS44C250 - TMS44C251 - TMSS44C256 - TMS44C260
(VRAM)
(VRAM)
(Parity)
TMS4C1 050- TMS4C1 060 . (Frame)
(Frame)
128K x 8 4096K
CMOS
256K
Modules
512K
TMS44100 4096K x 1 1024Kx 4 - TMS44400 -
1
L
TMS48C121t-TMS48C128t- TMS48C138t
(VRAM)
L
16 385K 1..:6 385K x 1 1024Kx4 DRAM -
TMS4C1070t
(Frame)
TMS44101
TMS44410 -
TMS44460t
TMS416100t
TMS416400t
TMS256GU9C
256K " 9 256K x 3 2 - TM256BBK32
256Kx 3 6 - TM256KBK36B
TM256KBK36C
512K x 3 2 - TM512BBK32
512Kx36- TM512LBK36B
TM512LBK36C
'024K1'024K"8 -
TM024GAD8- TM124GU8A
1024Kx9- TM024EAD9 - TM 124EAD9B -TM 124EAD9C
1024Kx 3 2 - TM124CBK32
1024Kx 3 6 - TM124MBK36A
4096K
EPROMs -
CMOS
1
TM124MBK36B
4096Kx 8 - TM4100GBD8
4096Kx 9 - TM4100EBD9
128K-- 16Kx8_ TMS27C128
TMS27C256 - TMS87C257
256K - - 32Kx8 -
(Latched)
512K - - 64Kx8 1024K
L
2048K _
4096K
T
128K x 8 - TMS27C010A
64Kx 1 6 - TMS27C210A
256K x 8 TMS27C020t
512K x 8 - TMS27C040t
256Kx 1 6 - TMS27C240t
OTP - - CMOS1'28K - - 16K x 8 PROMs
256K - - 32K x 8 512K - - 64K x 8 -
T
4096K T
1024K
Flash - - CMOS
EEPROM
TMS27PC510t
TMS27PC512
512K x 8 - TMS27PC040t
256Kx 1 6 - TMS27PC240t
256K _ _ 32K x 8 _
512K _ _ 64Kx8 _
1024K _
TMS27PC128
TMS27PC256
128K x 8 - TMS27PC010A
64Kx 1 6 - TMS27PC210A
16K _ _ 2K x 8 -
1
TMS27C51 ot - TMS27C512
128K x 8 _
TMS29F816
(JTAG)
TMS29F256 - TMS29F258 TMS29F512t
TMS29F259
TMS29F010t
t Product under development by TI
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
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HOUSTON, TEXAS 77001
1-7
General Information
MOS Memory Military
Ie Line-up
DRAMs- CMOS 11024K T
1024Kx 1 256K x 1 -'-
SMJ4C1024 ,
SMJ44C256- SMJ44C250 t -SMJ44C251At- SMJ44C251t
4096K x 1 1024K x 4 -
SMJ44100t
SMJ44400t
128K 256K -
16K x 8 32K x 8 -
SMJ27C128
SMJ27C256
512K -
64K x 8 -
SMJ27C512
L
(VRAM)
4096K T
L
[
EPROMs -
CMOS -
1024K - , - 128K x 8 -
SMJ27C010 t
L 64K x 16 -
SMJ27C210t
.
t Product under development by TI
TEXAS
l!1
INSTRUMENTS
1-8
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
(VRAM)
(VRAM)
Selection Guide
Selection Guide
Selection Guide
DRAM
Density
1024K
Power
Supply
(V)
Max Power
Dissipation
Device
Number
1024Kx1
TMS4C1024-60*
TMS4C1024-70*
TMS4C1024-80
TMS4C 1024-10
TMS4C1024-12
100
120
SMJ4C1024-10
SMJ4C1024-12
SMJ4C1024-15
TMS4C1025-80
TMS4C1 025-1 0
TMS4C1025-12
100
413
358
120
303
TMS4C1027-80
TMS4C1027-10
TMS4C1027-12
80
100
120
5± 10%
TMS44C256-60*
TMS44C256-70*
TMS44C256-80
TMS44C256-10
TMS44C256-12
60
70
80
100
120
SMJ44C256-10
SMJ44C256-12
SMJ44C256-15
256K x 4
128K x 8
4096K
Max
Access
Time (ns)
Organization
(Words x Bits)
4096K x 1
Package t
Comments
Page
18,
20/26,
20/26,20
N,
OJ
ON, SO
CMOS
Enhanced
Page ~ode
5-23
20/26,
HJ,
FO,HK
Military
CMOS
Enhanced
Page Mode
9-23
20,20
11
18,
20/26,
20/26,20
N,
OJ
ON, SO
CMOS
Nibble
Mode
5-23
413
358
303
11
18,
20/26,
20/26,20
N,
OJ
ON, SO
CMOS
Static
Mode
5-23
5± 10%
523
440
413
358
303
11
20,
20/26,
20/26,20
N,
OJ
ON, SO
CMOS
Enhanced
Page Mode
5-1
100
120
150
5 ± 10%
385
330
303
17
20,
20/26,20
JO,
HJ, FO
Military
CMOS
Enhanced
Page Mode
9-3
TMS48C128-70
TMS48C128-80
TMS48C128-10
70
80
100
5:!: 10%
468
440
385
11
24/26
OJ
CMOS
Enhanced
Page Mode
5-63
TMS48C138-70
TMS48C138-80
TMS48C 138-10
70
80
100
5± 10%
468
440
385
11
24/26
OJ
CMOS
Enhanced
Page Mode
Write·perBit Operation
5-63
TMS441 00-60
TMS441 00-70
TMS44100-80
TMS441 00-1 0
60
70
80
5 ± 10%
550
11
20/26,
OJ,
20/26,20 OM, SO
CMOS
Enhanced
Page Mode
5-87
100
SMJ44100-80§
SMJ441 00-1 O§
SMJ44100-12§
80
100
120
5 ± 10%
468
440
385
22
18,20,
20,20
Military
CMOS
Enhanced
Page Mode
9-41
TMS44101-60
TMS44101-70
TMS44101-80
TMS44101-10
60
70
80
5 ± 10%
523
468
413
358
11
20/26,
OJ,
20/26,20 OM, SO
CMOS
Nibble
Mode
5-107
Active
(mW)
Standby
(mW)
Pins
5 ± 10%
253
440
413
358
11
100
120
150
5± 10%
385
17
80
5± 10%
60
70
80
303
330
303
495
440
385
100
JO, HM
HJ, HR
N
Plaastic Dual In-Line Package (DIP)
OJ
Plastic Small-Outline J-Lead (SOJ)
ON
Plastic Thin Small-Outline J-lead (ThinSoJ)
OM
Plastic Small-Outline J-lead (SOJ)
FO
Ceramic Small-Outline leadless Chip Carrier (Military) (SOlCC)
HJ
Ceramic Small-Outline leadless J-lead (Military) (SOlCC)
HK
Flatpack (Military)
HM
Plastic Small-Outline leadless Chip Carrier (Military) (SOlCC)
HR
Flatpack (Military)
JO
Ceramic Side-Brazed Dual In-Line Package (Military) (DIP)
SO
Plastic Zig-Zag In-Line Package (ZIP)
Available only in OJ package
Advance Information for product under development by TI
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
2-1
Selection Guide
DRAM (Concluded)
Density
4096K
(cont'd)
16385K
Max Power
Dissipation
Max
Access
Time (ns)
Power
Supply
(V)
Active
(mW)
Standby
(mW)
TMS44400-60
TMS44400-70
TMS44400-80
TMS44400-10
60
70
80
100
5 ± 10%
550
495
440
385
11
SMJ44400-80l
SMJ44400-10l
SMJ44400-12l
80
100
120
5 ± 10%
468
440
358
TMS4441 0-60
TMS4441 0-70
TMS4441 0-80
TMS44410-10
60
70
80
100
5
10%
16 385K x 1
TMS416100-60l
TMS416100-70l
TMS416100-80l
TMS416100-10l
60
70
80
100
4096K x 4
TMS416400-60l
TMS416400-70l
TMS416400-80l
TMS416400-10l
60
70
80
100
Organization
(Words x Bits)
1024K x 4
Device
Number
Package t Comments
Page
20/26,
20/26,20
OJ,
OM, SO
CMOS
Enhanced
Page Mode
5-125
22
20,20,
20,20
JO, HM
HJ, HR
Military
CMOS
Enhanced
Page Mode
9-61
523
468
413
358
11
20/26,
20/26,20
OJ,
OM,SO
CMOS
Enhanced
Page Mode
Write-perBit Operation
5-145
5 ± 10%
495
440
385
330
11
24/28
OZ
CMOS
Enhanced
Page Mode
5-165
5 ± 10%
495
440
385
330
11
24/28
OZ
CMOS
Enhanced
Page Mode
5-187
±
OJ
Plastic Small-Outline J-lead (SOJ)
OM
Plastic Small-Outline J-lead (SOJ)
OZ
Plastic Small-Outline J-lead (SOJ)
HJ
Ceramic Small-Outline leadless J-lead (Military) (SOlCC)
HM
Plastic Small-Outline leadless Chip Carrier (Military) (SOlCC)
HR
Flatpack (Military)
JO
Ceramic Side-Brazed Oualln-Line Package (Military) (OIP)
SO
Plastic Zig-Zag In-Line Package (ZIP)
Advance Information for product under development by TI
TEXAS
l!1
INSTRUMENlS
2-2
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Pins
Selection Guide
DRAM Module
Density
Organization
(Words x Bits)
Device
Number
Max
Access
Time (ns)
Max Power
Dissipation
Power
Supply
(V)
Active
(mW)
Standby
(mW)
Pins
Package
Page
2304K
256K x 9
TM256GU9C-6
TM256GU9C-70
TM256GU9C-80
TM256GU9C-10
60
70
80
100
5
5
5
5
± 5%
± 10%
± 10%
± 10%
1496
1320
1238
1073
31
33
33
33
30
Single-Sided,
Socketable
6-1
8192K
1024K x 8
TM024GAD8-6
TM024GAD8-70
TM024GAD8-80
TM024GAD8-10
60
70
80
100
5
5
5
5
± 5%
± 100/;
± 10%
± 10%
3990
3520
3300
2860
84
88
88
88
30
Single-Sided,
Socketable
6-7
TM124GU8A-6
TM124GU8A-70
TM124GU8A-80
TM124GU8A-10
60
70
80
100
5±5%
5 ± 10%
5 ± 10%
5 ± 10%
998
935
825
715
21
22
22
22
30
Single-Sided,
Socketable
6-13
256K x 32
TM256BBK32-6
TM256BBK32-70
TM256BBK32-80
TM256BBK32-10
60
70
80
100
5±5%
5 ± 10%
5 ± 10%
5 ± 10%
3990
3520
3300
2860
84
88
88
88
72
Single-Sided,
Socketable
6-21
1024K x 9
TM024EAD9-6
TM024EAD9-70
TM024EAD9-80
TM024EAD9-10
60
70
80
100
5
5
5
5
±5%
± 10%
± 10%
± 10%
4489
3960
3713
3218
95
99
99
99
30
Single-Sided,
Socketable
6-31
TM 124EAD9B-6
TM 124EAD9B-70
TM124EAD9B-80
TM124EAD9B-10
60
70
80
100
5±5%
5 ± 10%
5 ± 10%
5 ± 10%
1496
1403
1238
1073
32
33
33
33
30
Single-Sided,
Socketable
6-37
TM124EAD9C-6
TM124EAD9C-70
TM 124 EAD9C-80
TM124EAD9C-10
60
70
80
100
5±5%
5 ± 10%
5 ± 10%
5 ± 10%
1496
1403
1238
1073
32
33
33
33
30
Single-Sided,
Socketable
6-37
TM256KBK36B-6
TM256KBK36B-70
TM256KBK36B-80
TM256KBK36B-10
60
70
80
100
5±5%
5 ± 10%
5 ± 10%
5 ± 10%
4489
3960
3713
3218
95
99
99
99
72
Single-Sided,
Socketable
6-45
TM256KBK36C-6.
TM256KBK36C-70
TM256KBK36C-80
TM256KBK36C-10
60
70
80
100
5±5%
5 ± 10%
5 ± 10%
5 ± 10%
4988
4400
4125
3575
105
110
110
110
72
Single-Sided,
Socketable
6-55
9216K
256K x 36
16384K
512Kx32
TM512CBK32-6
TM512CBK32-70
TM512CBK32-80
TM512CBK32-10
60
70
80
100
5±5%
5 ± 10%
5 ± 10%
5 ± 10%
4074
3608
3388
2948
168
176
176
176
72
Double-Sided,
Socketable
6-21
18432K
512Kx36
TM512LBK36B-6
TM512LBK36B-70
TM512LBK36B-80
TM512LBK36B-10
60
70
80
100
5
5
5
5
± 5%
± 10%
± 10%
± 10%
4583
4059
3812
3317
189
198
198
198
72
Double-Sided,
Socketable
6-45
TM512LBK36C-6
TM512LBK36C-70
TM512LBK36C·80
TM512LBK36C-10
60
70
80
100
5±5%
5 ± 10%
5 ± 10%
5 ± 10%
5093
4510
4235
3685
210
220
220
220
72
Double-Sided,
Socketable
6-55
,
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
2-3
Selection Guide
DRAM Module (Concluded)
DensIty
32768K
36864K
t
OrganIzation
(Words x Bits)
DevIce
Number
Power
Supply
Max
Access
TIme (ns)
M
Max Power
DIssIpation
ActIve
(mW)
Standby
(mW)
Package
Page
4096K x 8
TM4100GBD8-6
TM4100GBD8-70
TM4100GBD8-80
TM4100GBD8-10
60
70
80
100
5±5%
5± 10%
5 ± 10%
5 ± 10%
3990
3740
3300
2860
84
88
88
88
30
Single-Sided,
Socketable
6-65
1024K x 32
TM 124BBK32-6
TM124BBK32-70
TM124BBK32-80·
TM124BBK32-10
60
70
80
100
5±5%
5± 10%
5 ± 10%
5 ± 10%
3990
3740
3300
2860
84
88
88
88
72
Single-Sided,
Socketable
6-73
4096K x 9
TM4100EBD9-6
TM4100EBD9-70
TM4100EBD9-80
TM41 00EBD9-1 0
60
70
80
100
5±5%
5± 10%
5± 10%
5± 10%
4489
4208
3713
3218
95
99
99
99
30
Single-Sided,
Socketable
6-81
1024Kx 36
TM124MBK36A-6t
TM124MBK36A-7t
TM124MBK36A-8t
60
70
80
5±5%
5±5%
5±5%
5985
5250
4725
126
126
126
72
Double-Sided,
Socketable
6-89
TM124MBK36B-6t
TM124MBK36B-7t
TM124MBK36B-8t
60
70
80
5±5%
5±5%
5±5%
4489
4016
3544
95
95
95
72
Single-Sided,
Socketable
6-97
Advance Information for product under development by TI
TEXAS •
. INSlRUMENlS
2-4
PIns
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Selection Guide
EPROM/Flash EEPROM
Density
128K
256K
Organization
(Words x Bits)
16K x 8
32K x 8
Max Power
Dissipation
Device
Number
Max
Access
Time (ns)
Power
Supply
(V)
TMS27C128-100
TMS27C128-120
TMS27C128-12
TMS27C12-1
TMS27C128-15
TMS27C128-2
TMS27C128-20
TMS27C128
TMS27C128-25
100
120
120
150
150
200
200
250
250
5±5'7'0
5±5'7'0
5 ± 10%
5±5%
5± 10%
5±5'7'0
5 ± 10%
5±5'7'0
5 ± 10%
158
158
165
158
165
158
165
158
165
1.4
28
J
CMOS
7-1
SMJ27C128-12
SMJ27C128-15
SMJ27C128-17
SMJ27C128-20
SMJ27C128-25
SMJ27C128-30
120
150
170
200
250
300
5 ± 10%
220
1.7
28
J
Military
CMOS
9-81
TMS27C256-120
TMS27C256-12
TMS27C256-150
TMS27C256-15
TMS27C256-1
TMS27C256-17
TMS27C256-2
TMS27C256-20
TMS27C256
TMS27C256-25
120
120
150
150
170
170
200
200
250
250
5±5'7'0
5 ± 10%
5±5'7'0
5 ± 10%
5±5'7'0
5± 10%
5±5'7'0
5± 10%
5±5'7'0
5± 10%
158
165
158
165
158
165
158
165
158
165
1.4
28
J
CMOS
7-15
SMJ27C256-15
SMJ27C256-17
SMJ27C256-20
SMJ27C256-25
SMJ27C256-30
150
170
200
250
300
5± 10%
220
1.7
28
J
Military
CMOS
9-91
TMS29F256-170
TMS29F256-200
TMS29F256-20
TMS29F256-250
TMS29F256-25
TMS29F256-300
TMS29F256-30
170
200
200
250
250
300
300
5±5'7'0
5±5'7'0
5± 10%
5±5'7'0
5 ± 10%
5±5'7'0
5± 10%
83
17
28,28,
32
J, N,
FM
CMOS 5-V
Flash
EEPROM;
EPROM
Pinout
7-27
TMS29F258-170
TMS29F258-200
TMS29F258-20
TMS29F258-250
TMS29F258-25
TMS29F258-300
TMS29F258-30
170
200
200
250
250
300
300
5±5'7'0
5±5'7'0
5± 10%
5±5'7'0
5 ± 10%
5±5'7'0
5 ± 10%
83
17
28,28,
32
J, N,
FM
CMOS 5-V
Flash
EEPROM;
EEPROM
Pinout
7-27
TMS29F259-170
TMS29F259-200
TMS29F259-20
TMS29F259-250
TMS29F259-25
TMS29F259-300
TMS29F259-30
170
200
200
250
250
300
300
5±5'7'0
5±5'7'0
5 ± 10%
5±5'7'0
5 ± 10%
5±5'7'0
5 ± 10%
83
17
28,28,
32
J, N,
FM
CMOS 5-V
Flash
EEPROM;
12-V Flash
Memory
Pinout
7-27
Active
(mW)
Pins
Standby
CMOS
(mW)
Package t Comments
Page
tJ
Ceramic Dual In-Line Package (DIP)
Plastic Dual In-Line Package (DIP)
FM Plastic Chip Carrier
N
TEXAS
-1!1
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
2-5
Selection Guide
EPROM/Flash EEPROM
Density
Organization
(Words x Bits)
Max
Access
Time (ns)
Device
Number
Power
Supply
(V)
Max Power
Dissipation
Active
(mW)
Standby
CMOS
(mW)
Pins
Package t
Comments
Page
256K
(cont'd)
32K x 8
(cont'd)
TMS87C257-150
TMS87C257-1
TMS87C257-2
TMS87C257
150
170
200
250
5:!:5%
158
1.4
28
J
CMOS
Latched
EPROM
7-47
512K
64Kx8
TMS27C510-120l:
TMS27C510-12l:
TMS27C510-150l:
TMS27C510-15l:
TMS27C510-170l:
TMS27C510-17l:
TMS27C510-200l:
TMS27C510-20l:
TMS27C510-250l:
TMS27C510-25l:
120
120
150
150
170
170
200
200
250
250
5:!:5%
5± 10%
5:!:5%
5:!: 10%
5:!:5%
5 ± 10%
5:!:5%
5:!:10%
5:!:5%
5:!: 10%
158
165
158
165
158
165
158
165
158
165
1.4
32
J
CMOS;
1 Meg
EPROM
Compatible
Pinout
7-57
TMS27C512-100
TMS27C512-10
TMS27C512-120
TMS27C512-12
TMS27C510-150
TMS27C512-15
TMS27C512-2
TMS27C512-20
TMS27C512
TMS27C512-25
100
100
120
120
150
150
200
200
250
250
5±5%
5 ± 10%
5:!:5%
5:!: 10%
5±5%
5:!:10%
5:!:5%
5:!:10%
5:!:5%
5:!:10%
158
165
158
165
158
165
158
165
158
165
1.4
28
J
CMOS
7-69
SMJ27C512-20
SMJ27C512-25
SMJ27C512-30
200
250
300
5 ± 10%
263
1.8
28
J
Military
CMOS
9-101
TMS29F512-100l:
TMS29F512-120l:
TMS29F512-12l:
TMS29F512-150l:
TMS29F512-15l:
TMS29F512-200l:
TMS29F512-20l:
100
120
120
150
150
200
200
5:!:5%
5:!:5%
5± 10%
5:!:5%
5:!:10%
5:!:5%
5± 10%
79
79
83
79
83
79
83
5.5
32,32,
32
J, N,
FM
CMOS 5-V
Flash
EEPROM
7-81
TMS27C01 OA-1 00
TMS27C010A-120
TMS27C010A-12
TMS27C010A-150
TMS27C010A-15
TMS27C010A-200
TMS27C010A-20
100
120
120
150
150
200
200
5:!:5%
5:!:5%
5:!:10%
5:!:5%
5:!:10%
5:!:5%
5:!:10%
158
158
165
158
165
158
165
0.55
32
J
CMOS
7-85
SMJ27C010-17
SMJ27C010-20
SMJ27C010-25
170
200
250
5:!:10%
220
1.5
32
J
Military
CMOS
9-113
TMS29F010-100l:
TMS29F010-120l:
TMS29F010-12l:
TMS29F010-150l:
TMS29F010-15l:
TMS29F010-200l:
TMS29F010-20l:
100
120
120
150
150
200
200
5:!:5%
5:!:5%
5:!: 10%
5:!:5%
5:!:10%
5:!:5%
5:!: 10%
79
79
83
79
83
79
83
5.5
32,32,
32
J, N,
FM
CMOS 5-V
Flash
EEPROM
7-95
1024K
128K x 8
tJ
Ceramic Dual In-Line Package (DIP)
N
Plastic Dual In-Line Package (DIP)
FM Plastic Leaded Chip Carrier
l: Advance Information for product under development by TI
TEXAS •
INSlRUMENTS
2-6
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Selection Guide
EPROM/Flash EEPROM (Concluded)
Density
1024K
(cont'd)
t
Organization
(Words x Bits)
64K x 16
Power
Supply
(V)
Max Power
Dissipation
Device
Number
Max
Access
Time (ns)
TMS27C210A-120:f:
TM S27C21 OA-12:f:
TMS27C210A-150:f:
TMS27C210A-15:f:
TMS27C210A-200:f:
TMS27C210A-20:f:
TMS27C210A-250:f:
TMS27C210A-25:f:
120
120
150
150
200
200
250
250
5±5%
5± 10%
5±5%
5 ± 10%
5±5%
5± 10%
5±5%
5 ± 10%
158
165
158
165
158
165
158
165
0.55
SMJ27C210A-17
SMJ27C210A-20
SMJ27C210A-25
170
200
250
5 ± 10%
220
Active
(mW)
Package t
Comments
Page
40
J
CMOS
7-119
1.5
32
J
Military
CMOS
9-115
Standby
CMOS
(mW)
Pins
2048K
256K x 8
TMS27C020-100:f:
TMS27C020-120:f:
TMS27C020-12:f:
TMS27C020-150:f:
TMS27C020-15:f:
TMS27C020-200:f:
TMS27C020-2o:f:
TMS27C020-250:f:
TMS27C020-25:f:
100
120
120
150
150
200
200
250
250
5±5%
5±5%
5 ± 10%
5±5%
5 ± 10%
5±5%
5± 10%
5±5%
5± 10%
158
158
165
158
165
158
165
158
165
0.55
32
J
CMOS
7-129
4096K
512K x 8
TMS27C040-8:f:
TMS27C040-80:f:
TMS27C040-100:f:
TMS27C040-10:f:
TMS27C040-120:f:
TMS27C040-12:1:
TMS27C040-150:l:
TMS27C040-15:1:
80
80
100
100
120
120
150
150
5±5%
5± 10%
5±5%
5± 10%·
5±5%
5± 10%
5±5%
5±10%
263
275
263
275
263
275
263
275
0.55
32
J
CMOS
7-139
256K x 16
TMS27C240-8:1:
TMS27C240-80:f:
TMS27C240-100:f:
TMS27C240-10:l:
TMS27C240-120:l:
TMS27C240-12:1:
TMS27C240-150:l:
TMS27C240-15:1:
80
80
100
100
120
120
150
150
5±5%
5± 10%
5±5%
5± 10%
5±5%
5± 10%
5±5%
5± 10%
263
275
263
275
263
275
263
275
0.55
40
J
CMOS
7-149
Ceramic Dual In-Line Package (DIP)
:I: Advance Information for product under development by TI
TEXAS ~
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
2-7
Selection Guide
One-Time Programmable (OTP) PROM
Density
Organization
(Words x Bits)
Device
Number
Max Power
Dissipation
Power
Supply
Max
Access
Time (ns)
M
Active
(mW)
Standby
CMOS
(mW)
Pins
Package t Comments
Page
128K
16K x 8
TMS27PC128-1
TMS27PC128-15
TMS27PC128-2
TMS27PC128-20
TMS27PC128
TMS27PC128-25
150
150
200
200
250
250
5±5%
5 ± 10%
5±5%
5 ± 10%
5±5%
5± 10%
158
165
158
165
158
165
1.4
28,32
N, FM
CMOS
7-1
256K
32K x 8
TMS27PC256-150
TMS27PC256-15
TMS27PC256-1
TMS27PC256-17
TMS27PC256-2
TMS27PC256-20
TMS27PC256
TMS27PC256-25
150
150
170
170
200
200
250
250
5±5%
5 ± 10%
5±5%
5 ± 10%
5±5%
5 ± 10%
5±5%
5 ± 10%
158
165
158
165
158
165
158
165
1.4
28,32
N, FM
CMOS
7-15
512K
64K x 8
TMS27PC510-120t
TMS27PC51O-150 t
TMS27PC510-15t
TMS27PC510-170t
TMS27PC510-171:
TMS27PC510-200:t:
TMS27PC510-20t
TMS27PC510-250 t
TMS27PC510-25:t:
120
150
150
170
170
200
200
250
250
5±5%
5±5%
5 ± 10%
5±5%
5 ± 10%
5±5%
5± 10%
5±5%
5 ± 10%
158
158
165
158
165
158
165
158
165
1.4
32,32
N, FM
CMOS
1 Meg OTP
Compatible
Pinout
7-57
TMS27PC512-100
TMS27PC512-10
TMS27PC512-120
TMS27PC512-12
TMS27PC512-150
TMS27PC512-15
TMS27PC512-2
TMS27PC512-20
TMS27PC512
TMS27PC512-25
100
100
120
120
150
150
200
200
250
250
5±5%
5± 10%
5 ± 5% .
5± 10%
5±5%
5 ± 10%
5±5%
5± 10%
5±5%
5± 10%
158
165
158
165
158
165
158
165
158
165
1.4
28,32
N, FM
CMOS
7-69
1024K
128K x 8
TMS27PC01 OA-1 00
TMS27PC010A-120
TMS27PC010A-12
TMS27PC010A-150
TMS27PC010A-15
TMS27PC010A-200
TMS27PC010A-20
100
120
120
150
150
200
200
5±5%
5±5%
5± 10%
5±5%
5± 10%
5±5%
5 ± 10%
158
158
165
158
165
158
165
0.55
32
FM
CMOS
7-85
1024K
(cont'd)
64K x 16
TMS27PC210A-120:t:
TMS27PC210A-12t
TMS27PC210A-150t
TMS27PC210A-15 t
TMS27PC210A-200t
TMS27PC210A-20t
TMS27PC210A-250:t:
TMS27PC210A-25:1:
120
120
150
150
200
200
250
250
5±5%
5 ± 10%
5±5%
5± 10%
5 ± 5%
5 ± 10%
5±5%
5 ± 10%
158
165
158
165
158
165
158
165
0.55
44
FN
CMOS
7-119
N
Plastic Dual In-Line Package (DIP)
FM
Plastic Leaded Chip Carrier
FN
Plastic Leaded Chip Carrier
Advance Information for product under development by TI
TEXAS •
INSTRUMENTS
2-8
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Selection Guide
One-Time Programmable (OTP) PROM (Concluded)
Density
4096K
Organization
(Words x Bits)
Max
Access
Time (ns)
Device
Number
Power
Supply
(V)
Max Power
Dissipation
Active
(mW)
Standby
CMOS
(mW)
Pins
Package t Comments
Page
512KxB
TMS27PC040-B+
TMS27PC040-BO+
TMS27PC040-100+
TMS27PC040-10+
TMS27PC040-120+
TMS27PC040-12+
TMS27PC040-150+
TMS27PC040-15+
BO
SO
100
100
120
120
150
150
5±5%
5± 10%
5±5%
5 ± 10%
5±5%
5 ± 10%
5±5%
5± 10%
263
275
263
275
263
275
263
275
0.55
32
FM
CMOS
7-139
256Kx16
TMS27PC240-S+
TMS27PC240-BO+
TMS27PC240-100+
TMS27PC240-10+
TMS27PC240-120+
TMS27PC240-12+
TMS27PC240-150+
TMS27PC240-15+
BO
BO
100
100
120
120
150
150
5±5%
5 ± 10%
5±5%
5 ± 10%
5±5%
5± 10%
5±5%
5 ± 10%
263
275
263
275
263
275
263
275
0.55
44
FN
CMOS
7-149
TEXAS
l.!1
t FM Plastic Leaded Chip Carrier
FN
Plastic Leaded Chip Carrier
+Advance Information for product under development by TI
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
2-9
Selection Guide
Application Specific Memories (ASM)
Density
Organization
(Words x Bits)
Max
Access
Time (ns)
Device
Number
Power
Supply
Max Power
Dissipation
Pins
(V)
Active
(mW)
Standby
(mW)
Package t
Comments
Page
16K
2K x 8
TMS29F816 t
TBD
5 ± 10%
TBD
TBD
18
FM
SCOPE
Diary
Storage
Device
8-1
1024K
256K x 4
TMS44C250-1
TMS44C250-10
TMS44C250-12
100
100
120
5±5%
5 ± 10% .
5 ± 10%
578
605
523
184
193
193
28,28
DZ, SD
CMOS
Multipart
Video RAM
8-3
SMJ44C250-10t
SMJ44C250-1 ;
SMJ44C250-12t
SMJ44C250-2t
100
100
120
120
5 ± 10%
5±5%
5±10%
5±5%
635
635
550
550
90
90
83
83
28,28
HJ, JD
Military
CMOS
Multipart
Video RAM
9-117
TMS44C251-1
TMS44C251-10
TMS44C251-12
100
100
120
5±5%
5 ± 10%
5 ± 10%
578
605
523
184
193
193
28,28
DZ, SD
CMOS
Multipart
Video RAM
8-31
SMJ44C251-lOt
SMJ44C251-1t
SMJ44C251-12t
SMJ44C251-2t
100
100
120
120
5 ± 10%
5±5%
5 ± 10%
5±5%
TBD
TBD
28,28
HJ, JD
Military
CMOS
Multipart
Video RAM
9-147
SMJ44C251A-10t
S MJ44C251 A-1 t
SMJ44C251A-12t
SMJ44C251 A-2t
100
100
120
120
5± 10%
5±5%
5 ± 10%
5±5%
635
635
550
550
90
90
83
83
28,28
HJ, JD
Military
CMOS
Multipart
Video RAM
9-149
TMS44C260-60
TMS44C260-70
TMS44C260-80
TMS44C260-10
60
70
80
100
5± 10%
523
440
413
358
11
24/26
DJ
CMOS
Parity and
Enhanced
Page Mode
8-73
TMS4C1050-30
TMS4C1050-40
TMS4C1050-60
25
30
50
5± 10%
275
248
193
55
16,
20/26,20
N,
OJ, SO
CMOS
Field
Memory
8-125
TMS4C1060-30
TMS4C1060-40
TMS4C1060-60
25
30
50
5 ± 10%
275
248
193
55
16,
20/26,20
N,
DJ, SO
CMOS
Field
Memory
8-125
TMS4C1070-30t
TMS4C1070-40t
TMS4C1070-60;
25
30
50
5 ± 10%
275
248
193
55
18,
20/26,20
N,
OJ, SO
CMOS
Field
Memory
8-141
128K x 8
TMS48C121-80 t
TMS48C121-10t
TMS48C121-12t
80
100
120
5 ± 10%
660
523
468
193
193
165
40
OZ
CMOS
Mulitport
Video RAM
8-91
1024K x 4
TMS44460-60;
TMS44460-7ot
TMS44460-80;
TMS44460-10t
60
70
80
100
5 ± 10%
523
468
413
358
11
24/26
DJ
CMOS
Parity and
Enhanced
Page Mode
8-155
4096K
tN
Plastic Dual In-Line (DIP)
DJ Plastic Small-Outline J-Lead (SOJ)
DZ Plastic Small-Outline J-Lead (SOJ)
FM Plastic Leaded Chip Carrier
HJ Ceramic Small-Outline J-Lead (Military) (SOJ)
JD Ceramic Side-Brazed Dual In-Line Package (Military) (DIP)
SD Plastic Zig-Zag In-Line Package (ZIP)
; Advance Information for product under development by TI
TEXAS •
INSTRUMENTS
2-10
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Alternate Source Directory
"~:;~~~~~~~~~I
,
..
~,~~~~~~~~
.........•.
~~___________________________A_lt_e_rn_a_t_e_s_o_u_r_Ce__D_ir_e_c_to_r_y______~
..a:~~~~~~~~~~~
. .~<~~~~~~~~~~
Alternate Source Directory
DRAM
VENDOR
ORGANIZATION
PART NUMBER
TI
256K x 4
ALTERNATE SOURCES
TMS44C256
TI
Enhanced Page Mode
AT&T
M441024
Fujitsu
Hitachi
HM514256/8
Hyundai
Micron
Mitsubishi
Motorola
NEC
NMB
OKI
Panasonic
Samsung
Sharp
Siemens
Toshiba
256K x 4
Military
TI
Micron
MB81C4256
HY51C4256
MT4C4256/MT4C4258
M5M44C256
MCM514256A
f.lPD424256
AAA1M104
MSM414256/MSM514256
MN41C4256
KM44C256
LH64256/270
HYB514256
TC514256
SMJ44C256
MT4C4256
Enhanced Page Mode
1 Meg x 1
TI
TMS4C1024
Enhanced Page Mode
Fujitsu
MB81C1000
Goldstar
Hitachi
GM71C1000
Hyundai
Micron
Mitsubishi
Mosaic
NEC
OKI
Panasonic
Toshiba
Vitelic
1 Meg x 1
Military
TI
HM511000
HY5iC1000
MT4C1024/5/6
M5M4C1000
MDM11000
f.lPD421 000
MSM41000
MN41C1000
TC511000
V56C100
SMJ4C1024
Micron
MT4C1024
Enhanced Page Mode
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
3-1
Alternate Source Directory
DRAM (Continued)
VENDOR
ORGANIZATION
I
1 Meg x 1
Nibble Mode
TI
1 Meg x 1
Static Column
Decode Mode
TI
1 Meg x 4
Enhanced Page Mode
t
PART NUMBER
TI
ALTERNATE SOURCES
Dense-Pac
Hitachi
Hyundai
Micron
Mitsubishi
Motorola
NEC
NMB
OKI
Samsung
Toshiba
JAPD421 002
AAA1M100
MSM41002
KM41C1002
HYB511002
TC511002
Fujitsu
Hitachi
Micron
Mitsubishi
Mosaic
Motorola
NEC
NMB
OKI
Panasonic
Samsung
Siemens
Toshiba
TMS44400
TMS44410 (write-per-bit)
MB814400
HM514400
MT4C4001 /003
M5M44400
MDM41000
MCMS14400
JAPD424400
AAA4M104
MSM514400
MN41C41000
KM44C1000
HYB514400
TC514400
TI
TI
Product under development by TI
TEXAS ~
POST OFFICE BOX 1443
TMS4C1027
MB81C1002
HM511002
MT4C1026
M5M4C1002
MCM511002
Fujitsu
Hitachi
Micron
Mitsubishi
Motorola
NEC
NMB
OKI
Samsung
Siemens
Toshiba
INSTRUMENTS
3-2
TMS4C1025
DPD1MM1K
HM511001
HY51C1001
MT4C1025
M5M4C1001
MCM511001
JADP421001
AAA1M200
MSM41001
KM41C1001
TC511001
•
HOUSTON, TEXAS 77001
Alternate Source Directory
DRAM (Concluded)
VENDOR
ORGANIZATION
PART NUMBER
TI
1 Meg x 4
Military
Enhanced Page Mode
TI
4 Meg x 1
Enhanced Page Mode
TI
4 Meg x 1
ALTERNATE SOURCES
SMJ44400t
Micron
Dense-Pac
Fujitsu
Hitachi
Micron
Mitsuibishi
Mosaic
Motorola
NEC
NMB
OKI
Panasonic
Samsung
Siemens
Toshiba
Micron
TI
Mitsubishi
NEC
OKI
4 Meg x 4
Enhanced Page Mode
TI
16 Meg x 1
Enhanced Page Mode
TI
TMS44100
DPD4MM1K
MB814100
HM514100
MT4C1004/5/6
M5M44100
MDM14000
MCM514100
mPD424100
AAA4M100
MSM514100
MN41C4000
KM41 C4000/44C1 000
HYB514100
TC514100
SMJ44100t
TI
Military
Enhanced Page Mode
4 Meg x 1
Nibble Mode
MT4001
MT4C1004
TMS44101
M5M44101
flPQ424101
MSM5144101
Hitachi
TMS416400t
HM511640
Hitachi
TMS416100t
HM511610
t Product under development by TI
TEXAS . .
INSlRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
3-3
Alternate Source Directory
DRAM Modules
VENDOR
ORGANIZATION
256K x 9
PART NUMBER
TI
ALTERNATE SOURCES
TI
Fujitsu
Hitachi
Micron
OKI
1 Meg x 8
1 Meg x 8
1 Meg x 9
Dense-Pac
Fujitsu
Fujitsu
Hitachi
Micron
Mitsubishi
Motorola
NEC
OKI
Samsung
Toshiba
·TM024GAD8
DPD1MX8
M 885230/M 8855231
M885250
H856A181/H856C18
MT8C8024/25/26
MH1M08A
MCM81000
MC-421000A8
MSC2313A
KMM581000
THM81000
Dense-Pac
Fujitsu
Fujitsu
Hitachi
Micron
Mitsubishi
Motorola
NEC
OKI
Samsung
Toshiba
TM124GU8A
DPD1MX8
M 885230/M8855231
M885250
H856A181/H856C18
MT8C8024/25/26
MH1M08A
MCM81000
MC-421000A8
MSC2313A
KMM581000
THM81000
Dense-Pac
Fujitsu
Fujitsu
Hitachi
Micron
Mitsubishi
Motorola
Samsung
Siemens
Toshiba
TM024EAD9
DPD1MX9
M885235/M885237
M885265
H856A19/H856C19
MT8C9024/25/26
MH1M09A
MCM9L1000
KMM591000
HYM91 0005
THM91000
TI
TI
TI
TEXAS ~
INSlRUMENTS
3·4
POST OFFICE BOX 1443
TM256GU9
M885240
H8561003/H8561409
MT9259/MT8C9259
MSC2304YS9
•
HOUSTON, TEXAS 77001
Alternate Source Directory
DRAM Modules (Continued)
VENDOR
ORGANIZATION
1 Meg x 9
PART NUMBER
TI
ALTERNATE SOURCES
TI
Dense-Pac
Fujitsu
Fujitsu
Hitachi
Micron
Mitsubishi
Motorola
NEC
OKI
Samsung
Toshiba
1 Meg x 9
4 Meg x 8
4 Meg x 9
TI
TM124EAD9C
DPD1MX9
M B85235/M B85237
MB85265
HB56A 19/H856C19
MT8C9024/25/26
MH1M09A
MCM9L1000
MC-421000A9
Dense-Pac
Fujitsu
Fujitsu
Hitachi
Micron
Mitsubishi
Motorola
NEC
OKI
Samsung
Siemens
Toshiba
MSC2312
KMM591000
HYM910005
THM91000
Dense-Pac
Hitachi
TM4100GBD8
DPD4MX8
HB56A48A
TI
TI
Dense-Pac
Hitachi
NEC
OKI
Siemens
256K x 36
TM124EAD98
DPD1MX8
M B85230/M B855231
MB85250
HB56A181/HB56C18
MT8C8024/25/26
MH1M08A
MCM81000
MC-421000A9
MSC2312
KMM581000
THM81000
TI
TI
Hitachi
Micron
NEC
OKI
Samsung
Toshiba
Vitelic
TEXAS
TM4100EBD9
DPD4MX9
HB56A49A
MC-424100A9
MSC2340
HYM940005
TM256KBK36B
TM256KBK36C
HB56D25636
MT8C36256
MC-424256A36
MSC2320A
KMM36256
THM3625600A
VM55C104K36
-1!1
INSlRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
3-5
Alternate Source Directory
DRAM Modules (Concluded)
VENDOR
ORGANIZATION
512K x 36
PART NUMBER
TI
ALTERNATE SOURCES
Toshiba
Vitelic
TM512LBK36B
TM512LBK36C
HB56D51236
MT8C36512
MC-424512A36
MSC2321A
KMM36512
THM365120AS
VM55C1042K36
Hitachi
NEC
TM124MBK36A
TM124MBK36B
HB56D136B
MC-421000A36
TI
TI
Hitachi
Micron
NEC
OKI
Samsung
1 Meg x 36
TI
TI
TEXAS ~
INSTRUMENTS
3-6
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Alternate Source Directory
EPROMs/OTPs/Flash EEPROMs
VENDOR
ORGANIZATION
PART NUMBER
TI
16Kx 8
CMOS
ALTERNATE SOURCES
TMS27C128
TI
TI
TMS27PC128
AMD
AM27C128
Atmel
Cypress
AT27C128
CY7C251
Fujitsu
GI
Intel
Hitachi
Microchip
Mitsubishi
National
NEC
OKI
S-MOS
SEEO
Sharp
Toshiba
VLSI
VTI
Waferscale
16Kx 8
Military
CMOS
TI
AMD
Intel
Microchip
SEEO
MBM27C128/MBM27128
27C128
27C128
HN27128NHN4827128G
27HC256
M5L27128/M5M27C128
NMC27CP128
mPD27128
MSM27128/MSM27C128
SPM27129C
27128
LH57126/7/8
TMM27128
VT27C128
VT27C128
WS57C128F/VVS57C251
SMJ27C128
AM27128
MD27128A
27C128
27128
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
3-7
Alternate Source Directory
EPROMs/OTPs/Flash EEPROMs (Continued)
VENDOR
ORGANIZATION
32Kx 8
CMOS
PART NUMBER
TI
ALTERNATE SOURCES
TI
TI
AMD
Atmel
Catalyst
Cypress
Fujitsu
Hitachi
GI
Intel
Microchip
Mitsubishi
Motorola
National
NEC
OKI
Panatech
S-MOS
SEEO
SGS
Sharp
Signetics
Thomson
Toshiba
Waferscale
32K x. 8
Military
CMOS
TI
32K x8
Flash EEPROM
TI
TI
TI
AMD
Atmel
Intel
Microchip
SEEO
Signetics
AMD
Intel
TEXAS ~
INSTRUMENTS
3-8
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS27C256
TMS27PC256
Am27C256/Am27256
AT27C256/AT27256
CAT27HC256
CY7C271/4/7/9
M BM27C256/M BM27256
HN27C256/HN27256
27C256/27256
27256/27C25?
27C256
M5M27C256/M5L27256
MCM67256/9
NMC27C256
mPD27256
MSM27C256/MSM27256
RD27C256
SPM27C256
27C256
M27256A
LH57254/5/6
27C256
TS27C256
TMM27256/TC57256/54256
WS57C256F
SMJ27C256
Am27256
AT27C256
MD27256/27C256
27C256
DM27256/27C256
27C256
TMS29F256 (5-V EEPROM)
TMS29F258 (5-V EEPROM)
TMS29F259 (5-V EEPROM)
Am28F256
28F256 (12-V EPROM)
Alternate Source Directory
EPROMs/OTPs/Flash EEPROMs (Continued)
VENDOR
ORGANIZATION
TI
64Kx 8
CMOS
ALTERNATE SOURCES
TI
TI
TMS27C512
TI
TI
TMS27C510t
TMS27PC510t
TMS27PC512
AMD
Atmel
Catalyst
Am27512/Am27C512
AT27C512
CAT27512
Cypress
Fujitsu
CY7C285/6/7/9
MBM27C512
GI
Hitachi
Intel
Mitsubishi
64Kx 8
Military
PART NUMBER
NEC
OKI
Panatech
Toshiba
mPD27C512
MSM27512
SMJ27C512
Am27512
Atmel
AT27C512
Microchip
TI
TI
TMS27C512
TMM27512/TC57512/54512
AMD
Intel
64K x 16
CMOS
M5L27512
NMC27C512
CMOS
TI
HN27512
27C512
National
TI
64Kx 8
Flash EEPROM
27C512
AMD
Intel
National
MD27512
27C512
TMS29F512t
Am28F512
28F512 (12-V EPROM)
NMC48F512
TMS27C210A
TMS27PC210A
AMD
Atmel
Catalyst
Fujitsu
Hitachi
Intel
Microchip
National
NEC
Am27C1024
AT27C1024
CAT27C210
MBM27C1024
HN27C1024
27C210
27HC1616
NMC27C1024
mPD27C1000
OKI
SGS
Toshiba
TC571 024
Waferscale
WS27C210
MSM271 024/MSM27C1 024
M27C1024
t Product under development by TI
TEXAS •
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
3-9
Alternate Source Directory
EPROMs/OTPs/Flash EEPROMs (Concluded)
VENDOR
ORGANIZATION
TI
64K x 16
Military
CMOS
TI
128K x 8
CMOS
TI
TI
ALTERNATE SOURCES
Atmel
AMD
Atmel
Catalyst
Dense-Pac
Fujitsu
Hitachi
Intel
Mosaic
Mitsubishi
NEC
National
OKI
SGS
Sharp
Toshiba
Waferscale
128Kx 8
Military
CMOS
TI
128Kx 8
CMOS
Flash EEPROM
TI
256Kx 8
CMOS
TI
512Kx 8
CMOS
TI
TI
256K x 16
CMOS
AMD
Atmel
TMS27C010A
TMS27PC010A
Am27C010
AT27C010
CAT27010
DPV27C101
MBM27C1000/1
HN27C101/301
27C010
MLM8128
M5M27C100/1/2
J.lPD27C1000
NMC27C010/020
MCM271000
M27C1011
LH571 000/0001
TC571 000/TC541 00
WS27C010
SMJ27C010
Am27C010
AT27C010
TMS29F010t
Am28F010
CAT28F010
HN29C101
28F010 (12-V EPROM) .
28C010
48F010
AMD
Intel
Mitsubishi
National
TMS27C020t
Am27C020/2048
27C020
M5M27C201/2
NMC27020
AMD
Intel
Mitsubishi
National
Toshiba
TMS27C040t
TMS27PC040t
Am27C040
27C040
M5M27C402
NMC27040
TC57400
AMD
Hitachi
TMS27C240t
TMS27PC240t
Am27C04096
HN27C4096
TI
TI
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
SMJ27C210
AT27C1024
AMD
Catalyst
Hitachi
Intel
SEEQ
Signetics
t Product under development by TI
3-10
PART NUMBER
•
HOUSTON, TEXAS 77001
Alternate Source Directory
Application Specific Memories
VENDOR
ORGANIZATION
256K x 4
Video RAM
TI
ALTERNATE SOURCES
TI
TI
. Fujitsu
Hitachi
NEC
Micron
Mitsubishi
OKI
Samsung
Toshiba
256K x 4
Military
Video RAM
TI
128K x 8
Video RAM
TI
TMS44C250
TMS44C251
MB81 C4251/MB81 C4253
HM534251/2/3
f.lPD42274
MT42C4256
M5M442256
MSM514251/MSM514252
KM42C4256
TC524256/TC524257
SMJ44C250t
SMJ44C251t
TI
TI
TI
256K x 4
Parity
PART NUMBER
Micron
SMJ44C251At
MT42C4256 883C
Micron
TMS44C260
MT4C1664
Hitachi
Micron
Mitsubishi
NEC
Toshiba
TMS48C121t
HM538121/2/3
MT42C8128
N5N482128
f.lPD424400
TC528126A
t Product under development by TI
TEXAS ~
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
3-11
Alternate Source Directory
TEXAS •
INSTRUMENTS
3·12
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Glossaryrriming Conventions/Data Sheet Structure
GlossaryfTiming Conventions/Data Sheet Structure
Glossary/Timing Conventions/Data Sheet Structure
GENERAL CONCEPTS AND TYPES OF MEMORIES
Address - Any given memory location in which data can be stored or from which it can be retrieved.
Automatic Chip-Select/Power Down - see Chip Enable Input.
Bit - Contraction of Binary digiT; i.e., a 1 or a O. In electrical terms, the value of a bit may be represented by the presence or absence of charge, voltage, or current.
Byte - A word of 8 bits (see Word).
C of C - Certification of Conformance.
CDIP - Ceramic Dual In-Line Package.
CERPAC - CERamic flat PACk (hermetic).
CMOS -A complementary MaS technology that uses transisitors with electron (N-channel) and hole (P-channel) conduction.
Chip Enable Input - A control inputto an integrated circuitthat, when active, permits operation of the integrated circuit
for input, internal transfer, manipulation, refreshing, and/or output of data and, when inactive, causes the integrated
circuit to be in a reduced-power standby mode.
Chip Select Input - Chip select inputs are gating inputs that control the input to and output from the memory. They
may be of two kinds:
1.
Synchronous - Clocked/latched with the memory clock. Affects the inputs and outputs for the duration
of that memory cycle.
2.
Asynchronous - Has direct asynchronous control of inputs and outputs. In the read mode, an asynchronous chip select functions like an output enable.
Column Address Strobe (CAS) - A clock used in dynamic RAMs to control the input of column addresses. It .can
be active high (CAS) or active low (CAS).
CPAK - Ceramic flatPAcK.
CSOJ - Ceramic Small-Outline J-Iead integrated circuit package.
CZIP - Ceramic Zig-zag In-line Package.
Data - Any information stored or retrieved from a memory device.
Die - Unpackaged semiconductor.
DIP - Dual In-line Package.
DESC - Defense Electronics Supply Center.
Dynamic (Read/Write) Memory (DRAM) - A read/write memory in which the cells require the repetitive application
of control signals in order to retain the stored data.
NOTES:
1. The words "read/write" may be omitted from the term when no misunderstanding will result.
2.
Such repetitive application of the control signals is normally called a refresh operation.
3.
A dynamic memory may use static addressing or sensing circuits.
4.
This definition applies whether the control signals are generated inside or outside the integrated circuit.
TEXAS ~
INSlRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
4-1
Glossary/Timing Conventions/Data Sheet Structure
Electrically Erasable Programmable Read-Only Memory (EEPROM) - A nonvolatile memory that can be field-programmed like an OTP PROM or EPROM but that can be electrically erased by a combination of electrical signals
at its inputs.
EPIC - Enhanced Performance Implanted CMOS.
Erasable and Programmable Read-Only Memory (EPROM) - A field-programmable read-only memory that can
have the data content of each memory cell altered more than once.
Erase - Typically associated with EPROMs and EEPROMs. The procedure whereby programmed data is removed
and the device returns to its unprogrammed state.
ESD - Electrostatic Discharge.
Field Memory (FMEM) - A serial-access memory that performs high-speed, asynchronous read/write operations.
(Used mainly for fields of digital TVNTR that require higher speed operation, lower power consumption, and larger
capacity.)
Fit - Originally stood for Failures-In-Time. Currently means a failure rate of one failure in one billion hours.
FRAM - First-in first-out pseudo-static RAM or Field RAM.
Field-Programmable Read-Only Memory - See One-Time Programmable Read-Only Memory.
Fixed Memory-A common term for ROMs, EPROMs, EEPROMs, etc., containing data that is not normally changed.
A more precise term for EPROMs and EEPROMs is nonvolatile since their data may be easily changed.
Fully Static RAM -In a fully static RAM, the periphery as well as the memory array is fully static. The periphery is
thus always active and ready to respond to input changes without the need of clocks. There is no precharge required for static periphery.
GENERIC DATA - Group A, B, C, & D Quality Conformance Data.
JAN - Joint Army Navy. Specifically, a JM3851 0 qualified device.
JANB - Class B screened JAN device.
JANS - Class S screened JAN device.
JEDEC - Joint Electronic Device Engineering Council.
JTAG - Joint Testability Action Group.
K - When used in the context of specifying a given number of bits of information, 1K
64K = 64 x 1024 = 65 536 bits.
=21°= 1024 bits. Thus,
Large-Scale Integration (LSI) - The description of any IC technology that enables condensing more than 100 gates
onto a single chip.
.
LDCC - Ceramic Leaded Chip Carrier.
LCCC - Leadless Ceramic Chip Carrier.
Mask-Programmed Read-Only Memory - A read-only memory in which the data content of each cell is determined
during manufacture by the use of a mask, the data content thereafter being unalterable.
Memory - A medium capable of storing information that can be retrieved.
Memory Card - A pocket-size memory storage system.
TEXAS •
INSTRUMENTS
4-2
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Glossary/Timing Conventions/Data Sheet Structure
Memory Cell- The smallest subdivision of a memory into which a unit of data has been or can be entered in which
it is or can be stored, and from which it can be retrieved.
Metal-Oxide Semiconductor (MOS) - The technology involving photolithographic layering of metal and oxide to produce a semiconductor device.
MIL-M-38S10 - A military controlling specification pertaining mainly to JAN qualified devices (microcircuits).
MIL-STD-883 - A military controlling specification containing detailed descriptions of the screening processes pertaining to Class B and Class S devices (microcircuits).
NMOS - A type of MOS technology in which the basic conduction mechanism is governed by electrons. (Short for
N-channel MOS.)
Nonvolatile Memory - A memory in which the data content is maintained whether the power supply is connected
or not.
OTP - One-Time Programmable.
One-Time Programmable (OTP) Read-Only Memory - A read-only memory that, after being manufactured, can
have the data content of each memory cell altered once. Also referred to as OTP.
Output Enable - A control input that, when true, permits data to appear at the memory output, and when false, causes
the output to assume a high-impedance state. (See also chip select.)
PDIP - Plastic Dual-ln-Iine Package.
PLCC - Plastic Leaded Chip Carrier.
PMOS - A type of MOS technology in which the basic conduction mechanism is governed by holes. (Short for
P-channel MOS.)
Parallel Access - A feature of a memory by which all the bits of a byte or word are entered simultaneously at several
inputs or retrieved simultaneously from several outputs.
Power Down - A mode of a memory during which the device is operating in a low-power or standby mode. Normally
read or write operations of the memory are not possible under this condition.
Program - Typically associated with EPROM and OTP memories, the procedure whereby logical Os (or 1s) are stored
into various desired locations in a previously erased device.
Program Enable - An input signal that, when true, puts a programmable memory device into the program mode.
Programmable Read-Only Memory (PROM) - See One-Time Programmable (OTP) Read-Only Memory.
Printed Wiring Board (PWB) - A substrate of epoxy glass, clad material, or other material upon which a pattern of
conductive traces is formed to interconnect the components that will be mounted upon it.
Read - A memory operation whereby data is output from a desired address location.
Read-Only Memory (ROM) - A memory in which the contents are not intended to be altered during normal operation.
NOTE: Unless otherwise qualified, the term "read-only memory" implies that the contents are determined by its
structure and are unalterable.
Read/Write Memory - A memory in which each cell may be selected by applying appropriate electrical input signals
and the stored data may be either (a) sensed at appropriate output terminals, or (b) changed in response to other
similar electrical input signals.
Row Address Strobe (RAS) - A clock used in dynamic RAMs to control the input of the row addresses. It can be
active high (RAS) or active low (RAS).
TEXAS •
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
4-3
Glossary/Timing Conventions/Data Sheet Structure
SCD - Source Control Drawings.
Scaled-MOS (SMOS) - MOS technology under which the device is scaled down in size in three dimensions and in
operating voltages allowing improved performance.
Semi-Static (Quasi-Static, Pseudo-Static) RAM - In a semi-static RAM, the periphery is clock-activated (Le.,
dynamic). Thus the periphery is inactive until clocked, and only one memory cycle is permitted per clock. The peripheral circuitry must be allowed to reset after each active memory cycle for a minimum precharge time. No refresh
is required.
Serial Access - A feature of a memory by which all the bits are entered sequentially at a single input or retrieved
sequentially from a single output.
SIP - Single In-line Package.
Small Outline Integrated Circuit (SOIC) - A package in which an integrated circuit chip can be mounted to form
a surface-mounted component. It is made of a plastiC material that can withstand high temperatures and has leads
formed in a gull-wing shape along its two longer sides for connection to a PWB footprint.
SMD - Standard Military Drawing.
SOlCC - Small Outline Leadless ceramic Chip Carrier.
SOJ - Small Outline J-Iead package.
Static RAM (SRAM) - A read/write random-access device within which information is stored as latched voltage levels.
The memory cell is a static latch that retains data as long as power is applied to the memory array. No refresh is
required. The type of periphery circuitry sub-categorizes static RAMs.
ThlnSOJ - Thin Small-Outline J-Iead package.
ThlnSOP - Thin Small-Outline package.
Very-large-Scale Integration (VlSI) - The description of an IC technology that is much more complex than largescale integration (LSI) and involves a much higher equivalent gate count. At this time an exact definition including
a minimum gate count has not been standardized by JEDEC or the IEEE.
Video RAM (VRAM) - A dual-port dynamic random-access memory with a on-chip serial data register.
Volatile Memory - A memory in which the data content is .Iost when the power supply is disconnected.
Word - A series of one or more bits that occupy a given address location and then can be stored and retrieved in parallel.
Write -:- A memory operation whereby data is written into a desired address location.
Write Enable - A control signal that when true causes the memory to assume the write mode, and when false causes
it to assume the read mode.
ZIP - Zig-zag In-line Package.
TEXAS •
INSTRUMENTS
4-4
POST OFFICE BOX 1443
•
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Glossary/Timing Conventions/Data Sheet Structure
OPERATING CONDITIONS AND CHARACTERISTICS (INCLUDING LEITER SYMBOLS)
Capacitance
The inherent capacitance on every pin, which can vary with various inputs and outputs.
Example symbology:
Cj
Input capacitance
Co
Output capacitance
Cj(O)
Input capacitance, data input
Current
High-level input current, IIH
The current into an input when a high-level voltage is applied to that input.
High-level output current, 10H
The current into* an output with input conditions applied that according to the product specification will establish
a high level at the output.
Low-level input current, IlL
The current into an input when a lOW-level voltage is applied to that input.
LOW-level output current, 10L
The current into* an output with input conditions applied that according to the product specification will establish
a low level at the output.
Off-state (high-impedance state) output current (of a three-state output,) 10Z
The current into* an output having three-state capability with input conditions applied that according to the product
specification will establish the high-impedance state at the output.
Short-circuit output current, los
The current into* an output when the output is short-circuited to ground (or other specified potential) with input
conditions applied to establish the output logic level farthest from ground potential (or other specified potential).
Supply current, 188, Icc, 100, Ipp
The current into, respectively, the VBB, Vee, Voo, Vpp supply terminals.
*Current out of a terminal is given as a negative value.
Operating Free-Air Temperature
The temperature
(TN
range over which the device will operate and meet the specified electrical characteristics.
Voltage
High-level input voltage, VIH
An input voltage within the more positive (less negative) of the two ranges of values used to represent the binary
variables.
NOTE:
A minimum is specified that is the least positive value of high-level input voltage for which operation
of the logic element within specification limits is guaranteed.
TEXAS
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Glossary/Timing Conventions/Data Sheet Structure
High-level output voltage, VOH
The voltage at an output terminal with input conditions applied that according to the product specification will
establish a high level at the output.
Low-level Input voltage, VIL
An input voltage level within the less positive (more negative) of the two ranges of values used to represent the
binary variables.
NOTE:
A maximum is specified that is the most positive value of low-level input voltage for which operation
of the logic elment within specification limits is guaranteed.
Low-level output voltage, VOL
The voltage at an output terminal with input conditions applied that according to the product specification will
establish a low level at the output.
Supply voltages, Vee, Vee, Voo, Vpp
The voltages supplied to the corresponding voltage pins that are required for the device to function. From one
to four of these supplies may be necessary, along with ground VSS'
Time Intervals
New or revised data sheets in this book use letter symbols in accordance with standards recently adopted by
JEDEC, the IEEE, and the IEC. Two basic forms are used. The first form is usually used in this book when intervals
can easily be classified as access, cycle, disable, enable, hold, refresh, setup, transistion, or valid times and for
pulse durations. The second form can be used generally but in this book primarily for time intervals not easily classifiable. The second (unclassified) form will be described first. Since some manufacturers use this form for all time
intervals, symbols in the un-classified form are given with the examples for most of the classified time intervals.
Unclassified time Intervals
Generalized letter symbols can be used to identify almost any time interval without classifying it using traditional
or contrived definitions. Symbols for unclassified time intervals identify two signal events listed in from-to
sequence using the format:
tAB-CD
Subscripts A and C indicate the names of the signals for which changes of state or level or establishment of state
or level constitute signal events assumed to occur first and last, respectively, that is, at the beginning and end
of the time interval. E~ effort is made to keep the A and C subscript length down to one letter, if possible (e.g.,
R for RAS and C for CAS).
Subscripts Band 0 indicate the direction of the transitions and/or the final states or levels of the signals
represented by A and C, respectively. One or two of the following is used:
H
=high or transition to high
L = low or transition to low
V = a valid steady-state level
X
=unknown, changing, or "don't care" level
Z = high-impedance (off) state
The hyphen between the Band C subscripts is omitted when no confusion is likely to occur.
For examples of symbols of this type, see TMS44C256 (e.g., tRLCU'
TEXAS ."
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Glossary/Timing Conventions/Data Sheet Structure
Classified time intervals (general comments, specific times follow)
Because of the information contained in the definitions, frequently the identification of one or both of the two signal
events that begin and end the intervals can be significantly shortened compared to the unclassified forms. For
example, it is not necessary to indicate in the symbol that an access time ends with valid data at the output. However, if both signals are named (e.g., in a hold time), the from-to sequence is maintained.
Access time
The time interval between the application of a specific input pulse and the availability of valid signals at an output.
Example symbology:
Classifed
ta(A)
ta(S), ta(CS)
Cycle time
Description
Access time from address
Access time from chIp select (low)
Unclassified
tAVQV
tSLQV
The time interval between the start and end of a cycle.
NOTE:
The cycle time is the actual time interval between two signal events and is determined by the system
in which the digital circuit operates. A minimum value is spe~ified that is the shortest interval that must
be allowed for the digital circuit to perform a specified function (e.g., read, write, etc.) correctly.
Example symbology:
Unclassified
Description
Read cycle time
tc(R), tc(rd)
tAVAV(R)
Write cycle time
tc(W)
tAVAV(W)
NOTE: R is usually used as the abbreviation for "read"; however, in the case of dynamic memories, "rd" is used
to permit R to stand for RAS.
Classifed
Disable time (of a three-state output)
The time interval between the specified reference points on the input and output voltage waveforms, with the
three-state output changing from either of the defined active levels (high or low) to a high-impedance (off) state.
Example symbology:
Classifed
tdis(S)
tdis(W)
Unclassified
Description
tSHQZ
tWLQZ
Output disable time after chip select (high)
Output disable time after write enable (low)
These symbols supersede the older forms tpvz or tpxz.
Enable time (of a three-state output)
The time interval between the specified reference points on the input and output voltage waveforms, with the
three-state output changing from a high-impedance (off) state to either of the defined active levels (high or low).
NOTE:
For memories these intervals are often classified as access times.
Example symbology:
Classifed
Unclassified
Description
Output enable time after chip select low
tSLQV
ten(SL)
These symbols supersede the older from tpzv.
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Glossary/Timing Conventions/Data Sheet Structure
Hold time
The time interval during which a signal is retained at a specified input terminal after an active transition occurs
at another specified input terminal.
NOTES: 1. The hold time is the actual time interval between two signal events and is determined by the system
in which the digital circuit operates. A minimum value is specified that is the shortest interval for which
correct operation of the digital circuit is guaranteed.
2. The hold time may have a negative value in which case the minimum limit defines the longest interval
(between the release of the signal and the active transition) for which correct operation of the digital
circuit is guaranteed.
Example symbology:
Classifed
Unclassified
th(D)
tWHDX
tRHWH
th(RHrd)
tCHWH
th(CHrd)
tCL-CAX
th(CLCA)
tRL-CAX
th(RLCA)
th(RA)
tRL-RAX
These last three symbols supersede the older forms:
NEW FORM
Description
Data hold time (after write high)
Read (write enable high) hold time after RAS high
Read (write enable high) hold time after CAS high
Column address hold time after CAS low
Column address hold time after RAS low
Row address hold time (after RAS low)
OLD FORM
th(CLCA)
th(AC)
th(RLCA)
th(ARL)
th(RA)
th(AR)
NOTE: The from-to sequence in the order of subscripts in the unclassified form is maintained in the classified
form. In the case of hold times, this causes the order to seem reversed from what would be suggested
by the terms.
Pulse duration (width)
The time interval between the specified reference points on the leading and trailing edges. of the pulse waveform.
Example symbology:
Classifed
tw(W)
tw(RL)
Refresh time interval
Description
Write pulse duration
Pulse duration, RAS low
Unclassified
tWLWH
tRLRH
The time interval between the beginnings of successive signals that are intended to restore the level in a dynamic
memory cell to its original level.
NOTE:
The refresh time interval is the actual time interval between two refresh operations and is determined
by the system in which the digital circuit operates. A maximum value is specified that is the longest
interval for which correct operation of the digital circuit is guaranteed.
Example symbology:
Classifed
Description
Refresh time interval
Unclassified
trf
TEXAS ~
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Glossary/Timing Conventions/Data Sheet Structure
Setup time
The time interval between the application of a signal at a specified input terminal and a subsequent active
transition at another specified input terminal.
NOTES: 1. The setup time is the actual time interval between two signal events and is determined by the system
in which the digital circuit operates. A minimum value is specified that is the shortest interval for which
correct operation of the digital circuit is guaranteed.
2. The setup time may have a negative value in which case the minimum limit defines the longest interval (between the active transition and the application of the other signal) for which correct operation
of the digital circuit is guaranteed.
Example symbology:
Classifed
Description
Unclassified
tsu(D)
tDVWH
Data setup time (before write high)
tsu(CA)
tCAV-CL
Column address setup time (before CAS low)
Row address setup time (before RAS low)
tsu(RA)
tRAV-RL
Transition times (also called rise and fall times)
The time interval between two reference pOints (10% and 90% unless otherwise specified) on the same waveform
that is changing from the defined low level to the defined high level (rise time) or from the defined high level to
the defined low level (fall time).
Example symbology:
Classifed
Unclassified
Description
Transition time (general)
tt
tt(CH)
tr(C)
tf(C)
Valid time
(a)
(b)
tCHCH
Low-to-high transition time of CAS
tCHCH
tCLCL
CAS rise time
CAS fall time
General
The time interval during which a signal is (or should be) valid.
Output data-valid time
The time interval in which output data continues to be valid following a change of input conditions that could
cause the output data to change at the end of the interval.
Example symbology:
Classified
tv (A)
Unclassified
Description
Output data valid time after change of address
tAXQX
This supersedes the older form tpVX.
TEXAS ~
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4-9
Glossary/Timing Conventions/Data Sheet Structure
TIMING DIAGRAMS CONVENTIONS
Meaning
Timing Diagram Symbol
\\\\\
/11//
Input Forcing Functions
Output Response Functions
Must be steady high or low
Will be steady high or low
High-to-Iow changes permitted
Will be changing from high to low sometime
during designated intervals
Low-to-high changes permitted
Will be changing from low to high sometime
during designated intervals
Don't care
State unknown or changing
(Does not apply)
Centerline represents high-impedance
(off) state.
BASIC DATA SHEET STRUCTURE
The front page of the data sheet begins with a list of key features such as organization, interface, compatibility, operation (static or dynamic), access and cycle times, technology (N- or P-channel, silicon or metal oxide gate), and power.
In addition, the top view of the device is shown with the pinout provided. Next a general description of the device, system interface conSiderations, and elaboration on other device characteristics are presented. The next section is an
explanation of the device's operation which includes the function of each pin (Le., the relationship between each input
(output) and a given type of memory). The functions basically involve starting, achieving, and ending a given type of
memory cycle (e.g., programming or erasing EPROMs, or reading a memory location).
Augmenting the descriptive text there appears a logic symbol prepared in accordance with ANSI/IEEE Std 91-1984
and I EC Publication 617-12 and explained in Section 11 of t~is book. Following the symbol is usually a functional block
diagram, a flowchart of the basic internal structure of the device showing the signal paths for data, addresses, and
control Signals, as well as the internal architecture. Usually the next few pages contain the absolute maximum ratings
(e.g., voltage supplies, input voltage, and temperature) applicable over the operating free-air temperature range. If
the device is used outside of these values, it may be permanently destroyed or at least it would not function as intended. Next, typically, are the recommended operating conditions, (e.g., supply voltages, input voltages, and operating temperature). The memory device is guaranteed to work reliably and to meet all data sheet parameters when operated in accord with the recommended operating conditions and within the specified timing. If the device is operated
outside of these limits (minimum/maximum), it is no longer guaranteed to meet the data sheet parameters. Operation
beyond the absolute maximum ratings can result in catastrophic failures.
The next section provides a table of electrical characteristics over full ranges of recommended operating conditions
(e.g., input and output currents, output voltages, etc.). These are presented as minimum, typical, and maximum values. Typical values are representative of operation at an ambient temperature of T A = 25° C with all power supply
voltages at nominal value. Next, input and output capacitances are presented. Each pin has a capacitance (whether
an input, an output, or control pin). Minimum capacitances are not given, as the typical and maximum values are the
most crucial.
TEXAS ~
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Glossary/Timing Conventions/Data Sheet Structure
The next few tables involve the device timing characteristics. The parameters are presented as minimum, typical (or
nominal), and maximum. The timing requirements over recommended ranges of supply voltage and operating free-air
temperature indicate the device control requirements such as hold times, setup times, and transition times. These
values are referenced to the relative positioning of signals on the timing diagrams, which follow. The switching characteristics over recommended supply voltage range are device performance characteristics inherent to device operation
once the inputs are applied. These parameters are guaranteed for the test conditions given. The interrelation,ship of
the timing requirements to the switching characteristics is illustrated in timing diagrams for each type of memory cycle
(e.g., read, write, program.)
At the end of a data sheet additional applications information may be provided such as how to use the device, graphs
of electrical characteristics, or other data on electrical characteristics.
TEXAS "JI
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4-11
Glossary/Timing Conventions/Data Sheet Structure
TEXAS
l!I
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Dynamic RAMs
Dynamic RAMs
TMS44C256
262 144-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C -
DQ1
DQ2
• 262 144 x 4 Organization
TF
WRITE
AO
A1
A2
A3
CYCLE
VCC
• Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME
OR
TMS44C256-60
TMS44C256-70
TMS44C256-80
TMS44C256-10
TMS44C256-12
DQ4
DQ3
CAS
G
A8
A7
A6
A5
A4
W
ta(CA)
(tCAN
(MAX)
30 ns
35 ns
40 ns
45 ns
55 ns
SD Package
(Top View)
VSS
RAS
• Single 5-V Supply (10% Tolerance)
ta(C)
(tCAC)
(MAX)
15 ns
18 ns
20 ns
25 ns
30 ns
REVISED NOVEMBER 1990
N Package
(Top View)
This data sheet is applicable to al/
TMS44C256s symbolized with Revision "0"
and subsequent revisions as described
on page 5-21.
ta(R)
(tRAC)
(MAX)
60 ns
70 ns
80 ns
100 ns
120 ns
JUNE 1986 -
(MIN)
110 ns
130 ns
150 ns
180 ns
220 ns
G
DQ3
CAS
DQ4
DQ1
VSS
DQ2
RAS
AO
A2
W
TF
A1
A3
A4
A6
A8
VCC
A5
A7
DJ and DN Packages t
(Top View)
DQ1
DQ2
• Enhanced Page Mode Operation with
CAS-Before-RAS Refresh
W
RAS
VSS
DQ4
DQ3
CAS
TF
OE
AO
A1
A2
A3
A8
A7
A6
A5
A4
• Long Refresh Period ...
512-Cycle Refresh in 8 ms (Max)
• 3-State Unlatched Output
• Low Power Dissipation
• Texas Instruments EPIC™ CMOS Process
VCC
tThe packages shown here are for pinout reference only.
The OJ package is actually 75% of the length of the N
package.
• All Inputs and Clocks Are TTL Compatible
• High-Reliability Plastic 20-Pin 300-Mil-Wide
DIP, 20/26 J-Lead Surface Mount (SOJ)
('44C256-60 and '44C256-70 Available in
SOJ Only), 20/26 J-Lead Thin Surface
Mount (ThinSOJ), or 20-Pin Zig-Zag In-Line
(ZIP) Packages
PIN NOMENCLATURE
AO-AS
CAS
DQ1-DQ4
G
• Operation of TI's Megabit CMOS DRAMs
Can Be Controlled by TI's SN74ALS6301
and SN74ALS6302 Dynamic RAM
Controllers
RAS
TF
W
VCC
VSS
Address Inputs
Column-Address Strobe
Data In/Data Out
Data-Output Enable
Row-Address Strobe
Test Function
Write Enable
5-V Supply
Ground
• Operating Free-Air Temperature
... O°C to 70°C
description
The TMS44C256 series are high-speed, 1 048 576-bit dynamic random access memories, organized as
262 144 words of four bits each. They employ state-of-the-art EPIC ™ (Enhanced Process Implanted CMOS)
technology for high performance, reliability, and low power at low cost.
EPIC is a trademark of Texas Instruments Incorporated
PRODUCTION DATA documents contain Information current
as of publication date. Products conform to specifications per
the terms of Texas Instruments standard warranty. Production
processing does not necessarily Include testing of all
parameters.
TEXAS
"J1
Copyright © 1990. Texas Instruments Incorporated
INSTRUMENTS
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5-1
TMS44C256
262 144-WORD BY 4-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C -
JUNE 1986 - REVISED NOVEMBER 1990
description (continued)
These devices feature maximum RAS access times of 60 ns, 70 ns, SO ns, 100 ns, and 120 ns. Maximum power
dissipation is as low as 305 mW operating and 11 mW standby on 120 ns devices.
The EPIC technology permits operation from a single 5-V supply, reducing system power supply and decoupling
requirements, and easing board layout. ICC peaks are 140 mA typical, and a - 1-V input voltage undershoot can
be tolerated, minimizing system noise considerations.
All inputs and outputs, including clocks, are compatible with Series 54/74 TIL. All addresses and data-in lines
are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS44C256 is offered in a 20-pin dual-in-line (N suffix) package, a 20-pin zig-zag in-line (SO suffix) package,
a 20/26 J-Iead plastic surface mount SOJ (OJ suffix), and a 20/26 J-Iead thin plastic surface mount SOJ
(ON suffix). The TMS44C256-60 and TMS44C256-70 are available in the 20/26 J-Iead plastic surface mount SOJ
(OJ suffix) only. These packages are guaranteed for operation from O°C'to 7.0°C.
operation
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is thus eliminated. The
maximum number of columns that may be accessed is determined by the maximum RAS low time and the CAS
page cycle time used. With minimum CAS page cycle time, all512 columns specified by column addresses AO
through AS can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS44C256 to operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as column address is valid rather than when
CAS transitions low. This performance improvement is referred to as "enhanced page mode." Valid column
address may be presented immediately after th(RA) (row address hold time) has been satisfied, usually well in
advance of the falling edge of CAS. In this case, data is obtained after ta(C) max (access time from CAS low),
if ta(CA) max (access time from column address) has been satisfied. In the event that column addresses for the
next page cycle are valid at the time CAS goes high, access time for the next cycle is determined by the later
occurrence of ta(C) or ta(CP) (access time from rising edge of CAS).
'address (AO through AS)
Eighteen address bits are required to decode 1 of 262 144 storage cell locations. Nine row-address bits are set
up on pins AO through AS and latched onto the chip by the row-address strobe (RAS). Then nine column-address
bits are set up on pins AO through AS and latched onto the chip by the column-address strobe (CAS). All
addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable in
- that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select activating the output
buffer, as well as latching the address bits into the column-address buffers.
write enable (W)
The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from the standard
TIL circuits without a pull-up resistor. The data input is disabled when the read mode is selected. When W goes
low prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle, permitting a
write operation with G grounded.
TEXAS •
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TMS44C256
262 144-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C -
JUNE 1986 -
REVISED NOVEMBER 1990
data in (001-004)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early write cycle, W is brought low prior to CAS and
the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or
read-modify-write cycle, CAS will already be low, thus the data will be strobed in by Wwith setup and hold times
referenced to this signal. In a delayed-write or read-modify-write cycle, G must be high to bring the output buffers
to high-impedance prior to impressing data on the I/O lines.
data out (001-004)
The three-state output buffer provides direct TTL compatibility (no pull-up resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS and G are brought low. In a read cycle the output becomes valid after the access time interval ta(C)
that begins with the negative transition of CAS as long as ta(R) and t a(C.6) are satisfied. Th~output becomes valid
after the access time has elapsed and remains valid while CAS and G are low. CAS or G going high returns it
to a high-impedance state. This is accomplished by bringing G high prior to applying data, thus satisfying td(GHD)'
output enable
(G)
G controls the impedance of the output buffers. When G is high, the buffers will remain in the high-impedance
state. Bringing G low during a normal cycle will activate the output buffers putting them in the low-impedance
state. It is necessary for both RAS and CAS to be brought low for the output buffers to go into the low-impedance
state. Once in the low-impedance state, they will remain in the low-impedance state until either G or CAS is
brought high.
refresh
A refresh operation must be performed at least once every eight milliseconds to retain data. This can be achieved
by strobing each of the 512 rows (AD-AS). A normal read or write cycle will refresh all bits in each row that is
selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, thus conserving power
as the output buffer remains in the high-impedance state. Externally generated addresses must be used for a
RAS-only refresh. Hidden refresh may be performed while maintaining valid data at the output pin. This is
accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period,
similar to a RAS-only refresh cycle.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS [see parametertd(CLRL)RJ and holding
it low after RAS falls [see parameter td(RLCH)RJ. For successive CAS-before-RAS refresh cycles, CAS can
remain low while cycling RAS. The external address is ignored and the refresh address is generated internally.
The external address is also ignored during the hidden refresh option.
power-up
To achieve proper device operation, an initial pause of 200 !!s followed by a minimum of eight initialization cycles
is required after power-up to the full VCC level.
test function pin
During normal device operation the TF pin must either be disconnected or biased at a voltage less than or equal
to VCC'
TEXAS
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5-3
TMS44C256
262 144-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C -
JUNE 1986 -
REVISED NOVEMBER 1990
logic symbol t
AO
A1
A2
A3
A4
AS
A6
A7
A8
RAM 256Kx4
2009/2100
6
7
8
9
11
12
13
14
15
262143
4~
17~
Vi
G
31
16 -
r-.....
OQ2 2
18
OQ3
19
OQ4
20017/2108
C20[ROW]
G23/[REFRESH ROW]
24[PWR OWN]
t> C21/[COLUMN]
G24
t>
&
~ 23C22
23,210
G25
24,25EN
r
~
1 _
OQ1
0
A
1......
....
....
....
A,220
V26
A,Z26--
~
~
~
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
Pin numbers shown are for the N package.
TEXAS . .
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1MS44C256
262 144-WORD 8Y 4-811
DYNAMIC
RANDOM-ACCESS MEMORY
SMGS256C - JUNE 1986 - REVISED NOVEMBER 1990
functional block diagram
~
~
.
....
I
->
Row
Address
Buffers
"J
(9)
256K 1 Row·1
Array
Decode
~
..l
- ...
AD
A1
A2
A3
A4
r
:..
.
...
A5
A6
A7
AS
~
~
Timing and Control
I
256K
Array
'"
;,.
Sense Amplifiers
Column
Address
Buffers
(9)
M
-.I
Column Decode
=!:=
=!:=
=!:=
-..-
~
Data
In
Reg
~
.,
I/O
Buffers
4 of S
Selection
4
r--+~l
r+r+-
Data
Out
Reg
~
...
~
~
4
Sense Amplifiers
256K 1 Row
Array
Decode
I
256K
Array
001-0 04
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee ............................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. Oae to 70 0 e
Storage temperature range ....................................................... - 65°e to 150 0 e
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
V
Vee
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
V
0
°e
70
Operating free-air temperature
0
TA
..
..
..
NOTE 2: The algebraic convention, where the more negative (less positive) limit IS designated as minimUm, IS used In thiS data sheet for logic
voltage levels only.
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5-5
TMS44C256
262 144-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C -
JUNE 1986 -
REVISED NOVEMBER 1990
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
TMS44C256-60
TEST CONDITIONS
PARAMETER
VOH
High-level output voltage
10H =-5 mA
VOL
Low-level output voltage
10L = 4.2 mA
II
Input current (leakage)
10
ICC1
MIN
MAX
TMS44C256-70
MIN
MAX
2.4
2.4
UNIT
V
0.4
0.4
V
VI = 0 to 5.8 V, VCC = 5 V, All other pins = 0 V to VCC
± 10
±10
f1A
Output current (leakage)
Vo = 0 V to VCC, VCC = 5.5 V, CAS high
±10
±10
f1A
Read/write cycle current
tc(rdWl = minimum, VCC = 5.5 V
95
80
mA
2
2
mA
ICC2
Standby current
After 1 memory cycle, RAS and CAS high, VIH = 2.4 V
ICC3
Average refresh circuit
(RAS-only, or CSR)
tgl&W) = minimum, VCC = ~V, RAS cycling, CAS high
(RAS-only), RAS low, after CAS low (CSR)
90
80
mA
ICC4
Average page current
tc(P) = minimum, VCC = 5.5 V, RAS low, CAS cycling
70
60
mA
TMS44C256-10
TMS44C256-12
TMS44C256-80
TEST
CONDITIONS
PARAMETER
VOH
High-level output voltage
10H =-5 mA
VOL
Low-level output voltage
10L = 4.2 mA
II
Input current (leakage)
10
ICC1
MIN
MAX
MIN
MAX
2.4
2.4
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
VI = 0 to 5.8 V, VCC = 5 V,
All other pins = 0 V to VCC
±10
± 10
±10
f1A
Output current (leakage)
Vo = OtoVCC,
VCC = 5.5 V, CAS high
±10
± 10
±10
f1A
Read/write cycle current
tc(rdWl = minimum, VCC = 5.5 V
75
65
55
mA
ICC2
Standby current
After 1 memory cycle,
RAS and CAS high, VIH = 2.4 V
2
2
2
mA
ICC3
Average refresh circuit
(RAS-only, or GSR)
!9.MW) = minimum, VCC = 5.5 V
RAS cycling, CAS high (RAS-only),
RAS low, after CAS low (GSR)
70
60
50
mA
ICC4
Average page current
50
45
35
mA
~ = minimum, VCG = 5.5 V,
RAS low, GAS cycling
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(RC)
Input capacitance, strobe inputs
5
pF
Ci(W)
Input capacitance, write-enable input
5
pF
Ci(G)
Input capacitance, output-enable input
5
pF
Co
Output capacitance
7
pF
NOTE 3: VCG equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
TEXAS
lJ1
INSTRUMENTS
5-6
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44C256
262 144-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C -
JUNE 1986 -
REVISED NOVEMBER 1990
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
ALT.
SYMBOL
PARAMETER
TMS44C256-60
MIN
MAX
TMS44C256-70
MIN
MAX
UNIT
ta(C)
Access time from CAS low
tCAC
15
18
ns
ta(CA)
Access time from column-address
tCM
30
35
ns
ta(R)
Access time from RAS low
tRAC
60
70
ns
ta(G)
Access time from Glow
tGAC
15
18
ns
ta(CP)
Access time from column precharge
tCAP
35
40
ns
td(CLZ)
CAS low to output in low Z
tCLl
0
tdis(CH)
Output disable time after CAS high (see Note 4)
tOFF
0
15
0
18
ns
tdis(G)
Output disable time after G high (see Note 4)
tGOFF
0
15
0
18
ns
ALT.
SYMBOL
PARAMETER
TMS44C256-80
MIN
MAX
TMS44C256-10
MIN
ns
0
MAX
TM544C256-12
MIN
MAX
UNIT
ta(C)
Access time from CAS low
tCAC
20
25
30
ta(CA)
Access time from column-address
tCM
40
45
55
ns
ta(R)
Access time from RAS low
tRAC
80
100
120
ns
ta(G)
Access time from Glow
tGAC
20
25
30
ns
ta(CP)
Access time from column precharge
tCAP
40
50
60
ns
td(CLZ)
CAS low to output in low Z
tCLl
0
tdis(CH)
Output disable time after CAS high (see Note 4)
tOFF
0
20
0
25
0
30
ns
tdis(G)
Output disable time after G high (see Note 4)
tGOFF
0
20
0
25
0
30
ns
ns
0
0
ns
NOTE 4: tdis(CH) and tdis(G) are specified when the output is no longer driven.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-7
TMS44C256
262 144-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C - JUNE 1986 - REVISED NOVEMBER 1990
timing requirements over recommended ranges of suppiy voltage and operating free-air
temperature (continued)
ALT.
SYMBOL
PARAMETER
TMS44C256-60
MIN
MAX
TMS44C256-70
MIN
UNIT
MAX
tc(rd)
Read cycle time (see Note 6)
tRC
110
130
ns
tc(W)
Write cycle time
twc
110
130
ns
tc(rdW)
Read-write/read-modify-write cycle time
tRWC
155
181
ns
tc(P)
Page-mode read or write cycle time (see Note 7)
tpc
40
45
ns
tc(PM)
Page-mode read-modify-write cycle time
tpCM
85
96
ns
tw(CH)
Pulse duration, CAS high
tcp
10
10
tw(CL)
Pulse duration, CAS low (see Note 8)
tCAS
15
tw(RH)
Pulse duration, RAS high (precharge)
tRP
40
tw(RL)
Non-page-mode pulse duration, RAS low (see Note 9)
tRAS
60
10000
100000
10000
18
ns
10000
ns
70
10000
ns
70
100000
ns
ns
50
tw(RL)P
Page-mode pulse duration, RAS low (see Note 9)
tRASP
60
tw(WL)
Write pulse duration
twp
15
15
ns
tsu(CA)
Column-address setup time before CAS low
tASC
0
0
ns
tsu(RA)
Row-address setup time before RAS low
tASR
0
0
ns
tsu(D)
Data setup time before W low (see Note 10)
tDS
0
0
ns
tsu(rd)
Read setup time before CAS low
tRCS
0
0
ns
tsu(WCL)
W-Iow setup time before CAS low (see Note 11)
twcs
0
0
ns
tsu(WCH)
W-Iow setup time before CAS high
tCWL
15
18
ns
tsu(WRH)
W-Iow setup time before RAS high
tRWL
15
18
ns
th(C~
Column-address hold time after RAS low
tCAH
10
15
ns
th(RA)
Row-address hold time after RAS low
tRAH
10
10
ns
tAR
50
55
ns
Column-address hold time after RAS low (see Note 12)
th(RLCA)
Continued next page.
NOTES: 5.
6.
7.
8.
9.
1O.
11.
12.
Timing measurements in this table me reierenced to VIL max and VIH min.
All cycle times assume tt = 5 ns.
To guarantee tc(P) min, tsu(CA) should be greater than or equal to tw(CH)'
In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. (Depending on the user's transition times, this may require
additional CAS low time [tw(CL)))'
In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. (Depending on the user's transition times, this may require
additional RAS I~ time [tw(RL)))'
Later of CAS or W in write operations.
Early write operation only.
The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
TEXAS •
INSTRUMENTS
5-8
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44C256
262 144-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C -
JUNE 1986 -
REVISED NOVEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
ALT.
SYMBOL
PARAMETER
TMS44C256·80
MIN
MAX
TMS44C256·10
MIN
MAX
TMS44C256·12
MIN
UNIT
MAX
ns
tc(rd)
Read cycle time (see Note 6)
tRC
150
180
220
tc(W)
Write cycle time
twc
150
180
220
ns
tc(rdW)
Read-write/read-modify-write cycle time
tRWC
205
245
295
ns
tc(P)
Page-mode read or write cycle time (see Note 7)
tc(PM)
Page-mode read-modify-write cycle time
tpc
50
55
65
ns
tpCM
100
120
135
ns
10
tw(CH)
Pulse duration, CAS high
tcp
10
tw(CL)
Pulse duration, CAS low (see Note 8)
tCAS
20
tw(RH)
Pulse duration, RAS high (precharge)
tRP
60
tw(RL)
Non-page-mode pulse duration, RAS low
(see Note 9)
tRAS
80
10000
100
10000
120
10000
ns
tw(RL)P
Page-mode pulse duration, RAS low (see Note 9)
100000
100
100000
120
100000
ns
tw(WL)
Write pulse duration
tRASP
twp
80
15
15
20
ns
tsu(CA)
Column-address setup time before CAS low
tASC
0
0
0
ns
tsu(RA)
Row-address setup time before RAS low
tASR
0
0
0
ns
tsu(D)
Data setup time before W low (see Note 10)
tDS
0
0
0
ns
tsu(rd)
Read setup time before CAS low
tRCS
0
0
0
ns
tsu(WCL)
W-Iow setup time before CAS low (see Note 11)
twcs
0
0
0
ns
tsu(WCH)
W-Iow setup time before CAS high
tCWL
20
25
30
ns
tsu(WRH)
W-Iow setup time before RAS high
tRWL
20
25
30
ns
th(CA)
Column-address hold time after RAS low
tCAH
15
20
20
ns
th(RA)
Row-address hold time after RAS low
tRAH
12
15
15
ns
tAR
60
70
80
ns
Column-address hold time after RAS low
th(RLCA)
(see Note 12)
Continued next page.
NOTES: 5.
6.
7.
8.
9.
10.
11.
12.
10000
25
15
10000
30
ns
10000
90
70
ns
ns
Timing measurements in this table are referenced to VIL max and VIH min.
All cycle times assume tt = 5 ns.
,
To guarantee tc(P) min, tsu(CA) should be greater than or equal to tw(CH).
In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. (Depending on the user's transition times, this may require
additional CAS low time [tw(CL)j).
In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. (Depending on the user's transition times, this may require
additional RAS I~ time [tw(RL)j).
Later of CAS or W in write operations.
Early write operation only.
The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
TEXAS
l!1
INSTRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-9
TMS44C256
262 144·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMGS256C - JUNE 1986 - REVISED NOVEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
TMS44C256·60
ALT.
SYMBOL
MIN
MAX
PARAMETER
TMS44C256·70
MIN
MAX
UNIT
th(D)
Data hold time after CAS low (see Note 10)
tDH
10
15
ns
th(RLD)
Data hold time after RAS low (see Note 12)
tDHR
50
55
ns
th(WLGL)
G hold time after W low
tGH
15
18
ns
th(CHrd)
Read hold time after CAS high (see Note 13)
tRCH
0
0
ns
th(RHrd)
Read hold time after RAS high (see Note 13)
tRRH
0
0
ns
th(CLW)
Write hold time after CAS low (see Note 11)
tWCH
15
15
ns
th(RLW)
Write hold time after RAS low (see Note 12)
tWCR
50
55
ns
td(RLCH)
Delay time, RAS low to CAS high
tCSH
60
70
ns
td(CHRL)
Delay time, CAS high to RAS low
tCRP
0
0
ns
td(CLRH)
Delay time, CAS low to RAS high
tRSH
15
18
ns
td(CLWL)
Delay time, CAS low to W low (see Note 14)
tCWD
40
46
ns
td(RLCL)
Delay time, RAS low to CAS low (see Note 15)
tRCD
20
45
20
52
ns
td(RLCA)
Delay time, RAS low to column·address (see Note 15)
tRAD
15
30
15
35
ns
td(CARH)
Delay time, column-address to RAS high
tRAL
30
35
ns
td(CACH)
Delay time, column-address to CAS high
tCAL
30
35
ns
td(RLWL)
Delay time, RAS low to W low (see Note 14)
tRWD
85
98
ns
td(CAWL)
Delay time, column-address to W low (see Note 14)
tAW 0
55
63
ns
td(GHD)
Delay time, G high before data at DO
tGDD
15
18
ns
ns
td(GLRH)
Delay time, G low to RAS high
tGSR
10
10
td(RLCH)R
Delay time, RAS low to CAS high (see Note 16)
tCHR
15
15
ns
td(CLRL)R
Delay time, CAS low RAS low (see Note 16)
tCSR
10
10
ns
td(RHCL)R
Delay time, RAS high CAS low (see Note 16)
tRPC
0
trf
Refresh time interval
tREF
Transition time
tt
Continued next page.
NOTES: 5.
10.
11.
12.
13.
14.
15.
16.
IT
Timing measurements in this table are referenced to VIL max and VIH min.
Later of CAS or Vii in write operations.
Early write operation only.
The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
Read-modify-write operation only.
Maximum value specified only to guarantee access time.
CAS-before-RAS refresh only.
TEXAS . .
INSTRUMENTS
5·10
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
3
ns
0
8
50
3
8
ms
50
ns
TMS44C256
262 144-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C -
JUNE 1986 -
REVISED NOVEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
ALT.
SYMBOL
PARAMETER
TMS44C256-80
MIN
MAX
TMS44C256-10
MIN
MAX
TMS44C256-12
MIN
MAX
UNIT
them
Data hold time after CAS low (see Note 10)
tDH
15
20
25
ns
th(RLD)
Data hold time after RAS low (see Note 12)
tDHR
60
70
85
ns
ns
th(WLGL)
G hold time after W low
tGH
20
25
30
th(CHrd)
Read hold time after CAS high (see Note 13)
tRCH
0
0
0
ns
th(RHrd}
Read hold time after RAS high (see Note 13)
tRRH
0
0
0
ns
ns
th(CLW)
Write hold time after CAS low (see Note 11)
tWCH
15
20
25
th(RLW)
Write hold time after RAS low (see Note 12)
tWCR
60
70
85
ns
td(RLCH)
Delay time, RAS low to CAS high
tCSH
80
100
120
ns
ns
td(CHRL)
Delay time, CAS high to RAS low
tCRP
0
0
0
td(CLRH)
Delay time, CAS low to RAS high
tRSH
20
25
30
ns
td(CLWL)
Delay time, CAS low to W low (see Note 14)
tCWD
50
60
70
ns
td(RLCL)
Delay time, RAS low to CAS low (see Note 15)
tRCD
22
60
25
75
25
90
ns
td(RLCA)
Delay time, RAS low to column-address
(see Note 15)
tRAD
17
40
20
55
20
65
ns
td(CARH)
Delay time, column-address to RAS high
tRAL
40
45
55
td(CACH)
Delay time, column-address to CAS high
tCAL
40
45
55
ns
td(RLWL)
Delay time, RAS low to W low (see Note 14)
tRWD
110
135
160
ns
td(CAWL)
Delay time, column-address to W low
(see Note 14)
tAWD
70
80
95
ns
ns
td(GHD)
Delay time, G high before data at DO
tGDD
20
25
30
ns
td(GLRH)
Delay time, G low to RAS high
tGSR
10
10
10
ns
ns
td(RLCH)R
Delay time, RAS low to CAS high (see Note 16)
tCHR
20
25
25
td(CLRL)R
Delay time, CAS low RAS low (see Note 16)
tCSR
10
10
10
ns
td(RHCL)R
Delay time, RAS high CAS low (see Note 16)
tRPC
0
0
0
ns
trf
Refresh time interval
tREF
tt
Transition time
NOTES: 5.
10.
11.
12.
13.
14.
15.
16.
tT
8
3
50
8
3
50
3
8
ms
50
ns
Timing measurements in this table are referenced to VIL max and VIH min.
Later of CAS or IN in write operations.
Early write operation only.
The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
Read-modify-write operation only.
Maximum value specified only to guarantee access time.
CAS-before-RAS refresh only.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
5-11
TMS44C256
262 144-WORD BY 4-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C-JUNE 1986 - REVISED NOVEMBER 1990
PARAMETER MEASUREMENT INFORMATION
1.31 V
R1 = B2B Q
RL=21BQ
Output Under Test
Output Under Test
CL=100pF
T
CL=100pF
(b) Alternate Load Circuit
(a) Load Circuit
Figure 1. Load Circuits for Timing Parameters
read cycle timing
NOTE 17:
Output may go from high·impedance to an invalid data state prior to the specified access time.
TEXAS •
INSlRUMENTS
5-12
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
R2 = 295 Q
TMS44C256
262 144-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C -
JUNE 1986 -
REVISED NOVEMBER 1990
early write cycle timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-13
TMS44C256
262 144-WORD BY 4-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C - JUNE 1986 - REVISED NOVEMBER 1990
late write cycle timing
TEXAS ~
INSTRUMENTS
5-14
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44C256
262 144-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C -
JUNE 1986 -
REVISED NOVEMBER 1990
read-write/read-modify-write cycle timing
14
N
RAS
~I
tc(ROW)
tw(RL)
_-'-"IiI 14
~I
I I
--.I j+-
tt
14
,
tsu(RA)
-.l
I
,
I
~,
I... ,
I
0
I.
I I
t..o
""t+i -
th(RA)
I+-+t- ~su(CA)
.,J
td(RLCA)
~
AD-AS
I
N
I I
I,
.~~
:'4
~
,
"
t
'd(RLWL)
!+--f--tsU(rd) - - . I
I
~
I
I
I
,
,
I
I
,
001004
tsu(WCH)
ta(R)
1
I I
i "--
I
I
I
~I
14
~
1
Oau:
V'H
VIL
tsu(WRH)
tw(WL)
VIH
VIL
~----cJL._~,,~/'''~\I~\,"1'.\,''''1'\~\-:\~~~~~~~~VIH/VOH
0 t
1
VIL
~ tw(CH) - . !
N ~~~~~~~""""~§~cg~~e~~""'"
1
-
.::!
r.-
r.- ta(G) -.:--':
I
t1 IS (G)
I
~ th(WLGL)
11e4--"~ll-td(GHO)
GmHYE_)
NOTE 17:
I I
I ... I
,
,
}
td(CAWL)
~ I
~ td(CLWL) ---~ I
: ta(C)
\4
.1
-+I tOiIIT tsu(O)
~ ta(~A) - . I
I -.l ~ th(O)
I
I ,
td(CLZ) -.!
~ 1
I
Ie,,,,---
tw(RH)
vlH
1
I
(see Note 17)
~
I
I
~
I
I
~I
I:
'4
'
~I
~tt
I '
-----i-'_______-<
I
:+T
I ' - - - - - VIL
I
14
td(CHRL)
VIH
~
~Hh~~~,-_________
c~'umn
I...
...
IN
I
I
~.
tw(CL)
I ~ td(RLCL) --.I
I
Vi
:
~H*H~ :::
Output may go from high·impedance to an invalid data state prior to the specified access time.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5·15
TMS44C256
262 144-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C -
JUNE 1986 -
REVISED NOVEMBER 1990
enhanced page-mode read cycle timing
VIL
Column
AQ-AS
-+I I
~tsU(rd)~
I
-XXXXTi
j!
w '££i)'
:
I
I~
~~~~~Q4.:~~
I
I
td(RLCA)
Ith(RHrd)
I
j
I'Q<"X"YI
: ta(c):~
~I
f+--- ta(C~) --.J
ta(R)
I
~:
td(CLZ) ----j4-+I
I
001(see Note 17)
004 --------------------------~
f+--- th(C.Hrd)
1'\1/1
1
~
ta(CA) -.:
(see Note 19) I
I
VIL
~
I~
I
I
~ VIH
\QVIL
I~
tdls(CH)
ta(CP) - . ,
(see Note 19)
I
(see Note 1S)
-r-"----:IIi..
14--
.r--_..
~--------~X
VOH
>-----VOL
NOTES: 17. Output may go from high-impedance to an invalid data state prior to the specified access time.
18. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
19. Access time is ta(CP) or ta(CA) dependent.
TEXAS . .
INSTRUMENTS
5-16
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TMS44C256
262 144-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C -
JUNE 1986 -
REVISED NOVEMBER 1990
enhanced page-mode write cycle timing
tw(RH)
-+I
141~~-----------tw(RL)P -----------~.I
I
I
~
I
I+-
I
VIH
:~
~.----------------------------1 i 1"-- VIL
RASN
I
:
:~
td(RLCH)
td(RLCL)
tw(CL)
I~
: I
I I
:1
-.I
I
I
I
I
'K\~
:
j+.tsu(RA)
I
I
:
I
tsu(CA)
i+-
-.I
*-- th(RA) ~!
I~
I
~
I
I
.1 I~
tc(P)
I ~ tw(CH) --.I
~
i
I I
I
I
I
I
I
.1
::
~ td(CLRH) ~
I
I
I
I
I
I
I .1
I I
.1 I
I
td(CARH)
I
I
I
I
.r-------'-"
Row
I
!I !I
I I
~ td(CACH) -+I I
I~
I
*- td(CHAL) ~
\"1!:
Y:
*- th(CA) ~
I
th(RLC )
.r---J...-----~
AO-AS
.1
,,'7'0~~'7'0~~7\7' VIH
Column
I
~ td(RLCA) ----+1
I~
th(RLW) --;---t----1~
I
tsu(WCH)
I
~
~
:
~tSU(WRH) ~
1
I
," /'''.f'- /,1
~~~~~~~~~~~~--T_~~~~~~~~~~~~~~~~~~~~~~VIL
I~I
'-1
I I
~
ll~
04-
tsu(D)
(see Note 21)
001·
004
th(D)
-.I
~ (see Note 21) I
~th(D\
.1
(see Note 2 1 ) :
1'4----..+-1 th(WLGL)
I
thl RLD)
I
I
->.(s=-:e:..::..e...:..:N:..::..ot.:..=e--=2'-'-'1)'--_~.:
Valid Data In
I
--..1 I+- td(GHD)
I
114.1----...If- th(WLGL)
--.!
I
I
I
~ td(GHD)
NOTES: 20. A read cycle or a read-modify-write cycle can be intermixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
21. Referenced to CAS or 'ii, whichever occurs last.
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-17
TMS44C256
262 144-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C -
JUNE 1986 - REVISED NOVEMBER 1990
enhanced page-mode read-modify-write cycle timing
tw(RH) ~
~1~1-----------tw(RL)P -----------.;. I
I
RAS
~~I________________________________________~};r[\1 ~____
td(RLCL)
-+I-!I.~
I I~
I I
I
11
1
~
1f4~fl--I----tC(PM).1
I
tw(CL)
~1 I
I I
I tS~(CA)
~
I
I
1 I
1
-+l ~
I~
•:
.1
th(RA)
~
I
~ td(CAWL)
~
I
i
III
"\j
!x
I I-+.J
~
I
I
I I I I
ta(e) I I
tsu(rd) -+J I ~:
!~l
: ta(CA) :~ I
.1
~ tsu(D)
1111
J+--ta(R)
td(CLZ)
_I
I
~
I
I
I
I
VIL
td(CHRL)
VIH
VIL
VIH
VIL
:
'III
\;
I
I
~ ta(CP) -.J
...1
VIH
~VIL
141~-_-...I,--- th(WLGL)
II
:
I
I
I
I I
I
:
I
~ ~
I
I
VIH
I
-II~-~"
"'~f----:---t.~I- tsu(WRH)
L..
tsu(WCH)
~
_
'I
I
I
•
~
Column
!I I ;+ td(CLWL)~I
-.l
I
~ ~! 14~,--..t-1 t~(WL)
!.-td(RLWL) ~ I
J/-~-~
001004
Valid Out
~ ta(G)
I
I
G
tw(CH)
th(CA)
A~AB~: ~olumn ~
I
I
/
1 .
I~
I I
.1 I
I~ I
~
I
\.I~
I 't
1... 1
td(RLCA)
~td(CLRH) ~
j'
I
I
.1
_ _ ..I td(RLCH)
..·
~ ~tsu(RA)
Vi
~
I
I
I I
~
----.J
I
I
-ti-l ~
.:
tdls(G)
th(WLGL)
I
I~________~I
/
I
I
~:.-
td(GHD)
r l_ _ _ _ _ _-,~~~~~~
\~----J/
NOTES: 17. Output may go from high-impedance to an invalid data state prior to the specified access time.
22. A read orwrite cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not violated.
TEXAS ~
INSTRUMENlS
5-18
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44C256
262 144·WORD BY 4·BIT
DYNAMIC
RANDOM·ACCESS MEMORY
SMGS256C - JUNE 1986 - REVISED NOVEMBER 1990
RAS-only refresh timing
f4II- tw(RL) -.-l
N
RAS
td(CHRL) ---loII1"~~~1
:
~I
tc(rd)
:411
_ _ _ _ _ _ _ _ _ _ _ _...,:1
JI:
VIH
T\
VIL
~ tw(RH) ~
1
~ ~
:
tt
1411
~:
td(RHCL)R.
VIH
VIL
VIH
Row
VIL
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
5·19
TMS44C256
262 144-WORD BY 4-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C -
JUNE 1986 -
REVISED NOVEMBER 1990
hidden refresh cycle (enhanced page mode)
TEXAS
-1!1
INSTRUMENTS
5-20
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TMS44C256
262 144-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C -
JUNE 1986 -
REVISED NOVEMBER 1990
automatic (CAS-before-RAS) refresh cycle timing
14
...- - - - - - - - - - tc (rd) ----------~.I
~ tw(RH)
RAS
-A
td(RHCL)R
~
-+l
td(CLRL)R
CAS
-+J
N
1.
4.1
.-
~ ~
I...
\l
..,
-
-
-
-
-
-
yr-----
tw(RL) - - - - - - - . ,
..
1
:
tt
114... - - - - td(RLCH)R - - - - . !
.. I
Y
OQ1- - - - - - - - - - - - - - - - H I - Z - - - - - - - - - - - - - - oQ4
device symbolization
-SS
--
TI
TMS44C256r
Package Cod e
N DIP
OJ =SOJ
SO =ZIP
ON =ThinSO J
=
F
0
P
XXX
-
LL
--
Wafer Fab Co de
Ole Revision Code
Assembly Si te Code
Month Code
Lot Traceabl lity Code
Speed (-60, -70 -80, -10, -12
TEXAS
"!1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-21
TMS44C256
262 144-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMGS256C -
JUNE 1986 - REVISED NOVEMBER 1990
TEXAS •
INSlRUMENTS
5-22
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS4C1024, TMS4C1 025, TMS4C1 027
1 048 576·81T DYNAMIC RANDOM·ACCESS MEMORIES
SMGS024F - MAY 1986 - REVISED NOVEMBER 1990
This Data Sheet Is Applicable to All
TMS4C1024/5/7s Symbolized with Revision
"0" and Subsequent Revisions as Described
on Page 5-62.
A9
VSS
TF
AD
A1
A2
A3
• Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME
OR
ta(R)
ta(c)
ta(CA) WRITE
(tRAC)
(tCAC)
(tcw CYCLE
(MIN)
(MAX)
(MAX)
(MAX)
30 ns
110 ns
15 ns
60 ns
35 ns
130 ns
18 ns
70 ns
40 ns
150 ns
80 ns
20 ns
100 ns
25 ns
180 ns
45 ns
220 ns
30 ns
55 ns
120 ns
D
CAS
A9
A8
A7
A6
A5
A4
RAS
• Single 5-V Supply (10% Tolerance)
0
0
W
• 1 048576 x 1 Organization
TMS4C1024-60
TMS4C1024-70
TMS4C102 -80
TMS4C102--10
TMS4C102=-12
SO Package
(Top View)
N Package
(Top View)
RAS
NC
AD
A2
VCC
A5
A7
CAS
VSS
W
TF
NC
A1
A3
A4
A6
A8
OJ and ON Packages t
(Top View)
• TMS4C1024 - Enhanced Page Mode
Operation for Faster Memory Access
- Higher Data Bandwidth than Conventional
Page-Mode Parts
- RandomSingle-Bit Access Within a Row
With a Column Address
D
VSS
W
·0
CAS
NC
A9
RAS
TF
NC
• TMS4C1 025 - 4-Bit Nibble Mode Operation
- Four Sequential Single-Bit Access Within
a Row By Toggling CAS
AD
A1
A2
A3
• TMS4C1027- Static Column Decode Mode
Operation
- Random Single-Bit Access Within a Row
With Only a Column Address Change
AS
A7
A6
A5
A4
VCC
• One of TI's CMOS Megabit DRAM Family,
IncludlngTMS44C256 - 256Kx 4
Enhanced Page Mode
tThe packages shown here are for pinout reference only.
The DJ package is actually 75% of the length of the N
package.
• CAS-Before-RAS Refresh
PiN NOMENCLATURE
• Long Refresh Period ... 512-Cycle Refresh
in 8 ms (Max)
AO-A9
CAS
D
• 3-State Unlatched Output
NC
• Low Power Dissipation
Q
• Texas Instruments EPIC ™ CMOS Process
RAS
TF
• All Inputs/Outputs and Clocks Are TIL
Compatible
W
VCC
VSS
• Operating Free-Air Temperature Range
... O°C to 70°C
Address Inputs
Column-Address Strobe
Data In
No Connection
Data Out
Row-Address Strobe
Test Function
Write Enable
5-V Supply
Ground
• Operations of Tl's Megabit CMOS DRAMs
Can Be Controlled by TI's SN74ALS6301
and SN74ALS6302 Dynamic RAM
Controllers
• High-Reliability Plastic 18-Pin 300-Mil-Wide
DIP, 20/26 J-Lead Surface Mount (SOJ), 20/26
Thin J-Lead Surface Mount (ThinSOJ) or
20-Pin Zig-Zag In-line (ZIP) Packages
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA documents contain Information
current IS of publlcallon date. Products conform to
specilicalions per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily Include testing of all parameters.
TEXAS
-1!1
Copyright © 1990, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-23
TMS4C1024, TMS4C1025, TMS4C1027
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
description
The TMS4C1024, TMS4C1025, and TMS4C1027 are high-speed, 1 048 576-bit dynamic random access
memories, organized as 1 048 576 words of one bit each. They employ state-of-the-art EPICTM (Enhanced
Process Implanted CMOS) technology for high performance, reliability, and low power at a low cost.
These devices feature maximum RAS access times of 60 ns, 70 ns, 80 ns, 100 ns, and 120 ns. Maximum power
dissipation is as low as 305 mW operating and 11 mW standby on 120 ns devices.
The EPIC technology permits operation from a single 5-V supply, reducing system power supply and decoupling
requirements, and easing board layout. Icc peaks are 140 mA typical, and a - 1-V input voltage undershoot
can be tolerated, minimizing system noise considerations.
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS4C1 02_ are offered in an 18-pin plastic dual-in-line (N suffix) package, a 20/26 J-Iead plastic surface
mount SOJ (OJ suffix) package, a 20/26 J-Iead thin plastiC surface mount SOJ (ON suffix), and a 20-pin zig-zag
in-line (SO suffix) package. The TMS4C1024-60 and TMS4C1024-70 are available in the 20/26 J-Iead plastic
surface mount SOJ (OJ suffix) only. These packages are characterized for operation from O°C to 70°C.
operation
enhanced page mode (TMS4C1024)
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is thus eliminated.
The maximum number of columns that may be accessed is determined by the maximum RAS low time and the
CAS page cycle time used. With minimum CAS page cycle time, all 1024 columns specified by column addresses
AO through A9 can be accessed without intervening RAS cycles.
.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS4C1 024 to operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as column address is valid rather than when
C~S transitions low. This performance improvement is referred to as "enhanced page mode". Valid column
address may be presented immediately after row address hold time has been satisfied, usually well in advance
of the falling edge of CAS. In this case, data is obtained after ta(C) max (access time from CAS low), if ta(CA)
max (access time from column address) has been satisfied. In the event that column addresses for the next page
cycle are valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence
of ta(C) or ta(CP) (access time from rising edge of CAS).
TEXAS •
INSlRUMENTS
5-24
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS4C1024, TMS4C1025, TMS4C1027
1 048 576-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
nibble mode (TMS4C1025)
Nibble-mode operation allows high-speed read, write, or read-write-modify-write access of 1 to 4 bits of data.
The first bit is accessed in the normal manner with read data coming out at ta(C) time as long as ta(R) and ta(CA)
are satisfied. The next sequential bits can be read or written by cycling CAS while RAS remains low. The first
bit is determined by the row and column addresses, which need to be supplied only for the first access. Row A9
and column A9 provide the two binary bits for initial selection, with row A9 being the least-significant address
and column A9 being the most significant. Thereafter, the falling edge of CAS will access the next bit of the circular
4-bit nibble in the following sequence.
(00)
---.
(01)
---.
( 1 0)
(11)
=1
Data written in a sequence of more than 4 consecutive cycles shall be capable of being read back without exiting
from the nibble mode. In a sequence of consecutive nibble-mode cycles the control of the high-impedance state
for the data out (Q) pin is determined by each individual cycle. This facilitates fully mixed nibble-mode cycles (e.g.,
read/write/read-modify-write/read etc.).
static column decode mode (TMS4C1027)
The static column decode mode of operation allows high-speed read, write, or read-modify-write by reducing the
number of required signal setup, hold, and transition timings. This is achieved by first addressing the row and
column in the normal manner, but after the first access, maintaining CAS low. Subsequently changing the column
address produces valid data at ta(CA)' The first bit is accessed in the normal manner with read coming out at ta(R)
time. Similarly, write or read-modify-write cycle times can be achieved with appropriate toggling of W. The
addresses are latched during the write operation, and remain latched unitl CAS or W no longer remains low.
address (AO through A9) (TMS4C1024, TMS4C1025)
Twenty address bits are required to decode 1 of 1 048 576 storage cell locations. Ten row-address bits are set
up on inputs AD through A9 and latched onto the chip by the row-address strobe (RAS). The ten column-address
bits are set up on pins AD through A9 and latched onto the chip by the column-address strobe (CAS). All
addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable in that
it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select activating the output
buffer, as well as latching the address bits onto the column-address buffer.
address (AO through A9) (TMS4C1027)
Twenty address bits are required to decode 1 of 1 048 576 storage cell locations. Ten row-address bits are set
up on pins AD through A9 and latched onto the chip by the row-address strobe (RAS). The ten column-address
bits are set up on pins AD through A9. Row addresses must be stable on or before the falling edges of RAS.
RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. In a write cycle,
the later of CAS or W latches the column address bits.
write enable (W)
The read or write mode is selected through the write enable (W) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from the standard
TTL circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes
low prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle, permitting
common I/O operation.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
IX:
5-25
TMS4C1024, TMS4C1025, TMS4C1027
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 - REVISED NOVEMBER 1990
data in (0)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early write cycle, W is brought low prior to CAS and
the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or
read-modify-write cycle, CAS will already be low, thus the data will be strobed in by W with setup and hold times
referenced to this signal.
data out (0)
The three-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS is brought low. In a read cycle the output becomes valid after the access time interval ta(C) that begins
with the negative transition of CAS as long as ta(R) and ta(CA) are satisfied. The output becomes valid after the
access time has elapsed and remains valid while CAS is low; CAS going high returns it to a high-impedance
state. In a delayed-write or read-modify-write cycle, the output will follow the sequence for the read cycle.
refresh
A refresh operation must be performed at least once every eight milliseconds to retain data. This can be achieved
by strobing each of the 512 rows (AD-AS). A normal read or write cycle will refresh all bits in each row that is
selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, thus conserving power
as the output buffer remains in the high-impedance state. Externally generated addresses must be used for a
RAS-only refresh. Hidden refresh may be performed while maintaining valid data at the output pin. This is
accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period,
similar to a RAS-only refresh cycle.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS [see parameter td(CLRL) R] and holding
it low after RAS falls [see parameter td(RLCH)R]' For successive CAS-before-RAS refresh cycles, CAS can
remain low while cycling RAS. The external address is ignored and the refresh address is generated internally.
The external address is also ignored during the hidden refresh cycles.
power-up
To achieve proper device operation, an initial pause of 200 f-ts followed by a minimum of eight initialization cycles
is required after full VCC level is achieved.
test function pin
During normal device operation the TF pin must either be disconnected or biased at a voltage less than or equal
to VCC'
TEXAS ~
INSTRUMENTS
5-26
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TMS4C1024, TMS4C1025, TMS4C1027
1 048 576-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
logic symbol t
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
6
7
8
10
11
12
D
0
A 1 048575
13
14
15
20D19/21D9
C20[ROW]
G23/[REFRESH ROW]
24[PWR DWN]
C21[COL]
G24
3~
t>
F
>
16
Vi
RAM 1024K x 1
20D10/21DO '
5
2
1
1
&
r> 23C22
23210
A22D
24EN
A\l
17
Q
trhis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
The pin numbers are for the 18-pin dual-in-line N package.
TEXAS
"'!1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-27
TMS4C1024, TMS4C1025, TMS4C1027
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
functional block diagram
w
+
l~
...
Row
Address
Buffers
(10)
256K
Array
-.AO
A1
r
A2
A3
..
A4
A5
+
Timing and Control
I
~J
Row
Decode
+
I Array
256K
Sense Amplifiers
Column
Address
Buffers
(10)
Column Decode
-\
-I
~
A6
A7
.....-......-......-......-......-......-......-.-
...
~
Data
In
Reg .
~
o
r..-
Data
Out
Reg.
f-+
Q
1/0
Buffers
1 of 8
Selection
Sense Amplifiers
A8
256K
Array
A9
I
Row
Decode
I Array
256K
II
absolute maximum ratings overoperating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee ............................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 65°C to 150°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
DC
TEXAS
-IJ1
INSTRUMENTS
POST OFFICE BOX 1443
•
V
..
..IS designated as minimum,
IS used rn thiS data sheet for logic
..
NOTE 2: The algebraiC convention, where the more negative (less positive) Irmlt
voltage levels only.
5-28
UNIT
HOUSTON, TEXAS 77001
TMS4C1024, TMS4C1025, TMS4C1027
1 048 576-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
TMS4C1024·60
TEST CONDITIONS
PARAMETER
MIN
VOH
High-level output voltage
10H =-5 mA
VOL
Low-level output voltage
10L = 4.2 mA
II
Input current (leakage)
VI = 0 to 6.5 V, VCC = 5.5 V,
All other pins = 0 to VCC
10
Output current (leakage)
Va = 0 to VCC, VCC = 5.5 V, CAS high
ICC1
Read or write cycle current
Minimum cycle, VCC = 5.5 V
ICC2
Standby current
After 1 memory cycle, RAS and CAS high,
VIH = 2.4 V
ICC3
Average refresh current
(RAS-only, or CSR)
Minimum cycle, VCC = 5.5 V
RAS cycling, CAS high (RAS-only),
RAS low, after CAS low (CSR)
ICC4
Average page current
(TMS4C1024)
TMS4C1024·80
TMS4C1025·80
TMS4C1027·80
TEST CONDITIONS
MIN
High-level output voltage
10H =-5 mA
VOL
Low-level output voltage
10L = 4.2 mA
II
10
MIN
MAX
2.4
UNIT
V
V
±10
±10
flA
±10
±10
flA
95
80
mA
2
2
mA
90
80
mA
70
60
mA
TMS4C1024·10
TMS4C1025·10
TMS4C1 027-10
MIN
MAX
0.4
0.4
= minimum, VCC = 5.5 V,
RAS low, CAS cycling
VOH
TMS4C1024·70
2.4
2.4
~
PARAMETER
MAX
MAX
TMS4C1024·12
TMS4C1025·12
TMS4C1027·12
MIN
MAX
2.4
2.4
UNIT
V
0.4
0.4
0.4
V
Input current (leakage)
VI = 0 to 6.5 V, VCC = 5.5 V,
All other pins = 0 V to VCC'
±10
±10
±10
IlA
Output current (leakage)
Va = OtoVCC,
VCC = 5.5 V, CAS high
±10
±10
±10
IlA
75
65
55
mA
2
2
2
mA
70
60
50
mA
50
45
35
mA
50
45
40
mA
50
45
35
mA
ICC1
Read or write cycle current
Minimum cycle, VCC = 5.5 V
ICC2
Standby current
After 1 memory cycle,
RAS and CAS high, VIH = 2.4 V
ICC3
Average refresh current
(RAS-only, or CSR)
Minimum cycle, VCC '" 5.5 V
RAS cycling, CAS high (RAS-only),
RAS low, after CAS low (CSR)
ICC4
Average page current
(TMS4C1024)
~ = minimum, VCC = 5.5 V,
ICC5
Average nibble current
(TMS4C1025)
~
ICC6
Average static column
decode current
(TMS4C1027)
RAS low, CAS cycling
= minimum, VCC = 5.5 V,
RAS low, CAS cycling for 4 cycles
~W)SC = minimum, VCC = 5.5 V,
RAS low, CAS cycling
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-29
TMS4C1024, TMS4C1025, TMS4C1027
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
capacitance over recommended rang'es of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(D)
Input capacitance, data input
5
pF
pF
Ci(RC)
Input capacitance, strobe inputs
5
Ci(W)
Input capacitance, write-enable input
5
pF
Co
Output capacitance
7
pF
NOTE 3: VCC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
ALT.
PARAMETER
SYMBOL
TMS4C1024-60
MIN
MAX
TMS4C1024-70
MIN
MAX
UNIT
talC)
Access time from CAS low t
tCAC
15
18
ta(CA)
Access time from column-address t
tCAA
30
35
ns
ta(R)
Access time from RAS low t
tRAC
60
70
ns
40
ns
18
ns
ta(CP)
Access time from column precharge (TMS4C1024 only)
tCAP
td(CLZ)
CAS low to output in low Z
tCLZ
0
tdis(CH}
Output disable time after CAS high (see Note 4)t
tOFF
0
TMS4C102_-80
ALT.
PARAMETER
SYMBOL
MIN
MAX
35
TMS4C102_-10
MIN
ns
0
15
MAX
0
TMS4C102_-12
MIN
ns
UNIT
MAX
talC)
Access time from CAS low t
tCAC
20
25
30
ns
ta(CA)
Access time from column-address t
tCAA
40
45
55
ns
ta(R)
Access time from RAS lowt
tRAC
80
100
120
ns
ta(CP)
Access time from column precharge
(TMS4C1024 only)
tCAP
60
ns
td(CLZ)
CAS low to output in low Z
tCLZ
ta(C)N
Access time CAS low (TMS4C1 025 only)
tNCAC
20
25
25
ns
ta(WHQ)
Access time from W high (TMS4C1027 only)
tWRA
20
30
35
ns
ta(WLQ)
Access time from W low (TMS4C1027 only)
tALW
th(CAQ)
Static column decode mode output hold time
after address change (TMS4C1 027 only)
tAOH
tWOH
0
tdis(CH)
tOFF
tParameters apply uniformly to TMS4C1 024, TMS4C1 025, TMS4C1 027.
NOTE 4: tdis(CH) is specified when the output is no longer driven .
0
th(WQ)
decode mode output hold time
after W low (TMS4C1 027 only)
Output disable time after CAS high (see Note 4)t
0
0
20
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
0
ns
115
5
5
. TEXAS ~
5-30
0
95
75
5
Static~olumn
50
40
0
0
25
0
ns
ns
ns
30
ns
TMS4C1024
1 048 576-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
PARAMETER MEASUREMENT INFORMATION
1.31 V
~
OUlpul Under Tesl
VCC = 5V
RL" 21. g
~
CL=100pF
Output Under Test
T
CL=100pF
(b) Alternate Load Circuit
(a) Load Circuit
Figure 1. Load Circuits For Timing Parameters
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
ALT.
SYMBOL
TMS4C1024-60
MIN
MAX
TMS4C1024-70
MIN
UNIT
MAX
tc(rd)
Read cycle time (see Note 6)
tRC
110
130
ns
tc(W)
Write cycle time
twc
110
130
ns
tRWC
130
153
ns
tpc
40
45
ns
tpCM
60
68
ns
tcp
10
10
ns
tc(rdW)
Read-write/read-modify-write cycle time
tc(P)
Page-mode read or write cycle time (see Note 7)
tc(PM)
Page-mode read-modify-write cycle time
tw(CH)
Pulse duration, CAS high
10000
18
tw(Cl)
Pulse duration, CAS low (see Note 8)
tCAS
15
tw(RH)
Pulse duration, RAS high (precharge)
tRP
40
10000
tw(RL)
Non-page-mode pulse duration, RAS low (see Note 9)
tRAS
60
10000
70
10000
ns
ns
tw(RL)P
Page-mode pulse duration, RAS low (see Note 9)
tRASP
60
100000
70
100000
ns
tw(WL)
Write pulse duration
twp
15
15
ns
tsu(CA)
Column-address setup time before CAS low
tASC
0
0
ns
tsu(RA)
Row-address setup time before RAS low
tASR
0
0
ns
tsu(D)
Data setup time (see Note 10)
tDS
0
0
ns
tsu(rd)
Read setup time before CAS low
tRCS
0
0
ns
tsu(WCL)
W-Iow setup time before CAS low (see Note 11)
twcs
0
0
ns
tsu(WCH)
W-Iow setup time before CAS high
tCWL
15
18
ns
tsu(WRH)
W-Iow setup time before RAS high
tRWL
15
18
ns
th(CA)
Column-address hold time after CAS low
tCAH
10
15
ns
th(RA)
Row-address hold time after RAS low
tRAH
10
10
ns
th(RLCA)
Column-address hold time after RAS low (see Note 12)
tAR
50
55
ns
th(D)
Data hold time (see Note 10)
tDH
10
15
ns
th(RLD)
Data hold time after RAS low (see Note 12)
tDHR
50
55
ns
ns
50
Continued next page.
NOTES: 5. Timing measurements are referenced to VIL max and VIH min.
6. All cycle times assume tt = 5 ns.
7. To guarantee tc(P) min, tsu(CA) should be greater than or equal to tw(CH).
8. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed.
9. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed.
10. Referenced to the later of CAS or W in write operations.
11. Early write operation only.
12. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
TEXAS"
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-31
TMS4C1024
1 048 576-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
TMS4C1024-80
ALT.
MAX
TMS4C1024-10
TMS4C1024-12
MIN
MAX
UNIT
SYMBOL
MIN
tRC
150
180
220
ns
twc
150
180
220
ns
tRWC
175
210
255
ns
tpc
50
55
65
ns
tpCM
75
85
100
ns
MIN
MAX
tc(rd)
Read cycle time (see Note 6)
tc(W)
Write cycle time
tc(rdW)
Read-write/read-modify-write cycle time
tc(P)
Page-mode read or write cycle time (see Note 7)
tc(PM)
Page-mode read-modify-write cycle time
tw(CH)
Pulse duration, CAS high
tcp
10
tw(CL)
Pulse duration, CAS low (see Note 8)
tCAS
20
tw(RH)
Pulse duration, RAS high (precharge)
tRP
60
tw(RL)
Non-page-mode pulse duration, RAS low
(see Note 9)
tRAS
80
10000
100
10000
120
10000
ns
100000
100
100000
120
100000
ns
10
10000
25
15
10000
30
ns
10000
90
70
ns
ns
tw(RL)P
Page-mode pulse duration, RAS low (see Note 9)
tRASP
80
tw(WL)
Write pulse duration
twp
15
15
20
ns
tsu(CA)
Column-address setup time before CAS low
tASC
0
0
0
ns
tsu(RA)
Row-address setup time before RAS low
tASR
0
0
0
ns
tsu(D)
Data setup time (see Note 10)
tDS
0
0
0
ns
tsu(rd)
Read setup time before CAS low
tRCS
0
0
0
ns
tsu(WCL)
W-Iow setup time before CAS low (see Note 11)
twcs
0
0
0
ns
tsu(WCH)
W-Iow setup time before CAS high
tCWL
20
25
30
ns
tsu(WRH)
W-Iow setup time before RAS high
tRWL
20
25
30
ns
th(CA)
Column-address hold time after CAS low
tCAH
15
20
20
ns
th(RA)
Row-address hold time after RAS low
tRAH
12
15
15
ns
th(RLCA)
Column-address hold time after RAS low
(see Note 12)
tAR
60
70
80
ns
th(D)
Data hold time (see Note 10)
th(RLD)
Data hold time after RAS low (see Note 12)
tDH
15
20
25
ns
tDHR
60
70
85
ns
Conllnued next page.
NOTES: 5. Timing measurements are referenced to VIL max and VIH min.
6. All cycle times assume tt = 5 ns.
7. To guarantee tc(P) min, tsu(CA) should be greater than or equal to tw(CH).
8. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed.
9. In a read-modify-write CYC~(RI.,'tYL) and tsu(WRH) must be observed.
10. Referenced to the later of CAS or W in write operations.
11. Early write operation only.
12. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
TEXAS ~
INSTRUMENTS
5-32
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TMS4C1024
1 048 576-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
ALT.
TMS4C1024-60
SYMBOL
MIN
MAX
TMS4C1024-70
MIN
UNIT
MAX
th(CHrd)
Read hold time after CAS high (see Note 15)
tRCH
0
0
ns
th(RHrd)
Read hold time after RAS high (see Note 15)
tRRH
0
0
ns
th(CLW)
Write hold time after CAS low (see Note 11)
tWCH
15
15
ns
th(RLW)
Write hold time after RAS low (see Note 12)
twCR
50
55
ns
td(RLCH)
Delay time, RAS low to CAS high
tCSH
60
70
ns
td(CHRL)
Delay time, CAS high to RAS low
tCRP
0
0
ns
td(CLRH)
Delay time, CAS low to RAS high
tRSH
15
18
ns
td(CLWL)
Delay time, CAS low to W low (see Note 13)
tCWD
15
td(RLCL)
Delay time, RAS low to CAS low (see Note 14)
tRCD
20
45
td(RLCA)
Delay time, RAS low to column address (see Note 14)
tRAD
15
30
td(CARH)
Delay time, column-address to RAS high
tRAL
30
35
ns
td(CACH)
Delay time, column-address to CAS high
tCAL
30
35
ns
td(RLWL)
Delay time, RAS low to W low (see Note 13)
tRWD
60
70
ns
td(CAWL)
Delay time, column-address to W low (see Note 13)
tAWD
30
35
ns
td(RLCH)R
Delay time, RAS low to CAS high (see Note 16)
tCHR
15
15
ns
18
ns
20
52
ns
15
35
ns
td(CLRL)R
Delay time, CAS low to RAS low (see Note 16)
tCSR
10
10
ns
td(RHCL)R
Delay time, RAS high to CAS low (see Note 16)
tRPC
0
0
ns
trf
Refresh time interval
tREF
tt
Transition time
tT
8
3
50
3
8
ms
50
ns
Continued next page.
NOTES: 5. Timing measurements are referenced to VIL max and VIH min.
11. Early write operation only.
12. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
13. Read-modify-write operation only.
14. Maximum value specified only to guarantee access time.
15. Either th(RHrQ~.r th(CHrd) must be satisfied for a read cycle.
16. CAS-before-RAS refresh only.
TEXAS ~.
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
5-33
TMS4C1024
1 048 576-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 - REVISED NOVEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
ALT.
TMS4C1024·80
SYMBOL
MIN
MAX
TMS4C1024·10
MIN
MAX
TMS4C1024·12
MIN
UNIT
MAX
th(CHrd)
Read hold time after CAS high (see Note 15)
tRCH
0
0
0
ns
th(RHrd)
Read hold time after RAS high (see Note 15)
tRRH
0
0
0
ns
th(CLW)
Write hold time after CAS low (see Note 11)
tWCH
15
20
25
ns
th(RLW)
Write hold time after RAS low (see Note 12)
twCR
60
70
85
ns
td(RLCH)
Delay time, RAS low to CAS high
tCSH
80
100
120
ns
td(CHRL)
Delay time, CAS high to RAS low
tCRP
0
0
0
ns
td(CLRH)
Delay time, CAS low to RAS high
tRSH
20
25
30
ns
td(CLWL)
Delay time, CAS low to W low (see Note 13)
tCWD
20
25
30
td(RLCL)
Delay time, RAS low to CAS low (see Note 14)
tRCD
22
60
25
75
25
90
ns
tRAD
17
40
20
55
20
65
ns
td(RLCA)
Delay time, RAS low to column address
, (see Note 14)
ns
td(CARH)
Delay time, column·address to RAS high
tRAL
40
45
55
td(CACH)
Delay time, column-address to CAS high
tCAL
40
45
55
ns
td(RLWL)
Delay time, RAS low to W low (see Note 13)
tRWD
80
100
120
ns
td(CAWL)
Delay time, column-address to W low
(see Note 13)
tAWD
40
45
55
ns
td(RLCH)R
Delay time, RAS low to CAS high (see Note 16)
tCHR
20
25
25
ns
td(CLRL)R
Delay time, CAS low to RAS low (see Note 16)
tCSR
10
10
10
ns
td(RHCL)R
Delay time, RAS high to CAS low (see Note 16)
tRPC
0
trf
Refresh time interval
tt
Transition time
tREF
IT
0
8
3
50
NOTES: 5. Timing measurements are referenced to VIL max and VIH min.
11. Early write operation only.
12. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
13. Read-modify-write operation only.
14. Maximum value specified only to guarantee access time.
15. Either th(RH~r th(CHrd) must be satisfied for a read cycle.
16. CAS-before-RAS refresh only.
TEXAS . .
INSTRUMENTS
5-34
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
0
8
3
ns
50
3
ns
8
ms
50
ns
1MS4C1025
1 048576-811 DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
timing requirements over recommended ranges of s'upply voltage and operating free-air
temperature
ALT.
TMS4C1025-80
SYMBOL
MIN
TMS4C1025-10
MAX
MIN
MAX
TMS4C1025-12
MIN
UNIT
MAX
tc(rd)
Read cycle time (see Note 6)
tRC
150
180
220
ns
tc(W)
Write cycle time
twc
150
180
220
ns
tRWC
175
210
255
ns
tNC
40
45
50
ns
tNRMW
65
75
80
ns
tc(rdW)
Read-write/read-modify-write cycle time
tc(N)
Nibble-mode read or write cycle time
tc(rdW)N
Nibble-mode read-modify-write
cycle time
tcp
10
tCAS
20
tw(CH)
Pulse duration, CAS high
tw(CL)
Pulse duration, CAS low (see Note 8)
tw(RH)
Pulse duration, RAS high (precharge)
tRP
60
25
10000
70
10000
100
ns
15
10
10000
25
10000
90
ns
tw(RL)
Pulse duration, RAS low (see Note 9)
tRAS
80
tw(WL)
Write pulse duration
twp
15
15
20
ns
tsu(CA)
Column-address setup time
before CAS low
tASC
0
0
0
ns
tsu(RA)
Row-address setup time before RAS low
tASR
0
0
0
ns
tsu(D)
Data setup time (see Note 10)
tDS
0
0
0
ns
10000
120
ns
10 000
ns
tsu(rd)
Read setup time before CAS low
tRCS
0
0
0
ns
tsu(WCL)
W-Iow setup time before CAS low
(see Note 11)
twcs
0
0
0
ns
tsu(WCH)
W-Iow setup time before CAS high
tCWL
20
25
25
ns
tsu(WRH)
W-Iow setup time before RAS high
tRWL
20
25
25
ns
th(CA)
Column-address hold time after CAS low
tCAH
15
20
20
ns
th(RA)
Row-address hold time after RAS low
tRAH
12
15
15
ns
th(RLCA)
Column-address hold time after
RAS low (see Note 12)
tAR
60
70
80
ns
th(D)
Data hold time (see Note 10)
tDH
15
20
25
ns
th(RLD)
Data hold time after RAS low
(see Note 12)
tDHR
60
70
85
ns
th(CHrd)
Read hold time after CAS high
tRCH
0
0
0
ns
Read hold time after RAS high
0
.0
tRRH
th(RHrd)
Continued next page.
NOTES: 5. Timing measurements are referenced to VIL max and VIH min.
6. All cycle times assume tt = 5 ns.
8. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed.
9. In a read-modify-write cyc~(RLWL) and tsu(WRH) must be observed.
10. Referenced to the later of CAS or W in write operations.
11 . Early write operation only.
12.The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference
10
ns
TEXAS •
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
5-35
TMS4C1025
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORIES
SMCiS024F -
MAY 1986 -
REVISED NOVEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
ALT.
TMS4C1025-80
SYMBOL
MIN
TMS4C1025-10
MAX
MIN
MAX
TMS4C1025-12
MIN
MAX
UNIT
th(CLW)
Write hold time after CAS low
(see Note 11)
tWCH
15
20
25
ns
th(RLW)
Write hold time after RAS low
(see Notes 11 and 12)
tWCR
60
70
85
ns
td(RLCH)
Delay time, RAS low to CAS high
tCSH
80
100
120
ns
td(CHRL)
Delay time, CAS high to RAS low
tCRP
0
0
0
ns
td(CLRH)
Delay time, CAS low to RAS high
tRSH
20
25
25
ns
td(CLWL)
Delay time, CAS low to W low
(see Note 13)
tCWD
20
25
25
ns
td(RLCL)
Delay time, RAS low to CAS low
(see Note 14)
tRCD
22
60
25
75
25
90
ns
td(RLCA)
Delay time, RAS low to column-address
(see Note 14)
tRAD
17
40
20
55
20
65
ns
td(CARH)
Delay time, column-address to RAS high
tRAL
40
45
55
ns
td(CACH)
Delay time, column-address to CAS high
tCAL
40
45
55
ns
td(RLWL)
Delay time, RAS low to W low
(see Note 13)
tRWD
80
100
120
ns
td(CAWL)
Wlow (see Note 13)
tAWD
40
45
55
ns
td(RLCH)R
Delay time, RAS low to CAS high
(see Note 16)
tCHR
20
25
25
ns
td(CLRL)R
Delay time, CAS low to RAS low
(see Note 16)
tCSR
10
10
10
ns
0
Delay time, column-address to
td(RHCL)R
Delay time, RAS high to CAS low
tRPC
trf
Refresh time interval
tREF
tt
Transition time
0
8
tr
3
50
3
NOTES: 5. Timing measurements are referenced to VIL max and VIH min.
11. Early write operation only.
12. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
13. read-modify-write operation only.
14. Maximum value specified only to guarantee access time.
16. CAS-before-RAS refresh only.
TEXAS ~
INSTRUMENTS
5-36
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
0
8
50
3
ns
8
ms
50
ns
TMS4C1027
1 048 576-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
ALT.
TMS4C1027-80
SYMBOL
MIN
MAX
TMS4C1027-10
MIN
MAX
TMS4C1027-12
MIN
UNIT
MAX
tc(rd)
Read cycle time (see Note 6)
tRC
150
180
220
ns
tc(W)
Write cycle time
twc
150
180
220
ns
tc(rdW)
Read-write/read-modify-write cycle time
tRWC
175
210
255
ns
tc(rd)SC
Static column decode mode read cycle
time
tSCR
45
50
60
ns
tc(W)SC
Static column decode mode write cycle
time
tscw
45
50
60
ns
tc(rdW)SC
Static column decode mode
read-modify-write cycle time
tSCRMW
80
100
120
ns
tw(CH)
Pulse duration, CAS high
tcp
10
10
15
ns
tw(CL)
Pulse duration, CAS low (see Note 8)
tCAS
20
tw(RH)
Pulse duration, RAS high (precharge)
tRP
60
tw(RL)
Non-static column decode mode pulse
duration, RAS low (see Note 9)
tRAS
80
10 000
100
10 000
120
10000
ns
tw(RL)P
Static column decode mode pulse
duration, RAS low (see Note 9)
tRASP
80
100 000
100
100000
120
100000
ns
tw(WL)
Write pulse duration
twp
15
15
20
ns
tw(CA)
Static column decode mode
column-address pulse duration
tADP
40
45
55
ns
tw(WH)
Static column decode mode W high
pulse duration, inactive
tWI
10
10
15
ns
setup time before CAS,
W low (see Note 10)
tASC
0
0
0
ns
tsu(CAR)
Row-address setup time before RAS
tCAR
45
50
60
ns
tsu(RA)
Row-address setup time before RAS low
tASR
0
0
a
ns
tsu(D)
Data setup time
tDS
0
0
0
ns
tsu(rd)
Read setup time before CAS low
tRCS
a
0
a
ns
tsu(WCL)
W-Iow setup time before CAS low (see
Note 11)
twcs
0
0
a
ns
tsu(WCH)
W-Iow setup time before CAS high
tCWL
20
25
30
ns
25
30
ns
tsu(CA)
~olumn-address
10000
25
10 000
70
W-Iow setup time before RAS high
20
tsu(WRH)
tRWL
Continued next page.
NOTES: 5. Timing measurements are referenced to VIL max and VIH min.
6. All cycle times assume tt = 5 ns.
8. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed.
9. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed.
10. Referenced to the later of CAS or W in write operations.
11. Early write operation only.
30
10000
ns
ns
90
TEXAS •
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-37
TMS4C1027
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 - REVISED NOVEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
TMS4C1O.27-8O.
ALT.
SYMBOL
tsu(WHCH)
Setup time, W high to CAS high for early
write, high impedance
th(CA)
MIN
TMS4C1 0.27-1 0.
Mrus
MIN
MAX
TMS4C1O.27-12
MIN
MAX
UNIT
twH
0.
0
0
ns
Wlow (see Note 10)
tCAH
15
20
20
ns
th(RA)
Row-address hold time after RAS low
tRAH
12
15
15
ns
th(RLCA)
Column-address hold time after RAS low
(see Note 18)
tAR
80
100
120
ns
th(D)
Data hold time (see Note 10)
tDH
15
20
25
ns
th(RLD)
Data hold time after RAS low
(see Note 17)
tDHR
60.
70
85
ns
th(CHrd)
Read hold time after CAS high
(see Note 18)
tRCH
0
0
0
ns
th(RHrd)
Read hold time after RAS high
(see Note 18)
tRRH
0
0
10
ns
th(CLW)
Write hold time after CAS low
(see Note 11)
tWCH
15
20
25
ns
th(RLW)
Write hold time after RAS low
(see Note 17)
twCR
60
70
85
ns
th(RHCA)
Column-address hold time after
RAS high
tAH
10
10
15
ns
th(WLCA2)
Static column decode mode second
column-address hold time after Wlow
(see Note 13)
tAHLW
75
95
115
ns
td(RLCH)
Delay time, RAS low to CAS high
tCSH
80.
100
120
ns
td(CHRL)
Delay time, CAS high to RAS low
tCRP
0
0
0
ns
20
25
3D
ns
Column-address hold time after CAS or
Delay time, CAS low to RAS high
td(CLRH)
tRSH
Continued next page.
NOTES: 5. Timing measurements are referenced to VIL max and VIH min.
1D. Referenced to the later of CAS or W in write operations.
11. Early write operation only.
13. Read-modify-write operation only.
17. The minimum value is measured when td(RLCA) is set to td(RLCA) min as a reference.
18. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
TEXAS •
INSTRUMENTS
5-38
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TMS4C1027
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
ALT.
SYMBOL
TMS4C1027-80
MIN
TMS4C1027-10
MAX
MIN
MAX
TMS4C1027-12
MIN
UNIT
MAX
td(CLWL)
Delay time, CAS low to W low
(see Note 13)
tCWD
20
td(RLCL)
Delay time, RAS low to CAS low
(see Note 14)
tRCD
22
60
25
75
25
90
ns
td(RLCA)
Delay time, RAS low to column-address
(see Note 14)
tRAD
17
40
20
55
20
65
ns
td(WLCA)
Delay time, W low to column address
(see Note 14)
tlWAD
20
35
25
50
30
60
ns
td(CARH)
Delay time, column-address to RAS high
tRAL
40
45
55
ns
td(CACH)
Delay time, column-address to CAS high
tCAl
40
45
55
ns
td(RlWL)
Delay time, RAS low to W low
(see Note 13)
tRWD
80
100
120
ns
td(RLWL2)
Static column deco~ mode delay time,
RAS low to second W low
tRSW
80
100
120
ns
td(CAWl)
Delay time, column-address to W low
(see Note 13)
tAWD
40
45
55
ns
td(WQ)
Delay time, W high to output transition
from high impedance to active
tow
0
0
0
ns
td(RLCH)R
Delay time, RAS low to CAS high
(see Note 16)
tCHR
20
25
25
ns
td(CLRl)R
Delay time, CAS low to RAS
(see Note 16)
tCSR
10
10
10
ns
td(RHCl)R
Delay time, RAS high to CAS low
(see Note 16)
tRPC
0
0
0
ns
trf
Refresh time interval
tREF
tt
Transition time
I~w
25
8
tr
3
50
30
8
3
50
3
ns
8
ms
50
ns
NOTES: 5. TIming measurements are referenced to VIL max and VIH min.
13. Read-modify-write operation only.
14. Maximum value specified only to guarantee access time.
16. CAS-before-RAS refresh only.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443
-HOUSTON. TEXAS 77001
5-39
TMS4C1024, TMS4C1 025
1 048 576·81T DYNAMIC RANDOM·ACCESS MEMORIES
SMGS024F -
MAY 1986 - REVISED NOVEMBER 1990
read cycle timing
tc(rd)
N
'I11III
--~'1111111
"
tt --.:
tw(RL)
,
~
,
~.(
td(RLCAI
th(RA) ~
~
"
~ tsu(RA)
.
AO-A9
:
~:.
I
~
'I11III
~,
'I11III
'I11III
: th(RLCA)
1\,
,'--------
"
----.:
,
~td(CHRL) ~
,
td(RLCH)
L...o
,I11III
:i
,
~
!IIIIiI-- td(CLRH) ~ ~ tw(RH)
~td(RLCL) - . I
,~ ; I
,
, '
,
M
~
tw(CL)
,
tsu(CA)
,
I
,
,
td(CACH)
td(CARH)
i
.', ,,
flf-l--'--------~
¥~
I
---.! ,
-L-!---tw(CH)
loll,
}~----
---~
, .'
~
,
~ COlum~: ~~~'!""!"I"'!'f~~!"l"'I"'l"'t~~§§§»x~'--_ _ _ :::
,
,
J. t
....... su(rd)
--..!
~
~ th(CA)
,
~ th(RHrd)
, _I
~
~ th(CHrd)
,
,I',
VOH
a
VOL
NOTE 19:0utput may go from high-impedance to an invalid state prior to the specified access time.
TEXAS ."
INSTRUMENTS
5-40
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
1MS4C1027
1 048 576-811 DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
read cycle timing
,~
tC(rd)
X
----~, ~
-.,
~'
)fi
tw(RL)
11
tt
~ td(CLRH) ~
td(RLCL)
~
td(RLCH)
I ~
IlL..
~
I
th(RA)
~I'
~
~ ~
I I,
AO-A9
I
.i
1
14
~ tS,u(RA) ~
:. 1
1
~ RO~ ~
tw(CL)
td(RlCA~
1I
1 1 td(CACH)
td(CARH)
1 I th(RLCA)
vlL
: I
tw(RH)
I
~ ~ td(CHRL) ~
11 I I
111-1-1.1. 1------------~
!
f~ i i
~'----
11 I 1
tw(CH)
- . I 1 ~ ~ th(RHCA)
.,
1~ I '
1
::
-.l
:.-
1
Column
1 -.,
::
r--I '
w
I ~-------
I I
--.I ~
: \4--
~
k22x_ _ :::
1
~ th(RHrd)
tsu(rd) ~
th(CHrd) -,G----Dt
~~~~~~~----~---~-~I~---~~~~~~~~~~~~~ VIH
~ td(CLZ)
:
~t?(C) ~
~
I o e - - - - ta(CA)
a ----'-1- - HI-Z
1
(see Note 19)
~
.,
______
d_IS_(C_H_)_ _ _ _I
we
1
~..:....1,;0",~
"""""..:....1,;0",.......................................,;..........
VIL
t
Valid
)>------
VOH
VOL
.1
~
ta(R)
NOTE 19: Output may go from high-impedance to an invalid state prior to the specified access time.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
5-41
TMS4C1024, TMS4C1025
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
early write cycle timing
~
RAS
-----!lNiIII!~I-------- tw(RL)
I~
r-
tt -.:
I
I
ioIIl~f--- t
td(RLCL)
I ~
-
CAS
~
~~
i :
~
I
I:
:
I+--t-
~
~
I~
___
td(CHRL)
---al~:
j,1..j.1_ _ _ _ _ _ _ _ _ __ _
I,
tw(CH)
td(CACH)
I
td(CARH)
I
I
I
I
RO~ ~ co'~m~~~~X~a:~$2X'------ :::
I~
td(RLCA)
I
I
I
I~
I
~
~
I~
~
I
I
I
~ ~
§§:~o;Xc~~~
I
~
I I
I I
I I
I
J:
I ~
~
Ii
I I
~ tsu(D) ~
th(RLD)
Valid Data
~
I
i ~
~~
I . I
I
~I
th(CA)
tsu(WCH)
tsu(WRH)
~I
th(RLW}
I I
o
~ 1OI I '~f:-1
~:
~su(CA)
~
I
th(RLCA)
:::
;:
d(CLRH) --~I "'i~I--- tw(RH) --~~I
tw(CL)
II
I
~ tsu(RA)
~'-___
jfi.i
td~RLCH)
II
th(RA)
W
tc(W) -----------~~:
th(CLW)
.
tsu(WCL)
tw(WL)
~
~~~~~~~~~~~~~~'1'r:"?
~~o:l~~~~
~
I
~I
I
VIH
VIL
~ th(D) ~
~:
~~~X*Xe:~
VIL
VOH
Q - - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - - - -
VOL
TEXAS . .
INSTRUMENTS
5-42
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
1MS4C1027
1 048576·811 DYNAMIC RANDOM·ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
early write cycle timing
a
---------------HI·Z -----------------VOL
NOTE 10: Referenced to the later of CAS or Vi in the write operations.
TEXAS ~
INSTRUMENlS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
5-43
TMS4C1024, TMS4C1025
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
write cycle timing
Q
----------------------------~(~____N_o_tV_a_lId____·~)~----------------
TEXAS ~
INSTRUMENTS
5-44
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
VOH
VOL
TMS4C1027
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
write cycle timing
VIH
VIH
VIL
Q
----------------------------~(_____No_t_V_al_ld____~J~-----------------
NOTE 10: Referenced to the later of CAS or W in the write operation.
VOL
.
TEXAS •
INSIRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-45
TMS4C1024, TMS4C1025
1 048 576-81T DYNAMIC RANDOM·ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
read-wrlte/read-modlfy-wrlte cycle timing
NOTE 19: Output may go from high-impedance to an invalid state prior to the specified access time.
TEXAS 'If
INSTRUMENTS
5-46
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS4C1027
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F - MAY 1986 - REVISED NOVEMBER 1990
read-write/read-modify-write cycle timing
NOTE 19: Output may go from high-impedance to an invalid state prior to the specified access time.
TEXAS ~
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-47
TMS4C1024
1 048 576·81T DYNAMIC RANDOM·ACCESS MEMORIES
SMGS024F -
MAY 1986 - REVISED NOVEMBER 1990
enhanced page-mode read cycle timing
tw(RH)~
N
"....
, ....---td(RLCL)
, ,
~
, '..
, I""
,
,
tw(CL)
AO-A9
1'I
th(RA)
th(RLCA)
-.!
I
-.:
I
,
~
,I,
~
td(CHRLl
'
, I
""1
~
VIL
"
:
VIH
II
"
II
VIL
I I
, I
~ td(CACH) ~ I
, I
I
I , ,
th(CA)
~
I
td(CARH)
~ I
I
J'\7'.~~~'j':j~~'j' VIH
Column
-.:"
I'
~,
\\l
A
.-
I
~ tsu(rd) _Ir---I~~'
,
(see Note 20)
ta(CA)
1!4~f----
I
~
I
VIL
th(RHrd) I'I1II
!4-- th(CHrd) ~
I~'
~
~X>OQ¢f~~7-+'--------_+'--------~,----~I~~~~-----------+I----~I--------~~ VIH
Xi£!
I
I
I
I
:
I'"
a
~"
,~
t.-.L
"
• :1""
...' tsU(C~
I
II1II- td(RLCA)
,W
~
tc(P)
~I tw(CH)
,
1
14- td(CLRH)
7\\I}{
-!
I 1I
**", t~U(RA)
1
,
IN'''''
~ rIIII
, ,
,
~
h,' I . , .
- - - J...
~
td(RLCH),
II
',I
,
~
tw(RL)P
:.-ta(C)
td(CLZ)
~
"~f--- ta(CA):
~
W
~14-l-:- - - - ta(CP)
~I
,~
ta(R)
(see Note 20)
::
I
I
~
VIL
,
~~dIS(CH) ~
VOH
(see Note 19)
VOL
NOTES: 19. Output may go from high-impedance to an invalid state prior to the specified access time.
20.Access time is ta(CP) or ta(CA) dependent.
21.A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
TEXAS •
INSlRUMENlS
5-48
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS4C1024
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
,
MAY 1986 -
REVISED NOVEMBER 1990
enhanced page-mode write cycle timing
tw(RH)~
l<...
1li11 - - - - - - - - - - - - - tw(RL)P - - - - - - - - - - - - - - - - ' . 1
I
~
I
~
:~---- td(RLCH)
---l
..
I
14~--- td(RLCL)
:
'=
r-
tw(CL)
~
I
i
.1
I....
\l Y
~ tsu(CA)
th~RLCA)
jIIIII- th(RA) ~
I
I11III-:- tsu(RA)
:
I
:
.1
I11III-- td(CLRH)
~
I
~.--.!
~
I r~f-__.-t-tC(P) I
.1
td(CHRL)
I
I
I~
I
I
I
I
\
tw(CH')
~
I
I11III-- td(CACH) ~
~
th(CA,)
I
I
/,---"""""r- -
td(CARH)
I
I
VIH
VIL
-.I
~--------~~
I
~~~~~~~
AO-A9
VIL
VIH
D
Valid Data In
VIL
a ------------------------HI-Z - - - - - - - - - - - - - - - - - - - NOTES: 22.A read cycle or a read-modify-write cycle can be intermixed with write cycles as long as read and read-modify-write timing specifications
are not violated.
23. Referenced to CAS or W, whichever occurs last.
TEXAS •
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
5-49
TMS4C1024
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
enhanced page-mode read-modify-write cycle timing
tw(RH) ~
0,
i
! __________________________7
14- - - - - - - - - - - tW (RL)P - - - - - - - - - -...
~r
~
\;~,
,~
,
.1
.1
td(RJ-CH)
I
I _,
tw(CH) I 14
~td(RLCL)~
I I
I
\. ~ tw(CL) ~ I"
: tsu(CA)
L..
~~JI
I
I
jth(RLfA)
l"1li
I~
~ ~
~
I
I I
I I
'I
I
:vvvL:r
;~
w
~
I
I
-----r :
'I~
I
'd!RLWL)
~
:
I
, I
,
,
~
~i
~
~th(D)
i tSU(D)tl~
xxx>Y~N~~
1_
I
~ta(C) ~
14--- ta(r.A) ~
I II
t
I
I
~
&1~~~a~~VIH
I
I
Valid
~~f~~W?g
::"L
~
,
1+ tdls(CH) -.I
IOIII~I---- ta(CP) ---1.~1
I
VIL
:
I
I
,
II
II
_
- - su(J'lRH) - . ,
1..01
I
-+'----..:.,
l'
.1
14
I
:
~:
I
Valid } ~
ta(R)
td(CLZ)
~ .,
(see Note 19)
~(o~~cHm:::
tWI\ML)
\"1
...,
: N,~
I , I
I
, ii
I II
( II
tsu(J'lCH)
hi
14
VIL
, II
, II
:
~ ~ td(CLWL)
I ,
~ td(CAWL) ~
A
i i
' I
'h(CA)
.1
If'i------ VIH
\\-
Column ~ Column
,
,
Q
I
I,
,
I+- td(CLRH) ~
I
td(CHRL) 14
II
I
I
i
~
I
~
o
:
I
I
~ tsu(rd) ~
I
I
.,
~ td(R~CA) I
th(RA)
~
AO-A9
}:
I
V,H
:"--- VIL
I,
I
I
.1
I
tc(PM)
I
~
,~
I
(see Note 19)
I
I
I
VOH
NOTES: 19.0utput may go from high-impedance to an invalid state prior to the speCified access time.
24. A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not violated.
TEXAS ~
INSlRUMENTS
5-50
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS4C1025
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
nibble-mode read cycle timing
tw(RH)~
~
tw(RL)
~,i~
i 1:11--------------------I!
1
I~
1
1
td(RLCH) - . I
I
I !1
,,..--+1----
'~
1
1
1
1
1
~I
1 1
--.I j4t:
~ ~h(R~)
VIH
1
i
I
I
1
:
::
I
I
1
I
I
I
I
I
1
I
1
1
1
1
1
VIL
~RX%'Xe~ :::
~ tsu(rd)
Vi
Y
I~
th(RLCA)
I 1 1
:ROW
~
~i
1'1~
i1
i
1
~
1
!~
1
~ td(CLRH) 1~ 1
teeN)
~
1
1
J4- td(RLCL) ~
~
-------~.iH.
~I ~l tp(RLCA)
I
1
1
1
1
I
~ta(C) ~
~ta(CA) ~
1
ta(R) I
td(CLZ) - ,
WN
'\tY
1
I
th(RHr.d)
th(CHrd)
1
1
1
ta(C)N!!III
I
~I
I
~
l-a
~ v
IH
I
~I
~tdiS(CH) ~
I
1
VIL
I
Valid Out
(see Note 19)
VOL
NOTE 19: Output may go from high-impedance to an invalid state prior to the specified access time,
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-51
TMS4C1025
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
nibble-mode write cycle timing
tw(RH)~
RAS
~*I
I
I~
I
:
CAS
I
I
I
I
~
I
.1
AO-A9
W
X
td(RLCL) ~
td(RLGH)
I
'w(Cl) r
tsu(CA)
th~RLCf)
~
I
I
I
I
~
I
'.(CHRll
I
I
I
I
~
II
I
~ td(CACH)
th(CA) ~
th(RA)
~I
~
~I td~RLCA)
~th(RLD)
VIL
VIH
VIL
I
I
I
I
I
I
I
VIH
VIL
:
~~u~cr)~
-.I
VIH
I
:ROW ~: COlumn: ~
I
0
,
~ tw(CH)
I
I
I
11
I I~
-.I ~
I~:'-
~ td(CLRH) ~
I
~
- . I 14- tc(N)
N
I
I ~
~ tSU(RA)
~
I
.
~
~
tw(RL)
~~~~~~~§§S
~th(D)
VIH
VIL
~
VIH
Valid In
VIL
VOH
a
HI-Z
VOL
TEXAS ~
INSTRUMENTS
5-52
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS4C1025
1 048 576-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
nibble-mode read-modify-write cycle timing
RAS.
--N
tw(RH)~
'w(RL)
I I
I ~
td(RLCL,
~
td(RLCH)
~
ioIIII
I
I I
~I
III
: I
~
I
I
I
I
~ td(CLRH) ~
~ tw(CH) ~ I
~ I
I :
I
I :
~ tsu(RA)
I.
I
i!
L
I!:
I
I
I
I
I
.., td(RLCA)
~ ~ tsu(CA)
~th(~~CA) ~
vlL
I
I
I
I
I
I
I
I
I
I
VIH
VIL
~V
'h(CA)
~C~lumn ~~*H*~v::
I~ "'"!
I
I
~t~u(rd)
I
I
I
I
td(CLWL)
~
~
104- t,d(CAWL) ~
I I I
~tsU(WRH) ~
.
tw(WL)
I
.
~
~ th~O)
~"'(RLWL)4
I
I
VI
II1II1
~
~I
"I
'~
-
.:
I
I
td(CHRL)
tw(CH)
N-tW(CL)--YX
~I ~
AO-A9
-----------~YL V,H
I :
I
tc(rdW)N
~
~ !!
I
I
I
I
I
'Ii! Y
\l
-.!I ~ tSU(O\r
I
I I
~ tsu(WCH) ~
m
:
&X4~og~~*02S :::
I
o
Valid
I
I
l~
Q
- - - HI-Z
*ita(CA) ~
ta(R)
~
(see Note 19)
;,---~
tdls(CH) ....,
(see Note 19)
>-...;....--...;....~X
I
td(CLZ)
~
14I
VOH
Valid Out
VOL
I
1+ ta(C) -.l
NOTE 19:0utput may go from high-impedance to an invalid state prior to the specified access time.
TEXAS
l!}
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-53
TMS4C1027
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986- REVISED NOVEMBER 1990
static column decode mode read timing with CAS cycling
RAS
tw(RH) ~
~
~
------------.~~
tw(RL)P
, "'-1_--------------------------......;1 I ,
tt~ ~
I
~~--- td(RLCH)
""~I----""~~ td(RLCL)
~
if
CAS:
I
I,
I
1oII'~f-l--'tti(RLCA)
I
th(RA)
I
tsu(RA)
I ,
~tw(CL)
~I
:
-.I
~
I
r---
td(CHRL)
14- tw(CH) ---.I
I
I I
N
I
II
I
I
~
th(CA)
~:
:
I :
I I I
~ tsu(CAR) ~ I
~ tc(rd)SC ~,
~--I.-"--_ _ _ _ _~I
,
:
'L.-A
:
~,
:~
~,
I I
' : , - '-+1...1.'_ __
'----A,
y-
1_
td(CLRH)
I11III I I
'
VIL
,
th(RHCA) ---.,
I I:,.-_ _ _--'-_"'--~
I
AO-A9
wW'
I
I
I~
Q
I
'-' --.l
....
Ii 4 - ta(C)
W-----!.~
I~
td(CLZ)
I ta(CA)
ta,(R)
I11III
~I
'Wi!
1
-pi
.-1
I
t.....,
~I
I
-.I ~
h(CAQ)
I~
~-"":"vO':'""aU~II~O:--
tdls(CH) --111011~--~~1
tdls(CH)
I
......_V_al_ld_O_U_t
(see Note 19)
(see Note 19)
NOTE 19: Output may go from high-impedance to an invalid state prior to the specified access time.
TEXAS
-1!1
INSTRUMENTS
5-54
',~
I,W
t
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
(see Note 19)
~>-
VIL
VOH
VOL
TMS4C1027
1 048 576-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
static column decode mode read cycle timing
tw(RH)
---.l
!+-
t-.~f------------tw(RL)P ------------~.I I
RAS
N..~
1-
tt~~
. I
CAS
I~
!!
I I
~
I
VIH
if'.~VIL
':
~
i
II
I I
td(RLCL)
I!~:!~!~--
,
II I
!+- th(RA)
!~!++-th(R~CA) ~
~ ~ t~U(RA)
I
*--tc(rd)SC
~
: :
,._ _ _ _
AO-A9
th(RHCA) ~
~tsU(CAR) ~
I
::
!+-
: :
I
Column
I
:
~ta(CA) ~
I
th(CAa)~
I
VOH
a------f\
VOL
(see Note 19)
NOTE 19: Output may go from high-impedance to an invalid state prior to the specified access time.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-55
TMS4C1027
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
static column decode mode early write cycle timing
~ tw(RH)
:~
"AS
N
-~ !'-tt
I=
I j+-- td(RLCH)
---.0"1
iI
14- tw(CL)
.'1 td(RLCL)
I tIIII
I
CAS
~j
i i 1.{
--., I4l- tSU(R~)
.1
-.I
i
Y
;
\:\
A~A9 ~
W
::
I I I
'I I
tsu(CA)
I4r t~(RLCA)
I I
I
td(RLWL2)
/
I I
~ ~ tsu(O)
I
I
~
i4- tc(W)SC
I'"
I
I 14-- th(CA) ~
I ,
~ I+-
~
\l
tw(WL)
~ th(O)
,
I
r-
i
tw(WH)
~
.:
l~
I
I~
~
i
"\'----J
~
COlumn:
I
I
~
14 I
::
I ;,-1-:"--II~\
I
jl
~,
~
1"- :::
~ I
tfl(CHRL)
~ tw(CH) -.:
-.! 1+ tsu(WHCH)
I
I
td(CARH)
I
I+-
j@
Column
~V~Ii-\1\:
I
I
I
I
/_
,
14- t.h(RA)
tsu(CA) -.!
I ~,
,I th(RLCA)
.'
I
III
l~th(CA)-.!
I
I~
r:
:
..J I
14,
td(CLRH)
I
~
I
I
~
I
~
tw(RL)P
14-
'--
I I
th(RHC~) ~ 14-
II~
I
I
COIU+: _
I I
.1 tsu(WCH)
I
..~ tsu(WRH)
,
\l
/
~--------
I
tIIII--+ th(RLO) ~
I
I
o
Q
----------------HI-Z ----------------
TEXAS •
INSTRUMENTS
5-56
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
VIH
VIL
:::
1MS4C1027
1 048576-811 DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
static column decode mode late write cycle timing
IIIII~I-------------
RAS
~l~_____________________________________________________
~
-
CAS
tw(RL)P - - - - - - - - - - - - . 1
--.I
f.-
td(RLCL)
I I
~ tsu(RA)
:1
I
tt
~th(RA)
th(RLCA)
---.!
Column
AO-A9
141---_ _11-
~ tc(W)sc
td(RLCA)
I~
I
tsu(CA) ~
LIN I
w(j
I
I I
~tSU(D)~
o
Q
I
§§§2§X
th(RLD)
Valid In
~ tsu(WRH) ~
I
I I
~ tw(WH) ~ I
\l
~
~--------~
I
~I I~
td(RLWL2) I
~~~~""
--t.!
~ th(CA)
I
~I tw(WL)
VIH
VIL
I
~I
Ict-- th(D) ~
Valid
~'--_ _
_ In
__
} @ ( v a l l d In
X{§»)
)
-----~(~_____________________I_nd_e_te_rm_i_na_t_e____________________~
TEXAS
VIH
-J
VIL
VOH
VOL
-III
INSlRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-57
TMS4C1027
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
static column decode mode read-modify-write cycle timing with CAS cycling
tw(RH)
tw(RL)P
liliiii
~!
RAS
!I
~
I rI
I
I I
---.I ~ tsu(RA)
I
~
I.
Y
N
I I
~I
1
I
I I
~
I
I
1
1
I
Iii
I
~I
tc(rdW)SC
-r.! ~td(CLWL)
I
tsu(rd)
~
I I
I'"
I
I
cOlumn:
---.I
1
~I
I
I
I
II
II
tsu,(D)I~ I
I
I
I I I
tsu(CA) ~
I
I
I I
~ th(D)
~
I
1
I
I
I
I
I
I
I
----.!
I
I·
liliiii
I
I
I
1
I
I
1
~
I
14- ta(C)
~
ta(R)
td(CLZ)
1
~I 1
1 1
1 141.--......-
~I
I
I.
1
:r-__
~
Q-----------()(
(see Note 19)
NOTE 19:
Output may go from high·impedance to an invalid data state prior to the specified access time.
TEXAS
-III
INSTRUMENTS
5·58
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
i
II
I
++--.JI
I
I
I
VIH
~
VIL
i
I
I I
I
I
I
I
I
I.
I
I
I
X
ill
I
ta(CA) --I4--~
~ ta(CA) --.l
~ta(WHQ)~
~I
1I
Valid In
1
~I
1,..-.,..1...1_ _-
I
J...w
~t I
I
I rJ '~I s4(WCI"O
th(WLCA~)
I D)
I :
1
~------~--~ ~~~Ir---~--~
D
VIL
cOlu~n:: ~ :::
1I
~td(W<;l)~
ta(WLQ)
~----I'--1i th(~
I
~ tsu(WCH)
I
I
I
~I
td(WLCA)
~~~~~~I-+--k:1 I~ tw(WL) ~
W
14- tsu(CAR)
I
I
VIH
I I
I I
th(RHCA) ~
Ith(CAQ)~
liliiii
1
·1
I.
'----{
td(CAWL)
-a..!rJ
~
\1
I
I
I
~
tw(CA)
1
~ td(RLCA) ---.I~I
~ th(CA)
I
~td(RLWL) I
V
I
~
Column
I I
I I
td(CHRL)
I
~:
th(RLCA)
th(RA)
A~A9 X :ROW ~::
I
td(CLRH)
*- tw(CH) ~
I
I I
I
I
Ii
I
~
td(RLCH)
~ td(RLCL) ~
I+I
I
Ilr-\
! !\.
X~
I~
r-tt
-+I
~I
I
1
I
1
I
~ tSU~RH)
'r"
·~I
I
I
1MS4C1027
1 048576-811 DYNAMIC RANDOM-ACCESS MEMORIES
SMGS024F -
MAY 1986 -
REVISED NOVEMBER 1990
static column decode mode with read-modify-write cycle timing
Column
AO-A9
1 tsu(rd) ~
1
:4
,
~
,
,
,
'4
o
td(RLf~)
'
~
II
I
h(CA)
td(CAWL)
th(CAQ)~
tc(rdW)SC
,.
:
I'"
.:
:4-twIWL)~
Valid In
1
,
v.lldln
I
;
~ta(C)
~taCNHQ)~
:
1
1
~ta(CA)~
~.{
,
1
:
!J
VIH
- - - - -...-~
VIL
~
VIH
I
~
~
,
,
~~~ ~ V~~~
TEXAS
VIL
I
~thCNQ)
I
.1
ta(R)
Q ____________
'
,'
1~
_
1
~II--!~~'
,
-----jt>j,
,
1 1
,
,
I,
I
WRITE
(MAX)
(MAX)
(MAX)
(MAX)
'4SC12S/C13S-70
70 ns
25 ns
40 ns
130 ns
'4SC12S/C13S-S0
SO ns
25 ns
40 ns
150 ns
'48C128/C138-10 100 ns
30 ns
45 ns
180 ns
W
RAS
VSS
DQ8
DQ7
DQ6
OQ5
CAS
CYCLE
•
•
•
•
•
•
•
•
•
NC
AO
A1
A2
A3
TMS48C128 - Enhanced Page Mode
Operation with CAS-Before-RAS Refresh
TMS48C138 -
Vec
G
A8
A7
A6
A5
A4
tThe package is shown for pinout reference only.
Write-Per-Bit Operation
Long Refresh Period ...
512-Cycle Refresh in 8 ms (Max)
PIN NOMENCLATURE
AO-AS
3-State Unlatched Output
CAS
D01-D08
Lower Power Dissipation
G
Texas Instruments EPICTI" CMOS Process
NC
RAS
All Inputs and Clocks Are TTL Compatible
Vi
VCC
High-Reliability Plastic 24/26-lead
300-Mil-Wide Surface Mount (SOJ) Package
VSS
Address Inputs
Column-Address Strobe
Data In/Data Out
Data-Output Enable
No Connect
Row-Address Strobe
Write Enable
5-V Supply
Ground
Operating Free-Air Temperature Range
... O°C to 70°C
description
The TMS48C128 and the TMS48C138 series are high-speed, 1 048 576-bitdynamic random-access memories
organized as 131 072 words of eight bits each. They employ state-of-the-art EPICTM (Enhanced Process
Implanted CMOS) technology for high performance, reliability, and low power at a low cost.
These devices feature maximum RAS access times of 70 ns, 80 ns, and 100 ns. Maximum power dissipation
is as low as 413 mW operating and 11 mW standby on 80 ns devices.
The EPICTM technology permits operation from a single 5-V supply, reducing system power supply and
decoupling requirements, and easing board layout. Icc peaks are 140 mA typical, and a - 1-V input voltage
undershoot can be tolerated, minimizing system noise considerations.
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS48C128 and TMS48C138 are offered in a 300-mil 24/26-lead plastic surface mount SOJ (OJ suffix)
package. This package is characterized for operation from O°C to 70°C.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA documents contain Information current
IS of publication date. Products conform to specifications per
the terms of Texas Instruments standard warranty.
Production processing does nat necessarily Include testing
ofalt parameters.
TEXAS
~
Copyright © 1990, Texas Instruments Incorporated
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-63
TMS48C128, TMS48C138
131 072-WORD BY 8-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMGS128A -
DECEMBER 1989 -
REVISED DECEMBER 1990
operation
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is thus eliminated. The
maximum number of columns that may be accessed is determined by the maximum RAS low time and the CAS
page cycle time used. With minimum CAS page cycle time, all 256 columns specified by column addresses AO
through A7 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS48C128 to operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as column address is valid rather than when
CAS transitions low. This performance improvement is referred to as "enhanced page mode." Valid column
address may be presented immediately after tRAH (row address hold time) has been satisfied, usually well in
advance of the falling edge of CAS. In this case, data is obtained after tCAC max (access time from CAS low)
if tCAA max (access time from column address) has been satisfied. In the event that column addresses for the
next page cycle are valid at the time CAS goes high, access time for the next cycle is determined by the later
occurrence of tCAC or tCAP (access time 'from rising edge of CAS).
write-per-bit operation (TMS48C138)
The Wpin selects the write-per-bit option. The TMS48C138 is equipped with two modes of write operations. If
W is held low on the falling edge of RAS (during a random access operation), the write-per-bit mode is enabled.
When RAS has latched the write-per-bit mask on-chip, input data is driven onto the DO pins and is latched on
the falling edge of the latter of CAS or W (for early write operation, W can remain low for the entire RAS low
period). If a 0 is strobed into a particular I/O pin on the falling edge of RAS, then the write circuits for that particular
I/O will be inhibited and data will not be written from that I/O. If a 1 is strobed into a particular I/O pin on the falling'
edge of RAS, then the write circuits for that particular I/O will not be inhibited and data will be written from that
I/O.
Important: The write-per-bit operation is selected only if W is held Iowan the falling edge of RAS. If W is held
high on the falling edge of RAS, the write-per-bit function is not enabled and the write operation is identical to
a standard x4 or x8 DRAM, with aliI/Os being written by the data appearing on the DO pins when the latter of
W or CAS is brought low.
Table 1. State When RAS Falls
W
DOl-DOS
MODE
1
X
Write enable at D01-D08
0
1
Write to DO enabled
0
0
Write to DO disabled
,
TEXAS.
INSlRUMENlS
5-64
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS48C128, TMS48C138
131 072-WORD BY 8-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMGS128A -
DECEMBER 1989 -
REVISED DECEMBER 1990
address (AD through A8)
Seventeen address bits are required to decode 131 072 storage cell locations. Nine row-address bits are set
up on pins AO through A8 and latched on to the chip by the row-address strobe (RAS). Then eight
column-address bits are set up on pins AO through A7 and latched onto the chip by the first column-address
strobe (CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to
a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select
activating the output buffer, as well as latching the address bits into the column-address buffers.
write enable
rN>
The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from the standard
TTL circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes
low prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle, permitting
a write operation with IT grounded.
data in (001-008)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early write cycle, W is brought low prior to CAS and
the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed write or
read-modify-write cycle, CAS will already be low, thus the data will be strobed in by W with setup and hold times
referenced to this signal. In a delayed write or read-modify-write cycle, IT must be high to bring the output buffers
to high impedance prior to impressing data on the I/O lines.
data out (001-008)
The three-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS and IT are brought low. In a read cycle the output becomes valid after the access time interval tCAC
that begins with the negative transition of CAS as long as tRAC and tCAA are satisfied. The output becomes valid
after the access time has elapsed and remains valid while CAS and IT are low. CAS or G going high returns it
to a high-impedance state.
output enable
(<3)
IT controls the impedance of the output buffers. When IT is high, the buffers will remain in the high-impedance
. state. Bringing IT low during a normal cycle will activate the output buffers, putting them in the low-impedance·
state. It is necessary for both RAS and CAS to be brought low for the output buffers to go into low-impedance
state. Once in the low-impedance state, they will remain in the low-impedance state until either IT or CAS is
brought high.
.
TEXAS
-1!1
INSTRUMENTS
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•
HOUSTON, TEXAS 77001
5-65
TMS48C128, TMS48C138
131 072-WORD BY 8-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMGS128A- DECEMBER 1989 -
REVISED DECEMBER 1990
refresh
A refresh operation must be performed at least once every eight milliseconds to retain data. This can be achieved
by strobing each of the 512 rows (AO-AS). A normal read or write cycle will refresh all bits in each row that is
selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, thus conserving power
as the output buffer remains in the high-impedance state. Externally generated addresses must be l:lsed for a
RAS-only refresh. Hidden refresh may be performed while maintaining valid data at the output pin. This is
accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period,
similar to a RAS-only refresh cycle.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS (see parameter tCSR) and holding it
low after RAS falls (see parameter tCHR). For successive CAS-before-RAS refresh cycles, CAS can remain low
while cycling RAS. The external address is ignored and the refresh address is generated internally. The external
address is also ignored during the hidden refresh option.
power-up
To achieve proper device operation, an initial pause of 200 f!s followed by a minimum of eight initialization cycles
is required after power-up to the full VCC level.
logic symbol t
RAM 12SK x8
AO
A1
A2
A3
A4
AS
A6
A7
AS
9
20092100
10
11
12
14
0
A 131 071
15
16
17
18
200172108
6~
21
W 5
G 19
oa1
1
oa2
oa3
oa4
oa5
oa6
2
OQ7
oa8
....
3
4
f
1-
>
C20[ROW]
G23 [REFRESH ROW]
24[PWR OWN]
>
C21[COL]
G24
&
f> 23C22
24,25EN
,
r-. G25
4.
...
.... .....
r
A220
\726
A,Z26
~
....
.... .....
~
~
22
23
.... ..
.....
~
~
24
25
~
....
....
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
TEXAS •
INSTRUMENTS
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TMS48C128, TMS48C138
131 072-WORD BY 8-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMGS128A - DECEMBER 1989 -
REVISED DECEMBER 1990
functional block diagram
I
).
+ + + +
Timing And Control
~J
Row
Address
Buffers
(9)
rr;=
AO
12BKI12BK
Row
Decode
Array
Array
:,..
Sense Amplifiers
..
A4
A5
A6
A7
AB
12BKI12BK
1-
A1
A2
A3
I
~
Column
Address
Buffers
(B)
....... -~
....... '--~
....... -~
....... '--~
M
r--v
Column Decode
....... c--~
....... '-~
....... c--~
-
....... I--~
Sense Amplifiers
12BKI12BK
Array
Row
Decode
12BKI12BK
~
~
In
Reg
I/O
Muxlng
Out
Reg
Array
•
8
DO 1DO B
absolute maximum ratings over operating fr~e-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee ............................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 rnA
Power disSipation ........................................................................... 1 W
Operating free-air temperature range ..................................................
to 70 0
Storage temperature range ... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°e to 150 0 e
ooe
e
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device atthese or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliabifity.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
VCC
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage (see Note 2)
TA
Operating free-air temperature
MIN
NOM
MAX
4.5
5
5.5
0
UNIT
V
V
2.4
6.5
-1t
0.8
V
0
70
°c
V
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
t Characterized at 5.5 V VCC.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443
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HOUSTON, TEXAS 77001
5-67
TMS48C128, TMS48C138
131 072-WORD BY 8-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMGS128A- DECEMBER 1989 -
REVISED DECEMBER 1990
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
10H =-5 mA
VOL
Low-level output voltage
10L = 4.2 mA
II
Input current (leakage)
10
ICC1
'4SC12S-70
'4SC12S-S0
'4SC13S-70
'4SC13S-S0
'4SC13S-10
MIN
MIN
MIN
MAX
'4SC12S-10
MAX
2.4
2.4
UNIT
MAX
2.4
V
0.4
0.4
0.4
V
VI = 0 to 5.S V, VCC = 5 V,
All other pins = 0 to VCC
±10
±10
±10
JlA
Output current (leakage)
Va = 0 to VCC, VCC
CAS high
±10
±10
±10
JlA
Read/write cycle current
tRWC = minimum, VCC = 5.5 V
85
80
70
mA
ICC2
Standby current
After 1 memory cycle,
RAS and CAS high, VIH
2
2
2
mA
ICC3
Average refresh circuit
(RAS-only or CSR)
tRWC = minimum, VCC = 5.5 V,
RAS cycling, CAS high
(RAS-only), RAS low after CAS
low (CSR)
80
75
65
mA
ICC4
Average page current
tpc = minimum, VCC = 5.5 V,
RAS low, CAS cycling
60
50
45
mA
= 5.5 V,
= 2.4 V
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Ci(G)
Input capacitance, output-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 3: VCC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
PARAMETER
'4SC12S-70
'4SC12S-S0
'4SC13S-70
'4SC13S-S0
MIN
MIN
MAX
MAX
'4SC12S-10
'4SC13S-10
MIN
UNIT
MAX
tCAC
Access time from CAS low
25
25
30
ns
tCAA
Access time from column address
40
40
45
ns
tRAC
Access time from RAS low
70
80
100
ns
tGAC
Access time from Glow
25
25
30
ns
tCAP
Access time from column precharge
45
45
50
ns
tOFF
Output disable time after CAS high (see Note 4)
0
20
0
20
0
25
ns
tGOFF
Output disable time after G high (see Note 4)
0
20
0
20
0
25
ns
NOTE 4: tOFF and tGOFF are specified when the output is no longer driven.
TEXAS •
INSTRUMENTS
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TMS48C128, TMS48C138
131 072-WORD BY 8-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMGS128A -
DECEMBER 1989 -
REVISED DECEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
'4SC12S-70
'4SC13S-70
MIN
MAX
'4BC12S-S0
'4BC13S-S0
MIN
MAX
'4SC12S-10
'4SC13S-10
MIN
UNIT
MAX
tRC
Read cycle time (see Note 6)
130
150
180
ns
twc
Write cycle time
130
150
180
ns
tRWC
Read-write/read-modify-write cycle time
185
205
245
ns
tpc
Page-mode read or write cycle time (see Note 7)
50
50
55
ns
ns
tpCM
Page-mode read-modify-write cycle time
105
105
120
tcp
Pulse duration, CAS high
10
10
10
tCAS
Pulse duration, CAS low (see Note 8)
25
tRP
Pulse duration, RAS high (precharge)
50
tRAS
Non-page-mode pulse duration, RAS low (see Note 9)
70
10000
80
10000
tRASP
Page-mode pulse duration, RAS low (see Note 9)
70
100000
80
100000
twp
Write pulse duration
15
15
15
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
10000
25
10000
60
ns
10000
ns
100
10000
ns
100
100000
30
70
ns
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
tDS
Data setup time before W low (see Note 10)
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
ns
twcs
W-Iow setup time before CAS low (see Note 11)
0
0
0
ns
tCWL
W-Iow setup time before CAS high
20
20
25
ns
tRWL
W-Iow setup time before RAS high
20
20
25
ns
tCAH
Column-address hold time after CAS low (see Note 10)
15
15
20
ns
tRAH
Row-address hold time after RAS low
10
12
15
ns
tAR
Column-address hold time after RAS low (see Note 12)
55
60
70
ns
tDH
Data hold time after CAS low (see Note 10)
15
15
20
ns
tDHR
Data hold time after RAS low (see Note 12)
55
60
70
ns
tRCH
Read hold time after CAS high (see Note 13)
0
0
0
ns
ns
tRRH
Read hold time after RAS high (see Note 13)
0
0
10
twCH
Write hold time after CAS low (see Note 11)
15
15
20
ns
twCR
Write hold time after RAS low (see Note 12)
55
60
70
ns
Continued next page.
NOTES: 5. Timing measurements are referenced to VIL max and VIH min.
6. All cycle times assume tT =5 ns.
7. To guarantee tc(P) min, tsu(CA) should be greater than or equal to tw(CH).
8. In a read-modify-write cycle, tCWD and tCWL must be observed. Depending on the user's transition times, this may require additional
CAS low time (tCAS).
9. In a read-modify-write cycle, tRWD and tRWL must be observed. Depending on the user's transition times, this may require additional
RAS low time (tRAS).
10. Later of CAS or IN in write operations.
11. Early write operation only.
12. The minimum value is measured when tRCD is set to tRCD min as a reference.
13. Either tRCH or tRRH must be satisfied for a read cycle.
TEXAS •
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POST OFFICE BOX 1443
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5-69
TMS48C128, TMS48C138
131 072-WORD BY 8~BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMGS128A- DECEMBER 1989 -
REVISED DECEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5) (concluded)
MIN
'48C128·10
'48C138·10
'48C128·80
'48C138·80
'48C128·70
'48C138·70
MAX
MIN
MAX
MIN
UNIT
MAX
tGH
G command hold time
20
20
25
ns
tCSH
Delay time, RAS low to CAS high
70
80
100
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
25
25
30
ns
tCWD
Delay time, CAS low to W low (see Note 14)
55
55
65
tRCD
Delay time, RAS low to CAS low (see Note 15)
20
45
22
55
25
70
ns
tRAD
Delay time, RAS low to column address (see Note 15)
15
30
17
40
20
55
ns
tRAl
Delay time, column address to RAS high
40
40
45
tCAl
Delay time, column address to CAS high
40
40
45
ns
tRWD
Delay time, RAS low to W low (see Note 14)
100
110
135
ns
70
70
80
ns
0
0
0
ns
ns
ns
tAWD
Delay time, column address to W low (see Note 14)
tCLZ
Delay time, CAS low to DO in low-Z
tGDD
Delay time, G high before data at DO
20
20
25
ns
tGSR
Delay time, G low to RAS high
25
25
30
ns
tCHR
Delay time, RAS low to CAS high (see Note 16)
15
20
25
ns
tCSR
Delay time, CAS low to RAS low (see Note 16)
10
10
10
ns
tRPC
Delay time, RAS high to CAS low (see Note 16)
0
0
0
ns
tWBS
Write-per-bit setup time
0
0
0
ns
tWBH
Write-per-bit hold time
10
10
10
ns
twos
Write-per-bit selection setup time
0
0
0
ns
tWDH
Write-per-bit selection hold time
10
10
10
tREF
Refresh time interval
tT
Transition time
NOTES: 5.
14.
15.
16.
3
50
Timing measurements are referenced to Vil max and VIH min.
Read-modify-write operation only.
Maximum value specified only to guarantee access time.
CAS-before-RAS refresh only.
TEXAS
"J1
INSTRUMENTS
5-70
8
8
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
3
50
3
ns
8
ms
50
ns
TMS48C128, TMS48C138
131 072·WORD BY 8·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMGS128A- DECEMBER 1989 -
REVISED DECEMBER 1990
PARAMETER MEASUREMENT INFORMATION
1.31 V
~
Output Und"T••t
VCC
R L ,2'."
~
CL=100pF
=5V
Output Under Test
T
CL=100pF
(a) Load Circuit
(b) Alternate Load Circuit
Figure 1. Load Circuits For Timing Parameters
read cycle timing
NOTE 17: Output may go from high impedance to an invalid data state prior to the specified access time.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
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5-71
TMS48C128, TMS48C138
131 072·WORD 8Y 8·81T HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMGS128A- DECEMBER 1989 -
REVISED DECEMBER 1990
early write cycle timing
TEXAS •
INSTRUMENTS
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TMS48C138
131 072-WORD BY '8-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMGS128A- DECEMBER 1989 -
REVISED DECEMBER 1990
early write cycle (write-per-bit selected)
AQ·AS
tWBS ~
I
w~
DQ1·
DQS
TEXAS ~
INSTRUMENTS
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•
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5-73
TMS48C128, TMS48C138
131 072-WORD BY 8-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMGS128A -
DECEMBER 1989 -
REVISED DECEMBER 1990
NOTE 10: Later of CAS or W in write operation.
TEXAS ~
INSTRUMENTS
5-74
POST OFFICE BOX 1443
•
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TMS48C138
131 072-WORD BY 8-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMGS128A -
DECEMBER 1989 -
REVISED DECEMBER 1990
write cycle (write-per-bit selected)
AO-AS vvvvvn
TEXAS
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INSlRUMENTS
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5-75
TMS48C138
131 072·WORD BY 8·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMGS128A- DECEMBER 1989 - REVISED DECEMBER 1990
read-modify-write cycle (write-per-bit selected)
.~------------------------tRWC----------------------~~
I ~~-------------------tRAS------------------~~1 ~tRP~
_ _ _~I
~
~
tAR
1
I
I
N i t ~
~tCRP
r-rj4-tRCo~~ I
----------.-1~~ :
I I
I 14
I
I
tcsH---------------~.1
I
VIH
I "---VIL
I
I:
I
::
H-
tCRP
tASR
j4-
~
-.I
I
r-~~
..---+-1- - - - - - - - tRSH
\tt--t--+l-----:,
L~
t SC
I
tCAS
----~yl
tCAH
: !
1
~~~~~~~~~~~~~~~~~~~~~VIH
AQ-A8
~
~--~---J~~~~~~~~~~~~~~~~~~~~~VIL
i4-+-
, I I
tR~O 1 14
~ 11
tWBS
~
m'
III~
w~ll
1 I
II
G
001008
[
.1
I:"
~ 14- tRlcS
I 1
tWRH ~
r l1li I
~ ~
tAWO
~
N
tcwo
"
I I
.1 ..
~ - -...
~- twp
tRWO
I
II
N
I
14-- tCAA - t l
1
I
~
WOS -+j
1
14- tCAC
~ twOH
1
l1li
I
tRAC
.
I
I
If
VIH
:1
I
-.I
I
trioo l1li
, I.---.t-toH
I ,
., I
I
I
I 14-41- tos 1
~
I
1
I
I I
~ Mask
~Dataln: ~ ~
Valid
Data In
VIL
,
~VIH
~
VIL
.
-----OPEN
•
I
,
~
'@'\
)>-________________
Valid
Data Out,
TEXAS
POST OFFICE BOX 1443
•
~H
VOL
~
INSIRUMENlS
5-76
I
I I
VIL
~Lt
II
~ G,...A_C_ _ _ _"I"'"I+ I - - - - - - - - - - - - - - V I H
~
1
.1 tl~WL
It- tRWL --+I
HOUSTON, TEXAS 77001
TMS48C128, TMS48C138
131 072-WORD BY 8-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMGS128A -
DECEMBER 1989 -
REVISED DECEMBER 1990
read-modify-write cycle timing
.
i4
tRWC ------------Jof~
I
I
I 1J4.. ---------tRAS-----------lif~
I
~
RAS---"N.
~ ~I
I
IT
J4-i4-------tRSH-------+l;ri~~
~~-----------t
_ _ _ _ _~N
tRCD ~
CAS
~
~!~I======~tl-----tCSH-------~~
____ I tf-.
CAS
N
: I
I j t - t A R +-F=ii
tRAH +-.I !4j4 i
.,
~
II tASR ~tAS'
I
I
~I______~
}1:~
I I..-!--tcp~
j4---- tCWL ~
I
tCAH
14
~
AO-AS
TEXAS -If
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5-77
TMS48C128, TMS48C138
131 072·WORD BY 8·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMGS128A- DECEMBER 1989 - REVISED DECEMBER 1990
enhanced page-mode read cycle timing
-.!
I
I
I
I
AO-A8~
NOTES: 17. Output may go from high impedance to an invalid data state prior to the specified access time.
18. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
19. Access time is tCAP or tCAA dependent.
TEXAS
-I!I
INSTRUMENlS
5-78
POST OFFICE BOX 1443
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TMS48C128, TMS48C138
131 072-WORD BY 8-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMGS128A - DECEMBER 1989 -
REVISED DECEMBER 1990
enhanced page-mode write cycle timing
NOTES:20. A read cycle or a read-modify-write cycle can be intermixed with the write cycles as long as the read and read-modify-write
timing specifications are not violated.
21. Referenced to CAS or \fl, whichever occurs last.
TEXAS ~
INSTRUMENTS
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5-79
TMS48C128, TMS48C138
131 072-WORD BY 8-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMGS128A- DECEMBER 1989- REVISED DECEMBER 1990
enhanced page-mode write cycle (write-per-bit selected)
--------------------tRAsP--------------------~~
tRP ~
I
I
AO·A8
~ ~
I
I
I
I
twos
~
~)j
I
I:~I
II
~ tOHR ~
tos -.I I4-t-
~
I
I
I
twI?H-.lj4- I
OQ1·
OQS
I
tos
I
If-I
I
-.j
I
I
r
I
I
--.I
tOH
IV ",,, " " "
I
I4-t-
I I
I
tos
I
tGOO .
I~ ~I
t
~ OH
Valid
,,,,,I Oata In I
I I
~
I
I
I
~
------
~
-
TEXAS •
INSlRUMENlS
5-80
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
XXXXXXXXXXXXXXX VIH
II~v
It-!IL
I
I
I.-
."--I~oI-:
Valid
Oata In
t
OH
~I
"..~~~~~
~
VIH
VIL
TMS48C128, TMS48C138
131 072-WORD BY 8-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMGS128A- DECEMBER 1989 -
REVISED DECEMBER 1990
enhanced page-mode read-modify-write cycle timing
14I I
tRP --.j
~1~------------------------tRASP----------------------~~
RAS
~!
} I r \I.
i~~I~----t-CS-H-----~I---------------""';I1 I:~
I 14-----+!
I
14-14-------- tRSH ----~~I
I
I I
: I
CAS
~
I
!
HI
I
tRCO
i4---
tR~H ~
I
AD-AB
14I I
-.J
I I I
tWBH ~
I
XII
Wy
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:
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I
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r
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:
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I
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I
I
I
I
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-.j
---y------.I
~
I
I
I
I
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: Column
iI·i4I~ tRCS
:4
I Iit--+: - - -
I
I
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--.II4-+-
tCRP
+-1
I I
I tAR - . !
tRAO ~ I I :
I
~
tWBS~
~ tCAS ~ 14-14-----*~I- tcpl
tPCM --'-:---JoI~
I
I
r')\l
tASR
i4
~
VIH
VIL
I
I
~
/XXXXXXXXX
VIH
I ~""""'~~~~~
tos --'1 If+
VIL
~
I -+o1~1--*- tOH
I
,...-.:~'":':""':""S.. ..z.~~---i. ft:7<,~~~
VIH
tCAC
I4-r-~- tGOO
~1111----l+--tGOFF
I
:
fr------Vr---------
VIH
V!L
NOTES: 17. Output may go from high impedance to an invalid data state prior to the specified access time.
22. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write cycle timing specifications
are not violated.
TEXAS
-1!1
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-81
TMS48C128, TMS48C138
131 072·WORD BY 8·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMGS128A -
DECEMBER 1989 -
REVISED DECEMBER 1990
enhanced page-mode read-modIfy-write cycle (write-per-bit selected)
~i
i~
tAASP
VIH
}! !'-
!{
AAS
i: :
I 1.1
VIL
I 14
tCSH~ I
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I
14
tpCM t t = : - I
14
tASH - . I
I
AP
-*.1- tACO
I
I tcp
I
j+- t' AP -.I
_
I
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I4-tCAS---+I
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CAS tAAOI~1
I
I I
I I
I
I
I
~ .J
I I
I
I I
I I
I I
~ .-I
VIL
~ j4- tRt.H
I
~
ttt
I
--r-'"
I' tCAH
I
t
~
I 1'~
j4- tCAH I
I
CAH
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I
ASA II II -.j'--ltApc
I
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I
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I~ I
I
I I
1
-t-1-t'1--+-I-----
j4-- tWOH I I
I I
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I
=+I I+- tcLZ
I
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I Mask'"
I~
~VIH
Col
Add
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I .
I I
I
I I
I·
I
I
-.I ~ tCLZ I
Data
Data
VOL
VIH
1"_.1"_1"_1"_
TEXAS
-1!1
INSlRUMENTS
5-82
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
VIL
TMS48C128, TMS48C138
131 072-WORD BY 8-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMGS128A- DECEMBER 1989 - REVISED DECEMBER 1990
RAS-only refresh timing
VIH
VIL
VIH
VIL
VIH
Row
VIL
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-83
TMS48C128, TMS48C138
131 072-WORD BY 8-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMGS128A -
DECEMBER 1989 -
REVISED DECEMBER 1990
hidden refresh cycle
RAS
N
14- Refresh Cycle ~
14- Memory Cycle ~
14- Refresh Cycle --.t
1
14- tRP -.l
14- tRP -.l
1
14~
14~
I tRAS I
I
\
;-II----{
/
tCHR
I
14
N~
I 1 1 ~
--tj ~ tA~R I
1
tCAS
I
1
4~tRAH
l4IU
~
"----'
I
I 1
CAS
I
V
\l
I
I 1
I
I tRAS I
Vt
I
14
VIH
VIL
~
~
!y!r -
I
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I
1
I
1
VIH
VIL
~
~
A~A.~Z]nm~~~::
I
~
t
RCS
I1
wW:
1
I
~
14- tRRH
I
I
~
'02§0005]i{@~~~::
1
!:
1 1-.1 ~ tCAC
1
~ tCAA
tRAC
~
tOFF -.t
g~~. ------c~
~
G~
Valid Data Out
;;
VOH
VOL
I4--tGOFF~
I4--tGAC
~VIH
r)~-VIL
-
.
TEXAS
-III
INSTRUMENTS
5-84
r
14-
.I~---------------""""~T-~------~I
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS48C128, TMS48C138
131 072-WORD BY 8-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMGS128A -
DECEMBER 1989 -
REVISED DECEMBER 1990
automatic (CAS-before-RAS) refresh cycle timing
~~----------------tRC----------------~
.1
~ tRP ----.I ~'4----- tRAS
RAS
----IiJI '
1
1
V
I _________________________- J
~
l.-
tRPC -.I
,
tCSR, ~
CAS
N
------.t
~
,I,X
~
~
I-t-r
~14- - - - tCHR ---~
VIH
VIL
~
Y
~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
VIH
VIL
001- _____________________ HI-Z ______________________
VIH
DOS
VIL
. TEXAS-I!1
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-85
TMS48C128, TMS48C138
131 072-WORD BY 8-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMGS128A- DECEMBER 1989 -
REVISED DECEMBER 1990
TEXAS ~.
INSlRUMENlS
5-86
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
1MS44100
4 194 304-811
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 OB -
This Data Sheet is Applicable to All TMS441 ODs
Symbolized With Revision "B" and Subsequent
Revisions as Described on Page 5-106.
• Single 5-V Power Supply (±10% Tolerance)
• Performance Ranges:
SO Package t
(Top View)
VSS
Q
A9
W
RAS
NC
A1D
CAS
NC
A9
D
D
READ
TIME
TIME
TIME
OR WRITE
(tRAC)
(MAX)
(tCAC)
(MAX)
(tM)
CYCLE
(MAX)
(MIN)
TMS44100-60
60 ns
15 ns
30 ns
110 ns
TMS441 00-70
70 ns
1S ns
35 ns
130 ns
TMS44100-S0
SO ns
20 ns
40 ns
150 ns
TMS441 00-1 0'
100 ns
25 ns
45 ns
1S0 ns
REVISED JANUARY 1991
OM and OJ Packages t
(Top View)
• Organization ... 4 194 304 x 1
ACCESS ACCESS ACCESS
SEPTEMBER 1989 -
AD
A1
A2
A3
A8
A7
A6
A5
A4
VCC
Q
RAS
NC
AD
A2
VCC
A5
A7
CAS
VSS
W
A1D
NC
A1
A3
A4
A6
A8
tThe packages shown are for pinout reference only.
• Enhanced Page-Mode Operation for Faster
Memory Access
- Higher Data Bandwidth than
Conventional Page-Mode Parts
- Random Single-Bit Access Within a Row
With a Column Address
PIN NOMENCLATURE
AO-A 10
CAS
D
NC
Q
RAS
• CAS-Before-RAS Refresh
IN
• Long Refresh Period ...
1024-Cycle Refresh in 16 ms (Max)
VCC
VSS
Address Inputs
Column-Address Strobe
Data In
No Connection
Data Out
Row-Address Strobe
Write Enable
5-V Supply
Ground
• 3-State Unlatched Output
• Texas Instruments EPIC ™ CMOS Process
• High-Reliability Plastic 300-mil and 350-mil
20/26-Lead Surface Mount (SOJ) Packages
and a 20-Pin Zig-Zag In-line Package
• All Inputs/Outputs and Clocks are TTL
Compatible
• Operating Free-Air Temperature Range
... O°C to 70°C
• Low Power Dissipation
description
The TMS44100 series are high-speed 4 194 304-bit dynamic random-access memories, organized as
4 194304 words of one bit each. They employ state-of-the-art EPIC ™ (Enhanced Process Implanted CMOS)
technology for high performance, reliability, and low power at a low cost.
These devices feature maximum RAS access times of 60 ns, 70 ns, 80 ns, and 100 ns. Maximum power
dissipation is as low as 360 mW operating and 6 mW standby.
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Oata out is unlatched to allow greater system flexibility.
The TMS44100 is offered in a 300-mil 20/26-lead plastic surface mount SOJ package (OJ suffix), a 350-mil
20/26-lead plastic surface mount SOJ package (OM suffix), and a 20-pin plastic ZIP package (SO suffix). All
packages are characterized for operation from O°C to 70°C.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA documenls conlain Inlormalion
currenl IS 01 publlcallon dale. Products conlorm 10
speclficallons per Ihe terms oITelas Instruments standard
warranty. Production proceSSing does not necessarily
Include tesllng 01 all parameters.
Copyright © 1991. Texas Instruments Incorporated
TEXAS . .
INSlRUMENlS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
5-S7
TMS44100
4194304-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 OB - SEPTEMBER 1989 - REVISED JANUARY 1991
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is thus eliminated.
The maximum number.of columns that may be accessed is determined by the maximum RAS low time and the
CAS page cycle time used.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS441 00 to operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as the column address is valid rather than
when CAS transitions low. This performance improvement is referred to as enhanced page mode. Valid column
address may be presented immediately after row address hold time has been satisfied, usually well in advance
of the falling edge of CAS. In this case, data is obtained after tCAC max (access time from CAS low), iftAA max
(access time from column address) has been satisfied. In the event that column addresses for the next cycle
are valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence of tCAC
or tCPA (access time from rising edge of CAS).
address (AO through A10)
Twenty address bits are required to decode 1 of 4 194 304 storage cell locations. Eleven row-address bits are
set up on inputs AO through A 10 and latched onto the chip by the row-address strobe (RAS). The eleven
column-address bits are set up on pins AO through A 10 and latched onto the c:-Jip by the column-address strobe
(CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip
enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select activating
the output buffer, as well as latching the address bits into the column-address buffer.
write enable (W)
The read or write mode is selected through the write-enable 0N) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL
circuits without a pull-up resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle, permitting
common 110 operation.
data in (0)
Data is written during a write or read-write cycle. Depending on the mode of operation, the falling edge of CAS
or W strobes data into the on-chip data latch. In an early write cycle, W is brought low prior to CAS and the data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-write cycle,
CAS will already be low, thus the data will be strobed in by W with setup and hold times referenced to this Signal.
data out (Q)
The three-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating)
state until CAS is brought low. In a read cycle the output becomes valid after the access time interval tCAC that
begins with the negative transition of CAS as long as!B.6c and t~ satisfied. The output becomes valid after
the access time has elapsed and remains valid while CAS is low; CAS going high returns it to a high-impedance
state. In a delayed-write or read-write cycle, the output will follow the sequence for the read cycle.
refreSh
A refresh operation must be performed at least once every sixteen milliseconds to retain data. This can be
achieved by strobing each of the1 024 rows (AO-A9). A normal read or write cycle will refresh all bits in each row
that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, thus conserving
power as the output buffer remains in the high-impedance state. Externally generated addresses must be used
TEXAS
~
INSlRUMENTS
5-88
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TMS44100
4 194 304·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMHS410B -
SEPTEMBER 1989 -
REVISED JANUARY 1991
for a RAS-only refresh. Hidden refresh may be performed while maintaining valid data at the output pin. This
is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge
period, similar to a RAS-only refresh cycle. The external address is ignored during the hidden refr~sh cycles.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS [see parameter tc...s.sLand holding
it low after RAS falls [see parameter tCHR]' For successive CAS-before-RAS refresh cycles, CAS can remain
low while cycling RAS. The external address is ignored and the refresh address is generated internally.
power-up
To achieve proper device operation, an initial pause of 200 !-ls followed by a minimum of eight initialization cycles
is required after full V CC level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
test mode
An industry standard Design For Test (DFT) mode is incorporated in the TMS441 00. A CAS-before-RAS cycle
with W low (WCSR) cycle is used to enter test mode. In the test mode, data is written into and read from eight
sections of the array in parallel. Data is compared upon reading and if all bits are equal, the data out pin will
go high. If anyone bit is different, the data out pin will go low. Any combination of read, write, read-write, or
page-mode can be used in the test mode. The test mode function reduces test times by enabling the 4 meg
DRAM to be tested as if it were a 512K DRAM, where row address 10, column address 10, and also column
address a are not used. A RAS-only or CSR refresh cycle is used to exit the DFT mode.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
5-89
TMS44100
4 194 304·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMHS41 DB -
SEPTEMBER 1989 -
REVISED JANUARY 1991
logic symbol t
RAM 4096K x 1
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
9
10
11
30011/21 DO
12
14
15
16
17
>
18
5
r--...
24
2
1
31021/21010 ,.
~
C30[ROW]
G33 [REFRESH ROW]
34 [PWR OWN]
~
G34
r--...
o
0
4194303
22
3
w
A
C31 [COL]
&
~ 33C32
~ 33310
34 EN
A, 320
25
AV
Q
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
The pin numbers shown are for the 20/26 pin SOJ package.
functional block diagram
.
AO
A1
•
Column
Address
Buffers
•
'---
'---
~
1
16
8
Column' Decode
3
128KArray
128KArray
R
128KArray
16
Row
Address
Buffers
0
•
••
w
10
0
e
c
/
0
-
128KArray
•
••
e
128KArray
10
.,
128KArray
L
TEXAS ."
INSlRUMENTS
5-90
POST OFFICE BOX 1443
•
L$
16
"
I/O
Buffers
1 of 16
Selection
3-
d
1-
"r-I-
Sense Anipllflers
-I-
L
•
•
~
Timing and Control
/
•
•
A10
~
I
HOUSTON, TEXAS 77001
1-
~
~
In
Reg.
Out
Reg.
o
Q
1MS44100
4 194 304-811
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 OB -
SEPTEMBER 1989 -
REVISED JANUARY 1991
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee ............................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ...................................................... - 55°C to 150°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation ofthe device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
°c
UNIT
V
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics overfull ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TMS441 00-60
MIN
VOH
High-level output
voltage
10H =-5 rnA
VOL
Low-level output
voltage
IOL = 4.2 rnA
II
Input current
(leakage)
10
TM S441 00-70
TMS44100-aO
TMS44100-10
MIN
MIN
MIN
MAX
MAX
2.4
2.4
MAX
2.4
2.4
UNIT
MAX
V
0.4
0.4
0.4
0.4
V
VI = 0 to 6.5 V, VCC = 5.5 V,
All other pins = 0 V to VCC
±10
± 10
±10
±10
!!A
Output current
(leakage)
Vo = OtoVCC,
VCC = 5.5 V, CAS high
±10
±10
±10
±10
fAA
ICC1
Read or write cycle
current (see Note 3)
Minimum cycle, VCC = 5.5 V
95
85
75
65
rnA
ICC2
Standby current
After 1 memory cycle, RAS and
CAS high, VIH = 2.4 V (TTL)
2
2
2
2
rnA
After 1 memory cycle, RAS and
CAS high, VIH = VCC - 0.2 V
(CMOS)
1
~
1
1
rnA
ICC3
Average refresh
current (RAS-only
or CSR) (see Note 3)
Minimum cycle, VCC = 5.5 V,
RAS cycling, CAS high
(RAS-only), RAS low after
CAS low (CSR)
95
85
75
65
rnA
ICC4
Average page
current (see Note 4)
tpc = minimum, VCC = 5.5 V,
RAS low, CAS cycling
70
60
50
40
rnA
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-91
TMS44100
4 194 304-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 OB -
SEPTEMBER 1989 -
REVISED JANUARY 1991
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
MIN
PARAMETER
TYP
MAX
UNIT
pF
Ci(A)
Input capacitance, address inputs
5
Ci(D)
Input capacitance, data input
5
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 5: VCC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TMS441 00·60
TMS441 00·70
TMS441 00·80
MIN
MIN
MIN
MAX
MAX
MAX
tAA
Access time from column-address
30
35
40
tCAC
Access time from CAS low
15
18
20
TMS44100·10
MIN
MAX
UNIT
45
ns
25
ns
tCPA
Access time from column precharge
35
40
45
50
ns
tRAC
Access time from RAS low
60
70
80
100
ns
tCLZ
CAS to output in low Z
0
tOFF
Output disable time after CAS high
(see Note 6)
0
0
0
15
0
18
NOTE 6: tOFF is specified when the output is no longer driven.
TEXAS -111
INSlRUMENTS
5·92
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
0
0
20
0
ns
25
ns
TMS44100
4 194 304-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 OB -
SEPTEMBER 1989 -
REVISED JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS441 00-60
MAX
MIN
TMS44100-70
TMS441 00-80
MIN
MIN
MAX
MAX
TMS44100-10
MIN
MAX
UNIT
tRC
Random read or write cycle (see Note 7)
110
130
150
180
ns
tRWC
Read-write cycle time
130
153
175
210
ns
tpc
Page-mode read or write cycle time
(see Note 8)
40
45
50
55
ns
tPRWC
Page-mode read-write cycle time
60
68
75
85'
ns
tRASP
Page-mode pulse duration, RAS low
(see Note 9)
60
100 000
70
100 000
80
100 000
100
100 000
ns
tRAS
Non-page-mode pulse duration, RAS low
(see Note 9)
60
10 000
70
10 000
80
10 000
100
10 000
ns
tCAS
Pulse duration, CAS low (see Note 10)
15
10 000
18
10000
20
10 000
25
10 000
tcp
Pulse duration, CAS high
10
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
70
ns
twp
Write pulse duration
15
15
15
20
ns
tASC
Column-address setup time before CAS low
0
0
ns
tASR
Row-address setup time before RAS low
a
tDS
Data setup time (see Note 11)
0
a
a
a
ns
tRCS
Read setup time before CAS low
a
0
a
a
a
a
0
ns
tCWL
W-Iow setup time before CAS high
15
18
20
25
ns
tRWL
W-Iow setup time before RAS high
15
18
20
25
ns
twcs
W-Iow setup time before CAS low
(Early write operation only)
a
0
0
0
ns
tWSR
W-high setup time (CAS-before-RAS
refresh only)
10
10
10
10
ns
tWTS
W-Iow setup time (test mode only)
10
10
10
10
ns
tCAH
Column-address hold time after CAS low
10
15
15
20
ns
0
ns
0
ns
tDHR
Data hold time after RAS low (see Note 13)
50
55
60
75
ns
tDH
Data hold time (see Note 10)
10
15
15
20
ns
tAR
Column-address hold time after RAS low
(see Note 13)
50
55
60
75
ns
tRAH
Row-address hold time after RAS low
10
10
10
15
ns
tRCH
Read hold time after CAS high (see Note 12)
a
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 12)
0
0
0
0
ns
tWCH
Write hold time after CAS low
(Early write operation only)
15
15
15
20
ns
tWCR
Write hold time after RAS low (see Note 12)
50
55
60
75
ns
tWHR
W-high hold time (CAS-before-RAS
refresh only)
10
10
10
10
ns
lWTH
W-Iow hold time (test mode only)
10
10
10
10
ns
tAWD
Delay time, column address to W low
(Read-write operation only)
30
35
40
45
ns
Continued next page.
NOTES: 7. All cycle times assume tT = 5 ns.
8. To assure tpc min, tASC should be greater than or equal to tcp.
9. In a read-write cycle, tRWD and tRWL must be observed.
10. In a read-write cycle, tCWD and tCWL must be observed.
11. Referenced to the later of CAS or Win write operations.
12. Either tRRH or tRCH must be satisfied for a read cycle.
13. The minimum value is measured when tRCD is set to tRCD min as a reference.
TEXAS -1!1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-93
TMS44100
4 194 304-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 OB -
SEPTEMBER 1989 -
REVISED JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
TMS441 00-60
TMS441 00-70
MIN
MIN
MAX
MAX
TMS441 00-80
MIN
MAX
TMS44100-10
MIN
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
tCRP
Delay time, CAS high to RAS low
0
0
tCSH
Delay time, RAS low to CAS high
60
70
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
tCWD
Delay time, CAS low to W low
(Read-write operation only)
15
18
tRAD
Delay time, RAS low to column-address (see
Note 14)
15
tRAl
Delay time, column-address to RAS high
30
35
40
45
tCAl
Delay time, column address to CAS high
30
35
40
45
tRCD
Delay time, RAS low to CAS low
(see Note 14)
20
30
45
15
35
20
52
UNIT
20
ns
0
0
ns
80
100
ns
10
10
ns
20
25
ns
20
15
15
MAX
15
20
40
60
20
25
50
ns
ns
ns
75
ns
tRPC
Delay time, RAS high to CAS low
0
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
25
ns
tRWD
Delay time, RAS low to W low
(Read-write operation only)
60
70
80
100
ns
tTAA
Access time from address (test mode)
35
40
45
50
ns
tTCPA
Access time from column precharge (test
mode)
40
45
50
55
ns
65
75
85
105
tTRAC
Access time from RAS (test mode)
tREF
Refresh time interval
tT
Transition time
16
50
2
16
16
2
50
2
50
2
NOTE 14: The maximum value is specified only to assure access time.
PARAMETER MEASUREMENT INFORMATION
1.31 V
~
Oulpul Under Tea1
Vcc =5V
RL·21.0
-l
T
Output Under Test
CL
CL=100pF
=100 pF
(a) Load Circuit
(b) Alternate Load Circuit
Figure 1. Load Circuits for Timing Parameters
TEXAS
lJ1
INSTRUMENTS
5-94
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
ns
16
ms
50
ns
TMS44100
4 194 304-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 DB -
SEPTEMBER 1989 -
REVISED JANUARY 1991
read cycle timing
NOTE 15: Output may go from three-state to an invalid data state prior to the specified access time.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-95
TMS44100
4 194 304-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 OB -
SEPTEMBER 1989 - REVISED JANUARY 1991
early write cycle timing
VOH
Q - - - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - - -
VOL
TEXAS •
INSlRUMENTS
5-96
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44100
4 194 304-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 OB -
SEPTEMBER 1989 -
REVISED JANUARY 1991
write cycle timing
~1~--------------------------tRC----------------------~.'
I
141~------- tRAS ----------___.._
N
--~I
Y:
1
~ ~
, t-r
1 I~
tRCO
I~
!i
I 1
tRAH
-.!
~
~ tASR
.1 1
I
1 : 1
.1 I I
~ tCAH
--I
I
I tRAl
I I~ I
I I I
I I .1
-.II
I~
1
~tCWl
·1 1411
tos
--.!
I~
1
tWCR
tOHR
,
I
.-1
tRWl
*f
~VIH
I
I
I
Vil
tcP----~.-1
I I
1.1
I
.~f2RH_
I
I~
I
VIH
Vil
~H{~~~____ :::
celumn:
I~
I
~tRAO ~
D
tCAl
1
tAR
A~A'O ~ R~W ~
Vi
11i
N
tASC:~
~
I~
I I,
I I~,
I
1\. . ___
.1 1"III1~---tRP ----...,.1
.,,..~----- tRSH - - - . ; ,
I
,,..~--- tCAS ---~.I ~I~--rl--- tCRP ----~.,
tCSH
.1 1 1
1
1
1
1 .,----------.'
~~*H~:::
l~twP~
I 1
I I~
I
1
"I
.1 tOH
.1
I
I
I
I
&2§0Hn~RH~ ~all.Da,a ~*rK*g~:::
tCLZ
1
.1
1411
Q ______________
tOFF ~
-<~
"e,Vali.
~
~)------------- VOH
VOL
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-97
TMS44100
4 194 304-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 OB -
SEPTEMBER 1989 -
REVISED JANUARY 1991
read-write cycle timing
-+l
I
I
I
I
AO.Al0~
a
NOTE 15: Output may go from three-state to an invalid data state prior to the specified access time.
TEXAS ~
INSIRUMENTS
5-98
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
1MS44100
4 194304-811
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 DB - SEPTEMBER 1989 -
REVISED JANUARY 1991
enhanced page-mode read cycle timing
141
.1 I
I
tRP
141
I
tRASP
N,'~
.,
,
'
VIH
1i~
i
:"-- Vil
11
_
:..
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
I I
1 ~ tRCD ---+I
I 1
I
I 141
tCSH
II
~tCAS-..J
I
I
:.- tRAH
tASR
I4-t-
--.I
~
I'"
.11
tpc
.'
,
~ tASC'
,
I
,
1
~,tCRP ~
.1:
'~tRSH:
I - i - - - - - - VIH
i
.
r--I...
:
:\
0'X
1 ,I,
1
,41
I 1
"
~ tcp ~
I
N
I1 I
:
.'
141
I
"': :
- 11
tCAH 1 '41
tRAl
1'
tCAl
'I
I
I
.1
1 ~--------~
I I
I'
.1 I
I
Vil
~~~~~~~VIH
AO·A10
~
_I
w
II~ tRAD
1
,
1
---J-I
I
I
1
1
I
j4I--- tCAC
1
~14I-t-1-
141
1
1ooII'4If----
-.l
tAA
tRAC
tCLZ
W01
W
141
.,
,I''''''''''
~VIH
I
I
1
I
1
I
-----;-1-1.~1
tCPA
(see Note 16)
.1
.1
Q--------------(XXX:X)(X
(see Note 15)
1
Vil
I
~ tOFF ~
I ,
I '
Valid
Out
VOH
VOL
NOTES: 15. Output may go from three-state to an invalid data state prior to the specified access time.
16. Access time is tePA or tM dependent.
TEXAS •
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-99
TMS44100
4194304-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 DB -
SEPTEMBER 1989 -
REVISED JANUARY 1991
enhanced page-mode write cycle timing
VOH
Q
-----------------HI-Z ----------------VOL
NOTES: 17. Referenced to CAS or W, whichever occurs last.
18. A read cycle or a read-write cycle can be intermixed with write cycle as long as read and read-write timing specifications are not
violated.
TEXAS
-IJ1
INSlRUMENTS
5-100
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
1MS44100
4 194 304-811
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 OB -
SEPTEMBER 1989 -
REVISED JANUARY 1991
enhanced page-mode read-write cycle timing
tRP~
I~
RAS
N
I
1
:
1
I
1
1
~--------------------------
:<11
tCSH
tPRWC
I
~ tRCD ~
_I I~
I
-I
I
n
N
::~
~ tASR
I ~ 1<11I I~I
-:
tRAO
: :
j+ tASC --.I 1
tRAH
1
A~Al0~
tAR
I 14- tCAH ~
I 1
_
+~n
I0$HK2XOO :::
~
1
1
1
1
~tOFF
_I
I
I
(see Note 15)
--.I
I
I
I
I
VOH
Valid Out
VOL
NOTES: 15. Output may go from three-state to an invalid data state prior to the specified access time.
19. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
TEXAS
-1!1
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
5-101
TMS44100
4194304-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 OB -
SEPTEMBER 1989 -
REVISED JANUARY 1991
RAS-only refresh timing
Q ----------------------------------------------------------------------
VOL
NOTE 20: A10 is a don't care.
TEXAS ~
INSTRUMENTS
5-102
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44100
4194304-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 OB -
SEPTEMBER 1989 -
REVISED JANUARY 1991
automatic (CAS-before-RAS) refresh cycle timing
~1~r---------------------tRc--------------------~·~1
~ tRP ~
1410lIl------------ tRAS ___________.,.1
I
,
1
I
I
I."
RAS _ _
\.;
---J/:
tRPC
1
: I . f
i r - - - - VIH
VIL
:X!'--________________-E
,
~tCSR -.I 1
-.I ~
, 1140lIl------- tCHR
\{ 1 :I~
,
tWSR -1I14I11------~. I -_____~
w~
.....
----------.t.,
tT
.1
y~---------- VIH
VIL
tWHR
VIH
VIL
a - - - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - - -
VOH
VOL
NOTE 20: A 10 is a don't care.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-103
TMS44100
4194304-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 OB - SEPTEMBER 1989 - REVISED JANUARY 1991
hidden refresh cycle (read)
o
~g~~~f;:= _ _ :::
~~~
I~
: .:
~
Q
leu
I
tAA
tOFF
~tCAC
I+-
I
~~~--------------------~-II-d-D-at-a------~::'~:-------------~ :::
TEXAS "J1
INSlRUMENTS
5-104
-..1
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44100
4 194 304·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMHS410B -
SEPTEMBER 1989 -
REVISED JANUARY 1991
hidden refresh cycle (write)
I+-- Refresh Cycle
~ Memory Cycle ~
I
I
I
RAS
~
r+-- Refresh Cycle ~
I
!+-tRAS
I
I
~ ~tRP ~ ~tRAS +i ~tRP ~
11
I
~~
r:
Y \!
I
I
}~
r:
!
I
I I
I
I I
I"II!I
I
II
I
I I
I I
I
I I
I
I
I
I
I
I I
~ 14-1 tCAH
I :~ ~tASC
tRAH ~ 1-4+ I I I :
I I~ ! ! 1.1 tAR
~ ~tASR I I I
:
I I
I I
II
I I
I
N'
I
I
I
VIH
I"
I
tCHR
tCAS
((
.1
VIL
.. I
y l VIH
I
jJ
V
IL
I
:
I
I I
I I
AQ.A10 ~gm:'r{_IxxxxxxxxxxxxxxV'H
~~~L
twcs
I
I... I
I
I
tWCR ~
~
II
W
~
tRR~ ~
.1
I+-
I I:
I
I
I I~ I
I~
IWPI I I
L
I....
I4- tWHR
I
I ~ ,..- tWSR
I
I
I
V
,'J7
'I'f
: +.:~tDH1
I
I I
~
J
~
~
t+- tWCH
I
I
~tDHR~
o
a
i{
~,
~{oHsH.~:::
- - - - - - - - - - - - H I . Z - - - - - - - - - - -.......'/I.
j ....---------
VOH
VOL
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-105
TMS44100
4 194 304-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 OB -
SEPTEMBER 1989 -
REVISED JANUARY 1991
test mode entry cycle
~'~~---------------------tRC--------------------~·~'
~tRP~ ~1~~-----------tRAS--------------~.~1 I
---J;f
RAS
N
.
,
I
, *- tCSR --.I
tRPC
~
1
\l
~
I
I '
y;,..-----VIH
r
I
,I14~~------ tCHR ----------~.I
I~
tWTS
w~~~~~:
~
.,
VIL
j;~----------VIH
tT
VIL
~ tWTH
R~?e~V'H
VIL
D
~~h*X~
a
-----------------HI·Z -----------------
VIH
VIL
VOH
VOL
device symbolization
-~
TI
)
Speed (-60, -70, -80, -10)
TMS44100 DM
Package Code
WBP~¥-
Lot Traceability Code
I
Month Code
Assembly Site Code
Die Revision Code
Wafer Fab Code
TEXAS -If
INSlRUMENlS
5-106
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44101
4 194 304-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
This Data Sheet is Applicable to All
TMS4410 1s Symbolized with Revision "8"
and Subsequent Revisions as Described
on Page 5-124.
D
• Organization ... 4 194 304 x 1
• Single 5-V Power Supply (±10% Tolerance)
• Performance Ranges:
ACCESS ACCESS ACCESS
SMHS411 -
TIME
TIME
TIME
OR WRITE
(tRAC)
(MAX)
(tCAC)
(MAX)
15 ns
(tAA)
CYCLE
(MAX)
(MIN)
30 ns
110 ns
IN
VSS
Q
RAS
NC
A1D
CAS
NC
A9
A8
A7
A6
A5
A4
AD
A1
A2
A3
READ
VCC
TMS44101-60
60 ns
TMS44101-70
70 ns
18 ns
35 ns
130 ns
TMS44101-80
80 ns
20 ns
40 ns
150 ns
TMS44101-10
100 ns
25 ns
45 ns
180 ns
JANUARY 1991
SD Package t
(Top View)
DM and DJ Packages t
(Top View)
A9
Q
D
RAS
NC
AD
A2
VCC
A5
A7
CAS
VSS
IN
A1D
NC
A1
A3
A4
A6
A8
tThe packages shown are for pinout reference only.
PIN NOMENCLATURE
AO-Al0
CAS
D
NC
• 4-Bit Nibble Mode Operation
- Four Sequential Single-Bit Access
Within a Row by Toggling CAS
Q
• CAS-Before-RAS Refresh
RAS
IN
• Long Refresh Period ...
1024-Cycle Refresh in 16 ms (Max)
VCC
VSS
Address Inputs
Column-Address Strobe
Data In
No Connection
Data Out
Row-Address Strobe
Write Enable
5-V Supply
Ground
• 3-State Unlatched Output
• Texas Instruments EPIC ™ CMOS Process
• High-Reliability Plastic 300-mil and 350-mil
20/26-Lead Surface Mount (SOJ) Packages
and a 20-Pin Zig-Zag In-line Package
• All Inputs/Outputs and Clocks are TTL
Compatible
• Operating Free-Air Temperature
Range ... O°C to 70°C
• Low Power Dissipation
description
The TMS44101 series are high-speed 4 194 304-bit dynamic random-access memories, organized as
4 194304 words of one bit each. They employ state-of-the-art EPIC ™ (Enhanced Process Implanted CMOS)
technology for high performance, reliability, and low power at a low cost.
These devices feature maximum RAS access times of 60 ns, 70 ns, 80 ns, and 100 ns. Maximum power
dissipation is as low as 360 mW operating and 6 mW standby.
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS441 01 is offered in a 350-mil 20/26-lead plastic surface mount SOJ package (OM suffix), a 300-mil
20/26-lead plastic surface mount SOJ package (OJ suffix), and a 20-pin plastic ZIP package (SO suffix). All
packages are guaranteed for operation from O°C to 70°C.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.
TEXAS
-II}
Copyright © 1991, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-107
TMS44101
4194304-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS411 -
JANUARY 1991
operation
nibble mode
Nibble-mode operation allows high-speed read, write, or read-write access of 1 to 4 bits of data. The first bit is
accessed in the normal manner with read data coming out at tCAC as long as tRAC and tM are satisfied. The
next sequential bits can be read or written by cycling CAS while RAS remains low. The first bit is determined by
the row and column addresses, which need to be supplied only for the first access. Row A 10 and column A 10
provide the two binary bits for initial selection, with row A 10 being the least-significant address and column A 10
being the most significant. Therefore, the falling edge of CAS will access the next bit of the circular 4-bit nibble
in the following sequence
~
(00)
( 0 1 )
( 1 0 )
(11)~
Data written in a sequence of more than 4 consecutive cycles shall be capable of being read back without exiting
from the nibble mode. In a sequence of consecutive nibble-mode cycles the control of the high-impedance state
for the data out (0) pin is determined by each individual cycle. This facilitates fully mixed nibble-mode cycles (e.g.,
read/write/read-write, etc.)
address (AO through A 10)
Twenty address bits are required to decode 1 of 4 194 304 storage cell locations. Eleven row-address bits are
set up on inputs AO through A 10 and latched onto the chip by the row-address strobe (RAS). The eleven
column-address bits are set up on pins AO through A 10 and latched onto the chip by the column-address strobe
(CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip
enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select activating
the output buffer, as well as latching the address bits into the column-address buffer.
write enable (W)
The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL
circuits without a pull-up resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle, permitting common
I/O operation.
data in (0)
Data is written during a write or read-write cycle. Depending on the mode of operation, the falling edge of CAS
or W strobes data into the on-Chip data latch. In an early write cycle, W is brought low prior to CAS and the data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-write cycle,
CAS will already be low, thus the data will be strobed in by W with setup and hold times referenced to this signal.
data out (0)
The three-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS is brought low. In a read cycle the output becomes valid after the access time interval tCAC that begins
with the negative transition of CAS as long as tRAC and tM are satisfied. The output becomes valid after the
access time has elapsed and remains valid while CAS is low; CAS going high returns it to a high-impedance state.
In a delayed-write or read-write cycle, the output will follow the sequence for the read cycle.
TEXAS
lJ1
INSlRUMENTS
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TMS44101
4 194 304-81T
DYNAMIC RANDOM-ACCESS
MEMORY
REV A - SMHS411 - JANUARY 1991
refresh
A refresh operation must be performed at least once every sixteen milliseconds to retain data. This can be
achieved by strobing each of the1 024 rows (AO-A9). A normal read or write cycle will refresh all bits in each row
that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, thus conserving
power as the output buffer remains in the high-impedance state. Externally generated addresses must be used
for a RAS-only refresh. Hidden refresh may be performed while maintaining valid data at the output pin. This is
accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period,
similar to a RAS-only refresh cycle. The external address is ignored during the hidden refresh cycles.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS [see parameter teSR] and holding it
low after RAS falls [see parameter teHR]' For successive CAS-before-RAS refresh cycles, CAS can remain low
while cycling RAS. The external address is ignored and the refresh address is generated internally.
power-up
To achieve proper device operation, an initial pause of 200 I-ls followed by a minimum of eight initialization cycles
is required after full Vee level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
test mode
An industry standard Design For Test (OFT) mode is incorporated in the TMS441 01. A CAS-before-RAS cycle
with W low (WCSR) cycle is used to enter the test mode. In the test mode, data is written into and read from eight
sections of the array in parallel. Data is compared upon reading and if all bits are equal, the data out pin will go
high. If anyone bit is different, the data out pin will go low. Any combination read, write, read-write, or page-mode
can be used in the test mode. The test mode function reduces test times by enabling the 4 meg DRAM to be
tested as if it were a 512K DRAM, where row address 10, column address 10, and also column address 0 are
not used. A RAS-only or CSR refresh cycle is used to exit the OFT mode.
TEXAS . .
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DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS411 -
JANUARY 1991
logic symbol t
RAM 4096K x 1
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
9
10
11
12
14
15
16
17
18
22
5
24
o
>
A
0
4194303
31021/21010
C30 [ROW]
G33 [REFRESH ROW]
34 [PWR OWN]
r--..
C31 [COL]
G34
1'-..
3
W
30011/21 DO '
2
1
~
~
r-
&
> 33C32
34 EN
33310
A, 320
25
AV
Q
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
The pin numbers shown are for the 20/26 pin SOJ package.
functional block diagram
.
AO
~
I
•
·•
A10
Column
Address
Buffers
1
16
'---
-
Column Decode
3
128KArray
128K Array
R
128K Array
16<
Row
Address
Buffers
0
•
•
•
w
•
0
D
e
c
10
/
-
11-
~
Sense Amplifiers
-I-
L
•
•
•
~
8
/
A1
~
Timing and Control
d
e
128KArray
128KArray
•
•
•
L±
16
/
TEXAS . .
INSTRUMENTS
5-110
POST OFFICE BOX 1443
•
I/O
Buffers
1 of 16
Selection
3-
-+128KArray
..,.
10
~,
HOUSTON. TEXAS 77001
1f.-
~
a
~
In
Reg.
Out
Reg.
o
TMS44101
4 194 304-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS411 -
JANUARY 1991
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee (see Note 1) .................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range ..................................................
to 70 0
Storage temperature range ....................................................... - 55°e to 150 0 e
ooe
e
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
UNIT
V
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
°c
NOTE 2: The algebraic convention, where. the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TMS44101-60
MIN
MAX
TMS44101-70
MIN
MAX
TMS44101-80
MIN
MAX
TMS44101-10
MIN
MAX
UNIT
VOH
High-level output
voltage
VOL
Low-level output
voltage
10L = 4.2 mA
0.4
0.4
0.4
0.4
V
II
Input current
(leakage):!:
VI = 0 to 6.5 V, All other pins
= OVtoVCC
±10
±10
±10
±10
fAA
10
Output current
(leakage):!:
Va'" 0 to VCC, CAS high
±10
±10
±10
±10
fAA
ICCl
Read or write cycle
current (see Note 3)
Minimum cycle, VCC '" 5.5 V
95
85
75
65
mA
After 1 memory cycle,
RAS and CAS high,
VIH '" 2.4 V (TTL)
2
2
2
2
After 1 memory cycle,
RAS and CAS high,
VIH '" VCC - 0.2 V
1
1
1
1
ICC2
Standby current
2.4
10H =-5 mA
2.4
2.4
2.4
V
mA
ICC3
Average refresh
current (RAS-only or
CBR) (see Note 3):!:
RAS cycling, CAS high
(RAS-only), RAS low after
CAS low (CBR)
95
85
75
65
mA
ICC5
Average nibble mode
current:!:
RAS low, CAS cycling
70
60
50
40
mA
:!: Minimum cycle, VCC '" 5.5 V.
NOTE 3: Measured with a maximum of one address change while RAS = VIL.
TEXAS •
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DYNAMIC RANDOM-ACCESS MEMORY
REV A - SMHS411 - JANUARY 1991
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 4)
MIN
PARAMETER
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(D)
Input capacitance, data input
5
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 4: VCC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
TMS44101-60
PARAMETER
MIN
TMS44101-70
MAX
MIN
MAX
TMS44101-80
MIN
MAX
TMS441 01-1 0
MIN
MAX
UNIT
tM
Access time from column-address
30
35
40
45
ns
tCAC
Access time from CAS low
15
18
20
25
ns
tNCAC
Access time from CAS low (nibble operation)
15
18
20
25
ns
tRAC
Access time from RAS low
60
70
80
100
ns
tCLZ
CAS to output in low Z
a
0
Output disable time after CAS high (see Note 5)
tOFF
NOTE 5: tOFF IS specified when the output IS no longer driven.
15
0
0
18
0
0
20
0
0
ns
25
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS44101-60
TMS44101-70
TMS44101-80
MIN
MIN
MIN
MAX
MAX
MAX
TMS44101-10
MIN
MAX
UNIT
tRC
Random read or write cycle (see Note 6)
110
130
150
180
tRWC
Read-write cycle time
130
153
175
210
ns
tNC
Nibble-mode read or write cycle time
35
38
40
45
ns
tNRWC
Nibble-mode read-write cycle time
55
tRAS
Pulse duration, RAS low (see Note 7)
60
10000
70
10000
80
10 000
100
10000
ns
tCAS
Pulse duration, CAS low (see Note 8)
15
10000
18
10000
20
10000
25
10000
ns
tcp
Pulse duration, CAS high
10
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
70
ns
twp
Write pulse duration
15
15
15
20
ns
tASC
Column-address setup time before CAS low
0
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
0
ns
tDS
Data setup time (see Note 9)
0
0
0
0
ns
61
65
ns
ns
75
tRCS
Read setup time before CAS low
0
0
0
0
ns
tCWL
W-Iow setup time before CAS high
15
18
20
25
ns
tRWL
W-Iow setup time before RAS high
15
18
20
25
ns
twcs
W-Iow setup time before CAS low
(Early write operation only)
0
0
0
0
ns
tWSR
W-high setup time (CAS-before-RAS
refresh only)
10
10
10
10
ns
W-Iow setup time (test mode only)
10
10
10
10
ns
15
15
20
ns
twTs
Column-address hold time after CAS low
10
tCAH
Continued next page.
NOTES: 6. All cycle times assume IT = 5 ns.
7. In a read-write cycle, tRWD and tRWL must be observed.
8. In a read-write cycle, tCWD and tCWL must be observed.
9. Referenced to the later of CAS or IN in write operations.
TEXAS •
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TMS44101
4194304-81T
DYNAMIC RANDOM-ACCESS MEMORY
REVA-SMHS411 -JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
TMS44101-60
,MIN
MAX
TMS44101-70
TMS44101-80
TMS44101-10
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
tDHR
Data hold time after RAS low
50
55
60
75
ns
tDH
Data hold time (see Note 9)
10
15
15
20
ns
tAR
Column-address hold time after RAS low
50
55
60
75
ns
tRAH
Row-address hold time after RAS low
10
10
10
15
ns
tRCH
Read hold time after CAS high (see Note
10)
0
0
0
0
ns
tRRH
Read hold time after RAS high (see Note
10)
0
0
0
0
ns
twCH
Write hold time after CAS low
(Early write operation only)
15
15
15
20
ns
tWCR
Write hold time after RAS low
50
55
60
75
ns
tWHR
W-high hold time (CAS-before-RAS refresh
only)
10
10
10
10
ns
tWTH
W-Iow hold time (test mode only)
10
10
10
10
ns
tAWD
Delay time, column address to W-Iow
(Read-write operation only)
30
35
40
45
ns
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
15
15
20
20
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
0
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
100
ns
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
10
ns
tCWD
Delay time, CAS low to W-Iow
(Read-write operation only)
15
18
20
25
ns
tRAD
Delay time, RAS low to column-address
. (see Note 11)
15
Delay time, column-address to RAS high
30
tCAl
Delay time, column-address to CAS high
30
tRCD
Delay time, RAS low to CAS low (see Note
11)
20
tRAl
30
15
35
35
35
45
20
15
40
20
50
60
25
ns
ns
45
40
52
20
45
40
ns
75
ns
tRPC
Delay time, RAS high to CAS low
0
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
25
ns
tRWD
Delay time, RAS low to W-Iow
(Read-write operation only)
60
70
80
100
ns
ns
ITM
Access time from address (test mode)
35
40
45
50
ITRAC
Access time from RAS (test mode)
65
75
85
105
tREF
Refresh time interval
IT
Transition time
16
50
2
16
2
50
16
2
50
2
ns
16
ms
50
ns
NOTES: 9. Referenced to the later of CAS or Win write operations.
10. Either tRRH or tRCH must be satisfied for a read cycle.
11. The maximum value is specified only to guarantee access time,
TEXAS
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DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS411 -
JANUARY 1991
PARAMETER MEASUREMENT INFORMATION
1.31 V
~
Ou1pul Under Tesl
VCC =5V
"L=2180
-l
=828 Q
R2
=295 Q
Output Under Test - - . - - - .
CL=100pF
CL= 100 PF T
(b) Alternate Load Circuit
(a) Load Circuit
Figure 1. Load Circuits for Timing Parameters
read cycle timing
NOTE 12: Output may go from three-state to an invalid data state prior to the specified access time.
TEXAS . .
INSTRUMENTS
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R1
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TMS44101
4 194 304-81T
DYNAMIC RANDOM-ACCESS MEMORY
REVA-SMHS411-JANUARY 1991
early write cycle timing
a ----------------HI·Z ----------------
VOH
VOL
TEXAS ~
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TMS44101
4 194 304-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS411 -
JANUARY 1991
write cycle timing
TEXAS ~
INSTRUMENTS
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TMS44101
4 194 304-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A- SMHS411-JANUARY 1991
read-write cycle timing
~1~-----------------------tRWc----------------------~~1
i
i~~-----------------tRAS----------------~~i
RAS~I~
YT
r--
~---------------------~I
tT
I~
1 ~ tRCO - . I
-+I
:
tCAS
.-1
1. 1'4
~
:
-
I~~
II
tRA~
I I
~tASC
t~AO ~
I I~
I~ L
I t
I I
*
~ I tCAH
+~ AR~+n
I
I
1II1I
I
i
1>1
tRP
-.l
I~
1
I
·1
I+-- tCWL ~ 1
:II1II
tRWL I
I
.1
--.l
~twP~
1
1
: tAWO
}r
:1
*-tcwo~
~I
~
I
1 I
~I I
VIL
I
I
1
1
~
-.r
1
1
~~~-~~~~~*~~e~~~VIH
I
1
tcp
I
I 1
I
I
tRWO.
I tos
VIH
~~H~c~*_'----:::
1
1
1
II~
~ ~ tT
~I
w-_______ :::
~tCAC~
tAA
.. I
I
~I
tRAC
NOTE 12: Output may go from three-state to an invalid data state prior to the specified access time.
TEXAS •
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5-117
TMS44101
4 194 304-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS411 -
JANUARY 1991
nibble-mode read cycle timing
AO-A10
W
1fIllI1
L._
tRAD
f""--
1
--J"I
1
1
1
1
,
1
~ tCAC
1
1II1II
1
1
*-- tOFF ~
I
.,
1II1II
VIL
1
1
.1
tRAC
tCLZ
1
----.I
tAA
~VIH
1
.
1
1II1II
Q
V
1
.,
,
_ _ _ _ _ _ _ _ _-:----:-_~_(';>(XXXXX
Valid
Out
(see Note 12)
VOH
VOL
NOTE 12: Output may go from three-state to an invalid data state prior to the specified access time.
TEXAS
-1!1
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TMS44101
4 194 304-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A- SMHS411 -JANUARY 1991
nibble-mode write cycle timing
VOH
Q
-----------------HI-Z ----------------(see Note 14)
VOL
NOTES: 13. Referenced to CAS or 'N, whichever occurs last.
14. The output may go to an invalid state if a late write is completed.
TEXAS ~
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TMS44101
4 194 304·81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS411 -
JANUARY 1991
nibble-mode read-write cycle timing
tRP~
RAS
N
I..
1
I"
~'I..
tCSH
i
I
-+.I ~
.:
tRAO
tAse -.I
tRAH
,
r+-
AO.Al0~
,
,
,
,..
,
~I
:"'-twp
I ~I I
I
,
,
,..
,
,..
' I
1 1 ,
' I
I
I
, 1 I
III
-.I
I
I
I+tewL ~
I
I
I
I
I
,
j4-tRWL
1
I
1
'
.:
I
I
tOH
tCLZ~!.-1
..................................... : : :
1
I
1
tel.4:~
1
,
>_tHRaX{*0 :::
~
I ,
.,
':
,'
,
~
W*mHX: +'d
"
,
I ,
~
I I
~..,.L
I'
tos
I..
~ tCAe -+!
tAA
~,
tRA
,
, , ,
: N 10W' ')
,
.. I
~tOFF~
,
'
,,
,
(see Note 12) .
Q
1
i
I ~I
'
D2Q222$H*~_ Valid
,
;1l1-i-!-:-----:::
1 1 ' 1
~*
I 1
1
I
I,
,
,
,, *--t
--!--.!
I
AWo I
I
wXXXXX¥
1
*- tcwo
,,
I tRWO
VIL
teRP
_ _~omH~:::
+:mn
I
---t+I
~tRCS -.I I
,
~I
I": tNRwe
~ tCAH -.J
tAR I I
.:
~
I 1
i~!
:
,"
~ tASR
~:
VIH
tcp
,, I,
I i+-tRSH ~
I I
I~ tCAS
~r
~
I i
,
1.. 1
.1I
---.1,:
~tRCo - . I
I
,
~---------------------------------------------------I
--.:
Vl\I
I
14-
I I
~I
tRAS
(see Note 12)
-------..;...------..;....------(:X)(X)(X
VOH
Valid Out
VOL
NOTES: 12. Output may go from three-state to an invalid data state prior to the specified access time.
15. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
TEXAS •
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4 194 304-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS411 -
JANUARY 1991
RAS-only refresh timing
VOH
Q -------------------------------------------------------------VOL
NOTE 16: A 10 is a don't care.
automatic (CAS-before-RAS) refresh cycle timing
1~~----------------------tRC--------------------~-~1
r---- i
tRP
T.
RAS _ _ _--J1 :
tRPC
I
~',~------------- tRAS --------------..,~:
!
"\ I
}I Ti r - - - - VIH
: ~I\;.'____________________________---Jl:l
VIL
~ tCSR ---.I '
--.l ~
\l
I 14'~-------- tCHR ----------~_I
-1 :,i+-
y~----------------- VIH
tT
tWSR --1t4I----~-~I I, _____-.t-
....
-I
~L
tWHR
VOH
Q - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
VOL
TEXAS
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TMS44101
4 194 304-81T
DYNAMIC RANDOM-ACCESS MEMORY
REVA-SMHS411-JANUARY1991
hidden refresh cycle (read)
~ Refresh Cycle ~
~ Memory Cycle ~
~ Refresh Cycle ~
I
I_
I
I
I I+t
-.l ~tRP ~
~tRP ~
I
RAS
I
I ~ tRAS -.I I
I
1: Ii It
RAS,
I i
tAR
I
I
I
I
I
I
I i i
1
1 I
1
tCAS
1 I
I~ ~
1
~!++ tCAH
I I
I 41 ~tl SC
~ ,_ I I~ i I 't
tRAH ~ ~I I I I I
tASR~ ~ 1 I I I I
I~:::
r~
1\
I
tCHR
I
I
(
;
I
I
1
1
1
I
I
I
I
I
I
I
I
I
I
I
.1
1
!I
. y : 1 VIH
:1
I
I
1
I
1
I
1
I
I
I
I
VIL
I
1
1
1
I
1
1
I
I
I
I
I
AO-A10~}~-H~~~:::
I
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~
I
I
I I
"':~'-'!--+I••+-I IRCS
I
I
1
~ twHR
I
4J ~1w~
wW: i: V
I I
~
~
I
I+-tWHR
'- bm~
Vlltlii/
I
~~
TEXAS . .
INSTRUMENTS
5-122
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
~
1
~ ty.'HR
I
I
~1w-Gxxxxx
~
I
V,H
V,L
TMS44101
4 194 304-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
hidden refresh
cycle
~ Refresh Cycle ~
RAS
,
~ ~tRP ~
t4- t RAS
!r
N'
I I
I
I
I
I
I,
I
1..1
: I
,
11,,
~~
I I
I I
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I I
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~
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~~
I
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I 'I
twcs
I~,
I,
tWCR
Y \
"
I I
I I
II
I I
/~
rVIH
~
VIL
tCHR I~
.,1
.1
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I
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I I
,
,
,
'/,
VIL
I I
I I
I I
I I
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I I
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I
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I
: -t.J,...
,
~L
I+-
.,1,
I:
I
!: .1 II :
r+twp-M
I
~
tWCH
'~tDH1
i+--1tDHR
Q
+l ~tRP ~
----+j
~~H~R_~V'H
,
o
t+tRAS
ir
I '.,1 tAR
~tASR' I
~ Refresh Cycle
,
}~
~I tCAH
I
L... I I I
I I~ r-rTt~sc
-+.:,
I I
JANUARY 1991
(write)
~ Memory Cycle ~
,
,
,
SMHS411 -
if·'
~
~{ogHH.~:::
-----------HI-Z
-----------""')"1-,--------
VOH
VOL
TEXAS ~
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-123
TMS44101
4 194 304-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS411 -
JANUARY 1991
test mode entry cycle
1~~~---------------------tRC--------------------~.1
Jf
1
RAS
~ 141~---------- tRAS -----------~~~I
N
\l 1 r
: . - tRP
I
I
I
:
y~-----VIH
1
I
1 I
I
~tCSR-.J
tRPC ~ ~
1 114~-----tCHR -------~.I
_ _ _-J
~.......~~,..,....,t...,W~T~S..... I~
w~
VIL
y~----------VIH
tT
--1+1
i+-
.1
I
tWTH
VIL
~E~~~V'H
VIL
Q
-----------------HI-Z -----------------
VOH
VOL
device symbolization
-~
TI
P
Speed (-60, -70, -80, -10)
TMS441010M
Package Code
~_BP~~
Lot Traceability Code
I
Month Code
Assembly Site Code
Ole Revision Code
Wafer Fab Code
TEXAS •
INSTRUMENTS
5-124
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A- SMHS440B- OCTOBER 1989 -
DM AND DJ
Packages t
(Top View)
This Data Sheet Is Applicable to All TMS44400s
Symbolized With Revision "B" and Subsequent
Revisions as Described on Page 5-144.
DQ1
DQ2
• Organization ... 1 048 576 x 4
VSS
DQ4
DQ3
CAS
W
• Single 5-V Power Supply (±10% Tolerance)
RAS
A9
• Performance Ranges:
ACCESS ACCESS ACCESS
REVISED JANUARY 1991
OE
READ
TIME
TIME
TIME
OR WRITE
(tRAC)
(MAX)
(tCAC)
(MAX)
(tAA)
(MAX)
CYCLE
(MIN)
TMS44400-60
60 ns
15 ns
30 ns
155 ns
TMS44400-70
TMS44400-80
70 ns
80 ns
18 ns
20 ns
35 ns
40 ns
181 ns
205 ns
TMS44400-10
100 ns
25 ns
50 ns
245 ns
AD
A1
A2
A3
A8
A7
A6
A5
A4
VCC
SD Package t
(Top View)
• Enhanced Page Mode Operation for Faster
Memory Access
- Higher Data Bandwidth than
Conventional Page-Mode Parts
- Random Single-Bit Access Within a Row
With a Column Address
OE
DQ3
VSS
DQ2
RAS
AD
A2
• CAS-Before-RAS Refresh
VCC
• Long Refresh Period ...
1024-Cycle Refresh in 16 ms (Max)
A5
A7
• 3-State Unlatched Output
CAS
DQ4
DQ1
W
A9
A1
A3
A4
A6
A8
tThe packages shown are for pinout reference only.
• Low Power Dissipation
• Texas Instruments EPIC ™ CMOS Process
AO-A9
CAS
DQ1-DQ4
OE
• All Inputs/Outputs and Clocks are TTL
Compatible
w
• High-Reliability Plastic 300-Mil and 350-Mil
20/26-Lead Surface Mount (SOJ) Packages
and 20-Pin Zig-Zag In line (ZIP) Package
VCC
VSS
PIN NOMENCLATURE
Address Inputs
Column-Address Strobe
Data In/Data Out
Output Enable
Row-Address Strobe
Write Enable
5-V Supply
Ground
• Operating Free-Air Temperature Range
... O°C to 70 D C
description
The TMS44400 series are high-speed 4 194 304-bit dynamic random-access memories, organized as
1 048 576 words offour bits each. They employ state-of-the-art EPIC ™ (Enhanced Process Implanted CMOS)
technology for high performance, reliability, and low power at a low cost.
These devices feature maximum RAS access times of 60 ns, 70 ns, 80 ns, and 100 ns. Maximum power
dissipation is as low as 360 mW operating and 6 mW standby.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA documents contain Information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard
warranty. Production· processing does not necessarily
Include testing of all parameters.
Copyright © 1991, Texas Instruments Incorporated
TEXAS •
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5-125
TMS44400
1 048 S76-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS440B -
OCTOBER 1989 -
REVISED JANUARY 1991
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS44400 is offered in a 300-mil20/26-lead plastic surface mount SOJ package (OJ), a 350-miI20/26-lead
;Jlastic surface mount SOJ package (OM) and a 20-pin zig-zag in-line package (SO suffix). All packages are
characterized for operation from O°C to 70°C.
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is thus eliminated.
The maximum number of columns that may be accessed is determined by the maximum RAS low time and the
CAS page cycle time used. With minimum CAS page cycle time, all 1024 columns specified by column
addresses AO through A9 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS44400 to operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as the column address is valid rather than
when CAS transitions low. This performance improvement is referred to as enhanced page mode. Valid column
address may be presented immediately after row address hold time has been satisfied, usually well in advance
of the falling edge of CAS. In this case, data is obtained after tCAC max (access time from CAS low), if tAA max
(access time from column address) has been satisfied. In the event that column addresses for the next cycle
are valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence of tCAC
or tCPA (access time from rising edge of CAS).
address (AO through A9)
Twenty address bits are required to decode 1 of 1 048 576 storage cell locations. Ten row-address bits are set
up on inputs AD through A9 and latched onto the chip by the row-address strobe (RAS). The ten column-address
bits are set up on pins AO through A9 and latched onto the chip by the column-address strobe (CAS). All
addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable in that
it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select activating the output
buffer, as well as latching the address bits into the column-address buffer.
write enable CN)
The read or write mode is selected through the write-enable (W) input. A logic high on the Vii input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL
c:rcuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle permitting a write
operation independent of the state of OE. This permits early write operation to be completed with OE grounded.
data in/out (OQ1-0Q4)
The three-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS and OE are brought low. In a read cycle the output becomes valid after all access times are satisfied.
The output remains valid while CAS and OE are low. CAS or OE going high returns it to a high-impedance state.
This is accomplished by bringing OE high prior to applying data, thus satisfying tOED,
TEXAS •
INSTRUMENTS
5-126
POST OFFICE BOX 1443
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HOUSTON. TEXAS 77001
TMS44400
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
REV A -
SMHS440B - OCTOBER 1989 -
REVISED JANUARY 1991
output enable (OE)
OE controls the impedance ofthe output buffers. When OE is high, the buffers will remain in the high-impedance
state. Bringing OE low during a normal cycle will activate the output buffers putting them in the low-impedance
state. It is necessary for both RAS and CAS to be brought low for the output buffers to go into the low-impedance
state. Once in the low-impedance state, they will remain in the low-impedance state until either OE or CAS is
brought high.
refresh
A refresh operation must be performed at least once every sixteen milliseconds to retain data. This can be
achieved by strobing each of the1 024 rows (AO-A9). A normal read or write cycle will refresh all bits in each row
that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, thus conserving
power as the output buffer remains in the high-impedance state. Externally generated addresses must be used
for a RAS-only refresh. Hidden refresh may be performed while maintaining valid data at the output pin. This
is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period,
similar to a RAS-only refresh cycle. The external address is ignored during the hidden refresh cycles.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS [see parameter tesRl and holding it
low after RAS falls [see parameter teHR1. For successive CAS-before-RAS refresh cycles, CAS can remain low
while cycling RAS. The external address is ignored and the refresh address is generated internally.
power-up
To achieve proper device operation, an initial pause of 200 fls followed by a minimum of eight initialization cycles
is required after full Vee level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
test mode
A Design For Test (OFT) mode is incorporated in the TMS44400. A CA~-before-RAS with W low (WCBR) cycle
is used to enter test mode. In the test mode, data is written into and read from eight sections of the array in
parallel. All data is written into the array through 001. Data is compared upon reading and if all bits are equal,
all DO pins will go high. If anyone bit is different, a DO pin will go low. Any combination of read, write, read-write,
or page-mode can be used in the test mode. The test mode function reduces test times by enabling the 1 meg
x 4 DRAM to be tested as if it were a 512K DRAM where column address 0 is not used. A RAS-only or CBR
refresh cycle is used to exit the OFT mode.
TEXAS •
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HOUSTON. TEXAS 77001
5-127
TMS44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS440B -
OCTOBER 1989 -
REVISED JANUARY 1991
logic symbol t
RAM 1024K x 4
9
10
AO
A1
20D10/2100
11
A2
12
14
A3
A4
A5
A6
A7
A8
15
16
17
18
>A
5
A9
20D19/21D9
f'...
4
~
r--..
23
3
22
~
~
2
DQ2
24
25
DQ3
DQ4
C20[ROW]
G23/[REFRESH ROW]
24[PWR DWN]
C21 [COLUMN]
G24
I>
&
23C22
24,25EN
2321D
-,
f'... G25
1
DQ1
0
1048575
~
.....
r
A,22D
\7 26
A,Z26
...
....
~
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
The pin numbers shown are for the 20/26 pin SOJ packages.
functional block diagram
AO
A1
·•
•
A9
I
•
Column
Address
Buffers
'----
~
1
Column Decode
2
~
Sense Amplifiers
ir--f-
128KArray
16
10
J
16
/
128KArray
R
128K Array
Row
Address
Buffers
~
~
Timing and Control
8
L
•
•
•
~
••
0
128KArray
•
••
w
·
D
e
c
/
-±
> 16
0
2-
d
e
128KArray
10
.,
128KArray
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443
•
r-IDtIn
Reg.
~
Data
Out
Reg.
~:
DQ1· DQ4
/
5-128
~r
I/O
Buffers
4 of 16
Selection
HOUSTON, TEXAS 77001
TMS44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS440B -
OCTOBER 1989 -
REVISED JANUARY 1991
absolute maximum ratings over operating free-air temperature range {unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee ............................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. O°C to 70 c C
Storage temperature range ...................................................... - 55°C to 150°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
UNIT
V
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
°c
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TMS44400-60
TEST CONDITIONS
VOH
High-level output
voltage
10H =-5 mA
VOL
Low-level output
voltage
10L = 4.2 mA
II
Input current
(leakage)
10
ICC1
MIN
MAX
MIN
MAX
2.4
2.4
TMS44400-80
MIN
MAX
2.4
TMS44400-10
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
0.4
V
VI = 0 to 6.5 V, VCC = 5.5 V,
All other pins = 0 to VCC
±10
± 10
±10
±10
!1A
Output current
(leakage)
Va = OtoVCC,
VCC = 5.5 V, CAS high
±10
± 10
±10
±10
~A
Read or write cycle
current (see Note 3)
Minimum cycle, VCC = 5.5 V
95
85
75
65
mA
2
2
2
2
mA
1
1
1
1
mA
After 1 memory cycle, RAS and
CAS high, VIH = 2.4 V (TTL)
ICC2
TMS44400-70
Standby current
After 1 memory cycle,
RAS and CAS high,
VIH = VCC - 0.2 V (CMOS)
ICC3
Average refresh
current (RAS-only
or CSR) (see Note 3)
Minimum cycle, VCC = 5.5 V,
RAS cycling, CAS high
(RAS-only), RAS low
after CAS low (CSR)
95
85
75
65
mA
ICC4
Average page
current (see Note 4)
tpc = minimum, VCC = 5.5 V,
RAS low, CAS cycling
70
60
50
40
mA
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS
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5-129
TMS44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS440B -
OCTOBER 1989 -
REVISED JANUARY 1991
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 5: VCC equal to 5 V
±
0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TMS44400-60
TMS44400-70
TMS44400-80
TMS44400-10
MIN
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
MAX
tM
Access time from column-address
30
35
40
45
ns
tCAC
Access time from CAS low
15
18
20
25
ns
ns
tCPA
Access time from column precharge
35
40
45
50
tRAC
Access time from RAS low
60
70
80
100
ns
tOEA
Access time from OE low
15
18
20
25
ns
tCLZ
CAS to output in low l
0
tOFF
Output disable time after CAS high
(see Note 6)
0
15
0
18
0
20
0
25
ns
tOEl
Output disable time after OE high (see Note 6)
0
15
0
18
0
20
0
25
ns
0
0
NOTE 6: tOFF and tOEl are specified when the output is no longer driven.
TEXAS ."
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POST OFFICE BOX 1443
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HOUSTON, TEXAS 77001
0
ns
TMS44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A- SMHS440B-OCTOBER 1989 -
REVISED JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS44400-60
TMS44400-70
TMS444oo-ao
TMS44400-10
MIN
MIN
MIN
MIN
MAX
MAX
MAX
MAX
UNIT
110
155
130
181
150
205
180
245
ns
40
45
50
55
ns
tRC
Random read or write cycle (see Note 7)
tRWC
Read-write cycle time
tpc
Page-mode read or write cycle time
(see Note 8)
tpRWC
Page-mode read-write cycle time
85
tRASP
Page-mode pulse duration, RAS low
(see Note 9)
60
100000
70
100000
80
100000
100
100000
ns
tRAS
Non-page-mode pulse duration, RAS low
(see Note 9)
60
10000
70
10000
80
10000
100
10 000
ns
tCAS
Pulse duration, CAS low (see Note 10)
18
10
50
15
0
0
0
0
18
18
10000
20
10
60
15
0
0
0
0
20
20
10000
25
10
70
20
0
0
0
0
25
25
10 000
Pulse duration, CAS high
15
10
40
15
0
0
0
0
15
15
10000
tcp
tRP
Pulse duration, RAS high (precharge)
twp
Write pulse duration
tASC
Column-address setup time before CAS low
tASR
Row-address setup time before RAS low
tDS
Data setup time (see Note 11)
tRCS
Read setup time before CAS low
tCWL
W-Iow setup time before CAS high
tRWL
W-Iow setup time before RAS high
twcs
W-Iow setup time before CAS low
(Early write operation only)
tWSR
W-high setup time (CAS-before-RAS
refresh only)
105
96
ns
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
ns
10
10
10
10
ns
10
10
50
10
10
15
55
15
10
15
60
15
10
20
75
20
50
55
60
75
ns
10
0
0
10
0
0
10
0
0
15
0
0
ns
tWTS
W-Iow setup time (test mode only)
tCAH
Column-address hold time after CAS low
tDHR
Data hold time after RAS low (see Note 12)
tDH
Data hold time (see Note 11)
tAR
Column-address hold time after RAS low
(see Note 12)
tRAH
Row-address hold time after RAS low
tRCH
Read hold time after CAS high (see Note 13)
tRRH
Read hold time after RAS high (see Note 13)
tWCH
Write hold time after CAS low
(Early write operation only)
15
15
15
20
ns
tWCR
Write hold time after RAS low (see Note 12)
50
55
60
75
ns
tWHR
W-high hold time (CAS-before-RAS
refresh only)
10
10
10
10
ns
tWTH
W-Iow hold time (test mode only)
10
10
10
10
ns
tAWD
Delay time, column address to W low
(Read-write operation only)
55
63
70
80
ns
ns
ns
ns
ns
ns
ns
Continued next page.
NOTES: 7. All cycle times assume tT = 5 ns.
8. To guarantee tpc min, tASC should be greater than or equal to tcp.
9. In a read-write cycle, tRWD and tRWL must be observed.
10. In a read-write cycle, tCWD and tCWL must be observed.
11. Referenced to the later of CAS or W in write operations.
12. The minimum value is measured when tRCD is set to tRCD min as a reference.
13. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS
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POST OFFICE BOX 1443
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5-131
TMS44400
1 048 576-WORD BY 4-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS440B -
OCTOBER 1989 -
REVISED JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
TMS44400-60
MAX
MIN
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
TMS44400-70
TMS44400-80
MIN
MIN
MAX
MIN
20
15
15
TMS44400-10
MAX
MAX
UNIT
20
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
0
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
100
ns
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
10
ns
tCWD
Delay time, CAS low to W low
(Read-write operation only)
40
46
50
60
ns
tOEH
OE command hold time
15
18
20
25
ns
tOED
OE to data delay
15
18
20
25
ns
tROH
RAS hold time referenced to OE
10
10
10
10
ns
tRAD
Delay time, RAS low to column-address
(see Note 14)
15
tRAl
Delay time, column-address to RAS high
30
35
40
45
ns
tCAl
Delay time, column address to CAS high
30
35
40
45
ns
tRCD
Delay time, RAS low to CAS low
(see Note 14)
20
tRPC
Delay time, RAS high to CAS low
0
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
' 15
18
20
25
ns
tRWD
Delay time, RAS low to W low
(Read-write operation only)
85
98
110
135
ns
tTAA
Access time from address (test mode)
35
40
45
50
ns
tTCPA
Access time from column precharge
(test mode)
40
45
50
55
ns
tTRAC
Access time from RAS (test mode)
65
tREF
Refresh time interval
tT
Transition time
30
45
15
20
35
52
75
16
50
2
40
15
20
60
50
25
50
75
105
85
16
16
2
20
2
50
2
ns
ms
50
ns
PARAMETER MEASUREMENT INFORMATION
~
OUlpul Under Tesl
VCC
CL= 100pF
Output Under Test
T
CL
=100 pF
(a) Load Circuit
(b) Alternate Load Circuit
Figure 1. Load Circuits for Timing Parameters
TEXAs
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RL =2t."
~
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ns
16
NOTE 14: The maximum value is specified only to guarantee access time.
1.31 V
ns
TMS44400
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
REV A -
SMHS440B -
OCTOBER 1989 -
REVISED JANUARY 1991
read cycle timing
NOTE 15: Output may go from three-state to an invalid data state prior to the specified access time.
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TMS44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS440B -
OCTOBER 1989 -
REVISED JANUARY 1991
early write cycle timing
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TMS44400
1 048 576-WORD 8Y 4-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS440B -
OCTOBER 1989 -
REVISED JANUARY 1991
write cycle timing
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TMS44400
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS440B -
OCTOBER 1989 -
REVISED JANUARY 1991
read-write cycle timing
001-004-----l----------oexx
(see Note 15)
Data
Out
1
ioIIl
...~---tRAC
- - - -••1
I ~
14- tOEA -.I
I
OE~}~X~f~~
1
tOED
I
1+
I
tOEZ
I
---1II~'--'.1
I
VII)VOL
L
.. ,
~ tOEH
/~--~~~~*~~Xg~~K~20§§~ VIH
VIL
NOTE 15: Output may go from three-state to an invalid data' state prior to the specified access time.
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TMS44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS440B -
OCTOBER 1989 -
REVISED JANUARY 1991
enhanced page-mode read cycle timing
VIH
Column
AO-A9
~~~~.t.::..{.;.~~VIL
,l1li
tA~ I
~ tACS ~
W~~tAAO~
I
I
I
r
I
I
I:
w.xl
tAA -------LI-'~
*- tAAH -.-J
(see Note 16)
~ tACH ------..I
i
sWY
'r
~
VIH
y,..----------VIH
tWTH
VIL
_ _!~~.r;~{
VIH
VIL
;~.r~a~~
AO-A9
VIH
.
~o~~~*£
OE
VIL
VIH
VIL
VIH
oQ1-oQ4 - - - - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - - -
device symbolization
-~
TI
P
Speed (- 60, - 70, - 80, - 10)
TMS44400 OM
Package Code
YiBP~¥-
Lot Traceability Code
I
Month Code
Assembly Site Code
Ole Revision Code
Wafer Fab Code
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TMS44410
1 048 576-WORD BY 4-BIT WRITE-PER-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS441 -
JANUARY 1991
DM and DJ Package t
(Top View)
• Organization ... 1 048 576 x 4
• Single 5-V Power Supply (±10% Tolerance)
W1/001
• Performance Ranges:
ACCESS ACCESS ACCESS
READ
TIME
TIME
TIME
OR WRITE
(tRAC)
(MAX)
(tCAC)
(MAX)
(tAA)
(MAX)
CYCLE
TMS4441 0-60
60 ns
15 ns
30 ns
TMS4441 0-70
70 ns
18 ns
35 ns
TMS4441 0-80
80 ns
20 ns
40 ns
TMS4441 0-1 0
100 ns
25 ns
45 ns
W2/002
VSS
W4/004
WBiW
W3/003
RAS
CAS
A9
OE
155 ns
AO
A8
181 ns
A1
A7
205 ns
A2
A6
245 ns
A3
A5
VCC
A4
(MIN)
• Enhanced Page Mode Operation for Faster
Memory Access
- Higher Data Bandwidth than
Conventional Page-Mode Parts
- Random Single-Bit Access Within a Row
With a Column Address
- Write-Per-Bit Functionality
SD Package t
(Top View)
OE
CAS
W3/DQ3
W4/004
Vss
W1/001
W2/002
• CAS-Before-RAS Refresh
WBiW
RAS
A9
AO
• Long Refresh Period ... 1024-Cycle
Refresh in 16 ms (Max)
A1
A2
A3
A4
vee
• 3-State Unlatched Output
A5
A6
A7
• Low Power Dissipation
'----~
A8
t The packages shown are for pinout reference only.
• Texas Instruments EPIC ™ CMOS Process
PIN NOMENCLATURE
• All Inputs/Outputs and Clocks are TTL
Compatible
AO-A9
CAS
W1/DQ1-W4/DQ4
• High-Reliability Plastic 300-mil and 350-mil
20/26-Lead Surface Mount (SOJ) Packages
and 20-Pin Zig-Zag In line (ZIP) Package
RAS
WBfN
• Operating Free-Air Temperature Range
... O°C to 70°C
VCC
VSS
Address Inputs
Column-Address Strobe
Write-Per-Bit Data Mask/Data In/Data Out
Output Enable
Row-Address Strobe
Write-Per-Bit Enable/Write Enable
5-V Supply
Ground
description
The TMS44410 series are high-speed 4 194 304-bit dynamic random-access memories, organized as
1 048 576 words of four bits each. They employ state-of-the-art EPIC ™ (Enhanced Process Implanted CMOS)
technology for high performance, reliability, and low power at a low cost.
These devices feature maximum RAS access times of 60 ns, 70 ns, 80 ns, and 100 ns. Maximum power
dissipation is as low as 360 mW operating and 6 mW standby.
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatc.hed to allow greater system flexibility.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA documents contain Information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily
Include testing of all parameters.
Copyright © 1991, Texas Instruments Incorporated
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TMS44410
,
1 048 576·WORD BY 4·BIT WRITE·PER·BIT
DYNAMIC RANDOM·ACCESS MEMORY
REV A- SMHS441 -JANUARY 1991
The TMS4441 0 is offered in a 350-mil20/26-lead plastic surface mount SOJ package (DM), a 300-miI20/26-lead
plastic surface mount SOJ package (DJ), and a 20-pin zig-zag in-line package (SD suffix). These packages are
guaranteed for operation from O°C to 70°C.
operation
enhanced page-mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is thus eliminated.
The maximum number of columns that may be accessed is determined by the maximum RAS low time and the
CAS page cycle time used. With minimum CAS page cycle time, all 1024 columns specified by column addresses
AO through A9 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS4441 0 to operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as column address is valid rather than when
CAS transitions low. This performance improvement is referred to as enhanced page mode. Valid column
address may be presented immediately after row address hold time has been satisfied, usually well in advance
of the falling edge of CAS. In this case, data is obtained after tCAC max (access time from CAS low), if tM max
(access time from column address) has been satisfied. Inthe event that column addresses for the next cycle are
valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence of tCAC
or tCPA (access time from rising edge of CAS).
write-per-bit operation
The TMS4441 0 allows for writing only to selected quadrants using write-per-bit operations. This is accomplished
by having WB/W low when RAS drops, which latches in the write mask from the Wn/DOn pins. For each quadrant
which the Wn/DOn pin is held low when RAS drops, the write operations will be inhibited and will remain inhibited
until RAS is taken high. The setup and hold times for both WB/W and Wn/DOn pins are referenced to the falling
edge of RAS. Write-per-bit functionality can be used on all write, read-write, page-mode, and hidden refresh write
cycles.
By keeping WB/W high when RAS drops, the TMS44410 will complete a standard, nonwrite-per-bit, write
operation (see tWBH).
address (AO through A9)
Twenty address bits are required to decode 1 of 1 048 576 storage cell locations. Ten row-address bits are set
up on inputs AO through A9 and latched onto the chip by the row-address strobe (RAS). The ten column-address
bits are set up on pins AO through A9 and latched onto the chip by the column-address strobe (CAS). All
addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable in that
it activates the sense amp'lifiers as well as the row decoder. CAS is used as a chip select activating the output
buffer, as well as latching the address bits into the column-address buffer.
write-per-bit enable/write enable 0NB/W)
The read or write mode is selected through the write-per-bit enable/write-enable (WB/W) input. A logic high on
the WB/W input selects the read mode and a logic low selects the write mode. The write-enable terminal can
be driven from standard TTL circuits without a pull-up resistor. The data input is disabled when the read mode
is selected. When WB/W goes low prior to CAS (early write), data out will remain in the high-impedance state
for the entire cycle permitting a write operation independent of the state of OE. This permits early write operation
to be completed with OE grounded.
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TMS44410
1 048 576-WORD BY 4-BIT WRITE-PER-BIT
DYNAMIC RANDOM.;ACCESS MEMORY
REV A -
SMHS441 -
JANUARY 1991
write-per-bit data mask/data in/out (W1/DQ1-W4DQ4)
The three-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS and OE are brought low. In a read cycle the output becomes valid after all access times are satisfied.
The output remains valid while CAS and OE are low. CAS or OE going high returns it to a high-impedance state.
This is accomplished by bringing OE high prior to applying data, thus satisfying tOED'
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers will remain in the high-impedance
state. Bringing OE low during a normal cycle will activate the output buffers putting them in the low-impedance
state. It is necessary for both RAS and CAS to be brought low for the output buffers to go into the low-impedance
state. Once in the low-impedance state, they will remain in the low-impedance state until either OE or CAS is
brought high.
refresh
A refresh operation must be performed at least once every sixteen milliseconds to retain data. This can be
achieved by strobing each of the1 024 rows (AO-A9). A normal read or write cycle will refresh all bits in each row
that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, thus conserving
power as the output buffer remains in the high-impedance state. Externally generated addresses must be used
for a RAS-only refresh. Hidden refresh may be performed while maintaining valid data at the output pin. This is
accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period,
similar to a RAS-only refresh cycle. The external address is ignored during the hidden refresh cycles.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS [see parameter .!c.sB] and holding it
low after RAS falls [see parameter tCHR)' For successive CAS-before-RAS refresh cycles, CAS can remain low
while cycling RAS. The external address is ignored and the refresh address is generated internally.
power-up
To achieve proper device operation, an initial pause of 200 Jls followed by a minimum of eight initialization cycles
is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
test mode
A Design For Test (OFT) mode is incorporated in the TMS4441 O. A CAS-before-RAS with WB/W low (WCBR)
cycle is used to enter test mode. In the test mode, data is written into and read from eight sections of the array
in parallel. All data is written into the array through 001. Data is compared upon reading and if all bits are equal,
all DO pins will go high. If anyone bit is different; all the DO pins will go low. Any combination read, write,
read-write, or page-mode can be used in the test mode. The test mode function reduces test times by enabling
the 1 meg x 4 DRAM to be tested as if it were a 512K DRAM where column address 0 is not used. A RAS-only
or CBR refresh cycle is used to exit the OFT mode.
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5-147
TMS44410
1 048 576·WORD BY 4~BIT WRITE·PER·BIT
DYNAMIC RANDOM·ACCESS MEMORY
REV A -
SMHS441 - JANUARY 1991
logic symbol t
RAM 1024K x 4
20D10/2100
9
10
AO
A1
A2
11
12
A3
14
A4
>A
15
16
AS
A6
0
1048575
17
A7
18
A8
A9
5
r--..
4
~
r--..
23
3
22
1
W1/D01
2
24
W2/D02
W3/D03
25
W4/D04
~
~
20D19/2109
C20[ROW]
G23/[REFRESH ROW]
24[PWR DWN]
C21 [COLUMN]
G24
&
P 23C22
2321D
24,25EN
r--.. G25
....,
t.-..
r
A,22D
'V 26
A,Z26
....
.."
~
,
....
.."
...
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12, for the SOJ packages.
functional block diagram
•
AO
A1
•
•
A9
I
•
Column
Address
Buffers
~
1/
16
/
Column Decode·
2
Ir--f-
128K Array
~
128K Array
R
16<
a
•
••
w
10
D
e
c
/
a
128K Array
•
•
•
-±
> 16
128KArray
.,
128KArray
j
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~,.
I/O
Buffers
4 of 16
Selection
2~
d
e
10
5-148
Mask
Data
Sense Amplifiers
'--
'---
~
I""
1
128KArray
Row
Address
Buffers
J J
TimIng and Control
8
L
•
•
•
~
HOUSTON. TEXAS 77001
HZ»
In
Reg.
~
Data
Out
Reg.
Air
W1/D 01W4/D 04
TMS44410
1 048 576-WORD BY 4-BIT WRITE-PER-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS441 -
JANUARY 1991
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee ............................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 rnA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 150°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation ofthe device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 20:AII voltage values in this data sheet are with respect to VSS.
recommended operating conditions
UNIT
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
V
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
°c
NOTES: 21. The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electricalcharacteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TMS4441 0-60
MIN
TMS4441 0-70
MAX
MIN
MAX
TMS4441 0-80
MIN
MAX
TMS44410-10
MIN
MAX
UNIT
VOH
High-level output
voltage
VOL
Low-level output
voltage
10L = 4.2 mA
0.4
0.4
0.4
0.4
V
II
Input current
(leakage)
VI=O to 6.5 V, VCC = 5.5 V,
All other pins = 0 V to VCC
±10
±10
±10
±10
I-lA
10
Output current
(leakage)
Vo = OtoVCC,
VCC = 5.5 V, CAS high
±10
±10
±10
±10
I-lA
ICC1
Read or write cycle
current (see Note 3)
Minimum cycle, VCC = 5.5 V
95
85
75
65
mA
After 1 memory cycle, RAS and
CAS high, VIH = 2.4 V (TTL)
2
2
2
2
mA
After 1 memory cycle, RAS and
CAS high, VIH = VCC - 0.2 V
(CMOS)
1
1
1
1
mA
ICC2
Standby current
2.4
10H =-5 mA
2.4
2.4
V
2.4
ICC3
Average refresh
current (RAS-only
orCBR)
(see Note 3)
Minimum cycle, VCC = 5.5 V,
RAS cycling CAS high
(RAS-only), RAS low after CAS
high (CBR)
95
85
75
65
mA
ICC4
Average page
current (see Note 4)
tpc = minimum, VCC = 5.5 V,
RAS low, CAS cycling
70
60
50
40
mA
NOTES: 22. Measured with a maximum of one address change while RAS = VIL.
23. Measured with a maximum of one address change while CAS", VIH.
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TMS44410
1 048 576-WORD BY 4-BIT WRITE-PER-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS441 -
JANUARY 1991
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f 1 MHz (see Note 5)
=
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(D)
Input capacitance, data inputs
5
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(OE)
Input capacitance, output enable
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 24:VCC equal to 5 V ± 0.5 V and the bias on pins under test
IS
0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
TMS44410-60
PARAMETER
MAX
MIN
TMS44410-70
MIN
MAX
TMS44410-80
MIN
MAX
TMS44410-10
MIN
MAX
UNIT
tM
Access time from column-address
30
35
40
45
tCAC
Access time from CAS low
15
18
20
25
ns
ns
tCPA
Access time from column precharge
35
40
45
50
ns
ns
tRAC
Access time from RAS low
60
70
80
100
tOEA
Access time from OE low
15
18
20
25
tCLZ
CAS to output in low Z
0
tOFF
Output disable time after CAS high
(see Note 6)
0
15
0
18
0
20
0
25
ns
tOEZ
Output disable time after OE high (see Note 6)
0
15
0
18
0
20
0
25
ns
0
0
NOTE 25:tOFF and tOEZ are specified when the output is no longer driven.
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0
ns
ns
TMS44410
1 048 576-WORD BY 4-BIT WRITE-PER-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS441 -
JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS4441 0-60
TMS4441 0-70
TMS4441 0-80
TMS4441 0-10
MIN
MIN
MIN
MIN
MAX
MAX
MAX
MAX
UNIT
tRC
Random read or write cycle (see Note 7)
110
130
150
180
ns
tRWC
Read-write cycle time
155
181
205
245
ns
tpc
Page-mode read or write cycle time
(see Note 8)
40
45
50
55
ns
tpRWC
Page-mode read-write cycle time
85
96
105
120
ns
tRASP
Page-mode pulse duration, RAS low
(see Note 9)
60
100000
70
100000
80
100000
100
100 000
ns
tRAS
Non-page-mode pulse duration, RAS low
(see Note 9)
60
10 000
70
10 000
80
10 000
100
10 000
ns
10000
18
10000
20
10 000
25
10 000
tCAS
Pulse duration, CAS low (see Note 10)
15
tcp
Pulse duration, CAS high
10
10
10
10
ns
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
70
ns
twP
Write pulse duration
15
15
15
20
ns
tASC
Column-address setup time before CAS low
0
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
0
ns
ns
tDS
Data setup time (see Note 11)
0
0
0
0
tRCS
Read setup time before CAS low
a
0
0
0
ns
tCWL
WBN/-Iow setup time before CAS high
15
18
20
25
ns
tRWL
WBN/-Iow setup time before RAS high
15
18
20
25
ns
twcs
WBN/-Iow setup time before CAS low
(Early write operation only)
0
0
0
a
ns
tWSR
WBN/-high setup time (CAS-before-RAS
refresh only)
10
10
10
10
ns
tWTS
WBN/-Iow setup time (test mode only)
10
10
10
10
ns
tCAH
Column-address hold time after CAS low
10
15
15
20
ns
tDHR
Data hold time after RAS low (see Note 12)
50
55
60
75
ns
tDH
Data hold time (see Note 11)
10
15
15
20
ns
tAR
Column-address hold time after RAS low
(see Note 12)
50
55
60
75
ns
tRAH
Row-address hold time after RAS low
10
10
10
15
ns
tRCH
Read hold time after CAS high (see Note 13)
0
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 13)
0
0
0
0
ns
twCH
Write hold time after CAS low
(Early write operation only)
15
15
15
20
ns
twCR
Write hold time after RAS low (see Note 12)
50
55
60
75
ns
tWHR
WBN/-high hold time (CAS-before-RAS
refresh only)
10
10
10
10
ns
tWTH
WBN/-Iow hold time (test mode only)
10
10
10
10
ns
tWBS
Write setup before RAS low (WPB)
0
0
0
0
ns
tWDS
Data setup before RAS low (WPB)
0
0
0
0
ns
tWBH
Write hold after RAS low (WPB)
10
10
10
10
ns
Continued next page.
NOTES: 26. All cycle times assume tr =5 ns.
27. To guarantee tpc min, tASC should be greater than or equal to tcp.
28.ln a read-write cycle, tRWD and tRWL must be observed.
29.ln a read-write cycle, tCWD and tCWL must be observed.
30. Referenced to the later of CAS or W in write operations.
31. The minimum value is measured when tRCD is set to tRCD min as a reference.
32. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
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5-151
TMS44410
1 048 576·WORD BY 4·BIT WRITE·PER·BIT
DYNAMIC RANDOM·ACCESS MEMORY
REV A- SMHS441 -JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
TMS4441 0·60
MAX
MIN
TMS4441 0·70
TMS4441 0·80
TMS44410·10
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
tWDH
Data hold after RAS low (WPB)
10
10
10
10
ns
tAWD
Delay time, column address to WBm low
(Read-write operation only)
55
63
70
80
ns
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
15
15
20
20
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
0
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
100
ns
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
10
ns
tCWD
Delay time, CAS low to WBm low
(Read-write operation only)
40
46
50
60
ns
tOEH
OE command hold time
15
18
20
25
ns
tOED
OE to data delay
15
18
20
25
ns
tROH
RAS hold time referenced to OE
10
10
10
10
tRAD
Delay time, RAS low to column-address (see
Note 14)
15
tRAl
Delay time, column-address to RAS high
30
35
40
45
ns
tCAl
Delay time, column address to CAS high
30
35
40
45
ns
tRCD
Delay time, RAS low to CAS low (see Note
14)
20
tRPC
Delay time, RAS high to CAS low
0
0
0
0
tRSH
Delay time, CAS low to RAS high
15
18
20
25
ns
tRWD
Delay time, RAS low to WBm low
(Read-write operation only)
85
98
110
135
ns
tTAA
Access time from address (test mode)
35
40
45
50
ns
tTCPA
Access time from column precharge (test
mode)
40
45
50
55
ns
tTRAC
Access time from RAS (test mode)
65
75
85
105
tREF
Refresh time interval
Transition time
tT
NOTE 33: The maximum value
30
45
15
25
16
IS
2
50
specified only to guarantee access time.
35
52
15
40
20
60
16
2
50
20
25
16
2
2
50
ns
50
75
~
Outpul Unde. Tesl
VCC
-l
T
ns
16
ms
50
ns
Output Under Test - - - - . - - - - - .
CL
= 100 pF
(a) Load Circuit
(b) Alternate Load Circuit
Figure 2. Load Circuits for Timing Parameters
TEXAS ~
INSlRUMENlS
5-152
=5V
R L o 21""
CL= 100pF
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
ns
ns
PARAMETER MEASUREMENT INFORMATION
1.31 V
ns
TMS44410
1 048 576-WORD BY 4-BIT WRITE-PER-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS441 -
JANUARY 1991
read cycle timing
NOTE 34: Output may go from three-state to an invalid data state prior to the specified access time.
TEXAS
.J!1
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
5-153
TMS44410
1 048 576-WORD BY 4-BIT WRITE-PER-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS441 -
JANUARY 1991
early write cycle timing
~1~-------------------------tRC------------------------~~1
I
I
--~\ :
RAS
:Jf-r--------..i{
tRP
~ ~
I
I
I
I
I
I
I
I~~-- tRCO -----.:~:
..
I~+-I- - - tCRP
I
1"II1~'---- tCAS ------.:~I I I
I
14~-----------
I
tASC -+I~-----~~I
I
I I I
I 1 I
1 I I
1 I I~
AO-A9
I
I ~I~-I-I- - - tcp ----~~I
~:
II
"'1
I
~tCAH
I ~I
I
I I
I I
I I
tCWL
I
1 I
I ~tRAO
~ I
I
I I~
I
~:
~
I~
I
~I
J<>.J.-
20"\1 ~
tWBH
i I~ ~
twOH:
twos
i~
~ I
I
I
~I
:
I.
II~
~l~gl-~ M.S~D.t. ~
~
I:
I
.
1
I
tRWl
I
~:
tWCR
1
'+-- tWCH - - . ,
I
~tOH ~
1
1
~I
VIH
~*kH~29920222L,L
.: \wc'
I:
~
twp
~I
~I
I
tos
~*t
14
14----------tWCR
tRWl
:
twos
~
1
1
1
14
Ma.kData
I
'
I
I
~I
' - - - - - - - - Vil
3~&22222m§}H*H~ :::
.
i+f-
1414---~.1c- tOH
I
I
I~----~
~l;ggl-~
VIL
~
1 I .
1 ~twP~
tos
~
1
VIH
__ :
wa;w~-.....-,.:-;..141----1.~1
_.....;7:~
tWBH -+-1
1 I
1
tWOH ,-.IooII14t---~~~1
1
1
1
~
1144-,-1- - - - - tCRP _____~~I
1 1
1 1
-~H\CH~,-----V'H
Column
twas
VIH
\ ' - - - - Vil
I
1 .,1
1
1
----.t~1
}f l " \
;{ ~lhl------ tcp ---------II~ L
1\.1
I
I
tRP
1 1 1
i~
: \;
~
~
T.
------------------¥
I..
1144-------- tRSH -----..~
tOHR --j1r---------j~~1
-----...,;1
~
~
I
I
,
v
~a"dData ~zH*~~v::
I+-tOEOI
I
1'i1114f------------ tOEH -----~~I
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-155
TMS44410
1 048 576-WORD BY 4-BIT WRITE-PER-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS441 -
JANUARY 1991
read-write cycle timing
~1.r--------------------tRWC----------------------~.'
~"'.----------------tRAS
RAS
-.I
"
!.- tr
I~ tRCO -.1'4
~
,
I,
1
tCAS
------~1
I
1
~ tCRP ~
I , 1
I..
. ' tCAH
1
, I
,
:::
tRP
"'1':--------:11
~
I I
~tRAH
1
1
~
VtH
}r-:
Y~tcp
!,\l
i++-tASR
~'-----
: ,.
7 ~1oII~f-------
i I
CAS
-----------------Y:
JL,'
...
VtL
,
1 ,
*- t~AO,
I
-.I
I ,
I!
I'
~~ASC:
--+j
;.+-, tr
1
,1
,
,
AO-A9~
I.
'tAR
I
R~W ~
,
,
,
~tw~s,
WBNl
,
I..'
,
,
,
: :I
:
~
twos
~
W1/0Q1W4/0Q4
~
,
1
,
1
,
,
I
,~.----~.~:
~:
~, ,
tRWO
1
,
!
~I.I------ tcwo ----~.,
1
,
.
,tos
tAA
~,
-.I
I
,~tCLZ ~,
1
~ twp
,
1
1
1
I
~
:
~
,
"'1
I+- tOH
,
"
(see Note 15)
tOEA
,
,
~tCAC ~
,
,
---~~\{ ~gH~~2m :::
tAWO
"
1
I.
,
I+-
,
tOEZ
,
1
,.
,
~,
,
,
,
~ tOEH
0Wl*21~~~~
..
~*21~%i2m VIH
VIL
NOTE 15: Output may go from three-state to an invalid data state prior to the specified access time.
TEXAS •
INSTRUMENTS
5-156
tRWL
I·
+.J
tRCS
1 4 - - - - tRAC - - - - - . ,
OE
--------VIL
,
,
"
~_.,..-_~
~
~ :
1
:~
,_."
'
1
........
tCWL
1
,
Wi.
:
1
~lrr.X~II,------VIH
co,:: mn
I
,
' :
,
twOH
.,
1
~tWBH
I
1
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44410
1 048 576-WORD BY 4-BIT WRITE-PER-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS441 - JANUARY 1991
enhanced page-mode read cycle timing
~
I
AO-A9
1
tOEZ
r-
VOL
.-1
~VIH
VIL
NOTES: 15. Output may go from three-state to an invalid data state prior to the specified access time.
35. Access time is tePA or tAA dependent.
TEXAS •
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-157
TMS44410
1 048 576-WORD BY 4-BIT WRITE-PER-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS441 -
JANUARY 1991
enhanced page-mode write cycle timing
NOTES: 36. Referenced to CAS or W, whichever occurs last.
37. A read cycle or a read-write cycle can be intermixed with write cycle as long as read and read-write timing specifications are not
violated.
TEXAS ~
INSTRUMENTS
5-158
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44410
1 048 576-WORD BY 4-BIT WRITE-PER-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A- SMHS441 -JANUARY 1991
enhanced page-mode read-write cycle timing
AO-A9
W1/0Q1W4/0Q4
NOTES: 15. Output may go from three-state to an invalid data state prior to the specified access time.
38. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-159
TMS44410
1 048 576-WORD BY 4-BIT WRITE-PER-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS441 -
JANUARY 1991
RAS-only refresh timing
~f$f~
W1/001W~004
TEXAS ~
INSlRUMENTS
5-160
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
VIH
~L
TMS44410
1 048 576-WORD BY 4-BIT WRITE-PER-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS441 -
JANUARY 1991
automatic (CAS-before-RAS) refresh cycle timing
~14~-------------------tRC--------------------~~1
~ tRP ~ 14 4------ tRAS ______________..~I
1'1
~
RAS
-----I!f
I
tRPC
I
Ii
\l
tWSR:~
~I-----VIH
Y
Y,..----------
~tCSR~ I
--.I ~
:
I I~~---- tCHR -----~~I
11~
tr
VIH
~L
I
~ ~--.~I-I tWHR
WB/'ii
AO-A9
VIH
W1j001- - - - - - - - - - - - - - - - - H I - Z - - - - - - - - - - - - - - W4j004
'TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-161
TMS44410
1 048 576-WORD BY 4-BIT WRITE-PER-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A- SMHS441 -JANUARY 1991
hidden refresh cycle (read)
~ Refresh Cycle ~
~ Memory Cycle ~
!4- Refresh Cycle ~
1
~I
tRP
1
1
RAS
CAS
I.
1 I~
1I
N
~I I
tRAS
I
11
I
1
I.
NI I
I
~I II~ tRAS ~I
I
yl
1
--..L......i-!--U i i i
I~
tAR
I ~I
1
~ I'+ t
1 II 1 CAH
1
1
~I :.-t+tASC
I~ 1 1 I 1
tRAH 71 j4-j
I I
1
tRP.
~r---{
I
tCAS
1 1
II
1 1
1 1
1 1
1 I
~
1
i
I
tCHR
'i,
1
1
1
1
1
1
rVIH
:~
~I
i
1 I...
VIL
1'::::
1
1
1
1
1
1
1
1
1
1
1
1
VIH
V
~?
~'L
A~A9~r~!·_~VIH
1
1
I~
I
I
I 1 1
1
,tRRH, ~
I I I I
I ~I tRCS
I 1 I
I I I
i
I
~
~
I
~tWHR
~
1
I
I
I
I
I
I
I 4j ~twSR
--"1
1
j4-tWHR
I,
I
1
I
TEXAS . .
POST OFFICE BOX 1443
•
I
~tWSR
INSTRUMENTS
5-162
1 1
~
1
HOUSTON, TEXAS 77001
--..1
~
I
~trlHR
VIL
I
I
I
l.-tWSR
I
VOH
TMS44410
1 048 576-WORD BY 4-BIT WRITE-PER-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMHS441 -
JANUARY 1991
hidden refresh cycle (write)
I
I....
Memory Cycle ---------..~ I~ Refresh Cycle ~I
----tRAS----.~1 ~tRP-.j
: 141
..
NI I
::
tRAH
i
N:
tCAS
I ... ~
1 1
I
I I
N
V
1 I
1 I
j1
141"--.~;-1-1-:
~I~
1 II 1
tJ,\SR
II
:
;-Ir---{
r
~
'L-I
I ~ IRAS --;
I I
tASC
~
1
tCHR
~i
VIH
VIL
~y- VIH
I
'/,
tCAH
I.
ill
VIL
1
tAR 1-1_ _~.I
1
1
1
AO-A9
TEXAS
-1.!1
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-163
TMS44410
,
1 048 576-WORD BY 4-BIT WRITE-PER-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A- SMHS441 -JANUARY 1991
test mode entry cycle
~14~-------------------tRC --------------------~.I
t.--
tRP ----.;
L
RAS _ _
N
----'~
tRPe
t+
~I ~
1
\J.
tWTS
41 - - - - - - - - tRAS ___________
1<11
J
t
CSR
14
WBiW~~~~~:
---+I
I
-:
1
r
Y
1414----, tCHR
.1
:
1 ;,-1- - - - - V I H
1
~
~.I
-----~.I
IT
y,..----------VIH
~
tWTH
VIL
.
~o~~,r;~r
VIH
VIL
W1/0Q1-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HI-Z - - - -_ _ _ _ _ _ _ _ _ __
W4/0Q4
device symbolization
-~
TI
P
Speed (-60, -70, -80, -10)
TMS44410 OM
-r
Package Code
WBP~~
Lot Traceability Code
l
Month Code
Assembly Site Code
Ole Revision Code
Wafer Fab Code
TEXAS . .
INSlRUMENTS
5-164
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
VIH
TMS416100
16 777 216-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A - SMKS61 0- REVISED JANUARY 1991
•
•
•
DZ Package
(Top View)
Organization ... 16777216 x 1
Single 5-V Power Supply (10% Tolerance)
0
Performance Ranges:
TMS416100-60
TMS416100-70
TMS416100-80
TMS4161 00-1 0
VSS
VCC
•
Enhanced Page Mode Operation for Faster
Memory Access
•
•
CAS-before-RAS Refresh
Q
RAS
A11
NC
CAS
NC
A9
A10
AO
A1
A2
A3
AS
A7
A6
A5
A4
VCC
VSS
NC
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME OR WRITE
CYCLE
tAA
tRAC
tCAC
(MAX)
(MIN)
(MAX)
(MAX)
110 ns
15 ns
30 ns
60 ns
70 ns
18 ns
35 ns
130 ns
80 ns
20 ns
40 ns
150 ns
100 ns
25 ns
45 ns
180 ns
W
Long Refresh Period ... 4096 Cycles
Refresh in 64 ms
•
3-State Unlatched Output
•
Low Power Dissipation
•
All Inputs, Outputs and Clocks are
TTL Compatible
z
o-
.~
~
a:
PIN NOMENCLATURE
AO-A11
CAS
D
NC
•
Operating Free-Air Temperature Range
... O°C to 70°C
•
This Specification Is Fu"y Compatible with
the Preliminary 16 Megabit DRAM
Specification From Hitachi.
Q
RAS
Vi
VCC
VSS
o
u.
Address Inputs
Column-Address Strube
Data In
No Connect
Data Out
Row-Address strobe
Write Enable
5-V Supply
Ground
Z
W
(.)
Z
description
The TMS416100 series are high-speed 16 777 216-bit dynamic random-access memories, organized as
16 777 216-bit words by one bit each. They employ state-of-the-art EPICTM (Enhanced Process Implanted
CMOS) technology for high performance, reliability, and low power at a low cost.
These devices feature maximum RAS access times of 60 ns, 70 ns, 80 ns, and 100 ns.
All inputs, outputs, and clocks, are compatible with Series 74 TTL. All addresses and data-in lines are latched
on-chip to simplify system deSign. Data out is unlatched to allow greater system flexibility.
The TMS416100 is offered in a 400-mil 24/28-pin surface mount SOJ package (DZ suffix). The package is
characterized for operation from O°C to 70 D C.
operation
enhanced page mode
Page mode operation allows effectively faster memory access by keeping the same row address and strobing
random column addresses onto the chip. Thus, the time required to set up and strobe row addresses for the same
page is eliminated. The maximum number of columns that can be addressed is determined by tRAS, the
maximum RAS-Iow width.
EPIC is a trademark of Texas Instruments, Incorporated
ADVANCE INFORMATION documents contain information on
~::el~r:~~~:~ ~~at~aect:~1~8~inlal~r :;~P~~hd:'C~~~crn~~~~~:
are subleet to change without notice.
TEXAS
JJ1
Copyright © 1991, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-165
~
c
«
TMS416100
16 777 216-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A- SMKS610-JANUARY 1991
The Column Address Buffers in this CMOS device are activated on the falling edge of RAS. They act as a
transparent or flow-through latch, while CAS is high. The falling edge of CAS latches the addresses into these
buffers and also serves as an output enable.
This feature allows the TMS4161 00 to operate at a higher data bandwidth than conventional page-mode parts,
since retrieval begins as soon as the column address is valid, rather than when CAS transitions low. The
performance improvement is referred to as "enhanced page mode". Valid column address may be presented
immediately after row address hold time has been satisfied, usually well in advance of the falling edge of CAS.
In this case, data is obtained after tCAC max (access time from CAS low), if tM max (access time from column
address) and tRAC have been satisfied. In the event that the column address for the next cycle is valid at the
time CAS goes high, access time is determined by the later occurrence of tCPA or tCAC'
address (AO-A11)
Twenty-four address bits are required to decode 1 of 16 777 216 storage cell locations. Twelve row-address bits
are set on inputs AO through A 11 and latched during a normal access and during RAS-only refresh as the device
requires 4096 refresh cycles. All addresses must be stable on or before the falling edges of RAS and CAS. RAS
is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as
a chip select, activating the output buffer, as well as latching the address bits into the column buffer.
write enable CN)
The read or write mode is selected through the write-enable Winput. A logic high on the W input selects the read
mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TIL circuits
without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low prior
to CAS (early write), data out will remain in the high-impedance state for. the entire cycle, permitting common
I/O operation.
data-in (D)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling of CAS
or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS and data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-modify-write
cycle, CAS will already be low, thus data will be strobed in by W with setup and hold times referenced to this
signal.
'data-out (0)
The three-state output buffer provides direct TIL compatibility (no pullup resistor required) with a fan-out of two
Series 74 TIL loads. The output is in the high-impedance (floating) state until CAS is brought low. In a read cycle
the output becomes valid at the latest occurrence of tRAC, tM, tCAC, or tCPA and remains valid while CAS is
low. CAS going high returns it to a high-impedance state. In a delayed-write or read-modify-write cycle, the output
does not change, but retains the state just read.
TEXAS •
INSTRUMENTS
5-166
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TMS416100
16 777 216-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMKS61 0 -
JANUARY 1991
refresh
A refresh operation must be performed at least once every sixty-four milliseconds to retain data. This can be
achieved by strobing each of the 4096 rows (AO-A 11). A normal read or write cycle wi" refresh a" bits in each
row that is selected. A RAS-only operation can be used by holding CAS at a high (inactive) level, thus conserving
power since the output buffer remains in the high-impedance state. Externa"y generated addresses must be
used for a RAS-only refresh. Hidden refresh may be performed by holding CAS atVIL after a read operation and
cycling RAS after the specified precharge period, similar to a RAS-only refresh cycle except with CAS held low.
Valid data is maintained at the output throughout the hidden refresh cycle. An internal refresh address provides
the refresh address during hidden refresh.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS (see parameter teSR) and holding
it low after RAS falls (see parameter teHR)' For successive CAS-before-RAS refresh cycles, CAS can
remain low while cycling RAS. For this mode of refresh, the external addresses are ignored and the refresh
address is generated internally.
power-up
To achieve proper device operation, an initial pause of 200 fls followed by a minimum of eight initialization cycles
is required after full Vee level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
test mode
The test mode is initiated with a CAS-before-RAS refresh cycle while simultaneously holding the W input low
(WCBR). The initiate cycle performs an internal refresh cycle while internally setting the device to perform
para"el read or write on subsequent cycles. While in test mode, any desired data sequence can be performed
on the device. The device exits the test mode if a CAS-before-RAS (CBR) refresh cycle, with W input held high,or
a RAS-only refresh (ROR) cycle is performed.
Test mode causes the part to be internally reconfigured into a 1024K x 16 bit device, with 16-bit para"el read
and write data path. Column addresses CAO, CA1, CA1O, and CA11 are not used. During a read cycle all 16
bits of the internal data bus are compared. If all bits are the same data state, the output pin will go high. If one
or more bits disagree, the output pin will go low. Test time in test mode can thus be reduced by a factor of 16,
compared to normal memory mode.
~I
I...
1
Exit Cycle
Entry Cycle
~I
~
Test Mode Cycle t
1
1
Normal
Mode
VIH
RAS
VIL
VIH
CAS
VIL
Vi
~
t The states of W,
:~ \
/
VIH
VIL
Data-in, and Address are defined by the type of cycle used during test mode.
Figure 1. Test Mode Cycle
TEXAS . .
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•
HOUSTON. TEXAS 77001
5-167
TMS416100
16777216-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMKS61 0 -
JANUARY 1991
logic symbol t
RAM 16 384K x 1
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
10
11
12
13
16
17
18
19
20
23
9
6
30012/21 DO ...
0
A 16383K
I"--.
'5
~
I"--.
25
w
o
4
2
~
C
31023/21011
C30 [ROW]
G33 [REFRESH ROW]
34 [PWR OWN]
C31 [COL]
G34
&
~ 33C32
33310
A, 320
34 EN
27
AV
Q
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
functional block diagram
..
AO
~
I
1
8
32
/
A1
•
•
•
A11
Column
Address
Buffers
·•
'--
-
Column Decode
4
256KArray
256KArray
R
256KArray
32
Row
Address
Buffers
"r-I-
Sense Amplifiers
-I-
L
•
~
~
Timing and Control
0
•
•
•
•
•
•
w
D
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c
11
j
~
256KArray
>32
0
1f-"
e
256KArray
256KArray
_"J
11
/
TEXAS
l.!1
INSlRUMENTS
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POST OFFICE BOX 1443
•
I/O
Buffers
1 of 32
Selection
4-
d
-
~r
HOUSTON, TEXAS 77001
1f.-
~
~
In
Reg.
Out
Reg.
D
Q
TMS416100
16 777 216-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A-SMKS610 - JANUARY 1991
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage on any pin (see Note 1) ...................................................... - 1 V to 7 V
Voltage on Vee :................................................................... -1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range ..................................................
to 70 0
Storage temperature range ...................................................... - 55°e to 150 0 e
ooe
e
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation ofthe device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
UNIT
V
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
°c
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST
CONDITIONS
VOH
High-level output
voltage
IOH =-5 mA
VOL
LOW-level output
voltage
10L = 4.2 mA
II
Input current
(Ieakage):t:
VI = 0 to 6.5 V,
All other pins = 0 V to
VCC
10
Output current
(Ieakage):t:
~OtoVCC,
ICC1
Read or write cycle
current (see Note 3)
Minimum cycle,
VCC =5.5V
ICC2
Standby current
TMS416100-60
MAX
MIN
2.4
TMS416100-70
MIN
MAX
TMS416100-80
MIN
MAX
2.4
2.4
TMS416100-10
MIN
MAX
UNIT
V
2.4
z
o
~
:5
a:
o
I.L
Z
0.4
0.4
0.4
0.4
V
±10
±10
±10
±10
flA
±10
±10
±10
±10
flA
90
80
70
60
mA
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V (TTL)
2
2
2
2
mA
After 1 memory cycle,
RAS and CAS high,
VIH =VCC-0.2V
(CMOS)
1
1
1
1
mA
W
CAS high
ICC3
Average refresh
current (RAS-only or
CSR):t:
RAS cycling, CAS high
(RAS-only), RAS low
after CAS low (CSR)
90
80
70
60
mA
ICC4
Average page
current (see Note 4):t:
RAS low, CAS cycling
70
60
50
45
mA
ICC7
Standby current
output enable:t:
RAS = VIH, CAS = VIL,
Data out = enabled
5
5
5
5
mA
:t: Minimum cycle, VCC = 5.5 V.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS ."
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5-169
(..)
Z
~
c
«
TMS416100
16 777 216-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMKS61 0 -
JANUARY 1991
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f =1 MHz (see Note 5)
MIN
PARAMETER
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(D)
Input capacitance, data input
5
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 5: VCC equal to 5.0 V ± 0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
TMS416100-60
PARAMETER
MAX
MIN
»c
~
z("")
m
-
Z
TMS416100·70
TMS416100·80
TMS416100·10
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tM
Access time from column-address
30
35
40
45
ns
tCAC
Access time from CAS low
15
18
20
25
ns
tCPA
Access time from column precharge
35
40
45
50
ns
tRAC
Access time from RAS low
60
70
80
100
tCLZ
CAS to output in low Z
0
0
0
0
ns
tOH
Output disable start of CAS high
3
3
3
3
ns
tOFF
Output disable time afte~ CAS high
(see Note 6)
0
15
0
NOTE 6: tOFF is specified when the output is no longer driven.
"
o
:c
3:
-~
o
z
TEXAS
-If
INSTRUMENTS
5-170
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
18
0
20
0
25
ns
ns
TMS416100
16 777 216-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A-SMKS610 -JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS416100·60
TMS416100·70
TMS4161 00·80
TMS416100·10
MIN
MIN
MIN
MIN
MAX
MAX
MAX
MAX
UNIT
tRC
Random read or write cycle (see Note 7)
110
130
150
180
ns
tRWC
Read-write cycle time
130
153
175
210
ns
tpc
Page-mode read or write cycle time
(see Note 8)
40
45
50
55
ns
tpRWC
Page-mode read-write cycle time
60
68
75
85
ns
tRASP
Page-mode pulse duration, RAS low
(see Note 9)
60
100000
70
100000
80
100000
100
100000
ns
tRAS
Non-page-mode pulse duration, RAS low
(see Note 9)
60
10000
70
10 000
80
10000
100
10000
ns
10000
18
10000
20
10 000
25
10000
ns
tCAS
Pulse duration, CAS low (see Note 10)
15
tcp
Pulse duration, CAS high
10
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
70
ns
twp
Write pulse duration
15
15
15
15
ns
tASC
Column-address setup time before CAS low
0
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
0
ns
tDS
Data setup time (see Note 11)
0
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
0
ns
tCWL
W-Iow setup time before CAS high
15
18
20
25
ns
tRWL
W-Iow setup time before RAS high
15
18
20
25
ns
twcs
W·low setup time before CAS low
(Early write operation only)
a
a
a
0
ns
tWSR
W-high setup time (CAS-before-RAS
refresh only)
10
10
10
10
ns
tWTS
W-Iow setup time (test mode only)
10
10
10
10
ns
tCAH
Columo-address hold time after CAS low
15
15
15
15
ns
tDHR
Data hold time after RAS low (see Note 12)
50
55
60
75
ns
tDH
Data hold time (see Note 10)
15
15
15
15
ns
tAR
Column-address hold time after RAS low
(see Note 12)
50
55
60
75
ns
tRAH
Row-address hold time after RAS low
10
10
10
10
ns
tRCH
Read hold time after CAS high (see Note 13)
0
0
a
a
ns
tRRH
Read hold time after RAS high (see Note 13)
5
5
5
5
ns
tWCH
Write hold time after CAS low
(Early write operation only)
15
15
15
15
ns
tWCR
Write hold time after RAS low (see Note 12)
50
55
60
75
ns
tWHR
W-high hold time (CAS-before-RAS
refresh only)
10
10
10
10
ns
tWTH
W-Iow hold time (test mode only)
10
10
10
10
ns
Continued next page.
NOTES: 7. All cycle times assume tT = 5 ns.
8. To guarantee tpc min, tASC should be greater than or equal to tcP.
9. In a read-write cycle, tRWD and tRWL must be obseNed.
1O.ln a read-write cycle, tCWD and tCWL must be obseNed.
11. Referenced to the later of-CAS or Win write operations.
12. The minimum value is measured when tRCD is set to tRCD min as a reference.
13. Either tRRH or tRCH must be satisfied for a read cycle .
. TEXAS
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INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-171
z
o
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a:
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W
CJ
Z
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s:
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TMS4161 00-70
TMS416100-80
TMS416100-10
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tAWD
Delay time, column address to W low
(Read-write operation only)
30
35
40
45
ns
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
20
20
20
20
ns
tCRP
Delay time, CAS high to RAS low
5
5
5
5
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
100
ns
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
10
ns
lCWD
Delay time, CAS low to W low
(Read-write operation only)
15
18
20
25
ns
tRAD
Delay time, RAS low to column-address
(see Note 14)
15
30
15
35
40
15
15
55
ns
tRAl
Delay time, column-address to RAS high
30
35
40
45
ns
tCAl
Delay time, column-address to CAS high
30
35
40
45
ns
tRCD
Delay time, RAS low to CAS low
(see Note 14)
20
tRPC
Delay time, RAS high to CAS low
0
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
25
ns
tRWD
Delay time, RAS low to W low
(Read-write operation only)
60
70
80
100
ns
tCPRH
RAS hold time from CAS precharge
35
40
45
50
ns
45
20
52
20
60
20
75
ns
tcpw
Delay time, W from CAS precharge
35
40
45
50
ns
tTAA
Access time from address (test mode)
35
40
45
50
ns
tTCPA
Access time from column precharge
(test mode)
40
45
50
55
ns
65
75
85
105
tTRAC
Access time from RAS (test mode)
tREF
Refresh time interval
tT
Transition time
64
3
30
64
64
3
30
30
3
3
NOTE 14:The maximum value is specified only to guarantee access time.
Z
PARAMETER MEASUREMENT INFORMATION
1.31 V
~
Output Unde. Tesl
VCC
R1
RL=218Q
~
CL=100pF
=828 Q
Output Under Test
T
CL=100pF
(a) Load Circuit
(b) Alternate Load Circuit
Figure 2. Load Circuits for Timing Parameters
TEXAS
~
INSlRUMENTS
5-172
=5V
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
ns
64
ms
30
ns
TMS416100
16777216·BIT
DYNAMIC RANDOM·ACCESS MEMORY
REV A -
SMKS61 0 -
JANUARY 1991
-read cycle timing
~I
tRC
tAAS _ _ _ _ _ _~~ /.
I
T\
¥!
"----------------"'!I I
~I
:
i
I ' - - - - - - - - - VIL
I
I
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I I ~I I
~tCAS~ I I I
tASH
r 4 - -____
~+-1 tAAD
~
I
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ROW:
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tASC
I
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tRAl
~:
tCAl
I " ' - - - - Vll
I I
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tACS
I
II
II
tAR
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:
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w~~~~?o'-I~;.u
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I
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tAA
II
(see ,Note 15)
I
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:
I I
141~-J..I--+-1- - t c p -----.!~I
tCLZ
r-'
:
I~
I I
I I~
~I I ~ _
.~I
I
t+-tAAH
I
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~
:E
tRCH
~~*HH20m v," oa:
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VIL
tOFF
tOH
Valid
~
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VOH
VOL
I
Z
W
(J
i
~I
z
o
Z
I~
tRAC
~I
NOTE 15: Output may go from three-state to an invalid data state prior to the specified access time.
~
c
«
TEXAS •
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5-173
TMS416100
16 777 216-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A- SMKS610-JANUARY 1991
early write
cycl~
timing
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TEXAS •
INSTRUMENTS
5-174
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
VOH
TMS416100
16 777 216-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMKS61 0 -
JANUARY 1991
write cycle timing
~VIH
I
I
I
VIL
tcp----~~I
z
o
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a::
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LL
Z
W
(.)
Z
~
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«
TEXAS
-III
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-175
TMS416100
16 777 216-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A- SMKS610-JANUARY 1991
-.l
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~
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NOTE 15: Output may go from three-state to an invalid data state prior to the specified access time.
TEXAS . .
INSTRUMENTS
5-176
POST OFFICE BOX 1443
•
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TMS416100
16 777 216-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A-SMKS610 -JANUARY 1991
enhanced page-mode read cycle timing
.1 1
tRASP
1
~
I~
N,
-
1
1
1
1
1
1
tCS'H
:
N
.'
~tCAS~
1
: :
1 ,-
1
1
1 1
~ tRAH -+!
~
I"""
I~
~
1
, tCAH 1
tASC'
1
1
I~
I"
tRAL
tCAL
Wm¥~tRAD~
1
1
1
I..
w
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tAA
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1
I
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tcLZ~
I
1-
tOH
~ tCAC -+I
I
1II1I
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W
~l
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tCRP
I I I
N'
D_~~a~_
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1II1I
fcrt
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RWO
:t
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VIH'
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2@(: Column
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-.:
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tCLZ ~
I
tCPA
1II1II
:
(see Note 15)
_: I
l+-
:
1
I
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II
I
I
I
I
:
(see Note 15)
a ----...;....--......;-----<>CX)(XX
I
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VOH
Valid Out
TEXAS ~
INSTRUMENTS
•
HOUSTON, TEXAS 77001
~
a:
a:
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I 14
tWSR ---14:-1--1-.,.1
:I~
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VIL
t...--".+-I tWHR
,w~
VIH
VIL
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VIH
VIL
VOH
Q ---------------HI-Z ---------------
VOL
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test mode exit cycle (CAS-before-RAS refresh cycle)
z
TEXAS
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5-184
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
VIH
VIL
VIH
VIL
VOH
TMS416100
16 777 216·81T
DYNAMIC RANDOM·ACCESS MEMORY
REV A -
SMKS61 0 -
JANUARY 1991
device symbolization
-¥
TI
D
Speed (-60, -70, -80, -10)
TMS416100 DZ
.--
Package Code
~_AP~!:F
Lot Traceability Code
I
Month Code
Assembly Site Code
Die Revision Code
Wafer Fab Code
TEXAS •
INSTRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-185
TMS416100
16 777 216-81T
DYNAMIC RANDOM-ACCESS MEMORY
REV A- SMKS610 -JANUARY 1991
TEXAS l!I
INSTRUMENTS
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POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
1MS416400
4 194 304-WORD BY 4-B11
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
•
•
•
Organization ... 4 194 304
x
JANUARY 1991
DZ Package
(Top View)
4
Single 5-V Power Supply (10% Tolerance)
Performance Ranges:
TMS416400-60
TMS416400-70
TMS416400-80
TMS416400-10
SMKS640 -
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME OR WRITE
CYCLE
tAA
tCAC
tRAC
(MAX)
(MAX)
(MAX)
(MIN)
15 ns
30 ns
110 ns
60 ns
70 ns
18 ns
35 ns
130 ns
150 ns
80 ns
20 ns
40 ns
25 ns
45 ns
180 ns
100 ns
•
Enhanced Page Mode Operation for Faster
Memory Access
•
•
CAS-before-RAS Refresh
•
•
•
3-State Unlatched Output
Vee
Vss
DQ1
DQ2
DQ4
DQ3
CAS
Vii
Long Refresh Period ... 4096 Cycles
Refresh in 64 ms
RAS
A11
A9
A10
AO
A1
A2
A3
A8
A7
A6
A5
A4
Vee
VSS
DE
z
o
~
Low Power Dissipation
~
PIN NOMENCLATURE
A" Inputs, Outputs, and Clocks are
TTL Compatible
AO-A11
•
Operating Free-Air Temperature Range
... O°C to 70°C
DQ1-DQ4
OE
RAS
•
This specification is Fu"y Compatible with
the Preliminary 16 Megabit DRAM
Specification From Hitachi
eAS
W
vec
vss
a:
Address Inputs
Column-Address Strobe
Data In/Data Out
Output Enable
Row-Address Strobe
Write Enable
5-V Supply
Ground
ou.
Z
W
o
Z
description
The TMS416400 series are high-speed 16 777 216-bit dynamic random-access memories, organized as
4 194 304-bit words by four bits each. They employ state-of-the-art EPICTM (Enhanced Process Implanted
CMOS) technology for high performance, reliability, and low power at a low cost.
These devices feature maximum RAS access times of 60 ns, 70 ns, 80 ns, and 100 ns.
All inputs, outputs, and clocks, are compatible with Series 74 TTL. All addresses and data-in lines are latched
on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS416400 is offered in a 400-mil 28/24-pin surface mount SOJ package (DZ suffix). The package is
characterized for operation from O°C to 70°C.
EPIC is a trademark of Texas Instruments, Incorporated
ADVANCE INFORMATION documents contain Information on
new products In the sampling or preproduction phase of
development Characteristic data and other specifications ar.
sublect to chang. without notice.
Copyright © 1991, Texas Instruments Incorporated
TEXAS ."
INSTRUMENTS
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HOUSTON, TEXAS 77001
5-187
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18
4194303
19
20
23
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26
27
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2.
3
C20[ROW]
G23/[REFRESH ROW]
l.... .
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A,Z26
... ..
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...
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
TEXAS
-1!1
INSlRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5-191
TMS416400
4 194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMKS640 - JANUARY 1991
functional block diagram
Vi
AO
A1
·•
•
A11
I
•
Column
Address
Buffers t
L--
~
Timing and Control
1
32
8
/
Column Decode
2
256KArray
0
••
•
32<
1:---
t Column Address 10 and Column Address 11
••
•
0
e
c
/
-
256KArray
w
11
-
0
256KArray
256KArray
-'1
/
are not used.
TEXAS
-1!1
INSTRUMENTS
5-192
POST OFFICE BOX 1443
•
L1;
32
110
Buffers
4 of 32
Selection
2_
d
e
11
,
256KArray
R
256KArray
Row
Address
Buffers
\.-/-
Sense Amplifiers
-I-
L
•
•
•
~.
J_ J
HOUSTON, TEXAS 77001
1f..--
~
In
Reg.
~"
Data
Out
Reg.
A~
001-004
TMS416400
4 194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMKS640 -
JANUARY 1991
absolute maximum ratings over operating free-air temperature t
Voltage on any pin (see Note 1) ........................................ . . . . . . . . . . . . .. - 1 V to 7 V
Voltage range on Vee .......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 1 V to 7 V
Short circuit output current ................................................................ 50 rnA
Power dissipation .......................................................................... 1 W
to 70 0
Operating free-air temperature range ..................................................
Storage temperature range ...................................................... - 55°e to 150 0 e
ooe
e
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
°c
UNIT
V
NOTE 2: Then algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST
CONDITIONS
VOH
High-level output
voltage
10H =-5 mA
VOL
Low-level output
voltage.
10L = 4.2 mA
II
Input current
(leakage)*
VI = 0 to 6.5 V,
All other pins = 0 V to
VCC
10
Output current
(leakage)*
'YsJ...:: 0 to VCC,
ICC1
Read or write cycle
current (see Note 3)
Minimum cycle,
VCC = 5.5 V
ICC2
Standby current
TMS416400-60
MIN
MAX
TMS416400-70
MIN
2.4
MAX
2.4
0.4
TMS416400-80
MIN
MAX
2.4
0.4
TMS416400-10
MIN
MAX
V
2.4
0.4
UNIT
0.4
V
:z
o
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~
a:
o
LL
Z
W
()
±10
±10
±10
±10
fAA
±10
±10
±10
±10
fAA
90
80
70
60
mA
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V (TTL)
2
2
2
2
mA
After 1 memory cycle,
RAS and CAS high,
VIH = VCC - 0.2 V
(CMOS)
1
1
1
1
mA
CAS high
ICC3
Average refresh
current (RAS-only or
CSR)*
RAS cycling CAS high
(RAS-only), RAS low
after CAS low (CSR)
90
80
70
60
mA
ICC4
Average page
current (see Note 4)*
RAS low, CAS cycling
70
60
50
45
mA
ICC7
Standby current
output enable:!:
RAS = VIH, CAS = VIL,
Data out = enabled
5
5
5
5
mA
:!: Minimum cycle, VCC = 5.5 V.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one adddress change while CAS = VIH.
TEXAS •
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5-193
Z
~
c
«
TMS416400
4 194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMKS640 -
JANUARY 1991
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
MIN
PARAMETER
TYP
MAX
UNIT
pF
Ci(A)
Input capacitance, address inputs
5
Ci(RC)
Input capacitance, strobe inputs
7
pF
7
pF
7
'pF
10
pF
Ci(OE)
Input capacitance, output enable
Ci(W)
Input capacitance, write-enable input
Co
Output capacitance
NOTE 5: VCC equal to 5.0 V ± 0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
TMS416400-60
PARAMETER
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MAX
MIN
TMS416400-70
TMS416400-80
TMS416400-10
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
tM
Access time from column-address
30
35
40
45
ns
tCAC
Access time from CAS low
15
18
20
25
ns
tCPA
Access time from column precharge
35
40
45
50
ns
tRAG
Access time from RAS low
60
70
80
100
ns
tOEA
Access time from OE low
15
18
20
25
ns
tCLZ
CAS to output in low Z
0
0
0
0
ns
tOH
Output disable start of CAS high
3
3
3
3
ns
tOHO
Output disable time start of OE high
3
3
3
3
ns
tOFF
Output disable time after CAS high
(see Note 6)
0
15
0
18
0
20
0
25
ns
tOEZ
Output disable time after OE high
(see Note 6)
0
15
0
18
0
20
0
25
ns
NOTE 6: tOFF is specified when the output is no longer driven.
$:
~
o
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TEXAS
~
INSTRUMENlS
5-194
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
1MS416400
4 194 304-WORD BY 4-B11
DYNAMIC RANDOM-ACCESS MEMORY
REVA-SMKS640-JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS416400·60
MAX
MIN
TMS416400·70
TMS416400·80
TMS416400·10
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
tRC
Random read or write cycle (see Note 7)
110
130
150
180
ns
tRWC
Read-write cycle time
155
181
205
245
ns
tpc
Page-mode read or write cycle time
(see Note 8)
40
45
50
55
ns
tpRWC
Page-mode read-write cycle time
85
96
105
120
ns
tRASP
Page-mode pulse duration, RAS low
(see Note 9)
60
100 000
70
100 000
80
100 000
100
100 000
ns
tRAS
Non-page-mode pulse duration, RAS low
(see Note 9)
60
10 000
70
10 000
80
10 000
100
10000
ns
10 000
18
10 000
20
10 000
25
10000
ns
tCAS
Pulse duration, CAS low (see Note 10)
15
tcp
Pulse duration, CAS high
10
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
70
ns
twp
Write pulse duration
15
15
15
15
ns
tASC
Column-address setup time before CAS low
0
a
a
a
a
a
0
ns
0
ns
0
0
ns
tASR
Row-address setup time before RAS low
0
tDS
Data setup time (see Note 11)
0
tRCS
Read setup before CAS low
0
0
0
0
ns
tCWL
W-Iow setup time before CAS high
15
18
20
25
ns
tRWL
W-Iow setup time before RAS high
15
18
20
25
ns
twcs
W·low setup time before CAS low
(Early write operation only)
0
a
0
0
ns
tWSR
W-high setup time (CAS-before-RAS
refresh only)
10
10
10
10
ns
twrs
W-Iow setup time (test-mode only)
10
10
10
10
ns
tCAH
Column-address hold time after CAS low
15
15
15
15
ns
tDHR
Data hold time after RAS low (see Note 12)
50
55
60
75
ns
tDH
Data hold time (see Note 11)
15
15
15
15
ns
tAR
Column-address hold time after RAS low
(see Note 12)
50
55
60
75
ns
tRAH
Row-address hold time after RAS low
10
10
10
10
ns
tRCH
Read hold time after CAS high (see Note 13)
0
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 13)
5
5
5
5
ns
tWCH
Write hold time after CAS low
(Early write operation only)
15
15
15
15
ns
tWCR
Write hold time after RAS low (see Note 12)
50
55
60
75
ns
tWHR
W-high hold time (CAS-before-RAS refresh
only)
10
10
10
10
ns
twrH
W-Iow hold time (test mode only)
10
10
10
10
ns
Continued next page.
NOTES: 7. All cycle times assume tT = 5 ns.
8. To guarantee tpc min, tASC should be greater than or equal to tcp.
9. In a read-write cycle, tRWD and tRWL must be observed.
1O.ln a read-write cycle, tCWD and tCWL must be observed.
11. Referenced to the later of CAS or Win write operations.
12. The minimum value is measured when tRCD is set to tRCD min as a reference.
13. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS •
INSlRUMENTS
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•
HOUSTON, TEXAS 77001
5-195
z
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a:
o
LL
Z
W
()
Z
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TMS416400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
REVA-SMKS640-JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
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TMS416400-60
TMS416400-70
TMS416400-80
MIN
MIN
MIN
MAX
MAX
MAX
TMS416400-10
MIN
UNIT
MAX
tAWD
Delay time, column address to W low
(Read-write operation only)
55
63
70
80
ns
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
20
20
20
20
ns
tCRP
Delay time, CAS high to RAS low
5
5
5
5
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
100
ns
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
10
ns
tCWD
Delay time, CAS low to W low
(Read-write operation only)
40
46
50
60
ns
tOEH
OE command hold time
15
18
20
25
ns
tOED
OE to data delay
15
18
20
25
ns
tROH
RAS hold time referenced to OE
10
10
10
10
ns
tRAD
Delay time, RAS low to column-address
(see Note 14)
15
tRAL
Delay time, column-address to RAS high
30
tCAl
Delay time, column-address to CAS high
30
tRCD
Delay time, RAS low to CAS low
(see Note 14)
20
30
45
15
35
15
40
15
55
ns
35
40
45
ns
35
40
45
ns
20
52
20
60
20
75
ns
tRPC
Delay time, RAS high to CAS low
0
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
25
ns
tRWD
Delay time, RAS low to W low
(Read-write operation only)
85
98
110
135
ns
tCPRH
RAS hold time from CAS precharge
35
40
45
50
ns
tcpw
Delay time, W from CAS precharge
55
63
70
80
ns
tTAA
Access time from address (test mode)
35
40
45
50
ns
tTCPA
Access time from column precharge
(test mode)
40
45
50
55
ns
tTRAC
Access time from RAS
(test mode)
65
75
85
105
ns
tREF
Refresh time interval
tr
Transition time
64
3
30
64
3
NOTE 14:The maximum value is specified only to guarantee access time_
TEXAS
-Ill
INSlRUMENTS
5-196
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
30
64
3
30
3
64
ms
30
ns
TMS416400
4 194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMKS640 -
JANUARY 1991
PARAMETER MEASUREMENT INFORMATION
1.31 V
~
VCC =5V
RL =2'8"
Qu,pu, Unde,Te.' ~
CL=100pF
Output Under Test
T
CL=100pF
(b) Alternate Load Circuit
(a) Load Circuit
Figure 2. Load Circuits for Timing Parameters
read cycle timing
14
'
N
~ ~
tRC
1"4
:
~t
tRAS
1
}'
I
I
I
I
.1
tT
~I
I
I
I I...
tCSH
I i4- tRCD - - + i
1
I I'
j4
I I
I i i
.1
tRSH
i
I
~ tRP
I
I
I
I
I
1
1
1
I
:
I
I
1
14
I
I
I:.
:4
A~Al1 ~ ROW: ~
it
'I
,... tRCS
~
w~~*2f1W1I
1
!
001.004 - - - -.....1- - HI-Z
1
14
14
:1
I 1 I
1 1 I
1 1 I
.1 1 I
I tRAL
I 1
VIL
a:
------J-X'\- - - - - - VIL
1
~
i
t4--tCAC
ItAA
I i+'
tRRH
::
~IRCH
/+-'CAH
I ::I ~~i-2~H~ :'H
~ I
~II :4 I.- : to~FF
.
(see Note 15)
.1
tCLZ IIIf
tRAC
~tOEA
IL
:~:I
VOH
Valid Data Out
'
~~_ _ _ _ _ _....;;;
I' I
.1
I
-.I:
I
m0§~tt~~i~~tROH~
1
:
14
1
.,
VOL
tOHO
I
**tOEZ
~~I
~~~~~~'(c~~at~~~
VIH
VIL
NOTE 15:0utput may go from three·state to an invalid data state prior to the specified access time.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443
•
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tAR
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5·197
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TMS416400
4 194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMKS640 -
JANUARY 1991
early write cycle timing
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TEXAS ~
INSTRUMENTS
5-198
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
1MS416400
4194 304-WORD BY 4-B11
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMKS640 -
JANUARY 1991
write cycle timing
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TEXAS . .
INSlRUMENTS
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5-199
TMS416400
4 194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A -
SMKS640 - JANUARY 1991
read-write cycle timing
CAS
~
1
1
1
1
AO-A11~
»
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1
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I
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:s:
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oz
tOEA -Iwlllll----..
~*~X~~~~
OE§000)~X~~~~
NOTE 15: Output may go from three-state to an invalid data state prior to the specified access time.
TEXAS
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INSTRUMENTS
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POST OFFICE BOX 1443
•
HOUSTON, TEXAS 17001
VIH
VIL
TMS416400
4 194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A - SMKS640 - JANUARY 1991
enhanced page-mode read cycle timing
~
1
Column
AO·11
I~
~tRCS~
Wm¥~tRAD~
1
1
1
~
~~~~~~Q.
tAr -i-~I--~
1 - 4 - - - - - tAA --'---J..I----1~
I~ tRCH ----.I
(see Note 16)
1
I
W)'l
lax VIH
1
Wi:
!
1
1
14-- tCAC ~
114~-t-1tAA
"I
tRAC
"I
tCLZ -jol~
___-~
DQ1.DQ4-------------~''X'J.'J.'J.~
I
(see Note 15)
1
1
'(i
---+---i-I----1~1
"I
tCPA
I
(see Note 16) 1 1
1
VIL
t4-- tRRH ~
:
. VIL
1
~tOFF~
~tOH
.. :
VOH
Valid
Out
r..~
~
Valid
Out
I
tOHO
I+-tOEZ
tOHO
i'4
I tOEzl
OE~~HfL~toEA-J ~tOEA~
~
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VOL
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VIL
NOTES: 15. Output may go from three-state to an invalid data state prior to the specified access time.
16. Access time is tePA or tAA dependent.
W
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TEXAS •
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5-201
TMS416400
4194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REV A - SMKS640 -
JANUARY 1991
enhanced page-mode write cycle timing
Column
AO-A11
' 4 - - - tWCR
»
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1
1
~I
1
I~ 1 I
14------+-1-1-1 tOHR
.1 twp
1
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I
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--+;
~
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1
I~
~
I.
(see Note 17)
tos
tos
I
1
1
~I I~ I
: .1
1
~ tOH
tOH
(see Note 17)
1
1
OQ1-OQ4~-------va-lI-d-O-at"-a-ln-------~
11
I
~
o
:IJ
s:
~
1
~ tOEH --.:I
V~~ld
)@0~~~~:-7'o~~n'~f~~a~~~e2~«~V'H
I
I
~L
NOTES: 17. Referenced to CAS or iN, whichever occurs last.
18. A read cycle or a read-write cycle can be intermixed with write cycle as long as read and read-write timing specifications are not violated.
o
z
TEXAS ~
INSTRUMENTS
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TMS416400
4194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
REVA-SMKS640-JANUARY 1991
enhanced page-mode read-write cycle timing
tRP~
I
~
I
-RA-S N-1------------tRAsp-------------~~ VIH
I
~14t-----tC-S-H-__-_-_-_-_-_-_--1-~~--I-~::=========-tC-P-R-H----------------------l.~1
I I
I I
I 1II1II
CAS
:
~
,
i
~
tRCO
~,
'tIIIII
•
l1I'IIIIII----tRSH
,
~
N-tCAS
~ tASR
I...
tPRWC
I11III
I .1
I I
I
I ,
tcp
,
I
tAR
1
,.. I
tCRP
I
:
I
VIL
I
.1
,
;r-+:--':
,
I
,
I
-.,,~tASC:
.'1
- - - - i...1
VIH
VIL
AO·A11
tRAH
~
I
W
*-
II
I
~ tAWO
,II1II
II
~
~~~~~~~~~~c.:.VIL
,
,+-tcwo ~
I
I
--.:
tRWO
:' I
I
tcpw
I11III
~
~ L,..- tRWL -.l
I
I
I
I
I
I
I
1II1II
I
I
I
i\!~
~I i~r~--.thRww'!"!:
!'\
ItllllI
I
I
I
I III "
I II ,
I
... 1
~
I
~ I· .... I tRCS
1II1II, .1 tAA
I
iIIIII- tRAC '-+-I
~ tCWL --..l
I
I ....
~tCPA ~
I
1l1li
~
z
V,H
~ VIL
.1 tOEH
I
,
Valid Out
I
~ ~
tos
I
(see Note 15) I
," "1"tCAC I
I
~I I
VIHNOH
O Q 1 . 0 Q 4 - - - - - - -.....
1
I
~
Valid
~
1
Valid
~I_ _ _ _ _ __
I
_
In
.
In
I
~I I I I
I
I
I
VILNOL
tCLZ ~
Valid Outl
I
I
~,
tOEZ ~
I'11III
~ tOED
I
~ tOEA -.I II
14---.~t-, tOEH :
I
~
L/it-----...,;\XXXXXXXXXXXX~~~-~VIH
OE
tOHO
~
........................_ ................ VIL
.1
I
I
I+f-
tOH
I
I
I
I
~
'+t ,
rIIIII-
!!.,,-I
XXXX)6<)L
--'y ,..-
NOTES: 15.0utput may go from three-state to an invalid data state prior to the specified access time.
19.A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
TEXAS
-1!1
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5-203
o
~
~
a:
o
u.
Z
W
U
Z
~
c
A
2~
-
w 21~
0
1 04B 575
C21 [COL]
~
&
> 23C22
-23.210
24EN
-,
oa1
oa2
3
10
Oa4
13
Oa5
16
oas
20
oaB
A,Z31
6"4.- \l 31
Oa3
Oa7
r
A,220
~
..
~
~~
~
..
23
25 .....
t This symbol is in accordance with ANSI/lEEE Std. 9-1084 and lEG Publication 617-12.
TEXAS •
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6-9
TM024GAD8
1 048 576 BY 8-BIT
DYNAMIC RAM MODULE
SMMS10BA- MARCH 1990 - REVISED NOVEMBER 1990
functional block diagram
AO 4
5
A1
7
A2
B
A3
11
A4
12
AS
14
AS
15
A7
17
AB
18
"
"
A9
27
2
21
~ AO·A9
~ RAS
kr::, CAS
~ AO·A9
f-b RAS
I
f-r::, CAS
r--
001
1024K x 1
3
-
T
......
W
0
VCC Vss
all
16
DOS
T
1024K x 1
RAS
~ CAS
r--
002
6
T
...
0
~ AO·A9
RAS
~ CAS
Lt:,
......
10
003
~
......
VCC
VCC
VSS
VSS
13
1
T
006
VCC Vss
all
VCC Vss
......
W
1
0
~
......
W
all
25
008
301 _
1
Vcc Vss
TEXAS ~
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HOUSTON, TEXAS 77001
all
AO·A9
1024K x 1
CAS
W
0
Vcc Vss
I
ht c ... c T
all
1024K x 1
L-.b RAS
INS1RUMENlS
6·10
1024K x 1
W
T0
23
007
01
~ CAS
Lr-
VCC Vss
VCC Vss
~ AO·A9
~ RAS
1----r:> CAS
1024K x 1
RAS
CAS
0
20
1024K x 1
W
0
L..r::::,
004
a'l
T
Lr- AO·A9
0
~ RAS
r-...
W
VCC Vss
W
~ AO·A9
~ AO·A9
~
1024K x 1
all
TM024GAD8
1 048 576 BY 8-BIT
DYNAMIC RAM MODULE
SMMS108A- MARCH 1990- REVISED NOVEMBER 1990
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ... :............................................. - 1 V to 7 V
Voltage range on Vee (see Note 1) ..................................... '. . . . . . . . . . . . .. - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 8 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ...................................................... - 65°C to 150°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation ofthe device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.75
5
5.25
V
4.5
5
5.5
V
2.4
6.5
V
-1
0.8
V
70
°c
VCC
Supply voltage (TM024GAD8-6)
VCC
Supply voltage (TM024GAD8-70/-80/-1 0)
VIH
High-level input voltage
VIL
Low-level input voltage (see Note 2)
TA
Operating free-air temperature
0
UNIT
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
TM024GAD8·6
PARAMETER
TEST CONDITIONS
VOH
High-level output
voltage
10H =-5 mA
VOL
Low-level output
voltage
10L = 4.2 mA
II
Input current
(leakage)
TM024GAD8·70
MAX
MIN
2.4
MIN
MAX
2.4
TM024GAD8·80
MIN
MAX
2.4
TM024GAD8-10
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
0.4
V
VI = 0 to 6.5 V, VCC = 5.5 V,
All other pins = 0 V to VCC
±10
±10
±10
±10
flA
10
Output current
(leakage)
Vo = OtoVCC,
VCC = 5.5 V, CAS high
±10
±10
±10
±10
flA
ICCl
Read or write
cycle current
Minimum cycle,
VCC=5.5V
760
640
600
520
mA
Standby current
After 1 memory cycle, RAS
and CAS high, VIH = 2.4 V
16
16
16
16
mA
ICC3
Average refresh
current (RASonlyorCSR)
Minimum cycle, VCC = 5.5 V,
RAS cycling, CAS high (RASonly), RAS low after CAS low
(CSR)
720
640
560
480
mA
ICC4
Average page
current
560
480
400
360
mA
ICC2
tc(p)=minimum, VCC=5.5 V,
RAS low, CAS cycling
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
40
pF
Ci(RC)
Input capacitance, strobe inputs
40
pF
Ci(W)
Input capacitance, write-enable input
40
pF
Co
Output capacitance (DQ1-D08)
10
pF
NOTE 3: Vee equal to 5 V ± 0.5 V and the bias on pins. under test is 0 V.
TEXAS •
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6-11
TM024GAD8
1 048 576 BY 8·BIT
DYNAMIC RAM MODULE
SMMS1 OBA- MARCH 1990 -
REVISED NOVEMBER 1990
TI single-in-line package nomenclature
TM
024
024
Page Mode
G
AD
AD Package
(89,15 x 20,49 mm) (max)
(3.51 x 0.807 Inches)
(max)
TEXAS 1JI
INSTRUMENTS
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POST OFFICE BOX 1443
•
80
8
HOUSTON, TEXAS 77001
MIn Access
- 6
60 ns
-70 70 ns
- 80 80 ns
-10 100 ns
L
TM124GU8A
1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE
SMMS181 -
This Data Sheet is Applicable to All
TM124GUBAs Symbolized with Revision "B"
and Subsequent Revisions as Described on
Page 6-19.
•
•
•
•
U Single-in-Line
Package
(Top View)
1 048 576 x 8 Organization
VCC
CAS
D01
AO
A1
D02
A2
A3
VSS
D03
A4
A5
D04
A6
A7
D05
AB
A9
NC
D06
Single 5-V Power Supply
30-Pin Single-In-Line Package (SIP)
TM124GU8A Utilizes Two 4-Megabit
Dynamic RAMs in Plastic Small-Outline
J-Lead Packages (SOJs)
•
Long Refresh Period
... 16 ms (1024 Cycles)
•
All Inputs, Outputs, Clocks Fully TTL
Compatible
•
•
3-State Outputs
Performance Ranges:
ACCESS
ACCESS
READ
TIME
TIME
OR
(tRAC)
(tAA>
VCC
TOLERANCE
W
VSS
D07
NC
DOB
NC
RAS
NC
NC
VCC
WRITE
CYCLE
•
•
JANUARY 1991
(MAX)
(MAX)
(MIN)
'124GUBA-6
60 ns
30 ns
110 ns
±5%
'124GUBA-70
70 ns
35 ns
130 ns
±10%
'124GUBA-BO
BO ns
40 ns
150 ns
±10%
'124GUBA-10
100 ns
45 ns
1BO ns
±10%
1
2
3
4
5
6
7
B
9
10
11
12
13
14
15
16
17
1B
19
20
21
22
23
24
25
26
27
2B
29
30
D
D
c±>
Low Power Dissipation
Operating Free-Air Temperature Range
... O°C to 70°C
PIN NOMENCLATURE
AO-A9
CAS
D01-DOB
NC
RAS
VCC
VSS
description
The TM124GU8A is a dynamic random-access
memory module organized as 1 048 576 x 8 in a
30-pin single-in-line package.
The TM124GU8A is composed of two TMS44400,
1 048 576 x 4 bit dynamic RAMs in 20/26-lead
plastic small-outline J-Iead packages (SOJs).
Address Inputs
Column-Address Strobe
Data In/Data Out
No Internal Connect
Row-Address Strobe
5-V Supply
Ground
The TM124GU8A is mounted on a substrate with decoupling capacitors. The onboard capacitors eliminate the
need for bypassing on the motherboard and offer superior performance over equivalent leaded capacitors due
to reduced lead inductance. With the elimination of bypass capacitors on the motherboard, reduced PC board
size, and fewer plated through-holes, a cost savings can be realized.
PRODUCTION DATA documents contain Information
current IS of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necenarlly Includa testing of all parameters.
J!1
INSlRUMENTS
Copyright © 1991, Texas Instruments Incorporated
TEXAS
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6-13
TM124GU8A
1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE
SMMS181 -JANUARY 1991
TheTM124GU8A features RAS access times of60 ns, 70 ns, 80 ns, and 100 ns. All inputs and outputs, including
clocks, are compatible with Series 74 TTL. All address lines and data in are latched on-chip to simplify system
design. Data out is unlatched to allow greater system flexibility.
The TM 124GU8A is characterized for operation from O°C to 70°C.
operation
The TM124GU8A operates as two TMS44400s connected as shown in the functional block diagram. The
common I/O features of the TM124GU8A dictates the use of early write cycles to prevent contention on the DQ
lines.
specifications
Refresh period is extended to 16 milliseconds and, during this period, each of the 1024 rows must be strobed
with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power.
single-In-line package and components
PC substrate: 1,27 mm (0.05 inch) nominal thickness on contact area
Bypass capacitors: Multilayer ceramic
Leads: Tin/lead solder coated over phosphor-bronze
TEXAS . .
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TM124GU8A
1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE
SMMS181-JANUARY 1991
functional block diagram
AO 4
A1
A2
A3
A4
AS
A6
A7
AS
A9
5
7
S
11
12
14
15
17
1S
~
1024Kx1
001
002
003
004
AO-A9
" RAS
CAS
" Vi
27
2
21
JOE
VOO
1024K x 1
005
RAS
006
007
CAS
VOO
VOO
1
30
9
VSS
22
VSS
1
1
-.L
Vi
DaB
DE
VOO
-.L
001
002
003
004
16
20
23
25
005
006
007
VSS
LpQ- AO-A9
I
3
6
10
13
OOS
VSS
I
TC"'CT
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) .......................................... - 1 V to 7 V
Voltage range on Vee ................................ '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 2 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ...................................................... - 55°C to 125°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device atthese or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied, Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability,
NOTE 1: All voltage values are with respect to VSS.
TEXAS "J1
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6-15
TM124GU8A
1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE
SMMS181 -
JANUARY 1991
recommended operating conditions
VCC
Supply voltage (TM124GUSA-6)
VCC
Supply voltage (TM124GUSA-70/-S0/-1 0)
MIN
NOM
MAX
4.75
5
5.25
UNIT
V
4.5
5
5.5
V
V
VIH
High-level input voltage
2.4
6.5
VIL
Low-level input voltage (see Note 2)
-1
O.S
V
TA
Operating free-air temperature
0
70
°c
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
I
TM124GUSA-6
PARAMETER
TEST CONDITIONS
TM124GUSA-70
MAX
MIN
MIN
MAX
TM124GU8A-80
MIN
MAX
TM124GUSA-10
MIN
MAX
UNIT
VOH
High-level
output voltage
10H =-5 rnA
VOL
Low-level
output voltage
10L = 4.2 rnA
0.4
0.4
0.4
0.4
V
II
Input current
(leakage)
VI = 0 to 6.5 V, VCC = 5 V,
All other pins = 0 V to VCC
±10
±10
±10
±10
flA
10
Output current
(leakage)
Vo = OtoVCC,
VCC = 5.5 V, CAS high
±10
±10
±10
±10
flA
ICC1
Read or write
cycle current
(see Note 3)
Minimum cycle, VCC = 5.5 V
190
170
150
130
mA
4
4
4
4
mA
2
2
2
2
mA
190
170
150
130
mA
140
120
100
SO
mA
2.4
2.4
After 1 memory cycle,
RAS and CAS high,
ICC2
Standby
Current
2.4
2.4
V
VIH = 2.4 V (TTL)
After 1 memory cycle,
RAS and CAS high,
VIH = VCC - 0.2 V (CMOS)
ICC3
Average
refresh current
(see Note 3)
Average page
ICC4 . current
(see Note 4)
Minimum cycle, VCC = 5.5 V,
RAS cycling, CAS high
~ = minimum, VCC = 5.5 V,
RAS low, CAS cycling
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measrued with a maximum of one address change while CAS = VIH.
TEXAS •
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TM124GU8A
1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE
SMMS181-JANUARY 1991
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz
MIN
PARAMETER
MAX
UNIT
10
Ci(A)
Input capacitance, address inputs
Ci(DQ)
Input capacitance, data inputs/outputs
Ci(RC)
Ci(W)
pF
7
pF
Input capacitance, strobe inputs
14
pF
Input capacitance, W input
14
pF
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'124GU8A-6
PARAMETER
MIN
MAX
'124GU8A-70
'124GU8A-80
MIN
MIN
MAX
MAX
'124GU8A-10
MIN
MAX
UNIT
tAA
Access time from column-address
30
35
40
45
ns
tCAC
Access time from CAS low
15
18
20
25
ns
ns
tCPA
Access time from column precharge
35
40
45
50
tRAC
Access time from RAS low
60
70
80
100
tCLZ
CAS to output in low Z
0
tOFF
Output disable time after CAS high
(see Note 5)
0
0
15
0
0
18
0
20
0
ns
ns
0
25
ns
NOTE 5: tOFF is specified when the otuput is no longer driven.
TEXAS •
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POST OFFICE BOX 1443
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6-17
TM124GU8A
1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE
SMMS181-JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
'124GU8A-6
MAX
MIN
'124GU8A-70
MIN
MAX
'124GU8A-80
MIN
MAX
'124GU8A-10
MIN
MAX
UNIT
tRC
Random read or write cycle (see Note6)
110
130
150
180
ns
tpc
Page-mode read or write c;:ycle time
(see Note 7)
40
45
50
55
ns
tAASP
Page-mode pulse duration, RAS low
60
100000
70
100000
80
100000
100
100000
ns
tRAS
Non-page-mode pulse duration, RAS low
60
10000
70
10000
80
10000
100
10 000
ns
tCAS
Pulse duration, CAS low
15
10000
18
10000
20
10000
25
10 000
tcp
Pulse duration, CAS high
10
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
70
ns
twp
Write pulse duration
15
15
15
20
ns
tASC
Column-address setup time before CAS low
0
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
0
ns
tDS
Data setup time
0
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
0
ns
tCWL
W-Iow setup time before CAS high
15
18
20
25
ns
tRWL
W-Iow setup time before RAS high
15
18
20
25
ns
twcs
W-Iow setup time before CAS low
0
0
0
0
ns
tWSR
W-high setup time (CAS-before-RAS
refresh only)
10
10
10
10
ns
tWTS
W-Iow setup time (test mode only)
10
10
10
10
ns
tCAH
Column-address hold time after CAS low
10
15
15
20
ns
tDHR
Data hold time after RAS low (see Note 8)
50
55
60
75
ns
tDH
Data hold time
10
15
15
20
ns
tAR
Column-address hold time after RAS low
(see Note 8)
50
55
60
75
ns
tRAH
Row-address hold time after RAS low
10
10
10
15
ns
tRcH
Read hold time after CAS high (see Note 9)
0
0
0
0
ns
ns
tRRH
Read hold time after RAS high (see Note 9)
0
0
0
0
ns
tWCH
Write hold time after CAS low
15
15
15
20
ns
tWCR
Write hold time after RAS low (see Note 9)
50
55
60
75
ns
tWHR
W-high hold time (CAS-before-RAS
refresh only)
10
10
10
10
ns
tWTH
W-Iow hold time (test mode only)
10
10
10
10
ns
Continued next page.
NOTES: 6. All cycle times assume tT = 5 ns.
7. To guarantee tpc min, tASC should be greater than or equal to tcp.
8. The minimum value is measured when tRCD is set to tRCD min as a reference.
9. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS •
INSlRUMENTS
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POST OFFICE BOX 1443
•
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TM124GU8A
1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE
SMMS181-JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
'124GUBA·6
MIN
MAX
'124GUBA·70
MIN
MAX
'124GUBA·80
MIN
MAX
'124GU8A·10
MIN
MAX
UNIT
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
tCRP
Delay time, CAS high to RAS low
0
0
tCSH
Delay time, RAS low to CAS high
60
70
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
tRAD
Delay time, RAS low to column-address
(see Note 10)
15
tRAl
Delay time, column-address to RAS high
30
35
40
45
tCAl
Delay time, column-address to CAS high
30
35
40
45
tRCD
Delay time, RAS low to CAS low
(see Note 10)
20
tRPC
Delay time, RAS high to CAS low
0
0
0
0
tRSH
Delay time, CAS low to RAS high
15
18
20
25
ns
tTAA
Access time from address (test mode)
35
40
45
50
ns
tTCPA
Access time from column precharge
(test mode)
40
45
50
55
ns
'TRAC
Access time from RAS (test mode)
65
tREF
Refresh time interval
tT
Transition time
15
15
30
45
20
15
35
20
52
75
50
ns
0
·0
ns
80
100
ns
10
ns
40
15
20
60
85
16
2
20
50
25
50
16
2
50
2
ns
ns
ns
75
ns
ns
105
.16
2
20
ns
16
ms
50
ns
NOTE 10: The maximum value is specified only to guarantee access time.
device symbolization
The specifications contained in this data sheet are applicable to all TM124GU8As symbolized as shown in
Figure 1. Please note that the location of the part number may vary.
~.
I
TM124GU8A-xx- REV B
~
91
0000000000000000000000 0000000
01
.
Figure 1. Device Symbolization
TEXAS
J.f
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
6-19
TM124GU8A
1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE
SMMS181 -JANUARY 1991
TEXAS ~
INSTRUMENTS
6-20
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TM256BBK32 262 144 BY 32-BIT DYNAMIC RAM MODULE
TM512CBK32 524 288 BY 32-BIT DYNAMIC RAM MODULE
SMMS232 -
This Data Sheet is Applicable to All
TM256BBK32s and TM512CBK32s
Symbolized with Revision "B" and
Subsequent Revisions as Described
on Page 6-30.
•
•
•
TM256BBK32 ... 262 144 x 32 Organization
•
•
•
•
TM512CBK32 ... 524 288 x 32 Organization
3-State Output
Common CAS Control for Eight Common
Data-In and Data-Out Lines, in Four Blocks
•
TM256BBK32 ..• Utilizes Eight 1-Megabit
Dynamic RAMs in Plastic Small-Outline
J-Lead Packages (SOJs)
•
TM512CBK32 ... Utilizes Sixteen 1-Megabit
Dynamic RAMs in Plastic Small-Outline
J-Lead Packages (SOJs)
Performance Ranges:
ACCESS ACCESS
TIME
TIME
ta(R)
ta(C)
(tRAC)
(tCAC)
(MAX)
(MAX)
'256BBK32-6
60 ns
15 ns
70 ns
'256BBK32-70
18 ns
'256BBK32-80
80 ns
20 ns
'256BBK32-10
100 ns
25 ns
60 ns
'512CBK32-6
15 ns
'512CBK32-70
70 ns
18 ns
'512CBK32-80
80 ns
20 ns
'512CBK32-10
100 ns
25 ns
•
Distributed Refresh Period ..• 8 ms
(512 Cycles)
•
•
•
All Inputs, Outputs, Clocks Fully TTL
Compatible
Single 5-V Power Supply
72-pin Single-In-Line Package (SIP)
- Leadless Module for Use with Sockets
JANUARY 1991
READ
vCC
OR TOLERANCE
WRITE
CYCLE
(MIN)
5%
110 ns
130 ns
10%
150 ns
10%
180 ns
10%
110 ns
5%
130 ns
10%
150 ns
10%
180 ns
10%
Low Power Dissipation
Operating Free-Air Temperature
Range ... O°C to 70°C
description
TM256BBK32
The TM256BBK32 is a 8388K dynamic random-access memory module organized as four times
262 144 x 8 in a 72-pin single-in-line package (SIP).
The SIP is composed of eight TMS44C256DJ, 262 144 x 4-bit dynamic RAMs, each in a 20/26-lead plastic
small-outline J-Iead package (SOJs), mounted on a substrate together with decoupling capacitors. Each
TMS44C256DJ is described in the TMS44C256 data sheet.
The TM256BBK32 SIP is available in the single-sided BK leadless module for use with sockets.
The TM256BBK32 SIP features RAS access times of 60 ns, 70 ns, 80 ns, and 100 ns. This device is
characterized for operation from ODC to 70°C.
TM512CBK32
The TM512CBK32 is a 16777K dynamic random-access memory, module organized as four times
524288 x 8 in a 72-pin single-in-line package (SIP).
The SIP is composed of sixteen TMS44C256DJ, 262 144 x 4-bit dynamic RAMs, each in a 20/26-lead plastic
small-outline J-Iead package (SOJs), mounted on a substrate with decoupling capacitors. Each TMS44C256DJ
is described in the TMS44C256 data sheet.
The TM512CBK32 SIP is available in a double-sided BK lead less module for use with sockets.
The TM512CBK32 SIP features RAS access times of 60 ns, 70 ns, 80 ns, and 100 ns. This device is rated for
operation from O°C to 70°C.
PRODUCTION DATA documents contain Information
current II of publication date. Products conform to
specifications per the terms of Tuas Instruments
~~lcne~~r:'I~~~:I~~~ rer~1nu:~~~nP~~~:~~lt~~I~oes
not
TEXAS ~
Copyright © 1991, Texas Instruments Incorporated
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
6-21
TM256BBK32 262144 BY 32-BIT DYNAMIC RAM MODULE
TM512CBK32 524 288 BY 32-81T DYNAMIC RAM MODULE
SMMS232 -
JANUARY 1991
operation
TM256BBK32
The TM256BBK32 operates as eight TMS44C256DJs connected as shown in the functional block diagram.
Refer to the TMS44C256 data sheet for details of operation.
The common I/O feature of the TM256BBK32 dictates the use of early write cycles to prevent contention on
D and O.
TM512CBK32
The TM512CBK32 operates as sixteen TMS44C256DJs connected as shown in the functional block diagram.
Refer to the TMS44C256 data sheets for details of operation.
The common I/O feature of the TM512CBK32 dictates the use of early write cycles to prevent contention on
D and O.
specifications
Refresh period is extended to 8 milliseconds and, during this period, each of the 512 rows must be strobed with
RAS in order to retain data. Address line A8 must be used as most significant refresh address line (lowest
frequency) to assure correct refresh for the TMS44C256. CAS can remain high during the refresh sequence to
conserve power.
single-in-line package and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness on contact area
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: Nickel plate and gold plate on top of copper
TEXAS •
INSTRUMENTS
6-22
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TM256BBK32 262 144 BY 32·BIT DYNAMIC RAM MODULE
TM512CBK32 524 288 BY 32·81T DYNAMIC RAM MODULE
SMMS232 -
BK Singie-in-llne Package t
(Top View)
JANUARY 1991
TM512CBK32t
(Side View)
TM256BBK32t
(Side View)
0
vss
000
0016
001
0017
002
0018
003
0019
vCC
NC
AO
Al
A2
A3
A4
A5
A6
NC
004
0020
005
0021
006
0022
OQ7
0023
A7
NC
VCC
AS
NC
RAS3
RAS2
NC
NC
C) 1
C) 2
C) 3
B~6
C)
C)
C)
C)
c::J
C)
C)
C)
c::J
c::J
C)
c::J
C)
c::J
C)
C)
C)
c::J
C)
C)
C)
c::J
C)
C)
C)
C)
C)
C)
C)
C)
C)
C)
C)
C)
C)
C)
~ C)
CASl C )
RASO c::J
RASl C )
NC C )
W C)
NC C )
008 C )
0024 C )
009 C )
0025 c::J
0010 C )
0026 c::J
0011 C )
0027 C )
0012 C )
0028 C )
vcc C )
0029 C )
0013 C )
0030 C )
0014 C )
0031 c::J
0015 C )
NC C )
NC C )
NC C )
NC
NC
NC C )
VSS C )
NC
NC
VSS
CASO
CAS2
B
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
CJ
CJ
CJ
CJ
CJ
CJ
CJ
CJ
PIN NOMENCLATURE
AO-A8
Address Inputs
CASO-CAS3
Column-Address Strobe
000-0031
Data In/Data Out
NC
No Connection
RASO-RAS3
Row-Address Strobe
VCC
5-V Supply
VSS
Ground
Vii
Write Enable
0
t The packages shown here are for pinout reference only and are not drawn to scale. Parts locations may vary.
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
6-23
en
functional block diagram (for TM256BBK32)
0>
N
~
A012
A1 13
A214
A315
A416
AS 17
A618
------..
en
------..
I
f\)
w
f\)
------..
:'i>
z
c
------..
------..
------..
------..
A728
------..
A831
------..
CAS342
CAS241
CAS143
RAS234
RAS044
CAS040
Vi 47
VSS
:>
:0
-<
~
~4r
~~
WW
1\)1\)
en
I\)
1\)0)
~I\)
mOl
-<-<
..
mOl
=i=i
-
cc
~
4~
~t;:
r-....
:----
44C256
AO·AB
RAS
CAS
9
.
~
L..r:::"
--..I:::::,
G
OQ1·
OQ4
--..r:::",
Vi
-----.i:::::,
OQ20 21
OQ2123
OQ2225
nO?:l?7
l>l>
:::c :::c
' -
9~
~RAS
----b,
Vi
&AS
G
OQ1·
OQ4 ~
OQ1·
OQ4
' -
' -
OQ1257
OQ1361
OQ1463
OQ2858
OQ2960
OQ30 62
n01~ fi~
OO:l1 fi4
:s::s:
:s::s:
00
cc
c: c:
r- rmm
~ AO·A8
AO·AB
RAS
CAS
G
'-
Vi
OQ2450
OQ2552
OQ2654
OQ2756
-±
AO·A8
RAS
CAS
00
OQ1·
OQ4 ~
9~
"'44C256
OQ1·
OQ4 ~
~
r-....
'----
G
' -
... ~
~
OQ849
OQ951
OQ1053
OQ11 55
9~
~RAS
r-.... ~AS
W
4~
l>l>
:S::S:
44C256
Ao-A8
RAS
CAS
G
OQ1·
OQ4
'----
OQ163
OQ175
OQ187
OQ199
~ AO·A8
9
G
OQ1·
OQ4 ~
~
t?;:
~
G
OQ1·
OQ4
-<-<
zz
:----
44C256
AO·A8
~ RAS
~
CAS
r-.... Vi
~
Vi
-
:----
44C256
AO·A8
4.-lli RAS
L-.t:::,
4)CAS
r-.... Vi
G
OQ420
OQ522
OQ624
OQ726
1\)0)
om
mOl
ww
1\)1\)
:----
OQ02
OQ14
OQ26
OQ38
-1-1
:S::S:
en I\)
...... en
1\) ......
CO~
CO~
z
Ii
~
~
...
functional block diagram (TM512CBK32)
AO 12
Al13
A214
A315
A416
AS 17
A618
A728
A831
"U
-n_
0
en
--i
I
~
------~
~
~
~
---------
CAS342
RAS333
CAS241
RAS234
CASl43
RAS145
RAS044
CAS040
Vi 47
VSS
0
~Z
9
~
~~~
I-r:::
I-r:::
6~
~ (jj.ct I
001004
~l'!'1
en
.---
'C256
AO-A8
RAS
CAS
/.-.to
/.-.to
'C256
AO-A8
RAS
CAS
l-
Vi
G
~
~Vi
l-G
~c:
§Z
.---
/-b
I.....-
0002
0014
0026
0038
PIi::
AO-AB
RAS
......-
...---
'C256
AO-AB
RAS
CAS
r---
'C256
AO-A8
RAS
CAS
r---
~
!i:::
/.-.to
'C256
AO-A8
RAS
CAS
'C256
AO-AS
RAS
CAS
'C256
AO-AB
RAS
CAS
l-
Vi
G
.--~
Lr:,
~~r
~
-l----
~
Lt::
oo~~~
00849
i.-.--
Vi
G
001004
I-:--
f-
~
'C256
AO-AB
~
001004
L.....-
001257
001361
001463
001565
I.--
~
~
G
CAS
f-
~~~
I.....-
'C256
AO-AB
RAS
CAS
L-..J::" Vi
l---- G
Vi
'---G
001004 ~
I002021
002123
002225
002327
~
/-b
l-
P-
~
~Vi
Vi
G
001004
S:S:
U1 I\,)
...... U1
I\,)
ww
~'"
I\,) I\,)
I-G
~~
~
I002450
...---
~
Lt::
U1 I\,)
L..b
?-
c=;
I---t:: Vi
~
~
Oo~~rl
DOl004
L.....-
l----
I-
N
I\,)
mOl
=i=i
co
G
001-~
004
-<-<
ZZ
I.....-
l>l>
(J)
~
~
(J)
c.>
I\)
I
<»
z
c
»
:D
N
()'I
.:::a.
ww
I\)
0>
(X)
-<-<
'C256
AO-AS
RAS
CAS
00285S
002960
003062
003164
en
mOl
L.....c:: Vi
L-..J::" Vi
'--G
'--G
L--
'C256
AO-A8
RAS
CAS
I\,)
+:10 I\,)
N ......
(X) +:10
r---
r--
'C256
AO-A8
RAS
CAS
en
om
mOl
002552
002654
002756
..--
'C256
AO-AS
~
oo~~~
I-
00163
L...r:::, RAS
L-..J::" Vi
L--G
~~~~
L.....-
/-b
i.-.--
r---
L...r:::, RAS
LJ::, CAS
L..b
L-..J::" Vi
L--G
DOl004
00175
001S7
00199
.---
'C256
AO-AS
RAS
CAS
Lr:: Vi
l- G
f-G
001004 ~
I.--
...---
'C256
AO-AS
RAS
CAS
~
~
Lr::
~
~Vi
I-G
-1-1
r---
00951
001053
001155
....
00420
00522
00624
00726
~
~~~
~
l.....-
~
r-~ 'C256
-<
iO
~
S:S:
00
:c:c
l>l>
S:S:
S:S:
00
CO
c: c:
r- r-
mm
TM256BBK32 262 144 BY 32·BIT DYNAMIC RAM MODULE
TM512CBK32 524 288 BY 32·BIT DYNAMIC RAM MODULE
SMMS232-JANUARY 1991
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ............................................... :. - 1 V to 7 V
Voltage range on Vee (see Note 1) ................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 8 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ...................................................... - 55°C to 125°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
UNIT
4.75
5
. 5.25
V
Supply voltage (TM256BBK32-70/-80/-10 and TM512CBK32-70/-80/-10)
4.5
5
5.5
V
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
°c
VCC
Supply voltage (TM256BBK32-6 and TM512CBK32-6)
VCC
VIH
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
.
PARAMETER
TEST CONDITIONS
'256BBK32-6
MIN
MAX
'256BBK32-70
'256BBK32-80
'256BBK32-10
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
VOH
High-level output
voltage
IOH =-5mA
VOL
Low-level output
voltage
IOL = 4.2 mA
0.4
0.4
0.4
0.4
V
II
Input current
(leakage)
VI = 0 to 6.5 V,
VCC = 5.5 V, All other
pins = 0 to VCC
±10
±10
±10
±10
!!A
10
Output current
(leakage)
Vo = OtoVCC,
VCC = 5.5 V, CAS high
'±10
±10
±10
±10
!!A
ICC1
Read or write cycle
current (see Note 3)
Minimum cycle,
VCC = 5.5V
760
640
600
520
mA
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V (TTL)
16
16
16
16
mA
After 1 memory cycle,
RAS and CAS high,
VIH = VCC-O.2 V
(CMOS)
8
8
8
8
mA
720
640
560
480
mA
560
480
400
360
mA
ICC2
Standby current
ICC3
Average refresh
current (RAS-only or
CBR) (see Note 3)
ICC4
Average page
current (see Note 4)
2.4
2.4
Minimum cycle,
VCC = 5.5 V, RAS
cycling, CAS high
(RAS-only), RAS low
. after CAS low (CSR)
tc(P) = minimum,
VCC = 5.5 V,
RAS low, CAS cycling
2.4
NOTES: 3. Measured With a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS •
INSlRUMENTS
6-26
POST OFFICE BOX 1443
~
HOUSTON, TEXAS 77001
2.4
V
TM256BBK32 262 144 BY 32·BIT DYNAMIC RAM MODULE
TM512CBK32 524 288 BY 32·BIT DYNAMIC RAM MODULE
SMMS232 - JANUARY 1991
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
'512CBK32·6
PARAMETER
TEST CONDITIONS
MAX
MIN
'512CBK32·70
MIN
MAX
'512CBK32·80
'512CBK32·10
MIN
MIN
MAX
MAX
UNIT
VOH
High-level output
voltage
VOL
Low-level output
voltage
10L = 4.2 mA
0.4
0.4
0.4
0.4
V
II
Input current
(leakage)
VI =0 to 6.5 V,
VCC =5.5 V, All other
pins = 0 to VCC
±10
±10
±10
±10
f1A
10
Output current
(leakage)
Vo = OtoVCC,
VCC = 5.5 V, CAS high
±10
±10
±10
±10
f1A
ICCl
Aead or write
cycle current
(see Note 3)
Minimum cycle,
VCC =5.5V
776
656
616
536
mA
32
32
32
32
rnA
Standby current
After 1 memory cycle,
AAS and CAS high,
VIH = 2.4 V (TIL)
After 1 memory cycle,
AAS and CAS high,
VIH = VCC - 0.2 V
(CMOS)
16
16
16
16
rnA
ICC2
2.4
2.4
2.4
2.4
10H =-5mA
V
ICC3
Average refresh
current (AAS-only
or CSA)
(see Note 3)
Minimum cycle,
VCC = 5.5 V, AAS
cycling, CAS high,
(AAS-only), AAS low after
CAS low (CSA)
736
656
576
496
mA
ICC4
Average page
current
(see Note 4)
tc(P) =minimum,
VCC = 5.5 V,
RAS low, CAS cycling
576
496
416
376
rnA
-
NOTES: 3. Measured with a maximum of one address change while AAS =VIL.
4 Measured with a maximum of one address change while CAS == VIH.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz
.
TM256BBK32
PARAMETER
MIN
TM512CBK32
MAX
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
40
80
pF
Ci(C)
Input capacitance, CAS input
10
20
pF
Ci(A)
Input capacitance, AAS input
20
20
pF
Ci(W)
Input capacitance, write-enable input
40
80
pF
Co(DO)
Output capacitance on DO pins
7
14
pF
NOTE 5: VCC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
6-27
TM256BBK32 262 144 BY 32·BIT DYNAMIC RAM MODULE
TM512CBK32 524288 BY 32·BIT DYNAMIC RAM MODULE
SMMS232 -
JANUARY 1991
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
ALT.
SYMBOL
'256BBK32-6
'512CBK32-6
'256BBK32-70
'512CBK32-70
MIN
MAX
MIN
MAX
'256BBK32-80
'512CBK32-80
MIN
MAX
i256BBK32-10
'512CBK32-10
MIN
UNIT
MAX
ta(C)
Access time from CAS
tCAC
15
18
20
25
ns
ta(CA)
Access time from columnaddress
tCAA
30
35
40
45
ns
ta(R)
Access time from RAS
tRAC
60
70
80
100
ns
ta(CP)
Access time from column
precharge
tCAP
35
40
40
50
ns
td(CLZ)
CAS to output in low Z
tCLZ
0
tdis(CH)
2.!:!!eut disable time after
CAS high (see Note 6)
tOFF
0
0
15
0
0
18
0
ns
0
20
0
25
ns
NOTE 6: tOFF is specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
ALT.
SYMBOL
'256BBK32-6
'512CBK32-6
'256BBK32-70
'512CBK32-70
'256BBK32-80
'512CBK32-80
'256BBK32-10
'512CBK32-10
MIN
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
MAX
tc(rd)
Read cycle time
(see Note 7)
tRC
110
130
150
180
ns
tc{\fll)
Write cycle time
twc
110
130
150
180
ns
tc(P)
Page-mode read or write
cycle time
tpc
40
45
50
55
ns
tw(CH)
Pulse duration, CAS high
tcp
10
tw(CL)
Pulse duration, CAS low
tCAS
15
tw(RH)
Pulse duration, RAS high
(precharge)
tRP
40
tw(RL)
Non-page-mode pulse
duration, RAS low
tRAS
60
10000
70
10000
80
10000
100
10000
ns
tw(RL)P
duration, RAS low
tRASP
60
100000
70
100000
80
100000
100
100000
ns
tw(WL)
Write pulse duration
twp
15
15
15
15
ns
tsu(CA)
Column-address setup
time before CAS low
tASC
0
0
0
0
ns
tsu(RA)
Row-address setup time
before RAS low
tASR
0
0
0
0
ns
tsu(O)
Oata setup time before
CAS low
tos
0
0
0
0
ns
tsu(rd)
Read setup time before
CAS low
tRCS
0
0
0
0
ns
tsu(WCL)
W-Iow setup time before
CAS low
twcs
0
0
0
0
ns
tsu(WCH)
W-Iow setup time before
CAS high
tCWL
15
18
20
25
ns
tsu(WRH)
W-command setup time
before RAS high
tRWL
15
18
20
25
ns
Page-mo~lse
10
10000
18
10
10000
TEXAS ~
INSlRUMENTS
POST OFFICE BOX 1443
•
10
10000
60
50
NOTE 7: All cycle times assume tt = 5 ns.
6-28
20
HOUSTON, TEXAS 77001
25
ns
10000
70
ns
ns
TM256BBK32 262 144 BY 32-B11 DYNAMIC RAM MODULE
1M512CBK32 524 288 BY 32-B11 DYNAMIC RAM MODULE
SMMS232 - JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
PARAMETER
ALT.
SYMBOL
'2S6BBK32-6
'S12CBK32-6
'2S6BBK32-70
'S12CBK32-70
'2S6BBK32-80
'S12CBK32-80
'2S6BBK32-10
'S12CBK32-10
MIN
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
MAX
th(CA)
Column-address hold time
after CAS low
tCAH
10
15
15
20
ns
th(RA)
Row-address hold time after
RAS low
tRAH
10
10
12
15
ns
th(RLCA)
Column-address hold time
after RAS low (see Note 8)
tAR
50
55
60
70
ns
th(RLD)
Data hold time after RAS
low (see Note 8)
tDHR
50
55
60
70
ns
th(D)
Data hold time after CAS
low
tDH
10
15
15
20
ns
th(CHrd)
Read hold time after CAS
high (see Note 9)
tRCH
0
0
0
0
ns
th(RHrd)
Read hold time after RAS
high (see Note 9)
tRRH
0
0
0
0
ns
th(CLW)
Write hold time after CAS
low
twCH
15
15
15
20
ns
th(RLW)
Write hold time after RAS
low
tWCR
50
55
60
70
ns
td(RLCH)
Delay time, RAS low to
CAS high
tCSH
60
70
80
100
ns
td(CHRL)
Delay time, CAS high to
RAS low
tCRP
0
0
0
0
ns
Id(CLRH)
Delay time, CAS low to
RAS high
IRSH
15
18
20
25
ns
Id(RLCL)
Delay lime RAS low 10 CAS
low (see Nole 10)
tRCD
20
45
20
52
22
60
25
75
ns
td(RLCA)
Delay time, RAS low to
column-address
tRAD
15
30
15
35
17 .
40
20
55
ns
Id(CARH)
column-address
10 RAS high
IRAL
30
35
40
45
ns
Id(CACH)
De~ime, column-address
to CAS high
tCAL
30
35
40
45
ns
td(RLCH)R
Delay time, RAS low to
CAS high (see Nole 11)
tCHR
15
15
20
25
ns
td(CLRL)R
Delay time, CAS low to
RAS low (see Nole 11)
ICSR
10
10
10
10
ns
td(RHCL)R
Delay time, RAS high to
CAS low (see Nole 11)
tRPC
0
0
0
0
ns
trf
Distribution refresh time
interval
tREF
tl
NOTES: 8.
9.
10.
11.
De~ime,
Transition lime
tT
8
3
50
8
3
50
8
3
50
3
8
ms
50
ns
The minimum value is measured when td(RLCL) is sel to td(RLCL) min as a reference.
Either Ih(RHrd) or th(CHrd) must be satisfied for the read cycle.
Maximum value specified only 10 guarantee access time.
CAS-before-RAS refresh only.
TEXAS •
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6-29
TM256BBK32 262144 BY 32·BIT DYNAMIC RAM MODULE
TM512CBK32 524 288 BY 32·BIT DYNAMIC RAM MODULE
SMMS232 -
JANUARY 1991
device symbolization
The specifications contained in the data sheet are applicable to all TM256BBK32s and TM512CBKs symbolized
as shown in Figure 1. Please note that the location of the part number may vary.
o
DDDDDDDD
Figure 1. Device Symbolization
TEXAS •
INSTRUMENTS
6-30
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
o
TM024EAD9
1 048 576 BY 9-BIT
DYNAMIC RAM MODULE
SMMS109A- MARCH 1990- REVISED NOVEMBER 1990
This
Data
Sheet
is
Applicable
to
With
All
TM024EAD9s
Manufactured
TMS4C1024s Symbolized With Revision "0"
and Subsequent Revisions.
•
TM024EAD9 ... 1 048 576
•
•
Single 5-V Supply (10% Tolerance)
•
•
x
o
9 Organization
30-pin Single-In-Llne Package (SIP)
- Leadless Module for Use with Sockets
Utilizes Nine 1-Megablt Dynamic RAMs in
Plastic Small-Outline J-Lead (SOJ)
Packages
Long Refresh Period ... 8 ms
(512 Cycles)
•
All Inputs, Outputs, Clocks Fully TTL
Compatible
•
3-State Output
•
AD Single-in-Line Package
(Top View)
VCC
1
CAS
D01
AO
3
A1
5
6
A2
A3
7
VSS
8
9
003
10
A4
11
AS
D04
12
13
14
15
16
17
18
19
20
DOS
A8
A9
ACCESS
TIME
tRAC
NC
READ
VCC
OR TOLERANCE
D06
tCAC
WRITE
CYCLE
VSS
(MAX)
(MAX)
60 ns
15 ns
(MIN)
110 ns
5%
TMS4Cl024-70 70 ns
TMS4Cl024-80 80 ns
TMS4Cl024-10 100 ns
18 ns
20 ns
25 ns
130 ns
150 ns
180 ns
10%
10%
10%
TMS4Cl024-6
ACCESS
TIME
VIi
NC
21
22
23
24
D08
09
RAS
CAS9
09
25
26
27
28
29
VCC
30
DO?
•
Common CAS Control for Eight Common
Data-In and Data-Out Lines
•
Separate CAS Control for One Separate
Pair of Data-In and Data-Out Lines
•
•
Low Power Dissipation
o
PIN NOMENCLATURE
AO-A9
CAS, CAS9
DOl-DOS
D9
NC
09
RAS
VCC
VSS
Operating Free Air Temperature
... O°C to 70°C
description
The TM024EA09 is a 9216K (dynamic) randomaccess memory module,
organized as
1 048 576 x 9 bits [bit nine (09, 09) is generally
used for parity and is controlled by CAS9] in a
30-pin single-in-line (SIP) Package.
PRODUCTION DATA documents contain Information current
IS of publication date. Products conform to specifications
per the terms of Texas Instruments standard warranty.
Production processing does not necessarily Include testing
of.llparameters.
4
D02
A6
A?
Performance of Unmounted RAMs:
2
W
Address Inputs
Column-Address Strobe
Data In/Data Out
Data In
No Internal Connection
Data Out
Row-Address Strobe
5-V Supply
Ground
Write Enable
Copyright © 1990, Texas Instruments ,Incorporated
TEXAS •
INSTRUMENTS
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•
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6-31
TM024EAD9
1 048 576 BY 9-81T
DYNAMIC RAM MODULE
SMMS109A- MARCH 1990- REVISED NOVEMBER 1990
The TM024EAD9 is composed of nine TMS4C1 024DJ, 1 048 576 x 1-bit dynamic RAMs, each in 20/26-lead
plastic small-outline J-Iead package (SOJ), mounted on a substrate together with decoupling capacitors.
The TMS4C1024DJ is described in the TMS4C1024 data sheet and is fully electrically
tested and processed according to TI MIL-STD-883B flows (as am mended for commercial applications) prior
to assembly. After assembly onto the SIP, a further set of electrical tests is performed.
The TM024EAD9 SIP is available in the AD single-sided, leadless module for use wit~ sockets.
The TM024EAD9 SIP is rated for operation from O°C to 70°C.
operation
The TM024EAD9 operates as nine TMS4C1024DJs shown in the functional block diagram. Refer to the
TMS4C1024 data sheet for details of its operation. The common I/O feature of the TM024EAD9 dictates the
use of early write cycles to prevent contention on D and Q.
specifications
For TMS4C1 024DJ electrical specifications, refer to the TMS4C1 024 data sheet.
singie-in-line package and components
PC substrate: 1,27 (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: Nickel plate and solder plate (or coat) on top of copper
TEXAS •
INSlRUMENTS
6·32
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TM024EAD9
1 048 576 BY 9-BIT
DYNAMIC RAM MODULE
SMMS1 09A -
MARCH 1990 -
REVISED NOVEMBER 1990
functional block diagram
AO 4
5
A1
7
A2
8
A3
A4
A5
A6
A7
A8
A9
11
12
14
15
17
18
27'
2
21
"
"
"
4~ AO-A9
RAS
CAS
4 ~
D01
3
1
....r--1::::,
-
002
6
T
W
D
AO-A9
RAS
CAS
W
D
10
~
T
+
L.....t:::,.
'---
004
W
D
DOS
OJ
-
D06
T
Vcc VSS
D07
Oil
23
T
..
Vss
T
Vss 221
9
-1-
C
"'
C
W
D
,-
°l
D08
25
..
T
29
09 26
09
..
T.
--1-
on
1024K x 1
Vce Vss
O~
1024K x 1
CAS
W
D
Vcc VSS
~ AO-A9
28
_
CAS9
~
AO-A9
RAS
CAS
i-D- RAS
1024K x 1
-r-
Vcc
Vcc
Vec Vss
~ AO-A9
L...t:::,
1
W
D
~i-D- RAS
1024K x 1
Vcc VSS
T
20
t---
AO-A9
RAS
CAS
-- D
T
--1::::,
Oil
1024K x 1
CAS
....r-
W
13
-
16
1024K x 1
Vee Vss
~ AO-A9
LJ::" RAS
I
VCC VSS
~~ RAS
r - CAS
003
4~ AO-A9
1024K x 1
°l
1024Kx1
CAS
W
0
Vcc VSS
AO-A9
RAS
CAS
W
0
O~
1024K x 1
Vcc VSS
on
I
TEXAS •
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•
HOUSTON, TEXAS 77001
6·33
TM024EAD9
1 048 576 BY 9·BIT
DYNAMIC RAM MODULE
SMMS109A- MARCH 1990- REVISED NOVEMBER 1990
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................ - 1 V to 7 V
Voltage range on Vee (see Note 1) ................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation: ......................................................................... 9 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ...................................................... - 65°C to 150°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
Supply voltage (TM024EAD9-70/-80/-1 0)
4.5
5
5.5
V
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
°c
VCC
Supply voltage (TM024EA09-6)
VCC
NOTE 2:
The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TM024EAD9-6
MIN
MAX
TM024EAD9·70
MIN
MAX
TM024EAD9·80
MIN
MAX
TM024EAD9·10
MIN
UNIT
MAX
VOH
High-level
output voltage
VOL
Low-level
output voltage
IOL,=4.2 mA
0.4
0.4
0.4
0.4
V
II
Input current
(leakage)
VI = 0 to 6.5 V,
VCC = 5V,
All other pins = 0 to VCC
±10
±10
±10
±10
~
10
Output current
(leakage)
Vo = OtoVCC,
VCC = 5.5 V, CAS high
±10
±10
±10
±10
Il A
ICC1
Read or write cycle
current
VCC = 5.5 V
855
720
675
585
mA
18
18
18
18
mA
2.4
IOH =-5 mA
2.4
Minimum cycle,
2.4
V
2.4
ICC2
Standby current
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V
ICC3
Average refresh
current (RAS-only
orCBR)
Minimum cycle,
VCC = 5.5 V, RAS
cycling, CAS high
(RAS-only), RAS low
after CAS low (CBR)
810
720
630
540
mA
ICC4
Average page current
tc(P) = minimum,
VCC = 5.5 V,
RAS low, CAS cycling
630
540
450
405
mA
TEXAS •
INSTRUMENTS
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POST OFFICE BOX 1443
•
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TM024EAD9
1 048 576 BY 9-81T
DYNAMIC RAM MODULE
SMMS109A- MARCH 1990- REVISED NOVEMBER 1990
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
MIN
PARAMETER
MAX
UNIT
45
pF
5
pF
Input capacitance, strobe inputs
45
pF
Ci(W)
Input capacitance, write-enable input
45
pF
Co(OO)
Output capacitance (001-008)
10
pF
Co
Output capacitance (09 only)
7
pF
Ci(A)
Input capacitance, address inputs
Ci(O)
Input capacitance, data input (09 only)
Ci(RC)
NOTE 3: VCC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
TI single-In-line package nomenclature
TM
024
024
Page Mode
E
AD
9
AD Package
(89,15 x 20,49 mm) (max)
(3.51 x 0.807 Inches) (max)
·80
L
Min Access
- 6
-70
60 ns
70 ns
- 80 80 ns
-10 100 ns
TEXAS . .
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6-35
TM024EAD9
1 048 576 BY 9-81T
DYNAMIC RAM MODULE
SMMS109A- MARCH 1990 - REVISED NOVEMBER 1990
TEXAS ~
INSlRUMENTS
6-36
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TM124EAD9B,TM124EAD9C
1 048 576-WORD BY 9-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS191 -
This Data Sheet is Applicable to All
TM124EAD9Bs and TM124EAD9Cs
Symbolized with Revision "B" and Subsequent
Revisions as Described on Page 6-44.
•
•
Single 5-V Power Supply
•
30-Pin Single-In-Line Package (SIP)
•
TM124EAD98 ... Utilizes Two 4-Megabit
and One 1-Megabit Dynamic RAMs in
Plastic Small-Outline J-Lead Packages
(SOJs)
•
TM124EAD9C ... Utilizes Three 4-Megabit
Dynamic RAMs in Plastic Small-Outline
J-Lead Packages (SOJs)
•
Long Refresh Period. .. 16 ms
(1024 Cycles)
•
All Inputs, Outputs, Clocks Fully TTL
Compatible
•
3-State Outputs
•
Performance Ranges:
AD Single-in-Line
Package
(Top View)
1 048576 x 9 Organization
ACCESS ACCESS READ
TIME
TIME
tRAC
tAA
VDD
CAS
001
AD
Al
002
A2
A3
VSS
003
A4
A5
004
A6
A7
005
A8
A9
NC
006
W
VSS
007
NC
008
09
RAS
CAS9
09
VDD
VCC
OR TOLERANCE
WRITE
CYCLE
(MAX)
(MAX)
(MIN)
60 ns
30 ns
110 ns
±5%
'124EAD98/C-70 70 ns
35 ns
130 ns
±10%
'124EAD98/C-80 80 ns
40 ns
150 ns
±10%
'124EAD98/C-l0 100 ns
45 ns
180 ns
±10%
'124EAD98/C-6
•
•
JANUARY 1991
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
D
D
D
0
PIN NOMENCLATURE
AO-A9
CAS, CAS9
D01-D08
09
NC
09
RAS
VDD
VSS
Low Power Dissipation
Operating Free-Air Temperature Range
... O°C to 70°C
description
The TM124EAD9B and TM124EAD9C are
9216K,
dynamic random-access memory
modules organized as 1048 576 x 9 [bit nine is
generally used for parity] in 30-pin single-in-line
packages.
W
Address Inputs
Column-Address Strobe
Data In/Data Out
Data In
No Connect
Data Out
Row-Address Strobe
5-V Supply
Ground
Write Enable
The TM124EAD9B is composed of two TMS44400, 1048576 x 4-bit dynamic RAMs in 20/26-lead plastic
small-outline J-Iead packages (SOJs), and one TMS4C1 024, 1048 576 x 1-bit dynamic RAM in a 20/26-lead
plastic small-outline J-Iead package (SOJ).
PRODUCTION DATA documents contain Information current as
of publication date. Products conform to specifications per the
terms of Texas Instruments standard warranty. Production
processing does not necessarily Include te5ling of all
parameters.
TEXAS
-IJ,J
Copyright © 1991, Texas Instruments Incorporated
INSTRUMEN1S
POST OFFICE BOX 1443
•
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6-37
TM124EAD9B, TM124EAD9C
1 048 576·WORD BY 9·BIT DYNAMIC RANDOM·ACCESS MEMORY MODULES
SMMS191 -
JANUARY 1991
The TM124EAD9C is composed of two TMS44400, 1 04S 576 x 4-bit dynamic RAMs in 20/26-lead plastic
small-outline J-Iead packages (SOJs), and one TMS441 00, 4 194 304 x 1-bit dynamic RAM in a 20/26-lead
plastic, small-outline J-Iead package (SOJ).
The TM 124EAD9B and TM 124EAD9C are both mounted on a substrate together with three 0.2 I-tF decoupling
capacitors. The onboard capacitors eliminate the need for bypassing on the motherboard and offer superior
performance over equivalent leaded capacitors due to reduced lead inductance. With the elimination of bypass
capacitors on the motherboard, reduced PC board size, and fewer plated through-holes, a cost savings can be
realized.
The TM124EAD9B and TM124EAD9C each feature RAS access times of 60 ns, 70 ns, SO ns, and 100 ns.
All inputs and outputs, including clocks, are compatible with Series 74 TTl. All address and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TM124EAD9B and TM124EAD9Gare characterized for operation from O°C to 70°C.
operation
The TM124EAD9B operates as two TMS44400s and one TMS4C1024 connected as shown in the functional
block diagram.
The TM 124EAD9C operates as two TMS44400s and one TMS441 00 connected as shown in the functional block
diagram.
The common I/O features of the TM124EAD9B and TM 124EAD9C dictate the use of early write cycles to prevent
contention on the DQ lines.
specifications
The refresh period is extended to 16 milliseconds and, during this period, each ofthe 1024 rows must be strobed
with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power. For the
TM124EAD9B, the nine least significant row addresses (AO-AS) must be refreshed every S ms as required by
the TMS4C1 024.
single-in-line package and components
PC substrate: 1,27 mm (0.05 inch) nominal thickness on contact area
Bypass capacitors: Multilayer ceramic
Leads: Tin/lead solder coated over phosphor-bronze
TEXAS -I!I
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POST OFFICE BOX 1443
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TM124EAD9B, TM124EAD9C
1 048 576-WORD BY 9-BIT DYNAMIC RANDOM·ACCESS MEMORY MODULES
SMMS191-JANUARY 1991
functional block diagram (TM124EAD9B)
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
4
5
7
8
11
12
14
15
17
18
27
2
21
1024K x 4
DQ1
AO-A9
DQ2
RAS
... CAS
DQ3
DQ4
W
,...-- OE
~...
I
~
VSS
DQ1
DQ2
DQ3
DQ4
16
20
23
25
DQS
DQ6
DQ7
DQ8
I
1024K x 4
~ AO-A9
DQ5
... RAS
DQ6
DQ7
CAS
DQ8
W
OE
1
3
6
10
13
T
1024K x 1
AO-A9
.... RAS
... CAS
~
28
D9
'W
29
Q
26 Q9
D
TEXAS •
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POST OFFICE BOX 1443
•
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6-39
TM124EAD9B,TM124EAD9C
1 048 576-WORD BY 9-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS191-JANUARY 1991
functional block diagram (TM124EA09C)
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
4
5
7
8
11
12
14
15
17
18
27
2
21
1024K x 4
001
AO·A9
~~
RAS
002
" CAS
003
Vi
004
~
r--
001
002
003
004
OE
I
~
3
6
10
13
I
1024K x 4
DOS
i - AO·A9
RAS
006
007
" CAS
Vi
008
16 DOS
20 006
23 007
2S 008
OE
VSS
I
I
4096K x 1
'---
A10
L!9L-
AO·A9
,., RAS
,.., CAS
28
09
"Vi
29
0
0
TEXAS . .
INSTRUMENTS
6-40
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
26 09
TM124EAD9B,TM124EAD9C
1 048 576·WORD BY 9·BIT DYNAMIC RANDOM·ACCESS MEMORY MODULES
SMMS191-JANUARY 1991
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) .......................................... - 1 V to 7 V
Voltage range on Vee ............................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 3 W
Operating free-air temperature range .................................................. ooe to 70 0 e
Storage temperature range ...................................................... - 55°e to 125°e
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
VCC
Supply voltage (TM124EA09B-6 and TM124EA09C-6)
VCC
Supply voltage (TM 124EA09B-70/-80/-1 0 and TM 124EA09C-70/-80/-1 0)
MIN
NOM
MAX
4.75
5
5.75
V
4.5
5
5.5
V
UNIT
VIH
High-level input voltage
2.4
6.5
V
Vll
low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
°c
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
'124EAD9B-6
'124EAD9C-6
MIN
'124EAD9B-70 '124EAD9B-80
'124EAD9C-70 '124EAD9C-80
MAX
MIN
MAX
MIN
MAX
'124EAD9B-10
'124EAD9B-10
MIN
UNIT
MAX
VOH
High-level output
voltage
VOL
low-level output
voltage
IOl = 4.2 mA
0.4
0.4
0.4
0.4
V
II
Input current
(leakage)
VI=O to 6.5 V, VCC = 5.5 V,
All other pins = 0 V to VCC
± 30
± 30
± 30
± 30
flA
10
Output current
(leakage)
Vo = OtoVCC,
VCC = 5.5 V, CAS high
±10
±10
±10
±10
flA
ICC1
Read or write cycle
current (see Note 3)
Minimum cycle, VCC = 5.5 V
285
255
225
195
mA
After 1 memory cycle, RAS
and CAS high, VIH = 2.4 V
(TTl)
6
6
6
6
mA
After 1 memory cycle, RAS
and CAS high,
VIH = VCC - 0.2 V (CMOS)
3
3
3
3
mA
ICC2
Standby current
2.4
IOH =-5 mA
2.4
2.4
V
2.4
ICC3
Average refresh
current (RAS-only
or CBR) (see Note 3)
Minimum cycle, VCC = 5.5 V,
RAS cycling, CAS high
(RAS-only). RAS low after
CAS low (CBR)
285
255
225
195
mA
ICC4
Average page
current (see Note 4)
tpc = minimum, VCC = 5.5 V,
RAS low, CAS cycling
210
180
150
120
mA
NOTES: 3. Measured with a maximum of one address change while RAS = Vll.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS
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6-41
TM124EAD9B, TM124EAD9C
1 048 576·WORD BY 9·BIT DYNAMIC RANDOM·ACCESS MEMORY MODULES
SMMS191 -JANUARY 1991
capacitance over recommended ranges of suppiy voltage and operating free-air temperature,
f =1 MHz (see Note 5)
TM124EAD9B
TM124EAD9C
PARAMETER
UNIT
MAX
MIN
Ci(A)
Input capacitance, address inputs
15
pF
Ci(DO)
Input capacitance, data inputs/outputs
12
pF
Ci(RC)
Input capacitance, strobe inputs
21
pF
Ci(W)
Input capacitance, W input
21
pF
Ci(CAS9)
Input capacitance, CAS9 input
7
pF
Ci(D9)
Input capacitance on 09
5
pF
C olO9)
Output capacitance on 09
7
pF
NOTE 5: VCC equal to 5 V
±
0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
'124EAD9B-6
'124EAD9C-6
'124EAD9B-70
'124EAD9C-70
'124EAD9B-80
'124EAD9C-80
'124EAD9B-1O
'124EAD9C-10
MIN
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
MAX
tAA
Access time from column-address
30
35
40
45
tCAC
Access time from CAS low
15
18
20
25
ns
tCPA
Access time from column precharge
35
40
45
50
ns
tRAC
Access time from RAS low
100
ns
tCLZ
CAS to output in low Z
0
tOFF
Output disable time after CAS high
(see Note 6)
0
70
60
0
15
0
18
NOTE 6: tOFF is specified when the output is no longer driven.
TEXAS ."
INSTRUMENTS
6-42
POST OFFICE BOX 1443
•
80
0
HOUSTON, TEXAS 77001
0
0
20
0
ns
ns
25
ns
TM124EAD9B,1M124EAD9C
1 048 576-WORD BY 9-B11 DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS191-JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
'124EAD9B-6
'124EAD9C-6
'124EAD9B-70
'124EAD9C-70
'124EAD9B-80
'124EAD9C-80
MIN
MIN
MIN
MAX
MAX
130
110
MAX
150
'124EAD9B-10
'124EAD9C-10
MIN
UNIT
MAX
180
ns
tRC
Random read or write cycle (see Note 7)
tpc
Page-mode read or write cycle time
(see Note 8)
40
tRASP
Page-mode pulse duration, RAS low
60
100000
70
100000
80
100000
100
100000
ns
tRAS
Non-page-mode pulse duration, RAS low
60
10000
70
10000
80
10000
100
10 000
ns
tCAS
Pulse duration, CAS low
15
10000
18
10000
20
10000
25
10 000
tcp
Pulse duration, CAS high
10
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
70
ns
twp
Write pulse duration
15
15
15
20
ns
tASC
Column-address setup time before CAS low
0
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
0
ns
tDS
Data setup time
0
0
0
0
ns
ns
45
50
ns
55
ns
tRCS
Read setup time before CAS low
0
0
0
0
tCWL
W-Iow setup time before CAS high
15
18
20
25
ns
tRWL
W-Iow setup time before RAS high
15
18
20
25
ns
twcs
W-Iow setup time before CAS low
tWSR
W-high setup time (CAS-before-RAS
refresh only)
tCAH
Column-address hold time after CAS low
10
15
15
20
ns
tDHR
Data hold time after RAS low (see Note 9)
50
55
60
75
ns .
0
0
0
0
ns
10
10
10
10
ns
tDH
Data hold time
10
15
15
20
ns
tAR
Column-address hold time after RAS low
(see Note 9)
50
55
60
75
ns
tRAH
Row-address hold time after RAS low
10
10
10
15
ns
tRCH
Read hold time after CAS high (see Note 10)
0
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 10)
0
0
0
0
ns
tWCH
Write hold time after CAS low
15
15
15
20
ns
tWCR
Write hold time after RAS low (see Note 10)
50
55
60
75
ns
tWHR
W-high hold time (CAS-before-RAS
refresh only)
10
10
10
10
ns
Continued next page.
NOTES: 7. All cycle times assume IT = 5 ns.
8. To guarantee tpc min, tASC should be greater than or equal to tcp.
9. The minimum value is measured when tRCD is set to tRCD min as a reference.
10. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS . .
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POST OFFICE BOX 1443
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6-43
TM124EAD9B,TM124EAD9C
1 048 576-WORD BY 9-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS191-JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
'124EAD9B-6
'124EAD9C-6
MAX
MIN
'124EAD9B-70
'124EAD9C-70
MIN
MAX
'124EAD9B-80
'124 EAD9C-80
MIN
MAX
'124EAD9B-10
'124EAD9C-10
MIN
UNIT
MAX
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
tCRP
Delay time, CAS high to RAS low
0
0
tCSH
Delay time, RAS low to CAS high
60
70
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
tRAD
Delay time, RAS low to column-address
(see Note 11)
15
tRAl
Delay time, column-address to RAS high
30
35
40
45
ns
tCAl
Delay time, column-address to CAS high
30
35
40
45
ns
tRCD
Delay time, RAS low to CAS low
(see Note 11)
20
tRPC
Delay time, RAS high to CAS low
0
tRSH
Delay time, CAS low to RAS high
15
tREF
Distributed refresh time interval
tT
Transition time
15
15
30
45
15
20
20
35
52
0
50
2
ns
0
0
ns
80
100
ns
10
ns
15
20
60
50
20
25
75
50
2
ns
ns
ns
25
16
2
50
0
20
16
2
40
0
18
16
20
ns
16
ms
50
ns
NOTE 11: The maximum value is specified only to guarantee access time.
device symbolization
The specifications contained in this data sheet are applicable to all TM124EAD9Bs and TM124EAD9Cs
symbolized as shown in Figure 1. Please note that the location of the part number may vary.
o
Figure 1. Device Symbolization
TEXAS .J!1
INSlRUMENlS
6-44
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TM256KBK36B 262 144 BY 36-BIT DYNAMIC RAM MODULE
TM512LBK36B 524288 BY 36-BIT DYNAMIC RAM MODULE
SMMS236 -
•
Enhanced Page Mode Operation With
CAS-Before-RAS, RAS-Only, and Hidden
Refresh
•
3-State Output
Single 5-V Power Supply
•
72-pin Single-In-Line Package (SIP)
- Leadless Module for Use With Sockets
Common CAS Control for Nine Common
Data-In and Data-Out Lines, in Four Blocks
•
Performance Ranges:
•
TM256KBK36B .•. 262144 x 36
Organization
•
TM512LBK36B ... 524 288
Organization
•
•
•
•
JANUARY 1991
x
36
TM256KBK36B ... Utilizes Eight 1-Megabit
Dynamic RAMs in Plastic Sma"-Outline
J-Lead (SOJ) Packages and One 1-Megabit
Quad-CAS Dynamic RAM in a Plastic
Sma"-Outline J-Lead (SOJ) Package
Long Refresh Period ... 8 ms
(512 Cycles)
•
A" Inputs, Outputs, Clocks Fu"y TTL
Compatible
ACCESS
READ OR
TIME
TIME
WRITE
tRAC
(MAX)
tCAC
(MAX)
CYCLE
60 ns
15 ns
110 ns
±5%
'256KBK36B-70 70 ns
18 ns
130 ns
±10%
'256KBK36B-80 80 ns
20 ns
150 ns
±10%
'256KBK36B-10 100 ns
25 ns
180 ns
±10%
60 ns
15 ns
110 ns
±5%
'512LBK36B-70 70 ns
18 ns
130 ns
±10%
'512LBK36B-80 80 ns
'512LBK36B-10 100 ns
20 ns
150 ns
±10%
25 ns
180 ns
±10%
'256KBK36B-6
TM512LBK36B ... Utilizes Sixteen
1-Megabit Dynamic RAMs in Plastic
Sma"-Outline J-Lead (SOJ) Packages and
Two 1-Megablt Quad-CAS Dynamic RAMs
in Plastic Sma"-Outllne J-Lead (SOJ)
Packages
•
ACCESS
'512LBK36B-6
•
•
VCC
TOLERANCE
(MIN)
Low Power Dissipation
Operating Free-Air Temperature
Range ... O°C to 70°C
description
TM256KBK36B
The TM256KBK36B is a 9437K (dynamic) random-access memory module organized as four times
262144 x 9 [bit nine is generally used for parity] in a 72-pin single-in-line package (SIP). The SIP is composed
of eight TMS44C256DJ, 262 144 x 4-bit dynamic RAMs, each in 20/26-lead plastic small-outline J-Iead
packages (SOJs) and one TMS44C260DJ, 262 144 x 4-bit Quad-CAS dynamic RAM in a 24/26-lead plastic
small-outline J-Iead package (SOJ), mounted on a substrate together with decoupling capacitors. Each
TMS44C256DJ and TMS44C260DJ is described in the TMS44C256 or TMS44C260 data sheets (repectively).
The TM256KBK36B is available in a single-sided BK lead less module for use with sockets.
The TM256KBK36B features RAS access times of 60 ns, 70 ns, 80 ns, and 100 ns. This device is rated for
operation from O°C to 70°C.
TM512LBK36B
The TM512LBK36B is a 18 874K (dynamic) random-access memory module organized as four times
524288 x 9 [bit nine is generally used for parity] in a 72-pin single-in-line package (SIP). The SIP is composed
of sixteen TMS44C256DJ, 262 144 x 4-bit dynamic RAMs, each in 20/26-lead plastic small-outline J-Iead
packages (SOJs) and two TMS44C260DJ, 262 144 x 4-bit Quad-CAS dynamic RAMs in a 24/26-lead plastic
small-outline J-Iead package (SOJ), mounted on a substrate together with decoupling capacitors. Each
TMS44C256DJ and TMS44C260DJ is described in the TMS44C256 or TMS44C260 data sheets (repectively).
PRODUCTION DATA documents contain Information
current II of publication date. Products conform to
spfelfleations per the terms 01 Texas Instruments
~~e~~~a~II~~~~1~1~ r:I~1nu~~~~lr;~~:~~~~~s~oes not
Copyright © 1991, Texas Instruments Incorporated
TEXAS •
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•
HOUSTON, TEXAS 77001
6-45
TM256KBK36B 262 144 BY 36·BIT DYNAMIC RAM MODULE
TM512LBK36B 524288 BY 36·BIT DYNAMIC RAM MODULE
SMMS236 -
JANUARY 1991
BK Singie-in-line Package t
(Top View)
TM256KBK36Bt
(Side View)
TM512LBK36Bt
(Side View)
0
Vss
000
0016
001
0017
002
0018
003
0019
Voo
NC
AD
A1
A2
A3
A4
A5
A6
NC
004
0020
005
0021
006
0022
007
0023
A7
NC
Voo
A8
NC
RAS3
RAS2
MP2
MPO
MP1
MP3
VSS
CASO
CAS2
CAS3
CAS1
RASa
RAS1
NC
Vii
NC
008
0024
OQ9
0025
0010
0026
0011
0027
0012
0028
VOO
0029
0013
0030
0014
0031
0015
NC
POD
P01
P02
P03
NC
VSS
C)
C)
C)
C)
C)
c:::::::::)
C)
C)
C)
C)
C)
c.::::::J
C)
c.::::::J
c:::::::::)
C)
C)
c.::::::J
c.::::::J
C)
C)
c:::::::::)
c:::::::::)
C)
c.::::::J
[=::J
c.::::::J
C)
c:::::::::)
c:::::::::)
C)
C)
c.::::::J
C)
c.::::::J
C)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
C ) 37
C ) 38
C ) 39
c.::::::J
40
C=> 41
c:::::::::) 42
c.::::::J
C)
C)
C)
c:::::::::)
[=::J
c:::::::::)
c.::::::J
C)
c:::::::::)
C)
C)
C)
C)
c:::::::::)
C)
c.::::::J
C)
C)
C)
C)
C)
C)
C)
C)
C)
C)
C)
C)
c:::::::::)
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
c=J
c=J
c=J
c=J
c=J
c=J
c=J
c=J
c=J
PIN NOMENCLATURE
AO-AS
CASO-CAS3
Address Inputs
Column-Address Strobe
000-0031
MPO-MP3
NC
PDO-PD3
RASO-RAS3
Data In/Data Out
Parity
No Connection
VDD
VSS
W
Presence Detects
Row-Address Strobe
5-V Supply
Ground
Write Enable
0
t The packages shown here are for pinout reference only and are not drawn to scale.
TEXAS •
INSlRUMENTS
6-46
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TM256KBK36B 262 144 BY 36-BIT DYNAMIC RAM MODULE
TM512LBK36B 524288 BY 36-BIT DYNAMIC RAM MODULE
SMMS236-JANUARY 1991
The TM512LBK36B is available in a double-sided BK leadless module for use with sockets.
The TM512LBK36B features RAS access times of 60 ns, 70 ns, 80 ns, and 100 ns. This device is rated for
operation from DoC to 70°C.
operation
TM256KBK36B
The TM256KBK36B operates as eight TMS44C256DJs and one TMS44C260DJ connected as shown in the
functional block diagram and Table 1. The parity bits MPO-MP3 are provided by the TMS44C260DJ and are
controlled by RAS2. To ensure proper parity bit operation all memory accesses must include a RAS2 pulse. Refer
to the TMS44C256 and TMS44C260 data sheets for details of operation. The common I/O feature of the
TM256KBK36B dictates the use of early write cycles to prevent contention on D and O.
TM512LBK36B
The TM512LBK36B operates as sixteen TMS44C256DJs and two TMS44C260DJs connected as shown in the
functional block diagram and Table 1. The parity bits MPO-MP3 are provided by the TMS44C260DJs and are
controlled by RAS2 and RAS3 on side 1 and side 2 respectively. To ensure proper parity bit operation all memory
accesses to side 1/side 2 must include a RAS2/RAS3 pulse. Refer to the TMS44C256 and TMS44C260 data
sheets for details of operation. The common I/O feature of the TM512LBK36B dictates the use of early write
cycles to prevent contention on D and O.
single-in-line package and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: Nickel plate and gold plate on top of copper
Table 1. Connection Table
DATA BLOCK
RASx
CASx
SIDE 1
SIDE2
000-007
MPO
RASO
RAS2
RAS1
RAS3
CASO
CASO
008-0015
MP1
RASO
RAS2
RAS1
RAS3
CAS1
CAS1
0016-0023
MP2
RAS2
RAS2
RAS3
RAS3
CAS2
CAS2
0024-0031
MP3
RAS2
RAS2
RAS3
RAS3
CAS3
CAS3
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
6-47
TM256KBK36B 262 144 BY 36·BIT DYNAMIC RAM MODULE
TM512LBK36B 524 288 BY 36·BIT DYNAMIC RAM MODULE
SMMS236 -
JANUARY 1991
functional block diagram (for TM256KBK36B and TM512LBK36B)
A012
A1 13
A214
A315
A416
A517
A618
A728
A831
---"
---"
---"
---"
---"
---"
---"
---"
RAS333
RAS234
RAS145
RASO 44
CAS342
CAS241
CAS143
CAS040
W47
VSS
)
\
\
44C256
AO·A8
RAS
--D CAS
~
r-....
W
G
~
f-.2. OQO
d
f-...-b,
OQ1
OQ2
r--.
~OQ3
44C256
...--
AO·A8
0:~ RAS
CAS
~W
G
~OQ4
~OQ5
~OQ6
~OQ7
44C256
~ AO·A8
RAS
r-.... CAS
r--.
W
G
r-.... CAS
r-..,
W
G
~
W
G
44C256
AO·A8
RAS
CAS
W
G
§OQ8
, l l OQ9
-.53 OQ10
.M. OQ11
~OQ12
OQ13
: : OQ14
OQ15
44C256
~OQ16
:i
OQ17
OQ18
OQ19
44C256
~ AO·A8
RAS
~
~
44C256
AO·A8
RAS
CAS
~OQ20
~OQ21
~OQ22
~ AO·A8
RAS
r--. CAS
r--.
W
G
44C256
AO·A8
RAS
r-.... CAS
~
r--.,
Xl. OQ23
W
G
~OQ24
OQ25
M OQ26
~OQ27
MOQ28
~OQ29
-=:0
OQ30
.M OQ31
44C260
AO·A8
RAS
r--..,
CAS1
CAS2
CAS3 OQ1
r--.. CAS4 OQ2 ~MP3
.:J2 MP1
r-.... W
OQ3 ..3.5. MPO
OQ4
MP2
G
~
~
TEXAS •
INSlRUMENTS
6-48
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TM256KBK36B 262 144 BY 36·BIT DYNAMIC RAM MODULE
TM512LBK36B 524288 BY 36·BIT DYNAMIC RAM MODULE
SMMS236 -
JANUARY 1991
functional block diagram (for TM512LBK36B)
AO-A8 ~
'I
RAS3 ~
(
RAS1
CAS3
CAS2
CAS1
CASO
II
'r-'r--
Iii
VSS
44C256
AO-A8
~ RAS
CAS
+
~W
G
t-
+
[±
r-......
T
r-......
r-......
--t
002
---'- 003
Iii
G
ooa
~ 0010
~
0011
~ 0012
~007
Iii
G
~ 0015
i
44C256
AO-A8
RAS
CAS
Iii
G
Iii
G
r-......
~
....5..1 009
44C256
AO-A8
RAS
CAS
r-ZQ
~
000
~001
44C256
AO-A8
RAS
CAS
44C256
AO-AB
RAS
r--... CAS
r-......
-t
44C256
AO-AS
~ RAS
-I::::::,
CAS
~
004
~005
~006'
~
r--..
~
0016
0017
:j:0018
0019
44C256
AO-AS
RAS
CAS
~0020
Iii
G
~0023
+
[±
r-......
r--...
Iii
G
44C256
AO-AS
~
'r--...
RAS
r-......
CAS
r= 0021
~0022
~
~
r--...
~
r--..
r--...
r-......
Iii
G
~
0013
~ 0014
~ 0024
~ 0025
r-M 0026
~ 0027
0028
~ 0029
~ 0030
~ 0031
44C260
AO-AS
RAS
CAS1
CAS2
001 ~ MP3
CAS3
CAS4' 002 ~ MP1
003 ~. MPO
Iii
004 ~ MP2
G
TEXAS -111
INSTRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
6-49
TM256KBK36B 262 144 BY 36-BIT DYNAMIC RAM MODULE
TM512LBK36B 524288 BY 36-BIT DYNAMIC RAM MODULE
SMMS236 -
JANUARY 1991
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee (see Note 1) ................................................... -1 V to 7 V
Short circuit output current .......................................................... ,..... 50 mA
Power dissipation .......................................................................... 9 W
Operating free-air temperature range .................................................. DoC to 70°C
Storage temperature range ...................................................... - 55°C to 125°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
VCC
Supply voltage (TM256KBK36B-6 and TM512LBK36B-6)
VCC
Supply voltage (TM256KBK36B-70/-80/-1 0 and TM512LBK36B-70/-80/-1 0)
VSS
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage (see Note 2)
TA
Operating free-air temperature
MIN
NOM
MAX
4.75
5
5.25
UNIT
V
4.5
5
5.5
V
2.4
6.5
V
-1
0.8
V
0
70
°c
V
0
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output
voltage
IOH =-5 mA
VOL
Low-level output
voltage
IOL = 4.2 mA
II
Input current
(leakage)
'256KBK36B-6
'256KBK36B-70
'256KBK36B-80
'256KBK36B-10
MIN
MIN
MIN
MIN
MAX
2.4
MAX
2.4
MAX
2.4
UNIT
MAX
2.4
V
0.4
0.4
0.4
0.4
V
±90
±90
± 90
± 90
f.lA
±10
±10
±10
±10
f.lA
855
720
675
585
mA
18
18
18
18
mA
810
720
630
540
mA
630
540
450
405
mA
VI = 0 to 6.5 V,
VCC = 5.5 V, All other
pins = 0 V to VCC
10
Output current
(leakage)
Va = 0 to Vcc,
VCC = 5.5 V, CAS high
ICC1
Read or write
cycle current
VCC = 5.5V
ICC2
Standby current
Minimum cycle,
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V
ICC3
Average refresh
current (RAS-only
orCBR)
Minimum cycle, VCC =
5.5 V, RAS cycling, CAS
high (RAS-only), RAS
low after CAS low (CSR)
tc(P) = minimum,
ICC4
Average page
current
VCC = 5.5 V, RAS low,
CAS cycling
TEXAS •
INSlRUMENTS
6-50
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TM256KBK36B 262144 BY 36-BIT DYNAMIC RAM MODULE
TM512LBK36B 524288 BY 36-BIT DYNAMIC RAM MODULE
SMMS236 - JANUARY 1991
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
'512LBK36B·6
MAX
MIN
VOH
High-level output
voltage
10H =-5 mA
VOL
Low-level output
voltage
10L = 4.2 mA
II
Input current
(leakage)
10
'512LBK36B·70
'512LBK36B·80
'512LBK36B·10
MIN
MIN
MIN
MAX
2.4
2.4
MAX
2.4
MAX
2.4
UNIT
V
0.4
0.4
0.4
0.4
VI = 0 to 6.5 V,
VCC = 5.5 V, All other
pins = 0 V to VCC
± 180
± 180
±180
± 180
~A
Output current
(leakage)
Vo = Oto VCC,
VCC = 5.5 V, CAS high
± 20
± 20
20
± 20
~
ICC1
Read or write
cycle current
VCC = 5.5 V
873
738
693
603
mA
ICC2
Standby current
After 1 memory cycle,
RAS and CAS high,
36
36
36
36
mA
828
738
648
558
mA
648
558
468
423
mA
Minimum cycle,
:!:
V
VIH = 2.4 V
ICC3
Average refresh
current (RAS-only
orCSR)
ICC4
Average page
current
Minimum cycle, VCC =
5.5 V, RAS cycling, CAS
high (RAS-only), RAS
low after CAS low (CSR)
tc(P) = minimum,
VCC = 5.5 V, RAS low,
CAS cycling
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
TM256KBK36B
PARAMETER
MIN
TM512LBK36B
MAX
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
45
90
Ci(R)
Input capacitance, RAS inputs
25
25
pF
pF
Ci(C)
Input capacitance, CAS inputs
15
30
pF
Ci(W)
Input capacitance, write-enable input
45
90
pF
Co(DO)
Output capacitance on DO pins
7
14
pF
CO(MP)
Output capacitance on MP pins
7
14
pF
NOTE 3: VCC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
6-51
TM256KBK36B 262 144 BY 36-BIT DYNAMIC RAM MODULE
TM512LBK36B 524288 BY 36-BIT DYNAMIC RAM MODULE
SMMS236 -
JANUARY 1991
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
ALT.
SYMBOL
'256KBK36B·6
'512LBK36B·6
MIN
MAX
'256KBK36B·70
'512LBK36B·70
MIN
MAX
'256KBK36B·80
'512LBK36B·80
MIN
MAX
'256KBK36B·10
'512LBK36B·10
MIN
UNIT
MAX
18
20
25
ns
30
35
' 40
45
ns
tRAC
60
70
80
100
ns
tCAP
35
40
40
50
ns
talC)
Access time from CAS
ta(CA)
Access time from columnaddress
tCM
talR)
Access time from RAS
ta(CP)
Access time from column
precharge
td(CLZ)
CAS to output in low Z
tCLl
0
tdis(CH)
Output disable time after
CAS high (see Note 4)
tOFF
0
15
tCAC
0
15
0
18
0
0
20
0
ns
25
ns
NOTE 4: tOFF is specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
ALT.
SYMBOL
'256KBK36B·6
'256KBK36B·70
'512LBK36B·6 . '512LBK36B·70
MIN
MAX
MIN
MAX
'256KBK36B·80
'512LBK36B·80
MIN
MAX
'256KBK36B·10
'512LBK36B·10
MIN
UNIT
MAX
tc(rd)
Read cycle time
(see Note 5)
tRC
110
130
150
180
ns
tc(W)
Write cycle time
!wc
110
130
150
180
ns
tc(P)
Page-mode read or write
cycle time
tpc
40
45
50
55
ns
tw(CH)
Pulse duration, CAS high
tcp
10
tw(CL)
Pulse duration, CAS low
tCAS
15
tw(RH)
Pulse duration, RAS high
(precharge)
tRP
40
tw(RL)
Non-page-mode pulse
duration, RAS low
tRAS
60
10000
70
10000
80
10000
100
10000
ns
tw(RL)P
Page-mode pulse duration,
RAS low
tRASP
60
100000
70
100000
80
100000
100
100000
ns
tw(WL)
Write pulse duration
twp
15
15
15
15
ns
tsu(CA)
Column-address setup time
before CAS low
tASC
0
0
0
0
ns
tsu(RA)
Row-address setup time
before RAS low
tASR
0
0
0
0
ns
tsu(D)
Data setup time before CAS
low
tDS
0
0
0
0
ns
tsu(rd)
Read setup time before
CAS low
tRCS
0
0
0
0
ns
tsu(WCL)
W-Iow setup time before
CAS low
twcs
0
0
0
0
ns
tsu(WCH)
W-Iow setup time before
CAS high
tCWL
15
18
20
25
ns
tsu(WRH)
Write-command setup time
before RAS high
tRWL
15
18
20
25
ns
10
10000
18
10
10000
50
~
INSTRUMENTS
6-52
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
ns
10
10000
60
NOTE 5: All cycle times assume tt = 5 ns.
TEXAS
20
25
10000
ns
ns
70
TM256KBK36B 262 144 BY 36-BIT DYNAMIC RAM MODULE
TM512LBK36B 524288 BY 36-BIT DYNAMIC RAM MODULE
SMMS236 -
JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
PARAMETER
ALT.
SYMBOL
'256KBK36B·6
'512LBK36B·6
MIN
MAX
'256KBK36B·70
'512LBK36B·70
MIN
MAX
'256KBK36B·80
'512LBK36B·80
MIN
MAX
'256KBK36B·1O
'512LBK36B·10
MIN
UNIT
MAX
th(CA)
Column-address hold time
after CAS low
tCAH
10
15
15
20
ns
th(RA)
Row-address hold time after RAS low
tRAH
10
10
12
15
ns
th(RLCA)
Column-address hold time
after RAS low (see Note 6)
tAR
50
55
60
70
ns
th(CLCH)
Hold time, CAS low to CAS
high (see Note 7)
tAR
50
55
60
70
ns
th(RLD)
Data hold time after RAS
low (see Note 6)
tDHR
50
55
60
70
ns
th(D)
Data hold time after CAS
low
tDH
10
15
15
20
ns
th(CHrd)
Read hold time after CAS
high (see Note 8)
tRCH
0
0
0
0
ns
th(RHrd)
Read hold time after RAS
high (see Note 8)
tRRH
0
0
0
0
ns
th(CLW)
Write hold time after CAS
low
tWCH
15
15
15
20
ns
th(RLW)
Write hold time after RAS
low
twCR
50
55
SO
70
ns
td(RLCH)
Delay time, RAS low to
CAS high
tCSH
SO
70
80
100
ns
td(CHRL)
Delay time, CAS high to
RAS low
tCRP
0
0
0
0
ns
td(CLRH)
Delay time, CAS low to
RAS high
tRSH
15
18
20
25
ns
td(RLCL)
Delay time, RAS low to
CAS (see Note 9)
tRCD
20
45
20
52
22
SO
25
75
ns
td(RLCA)
Delay time, RAS low to
column-address
tRAD
15
30
15
35
17
40
20
55
ns
td(CARH)
Delay time, column-address to RAS high
tRAL
30
35
40
45
ns
td(CACH)
Delay time, column-address to CAS high
tCAL
30
35
40
45
ns
td(RLCH)R
Delay time, RAS low to
CAS high (see Note 10)
tCHR
15
15
20
25
ns
td(CLRL)R
Delay time, CAS low to
RAS low (see Note 10)
tCSR
10
10
10
10
ns
td(RHCL)R
Delay time, RAS high to
CAS low (see Note 10)
tRPC
0
0
0
0
ns
trf
Distribution refresh time
interval
tREF
tt
Transition time
NOTES: S.
7.
8.
9.
10.
IT
8
8
3
50
3
50
8
3
50
3
8
ms
50
ns
The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
Reference TMS44C2S0 data sheet.
Either th(RHrd) or th(CHrd) must be satisfied for the read cycle.
Maximum value specified only to guarantee access time.
CAS-before-RAS refresh only.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
S-53
TM256KBK36B 262 144 BY 36-BIT DYNAMIC RAM MODULE
TM512LBK36B 524288 BY 36-BIT DYNAMIC RAM MODULE
SMMS236 -
JANUARY 1991
PARAMETER MEASUREMENT INFORMATION
--J
VCC = 1.31 V
Output Under Test
VCC = 5V
RL=218Q
T
=828 Q
R2
=295 Q
Output Under Test
CL = 100 pF
CL=100 pF
(a) Load Circuit
(b) Alternate Load Circuit
Figure 1. Load Circuits for Timing Parameters
TEXAS •
INSTRUMENTS
6-54
R1
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TM256KBK36C 262144 BY 36-BIT DYNAMIC RAM MODULE
TM512LBK36C 524 288 BY 36-BIT DYNAMIC RAM MODULE
SMMS237 -
•
TM256KBK36C ... 262144 x 36-Bit
Organization
•
TM512LBK36C ... 524288 x 36-Bit
Organization
•
•
•
•
•
•
•
•
JANUARY 1991
Performance Ranges:
ACCESS ACCESS
TIME
TIME
READ OR
VCC
WRITE TOLERANCE
tRAC
(MAX)
tCAC
(MAX)
CYCLE
'256KBK36C-6
60 ns
15 ns
110 ns
±5%
72-pin Single-In-Line Package (SIP)
- Leadless Module for Use With Sockets
'256KBK36C-70
70 ns
18 ns
130 ns
±10%
'256KBK36C-80
80 ns
20 ns
150 ns
±10%
'256KBK36C-10 100 ns
25 ns
180 ns
±10%
TM256KBK36C ... Utilizes Eight
1-Megabit Dynamic RAMs in Plastic
Small-Outline J-Lead (SOJ) Packages and
Two 1-Megabit Quad-CAS Dynamic RAMs
in Plastic Small-Outline J-Lead (SOJ)
Packages
'512LBK36C-6
60 ns
15 ns
110 ns
±5%
'512LBK36C-70
70 ns
18 ns
130 ns
±10%
'512LBK36C-80
80 ns
20 ns
150 ns
±10%
'512LBK36C-10
100 ns
25 ns
180 ns
±10%
Single 5-V Power Supply
TM512LBK36C ... Utilizes Sixteen
1-Megabit Dynamic RAMs in Plastic
Small-Outline J-Lead (SOJ) Packages and
Four 1-Megabit Quad-CAS Dynamic RAMs
in Plastic Small-Outline J-Lead (SOJ)
Packages
•
Common CAS Control for Nine Common
Data-In and Data-Out Lines
•
Separate RAS Control for Eighteen
Data-In and Data-Out Lines in Two Blocks
•
Low Power Dissipation
•
Operating Free-Air Temperature
Range ... O°C to 70°C
•
Enhanced Page Mode Operation with
CAS-before-RAS, RAS-only, and Hidden
Refresh
Long Refresh Period ... 8 ms (512 Cycles)
All Inputs, Outputs, Clocks Fully TTL
Compatible
(MIN)
3-State Output
description
TM256KBK36C
The TM256KBK36C is a 9216K dynamic random-access memory module organized as four times
262 144 x 9 [bit nine is generally used for parity] in a 72-pin single-in-line package (SIP). The SIP is composed
of eight TMS44C256DJ, 262 144 x 4-bit dynamic RAMs, each in 20/26-lead plastic small-outline J-Iead
packages (SOJs) and two TMS44C260DJ, 262 144 x 4-bit Quad-CAS dynamic RAMs in 24/26-lead plastic
small-outline J-Iead packages (SOJs), mounted on a substrate together with decoupling capacitors. Each
TMS44C256DJ and TMS44C260DJ is described in the TMS44C256 orTMS44C260 data sheets (respectively).
The TM256KBK36C SIP is available in a single-sided BK leadless module for use with sockets.
The TM256KBK36C SIP features RAS access times of 60 ns, 70 ns, 80 ns and 100 ns. This device is rated for
operation from O°C to 70°C.
PRODUCTION DATA dotuments tontaln Inlormation
tUllent IS 01 publltatlon date. Produtts conlorm to
Ipetlfitatlons per the terms 01 Texas Instruments
~~t~~~:r'~~~~~~i r;~1nu;~~~,r~~~:~~lt~~s~oes not
11
•
Copyright © 1991, Texas Instruments Incorporated
INSTR~NTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
6-55
TM256KBK36C 262144 BY 36·BIT DYNAMIC RAM MODULE
TM512LBK36C 524 288 BY 36·BIT DYNAMIC RAM MODULE
SMMS237 -
JANUARY 1991
TM512LBK36C
The TM512LBK36C is a 18 432K dynamic random-access memory module organized as four times
524288 x 9 [bit nine is generally used for parity] in a 72-pin single-in-Iine package (SIP). The SIP is composed
of sixteen TMS44C256DJ, 262 144 x 4-bit dynamic RAMs, each in 20/26-lead plastic small-outline J-Iead
packages (SOJs) and four TMS44C260DJ, 262 144 x 4-bit Quad-CAS dynamic RAMs in 24/26-lead plastic
, small-outline J-Iead packages (SOJs), mounted on a substrate together with decoupling capacitors. Each
TMS44C256DJ and TMS44C260DJ is described in the TMS44C256 or TMS44C260 data sheets (respectively).
The TM512LBK36C is available in a double-sided BK leadless module for use with sockets.
The TM512LBK36C features RAS access times of 60 ns, 70 ns, 80 ns and 100 ns. This device is rated for
operation from O°C to 70°C.
operation
TM256KBK36C
The TM256KBK36C operates as eight TMS44C256DJs and two TMS44C260DJs connected as shown in the
functional block diagram and Table 1. Refer to the TMS44C256 and TMS44C260 data sheets for details of
operation. The common I/O feature of the TM256KBK36C dictates the use of early write cycles to prevent
contention on D and Q.
TM512LBK36C
The TM512LBK36C operates as sixteen TMS44C256DJs and four TMS44C260DJs connected as shown in the
functional block diagram and Table 1. Refer to the TMS44C256 and TMS44C260 data sheets for details of
operation. The common I/O feature of the TM512LBK36C dictates the use of early write cycles to prevent
contention on D and Q.
single-in-line package and components
PC substrate: 1,27 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: Nickel plate and gold plate on top of copper
Table 1. Connection Table
RASx
DATA BLOCK
CASx
Side 1
Side 2
OOO-OO?
MPO
RASO
RAS1
CASO
008-0015
MP1
RASO
RAS1
CAS1
0016-0023
MP2
RAS2
RAS3
CAS2
0024-0031
MP3
RAS2
RAS3
CAS3
TEXAS
-1!1
INSlRUMENlS
6-56
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TM256KBK36C 262 144 BY 36·BIT DYNAMIC RAM MODULE
TM512LBK36C 524288 BY 36·BIT DYNAMIC RAM MODULE
SMMS237 -
BK Singie-in-line Package t
(Top View)
JANUARY 1991
TM512LBK36C
BK Singie-in-line Package t
(Side View)
TM256KBK36C
BK Singie-in-line Package t
(Side View)
G
E:::)
E:::)
E:::)
E:::)
E:::)
E:::)
E:::)
E:::)
E:::)
E:::)
E:::)
E:::)
E:::)
A2 E:::)
A3 E:::)
A4 E:::)
A5 E:::)
A6 E:::)
NC E:::)
004 E:::)
0020 E:::)
005 E:::)
0021 E:::)
006 E:::)
0022 E:::)
007 E:::)
0023 E:::)
A7 E:::)
NC E:::)
Vec E:::)
A8 E:::)
NC E:::)
RAS3 E:::)
RAS2 E:::)
MP2 E:::)
MPO E:::)
Vss
000
0016
001
0017
002
0018
003
0019
VCC
NC
AO
Al
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
MPl E:::) 37
MP3 E:::) 38
VSS E:::) 39
CASO E:::) 40
CAS2 E:::) 41
CAS3 E:::) 42
CASl E:::) 43
RASO E:::) 44
RASl E:::) 45
t:!Q E:::) 46
W E:::) 47
NC E:::) 48
008 E:::) 49
0024 E:::) 50
009 E:::) 51
D025 c::::=J 52
0010 E:::) 53
0026 c::::=J 54
0011 E:::) 55
0027 E:::) 56
0012 E:::) 57
0028 E:::) 58
VCC E:::) 59
0029 E:::) 60
0013 E:::) 61
0030 E:::) 62
0014 E:::) 63
0031 E:::) 64
0015 E:::) 65
NC E:::) 66
POO
67
POl E:::) 68
P02 E:::) 69
P03 E:::) 70
NC E:::) 71
VSS E:::) 72
c=:>
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PIN NOMENCLATURE
AO-AB
CASO-CAS3
RASO-RAS3
DOO-D031
Address Inputs
Column-Address Strobe
Row-Address Strobe
VCC
VSS
PDO-PD3
Data In/Data Out
Write Enable
No External Connection
5-V Supply
Ground
Presence Detects
MPO-MP3
Parity
W
NC
G
t The packages shown here are for pinout reference only and are not drawn to scale.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
6-57
TM256KBK36C 262144 BY 36·BIT DYNAMIC RAM MODULE
TM512LBK36C 524288 BY 36·BIT DYNAMIC RAM MODULE
SMMS237 -
JANUARY 1991
functional block diagram (TM256KBK36C)
12
13
14
15
16
17
18
28
31
AD
Al
A2
A3
A4
AS
A6
A7
A8
44
RASO
34
RAS2
40
CASO
43
CASI
41
CAS2
42
CAS3
-
47
W
TMS44C2s6
~ AD-A8
.--~
RAS
oa2
CAS
'"',",Iii
t-
~
oa3
r--!!-
oa4
-
G
+
TMS44C2s6
AD-A8
oal
RAS
H- --b
r2r--!-
oal
VCC
VSS
I
I
"- CAS
,",Iii
oao
oal
oa3
oa3
oas
~G Vcc VSS
~
-~
TMS44C260
CASI
'"' CAS2
'"'
,-b
CAS3
~
CAS4
~ MPO
oa2 ~ MPI
oal
t-t--
oa3
oa4
NC
G
~
"-
VCC
VSS
-
t~l··
• • •
+
C20
0.22 uF
~
G
I
.2! oa12
oa2 ~ oa13
oa3 ,..E oa14
oa4 ~ DaIS
VCC VSS
TMS44C260
AO-A8
"- RAS
,...D
~
oal
CASl
CAS2
'"-"' CAS4
CAS3
-
NC
oa3
-~
MP2
oa4
c2!
MP3
oa2
~
~
,...
r2-
oa20
oa2 ~ oa21
~ oa22
~ 0023
003
oa4
VCC VSS
NC
VCC VSS
1
TMS44C256
AO-A8
oal ~ 0024
RAS
oa2 .23 oa25
CAS
oa3 ~ 0026
"-Iii
G
oa4 ~ oa27
VCC VSS
TMS44C2S6
AO-A8
oal ~ oa28
"- RAS
oa2 ~ oa29
CAS
"oa3 ,E oa30
"-Iii
004 ~ oa31
~G VCC VSS
I
1
TEXAS -1!1
POST OFFICE BOX 1443
G
L-~
INSlRUMENTS
6-58
.-- G
-
TMS44C256
AD-A8
oal
RAS
,",Iii
I
,,-Iii
oa4 ~ oa19
VCC VSS
"- CAS
'---
VSS
"- CAS
r1-
"-Iii
e-..,L
Vcc
"-Iii
1
G
-~ ~
rt--
VCC VSS
TMS44C256
AO-A8
oal ~ oa16
"- RAS
oa2 ~ oa17
"- CAS
oa3
oa18
-
~
TMS44C2s6
AD-A8
oal
RAS
NC
"-Iii
rt--
G
~
AO-A8
RAS
~
oa4 ~ oa11
r--
oa6
oa4 ~ OQ7
2!
'"',",Iii
oa2
~ oa4
rErE-
oa2
TMS44C2s6
AO-A8
oal ~ oa8
"- RAS
oa9
oa2
CAS
oa3 ~ oal0
~
•
HOUSTON. TEXAS 77001
I
functional block diagram (TM512LBK36C)
AO
Al
-E.
.-ll
A2~
A3~
A4...1§.
AS-1I
A6 ~
A7 ...ll!
AS.2!
RASO
44
RASl ~
RAS3....1;!
RAS2
CASO
...M.
30.
~
CAS2 ~
CASl
CAS3
Vi
42
47
I
"
a
(f)
"TI_
-i
a
~Z
~~~
~C
6~
~f'f'J
_~
Z
~ U3~
E
•
H
(f)
~
::!:C:~1~4
RAS
002
003
W
0Q4
aVcc VSS
~AS
6
8
000
001
002
003
~
1~~C256
RAS
CAS
001
002
W
003
G
0Q4
VCCVSS
~
TMS44C260
AD-A8
RAS
001
CASl
CAS2
CAS3
~20
004
24 DOS
26 006
007
002~7
36 MPO
MPl
NC
NC
~
~
m
in
co
~+t
61"
,
VSS
• ••
I
,,~AS
~
~
0011
~
e-t-t---r-t-'-1'!j
~~
~
~61
0012
63 0013
65
~
CASl
CAS2
" CAS3
... CAS4
~~~:
0020
0021
0022
0023
1
NC
NC
MP2
MP3
1
I
9
L..r"
~
L-c,
,---D
~
"
+--
1
~
~
G VCC VSS
l I T
~ 004
~
DOS
26 000
007
RAS
CAS
Vi
TMS44C260
AO-AS
RAS
CASl
CAS2
CAS3
CAS4
001
002
003
004
w
TMS44C256
RAS
CAS
....+++---t-'''t'!j
58
t-
~37 MPl
MPO
NC
NC
~
I
JIIj
I
I
,,~AS
~
0031
~
61 0012
63 0013
65
~~~:
21
002~
003~
0022
0023
.
"~004
G VCC VSS
1~~C256
,,~AS
r-
~
mOl
-<-<
cncn
I
mOl
TMS44C256
AD-AS
~O
"RAS
001 520024
,,002 54 0025
~AS
003 56 0026
0027
9
N-'
co .r:::ta
co .r:::ta
ww
9
"RAS
,,-
00
~N
NC
NC
MP2
MP3
1'----1'
'23 0020
'25 0021
ww
""
cncn
Ncn
"lcAS4
-
mOl
c.n N
1 "IVi
001
002
003 ~
004 f--=
G VCC VSS
~~
I"
~7
rt-ia VCC VSS
0Q4~
1~~C256
RAS
,,-
Oal
002
-1-1
S:S:
c.nN
-. c.n
Ncn
TMS44C260
AD-A8
RAS
Oal
CASl
CAS2
CASJ
0Q4
~
G VCC VSS
9
'6ii OQ2S
f--62 0Q29
r-s4 0030
55 0alO
0011
G VCcVSS
f-5
~
~9 DOS
002~! 009
--.,.-,-
t+~rr~~~AD-A8
TMS44C256
AO-AS 001 3
0016
RAS
" 002 I-'- 0017
,,~AS
003 ~ 001S
0019
-
oal
003
_
0Q4
GVCC VSS
9
9
0Q4~0027
G VCC VSS
001
002
003
004
.w
001
002
003
004
a VCC VSS
~
1
TMS44C256
AO-AS
50
RAS
001 ~ 0024
,,002 i-=: 0Q25
~AS
003 ~ 0026
_......t:> RAS
" ~AS
-rT
~
TMS44C256
AD-AS
G VCCVSS
001 t 002 t-:::::
003 ~
004 ~
~ 1~~44C256
2
-=-
w
i-+-+t--t-t-,- I ~AS
~+1rt-tI-r-
~
..-f--..-b
~
001~
000
002: 001
003 8 002
_
004
003
GVCC VSS
RAS
CAS
9 AD-A8
RAS
9
0016
0017
001S
0019
TMS44C256
AD-AS
TMS44C256
TMS44C260
I ~ AO-AS
H--t>
RAS
-
001
002 ~
003 ~
0Q4....!!..
G VCC VSS
1
C20 _
0.22 uF
_
0Q4
GVCC VSS
I~--'
G VCC VSS
RAS
,,-
~~~ :~~O
I--t> W
TMS44C256
AO-AS
3
RAS
001 ~
,,002 -=~AS
0032
"w
004
~ l~~C256
~4~ 008
rt- a VCC VSS
9
L - f-..t::>
001
9 :::rC::l
'-1---t-r-...".CAS
002
CAS4
~
r-
~AS
9
-- Vi
T I I
E
RAS
G VCCVSS
003
004
~
TMS44C256
AD-AS
001
002
003
0Q4
G VCC VSS
i~
I
I
5S
~O 0,028
62 0029
62 0030
0031
=i=i
cc
-<-<
-ZZ
l>l>
s:s:
00
::tI ::tI
l>l>
s:s:
s:s:
00
CC
c::: c:::
II
mm
TM256KBK36C 262144 BY 36·BIT DYNAMIC RAM MODULE
TM512LBK36C 524288 BY 36·BIT DYNAMIC RAM MODULE
SMMS237 -
JANUARY 1991
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee ............................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation ......................................................................... 10 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ...................................................... - 65°C to 150°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
VCC
Supply voltage (TM256KSK36C-6 and TM512LSK36C-6)
VCC
Supply voltage (TM256KSK36C-70/-80/-10 and TM512LSK36C-70/-80/-1 0)
VSS
Supply voltage
,vIH
High-level input voltage
VIL
Low-level input voltage (see Note 2)
TA
Operating free-air temperature
MIN
NOM
MAX
4.75
5
5.25
V
4.5
5
5.5
V
2.4
6.5
V
-1
0.8
V
0
70
°c
0
UNIT
V
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logiC
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
'256KBK36C-6
MIN
VOH
High-level
output voltage
10H =-5 mA
VOL
Low-level
output voltage
IOL= 4.2 mA
II
Input current
(leakage)
'256KB K36C-70
MAX
MIN
2.4
2.4
VI = 0 to 6.5 V, VCC = 5 V
All other pins = 0 V to
MAX
'256KBK36C-80
MIN
MAX
2.4
'256KBK36C-10
MIN
UNIT
MAX
V
2.4
0.4
0.4
0.4
0.4
V
±100
±100
±100
±100
flA
VCC
10
Output
current
(leakage)
Vo = 0 to 6.5 V,
VCC = 5.5 V, CAS high
±10
±10
±10
±10
flA
ICC1
Read or write
cycle current
tRWC = minimum,
VCC = 5.5 V
950
800
750
650
mA
ICC2
Standby
current
20
20
20
20
mA
900
800
700
600
mA
700
600
500
450
mA
ICC3
Average
refresh
current
(RAS-only or
CSR)
ICC4
Average page
current
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V
tRWC = minimum,
VCC = 5.5 V, RAS cycling,
CAS high (RAS-only),
RAS low after CAS low
(CSR)
tpc = minimum,
VCC = 5.5 V,
RAS low, CAS cycling
TEXAS
~
INSlRUMENTS
6-60
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TM256KBK36C 262 144 BY 36-BIT DYNAMIC RAM MODULE
TM512LBK36C 524288 BY 36-BIT DYNAMIC RAM MODULE
SMMS237 - JANUARY 1991
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
'512LBK36C-6
MIN
VOH
High-level
output voltage
10H =-5 rnA
VOL
Low-level
output voltage
10L = 4.2 rnA
II
Input current
(leakage)
10
Output
current
(leakage)
ICC1
Read or write
cycle current
ICC2
Standby
current
'512LBK36C-70
MIN
MAX
MAX
2.4
2.4
'512LBK36C-80
MIN
MAX
'512LBK36C-10
MIN
2.4
2.4
UNIT
MAX
V
V
0.4
0.4
0.4
0.4
±200
±200
±200
±200
flA
±20
±20
±20
±20
flA
970
820
770
670
rnA
40
40
40
40
rnA
920
820
720
620
rnA
720
620
520
470
rnA
VI = 0 to 6.5 V,
VCC = 5 V,
All other pins = 0 V to
VCC
ICC3
Average
refresh
current
(RAS-only
orCSR)
ICC4
Average page
current
Vo = 0 to 6.5 V,
VCC = 5.5 V, CAS high
tRWC = minimum,
VCC = 5.5 V
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V
tRWC = minimum,
VCC = 5.5 V, RAS cycling,
CAS high (RAS-only),
RAS low after CAS low
(CSR)
tpc = minimum,
VCC = 5.5 V,
RAS low, CAS cycling
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f =1 MHz (see Note 3)
PARAMETER
TM256KBK36C
TM512LBK36C
MIN
MIN
UNIT
MAX
MAX
Input capacitance, address inputs
50
100
pF
Ci(R)
Input capacitance, RAS inputs
25
25
pF
Ci(C)
Input capacitance, CAS inputs
15
30
pF
Input capacitance, write-enable input
50
100
pF
Output capacitance, DO
7
14
pF
Output capacitance on MP pins
7
14
pF
Ci(A)
Ci(W)
Co(DO)
Co(MP)
NOTE 3: VCC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
6-61
TM256KBK36C 262 144 BY 36-BIT DYNAMIC RAM MODULE
TM512LBK36C 524 288 BY 36-BIT DYNAMIC RAM MODULE
SMMS237 - JANUARY 1991
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
MIN
TM25SKBK3SC·80
TM512LBK36C·80
TM25SKBK3SC·70
TM512LBK36C·70
TM256KBK36C·S
TM512LBK3SC·S
MAX
MAX
MIN
TM25SKBK3SC·10
TM512LBK36C·10
MAX
MIN
MIN
UNIT
MAX
tCAC
Access time from
CAS low
15
18
20
25
ns
tCM
Access time from
column-address
30
35
40
45
ns
tRAC
Access time from
RAS low
60
70
80
100
ns
tCAP
Access time from
column precharge
35
40
40
50
ns
tOFF
Output disable time after
CAS high (see Note 4)
25
ns
0
15
18
0
20
0
0
NOTE 4: tOFF is specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
'25SKBK3SC·70
'512LBK36C·70
'256KBK3SC·6
'512LBK3SC·S
PARAMETER
MIN
MAX
MIN
MAX
'25SKBK3SC·80
'512LBK36C·80
MIN
MAX
'256KBK36C·10
'512LBK36C·10
MIN
UNIT
MAX
tRC
Read cycle time (see Note 6)
110
130
150
180
ns
twc
Write cycle time
110
130
150
180
ns
tpc
Page-mode read or write cycle time
(see Note 7)
40
45
50
55
ns
tcp
Pulse duration, CAS high
10
tCAS
Pulse duration, CAS low
15
tRP
Pulse duration, RAS high (precharge)
40
tRAS
Non-page-mode pulse duration,
RAS low
SO
10000
70
10000
80
10000
100
10000
ns
tRASP
Page-made pulse duration, RAS low
60
100000
70
100000
80
100000
100
100000
ns
twp
Write pulse duration
15
tASC
Column-address setup time before
CAS low
tASR
Row-address setup time before RAS low
tDS
Data setup time before W low
tRCS
10
18
10000
10
10000
50
20
ns
10
10000
60
25
10000
ns
ns
70
15
15
15
ns
0
0
0
0
ns
0
0
0
0
ns
0
0
0
0
ns
Read setup time before CAS low
0
0
0
0
ns
twcs
W-Iow setup time before CAS low
0
0
0
0
ns
tCWL
W-Iow setup time before CAS high
15
18
20
25
ns
tRWL
W-Iow setup time before RAS high
15
18
20
25
ns
tCAH
Column-address hold time after CAS low
10
15
15
20
ns
tRAH
Row-address hold time after RAS low
10
10
12
15
ns
tAR
Column-address hold time after RAS low
(see Note 8)
50
55
60
70
ns
NOTES: 5.
6.
7.
8.
Timing measurements are referenced to VIL max or VIH min.
All cycle times assume tt = 5 ns.
tpc > tcp min + tCAS min + 2tr.
The minimum value is measured whcntRCD is sct to tRCD min as a reference.
TEXAS •
INSlRUMENTS
6-62
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TM256KBK36C 262 144 BY 36-81T DYNAMIC RAM MODULE
TM512LBK36C 524288 BY 36-81T DYNAMIC RAM MODULE
SMMS237 - JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
'256KBK36C·6
'512LBK36C·6
PARAMETER
MIN
tClCH
Hold time, CAS low to CAS high
(see Note 12)
MAX
'256KBK36C·70
'512lBK36C·70
MIN
MAX
'256KBK36C·8O
'512lBK36C·8O
MIN
MAX
'256KBK36C-10
'512lBK36C-10
MIN
UNIT
MAX
5
ns
15
20
ns
ns
5
5
5
10
15
tDH
Data hold time after CAS low
tDHR
Data hold time after RAS low
(see Note 8)
tRCH
Read hold time after CAS high
(see Note 9)
tRRH
Read hold time after RAS high
(see Note 9)
0
0
tWCH
Write hold time after CAS low
15
15
tWCR
Write hold time after RAS low
(see Note 8)
50
55
tCSH
Delay time, RAS low to CAS high
60
70
tCRP
Delay time, CAS high to RAS low
0
tRSH
Delay time, CAS low to RAS high
15
tRCD
Delay time, RAS low to CAS low
.(see Note 10)
20
45
20
52
22
60
25
75
ns
tRAD
Delay time, RAS low to column-address
(see Note 10)
15
30
15
35
17
40
20
55
ns
tRAl
Delay time, column-address to RAS high
30
35
40
45
ns
tCAl
Delay time, column-address to CAS high
30
35
40
45
ns
tCHR
Delay time, RAS low to CAS high
(see Note 11)
15
15
20
25
ns
tCSR
Delay time, CAS low to RAS low
(see Note 11)
10
10
10
10
ns
tRPC
Delay time, RAS high to CAS low
(see Note 11)
0
0
0
0
ns
tREF
Refresh time interval
tT
Transitiion time
NOTES: 8.
9.
10.
11.
12.
50
55
60
70
0
0
0
0
ns
0
0
ns
15
20
ns
60
70
ns
80
100
ns
0
0
'0
ns
18
20
25
ns
8
8
3
50
3
50
8
3
50
3
8
ms
50
ns
The minimum value is measured when tRCD is set to tRCD min as a reference.
Either tRRH or tRCH must be satisfied for the read cycle.
Maximum value specified only to guarantee access time.
CAS-before-RAS refresh only.
See TMS44C260 data sheet.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
6-63
TM256KBK36C 262 144 BY 36-BIT DYNAMIC RAM MODULE
TM512LBK36C 524288 BY 36-BIT DYNAMIC RAM MODULE
SMMS237 - JANUARY 1991
PARAMETER MEASUREMENT INFORMATION
-I
VCC = 1.31 V
Output Under Test
I
VCC = 5 V
=828 Q
R2
=295 Q
Output Under Test
CL=100pF
CL=100pF
(a) Load Circuit
(b) Alternate Load Circuit
Figure 1. Load Circuits for Timing Parameters
TEXAS
~
INSTRUMENTS
6-64
R1
"l=21S0
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TM4100GBD8
4194304 BY 8-BIT DYNAMIC RAM MODULE
SMMS408 -
This Data Sheet is Applicable to All
TM4100GBDBs Symbolized with Revision "B"
and Subsequent Revisions as Described on
Page 6-71.
•
4 194 304 x 8 Organization
•
Single 5-V Power Supply
•
3D-Pin Single-In-Line Package (SIP)
- Leadless Module for Use with Sockets
•
Utilizes Eight 4-Megabit Dynamic RAMs in
Plastic Small-Outline J-Lead Packages
(SOJs)
•
Long Refresh Period. .. 16 ms
(1024 Cycles)
•
All Inputs, Outputs, Clocks Fully TTL
Compatible
•
•
3-State Output
BD Single-in-Line
Package t
(Top View)
0
vcc
CAS
DOl
AO
Al
D02
A2
A3
·VSS
D03
A4
A5
D04
A6
A7
D05
A8
A9
Al0
D06
Performance Ranges:
ACCESS
ACCESS ACCESS
W
READ
TIME
TIME
TIME
OR
tRAC
tAA
tCAC
WRITE
(MAX)
(MAX)
(MAX)
(MIN)
60 ns
30 ns
15 ns
110 ns
VSS
D07
NC
D08
NC
RAS
NC
NC
VCC
CYCLE
'4100GBD8-6
JANUARY 1991
'4100GBD8-70
70 ns
35 ns
18 ns
130 ns
'4100GBD8-80
80 ns
40 ns
20 ns
150 ns
'4100GBD8-10 100 ns
50 ns
25 ns
180 ns
•
Common CAS Control for Eight Common
Data-In and Data-Out Lines
•
Seperate CAS Control for One Separate
Pair of Data-In and Data-Out Lines
•
Low Power Dissipation
•
Operating Free-Air Temperature Range
... DoC to 70°C
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
D
D
D
D
D
D
D
D
0
t The package shown is for pinout reference only.
PIN NOMENCLATURE
AO-Al0
CAS
D01-D08
NC
RAS
VCC
VSS
description
W
Address Inputs
Column-Address Strobe
Data In/Data Out
No Connection
Row-Address Strobe
5-V Supply
Ground
Write Enable
The TM4100G808 is a 36 864K (dynamic)
random-access memory module organized as
4 194 304 x 8-bits in a 30-pin single-in-line
package (SIP).
The SIP is composed of eight TMS441 OOOM or TMS441 OOOJ, 4 194304 x 1-bit dynamic RAMs in 20/26-lead
plastic small-outline J-Iead packages (SOJ), mounted on a substrate with decoupling capacitors.
PRODUCTION DATA documents contain Information current as
of publication date. Products conform to specifications per the
terms of TexIS Instruments standard warranty. Production
processing does not necessarily Include testing of all
parameters.
TEXAS
-I!}
Copyright © 1991, Texas Instruments Incorporated
INSIRUMENlS
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TM4100GBD8
4 194304 BY 8-BIT DYNAMIC RAM MODULE
SMMS408 -
JANUARY 1991
The TMS41 00GB08 SIP is available in the BO single-sided, lead less module for use with sockets.
The TMS41 00GB08 SIP is characterized for operation from O°C to 70°C.
operation
The TMS41 00GB08 operates as eight TMS441 OOOMs or TMS441 OOOJs connected as shown in the functional
block diagram. Refer to the TMS441 00 data sheet for details of its operation. The common I/O feature of the
TM41 00GB08 dictates the use of early write cycles to prevent contention on 0 and Q.
single-in-line package and components
PC substrate: 1,27 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: Nickel plate and solder plate on top of copper
TEXAS ~
INSlRUMENTS
6-66
POST OFFICE BOX 1443
•
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TM4100GBD8
4 194304 BY 8-BIT DYNAMIC RAM MODULE
SMMS408 -
JANUARY 1991
functional block diagram
AO
A1
A2
A3
A4
AS
AS
A7
A8
A9
A10
5
7
8
11
12
14
15
17
18
19
RAS
CAS
27
2
21
Vi
t-+llD01
4096K
AO-A10
RAS
CAS
Vi
3
D
VCC
r
t-+llD02
409SK
AD-A10
RAS
CAS
D
~
VCC
4096K
AO-A10
RAS
CAS
D
VCC
Lp.L
--b
VCC
VCC
VSS
VSS
~
Vss
I
1
~
D
VCC
-1TC-"CT
an
Vss
1S
D
r
VCC
4096K
AD-A10
RAS
--" CAS
~
an
~
DOS
20
x1
D
~
an
Vss
VCC
4096K
AO-A10
RAS
CAS
Vss
23
1
Lp.L
--b
an
D
VCC
4096K
AD-A10
RAS
CAS
Vss
25
~
r
1
D
VCC
an
x1
Vi
D08
or
x1
Vi
D07
an
x1
Vi
r
x1
Vss
4096K
AO-A10
RAS
CAS
w
DOS
x1
Vi
13
1
30
4096K
AD-A1D
RAS
CAS
~
x1
Vi
10
r
D04
Vss
Vi
S
I
D03
x1
Vss
an
I
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) ........................ :................. - 1 V to 7 V
Voltage range on Vee .............................. '. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 8 W
Operating free-air temperature range .................................................. ooe to 70°C
Storage temperature range ...................................................... - 55°C to 125°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
,
TEXAS ~
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TM4100GBD8
4 194 304 BY 8-BIT DYNAMIC RAM MODULE
SMMS40B -
JANUARY 1991
recommended operating conditions
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
Supply voltage (TM41 00GBD8-70/-80/-1 0)
4.5
5
5.5
V
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
°e
Vee
Supply voltage (TM41 00GBD8-6)
Vee
VIH
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VOH
High-level
output voltage
10H
VOL
Low-level
output voltage
IOL =4.2 mA
II
Input current
(leakage)
10
lee1
=-5 mA
'4100G808-6
'4100G808-70
'4100G808-80
MIN
MIN
MIN
MAX
'41 00G808-1 0
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
0.4
V
VI =0 to 6.5 V, Vee = 5 V,
All other pins =0 V to Vee
±10
±10
±10
±10
IlA
Output current
(leakage)
Vo =OtoVee,
Vee =5.5 V, eAS high
±10
±10
±10
±10
IlA
Read or write
cycle current
(see Note 3)
Minimum cycle, Vee
760
680
600
520
mA
16
16
16
16
mA
8
8
8
8
mA
760
680
600
520
mA
560
480
400
320
mA
Standby
Current
ICC3
Average
refresh current
(see Note 3)
ICC4
Average page
current
(see Note 4)
=5.5 V
VIH
=2.4 V (TTL)
After 1 memory cycle,
RAS and CAS high,
VIH =VCC - 0.2 V (CMOS)
Minimum cycle, VCC = 5.5 V,
RAS cycling, CAS high
~ =
minimum, VCC = 5.5 V,
RAS low, CAS cycling
NOTES: 3. Measured with a maximum of one address change while RAS =VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS -III.
INSlRUMENTS
6-68
MAX
2.4
2.4
2.4
After 1 memory cycle,
RAS and CAS high,
ICC2
MAX
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TM4100GBD8
4 194 304 BY 8-BIT DYNAMIC RAM MODULE
SMMS40a -
JANUARY 1991
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f =1 MHz
MIN
PARAMETER
UNIT
MAX
Ci(A)
Input capacitance, address inputs
40
pF
Ci(RC)
Input capacitance, strobe inputs
56
pF
Ci(W)
Input capacitance, write-enable input
56
pF
Co
Output capacitance (pins 001-008)
12
pF
NOTE 5: VCC equal to 5 V
±
0.5 V and the bias on the pin under test is 0 v.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'4100GBD8-6
PARAMETER
MAX
MIN
'4100GBD8-70
'4100GBD8-80
MIN
MIN
MAX
MAX
'4100GBD8-10
MIN
MAX
UNIT
tAA
Access time from column-address
30
35
40
45
ns
tCAC
Access time from CAS low
15
18
20
25
ns
tCPA
Access time from column precharge
35
40
45
50
ns
tRAC
Access time from RAS low
60
70
80
100
ns
tCLZ
CAS to output in low Z
0
tOFF
Output disable time after CAS high
(see Note 6)
0
0
15
0
18
0
ns
0
0
20
0
25
ns
NOTE 6: tOFF is specified when the output is no longer driven.
TEXAS
~
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6-69
TM4100GBD8
4 194 304 BY 8-BIT DYNAMIC RAM MODULE
SMMS40B -
JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
tRC
Random read or write cycle (see Note 7)
tpc
Page-mode read or write cycle time
(see Note 8)
tRASP
Page-mode pulse duration, RAS low
tRAS
Non-page-mode pulse duration, RAS low
tCAS
Pulse duration, CAS low
tcp
Pulse duration, CAS high
tRP
Pulse duration, RAS high (precharge)
twp
Write pulse duration
tASC
Column-address setup time before CAS low
tASR
Row-address setup time before RAS low
tos
Data setup time
tRCS
Read setup time before CAS low
tCWL
W-Iow setup time before CAS high
'4100GBDS-6
'4100GBDS-70
'4100GBDS-SO
'4100GBDS-10
MIN
MIN
MIN
MIN
tRWL
W-Iow setup time before RAS high
W-Iow setup time before CAS low
tWSR
W-high setup time (CAS-before-RAS
refresh only)
tWTS
W-Iow setup time (test mode only)
tCAH
Column-address hold time after CAS low
tDHR
Data hold time after RAS low (see Note 9)
tOH
Data hold time
tAR
Column-address hold time after RAS low
(see Note 9)
tRAH
Row-address hold time after RAS low
tRCH
Read hold time after CAS high (see Note 10)
tRRH
Read hold time after RAS high (see Note 10)
tWCH
Write hold time after CAS low
tWCR
Write hold time after RAS low (see Note 10)
MAX
MAX
MAX
UNIT
110
130
150
180
ns
40
45
50
55
ns
60
60
15
10
40
15
0
0
0
0
15
15
0
twcs
MAX
100000
10000
10000
70
70
18
10
50
15
0
0
0
0
18
lS
0
100000
10000
10000
80
SO
20
10
60
15
0
0
0
0
20
20
0
100000
10000
10000
100
100
25
10
70
20
0
0
0
0
25
25
0
100000
10 000
10000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
10
10
10
10
50
10
10
15
55
15
10
15
60
15
10
20
75
20
50
55
60
75
ns
10
0
0
15
50
10
0
0
15
55
10
0
0
15
60
15
0
0
20
75
ns
ns
tWHR
W-high hold time (CAS-before-RAS
refresh only)
10
10
10
10
ns
tWTH
W-Iow hold time (test mode only)
10
10
10
10
ns
Continued next page.
NOTES: 7. All cycle times assume tT = 5 ns.
S. To guarantee tpc min, tASC should be greater than or equal to tcp.
9. The minimum value is measured when tRCD is set to tRCO min as a reference.
10. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS
~
INSlRUMENTS
6-70
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
ns
ns
ns
ns
ns
ns
ns
ns
TM4100GBD8
4 194304 BY 8-81T DYNAMIC RAM MODULE
SMMS408 -
JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
'4100G808-6
MIN
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
tCHR
MAX
'4100G808-70
MIN
MAX
'4100G808-80
15
15
MAX
MIN
20
'4100G808-10
MIN
MAX
UNIT
20
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
0
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
100
ns
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
10
ns
tRAD
Delay time, RAS low to column-address
(see Note 11)
15
tRAL
Delay time, column-address to RAS high
30
35
40
45
ns
tCAl
Delay time, column-address to CAS high
30
35
40
45
ns
tRCD
Delay time, RAS low to CAS low
(see Note 11)
20
tRPC
Delay time, RAS high to CAS low
0
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
25
ns
tTAA
Access time from address (test mode)
35
40
45
50
ns
tTCPA
Access time from column precharge
(test mode)
40
45
50
55
ns
65
tTRAC
Access time from RAS (test mode)
tREF
Refresh time interval
tT
Transition time
30
45
15
20
35
52
75
16
50
2
15
40
20
60
50
25
50
75
105
85
16
16
2
20
2
50
2
ns
ns
ns
16
ms
50
ns
NOTE 11: The maximum value is specified only to guarantee access time.
device symbolization
The specifications contained in this data sheet are applicable to all TM4100GBD8s symbolized as shown in
Figure 1. Please note that the location of the part number may vary.
DDDDDDDD
TM41 00GBD8-xx -
0
REV B
Figure 1. Device Symbolization
TEXAS •
INSlRUMEN1S
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6-71
TM4100GBD8
4 194 304 BY 8-BIT DYNAMIC RAM MODULE
SMMS408 -
JANUARY 1991
TEXAS ~
INSlRUME~TS
6-72
POST OFFICE BOX 1443-
HOUSTON, TEXAS 77001
TM124BBK32
1 048 576 BY 32-BIT
DYNAMIC RAM MODULE
SMMS132 -
This Data Sheet is Applicable to All
TM124BBK32s Symbolized with
Revision "B" and Subsequent Revisions
as Described on Page 6-79.
•
•
•
•
•
•
TM124BBK32 ... 1 048576 x 32
Organization
JANUARY 1991
•
3-State Output
•
Common CAS Control for Eight Common
Data-In and Data-Out Lines, In Four Blocks
• Performance Ranges:
Single 5-V Power Supply
72-pin Single-In-Line Package (SIP)
- Leadless Module for Use With Sockets
ACCESS
ACCESS
TIME
TIME
tRAC
tCAC
READ
VCC
OR TOLERANCE
WRITE
CYCLE
Utilizes Eight 4-Megabit Dynamic RAMs in
Plastic Small-Outline J-Lead (SOJ)
Packages
(MAX)
(MAX)
(MIN)
60 ns
15 ns
110 ns
±5%
'124BBK32-70 70 ns
18 ns
130 ns
±10%
'124BBK32-80 80 ns
20 ns
25 ns
150 ns
180 ns
±10%
'124BBK32-10 100 ns
'124BBK32-6
Distributed Refresh Period ... 16 ms
(1024 Cycles)
• Low Power Dissipation
All Inputs, Outputs, Clocks Fully TTL
Compatible
• Operating Free-Air-Temperature
Range ... O°C to 70°C
±10%
description
The TM124BBK32 is a 33 526K (dynamic) random-access memory organized as four times 1 048576 x 8 in
a 72-pin single-in-line package (SIP). The SIP is composed of eight TMS44400, 1 048576 x 4-bit dynamic
RAMs, each in 20/26-lead plastic sma"-outline J-Iead packages (SOJs), mounted on a substrate with decoupling
capacitors mounted beneath the SOJs. Each TMS44400 is described in the TMS44400 data sheet.
The TM124BBK32 SIP is available in the single-sided BK leadless module for use with sockets.
The TM124BBK32 SIP features RAS access times of 60 ns, 70 ns, 80 ns, and 100 ns. This device is rated for
operation from O°C to 70°C
operation
The TM 124BBK32 operates as eightTMS44400DMs connected as shown in the functional block diagram. Refer
to the TMS44400 data sheet for details of operation. The common I/O feature of the TM 124BBK32 dictates the
use of early write cycles to prevent contention on D and Q.
specifications
Refresh period is extended to 16 milliseconds and, during this period, each of the 1024 rows must be strobed
with RAS in order to retain data. AO-A9 address lines must be refreshed every 16 ms as required by the
TMS44400 DRAM. CAS can remain high during the refresh sequence to conserve power.
single-in-line package and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: Nickel plate and gold plate on top of copper
PRODUCTION DATA documents contain Information
current IS of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily Include testing of all parameters.
!
TEXAS
"11
Copyright © 1991, Texas Instruments Incorporated
INSTRUMENTS
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TM124BBK32
1 048 576 BY 32·BIT
DYNAMIC RAM MODULE
SMMS132- JANUARY 1991
BK Single-In-line Package t
(Top View)
TM124BBK32t
(Side View)
G
vss
000
0016
001
0017
002
0018
003
0019
VCC
NC
AO
A1
A2
A3
A4
A5
A6
NC
004
0020
005
0021
006
0022
007
0023
A7
NC
VCC
A8
A9
RAS3
RAS2
NC
NC
NC
NC
VSS
CASO
CAS2
CAS3
CAS1
RASO
RAS1
NC
Vi
NC
OOS
0024
009
0025
0010
0026
0011
0027
0012
0028
Vcc
0029
0013
0030
0014
0031
0015
NC
NC
NC
NC
NC
NC
VSS
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
c::J
c::J
c::J
c::J
c::J
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
c::=J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
c::J
CJ
D
D
D
D
D
D
D
PIN NOMENCLATURE
AO-A9
CASO-CAS3
000-0031
NC
RASO-RAS3
VCC
VSS
IN
G
t The packages shown here are for pinout reference only and are not drawn to scale.
TEXAS •
INSlRUMENTS
6-74
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
Address Inputs
Column-Address Strobe
Data In/Data Out
No Internal Connection
Row-Address Strobe
5-V Supply
Ground
Write Enable
functional block diagram
A012
A113
A214
A315
A416
A517
A618
A728
A831
A932
CAS342
CAS241
CAS143
RAS145
RAS044
CAS040
W47
VSS
z
~
~
~
~
~
~
~
~
-
r-
10~
I[
~4r
--------
------
~ AO-A9
.. ~ RAS
...•
I"'---~S
W
DQODQ4 ~
DQ02
DQ14
DQ26
DQ38
DQ163
DQ175
DQ187
DQ199
10
L.:..r::::" RAS
L..-D
CAS
I"'---W
G
~
01
-
G
DQODQ4
DQODQ4
~
'---
DQ2021
DQ2123
DQ2225
DQ2327
W
G
DQO-~
DQ849
DQ951
DQ1053
DQ1155
~AO-A9
L---1:::::. RAS
~~AS
AO-A9
RAS
~~AS
DQODQ4 ~
~
10~
'"'44400"
•
G
'---
~ AO-A9
0)
~
~
DQODQ4 ~
~
10~
tt
•
44400
AO-A9
RAS
-1:::::,
CAS
r-...
W
~
G
G
DQ420
DQ522
DQ624
DQ726
r-
44400
.~ AO-A9
~f-t::" RAS
CAS
r-..
W
~
DQ2450
DQ2552
DQ2654
PQ2756
10
"444'0'0
10
~
RAS
~~AS
...
~W
W
G
G
DQODQ4 ~
DQO-~
DQ4
~
~
DQ1257
DQ1361
DQ1463
DQ1565
~
44400
AO-A9
RAS
L-t:::" CAS
~AO-A9
DQ2858
DQ2960
DQ3062
DQ3164
c
-<
z
l> .....
:5: 0
cn-~
~ (") co
~:a
c:.n
-I
fd l> ~ :5:
l:5:
.....
to
cOe:,..) to
~CNto
~:5:-<~
-
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:::>
c:J
c:::>
c:J
c:J
c:J
c:::>
c:::>
c:::>
c:::>
c:J
c:::>
c:::>
c:J
c:::>
c:::>
c:::>
c:::>
c:J
c:J
c:::>
c:::>
c:::>
c:J
c:J
c:::>
c:::>
~ c:::>
CAS2 c:::>
CAS3 c:::>
CASl c:::>
RASO c:J
NC c:::>
NC c:::>
Iii c:::>
NC c:::>
008 c:::>
0024 c:::>
MPl
MP3
Vss
009
.0025
0010
0026
0011
0027
0012
0028
VCC
0029
0013
0030
0014
0031
0015
NC
POO
POl
P02
PD3
NC
Vss
c:J
c:J
c:J
c:::>
c:::>
c:::>
c:::>
c:J
c:::>
c:::>
c:::>
c:::>
c:J
c:::>
c:::>
c:::>
c:::>
c:J
c:J
c:::>
c:::>
c:::>
c:J
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
TM124MBK36At
(Side View)
D
D
PIN NOMENCLATURE
AO-A9
CASO-CAS3
DOO-D031
MPO-MP3
NC
PDO-PD3
RASO,RAS2
VCC
VSS
W
t The package shown here is for pinout reference only and is not drawn to scale.
TEXAS
-1!1
INSTRUMENTS
6-90
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Address Inputs
Column-Address Strobe
Data In/Data Out
Parity
No Connection
Presence Detects
Row-Address Strobe
5-V Supply
Ground
Write Enable
TM124MBK36A
1 048 575 BY 36-BIT
DYNAMIC RAM MODULE
SMMS136 -
JANUARY 1991
Table 1. Connection Table
DATA BLOCK
RASx
CASx
DO-D07
MPO
RAsa
008-0015
MP1
RAsa
CAS1
0016-0023
MP2
RAS2
CAS2
0024-0031
MP3
RAS2
CAS3
--
CASO
single-in-line package and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: Nickel plate and gold plate on top of copper
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
6-91
0>
A012
A113
A214
A315
A416
A517
A618
A728
A831
A932
-z
.;i
::r:
rr1
oz.
-~ ~~
-i
~
mC -a. -t
functional block diagram
O) N
----,
mZ
----,
Ol::::llc.n~
----,
'=: . . . . :s:
----,
j;o 0') CJ
----,
2:c CJ
----,
-<::::IIWO')
-------------
~:5:
to
0-
c-t
c:
rm
-
:44400
4
~~
f"..-
~
~
CAS
r---.
W
-
....
....
a
a
4
...
OE
-
DOOD03
:-
~
L1:::,
~
"-
l..-
RAS
4
W
OE
DOOD03
""'---
D01257
D01361
D01463
D01565
....
D020 21
D02123
D02225
D02327
.....--
Il
MP137
D
0
I---
DOO-~
D03
-44400
10
RAS
f..AS
4~
~
w
-
OE
10~
~n
-
D02858
D02960
D03062
D03164
DOOD03 ~
:-
~
4C1024
AO-A9
~ RAS
RAS
n
~ RAS
f"..- f..AS
~
~ CAS
,~~AS
MP235
-44400
~ AO-A9
W
DOOD03
~ AO-A9
~
L-...b W
~
W
~
D02450
D02552
D02654
D02756
OE
10 4C1024
AO-A9
RAS
~ CAS
W
0
10
44400
AO-A9
RAS
CAS
OE
~ AO-A9
..J::::" CAS
4C1024
AO-A9
RAS
CAS
D
.J::::"
~r--..
~
"------
D0163
D0175
D0187
D0199
~
~W
RAS
f..AS
W
DOOD03 ~
44400
.;g AO-A9
4
~
4~
OE
~
D0849
D0951
D010 53
D01155
CAS
DO'~ 20
D0522
D0624
D0726
W
~
DOO-#
-44400
~
t~ AO-A9
4
RAS
rJl
4
4
OE
DOOD03 #
:-
~
10 44400
~ AO-A9
4
OE
D002
D014
D026
D038
-
44400
AO-A9
4
RAS
~ CAS
~ AO-A9
4~
4
RAS
MP036
~
5j;t>-
----,
~
MP338
-
W
~n
TM124MBK36A
1 048 576 BY 36-BIT
DYNAMIC RAM MODULE
SMMS136- JANUARY 1991
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee (see Note 1) ................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation ......................................................................... 12 W
Operating free-air temperature range .................................................. DoC to 70°C
Storage temperature range ... :.................................................. - 55°C to 125°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation ofthe device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for ex1ended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage (see Note 2)
TA
Operating free-air temperature
MIN
NOM
MAX
4.75
5
5.25
UNIT
V
2.4
6.5
V
-1
0.8
V
0
70
°c
z
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
o-
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
a:
PARAMETER
VOH
High-level output voltage
TEST CONDITIONS
'124MBK36A-7
MIN
MIN
MAX
MAX
2.4
2.4
IOH =-5 mA
'124MBK36A-8
MIN
UNIT
MAX
V
2.4
V
0.4
0.4
0.4
± 120
± 120
± 120
flA
Output current (leakage)
Vo = OtoVCC,
VCC = 5.5 V, CAS high
±10
±10
±10
~tA
Read or write cycle current
(see Note 3)
Minimum cycle, VCC = 5.5 V
1140
1000
900
mA
After 1 memory cycle, RAS and
CAS high, VIH = 2.4 V (TTL)
24
24
24
mA
After 1 memory cycle, RAS and
CAS high, VIH =VCC - 0.2 V
(CMOS)
12
12
12
mA
VOL
Low-level output voltage
IOL = 4.2 mA
II
Input current (leakage)
VI = 0 to 6.5 V, VCC = 5.5 V,
All other pins = 0 V to VCC
10
ICC1
ICC2
'124MBK36A-6
Standby current
ICC3
Average refresh current
(RAS-only or CSR)
(see Note 3)
Minimum cycle, VCC = 5.5 V,
RAS cycling, CAS high
(RAS-only), RAS low after
CAS low (CSR)
1120
1000
880
mA
ICC4
Average page current
(see Note 4)
tpc = minimum, VCC =5.5 V,
RAS low, CAS cycling
840
720
600
mA
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS . .
INSTRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
6-93
~
~
o
u.
Z
W
U
Z
~
c
«
TM124MBK36A
1 048 576 BY 36·BIT
DYNAMIC RAM MODULE
SMMS136-JANUARY 1991
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
TYP
MIN
PARAMETER
MAX
UNIT
Ci(A)
Input capacitance, address inputs
60
pF
Ci(C)
Input capacitance, CAS inputs
19
pF
Ci(R)
Input capacitance, RAS inputs
38
pF
Ci(W)
Input capacitance, write-enable input
76
pF
Co (DO)
Output capacitance on DO pins
7
pF
Output capacitance on MP pins
12
pF
Co(MP)
NOTE 5: VCC equal to 5 V ± 0.5 V and the bias on pins unde,r test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
»c
~
z(')
m
-z
"o:xJ
~
~
o
z
'124MBK36A-6
'124MBK36A-7
'124MBK36A-8
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
tAA
Access time from column-address
30
35
40
ns
tCAC
Access time from CAS low
15
18
20
ns
tCPA
Access time from column precharge
35
40
45
ns
tRAC
Access time from RAS low
60
70
80
ns
tCLZ
CAS to output in low Z
0
tOFF
Output disable time after CAS high (see Note 6)
a
0
15
a
ns
0
18
0
20
ns
NOTE 6: tOFF is specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and qperating free-air
temperature
'124MBK36A-6
'124MBK36A-7
'124MBK36A-8
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
tRC
Random read or write cycle (see Note 7)
110
130
150
tpc
Page-mode read or write cycle time (see Note 8)
40
45
50
tRASP
Page-mode pulse duration, RAS low
60
100 000
70
100000
80
100000
ns
tRAS
Non-page-mode pulse duration, RAS low
60
10 000
70
10000
80
10000
ns
tCAS
Pulse duration, CAS low
15
10 000
18
10000
20
10000
ns
tcp
Pulse duration, CAS high
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
ns
twp
Write pulse duration
15
15
15
ns
tASC
Column-address setup time before CAS low
0
0
ns
tASR
Row-address setup time before RAS low
Data setup time
tRCS
Read setup time before CAS low
a
a
a
0
a
a
a
ns
tDS
a
a
a
tCWL
W-Iow setup time before CAS high
15
18
20
ns
tRWL
W-Iow setup time before RAS high
15
18
20
ns
twcs
W-Iow setup time before CAS low
0
0
a
ns
tWSR
W-high setup time (CAS-before-RAS refresh only)
10
10
10
ns
NOTES: 7. All cycles assume tT = 5 ns.
8. To guarantee tpc min, tASC should be greater than or equal to tcP'
TEXAS
-1!1
INSlRUMENTS
6-94
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
ns
ns
ns
ns
TM124MBK36A
1 048 576 BY 36-BIT
DYNAMIC RAM MODULE
SMMS136-JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
'124MBK36A-6
'124MBK36A-7
'124MBK36A-8
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
tCAH
Column-address hold time after CAS low
10
15
15
ns
tDHR
Data hold time after RAS low (see Note 9)
50
55
60
ns
tDH
Data hold time
10
15
15
ns
tAR
Column-address hold time after RAS low (see Note 9)
50
55
60
ns
tRAH
Row-address hold time after RAS low
10
10
12
ns
tRCH
Read hold time after CAS high (see Note 10)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 10)
0
0
0
ns
tWCH
Write hold time after CAS low
15
15
15
ns
tWCR
Write hold time after RAS low (see Note 10)
50
55
60
ns
tWHR
W-high hold time (CAS-before-RAS refresh only)
10
10
10
ns
tCHR
Delay time, RAS low to CAS high (CAS-before-RAS
refresh only)
15
15
20
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
,ns
tCSR
Delay time, CAS low to RAS low (CAS-before-RAS
refresh only)
10
10
10
ns
tRAD
Delay time, RAS low to column-address (see Note 11)
15
tRAl
Delay time, column-address to RAS high
30
35
40
ns
tCAl
Delay time, column-address to CAS high
30
35
40
ns
tRCD
Delay time, RAS low to CAS low (see Note 11)
20
tRPC
Delay time, RAS high to CAS low
0
tRSH
Delay time, CAS low to RAS high
15
tREF
Refresh time interval
tT
Transition time
30
45
15
20
35
52
0
50
22
60
50
3
ns
ns
ns
ns
20
16
3
40
0
18
16
3
17
16
ms
50
ns
The specifications contained in this data sheet are applicable to all TM124MBK36As symbolized as shown in
Figure 1. Please note that the location of the part number may vary.
DDDDDDc
Figure 1. Device Symbolization
-I!I
INSlRUMENTS
POST OFFICE BOX 1443
•
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~
0:
o
LL
Z
W
(J
~
c
device symbolization
TEXAS
~
Z
NOTES: 9. The minimum value is measured when tRCD is set to tRCD min as a reference.
10. Either tRRH or tRCH must be satisfied for a read cycle.
11. The maximum value is specified only to guarantee access time.
o
z
o
6-95
<3:
TM124MBK36A
1 048 576 BY 36-BIT
DYNAMIC RAM MODULE
SMMS136-JANUARY 1991
TEXAS "!1
INSTRUMENTS
6-96
POST OFFICE BOX 1443
•
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TM124MBK36B
1 048 576 BY 36-BIT
DYNAMIC RAM MODULE
SMMS137-JANUARY 1991
This Data Sheet is Applicable to All
TM124MBK36Bs Symbolized with
Revision "B" and Subsequent Revisions
as Described on Page 6-103.
•
Common CAS Control for Nine Common
Data-In and Data-Out Lines, in Four Blocks
•
•
TM124MBK36B ... 1 048576 x 36
Organization
Enhanced Page Mode Operation with CASBefore-RAS, RAS-Only, and Hidden Refresh
•
Performance Ranges:
•
Single 5-V Power Supply (5% Tolerance)
•
72-pin Single-In-Line Package (SIP)
- Leadless Module for Use With Sockets
•
Long Refresh Period ... 16 ms
(1024 Cycles)
•
All Inputs, Outputs, Clocks Fully TTL
Compatible
ACCESS ACCESS
READ
TIME
TIME
TIME
OR
tRAC
tAA
tCAC
WRITE
(MAX)
(MAX)
(MAX)
(MIN)
'124MBK36B-6
60 ns
30 ns
15 ns
110 ns
'124MBK36B-7
70 ns
35 ns
18 ns
130 ns
'124MBK36B-8
80 ns
40 ns
20 ns
150 ns
CYCLE
Utilizes Eight 4-Megabit Dynamic RAMs in
Plastic Small-Outline J-Lead (SOJ)
Packages and One 4-Megabit Quad-CAS
Dynamic RAM in a Plastic Small-Outline
J-Lead (SOJ) Package
•
o
ACCESS
•
Low Power Dissipation
•
Operating Free-Air-Temperature
Range ... O°C to 70°C
•
Presence Detect
.
z
o
~
a
a:
o
LL
3-State Output
description
The TM124MBK36B is a37 748K (dynamic) random-access memory organized as four times 1 048576 x 9 [bit
9 is generally used for parity] in a 72-pin single-in-line package (SIP). The SIP is composed of eight
TMS44400DM or TMS44400DJ, 1 048 576 x 4-bit dynamic RAMs, each in 20/26-lead plastic small~outline
J-Iead packages (SOJs), and one TMS44460DJ, 1 048 576 x 4-bit Quad-CAS dynamic RAM, in a 24/26-lead
plastic small-outline J-Iead package (SOJ) mounted on a substrate with decoupling capacitors. Each
TMS44400DM or TMS44400DJ and TMS44460DJ is described in the TMS44400 and TMS44460 data sheets
(respectively) .
The TM124MBK36B SIP is available in the single-sided BK leadless module for use with sockets.
TheTM124MBK36B SIP features RAS access times of60 ns, 70 ns, and 80 ns. This device is rated foroperation
from O°C to 70°C
operation
The TM 124MBK36B operates as eight TMS44400DMs or TMS44400DJs and one TMS44460DJ connected as
shown in the functional block diagram and Table 1. The parity bits MPO-MP3 are provided by the TMS44460DJ
and are controlled by RAS2. To ensure proper parity bit operation all memory accesses should include a RAS2
pulse. Refer to the TMS44400 and TMS44460 data sheets for details of operation. The common I/O feature
dictates the use of early write cycles to prevent contention on 0 and Q.
ADVANCE
INFORMATION
documents
contain
Information on new products In the sampling or
preproduction phase of development. Characteristic
data and other specifications are subject to change
without notice.
TEXAS
~
Copyright © 1991, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443
•
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6-97
Z
W
U
Z
~
c
. .~~~~~~~~.
EPROMs/OTPs/Flash EEPROMs
TMS27C128131 072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC128131 072·BIT PROGRAMMABLE READ·ONLY MEMORY
REV A -
SMLS 1280 -
This Data Sheet is Applicable to All
TMS27C128s and TMS27PC128s Symbolized
with Code "8" as Described on Page 7-12.
•
•
Organization ... 16K x 8
•
Pin Compatible With Existing 128K MOS
ROMs, PROMs, and EPROMs
•
•
All Inputs/Outputs Fully TTL Compatible
'27C128-100
'27C128-120
'27C/PC128-1
'27C/PC128-2
'27C/PC128
100
'27C128-12
120
'27C/PC128-15 150
'27C/PC128-20 200
'27C/PC128-25 250
•
•
Very High-Speed SNAP! Pulse Programming
•
VCC
A12
A?
A6
A5
PGM
A13
A8
A9
A11
A2
A1
AO
DQ1
DQ2
DQ3
GND
ns
ns
ns
ns
ns
Power Saving CMOS Technology
•
Vpp
IT
•
•
(Top View)
Max Access/Min Cycle Times
Vee ± 10%
REVISED JANUARY 1991
J and N Packages
Single 5-V Power Supply
Vee±5%
OCTOBER 1984 -
A10
E
D08
DO?
D06
D05
D04
FM Package
(Top View)
3-State Output Buffers
400-mV Minimum DC Noise Immunity With
Standard TTL Loads
A6
A5
A4
A3
A2
Latchup Immunity of 250 rnA on All Input
and Output Lines
=
Low Power Dissipation (Vee 5.25 V)
- Active ... 158 m'w Worst Case
- Standby ... 1.4 mW Worst Case
(CMOS Input Levels)
D01
•
PEP4 Version Available With 168 Hour
Burn-in and Choices of Operating
Temperature Ranges
•
128K EPROM Available With MIL-STD-883C
Class B High-Reliability Processing
(SMJ27C128)
0
3231 30
29
6
28
7
27
A8
A9
A11
8
26
NC
9
25
IT
A10
E
D08
DO?
10
24
11
23
12
22
21
13
14 15 16 17 18 19 20
PIN NOMENCLATURE
AO-A13
description
E
G
The TMS27C128 series are 131 072-bit, ultraviolet-light erasable, electrically programmable
read-only memories.
GND
NC
NU
PGM
The TMS27PC128 series are 131 072-bit, onetime, electrically programmable read-only memories.
PROOUCTION DATA documents contain Information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily Include testing of all parameters.
4 321
5
D01-D08
VCC
VPP
Address Inputs
Chip Enable/PowerClown
Output Enable
Ground
No Connection
Make No External Connection
Program
Inputs (programming)/Outputs
S-V Power Supply
12-13 V Programming Power Supply
Copyright © 1991, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
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•
HOUSTON, TEXAS 77001
7-1
TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
REV A -
SMLS128D -
OCTOBER 1984 -
REVISED JANUARY 1991
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The data outputs are three-state for connecting multiple devices to a common bus. The TMS27C128 and the
TMS27PC128 are pin compatible with 28-pin 128K MOS ROMs, PROMs, and EPROMs.
The TMS27C128 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 1S,2-mm (600-mil) centers. The TMS27C128 is offered with two operating temperature
ranges of O°C to 70°C and - 40°C to 8SoC (TMS27C128-__JL and TMS27C128-__JE, respectively). The
TMS27C128 is also offered with 168-hour burn-in temperature ranges (TMS27C128-__ JL4 and
TMS27C128-__JE4, respectively). (See table below).
The TMS27PC128 PROM is offered in a dual-in-line plastic package (N suffix) designed for insertion in mounting
hole rows on 1S,2-mm (600-mil) centers. The TMS27PC128 is also supplied in a 32-lead plastic leaded chip
carrier package using 1,2S-mm (SO-mil) lead spacing (FM suffix). The TMS27PC128 is also offered with two
operating temperature ranges of O°C to 70°Cand- 40°C to 8SoC (TMS27PC128-__ NL, TMS27PC128-__NE
and TMS27PC128-__ FML, TMS27PC128-__FME respectively). The TMS27PC128 is also offered with 168
NL4, TMS27PC128NE4 and TMS27PC128FML4,
hour burn-in temperature ranges (TMS27PC128TMS27PC128-__ FME4, respectively). (See table below).
- -All package styles conform to JEDEC standards:
EPROM
AND
PROM
SUFFIX FOR OPERATING
TEMPERATURE RANGES
WITHOUT PEP4 BURN-IN
SUFFIX FOR OPERATING
TEMPERATURE RANGES WITH
PEP4 168 HR. BURN-IN
O°C TO 70°C
- 40°C TO 85°C
O°CT070°C
TMS27C128-XXX
JL
JE
JL4
- 40°C TO 85°C
JE4
TMS27PC128-XXX
NL
NE
NL4
NE4
TMS27PC128-XXX
FML
FME
FML4
FME4
These EPROMs and PROMs operate from a single S-V supply (in the read mode), thus are ideal for use in
microprocessor-based systems. One other 12-13 V supply is needed for programming. All programming signals
are TTL level. These devices are programmable by using the SNAP! Pulse programming algorithm.The SNAP!
Pulse programming algorithm uses a Vpp of 13 V and a Vee of 6.S V for a nominal programming time of two
seconds. For programming outside the system, existing EPROM programmers can be used. Locations may be
programmed singly, in blocks, or at random.
TEXAS
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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
REV A- SMLS128D- OCTOBER 1984- REVISED JANUARY 1991
operation
There are seven modes of operation listed in the following table. Read mode requires a single 5-V supply. All
inputs are TTL level exceptforVpp during programming (13 VforSNAPI Pulse) and 12 Von A9 for signature
mode.
MODE
FUNCTION
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE
MODE
VIL
vlL
VIH
VIL
VIH
VIL
VIH
Vpp
X
X
VIH
Vpp
Vee
E
VIL
VIL
G
VIL
VIH
VIH
xt
PGM
VIH
VIH
X
Vpp
Vee
Vee
Vee
VIL
Vpp
Vee
Vee
X
Vee
x
Vee
x
Vee
x
Vee
A9
Vee
x
X
VH
AO
X
X
X
X
X
X
VIL
VIL
Vee
I
I
VHt
VIH
eODE
DQ1-DQ8
Data Out
HI-Z
Data In
HI-Z
Data Out
HI-Z
MFG
I
DEVleE
97
I
83
t X can be VIL or VIH.
t VH = 12 V ± 0.5 V.
TEXAS .J!}
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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
REV A -
SMLS128D -
OCTOBER 1984 -
REVISED JANUARY 1991
read/output disable
When the outputs of two or more TMS27C128s or TMS27PC128s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs of
the other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All
other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these pins.
Output data is accessed at pins 001 through 008.
latchup immunity
Latchup immunity on the TMS27C128 and TMS27PC128 is a minimum of 2S0 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input/output layout approach controls latchup
without compromising performance or packing density.
For more information see application report SMLA001, "Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family", available through TI Sales Offices.
power down
Active Icc supply current can be reduced from 30 mA to SOO I-lA (TTL-level inputs) or 2S0 I-lA (CMOS-level inputs)
by applying a high TTL or CMOS signal to the E pin. In this mode all outputs are in the high-impedance state.
erasure (TMS27C128)
Before programming, the TMS27C128 EPROM is erased by exposing the chip through the transparent lid to
a high intensity ultraviolet light (wavelength 2537 A). EPROM erasure before programming is necessary to
assure that all bits are at the logic high level. Logic lows are programmed into the desired locations. A programmed logic low can be erased only by ultraviolet light. The recommended minimum ultraviolet light exposure dose (UV intenSity x exposure time) is 1S-W·s/cm2. A typical 12-mW/cm2, filterless UV lamp will erase
the device in 21 minutes. The lamp should be located about 2.S cm above the Chip during erasure. It should
be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when using the
TMS27C128, the window should be covered with an opaque label.
initializing (TMS27PC128)
The one-time programmable TMS27PC128 PROM is provided with all bits at the logic high level. The logic lows
are programmed into the desired locations. Logic lows programmed into a PROM cannot be erased.
SNAP! Pulse programming
The 128K EPROM and PROM are programmed using the TI SNAP! Pulse programming algorithm illustrated
by the flowchart in Figure 1, which programs in a nominal time of two seconds. Actual programming time will
vary as a function of the programmer used.
Data is presented in parallel (eight bits) on pins 001 to 008. Once addresses and data are stable, PGM is
pulsed.
The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (I-ls) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-l-ls
pulses per byte are provided before a failure is recognized ..
The programming mode is achieved when Vpp = 13 V, Vee = 6.S V, G = VIH, and E = VIL. More than
one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified
with Vee = Vpp = S V.
program inhibit
Programming may be inhibited by maintaining a high level input on the E or PGM pin.
TEXAS
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TMS27C128 131 072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC128 131 072·BIT PROGRAMMABLE READ·ONLY MEMORY
REV A -
SMLS128D -
OCTOBER 1984 -
REVISED JANUARY 1991
program verify
Programmed bits may be verified with Vpp = 13 V when G = VIL,
E = VIL, and PGM = VIH.
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode
is activated when A9 is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by AO; i.e., AO
VIL
accesses the manufacturer code, which is output on 001-008; AO = VIH accesses the device code, which
is output on 001-008. All other addresses must be held at VIL' Each byte possesses odd parity on bit
008. The manufacturer code for these devices is 97, and the device code Is 83.
=
TEXAS ~
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7-5
TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
REV A -
SMLS128D -
OCTOBER 1984 -
REVISED JANUARY 1991
Interactive
Mode
Final
Verification
j
Figure 1. SNAP! Pulse Programming Flowchart
TEXAS
~
INSTRUMENTS
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POST OFFICE BOX 1443
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TMS27C128131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-81T PROGRAMMABLE READ-ONLY MEMORY
REV A -
SMLS12BD -
OCTOBER 1984 -
REVISED JANUARY 1991
logic symbols t
PROM 16 384 x 8
EPROM 16 384 x 8
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11
A12
A13
E
o"
10
9
8
7
6
5
4
3
25
24
21
23
2
26
20
>
A_O_
16383
AV
AV
AV
AV
AV
AV
AV
AV
11
12
13
15
16
17
18
19
AO
A1
A2
A3
001
CO2
C03
C04
COS
C06
C07
C08
A4
AS
A6
A7
A8
A9
A10
A11
A12
A13
13
L
22
"-
27
"-
E
[PWR CWN]
10
9
8
7
6
5
4
3
25
24
21
23
2
26
20
>
&
11
12
13
15
16
17
18
19
001
C02
C03
C04
COS
C06
C07
C08
13
[PWR CWN]
22
"-
PGM 27
f'...,
G
A_O_
16383
AV
AV
AV
AV
AV
AV
AV
AV
L&
'-
EN
0
EN
t These symbols are in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
Pin numbers shown are J and N packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)*
Supply voltage range, Vee (see Note 1) .............................................. - 0.6 V to 7 V
Supply voltage range, Vpp (see Note 1) ............................................. - 0.6 V to 14 V
Input voltage range (see Note 1), All inputs except A9 ................................ - 0.6 V to 6.5 V
A9 ............................................... - 0.6 V to 13.5 V
Output voltage range (see Note 1) ............................................. - 0.6 V to Vee + 1 V
Operating free-air temperature range (,27C128-__JL and JL4, '27PC128-__NL, and NL4
FML, and FML4) .................................. O°C to 70°C
Operating free-air temperature range ('27C128-__JE and JE4, '27PC128-.:.... _NE, NE4,
FME, and FME4) ................................ - 40°C to 85°C
Storage temperature range ....................................................... - 65°C to 150°C
:j: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section
of this specification is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
.
NOTE 1: Under absolute maximum ratings, voltage values are with respect to GND.
TEXAS
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7-7
TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-B11 PROGRAMMABLE READ-ONLY MEMORY
REV A- SMLS128D- OCTOBER 1984- REVISED JANUARY 1991
recommended operating conditions
'27C128·100
'27C128·120
'27C/PC128·1
'27C/PC128·2
'27C/PC128
Vee Supply Voltage
VPP Supply voltage
'27C128·12
'27C/PC128·15
'27C/PC128·20
'27C/PC128·25
UNIT
MAX
MIN
NOM
MAX
MIN
NOM
Read mode (see Note 2)
4.75
5
5.25
4.5
5
5.5
SNAP! Pulse programming algorithm
6.25
6.5
6.75
6.25
6.5
6.75
Read mode (see Note 3)
VIH High-level input voltage
VIL Low-level input voltage
Vee+ 0.6 Vec- 0.6
Vee- 0.6
SNAP! Pulse programming algorithm
12.75
TTL
2
CMOS
13.25
13
VCC+1
VCC-0.2
VCC+ 1
V
VCC + 0.6
12.75
13.25
13
2
V
VCC+1
VCC- 0.2
VCC+1
V
TTL
-0.5
0.8
-0.5
0.8
V
CMOS
-0.5
0.2
-0.5
0.2
V
0
70
0
70
°c
-40
85
- 40
85
°c
'27C128- __JL,JL4
T A Operating free-air temperature '27PC128-__ NL,NL4
FML, FML4
'27C128-__JE,JE4
T A Operating free-air temperature '27PC128-__ NE,NE4
FME, FME4
NOTES: 2. VCC must be applied before or atthe same time asVpp and removed afteror atthe same time as Vpp. The device must not be inserted
into or removed from the board when VPP or VCC is applied.
3. VPP can be connected to VCC directly (except in the program mode). VCC supply current in this case would be ICC + Ipp.
electrical characteristics over full ranges of operating conditions
PARAMETER
VOH
VOL
TEST CONDITIONS
High-level output voltage
Low-level output voltage
TYpt
MIN
MAX
UNIT
V
10H= -2.5mA
3.5
10H = -20!!A
Vec- 0. 1
V
10L= 2.1 mA
0.4
V
IOL = 20 !!A
0.1
V
II
Input current (leakage)
VI = Oto 5.5 V
±1
J!A
10
Output current (leakage)
Vo = OtoVCC
±1
!!A
IpP1
Vpp supply current
Vpp = VCC = 5.5 V
IpP2
Vpp supply current (during program pulse)
Vpp=13V
Ice1
Vee supply current (standby)
ITTL-input level
Vee = 5.5 V, E = VIH
I
CMOS-input level
lee2
Vee = 5.5 V,
E = Vec
Vee = 5.5 V, E = VIL,
tcycl e = minimum cycle time,
outputs open
Vee supply current (active)
1
10
!!A
35
50
mA
250
500
J!A
100
250
!!A
15
30
mA
t Typical values are at TA = 25°e and nominal voltages.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f
1 MHz;
=
TYpt
MAX
ei
Input capacitance
VI = 0, f = 1 MHz
6
10
pF
Co
Output capacitance
Vo = 0, f = 1 MHz
10
14
pF
PARAMETER
TEST CONDITIONS
t Typical values are at TA = 25°C and nominal voltages.
:j: Capacitance measurements are made on sample basis only.
TEXAS
~
INSTRUMENTS
7-8
POST OFFICE BOX 1443
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MIN
UNIT
TMS27C128 131 072·BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
REV A- SMLS128D- OCTOBER 1984 -
REVISED JANUARY 1991
switching characteristics overfull ranges of recommended operating conditions (see Notes 4 and 5)
TEST CONDITIONS
(SEE NOTES 4 AND 5)
PARAMETER
'27C128-120
'27C128-12
'27C128-100
MIN
MAX
MIN
UNIT
MAX
ta(A)
Access time from address
100
120
ns
tatE)
Access time from chip enable
100
120
ns
ten (G)
Output enable time from G
50
55
ns
tdis
Output disable time from Gor E, whichever occurs firstt
45
ns
tv (A)
Output data valid time after change of address,
E, or G, whichever occurs first t
PARAMETER
CL = 100 pF,
1 Series 74 TTL Load,
Input tr S 20 ns,
Input tf S 20 ns
0
40
0
TEST CONDITIONS
(SEE NOTES 4 AND 5)
0
ns
0
'27C/PC128-1
'27C/PC128-15
'27C/PC 128-2
'27C/PC128-20
'27C/PC128
'27C/PC128-25
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
ta(A)
Access time from address
150
200
250
ns
tatE)
Access time from chip enable
150
200
250
ns
ten(G)
Output enable time from G
75
75
100
ns
tdis
Output disable time from G
or E, whichever occurs firstt
60
ns
tv (A)
Output data valid time after
change of address, E, or G,
whichever occurs first t
CL = 100 pF,
1 Series 74 TTL Load,
Input tr S 20 ns,
Input tf S 20 ns
0
60
0
0
60
0
ns
0
0
t Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.
switching characteristics for programming:Vee = 6.5 V and Vpp = 13 V (SNAP! Pulse), TA = 25°C
(see Note 4)
MIN
PARAMETER
tdis(G)
Output disable time from G
ten(G)
Output enable time from G
NOM
0
MAX
UNIT
130
ns
150
ns
recommended timing requirements for programming: Vee = 6.5 V and Vpp =13 V (SNAP!
Pulse), TA = 25°C (see Note 4)
ISNAP! Pulse programming algorithm
MIN
NOM
MAX
95
100
105
UNIT
tw(IPGM)
Initial program pulse duration
tsu(A)
Address setup time
2
fls
tsu(E)
E setup time
2
fls
tsu(G)
G setup time
2
fls
tsu(D)
Data setup time
2
fls
tsu(VPP)
VPP setup time
2
flS
tsu(VCC)
VCC setup time
2
!As
th(A)
Address hold time
'0·
fls
th(D)
Data hold time
2
fls
fls
NOTES: 4. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high
and 0.8 V for logic low (reference page 7-10).
5. Common test conditions apply for tdis except during programming.
TEXAS
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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
REV A -
SMLS128D -
OCTOBER 1984 -
REVISED JANUARY 1991
PARAMETER MEASUREMENT INFORMATION
2.08 V
Output
Under Test
-J
.
T
RL=800Q
CL= 100 pF
Figure 2. AC Testing Output Load Circuit
AC testing input/output wave forms
2.4V----X~o.~~
_
0.4 V
. . ___
O.~~X
_ _- J
AC testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
read cycle timing
AO-A13
X
Addresses Valid
~
\
E
I
I
I
I
I
I
I
tv(A)
~~
TEXAS
POST OFFICE BOX 1443
•
l1li
Output Valid
-1!1
INSlRUMENTS
7-10
VIL
I
I
I
VIH
I~tdls~
I
I
HI-Z
VIL
}':
I
~ten(G)~
OQ1-0Q8
JA
VIH
I
I
~ta(E)~
\
G
X
I
I
~
ta(A)
vlH
HOUSTON, TEXAS 77001
~
VIL
I
~22»-
HI-Z - : : :
TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
REV A- SMLS128D -
OCTOBER 1984 -
REVISED JANUARY 1991
program cycle timing
'4~--- Verify~
IG~----
AO·A13
Program---... '
,
I
,
:
~~-------------A-d-dr-es-s-S~ta-b-le-------------~2<~_·
__A_~d_~_~_s___
I
~ tsu(A)
001·00a
Vpp
---~~
, I
~ th(Al ~
+'n
Stab',
f)---..J....---c~ o*ut
~tsu(O)
I
I
I
{:
I
I
I
I
~:
~ tsu(VPP)
~tdiS(G)t
.
{:
~:
:
I
I~
LI
~ tsu(VCC)
E~:
\;
I
I
I
Vpp
I
I
I
I
Vcc
I
I
:
i
I:
I
Vcc
f>----------
I
I
I
:
I
I
I
I
I
I
I
VCC;
VCC
::
I
t tdis(G) and ten(G) are characteristics of the device but must be accommodated by the programmer.
:\: 13-V Vpp and 6.S-V Vee for SNAP! Pulse programming.
TEXAS
-1!1.
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7-11
TMS27C128 131 072-81T UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-81T PROGRAMMABLE READ-ONLY MEMORY
REV A -
SMLS128D -
OCTOBER 1984 -
REVISED JANUARY 1991
device .symbolization
This data sheet is applicable to all TI TMS27C128 CMOS EPROMs and TMS27PC128 PROMs with the data
sheet revision code "Au as shown below.
0
TMS27PC128
.§.
TMS
27C128
Jr _x_.P 'f.Y '!!:f!-
_~ L_
Data Sheet Revis ion Code Front End Code
Die Revision Cod e
Back End Code
Year of Manufact ure
Week of Manufacture
TEXAS -1!1
INSTRUMENlS
7-12
.....
'-
TI FML
POST OFFICE BOX 1443
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~
2- iU 1.00
E
..
c: om Z
en -0.75
r--
I
TA -
25
50
75
Free·Air Temperature -
1.50
~
::l
4.5
°C
1.25
~i
::l N
CJ)
~
.~
E
-
0
:J
I
vs
SUPPLY VOLTAGE
C
I
~ 0.75
0.50
-75 -SO -25
TA -
1.50
~
:;
o
'",-
0
25
>-
1.25
~i
::l N
CJ)
CI)
75
Free·Air Temperature -
.~
---
............ ............
50
-
.-
iU 1.00
E
1:) ~
i-
0.75
r
..-V
o
o
0.50
4.25
4.5
°C
4.75
Vee -
U
I
1.50
I
~
1.25
..E
0
~ ~ 0.75
~
5.25
5
V
./
/"
5;5
5.75
Supply Voltage - V
vs
~
~ ~ 1.00
---
ACCESS TIME
CI)
~
~
SUPPLY VOLTAGE
til
V
N
100 125
Vee = 5 V
E
~
~
FREE·AIR TEMPERATURE
1=til 'C
5.75
I
I
vs
I
5.5
TA =25 °C
f=Max
ACCESS TIME
1.50
Supply Voltage -
FREE·AIR TEMPERATURE
" "'-"- -........
/V
ACTIVE SUPPLY CURRENT
N
8
5.25
vs
I
1.00
V
5
4.75
Vee -
Vee =5V
c;.
V
/'
0.50
4.25
o
100 125
/
ACTIVE SUPPLY CURRENT
C
/'
.0
'C
[)
0
I
1.25
~S
I
0.50
-75 -50 -25
I
TA = 25°C
~
[)
o
1.50
:;
o
"',-
"""
SUPPLY VOLTAGE
~
I
Vee = 5V
>1.25
Q.o.'C
::l
I
vs
-
FREE·AIR TEMPERATURE
V
~
.§
V"
t-til
I
I
TA =25 °C
CI)
1.25
'C
g~ ~m
........
1.00
~
E
~
-0.75
-
~ r---..-.
I~
~
0.50
-75 -50 -25
TA -
0
25
50
75
Free·Alr Temperature -
0.50
4.25
100 125
°C
4.5
"4.75
Vee -
TEXAS
5
5.25
Supply Voltage -
5.5
5.75
V
-If
INSlRUMENTS
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7·13
TMS27C128131 072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC128 131 072·BIT PROGRAMMABLE READ·ONLY MEMORY
REV A -
SMLS128D -
OCTOBER 1984 -
REVISED JANUARY 1991
TEXAS
~
INSlRuMENTS
7-14
POST OFFICE BOX 1443
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TMS27C256 262 144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC256 262 144-BIT PROGRAMMABLE READ-ONLY MEMORY
REV A -
SMLS256E - SEPTEMBER 1984 -
This Data Sheet is Applicable to All
TMS27C256s and TMS27PC256s
Symbolized with Code "B" as Described
on Page 7-25.
•
•
•
Organization .• : 32K x 8
•
•
All Inputs/Outputs Fully TIL Compatible
•
•
•
J and N Packages
(Top View)
Single 5-V Power Supply
Pin Compatible With Existing 256K MOS
ROMs, PROMs, and EPROMs
Max Access/Min Cycle Time
Vee ± 5%
Vee ± 10%
'27C/PC256-100
'27C/PC256-120
'27C/PC256-150
'27C/PC256-1
'27C/PC256-2
'27C/PC256
'27C/PC256-10
'27C/PC256-12
'27C/PC256-15
'27C/PC256-17
'27C/PC256-20
'27C/PC256-25
100 ns
120 ns
150 ns
170 ns
200 ns
250 ns
Vpp
1
28
VCC
A12
A?
A6
A5
A4
A3
A2
A1
AD
001
D02
003
2
27
3
26
A14
A13
AS
A9
A11
GND
4
25
5
24
6
23
G
7
8
21
A1D
9
E
10
DOS
DO?
D06
D05
D04
11
12
13
14
FM Package
(Top View)
Power Saving CMOS Technology
Very High-Speed SNAP! Pulse Programming
3-State Output Buffers
•
400-mV Minimum DC Noise Immunity With
Standard TIL Loads
•
Latchup Immunity of 250 mA on All Input
and Output Lines
•
REVISED JANUARY 1991
AS
A9
A11
A5
A4
A3
NC
G
A1D
Low Power Dissipation (Vee =5.5 V)
- Active ... 165 mW Worst Case
- Standby ... 1.4 mW Worst Case
(CMOS Input Levels)
AD
E
NC
DOS
DO?
D01
C\JC")O~~LOCO
OOzzOOO
•
PEP4 Version Available With 168 Hour
Burn-in, and Choices of Operating
Temperature Ranges
•
256K EPROM Available With MIL-STD-883C
Class B High Reliability Processing
(SMJ27C256)
000
000
PIN NOMENCLATURE
AO-A14
E
G
GND
NC
NU
DQ1-DQ8
description
The TMS27C256 series are 262 144-bit, ultraviolet-light erasable, electrically programmable
read-only memories.
VCC
VPP
Address Inputs
Chip Enable/Powerdown
Output Enable
Ground
No Internal Connection
Make No External Connection
Inputs (programming)/Outputs
5-V Power Supply
13 V Programming Power Supply
The TMS27PC256 series are 262 144-bit,
one-time, electrically programmable read-only
memories.
PROOUCTION OATA documents contain Information current
.. of publication data. Products conform to speCifications
per the terms of Texas Instruments slandard warranty.
Production processing does not necessarily Include testing
of.llparameters.
TEXAS
-II}
Copyright © 1991, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-15
TMS27C256 262 144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC256 262 144-BIT PROGRAMMABLE READ-ONLY MEMORY
REV A -
SMLS256E -
SEPTEMBER 1984 -
REVISED JANUARY 1991
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MaS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The data outputs are three-state for connecting multiple devices to a common bus. The TMS27C256 and the
TMS27PC256 are pin compatible with 28-pin 256K MOS ROMs, PROMs, and EPROMs.
The TMS27C256 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27PC256 OTP PROM is offered in a dual-in-Iine
plastic package (N suffix) designed for insertion in mounting hole rows on 15,2-mm (600-mil) centers. The
TMS27PC256 OTP PROM is also supplied in a 32-lead plastic leaded chip carrier package using 1,25-mm
(50-mil) lead spacing (FM suffix).
The TMS27C256 and TMS27PC256 are offered with two choices of temperature ranges of O°C to 70°C and
- 40°C to 85°C (TMS27C256-__JL and TMS27C256-__JE; TMS27PC256-__NL and TMS27PC256-__NE;
TMS27PC256-__ FML and TMS27PC256-__FME, respectively). The TMS27C256 and the TMS27PC256 are
also offered with 168-hour burn-in on both temperature ranges (TMS27C256-__JL4 and TMS27C256-__JE4;
TMS27PC256-__FML4 and TMS27PC256-__FME4, respectively); see table below.
All package styles conform to JEDEC standards.
EPROM
AND
OTP
PROM
SUFFIX FOR OPERATING
TEMPERATURE RANGES
WITHOUT PEP4 BURN·IN
SUFFIX FOR PEP4
168 HR. BURN-IN
VSTEMPERATURERANGES
O'CTO 70'C
- 40'C TO 85'C
O'CTO 70'C
TMS27C256-XXX
JL
JE
JL4
JE4
TMS27PC256-XXX
NL
NE
NL4
NE4
TMS27PC256-XXX
FML
FME
FML4
FME4
- 40'C TO 85'C
These EPROMs and OTP PROMs operate from a Single 5-V supply (in the read mode), thus are ideal for use
in microprocessor-based systems. One other 13-V supply is needed for programming. All programming signals
are TTL level. These devices are programmable by the SNAP! Pulse programming algorithm. The SNAP! Pulse
programming algorithm uses a Vpp of 13-V and a Vee of 6.5-V for a nominal programming time offour seconds.
For programming outside the system, existing EPROM programmers can be used. Locations may be
programmed singly, in blocks, or at random.
TEXAS ."
INSTRUMENTS
7-16
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS27C256 262 144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC256 262 144-B11 PROGRAMMABLE READ-ONLY MEMORY
REV A -
SMLS256E -
SEPTEMBER 1984 -
REVISED JANUARY 1991
operation
There are seven modes of operation listed in the following table. The read mode requires a single 5-V supply. All
inputs are TTL level exceptforVpp during programming (13-Vfor SNAP! Pulse) and 12-Von A9forsignature
mode.
MODE
FUNCTION
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE
MODE
VIL
E
VIL
VIL
VIH
VIL
VIH
VIH
G
VIL
VIH
xt
VIH
VIL
VIH
VIL
Vpp
Vee
Vee
Vee
Vpp
Vpp
Vpp
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
A9
x
X
·X
x
x
VH:j:
X
x
x
X
AD
x
x
X
VIL
Vee
I
VH:j:
I
VIH
eo DE
DQ1-DQ8
Data Out
HI-Z
Data Out
Data In
HI-Z
HI-Z
MFG
97
I
I
DEVleE
04
t X can be VIL or VIH.
:j: VH = 12 V ± 0.5 V.
read/output disable
When the outputs of two or more TMS27C256s or TMS27PC256s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs of
the other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All
other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these pins.
Output data is accessed at pins 001 through DOS.
latchup immunity
Latchup immunity on the TMS27C256 and TMS27PC256 is a minimum of 250 rnA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup
without compromising performance or packing density.
For more information see application report SMLA001, "Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family", available through TI Sales Offices.
power down
Active ICC supply current can be reduced from 30 mA to 500 flA (TTL-level inputs) or 250 ~ (CMOS-level inputs)
by applying a high TTL or CMOS signal to the E pin. In this mode all outputs are in the high-impedance state.
erasure (TMS27C256)
Before programming, the TMS27C256 EPROM is erased by exposing the chip through the transparent lid
to a high intensity ultraviolet light (wavelength 2537 A). EPROM erasure before programming is necessary
to assure that all bits are in the logic high state. Logic lows are programmed into the desired locations, A
programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose
(UV intensity x exposure time) is 15-W-s/cm 2, A typical 12-mW/cm2, filterless UV lamp will erase the device
in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. It should be noted
that normal ambient light contains the correct wavelength for erasure. Therefore, when using the
TMS27C256, the window should be covered with an opaque label.
TEXAS
"JI
INSlRUMENlS
POST OFFICE BOX 1443
-
HOUSTON, TEXAS 77001
7-17
TMS27C256 262 144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC256 262 144-BIT PROGRAMMABLE READ-ONLY MEMORY
REV A -
SMLS256E -
SEPTEMBER 1984 -
REVISED JANUARY 1991
initializing (TMS27PC256)
The one-time programmable TMS27PC256 PROM is provided with all bits in the logic high state, then logic lows
are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAP! Pulse programming
The 256K EPROM and OTP PROM are programmed using the TI SNAP! Pulse programming algorithm
illustrated by the flowchart in Figure 1, which programs in a nominal time of four seconds. Actual programming
time will vary as a function of the programmer used.
Data is presented in parallel (eight bits) on pins 001 to 008. Once addresses and data are stable, E is pulsed.
The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (lAs) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 1DO-lAs
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when Vpp = 13 V, Vee = 6.5 V, G.= VIH, and E = VIL. More than
one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified
with Vee = Vpp = 5 V.
program inhibit
Programming may be inhibited by maintaining a high level inputs on the
E and G pins.
program verify
Programmed bits may be verified with Vpp
= 13 V when G = VIL and E = VIH'
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This
is activated when A9 is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by AD; i.e., AD
accesses the manufacturer code, which is output on 001-008; AD = VIH accesses the device code,
is output on 001-008. All other addresses. must be held at VIL. Each byte possesses odd parity
008. The manufacturer code for these devices is 97, and the device code is 04.
TEXAS
lJ1
INSlRUMENlS
7-18
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
mode
= VIL
which
on bit
TMS27C256 262 144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC256 262 144-BIT PROGRAMMABLE READ-ONLY MEMORY
REV A -
SMLS256E -
SEPTEMBER 1964 -
REVISED J.A.NUARY 1991
Program
Mode
Interactive
Mode
Final
Verification
~
Figure 1. SNAP! Pulse Programming Flowchart
TEXAS
J!1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
7-19
TMS27C256 262144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC256 262144-BIT PROGRAMMABLE READ-ONLY MEMORY
REV A -
SMLS256E -
SEPTEMBER 1984 -
REVISED JANUARY 1991
logic symbol t
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11
A12
A13
A14
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
EPROM
32768 x 8
o\
_
A_O
32767
A'V
A'V
A'V
A'V
A'V
A'V
A'V
A'V
11
12
13
15
16
17
18
19
OQ1
OQ2
OQ3
OQ4
OQ5
OQ6
OQ7
OQ8
141
20
- I
'"
Lb,.
22
E 20
[PWR OWN]
&
G
EN
22
OTP PROM
32768 x 8
o,
AO 10
A1 9
A2 8
7
A3
6
A4
AS 5
4
A6
A7 3
A8 25
24
A9
A10 21
A11 23
A12 2
A13 26
A14 27
A_O
_
32767
A'V
A'V
A'V
A'V
A'V
A'V
A'V
A'V
11
12
13
15
16
17
18
19
OQ1
OQ2
OQ3
OQ4
OQ5
OQ6
OQ7
OQ8
14
-Lb.
'"
[PWR OWN]
I
i-----.
&
EN
t These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for J and N packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted):t:
Supply voltage range, Vee (see Note 1) .............................................. - 0.6 V to 7 V
Supply voltage range, Vpp ......................................................... - 0.6 V to 14 V
Input voltage range (see Note 1): All inputs except A9 ................................ - 0.6 V to 6.5 V
A9 ............................................... - 0.6 V to 13.5 V
Output voltage range (see Note 1) ............................................. - 0.6 V to Vee + 1 V
Operating free-air temperature range ('27C256-__JL and JL4, '27PC256-__NL, NL4, FML,
and FML4) ....................................... 0° C to 70°C
Operating free-air temperature range ('27C256-__JE and JE4, '27PC256-__NE, NE4, FME,
and FME4) .................................... - 40° C to 85°C
Storage temperature range ....... ; ............. ~ ................................. - 65°C to 150°C
*Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
. functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
TEXAS
lJ1
INSlRUMENTS
7-20
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS27C256 262 144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC256 262 144-BIT PROGRAMMABLE READ-ONLY MEMORY
REV A -
SMLS256E - SEPTEMBER 1984 -
REVISED JANUARY 1991
recommended operating conditions
TMS27C/PC256-100
TMS27C/PC256-120
TMS27C/PC256-150
TMS27C/PC256-1
TMS27C/PC256-2
TMS27C/PC256
VCC
Vpp
Supply voltage
Supply voltage
MIN
NOM
MAX
MIN
NOM
4.75
5
5.25
4.5
5
5.5
SNAPI Pulse programming algorithm
6.25
6.5
6.75
6.25
6.5
6.75
VCC+0.6
VCC- 0.6
13.25
12.75
Read mode (see Note 3)
VCC-0.6
High-level input voltage
Low-level input voltage
13
12.75
TIL
2
CMOS
VIL
UNIT
Read mode (see Note 2)
SNAP! Pulse programming algorithm
VIH
TMS27C/PC256-10
TMS27C/PC256-12
TMS27C/PC256-15
TMS27C/PC256-17
TMS27C/PC256-20
TMS27C/PC256-25
VCC+1
VCC -0.2
VCC+1
MAX
VCC+0.6
13
2
V
VCC+1
VCC - 0.2
V
13.25
V
VCC+1
TIL
-0.5
0.8
-0.5
0.8
CMOS
-0.5
0.2
-0.5
0.2
V
TA
Operating free-air
temperature
'27C256- JL, JL4
'27 PC 256-':::-_NL, NL4,
FML, FML4
0
70
0
70
°C
TA
Operating free-air
temperature
'27C256-__JE, JE4
'27PC256-__ NE, NE4,
FME, FME4
-40
85
-40
85
°C
NOTES: 2. VCC must be applied before or atthe same time as Vpp and removed after or at the same time as Vpp. The device must not be inserted
into or removed from the board when Vpp or VCC is applied.
3. Vpp can be connected to Vce directly (except in the program mode). VCC supply current in this case would be ICC + Ipp.
electrical characteristics over full ranges of operating conditions
TEST CONDITIONS
PARAMETER
VOH
10H =-2.5 mA
High-level output voltage
10H = - 20!lA
VOL
Low-level output voltage
MIN
TYpt
MAX
3.5
UNIT
V
VCC- 0 .1
10L= 2.1 mA
0.4
IOL = 20 fAA
0.1
V
II
Input current (leakage)
VI = Oto 5.5 V
±1
fAA
10
Output current (leakage)
Vo = OtoVCC
±1
fAA
IpP1
Vpp supply current
Vpp = VCC = 5.5 V
1
10
IpP2
Vpp supply current (during program pulse)
Vpp = 13 V
35
50
fAA
mA
VCC supply current (standby)
VCC = 5.5 V, E = VIH
250
500
ICC1
VCC = 5.5 V, E = VCC
100
250
ICC2
VCC supply current (active).
15
30
I TIL-input level
I CMOS-input level
VCC = 5.5 V, E = VIL,
tcycl e = minimum cycle time,
outputs open
fAA
mA
tTypical values are at T A = 25°C and nominal voltages.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHzt:
PARAMETER
TEST CONDITIONS
MIN
TYpt
MAX
UNIT
Cj
Input capacitance
VI = 0, f = 1 MHz
6
10
pF
Co
Output capacitance
Vo = 0, f = 1 MHz
10
14
pF
tTypical values are at TA = 25°C and nominal voltages.
*Capacitance measurements are made on a sample basis only.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-21
TMS27C256 262144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC256 262 144·BIT PROGRAMMABLE READ·ONLY MEMORY
REV A -
SMLS256E -
SEPTEMBER 1984 -
REVISED JANUARY 1991
switching characteristics over full ranges of recommended operating conditions (see Notes 4
and 5)
TEST CONDITIONS
(see Notes 4 and 5)
PARAMETER
ta(A)
Access time from address
ta(E)
Access time from chip enable
ten(G)
Output enable time from G
tdis
Output disable time from G or E,
whichever occurs firstt
tv(A)
Output data valid time after change of
address, E, or G, whichever occurs firstt
'27C256-100
'27PC256-100
'27C256-10
'27PC256-10
'27C256-120
'27PC256-120
'27C256-12
'27PC256-12
'27C256-150
'27PC256-150
'27C256-15
'27PC256-15
MIN
MIN
MIN
CL = 100 pF,
1 Series 74 TTL Load,
Input tr S 20 ns,
Input tf S 20 ns
MAX
120
150
100
120
150
ns
55
55
75
ns
60
ns
45
0
45
0
0
'27C256-1
'27PC256-1
'27C256-17
'27PC256-17
MIN
MAX
100
0
TEST CONDITIONS
(see Notes 4 and 5)
PARAMETER
0
MAX
UNIT
MAX
ns
0
'27C256-2
'27PC256-2
'27C256-20
'27PC256-20
MIN
MAX
'27C256
'27PC256
'27C256-25
'27PC256-25
MIN
ns
UNIT
MAX
ta(A)
Access time from address
170
200
250
ta(E)
Access time from chip enable
170
200
250
ns
ten (G)
Output enable time from G
75
75
100
ns
tdis
Output disable time from G or E,
whichever occurs firstt
60
ns
tv (A)
Output data valid time after change of
address, E, or G, whichever occurs firstt
CL = 100 pF,
1 Series 74 TTL Load,
Input tr S 20 ns,
Input tf S 20 ns
0
60
0
0
60
0
0
ns
ns
0
tValue calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.
switching characteristics for programming: Vee = 6.50 V and Vpp = 13 V (SNAP! Pulse), T A = 25°C
.
(see Note 4)
PARAMETER
tdis(G)
MIN
Output disable time from G
0
NOM
MAX
UNIT
130
ns
Output enable time from G
150
ns
ten(G)
NOTES: 4. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8
V for logic low). (Reference page 7-23.)
5 .• Common test conditions apply for the tdis except during programming.
TEXAS ~
INSTRUMENTS
7-22
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS27C256 262 144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC256 262 144-BIT PROGRAMMABLE READ-ONLY MEMORY
REV A -
SMLS256E - SEPTEMBER 1984 -
REVISED JANUARY 1991
recommended timing requirements for programming: VCC = 6.5 V and Vpp = 13 V,
TA = 25°C (see Note 4)
tw(lPGM)
Initial program pulse duration
tsu(A)
Address setup time
tsu(G)
tsu(E)
MIN
NOM
MAX
95
100
105
UNIT
I-ls
2
I-ls
G setup time
2
I-ls
E setup time
2
I-ls
tsu(D)
Data setup time
2
!!s
tsu(VPP)
Vpp setup time
2
I-lS
tsu(VCC)
VCC setup time
2
!!S
th(A)
Address hold time
0
I-lS
Data hold time
2
I-ls
thlDl
NOTE 4:
For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8
V for logic low). (Reference page 7-23.)
PARAMETER MEASUREMENT INFORMATION
2.08V
Output
Under Test
-1
T
RL=800Q
CL=100pF
Figure 2. AC Testing Output Load Circuit
AC testing input/output wave forms
2.4V----v.
O.4V
O.! ~
____-'1\- ~.~ v
X'-____
A.C. testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
INSTRUMENTS
TEXAS "'"
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
7-23
TMS27C256 262 144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC256 262 144·BIT PROGRAMMABLE READ·ONLY MEMORY
REV A - SMLS256E - SEPTEMBER 1984 -
REVISED JANUARY 1991
read cycle timing
AO-A14
~
_
VI- - - - - - - 1\
Addresses Valid
~-------------~I
VIH
' - - - - - - - - - - VIL
I
-------:
:
:!
I
\~-------------':r.,.:
i
~ta(E)~
---+-i-----\
:
,y[j,-o--------
:
k- ten (G) -.l
,
,
I
141~1--- ta(A)
DQ1-DQB
tv (A)
~I
-HI-Z----<~
II~
:.-.,
tdls
~
VIH
VIL
I
VOH
OutputV.lld
»»»>>-Ht.ZVOL
program cycle timing (SNAP! Pulse programming)
Program-----..~II_-~
~~
1l1li
1
v:
~~
AO-A14 _ _ _ _
"I
~.
;
:--X Ad~!~SS
_________
A_dd_re_s_s_S'I""ta-b-le------__
I
~
I
I+-- th(A) ~
' _ - _.....I-~I
I+- tsu(A)
----«
VIL
,
1
DQ1-DQB
VIH
"'",-""'l,------,
Data In Stable
: } - - HI-Z
~tSU(D)
+-{:
"
'I
,
VIH/VOH
Data Out Valid ) .....- - - - -
I
I
tdls(G)t~
VIL/VOH
1
I
"
I
t--~,----------~,---------I~--·I------I~---------VpP*
VPP
--f!'
I
,
1
,
,
I
I
'
,
~ tsu(E)
i
~ tsu(VPP)
'I
I
' I '
'I
I
'I
I
VCC
;f.,.-~I~----~I------+'-~i------+I------------VCC*
VCC
E
--f!"
tIIII"-* tsu(VCC)
f---i....: -
1OIIII1
..
th(D)
'I
'I
::
I
I
:
'I
I
}l
-------..1.{.'L/~--.,.....-------+i
..
i
VCC
--.-ti--t-en-(G-)-t+!- - - - - - - - - - - - - VIH
I
tw(IPGM) ~
I
I'I1II-
~ tsu(G) -+I
I
,
I
VIL
I
,
-----------------------~I~
/
I~-------VIH
VIL
t tdis(G) and ten (G) are characteristics of the device but must be accomodated by the programmer.
:\: 13-V Vpp and 6.S-V Vee for SNAP! Pulse programming.
TEXAS
~
INSTRUMENTS
7-24
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS27C256 262 144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC256 262 144-BIT PROGRAMMABLE READ-ONLY MEMORY
REV A -
SMLS256E -
SEPTEMBER 1984 -
REVISED JANUARY 1991
device symbolization
This data sheet is applicable to all TI TMS27C256 CMOS EPROMs and TMS27PC256 CMOS OTP PROMs
with the data sheet revision code "S" as shown below.
0
B _L
~?
........
r---....
TI FML
TMS27PC256
TMS
27C256
YV'!:!:!i
_B
Data Sheet Rev ision Code
Front End Code
Die Revision Co de
8ackend Code
Year of Manufacture
Week of Manufacture
~ ~ p
~
YV'!:!:!i
Data Sheet Rev ision Code
Front End Code
Die Revision Code
Backend Code
Year of Manufacture
Week of Manufacture
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-25
TMS27C256 262144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC256 262144-BIT PROGRAMMABLE READ-ONLY MEMORY
REV A -
SMLS256E -
SEPTEMBER 1984 -
REVISED JANUARY 1991
TYPICAL TMS27C/PC256 CHARACTERISTICS
STANDBY SUPPLY CURRENT
STANDBY SUPPLY CURRENT
vs
C
f!
1.50
:5
(J
>1.25
c."C
I
I
...........
Q)
~ ~ 1.00
:§ E
c::
I
TA
-a _ 1.25
i'--..~
.............
~
r--..
c::
~
CIS
en
/':
/~
TA -
0.50
4.25
(J
25
50
75
100 125
Free-Air Temperature -
4.5
°C
1.50
!!:!
:;
c;
1.25
en
N
~
.t)~ E
0
vs
SUPPLY VOLTAGE
=5 V
1.50
~
>-
1.25
::I
.............
"""""-- r---
I
N
0.50
-75 -50 -25
TA -
0
25
50
75
Free-Air Temperature -
I
l"-
1.00
t)~
iN
(J
(J
0.75
,
II)
4.5
4.75
Vee -
1.50
=5V
l/
V
./
~
0.50
-75 -50 -25
TA -
/
~
V
E
i=:c
II)
0
25
50
1.25
Q)
~ .!::!
() co
""
I
TA
Q)
=25°C
........
~
1.00
5.5
5.75
V
I
-
~
:J. E
I~
t5 - 0.75
75
Free-Air Temperature -
0.50
4.25
100 125
°C
4.5
4.75
Vee -
TEXAS •
INSlRUMENTS
7-26
Supply Voltage -
vs
:J. E
~
5.25
SUPPLY VOLTAGE
8 ~ 1.00
(5
- ~ 1.00
.0 E
"C
...
I
0.50
-75 -50 -25
I
=25°C
~ .~
ti5 ~ 0.75
I
(J
1.50
:5
(J
0
u
SUPPLY VOLTAGE
c
e
Vee =5V
'i"oo..
c.._
:l
vs
FREE-AIR TEMPERATURE
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5
5.25
Supply Voltage -
5.5
V
. 5.75
TMS29F256, TMS29F258, TMS29F259
262 144·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORIES
REV A -
• Organization 32K x 8
SMJS256C -
TMS29F258 ... N Package
TMS29F258 ... J Package
(Top View)
(Top View)
• HVCMOS Technology
A12
• All Inputs/Outputs TTL Compatible
• Max Access/Min Cycle Time
'29F256/8/9-170
'29F256/8/9-200
'29F256/8/9-250
'29F256/8/9-300
Vee ± 10%
VCC
VCC
A14
A13
A8
A9
A11
W
A5
A4
A3
A2
A1
AO
DOO
D01
D02
G
170 ns
200 ns
250 ns
300 ns
'29F256/8/9-20
'29F256/8/9-25
'29F256/8/9-30
A10
E
DO?
D06
D05
D04
D03
D01
D02
• Self-Timed Erasure of the Entire Memory
Before any Reprogramming (15 ms MAX)
VSS
• Single Byte and Page (64 Bytes) Program:
- Latched Address and Data
- Self-Timed Programming Operation
(15 ms MAX)
- Data Polling Verification
A13
A8
A9
A11
G
A10
9
VSS
E
DO?
D06
D05
D04
D03
TMS29F259 ... N Package
TMS29F259 ... J Package
(Top View)
• 100, 1000, and 10000 Cycles Endurance
Versions
VCC
W
• Software Inadvertent Write Protection
NC
A12
A?
A6
• Software Erase Mode Entry
• TMS29F256 Pinout Compatible With
EPROM JEDEC Standard
A4
A3
A2
A1
AO
DOO
D01
D02
• TMS29F258 Pinout Compatible With
EEPROM JEDEC Standard
• Choice of Operating Temperature Ranges
description
The TMS29F256, TMS29F258, and TMS29F259 are
262 144-bit, programmable read-only memories that
can be electrically bulk-erased and reprogrammed.
These devices are fabricated using HVCMOS flotox
technology for high reliability and very low power
dissipation. They perform the erase/program
operations automatically with a single 5-V supply,
and they can program a single byte or any number of
bytes between 1 and 64.
VSS
6
A14
A13
A8
A9
A11
G
A10
E
DO?
D06
D05
D04
D03
PIN NOMENCLATURE
AO-A14
E
G
NC
The TMS29F256, TMS29F258, and TMS29F259
Flash EEPROMs are offered in a dual-in-line ceramic
package (J suffix) designed for insertion in
mounting-hole rows on 15,2-mm (600-mil) centers.
The TMS29F256, TMS29F258, and TMS29F259 in
PRODUCTION DATA documenls conlaln information current
IS of publication dale. Products conform to specifications
per the terms of Texas Instrumenls standard warranty.
Production processing does not necessarily Include testing
of III parlmelers.
REVISED JANUARY 1991
TMS29F256 ... N Package
TMS29F256 ... J Package
• Single 5-V Power Supply
Vee±5%
MARCH 1989 -
W
DOO-DQ7
VCC
VSS
TEXAS
~
Address Inputs
Chip Enable
Output Enable
No Internal Connection
Write Enable
Data In/Data Out
5-V Power Supply
Ground
Copyright © 1991, Texas Instruments Incorporated
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-27
TMS29F256, TMS29F258, TMS29F259
262144-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
REV A -
SMJS256C -
MARCH 1989 -
REVISED JANUARY 1991
the ceramic package are each offered with three guaranteed temperature ranges of O°C to 70°C, - 40°C to
85°C, and - 40°C to 125°C (TMS29F256-__JL, TMS29F258-__JL, and TMS29F259-__JL for O°C to 70°C;
TMS29F256-__JE, TMS29F258-__JE, and TMS29F259-__JE for - 40°C to 85°C; and TMS29F256-__JQ,
TMS29F258-__JQ, and TMS29F259-__JQ for - 40°C to 125°C).
4
TMS29F256
FM PACKAGE
TMS29F258
FM PACKAGE
TMS29F259
FM PACKAGE
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
3
2
1 32 31 30
29
0
28
27
4
A8
A9
3 2 1 3231 30
29
0
28
A11
A8
4
3 2 1 32 31 30
o
29
A14
A9
28
A13
27
A11
27
A8
8
NC
8
26
NC
8
26
A9
9
G
9
25
G
9
25
A11
24
A10
10
24
A10
10
24
G
23
E
D07
DOS
23
E
D07
DOS
10
22
12
21
13
14 15 16 17 18 19 20
,...
(\J
(J) ( )
C')
"1"
to
gg~zggg
22
12
21
13
14 15 16 17 18 19 20
,...
(\J
(J) ( )
(t)
"1"
12
23
A10
22
E
13
21
14 15 16 17 18 19 20
D07
to
gg~zggg
The TMS29F256, TMS29F258, and TMS29F259 are also offered with 168 hour burn-in temperature ranges
(TMS29F256-__ JL4, JE4, and JQ4; TM,S29F258-__ JL4, JE4, and JQ4; TMS29F259-__ JL4, JE4, and JQ4,
respectively). (See table on page 7-29.)
The TMS29F256, TMS29F258, and TMS29F259 are also offered in a dual-in-line plastic package (N suffix)
designed for insertion in mounting-hole rows on 15,2-mm (600-mil) centers. The TMS29F256, TMS29F258, and
TMS29F259 are offered in a 32-lead plastic leaded chip carrier package using 1,25-mm (50-mil) lead spacing
(FM suffix). These packages are guaranteed from O°C to 70°C (NL or FML suffix).
The TMS29F256, TMS29F258, and TMS29F259 are organized as 32K x 8 bits. They feature internal circuitry
to minimize the external hardware interface that provides latched address and data, self-timed programming,
and data polling verification. In the erased state all bits are at a logic high. To reprogram, all memory bits are
erased first, then those bits that should be logic lows are programmed accordingly. During programming, the
data polling function is enabled, causing the memory to respond with the last data read except that the most
significant bit is inverted to inform the host microprocessor that the memory is busy until the programming is
completed.
The TMS29F256, TMS29F258, and TMS29F259 are available in 100 cycle endurance versions and will be
available in 1000 and 10 000 cycle endurance versions.
TEXAS •
INSlRUMENTS
7·28
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TMS29F256, TMS29F258, TMS29F259
262 144-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
REV A -
SMJS256C -
MARCH 1989 -
REVISED JANUARY 1991
MODE
FUNCTION
(PINS)
Read
E
(20)§
Output Disable
Standby and
Write Inhibit
Write
Signature Mode
VIL
VIL
VIH
VIL
VIL
G
(22)§
VIL
VIH
xt
VIH
VIL
AO
(10)§
X
X
X
X
A9
(24)§
X
X
X
X
VIH
VIH
X
VIL
W
(1)§
DOO-DO?
(11-13,15-19)§
VIL
VH l
VIH
MFG
Data Out
HI-Z
Data In
HI-Z
VIH
I
9?
I
I
DEVICE
F1
t X = Don't care for V < VCC.
t 12.5 V < VH < 15 V.
§ TMS29F256 J and N package pins.
operation
read/output disable
When the outputs of two or more TMS29F256s, TMS29F258s, and TMS29F259s are connected in parallel on
the same bus, the output of any particular device in the circuit can be read with no interference from the
competing outputs of the other devices.
To read the output of the TMS29F256, TMS29F258, or TMS29F259 a low-level signal is applied to the E and
G pins. All other devices in the circuit should have their outputs disabled by applying a high-level signal to one
of these pins.
power down
Active ICC current can be reduced from 20 rnA to 2 mA typically, by applying a high TTL signal to the E pin. In
this mode all the outputs are in the high-impedance state.
single-byte program
The single-byte program initiates with Vii low and G high applied to a selected device. The addresses on the
address pins will be latched on the falling edge of E or W, whichever comes first. Figure 1 illustrates the
single-byte programming flow.
After the latching operations are completed, the device starts automatically programming the data in the
addressed location within the memory array. This internal programming operation is completed in 15 ms
maximum.
SUFFIX FOR PEP4
168 HR. BURN·IN
vs TEMPERATURE RANGES
SUFFIX FOR OPERATING
TEMPERATURE RANGES
WITHOUT PEP4 BURN·IN
FLASH
EEPROM
O°C to 70°C
- 4QoC to 85°C
- 40°C to 125°C
QOC to 70°C
- 40°C to 85°C
- 4QoC to 125°C
TMS29F256-xxx
JL,NL,FML
JE
JQ
JL4
JE4
JQ4
TMS29F258-xxx
JL,NL,FML
JE
JQ
JL4
JE4
JQ4
TMS29F259-xxx
JL,NL,FML
JE
JQ
JL4
JE4
JQ4
TEXAS
~
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
7-29
TMS29F256, TMS29F258, TMS29F259
262 144·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORIES
REV A -
SMJS256C -
MARCH 1989 -
REVISED JANUARY 1991
Programming
Mode
. (see Note 2)
.--___
~=~-.....,
(see Note 1)
Interactive
Mode
(see Note 2)
Sequence pgm Verity Cmds
Final
Verification
_________1
NOTES: 1. Upon the three-step sequence completion, the device is latched into programming mode. The byte is latched and the byte programming
operation starts if a subsequent rising edge of iN is not detected within 100 fis.
2. Similar to the page programming mode.
Figure 1. Single-byte Programming Flowchart
TEXAS .J.!I
INSlRUMENlS
7-30
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS29F256, TMS29F258, TMS29F259
262 144-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
REV A -
SMJS256C -
MARCH 1989 -
REVISED JANUARY 1991
automatic page program
The page mode of the '29F256, '29F258, and '29F259 allow the user to program 2 to 64 bytes at a time. These
bytes are initially loaded in the internal device register and then automatically stored in the addressed memory
locations within the memory array. The internal programming operation is completed in 15 ms maximum,
regardless of the number of bytes (64 maximum) loaded. During the page loading, the page address (A6 to A 14)
must be the same as the initial page address. Figure 2 illustrates the automatic page programming flow.
The page mode operation initiates in the same way as the single byte mode: After the first byte has been loaded,
the '29F256, '29F258, and '29F259 can be loaded with 1 to 63 additional bytes. Each byte load cycle starts with
the falling edge ofW, or E, whichever comes last. A successive byte must be loaded within 100 [ls from the rising
edge of the previous byte load cycle. If a subsequent rising edge of Wis not detected within 100 [ls, the internal
programming operation starts automatically and subsequent attempts to load additional bytes are ignored until
the operation is completed.
Note that both the single byte and the automatic page programs can be entered after a proper "dummy"
sequence of bytes has been loaded (see inadvertent write protection).
TEXAS .JJ1
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
7-31
TMS29F256, TMS29F258, TMS29F259
262 144-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
REV A -
SMJS256C -
MARCH 1989 -
REVISED JANUARY 1991
Programming
Mode
Exit Se uence P m Veri
Cmds
Interactive
Mode
Final
Verify
Mode
________,1_
NOTES: 3. Upon the three-step sequence completion, the device is latched into programming mode. From 2 up to 64 bytes are latched at a rate
of 1 I-ls up to 100 I-ls per byte.
4. Upon the three-step sequence completion, the device is latched into the program verify mode. All the bytes are read with a sense
voltage of: (internal Vsense volt) + (program margin voltage).
5. Upon the three-step sequence completion, the device exits the program verify mode and returns to the page write setup.
Figure 2. Page Programming F.lowchart -
Entire Memory Algorithm
TEXAS "J1
INSlRUMENTS
7-32
POST OFFiCE BOX 1443
•
HOUSTON, TEXAS 77001
TMS29F256, TMS29F258, TMS29F259
262 144·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORIES
REV A -
SMJS256C -
MARCH 1989 -
REVISED JANUARY 1991
data polling
During a programming operation, the data polling software function is enabled to notify the host microcomputer
that the memory is busy with programming and ignores any command until the programming operation is
completed. If an attempt to read any byte occurs during the programming cycle, the device answers with the
last loaded byte, but with the inverted logical value of DQ7. (See page 7-44 for data polling timing diagram.)
flash erase mode
The flash erase operation can be activated via software by loading a dummy sequence of data/address strings.
The timing characteristics of this sequence are the same as those used for the page mode. The device detects
this particular sequence and automatically starts the self-timed erase. If the sequence load cycle is longer than
100 fis, the device ignores it. This sequence should not be used in the actual software program to prevent
inadvertent flash erase operations.
The specified dummy sequence to initiate the flash erase mode is:
STEP
1
2
3
4
5
6
MODE
Access
Access
Access
Access
Access
Access
A14-AO
Write
Write
Write
Write
Write
Write
D07-DOO
5555
AA
2AAA
55
5555
5555
80
AA
2AAA
55
5555
10
The self-timed flash erase mode starts automatically.
TEXAS
-IJ1
INSTRUMENlS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
7-33
TMS29F256, TMS29F258, TMS29F259
262 144-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
REV A -
SMJS256C -
MARCH 1989 -
REVISED JANUARY 1991
Programming
Mode
Interacllve
Mode
Final
Verily
___ ~L
NOTES: 3. Upon the three-step sequence completion, the device is latched into programming mode. From 2 up to 64 bytes are latched at a rate
of 1 fls up to 100 fls per byte.
4. Upon the three-step sequence completion, the device is latched into the program verify mode. All the bytes are read with a sense
voltage of: (internal Vsense volt) + (program margin voltage).
5. Upon the three-step sequence completion, the device exits the program verify mode and returns to the page write setup.
Figure 3. Page Programming Flowchart -
Standard Algorithm
TEXAS • .
INSlRUMENlS
7-34
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS29F256, TMS29F258, TMS29F259
262 144-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
REV A -
Count
SMJS256C -
MARCH 1989 -
REVISED JANUARY 1991
=Count + 1
Erase Failed
NOTES: 6. The bulk-erase operation starts automatically once the six-step sequence is completed.
7. The device is latched into the Erase Verify mode once the three-step sequence is completed. All bytes are read with a sense voltage
of: (internal Vsense voltage) - (erase margin voltage).
8. Upon the three-step sequence completion, the device is de-latched and returns to Flash operating setup.
Figure 4. Flash Erase Flowchart
----------------------------------------------------------------------------------------
TEXAS ~
INSlRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-35
TMS29F256, TMS29F258, TMS29F259
262144-81T FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
REV A -
SMJS256C -
MARCH 1989 -
REVISED JANUARY 1991
signature mode
The signature mode provides access to two bytes contained in a spare row. One byte designates the
manufacturer, the other byte designates the device code. The signature mode can be entered through either
a hardware or a software operation.
The hardware entry mode is specified in the mode table in the description section. Setting the device in the read
mode and applying VH on pin A9 produces the manufacturer byte code at the I/O pins if AO = VIL' or the device
identifier byte code if AO = VIH. The information provided by these two bytes helps the programmer select the
proper programming algorithm.
The signature mode software entry sequence is specified as follows:
STEP
MODE
A14-AO
D07-DOO
1
2
Access Write
Access Write
Access Write
5555
2AAA
5555
AA
55
3
90
exit mode
The software exit sequence for any mode is specified as follows:
STEP
MODE
A14-AO
D07-DOO
1
2
3
Access Write
Access Write
Access Write
5555
2AAA
5555
AA
55
FO
program verify mode
The program verify mode allows the programmer to verify the adequacy of the programming.
STEP
MODE
A14-AO
D07-DOO
1
2
3
Access Write
Access Write
Access Write
5555
2AAA
5555
AA
55
BO
Upon completion of the three-step sequence, the device is latched into the program verify mode. All the bytes
are read with a sense voltage of:
(internal Vsense voltage) + (program margin voltage)
The three access write (steps 1-3) are used only to enable the program verify mode: no data will actually be
written to the device.
The software exit sequence must be applied to exit this program verify mode.
erase verify mode
The erase verify mode allows the programmer to verify the extent of erasure.
The device provides the following software sequence to access the erase verify mode:
STEP
MODE
A14-AO
D07-DOO
1
2
3
Access Write
Access Write
Access Write
5555
2AAA
5555
AA
55
DO
Upon completion of the three-step sequence, the device is latched into erase verify mode. All the bytes are read
with a sense voltage of:
(internal Vsense voltage) - (erase margin voltage)
The software exit sequence must be applied to exit this program verify mode.
TEXAS •
INSlRUMENTS
7-36
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TMS29F256, TMS29F258, TMS29F259
262 144·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORIES
REV A -
SMJS256C -
MARCH 1989 -
REVISED JANUARY 1991
Inadvertent write protection
The device is protected against write commands during power-up and power down. The protection is released
only if Vee is higher than 3 V. Moreover, the device provides a hardware and a software protection against
inadvertent write commands that may occur even with a stable Vee.
The hardware protection consists of noise immunity to a pulse on W shorter than 20 ns, which is unable to start
a program cycle, and of a logic inhibit that prevents starting the program cycle unless the conditions of W low,
E low, and G high are satisfied simultaneously.
The software protection is such that no program operation is enabled unless preceded by a sequence of three
dummy write operations. Should the specified sequence not be loaded before any program operation or the
sequence load cycle is longer than 100 f.!s, the device ignores the program commands.
The inadvertent write protection software sequence is specified as follows:
STEP
MODE
1
Access Write
Access Write
Access Write .
Page Program
2
3
4
5555
AO 10
E
G
Vi
DOO
D01
D02
D03
D04
D05
D06
D07
9
8
7
6
5
4
3
25
24
21
23
2
26
27
20
22
1
0
~
11
12
13
15
16
17
18
19 ~
4-
AO
5555
page address +
1st byte address
up to the 64th
1st data up to the 64th
FLASH
EEPROM 32 768 x 8
>
,....
,....
AA
55
2AAA
logic symbol t
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
DQ7-DQO
A14-AO
A _O_
32767
14
G1
G2
1,2 EN (READ)
...,1C3 (WRITE)
r
AZ4
AD3
'174
t This symbol is in accordance with ANSI/EEE Std 91-1984 and IEC Publication 617-12.
The pin numbers shown are for the TMS29F256 J and N packages.
TEXAS . .
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-37
TMS29F256, TMS29F258, TMS29F259
262 144-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
REV A -
SMJS256C -
MARCH 1989 -
REVISED JANUARY 1991
functional block diagram
AO
A1
A2
A3
A4
AS
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11
A12
A13
A14
Add
Latch
262,144 Bit
Flash
EEPROM
Array
Row
Decoder
I/O
Buffers
000
001
002
003
004
DOS
006
007
E - - - ' - - 1 Control Logic
G
Timing
W
Programming
High Voltage Generator
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 9) .............................................. - 0.6 V to 7 V
Input voltage range: All except G and A9 ........................................... - 0.6 V to 6.5 V
G and A9 ....................................................... 0.6 V to 15 V
Output voltage (see Note 9) ................................................ - 0.6 V to Vee + 0.6 V
Operating free-air temperature range ('29F256-__ JL, JL4, NL. and FML;
'29F258-__ JL. JL4, NL. and FML; '29F259-__ JL. JL4, NL, and FML) ............... ooe to 70°C
Operating free-air temperature range ('29F256-__ JE and JE4;
'29F258-__ JE and JE4; '29F259-__ JE and JE4) .............................. - 40°C to 85°C
Operating free-air temperature range (,29F256-__ JO and J04;
'29F258-__ JO and J04; '29F259-__ JO and J04) ............................ - 40°C to 125°C
Storage temperature range ...................................................... - 65°C to 125°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. and
functional operation ofthe device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 9: Ail voltage values are with respect to the most negative supply voltage VSS (substrate).
TEXAS ~
INSlRUMENTS
7-38
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS29F256, TMS29F258, TMS29F259
262 144-81T FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
REV A -
SMJS256C -
MARCH 1989 -
REVISED JANUARY 1991
recommended operating conditions
VCC
Supply voltage
'29F256·170
'29F258·170
'29F259·170
'29F256·250
'29F258·250
'29F259·250
'29F256·20
'29F258·20
'29F259·20
'29F256·200
'29F258·200
'29F259·200
'29F256·300
'29F258·300
'29F259·300
'29F256·25
'29F258·25
'29F259·25
High-level input voltagt
NOM
MAX
MIN
NOM
4.75
5
5.25
4.5
5
VCC+1
2
VIL
Low-level input voltage
2
CMOS
VCC-0.2
TTL
-0.5
CMOS
-0.5
TA
Operating free-air
temperature
'29F256-__JL,JL4,NL,FML
'29F258-__ JL,JL4,NL,FML
'29F259-__JL,JL4,NL,FML
TA
Operating free-air
temperature
TA
Operating free-air
temperature
UNIT
MIN
TTL
VIH
'29F256·30
'29F258·30
'29F259·30
VCC+1
0.8
GND+O.2
MAX
5.5
V·
VCC+1
VCC- 0.2
V
VCC+1
-0.5
0.8
-0.5
GND+0.2
V
0
70
0
70
DC
'29F256-__JE,JE4
'29F258-__JE,JE4
'29F259- __JE,JE4'
-40
85
-40
85
DC
'29F256-__JO,J04
'29F258-__JO,J04
'29F259- JO,J04
-40
125
-40
125
DC
electrical characteristics over full range of operating conditions
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = - 400 !tA
VOL
Low-level output voltage
10L= 2.1 rnA
II
10
ICC1
Input current (leakage)
IAll except A9
IA9
Output current (leakage)
VCC supply current (standby)
MIN
TYpt
VI = Oto 5.5 V
±1
VI = Oto 15 V
±50
VCC = 5.5 V, E = VIH
ICMOS-input level
VCC = 5.5 V, E = VCC
UNIT
V
0.4
±10
Vo = 0.1 V to VCC
ITTL-input level
MAX
2.4
2
3.5
1.5
3
V
I-lA
I-lA
rnA
ICC2
Vce average supply current (active read)
tcycle = minimum cycle time,
outputs open
15
rnA
ICC3
Vec average supply current (active write)
tcycle = 15 ms
10
rnA
t Typical values are at T A = 25 DC and nominal voltages.
TEXAS ~
INSlRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-39
TMS29F256, TMS29F258, TMS29F259
262 144-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
REV A -
SMJS256C -
MARCH 1989 -
REVISED JANUARY 1991
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f =1 MHz:l:
PARAMETER
Ci
Input capacitance
Co
Output capacitance
TEST CONDITIONS
MIN
=0, f = 1 MHz
Vo = 0, f = 1 MHz
VI
TYpt
MAX
4
6
pF
8
12
pF
UNIT
t Typical values are at T A = 25°C and nominal voltage.
*
Capacitance measurements are made on sample basis only.
PARAMETER MEASUREMENT INFORMATION
2.0SV
-I
RL=SOOQ
Output
Under Test
T
CL=100
pF
Figure 5. Output Load Circuit
AC testing Input/output wave forms
2.
4V
0.40 V
==X
O.:~
2V
O.SV
X'-___
A.C. testing inputs are driven at 2.4 V for logic high and 0.4 for logic low. Timing measurements are made at 2 V for
logic high and 0.8 V for both inputs and outputs. Each device should have a 0.1 /-IF ceramic capaCitor connected
between Vee and Vss as close as possible to the device pins.
TEXAS
-111
INSTRUMENTS
7-40
POST OFFICE BOX 1443
•
HOUSTON. TEXAS n001
TMS29F256, TMS29F258, TMS29F259
262 144-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
REV A -
SMJS256C -
MARCH 1989 -
REVISED JANUARY 1991
switching characteristics over full ranges of recommended operating conditionst
'29F256-170
'29F258-170
'29F259-170
PARAMETER
MIN
MAX
'29F256-200
'29F258-200
'29F259-200
'29F256-20
'29F258-20
'29F259-20
MIN
MAX
'29F256-250
'29F258-250
'29F259-250
'29F256-25
'29F258-25
'29F259-25
MIN
MAX
'29F256-300
'29F258-300
'29F259-300
'29F256-30
'29F258-30
'29F259-30
MIN
UNIT
MAX
talA)
Access time from address
170
200
250
300
ns
talE)
Access time from chip enable
200
250
Output enable time from G
85
100
300
120
ns
ten(G)
170
75
tc(R)
Read cycle time
200
170
250
300
ns
ns
td(E)
Delay time, chip enable low to output
10
40
15
50
20
60
25
70
td(G)
Delay time, output enable low to output
10
20
60
25
70
ns
Hold time, chip enable to HI-Z output
10
15
15
50
th(E)
40
40
50
20
60
25
70
ns
th(G)
Hold time, output enable to HI-Z output
10
40
15
50
20
60
25
70
ns
Hold time, data valid to address
thlD)
t These parameters are guaranteed in regular read mode only.
20
40
30
50
40
60
50
70
ns
timing requirements over recommended ranges of supply voltage
temperature
and operating free-air
MIN
tc(W)
Write cycle time
tc(VV)B
Byte load cycle time
tsu(A)
Address setup time
tsu(W)
ns
1
MAX
UNIT
15
ms
100
its
10
ns.
Write setup time
0
ns
tsu(D)
Data setup time
80
ns
tsu(G}
Output enable setup time
10
ns
th(A)
Address hold time
150
ns
th(W)
Write hold time
Output enable hold time
0
10
ns
th(G)
th(D)
Data hold time
10
ns
tw(W)
Write pulse duration
200
ns
tr(W)
Write high recovery time
800
ns
trec(W)
Write high recovery time in page mode
800
ns
treE)
Chip enable high recovery time
800
tv(D)
Data valid time
tw(E)
Chip enable pulse duration
ns
ns
300
200
TEXAS
its
ns
-1!1
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 17001
7-41
TMS29F256, TMS29F258, TMS29F259
262 144-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
REV A -
SMJS256C -
MARCH 1989 -
REVISED JANUARY 1991
read cycle
~14---tC(R) --~.I
I
AO-A14
I
---,X,-___
~~_ _ _ _ _ _--7'X",-_______
~ta(E)--.I
1
1
\l
E
1
-----k.1
G
r-
l\l
I I
I
If
I
ten(G)
.
4
1
1.-1 th(E)-.J
iii
I
1 I
1 1
1
I
I
1
II
I
W controlled write cycle
14
tc(W)
TEXAS
l!1
INSlRUMENTS
7-42
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
.1I
TMS29F256, TMS29F258, TMS29F259
262 144-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
REV A -
SMJS256C -
MARCH 1989 -
REVISED JANUARY 1991
E controlled write cycle
page write cycle
G
E
Ii)
Il!I!l!
\ A
~tc
~~ A
A
A
.~
.~
~
I
W
AO-A14
X
Dao-Da7~
X X :><
X
>e:
Byte 0
Byte 1
Byten
X
X
Byten+1
X
X
:.
I
Last Byte
>r----f-
I
I
I
I+-- tc(W) ---.I
TEXAS . .
INSlRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-43
TMS29F256, TMS29F258, TMS29F259
262 144-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
REV A -
SMJS256C -
MARCH 1989 -
REVISED JANUARY 1991
data polling
DOO-DOG
Last Byte 007
007
1
1
1
I~
1
1
1
.1 4
~tc(W)B
Data Out
Valid
Data Out
Valid 007
Data Out
Valid
007
tc(W)
1
1
Page Write Cycle
Data Out Valid
Read During
Program Operation
.1 4
TEXAS •
INSTRUMENTS
7·44
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
~I
1
1
.1 4
Read After Program
1
1
1
~
TMS29F259
PACKAGE ADDENDUM
The following 32-pin Thin Small-Outline Package (TSOP) is under developement by Texas Instruments for the
TMS29F259. Please see Chapter 14, Mechanical Data for complete package specifications.
DD Package t
Top View
A11
A9
AS
A13
A14
NC
W
Vee
NC
NC
NC
A12
A7
AS
AS
A4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
10
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
G
A10
E
007
006
DOS
004
003
Vss
Z
002
001
000
AO
A1
A2
A3
0
~
:s.:
a:
0
u.
t The package shown is for pin~ut reference only.,
Z
W
U
Z
~
c
«
TEXAS •
INSlRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-45
TMS29F259
PACKAGE ADDENDUM
TEXAS •
INSTRUMENTS
7-46
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS87C257 262 144-BIT LATCHED UV
ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMLS857 -
•
Organization ... 32K x 8
•
•
Single 5-V Power Supply
..
J Package
(Top View)
ASNpp
A12
A?
A6.
AS
A4
A3
A2
A1
Intergrated Address Latch
. Max Access/Min Cycle Time
TMS87C257-150
150 ns
TMS87C257-1
170 ns
TMS87C257-2
200 ns
TMS87C257
250 ns
(Vee ± 5%)
•
Power-Saving CMOS Technology
•
Very High-Speed SNAP! Pulse Programming
•
•
NOVEMBER 1990
AD
DOO
D01
D02
GND
3-State Output Buffers
Low Power Dissipation (Vee = 5.5 V)
- Active ... 263 mW Worst Case
- Standby ... 1.4 mW Worst Case
(CMOS Input Levels)
1
Vcc
A14
A13
A8
A9
A11
G
A1D
E
DO?
D06
DOS
D04
D03
PIN NOMENCLATURE
description
AO-A14
E
The TMS87C257 series are 262 144-bit, ultraviolet-light erasable, electrically programmable
read-only memories.
G
GND
NC
Address Inputs
Chip Enable/Powerdown
Output Enable
Ground
No Internal Connection
Make No External Connection
Inputs (programming)/Outputs
5-V Power Supply
Address Strobe/13-V Programming
Power Supply
NU
These devices are fabricated using pO\IVer-saving
DOO-D07
CMOS technology for high speed and simple
VCC
interface with MaS and bipolar circuits.
ASNpp
All inputs(including program data inputs) can be
driven by Series 74 TTL circuits without the use of
external pullup resistors. Each output can drive one Series 74 TTL circuit without external resistors. The data
outputs are three-state for connecting multiple devices to a common bus.
The TMS87C257 incorporates internal address latches on address inputs AO-A7. The internal address latch
allows address and data pins to be tied directly to the processor's multiplexed address/data pins which can
simplify design, reduce chip connect, and lower the cost of multiplexed bus systems.
The TMS87C257 is offered in a dual-in-Iine ceramic package (J suffix) designed for insertion in mounting hole
rows on 15,2-mm (600-mil) centers. The TMS87C257 is characterized for operation from - 40°C to 85°C
(E suffix).
These EPROMs operate from a single 5-V supply (in the read mode), thus are ideal for use in
microprocessor-based systems. One other 13 V supply is needed for programming. All programming signals
are TTL level. These devices are programmable by the SNAP! Pulse programming algorithm. The SNAP! Pulse
programming algorithm uses a Vpp of 13 Vand a Vee of6.5 Vfor a nominal programming time offour seconds.
For programming outside the system, existing EPROM programmers can be used. Locations may be
programmed singly, in blocks, or at random.
PRODUCTION DATA documents contain Information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily Include testing of all parameters.
Copyright © 1990, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-47
TMS87C257 262 144-BIT LATCHED UV
ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMLS857 -
NOVEMBER 1990
operation
There are seven modes of operation listed in the following table. The read mode requires a single 5-V supply.
ASNpp during programming requires 13 V for SNAPI Pulse and 12 V on A9 for signature mode.
MODE
FUNCTION
READ
OUTPUT
DISABLE
STANDBY
VIH
E
VIL
VIL
G
VIL
VIH
ASNpp
VIL§
Vee
A9
AO
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE
MODE
VIL
VIL
VIH
VIH
VIH
VIL
X
VIL
x
xt
x
Vpp
Vpp
Vpp
VIH
Vee
Vee
Vee
Vee
Vee
Vee
x
X
x
x
x
X
VH*
X
X
X
X
X
X
VIL
Vee
I
I
VH*
VIH
CODE
DOO-D07
Data Out
HI-Z
HI-Z
Data In
Data Out
HI-Z
MFG
97
I
J
DEVICE
e2
t X can be VIL or ViH*VH = 12V ± 0.5 V.
§ VIL latches the address inputs AO-A7, VIH unlatches those inputs.
read/output disable
. When the outputs of two or more TMS87C257s are connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no interference from the competing outputs of the other devices.
To read the output of a single device, a lOW-level Signal is applied to the E and G pins. All other devices in the
circuit should have their outputs disabled by applying a high-level signal to the G pin while the device is powered
up (E is low). Output data is accessed at pins 000 through 007.
latchup immunity
Latchup immunity on the TMS87C257 is a minimum of 250 rnA on all inputs and outputs. This feature provides
latchup immunity beyond any potential transients at the P.C. board level when the EPROM is interfaced to
industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup without
compromising performance or packing density.
For more information see application report SMLA001, "Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family", available through TI Sales Offices.
power down
Active Icc supply current can be reduced from 30 rnA to 250 !lA (CMOS-level inputs) by applying a high-level
(CMOS) signal to the E pin. In this mode all outputs are in the high-impedance state, independent of G. Data
and address inputs are at static CMOS levels.
erasure
Before programming, the TMS87C257 EPROM is erased by exposing the chip through the transparent
lid to a high intensity ultraviolet light (wavelength 2537 A). EPROM erasure before programming
is necessary to assure that all bits are In the logic high state. Logic lows are programmed into the desired
locations. A programmed logic low can be erased only by ultraviolet light. The recommended minimum
exposure dose (UV intenSity x exposure time) is 15-W·s/cm2. A typical 12-mW/cm2, filterless UV lamp will
erase the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. It
should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when
using the TMS87C257, the window should be covered with an opaque label. After erasure (all bits in logic
high state), logic lows are programmed into the desired locations. A programmed zero low can be erased
only by ultiaviolet light.
.
TEXAS
~
INSlRUMENTS
7-48
POST OFFICE BOX 1443 .•
HOUSTON, TEXAS 77001
TMS87C257 262 144-BIT LATCHED UV
ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMLS857 -
NOVEMBER 1990
SNAP! Pulse programming
The 256K latched CMOS EPROM is programmed using the TI SNAP! Pulse programming algorithm as
illustrated by the flowchart in Figure 1, which can reduce time to a nominal of four seconds. Actual programming
time will vary as a function of the programmer used.
Data is presented in parallel (eight bits) on pins 000 to 007. Once addresses and data are stable, E is pulsed.
The SNAP! Pulse. programming algorithm uses initial pulses of 100 microseconds (f-ls) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-f-ls
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when ASNpp = 13 V, Vee = 6.5 V, G = VIH, and E = VIL' During
the programming mode, the address 'latch becomes effectively transparent. More than one device can
be programmed when the devices are connected in parallel. Locations can be programmed in any
order. When the SNAP! Pulse programming routine is complete, all bits are verified with Vee = Vpp =
5 V.
program inhibit
Programming may be inhibited by maintaining a high level input on the
E pin.
pr9gram verify
Programmed bits may be verified with ASNpp
signatur~
=13 V when G =VIL and E =VIH'
mode
The signature mode provides access to a binary code identifying the manufacturer and type. This
is activated' when A9 is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by AO; i.e., AO
accesses the manufacturer code, which is output on 000-007; AO = VIH accesses the device code,
is output on 000-007. All other addresses must be held at VIL' Each byte possesses odd parity
007. The manufacturer code for these devices is 97, and the device code is C2.
mode
= VIL
which
on bit
memory address lines
Fifteen memory address lines (AO-A 14) are provided on the device and are used in conjunction with G and
select one of 32 768 eight bit locations in the memory array. Addresses AO through A7 are latched
on the negative edge of the address strobe signal.
E to
address strobe line
The address strobe (AS) input is multiplexed with Vpp on pin 1. The negative edge of AS latches the low
order address lines (AO-A7) to demultiplex the address/data bus while the positive edge of AS unlatches
these address lines.
TEXAS -1!1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
7-49
TMS87C257 262 144·BIT LATCHED UV
ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMLS857 -
NOVEMBER 1990
Program
Mode
Increment
Address
Interactive
Mode
No
Yes
Vee = Vpp = 5 V ±10%
Fail
Final
~O"
Figure 1. SNAP! Pulse Programming Flowchart
TEXAS
-IJ1
INSlRUMENlS
7-50
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS87C257 262144-BIT LATCHED UV
ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMLS857 -
NOVEMBER 1990
logic symbol t
ASNpp
1
10
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A12
A13
A14
I-
9
8
7
6
5
4
3
25
24
21
23
2
26
27
TMS87C257
simplified version (programming features not shown)
TMS87C257
EPROM 32Kx 8
EPROM 32K x 8
ASNpp
C20
[13 V], 21,22C23
20DO:
2007
8
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A12
A13
A14
A __
O_
262143
14
20
22
-Lt:,.
E
[PWR DWN)
G21
20DO
20D7
8
O_
A __
262143
AV
AV
AV
AV
AV
AV
AV
AV
11
12
13
15
16
17
18
19
DOl
D02
D03
D04
D05
D06
D07
D08
14
20
G 22
"- 21EN
Lt:,.
C20
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
EN
G22
1
r
AV
A23D
_ 11
~
r
:, :'"
....
....
....
, '"
. ..
,.,.
,
r
DOO
12
13
15
16
17
18
19
DOl
D02
D03
D04
D05
DOS
D07
t These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings ove'r operating free-air temperature range (unless otherwise noted)l
Supply voltage range, Vee (see Note 1) .............................................. - 0.6 V to 7 V
Supply voltage range, Vpp ......................................................... - 0.6 V to 14 V
Input voltage range (see Note 1): All inputs except A9 ................................ - 0.6 V to 6.5 V
A9 ............................................... - 0.6 V to 13.5 V
Output voltage range (see Note 1) ............................................. - 0.6 V to Vee + 1 V
Operating free-air temperature range ('87C257-__JE ......................... ~ ....... - 40° C to 85°C
Storage temperature range ............................................. : ......... - 65°C to 150°C
:t: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
TEXAS
-III
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-51
TMS87C257 262 144-81T LATCHED UV
ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMLS857 -
NOVEMBER 1990
recommended operating conditions
TMS87C257-150
TMS87C257-1
TMS87C257-2
TMS87C257
MIN
VCC
Supply voltage
VPP
Supply voltage
UNIT
NOM
MAX
Read mode (see Note 2)
4.75
5.
5.25
SNAPI Pulse programming algorithm
6.25
6.5
6.75
Read mode (see Note 3)
VCC-0.6
SNAP! Pulse programming algorithm
12.75
VCC + 0.6
13
13.25
V
V
VIH
High-level input voltage (CMOS)
VCC x 0.7
VCC+ 1
V
VIL
Low-level input voltage (CMOS)
-0.5
0.8
V
TA
Operating free-air temperature
-40
85
°c
NOTES: 2. VCC must be applied before or at the same time as VPP and removed after or atthe same time as Vpp. The device must not be inserted
into or removed from the board when Vpp or Vce is applied.
3. Vpp can be connected to VCC directly (except in the program mode). VCC supply current in this case would be ICC + Ipp.
electrical characteristics over full ranges of operating conditions
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
TEST CONDITIONS
IOH =-2.5 rnA
IOH = - 20
fAA
MIN
TYpt
MAX
V
VCC- 0 . 1
IOL= 2.1 rnA
0.4
10L = 20 flA
0.1
II
Input current (leakage)
VI = Oto 5.5 V
±1
10
Output current (leakage)
Vo = OtoVCC
±1
IpP1
Vpp supply current
Vpp = VCC = 5.5 V
IpP2
Vpp supply current (during program pulse)
Vpp = 13 V
ICC1
VCC supply current (standby)
ICC2
I CMOS-input level
VCC = 5.5 V, E = VCC
VCC = 5.5 V, E = VIL,
tcycle = minimum cycle time,
outputs open
VCC supply current (active)
UNIT
3.5
V
1
10
fAA
fAA
fAA
35
50
rnA
100
250
flA
15
30
rnA
tTypical values are at T A = 25°C and nominal voltages.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz+
PARAMETER
TEST CONDITIONS
MAX
UNIT
Input capacitance §
VI = 0, f = 1 MHz
6
10
pF
Co
Output capacitance
Vo
=0, f = 1 MHz
10
14
pF
tTypical values are at T A = 25°C and nominal voltages.
:f: CapaCitance measurements are made on a sample basis only.
§ ASNpp is not included in input capacitance.
TEXAS
-1!1
INSTRUMEN1S
7-52
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
MIN
TYpt
Ci
TMS87C257 262 144·81T LATCHED UV
ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMLS857 -
NOVEMBER 1990
switching characteristics over full ranges of recommended operating conditions (see Notes 4
and 5)
PARAMETER
TEST CONDITIONS
(SEE NOTES 4 & 5)
'87C257-150
MIN
MAX
'87C257-1
MIN
MAX
'87C257
'87C257-2
MIN
MAX
MIN
MAX
UNIT
ta(A)
Access time from
address
150
170
200
250
ns
tatE)
Access time from chip
enable
150
170
200
250
ns
ten (G)
G
75
75
75
100
ns
60
ns
Output enable time from
Output disable time from
tdis
G or E, whichever
occurs firstt
tv(A)
Output data valid time
after change of address,
E, or G, whichever
occurs firstt
CL = 100 pF,
1 Series 74 TTL Load,
Input tr S 20 ns,
Input tf :s; 20 ns
0
60
0
0
60
0
0
60
0
0
0
ns
tsu(AS)
Address to ASNpp fall
20
20
20
20
ns
tw(AS)
Address strobe pulse
width
90
90
90
90
ns
th(AS)
Address hold from
ASNppfall
30
30
30
30
ns
tValue calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.
switching characteristics for programming: Vee
=6.5 V and Vpp =13 V, TA =25°C (see Note 4)
MIN
PARAMETER
tdislG)
Output disable time from G
0
NOM
MAX
130
UNIT
ns
150
Output enable time from G
ns
ten (G)
NOTES: 4. For all switching characteristics the input pulse levels are 0.4 V to VCC x 0.7 V. Timing measurements are made at 3 V for logic high
and 0.8 V for logic low. (reference AC Testing Wave Form)
5. Common test conditions apply for the tdis except during programming.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-53
TMS87C257 262144-BIT LATCHED UV
ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMLS857 -
NOVEMBER 1990
recommended timing requirements for programming: VCC
T A = 25°C (see Note 4)
= 6.5
V and Vpp
MIN
NOM
MAX
95
100
105
= 13
UNIT
tw(PGM)
Program pulse duration
tsu(A)
Address setup time
2
fls
tsu(G)
G setup time
2
fls
tsuLE)
E setup time
2
fls
tsu(Dl
Data setup time
2
fls
tsu(vPPl
Vpp setup time
2
fls
tsu(VCC)
VCC setup time
2
fls
th(A)
Address hold time
0
fls
th(D)
Data hold time
2
fls
NOTE 4:
V,.
fls
For all switching characteristics the input pulse levels are 0.4 V to VCC x 0.7 V. Timing measurements are made at 3 V for logic high
and 0.8 V for logic lOW}. (reference AC Testing Waveform)
PARAMETER MEASUREMENT INFORMATION
2.08V
Output
Under Test
-!
T
RL=800Q
CL=100 pF
Figure 2. AC Testing Output Load Circuit
AC testing input/output wave forms
Vcc V----x
x 0.7
_
0.4 V
_ _ _...J
~ ~.~V
A.C. testing inputs are driven at Vee x 0.7 V for logic high and 0.4 V for logic low. Timing measurements are
made at 3 V for logic high and 0.8 V for logic low for both inputs and outputs.
TEXAS •
INSTRUMENTS
7-54
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS87C257 262 144-81T LATCHED UV
ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMLS857 -
NOVEMBER 1990
read cycle timing
~~______________A_d_d_rc_s_s_cs_v_a_lid__________~J>(~_________________
A8-A14
1.iiI1.J------ta(A)
I
\
--------l~,
, ' :
,
,
1
: :\
1
th(AS)~
1
:
I.
I
..'
,
-----« ~,"::,~s
:;rr--------
~!\---t------+-------~~,II
... I'
'dls -l>I
en(G)~
,
I
1
1
1
1
) - HI.Z
.-{«{
VIL
1
:
I....
000-007, AO-A7
VIH
\-~----------------!:--------_t:-------------------
------II
tsu(AS)
V
:
~-------------~----~I--------~-,
:....1 - - - - ta(E) ----~.,
tW(AS)~
r-\.
ASNpp
:
I ,
tv (A)
~
~
j'j)}--
Oulpul Valid
VIH
V,L
HI·Z - - - :::
program cycle timing (SNAP! Pulse programming)
l.....___
Program----~
..
1l1li
r
1
AO·A14 _ _
"'1
~~
~
:
--,_...;IX
Ad~:~SS
v, _____________A_d_d_rc_s_s_Sr-ta_b_le
; _________
--'f\-~I
I
~
000·007
I
~ tsu(A)
1
----«
+-<
1
1
Data In Stable
} - HI-Z
j""---rI --------"-
,,-------11-----'111
Data Out Valid
',-
~tsu(O)
VPP
~ th(A) ~
1
,
_
VIH
~L
)>---------
VIH / VOH
-,
VIL/VOH
,tdis(G)t~
- - - - I - - - - - - - - - - - - - - - - - - , I__--.I------~'---------------VpPt
----./!f
1
'I
I
I
VCC
I"
~ tsu(VPP)
' I '
1
I"
--~'--------~-----~I-~I-----+'--------------Vcct
VCC
~~
1
I"
1
1
'
I
------v
tsu(VCC)
~ tsu(E)
l
1
tw(PGM)
I
:,
14''''--I.~'- th(O)
~
1
~
1
,I
,
-.....,..1------+-,-......,.,----+,--------
~ .!
,.....
'
E
I
1
1
!
~tsu(G)~
1
I
I
1
len(G)!
,
VCC
VIH
~L
1
G ------------------~\{
/,...------------- VIH
VIL
t tdis(G) and ten (G) are characteristics of the device but must be accommodated by the programmer.
:j: 13-V Vpp and 6.5-V Vee for SNAP! Pulse programming.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-55
TMS87C257 262144-BIT LATCHED UV
ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMLS857 -
NOVEMBER 1990
TEXAS •
INSlRUMENTS
7·56
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS27C510 524 288-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC510 524 288-BITPROGRAMMABLE READ-ONLY MEMORY
SMLS510 - AUGUST 1990
J and N Packages
•
Organization ..• 64K x 8
•
Single 5-V Power Supply
•
Pin Compatible With Existing 1 Meg MOS
ROMs, PROMs, and EPROMs
•
•
All Inputs/Outputs Fully TIL Compatible
'27C/PC51 0-120
'27C/PC510-150
'27C/PC51 0-170
'27C/PC51 0-200
'27C/PC51 0-250
'27C510-12
'27C/PC51 0-15
'27C/PC51 0-17
'27C/PC51 0-20
'27C/PC51 0-25
A12
A?
A6
AS
A14
A13
A8
A9
A11
A2
A1
AD
001
002
D03
Power Saving CMOS Technology
10
11
GNO
•
•
3-State Output Buffers
•
Latchup Immunity of 250 rnA on All Input
and Output Lines
•
NC
NC
G
120 ns
150 ns
170 ns
200 ns
250 ns
Very High Speed SNAP! Pulse
Programming
•
Vcc
NC
Vee ± 10%
•
•
Vpp
Max Access/Min Cycle Times
Vee±5%
•
(Top View)
22
12
21
13
20
14
19
15
18
16
17
A1D
E
DOB
DO?
D06
DOS
D04
z
a
~
FM Package
(Top View)
400 mV Guaranteed DC Noise Immunity
With Standard TIL Loads
. C\J
l!)
()
~
a:
0... 0
;{;{zg-~~~
A?
A6
AS
A4
Low Power Dissipation (Vee = 5.25 V)
- Active . . . 158 mW Worst Case
- Standby . . . 1.4 mW Worst Case
(CMOS-Input Levels)
A2
A1
AD
001
PEP4 Version Available With 168 Hour
Burn-In, and Choices of Operating
Temperature Range
a
6
3231 30
29
0
28
4
u.
321
7
27
8
26
25
A14
A13
A8
A9
A11
10
24
G
11
23
A1D
12
22
E
5
21
13
14 15 16 17 18 19 20
z
w
(.)
z
~
::>
c
-------
:I
~ tSU(VPP)
Vee
.
I
tw(PGM)
II'"
.11
I
:...
I
I
I tSu(G)
~I
I I
1111
------------------------~
:
I
I
I
.1 ten(G) ~.1
i
;[~----------------
t tdis(G) and ten (G) are characteristics of the device but must be accommodated by the programmer.
:j: 13.0-V Vpp and 6.5-V Vee for SNAP! Pulse programming.
-o~
z
TEXAS •
INSTRUMENTS
7-66
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
VIH/VOH
VIL/VOL
Vee
Vec
TMS27C510 524 288-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC510524 288-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS510-AUGUST 1990
device symbolization
0
i'-...
TI FML
TMS27PC510
-
TMS
27C510
-....
~
yy
WW
L X P yy WW
-- -r -- - r
--
-r -r -r - -
L
x P
Front End Code
Ole RevIsIon Co de
Backend Code
Year of Manufacture
Week of Manufa cture
-r-
Front End Code
Ole RevIsIon Co de
Backend Code
Year of Manufacture
Week of Manufa cture
z
o
~
:E
a::
o
u.
Z
W
o
Z
~
c
«
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-67
TMS27C510 524 288-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC510 524 288-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS510 -
AUGUST 1990
TYPICAL TMS27C/PC510 CHARACTERISTICS
STANDBY SUPPLY CURRENT
STANDBY SUPPLY CURRENT
-
1.50
c
I!!
:5
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
1.50
Vee=5.0V
TA = 25°C
.......... t--.,
0
>0
ii:c
e.G,)
1.25
..........
~~ 1.00
~
1.25
I'-......
~
>oC'll
.c
E
-g~ 0.75
.19-(/)
1.00
r-- r-- t--
V
V
V
V
./
0.75
/'
I
C\I
0.50
-75
0
9
-50
-25
0
25
50
75
100
0.50
4.25
125
4.5
TA-Free-Alr Temperature-°e
»C
~
c
m
0
(")
-Z
"::D0
3:
~
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
1.50
1.50
>0 ..-
1.25
'"""' ....... ..........
-"C
e.G,)
e.N
::1=
C'Il
1.00
~~
0.75
(/)
CD
TA = 25°C
f=MAX
Vee = 5.0 V
~
::I
E
~--
~
1.25
~
-......
I
----
1.00
t---- ~
0.75
N
0
...0
0.50
-75
5.75
ACTIVE SUPPLY CURRENT
ACTIVE SUPPLY CURRENT
Z
4.75
5.0
5.25
5.5
Vee-Supply VoJtage-V
-50
-25
o
25
50
75
100
"
0.50
4.25
125
'/"
V
4.5
TA-Free-Alr Temperature-°e
4.75
~
5.0
l..---'
5.25
--
5.5
5.75
vee-Supply Voltage-V
0
Z
ACCESS TIME
ACCESS TIME
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
1.50
1.50
Vee=5.0V
~
CD
E ..- 1.25
I="g
= 1.00
en N
en
CD C'Il
H 0E
Ie 0.75
. ~
~
0.50
-75
~
~
-50
~
-25
~
J.....--'""'
CD
E..-
1.25
I="g
::!CD
~
~
C'Il
HE
0
Ie
1.00
t--
25
50
75
100
125
0.75
0.50
4.25
TA-Free-Alr Temperature-°e
4.5
4.75
5.0
5.25
5.5
Vee-Supply Voltage-V
TEXAS . .
INSlRUMENTS
7-68
" f'.....
~
~
0
TA = 25°C
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
5.75
TMS27C512 524 288·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC512 524 288·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS512D - NOVEMBER 1985 - REVISED OCTOBER 1990
This Data Sheet is Applicable to All
TMS27C512s and TMS27PC512s
Symbolized with Code "B" as Described
on Page 7-79.
•
•
•
•
•
J and N Packages
(Top View)
VCC
Organization ... 64K x 8
Max Access/Min Cycle Time
Vee ± 10%
Vee ±5%
'27C/PC512-100
'27C/PC512-10
'27C/PC512-120
'27C/PC512-12
'27C/PC512-150
'27C/PC512-15
'27C/PC512-2
'27C/PC512-20
'27C/PC512
'27C/PC512-25
AS
A9
A11
G/Vpp
A1D
E
DOS
DO?
100 ns
120 ns
150 ns
200 ns
250 ns
D02
D03
GND
D06
D05
D04
FM Package
Very High-Speed SNAP! Pulse Programming
•
400-mV Minimum DC Noise Immunity With
Standard TTL Loads
•
A6
A5
A4
A3
A2
All Inputs/Outputs Fully TTL Compatible
•
•
•
A13
Pin Compatible With Existing 512K MOS
ROMs, PROMs, and EPROMs
Power Saving CMOS Technology
•
A14
A?
Single 5-V Power Supply
•
•
A12
(Top View)
3-State Output Buffers
4
Latchup Immunity of 250 mA on All Input
and Output Lines
Low Power Dissipation (Vee = 5.25 V)
- Active ... 158 mW Worst Case
- Standby ..• 1.4 mW Worst Case
(CMOS Input Levels)
3 2 1
0
AS
A6
A5
A4
5
6
7
A3
A2
8
NC
9
G/Vpp
A1
AD
10
A1D
11
E
DOS
DO?
NC
D01
PEP4 Version Available With 168 Hour
Burn-in, and Choices of Operating
Temperature Ranges
A9
A11
12
13
21
14 15 16 17 18 19 20
C\JC')O::J~LOCD
0022000
OOC)
512K EPROM Available With MIL-STD-883C
Class B High Reliability ProceSSing
(SMJ27C512)
000
PIN NOMENCLATURE
description
The TMS27C512 series are 524 288-bit, ultraviolet-light erasable, electrically programmable
read-only memories.
AO-A15
Address Inputs
E
G/vpp
Chip Enable/Powerdown
13 V Programming Power Supply
GND
Ground
NC
No Internal Connection
NU
DQ1-DQ8
Make No External Connection
Inputs (Programming) / Outputs
VCC
5-V Power Supply
The TMS27PC512 series are 524 288-bit, one-time, electrically programmable read-only memories.
PRODucnON DATA documents contain Information
curnnt I I of publication date. Productl conform to
specifications per th. terms of Texn Instruments
stlndard warranty. Production proceSSing does not
necessarily Includ. testing of III parameters.
TEXAS
~
Copyright © 1990, Texas Instruments Incorporated
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-69
TMS27C512 524 288-BIT ERASABLE UV PROGRAMMABLE READ-ONLY MEMORY
TMS27PC512 524 288-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS512D- NOVEMBER 1985 - REVISED OCTOBER 1990
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The data outputs are three-state for connecting multiple devices to a common bus. The TMS27C512 and the
TMS27PC512 are pin compatible with 28-pin 512K MOS ROMs, PROMs, and EPROMs.
The TMS27C512 EPROM is offered in a dual-in~line ceramic package (J suffix)· designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27PC512 OTP PROM is offered in a dual-in-line
plastic package (N suffix) designed for insertion in mounting hole'rows on 15,2-mm (600-mil) centers. The
TMS27PC5120TP PROM is also supplied in a 32-lead plastic leaded chip carrier package using 1,25-mm
(50-mil) lead spacing (FM suffix).
The TMS27C512 and TMS27PC512 are offered with two choices of temperature ranges of O°C to 70°C and
- 40°C to 85°C (TMS27C512-__JL and TMS27C512-__JE; TMS27PC512-__NL and TMS27PC512-_ ~NE;
TMS27PC512-__ FML and TMS27PC512-__ FME respectively). The TMS27C512 and TMS27PC512 are also
offered with 168-hour burn-in on both temperature ranges (TMS27C512-__JL4 and TMS27C512-__JE4;
TMS27PC512-__ NL4 and TMS27PC512-__NE4; TMS27PC512-__FML4 and TMS27PC512-__FME4,
respectively); see table below.
All package styles conform to JEDEC standards.
SUFFIX FOR OPERATING
TEMPERATURE RANGES
WITHOUT PEP4 BURN-IN
SUFFIX FOR PEP4
168 HR. BURN-IN
VS TEMPERATURE RANGES
EPROM
AND
OTP
PROM
ooe TO 70 0 e
- 40 0 e TO 85°e
TMS27C512-XXX
JL
JE
JL4
JE4
TMS27PC512-XXX
NL
NE
NL4
NE4
TMS27PC512-XXX
FML
FME
FML4
FME4
ooe TO 70 0 e
- 40 0 e TO 85°e
These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use
in microprocessor-based systems, One other 13-V supply is needed for programming. All programming signals
. are TTL level. The device is programmed using TI's SNAP! Pulse programming algorithm. The SNAP! Pulse
programming algorithm uses a Vpp of 13-V and a Vee of 6.5-V for a nominal programming time of seven
seconds. For programming outside the system, existing EPROM programmers can be used. Locations may be
programmed singly, in blocks, or at random.
TEXAS ~
INSlRUMENTS
7-70
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS27C512 524 288-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC512 524 288-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS512D - NOVEMBER 1985 - REVISED OCTOBER 1990
operation
There are seven modes of operation listed in the following table. The read mode requires a single 5-V supply. All
inputs are TTL level exceptforVpp during programming (13 Vfor SNAP! Pulse) and 12 Von A9for signature
mode.
MODE
FUNCTION
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE
MODE
VIL
E
VIL
VIL
VIH
VIL
VIL
VIH
G/Vpp
VIL
VIH
xt
Vpp
VIL
Vpp
VIL
Vee
Vee
Vee
X
Vee
Vee
Vee
Vee
x
x
Vee
X
VH l
X
x
x
X
VIL
x
x
A9
AD
x
x
VH l
I
I
VIH
CODE
DQ1-DQ8
Data Out
HI-Z
HI-Z
Data In
Data Out
HI-Z
MFG
97
I
I
DEVICE
85
t X can be VIL or VIH.
l VH = 12 V
±
0.5 V.
read/output disable
When the outputs of two or more TMS27C512s or TMS27PC512s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs of
the other devices. To read the output of a single device, a lOW-level signal is applied to the E and G / Vpp pins.
All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins. Output data is accessed at pins 01 through 08.
latchup immunity
Latchup immunity on the TMS27C512 and TMS27PC512 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup
without compromising performance or packing density.
For more information see application report SMLA001, "Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family", available through TI Sales Offices.
power down
Active IcC supply current can be reduced from 30 mA to 500 itA (TTL-level inputs) or 250 !-tA (CMOS-level inputs)
by applying a high TTL / CMOS signal to the E pin. In this mode all outputs are in the high-impedance state.
erasure (TMS27C512)
Before programming, the TMS27C512 EPROM is erased by exposing the chip through the transparent lid
to a high intensity ultraviolet light (wavelength 2537 angstroms). EPROM erasure before programming is
necessary to assure that all bits are in the logic high state. Logic lows are programmed into the desired
locations. A programmed logic low can be erased only by ultraviolet light. The recommended minimum
exposure dose (UV intensity x exposure time) is 15-W·s/cm2 . A typical 12-mW/cm2, filterless UV lamp will
erase the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. It
should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when
using the TMS27C512, the window should be covered with an opaque label.
TEXAS ~
. INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-71
TMS27C512 524 288-BIT ERASABLE UV PROGRAMMABLE READ-ONLY MEMORY
TMS27PC512 524 288-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS512D - NOVEMBER 1985 - REVISED OCTOBER 1990
initializing (TMS27PC512)
The one-time programmable TMS27PC512 PROM is provided with all bits in the logic high state, then logic lows
are programmed into the desired locations. Logic lows programmed into a PROM cannot be erased.
SNAPI Pulse programming
The 512K EPROM and OTP PROM is programmed using the TI SNAP! Pulse programming algorithm illustrated
by the flowchart in Figure 1, which programs in a nominal time of seven seconds. Actual programming time will
vary as a function of the programmer used.
Data is presented in parallel (eight bits) on pins 001 to 008. Once addresses and data are stable, E is pulsed.
The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (f-ls) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-f-ls
pulses per byte are provided before a failure is recognized.
The programming mode is achieved with G /Vpp = 13 V, Vee = 6.5 V, and E = VIL. More than one
device can be programmed when the devices are connected in parallel. Locations can be programmed
in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with
Vee = 5 V, G/Vpp = VIL, and E = VIL'
program Inhibit
Programming may be inhibited by maintaining a high level input on the E pin.
program verify
Programmed bits may be verified when G / Vpp and
E =VIL'
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This
is activated when A9 is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by AO; i.e., AO
accesses the manufacturer code, which is output on 001-008; AO = VIH accesses the device code,
is output on OQ1-008. All other addresses must be held at VIL' Each byte possesses odd parity
008. The manufacturer code for these devices is 97, and the device code is 85.
TEXAS •
INSTRUMENTS
7-72
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
mode
= VIL
which
on bit
TMS27C512 524 288-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC512 524 288-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS512D - NOVEMBER 1985 - REVISED OCTOBER 1990
Vee
T
Program
Mode
=6.5 V ± 0.25 V, G / Vpp =13 V ± 0.25 V
Interactive
Mode
No
Yes
Vee = 5 V ± 0.5 V,
G /Vpp = VIL
Fall
Final
I
Figure 1. SNAP! Pulse Programming Flowchart
TEXAS ~
INSlRuMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-73
TMS27C512 524 288-BIT ERASABLE UV PROGRAMMABLE READ-ONLY MEMORY
TMS27PC512 524 288-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS512D - NOVEMBER 1985 - REVISED OCTOBER 1990
logic symbols t
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
E
G/Vpp
o,
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
1
20
22
EPROM
A_O
_
65535
L.b.
-~
AO
A1
A2
A3
65536 x 8
A'V
A'V
A'V
A'V
A'V
A'V
A'V
A'V
11
12
13
15
16
17
18
19
A4
AS
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
001
002
003
004
DOS
006
007
008
151
[PWR OWN]
E
I
~
&
EN
G/Vpp
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
1
20
22
OTP PROM
o\
65536 x 8
A-O65535
A'V
A'V
A'V
A'V
A'V
A'V
A'V
A'V
11
12
13
15
16
17
18
19
001
002
003
004
DOS
006
007
008
151
[PWR OWN]
..
L.b. ------.
_I'..
&
I
EN
t These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for J and N packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted):J:
Supply voltagerange, Vee (see Note 1) ..........................................,.... - 0.6 V to 7 V
Supply voltage range, Vpp ......................................................... - 0.6 V to 14 V
Input voltage range (see Note 1): All inputs except A9 ................................ - 0.6 V to 6.5 V
A9 ............................................... - 0.6 V to 13.5 V
Output voltage range (see Note 1) ............................................. - 0.6 V to Vee + 1 V
Operating free-air temperature range ('27C512-__JL and JL4, '27PC512-__ NL and NL4,
and FML and FML4) ............................... DoC to 70°C
Operating free-air temperature range (,27C512-__JE and JE4, '27PC512-__ NE and NE4,
and FME and FME4) ............................ - 40°C to 85°C
Storage temperature range ....................................................... - 65°C to 150°C
*Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
TEXAS
If
INSlRUMENTS
7-74
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
1MS27C512 524 288·B11 UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC512 524288·811 PROGRAMMABLE READ·ONLY MEMORY
SMLS512D- NOVEMBER 1985 - REVISED OCTOBER 1990
recommended operating conditions
TMS27C/PC512-100
TMS27C/PC512-120
TMS27C/PC512-150
TMS27C/PC512-2
TMS27C/PC512
TMS27C/PC512-10
TMS27C/PC512-12
TMS27C/PC512-15
TMS27C/PC512-20
TMS27C/PC512-25
UNIT
MIN
NOM
MAX
MIN
NOM
Read mode (see Note 2)
4.75
5
5.25
4.5
5
5.5
SNAP! Pulse programming algorithm
6.25
6.5
6.75
6.25
6.5
6.75
G / VPP Supply voltage SNAP! Pulse programming algorithm
12.75
13.25
12.75
13
VCC+ 1
VCC+ 1
2
VCC
Supply voltage
13 .
V
13.25
V
VCC+ 1
VCC+ 1
V
TTL
VIH
High-level input
voltage
VIL
High-level input
voltage
TTL
-0.5
0.8
-0.5
0.8
CMOS
-0.5
0.2
-0.5
0.2
TA
Operating free-air
temperature
'27C512-__JL, JL4
'27PC512-__ NL, NL4, FML, FML4
0
70
0
70
°c
Operating free-air
temperature
'27C512-__JE, JE4
'27PC512-__ NE, NE4, FME,
FME4
-40
85
-40
85
°c
TA
2
MAX
CMOS
VCC - 0.2
VCC- 0.2
V
NOTE 2: VCC must be applied before or at the same time as G / VPP and removed after or at the same time as G / Vpp. The device must not
be inserted into or removed from the board when Vpp or VCC is applied.
electrical characteristics over full ranges of recommended operating conditions
PARAMETER
VOH
TEST CONDITIONS
10H =-2.5 mA
High-level output voltage
10H =-20 IlA
MIN
TYpt
MAX
3.5
UNIT
V
VCC- 0 . 1
IOL= 2.1 mA
0.4
VOL
Low-level output voltage
10L = 20 IlA
0.1
II
Input current (leakage)
VI = Oto 5.5 V
±1
10
Output current (leakage)
Vo = OtoVCC
±1
IlA
IlA
Ipp
G / Vpp supply current (during program pulse)
mA
ICCl
ICC2
ITTL-input level
VCC supply current (standby) I CMOS'
I
-Input evel
35
50
VCC = 5.5 V, E = VIH
250
500
VCC = 5.5 V, E = VCC
100
250
VCC supply current (active)
VCC = 5.5 V, E = VIL,
tcycl e = minimum cycle time,
outputs open
15
30
GlVpp = 13V
V
IlA
mA
t Typical values are at T A = 25°C and nominal voltages.
capacitance over recommended ranges of- supply voltage and operating free-air temperature,
f = 1 MHz:J:
PARAMETER
Ci
Input capacitance
Co
Output capacitance
CG /VPP
G / Vpp input capacitance
t Typical values are at TA
TEST CONDITIONS
MIN
TYpt
MAX
UNIT
VI = 0, f = 1 MHz
6
10
pF
= 0, f = 1 MHz
G / Vpp = 0, f = 1 MHz
10
14
pF
20
25
pF
Vo
=25°C and nominal voltages.
*Capacitance measurements are made on a sample basis only.
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-75
TMS27C512 524 288-BIT ERASABLE UV PROGRAMMABLE READ-ONLY MEMORY
TMS27PC512 524 288-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS512D- NOVEMBER 1985- REVISED OCTOBER 1990
switching characteristics over full ranges of recommended operating conditions (see Notes 3
and 4)
TEST CONDITIONS
(SEE NOTES 3 AND 4)
PARAMETER
TMS27C/PC512-100
TMS27C/PC512-10
MIN
MAX
TMS27C/PC512-120
TMS27C/PC512-12
MIN
UNIT
MAX
ta(A)
Access time from address
100
120
ns
ta(E)
Access time from chip enable
100
120
ns
ten (G)
Output enable time from G / Vpp
55
55
ns
tdis
Output disable time from G / Vpp or E,
whichever occurs firstt
45
ns
tv(A)
Output data valid time after change of address,
E, or G / Vpp, whichever occurs firstt
CL = 100 pF,
1 Series 74 TTL Load,
Input tr ,;; 20 ns,
0
Input tf ,;; 20 ns
45
0
0
0
TMS27C/PC512-150
TMS27C/PC512-15
TEST CONDITIONS
(SEE NOTES 3 AND 4)
PARAMETER
ns
UNIT
MAX
MIN
ta(A)
Access time from address
150
ns
ta(E)
Access time from chip enable
150
ns
ten(G)
Output enable time from G / Vpp
75
ns
tdis
Output disable time from G / Vpp or E,
whichever occurs firstt
60
ns
tv (A)
Output data valid time after change of address,
E, or G / Vpp, whichever occurs first t
CL = 100 pF,
1 Series 74 TTL Load,
Input tr ,;; 20 ns,
Input tf
0
20 ns
0
TEST CONDITIONS
(SEE NOTES 3 AND 4)
PARAMETER
S
TMS27C/PC512-2
TMS27C/PC512-20
MIN
MAX
ns
TMS27C/PC512
TMS27C/PC512-25
MIN
UNIT
MAX
ta(A)
Access time from address
200
250
ns
ta(E)
Access time from chip enable
200
250
ns
ten (G)
Output enable time from G / Vpp
75
100
ns
tdis
Output disable time from G / Vpp or E,
whichever occurs firstt
-
60
ns
tv(A)
Output data valid time after change of address,
E, or G / Vpp, whichever occurs first t
CL = 100 pF,
1 Series 74 TTL Load,
Input tr ,;; 20 ns,
Input tf';; 20 ns
0
60
0
0
ns
0
t Value calculated from 0.5 V delta to measured output level. This parameter is only sampled and not 100% tested.
switching characteristics for programming: Vee
T A = 25°C (see Note 3)
= 6.50
V and
PARAMETER
tdiS(G)
G / Vpp
= 13 V
MIN
o
Output disable time from G / Vpp
(SNAP! Pulse),
NOM
MAX
130
NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low. (Reference page 7-77).
4. Common test conditions apply for tdis except during programming.
TEXAS •
INSTRUMENTS
7-76
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS27C512 524 288·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC512 524 288·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS512D - NOVEMBER 1985 - REVISED OCTOBER 1990
recommended timing requirements for programming: VCC = 6.50 and GNpp = 13 V (SNAP!
Pulse), TA = 25°C (see Note 3)
MIN
TYP
MAX
95
100
105
UNIT
tw(IPGM)
Inital program pulse duration
tsu(A)
Address setup time
2
!-Is
tsu(D)
Data setup time
2
!-Is
tsu(VPP)
G / Vpp setup time
2
!-IS
tsu(VCC)
VCC setup time
2
!-IS
th(A)
Address hold time
0
!-Is
th(D)
Data hold time
2
!-IS
th(VPP)
G / Vpp hold time
2
!-IS
trec(PG)
G / Vpp recovery time
2
!-IS
tEHD
Data valid from E low
tr(PG)G
1
50
G / Vpp rise time
!-IS
!-Is
ns
NOTE 3: For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low. (Reference below).
PARAMETER MEASUREMENT INFORMATION
2.08V
Output
Under Test
--!
T
RL=800Q
CL=100pF
Figure 2. AC Testing Output Load Circuit
AC testing Input/output wave forms
2.4V---~v.
0.4V
0.: ~X'-
____..J!\ ~.~ v
____
A.C. testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
TEXAS . .
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-77
TMS27C512 524 288·BIT ERASABLE UV PROGRAMMABLE READ·ONLY MEMORY
TMS27PC512 524 288·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS512D- NOVEMBER 1985 - REVISED OCTOBER 1990
read cycle timing
AO-A15
~
~\/I
_ __________________________
Addresses Valid
Jt\.~---------------- VIH
I
1-oIII1~1----- ta(A)
I
I
~:
----------~~
:
t~"'11----------
I
I
I
fI :I
i
Jxr:------------ :::
~ta(E)~1
G/Vpp
-------------~~
-
HI-Z
VIH
VIL
I~tdls~
~ ten(G) --.-:
OQ1-0QS
' - - - - - - - - - - - - - VIL
---««<<<<<
~
tv(A)
Output Valid
~I
I
) ) ) ) } - HI-Z -
program cycle timing (SNAP! Pulse programming)
AO-A15
~
r * tsu(A)
~
OQ1-0QS
I
I I~
I I
-.J ~
I
I
I
:
HI-Z
~
th(VPP)
tr(PG)G
I
:
I
iI
I
I
I
I
~
I
I
~I
t_E_H_O_~
VPP
_ _ _ _ __
I
I
I
,~
I
X~,______-'
tw(IPGM)
I
VCC:t:
VCC~
VCC
t tdis(Gl is a characteristic of the device but must be accommodated by the programmer.
:t: 13-V G / Vpp and 6.5-V Vee for SNAP! Pulse programming.
TEXAS •
INSTRUMENlS
7-78
I
I
I"'~I---I~":-I trec(PG)
I
I
I
J>----
~ tdls(G)t
--t'_____r
T
-l.--.l ~
I
I
I
I
I
I
--t5'n...z
• Very High-Speed SNAP! Pulse
Programming
Include testing of .11 parameters.
PGM
NC
A14
A13
A8
A9
A11
FM Package
(Top View)
• 8-Bit Output For Use in
Microprocessor-Based Systems
PRODUCTION DATA documents contain
Information current IS of pubtlcatlon date.
Products conform to specifications per the terms
VCC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
AO
D01
D02
D03
GND
vPP
Address inputs
Chip Enable
Output Enable
Ground
No Internal Connection
Program
Inputs (programming)/Outputs
S-V Supply
13-V Power Supplyt
tOnly in program mode.
TEXAS
-IJ1
Copyright © 1990, Texas Instruments Incorporated
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
7-85
TMS27C010A 1 048 576·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC010A 1 048 576·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS110-NOVEMBER 1990
The TMS27PC01 OA series are 1 048 576-bit. one-time. electrically programmable read-only memories.
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the the use of external pullup resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The TMS27C010A EPROM is offered in a dual-in-Iine ceramic package (J suffix) designed for insertion in
mounting hole rows on 15.2-mm (600-mil) centers. The TMS27C010A is also offered with two choices of
temperature ranges of O°C to 70°C and - 40°C to 85°C (TMS27C01 OA-__JL and TMS27C01 OA-__JE.
respectively). The TMS27C010A is also offered with 168 hour burn-in on both temperature ranges
(TMS27C01 OA-__JL4and TMS27C01 OA-__JE4, respectively). (See table below).
The TMS27PC01 OA OTP PROM is offered in a 32-lead plastic leaded chip carrier package using 1,25-mm
(50-mil) lead spacing (FM suffix). The TMS27PC01 OA is offered with two choices of temperature ranges of O°C
to 70°C and - 40°C to 85°C (TMS27PC01 OA-__ FML and TMS27PC01 OA-__FME, respectively). (See table
below).
SUFFIX FOR PEP4
168 HOUR BURN-IN
VS TEMPERATURE RANGES
SUFFIX FOR OPERATING
TEMPERATURE RANGES
WITHOUT PEP4 BURN-IN
EPROM.
AND
OTP PROM
oOeto 70°C
- 40°C to 85°C
ooe to 70°C
- 40°C to 85°C
TMS27e010A-xxx
JL
JE
JL4
JE4
TMS27pe010A-xxx
FML
FME
orp
These EPROMs and
PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use
in microprocessor-based systems. One other 13-V supply is needed for programming. All programming signals
are TTL level. These devices are programmable using the SNAP! Pulse programming algorithm. The SNAP!
Pulse programming algorithm uses a Vpp of 13 V and a Vee of 6.5 Vfor a nominal programming time of thirteen
seconds. For programming outside the system, existing EPROM programmers can be used. Locations may be
programmed singly, in blocks. or at random.
operation
There are seven modes of operation listed in the following table. The read mode requires a single 5-V supply.
All inputs are TTL level except for Vpp during programming (13 V for SNAP! Pulse) and 12 V on A9 for signature
mode.
.
MODE
FUNCTION
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE
MODE
E
VIL
vlL
VIH
VIL
VIL
VIH
VIL
G
VIL
VIH
xt
vlH
VIL
X
VIL
PGM
X
X
X
VIL
VIH
X
X
VPP
Vee
Vee
Vee
VPP
VPP
VPP
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
A9
x
X
x
X
x
X
VH:j:
AO
X
X
X
X
X
X
VIL
Vee
I
I
VH:j:
VIH
CODE
DQ1-DQ8
Data Out
HI-Z
HI-Z
Data In
Data Out
HI-Z
MFG
97
t X can be VIL or VIH.
:j: VH
=12 V ± 0.5 V.
TEXAS ~
INSTRUMENTS
7-86
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
I DEVICE
I
D6
TMS27C010A 1 048 576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC010A 1 048 576-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS110- NOVEMBER 1990
read/output disable
When the outputs of two or more TMS27C01 OAs orTMS27PC01 OAs are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from competing outputs of the
other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All other
devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins.
latchup immunity
Latchup immunity on the TMS27C01 OA and TMS27PC01 OA is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry standard TTL or MOS logic devices. The input/output layout approach controls latchup
without compromising performance or packing density.
For more information see application report SMLA001, "Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family", available through TI Sales Offices.
power down
Active lee supply current can be reduced from 30 mA to 500 !J.A for a high TTL input on
high CMOS input on E. In this mode all outputs are in the high-impedance state.
E and to 100 !J.A for a
erasure (TMS27C010A)
Before programming, the TMS27C01 OA EPROM is erased by exposing the chip through the transparent lid to
a high intensity ultraviolet light (wavelength 2537 A). The recommended minimum exposure dose (UV intenSity
x exposure time) is 15-W·s/cm 2. A typical 12-mW/cm 2, filterless UV lamp will erase the device in 21 minutes.
The lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high
state. It should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when
using the TMS27C01 OA, the window should be covered with an opaque label. After erasure (all bits in logic high
state), logic lows are programmed into the desired locations. A programmed low can be erased only by ultraviolet
light.
initializing (TMS27PC010A)
The one-time programmable TMS27PC01 OA PROM is provided with all bits in the logic high state, then logic
lows are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAP! Pulse programming
The TMS27C01 OA and TMS27PC01 OA are programmed using the TI SNAP! Pulse programming algorithm
illustrated by the flowchart in Figure 1, which programs in a nominal time of thirteen seconds. Actual
programming time will vary as a function of the programmer used.
The SNAP! Pulse programming algorithm uses an initial pulse of 100 microseconds (!J.s) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-!J.s
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when Vpp = 13 V, Vee = 6.5 V, E = VIL, G = VIH' Data is presented
in parallel (eight bits) on pins 001 through 008. Once addresses and data are stable, PGM is pulsed low.
More than one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with
Vee = Vpp = 5 V ± 10%.
program inhibit
Programming may be inhibited by maintaining a high level input on the E or PGM pins.
program verify
Programmed bits may be verified with Vpp
= 13 V when G =VIL, E =VIL, and PGM =VIH.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-87
TMS27C010A 1 048 576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC010A 1 048 576-BIT PROGRAMMABLE READ-ONLY MEMORY
SMlS110-NOVEMBER 1990
l
Program
Mode
Increment Address
No
Increment
Address
Interactive
Mode
No
Yes
Device Failed
Final
Verification
J
Figure 1. SNAP! Pulse Programming Flowchart
TEXAS ~
INSlRUMENTS
7·88
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS27C010A 1 048 576·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC010A 1 048 576·BIT PROGRAMMABLE READ·ONLY MEMQRY
SMLS110- NOVEMBER 1990
signature mode·
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 (pin 26) is forced to 12 V. Two identifier bytes are accessed by toggling AO. All addresses
must be held low. The signature code for these devices is 9706. AO low selects the manufacturer's code 97
(Hex), and AO high selects the device code 06 (Hex), as shown by the signature mode table below.
PINS
IDENTIFIERt
AO
DOS
D07
D06
DOS
D04
D03
D02
D01
MANUFACTURER CODE
VIL
1
0
0
1
0
1
1
1
97
DEVICE CODE
VIH
1
1
0
1
0
1
1
0
D6
HEX
tE = G = VIL, A1-A8 = VIL, A9 = VH, A10-A16 = VIL. Vpp = VCC.
logic symbol:J:
EPROM 131 072 x 8
AO
A1
A2
A3
A4
AS
A6
A7
AS
A9
A10
A11
A12
A13
A14
A1S
A16
E
o ..
12
11
10
9
8
7
6
S
27
26
23
25
4
2S
29
3
2
>
13
14
15
17
18
19
20
21
D01
D02
D03
D04
DOS
D06
D07
DOS
16
22
~
24
A _O_
131071
AV
AV
AV
AV
AV
AV
AV
AV
r-......
[PWR DOWN]
&
I
EN
:I: This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
J package illustrated.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-89
TMS27C010A 1 048 576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC010A 1 048 576-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS110-NOVEMBER 1990
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. - 0.6 V to 7 V
Supply voltage range, Vpp ......................................................... - 0.6 V to 14 V
Input voltage range, All inputs except A9 ........................................ - 0.6 V to Vee + 1 V
A9 .......................................................... - 0.6 V to 13.5 V
Output voltage range, with respect to Vss (see Note 1) ........................... - 0.6 V to Vee + 1 V
Operating free-air temperature range ('27C01 OA-__JL and JL4,
'27PC01 OA-__ FML) ............................... O°C to 70°C
Operating free-air temperature range ('27C01 OA-__JE and JE4, '27PC01 OA-__ FME) .... - 40°C to 85°C
Storage temperature range ....................................................... - 65°C to 150°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
'27C01 0A/PC01 OA-1 00
'27C01 0A/PC01 OA-120
'27C01 0A/PC01 OA-150
'27C01 0A/PC01 OA-200
Vee Supply voltage
Vpp Supply voltage
UNIT
MAX
MIN
TYP
MAX
MIN
TYP
Read mode (see Note 2)
4.75
5
5.25
4.5
5
5.5
V
SNAP! Pulse programming algorithm
6.25
6.5
6.75
6.25
6.5
6.75
V
Read mode (see Note 3)
Vee- 0 .6
SNAPI Pulse programming algorithm
VIH High-level input voltage
12.75
13
Vee+ 0.6
13.25
Vee- 0 .6
12.75
Vee
13
Vee + 0.6
V
13.25
V
2.0
Vee+ 0.5
2.0
Vee+ 0.5
Vee- 0 .2
Vee+ 0.5
Vee- 0 .2
Vee+ 0.5
TTL
CMOS
Vee
TTL
-0.5
0.8
-0.5
CMOS
-0.5
GND + 0.2
-0.5
VIL
Low-level input voltage
TA
Operating free-air temperature
'27e01 OA-__JL,JL4
'27pe010AFML
0
70
Operating free-air temperature
'27e010A-__JE,JE4
'27pe01 OA-__ FME
-40
85
TA
'27C01 0A/PC01 OA-12
'27C010A/PC010A-15
'27C01 0A/PC01 OA-20
0
-40
0.8
GND + 0.2
V
V
70
°e
85
°e
NOTES: 2. Vee must be applied before or atthe same time as Vpp and removed after or atthe same time as Vpp. The device must not be inserted
into or removed from the board when Vpp or Vee is applied.
3. Vpp can be connected to Vee directly (except in the program mode). Vee supply current in this case would be ICC + Ipp. During
programming, Vpp must be maintained at 13 V ± 0.25 V.
TEXAS l!1
INSlRUMENTS
7-90
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TMS27C010A1 048 576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC010A 1 048 576-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS110- NOVEMBER 1990
electrical characteristics over full range of operating conditions
TEST CONDITIONS
PARAMETER
VOH
VOL
t
High-level output voltage
Low-level output voltage
MIN
MAX
10H = - 2Of-lA
Vee- O.2
10H = -2.5 mA
3.5
UNIT
V
IOL=2.1 mA
0.4
10L = 20 f-lA
0.1
V
II
Input current (leakage)
VI = Oto 5.5 V
±1
f-lA
10
Output current (leakage)
Va = OtoVee
±1
IpP1
Vpp supply current
Vpp = Vee = 5.5 V
10
f.!A
f.!A
IpP2
Vpp supply current (during program pulse)
50
mA
Vpp = 13 V
ITTL-input level
ICC1
VCC supply current (standby)
Ice2
VCC supply current (active) (output open)
ICMOS-input level
E = VIH, Vee = 5.5 V
500
E = VCC ± 0.2 V, Vce = 5.5 V
100
E = VIL, VCC = 5.5 V,
tcycl e = minimum cycle timet,
outputs open
30
~A
mA
Minimum cycle time = maximum access time.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz*
TYP§
MAX
Ci
Input capacitance
VI = 0, f = 1 MHz
4
8
pF
Co
Output capacitance
Va = 0, f = 1 MHz
6
10
pF
PARAMETER
TEST CONDITIONS
MIN
UNIT
:t: Capacitance measurements are made on sample basis only.
§ All typical values are at TA = 25°C and nominal voltages.
switching characteristics overfull ranges of recommended operating conditions (see Notes 4 and 5)
PARAMETER
TEST CONDITIONS
'27C01OA-100
(SEE NOTES 4 & 5) '27PC01 OA-1 00
MIN
MAX
ta(A) Access time from address
tatE)
Access time from chip
enable
ten (G) Output enable time from G
tdis
tv (A)
Output disable time from G
or E, whichever occurs first ll
CL = 100 pF,
1 Series 74
TTL load,
Input tr S 20 ns,
0
'27C010A-120
'27PC010A-120
'27C010A-12
'27PC010A-12
MIN
MAX
'27C010A-150
'27PC010A-150
'27C010A-15
'27PC010A-15
MIN
MAX
'27C010A-200
'27PC010A-200
'27C010A-20
'27PC010A-20
MIN
UNIT
MAX
100
120
150
200
ns
100
120
150
200
ns
55
55
75
75
ns
60
ns
50
0
50
0
60
0
Input tf S 20 ns
Output data valid time after
change of address, E, or G,
whichever occurs first
0
0
0
0
ns
11 Value calculated from 0.5-V delta to measured output level.
NOTES: 4. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2V for logic high and
0.8 V for logic low (reference AC Testing Wave Form).
5. Common test conditions apply for tdis except during programming.
TEXAS
~
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-91
TMS27C010A 1 048 576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC010A 1 048 576-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS110 -
NOVEMBER 1990
switching characteristics for programming: Vee
(see Note 4)
= 6.5 V and Vpp = 13 V (SNAP! Pulse), TA =25°C
PARAMETER
tdis(G)
Output disable time from G
ten (G)
Output enable time from G
MIN
NOM
0
recommended timing requirements for programming: Vee
T A = 25°C, (see Note 4)
MAX
UNIT
130
ns
150
ns
= 6.5 V and Vpp = 13 V (SNAP! Pulse),
ISNAP! Pulse programming algorithm
MIN
TYP
MAX
95
100
105
UNIT
tw(PGM)
Program pulse duration
tsu(A)
Address setup time
2
fls
tsu(E)
E setup time
2
fls
tsu(G)
G setup time
2
fls
tsu(D)
Data setup time
2
fls
tsu(VPP)
Vpp setup time
2
fls
fls
fls
tsu(VCC)
VCC setup time
2
th(A)
Address hold time
0
fls
th(D)
Data hold time
2
fls
NOTES: 4. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (reference AC Testing Wave Form).
TEXAS ~
INSlRUMENlS
7-92
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TMS27C010A 1 048 576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC010A 1 048 576-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS110 -
NOVEMBER 1990
PARAMETER MEASUREMENT INFORMATION
2.08V
Output
Under Test
-i
T
RL=800Q
CL= 100pF
Figure 2. AC Test Output Load Circuit
AC testing input/output wave forms
_
0.4V
_ _- - I
X. . ___
O.! ~
2.4V----X
~ ~.~ V
AC testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
read cycle timing
--J!Xr---------
AO-A16 _ _ _ _XJl;.I______A_d_dr_es_s_v_al_ld_ _ _ _ _
I '---------
I
141~---- ta(A)
.. I
y!Jt:-i- - - - - - - - VIH
I
I
14-- ta(E) - . I
I I
~ ten(G)
DQ1-DQ8 - - - HI-Z
I Jt:-I________
1:
i
I
--.j
I
VIL
I I
I
\
I
tv (A)
I~
VIH
~tdis~
..:
I
----4('\.Jio«...Jio.<~<<
. .<~~-=---_o_ut_pu_tva_lid_...-.;;2~1)..L)L.l»;..L).L;;J)J--
TEXAS
VIL
I
iI
\
VIH
HI-Z -
:::
-I.!I
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-93
TMS27C010A 1 048 576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC010A1 048 576-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLSll0-NOVEMBER 1990
program cycle timing (SNAP! Pulse programming)
.,,...
Program
''
=x
I
AO·A16
Verlfy~
,
:x
I
Address Stable
I
~tsu(A)
.
j+-th(Al
~ D~la In Slabl,
DQ1·DQ8
I
I
I
---.I!,
I
~.
1
I
I
1
1
I
I
I
.
~
1
'---/
tw(PGM)
I
VIUVOL
Vee
1
I
I...
I
.1
I
I
Vee:\:
1
1
Vee
I
1
1
1
1
VIH
I
1
I
VIL
~ th(D)
I
I
I
I
1
1
I
1
1
I'"
I
1
.1 I1 tsu(G)
1
1 I'"
VIH
I
t tdis(G) and ten(G) are characteristics of the device but must be accommodated by the programmer.
:\: 13-V Vpp and 6.5-V Vee for SNAP! Pulse programming.
TEXAS
l!1
INSlRUMENTS
POST OFFICE BOX 1443
•
VIL
.lten(G)tl
\l
G
7-94
VIH/VOH
VPP
I
I+-tSU(E) ~
PGM
)I
~tdls(G)t
I
I
I
I
I
I
~tsu(Vee)
E
VIL
1
~tsu(VPP)
Vee
VIH
+t
I
---1'1 :
I
J
Valid
1
1
~tSU(D)
VPP
~ Dat~ Dul
I
Address
N +1
HOUSTON. TEXAS 77001
VIH
VIL
TMS29F010
1 048 576·BIT FLASH/BLOCK
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS01 OA -
• Organization 128K x 8 or 4 Blocks of
32K x 8 Each
AUGUST 1990 -
Nand J Packages
(Top View)
• Single 5-V Power Supply
VCC
• All Inputs/Outputs TTL Compatible
±
5%
Vee
±
10%
'29F010-12
'29F010-15
'29F010-20
G
A3
A2
A1
AD
100 ns
120 ns
150 ns
200 ns
A1D
E
DO?
D06
D05
D04
D03
DOD
D01
D02
• Self-Timed Erasure of the Entire Memory Or
Block-Erase Option (4 Blocks) Before any
Reprogramming (20 ms Max)
VSS
• Single Byte and Page (128 Bytes) Program:
- Latched Address and Data
- Self-Timed Programming Operation
(10 ms Max)
- Data Polling Verification
z
o
~
FM Package
(Top View)
N
l!')
~
0
A
0
131 071
16
r-....
G1
h, [PWR
DWN]
G2
~ 1,2 EN (READ)
.,1C3 (WRITE)
'"
13
14
15
17
18
19
20
21
FLASH/BLOCK
EEPROM
131072x8
1.,
.....
,
, ...
.....
"
A,D3
\74
r
A,Z4
-.a ..
.....
,
.....
...
"........
,r
t This symbol is in accordance with ANSI/EEE Std 91-1984 and lEG Publication 617-12.
J and N packages shown.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-107
TMS29F010
1 048 576·BIT FLASH/BLOCK
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS01 OA -
AUGUST 1990 -
REVISED DECEMBER 1990
functional block diagram
AO
A1
A2
A3
A4
~,,"
I
»0
~
Z
(")
m
-Z
"TI
0
+
+
A2 +
A3 +
A4 +
AO
I-
A1
-
A6
A10 -+-
+
A12 +
A11
:JJ
A13
-0~
A15
s:
-
A5 -+-
+
A7 +
AS +
A9 +
-.-
+
+
A16 +
A14
if-
Add
Latch
,
32 Bytes -.
~,
I I
0
2
4 262144 Bit
Flash
I
R EEPROM
w
s
..
.....
Row
Decode
~
Block Decoder
110.
r++-
f++-
.....-..~
~
....
...
..
262144 Bit
Flash
EEPROM
DOO
f++- D01
~
I/O
Buffers
~
262144 Bit
Flash
EEPROM
I
1
0
r++ D02
..--.~
~
..--...--.-
.....-..~
D03
D04
DOS
D06
D07
_110.
..
.
E
G
.
.....
~~
Control Logic.
r
W
Z
"
Column Decoder
262144 Bit
Flash
EEPROM
..
.......
...
.....
~
Timing
Programming
High Voltage Generator
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 10) .............................................. - 0.6 V to 7 V
Input voltage range: All except A9 ................................................. - 0.6 V to 6.5 V
A9 ........................................................... - 0.6 V to 15 V
Output voltage (see Note 10) ............................................... - 0.6 V to Vee + 0.6 V
Operating free-air temperature range .................................................. ooe to 70 0 e
Storage temperature range ...................................................... - 65°e to 125°e
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation ofthe device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 10: Under absolute maximum ratings, voltage values are with respect to the most negative supply voltage VSS (substrate).
TEXAS •
INSTRUMENlS
7-108
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS29F010
1 048 576-BIT FLASH/BLOCK
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS01 OA - AUGUST 1990 - REVISED DECEMBER 1990
recommended operating conditions
'29FOl 0-1 00
'29F010·120
'29F010-150
'29F010-200
...
VCC
Supply voltage
MIN
MAX
MIN
5.25
4.5
5.5
2
VCC+l
2
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature
'29F010-__ JL and JL4
'29FOlO-__ NL and NL4
'29F010-__ FMLand FML4
TA
Operating free-air temperature
'29F010-
JE and JE4
TA
Operating free-air temperature
'29F010-
JQ and JQ4
CMOS
VCC - 0.2
TTL
-0.5
GND-0.2
CMOS
UNIT
4.75
TTL
VIH
'29F010·12
'29F010-15
'29F010·20
0
VCC+l
MAX
VCC -0.2
VCC+0.2
VCC+0.2
-0.5
0.8
GND+0.2
0.8
GND -0.2
V
V
V
GND+0.2
70
0
70
°c
-40
105
-40
105
°c
-40
125
-40
125
°c
z
electrical characteristics over full range of operating conditions
PARAMETER
TEST CONDITIONS
MIN
TYpt
MAX
VOH
High-level output voltage
10H = - 400 I1A
VOL
Low-level output voltage
10L= 2.1 mA
0.4
VI = Oto 5.5 V
±1
VI = Oto 15 V
±50
Vo = OVtoVCC
±10
II
Input current (leakage)
10
Output current (leakage)
ICCl
VCC supply current (standby)
IAll except A9
IA9
ITTL-input level
2.4
VCC = 5.5 V, E = VIH
ICMOS-input level
VCC = 5.5 V,
E = VCC
UNIT
V
1
1.5
0.5
1
V
~
J.tA
o
~
~
a:
o
LL
mA
Z
W
ICC2
VCC average supply current (active read)
tcycl e = minimum cycle time,
outputs open
15
mA
(J
ICC3
VCC average supply current (active write)
tcycle = 10 ms
10
mA
Z
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHzt
PARAMETER
TEST CONDITIONS
MIN
TYP;
MAX
UNIT
Ci
Input capacitance
VI = 0, f = 1 MHz
6
10
pF
Co
Output capacitance
Vo = 0, f = 1 MHz
10
14
pF
t Capacitance measurements are made on sample basis only.
; Typical values are at TA = 25° and nominal voltages.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-109
~
c
<
>e:
Byten
TEXAS
Byte n + 1
X
X
::~
I
Last Byte
I
Jr--+1
1
I
\ 4 - te(E) ---+I
-IJI
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Z
W
U
Z
~
~ cC
Dao-Da7~,-_ _
Step 1
X
X
Step 2
Step 3
Step 4
~
z("')
m
-z
."o
:IJ
s:
?j
o
z
TEXAS
~
INSTRUMENTS
7-114
POST OFFICE BOX 1443
X'--T------'>m~
X
e, HOUSTON, TEXAS 77001
Step 5
I
~
I
StepS
>~
I
I
I4-tc(E)~
TMS29F010
1 048 576-BIT FLASH/BLOCK
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS010A-AUGUST 1990- REVISED DECEMBER 1990
data polling
'!
E~A&~
I
~trec(W)~
.
W'-
I!+- tc(W)B -+!I
r-\I r-\I
X
X
__
tdp(E)
I
1
1
I
~II th(D)
I~____________~I________~_________________
:Addressn
I
I
I
I
I
~,-_AT"""~d_re_s_sn_...J_~~~,-_ _A_dd_r_es_s_nt_ __
1
I
Last Byte D07
I
I
I
ten(G)~
!
14-1.---l~~1
I
I
'\J\......../y
AO-A16
~th(D)
'(
I
Valid D07
'~~~~~~L~~Da~t~a~Ou~t~~22~~~~~
~~~~IV
Data Out
Valid
D07
~tc(W)B _--...-~I.-------_tc(W) _ _ _~~I
1
I
I
I
I
I
Read During
I
I
~I.----- Page Write Cycle -----.~,.I.-- Program Operation --*~I"f- Read After Program ~
I
I
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o
~
~
a:
o
u..
t Same address
Z
W
(J
Z
~
c
«
TEXAS .J.!1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-115
TMS29F010
1 048 576·BIT FLASH/BLOCK
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS01 OA -
AUGUST 1990 -
REVISED DECEMBER 1990
TEXAS •
INSlRUMENTS
7-116
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS29F010
PACKAGE ADDENDUM
The following 32-pin Thin Small-Outline Package (TSOP) is under developement by Texas Instruments for the
TMS29F010. Please see Chapter 14, Mechanical Data for complete package specifications.
DO Package t
Top View
A11
A9
AS
A13
A14
NC
IN
Vee
NC
A16
A15
A12
A7
A6
A5
A4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
10
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
G
A10
E
D07
D06
D05
D04
003
Vss
Z
D02
D01
DOO
AO
A1
A2
A3
0
~
:aE
a:
0
LL
t The package shown is for pinout reference only.
Z
W
(J
Z
~
c
Z
>
0... Z
« «
7
2 1 44 4342 41 40
39
8
38
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
C8
~
a 1(9 ~
0000
lJ1
INSTRUMENTS
~ ~ ~ ~
A13
A12
A11
A10
A9
VSS
NC
AS
A7
A6
AS
=1
Copyright © 1990, Texas Instruments Incorporated
TEXAS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
~
c
«
FN Package
(Top View)
• No Pullup Resistors Required
ADVANCE
INFORMATION
documents
contain
Information on new products In the sampling or
preproduction phase of development Characteristic
data and other specifications are sublect to change
without notice.
z
o
7-119
TMS27C210A 1 048 576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC210A 1 048 576-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS310-NOVEMBER 1990
The TMS27PC21 OA series are 1 048 576-bit, one-time, electrically programmable read-only memories.
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipola~ circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The TMS27C210A EPROM is offered in a dual-in-Iine ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C210A is also offered with two guaranteed
temperature ranges of O°C to 70°C and - 400G to 85°C (TMS27C210AJL and TMS27C210AJE,
respectively). The TMS27C210A is also offered with 168 hour burn-in an both temperature ranges
(TMS27C21 OA-__JL4and TMS27C21 OA-__JE4, respectively). (See table below).
The TMS27PC210A OTP PROM is offered in a 44-lead plastic leaded chip carrier package using 1,25-mm
(50-mil) lead spacing (FN suffix). The TMS27PC210A is offered with a temperature range of O°C to 70°C.
EPROM
AND
OTP PROM
SUFFIX FOR OPERATING
TEMPERATURE RANGES
WITHOUT PEP4 BURN·IN
SUFFIX FOR PEP4
168 HOUR BURN-IN
VS TEMPERATURE RANGES
ooe to 70°C
- 40°C to 85°C
oOeto 70°C
- 40°C to 85°C
TMS27e21oA-xxx
JL
JE
JL4
JE4
TMS27pe21oA-xxx
FNL
These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), they are ideal for use·
in microprocessor based systems. One other (13 V) supply is needed for programming. All programming signals
are TTL level. For programming outside the system, existing EPROM programmers can be used.
operation
There are seven modes of operation for the TMS27C21 OA and TMS27PC21 OA which are listed in the following
table. The read mode requires a single 5-V supply. All inputs are TTL level except for Vpp during programming
(13 V) and 12 V on A9 for signature mode.
MODE
FUNCTION
READ
Output
Disable
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE
MODE
E
VIL
VIL
VIH
VIL
VIL
VIH
VIL
G
VIL
VIH
xt
VIH
VIL
X
VIL
PGM
X
X
X
VIL
VIH
X
X
Vpp
Vee
Vee
Vee
Vpp
Vpp
Vpp
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
A9
X
X
X
X
X
X
VH l
AO
X
X
X
X
X
X
VIL
Vee
I
I
VH l
VIH
CODE
001-0016
Data Out
HI-Z
HI-Z
Data In
Data Out
HI-Z
MFG
97
t X can be VIL or VIH.
:I: VH = 12V±0.5V.
TEXAS ."
INSTRUMENTS
7-120
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
I DEVICE
I
AS
TMS27C210A 1 048 576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC210A 1 048 576-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS310-NOVEMBER 1990
read/output disable
When the outputs of two or more TMS27C21 OAs orTMS27PC21 OAs are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from competing outputs of the
other devices. To read the output of a single device, a low level signal is applied to the E and G pins. All other
devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins.
latchup immunity
Latchup immunity on the TMS27C21 OA and TMS27PC21 OA is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the EPROM
is interfaced to industry standard TTL or MOS logic devices. The inpuVoutput layout approach controls latchup
without compromising performance or packing density.
For more information see application report SMLA001, "Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family", available through TI Sales Offices.
power down
Active lee supply current can be reduced from 30 mA to 500 fAA for a high TTL input on E and to 100 fAA for a
high CMOS input on E. In this mode all outputs are in the high impedance state.
erasure (TMS27C210A)
Before programming, the TMS27C21 OA is erased by exposing the chip through the transparent lid to a high
intenSity ultraviolet light (wavelength 2537 ft.). The recommended minimum exposure dose (UV intensity x
exposure time) is 15-We s/cm2. A typical 12-mW/cm2, filterless UV lamp will erase the device in 21 minutes. The
lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state.
It should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when using
the TMS27C21 OA the window should be covered with an opaque label.
initializing (TMS27PC210A)
The one-time programmable TMS27PC21 OA PROM is provided with all bits in the logic high state, then logic
lows are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAP! Pulse programming
The TMS27C21 OA and TMS27PC21 OA are programmed using the TI SNAP! Pulse programming algorithm
illustrated by the flowchart in Figure 1, which can program in a nominal time of seven seconds. Actual
programming time will vary as a function of the programmer used.
The SNAP! Pulse programming algorithm uses an initial pulse of 100 microseconds (fAs) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-fAs
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when Vpp = 13 V, Vee = 6.5 V, E = VIL, G = VIH. Data is presented
in parallel (sixteen bits) on pins 001 through 0016. Once addresses and data are stable, PGM is pulsed
low.
More than one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with
Vee = Vpp = 5 V ± 10%.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
e
HOUSTON, TEXAS 77001
7-121
TMS27C210A 1 048 576·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC210A 1 048 576·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS310- NOVEMBER 1990
program Inhibit
Programming may be inhibited by maintaining a high level input on the E or PGM pins.
program verify
Programmed bits may be verified with Vpp = 13 V when
G = VIL, E = VIL, and PGM = VIH.
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 is forced to 12 V. Two identifier bytes are accessed by toggling AD. DQ1-DQ8 contain the
valid codes. All other addresses must be held low. The signature code for these devices is 97 AB. AD low selects
the manufacturer's code 97 (Hex), and AD high selects the device code AB (Hex), as shown by the signature
mode table below.
signature mode t
PINS
IDENTIFIERt
AO
DQ8
DQ7
DQ6
DQS
DQ4
DQ3
DQ2
DQ1
MANUFACTURER CODE
VIL
1
0
0
1
0
1
1
1
97
DEVICE CODE
VIH
1
0
1
0
1
0
1
1
AB
t'E =G =VIL. A9
=VH. A1-A8 =VIL. A10-A15 =VIL. Vpp =VCC. PGM =VIH or VIL.
TEXAS . .
INSlRUMENTS
7-122
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
HEX
TMS27C210A 1 048 576·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC210A 1 048 576·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS310-NOVEMBER 1990
l
Program
Mode
Increment Address
No
Increment
Address
Interactive
Mode
No
Yes
Device Failed
Final
Verification
J
Figure 1. SNAP! Pulse Programming Flowchart
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-123
TMS27C210A 1 048 576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC210A 1 048 576-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS310- NOVEMBER 1990
logic symbol t
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11
A12
A13
A14
»c
A1S
21
22
23
24
25
26
27
28
29
31
32
33
34
35
36
37
0
...
EPROM 65 536 x 16
"
0
>A 65535
15
~
z
2
('1
I
-zm
20
."
o
:IJ
s:
~
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
19
18
17
16
15
14
13
12
10
9
8
7
6
5
4
3
001
002
003
004
005
006
007
008
009
0010
0011
0012
0013
0014
0015
0016
[PWR OWN]
f'...
&
f'...
EN
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted):t:
Supply voltage range, Vee (see Note 1) .............................................. - 0.6 V to 7 V
Supply voltage range, Vpp ......................................................... - 0.6 V to 14 V
Input voltage range (see Note 1): All inputs except A9 ............................ - 0.6 V to Vee + 1 V
A9 ............................................... -0.6Vto 13.5V
Output voltage range (see Note 1) ............................................. - 0.6 V to Vee + 1 V
Operating free-air temperature range ('27C21 OA-__JL and JL4, '27PC21 OA-__ FNL) ....... 0° C to 70°C
Operating free-air temperature range ('27C21 OA-__JE and JE4) ...................... - 40° C to 85°C
Storage temperature range ....................................................... - 65°C to 150°C
o
z
:j: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section
of this specification is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
.
TEXAS ~
INSTRUMENTS
7-124
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS27C210A 1 048 576-81T UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC210A 1 048 576-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS310-NOVEMBER 1990
recommended operating conditions
TMS27C/PC210A·120
TMS27C/PC210A·150
TMS27C/PC210A·200
TMS27C/PC210A·250
VCC Supply voltage
Vpp Supply voltage
VIH
UNIT
MIN
NOM
MAX
MIN
NOM
Read mode (see Note 2)
4.75
5
5.25
4.5
5
5.5
SNAP! Pulse programming algorithm
6.25
6.5
6.75
6.25
6.5
6.75
VCC+ 0 .6
VCC- 0.6
VCC-O· 6
Read mode (see Note 3)
SNAP! Pulse programming algorithm
High-level input voltage
Low-level input voltage
12.75
VCC
13
2
TIL
CMOS
VIL
TMS27C/PC210A·12
TMS27C/PC210A·15
TMS27C/PC210A·20
TMS27C/PC210A·25
13.25
VCC+0.5
VCC-0.2
VCC+0.5
VCC
12.75
MAX
VCC+0.6
13
2
V
VCC+0.5
VCC- 0.2
V
13.25
V
VCC+0.5
TIL
-0.5
0.8
-0.5
0.8
CMOS
-0.5
GND+0.2
-0.5
GND+O.2
V
TA
Operating free-air
temperature
'27C210A-__JL, JL4
'27PC210A- FNL
0
70
0
70
°c
TA
Operating free-air
temperature
'27C21 OA-__JE, JE4
-40
85
-40
85
°c
--
NOTES: 2. VCC must be applied before or atthe same time as Vpp and removed after or at the same time as Vpp. The device must not be inserted
into or removed from the board when Vpp or VCC is applied.
3. Vpp can be connected to VCC directly (except in the program mode). VCC supply current in this case would be ICC + Ipp.
TEST CONDITIONS
VOH
VOL
IOH =-20
High-level output voltage
f.lA
10H =-2 mA
Low-level output voltage
0:
MAX
MIN
VCC- 0.2
UNIT
V
2.4
10L= 2.1 mA
0.4
IOL = 20 f1A
0.1
V
II
Input current (leakage)
VI = Oto 5.5 V
±1
f1A
10
Output current (leakage)
Vo = OtoVCC
±1
f1A
IpP1
Vpp supply current
Vpp = VCC = 5.5 V
10
f1A
IpP2
Vpp supply current (during program pulse)
50
mA
ICC1
ICC2
VCC supply current (standby)
Vpp = 13 V
ITIL-input level
ICMOS-input level
VCC = 5.5 V, E = VIH
500
VCC = 5.5 V, E = VCC
100
VCC = 5.5 V, E = VIL,
tcycl e = minimum cycle time,
outputs open t
VCC supply current (active)
30
f1A
mA
t Minimum cycle time = maximum address access time.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz:f:
TYP§
MAX
Ci
Input capacitance
VI = 0, f = 1 MHz
8
12
pF
Co
Output capacitance
Vo = 0, f = 1 MHz
12
15
pF
TEST CONDITIONS
PARAMETER
MIN
UNIT
:j: Capacitance measurements are made on a sample basis only.
§ Typical values are at TA
=25°C and nominal voltages .
• m
TEXAS
-III
INSlRUMENTS
POST OFFICE BOX 1443
:i,
•
HOUSTON, TEXAS 77001
~
~
electrical characteristics over full ranges of operating conditions
PARAMETER
z
o
7-125
oLL
Z
W
(J
Z
~
c
}
~tdls~
Output VaHd
INSlRUMENTS
VIH
~I
I
HI-Z -
:::
TMS27C040 4194 304-BIT UVERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC040 4 194 304-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS040- NOVEMBER 1990
VIH
VIL
VIH/VOH
DOO-D07
VI L/VO L
Vpp
Vpp
Vee
Vee+ 1
Vee
Z
Vee
0
-
~
VIH
VIL
~
a:
VIH
0
U.
VIL
Z
W
U
Z
~
c
<1:
TEXAS •
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
7-147
TMS27C040 4194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC040 4 194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS040-NOVEMBER 1990
TEXAS .JJ.J
INSlRUMENTS
7-148
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS27C240 4 194 304-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC240 4 194 304-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS240 -
TMS27C240
J Package
(Top View)
•
•
Wide-Word Organization' ... 256K x 16
•
All Inputs/Outputs Fully TTL Compatible
•
•
Static Operations (No Clocks, No Refresh)
Single 5-V Power Supply
Vpp
'27C/PC240-80
'27C/PC240-10
'27C/PC240-12
'27C/PC240-15
D015
D014
D013
D012
D011
D010
D09
D08
GNDt
D07
D06
D05
D04
D03
D02
D01
DOO
80 ns
100 ns
120 ns
150 ns
•
16-Bit Output ~or Use in MicroprocessorBased Systems
•
Very High Speed SNAP! Pulse
Programming
•
Power-paving CMOS Technology
•
•
3-State Output Buffers
400-mV Minimum DC Noise Immunity-With
Standard TTL Loads
Latchup Immunity of 250 rnA on All Input
and Output Lines
•
No Pullup Resistors Required
•
Low Power Dissipation (Vee =5.5 V)
- Active ... 275 mW Worst Case
- Standby ..• 0.55 mW Worst Case
(CMOS-Input Levels)
z
o
~
:E
a:
PIN NOMENCLATURE
AO-A17
E
G
GNO
NC
000-0015
VCC
vPP
o
u.
Address Inputs
Chip Enable
Output Enable
Ground
No Connection
Inputs (programming)fOutputs
5-V Supply
13·V Power Supply:!:
Z
W
(.)
Z
t Pins 11 and 30 must be connected externally to ground.
:/: Only in program mode.
~
c
TMS27PC240
FN Package
PEP4 Version Available With 168 Hour
Burn-In, and Choices of Operating
Temperature Ranges
«
(Top View)
~:'! ~
0...
0
000
0...0 0 ~ ~ ~ :'!
OOOIW>Z> A
-0 262143
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
19
18
17
16
15
14
13
12
10
9
8
7
6
5
4
3
OQO
OQ1
OQ2
OQ3
OQ4
OQ5
OQ6
OQ7
OQB
OQ9
OQ10
OQ11
OQ12
OQ13
OQ14
OQ15
17
I
-Z
o
0
[PWR OWN]
r--...
&
r--...
EN
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted):t:
Supply voltage range, Vee (see Note 1) .............................................. - 0.6 V to 7 V .
Supply voltage range, Vpp ......................................................... - 0.6 V to 13 V
Input voltage range (see Note 1): All inputs except A9 ................................. - 0.6 V to 6.5 V
A9 ............................................... -0.6Vt013.5V
Output voltage range (see Note 1) ............................................. - 0.6 V to Vee + 1 V
Operating free-air temperature range ('27C240-__JL and JL4,
'27PC240-__FNL) ..................... :......... 0° C to 70°C
Operating free-air temperature range ('27C240-__JE and JE4) ........................ - 40° C to 85°C
Storage temperature range ....................................................... - 65°C to 150°C
o
z
:t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section
of this specification is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
TEXAS •
INSlRUMENTS
7-154
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS27C240 4 194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC240 4 194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS240 -
NOVEMBER 1990
recommended operating conditions
TMS27C/PC240-8
TMS27C/PC240-100
TMS27C/PC240-120
TMS27C/PC240-150
Vee
Supply voltage
VPP
Supply voltage
TMS27C/PC240-80
TMS27C/PC240-10
TMS27C/PC240-12
TMS27C/PC240-15
UNIT
MIN
NOM
MAX
MIN
NOM
Read mode (see Note 2)
4.75
5
5.25
4.5
5
5.5
SNAP! Pulse programming algorithm
6.25
6.5
6.75
6.25
6.5
6.75
VCC+0.6
Vce- 0.6
13.25
12.75
Read mode (see Note 3)
VCC-0.6
SNAP! Pulse programming algorithm
TTL
VIH
High-level input
voltage
VIL
Low-level input voltage
13
12.75
Vee+ 0 .5
2
CMOS
VCC-0.2
Vec+0.5
MAX
V
Vce+ 0 .6
13
2
Vec+0.5
Vec-0.2
V
13.25
V
VCC+0.5
TTL
-0.5
0.8
-0.5
0.8
CMOS
-0.5
0.2
-0.5
0.2
V
TA
Operating free-air
temperature
'27C240-__JL, JL4
'27PC240-__ FNL
0
70
0
70
°c
TA
Operating free-air
temperature
'27C240-__JE, JE4
-40
85
-40
85
°c
NOTES: 2. Vec must be applied before or atthe same time as VPP and removed after or at the same time as Vpp. The device must not be inserted
into or removed from the board when Vpp or VCC is applied.
3. Vpp can be connected to VCC directly (except in the program mode). VCC supply current in this case would be ICC + Ipp. During
programming, VPP must be maintained at 13 V ± 0.25 V.
VOH
High-level output voltage
VOL
Low-level output voltage
TEST CONDITIONS
MIN
f.lA
MAX
V
Vee- 0.1
f.lA
0.1
Z
Input current (leakage)
VI = Oto 5.5 V
±1
f.lA
Output current (leakage)
Vo = OtoVCC
±1
flA
IpP1
Vpp supply current
Vpp = VCC = 5.5 V
10
flA
IpP2
Vpp supply current (during program pulse)
Vpp = 13 V
50
mA
ICC1
VCC supply current (standby)
ICC2
Vce supply current (active)
VCC = 5.5 V, E = Vec
1
mA
100
flA
50
mA
VCC = 5.5 V, E = VIL,
tcycle = minimum cycle time,
outputs open
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHzt
PARAMETER
TEST CONDITIONS
MIN
TYP+
MAX
UNIT
Ci
Input capacitance
VI =0
4
8
pF
Co
Output capacitance
Vo =0
8
12
pF
tCapacitance measurements are made on a sample basis only.
+ Typical values are at T A = 25°C and nominal voltages.
TEXAS
-If
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POST OFFICE BOX 1443
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Z
(.)
II
VCC = 5.5 V, E = VIH
o
u.
V
10
I TTL-input level
I CMOS-input level
~
W
0.4
IOL= 2.1 rnA
IOL = 20
UNIT
2.4
IOH =-2.5mA
IOH = - 20
~
a:
electrical characteristics over full ranges of operating conditions
PARAMETER
z
o
7-155
~
c
Vee
c
~
z(")
-zm
"o
:c
3:
~
o
z
TEXAS ~
INSlRUMENTS
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POST OFFICE BOX 1443
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HOUSTON, TEXAS 17001
Application Specific Memories
Application Specific Memories
TMS29F816
16 384·BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE
DEVICE
SMJS816- NOVEMBER 1990
•
Device is a Member of Texas Instruments
SCOPE™ Family of Testability Products
•
•
IEEE 1149.1 Serial Test Bus Compatible
o
•
FM PACKAGE
(TOP VIEW)
OOUO
ZZZZ
Embedded 2048 x 8-Bit Flash Memory
2
TMS
TCK
NC
TOI
GNO
5-Volt Program/Erase/.Read Operation
4 Flash Erasable Blocks (128, 384, 512, and
1024 Byte Size)
•
•
Write-Once Protection Bits
•
Self-Timed Write/Erase Cycles
•
•
•
Data Flow Read Mode
3
Software Sequence Write/Erase Protection
1
0
18 17
16
4
15
5
14
6
13
12
7
8
9 10
VCC
OLB
NC
OLA
TOO
11
0000
ZZZZ
32-Byte Page Programming Mode
PIN NOMENCLATURE
TMS
TCK
TDI
TOO
DLA
DLB
VCC
GND
NC
CMOS Technology
•
•
Single 5-V Power Supply (± 10% Tolerance)
•
Operating Free-Air Temperature Range
... O°C to 70°C
18-Pin Plastic Leaded Chip Carrier Package
(FM Sufix)
Test Mode Select
Test Clock
Test Data In
Test Data Out
Disable Lock A
Disable Lock B
5-V Power Supply
Ground
No Connect
3:
w
>
w
a:
a..
I-
U
desc~iption
:)
The TMS29F816 SCOPE™ Diary is a 16 384-bit, programmable storage device that can be electrically
bulk-erased and reprogrammed. All device operations are accomplished via a 4-wire Test Access Port (TAP)
interface. This interface complies with the IEEE 1149.1 Serial Test Bus standard (JTAG). The interface consists
of two control signals; Test Mode Select (TMS) and Test Clock (TCK); and two test data pins, Test Data In (TDI)
and Test Data Out (TDO). The JTAG Test Access Protocol defines how this 4-wire test bus is used to scan-in
instructions and data, to execute instructions, and to scan-out the resulting data.
All test information is serially loaded into the chip via TDI and out of the chip via TDO. The Diary has the three
JTAG mandatory components, a Test Access Port (TAP) controller, a set of Test Data Registers, and an
Instruction Register. The TAP controller interfaces the Test Data Registers and the Instruction Register to the
4-wire test bus. The Test Data Registers apply and/or capture test data. The Instruction Register selects the Test
Data Register to be accessed and the test to be performed.
The Test Data Registers consists of three different types: the Data Scan Registers (DSR), the Bypass Register
(BR), and the Device Identification Register (DIR).
The TMS29F816 SCOPE Diary features an embedded Flash EEPROM array, internal circuitry for self-timed
programming/erasing, and completion polling. In the erased state all bits are at a logic 1. To reprogram, all
memory bits in a selected block are erased first, and then those bits that should be logic zeroes are programmed
accordingly. The device is fabricated using HVCMOS flotox technology for high-reliability and very low power
dissipation. It performs the erase/program operations automatically with a single 5-V supply, and it can program
a single byte or any number of bytes between 1 and 32 within the same page. During programming and erasing,
the completion status is available, allowing the system to maximize throughput.
SCOPE is a trademark of Texas Instruments
PRODUCT PREVIEW documents contain Information
on products in the formative or design phase of
development. Characteristic data and other
specifications are deSign goals. Texas Instruments
reserves the right to change or discontinue these
products without notice.
TEXAS ~
Copyright © 1990, Texas Instruments Incorporated
INSlRUMENTS
POST OFFiCE BOX 1443
•
HOUSTON, TEXAS 77001
8-1
C
o
a:
a..
TMS29F816
16 384-BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SMJS816 -
NOVEMBER 1990
The TMS29F816 is divided into four independently flash erasable blocks. These block are configured as 128,
384, 512, and 1024 bytes in size. Four write-once, lock-bits can be programmed to prevent erasure and
programming of each block.
The device is protected against write and erase commands during power-up and power down by an on-chip
power supply reference comparator. Software sequences are used to protect against inadvertent program and
erase commands during normal operation.
The TMS29F816 is available in a 1000 cycle endurance version, and is characterized for operation from
to 70 o e.
oDe
The TMS29F816 is offered in an 18-pin plastic leaded chip carrier package (FM suffix).
pin descriptions
PIN NO.
I/O
DESCRIPTION
TMS
I
Test Mode Select. Controls transition of TAP finite state machine. This input is sampled on the rising edge
of TCK.
TCK
I
Test Clock. Input clock to TAP finite state machine. All changes in state are synchronous to the test clock
TCK.
TDI
I
Test Data In. Data input to the internal register scan path. Data on this pin is sampled on the rising edge of
TCK.
o
TOO
0
Test Data Out. Data output from the internal register scan path. Data is updated on this pin on the falling
edge of TCK.
C
DLA
I
Disable Lock A. Controls lock-bit functionally for memory array bank O. When DLA =VIL. the state of
lock-bit 0 (LCKO) determines whether bank 0 can be erased or programmed. When DLA = VIH. bank 0
can be erased or programmed irrespective of the state of lock-bit O. (When DLA = VH (VH » VCC). the
device enters a special manufacturing test mode.
DLB
I
Disable Lock B. Input that controls lock bit functionality for memory banks 1. 2 and 3. When DLB = VIL.
the states of lock-bits 1. 2 and 3 (LCK1 • LCK2. LCK3) determine whether their respective banks (1. 2 and
3) can be erased or programmed. When DLB = VIH. banks 1. 2 and 3 can be erased or programmed.
irrespective of the state of their associated lock-bits.
VCC
I
5-V Power Supply. 5-V ± 10% operating power supply connection.
""C
JJ
C
(')
-t
""C
JJ
m
!5
m
:E
TEXAS
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TMS44C250
262144 BY 4·BIT MULTIPaRT VIDEO RAM
REV A - SMVS250 - JUNE 1990 - REVISED JANUARY 1991
DZ Package
(Top View)
•
DRAM: 262 144 Words x 4 Bits
SAM: 512 Words x 4 Bits
•
Dual Port Accessibility - Simultaneous
and Asynchronous Access from the DRAM
and SAM Ports
•
Bidirectional Data Transfer Function
Between the DRAM and the Serial Data
Register
Write Per Bit Feature for Selective Write to
Each RAM I/O.
•
Enhanced Page Mode Operation for Faster
Access
•
CAS-before-RAS and Hidden Refresh
Modes
•
RAM Output Enable Allows Direct
Connection of DQ and Address Lines to
Simplify System Design
GND/NC
RAS
A8
A6
A5
A4
VCC
AO-A8
CAS
DQO-DQ3
SE
RAS
SC
SDQO-SDQ3
TRG
DRAM Port Is Compatible with the
TMS44C256
•
Up to 33 MHz Uninterrupted Serial Data
Streams
•
3-State Serial I/Os Allow Easy Multiplexing
of Video Data Streams
•
512 Selectable Serial Register Starting
Locations
•
All Inputs and Outputs TTL Compatible
•
Performance Ranges:
±
D02
SE
SD03
SC
SD01
DOO
W
RAS
A6
A4
A7
A2
AO
CAS
PIN NOMENCLATURE
Long Refresh Period ... Every 8 ms (Max)
Vee
GND
SD03
D03
SD02 SD02
SE
VSS
SDOO
D03
TRG
D02
D01
GND
CAS GND/NC
GND/NC A8
A5
AO
VCC
A1
A3
A2
A1
A3
GND/NC
A7
VSS
W
•
•
•
SC
SDOO
SD01
TRG
DOO
D01
SD Package
(Top View)
W
GND/NC
VCC
VSS
GND
•
10%
Address Inputs
Column Enable
DRAM Data In-Out/Write Mask Bit
Serial Enable
Row Enable
Serial Data Clock
Serial Data In-Out
Transfer Register/Q Output Enable
Write Mask Select/Write Enable
No Connect or Ground Only
5-V Supply
Ground
Ground (Important: not connected to
internal VSS)
Performance Ranges:
ACCESS
TIME
ROW
ADDRESS
(MAX)
ta(R)
1 MS44C250-1 100 ns
ACCESS ACCESS ACCESS ACCESS
TIME
TIME
TIME
TIME
ROW
COLUMN SERIAL SERIAL
DATA
ENABLE
ADDRESS ENABLE
(MAX)
(MAX)
(MAX)
(MAX)
ta(R)
ta(C)
ta(SC)
ta(SE)
TMS44C250-10 100 ns
25 ns
20 ns
30 ns
TMS44C250-12 120 ns
30 ns
35 ns
25 ns
•
Vee
ACCESS
TIME
COLUMN
ENABLE
(MAX)
ta(C)
25 ns
±
5%
ACCESS ACCESS
TIME
TIME
SERIAL SERIAL
DATA
ENABLE
(MAX)
(MAX)
ta(SC)
ta(SE)
30 ns
20 ns
Texas Instruments EPIC ™ CMOS Process
description
The TMS44C250 Multiport Video RAM is a high speed, dual ported memory device. It consists of a dynamiC
random-access memory (DRAM) organized as 262 144 words of 4 bits each, interfaced to a serial data register,
or Serial Access Memory (SAM), organized as 512 words of 4 bits each. The TMS44C250 supports three basic
types of operation: random access to and from the DRAM, serial access to and from the serial register, and
bidirectional transfer of data between any row in the DRAM and the serial register. Except during transfer
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA documents contain Information current
as of publication date. Products conform to specifications
per the terms of Texas Instruments standard warranty.
Production processing does not necessarily Include testing
of all parameters.
TEXAS
~
Copyright © 1991, Texas Instruments Incorporated
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8-3
TMS44C250
262144 BY 4-BIT MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
operations, the TMS44C250 can be accessed simultaneously and asynchronously from the DRAM and SAM
ports. During transfer operation, the 512 columns of the DRAM are connected to the 512 positions in the serial
data register. The 512 x 4 bit serial data register can be loaded from the memory row (transfer read) or else the
contents of the 512 x 4 bit serial data register can be written to the memory row (transfer write).
The SAM can also be configured in input mode, accepting serial data from an external device. Once the serial
register within the SAM is loaded, its contents can be transferred to the corresponding column positions in any
row in memory in a single memory cycle. The SAM port is designed for maximum performance. Data can be
input to or accessed from the SAM at serial rates up to 33 MHz.
All inputs, outputs, and clock signals on the TMS44C250 are compatible with Series 74 TTL. All address lines
and data-in are latched on-chip to simplify system design. All data-outs are unlatched to allow greater system
flexibility.
The TMS44C250 employs state-of-the-art Texas Instruments EPIC™ scaled-CMOS, double level
polysilicon/polycide gate technology for very high performance combined with low cost and improved reliability.
The TMS44C250 is offered in a 2B-pin small-outline J-Ieaded package (DZ suffix) for direct surface mounting
in rows on 400-mil (5,OB-mm) centers. It is also offered in a 400-mil, 2B-pin zig-zag in-line package (SO suffix).
80th packages are characterized for operation from O°C to 70°C (L suffix).
The TMS44C250 and other Multiport Video RAMs are supported by a broad line of graphics processor and
control devices from Texas Instruments.
TEXAS ~
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TMS44C250
262144 BY 4·BIT MULTIPaRT VIDEO RAM
REV A -
SMVS250 - JUNE 1990 -
REVISED JANUARY 1991
m
functional block diagram
o
000
001
002
003
B
+-<>
vCC
+-0
+-0
+-0
+-0
+-0
+-0
+-0
+-0
+-0
AO
AI
A2
A3
A4
AS
AS
A7
AS
+-0 vss
O-+-If--+~
Write
Per Bit
Control
B
RC
e
0
f u
r n
e t
5
h
SOOO
SOOI
SOO2
SOO3
e
r
G
Te
I n
me
I r
n
a
t
9 0
+-0
+-0
+-0
+-0
+-0
+-0
RAS
CAS
TRG
Vi
SC
SE
Detailed Pin Description vs Operational Mode
PIN
TRANSFER
DRAM
AO-AS
Row, Column Address
Row, Tap Address
CAS
DQi
Column Enable, Output Enable
Tap Address Strobe
DRAM Data I/O, Write Mask Bits
Serial-In Mode Enable
SE
RAS
SAM
Row Enable
Serial Enable
Row Enable
Serial Clock
SC
Serial Data 1/0
SDOi
TRG
a Output Enable
W
Write Enable, Write per Bit Select
Transfer Enable
Transfer Write Enable
VCC
5-V Supply (typical)
VSS
GND/NC
No Connect or Ground Only
GND
System Ground
Device Ground
TEXAS ~
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S-5
TMS44C250
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
operation
random access operation
Refer to Table 1, Functional Table, for Random Access and Transfer Operations. Random access operations
are denoted by the designator "R" and transfer operations are denoted by a " T."
transfer register select and DQ enable (TRG)
The TRG pin selects either register or random access operation as RAS falls. For random access (DRAM) mode,
TRG must be held high as RAS falls. Asserting TRG high as RAS falls causes the 512 storage elements of each
data register to remain disconnected from the corresponding 512-bit lines of the memory array. (Asserting TRG
low as RAS falls connects the 512-bit positions in the serial register to the bit lines and indicates that a transfer
will occur between the data registers and the selected memory row. See ''Transfer Operation" for details.)
During random access operations, TRG also functions as an output enable for the random (0) outputs.
Whenever TRG is held high, the 0 outputs are in the high-impedance state to prevent an overlap between the
address and DRAM data. This organization allows the connection of the address lines to the data I/O lines but
prohibits the use of the early write cycle. It also allows read-modify-write cycles to be performed by providing
a three-state condition to the common I/O pins so that write data can be driven onto the pins after output read
data has been externally latched.
address (AD through AS)
Eighteen address bits are required to decode 1 of 262 144 storage cell locations. Nine row address bits are set
up on pins AD through A8 and latched onto the chip on the falling edge of RAS. Then, the nine column address
bits are set up on pins AD through A8 and latched onto the chip on the falling edge of CAS. All addresses must
be stable on or before the falling edges of RAS and CAS.
RAS and CAS address strobes and device control clocks
RAS is a control input that latches the states of the row address, W, TRG, SE, and CAS, onto the chip to invoke
the various DRAM and Transfer functions of the TMS44C25D. RAS is similar to a chip enable in that it activates
the sense amplifiers as well as the row decoder. CAS is a control input that latches the states of the column
address. CAS also acts as an output enable for the DRAM output pins.
write enable, write-per-bit enable (W)
The W pin enables data to be written to the DRAM and is also used to select the DRAM write per bit mode of
operation. A logic high level on the W input selects the read mode and logic low level selects the write mode.
In an early write cycle, W is brought low before CAS and the DRAM output pins (DO) remain in the
high-impedance state for the entire cycle. During DRAM write cycles, holding W low on the falling edge of RAS
will invoke. the write per bit operation.
A four-bit binary code (the write-per-bit mask) is input to the device via the random DO pins and is latched on
the falling edge of RAS. The write-per-bit mask selects which of the four random I/Os are written and which are
not. After RAS has latched the write mask on-chip, input data is driven onto the DO pins and is latched on the
falling edge of the later of CAS or W. If a D was strobed into a particular I/O pin on the falling edge of RAS, data
will not be written to that I/O. If a 1 was strobed into a particular I/O pin on the falling edge of RAS, data will be
written to that I/O.
See the corresponding timing diagrams for details. IMPORTANT: The write-per-bit operation is invoked only if
W is held low on the falling edge of RAS. If W is held high on the falling edge of RAS, write per bit is not enabled
and the write operation is identical to that of standard x 4 DRAMs.
TEXAS ."
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TMS44C250
262144 BY 4-BIT MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
data I/O (DOO-DQ3)
DRAM data is written during a write or read-modify-write cycle. The falling edge ofW strobes data into the on-chip
data latches. In an early write cycle, W is brought low prior to CAS and the data is strobed in by CAS with data
setup and hold times referenced to this signal. In a delayed write or read-modify-write cycle, CAS will already
be low. Thus, the data will be strobed-in by W with data setup and hold times referenced to this signal.
The three-state output buffers provide direct TTL compatability (no pullup resistors required) with a fanout of
two Series 74 TTL loads. Data-out is the same polarity as data-in. The outputs are in the high impedance
(floating) state as long as CAS or TRG is held high. Data will not appear at the outputs until after both CAS and
TRG have been brought low. Once the outputs are valid, they remain valid while CAS and TRG are low. CAS
and TRG going high returns the outputs to a high-impedance state. In an early write cycle, the outputs are always
in the high-impedance state. In a register transfer operation (memory to register or register to memory), the
outputs remain in the high-impedance state for the entire cycle.
enhanced page mode
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows theTMS44C250 to operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as column address is valid rather than when
CAS transitions low. This performance improvement is referred to as "enhanced page mode." Valid column
address may be presented immediately after row address hold time has been satisfied, usually well in advance
of the falling edge of CAS. In this case, data is obtained after ta(C) max (access time from CAS low), if ta(CA)
max (access time from column address) has been satisfied. In the event thatcolumn addresses for the next page
cycle are valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence
of ta(C) or ta(CP) (access time from rising edge of CAS).
Enhanced page mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row address setup, row address hold, and address multiplex is thus
eliminated, and a memory cycle time reduction of up to 3 x can be achieved, compared to minimum RAS cycle
times. The maximum number of columns that may be accessed is determined by the maximum RAS low time
and page mode cycle time used. The TMS44C250 allows a full page (512 cycles) of information to be accessed
in read, write, or read-modify-write mode during a single RAS low period using relatively conservative page mode
cycle times.
refresh
A refresh operation must be performed to each row at least once every eight milliseconds to retain data. Since
the output buffer is in the high-impedance state (unless CAS is applied), the RAS-only refresh sequence avoids
any output during refresh. Strobing each of the 512 row addresses with RAS causes all bits in each row to be
refreshed. CAS can remain high (inactive) for this refresh sequence to conserve power.
CAS-before-RAS refresh
CAS-before-RAS refresh is accomplished by bringing CAS low earlier than RAS. The external row address is
ignored and the refresh address is generated internally.
GND
This pin is reserved for the manufacturer's test operation. It is an input and should be tied to system ground or
left floating (no connection) to ensure proper device operation.
IMPORTANT: GND is not connected internally to Vss.
TEXAS •
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8-7
TMS44C250
262 144 8Y 4·81T MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
Table 1. Functional Table
T
RAS FALL
ADDRESS
000-003
Y
p
Et
R
FUNCTION
CAS*
CAS
L
TRG
Vi
SE
RAS
CAS
RAS
Vi
X§
X
X
X
X
X
X
CAS-8efore-RAS Refresh
Tap
Point
X
X
Register to Memory Transfer
(Transfer Write)
T
H
L
L
"L
Row
Addr
T
H
L
L
H
Refresh
Addr
Tap
Point
X
X
Serial Write-mode Enable
(Pseudo-Transfer Write)
T
H
L
H
X
Row
Addr
Tap
Point
X
X
Memory to Register Transfer
(Transfer Read)
R
H
H
L
X
Row
Addr
Col
Addr
Write
Mask
Valid
Data
Load and use Write Mask,
Write Data to Dram
R
H
H
H
X
Row
Addr
Col
Addr
X
Valid
Data
Normal Dram Read/VVrite
(Non Masked) "
t R =Random access operation; T
=Transfer operation.
*000-3 are latched on the later of Wor CAS falling edge.
§ X = Don't care.
WRITE MASK = 1 write to I/O enabled.
random port to serial port interface
Random-access Port
Col
Col
511
o
Row
o
Memory Array
262,144 Bits
DO
Row
511
Transfer
Control
Logic
512 Bit Data Register
SC
AO-A8
Figure 1. Block Diagram Showing One Random and One Serial 110 Interface
TEXAS -1!1
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TMS44C250
262144 BY 4-BIT MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
random address space to serial address space mapping
The 512 bits in each of the four data registers of the SAM are connected to the 512 column locations of each
of the four random I/Os. Data can be accessed in or out of the SAM starting at any of the 512 data bit locations.
This start location is selected by addresses AD through AS on the falling edge of CAS during any transfer cycle.
The SAM is accessed starting from the selected start address, proceeding from the lowest to the highest
significant bits. After the most significant bit position (511) is accessed, the serial counter wraps around such
that bit Dis accessed on the next clock pulse. The selected start address is stored and used for all subsequent
transfer cycles until CAS is again brought low during any transfer cycle. Thus, the start address can be set once
and CAS held high during all subsequent transfer cycles and the start address point will not change regardless
of data present on AD through AS.
transfer operations
As illustrated in Table 1, the TMS44C25D supports three basic transfer modes of operation:
1.
2.
3.
Write Transfer (SAM to DRAM)
Pseudo Write Transfer (Switches serial port from serial out mode to serial in mode. No actual data transfer
takes place between the DRAM and the SAM.)
Read Transfer (Transfer entire contents of DRAM to SAM)
transfer register select (TRG)
Transfer operations between the memory array and the data registers are invoked by bringing TRG low before
RAS falls. The states of Wand SE, which are also latched on the falling edge of RAS, determine which transfer
operation will be invoked. (See Table 2.)
During read transfer cycles, TRG going high causes the addressed row of data to be transferred into the data
register. Although the previous data in the data register is overwritten, the last bit of data appearing at SDO before
TRG goes high will remain valid until the first positive transition of SC after TRG goes high. The data at SDO
will then switch to new data beginning from the selected start, or "tap," position.
transfer write enable (W)
In register transfer mode, W determines whether a read or a write transfer will occur. To perform a write transfer,
Wand SE are held low as RAS falls. If SE is high during this transition, no transfer of data from the data register
to the memory array occurs, but the SDOs are put into the input mode. This allows serial data to be input into
the SAM. To perform a read transfer operation, W is held high and SE is a Don't Care as RAS falls. This cycle
also puts the SDOs into the read mode, allowing serial data to be shifted out of the data register. (See Table 2.)
column enable (CAS)
If CAS is brought low during a control cycle, the address present on the pins AD through AS will become the new
register start location. If CAS is held high during a control cycle, the previous tap address will be retained from
the last transfer cycle in which CAS went low to set the tap address.
addresses (AD through AS)
Nine address bits are required to select one of the 512 possible rows involved in the transfer of data to or from
the data registers. The states of AD-AS are latched on the fallling edge of RAS to select one of 512 rows for the
transfer operation.
To select one of the 512 positions in the SAM from which the first serial data will be accessed, the appropriate
9-bit column address (AD-AS) must be valid when CAS falls. However, the CAS and start (tap) position need
not be supplied every cycle, only when changing to a different start position.
serial access operation
Refer to Tables 2 and 3 for the following discussion on serial access operation.
TEXAS "-!1
INSTRUMENTS
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TMS44C250
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
serial clock (SC)
Data (SOO) is accessed in or out of data registers on the rising edge of SC. The TMS44C250 is designed to
work with a wide range of clock duty cycles to simplify system design. Since the data registers comprising the
SAM are of static design, there are no SAM refresh requirements and there is no minimum SC clock operating
frequency.
serial data input/output (SOQO-SOQ3)
SO and SO share a common I/O pin. Data is input to the device when SE is low during write mode and data is
output from the device when SE is low during read mode. The data in the SAM will be accessed in the direction
from least significant bit to most significant bit. The data registers operate modulo 512. Thus, after bit 511 is
accessed, the next bits to be accessed will be bits 00, 01, 02, and so on.
serial enable (SE)
The Serial Enable pin has two functions: first, it is latched on the falling edge of RAS, with both TRG and W low
to select one ofthe transfer functions (see Table 3.) If SE is low during this transition, then a transfer write occurs.
If SE is high as RAS falls, then a write mode control cycle is performed. The function of this cycle is to switch
the SOOs from the output mode to the input mode, thus allowing data to be shifted into the data register. NOTE:
All transfer read and serial mode enable (pseudo transfer write) operations will perform a memory refresh
operation on the selected row.
Second, during serial access operations, SE is used as an SOO enable/disable. In the write mode, SE is used
as an input enable. SE high disables the input and SE low enables the input. To take the device out of the write
mode and into the read mode, a transfer read cycle must be performed. The read mode allows data to be
accessed from the data register. While in the read mode, SE high disables the output and SE low enables the
output.
IMPORTANT: While SE is held high, the serial clock is NOT disabled. Thus, external SC pulses will increment
the internal serial address counter regardless of the state of SE. This ungated serial clock scheme minimizes
access time of serial output from SE low since the serial clock input buffer and the serial address counter are
not disabled by SE.
Table 2. Transfer Operation Logic
TRG
W
SE
L
L
L
L
L
H
L
H
MODE
Register to memory (write) transfer
Serial write mode enable
Memory to register (read) transfer
X
NOTE: Above logic states are assumed valid on the falling edge of RAS.
Table 3. Serial Operation Logic
LAST TRANSFER CYCLE
Serial write mode enable t
Serial write mode enable t
Memory to register
Memory to register
SE
SDa
L
H
L
H
Input enable
Input disable
Output enabled
Hi-Z
tPseudo transfer write
power up
To achieve proper device operation, an initial pause of 200 ~s is required after power up, followed by a minimum
of eight RAS cycles or eight CAS-before-RAS cycles, a memory-to-register transfer cycle and two SC cycles.
TEXAS ~
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TMS44C250
262144 BY 4-BIT MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Voltage on any pin except DO and SDO (see Note 1) ..................................... - 1 V to 7 V
Voltage on DO and SDO (see Note 1) ................................................. - rv to Vee
Voltage range on Vee (see Note 1) ..................................................... a V to 7 V
Short circuit output current (per output) ..................................................... 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range ..................................................
to 70 0
Storage temperature range ....................................................... - 65°e to 150 0 e
ooe
e
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
VCC
Supply Voltage
ITMS44C250-1
ITMS44C250-1 0, TMS44C250-12
VSS
Supply voltage
VIH
Higt.-Ievel input voltage
VIL
Low-level input voltage (see Note 2)
VOH
High-level output voltage
VOL
Low-level output volage
TA
Operating free-air temperature
MIN
NOM
MAX
4.75
5
5.25
4.5
5
5.5
UNIT
V
V
0
2.4
VCC
-1.0
0.8
V
V
2.4
VCC
V
-1
0.4
V
0
70
°c
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
TEXAS
l.!1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
8-11
TMS44C250
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
electrical characteristics over full ranges of recommended operating conditions
PARAMETER
TEST CONDITIONS
TMS44C250-1
TMS44C250-10
MIN
MAX
MIN
UNIT
MAX
V
VOH
High level output voltage
10H =-5.0mA
VOL
Low level output voltage
10L = 4.2 mA
0.4
0.4
V
TMS44C250-10,
TMS44C250-12
VI = 0 V to 5.8 V, VCC = 5.5 V
All other pins = 0 V to VCC
±10
±10
itA
TMS44C250-1
VI = 0 Vto 5.55 V, VCC =5.25 V
All other pins =0 V to VCC
±10
±10
itA
10
Output leakage current
(see Note 3)
TMS44C250-10,
TMS44C250-12
Vo
= 0 V to VCC, VCC = 5.5 V
±10
±10
itA
10
Output leakage current
(see Note 3)
TMS44C250-1
Vo = 0 V to VCC, VCC
±10
±10
flA
IL
Input leakage current
PARAMETER
2.4
TMS44C250-12
=5.25 V
SAM PORT
TMS44C250-1
TMS44C2S0-10
MIN
ICCl
Operation current tc(RW) = Minimum
Standby
ICC1A
tc(SC) = Minimum
Active
2.4
MAX
TMS44C2S0-12
UNIT
MIN
MAX
90
80
110
95
ICC2
Standby current, All clocks = VCC
Standby
10
10
ICC2A
tc(SC) = Minimum
Active
35
35
=Minimum
Standby
90
80
110
95
Standby
50
45
Active
60
55
Standby
90
80
110
95
ICC3
RAS-only refresh current, tc(RW)
ICC3A
tc(SC) = Minimum
Active
ICC4
Page mode current, tc(P) = Minimum
ICC4A
tc(SC) = Minimum
ICC5
CAS-before-RAS current, tc(RW)
ICC5A
tc(SC)
ICC6
ICC6A
= Minimum
= Minimum
. Data transfer current, tc(RW)
Active
=Minimum
Standby
Active
tc(SC) = Minimum
NOTE 3: SE is disabled for SDa output leakage tests.
TEXAS
lJ1
INSTRUMENlS
8-12
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
90
80
110
95
mA
TMS44C250
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
capacitance over-recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 4)
MIN
PARAMETER
MAX
UNIT
Ci(A)
Input capacitance, address inputs
6
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write enable input
7
pF
Ci(SC)
Input capacitance, serial clock
7
pF
pF
Ci(SE)
Input capacitance, serial enable
7
Ci(TRG)
Input capacitance, transfer register input
7
pF
Co(O)
Output capacitance, SDO and DO
7
pF
NOTE 4: VCC equal to 5 V
±
0.5 V for TMS44C250-10, and TMS44C250-12; 5 V
±
0.25 V for TMS44C250-1, and the bias on pins under test
is OV.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
TEST
CONDITIONS
PARAMETER
ta(C)
Access time from CAS
tA(CA)
Access time from column address
ta(CP)
Access time from CAS high
ta(R)
Access time from RAS
ta(G)
Access time of
ta(SO)
Access time of SO from SC high
ta(SE)
Access time of SO from SE low
ALT.
SYMBOL
=MAX
=MAX
td(RLCL) = MAX
td(RLCL) =MAX
tdis(CH)
Random output disable time from TRG high
tdis(SE)
Serial output disable time from SE high
UNIT
MIN
MAX
ns
tCAC
25
30
tCM
50
60
ns
tCAP
55
65
ns
tRAC
100
120
ns
tOEA
25
30
ns
tSCA
30
35
ns
=50 pF
CL = 50 pF
CL = 100 pF
CL = 100 pF
CL = 50 pF
0
MAX
td(RLCL)
CL
tdis(G)
MIN
TMS44C250-12
td(RLCL)
a from TRG low
RanClom output disable time from CAS high
TMS44C250-1
TMS44C250-10
25
ns
tOFF
0
20
0
20
ns
tOEZ
0
20
0
20
ns
tSEZ
0
20
0
20
ns
20
tSEA
NOTE 5: Switching times assume CL = 100 pF unless otherwise noted (see Figure 2).
TEXAS •
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8-13
TMS44C250
262 144 BY 4·B1T MULTIPaRT VIDEO RAM
REV A- SMVS250-JUNE 1990- REVISED JANUARY 1991
timing requirements over recommended ranges of supply voltage and· operating free-air
temperature t
ALT.
SYMBOL
TMS44C250-1
TMS44C250-10
MIN
MAX
TMS44C2S0-12
UNIT
MIN
MAX
tc(rd)
Read cycle time (see Note 6)
tRC
190
220
ns
tc(W)
Write cycle time
twc
190
220
ns
tc(rdW)
Read·modify·write cycle time
tRWC
250
290
ns
tc(P)
Page-mode read, write cycle time
tpc
60
70
ns
tc(RDWP)
Page-mode read-modify-write cycle time
tRWC
105
125
ns
tc(TRD)
Transfer read cycle time
tRC
190
220
ns
tc(TW)
Transfer write cycle time
twc
190
220
ns
tc(SC)
Serial clock cycle time (see Note 7)
tscc
30
35
ns
tw(CH)
Pulse duration, CAS high
tcp
10
15
tw(CL)
Pulse duration, CAS low (see Note 8)
tCAS
25
tw(RH)
Pulse duration, RAS high
tRP
80
tw(RL)
Pulse duration, RAS low (see Note 9)
tRAS
100
tw(WL)
Pulse duration, W low
twp
25
25
ns
tw(TRG)
Pulse duration, TRG low
25
35
ns
tw(SCH)
Pulse duration, SC high
tsc
10
12.
ns
tw(SCL)
Pulse duration, SC low
tscp
10
12
ns
tsu(CA)
Column address setup time
tASC
0
0
ns
tsu(RA)
Row address setup time
tASR
0
0
ns
tsu(WMR)
W setup time before RAS low
tWSR
0
0
ns
tsu(DOR)
DO setup time before RAS low
tMS
0
0
ns
tsu(TRG)
TRG setup time before RAS low
tTLS
0
0
ns
tsu(SE)
SE setup time before RAS low
tESR
0
0
ns
tsu(DCL)
Data setup time before CAS low
tDSC
0
0
ns
tsu(DWL)
Data setup time before W low
tDSW
0
0
ns
tsu(rd)
Read command setup time
tRCS
0
0
ns
tsu(WCL)
Early write command setup time before CAS low
twcs
-5
-5
ns
tsu(WCH)
Write setup time before CAS high
tCWL
25
30
ns
tsu(WRH)
Write setup time before RAS high with TRG = W = low
tRWL
25
30
ns
tsu(SDS)
SO setup time before SC high
tSDS
3
3
ns
th(CLCA)
Column address hold time after CAS low
tCAH
20
20
ns
th(RA)
Row address hold time after RAS low
tRAH
15
15
ns
75000
30
ns
75000
90
75000
120
ns
ns
75000
ns
Continued next page.
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 6. All cycle times assume tt = 5 ns.
7. When the odd tap is used (tap address can be 0-511, and odd taps are 1,3,5, etc.), the cycle time for SC in serial data out cycle needs
to be 50 ns minimum.
8. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user's transition times, this may require
additional CAS low time [tw(CL)j.
9. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user's transition times, this may require
additional RAS low time [tw(RL)j.
TEXAS •
INSlRUMENTS
8-14
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44C250
262 144 BY 4-BIT MULTIPORT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)t
TMS44C250-1
ALT.
TMS44C250-10
SYMBOL
MIN
MAX
TMS44C250-12
UNIT
MIN
MAX
th(TRG)
TRG hold time after RAS low
tTLH
15
15
ns
th(SE)
SE hold time after RAS low with TRG = W = low
tREH
15
15
ns
th(RWM)
Write mask, transfer enable hold time after RAS low
tRWH
15
15
ns
th(RDO)
DO hold time after RAS low (write mask operation)
tMH
15
15
ns
th(RLCA)
Column address hold time after RAS low (see Note 9)
tAR
45
45
ns
ns
th(CLD)
Data hold time after CAS low
tDH
20
25
th(RLD)
Data hold time after RAS low (see Note 10)
tDHR
45
50
ns
th(WLD)
Data hold time after W low
tDH
20
25
ns
th(CHrd)
Read hold time after CAS (see Note 11)
tRCH
0
0
ns
th(RHrd)
Read hold time after RAS (see Note 11)
tRRH
10
10
ns
th(CLW)
Write hold time after CAS low
twCH
25
30
ns
th(RLW)
Write hold time after RAS low (see Note 10)
twCR
50
55
ns
th(WLG)
TRG hold time after W low (see Note 12)
tOEH
25
30
ns
th(SDS)
SD hold time after SC high
tSDH
5
5
ns
th(SHSO)
SO hold time after SC high
tSOH
10
10
ns
td(RLCH)
Delay time, RAS low to CAS high
tCSH
100
120
ns
td(CHRL)
Delay time, CAS high to RAS low
tCRP
0
0
. ns
td(CLRH)
Delay time, CAS low to RAS high
tRSH
30
35
ns
td(CLWL)
Delay time, CAS low to W low (see Notes 13 and 14)
tCWD
55
65
ns
td(RLCL)
Delay time, RAS low to CAS low (see Notes 15 and 16)
tRCD
25
td(CARH)
Delay time, column address to RAS high
tRAL
50
60
td(RLWL)
Delay time, RAS low to W low (see Note 13)
tRWD
130
155
ns
td(CAWL)
Delay time, column address to W low (see Note 13)
tAWD
85
100
ns
td(RLCH)
Delay time, RAS low to CAS high (see Note 11)
tCHR
25
25
ns
td(CLRL)
Delay time, CAS low to RAS low (see Note 17)
tCSR
10
10
ns
td(RHCL)
Delay time, RAS high to CAS low (see Note 17)
tRCP
5
5
ns
td(CLGH)
Delay time, CAS low to TRG high
tCTH
25
35
ns
25
30
ns
tRTH
90
95
ns
td(GHD)
Delay time, TRG high before data applied at DO
td(RLTH)
Delay time, RAS low to TRG high
75
25
90
ns
ns
Continued next page.
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 9. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user's transition times, this may require
additional RAS low time [tw(RL)l.
10. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
11. Either th(RHrd) or t(CHrd) must be satisfied for a read cycle.
12. Output enable controlled write. Output remains in the high-impedance state for the entire cycle.
13. Read-modify-write operation only.
14. TRG must disable the output buffers prior to applying data to the DO pins.
15. Read cycles only.
16. Maximum value specified only to guarantee RAS access time.
17. CAS-before-RAS refresh operation only.
TEXAS
-I!I
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-15
TMS44C250
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)t
ALT.
SYMBOL
TMS44C250-1
TMS44C250·10
MIN
MAX
TMS44C250-12
UNIT
MIN
MAX
td(ALSH)
Delay time, RAS low to first SC high after TAG high (see Note 18)
tRSD
130
135
td(CLSH)
Delay time, CAS low to first SC high after TAG high (see Note 18)
tCSD
40
45
ns
td(SCTA)
Delay time, SC high to TAG high (see Notes 18 and 19)
tTSL
10
15
ns
td(THAH)
Delay time, TRG high to RAS high (see Note 18)
tTAD
-10
-10
ns
td(SCAL)
Delay time, SC high to AAS low with TAG
(see Notes 20 and 21)
tSAS
10
10
ns
=W =low
ns
td(SCSE)
Delay time, SC high to SE high in serial input mode
20
20
ns
td(AHSC)
Delay time, RAS high to SC high (see Note 21)
tSAD
25
30
ns
td(THAL)
Delay time, TAG high to RAS low (see Note 22)
tTAP
td(THSC)
Delay time, TAG high to SC high (see Note 22)
tTSD
35
td(SESC)
Delay time, SE low to SC high (see Note 23)
tsws
10
trf(MA)
Aefresh time interval, memory
tAEF
tt
Transition time
tT
tw(AH)
40
ns
15
8
3
ns
tw(AH)
50
3
ns
8
ms
50
ns
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 18. Memory to register (read) transfer cycles only.
19. In a transfer read cycle, the state of SC when TRG rises is a Don't Care condition. However, to guarantee proper sequencing of the
internal clock circuitry, there can be no positive transitions of SC for at least 10 ns prior to when TRG goes high.
20'. In a transfer write cycle, the state of SC when RAS falls is a Don't Care condition. However, to guarantee proper sequencing of the
internal clock circuitry, there can be no positive transitions of SC for at least 10 ns prior to when RAS goes low.
21. Aegister to memory (write) transfer cycles reserved only.
22. Memory to' register (read) and register to memory (write) transfer cycles only.
23. Serial data-in cycles only.
PARAMETER MEASUREMENT INFORMATION
1.31 V
218 Q
Load Circuit
Figure 2. Load Circuit
TEXAS •
INSlRUMENTS
8-16
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TMS44C250
262 144 BY 4-BIT MULTIPORT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
read cycle timing
I..
RAS
,
CAS
~
,
j 4 - td(CLRH)
,
,
,
1
1
~
,
,
i
f4- th(RA)
i '\
1
,
II~th(RLCA)
I
AD-AS
JJ1U
td(RLCH)
}
H
t
1
SU(CA)
-.I
Row
TRG2l&¥
!
I
~
1
;
1
1
.,
I
., th(CLCA)I"
~
I
t
"
I
·1
'---------
I.-
I ~I:I
'w(TRG)
i ~
!
1 ~ I ~ th(RHrd)
l"(e"'d) I'
jl
i
,=
1
1
,I,~
W
,
,
I,
'14-
:
!
'
,..
j4-- t~ls(CH) - - . I
ta(G) ---.:
14- tdls(G) -.:
~-----~
~
Valid
J>-------
~ta(C)-J
1
:
I
1
1
,
DQ
I
I'
:
~
-.I
I \...._ _
~W(CH)
_
tsu(rd)
}-
'
~td(cLGH)~1
i ~\l
I
,
-I :
I
~ tsu(TRG)
l->j
H
I~
c c~lumn
~
--'1
,
~
J.-- tw(RH) --.l ,-,- - - - -
,
'
.1
td(CHRL) - - - . j
tw(CL) - . . .,.._+1_ _ _ _ _ _----..
I'
1
i
.1
tw(RL)
-4l
tsu(RA) -.j
.1
tc(rd)
i I..
- - -.....N ,r"
,
I"
-I
ta(CA)
ta(R)
_,
TEXAS
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INSlRUMENTS
POST OFFICE BOX 1443
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8-17
TMS44C250
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
early write cycle timing
I"
_ _ _~I
N
RAS
tt
l
I I..
I I
~I
~I
,..
I ~ td(RLCL) ~..
I I I
II
-t+I ~th(RA) I
I ~ th(RLCA)
r
I
Vi
I rtw(RH)
td(CLRH)
tw(CL)
I:i~1
I
I I" I
~I
tw(CH)
A~A8 ~ ~mn ~'I...
tsu(TRG)
-+I I4-l--
,
I -41 ~ th(TRG)
,.11
TRG
I I I
I I I
-41 l4-'t su (W;;;
I I
I..
I I
I..
I I..
I
I I
I
th(RWM)
I+I
M
W
~
J4f
I
I
tsu(OOR)
-+t
I
1
I
I
I
I
I
I
I
I
I
I"
I
I
I
I
I
,
~I
tsu(WCH)
tsu(WRH)
th(RLW)
~I
r-
I
~I
~:
th(CLW)
~tsU(WCL)
I I
i+f
I"
I
OO~
~II
~I
h(CLO)
I
th(RLO)
3
NOTE 24: See "Write Cycle State Table" for the logic state of "1", "2", and "3",
TEXAS
~
INSTRUMENTS
8-18
I
I
~I~----------------------~~~~~~
I I I
I
I" I I
tw(WL)
~I
ItsU(OCL) -+II
t
~I
I
I
th(R~Q) ~ ..
I
i
I
I I
I I
POST OFFICE BOX 1443
•
4
~
I -+I I.- tt
I
I ~I I
I
~I j4----l- td(CHRL) --+I
I
I
td(RLCH)
r
N'
CAS
~I
tc(W)
tw(RL)
I..
HOUSTON, TEXAS 77001
~
I
I
~I
_ _ _ _ __
TMS44C250
262144 BY 4-BIT MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
delayed write cycle timing
14!4---..,.-----------tC(W) ------------~.!
I 1 1 4 - 1 I I - - - - - - - - - tW(RL) _ _ _ _ _ _ _ _ _~.I
!
Y':
------~~
~
4
r
I 1111
.1 I
tw(RH)
I I..- - - - - - - - td(RLCH) -------~I -.I I.- tt
I
tt ---+I 14-.
114-111------ td(CLRH) -------.1-+-1~.I
I
I 14- td(RLCL) --I~*,IIIIf------ tw(CL) - - - - -...1 I4--l- td(CHRL) ~
I I
I
I
th(RA)
'sU(RA)-->j
AO·AS
~
14I ~
~
1\!
IX
th(RLCA)
,'su(CA)"":
~
!
I I I
-+I
tsu(TRG)
n
I
'+
I
I 1111 I
.1
"\
:' -
tc(W) ----+1.1
~'I
'~I
-.
mn
I
I
-Vi
~,-,-----I
I
I
I
NOTE 24: See "Write Cycle State Table" for the logic state of "1", "2", and "3",
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-19
TMS44C250
262144 BY 4-BIT MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
write cycle state table
STATE
CYCLE
1
2
Write mask load/use
Write DOs to I/Os
L
Write
Mask
Valid
Data
Normal early or late
Write operation
H
Don't
Care
ValidData
TEXAS ~
INSTRUMENTS
8-20
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
3
TMS44C250
262144 BY 4-BIT MULTIPaRT VIDEO RAM
REV A- SMVS250-JUNE 1990 - REVISED JANUARY 1991
read-wrlte/read-modify-write cycle timing
I..
I
I I'll
tc(rdW) -------------~.I
---:liN·
I
tW(RL) -----------~~I
~
I
I I
I'll
IOt1
2QO':
:
I
'\
\
I
tsu(WMR) --;
W
J.-C
.1
1
I!
th(RWM)
I
I
I
.
22M
I
..
:Jill
I'
2
.. I
td(CAWL)
~
~
~I
(:
th(RLW)
I
I~
t
I
I
I
i
h(WL
i
I
I+- td(GHD)
td(RLWL)
G)'
ta(R)
I
~:
~.a(c) I
-.j
ie
~
~ tW(WL)
i'~
~ ~
~ r
"""'I
~ ov:,~~; ~
ta(G)
=
~!I ~
~~~~~~~~~
I
I I
I I
"I
I
~ tsu(WRH) ~
I I
,
th(CLW)
td(C~WL)
III
22M ::' ~ L.JA)~
'SU(DOR)->j
DO
~II
~ tsu(WCH) - - ;
I
I
I
I I I..
tsu(TRG) -+I
~I $e
I
.. I
-..J
~
-J
th(WLD)
l+--'su(DWl)
3
1
1
~
+I!+-- tdis(G)
!+-
NOTE 24: See "Write Cycle State Table" for the logic state of "1", "2", and "3", Same logic as delayed write cycle,
TEXAS
J!1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-21
TMS44C250
262 144 BY 4-81T MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
enhanced page-mode read cycle timing
tW(RH)
141~-----------,-----tw(RL)
'4
1
,
~
14I
I
W"U(RA)
, 1 14
1
\x If
1
td(CHRL)'
I~!
1
i1
.1, 1
tc(P)
i, : ~ th(RA) --+i
4 ' ---+l,
~
~ td(CLRH)
td(RLCL)
, I t + -tw(CH) 4
CAS
I
~
RASi'-l
,
-.l
I
.,
i
':
td(CARH) - - ; - - - - . t
~~~~~~
Column
AO-A8
1
1
,
1
H 4 tsu(TRG)
tl
TRG
W *t
-.l
W-
14
1 1
, 1
.
I
I
.1 th(TRG)
1
1
,
,
,
1
'
, X
! \ 'I ,,
\
,
tsu(WMR) ,
1
tsu(rd) ,
I
1
I
1
1
! th(RHrd)
~·--~,-+,--~--------~,------~'------------~I
1
~
I'
I '
1 .,
I '
~th(CHrd)
IWI
II
I
I
~
14-
-.j
"<@
NOTE 25: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
TEXAS •
INSlRUMENTS
8-22
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44C250
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
enhanced page mode write cycle timing
N
I
1l1li
I
1l1li
,
:
td(RLCH)
td(RLCL)
tw(CL)
U
r',
~
---+II
t
su(RA)
tsu(CA)
r
Row
tc(P)
'+- tw(CH) ~
I
I
,L
~
!
!
r
1
r
r \ AI'XIt-.
,
,
A,'
ta(CLCA)
J
~
Column
td(CARH)
l1li
w=X
:
1
DQ
:
1
IVV'hvvvvvv '
,
,
I
I
,
~ tsu(WCH) ~
r'
___J0<
=X~_2
~
,
i'SU(W,RH)-.j
11111:'-~: tsU(~th(CLD)t i
14- th(RDQ) -+l
,
I,
1
'
:. ~~
j@hl:
tsu(DWL)t
tsu(WCH)
:--r'W(WL1---:
:'h(RWM) --.:
~
-.J
'!'
l4-;tsU (WMR)
1l1li
1
~
I I
tsu(DQR) --.{
I,
r \
Column
tsu(TRG)
XX!T , 1
'&Y , I
-+I
I
1
'I 1
I
~I 1
1
1++
1
~ td(CL,RH) -.l 1
1
1
~ td(CHRL) ~
\\1
~I
I ~I
1l1li
th(RLCA)
r
1
Yrl\-
~I
1
!\\l 0,
-.J
J0<
r r
,
~1
1l1li
I
I I t+- th(RA) ---+I
I , 1l1li
I
I
AQ-AB
~IIIII
~I
.
-..l
~I
tw(RL)
1l1li
th(WLD) t
1l1li
th(RLD)
~I
~I
3
~,--_3--J~
t Referenced to CAS or Vi, whichever occurs last.
NOTES: 24. See "Write Cycle State Table" for the logic state of "1", "2", and "3".
26. A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing
specifications. TRG must remain high throughout the entire page-mode operation if the late write feature is used, to guarantee
page-mode cycle time. If the early write cycle timing is used, the state ofTRG is a Don't Care after the minimum period th(TRG) from
the falling edge of RAS.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-23
TMS44C250
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
REV A- SMVS250-JUNE 1990- REVISED JANJARY 1991
enhanced page-mode read-modify-write cycle timing
~14-------------------------tw{R~--------------------------~~1
RAS
~I
I
~i
I~
}I
I
I ~I--------------------------------------------------- I
I
I ~
td(RLCH)
~I
tw{RH) ~
I I
1"4
tc{RDWP)
1
.. ,
J.4- t d(CLRH)
~I
I
CAS
tSU{RA)
~
:
~td{RLC~ ~~tW{CL) ~ ~tW(fH)
:
I
i+-L
th(RA)'--.J
~
I~
It
~
~
CA I
su{
I ~th(5L~:A)
AO-A8
I
Row
~
I
Yf [\\l
~ ~
J
)~th{CLCA)
:
td{CHRL)
I
I:
I
I
I
I
I
I:::
~
~column~
.
G
U
JooI
II
I
WI11
-.r
I
I
k-l
1 .1 I tsu{RD)
j 4 - td{CLW~
r:1I!i
I
Itsu{DOR)
I
~: f4
~d(RLWL)
·1 I
I
I
III
jet- th(RDO)
~I
I
I
ta{CA) t
tSU{DWL)
'
~
I
~I
I
I
tw(WL)
I
I
tsu(WRH)
NJ
I Y
I I
1111
I
-4114- ta{C)
I
I
tsu(WCH) ~
-.r
td{CAWL)
~I
~
Column
III
tsu(WMR)..J.-.j I
I I
I
th{RV{M) j+I
H
I
I
I
I"
~ 14I
I
I
~I
J..- t
!
1111
\. !I
"\
I
I
~I
!?XXXXYV\
~
'"-_-I.t.~~~~~
th(WLD)
(CP) t
-+j. r - -__""'lL
DO
J..I
I I 14- ta(G) -+I
______I..~I : ta(R) ~
~"____
141~---.t- td(GHD)
~I_____________
,
~ tdls(G)
rl___________________
\J
__JI
t Output may go from the high-impedance state to an invalid data state prior to the specified access time.
NOTES: 24. See "Write Cycle State Table" for the logic state of "1 ", "2", and "3".
27. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not
violated.
TEXAS
~
INSTRUMENTS
8-24
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44C250
262 144 BY 4-81T MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
RAS-only refresh timing
14-111------ tc{rd) --------..!~I
1
RAS
I+--- tw{RL) --~~,
----------------------------~f\t
I rtW(RH)~
I I
-.J
r--
, I
CAS
AD·AS
tt
tt
---.j
I *11II-___~+-1-JooII:IIII--+l~1 I
I
~
~o~
,
I
~I
,III
tsu{TRG)
'III
~
I
.~
:
tsu(RA)
1
~
th{RA)
~I.....---RO_W
~,
,
_
th{TRG)
Vi
DQ
CAS-before-RAS refresh
1111
IT
-----I
1111
~I
tc{rd)
I+--
~I
,
t4-
~
Y------
tw{RL) ---~~,
N
tw{RH) - . j
td(RHCL)
td{CLRL)
'III
I
I """I--------------------~
I I
+j J+-- td(RLCH) ~
I~-----------
Vi
DQ
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-25
TMS44C250
262 144 BY 4-81T MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
hidden refresh cycle timing
~ MEMORY CYCLE ~ REFRESH CYCLE --+I
tw(RH)
I..
~l
/011
~I I
I
I
tW(RL)
I
~:.- REFRESH CYCLE ---..j
tw(RH) lOll
lOll
I
I
~I
I tw(RL)
I
I
I
I
~
~ _ _T
td(RLCH)
AQ-AS
DQ
TEXAS
~
INSIRUMENTS
8-26
POST OFFICE BOX 1443
;--VIH
"------I
I
•
HOUSTON. TEXAS 77001
lOll
~I
VIL
TMS44C250
262 144 BY 4-81T MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
write-mode control pseudo write transfer timing
The write-mode control cycle is used to change the SOQs from the output mode to the input mode. This allows
serial data to be written into the data register. The diagram below assumes that the device was originally in the
serial read mode.
14
14
tw(RL)
1
r-td(RLCL)
~
---~N
I
1
I
14
td(RLCH)
-.!
I
I
1
!
Ie
0
1
1-
~
th(RA)
I
'h(RLCA):
1
7\11
tw(CL)
VIH
VIL
1
:
~0~
}
~I
'I
1:4
"'-----
~I
I
~ tsu(RA)
~
1
:
Nf+-~
iI
I
~I
i
1
I
~I
tc(TW)
I
I
1
VIH
I
- 1
th(CLCA) 1
VIL
I.
~
I
A~A. ~ ~+ ~ ~Olumn ~grk~z/fXXXXXXX:::
1
I
tsu(TRG) ~
TRG
~ th(TRG)
1
1
1
~
:.- t
td(THRL)
~ ! i ~EHgH~
1
I
tsu(WMR) ~
1
WE~
I
I
114
II
~II
~ tW(SCH) 04i
td(SCRL)
14
~I I I
1
SC-./
I
:
VIH
14
III
! i\\\\\\\\\
Data
Out
I
I
1
1
I
1
:::
~~I
th(RWM)
tw(SCL)
I 1
soa
~I
1
14
su(CA) ~
14
tsu(SOS) ~
VIL
~I
td(RHSC)
~I_ _---...
~
~
1_-'
\~_:::
L..m
roo- th(SOS)
I
tdls(SE) ~ ~+-.!
tsu(SE) 14
~I
SE
§§§§W
VIH
NOTES: 28. Random-mode Q outputs remain in the high-impedance state for the entire write-mode control.
29. SE must be high as RAS falls in order to perform a write-mode control cycle.
TEXAS ~
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-27
TMS44C250
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
data register to memory timing, serial input enabled
14
1111
tw(RL)
I4-td(RLCL) ~
,
1
---~N
I
AO-AS
td(R~CH)
tsu(TRG)
TRG
-i4-14-"'~1
w~
tsu(CA)
~I
~:
~I
!\
tw(RH)
----.J '----
I
1
1
IV
N
th(CLCA)
1
1
1
1
1
1
1
' .
1
~ Column ~Hn2RH_
!.- th(TRG) -+l
1 14
~I I
I
I!
I I
I I
DO
,
~lth(RWM)
14-1 td(THRL) -.j
I
?
~gf4RH~
1
,
1 1
td(SCRL)
td(RHSC)
..
~I 11~4-----J~>t--11 tw(SCH)
14
I
I
1
1
1
1
.{
I
1
I
1
lA
,
I
1
:
I
1
--../1
th(~DS)~
2M
HI-Z - - - - - - - ! - I - - - - - - - - - - -
I I
---l+---~
'III
..
~ ~tSU(SDS) I'
SOO
~I
,
~,,~
~114
SC
1
~tw(CL)
-~IIII-...~1! 1
1 1
I
I ~ th(RA) -+I
--.l ~
I
I 14
t~(RLCA)'
1
I
1 1
1
I 14
~ : ~ow
11:r-
1
14
1
I
~I
1
I
I:
tSU(RA)
~I
tc(TW)
I
I
1
(see Note 32)
\
~:
"-tW(SCL)~:..4--l~~I-th(SDS)
tsu(SDS)
---+l t.-+
I
D,~a ~ '~~~a ~
tsu(SE) - . :
~ th(SE) ~I
14-1. td(SESC)----+!
r"'
;'----~~~~~~~
I
NOTES: 30. Random mode Q outputs remain in the high-impedance state for the entire data register to memory transfer cycle. This cycle is used
to transfer data from the data register to the memory array. Every one of the 512 locations in each data register is written into the
corresponding 512 columns of the selected row. Data in the data register may proceed from a serial shift-inor from a parallel load
from one ofthe memory array rows. The above diagram assumes that the device is in the serial write mode (i.e., SO is enabled by
a previous write mode control cycle, thus allowing data to be shifted-in).
.
31. Successive transfer writes can be performed without serial clocks for applications requiring fast memory array clears.
32. SC transitions are not allowed between RAS low and TRG high.
33. For multiple transfer write operation; a transfer read cycle needs to be done from the same row after the first transfer write is carried
out, then do multiple transfer write for subsequent rows.
TEXAS
-III
INSTRUMENTS
8-28
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44C250
262 144 BY 4-81T MULTIPORT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
memory to data register transfer timing
AO·A8
w
222W'
14- tw(SCH)
1
1
iT
SC
_ _ _. I
1
~
th(SHSQ)
14
Old Data
SDQ
td(SCTR)
1I
14
\
t.- ta(SQ) -+l
I
~Hh*g~
~I
~I
i
I
~i I
1
1
14
M
14
1
1
14
~ td(CLSH) ----+I
I td(RLSH)
~I
I
Vi
\
I
1
I
~I
td(THSC)
14
r
tw(SCL)
X
Old Data
th(SHSQ)
tc(SC) ------+1111
ta(SQ) ---.j
til I
MJI'",---N-ew-D-a-ta---
14
Old Data
H
L
NOTES: 34. Random mode (a outputs) remain in the high-impedance state for the entire memory to data register transfer cycle. The memory
to data register transfer cycle is used to load the data registers in para"el from the memory array. The 512 locations in each data
register are written into from the 512 corresponding columns of the selected row. The data that is transferred into the data registers
may be either shifted out or transferred back into another row.
sa
is enabled), thus allowing data to
35. Once data is transferred into the data registers, the SAM is in the serial read mode (i.e., the
be shifted out of the registers. Also, the first bit to be read from the data register after TRG has gone high must be activated by a
positive transition of SC.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-29
TMS44C250
262144 BY 4·BIT MULTIPaRT VIDEO RAM
REV A -
SMVS250 -
JUNE 1990 -
REVISED JANUARY 1991
serial data-in timing
I"
tc(SC)
I . - tw(SCL) - . !
sc
~I
~ tw(SCH) ~ I . - tw(SCL) - . l
~ tsu(SOS) --.J ~!
I
soo
\l
~Y:
--
~
V'"dO"':
~ th(SOS)
11
~ tsu(SOS) --+l ~_
~
..
L
t
~ h(SDS)
I
V,IIdO",
~
I
~td(SESC)~
\{~--------------------------------------------------
The serial data-in cycle (SO) is used to input serial data into the data registers. Before data can be written into
the data registers via SO, the device must be put into the write mode by performing a write mode control, or
pseudo-transfer, cycle. Transfer write cycles occurring between the write mode control cycle and the subsequent
writing of data will take the device out of the write mode. However, a transfer read cycle during that time will take
the device out of the write mode and put it into the read mode, thus disabling the input of data. Data will be written
starting at the location specified by the input address loaded on the previous transfer cycle.
While accessing data in the serial data registers, the state of TRG is a Don't Care as long as TRG is held high
when RAS goes low to prevent data transfers between memory and data registers.
serial data-out timing
I..
I
sc
14-- tw(SCH) ~ I
I
I
if
~
t+- th(SHSO) ~
<
SOO
~I
tc(SC)
j+--tw(SCL)·-.I
~tW(SCL)-.I
'\
~ta(SO)--M
)(
I
--.j
SE
NOTES:
~~:
Y:I.-
"ta(SO)
----+I
x=
I
~ ta(SE)
_______________________________________________________________
7. When the odd tap is used (tap addresses can be 0-511, and odd taps are 1,3,5 ... etc.), the cycle time for SC in serial data out cycle
needs to be 50 ns minimum.
36. While reading data through the serial data register, the state of TRG is a Don't Care as long as TRG is held high when RAS goes
low. This is to avoid the initiation of a register to memory or memory to register data transfer operation.
The serial data-out cycle is used to read data out of the data registers. Before data can be read via sa, the device
must be put into the read mode by performing a transfer read cycle. Transfer write cycles occurring between
the transfer read cycle and the subsequent shifting out of data will not take the device out of the read mode. But
a write mode control cycle at that time will take the device out of the read mode and put it in the write mode, thus
not allowing the reading of data.
TEXAS -III
INSTRUMENlS
8-30
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44C251
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SMVS251 F - AUGUST 1988 -
This Data Sheet Is Applicable to All
TMS44C251 s Symbolized With Revision "I" and
Subsequent Revisions as Described on Page
8-71.
REVISED DECEMBER 1990
so Package t
DZ Package t
(Top View)
SC
SDQD
SDQ1
TRG
DQD
DQ1
• DRAM: 262 144 Words x 4 Bits
SAM: 512 Words x 4 Bits
• Dual Port Accessibility - Simultaneous
and Asynchronous Access from the DRAM
and SAM Ports
W
NC/GND
RAS
A8
A6
A5
A4
• Bidirectional Data Transfer Function
Between the DRAM and the Serial Data
Register
• 4 x 4-Block Write Feature for Fast Area Fill
Operations. As Many as Four Memory
Address Locations Written Per Cycle From
an On-Chip Color Register
VCC
(Top View)
VSS
SDQ3
SDQ2
SE
DQ3
DQ2
DSF
CAS
QSF
AD
A1
A2
A3
A7
tThe packages shown here are for pinout reference only
and are not drawn to scale.
• Write-Per-Bit Feature for Selective Write to
Each RAM I/O. Two Write-Per-Bit Modes to
Simplify System Design
PIN NOMENCLATURE
AO-AS
CAS
DQO-DQ3
SE
RAS
SC
SDQO-SDQ3
TRG
• Enhanced Page Mode Operation for Faster
Access
• CAS-Before-RAS and Hidden Refresh
Modes
• RAM Output Enable Allows Direct
Connection of DQ and Address Lines to
Simp!ify System Design
W
DSF
QSF
VCC
VSS
NC/GND
• Long Refresh Period ... Every 8 ms (Max)
• DRAM Port Is Compatible with the
TMS44C256
Address Inputs
Column Enable
DRAM Data In-Out/Write Mask Bit
Serial Enable
Row Enable
Serial Data Clock
Serial Data In-Out
Transfer Register/Q Output Enable
Write Mask Select/Write Enable
Special Function Select
Split-Register Activity Status
5-V Supply
Ground
No Connect/Ground (Important:
not connected to internally to VSS)
• Performance Ranges:
• Up to 33 MHz Uninterrupted Serial Data
Streams
Vee±5%
ACCESS ACCESS ACCESS ACCESS
TIME
TIME
TIME
TIME
ROW COLUMN SERIAL SERIAL
ADDRESS ENABLE
DATA
ENABLE
(MAX)
(MAX)
(MAX)
(MAX)
ta(R)
ta(C)
ta(SQ)
ta(SE)
• Split Serial Data Register for Simplified
Realtime Register Reload
• 3-State Serial I/Os Allow Easy Multiplexing
of Video Data Streams
TMS44C251 -1
• 512 Selectable Serial Register Starting
Locations
100 ns
Vee
TMS44C251-10
TMS44C251-12
• All Inputs and Outputs TTL Compatible
100 ns
120ns
25 ns
±
30 ns
20 ns
30 ns
35 ns
20 ns
25 ns
10%
25 ns
30 ns
• Texas Instruments EPIC ™ CMOS Process
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA documents contain Information current
IS of publication date. Products conform to speclflcatlons per
the terms 01 Texas Instruments standard warranty.
Production processing does not necessarily Include testing
ol.Jlparameters.
TEXAS
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S·31
TMS44C251
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
description
The TMS44C251 multiport video RAM is a high speed, dual ported memory device. It consists of a dynamic
random-access memory (DRAM) organized as 262 144 words of 4 bits each interfaced to a serial data register,
or Serial Access Memory (SAM) ,',organized as 512 words of 4 bits each. The TMS44C251 supports three basic
types of operation: random access to and from the DRAM, serial access to and from the serial register, and
bidirectional transfer of data between any row in the DRAM and the serial register. Except during transfer
operations, the TMS44C251 can be accessed simultaneously and asynchronously 'from the DRAM and SAM
ports .. During transfer operations, the 512 columns of the DRAM are connected to the 512 positions in the serial
data register. The 512 x 4 bit serial data register can be loaded from the memory row (transfer read), or else
the contents of the 512 x 4 bit serial data register can be written to the memory row (transfer write).
The TMS44C251 is equipped with several features designed to provide higher system-level bandwidth and
simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel draw rates can
be achieved by the device's 4 x 4 Block Write mode. The Block Write mode allows four bits of data present in
an on-chip color data register to be written to any combination of four adjacent column address locations. As
many as 16 bits of data can be written to memory during each CAS cycle time. Also on the DRAM port, a write
mask register provides a persistent write-per-bit mode without repeated mask loading.
On the serial register, or SAM port, the TMS44C251 offers a split-register transfer read (DRAM to SAM) option,
which enables realtime register reload implementation for truly continuous serial data streams without critical
timing requirements. The register is divided into a high half and a low half. While one half is being read out of
the SAM port, the other half can be loaded from the memory array. This new realtime register reload
implementation allows truly continuous serial data. For applications not requiring realtime register reload (for
example, reloads done during CRT retrace periods), the single register mode of operation is retained to simplify
design. The SAM can also be configured in input mode, accepting serial data from an external device. Once the
serial register within the SAM is loaded, its contents can be transferred to the corresponding column positions
in any row in memory in a single memory cycle.
The SAM port is designed for maximum performance. Data can be input to or accessed from the SAM at serial
rates up to 33 MHz. During a split-register mode of operation, internal circuitry detects when the last bit pOSition
is accessed from the active half of the register and immediately transfers control to the opposite half. A separate
open-drain output, deSignated QSF, is included to indicate which half of the serial register is active at any given
time in the split register mode.
All inputs, outputs, and clock signals on the TMS44C251 are compatible with Series 74 TTL. All address lines
and data-in are latched on-chip to simplify system design. All data-outs are unlatched to allow greater system
flexibility.
The TMS44C251 employs state-of-the-art Texas Instruments EPIC™' scaled-CMOS, double-level
polysilicon/polycide gate technology for very high performance combined with low cost and improved reliability.
The TMS44C251 is offered in a 28-pin small-outline J-Iead package (DZ suffix) for direct surface mounting in
rows on 400-mil (5,08-mm) centers. It is also offered in a 400-mil, 28-pin zig-zag in-line package (SO suffix). Both
packages are characterized for operation from O°C to 70°C (L suffix).
The TMS44C251 and other Multiport Video RAMs are supported by a broad line of graphics processor and
control devices from Texas Instruments, including the TMS34020 Graphics System Processor.
TEXAS JJ}
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262144 BY 4·BIT MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
functional block diagram
o
B
u e
r-II--I--+-t t r
DOD
001
002
003
. - 0 vcc
. - 0 vss
o--+-HH
~ AD
Al
A2
A3
A4
AS
A6
~ A7
~ AS
.-0
.-0
.-0
.-0
.-0
.-0
OSF 0 - - - - - 1
u e
t r
SOOD
SOOl
S002
S003
0--+--1--1----.
T e
I n
me
I r
B
a
n t
9 0
OSF
Detailed Pin Description vs Operational Mode
PIN
DRAM
TRANSFER
AO-AS
Row, Column Address
Row, Tap Address
CAS
Column Enable, Output Enable
Tap Address Strobe
DQi
DRAM Data I/O, Write Mask Bits
DSF
Block Write Enable
Split-Register Enable
Persistent Write-per-Bit Enable
Alternate Write Transfer Enable
SAM
Color Register Load Enable
Write-per-Bit Mask Load Enable
RAS
Row Enable
Row Enable
SE
Serial-In Mode Enable
Serial Enable
Serial Clock
SC
SDQi
Serial Data I/O
TRG
Q Output Enable
Transfer Enable
W
Write Enable, Write-per-Bit Select
Transfer Write Enable
QSF
Split Register
Active Status
VCC
5-V Supply (typical)
VSS
NC/GND
Device Ground
Make No External Connection or Tie to System Ground
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TM544C251
262144 BY 4-BIT MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
operation
random-access operation
Refer to Table 1, Function Table, for Random-Access and Transfer Operations. Random-access operations are
denoted by the designator "R" and transfer operations are denoted by a "T".
transfer register select and DQ enable (TRG)
The TRG pin selects either register or random-access operation as RAS falls. For the random-access (DRAM)
mode, TRG must be held high as RAS falls. Asserting TRG high as RAS falls causes the 512 storage elements
of each data register to remain disconnected from the corresponding 512-bit lines of the memory array.
(Asserting TRG low as RAS falls connects the 512-bit positions in the serial registerto the bit lines and indicates
that a transfer will occur between the data registers and the selected memory row. See 'Transfer Operation" for
details.)
During random-access operations, TRG also functions as an output enable for the random (0) outputs.
Whenever TRG is held high, the 0 outputs are in the high-impedance state to prevent an overlap between the
address and DRAM data. This organization allows the connection of the address lines to the data I/O lines but
prohibits the use of the early write cycle. It also allows read-modify-write cycles to be performed by providing
a three-state condition to the common I/O pins so that write data can be driven onto the pins after output read
data has been externally latched.
.
address (AO through A8)
Eighteen address bits are required to decode 1 of 262 144 storage cell locations. Nine row address bits are set
up on pins AO through A8 and latched onto the chip on the falling edge of RAS. Then, the nine column address
bits are set up on pins AD through A8 and latched onto the chip on the falling edge of CAS. All addresses must
be stable on or before the falling edges of RAS and CAS.
•
RAS and CAS address strobes and device control clocks
RAS is a control input that latches the states of the row address, W, TRG, SE, CAS, and DSF onto the chip to
invoke the various DRAM and Transfer functions of the TMS44C251. RAS is similar to a chip enable in that it
activates the sense amplifiers' as well as the row decoder. CAS is a control input that latches the states of the
column address and DSF to control various DRAM and Transfer functions. CAS also acts as an output enable
for the DRAM output pins.
special function select (DSF)
The SpeCial Function Select input is latched on the falling edges of RAS and CAS, similarly to an address, and
serves four functions. First, during write cycles DSF invokes persistent write-per-bit operation. If TRG is high,W
is low, and DSF is low on the falling edge of RAS, the write mask will be reloaded with the data present on the
DO pins. If DSF is high, the mask will not be reloaded but will retain the data from the last mask reload cycle.
Second, DSF is used to change the internally stored write-per-bit mask register (or write mask) via the load write
mask cycle. The data present on the DO pins when W falls is written to the write mask rather than to the
addressed memory location. See "Delayed Write Cycle Timing" and the accompanying "Write Cycle State Table"
in the timing diagram section. Once the write mask is loaded, it can be used on subsequent masked write-per-bit
cycles. This feature allows systems with a common address and data bus to use the write-per-bit feature,
eliminating the time needed for multiplexing the write mask and input data on the data bus.
Third, DSF is used to load an on-chip four-bit data, or "color", register via the Load Color Register cycle. The
contents of this register can subsequently be written to any combination of four adjacent column memory
locations using the 4 x 4-Block Write feature. The load color register cycle is performed using normal write cycle
timing except that DSF is held high on the falling edges of RAS and CAS. Once the color register is loaded, it
retains data until power is lost or until another load color register cycle is performed.
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TMS44C251
262 144 BY 4-81T MULTIPaRT VIDEO RAM
SMVS251F - AUGUST1988 -
REVISED DECEMBER 1990
After loading the color register, the block write cycle can be enabled by holding DSF high on the falling edge of
CAS. During block write cycles, only the seven most significant column addresses (A2-A8) are latched on the
falling edge of CAS. The two least significant addresses (AD-A 1) are replaced by the four DO bits, which are
also latched on the later of CAS or W falling. These four bits are used as an address mask and indicate which
of the four column address locations addressed by A2-A8 will be written with the contents of the color register
during the write cycle, and which ones will not. DOO enables a write to column address A 1 is low, AD is low; D01 .
enables a write to A 1 is low, AD is high; D02 enables a write to A 1 is high, AD is low; and D03 enables a write
to A 1 is high, AD is high. A logic high level enables a write and a logic low level disables the write. A maximum
of 16 bits can be written to memory during each CAS cycle (see Figure 1, Block Write Diagram).
Fourth, the DSF pin is used to invoke the split-register transfer and serial access operation, described in the
sections "Transfer Operation" and "Serial Operation".
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TMS44C251
262144 BY 4·81T MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
DOO
D01
D02
D03
I Load Color Register Cycle
I
I
Block Write Cycle
(No DO Mask)
t
Block Write C,)"cle t
(Load and Use DQ Mask)
Block Write Cycle t
(Use Previously
Loaded DO Mask)
I
I
I
RAS n
/ \
/ \
/--+--~\,------n
CAS :
\'-_-J/,...-r---~\
/~---~\
/
\'-----r;
AO-AS ~::C:~~~~~~~~J2[:~K:~::~~~~J[:)€K::~:>~~~c:r:~~:JC:~~~
wt~~
Da~D:::
t W must be low during the Block Write Cycle.
:j: DOO-D03 (CAS) are latched on the later of W or CAS falling edge. DOO-D03 (RAS) are latched on RAS falling edge.
Legend:
1.
Refresh Address
2.
Row Address
3.
Block Address (A2-A8)
4.
Color Register Data
5. Column Mask Data
6.
DQ Mask Data
~ = Don't Care
Figure 1. Block Write Diagram
write enable, write-per-bit enable (W)
The W pin enables data to be written to the DRAM and is also used to select the DRAM write-per-bit mode of
operation. A logic level high on the W input selects the read mode and a logic low level selects the write mode.
In an early write cycle, W is brought low before CAS, and the DRAM output pins (DQ) remain in the
high-impedance state for the entire cycle. During DRAM write cycles, holding W low on the falling edge of RAS
will invoke the write-per-bit operation. Two modes of write-per-bit operation are supported.
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TMS44C251
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
Case 1. If DSF is low on the falling edge of RAS, the write mask is reloaded. Accordingly, a four-bit binary code
(the write-per-bit mask) is input to the device via the random DO pins and is latched on the falling edge of RAS.
The write-per-bit mask selects which of the four random I/Os are written and which are not. After RAS has latched
the write mask on-chip, input data is driven onto the DO pins and is latched on the falling edge of the later of
CAS or W. If a low was strobed into a particular I/O pin on the falling edge of RAS, data will not be written to
that I/O. If a high was strobed into a particular I/O pin on the falling edge of RAS, data will be written to that I/O.
Case 2. If DSF is high on the falling edge of RAS, the mask is not reloaded from the DO pins but instead retains
the value stored during the last write-per-bit mask reload. This mode of operation is known as Persistent
Write-per-Bit, since the write-per-bit mask is persistent over an arbitrary number of cycles.
See the'corresponding timing diagrams for details.
IMPORTANT: The write-per-bit operation is invoked only if W is held low on the falling edge of RAS. If Vii is held
high on the falling edge of RAS, write-per-bit is not enabled and the write operation is identical to that of standard
x 4 DRAMs.
data I/O (DOO-D03)
DRAM data is written during a write or read-modify-write cycle. The falling edge ofW strobes data into the on-chip
data latches. In an early write cycle, W is brought low prior to CAS and the data is strobed in by CAS with data
setup and hold times referenced to this signal. In a delayed write or read-modify-write cycle, CAS will already
be low. Thus, the data will be strobed-in by W with data setup and hold times referenced to this signal.
The three-state output buffers provide direct TTL compatibility (no pullup resistors required) with a fanout of two
Series 74 TTL loads. Data-out is the same polarity as data-in. The outputs are in the high impedance (floating)
state as long as CAS or TRG is held high. Data will not appear at the outputs until after both CAS and TRG have
been brought low. Once the outputs are valid, they remain valid while CAS and TRG are low. CAS or TRG going
high returns the outputs to a high-impedance state. In an early write cycle, the outputs are always in the
high-impedance state. In a register transfer operation (memory to register or register to memory), the outputs
remain in the high-impedance state for the entire cycle.
enhanced page mode
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows theTMS44C251 to operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as column address is valid rather than when
CAS transitions low. This performance improvement is referred to as enhanced page mode. Valid column
address may be presented immediately after row address hold time has been satisfied, usually well in advance
of the falling edge of CAS. In this case, data is obtained after ta(C) max (access time from CAS low), if ta(CA)
max (access time from column address) has been satisfied. In the event that column addresses for the next page
cycle are valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence
of ta(C) or ta(CP) (access time from rising edge of CAS).
Enhanced page mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row address setup, row address hold, and address multiplex is thus
eliminated, and a memory cycle time reduction of up to 3 x can be achieved, compared to minimum RAS cycle
times. The maximum number of columns that may be accessed is determined by the maximum RAS low time
and page mode cycle time used. The TMS44C251 allows a full page (512 cycles) of information to be accessed
in read, write, or read-modify-write mode during a single RAS low period using relatively conservative page mode
cycle times.
During write-per-bit operations, the DO pins are used to load the write-per-bit mask register using either mode
of write-per-bit operation described above under the W pin description.
During block write operations, the DO pins are used to load the on-chip color register during the load color
register cycle and are also used as a write enable during block write cycles.
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TMS44C251
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
refresh
A refresh operation must be performed to each row at least once every eight milliseconds to retain data. Since
the output buffer is in the high-impedance state (unless CAS is applied), the RAS-only refresh sequence avoids
any output during refresh. Strobing each of the 512 row addresses with RAS causes all bits in each row to be
refreshed. CAS can remain high (inactive) for this refresh sequence to conserve power.
CAS-before-RAS refresh
CAS-before-RAS refresh is accomplished by bringing CAS low earlier than RAS. The external row address is
ignored and the refresh address is generated internally.
NC/GND
This pin is reserved for the manufacturer's test operation. It is an input and should be tied to system ground or
left floating for proper device operation.
IMPORTANT: NC/GND is not connected internally to
Vss.
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262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
Table 1. Function Table
T
CAS
FALL
RAS FALL
Y
ADDRESS
000-3
CAS;
p
Et
CAS
R
L
TRG
X§
w~
X
RAS
FUNCTION
DSF
SE
DSF
RAS
CAS
X
X
X
X
X
X
X
CAS-Before-RAS Refresh
Tap
Point
X
X
Register to Memory Transfer
(Transfer Write)
W
T
H
L
L
X
L
X
Row
Addr
T
H
L
L
H
X
X
Row
Addr
Tap
Point
X
X
Alternate Transfer Write
(Independent of SE)
T
H
L
L
L
H
X
Refresh
Addr
Tap
Point
X
X
Serial Write-Mode Enable
(Pseudo-Transfer Write)
T
H
L
H
L
X
X
Row
Addr
Tap
Point
X
X
Memory To Register Transfer
(Transfer Read)
T
H
L
H
H
X
X
Row
Addr
Tap
Point
X
X
Split Register Transfer Read
(Must Reload Tap)
R
H
H
L
L
X
L
Row
Addr
Col
Addr
Write
Mask
Valid
Data
Load and Use Write Mask,
Write Data to DRAM
R
H
H
L
L
X
H
Row
Addr
Col
A2-A8
Write
Mask
Addr
Mask
Load and Use Write Mask,
Block Write to DRAM
R
H
H
L
H
X
L
Row
Addr
Col
Addr
X
Valid
Data
Persistent Write-per-Bit,
Write Data to DRAM
R
H
H
L
H
X
H
Row
Addr
Col
A2-A8
X
Addr
Mask
Persistent Write-per-Bit,
Block Write to DRAM
R
H
H
H
L
X
L
Row
Addr
Col
Addr
X
Valid
Data
Normal DRAM ReadtWrite
(Non-Masked)
R
H
H
H
L
X
H
Row
Addr
Col
A2-A8
X
Addr
Mask
Block Write to DRAM
(Non-Masked)
R
H
H
H
H
X
L
Refresh
Addr
X
X
Write
Mask
Load Write Mask
R
H
H
H
H
X
H
Refresh
Addr
X
X
Color
Data
Load Color Register
t R = Random access operation; T = Transfer operation.
000-3 are latched on the later of Wor CAS falling edge.
*
§ X = Don't care.
~ In persistent write-per-bit function, Wmust be high during the refresh cycles.
Addr Mask = 1; write to address location enabled.
Write Mask = 1; write to 1/0 enabled.
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TMS44C251
262 144 BY 4·BIT MULTIPORT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
random port to serial port interface
Random·access Port
COL
o
COL
COL
255
256
COL
511
ROW
o
TRG
A8
DSF
W
Transfer
Control
Logic
SE
SC
AQ·A8
A8
soa
SE
TRG
W
Figure 2. Block Diagram Showing One Random and One Serial I/O Interface
random-address space to serial-address space mapping
The 512 bits in each of the four data registers of the SAM are connected to the 512 column locations of each
of the four random I/Os. Data can be accessed in or out of the SAM starting at any of the 512 data bit locations.
This start location is selected by addresses AD through AS on the falling edge of CAS during any transfer cycle.
The SAM is accessed starting from the selected start address, proceeding from the lowest to the highest
significant bits. After the most significant bit position (511) is accessed, the serial counter wraps around such
that bit D is accessed on the next clock pulse. The selected start address is stored and used for all subsequent
transfer cycles until CAS is again brought low during any transfer cycle. Thus, the start address can be set once
and CAS held high during all subsequent transfer cycles and the start address pOint will not change regardless
of data present on AD through AS.
split-register mode random-address to serial address-space mapping
In split-register transfer operations, the serial data register is split into halves, the low half containing bits D
through 255 and the high half containing bits 256 through 511. When a split-register transfer cycle is performed,
the tap address must be strobed in on the falling edge of CAS. The most significant column address bit (AS)
determines which register half will be reloaded from the memory array. The eight remaining column address bits
(AD-A7) are used to select the SAM starting location for the register half selected by AS.
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SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
To insure proper operation when using the split-register read transfer feature, a non-split-register transfer must
precede any split-register sequence. The serial start address must be supplied for every split-register transfer.
(See Split Register Operating Sequence on page 8-69.)
transfer operations
As illustrated in Table 1, the TMS44C251 supports five basic transfer modes of operation:
1.
2.
3.
4.
5.
Normal Write Transfer (SAM to DRAM)
Alternate Write Transfer (independent of the state of SE)
Pseudo Write Transfer (Switches serial port from serial-out mode to serial-in mode. No actual data
transfer takes place between the DRAM and the SAM.)
Normal Read Transfer (Transfer entire contents of DRAM to SAM)
Split-Register Read Transfer (Divides the SAM into a high and a low half. Only one half is transferred to
the SAM while the other half is read from the serial I/O port.)
NOTES: A. All transfer write operations will switch the soa pins into the input (write) mode. Before data can be clocked into the serial port via
the soa pins and SC serial clock, it is necessary to switch the soa pins into input mode via a previous transfer write operation.
B. Pseudo Transfer Write Mode has the same meaning as the term "Write Mode Control Cycle" as used in some VRAM data sheets. Both
modes, or control cycles, serve to switch the direction of the soas without an actual data transfer taking place.
C. All transfer read operations will switch the soa pins into the output (read) operation
O. All transfer read operations and the pseudo transfer write operation perform a memory refresh on the selected row.
Table 2. Transfer Operation Logic
TRG
W
SE
MODE
DSF
L
L
L
X
L
L
X
H
L
L
H
L
L
L
H
H
X
X
H
Register to memory (write) transfer,
serial write mode enable
Alternate register to memory transfer,
serial write mode enable
Pseudo write transfer, serial write
mode enable
Memory to register (read) transfer
Split-register read transfer
L
NOTE: Above logic states are assumed valid on the falling edge of RAS.
transfer register select (TRG)
Transfer operations between the memory array and the data registers are invoked by bringing TRG low before
RAS falls. The states of W, SE, and DSF, which are also latched on the falling edge of RAS, determine which
transfer operation will be invoked. (See Table 2.)
During read transfer cycles, TRG going high causes the addressed row of data to be transferred into the data
register. Although the previous data in the data register is overwritten, the last bit of data appearing at SDa before
TRG goes high will remain valid until the first positive transition of SC after TRG goes high. The data at SDa
will then switch to new data beginning from the selected start, or tap, position.
transfer write enable (W)
In any transfer operation, the state of W while RAS falls determines whether a read or write transfer will occur.
To invoke any of the three possible write transfer operations, modes 1, 2, or 3 above, W must be low when RAS
falls. If W is high when RAS falls, the transfer operation will be a read transfer (mode 4 or 5 above).
serial enable (SE)
The serial enable pin has two functions, one that controls the transfer operations and one that controls the serial
access operation.
For transfer operation, SE is latched together with DSF on the falling edge of RAS during any transfer write
operation, i.e. when TRG and Ware low when RAS falls (see Table 2):
TEXAS ~
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262 144 BY 4-81T MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
- If SE is low at that time, a regular transfer write operation will occur.
- If SE is high and DSF is low at that time, a pseudo write transfer will occur, i.e. the SDO pins will be switched
from output to input mode without any data transfer from register to memory.
- If DSF is high, then an alternate register to memory transfer will occur, i.e. the state of SE is don't care.
column enable (CAS)
If CAS is brought low during a transfer cycle, the address present on the pins AO through AS will become the
new register start location. If CAS is held high during a control cycle, the previous tap address will be retained
from the last transfer cycle in which CAS went low to set the tap address.
addresses (AO through AS)
Nine address bits are required to select one of the 512 possible rows involved in the transfer of data to or from
the data registers. The states of AO-AS are latched on the faliling edge of RAS to select one of 512 rows for the
transfer operation.
If CAS makes a high-to-Iow transition during any transfer cycle, the 9-bit address present on AO-AS selects one
of the 512 possible positions in the SAM from which the first serial data will be read or into which the first serial
data will be written. This is also referred to as setting the tap point. During the very first transfer cycle, the tap
paint must be set. In subsequent transfer cycles, CAS need not go low, in which case the previously set tap point
will be used.
In the split-register transfer mode, the most significant column address bit (AS) selects which half of the register
will be reloaded from the memory array. The remaining eight addresses (AD-A?) determine the register starting
location for the register to be reloaded.
special function input (DSF)
In the read transfer mode, holding DSF high on the falling edge of RAS selects the split-register mode transfer
operation. This mode divides the serial data register into a high order half and a low order half; one active, and
one inactive. When the cycle is initiated, a transfer occurs between the memory array and either the high half
or the low half register, depending on the state of the most significant column address bit (AS) that is strobed
in on the falling edge of CAS. If AS is high, the transfer is to the high half of the register. If AS is low, the transfer
is to the low half ofthe register. Use of the split-register mode read transfer feature allows on-the-fly read transfer
operation without synchronizing TRG to the serial clock.
In the write transfer mode, holding DSF high on the falling edge of RAS permits use of an alternate mode of
transfer write. This mode allows SE to be high on the falling edge of RAS without permitting a pseudo write
transfer, with the serial port disabled during the entire transfer write cycle.
serial access operation
Refer to Table 2 for the following discussion on serial access operation.
serial clock (SC)
Data (SDQ) is accessed in or out of data registers on the rising edge of SC. The TMS44C251 is designed to
work with a wide range of clock duty cycles to simplify system design. Since the data registers comprising the
SAM are of static design, there are no SAM refresh requirements and there is no minimum SC clock operating
frequency.
serial data input/output (SOQO-SOQ3)
SO and SO share a common I/O pin. Data is input to the device when SE is low during write mode, and data
is output from the device when SE is low during read mode. The data in the SAM will be accessed in the direction
from least significant bit to most significant bit. The data registers operate modulo 512. Thus, after bit 511 is
accessed, the next bits to be accessed will be bits 00,01,02, and so on.
TEXAS
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TMS44C251
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
serial enable (SE)
For serial access operation, SE enables or disables the SOQ pins. If the SOQ pins have been switched into input
mode (write) by a previous transfer operation, SE high disables input and SE low enables input. If a previous
transfer operation has switched the SDQ pins into output mode (read), SE high disables output and SE low
enables output.
IMPORTANT NOTE: While SE is held high, the serial clock is NOT disabled. Thus, any SC pulses applied will
increment the internal serial address counter regardless of the state of SE. This ungated serial clock scheme
minimizes access time of serial output from SE low since the serial clock input buffer and the serial address
counter are not disabled by SE.
QSF active status output for revision "I" and subsequent revision devices
During the split-register mode of serial access operation, QSF indicates which half of the serial register in the
SAM is being accessed. If QSF is low, then the serial address pointer is accessing the lower (least significant)
256 bits of the SAM. If QSF is high, then the pointer is accessing the higher (most significant) 256 bits of the
SAM. QSF changes state upon completing a transfer cycle, and the state of QSF is determined by the tap point
loaded in that transfer cycle. QSF also changes state upon crossing the boundary between the two register
halves in split-register mode. QSF is not an open-drain output pin.
QSF active status output for revision "H" devices
QSF is an open-drain output pin. During the split register mode of serial access operation, QSF indicates which
half of the serial register in the SAM is being accessed. If QSF is low, then the serial address pointer is accessing
the lower (least significant) 256 bits of the SAM. IF QSF is high, then the painter is accessing the higher (most
significant) 256 bits of the SAM.
QSF changes state upon crossing the boundary between the two register halves. When the SAM is not operating
in split-register mode, the QSF output remains in the high-impedance state.
QSF is designed as an open drain output to allow OR-tying of QSF outputs from several chips. Thus, an external
pullup resistor is required for the zero to one transition on QSF and the output rise time is determined by the
load-capacitance and the value of the pullup resistor. The specification for QSF switching time assumes a pullup
resistor of 820 ohms and a load capaticance of 50 picofarads illustrated as follows.
5V
a----i
I'
820 Q
50 pF
vss
Figure 3. QSF Load Circuit (ReviSion "H" only)
power-up
To achieve proper device operation, an initial pause of 200 I-ls is required after power-up, followed by a minimum
of eight RAS cycles or eight CAS-before-RAS cycles, a memory-to-register transfer cycle, and two SC cycles.
TEXAS ~
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262 144 BY 4-BIT MULTIPORT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
absolute maximum ratings over operating free-air temperature t
Voltage on any pin except DO and SDO (see Note 1) ..................................... - 1 V to 7 V
Voltage on DO and SDO (see Note 1) ............................................. - 1 V to Vee + 1
Voltage range on Vee (see Note 1) .................................................... -1 V to 7 V
Short circuit output current (per output) ..................................................... 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 65°C to 150°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
I TMS44C251-1
I TMS44C251-10, TMS44C251-12
MIN
NOM
MAX
4.75
5
5.25
4.5
5
5.5
VCC
Supply voltage
VSS
Supply voltage
VIH
High·level input voltage
2.4
0
UNIT
V
V
VCC+1
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
VOH
High-level output voltage
2.4
VCC
V
VOL
Low-level output volage
-1
0.4
V
TA
Operating free-air temperature
70
°c
0
25
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
TEXAS ~
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8-44
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TMS44C251
262144 BY 4-BIT MULTIPaRT VIDEO RAM
SMVS251F -AUGUST19BB -
REVISED DECEMBER 1990
electrical characteristics over full ranges of recommended operating conditions
PARAMETER
TEST CONDITIONS
TMS44C251-1
TMS44C251-10
MIN
VOH
High-level output voltage
10H =-2 mA
VOL
Low-level output voltage
10L = 2 mA
IL
10
Input leakage current
Output leakage current
(see Note 3)
MAX
2.4
TMS44C251-12
MIN
UNIT
MAX
2.4
V
0.4
0.4
V
TMS44C251-10,
TMS44C251-12
VI = 0 to 5.8 V, VCC = 5.5 V
All other pins = to VCC
±10
±10
Il A
TMS44C251-1
VI = 0 to 5.55 V, VCC = 5.25 V
All other pins = 0 to VCC
±10
±10
Il A
TMS44C251-10,
TMS44C251-12
Va =
±10
±10
rIA
TMS44C251-1
Va = 0 to Vcc, Vcc = 5.25 V
±10
±10
Il A
TMS44C251-1
TMS44C251-10
TMS44C251-12
a
a to Vcc, Vcc = 5.5 V
PARAMETER
SAM PORT
MIN
MAX
MIN
ICC1
Operation current, tc(RW) = Minimum
Standby
ICC1A
tc(SC) = Minimum
Active
ICC2
Standby current, All clocks = VCC
Standby
10
10
ICC2A
tc(SC) = Minimum
Active
35
35
ICC3
RAS-only refresh current, tc(RW) = Minimum
Standby
ICC3A
tc(SC) = Minimum
Active
ICC4
Page mode current, tc(P) = Minimum
Standby
90
80
110
95
90
80
110
95
50
45
55
ICC4A
tc(SC) = Minimum
Active
60
ICC5
CAS-before-RAS current, tc(RW) = Minimum
Standby
90
80
ICC5A
tc(SC) = Minimum
Active
110
95
ICC6
Data transfer current, tc(RW) = Minimum
Standby
ICC6A
tc(SC) = Minimum
Active
UNIT
MAX
90
80
110
95
mA
NOTE 3: SE is disabled for SDa output leakage tests.
TEXAS •
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TMS44C251
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f =1 MHz (see Note 4)
MIN
PARAMETER
MAX
UNIT
Ci(A)
Input capacitance, address inputs
6
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write enable input
7
pF
Ci(SC)
Input capacitance, serial clock
7
pF
Ci(SE)
Input capacitance, serial enable
7
pF
Ci(OSF)
Input capacitance, special function
7
pF
Ci(TRG)
Input capacitance, transfer register input
7
pF
ColO)
Output capacitance, SOO and 00
7
pF
Co(OSF)
Output capacitance, OSF
10
pF
NOTE 4: VCC equal to 5 V ± 0.5 Vfor TMS44C251-10 and TMS44C251-12, 5 V
±
Ov.
0.25 V for TMS44C251-1, and the bias on pins under test is
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
TEST
CONDITIONS
PARAMETER
ta(C)
Access time from CAS
td(RLCL)
MAX
=
ta(CA)
Access time from column address
td(RLCL)
MAX
=
ta(CP)
Access time from CAS high
td(RLCL)
MAX
=
ta(R)
Access time from RAS
td(RLCL)
MAX
=
a from TRG low
ta(G)
Access time of
ta(SO)
Access time of SO from SC high
TMS44C251-1
ALT.
TMS44C251-10
SYMBOL
MIN
MAX
TMS44C251-12
UNIT
MIN
MAX
tCAC
25
25
ns
tAA
50
25
ns
tCPA
55
25
ns
tRAC
100
25
ns
tOEA
25
30
ns
tSCA
30
35
ns
20
25
ns
60
60
ns
talSE)
Access time of SO from SE low
ta(OSF)
Access time of OSF from SC low
= 30 pF
CL = 30 pF
CL = 30 pF
tdis(CH)
Random output disable time from CAS high
(See Note 6)
CL = 100 pF
tOFF
0
20
0
20
ns
tdis(G)
Random output disable time from TRG high
(See Note 6)
CL = 100 pF
tOEZ
0
20
0
20
ns
tdis(SE)
Serial output disable time from SE high
(See Note 6)
CL
tSEZ
0
20
0
20
ns
CL
= 30 pF
tSEA
NOTES: 5. Switching times for RAM port output are measured with a load equivalent to 1TTL load and 100 pF, data out reference level is
VOHNOL'" 2.4 V/O.S V. Switching times for SAM port output are measured with a load equivalent to 1TTL load and 30 pF, serial data
out reference level is VOHNOL = 2 V/O.B V.
6. tdis(CH), tdis(G), and tdis(SE) are specified when the output is no longer driven.
TEXAS
~
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B-46
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TMS44C251
262 144 8Y 4-81T MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature t
ALT.
SYMBOL
TMS44C251·1
TMS44C251·10
MIN
MAX
TMS44C251·12
MIN
UNIT
MAX
tc(rd)
Read cycle time (see Note 7)
tRC
180
210
tc(W)
Write cycle time
twc
180
210
ns
tc(rdw)
Read-modify-write cycle time
tRMW
240
280
ns
tc(P)
Page-mode read, write cycle time
ns
tpc
60
70
ns
tpRMW
105
125
ns
tc(RDWP)
Page-mode read-modify-write cycle time
tc(TRD)
Transfer read cycle time
tRC
180
210
ns
tc(TW)
Transfer write cycle time
twc
180
210
ns
tc(SC)
Serial clock cycle time (see Note 8)
tscc
30
35
ns
tw(CH)
Pulse duration, CAS high
tCPN
10
15
ns
tCAS
25
70
75000
100
25
75000
tw(CL)
Pulse duration, CAS low (see Note 9)
t"",(RH)
Pulse duration, RAS high
twiRL)
Pulse duration, RAS low (see Note 10)
tRP
tRAS
30
80
75000
120
75000
ns
ns
ns
25
ns
25
30
ns
tw(WL)
Pulse duration, W low
tw(TRG)
Pulse duration, TRG low
tw(SCH)
Pulse duration, SC high
tsc
10
12
ns
tw(SCl)
Pulse duration, SC low
tscp
10
12
ns
tsu(CA)
Column address setup time
tASC
0
0
ns
tsu(SFC)
DSF setup time before CAS low
tFSC
0
0
ns
tsu(RA)
Row address setup time
tASR
0
0
ns
tsu(WMR)
W setup time before RAS low
twSR
0
0
ns
ns
tsu(OOR)
00 setup time before RAS low
twp
tMS
0
0
ITHS
0
0
ns
tESR
0
0
ns
tsu(TRG)
TRG setup time before RAS low
tsu(SE)
SE setup time before RAS low with TRG = W
tsu(SFR)
DSF setup time before RAS low
tFSR
0
0
ns
tsu(OCL)
Oata setup time before CAS low
tosc
0
0
ns
tsu(OWL)
Data setup time before W low
tosw
0
0
ns
tsu(rd)
Read command setup time
tRCS
0
0
ns
tsu(WCl)
Early write command setup time before CAS low
twcs
-5
-5
ns
tsu(WCH)
Write setup time before CAS high
tCWL
25
30
ns
tsu(WRH)
Write setup time before RAS high
tRWL
25
30
ns
tsu(SDS)
SO setup time before SC high
tsos
Column address hold time after CAS low
tCAH
3
20
ns
th(CLCA)
3
20
th(SFC)
DSF hold time after CAS low
tCFH
20
20
ns
th(RA)
Row address hold time after RAS low
tRAH
15
15
ns
=low
ns
Continued next page.
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 7. All cycle times assume tt = 5 ns.
8. For mid-line load, tc(SC) = 50 ns for Revision I and subsequent revisions; tc(SC) = 55 ns for Revision H only. For split-register,
tc(SC) = 40 ns for Revision Hanly.
.
9. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user's transition times, this may require
additional CAS low time [tw(CL))'
1O. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user's transition times, this may require
additional RAS low time [twIRL))'
TEXAS •
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TMS44C251
262 144 BY 4·BIT MULTIPORT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)t
ALT.
SYMBOL
th(TRG)
TRG hold time after RAS low
= W = low
TMS44C251-1
TMS44C251-10
TMS44C251-12
MIN
MIN
MAX
UNIT
MAX
fTHH
15
15
ns
tREH
15
15
ns
tRWH
15
15
ns
15
ns
th(SE)
SE hold time after RAS low with TRG
th(RWM)
Write mask, transfer enable hold time
after RAS low
th(RDO)
DO hold time after RAS low
(write mask operation)
tMH
15
th(SFR)
DSF hold time after RAS low
tRFH
15
15
ns
th(RLCA)
Column address hold time after RAS low
(see Note 10)
tAR
45
45
ns
th(CLD)
Data hold time after CAS low
th(RLD)
Data hold time after RAS low (see Note 11)
th(WLD)
Data hold time after W low
th(CHrd)
Read hold time after CAS (see Note 12)
tDH
20
25
ns
tDHR
45
50
ns
ns
tDH
20
25
tRCH
0
0
ns
th(RHrd)
Read hold time after RAS (see Note 12)
tRRH
10
10
ns
th(CLW)
Write hold time after CAS low
tWCH
25
30
ns
thLRLW)
Write hold time after RAS low (see Note 11)
tWCR
50
55
ns
th(WLG)
TRG hold time after W low (see Note 13)
tOEH
25
30
ns
th(SDS)
SD hold time after SC high
tSDH
5
5
ns
thJSHSO)
SO hold time after SC high
tSOH
5
5
ns
td(RLCH)
Delay time, RAS low to CAS high
tCSH
100
120
ns
td(CHRL)
Delay time, CAS high to RAS low
tCRP
0
0
ns
td(CLRH)
Delay time, CAS low to RAS high
tRSH
25
30
ns
td(CLWL)
Delay time, CAS low to W low
(see Notes 14 and 15)
tCWD
55
65
ns
td(RLCL)
Delay time, RAS low to CAS low
(see Note 16)
tRCD
25
td(CARH)
Delay time, column address to RAS high
tRAL
50
60
ns
td(RLWL)
Delay time, RAS low to W low (see Note 14)
tRWD
130
155
ns
td(CAWL)
Delay time, column address to W low
(see Note 14)
tAWD
85
100
ns
td{RLCHl
Delay time, RAS low to CAS high (see Note 17)
tCHR
25
25
ns
td(CLRL)
Delay time, CAS low to RAS low (see Note 17)
tCSR
10
10
ns
75
25
90
ns
Delay time, RAS high to CAS low (see Note 17)
5
ns
5
tRPC
tdIRHCL)
Continued next page.
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 10. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user's transition times, this may require
'
additional RAS low time [tw(RL)j.
11. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
12. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
13. Output Enable controlled write. Output remains in the high-impedance state for the entire cycle.
14. Read-modify-write operation only.
15. TRG must disable the output buffers prior to applying data to the DO pins.
16. Maximum value specified only to guarantee RAS access time.
17. CAS-before-RAS refresh operation only.
TEXAS~
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8-48
POST OFFICE BOX 1443
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HOUSTON, TEXAS 77001
TMS44C251
262144 BY 4-BIT MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)t
ALT.
SYMBOL
TMS44C251-1
TMS44C251-10
TMS44C251-12
MIN
MIN
MAX
UNIT
MAX
td(CLGH)
Delay time, CAS low to TRG high
tCTH
25
35
ns
td(GHD)
Delay time, TRG high before data applied at DO
tOED
25
30
ns
Delay time, RAS low to TRG high
th(TRG)
th(TRG)
td(RLTH)
85
90
td(RLSH)
Dela~e, RAS low to first SC high
after TRG high (see Note 18)
Early load
Revision
ns
tRTH
Mid-line load
H
125
135
105
115
ns
tRSD
Revision I
td(CLSH)
Delay time, CAS low to first SC high
after TRG high (see Note 18)
tCSD
35
40
ns
td(SCTR)
Delay time, SC high to TRG high
(see Notes 18 and 19)
tTSL
10
15
ns
td(THRH)
Delay time, TRG high to RAS high
(see Note 18)
tTRD
-10
-10
ns
td(SCRL)
Delay time, SC high to RAS low with
TRG =W = low (see Notes 20 and 21)
tSRS
10
10
ns
td(SCSE)
Delay time, SC high to SE high in
serial input mode
20
20
ns
td(RHSC)
Delay time, RAS high to SC high (see Note 21)
tSRD
25
30
ns
td(THRL)
Delay time, TRG high to RAS low (see Note 22)
trRP
tw(RH)
tw(RH)
ns
35
40
30
35
Revision H
td(THSC)
Delay time, TRG high to SC high (see Note 22)
ns
trSD
Revision I
td(THSC)
Delay time, TRG high to SC high (see Note 22)
tTSD
35
40
ns
td(SESC)
Delay time, SE low to SC high (see Note 23)
tsws
10
15
ns
td(RHMS)
Delay time, RAS high to last (most significant)
rising edge of SC before boundary switch during
split read transfer cycles
25
30
ns
td(TPRL)
Delay time, first (TAP) rising edge of SC after
boundary switch to RAS low during split read
transfer cycles
20
25
ns
trf(MA)
Refresh time interval, memory
tt
Transition time
8
tREF
tr
3
50
3
8
ms
50
ns
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 18. Memory to register (read) transfer cycles only.
19. In a transfer read cycle, the state of SC when TRG rises is a Don't Care condition. However, to guarantee proper sequencing of the
internal clock circuitry, there can be no positive transitions of SC for at least 10 ns prior to when TRG goes high.
20. In a transfer write cycle, the state of SC when RAS falls is a Don't Care condition. However, to guarantee proper sequencing of the
internal clock circuitry, there can be no positive transitions of SC for at least 10 ns prior to when RAS goes low.
21. Register to memory (write) transfer cycles only.
22. Memory to register (read) and register to memory (write) transfer cycles only.
23. Serial data-in cycles only.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
8-49
TMS44C251
262 144 BY 4-81T MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
read cycle timing
14
I
tc(rd)
~
tw(RL)
'd(ALCH)
-----,., 14
N
RAS
tt
.1
I
~
1
0~tW(RH) --.l
I
-.I !4~ td(CLRH), -Jill I
I
~td(RLCL) ~tW(CL) - . : Htd(CHRL) ~
CAS
I
I
~
14- th(RA)
::
I
I
tsu(RA)
~
~
;.-+-
-.! j+t
t
I
I\.
I
th(RLCA,)
~
i ""
-I:
}. ;
~td(CLGH)
.1
~
I
I
\
-t4:
: \.'-_ _
I
I
II
II
I
th(CLCA) 14
~
'--____
~
t (CH)
A~AB ~ :+mn ~'-_____
tsu(SFR) ~
i4I
~
~ tsu(SFC)
I
II
I~ *-th(SFR) I ~
.~Ith~
~!II!~:III-
DSF~II
~II
I
- I I - I I
~ I4-r tsu(TRG)
I
I I
~
th(TRG) I I
:
TRG
Vi
DQ
'
*
II
14- tw(TRG) ~ I
~~~~.,.,-----'!flli' : \ \lII~
:~
I . '
I'
I
I tsu(rd)
th(CHrd)!..
-.J
14-!~II
I
-41 ~ th(RHrd)
f\XXXXXXXXXXXXX
IC"jl
I
I
IIII~
I
I
I
I
I
i
i
I
:
~
~
I
I
'
I
14- tdls(CH) - . J
14-- ta(G) --.:
!4- tdls(G) ~
(valid
~ta(C)-.!
~~~
~
~~
~
TEXAS
-II
INSTRUMENTS
8-50
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
2>-------
TMS44C251
262144 BY 4-BIT MULTIPORT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
early write cycle timing
AO-A8
OSF
mr
'l
I I
I I
~ 14- tsu(WMR)
, I 1
, I I
,
th(RWM)
'
H II11III1
1II1II
14
.~--+-I- + - - - - tsu(WCH) -----.~~
~
I
tsu(WRH)
th(RLW)
:"
1
1
th(CLW)
,II1II
~ !lllllitsu(WCL)
II,
131~11,
W
~
tsu(OQR)
-.I
,
iIIIIIf
1
th(ROIQ) ~
,I
tsu(OCL)
~
I'" II
~
----.~
~I
~
I
~~--t-!~--+1'--- tw(WL) -----~.:
~
----Dl.,
~
I
....
, ---th(CLO)
th(RLO) ------~.I
II ____________________
~I
OQ~
NOTE 24:
1
,
------~~
5
See "Write Cycle State Table" for the logiC state of "1", "2", "3", "4", and "5",
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-51
TMS44C251
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 - REVISED DECEMBER 1990
delayed write cycle timing
tc(W)
~
---~N
I ~
tt ~
~
~ td(RLCL)
I
th(RA)
AO-A8
I I
II
~ 14-
~
1~i4-tt
~
td(CLRH)
tw(CL)
.~
N'
I
i~
I:
I
I
I
I
I ~ I
I ~ th(RLCA) ~ I
I
I
}
i "---
tw(CH)
~
q,:mn
~'-______
tsu(SFR) ~
1 ~
~ th(SFC)
I
j4-r
I
~
I
*-1
~ ~ tsu(SFC)
I
I
I
I
I
I
I
~:2 ~'--j4-r t su(TRG)
L I I
~~ ~
~ I I
I ~ I
It-I tsu(WMR)
131
-----"'"
-
~
I
I
I
I
~
th(RWM):
1 td(GHD) ~
~
-1
tsu(WRH)
tsu(WCH)
~
,'I
I~ :
I
!
-.1
~
-.:
~I
~
:~
"I
~
't
tsu(DWL) ..,1,1
~ I su(DOR)
I....
tw(WL)
~ 14- th(RDO)
I
14- th(WLD) - . I
~ I
I th(RLD)
-.1
t.._
:
:
-.1
th(RLW)
th(CLW)
I '
I
DO
5
NOTE 24: See "Write Cycle State Table" for the logic state of "1 ", "2", "3", "4", and "5".
TEXAS
-IJ1
INSTRUMENTS
8-52
I
~I ~ td(CHRL) ~
~
-w
I
1
~
j4- tw(RH) ~
~
(SFR)
DSF
--------.t-.I
td(RLCH)
II
-.1
v:
~
tw(RL)
II1II
1
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
1
-'1
__
TMS44C251
262144 BY 4-81T MULTIPORT VIDEO RAM
SMVS251 F
AUGUST 1988
REVISED DECEMBER 1990
write cycle state table
STATE
CYCLE
1
2
3
4
'5
Valid
Data
Write mask load/use write DOs to I/Os
L
L
L
Write
Mask
Write mask load/use block write
L
H
L
Write
Mask
Addr
Mask
Use previous write mask, write DOs to I/Os
H
L
L
Don't
Care
Valid
Data
Use previous write mask, block write
H
H
L
Don't
Care
Addr
Mask
Load write mask on later of IN fall and CAS fall
H
L
H
Don't
Care
Write
Mask
Load color register on later of W fall and CAS fall
H
H
H
Don't
Care
Color
Data
Write mask disabled, block write to all I/Os
L
H
H
Don't,
Care
Addr
Mask
Normal early or late write operation
L
L
H
Don't
Care
Valid
Data
TEXAS
J!}
INSTRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-53
TMS44C251
262 144 8Y 4-81T MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
read-write/read-modify-write cycle timing
tc(rdW) -------------.!~
,
,
I11III
,
RAS
---·""'!oN,'~
~
, I
, 14- td(RLCL)
CAS
I.'nl.1
'h(RA)!
I
--.J
,tsu(CA)
tsu(RA
I'
~111111------ td(CLRH) - - - - - - - . . . . ,
~.4------- tw(CL) ------~}lf
~
rI
_',I
~
,
'I:
See "Write Cycle State Table" for the logic state bf "1", "2", "3", "4", and "5", Same logic as delayed write cycle,
TEXAS
lJ1
INSlRUMENlS
8-54
POST OFFICE BOX 1443
•
I11III
,
.,
~
tw(RH)
'd(CHRL)
\\-
t.. __ t
_~
, ,~ w(CH) --.,
~ th(CLCA)
AQ·AS
NOTE 25:
,
tw(RL) ------------.t~
'4
HOUSTON, TEXAS 77001
TMS44C251
262144 BY 4-BIT MULTIPORT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
enhanced page-mode read cycle timing
tw(RH)
RASI\l
I ~
I I
~
td(RLCL)
*- tw(CL) ~
U
CAS
:
:.- th(RA)
I
\ \{ Ii
~ ~
~
4
14-
th(CLCA)
ICI----
I
I
~
I
td(CHRL)'
~I
tC(P)
~
I
I
14--- td(CLRH)
~ tw(CH) ~
11
I
!su(RA)
I 14
~
.1
1 1 1 1 1 1 4 1 - - - - - - - - - - - - - - tw(RL)
!
I
~
i
1 1
I:
:
td(CARH) -----,,--~;;.:~~~~~
Column
AO-AS
I~ I t
~
I
su(SFR)
tsu(CA) ~
: 1+ th(SFR) ~
DSF
1
I
I
~ tsu(TRG) ~I
I I
TRGW
~
I
I~
wW
~
I
::
r--f-I tsu(WMR)
I
i
th(TRG)
\
I
I
1
I
I
tsu(rd)
1
I
I
I
I
I
~
ta(R)*
~~ ~th(SFC)
i+-tsu(SFC)
I
I
I
I
~~~~~~~~
I I
I
I
I
I
I
I
I
I
~
I
I
I
I
I
I
~
~ ta(CA)
I
I
14-- ta(C)
DO
I
:
~
~
,th(RHrd) ~
~ ta(CA) t ---.!
~
~
(
Out
14-
~th(CHrd) ~
I
1
ta(Cp)t
1
1
1
1
I
{i
IW I
I
-.I
I4-ta(G)~
1
I
1
1
1
1
1
I 1
1 I
1
1 I4----*-
~
tdIS(G)
~tdiS(CH)*
Valid
Out
)
t Access time is ta(CP) or ta(CA) dependent.
*Output may go from high-impedance state to an invalid data state prior to the specified access time.
NOTE 26:
A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of DSF is selected on the falling edges of RAS and CAS to select the desired
write mode (normal, block write, etc.).
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-55
TMS44C251
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SMVS251 F - AUGUST 1988 - REVISED DECEMBER 1990
enhanced page-mode write cycle timing
14
~
tw(RL)
~
RASN
I
~~---------t-d-(R-LC-H-)---------~~~--------t-C(-~-~--------.-I--tw-(R-H-~~
. I ~
td(RLCL)
~....
I
tw(CH)
14-- td(CL,RH)
I
I I
4
CAS
tw(CL)
tsu(RA)
tsu(CA)
I I
I !4- th(RA) ~
I ~
I
/4-
I
Y
~\ ~I
I'
I:
~ I
7\ ~ /
I
I
I
-I
I
I
j4-- td(C~RL) ~
th(CLCA)
~
I
I
I
:
I
I
I
I
I
td(CARH)
~
I
I
14- 'h(:FC) --:
I
AO-AS
tsU(SFR)
OSF
-+I ~
tsu(SfC)
I :' ~: 'h(SFR) ~
~.
~
1
14+ tsu(TRG)
I I I
I~
I
:
)@<.
I
tsu(SFC)
r- 'h(SFC) --:
~
~
I
: ~
I
I
2
~
l
I
I
I
I
t Referenced to CAS or W, whichever occurs last.
NOTES; 24. See "Write Cycle State Table" for the logic state of "1", "2", "3", "4", and "5".
27. A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing
specifications. TRG must remain high throughout the entire page-mode operation if the late write feature is used, to guarantee
page-mode cycle ti~f the early write cycle timing is used, the state of TRG is a Don't Care after the minimum period th(TRG) from
the falling edge of RAS.
TEXAS ~
INSTRUMENTS
8-56
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44C251
262144 BY 4-BIT MULTIPaRT VIDEO RAM
SMVS251F -AUGUST1988 -
REVISED DECEMBER 1990
enhanced page-mode read-modify-write cycle timing
14
~
tw(RL)
I
I
RAS~
I I
I ~
~
I I
~
I I
I
.1
td(RLCH)
~I
I
tc(RDWP)
tw(RH) ~
CAS
:
tsu(RA)
:
~ I
th(RA) '-.1!4I
I ~:
7\
~
I
I th(RLCA)
A~AB ~
~
~ th(CLCA)
I
~
~ th(SFC)
~ tSU(SFC):
I:
DSF~:>
tsu(WMR) ~
I
th(RWM)
I
I I
~
; ;COlumn:
~ 14- th(SFR) I I
tsu(SFR)
14
I
~
G
~ I tsu(RD)
I
I
I
~
14
I
11
I
I
I
I
I
I
I
I
I
I
I
I
I
tsu(WCH) ~
I
I
.1
I
I
I
I
~
.1
2
--.I ~ ta(C)
I
...
su(DOR)
th(RDO)
~
I
I
I
I
ta(CA) t
tsu(DWL)
I
I
14
~ 14I
I
~
th(SFC)
~
I
iii
tw(WL)
I
I
I
~
~
tSU(S'FC):
'liY
3:1
~t
I
~Olumn:
~ 14 I
td(CAWL)
~
I
~d(RLWL)
"i I
- ' 1 1
W
I
I
~td(CLWL)~
I
I:
I
I
:
~:
~
td(CHRL)
,0 7\\1
~
tsu(CA)
I I
~
14--- td(CLRH)
: j4- t d(RLCL) ~~tW(CL) ~ ~tW(fH)
14
t
su(WRH)
I
I
\l~
~-~""""""""""""......."""""'
I
I .1 th(WLD)
14- t~(CP) t ~
,
I
.r---~
DO
I
I
I
I' 14- ta(G) -.!
_ _ _ _14---'.!i1 : ta(R) ~
~~
14/e--._ td(GHD)
liI--_ _ _ _ _ _....
V
_ ____JI
I4-----.t-- tdis(G)
~I_ _ _ _ _ _ _ _ _ _ __
t Output may go from the high-impedance state to an invalid data state prior to the specified access time.
NOTES: 24. See "Write Cycle State Table" for the logic state of "1 ", "2", "3", "4", and "5".
28. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not
violated.
TEXAS ~
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-57
TMS44C251
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
RAS-only refresh timing
~~------tc(rd) -------~.I
I 1 4 - tw(RL)
RAS
----------------------------~i'l
---~~
~~
I I
~
J4-
tt
w
DQ
NOTE 29:
In persistent write-per-bit function,
Vi must be high during the refresh cycles.
TEXAS ~
INSlRUMENTS
8-58
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
I
tt
I ~tW(RH)~
--.! ~
TMS44C251
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
CAS·before·RAS refresh
~~--------- tc(rd)
----.t~ te~---- tw(AL) -----.t~
14- tw(AH)
J':
----
~
~
.1
1
}r~-------------
td(AHCL)
I I
,
I ,
~ td(CLAL) ~ ~ td(ALCH) ----.I
.'
\{
Y
TAG
w
DSF
NOTE 29: In persistent write-per-bit function,
IN must be high during the refresh cycles.
TEXAS
.J!1
INSTRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-59
TMS44C251
262144 BY 4-BIT MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
CAS-before-RAS refresh counter test timing
14-~------------tc(rd)
I
~ tw(RH) - I I I
A
I
~I
I
I
I
td(CLRL)
jIIII
I
------------.!.I
I
I
td(RHCL)7\I\------------------1
. I
I I
I
~
\{
i
I
itd!RLCH)Y
I
:"'L
tsu(SFR) ~I ~I
I
y1
tsu(SFC)-+1
I
1
I~
I
~.
I
I ~th(SFC)
I
I
!4---r th(SFR)
1
DSF
1
1
I
f
I
1
N
I
I
~
tw(CL)
141
tw(CH) ~~--~.I
1
r-t
I
I
~:
~~III
-~II
I I
I I
TRG~DzzK*g~
I
~tsu~CH) ~
1
~tsu~RH)~
I I
I
141---1 th(CLW) ~
I ~ th(CLD) ~ I
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-.,..I_I~
W
lIN
!
141
~
.1
I
L.l
tsu(DWL) I~'
DO - - - - - - - - - H I - Z
tSU(CA)~
I
TEXAS ~
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Data In
Y
th~LD)
)~----
I
~th(CLCA)
Column
INSIRUMENlS
8-60
!~
<
--------.,.-(!
AO-AS
I+-tw~L)I~
~"'~~~~~""1'::'1'~
TMS44C251
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
hidden refresh cycle timing
f4- Memory Cycle
I~
tw(RH)
~I
I
.1
1
I
~ Refresh Cycle ~
~
tw(RL)
t W (RH):4
1 14
1
.1 1 tw(RL)
1
1
1
~~ Refresh Cycle ~
1
~I
VIL
1
td(RLCH)
'\ :
I
~
:
t
AO-AS
1
~I
14
~~ VIH
tw(Cl)
!\{_
I
VIH
1
.
()
1
f4- th(CLCA)
I
I
VIL
:
- I -.I ~ tsu(CA)
h(RA) I~ I4-t- I I I'
1
I
~~~
~*HH'~::~:::
w.:I J
t
0
I
I
I
1
su(rd)~
~th(RHrd)
I
I
~ta(c~*RX*X'~::~~::
<
Data
;1
>l'
I !4-- ta(R) -J
I I
"'
DQ
--.!
I
I
I
¥
!4-f tsu(TRG)
tdis(CH) --.,
Valid
VOH
I
I
~ta(G)
I
~
tdls(G)
~th(TRG)
I
~
I
VOL
1
I
IL'---:::
1
-----------------------J()-,..I
\11\0,.:
J
_______
VIH
DSF
VIL
TEXAS
-IJ1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-61
TMS44C251
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SMVS251F -
AUGUST1988- REVISED DECEMBER 1990
write-mode control pseudo write transfer timing
The write-mode control cycle is used to change the SOOs from the output mode to the input mode. This allows
serial data to be written into the data register. The diagram below assumes that the device was originally in the
serial read mode.
~
:
_ _ _ _ _~I
~~
~
~td(RLCL) ~
N
: ! 14 I
AO-AS
N
I
I
I
I
0
1-
I
- 1
th(CLCA) 1
th(RA)
I ~
IJlj
'h("LCA)
I
.,
I
I~
tsu(CA)
I
VIH
VIL
I
~
~ ~o7 ~ ~olumn ~&H*~~:::
I ~ th(SFR)
tsu(SFR)~1
DSF
I
Y~tW(RH)~\~---:::
td(RLCH~
~
i4- t w(CL) ~
II
~ tsu(RA)
1
I 14
.1
:
:
:
~
: :
I
~
~
tw(RL)
~:I
1
~I~
III
~III
I I
I ~ th(TRG)
tsu(TRG) ~ I
1
VIL
~
1
.1
~
td(THRL)
~ i i ~Hn2gHxxxxx¥xxxy
I
tsu(WMR) ~
I
:::
1
1114~~t~
~
II:
VIH
'
VIL
~!I
I...
,
~tw(SCH)~
td(SCRL) ~
.:: :
sc
SDa
~
Data
Out
tdIS(SE) ~
tsu(SE) ~
~
:\\\\\\\'\~
:
I I
I
I
I
I
I
1
1
I
14- I
~
t
w(SCL)
~
~
td(RHSC)
0
.1
1
\
1
~ th(SDS)
1
~th(SE)
td(SESC) - - I 4 - - - - . t
1
NOTES: 30. Random-mode Q outputs remain in the high-impedance state for the entire write-mode control.
31. SE must be high as RAS falls in order to perform a write-mode control cycle.
TEXAS
-'!1
INSTRUMENTS
8-62
VIH
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
VIH
VIL
TMS44C251
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
data register to memory timing, serial input enabled
~
~~
I ~
tw(RL)
I ~td(RLCL) ~
RAS
:
--------~~
I
I
1
~
14
tsu(RA)
I
I
I
AD-AB
~
~
tsu(SFR)
1
OSF
~
~
tsu(TRG)
~ow
1
I
!. t
W
1-
td(SCRL)
sc
11-1
I
~
~
I
:.-isu(sos)
1
: :
1
I
tsu(CA)
1
~
Column
I
1
1
I
I
I
I
~H0RH_
th(RWM)
I
~
1
I 1
I I
I I
-111411-----...1 1
.~I-----t-I--+II~~
1
~---
:
~g~~gH~
~ Ii Ii
DO
IV
---.I
~
I
lei- td(THRL) --.!
h(TRG)""~1
I
I
I I
I lei
~
tw(CL)
~ th(CLCA)
J0(
::'
~
~
1- t
_~
loCI- h(SFR) ~
~II
TRG~
II
tsu(WMR)
I4f1
~
j4-- tw(RH)
1
14- th(RA) ~
-.I
I 14
th(RLCA)'
I i i
:
I
:
11
N
J:
I
I
I
td(RLCH)
!:
~
~
2~n:2*r~
.
HI-Z
tw(SCH)
I
I
- - - - - - : - 1- - - - - - - - - - I
td(RHSC)
loll
.1
1 141C1----t~1f-1 tw(SCH)
1
I-r--_ _.....
\\\\\\\\\\\\\\\\\\\\\\\\W\·
J1
tW(SCL~
"--
1
I t~(SOS)
I ICItCI-~-
SOO
tsu(SE)
SE
~
/
!4- th(SE)
~
~ td(SESC) -l>!
3
NOTES: 32. Random mode Q outputs remain in the high-impedance state for the entire data register to memory transfer cycle. This cycle is
used to transfer data from the data register to the memory array. Everyone of the 512 locations in each data register is written into
the corresponding 512 columns of the selected row. Data in the data register may proceed from a serial shift-in or from a parallel
load from one of the memory array rows. The above diagram assumes that the device is in the serial write mode (i.e., SO is enabled
by a previous write mode control cycle, thus allowing data to be shifted-in).
33. See "Register Transfer Function Table" for logic state of "1" and "3".
34. Successive transfer writes can be performed without serial clocks for applications requiring fast memory array clears.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443
•
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8-63
TMS44C251
262 144 BY 4·BIT MULTIPORT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
register transfer function table
RAS FALL
TRG
W
DSF
(1)
Register to memory transfer, serial input enabled, serial write mode enable
L
L
X
L
Register to memory transfer, alternate transfer write, serial write modtl enable
L
L
H
X
Pseudo-transfer SDO control, serial write mode enable
L
L
L
H
Memory to register transfer
L
L
H
L
X
H
H
X
FUNCTION
Split-register transfer
TEXAS ~.
INSlRUMENlS
8-64
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SE
(3)
TMS44C251
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SMVS251 F -
AUGUST 1988 -
REVISED DECEMBER 1990
alternate data register to memory timing
~
1
~~
~
~
tw(RL)
II1II
* - td(RLCL) - . !
----------~
i
I
1
CAS
~
tsu(RA)
1
1
J4-- tw(CL)
N
I:
.1! I
~
tsu(SFR)
I
1
r-
i4fI
:y
tsu(CA)
~
SC
~
-- C20[ROW]
G23/REFRESH ROW
4
RAS - -____- - I 24,34,44,54 [PWR OWN]
CAS1
CAS2
CAS3
CAS4
W
OE
5
6
21
23
3
22
001
002
003
004
2
24
25
t This symbol is in accordance with ANSI/IEEE Std. 91-1984 and lEG Publication 617-12.
TEXAS
~
INSlRUMENTS
8-76
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44C260
262 144 WORD BY 4-BIT QUAD CAS
DYNAMIC RANDOM-ACCESS MEMORY
SMGS260B - JANUARY 1990 -
REVISED NOVEMBER 1990
functional block diagram
+J J + +
II>.
~
::
:::
~
::-
AO
A1
A2
A3
A4
A5
AS
A7
AS
G
256KI
Row I 256K
Array
Decode
Array
(9)
"'-../;7
~
Sense Amplifiers
~
::
::
L
.Ll
Row
Address
Buffers
Ir+.
1
+ +
Timing and Control
Column
Address
Buffers
(9)
h
~
Column Decode
Sense Amplifiers
256K
Array
I
Row
Decode
I
I:I: :=
I: :
I/O
Buffers
4 of S
Selection
~
256K
Array
I
:
~
t:=
4
Data
In
Reg
~
Data
Out
Reg
f+-+
4
........
....... ""
4
II.
001·0 04
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee ............................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 rnA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. DoC to 70°C
Storage temperature range ...................................................... - 65°C to 150°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation ofthe device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.5
5
0
5.5
UNIT
VCC
Supply voltage
VSS
Supply voltage
V
VIH
High-level input voltage
2.4
6.5
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
DC
V
V
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for
logic voltage levels only.
TEXAS •
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8-77
TMS44C260
262 144 WORD BY 4·81T QUAD CAS
DYNAMIC RANDOM·ACCESS MEMORY
SMGS260B -
JANUARY 1990 -
REVISED NOVEMBER 1990
electrical characteristics overfull ranges of recommended operating conditions (unless otherwise
noted)
TMS44C260-60
TEST
PARAMETER
CONDITIONS
VOH
High-level output
voltage
10H =-5 mA
VOL
Low-level output
voltage
10L = 4.2 mA
II
Input current
(leakage)
10
ICCl
MAX
MIN
2.4
TMS44C260-70
MIN
MAX
TMS44C26Q-aO
MIN
MAX
MIN
MAX
UNIT
V
2.4
2.4
2.4
TMS44C26Q-10
0.4
0.4
0.4
0.4
V
VI = 0 to 6.5 V,
VCC = 5 V, All other
pins = 0 V to VCC
±10
±10
±10
±10
rtA
Output current
(leakage)
Vo = Ot06.5~
VCC = 5.5 V, CAS high
±10
±10
±10
±10
~A
Read/write cycle
current
tRWC = minimum,
VCC = 5.5 V
95
80
75
65
mA
ICC2
Standby current
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V
2
2
2
2
mA
ICC3
tRWC = minimum,
VCC = 5.5 V,
Average refresh
current (RAS-only RAS cycling, CAS high
orCBR)
(RAS-only),
RAS low, after CAS low (CBR)
90
80
70
60
rnA
ICC4
Average page
current
70
60
50
45
rnA
tpc = minimum,
VCC = 5.5 V,
RAS low, CAS cycling
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f 1 MHz (see Note 3)t
=
MIN
PARAMETER
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(RC)
Input capacitance, strobe inputs
5
pF
Ci(W)
Input capacitance, write-enable input
5
pF
Ci(OE)
Input capacitance, output-enable input
5
pF
Co
Output capacitance
7
pF
t Capacitance measurements are made on a sample basis only.
NOTE 3: Vec equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
TMS44C260-60
PARAMETER
MIN
MAX
TMS44C260-70
MIN
MAX
TMS44C260-80
MIN
MAX
TMS44C260-10
MIN
MAX
UNIT
tCAC
Access time from CAS low
15
18
20
25
ns
tCAA
Access time from column address
30
35
40
45
ns
tRAC
Access time from RAS low
60
70
80
100
ns
tOEA
Access time from OE low
15
18
20
25
ns
tCAP
Access time from column precharge
50
ns
tOFF
Output disable time after CAS high
(see Note 4)
0
15
0
18
0
20
0
25
ns
tOEZ
Output disable time after OE high (see Note 4)
0
15
0
18
0
20
0
25
ns
NOTE 4: tOFF and tOEZ are specified when the output is no longer driven.
TEXAS -If
INSlRUMENTS
8-78
POST OFFICE BOX 1443
•
40
40
35
HOUSTON. TEXAS 77001
TMS44C260
262 144 WORD BY 4-BIT QUAD CAS
DYNAMIC RANDOM-ACCESS MEMORY
SMGS260B - JANUARY 1990 -
REVISED NOVEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
TMS44C260-60
MAX
MIN
TMS44C260-70
MIN
MAX
TMS44C260-80
MIN
MAX
TMS44C260-10
MIN
MAX
UNIT
tRC
Read cycle time (see Note 6)
110
130
150
180
twc
Write cycle time
110
130
150
180
ns
155
181
205
245
ns
ns
tRWC
Read-write/read-modify-write cycle time
tpc
Page-mode read or write cycle time
(see Note 7)
40
45
50
55
ns
tpCM
Page-mode read-modify-write cycle time
85
96
100
120
ns
tcp
Pulse duration, CAS high
10
10
10
10
tCAS
Pulse duration, CAS low (see Note 8)
15
tRP
Pulse duration, RAS high (precharge)
40
tRAS
Non-page-mode pulse duration, RAS low
(see Note 9)
60
10000
70
10000
80
10000
100
10000
ns
tRASP
Page-mode pulse duration, RAS low
(see Note 9)
60
100000
70
100000
80
100000
100
100000
ns
10000
18
10000
20
10000
60
50
25
ns
10000
70
ns
ns
twp
Write pulse duration
15
15
15
15
tASC
Column-address setup time before CAS low
0
0
0
0
ns
ns
tASR
Row-address setup time before RAS low
0
0
0
0
ns
tDS
Data setup time before W low (see Note 10)
0
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
0
ns
twcs
W-Iow setup time before CAS low
(see Note 11)
0
0
0
0
ns
tCWl
W-Iow setup time before CAS high
15
18
20
25
ns
tRWl
W-Iow setup time before RAS high
15
18
20
25
ns
tCAH
Column-address hold time after CAS low
(see Note 10)
10
15
15
20
ns
tRAH
Row-address hold time after RAS low
10
10
12
15
ns
tAR
Column-address hold time after RAS low
(see Note 12)
50
55
60
70
ns
tClCH
Hold time, CAS low to CAS high
5
5
5
5
ns
tDH
Data hold time after CAS low (see Note 10)
10
15
15
20
ns
tDHR
Data hold time after RAS low (see Note 12)
50
55
60
70
ns
tRCH
Read hold time after CAS high (see Note 13)
0
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 13)
0
0
0
0
ns
tWCH
Write hold time after CAS low (see Note 11)
15
15
15
20
ns
tWCR
Write hold time after RAS low (see Note 12)
50
55
60
70
ns
ns
15
18
20
OE command hold time
25
tOEH
Continued next page.
NOTES: 5. Timing measurements are referenced to Vil max and VIH min.
6. All cycle times assume tT = 5 ns.
7. tpc > tcp min + tCAS min + 2tT'
8. In a read-modify-write cycle, tCWD and tCWl must be observed. Depending on the user's transition times, this may require additional
CAS low time (tCAS).
9. In a read-modify-write cycle, tRWD and tRWl must be observed. Depending on the user's transition times, this may require additional
RAS low time (tRAS).
10. later of CAS or Vii in write operations.
11. Early write operation only.
12. The minimum value is measured when tRCD is set to tRCD min as a reference.
13. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS . .
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-79
TMS44C260
262 144 WORD BY 4·81T QUAD CAS
DYNAMIC RANDOM·ACCESS MEMORY
SMGS260B -
JANUARY 1990 -
REVISED NOVEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5) (concluded)
TMS44C260-60
TMS44C260-70
MAX
MIN
MIN
MAX
TMS44C260-80
MIN
MAX
TMS44C260-10
MIN
MAX
UNIT
tCSH
Delay time, RAS low to CAS high
60
70
80
100
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
25
ns
tCWD
Delay time, CAS low to W low (see Note 14)
40
46
50
60
tRCD
Delay time, RAS low to CAS low (see Note 15)
20
45
20
52
22
60
25
75
ns
tRAD
Delay time, RAS low to column address
(see Note 15)
15
30
15
35
17
40
20
55
ns
tRAl
Delay time, column address to RAS high
30
35
40
45
ns
tCAl
Delay time, column address to CAS high
30
35
40
45
ns
tRWD
Delay time, RAS low to W low (see Note 14)
85
98
110
135
ns
tAWD
Delay time, column address to W low
(see Note 14)
55
63
70
80
ns
tCLZ
Delay time, CAS low to output low Z
0
0
0
0
ns
tOED
Delay time, OE high before data at DQ
15
18
20
25
ns
tROH
Delay time, OE low to RAS high
10
10
10
10
. ns
tCHR
Delay time, RAS low to CAS high
(see Note 16)
15
15
20
25
ns
tCSR
Delay time, CAS low to RAS low (see Note 16)
10
10
10
10
ns
tRPC
Delay time, RAS high to CAS low
(see Note 16)
0
a
0
0
ns
tREF
Refresh time interval
IT
Transition time
8
8
50
3
3
50
ns
8
3
50
3
8
ms
50
ns
NOTES: 5.Timing measurements are referenced to Vil max and VIH min.
14. Read-modify-write operation only.
15. Maximum value specified only to guarantee access time.
16. CAS-before-RAS refresh only.
PARAMETER MEASUREMENT INFORMATION
1.31 V
~
Oulpul Under Tesl
VCC
"L,2laQ
Rl = 828 Q
~
CL=100pF
Output Under Test - - - . - - - - - - .
T
Cl = 100 pF
(a) Load Circuit
(b) Alternate Load Circuit
Figure 1. Load Circuits for Timing Parameters
TEXAS •
INSlRUMENTS
8-80
=5V
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
R2
=295 Q
TMS44C260
262144 WORD BY 4·BIT QUAD CAS
DYNAMIC RANDOM·ACCESS MEMORY
SMGS260B - JANUARY 1990 -
REVISED NOVEMBER 1990
read cycle
i4~---------------------tRC----------------------~~
RAS
~1IO.~~-=--=--=--=--=--=-::======_tR_A_S_-_-_-_-_-_-_-_-_-_-_-_-_-_-----:Yi
t,- ~ 14I ~ tRCO
~'-____
~I
! tRP I
::~
I..
----.,
~tCAS--y
:I
I
I
I
.
:
I I
I I
I
::
r-------+I~------+----+·---
/:
\l
---~~-----~~-~
~I tClCH
:
I
~tRAO 4
I
I
I
I
~tRAHI
I
I
I
~ .J
I
I tASC ~
~ I
I
I~
'ASR- ~
I
~ I
: tCSH
I~
I
I
I
I
I
I
I
/~-----T:-!------!---+:--
"I
I~
I
~I
i i \1.
14
I
:
I
I
I
~
: :.
I I tClCH
:
I
I:
tClCH (see Note 20)
: :\1.
I
I
I I
I
I
~I
i : i4I
I
14
tcp
I
I
---+I--~~
I
l~tfRP~
I
~
tRSH
:
I
I
I
~I
tCAl
I
I I
I I
I I
tRAl
I
I
I
I
I
I
I
I
I I
~I I
I I
I
I
I I
I I
I
I
~
A~A8 X ~ c~+ ~*H*~:XxfE,,---R:
t
I
I
;,r :
I
t
I ~ tCAH
I
~I
I
I
I
~
~
I
tRRH
~tRCH-1
001·004
NOTES: 17.ln order to hold the address latched by the first CASx going low, the parameter tCLCH must be met.
18. tCAC is measured from CAS x to its corresponding DQx.
19. CAS x order is arbitrary.
20. Output may go from high-impedance to an invalid data state prior to the specified access time.
TEXAS •
INSlRUMENlS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
8-81
TMS44C260
262 144 WORD BY 4-81T QUAD CAS
DYNAMIC RANDOM-ACCESS MEMORY
SMGS260B -
JANUARY 1990 -
REVISED NOVEMBER 1990
write cycle
~
I
I
I
I
~
OE~
NOTES: 10.
17.
18.
19.
\ ' - - -_ _
Later of CAS or IN in write operations.
In order to hold the address latched by the first CASx going low, the parameter tCLCH must be met.
tCAC is measured from CASx to its corresponding DQx.
CASx order is arbitrary.
TEXAS
l!}
INSTRUMENTS
8-82
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TMS44C260
262144 WORD BY 4·BIT QUAD CAS
DYNAMIC RANDOM·ACCESS MEMORY
SMGS260B - JANUARY 1990 -
REVISED NOVEMBER 1990
early write cycle timing
__________ ~I~--------------------twc---------------------~I
~I
~~------------tRAS--------------~~
tT ~
14-
,
, 14-- tRCO ~
~
,
CAS2
I
I I
Nl4-tCAS
,, ,,
, ,
~
, ,
:
rtClCH
I:
,I
, I
, ,
I I
,I
~
v
i
I
tRP
~
,
I,
,I,
!,' " - - -
'"
:
: '
I
_,'
, I
'-----
.,'
,
-+,----'-----..,
I
,
,
, I
I .t4-------- tRSH
I
-----------1~,----------4,~,~.\
/~:~--~I--------------,~--
,,
CAS4
1
, ~tCRP-.J
-.ly
'
, ,
CAS3
-----------cr...,
tCSH
, ,
CAS1
~,'
~
L..
,
,I.
,
,
,,
I ,
,
~ tRAO
, I
I~
tASR --l4---~~
,
'
I
"
Jif
,
I
,
~--~,--------------I~-i'
i
,
'--------~, 14-1"1--+--- tcp -------.r.1
-.!:' \.
'I
I,
'
,I ,
,'
I
tCAl - - - - . - ; . :
I
I
,~tRAH " I
I
I
, ,tASC~'
I
: I
~:
I
I ______~~I
~
,
. , '
,
,
~t~RA~l~-~-~-~-~'~-~-~-~-~~~~~~~~~~~
AO-AB
.!~--twcs
w
tAR
, \ ~
''{
,
I
:
-I144----.!~
ri
, J4- tWCH
I I
-.,V
"
!I~
------------+:----<~
:
i
I
,
I tCWl
I
,
I I
tRWl ---I~-------bl~
i.II
~
~~,-~--tWCR
OQ1-0Q4
:
:
::
Valid
~
~
Dat~n
I
I
~
twp
)>-------------------------------I
I
tOH
14'~------!-1- - tOHR ~
14-- tos ~
NOTES: 17. In order to hold the address latched by the first CASx going low, the parameter tClCH must be met.
18. tCAC is measured from CAS x to its corresponding OQx.
19. CASx order is arbitrary.
. TEXAS-I!1
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-83
TMS44C260
262 144 WORD BY 4-BIT QUAD CAS
DYNAMIC RANDOM-ACCESS MEMORY
SMGS260B -
JANUARY 1990 -
REVISED NOVEMBER 1990
read-write/read-modify-write cycle
NOTES: 17. In order to hold the address latched by the first CASx going low, the parameter tCLCH must be met.
18. tCAC is measured from CASx to its corresponding OQx.
19. CASx order is arbitrary.
TEXAS l/1
INSTRUMENTS
8-84
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44C260
262 144 WORD BY 4-BIT QUAD CAS
DYNAMIC RANDOM-ACCESS MEMORY
SMGS260B -
JANUARY 1990 -
REVISED NOVEMBER 1990
enhanced page-mode read cycle timing
rt .,
~~--------------------tAASP------------------~~
tAP
I 14- tACO
I I
:
~
~:'--1-~
/
I
I
CAS2
CAS3
CAS4
1
--------~i----~~
~
----:!INI I~
-----+~:I
I
•
!
i4-- tAA
I ~.
I
I
I
I
ti
tAAH
~
I
I
~
I I
AII tCLCH
~ ~
tCSH
1
1
I1
1
1
I
I
!
I~
tpc
"'1 I
!
:
I~
I I
tcp
~
1
1
1
."
~
tASH
I
I
.1}~~'!I~__~!t
r: tCAS --ry
I
'L
Y!
Lw.
I'" I
I I
I:
,,~------~r1~------+i~---------
14-~--~1
1
~
-----+'+'--~N
sA
i
I~ tCAP
I
I
I
1
:
I
I
1
1
~ I
I
I
'tAAL .-------~
/4-tCAL
I
tASC
~
tCAH
AO·AS
OQ1
OQ2
OQ3
OQ4
------------<~ V~~? )>-----<<< "J~~ )>-------
r---
I
tOEA - - . ,
\{,,--I_ _ _ _
-----II
NOTES: 17.
18.
19.
20.
21.
In order to hold the address latched by the first CAS x going low, the parameter tCLCH must be met.
tCAC is measured from CASx to its corresponding OQx.
CASx order is arbitrary.
Output may go from high-impedance to an invalid data state prior to the specified access time.
A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
22. Access time is tCAP or tCAA dependent.
TEXAS ~
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TMS44C260
262 144 WORD BY 4-81T QUAD CAS
DYNAMIC RANDOM-ACCESS MEMORY
SMGS260B -
JANUARY 1990 -
REVISED NOVEMBER 1990
enhanced page-mode write cycle timing
N
:
tRASP
:~------------------------------~-------tR-S-H-~--~1
~
~I
Ii
I I
j
I 1_
I I
I I
I I
I ~
: Lt
I
f'"
RCO
I 14
I~
I
.i i
N--
I ~
~tAR I I
I
I I
I tASC -'1 ~
I~
II"
I
I
;
I
I
I
V
I~
I ~
~ 14-
I : tCSH
IASR
N
tCLCH ~
LJ\
I
I
IR:~
-----------ty
i\
leAS
.1
-r
I
I
I:
iI
I
114---111 tCRP
: \
I:
~
I
I
~
-----
!
I
I
-.I
~
1.,.---+-_ _ _ _ _ __
tpc
I
I
I
I
I
I
tCAH
~
tcp
/
I
I
I
I
:
I
~
I
_--"-I-
~---~~.
....
~~~~~~~~~~~~~~
AD-A8
II
I
14----i-L,- - tCWL
I
I twp ~
(see Note 23) ~~-7---+-r1 tWCR
tos
~
I
w
I I
I
----<
----<
----<
----<
I
I
I
I
tWCH
I
I
:V.II. In
~tOH
Valid In
~
I
J
~
(
Valid In
>
(
Not Written
(
Valid In
(
Valid In
>
>
>
(see Note 23)
)
I
Valid In
,
004
tRWL - - - .
tOHR ~
I
003
.1
I
~
I
I
I
002
1!4
~twcs
~-~~~·I
I
I
.:
I
-t1
I
001
~tCWL~
----.!'
)
I
Valid In
I
J
14- tOED
OEJ
NOTES: 17.
18.
19.
21.
In order to hold the address latched by the first CASx going low, the parameter tCLCH must be met.
tCAC is measured from CASx to its corresponding DQx.
CASx order is arbitrary.
A write cycle or read-modify-writc cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
23. Referenced to CASx or W, whichever occurs last.
TEXAS -I!I
INSlRUMENTS
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TMS44C260
262 144 WORD 8Y 4-81T QUAD CAS
DYNAMIC RANDOM-ACCESS MEMORY
SMGS260B -
JANUARY 1990 -
REVISED NOVEMBER 1990
enhanced page mode read-modify-write cycle
~
~I I
tRP
14
I
RAS
tRASP
~
tCSH
CAS3
CAS4
-.I ~
AO·A8
W
I
I
I I
11
I I
tASR
~ ~
.:
I
~
I I...
-+J
I
IIII i+-tcwo
~ tAWO -..! I~
I 1
~ tRAC
tCLZ
-.j
1
_I
--..I
I
Column
I
tCWL
~I twp
1 I
VIH
VIH
VIL
1
-.ll.L1
1
1 1
I 1
~
I~
~
I
I
I
:
J+
tCAP
tos
VIH
VIL
I
1
I
I
I
I
I
I
I
VIH
VIL
~
1
I
.'1
N _1
~ tCA<
I ~
I~ 1
I I
V
I
tCAH
::~
tRCS
I tCAA
+I
I~
I
I
I
I
I
~I
VIH
VIL
1
_I
tRWL
~
~I
I
I
I
I
I
VIH
VIL
tOEH
VIH/VOH
VILIvOL
I
Valid Out
I
l.-tOEA~
I
G
tCRP
VIL
I
I
4\:
I II I
001·
004
~
r
1
I
.:,t~WD
I
VIL
I
I
I
~
--.I
VIH
V
.1
~~Olumn~
--.l
tRAH
1
I
~
I
I
I
1
1
tcp
tt SC
tRAO
I
tCAS
1
I
I
1
I
I
I
I
I
I
1
I
I
I
I I
I I
I I
I I
I I 1
CAS2
I~ I
tpCM
I
CASl
0
~I
tRSH
~
1
I
tRCO
1I
~
NOTES: 17.
18.
19.
24.
tOEH
-Ji.l
tOEZ
I~
I
1
I
I
tOED
~
VIH
VIL
In order to hold the address latched by the first CAS x going low, the parameter tCLCH must be met.
tCAC is measured from CAS x to its corresponding OQx.
CASx order is arbitrary.
A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write cycle timing specifications are
not violated.
TEXAS ~
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8-87
TMS44C260
262 144 WORD BY 4·BIT QUAD CAS
DYNAMIC RANDOM·ACCESS MEMORY
SMGS260B -
JANUARY 1990 -
REVISED NOVEMBER 1990
RAS-only refresh timing
OQ1-0Q4 - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - -
NOTE 25:
All CASx must be high.
TEXAS
4J1
INSlRUMENTS
8-88
POST OFFICE BOX 1443
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TMS44C260
262144 WORD 8Y 4-81T QUAD CAS
DYNAMIC RANDOM-ACCESS MEMORY
SMGS260B - JANUARY 1990 -
REVISED NOVEMBER 1990
hidden refresh cycle
~ Refresh Cycle ~
14- Memory Cycle ----.I
tRAS:
~
~I
CASx
tASR
I
tRP
I I
I I
I ~
I
I
I
I I
I
~~
tRAH
Icl- Refresh Cycle ~
~ lei
~
\
I
~
1'4
N
14
I I
~
N 11
Y!
RASN
I
I I
-
tRAS:
tRP
:
I~VIH
VIL
I
tCHR
tCAS
Y! r! - VIH
Row
t
~? I
RCS~I
~
ww: ::I~
I
I
tRAC
I~
VIL
I
cOI:gg~\~l~«XXX><50
~tCAC
I
_ _
~
~ tCAA
~IH
~L
I
tOFF --r-!
~
VIH
VIL
14-
I
DQ1-DQ4~~~~~~~1~~~~~~~~~~~-v-a-li-d-D-~-a~~~~~~:~~~~~~~~~VIH/VOH
~I~~~~~~~~~~~~~~~~~~~~~~~~~~~~I
~
~ tOEA
VIL/VOL
lei-- tOEZ ~
\i_!~~~~~~~~~~~~~~_~~_---'1()~.....~-~~~~-~::
1
automatic (CAS-before-RAS) refresh cycle timing
~~---------------------tRC--------------------~
~
~ tRP ---.r ~~------tRAS - - - - - - - - - D~i
RAS
~~:~--~~~~~-~~~~~~~~~~~~~~V
tRPC
-.J
r-
____~~~,
CASx
I
I
--.j
I
~ tT
VIH
VIL
~leI----tCHR------ 1>1
V
\ ,~~tCSR~
'\
gx~tgir!
AO-AS
VIH
VIL
VIH
VIL
gx~tgir!
W
VIH
VIL
DQ1-DQ4
NOTE 26:
-~~~~~~~~~~~~~~-
HI-Z
VIH
-~~~~~~~~~~~~~-
Any CASx may be used.
TEXAS •
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TMS44C260
262 144 WORD BY 4-81T QUAD CAS
DYNAMIC RANDOM-ACCESS MEMORY
SMGS260B -
JANUARY 1990 -
REVISED NOVEMBER 1990
TEXAS ~
INSlRUMENlS
8-90
POST OFFICE BOX 1443
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TMS48C121
131 072 BY 8·BIT
MULTIPaRT VIDEO RAM
SMVS121 A -
•
DRAM: 131 072 Words x a Bits
SAM: 256 x a Bits
•
Dual Port Accessibility - Simultaneous
and Asynchronous Access From the
DRAM and SAM Ports
•
•
•
APRIL 1989 -
REVISED NOVEMBER 1990
DZ Package
(Top View)
SC
Bidirectional Data Transfer Function
Between the DRAM and the Serial Data
Register
SDOO
VSS
SDQ7
SD01
SD06
SD02
SDOS
SD03
SD04
TRG
SE
DOO
D07
D01
D06
4 x a-Block Write Feature for Fast Area Fill
Operations. As Many as Four Memory
Address Locations Written Per Cycle From
an On-Chip Color Register
D02
DOS
D03
D04
VCC
VSS
DSF
VIi
Write-Per-Bit Feature for Selective Write to
Each RAM I/O. Two Write-Per-Bit Modes to
Simplify System Design
NC
RAS
NC
CAS
•
NC
OSF
Enhanced Page-Mode Operation for Faster
Access
AS
AO
A6
A1
•
CAS-before-RAS and Hidden Refresh
Modes
AS
A2
A4
A3
VCC
A7
•
•
Up to 33 MHz Uninterrupted Serial Data
Streams
PIN NOMENCLATURE
Split Serial Data Register for Simplified
Realtime Register Reload
•
3-State Serial I/Os Allow Easy Multiplexing
of Video Data Streams
•
256 Selectable Serial Register Starting
Locations
•
~
a:
ou.
z
Long Refresh Period ... Every a ms (Max)
•
•
z
o
~
AO-AS
CAS
000-007
SE
RAS
SC
SDOO-SD07
TRG
Vi
DSF
OSF
VCC
VSS
NC
All Input/Outputs and Clocks TTL
Compatible
Address Inputs
Column Enable
DRAM Data In-Out/Write Mask Bit
Serial Enable
Row Enable
Serial Data Clock
Serial Data In-Out
Transfer Register/O Output Enable
Write Mask Select/Write Enable
Special Function Select
Split-Register Activity Status
5-V Supply (TYP)
w
(.)
z
~
c
m--
~S:=i~
TMS48C121
131 072 BY 8·BIT
MULTIPORT VIDEO RAM
SMVSI21A-APRIL 1989 - REVISED NOVEMBER 1990
Detailed Pin Description vs Operational Mode
PIN
AD-AS
CAS
DO
DSF
RAS
SE
SC
SDO
TRG
IN
TRANSFER
DRAM
Row, Column Address
Column Enable, DO Output Enable
DRAM Data I/O, Write Mask Bits
Block Write Enable
Persistent Write-Per-Bit Enable
r
Color Register Load Enable
Row Enable
Split Register Enable
Alternate Write'Transfer Enable
Row Enable
Serial-In Mode Enable
Q Output Enable
Write Enable, Write-Per-Bit Select
"
Serial Enable
Serial Clock
Serial Data I/O
Transfer Enable
Transfer Write Enable
QSF
Split Register
Active Status
NC
Not Connected to External VSS
VCC t
5-V Supply
Ground
vsst
SAM
Row, Tap Address
Tap Address Strobe
t For proper device operation, both VCC pins must be connected to a 5-V supply and both VSS pins must be tied to ground.
operation
random access operation
Refer to Table 1, Functional Truth Table, for Random Access and Transfer Operations. Random access
operations are denoted by the designator "R" and transfer operations are denoted by a "T".
transfer register select and DQ enable (TRG)
The TRG pin selects either register or random access operation as RAS falls. For the random access (DRAM)
mode, TRG must be held high as RAS falls. Asserting TRG high as RAS falls causes the 256 storage elements
of each data register to remain disconnected from the corresponding 256-bit lines of the memory array.
(Asserting TRG low as RAS falls connects the 256-bit positions in the serial register to the bit lines and indicates
that a transfer will occur between the data registers and the selected memory row. (See "Transfer Operation"
for details.)
During random access operations, TRG also functions as an output enable for the random (0) outputs.
Whenever TRG is held high, the Q outputs are in the high-impedance state to prevent an overlap between the
address and DRAM data. This organization allows the connection of the address lines to the data I/O lines but
prohibits the use of the early write cycle. It also allows read-modify-write cycles to be performed by providing
a three-state condition to the common I/O pins so that write data can be driven onto the pins after output read
data has been externally latched.
address (AD through AS)
Seventeen address bits are required to decode 1 of 131 072 storage cell locations. Nine row address bits are
set up on pins AO through A8 and latched onto the chip on the falling edge of RAS. Then, eight column address
bits are set up on pins AO through A7 and latched onto the chip on the falling edge of CAS. All addresses must
be stable on or before the falling edges of RAS and CAS .
TEXAS
.
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~
INSlRUMENlS
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POST OFFICE BOX 1443
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TMS48C121
131 072 BY 8-BIT
MULTIPORT VIDEO RAM
SMVS121A -APRIL 1989 -
REVISED NOVEMBER 1990
RAS and CAS address strobes and device control clocks
RAS is a control input that latches the states of the row address, W, TRG, SE, CAS, and DSF onto the chip to
invoke the various DRAM and transfer functions of the TMS48C121. RAS is similar to a chip enable in that it
activates the sense amplifiers as well as the row decoder. CAS is a control input that latches the states of the
column address and DSF to control various DRAM and transfer functions. CAS also acts as an output enable
for the DRAM output pins.
special function select (OSF)
The Special Function Select input is latched on the falling edges of RAS and CAS, similarly to an address, and
serves four functions. First, during write cycles DSF invokes persistent write-per-bit operation. If TRG is high,
W is low, and DSF is low on the falling edge of RAS, the write mask will be reloaded with the data present on
the DO pins. If DSF is high, the mask will not be reloaded but will retain the data from the last mask reload cycle.
Secondly, the DSF is used to change the internally stored write per bit mask register (or write mask) via the load
write mask cycle. The data present on the DO pins when W falls is written to the write mask rather than to the
addressed memory location. See "Delayed Write Cycle Timing" and the accompanying "Write Cycle State Table"
in the timing diagram section. Once the write mask is loaded, it can be used on subsequent masked write per
bit cycles. This feature allows systems with a common laddress and data bus to use the write-per-bit feature,
eliminating the time needed for multiplexing the write mask and input data on the data bus.
Third, the DSF is used to load an on-chip four-bit data, or "color," register via the Load Color Register cycle. The
contents of this register can subsequently be written to any combination of four adjacent column memory
locations using an 4 x 8-Block Write feature. The load color register cycle is performed using normal write cycle
timing except that DSF is held high on the falling edges of RAS and CAS. Once the color register is loaded, it
retains data until power is lost or until another load register cycle is performed.
After loading the color register, the block write cycle can be enabled by holding DSF high on the falling edge of
CAS. During block write cycles, only the six most significant column addresses (A2-A7) are latched on the falling
edge of CAS. The two least significant addresses (AO-A 1) are replaced by four DO bits (000, 001, 002, and
003), which are also latched on the later of CAS or Wfalling. These four bits are used as an address mask or
column select and indicate which of the four column address locations addressed by A2-A7 will be written with
the contents of the color register during the write cycle. 000 enables a write to column address A 1 = 0 (A 1 low),
AD = D (AD low) 001 enables awrite to column address A 1 = D (A 1 low), AO = 1 (AO high); 002 enables a write
to column address A1 = 1 (A1 high), AO = D (AD low); and 003 enables a write to column address
A1 = 1 (A1 high), AO = 1 (AO high). A high logic level enables a write and a low logic level disables the write. A
maximum of 32 bits can be written to memory during each CAS cycle (see Figure 1, Block Write Diagram).
Fourth, the DSF pin is used to invoke the split register transfer and serial access operation described in the
sections "Transfer Operation" and "Serial Operation."
TEXAS •
INSTRUMENTS
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8-95
TMS48C121
131 072 BY 8-BIT
MULTIPaRT VIDEO RAM
SMVS121A- APRIL 1989 - REVISED NOVEMBER 1990
N+1
N
N+2
N+3
1/07D DDD
Block Write
Enable
AO-A1
A2-A7
DO
Load
Color
Register
---J
'1
I Load Color Register Cycle
I
I
RAS
n
Block Write Cycle
(No DO Mask)
1
t
Block Write Cycle t
(Load and Use DO Mask)
''______1 '
,'___~/,..~----....,'_____/,..~----....\
AO-AB
Block Write Cycle t
(Use Previously
Loaded DO Mask)
I
I
I
---J1"l
/,--t---....,'-_ _ _
1
---J;-;
,'-__
2
wt~~
DQ~D:::
t W must be low during the Block Write Cycle.
t DOD-D07
(CAS) are latched on the later of War CAS falling edge. DOD-D07 (RAS) are latched on RAS falling edge.
Legend:
1.
Refresh Address
2.
Row Address
3.
Column Start Address (AD-A8)
4.
Color Register Data
5.
Column Mask Data
6.
DO Mask Data
~ '" Don't Care
Figure 1. Block Write Diagram
write enable, write-per-bit enable and persistent write-per-bit enable (W)
The W pin enables data to be written to the DRAM and also is used to select the DRAM write-per-bit mode of
operation. A logic high level on the W input selects the read mode and logic low level selects the write mode.
In an Early Write cycle, W is brought low before CAS and the DRAM output pins (DQ) remain in the
high-impedance state for the entire cycle. During DRAM write cycles, holding W 10'1/ on the falling edge of RAS
will invoke the write-per-bit operation. Two modes of write-per-bit operation are supported .
TEXAS
.
,.
~
INSlRUMENTS
8-96
POST OFFICE BOX 1443
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HOUSTON, TEXAS 77001
TMS48C121
131 072 BY 8-BIT
MULTIPaRT VIDEO RAM
SMVS121A -APRIL 1989- REVISED NOVEMBER 1990
Case 1. If DSF is low on the falling edge of RAS, the write mask is reloaded. Accordingly, a four-bit binary code
(the write-per-bit mask) is input to the device via the random DO pins and is latched on the falling edge of RAS.
The write-per-bit mask selects which of the four random I/Os are written and which are not. After RAS has latched
the write mask on-chip, input data is driven onto the DO pins and is latched on the falling edge of the later of
CAS or W. If a low was strobed into a particular I/O pin on the falling edge of RAS, data will not be written to
that I/O. If a high was strobed into aparticular I/O pin on the falling edge of RAS, data will be written to that I/O.
Case 2. If DSF is high on the falling edge of RAS, the mask is not reloaded from the DO pins but instead retains
the value stored during the last write-per-bit mask reload. This mode of operation is known as persistent writeper-bit, since the write-per-bit mask is persistent over an arbitrary number of cycles.
See the corresponding timing diagrams for details. IMPORTANT: The write-per-bit operation is invoked only if
Wis held low on the falling edge of RAS. If W is held high on the falling edge of RAS, write-per-bit is not enabled
and the write operation will be performed to all 8 inputs.
data I/O (DQO-DQ7)
DRAM data is written during a write or read-modify-write cycle. The falling edge of W strobes into the on-chip
data latches. In an early-write cycle, W is brought low prior to CAS and the data is strobed in by early CAS with
data setup and hold times referenced to this signal. In a delayed write or read-modify-write cycle, CAS will
already be low. Thus, the data will be strobed-in by W with data setup and hold times referenced to this signal.
The three-state output buffers provide direct TTL compatibility (no pull-up resistors) with a fanout of two Series
74 TTL loads. Data-out is the same polarity as data-in. The outputs are in the high-impedance (floating) state
as long as CAS or TRG is held high. Data will not appear at the outputs until after both CAS and TRG have
been brought low. Once the outputs are valid, they remain valid while CAS and TRG are low. CAS orTRG going
high returns the outputs to a high-impedance state. In an early-write cycle, the outputs are always in the
high-impedance state. In a register transfer operation (memory to register or register to memory), the outputs
remain in the high-impedance state for the entire cycle.
refresh
A refresh operation must be performed to each row at least once every eight milliseconds to retain data. Since
the output buffer is in the high-impedance state (unless CAS is applied), the RAS-only refresh sequence avoids
any output during refresh. Strobing each of the 512 row addresses with RAS causes all bits in each rowto be
refreshed. CAS can remain high (inactive) for this refresh sequence to conserve power.
CAS-before-RAS refresh
CAS-before-RAS refresh is accomplished by bringing CAS low earlier than RAS. The external row address is
ignored and the refresh address is generated internally when using CAS-before-RAS refresh. 512 cycles must
be performed within eight milliseconds, but not necessarily in succession. Other cycles may be performed in
between CAS-before-RAS cycles without disturbing the internal address generation.
NC
The pins should be tied to system ground or left floating (no connection) for proper device operation.
IMPORTANT: NC is not connected internally to
Vss.
TEXAS
lJ1
INSTRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-97
TMS48C121
131 072 BY 8-BIT
MULTIPORT VIDEO RAM
SMVS121A-APRIL 1989- REVISED NOVEMBER 1990
Table 1. Function Table
T
Y
p
Et
CAS
FALL
RAS FALL
CAS
TRG
Wfl
DSF
SE
DSF
ADDRESS
RAS
DOC-D07
CAS
RAS
CAS:!:
FUNCTION
W
R
L
X§
x
x
x
x
x
x
x
X
CAS-before-RAS refresh
T
H
L
L
X
L
X
Row
Addr
Tap
Point
X
X
Register to memory transfer
(Transfer Write)
T
H
L
L
H
X
X
Row
Addr
Tap
Point
X
X
Alternate transfer write
(Independent of SE)
T
H
L
L
L
H
X
Refresh
Addr
Tap
Point
X
X
Serial write-mode enable
(Psuedo-transfer write)
T
H
L
H
L
X
X
Row
Addr
Tap
Point
X
X
Memory to register transfer
(Transfer read)
T
H
L
H
H
X
X
Row
Addr
Tap
Point
X
X
Split register transfer read
(Must reload tap)
R
H
H
L
L
X
L
Row
'Addr
Col
Addr
Write
Mask
Valid
Data
Load and use write mask,
write data to DRAM
R
H
H
L
L
X
H
Row
Addr
Col
A2-A7
Write
Mask
Addr
Mask
Load and use write mask,
block write to DRAM
R
H
H
L
H
X
L
Row
Addr
Col
Addr
X
Valid
Data
Persistent write per bit,
write data to DRAM
R
H
H
L
H
X
H
Row
Addr
Col
A2-A7
X
Addr
Mask
Persistent write per bit,
block write to DRAM
R
H
H
H
L
X
L
Row
Addr
Col
Addr
X
Valid
Data
Normal DRAM read/write
(Non masked)
R
H
H
H
L
X
H
Row
Addr
Col
A2-A7
X
Addr
Mask
Block write to DRAM
(Non masked)
R
H
H
H
H
X
L
Refresh
Addr
X
X
Write
Mask
Load write mask
R
H
H
H
H
X
H
Refresh
Addr
X
X
Color
Data
Load color register
tR
=,Random access operation; T = Transfer operation
:j: DOO-D07 are latched on the later of Wor CAS falling edge,
§ X = Don't care
flln persistent write-per-bit function, Wmust be high during the refresh cycle.
Addr Mask = H: Write to address/column location enabled (DOO, D01, D02, D03).
Write Mask = H: Write to I/O enabled.
Jl~
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TMS48C121
131 072 BY 8-BIT
MULTIPaRT VIDEO RAM
SMVS121A -APRIL 1989 -
REVISED NOVEMBER 1990
random port to serial port interface
Random-Access Port
Col
127
Col
o
Col
128
Col
255
Row
o
TRG
A7
DSF
Vi
Transfer
Control
Logic
SE
SC
AO-A7
Figure 1. Block Diagram Showing One Random and One Serial I/O Interface
random-address space to serial-address space mapping
The 256 bits in each of the eight data registers of the SAM are connected to the 256 column locations of each
of the eight random I/Os. Data can be accessed in or out of the SAM starting at any of the 256 data bit locations.
This start location is selected by addresses AO through A7 on the falling edge of CAS during any transfer cycle.
The SAM is accessed starting from the selected start address, proceeding from the lowest to the highest
significant bits. After the most significant bit position (255) is accessed, the serial counter wraps around such
that bit 0 is accessed on the next clock pulse. The selected start address is stored and used for all subsequent
transfer cycles until CAS is again brought low during any transfer cycle. Thus, the start address can be set once
and CAS held high during all subsequent transfer cycles and the start address paint will not change regardless
of data present on AO through A7.
split-register mode random-address to serial-address space mapping
In split-register transfer operation, the serial-data register is split into halves, the low half containing bits 0 through
127 and the high half containing bits 128 through 255. When a split-register transfer cycle is performed, the "tap"
address must be strobed in on the falling edge of CAS. The most significant column address bit A7 determines
which register half will be reloaded from the memory array. The seven remaining column address bits (AO-A6)
are used to select the SAM starting location for the register half selected by A7.
To insure proper operation when using the split-register read transfer feature, a non-split register transfer must
precede any split register sequence. The serial start address must be supplied for every split-register transfer.
(See Split-Register Operating Sequence on page 8-123.)
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SMVS121A- APRIL 1989 - REVISED NOVEMBER 1990
transfer operations
The Serial Enable pin SE has two functions: first, it is latched on the fallilng edge of RAS, with both TRG and
W low to select one of the transfer functions. If SE is low during this transition, then a transfer write occurs. If
SE is high as RAS falls and OSF is low, then a write mode control cycle is performed. The function of this cycle
is to switch the SOOs from the output mode to the input mode, thus allowing data to be shifted into the data
register.
NOTE: All transfer-write modes will switch the SOOs from the output mode to the input mode. All transfer read
and serial mode enable (psuedo transfer write) operations will perform a memory refresh operation on the
selected row.
As illustrated in Table 1, the TMS48C121 supports five basic modes of transfer operation:
1.
2.
3.
4.
5.
Normal Write Transfer (SAM to DRAM)
Alternate Write Transfer (independent of the state of SE)
Pseudo Write Transfer (Switches serial port from serial out mode to serial in mode. No actual data transfer
takes place between the ORAM and the SAM.)
Normal Read Transfer (Transfer entire contents of DRAM row to SAM)
Split-Register Read Transfer (Oivides the SAM into a high and a low half. Only one half is transferred to the
SAM while the other half is read from the serial I/O port.)
Note: All transfer write modes will switch the SDO's from the output mode into the input mode.
transfer register select (TRG)
Transfer operations between the memory array and the data registers are invoked by bringing TRG low before
RAS falls .. The states of W, SE, and DSF, which are also latched on the falling edge of RAS, determine which
transfer operation will be invoked.
During read transfer cycles, TRG going high causes the addressed row of data to be transferred into the data
register. Although the previous data in the data register is overwritten, the last bit of data appearing at SOO before
TRG goes high will remain valid until the first positive transition of SC after TRG goes high. The data at SDO
will then switch to new data beginning from the selected start, or "tap" position.
transfer write enable (W)
In the register-transfer mode, W determines whether a read or a write transfer will occur.·To perfom a write
transfer, Wand SE are held low as RAS falls except for alternate transfer-write. If SE is high during this transition,
no transfer of data from the data register to the memory array occurs, but the SDOs are put into the input mode.
This allows serial data to be input into the SAM. An alternative way to perform the transfer-write cycle is by
holding DSF high on the falling edge of RAS. In this way, the state of SE is a don't care as RAS falls. To perform
a read transfer operation, W is held high and SE is a don't care as RAS falls. This cycle also puts the SDOs into
the read mode, allowing data to be shifted out of the data register.
column enable (CAS)
If CAS is brought low during a pseudo write transfer cycle, the address present on the pins AO through A7 will
become the new register start location. If CAS is held high during a pseudo write transfer cycle, the previous
tap address will be retained from the last transfer cycle in which CAS went low to set the tap address.
address (AO through AS)
Nine bits are required to select one of the 512 possible rows involved in the transfer of data to or from the data
registers. The states of AO-A8 are latched on the falling edge of RAS to select one of 512 rows for the transfer
operation.
To select one of the 256 positions in the SAM from which the first serial data will be accessed, the appropriate
8-bit column address (AO-A7) must be valid when CAS falls. However, the CAS and start (tap) position need
not be supplied every cycle, only when changing to a different start position.
".
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TMS48C121
131 072 BY 8·BIT
MULTIPaRT VIDEO RAM
SMVS121A -APRIL 1989- REVISED NOVEMBER 1990
In the split-register transfer mode, the most significant column address bit (A7) selects which half of the register
will be reloaded from the memory array. The remaining seven addresses (AO-AS) determine the register starting
location for the register to be reloaded.
special function input (DSF)
In the read-transfer mode, holding DSF high on the falling edge of RAS selects the split-register mode transfer
operation. This mode divides the serial data register into a high-order half and a low-order half; one active, and
one inactive. When the cycle is initiated, a transfer occurs between the memory array and either the high-half
or the low-half register, depending on the state of most significant column address bit (A7) that is strobed in on
the falling edge of CAS. If A7 is high, the transfer is to the high half of the register. If A7 is low, the transfer is
to the low half of the register. Use of the split-register-mode read-transfer feature allows on-the-fly read transfer
operation without synchronizing TRG to the serial clock.
In the write-transfer mode, holding DSF high on the falling edge of RAS permits use of an alternate mode of
transfer write. This mode allows SE to be high on the falling edge of RAS without performing a pseudo write
transfer, with the serial port disabled during the entire transfer write cycle.
serial clock (Se)
Data (SDO) is accessed in or out of the data registers on the rising edge of SC. The TMS48C121 is designed
to work with a wide range of clock duty cycles to simplify system design. Since the data registers comprising
the SAM are of static design, there are no SAM refresh requirements and there is no minimum SC clock
operating frequency.
serial data input/output (SDQO-SOQ7)
SO and SO share a common I/O pin. Data is input to the device when SE is low during a write mode and data
is output from the device when SE is low during read mode. The data in the SAM will be accessed in the direction
from least significant bit to the most significant bit. The data registers operate modulo 25S. Thus, after bit 255
is accessed, the next bits to be accessed will be bits 00, 01, 02, and so on.
serial enable (SE)
During serial access operations, SE is used as an SDO enable/disable. In the write mode, SE is used as an input
enable. SE high disables the input and SE low enables the input. To take the device out of the write mode and
into the read mode, a transfer read cycle must be performed. The read mode allows data to be accessed from
the data register. While in the read mode, SE high disables the output and SE low enables the output.
IMPORTANT: While SE is held high, the serial clock is not disabled. Thus, external SC pulses will increment
the internal serial address counter regardless of the state of SE. This ungated serial clock scheme minimizes
access time of serial output from SE low since the serial clock input buffer and the serial address counter are
not disabled by SE.
split-register active-status output (QSF)
During the split-register mode of serial access operation, OSF indicates which half of the serial register in the
SAM is being accessed. If OSF is low, the serial address pointer is accessing the lower (least significant) 128
bits of the SAM. If OSF is high, the pOinter is accessing the higher (most significant) 128 bits of the SAM. OSF
changes state upon crossing the boundary between the two register halves.
power-up
To achieve proper device operation, an initial pause of 200 Ils is required after power-up, followed by a minimum
of eight RAS cycles or eight CAS-before-RAS cycles, a memory to register transfer cycle, and two SC cycles.
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MULTIPaRT VIDEO RAM
SMVS121A-APRIL 1989- REVISED NOVEMBER 1990
absolute maximum ratings over operating free-air temperature t
Voltage on any pin except DO and SDO '(see Note 1) .................................... - 1 V to 7 V
Voltage on DO and SDO (see Note 1) ................................................ - 1 V to 6.5 V
Voltage range on Vee (see Note 1) ................................................... -1 V to 7 V
Short-circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... -1 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ...................................................... - 65°C to 150°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may ~ause permanent damage to the device. This is a stress rating only. and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
»
c
~
z
o
m
-z
-n
o
:c
s:
~
o
z
VCC
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage (see Note 2)
TA
Operating free-air temperature
MIN
NOM
MAX
4.5
5
5.5
V
2.4
6.5
V
-1
0.8
V
0
70
°c
UNIT
V
0
NOTE 2: The algebraic convention, where the more negative (less psoitive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions
PARAMETER
TEST
CONDITIONS
VOH
High-level output voltage
10H =-2mA
VOL
Low-level output voltage
10L = 2 mA
II
SAM
PORT
TMS48C121-80
MIN
MAX
2.4
TMS48C121-10
MIN
MAX
2.4
TMS48C121-12
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
Input current (leakage)
VI = 0 to 5.8,
VCC = 5.5
All other pins at
OtoVCC
±10
±10
±10
IlA
10
Output leakage current
(see Note 3)
Vo = OtoVCC,
VCC = 5.5 V
±10
±10
±10
IlA
ICCI
Operating current, tc(RW) = minimum
Standby
100
80
70
ICC1A
Operating current, tc(SC) = minimum
Active
120
95
85
ICC2
Standby current, All clocks = VCC
Standby
10
10
10
ICC2A
Standby current, tc(SC) = minimum
Active
35
35
30
ICC3
RAS-only refresh current, tc(RW) = minimum
Standby
100
80
70
ICC3A
RAS-only refresh current, tc(SC) = minimum
Active
120
95
85
ICC4
Page-mode current, tc(P) = minimum
Standby
'55
45
40
ICC4A
Page-mode current, ta(SC) = minimum
Active
65
55
50
ICC5
CAS-before-RAS current, tc(RW) = minimum
Standby
100
80
70
ICC5A
CAS-before-RAS current, tc(SC) = minimum
Active
120
95
85
ICC6
Data transfer current, tc(RW) = minimum
Standby
100
80
70
Data transfer current, tc(SC) = minimum
Active
120
95
85
ICC6A
-
NOTE 3: SE is disabled for SDa output leakage tests.
..-
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mA
TMS48C121
131 072 BY 8-BIT
MULTIPaRT VIDEO RAM
SMVS121A -
APRIL 1989 -
REVISED NOVEMBER 1990
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 4)
MIN
PARAMETER
MAX
UNIT
Ci(A)
Input capacitance. address inputs
6
pF
Ci(RC)
Input capacitance. strobe inputs
7
pF
Ci(W)
Input capacitance. write enable input
7
pF
Ci(SC)
Input capacitance. serial clock
7
pF
Ci(SE)
Input capacitance. serial enable
7
pF
Ci(OSF)
Input capacitance. special function
7
pF
Ci(TRG)
Input capacitance. transfer register input
7
pF
Co(O)
Output capacitance. SOO and DO
7
pF,
Co(OSF)
Output capacitance. OSF
10
pF
NOTE 4: VCC equal to 5 V::t: 0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
PARAMETER
TEST
CONDITIONS
=Max
ta(C)
Access tirTje from CAS
td(RLCL)
ta(CA)
Access time from
column address
= Max
td(RLCL) = Max
td(RLCL) = Max
TMS4SC121-10
tCAC
20
25
30
ns
tM
40
50
60
ns
:E
o
u.
td(RLCL)
MAX
MAX
UNIT
tCPA
45
55
65
ns
80
100
120
ns
tOEA
20
25
30
ns
tSCA
25
30
35
ns
Access time from CAS high
Access time from RAS
ta(G)
Access time of
TAG low
ta(SO)
Access time of SO
from SC high
CL
ta(SE)
Access time of SO
from SE low
CL =30 pF
ta(OSF)
Access time of OSF
from SC low
CL =30 pF
tdis(CH)
Random output disable time
from CAS high (see Note 6)
CL
=30 pF
tOFF
0
20
0
20
tdis(G)
Random output disable time
from TRG high (see Note 6)
CL
=30 pF
tOEZ
0
20
0
tdis(SE)
Serial output disable time from
SE high (see Note 6)
CL
=30 pF
tSEZ
0
20
0
=30 pF
MIN
tRAC
ta(CP)
ta(R)
a from
o
TMS4SC121-S0
ALT.
SYMBOL MIN
MAX
MIN
TMS4SC121-12
Z
tSEA
20
20
25
ns
60
60
60
ns
O·
20
ns
20
0
20
ns
20
0
20
ns
NOTES: 5. Switching times for RAM port output are measured with a load equivalent to 1 TIL load and 100 pF. Data out reference level:
VOHNOL = 2.4 V/O.S V. Switching times for SAM port output are measured with a load equivalent to 1 TIL load and 30 pF. Serial
data out reference level: VOHNOL = 2 V/O.8 V.
6. tdis(CH). tdis(G). and tdis(SE) are specified when the output is no longer driven.
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S-103
~
a:
Z
W
U
Z
~
c
«
TMS48C121
131 072 BY 8-BIT
MULTIPaRT VIDEO RAM
SMVS121A-APRIL 1989- REVISED NOVEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature t
TMS48C121·80
ALT.
SYMBOL MIN
MAX
»
c
~
z
(")
m
-z
"
o
:D
s:
-o~
z
TMS48C121·10
MIN
MAX
TMS48C121·12
MIN
MAX
UNIT
tc(rd)
Read cycle time (see Note 7)
tRC
160
180
210
ns
tc(W)
Write cycle time
twc
160
180
210
ns
tc(rdW)
Read-modify-write cycle time
tRMW
215
240
280
ns
tc{P)
Page-mode read, write cycle time
50
60
70
,ns
tpc
tC(RDWP)
Page-mode read-modify-write cycle time
tpRMW
90
105
125
ns
tc(TRD)
Transfer read cycle time
tRC
160
180
210
ns
tc(TW)
Transfer write cycle time
twc
160
180
210
ns
tc(SC)
Serial clock cycle time
tscc
30
30
35
ns
tw(CH)
Pulse duration, CAS
tCPN
10
10
15
tw(CL)
Pulse duration, CAS low (see Note 8)
tCAS
20
tw(RH)
Pulse duration, RAS high
tRP
70
twIRL)
Pulse duration, RAS low (see Note 9)
tRAS
80
t~(WL)
Pulse duration, W low
twp
15
25
25
ns
tw(TRG)
Pulse duration, TRG low
20
25
30
ns
tw(SCH)
Pulse duration, SC high
tw(SCL)
Pulse duration, SC low
I
75000
25
75000
100
75000
30
75000
120
70
ns
75000
ns
ns
80
75000
ns
tsc
10
10
12
ns
tscp
10
10
12
ns
tsu(CA)
Column address setup time
tASC
0
0
0
ns
tsu(SFC)
DSF setup time before CAS low
tFSC
0
0
0
ns
tsu(RA)
Row address setup time
tASR
0
0
0
ns
tsu(WMR)
W setup time before RAS low
twSR
0
0
0
ns
tsu(DOR)
DO setup time before RAS low
tMS
0
0
0
ns
tsu(TRG)
TRG setup time before RAS low
trHS
0
0
0
ns
tsu(SE)
SE setup time before RAS low
tESR
0
0
0
ns
tsu(SFR)
DSF setup time before RAS low
tFSR
0
0
0
ns
tsu(DCL)
Data setup time before CAS low
tDSC
0
0
0
ns
tsu(DWL)
Data setup time before W low
tDSW
0
0
0
ns
tsu(rd)
Read command setup time
tRCS
0
0
0
ns
tsu(WCL)
Early write command setup time before CAS low
twcs
0
0
0
ns
tsu(WCH)
Write setup time before CAS high
tCWL
20
25
30
ns
tsu(WRH)
Write setup ~e before RAS high
with TRG =W =low
tRWL
20
25
30
ns
tsu(SDS)
SO setup time before SC high
tSDS
3
3
3
ns
thlcLCA)
Column address hold time after CAS low
tCAH
20
20
20
ns
th(SFC)
DSF hold time after CAS low
tCFH
20
20
20
ns
th(RA)
Row address hold time after RAS low
tRAH
15
15
15
ns
th[TRG)
TRG hold time after RAS low
trHH
15
15
15
ns
th(SE)
SE hold time after RAS low
with TRG =IN =low
tREH
15
15
15
ns
th(RWM)
Write mask, transfer enable hold time
after RAS low
tRWH
15
15
15
ns
Continued next page.
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 7. All cycle times assume tt = 5 ns.
8. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user's transition times, this may require
additional CAS low time [tw(CL)l.
9. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user's transition times, this may require
additional RAS low time [tw(RL)l.
.,.
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131 072 BY 8-BIT
MULTIPaRT VIDEO RAM
SMVS121A -APRIL 1989- REVISED NOVEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)t
ALT.
SYMBOL
th(RDQ)
DQ hold time after RAS low
(write mask operation)
th(SFR)
DSF hold time after RAS low
th(RLCA)
Column·address hold time after RAS low
(see Note 9)
TMS48C121·80
MIN
MAX
TMS48C121·10
MIN
MAX
TMS48C121·12
MIN
MAX
UNIT
tMH
15
15
15
ns
tRFH
15
15
15
ns
tAR
45
45
45
ns
tDH
20
25
25
ns
th(CLD)
Data hold time after CAS low
th(RLD)
Data hold time after RAS low (see Note 10)
th(WLD)
Data hold time after W low
th(CHrd)
Read hold time after CAS (see Note 11)
tRCH
0
th(RHrd)
Read hold time after RAS (see Note 11)
tRRH
,10
th(CLW)
Write hold time after CAS low
tWCH
15
th(RLW)
Write hold time after RAS low (see Note 10)
tWCR
th(WLG)
TRG hold time after W low (see Note 12)
tOEH
tDHR
45
50
50
ns
tDH
20
25
25
ns
0
0
ns
10
10
ns
25
30
ns
45
50
55
ns
20
25
30
ns
th(SDS)
SO hold time after SC high
tSDH
5
5
5
ns
th(SHSQ)
SQ hold time after SC high
tSOH
5
5
5
ns
ns
z
o
~
:as
td(RLCH)
Delay time, RAS low to CAS high
tCSH
80
100
120
td(CHRL)
Delay time, CAS high to RAS low
tCRP
0
0
0
ns
td(CLRH)
Delay time, CAS low to RAS high
tRSH
25
25
30
ns
td(CLWL)
Delay time, CAS low to W low
(see Notes 13 and 14)
tCWD
45
55
65
ns
td(RLCL)
Delay time, RAS low to CAS low
(see Notes 15 and 16)
tRCD
20
td(CARH)
Delay time, column address to RAS high
tRAL
40
50
60
ns
td(RLWL)
Delay time, RAS low to W low (see Note 13)
tRWD
110
130
155
ns
td(CAWL)
Delay time, column address to W low
(see Note 13)
tAWD
75
85
100
ns
(.)
td(RLCH)
Delay time, RAS low to CAS high (see Note 17)
tCHR
20
25
25
ns
Delay time, CAS low to RAS low (see Note 17)
tCSR
10
10
10
ns
Z
td(CLRL)
td(RHCL)
Delay time, RAS high to CAS low (see Note 17)
tRPC
5
5
5
ns
td(CLGH)
Delay time, CAS low to TRG high
tCTH
20
25
35
ns
td(GHD)
Delay time, TRG high before data applied at DQ
30
ns
td(RLTH)
_
_
Delay time, RAS low to TRG high
(see Notes 18 and 19)
I Early load
60
25
tOED
th(TRG)
IM'Id-rIne reaI-
tRTH
time load
65
25
30
th(TRG)
70
75
25
90
ns
th(TRG)
80
ns
Continued next page.
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 9. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user's transition times, this may require
additional RAS low time [tw(RL)l.
10. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
11. Either th(RHrd) or t(CHrd) must be satisfied for a read cycle.
12. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle.
13. Read-modify-write operation only.
14. TRG must disable the output buffers prior to applying data to the DQ pins.
15. Read cycles only.
16. The maximum value is specified only to guarantee RAS access time.
17. CAS-before-RAS refresh operation only.
18. TRG may be brought high "early" when real time memory to register data transfer is not required, provided that the th(TRG),
td(SCTR), and td(RLSH) specifications are met.
19. Memory to register (read) transfer cycles only.
TEXAS •
INSIRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
8-105
a::
o
LL
Z
W
~
c
c
~
z
n
m
-z
"o
:D
s:
~
o
z
TMS48C121-80
MIN
MAX
TMS48C121-10
MIN
MAX
TMS48C121-12
MIN
MAX
UNIT
td(RLSH)
Delay time, RAS low to first SC high after
TRG high (see Note 19)
tRSD
85
95
105
ns
td(CLSH)
Delay time, CAS low to first SC high after
TRG high (see Note 19)
tCSD
35
40
45
ns
td(SCTR)
Delay time, SC high to TRG high
(see Notes 19 and 20)
trSL
10
15
15
ns
td(THRH)
Delay time, TRG high to RAS high (see Note 19)
tTRD
-10
-10
-10
ns
td(SCRL)
Delay time, SC high to RAS low with
TRG = Vi = low (see Notes 21 and 22)
10
10
10
ns
td(SCSE)
Delay time, SC high to SE high
in serial input mode
15
20
20
ns
tSRS
td(RHSC)
Delay time, RAS high to SC high (see Note 22)
tSRD
20
30
30
ns
td(THRL)
Delay time, TRG high to RAS low (see Note 23)
tTRP
Delay time, TRG high to SC high (see Note 23)
trSD
tw(RH)
25
tw(RH)
40
ns
td(rHSC)
tw(RH)
20
td(SESC)
Delay time, SE low to SC high (see Note 24)
tsws
10
15
15
ns
td(RHMS)
Delay time, RAS high to last (most significant)
rising edge of SC before boundary switch during
split read transfer cycles
20
25
30
ns
td(TPRL)
Delay time, first (TAP) rising edge of SC after
boundary switch to RAS low during split read
transfer cycles
20
25
25
ns
trf(MA)
Refresh time interval, memory
tt
Transition time
8
tREF
tT
3
50
8
3
50
3
ns
8
ms
50
ns
t timing measurements are referenced to VIL max and VIH min.
NOTES: 19. Memory to register (read) transfer cycles only.
20. In a transfer read cycle, the state of SC when TRG rises is a Don't Care condition. However, to guarantee proper sequencing of the
internal clock circuitry, there can be no positive transitions of SC for at least 10 ns prior to when TRG goes high.
21. In a transfer write cycle, the state of SC when RAS falls is a Don't Care condition. However, to guarantee proper sequencing of the
internal clock circuitry, there can be no positive transitions of SC for at least 10 ns prior to when RAS goes low.
22. Register to memo'ry (write) transfer cycles only.
23. Memory to register (read) and register to memory (write) transfer cycles only.
24. Serial data-in cycles only.
at_
TEXAS ~
, INSTRUMENTS
8-106
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS48C121
131 072 BY 8-BIT
MULTIPaRT VIDEO RAM
SMVS121A -APRIL 1989- REVISED NOVEMBER 1990
read cycle timing
1
1
"'1
AO-AS
I
I
~
tsu(SFR) ~ ~
I~
1.... 1
~ tsu(SFC)
DSF~11 ~II
~
TRG
1Jll?
i
1
I
:
I
~
~
1
1
~I
z
o
1
~\
1 tsu(rd)
1
:
~II~II
--.! I~ tsu(TRG)
I
~~I
1tJ(SFC
1+ th(SF,R) 1 I·
\l
I 1
~
~
1
,
'-I
,.....
'h(eH,d)
~
1
~'w(TRG)
I..
~
a:
~
h(RHrd)
o
u.
--.rI...
I'"
1"1
Z
w
o
z
~
c
«
TEXAS ~
INSlRuMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-107
TMS48C121
131 072 BY 8-BIT
MULTIPaRT VIDEO RAM
SMVS121A -
APRIL 1989 -
REVISED NOVEMBER 1990
early write cycle timing
r
N
____
RAS
t
L.f
(""'III
I 14
....
tt
"'1
tc(W)
w(RL)
hi
td(RLCH)
JIll'"
-.!I 11"14
l<1li
....1 - - - - - - td(CLRH)
I j+- td(RLCL) ~~
tw(CL)
I I
I
I
I I
I~I 1
:1
1
1
~ tsu(CA\
1 I....
...1
--.1
I
I ~I
~ t
(""'III
I
t
I
.1 I :
I
1
I
--"o.J
~: l++- td(CHRL) --+I
~
th(RA) :
th(RLCA)
0~tW(RH)~~
----'--'JIII"'~
N'~
-f.i~
~
.,
JIll'"
1
I11III
I
"X
i "--
tw(CH)
~:
I
1
~~~~
AO-A8~
:+mn ~,-,______
»
c
I
--'1
~ tsu(SFR)
1 1
I 1 1
1
1 1 1II1II
I I
~!
~
.1 th(SFC)
1
tsu(SFG)
1
1
1
1
1
1
I
1
DSF~)::2 ~'-
~
z
(1
-.1 ~ tsu(TRG)
m
I I
I~
-z
"o
'!)QQ()f
~
~
tsu(TRG)
'
th(SFC)
"
~ td(GHO)
,
'"
~
~~MR)
VI
13
I
I
1
~I
i4IIIIT
I
"
14-
HII1
~,II tw(Wl,.) -I>!
~
~:
~,
tsu(WCH)
~
,
-c>l
I ,
~
~
,
a:
i4- tsu(WAH) ~
',~
~
~
,
~~~I--~I--~!--~~~~~~~~~~~~--~~~~~~~~
~ ~ tsu(DQA) tSU(DCL)t~~• .tSU(~114~J-t------I.~II
~ th(ADQ) ~
:
,0lIl
I
I I~
I th(ALD)
DQ=X~_~
---1~~1
--------a!.:
th(WLD) t
th(CLD)t
W
t Referenced to CAS or W, whichever occurs last.
NOTES: 25. See "Write Cycle State Table" for the logic state of "1 ", "2", "3", "4", and "5".
28. A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing
specifications. TRG must remain high throughout the entire page-mode operation if the late write features is used, to guarantee
page-mode cycle time. ~ early write cycle timing is used, the state of TRG is a Don't Care after the minimum period th(TRG)
from the falling edge of RAS.
TEXAS ~
INSfRUMENTS
•
HOUSTON. TEXAS 77001
Z
(J
~~----'~
POST OFFICE BOX 1443
o
LL
8-113
Z
~
c
«
TMS48C121
131 072 BY 8-BIT
MULTIPaRT VIDEO RAM
SMVS121A-APRIL 1989 - REVISED NOVEMBER 1990
enhanced page-mode read-modify-write cycle timing
I~
RAS
tw(RL) ------------~.I
~I ________________________________________________________ J~I·II
I~~
~/i
I I
I I~
I I
I
td(RLCH)
I"
~td(RLCL)~~
.I I
I'
I:
CAS
~
7\ \l
~
~ tsu(CA)1
;;
:
~ 1 ~colum; -~
~
.... 1
I
I
I
m
-z
"T1
o
Vi
:0
3:
-o~
z
:1:
~
~.~
t I"
!
~ Sl,lrtJ MR ),
.1
I
I
I I I~
1
I I~ 1
~th(RDO)
i\~
II
I
I
:
:
:
.1
.1
~
I~
I
I
1
t---·\----I,~
t~
!"III
~__,.-2--~~
.tsu(rd)
tsu(\AlCH)
I
1.td(CLWL) ~II
I
I
'"
I"
.1 I
td(CAWL)
!d(RLWL)
.1
i~
I
~
I
~
tsu(SFC)
I
I
i',.if
:colum~
I..
~ th(SFC) I
~I
i ~*-ta(c)
~
I..
~
r!i tsu(DOR)
~
~
:~: tsu(SFC)
~ ~ th(~WM)
iJY}
I
I
.. 2
:
I... 1
I I
I I
tw(RH)
td(CLRH) ~
td(CHRL)
I
vi
I
:
1
~
z(")
~
~~r-th(iA>..lR~CA) ~:l ~th(CLCA)
th(SFR)
~ tsu(SFR)
»
c
~~
I
I I ~
.1~tW'(CH)
I..
.1
tC(RDWP) I
~~W
I I
~
I
I
tsuf\AlRH)
'"
1
.1 twrtJL)
II"
I
I..
I
I
NJY,...----~\l
1
ta(CA)t
1
I
~thf\AlLD)
I" _... 1
'"
~ I~ I
1
.:
I
I
.1
~
~--...~~~~
.,
~----~
DO
I
1
I
~
I ~ ta(G) -.l
I
~ta(R)~
TRG
\l
I
I..
I
1
.1 td(GHD)
~
1
1
~ tdls(G)
\J
t Output may go from the high-impedance state to an invalid data state prior to the specified access time.
NOTES: 25. See "Write Cycle State Table" for the logic state of "1 ", "2", "3", "4", and "5".
29. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not
violated.
TEXAS
lJ1
INSlRUMENTS
8-114
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS48C121
131 072 BY 8-BIT
MULTIPaRT VIDEO RAM
SMVS121A -APRIL 1989 -
REVISED NOVEMBER 1990
RAS-only refresh timing
~
______________~I
~
N
RAS
tw(RL)
~~
1:i1
I
tt
~
r4-
iL
tw(RH)
~
z
o
:
- 1 ' 1 1 tsu(TRG)
I,
,--
'~th(TRG)
~,
I
~
a:
0:
o
u..
Vi
Z
W
DQ
U
NOTE 30:
In persistent write-per-bit function,
2:
iN must be high during the refresh cycle,
~
C
«
TEXAS •
INSTRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-115
TMS48C121
131 072 BY 8-BIT
MULTIPaRT VIDEO RAM
SMVS121 A ~ APRIL 1989 - REVISED NOVEMBER 1990
CAS-before-RAS refresh
tc(rd) ---------.;~,
,.
~ tw(RH) ~
;1
_ _--..J
,.
td(CLRL)
, CAS
~:
td(RHCL)
,04
-----------,~
tw(RL) ----.l~,
,.
N
I
Y
I
~,
~ td(RLCH) ~
yl
'\
_
~i'h~~
TRG
Vi
»c
~
z
(')
DSF
m
-z
"..'________
DQ - - - - - - - - - - - - - - H I - Z - - - - - - - - - - - - - - - - NOTE 30: In persistent write-per-bit function,
W must be high during the refresh cycle,
."
o
:IJ
:s:
~
o
z
TEXAS
-iJ1
INSTRUMENTS
8-116
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS48C121
131 072 BY 8-BIT
MULTIPORT VIDEO RAM
SMVS121A -APRIL 1989- REVISED NOVEMBER 1990
hidden refresh cycle timing
~ Memory Cycle ~~ Refresh Cycle -f>!
_
I
tw(RH)
~ l'~
Y!I
!\l
I
RAS
I I
I I
I I
I:
tw(RH)
f.I f4:
\l
~ Refresh Cycle -i>j
~I ~\
Y
I
\
I
I
!.~
!~
"\
I I
I
~
I I
I I -+l ~
th(RA)
~
+III
~: ~l tW(RL~ 1'1~
/
r--1~1
~,----~
I
td(RLCH)
I
I
11ts~tCA)
:
1<1-
~~
tw(CL)
I
-t>I
Ii
th(CLCA)
II
I
I
I
I
:
~s~:~
~
AO-A8~R~~H~:~
I
I
tsu(rd
W """"'''1'
:
DO
J~
iCf- th(RHrd)
I
I
I
I
I
I ~
talC)
.
.
tdis(CH)
Valid Data
-I>l
l<'-
2-
;,:
tSU(TRG»)
I
I
-+ll
z
I
C
:I
W
I~
~
~ ta(R) -I>j
~ ~
TRG
I
~ ta(G)
t4t th(TRG)
tdis(G)
~
1/)
I
.... 1
I
J4-
o
~
:E
0:
o
u.
z
w
I
U
Z
~
c
DSF
11
~
tc(TRO)
, ra,
-
I
I ,I
"~~
'
,
,
,
,,
~ +mn~*R-r~K~
...,
"
,
-!!~~~
z
o
~
?-
0:
o
LL.
Z
w
()
Z
~
c
SC
I
SE
~ ta(SE)
Vi
I
~
~ ta(sa)~
>C
~~i_____________________________________________________________
NOTE 38: While reading data through the serial data register, the state of TRG is a Don't Care as long as TRG is held high when RAS goes low.
This is to avoid the initiation of a register to memory to register data transfer operation.
The Serial Data-out cycle is used to read data out of the data registers. Before data can be read via sa, the device
must be put into the read mode by performing a transfer read cycle. Any transfer write cycles occurring between
the transfer read cycle and the subsequent shifting out of data will take the device out of the read mode and put
it in the write mode, thus not allowing the reading of data.
TEXAS
lJ1
INSTRUMENTS
8·124
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS4C1050, TMS4C1060
. 262 264-WORD BY 4-BIT
FIELD MEMORIES
SMGS050C CI
262264 x 4 Organization
•
Single 5-V Power Supply (± 10% Tolerance)
CI
•
•
REVISED NOVEMBER 1990
N Package
(Top View)
VCC
Fast FIFO (First-In First-Out) Operation
- Fu" Word Continuous Read/Write
- Asynchronous Read/Write
RSTW
SWCK
DO
01
Quasi-Static (Refresh Free)
R
RSTR
SRCK
00
01
02
High-Speed Read/Write Operation
ACCESS
TIME
(MAX)
TMS4C1050/4C1060-30 25 ns
TMS4C1050/4C1060-40 30 ns
TMS4C1050/4C1060-60 50 ns
CI
JANUARY 1988 -
CYCLE
TIME
READ
(MIN)
30 ns
40 ns
60 ns
CYCLE
TIME
WRITE
(MIN)
30 ns
40 ns
60 ns
VSS
SRCK
R
W
SWCK
NC
NC
01
03
03
01
Low Power Dissipation (Average
100 = 50 rnA at Minimum Cycle)
o
Plastic 16-Pin 300-mil-Wide DIP, 20-Pin
400-mil ZIP, or 20/26-Lead Surface-Mount
(SOJ) Package
o
Texas Instruments EPIC™ (Enhanced
Process Implanted CMOS) Technology
OJ Package
(Top View)
SO Package
(Top View)
Operating Free-Air Temperature
... O°C to 70°C
RSTR
VCC
RSTW
DO
NC
NC
02
VSS
02
00
W
RSTW
SWCK
DO
NC
NC
01
02
03
VSS
VCC
R
RSTR
SRCK
NC
NC
ao
01
02
03
description
The TMS4C1050 and TMS4C1060 are Field
Memories (FMEM) which read and write data
exclusively through serial ports, 4 bits wide.
Maximum storage capacity is 262 264 words by
four bits each. Addressing is controlled by write
address and read address pointers, which must be
reset to zero before memory access begins.
PIN
00-03
00-03
R
RSTR
RSTW
SRCK
SWCK
W
NC
VCC
VSS
Read and write access may occur asynchronously, if desired by the user. When read access is
delayed relative to write access, the TMS4C1 050
and the TMS4C1060 function like a First-In
First-Out (FIFO) register. The amount of delay
determines the "length" of the FIFO register.
NOMENCLATURE
Data-In
Data-Out
Read Enable
Reset Read
Reset Write
Serial Read Clock
Serial Write Clock
Write Enable
No Internal Connection
5-V Power Supply
Ground
Unlike in a conventional FIFO register, however, data may be read as many times as desired, after it is written
into the storage array. Even if the content of the read address pOinter is lost because the requirements for its
integrity have been violated (i.e., at least one clock period per 1 ms while R is active), the data stored is not lost
and can be recovered by resetting the read address pointer to zero again.
EPIC is a trademark of Texas Instruments Incorporated.
PRODucnON DATA documents contain information
current IS of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1990, Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-125
TMS4C1050, TMS4C1 060
262 264·WORD BY 4·BIT
FIELD MEMORIES
SMGS050C - JANUARY 1988 -
REVISED NOVEMBER 1990
description (continued)
Minimum delay between writing into the device and reading out data is 600 SWCK cycles. Maximum delay is
one full field (262 264 write cycles) plus another 119 SWCK cycles.
T
The TMS4C1050 and TMS4C1060 employ state-of-the-art EPIC " (Enhanced Process Implanted CMOS)
technology for high performance, reliability, and power at a low cost.
Dynamic data storage cells are employed as the main data memory to achieve high density. Self-refresh and
arbitration logic is implemented in the TMS4C1 050 and TMS4C1 060 supplying a refresh-free system. This logic
prevents any conflict between data-saving/data-Ioading/memory-refresh requests.
The write address counting scheme of the TMS4C1 060 has been modified relative to its read address counting
scheme, to allow easy cascading of several memory devices. In this respect the TMS4C1050 and the
TMS4C1 060 differ. Another difference between both memories is the timing of output enabling and disabling.
In the TMS4C1 060, this timing is clock edge controlled, while in the TMS4C1 050 enabling and disabling is level
controlled.
The TMS4C1 050 and TMS4C1 060 are offered in a 16-pin dual-in-line plastic package (N suffix) designed for
insertion in mounting hole rows on 7,62-mm (300-mil) centers. These devices are also offered in a 20-pin 400-Mil
ZIP package (SO suffix) and a 300-Mil 20/26 J-Iead plastic surface mount SOJ package (OJ suffix). These
devices are guaranteed for operation from O°C to 70°C (L suffix).
operation
write operation
The write operation is controlled by two clocks, SWCK and RSTW, and W. It is accomplished by cycling SWCK
and holding W high after write address pOinter reset operation (RSTW). Each write operation, which begins with
RSTW, must contain at least 120 active write cycles, i.e. SWCK cycles while W is high. To transfer the last data
.written into the device, which at that time is still stored in the write line buffer, to the memory array, an RSTW
operation is required after the last SWCK cycle.
reset write (RSTW)
The first positive transition of SWCK after RSTW going high, resets the write address pOinters to zero. RSTW
setup and hold times are referenced to the rising edge of SWCK. The state of W may be high or low during any
reset operation. Before RSTW may be brought high again for a futher reset operation, it must have been low
for at least two SWCK cycles.
data inputs (00-03) and write clock (SWCK)
The SWCK input latches the data inputs on chip when W is high and also increments the internal write address
pointer. Data-in setup and hold times [tsu(D), th(D)l are referenced to the rising edge of SWCK.
write enable (W)
W is used as a data-in enable/disable. A logic high on the W input enables the input, and a logic low disables
the input and holds the internal write address pOinter. W disable time (low) can be expanded to 1 ms. In case
W is held low over 1 ms, the content of the write address pointer may get lost. In this case an RSTW operation
is required to re-initialize this pOinter.
Note that W setup and hold times are referenced to the riSing edge of SWCK.
read operation
The read operation is controlled by two clocks, SRCK and RSTR, and Rlt is accomplished by cycling SRCK
and holding R high after a read address pOinter reset operation (RSTR). Each read operation, which begins with
RSTR, must contain at least 120 active read cycles, i.e. SRCK cycles while R is high.
TEXAS
lJ1
INSlRUMENTS
8-126
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS4C1050, TMS4C1060
262 244-WORD BY 4-BIT
FIELD MEMORIES
SMGS050C - JANUARY 1988 -
REVISED NOVEMBER 1990
reset read (RSTR)
The first positive transition of SRCK after RSTR has gone high resets the read address pointers to zero. RSTR
setup and hold times are referenced to the rising edge of SRCK. The state of R may be high or low during any
reset operation. Before RSTR may be brought high again for a further reset operation, it must have been low
for at least two SRCK cycles.
data out (QO-Q3) and read clock (SRCK)
Data is shifted out of the data registers on the riSing edge of SRCK when R is high during a read operation. The
SRCK input increments the internal read address pOinter when R is high.
The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same
polarity as data in. The output becomes valid after the access time interval tAC that begins with the positive
transition of SRCK.
Output valid time [tv(OUT)l is referenced to the rising edge of SRCK in the next cycle.
output enabling and disabling (TMS4C1050 only)
When R changes state, the outputs will become enabled or disabled. However, SRCK must go low also, before
a change of the state of R can be noticed at the outputs. The state of SRCK influences the outputs only during
the first SRCK cycle following each change of state of R.
In order for the outputs to become enabled, R must go high and SRCK must go low. Enable time is determined
by whichever transition (R going high or SRCK going low) occurs last. In order for the outputs to become
disabled, R must go low and SRCK must go low. Disable time is determined by whichever transition (R going
low or SRCK going low) occurs last. See the timing diagrams under read cycle timing (output enable and disable)
for an illustration of enable and disable timing.
output enabling and disabling (TMS4C1060 only)
The state of R is latched in by the read clock. SRCK determines whether the outputs will be enabled or disabled.
If R is high at the rising edge of SRCK, the outputs will be enabled. If R is low at the rising edge of SRCK, the
outputs will be disabled. R setup and hold times are referenced to the rising edge of SRCK.
read enable (R)
R performs a double function. First, R gates the SRCK clock, for incrementing the read pointer. When R is high
before the rising edge of SRCK, the read pOinter is incremented. When R is low, the read pointer is not
incremented. R setup times (tRHSRH and tRLSRH) and R hold times [th(RE)l are referenced to the rising edge
of the SRCK clock.
The second function of R is to enable and disable the outputs. See the appropriate section on "output enabling
and disabling".
After a read operation has started, R may be brought low for a maximum of 1 ms, before the contents of the read
address pOinter will be lost due to the dynamic nature of the read address pOinter register. In this case,
information stored in the memory will not be lost, but it will be necessary to restart the read cycle at the beginning
address (zero) by performing an RSTR operation.
power-up and initialization
On powering up, the device is designed to begin proper operation after at least 100 !ls after V CC has stabilized
to a value within the range of recommended operating conditions. After this 100 !ls stabilization interval, the
following initialization sequence must be performed.
Because the read and write address pointers are not valid after power-up, a minimum of 130 dummy read
operations (SRCK cycles) must be performed, followed by an RSTR operation, to properly initialize the read
address pOinter. A minimum of 130 dummy write operations (SWCK cycles) must be performed, followed by an
RSTW operation, to properly initialize the write address pOinter. Dummy read cycles/RSTR and dummy write
cycles/RSTW may occur simultaneously.
TEXAS ~
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TMS4C1050, TMS4C1060
262 264·WORD BY 4·BIT
FIELD MEMORIES
SMGS050C -
JANUARY 1988 -
REVISED NOVEMBER 1990
If these dummy read and write operations start while vee and/or the substrate voltage have not stabilized, it
is required to perform an RSTR operation plus a minimum of 130 SRCK cycles plus another RSTR operation,
and an RSTW operation plus a minimum of 130 SRCK cycles plus another RSTW operation to properly initialize
read and write address pointers.
old/new data access
There must be minimum delay of 600 SWCK cycles between writing into memory and reading out from memory.
If reading from the first field starts with an RSTR operation, before the start of writing the second field, (before
the next RSTW operation), then the data just written in will be read out.
The start of reading out the first field of data may be delayed past the beginning of writing in the second field
of data for as many as 119 SWCK cycles. If the RSTR operation for the first field read-out occurs less than 120
SWCK cycles after the RSTW operation for the second field write-in, then the internal buffering of the device
assures that the first field will still be read out. The first field of data that is read out while the second field of data
is written is called old data.
In order to read out new data, i.e., the second field written in, the delay between an RSTW operation and an
RSTR operation must be at least 600 SRCK cycles. If the delay between RSTW and RSTR operations is more
than 120 but less than 600 cycles, then the data read out will be undetermined. It may be old data or new data
or a combination of old and new data. Such a timing should be avoided. '
cascade operation (TMS4C1060 only)
The TMS4C1 060 has been designed to allow easy cascading of multiple memory devices, in order to obtain a
higher storage depth 'or a longer delay than can be achieved with only one memory device. See the
interconnection diagram on page 8-138 for details.
As'illustrated in the timing diagram on page 8-138, the positive SRCK/SWCK edge at the beginning of a clock
cycle serves to initiate read-out, whereas writing in is initiated by the positive SWCK/SRCK edge at the end of
a cycle. This differs from the functionality of the TMS4C1050, in which both the read-out and the write-in are
initiated at the beginning of a clock cycle.
internal operation
writing into memory
The first 120 words of data following the initial RSTW operation after power-up are written into a cache buffer
(A) initially, and will never be stored elsewhere, to allow read-out of data later without the delay involved in
retrieving it from the main memory array.
Starting from address 121, data is written into the write line buffer, top block, until this block (256 words long)
is full. Further writing then occurs to the bottom block of the write line buffer, while the top block is transferred
to the main memory array. By the time the bottom block is full, the top block has been transferred to memory
and can be used again to receive new incoming data. The channelling of input data into the top or bottom block
is controlled internally by the device and is transparent to the user.
After the 120-word long cache buffer has been filled with incoming data, the input line selector switches the
connection of the input port over to the B line buffer to assure that the next field of data, which will arrive later
after a subsequent RSTW operation, does not over write the content of the cache buffer. Each subsequent filling
of the cache buffer toggles the connection of the input port between the A and the B line buffers with the 121 st
SWCK pulse. The A and B line buffers, as well as the input line selector, are static registers.
The connection of the output port will also be toggled between A and B line buffers by the 121 st SWCK pulse,
providing no read operation from a cache buffer is in progress at this time. The output port will always be
connected to the line buffers opposite to the one connected to the input port. In case a read operation from a
cache buffer is in progress when the 121 st SWCK occurs, the toggling of the output port connection will be
delayed until the cache buffer has been read out completely.
TEXAS
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INSTRUMENTS
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TMS4C1050, TMS4C1 060
262 244-WORD BY 4-BIT
FIELD MEMORIES
SMGS050C -
JANUARY 1988 -
REVISED NOVEMBER 1990
The requirement stated on page 8-126 that each write operation must contain at least 120 active SWCK cycles,
exists in order to assure that the toggling of the input and output ports between the A line buffer and the B line
buffer functions without errors as described above.
The serial write pointer stores the (column) address of the last input data word received, while the write counter
stores the row address. The serial write pointer is a dynamic register and must be clocked at least once per
1 ms. Holding W low will inhibit clocking; thus W must not be held low for more than 1 ms, and the SWCK must
not be inactive for more than 1 ms, to assure integrity of the serial write painter. Only when the serial write painter
stores the address zero, i.e. the initial address or head address, may this value of 1 ms be exceeded.
After the last word of a full write cycle has been latched in (with a positive transition of the SWCK clock), the write
line buffer most likely will be partially filled without having been transferred to the main memory array. To assure
that the information contained in the write line buffer is stored also and cannot be lost, it is required that an RSTW
operation be performed within 1 ms after input when write clocking has stopped.
In addition to transferring the partially filled write line buffer into the main memory array, this RSTW operation
will also reset the write addresses (serial write pointer) to zero, and due to the internal construction of the dynamiC
serial write pointer register, this internal address of zero remains stored indefinitely. Regardless of how much
later a new write cycle starts, it is not necessary to perform another RSTW operation again at that time.
reading from memory
ft..fter an RSTR operation, data from the 'main memory array (starting at address 121) will be transferred to a read
line buffer. Because this transfer requires some time, the first 120 words will be read out of the A or B line buffers,
where they had been previously stored (see writing into memory above).
If the first RSTR operation occurs after the first RSTW operation but before the second RSTW operation, read
access will be to the same buffer that data had been written into during the first write cycle. Thus old data will
be read out.
If the first RSTR operation occurs after the second RSTW operation, i.e. after the writing in of new data has
already started, then the delay between the second RSTW and the first RSTR operation determines whether
old data or new data will be read out.
If this delay is less than 120 SWCK cycles, data will be read out from the line buffer that was written into during
the previous write cycle; i.e., old data will be read out. A delay of less than 120 SWCK cycles also assures that
all following data bits are old data, because replacement of old data by new data in the main memory array will
occur later than the respective read access to each address in the array.
If this delay is more than 600 SWCK cycles, data will be read out from the line buffer that it was written into during
the current write cycle; i.e., new data will be read out. A delay of more than 600 SWCK cycles also assures that
all following data bits are new data, because replacement of old data by new data in the main memory array will
occur before the respective read access to each address in the array.
If this delay is more than 120 but less than 600 SWCK cycles, data read out can be either old or new or a mixture
of old and new data, because it cannot be predicted accurately whether a word accessed for reading has already
been replaced by new data or not. Such a situation should be avoided.
After the first 120 words bits are read out of the A or B line buffer, read transfer from the main memory array
to the read line buffer is finished, and subsequent reading will occur from this buffer. Similar to the write operation,
while one half of this buffer is being read out, the other half will be filled again by a new read transfer from the
main memory array.
The serial read pointer stores the (column) address of the last data word read out, while the read counter stores
the row address. The serial read pointer is a dynamiC register and must be clocked at least once per 1 ms. Holding
R low will inhibit clocking. R must not be held low for more than 1 ms, and the SRCK must not be inactive for
more than 1 ms to assure integrity of the serial read pointer. Only when the serial read pointer stores the address
zero; i.e., the initial address or head address, may this value be exceeded.
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443
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8-129
TMS4C1050, TMS4C1 060
262 264-WORD BY 4-BIT
FIELD MEMORIES
SMGS050C -
JANUARY 1988 -
REVISED NOVEMBER 1990
self-refresh and arbitration logic
The self-refresh and arbitration logic will keep the main memory information refreshed automatically without
requiring any user action, control the address pointers for both read and write, and control the flow of information
both into and out of the main memory.
.
functional block diagram
W
R~---,
DATA
IN
(x4)
DATA
OUT
(x4)
~
Q).~
(1)~
Array
(256 K)
c:Q)e.
enE
Array
(256 K)
~
Q)
«
c
'0
a.
.!!l
~
RSTR
:§
CIl.~
cn~
Array
(256'K)
c:Q)e.
enE
RSTW
iii
en
~
Array
(256 K)
«
SWCK
SRCK
Write Counter
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (TMS4C1050) (see Note 1) .... ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 1 V to 7 V
Voltage range on Vee ................................................................. a V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ...................................................... - 65°C to 150°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE1: All voltage values in this data sheet are with respect to VSS.
TEXAS •
INSTRUMENlS
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POST OFFICE BOX 1443
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TMS4C1050, TMS4C1060
262 244-WORD BY 4-BIT
FIELD MEMORIES
SMGS050C - JANUARY 1988 -
REVISED NOVEMBER 1990
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
VIH
High-level input voltage
2.4
VIL
Low-level input voltage (see Note 2)
-1
TA
Operating free-air temperature
PARAMETER
VCC+ 1
0.8
a
70
UNIT
V
V
V
°c
NOTE 2: VIL = - 1.5 V undershoot is allowed when device is operated in the range of recommended supply voltage.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TMS4C10S0-30
TMS4C1060-30
TEST CONDITIONS
MIN
MAX
TMS4C10S0-40
TMS4C1060-40
MIN
TMS4C10S0-60
TMS4C1060-60
MAX
MIN
2.4
UNIT
MAX
2.4
V
VOH
High-level output voltage
10H =-S mA
VOL
Low-level output voltage
10L = 4.2 mA
0.4
0.4
0.4
V
II
Input current (leakage)
VI = 0 to 6.S V, VCC = 5.5 V,
All other pins = a V to VCC
±10
±10
±10
t-t A
10
Output current (leakage)
Vo = a to Vcc, Vcc = S.5 V, R low
±10
±10
±10
t-tA
Average operating current
Minimum write/read cycle,
output open
50
4S
3S
mA
Standby current
After 1 RSTW/RSTR cycle,
Wand R low
10
10
10
mA
1001
1002
2.4
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f =1 MHzt
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Ci
Input capacitance
VI = 0, f = 1 MHz
7
pF
Co
Output capacitance
VI = 0, f = 1 MHz
10
pF
t VCC equal to 5 V ± O.S V and the bias on pins under test is a v.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
TEST
CONDITIONS
PARAMETER
TMS4C10S0-30
TMS4C1060-30
TMS4C10S0-40
TMS4C1060-40
TMS4C10S0-60
TMS4C1060-60
MIN
MIN
MIN
MAX
25
MAX
30
UNIT
MAX
tAC
Access time from SRCK high
see Note 3
tv(OUn
Output valid time after SRCK high
see Note 3
6
tdis(CKL)
Output disable time after SRCK low
see Note 4
4
15
4
15
4
15
ns
tcn(CKL)
Output enable time after SRCK low
see Note 3
0
15
15
ns
Output enable time after R high
see Note 3
0
15
15
a
a
15
tcn(RH)
a
a
15
ns
tdislRU
Output disable time after R low
see Note 4
4
15
4
1S
4
15
ns
6
50
ns
ns
6
NOTES: 3. The load connected to each output is a SO-pF capacitor to ground, in parallel with a 218-Q resistor to 1.31 V as illustrated by
Figure 1.
4. Oisable times are specified from the initiating timing edge until the output is no longer driven by the memory. If disable times are to
be measured by observing output voltage waveforms, sufficiently low load resistors and capacitors have to be used, and the RC time
constants of the load have to be taken into account.
TExAs
.JJ1
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8-131
TMS4C1050, TMS4C1060
262 264-WORD BY 4-81T
FIELD MEMORIES
SMGSOSOC - JANUARY 1988 - REVISED NOVEMBER 1990
PARAMETER MEASUREMENT INFORMATION
RL=218Q
00-03 (Outputs) ~ 1.31 V
CL=50pF
±
Figure 1. Load Circuit for Timing Parameters
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Notes 5 and 6)
TMS4C1050-30
TMS4C1060-30
TMS4C1050-40
TMS4C1060-40
TMS4C1050-60
TMS4C1060-60
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
tc(W)
Write cycle time (see Notes 5 and 6)
30
1000 000
40
1000 000
60
1 000 000
ns
tc(R)
Read cycle time (see Notes 5 and 6)
30
1 000 000
40
1 000 000
60
1000 000
ns
tw(R)
Pulse duration, R low (see Notes 5 and 6)
10
1000 000
10
1000 000
10
1 000 000
ns
tw(W)
Pulse duration, W low (see Notes 7 and 8)
10
1000 000
10
1000 000
10
1 000 000
ns
tw(RH)
Pulse duration, SRCK high
12
17
20
ns
tw(RL)
Pulse duration, SRCK low
12
17
20
ns
tw(WH)
Pulse duration, SWCK high
12
17
20
ns
tw(WL)
Pulse duration, SWCK low
12
17
20
ns
tsu(D)
Data setup time before SWCK high
5
5
5
ns
tsu(RH)
R-high setup time before SRCK high
0
ns
tsu(RL)
R-Iow setup time before SRCK high
a
a
a
a
a
a
a
tsu(WH)
W-high setup time before SWCK high
tsu(WL)
W-Iow setup time before SWCK high
a
a
a
a
tsu(RSTR)
RSTR setup time before SRCK high
3
3
3
tsu(RSTW)
RSTW setup time before SWCK high
3
3
3
ns
th(D)
Data hold time after SWCK high
6
6
6
ns
th(R)
R-hold time after SRCK high
6
6
6
ns
th(W)
W-hold time after SWCK high
6
6
6
ns
ns
th(RSTR)
RSTR hold time after SRCK high
6
6
6
th(RSTW)
RSTW hold time after SWCK high
6
6
6
tT
Transition time
3
30
3
30
3
ns
ns
ns
ns
ns
30
ns
NOTES: 5. No restrictions apply to the maximum value, if the read and write address pointers are addressing the first address.
6. If the read and write address pointers are not addressing the first address, tc(W), tc(R). tw(WH). tw(WL) , tw(WE). tw(RH). tw(RL). and
tw(R) must be 1 ms or less. After improper operation (over 1 ms), an RSTW or RSTR cycle is required to initialize the read or write
address pointers.
7. Timing measurements are referenced to VIH (MIN) = 2.4 Vand VIL (MAX) = 0.8 V.IT is measured between VIH (MIN) and VIL (MAX).
8. All cycle times assume tT = 3 ns.
TEXAS
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INSlRUMENTS
8-132
POST OFFICE BOX 1443
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1MS4C1050
262 244·WORD BY 4·B11
FIELD MEMORIES
SMGS050C-JANUARY 1988 - REVISED NOVEMBER 1990
write cycle timing (reset write)
~N~
I+--
N-1 ~
!.tclW\
1\ .. ,
~
rl
I
I
SWCK
~1~
~ 0
I
~ tw(WL)
I
I I
I
I
I
I I
I
:
I
: I
I
~ I+- tsu(D)
I
I
I
tS~(RSTW)"1
i ~ tWrM~:
RSTW
. I
-.!
II
I
I
I
I
I
I.--
th(RSTW)
~
I
I
II
I
I
----.I
~
:
I ~
I
\ . . ___ :::
:+- th(D)
DATA IN
W
----------------------------------------~---------
VIH
write cycle timing (write enable)
SWCK
W
DATA IN
VIH
RSTW
----------------------~)~)---------------------------
VIL
TEXAS •
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8-133
TMS4C1060
262 264-WORD BY 4-81T
FIELD MEMORIES
SMGS050C -
JANUARY .1988 -
REVISED NOVEMBER 1990
write cycle timing (reset write)
~N~
104-- 0 - . I
I
:.-
~ tc(W)
I I
SWCK
I
I
I
I
I
RSTW
14-1~
I+-- N-1 --+I
I
4
I
I
I
I
I
I
I
I
I
I
I
I ~
I
I
-+I 14- tsu(D)
I
I
I
I
tw(WL)
:
I
I
1
1
1 4 - - - th(RSTW)
1
-+I
tsu(RSTW)
I
I
~
I
--~~I
~
I
I
Ir------------:lI"---- :::
tW(WH)!
I
-.I :.-
th(D)
DATA IN
W
- - - - - - - - - - - - - - - - - - - - - - - - - - - - VIH
VIL
write cycle timing (write enable)
~
Disable
1
1
SWCK
I+-
I
I I
I
I
~ ~
1
I
tsu(WH)
1l1li
th(W)
\{
w
Disable--.l
I
I
tsu(WL)
14--- N+1 ----..!
~
~ N ~
I
I I
I I
-.! i+1
~I
I
1 I
V
1
141l1li---
1
tw(W) ---~~I
VIL
I
1411111----1.~I- th(W)
I
"-:::
,
DATA IN
VIH
N-1
N
N+1
-
VIL
VIH
RSTW
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - VIL
TEXAS •
INSTRUMENTS
8-134
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•
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TMS4C1060
262 244-WORD BY 4-BIT
FIELD MEMORIES
SMGS050C - JANUARY 1988 -
REVISED NOVEMBER 1990
read cycle timing (reset read)
14-- N-1 ~
~--o --~
I I
1OC:::
tdls(CKL)
)@(-N---1-~
>@<__ >@<______
N
O
__
R
read cycle timing (read enable)
~
~
SRCK
I
I
N
---.l
Disable
--.!
:.--
I
1
~
1
I
I
tsu(RL)
tsu(RH)
I I I~
R
DATA OUT
th(R)
\{
•
I~
N-1
:
tW(R)
I
1
I
I ~ th(R) -+I
-.! I+t
.1 I
I
I
I
I
\
y:
-
.:
:.- tAC --.!
' - - - - VIL
I
1
~ ten(CKU
I
~
~
I
I I
I I
~ ~
N+1
Disable - - . :
N
I
~--N-+1-"'X
:::
RSTR
TEXAS •
INSTRUMENTS
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HOUSTON, TEXAS 77001
8-135
TMS4C1050
262 264·WORD BY 4·BIT
FIELD MEMORIES
SMGS050C -
JANUARY 1968 -
REVISED NOVEMBER 1990
read cycle timing (reset read)
14-- N-1 ----.I
14---0--~
I~
1
104
1
1 I
1
1
~tC(R)~
SRCK
1
I~
1
i
~tAC~
1
R
N-2
~
N-1
1
1 4 - - - - t h(RSTR)
- - -....:
\~
I
--.! ~
I
DATA OUT
.
tsu(RSTR) ~
1
1
tw(RL)
1
1
1
1
RSTR
.1
1
1
1
tW(RH)
.1
1
N
VIL
tv(OUT)
j@(
N
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - VIH
VIL
read cycle timing (read enable)
~Dlsable~
SRCK
- -...:
1
1
I4--N+1----.1
: . - DISable---':
1
1
1
1
1
VIL
1
-+i
I ~ th(R) ~
-+i ~ tsU(RH) 1
tsu(RL)
\l
I
R
t
1 4 - - - - h(R)
1
04
tW(R)
14
1..
DATA OUT
v:TJ)J
-----t~"i l.- tAC ~
1
---------o.4,'j.,..'j__________.J1
.•
110.
hll
JII"
t
.:
dls(RL)
1
~ ten(RH)
1
\
' - - - - VIL
1
1
1
r::v:x:v.~---X.
N_......,.2>---...,'/;---HI.Z------~
N+1
.
__
N-_1_1'<:£U\_ _
VOH
VOL
VIH
RSTW
---------------------------...)\~~--------------------------------
TEXAS •
INSlRUMENTS
8-136
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
VIL
TMS4C1050
262 244-WORD BY 4-BIT
FIELD MEMORIES
SMGS050C- JANUARY 1988 -
REVISED NOVEMBER 1990
read cycle timing (output enable and disable)
Case 1
SRCK
\,
/
..,,
I~
\
R
\
/
;1
1
tdls(CKL)
l~
/
I
I
.. I ten(CKL)
I
2
DATA OUT
<
Case 2
SRCK
R
/
\
i~
.,
tdls(RL)
I
J
DATA OUT
;-
\
/
\
Ii
1
ten(RH)
I~
.. I
1
C
TEXAS ~
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8-137
TMS4C1050, TMS4C1060
262 264-WORD BY 4-81T
FIELD MEMORIES
SMGS050C - JANUARY 1988 -
REVISED NOVEMBER 1990
cascade mode
RSTW,
RSTR
../
\------------------------------------
o
2
DOUT
6
7
1
CLOCK edge that
Initiates READ for WORD3
W/R
5
4
3
SWCK,
SRCK
../
-----«
--.I
: . - CLOCK edge that
1
Initiates WRITE for WORD3
1
1
tAC for WORD3 -+1
X
o
X
1
14-
X
2
1
1
3
II
~ 14-
X
4
X
X__6---,X___
5
tsu(D) for WORD3
cascade operation-signal connections
Reset Signa I
Serial Clock
TMS4C10XX
Data Inputs
4 Bits
.---
TMS4C10XX
RSTW
SWCK
RSTR
SRCK
Data In
Data Out
W
R
4 Bits
Enable Signal
TEXAS •
INSIRUMENTS
8-138
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
RSTW
SWCK
RSTR
SRCK
Data In
Data Out
W
r---r---
4 Bits
Rf-
TMS4C1050, TMS4C1060
262 244·WORD BY 4·BIT
FIELD MEMORIES
SMGS050C - JANUARY 1988 -
REVISED NOVEMBER 1990
new data access mode (TMS4C1050)
o
2
599
3
600
601
602
SWCK
wJ
RSTW
DA;~
J
=x
New 0
\~------------~)T\------------------------X
X
X
X
X
X
New 1
New 2
New 3
){ New 598
New 599
New 600
New 601
o
x==
2
SRCK
R
RSTR
D~~~
--------------------------~\T\----~/
------------------~)~
\~-----
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~\'II-)_ _ _ _ _ ___«
New 0
X
New 1
~
new data access mode (TMS4C1060)
0
2
599
3
600
601
602
SWCK
WJ
RSTW
DA;~
J
'/;
=x
\~------~)~\-------------X
X
X
X
X
X
_ _ _ _- J
New 0
New 1
New 2
){ New 599
New 600
New 601
New 602
o
x==
2
SRCK
R
RSTR
Data
Out
-----------~)~\-~/
--------------------~\~
-------------------~)I,~--------«
TEXAS
\'-------NewO
)(
New1
~
-1!1
INSTRUMENTS
POST OFFICE BOX 1443
•
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8-139
TMS4C1050, TMS4C1060
262 264·WORD BY 4·81T
FIELD MEMORIES
SMGS050C -
JANUARY 1988 -
REVISED NOVEMBER 1990
old data access mode (TMS4C1050)
0
2
119
3
120
122
121
SWCK
wJ
ASTW
DA;~
';';
.J
=x
NewO
\
New 1
X'--_--IX
'/;
New2
X
New3
){ New 119 X
New120X New121
X New122X==
o
2
SACK
A
----------------------~\~\--~/
\ ....._-----
ASTA
D~~~
----------------....,'/T;--------«
Old 0
X
Old 1
><==
old data access mode (TMS4C1060)
120
2
0
121
122
SWCK
wJ
J
'I';
\~--------------~SI~S------------------------------
ASTW
DA;~
=x
X
_ _- J
New 0
X
X
New 1
New 2 ){ New 118
X New 119 X New 120 X
o
New 121
x==
2
SACK
A
ASTA
DATA
OUT
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~\~\---J/
------------------~\~
----------------~S~\-------o«
-
TEXAS
~
INSlRUMENTS
8-140
POST OFFICE BOX 1443
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\ ....._----Old 0
X
Old 1
><==
TMS4C1070
262 264 WORD BY 4·BIT
FIELD MEMORY
SMGS070- NOVEMBER 1990
•
•
•
•
•
N Package
(Top View)
262 264 x 4 Organization
Single 5-V Power Supply (±10% Tolerance)
IE
Fast FIFO (First-In First-Out) Operation
- Full Word Continuous Read/Write
- Asynchronous Read/Write
25 ns
30 ns
50 ns
OE
R
RSTR
SRCK
DO
01
02
03
High Speed Read/Write Operation
TMS4C1070-30
TMS4C1070-40
TMS4C1070-60
VCC
W
RSTW
Fully Static (Refresh Free)
ACCESS
TIME
(MAX)
READ
CYCLE
TIME
(MIN)
WRITE
CYCLE
TIME
(MIN)
30ns
40 ns
60 ns
30 ns
40 ns
60 ns
00
01
02
03
VSS
•
Write Mask Function By Input Enable
•
Cascade Connection Capability
•
SO Package
(Top View)
SRCK
R
VCC
W
SWCK
NC
01
03
03
01
RSTR
OE
IE
RSTW
DO
NC
02
VSS
02
00
OJ Package
(Top View)
z
o
~
VCC
OE
Low Power Dissipation (Average
= 50 rnA at Minimum Cycle)
100
DO
•
1 Meg DRAM Compatible Process
Technology
•
18-Pin 300-MIL DIP, 20-Pin ZIP, 20/26-Lead
Surface Mount SOJ
~
a:
description
NC
NC
D1
D2
03
00
01
02
03
VSS
The TMS4C1070 is a 4-bit wide dynamic Field
Memory (FMEM) that refreshes its storage cells
automatically, so that it appears fully static to the
user. Internal arbitration logic prevents any conflict
between user access to memory and internal
refresh operations.
oLL
Z
W
o
Z
~
PIN NOMENCLATURE
00-03
IE
NC
OE
00-03
The TMS4C1070 is similar in operation and
functionality to Texas Instruments original serialaccess memory, the TMS4C1050. Compared to
the TMS4C1050, the TMS4C1070 has the
following additional functions and features:
a.
R
RSTR
SRCK
R
RSTR
RSTW
SRCK
SWCK
VCC
The Input enable function of the '4C1070
allows the user to write into selected locations
of the memory only, leaving the rest of the
memory contents unchanged.
Vss
W
c
Data Inputs
Input Enable
No Internal Connection
Output Enable
Data Outputs
Read Enable
Reset Read
Reset Write
Serial Read Clock
Serial Write Clock
5-V Supply
Ground
Write Enable
«
b.
The serial write and read pointers of the '4C1070 are static registers. This allows the user to interrupt
continuous write or read operations for an infinite length of time.
c.
The' 4C1 070 has been designed to allow easy cascading of several memory devices, in order to obtain a
larger storage depth or a longer delay.
ADVANCE INFORMATION document. contain information
~~vnei~:~~~rC~~~~!~re~~,~~I~a~:~~de~;~:~~::~jK~:t~:;!
are subject to change without notice.
Copyright © 1990, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
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8-141
TMS4C1070
262 264 WORD BY 4-81T
FIELD MEMORY
SMGS070 -
NOVEMBER 1990
Maximum storage capacity is 262 264 words x 4-bits. Read and write access to the TMS4C1070 occurs
serially, and normally starts at address 0, after read and write pointers are reset via RSTW and RSTR operations.
Read and write access may occur asynchronously, if desired by the user. When read access is delayed relative
to write access, the TMS4C1070 functions like a First-In First-Out (FIFO) register. The amount of delay
determines the "length" of this FIFO register. Unlike in a conventional FIFO register, however, data may be read
as many times as desired, after it is written into the storage array.
Minimum delay between writing into the device and reading out data is 600 SWCK cycles. Maximum delay is
one full field (262 144 write cycles) plus another 119 SWCK cycles.
The TMS4C1 070 is offered in an 18-pin dual-in-line plastic package (N suffix), a 20-pin zig-zag in-line package
(SD suffix), and a 20/26-lead surface mount SOJ package (DJ suffix). All are characterized for operation from
O°C to 70°C (L suffix).
operation
write operation
The write operation is controlled by two clocks, SWCK, RSTW, and with W, anci IE. The write operation is
accomplished by cycling SWCKand holding Wand IE high after a write address pointer reset operation (RSTW).
Each write operation must contain at least 120 write cycles, i.e. two successive RSTW operations must be
separated by at least 120 active write cycles (SWCK cycles) while W is high.
To transfer the last data written into the device, which at that time is still stored in the write line buffer to the
memory array, an RSTW operation is required after the last SWCK cycle.
reset write (RSTW)
The first positive transition of SWCK after RSTW has gone high resets the write address pOinters to zero. RSTW
setup and hold times are referenced to the rising edge of SWCK. The state of W may be high or low during any
reset operation. Before RSTW may be brought high again for a further reset operation, it must have been low
for at 1east 2 SWCK cycles.
data inputs (00-03) and write clock (SWCK)
The SWCK input latches the data inputs on chip when Wand IE are high. SWCK also increments the internal
write address pointer, when Wis high, regardless of the state of IE. Data-in setup and hold times are referenced
to the rising edge of SWCK.
.
write enable (W)
W is used to enable/disable incrementing the internal write address pOinter and to enable/disable writing into
the memory. A logic high on the W input serves to enable both functions and a logic low serves to disable both
functions. W setup and hold times are referenced to the rising edge of SWCK.
TEXAS
l.!1
INSTRUMENTS
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TMS4C1070
262264 WORD BY 4-BIT
FIELD MEMORY
SMGS070 -
NOVEMBER 1990
Input enable (IE)
IE is used to enable/disable writing into memory. A logic high on the IE enables writing, and a logic low disables
writing. The internal write address pointer is always incremented by cycling SWCK regardless of IE logic level.
Note that IE setup and hold times are referenced to the rising edge of SWCK.
Write. Cycle Function Table
SWCK RISING EDGE
X
W
IE
H
H
H
L
L
X
Write Address Pointer
Address Pointer Increment
Address Pointer Stop
00-03
Store Data
Not Store
Not Store
= Don't Care
read operation .
The read operation is controlled by four clocks, SRCK, RSTR, R, and OE. It is accomplished by cycling SRCK
and holding Rand OE high after a read address pointer reset operation (RSTR). Each read operation must
contain at least 120 read cycles, i.e. two successive RSTR operations must be separated by at least active 120
read cycles (SRCK cycles) while R is high.
Read Cycle Function Table
SRCK RISING EDGE
R
OE
H
H
H
L
L
H
L
L
Read Address Pointer
Address Pointer Increment
Address Pointer Stop
00-03
Data Out
HI-Z
Data Out
HI-Z
reset read (RSTR)
The first positive transition of SRCK after RSTR has gone high resets the read address pointers to zero. RSTR
setup and hold times are referenced to the rising edge of SRCK. The state of R may be high or low during any
reset operation. Before RSTR may be brought high again for a further reset operation, it must have been low
for at least 2 SRCK cycles.
data outputs (QO-Q3) and read clock (SRCK)
Data is shifted out of the data registers on the riSing edge of SRCK when Rand OE are high during a read
operation. The SRCK input increments the internal read address pOinter when R is high.
.
The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same
polarity as data in. The output becomes valid after the access time interval (tAd that begins with the positive
transition of SRCK. Data out valid time [tv(OUn 1is referenced to the rising edge of SRCK in the next cycle.
read enable (R)
R is used to enable/disable incrementing the internal read address pointer. A logic high on the R input enables
pointer incrementing by the next following positive SRCK transition, and a logic low disables pointer
incrementing. R setup and hold times are referenced to the rising edge of SRCK. The data at the outputs will
be the data read out during the SRCK cycle prior to R going low.
TEXAS ~
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8-143
TMS4C1070
262 264 WORD BY 4·81T
FIELD MEMORY
SMGS070 -
NOVEMBER 1990
output enable (DE)
DE is used as a data out enable/disable. A logic high on the DE input enables the output, and a logic low disables
the output. The internal read address pOinter is always incremented by cycling SRCK regardless of DE logic
level. The outputs will be clocked into the high-impedance (floating) state by the next positive SRCK transition
following DE being low. The disable time [tdis(CK)1 applies. The outputs will be enabled by the next positive SRCK
transition following DE being high. The enable time [t en (CK)1 applies.
power-up and Initialization
When the device is powered-up, it is not guaranteed to function properly until at least 100 ~s after VCC has
stabilized to a value within the range of recommended operating conditions. This time is defined as tpOWER-OK'
After tpOWER-OK, the following initialization sequence must be performed.
Because the read and write address pOinters are not valid after power-up, a minimum of 130 dummy read
operations (SRCK cyclfilS) must be performed, followed by an RSTR operation, to properly initialize the read
address pointer, and a minimum of 130 dummy write operations (SWCK cycles) must be performed, followed
by an RSTW operation, to properly initialize the write address pOinter. Dummy read cycles/RSTR and dummy
write cycles/RSTW may occur simultaneously.
If these dummy read and write operations start earlier than tpOWER-OK, while V CC and/or the substrate voltage
have not stablized yet, then it is required to perform an RSTR operation plus a minimum of 130 SRCK cycles
plus another RSTR operation, and an RSTW operation plus a minimum of 130 SRCK cycles plus another RSTW
operation, to properly initialize read and write address pointers.
old/new data access
There must be a minimum delay of 600 SWCK cycles between writing into memory and reading out from
memory. If reading of the first field starts, with an RSTR operation, before the start of writing the second field,
i.e. before the next RSTW operation, then the data just written in will be read out.
The start of reading out the first field of data may be delayed past the beginning of writing in the second field
of data for as many as 119 SWCK cycles. If the RSTR operation for the first field read-out occurs less than 120
SWCK cycles after the RSTW operation for the second field write-in, then the internal buffering of the device
assures that the first field will still be read out. The first field of data that is read out while the second field of data
is written is called old data.
In order to read out new data, i.e. the second field written in, the delay between RSTW operation and RSTR
operation must be at least 600 SWCK cycles. If the delay between RSTW and RSTR operations is more than
120 but less than 600 cycles, then the data read out will be undetermined, it may be old data or new data or a
combination of old and new data. Such a timing should be avoided.
cascade operation
The TMS4C1 070 has been designed to allow easy cascading of several memory devices, in order to obtain a
higher storage depth or a longer delay than can be achieved with only one memory device. See the
interconnection diagram on page 8-152 for details.
As illustrated in the timing diagram on page 8-152, the positive SRCK/SWCK edge at the beginning of a clock
cycle serves to initiate read-out, whereas writing in is initiated by the positive SWCK/SRCK edge at the end of
a clock cycle. This differs from the functionality of the TMS4C1 050, in which both the read-out and the write-in
are initiated at the beginning of a clock cycle.
TEXAS . .
INSTRUMENTS
8-144
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
1MS4C1070
262 264 WORD BY 4·B11
FIELD MEMORY
SMGS070 -
NOVEMBER 1990
internal operation
writing into memory
The first 120 words of data following the initial RSTW operation after power-up are written into a cache buffer,
the A line buffer initially, and will never get stored elsewhere, to allow read-out of data later without the delay
involved in retrieving it from the main memory array.
Starting from address 121, data is written into the write line buffer, top block, until this block (256 words long)
is full. Further writing then occurs to the bottom block of the write line buffer, while the top block is transferred
to the main memory array. By the time the bottom block is full, the top block has been transferred to memory
and can be used again to receive new incoming data. The channelling of input data into the top or bottom block
is controlled internally by the device and is transparent to the user.
After the 120-word long cache buffer has been filled with incoming data, the input line selector switches the
connection of the input port over to the B line buffer, to assure that the next field of data which will arrive later,
after a subsequent RSTW operation, does not over-write the content of the cache buffer. Each subsequent filling
of the cache buffer toggles the connection of the input port between the A and the B line buffers with the 121 st
SWCK pulse. The A and B line buffers, as well as the input line selector, are static registers.
The connection of the output port will also betoggled between the A and B line buffers by the 121 st SWCK pulse,
providing no read operation from a cache buffer is in progress at this time. The output port will always be
connected to the line buffer opposite to the one connected to the input port. In case a read operation from a cache
buffer is in progress when the 121 st SWCK occurs, the toggling of the output port connection will be delayed
until the cache buffer has been read out completely.
The requirement stated on page 8-143 that each write operation must contain at least 120 active SWCK cycles,
exists in order to assure that the toggling of the input and the output ports between the A line buffer and the B
line buffer functions without errors as described above.
The serial write pointer stores the (column) address of the last input data word received, while the write counter
stores the row address. The serial write pOinter of the TMS4C1 070 is a static register. Therefore no limit exists
for the maximum period of clocking inactivity, as was the case for the TMS4C1 060.
After the last worq of a full write cycle has been latched in (with a positive transition of the SWCK clock), the write
line buffer most likely will be partially filled without having been transferred to the main memory array. To assure
that the information contained in the write line buffer is stored also and cannot be lost, it is required that an RSTW
operation be performed within 1 ms after input = write clocking has stopped.
In addition to transferring the partially filled write line buffer into the main memory array, this RSTW operation
will also reset the write addresses (serial write pOinter) to zero, and due to the interna,l construction of the dynamic
serial write pointer register, this initial address of zero remains stored indefinitely. So regardless of how much
later a new write cycle starts, it is not necessary to perform another RSTW operation again at that time.
reading from memory
After an RSTR operation, data from the main memory array (starting at address 121) will be transferred to read
line buffer. Because this transfer required some time, the first 120 words will be read out of the A or B line buffer,
where they had been stored before (see writing into memory).
If the first RSTR operation occurs after the first but before the second RSTW operation, read access will be to
the same buffer that data had been written into during the first write cycle. Thus old data will be read out.
If the first RSTR occurs after the second RSTW operation, i.e. after the writinging of new data has already started,
then the delay between second RSTW and first RSTR operation determines, whether old data or new data will
be read out.
TEXAS •
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8-145
TMS4C1070'
262 264 WORD BY 4-BIT
FIELD MEMORY
SMGS070 -
NOVEMBER 1990
If this delay is less than 120 SWCK cycles, then the data will be read out from the line buffer that it was written
into during the previous write cycle, i.e. old data will be read out. A delay of less than 120 SWCK cycles will also
assure that all following data words are old data, because replacement of old data by new data in the main
memory array will occur later than the respective read access to each address in the array.
If this delay is more than 600 SWCK cycles, then the data will be read out from the line buffer that it was written
into during the current write cycle, i.e. new data will be read out. A delay of more than 600 SWCK cycles will also
assure that all following data words are new data, because replacement of old data by new data in the main
memory array will occur before the respective read access to each address in the array.
If this delay is more than 120 but less than 600 SWCK cycles, then the data read out can be either old or new
or a mixture of old and new data, because it cannot be predicted accurately, whether a word accessed for reading
has already been replaced by new data or not. Such a situation should be avoided.
After the first 120 words are read out of the A or B line buffer, read transfer from the main memory array to read
line buffer is finished, and subsequent reading will occur from this buffer. Similar to the write operation, while
one half of this buffer is being read out, the other half will be filled again by a new read transfer from the main
memory array.
»
c
~
z
o
m
-z
."
o
The serial read pOinter stores the (column) address of the last data word read out, while the read counter stores
the row address. The serial read pointer of the TMS4C1 070 is a static register. Therefore no limit exists for the
maximum period of clocking inactivity.
self-refresh and arbitration logic
The self-refresh and arbitration logic will keep the main memory information refreshed automatically without
requiring any user action, control the address pOinters for both read and write, and control the flow of information
both into and out of the main memory.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin except (see Note 1) .......................................... - 1 V to 7 V
Voltage range on Vee ................................................................. 0 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation ........................................................................... 1 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ...................................................... - 65°C to 150°C
:II
s:
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t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. and
functional operation ofthe device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
PARAMETER
UNIT
MIN
TYP
MAX
VCC
Supply voltage
4.5
5
5.5
VIH
High-level input voltage
2.4
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
°c
NOTE 2: VIL = - 1.5 V undershoot is allowed when device is operated in the range of recommended supply voltage.
TEXAS •
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8-146
POST OFFICE BOX 1443
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HOUSTON. TEXAS 77001
VCC+1
V
V
TMS4C1070
262 264 WORD 8Y 4-81T
FIELD MEMORY
SMGS070 -
NOVEMBER 1990
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
TMS4C1070-30
TEST CONDITIONS
PARAMETER
MIN
MAX
2.4
TMS4C1070-40
MIN
TMS4C1070-60
MAX
MIN
2.4
MAX
UNIT
V
2.4
VOH
High-level output voltage
10H =5 mA
VOL
low-level output voltage
10l = 4.2 mA
0.4
0.4
0.4
V
Input current (leakage)
VI = 0 to 6.5 V, VCC = 5 V,
All other pins = 0 V to VCC
±10
±10
±10
IlA
II
10
Output current (leakage)
Vo = 0 to VCC, VCC = 5 V, OE low
±10
±10
±10
1001
Average operating current
Minimum write/read cycle, OE low
50
45
35
IlA
mA
1002
Average standby current
After 1 RSTW/RSTR cycle,
Wand R low
10
10
10
mA
·capacltance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHzt
PARAMETER
MIN
TEST CONDITIONS
TYP
MAX
UNIT
CI
Input capacitance
VI =0
7
pF
Co
Output capacitance
VI = 0
10
pF
Z
t VCC equal to 5 V ± 0.5 V and the bias under test is 0 V.
Q
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
~
:aE
TEST
CONDITIONS
PARAMETER
TMS4C1070-30
MIN
MAX
TMS4C1070-40
MIN
MAX
TMS4C1070-60
MIN
30
MAX
UNIT
tAC
Access time from SRCK high
see Note 3
50
ns
tdis(CK)
Output disable time after SRCK high
see Note 4
6
25
6
25
6
25
ns
ten(CK)
Output enable time after SRCK high
see Note 3
6
25
6
25
6
25
ns
tv(OUn
Output valid time after SRCK high
See Note 3
6
25
6
6
ns
NOTES: 3. The load connected to each output is a 50 pF capacitor to ground, in parallel with a 218 Ohm resistor to 1.31 V. (See Figure 1.)
4. Disable times are specified from the initiating timing edge until the output is no longer driven by the memory. If disable times are to
bo measured by observing output voltage waveforms, sufficiently low load resistors and capacitors have to be used, and the RC time
constants of the load have to be taken into account.
a:
o
LL
Z
W
U
Z
>
.A
C
«
PARAMETER MEASUREMENT INFORMATION
Output
Under Test
---I. . .
R = 218 Q
-~'\Nv-- 1.31 V
T
CL=50pF
Figure 1. Output Load Circuit
TEXAS •
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8-147
TMS4C1070
262 264 WORD BY 4-BIT
FIELD MEMORY
SMGS070 -
NOVEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Notes 5 and 6)
TMS4C1070-30
MIN
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~
z
(")
m
'z-n
o
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s:
~
o
z
MAX
TMS4C1070-40
MIN
MAX
TMS4C1070-60
MIN
60
MAX
UNIT
tc(W)
Write cycle time
30
40
tc(R)
Read cycle time
30
40
60
ns
twiRl
Pulse duration, R-Iow
10
10
10
ns
ns
tw(W)
Pulse duration, W-Iow
10
10
10
ns
tw(lEt
Pulse duration, IE low
10
10
10
ns
tw(OE)
Pulse duration, OE low
10
10
10
ns
tw(RH)
Pulse duration, SRCK high
12
17
20
ns
twiRL)
Pulse duration, SRCK low
12
17
20
ns
tw(WH)
Pulse duration, SWCK high
12
17
20
ns
tw(WL)
Pulse duration, SWCK low
12
17
20
ns
tsu(D)
Data setup time before SWCK high
5
5
5
ns
tsu(RH)
R-high setup time before SRCK high
0
0
0
ns
tsu(RL)
R-Iow setup time before SRCK high
0
0
0
ns
tsu(VJl-il
W-high setup time before SWCK high
0
0
0
ns
tsu(WL)
W-Iow setup time before SWCK high
0
0
0
ns
tsu(IEH)
IE high setup time before SWCK high
0
0
0
ns
tsu(lEL)
IE low setup time before SWCK high
0
0
0
ns
tsu(OEH)
OE high setup time before SRCK high
0
0
0
ns
tsu(OEL)
OE low setup time before SRCK high
0
0
0
ns
tsu(RSTR)
RSTR setup time before SRCK high
3
3
3
ns
tsu(RSTW)
RSTW setup time before SWCK high
3
3
3
ns
th(D)
Data hold time after SWCK high
6
6
6
ns
th(R)
R hold time after SRCK high
6
6
6
' ns
th(W)
W hold time after SWCK high
6
6
6
ns
th(IE)
IE hold time after SWCK high
6
6
6
ns
th(OE)
OE hold time after SRCK high
6
6
6
ns
th(RSTR)
RSTR hold time after SRCK high
6
6
6
ns
th(RSTW)
RSTW hold time after SWCK high
6
6
6
IT
Input transition time
3
30
;3
30
3
ns
30
ns
NOTES: 5. Timing measurements are referenced to VIH (MIN) = 2.4 V and VIL (MAX) = 0.8 V. tT is measured between VIH (MIN) and VIL (MAX).
6. All cycle times assume IT =35 ns.
TEXAS
~
INSTRUMENTS
8-148
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
1MS4C1070
262 264 WORD 8Y 4·811
FIELD MEMORY
SMGS070 -
NOVEMBER 1990
write cycle timing (reset write)
I+--N-1
1
~
~o--~
~14----N----~~1
~tcCN)~
1
SWCK
1 1
___..rl
tW(WH):
I
I
~
00·03
=x
~I:
14
1
RSTW
I+N-2
1
1
1
tw(WL)
1 ~__~
1
1
1
1
1
-14-14--+t~:
1
1
1
tsu(RSTW)
VIH
VIL
~
I
rl--....;....----""'\
VIH
' - - - - - - - - - - VIL
-+I:+- th(O)
~ N-1 ~"",--_N__~_ _O-,~_ _~>C ~::
tsu(O)
W - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - VIH
and
VIL
IE
z
o
write cycle timing (write enable)
1l1li
~I
~ Olsable----J>j
~Olsable~
N
1
1
1
1
SWCK
1
1
1
---'
1_
tsu(WL)
1
1
1
1
!
-+\ ~
1
1+14---- t hCN)
~
W
VIH
'--_.-I"
1
00·03
=x
-+I
1
----+l~1
y_---;-:--.---i.~
VIH
1'- th(W) -.J ' - - - - -
1
~
tsu(WH)
1
~11III-----twCN) ----~~I
N-1
VIL
1
14-1
N
N+1
VIL
>C ~::
VIH
IE
VIL
=write mask operation)
write cycle timing (input enable
14
14
1
SWCK
1
N
1
~I
~ Olsable~
r---- Olsable~
r---- N + 3 --+l
1
I
I
I
1
1
1
1
1 1
1
1
I
1 1
1
1
"--_oil" 1
tsu(IEL)
-+\
1l1li
1
~~------------IY
IE
00·03
th(IE)
-+I
~I 1
=x
1
14 4 - - - - - - tw (IE)
!
N-1
~
I+i tsu(IEH)
1
:
VIH
VIL
I
I4-i
~
VIH
1\
~th(IE) ~
VIL
~I
N
N+3
>C ~::
VIH
W
VIL
TEXAS -111
INSTRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
c:
o
LL
Z
W
(,)
Z
~
c
WC :::
~--N-->W<
N -1
0
> W <_ _ _ _
00-03 --N---2--->W<
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ VIH
R
and
OE
»c
~
z
C')
read cycle timing (read enable)
14-1~----N ----~~I
SRCK
m
s:
I4---Dlsable~
I
~Dlsable~
~N+1~
I
I
I
I
I
I
1
I
I
I I
"-_.r
1
tsu(RL)
-z
"o:xJ
VIL
~
I
I
I
I
~
I
_ _ _ _ _ _ _ _ _ _""'1
I~
I~
VIL
Y ~th(R)~\----
~I
tw(R)
~I
1l1li
VIH
VIL
tAC
ten(CK)~
I
~~-N-+-1--
>C
N
00-03 _ _N_-_1_ _> W <
~
I
~ ~ tsu(RL)
"..1_11--_ _ _"'"'
VIH
~I
th(R)
~
R
I
I
I
VIH
VIL
OE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - VIH
o
z
VIL
read cycle timing (output enable)
14--- Disable~
~I
.---- N
SRCK
tsu(OEL)
~Dlsable~
~N+3~
I
1
I
1
I
I
I
I
I
I 1
I
1
1
~ ~
_________"""'\ 1 I 14
II
1'4 I
VIL
~ I+{ tsu(OEH)
~I
th(OE)
\l :
OE
VIH
I....-~II--_ _~~
Y ,....
I
~I
tw(OE)
tdls(CK) ~
th(OE)
VIH
-.i \
1
-----
J+- tAC
ten(CK) ~
VIL
~
I
>C
VIH
R -----~-----------------------------
VIH
00-03
N-1
>W<
N
)
HI-Z
@(..----N-+-3-
VIL
VIL
TEXAS
~
INSTRUMENTS
8-150
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
1MS4C1070
262 264 WORD BY 4-811
FIELD MEMORY
SMGS070 -
NOVEMBER 1990
write mask operation
SWCK
IE
\'-------'/
W
X
00-03
N
X
N
N+ 1
N+1
X
N+2
N+ 2
X
N+3
~
N+4
N+3
N+5
N+6
N+7
N+6
X
N+7
N+8
SRCK
OE
\
z
/
0
~
R
(New)
00-03
X
N
r---
(New)
HI-Z - - - - {
N+3
X
(Old)
(Old)
N+4
X N+5
(New)
X
N+6
~
(New)
X N+7 >C
a::
0
u.
Z
W
()
Z
~
c
«
-
TEXAS ~
INSTRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-151
TMS4C1070
262264 WORD BY 4-BIT
FIELD MEMORY
SMGS070- NOVEMBER 1990
cascade mode
..J
RSTW,
RSTR
SWCK,
SRCK
\~---------------------------------2
°
J
DOUT
4
1
CLOCK edge that
Initiates READ for WORD3
WilE,
R/OE
3
--+'
1
14-
X
><_---:-3
X
2
Initiates WRITE for WORD3
1
tAC for WORD3 -.1
---«'"-_0----.J
7
: . - CLOCK edge that
I
1
6
5
1
X
-:-1....J
II
~
X
4
x__
X'--__
6-J
5
1"- tsu(D) for WORD3
DIN
»
c
~
z
n
m
-z
cascade operation-signal connections
."
o
Reset Signa I
Serial Clock
:D
3:
TMS4C1070
~
-
o
Data Inputs
z
TMS4C1070
RSTW
SWCK
RSTR
SRCK
Data In
Data Out
4 Bits
RSTW
SWCK
Data In
4 Bits
-
~
R
OE
W
IE
Enable Signa I
TEXAS •
INSTRUMENTS
8-152
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
W
IE
RSTR I - SRCK
Data Out
4 Bits
R t--OE ~
TMS4C1070
262264 WORD BY 4·BIT
FIELD MEMORY
SMGS070 -
NOVEMBER 1990
new data access mode
o
2
600
601
602
SWCK
WilE
...I
RSTW
...I
00-03
=><",-_-,X
\_----------------------------------New 0
X New 1 X'-_---'X'-_---IXNew 599 ~ New 601 C
o
2
SRCK
R/OE
RSTR
00-03
z
o
1
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
----------------------~I
i:::;
«
:E-
\_--------
--------------------«
X
New 0
o:
o
LL
New 1
old data access mode
o
120
2
121
Z
122
W
SWCK
WilE
o
Z
...I
RSTW
...I
00-03
=><__-JX
~
(:1
\_---------------------------------NewO X
Newl
IIc:. C20[ROW]
G23/REFRESH ROW
4
RAS --=--___- - f 24,34,44,54 [PWR OWN]
CAS1
CAS2
CAS3
CAS4
5
6
21
23
&
23C22
&
23C32
&
23C42
&
23C52
24,25EN27
34,25EN37
44,25EN47
54,25EN57
W 3
OE 22
OQ1
A,226
OQ2
2
OQ3
24
OQ4
25
A,236
A,246
A,256
t This symbol is in accordance with ANSI/IEEE Std. 91-1984 and lEG Publication 617-12.
TEXAS
lJ1
INSTRUMENTS
8-158
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44460
1 048576 WORD 8Y 4·81T QUAD CAS
DYNAMIC RANDOM·ACCESS MEMORY
SMHS460 -
NOVEMBER 1990
functional block diagram
I
~
~ ~
•
A9
Column
Address
Buffers
16
·•
Column Decode
2
128K Array
128K Array
R
128KArray
16<
Row
Address
Buffers
fr+
Sense Amplifiers
~
L
•
~ ~
1
/
A1
•
~
Timing and Control
8
AO
•
~
'~
0
•
••
w
D
e
c
10
1
-±
128K Array
·••
>16
0
2
d
e
'---
-
128KArray
10
.,
I/O
Buffers
4 of 16
Selection
V
~
~
In
Reg.
Data
Out
Reg.
.
o
o
J
~
001-D04
128K Array
z
o
~
/
:E
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ....................................,............. - 1 V to 7 V
Voltage range on Vee ............................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. O°C to 70 0
Storage temperature range ...................................................... - 65°e to 150 0 e
e
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
Supply voltage
VSS
Supply voltage
V,H
High-level input voltage
2.4
6.5
V,L
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
°c
V
V
0
V
NOTE 2: Tho algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for
logic voltage levels only.
TEXAS ~
INS1R.UMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-159
a:
ou.
Z
W
(.)
Z
~
c
«
TMS44460
1 048 576 WORD BY 4-BIT QUAD CAS
DYNAMIC RANDOM-ACCESS MEMORY
SMHS460 -
NOVEMBER 1990
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
VOH
High-level output
voltage
10H =-5 mA
VOL
Low-level output
voltage
10L = 4.2 mA
II
Input current
(leakage)
10
m
-z
'"T1
o
:D
s:
~
o
z
_TMS44460·70
MAX
MIN
MIN
2.4
MAX
2.4
TMS44460·80
TMS44460·10
MIN
MIN
MAX
2.4
MAX
UNIT
2.4
V
0.4
0.4
0.4
0.4
V
VI = 0 to 6.5 V,
VCC = 5 V, All other
pins = 0 V to VCC
±10
±10
±10
±10
t-tA
Output current
(leakage)
Vo = 0 to 6.5 V,
VCC = 5.5 V, CAS high
±10
±10
±10
±10
ICC1
Read/write cycle
current
tRWC = minimum,
VCC = 5.5 V
95
85
75
65
-2
2
2
Standby current
After 1~mory_ TTL
cycle, RAS and CAS
high, VIH = 2.4 V
CMOS
2
ICC2
1
1
1
1
95
85
75
65
mA
70
60
50
40
mA
»c
~
z(1
TMS44460·60
TEST
CONDITIONS
PARAMETER
ICC3
tRWC = minimum,
VCC = 5.5 V,
Average refresh
current (RAS-only RAS cycling, CAS high
orCBR)
(RAS-only),
RAS low, after CAS low (C B R)
ICC4
Average page
current
-
~A
mA
mA
tpc = minimum,
VCC = 5.5 V,
RAS low, CAS cycling
capacItance over recommended ranges of supply voltage and operating free-air temperature,
f =1 MHz (see Note 3)t
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(D)
Input capacitance, data inputs
5
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
t Capacitance measurements are made on a sample basis only.
NOTE 3: VCC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
TMS44460·60
PARAMETER
TMS44460·70
MAX
MIN
MIN
MAX
TMS44460·80
MIN
MAX
TMS44460·10
MIN
MAX
UNIT
tCAC
Access time from CAS low
15
18
20
25
ns
tCAA
Access time from column address
30
35
40
45
ns
tRAC
Access time from RAS low
60
70,
80
100
ns
tOEA
Access time from OE low
15
18
20
25
ns
tCAP
Access time from column precharge
35
40
45
50
ns
tOFF
Output disable time after CAS high
(see Note 4)
0
15
0
18
0
20
0
25
ns
tOEZ
Output disable time after OE high (see Note 4)
0
15
0
18
0
20
0
25
ns
NOTE 4: tOFF and tOEZ are specified when the output is no longer driven.
TEXAS •
INSTRUMENTS
8-160
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS44460
1 048 576 WORD BY 4-BIT QUAD CAS
DYNAMIC RANDOM-ACCESS MEMORY
SMHS460- NOVEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
TMS44460-60
MAX
MIN
TMS44460-70
MIN
MAX
TMS44460-80
MIN
MAX
TMS44460-10
MIN
MAX
UNIT
tRC
Read cycle time (see Note 6)
110
130
150
180
twc
Write cycle time
110
130
150
190
ns
tRWC
Read-write/read-modify-write cycle time
155
181
205
245
ns
tpc
Page-mode read or write cycle time
(see Note 7)
40
45
50
55
ns
ns
ns
tpCM
Page-mode read-modify-write cycle time
85
96
105
120
tcp
Pulse duration, CAS high
10
10
10
10
tCAS
Pulse duration, CAS low (see Note 8)
15
tRP
Pulse duration, RAS high (precharge)
40
tRAS
Non-page-mode pulse duration, RAS low
(see Note 9)
60
10000
70
10000
80
10000
100
10000
ns
tRASP
Page-mode pulse duration, RAS low
(see Note 9)
60
100000
70
100 000
80
100 000
100
100 000
ns
twp
Write pulse duration
15
15
15
20
ns
a
a
a
a
a
ns
0
ns
0
0
0
ns
0
0
0
ns
10000
18
10000
50
20
10000
60
25
ns
10000
ns
ns
70
z
o
tASC
Column-address setup time before CAS low
tASR
Row-address setup time before RAS low
tDS
Data setup time before W low (see Note 10)
tRCS
Read setup time before CAS low
a
a
a
a
tWSR
W-high setup time (see Note 11)
10
10
10
10
ns
twcs
W-Iow setup time before CAS low
(see Note 12)
0
0
0
0
ns
tCWl
W-Iow setup time before CAS high
15
18
20
25
ns
tRWL
W-Iow setup time before RAS high
15
18
20
25
ns
tCAH
Column-address hold time after CAS low
(see Note 10)
10
15
15
20
ns
(.)
tRAH
Row-address hold time after RAS low
10
10
10
15
ns
Z
tAR
Column-address hold time after RAS low
(see Note 13)
50
55
60
75
ns
tClCH
Hold time, CAS low to CAS high
5
5
5
5
ns
tDH
Data hold time after CAS low (see Note 10)
10
15
15
20
ns
tDHR
Data hold time after RAS low (see Note 13)
50
55
60
75
ns
a
a
0
ns
0
ns
tRCH
Read hold time after CAS high (see Note 14)
0
0
tRRH
Read hold time after RAS high (see Note 14)
0
0
W-high hold time (see Note 11)
10
10
10
10
ns
tWHR
Continued next page.
NOTES: 5. Timing measurements are referenced to VIL max and VIH min.
6. All cycle times assume tT = 5 ns.
7. tpc > tcp min + tCAS min + 2'T.
8. In a read-modify-write cycle, tCWD and tCWL must be observed. Depending on the user's transition times, this may require additional
CAS low time (tCAS).
9. In a read-modify-write cycle, tRWD and tRWL must be observed. Depending on the user's transition times, this may require additional
RAS low time (tRAS).
10. Later of CAS or Win write operations.
11. CAS-before-RAS refresh only.
12. Early write operation only.
13. The minimum value is measured when tRCD is set to tRCD min as a reference.
14. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS
l!1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-161
~
.~
a:
o
u.
Z
W
~
C
cd:
TMS44460
1 048576 WORD BY 4-BIT QUAD CAS
DYNAMIC RANDOM-ACCESS MEMORY
SMHS460 -
NOVEMBER 1990
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5) (concluded)
TMS44460-60
MIN
»c
~
z
(')
m
-Z
-n
a
:c
s:
~
a
z
MAX
TMS44460-70
MIN
MAX
TMS44460-80
MIN
MAX
TMS44460-10
MIN
MAX
UNIT
tWCH
Write hold time after CAS low (see Note 12)
15
15
15
20
ns
tWCA
Write hold time after AAS low (see Note 13)
50
55
60
75
ns
tOEH
OE command hold time
15
18
20
25
ns
tCSH
Delay time, AAS low to CAS high
60
70
80
100
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
0
ns
tASH
Delay time, CAS low to RAS high
15
18
20
25
ns
tCWD
Delay time, CAS low to W low (see Note 15)
40
tRCD
Delay time, RAS low to CAS low (see Note 16)
20
45
20
52
20,
60
25
75
ns
tAAD
Delay time, RAS low to column address
(see Note 16)
15
30
15
35
15
40
20
50
ns
tAAl
Delay time, column address to RAS high
30
35
40
45
ns
tCAl
Delay time, column address to CAS high
30
35
40
45
ns
tAWD
Delay time, RAS low to W low (see Note 15)
85
98
110
135
ns
tAWD
Delay time, column address to W low
(see Note 15)
55
63
70
80
ns
tcu
Delay time, CAS low to output low Z
0
0
0
0
ns
tOE;D
Delay time, OE h!gh before data at DQ
15
18
20
25
ns
tAOH
Delay time, OE low to AAS high
10
10
10
10
ns
tCHA
Delay time, AAS low to CAS high
(see Note 11)
15
15
20
20
ns
tCSA
Delay time, CAS low to RAS low (see Note 11)
10
10
10
10
ns
tAPC
Delay time, AAS high to CAS low
(see Note 11)
0
0
0
0
ns
tREF
Refresh time interval
IT
Transition time
46
16
50
2
16
2
NOTES: 5.Timing measurements are referenced to Vil max and VIH min.
11. CAS-before-AAS refresh only.
12. Early write operation only.
13. The minimum value is measured when tACO is set to tACO min as a reference.
15. Aead-modify-write operation only.
16. Maximum value specified only to guarantee access time.
TEXAS ."
INSTRUMENTS
8-162
POST OFFICE BOX 1443
•
50
HOUSTON. TEXAS 77001
50
60
16
2
50
2
ns
16
ms
50
ns
TMS44460
1 048 576 WORD BY 4-BIT QUAD CAS
DYNAMIC RANDOM-ACCESS MEMORY
SMHS460 -
NOVEMBER 1990
PARAMETER MEASUREMENT INFORMATION
1.31 V
~
Oulpu' Undene.'
---1
T
VCC =5V
RL=2l8Q
R1
=828 Q
R2
=295 Q
Output Under Test
CL = 100 pF
CL=100pF
(a) Load Circuit
(b) Alternate Load Circuit
Figure 1. Load Circuits for Timing Parameters
z
o
~
~
a:
o
LL
Z
W
(.)
Z
~
C
~
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON", TEXAS 77001
8-163
TMS44460
1 048576 WORD BY 4-BIT QUAD CAS
DYNAMIC RANDOM-ACCESS MEMORY
SMHS460 -
NOVEMBER 1990
read cycle
:~
tRC
~
Vi
I
: :
I
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I :
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CAS
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II
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~ tCAH
I
tRCS
I
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~
tRCH --.:
z
001·004
In order to hold the address latched by the first CASx going low, the parameter tClCH must be met.
tCAC is measured from CASx to its corresponding OQx.
CAS x order is arbitrary.
Output may go from high-impedance to an invalid data state prior to the specified access time.
TEXAS
..l,s
'V
INSlRUMENTS
8-164
--+-I--·~
.1 I
I::
,
POST OFFICE BOX 1443
•
I
I
o
NOTES: 17.
18.
19.
20.
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14
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::
tRAS
*-
tr ~
I ~tRCD-"
:
~
HOUSTON, TEXAS 77001
__
tRRH
TMS44460
1 048 576 WORD BY 4-BIT QUAD CAS
DYNAMIC RANDOM-ACCESS MEMORY
SMHS460 -
NOVEMBER 1990
write cycle
~~-----------------------twc--------------------~~
I
RAS
N-!I"-I-_-_-___-_-_-___-_-_-___-_-_-_-_-_-_t_R_A_S:~~::_-_-_-~_
-~--1y:
-_-_
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:\1
/
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(see Note 10):
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r----~
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(see Note 23) 14
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Valid In
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Valid In
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Valid In
)>-'------------
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Valid In
)>-------~(
I
~tOEO
'OEJ
NOTES: 17. In order to hold the address latched by the first CASx going low, the parameter tCLCH must be met.
18. tCAC is measured from CASx to its corresponding OQx.
19. CASx order is arbitrary.
.
21. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
23. Referenced to CAS x or W, whichever occurs last.
TEXAS
-IJ1
INSlRUMENlS
POST OFFICE BOX 1443
•
~
II:
I
tWCH
tOHR ~
I
004
~ tCWL ~
----.:
-.!
tWCR
2S~OtR'i~aL
:
002
~L
I
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~twcs
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oat
twp
1
~~
I
W
1
:
~
HOUSTON, TEXAS 77001
8-169
TMS44460
1 048 576 WORD BY 4-BIT QUAD CAS
DYNAMIC RANDOM-ACCESS MEMORY
SMHS460 -
NOVEMBER 1990
RAS-only refresh timing
»c
~
OQ1-0Q4 - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - -
VIL/VOL
z
(")
m
-z
"'T1
o:IJ
NOTE 24:
All CASx must be high.
s:
~
o
z
TEXAS . .
INSTRUMENTS
8-170
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
TMS44460
1 048576 WORD BY 4-BIT QUAD CAS
DYNAMIC RANDOM-ACCESS MEMORY
SMHS460 -
NOVEMBER 1990
hidden refresh cycle
z
o
~
:E
a::
oLL
Z
W
o
Z
~
c
«
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
8-171
TMS44460
1 048 576 WORD BY 4·BIT QUAD CAS
DYNAMIC RANDOM·ACCESS MEMORY
SMHS460 -
NOVEMBER 1990
automatic (CAS-before-RAS) refresh cycle timing
1~~--------------------tRC------------------~~1
~ tRP -----+j ~I~___________ tRAS -----------~~I
"\;
}IT~--VIH
:~II..I_ _ _ _ _ _ _ _ _ _ _ _ _ _--"7
VIL
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. I 141-11II-------tCHR -------~~I
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11~
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y,..---------VIH
VIL
--joI~t---~~1 t..---.~t-I tWHR
:t=O
~
Z
(1
m OQ1-0Q4---------------HI-Z - - - - - - - - - - - - - - -
-Z
"oII
VIHNOH
VILNOL
NOTE 25:
Any CASx may be used.
s:
~
o
z
TEXAS
.J!}
INSTRUMENlS
8-172
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
::::
Military Products
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Military Products
-.<
ii
Introduction to Military Data Sheets
This section contains data sheets of Military MOS Memory devices. In conformance with M IL-STD-883, all parameters
listed on the appropriate data sheet are tested if a min or max limit is specified unless there are exceptions listed in
the Military Products Baseline and Errata to Data Books. The errata book should be referenced for a complete errata
status of all data sheets. Errata will include actual parametric limit changes, notations that indicate that a parameter
is not production tested, parametric test condition changes, and clarifying notes. The Military Products Baseline and
Errata to Data Books is published twice a year (20 and 40) with updates published on a monthly basis. If you desire
to be added to the mailing list for this publication contact:
Linda Bonner
Market Communications
Texas Instruments Incorporated
P.O. Box 60448, MIS 3028
Midland, TX 79711-0448
(915) 561-7142
Process Flows
Several process flows are available for devices manufactured by Texas Instruments Military Products. They include
Class B and Class S screened devices that conform to MIL-STD-883 Method 5004, as well as special flows such as
the Lockheed Monitored Line (Space Level) and the DESC Standard Military Drawing (SMD). These and other process flows are described in the Military Products Designer's Reference Guide, literature number SGYZ001 C. The
flows are typical and may vary depending on changes to applicable military standards, such as MIL-M-3851 0 or MILSTD-883. Contact. the factory for the processing levels available by device.
PROCESS
FLOWS
DESCRIPTION
JAN S
QPL products processed to MIL-M-38510 Level S for space-level applications.
LMSC
Products processed on the Lockheed Monitored Line A program developed by the Air Force for space-level applications.
SEQ
JAN B
DESC/SMD
SNJ/SMJ
SN/SM
Non-JAN products processed to Level S to negotiated electrical specifications for space-level applications.
QPL products processed to MIL-M-851 0 Level B for military applications.
Standard Military Drawing products processed to Level B with Table 1 Electricals controlled by DESC.
Products processed to MIL-STD-883.
Products processed per test flow defined in reference document.
*
SMXt/SNX
Products assembled and tested by Military Products prior to production release. No minimum screening or testing required.
SMP/SNP
Devices representative of production material with military temperature range testing. Shipped without generic coverage.
SMX devices are experimental or have not been fully characterized and specifications are preliminary and subject to change. Notwithstanding
any provisions to the contrary. TI makes no warranty, either expressed, implied or statutory (including any implied warranty of merchantability
or fitness for a specific purpose) as to devices or that a final production version will be sold.
Refer to Military Products Designer's Reference Guide, SGYZ001C.
TEXAS .J!}
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
9-1
Introduction to Military Data Sheets
TEXAS ~
INSlRUMENTS
9-2
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ44C256
262,144-WORD BY 4-811 DYNAMIC RANDOM-ACCESS MEMORY
MAY 1989-REVISED FEBRUARY 1990
•
•
•
262,144 x 4 Organization
(TOP VIEW)
Single 5-V Supply (10% Tolerance)
001
Performances Ranges:
SMJ44C256-10
SMJ44C256-12
SMJ44C256-15
•
JD PACKAGEt
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME
OR
(ta(C)
ta(R)
ta(CA) WRITE
(tRAC)
(tCAC)
(tCAA) CYCLE
(MAX)
(MAX)
(MAX)
(MIN)
100 ns
25 ns
45 ns
190 ns
120 ns
30 ns
55 ns 220 ns
150 ns
40 ns
70 ns 260 ns
Long Refresh Period . . .
512-Cycle Refresh in 8 ms (Max)
•
3-State Unlatched Output
W
003
CAS
TF
G
AO
A1
A8
A7
A6
A2
A3
A5
VCC
A4
HJ. HL. AND FQ PACKAGEst
(TOP VIEW)
OQ1
10 26
PVSS
25
004
002 ::2
W 3
RAS r'4
•
Lower Power Dissipation
•
Texas Instruments EPIC'" CMOS Process
•
All Input and Clocks Are TTL-Compatible
•
- 55°C to 125°C Operating Temperature
Range
•
Packaging Offered:
20-Pin 300-Mil Ceramic DIP (JD Suffix)
.20-Lead Ceramic Surface Mount Package
(HJ Suffix)
20-Terminal Low-Profile Leadless Ceramic
Surface Mount Package (HL Suffix)
20-Terminal Leadless Ceramic Surface
Mount Package (Fa Suffix)
•
VSS
004
RAS
Enhanced Page Mode Operation with
CAS-Before-RAS Refresh
•
002
TF
5
AO
A1
9
24 t:: 003
23
CAS
G
22
18
A8
10
A2 r'11
17
16
A7
A6
A3
12
15
A5
VCC [ 13
14
A4
tThe packages shown here are for pinout reference only.
PIN NOMENCLATURE
High Reliability MIL-STD-883C Processing
description
The SMJ44C256 is a high-speed, 1,048,576-bit
dynamic random-access memory organized as
262,144 words of four bits each. This device
employs state-of-the-art EPIC'" (Enhanced
Process Implanted CMOS) technology for high
performance, reliability, and low power ata low
cost.
AO-A8
Address Inputs
CAS
DQ1-DQ4
Column-Address Strobe
Data In/Data Out
G
Data-Output Enable
RAS
Row-Address Strobe
TF
Test Function
iN
VCC
Write Enable
5-V Supply
VSS
Ground
operation
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row-address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is thus eliminated. The
maximum number of columns that may be accessed is determined by the maximum RAS low time and
the CAS page-mode cycle time used. With minimum CAS page cycle time, all 512 columns specified by
column addresses AO through A8 can be accessed without intervening RAS cycles.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA documents contain information
current I I of publication date. Products conform to
spacifications per the terms of TeXIs Instruments
standard warranty. Production processing does not
nacllllarily include testing of all parameten.
Copyright © 1990, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
9-3
SMJ44C256
262,144·WORD BY 4·B11 DYNAMIC RANDOM·ACCESS MEMORY
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the
falling edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling
edge of CAS latches the column addresses. This feature allows the SMJ44C256 to operate at a higher
data bandwidth than conventional page-mode parts, since data retrieval begins as soon as column address
is valid rather than when CAS transitions low. This performance improvement is referred to as "enhanced
page-mode". Valid column address may be presented immediately after th(RA) (row-address hold time)
has been satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained after
talC) max (access time from CAS low,) if ta(CA) max (access time from column address) has been satisfied.
In the event that column addresses for the next page cycle are valid at the time CAS goes high, access time
for the next cycle is determined by the later occurrence of talC) or ta(CP) (access time from rising edg~
of CAS).
address (AO through AS)
Eighteen address bits are required to decode 1 of 262,144 storage cell locations. Nine row-address bits
are set up on pins AO through AS and latched onto the chip by the row-address strobe (RAS). Then nine
column-address bits are set up on pins AO through A8 and latched onto the chip by the column-address
strobe (CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar
to a chip enable in that it activates the sense amplifiers as well as the row decoder. The SMJ44C256 CAS
is used as a chip select activating the output buffer, as well as latching the address bits into the columnaddress buffers.
write enable (W)
The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects
the read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard
TTL circuits without a pull-up resistor. The data input is disabled when the read mode is selected. When
W goes low prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle
permitting a write operation with G grounded.
data in (001-004)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling
edge of CAS or W strobes data into the on-chip data latch. In an early write cycle, W is brought low prior
to CAS and the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed
write or read-modify-write cycle, CAS will already be low, thus the data will be strobed in by W with setup
and hold times referenced to this signal. In a delayed or read-modify-write cycle, G must be high to bring
the output buffers to high impedance prior to impressing data on the 110 lines.
TEXAS •
INSTRUMENTS
9-4
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
SMJ44C256
262,144·WORD BY 4·BI1 DYNAMIC RANDOM·ACCESS MEMORY
data out (001-004)
The three-state output buffer provides direct TTL compatability (no pull-up resistor required) with a fanout
of two Series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance
(floating) state until CAS and G are brought low. In a read cycle the output becomes valid after the access
timer interval talC) that begins with the negative transition of CAS as long as ta(R) and ta(CA) ar~satisfied.
The output becomes valid after the access time has elapsed and remains valid while CAS and G are low ..
CAS or G going high returns it to a high-impedance state. This is accomplished by bringing G high prior
to applying data, thus satisfying td(GHD).
output enable (6)
Gcontrols the impedance of the output buffers. When Gis high, the buffers will remain in the high-impedance
state. Bringing G low during a normal cycle will activate the output buffers putting them in the lowimpedance state. It is necessary for both G and CAS to be brought low for the output buffers to go
into the low-impedance state. Once in the low-impedance state, they will remain in the low-impedance
state until either G or CAS is brought high.
refresh
A refresh operation must be performed at least once every eight milliseconds to retain data. This can be
achieved by strobing each of the 512 rows (AO-A8). A normal read or write cycle will refresh all bits in
each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
thus conserving power as the output buffer remains in the high-impedance state. Externally generated
addresses must be used for a RAS-only refresh. Hidden refresh may be performed while maintaining valid
data at the output pin. This is accomplished by holding CAS at VIL after a read operation and cycling RAS
after a specified precharge period, similar to a RAS-only refresh cycle.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS [see parameter td(CLRL)Rl and
holding it low after RAS falls [see parameter td(RLCH)R]. For successive CAS-before-RAS refresh cycles,
CAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated
internally. The external address is also ignored during the hidden refresh option.
power up
To achieve proper device operation, an initial pause of 200 p's followed by a minimum of eight initialization
cycles is required after power up to the full V CC level.
test function pin
During normal device operation, the TF pin must be either disconnected or biased at a voltage less than
or equal to VCC.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
9-5
SMJ44C256
262.144·WORD BY 4·81T DYNAMIC RANDOM·ACCESS MEMORY
logic symbol t
AO
A1
A2
A3
A4
A5
A6
A7
A8
RAM 256K x 4
2009/2100
6
7
8
9
11
12
13
14
15
>A
4P:
17~
W
G
001
002
003
004
20017/2108 ,
~C20[ROW)
G23/[REFRESH ROW)
24[PWR OWNI
~ C21 [COL)
G24
&
3r
16
1
0
262.143
23.210
r---.. G25
P.23C22
24.25EN
....,
r
A.220
2'k- 'V 26
A.Z26"r
18
19
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for the JD package.
TEXAS
~
INSTRUMENTS
9-6
POST OFFICE BOX 1443 •
HOUSTON .. TEXAS 77001
262,144-WORD BY 4-811
SMJ44C256
MEMORY
DY~JArJlIC RA~JDOM-ACCESS
functional block diagram
t t f t
TIMING AND CONTROL
}
--..
ROW
ADDRESS
BUFFERS
(91
r-+-
AO
---[
,I
1I
256K
ROW
256K
ARRA Y DECODE ARRAY
SENSE AMPLIFIERS
·v
A1
r-----
A2
~
A3
COlUMN
ADDRESS
BUFFERS
r-----
........
---........
1/0
BUFFERS
~ 4 OF 8
~ SELECTION
r--
A7
~
f---
A8
~
A4
A5
A6
(9)
~
~
COLUMN DECODE
~
SENSE AMPLIFIERS
,I
256K
ARRA Y
ROW
DECODE
I
r-r--
DATA
IN
REG,
DATA
OUT
REG,
4
r-t-
4
I
4
I'-
256K
ARRAY
D01- D04
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
Voltage range on any pin (see Note 1) ...................................... -1 V to 7 V
Voltage range-on Vee ................................................... 0 V to 7 V
Short-circuit output current .................................................. 50 rnA
Power dissipation ............................................................ 1 W
Operating free-air temperature range ................................... - 55°C to 125°C
Storage temperature range .......................................... - 65°C to 1 50°C
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
9-7
SMJ44C256
262,144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
recommended operating conditions
L VERSION
MIN
VCC Supply voltage
VSS Supply voltage
M VERSION
NOM
MAX
MIN
5
5.5
4.5
4.5
0
MAX
5
5.5
UNIT
V
V
0
VIH
High-level input voltage
2.4
6.5
VIL
TA
Low-level input voltage (see Note 2)
-1
0.6
Operating free-air temperature
TC
Case temperature
NOTE 2:
NOM
2.4
-1
6.5
V
0.6
V
-55
0
°c
70
125
°c
The algebraic convention, where the negative (less positive) limit is designated as maximum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
PARAMETER
SMJ44C256-10
TEST
CONDITIONS
MIN
VOH High-level output voltage 10H = - 5 rnA
VOL Low-level output voltage 10L = 4.2 rnA
II
10
Input current (leakage)
Output current (leakage)
ICC1 Read/write cycle current
ICC2 Standby current
MAX
2.4
VI = 0 V to 5.8 V, VCC = 5 V,
All other pins = 0 V to VCC
Vo = 0 V to Vcc, Vcc = 5.5 V,
CAS high
tc(rdW) = minimum,
VCC = 5.5 V
After 1 memory cycle,
RAS and CAS high, VIH = 2.4 V
SMJ44C256-12 SMJ44C256·15
MIN
MAX
MIN
MAX
2.4
2.4
UNIT
V
0.4
0.4
0.4
V
±10
±10
±10
p.A
±10
±10
±10
p.A
70
60
55
rnA
3
3
3
rnA
ICC3 Average refresh current
tc(rdW) = minimum, VCC = 5.5 V,
RAS cycling, CAS high
65
55
50
rnA
ICC4 Average page current
tc(P) = minimum, VCC = 5.5 V,
RAS low, CAS cycling
45
35
30
rnA
TEXAS.
INSTRUMENTS
9-8
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
262,144·V'JORD BY 4·811
SMJ44C256
MEMORY
DYr~AMIC RAr~DOM·ACCESS
capacitance over recommended supply voltage range and operating temperature range, f
(see Note 3)
PARAMETERt
Ci(A)
MIN
1 MHz,
TYP:t MAX
Input capacitance, address inputs
Ci(RC) Input capacitance, strobe inputs
Ci(W) Input capacitance, write-enable input
Output capacitance
Co
UNIT
5
7
pF
6
8
8
8
pF
6
6
pF
pF
NOTE 3: Vee equal to 5.0 V ± 0.5 V and the bias on pins under test is 0.0 V.
tCapacitance is sampled only at initial design and after any major change.
:tAli typical values are at TC = 25°C and nominal supply voltages.
switching characteristics over recommended supply voltage range and operating temperature range
(see Figure 1)
ALT.
PARAMETER
SMJ44C256-10
SYMBOL
MIN
MAX
SMJ44C256-12 SMJ44C256-15
MIN
MAX
MIN
MAX
UNIT
talC)
Access time from CAS low
tCAC
25
30
40
ns
ta(CA)
Access time from column address
tCAA
45
55
70
ns
ta(R)
Access time from RAS low
tRAC
100
120
150
ns
ta(G)
Access time from Glow
tGAC
25
30
40
ns
Access time from column precharge
tCAP
50
60
75
ns
ta(CP)
Output disable time after CAS
tdis(CH)
high (see Note 4)
tOFF
0
25
0
30
0
35
ns
tGOFF
0
25
0
30
0
35
ns
Output disable time after G
tdis(G)
NOTE 4:
high (see Note 4)
tdis(CH) andtdis(G) are specified when the output is no longer driven.
TEXAS
-II}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
9·9
SMJ44C256
262,144·WORD BY 4·BIT DYNAM.IC RANDOM·ACCESS MEMORY
timing requirements over recommended supply voltage range and operating temperature range
ALT.
SMJ44C256-10
SMJ44C256-12 SMJ44C256-15
MIN
MAX
MIN
MAX
UNIT
SYMBOL
MIN
tc(rd)
Read cycle time (see Note 6)
tRC
190
220
260
tc(W)
Write cycle time
twc
190
220
260
ns
tc(rdW)
Read-write/read·modify-write cycle time
tRWC
270
305
355
ns
tpc
55
65
80
ns
tpCM
ns
Page-mode read or write
tc(P)
cycle time (see Note 7)
tc(PM)
Page·mode read-modify-write cycle time
tw(CH)
Pulse duration, CAS high
tw(CL)
Pulse duration, CAS low (see Note 8)
tw(RH)
Pulse duration RAS high (precharge)
135
150
175
tcp
10
15
25
tCAS
25
tRP
80
tRAS
100
Non-page·mode pulse duration,
twiRL)
RAS low (see Note 9)
Page-mode pulse duration,
tw(RL)P
tRASP
RAS low (see Note 9)
MAX
10,000
30
10,000
90
10,000
100 100,000
120
ns
10,000
10,000
ns
ns
100
120 100,000
10,000
ns
150100,000
ns
150
tw(WL)
Write pulse duration
twp
15
25
ns
tsu(CA)
Column-address setup time before CAS low
tASC
5
5
5
ns
tsu(RA)
Row-address setup time before RAS low
tASR
0
0
0
ns
tDS
0
0
0
ns
tRCS
0
0
0
ns
twcs
0
0
0
ns
Data setup time before
tsu(D)
tsu(rd)
W low (see Note 10)
Read setup time before CAS low
W-Iow setup time before
tsu(WCL)
CAS low (see Note 11 )
20
40
ns
tsu(WCH)
W-Iow setup time before CAS high
tCWL
25
30
40
ns
tsu(WRH)
W-Iow setup time before RAS high
tRWL
25
30
40
ns
tCAH
20
20
25
ns
tRAH
15
15
15
ns
tAR
70
80
100
ns
Column·address hold time after
th(CA)
th(RA)
CAS low (see Note 10)
Row·address hold time after RAS low
Column-address hold time after RAS low
th(RLCA)
(see Note 12)
th(D)
Data hold time after CAS low (see Note 10)
tDH
20
25
30
ns
th(RLD)
Data hold time after RAS low (see Note 12)
tDHR
70
85
110
ns
Continued next page.
NOTES:
5. Timing measurements are referenced to VIL max and VIH min.
6. All cycle times assume tt = 5 ns.
7. tc(P) > tw(CH) min + tw(CL) min + 2 tt.
8. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user's transition times, this may require
additional CAS low time [tw(CL)]'
9. In a read-modify-write cycle, td(RLWL) and tsu(WRH) mustbe observed. Depending onthe user's transition times, this may require
additional RAS low time [twiRL)].
10. Later of CAS or W in write operations.
11. Early write operation only.
12. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
TEXAS •
INSTRUMENTS
9-10
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
262,144·VJORD BY 4·811 DYr~AMIC
SMJ44C256
MEMORY
RAr~DOM·ACCESS
timing requirements over recommended supply voltage range and operating temperature range
(concluded)
ALT.
SMJ44C25G-10
SYMBOL
MIN
MAX
SMJ44C25G-12 SMJ44C25G-15
MIN
MAX
MIN
MAX
UNIT
th(CHrd)
Read hold time after CAS high (see Note 14)
tRCH
0
0
0
ns
th(RHrd)
Read hold time after RAS high (see Note 14)
tRRH
10
10
10
ns
th(CLW)
Write hold time after CAS low (see Note 11 )
tWCH
20
25
30
ns
th(RLW)
Write hold time after RAS low (see Note 12)
tWCR
75
90
105
ns
td(RLCH)
Delay time, RAS low to CAS high
tCSH
100
120
150
ns
td(CHRL)
Delay time, CAS high to RAS low
tCRP
0
0
0
ns
td(CLRH)
Delay time, CAS low to RAS high
tRSH
25
30
40
ns
td(CLWL)
Delay time, CAS low to W low (see Note 15)
tCWD
70
80
90
ns
tRCD
30
75
30
90
30
110
ns
tRAD
20
55
20
65
25
80
ns
Delay time, RAS low to CAS low
td(RLCL)
(see Note 13)
Delay time, RAS low to column address
td(RLCA)
(see Note 13)
td(CARH)
Delay time, column address to RAS high
tRAL
45
55
70
ns
td(CACH)
Delay time, column address to CAS high
tCAL
45
55
70
ns
td(RLWL)
Delay time, RAS low to W low (see Note 15)
tRWD
150
170
200
ns
tAWD
95
105
120
ns
tGDD
25
30
40
ns
tGSR
25
30
40
ns
tCHR
25
25
30
ns
tCSR
10
10
15
ns
tRPC
0
0
0
ns
Delay ti~e, column address to W low
td(CAWL)
(see Note 15)
td(GHD)
Delay time, G high before data at DQ
td(GLRH)
Delay time, G low to RAS high
Delay time, RAS low to
td(RLCH)R
CAS high (see Note 16)
Delay time, CAS low to
td(CLRL)R
RAS low (see Note 1 6)
Delay time, RAS high to
td(RHCL)R
Refresh time interval
trf
NOTES:
CAS low (see Note 16)
11.
12.
13.
14.
15.
16.
17.
8
tREF
8
8
ms
Early write operation only.
The minimum value is measured when !d(RLCL) is set to td(RLCL) min as a reference.
Maximum value specified only to guarantee access time.
Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
Read-modify-write operation only.
CAS-before-RAS refresh only.
System transition times (rise and fall) are to be a minimum of 3 ns and a maximum of 50 ns.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
9-11
SMJ44C256
262,144-WORD BY 4-B11 DYNAMIC RANDOM·ACCESS MEMORY
PARAMETER MEASUREMENT INFORMATION
1.31 V
VCC = 5 V
OUTPUT - l R L = 218
UNDER
TEST
1
Cl
n
= 80 pF
R1 = 828
n
OUTPUT
UNDER------·
TEST
R2 = 295
CL = 80 pF
n
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
FIGURE 1. LOAD CIRCUITS FOR TIMING PARAMETERS
read cycle timing
I·
I
tc(rd)
--~:t
tt ~
1':
twiRl!
!--
I I~. td(RLCL)
I
I I
::
•
•
N
I
I·
. ._______ ~::
~
tw(RH)--J
I
t-t-t- td(CHRL)-------fI
...--~I-+I---------_.....
l{::
\1
I I
'I
'----I ;..1-......,.....'+1---tw(CH)------.--t1
I I I I
I I 'I
•
I
.
t-:- tsu(RA)
I
----I, l---
r----
td(CLRH)
----.
td(RLCH)
• ,
r---tw(Cl) - I
I I
I
I I
I ,• td(RLCA) , 1
, I
:• I t::;u(CA)
th(RA) --:.J I-I·
I td(CACH)
--,
·1
,
1 I td(CARH)
~~;h(RLCA)~
I
VIL
II
• I
I I
~ COl~H+:~i~I§Z'§9(\----_----::
~
~
w 2NoE{AHWI
i i i ~~o}X~H~
..................
........
AO-A8
I
I
,
~
'-IooI.lIo~I
I
I
DO,-
D04
:
~
I I
I
,
I.
,-
ta(CA)
.
t-----t-th(RHrd)
• 1 thlCHrd)
.:,
t---ta(C)-----, I· ,
•
(rNOTE
HI-Z
I
t
\.,_1~ _ ~
I
I-
I
I I
I- ,
th(CA)
I
tsu(rd) --,
I
ta(R)
.. I
I---ta(G)~
I
V,H
-VIL
-
I
NOTE
VALID
.J.
18
I
I
I-
VOL
I
I
I
r----td(GLRH)-----i
'
--Jl
r
'\J\",'_ _ _ _ _ _ _ _ _ _ _ _
---------
Output may go from high impedance to an invalid data state prior to the specified access time.
TEXAS
.J./}
INSTRUMENTS
9-12
VOH
}\)-_ _ _ _ __
I I
"""----+-1 tdis(G)
1 .
NOTE 18:
.. I
tdis(CH)
I
PO::' T OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
::~
SMJ44C256
262,144-WORD BY 4-B11 DYNAMIC RANDOM-ACCESS MEMORY
early write cycle timing
~I-------------------------tcIW)------------------------~-~1
N
Ii
il
~
I-l-----tw'Rl)------l-0'
{
..
,I
_ 1..
----tw(RHI-----i\
~------------------------------~
I.
r-tt
td(RlCl)
I :-
4
,
I
I
t
----i _
td(ClRH)
tw(Cl)
tltd}RlCHI
SUIRA,'
I.
0II .I
I
,
1-o11t-,- - -
-, ;
td(CACH)
Itd(CARH)
t----t tsu(CA)
•
• ,
~-----
td(CHRl) - - -..
...;1
1\
!
Vil
~ ~~~----twICH)-----~
VIH
" - - - Vil.
-l,
I
,
,
.. ,
,
,
,
, . - - - - - - - - - - - - - - - - - - - - - - - VIH
AO-A8
" - - - - - - - - - - - - - - - - - - - - - - - Vil
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
9-13
SMJ44C256
262, 144·WORDBY 4·BIT DYNAMIC RANDOM·ACCESS
M~MORY
write cycle timing
;--------------tc(WI------------<--i1
---------tw(RL)----------t-1
I
~___________________J1
1----- t
d(CLRH)
1 I
- - _ <.....
I
---------ll
L ::
I
t---tw(RH)~
ijtd(CHRL)---t
!
tW(CL'----~i fl'
1\
'-----------/!
I ,..1·~I~--tw(CH)---<-.-.j1
I•
td(CARH)
!•
td(CACH)
I ~I
t---+--th(RLCA)
AO-AS
•
.
I
-I
I
:
I
I
-r ~tsu(WCH)
t-------1
.
NOTE10
I•
I
tsu(WRHI
I
I
•
rt7"t7"'r:~':T"rJ"~~7"f7"~~~':T"rJ"~"t7' VIH
"",,,,,,,,,,,... I
Later of CAS or Win write operation.
-I/}
TEXAS
INSTRUMENTS
9-14
VIL
COlUM~ ~HN:{~AH_,---_ :::
th(CA)
NOTE 1 0:
VIH
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
SMJ44C256
262, 144·~JORD BY 4·811 DVfJAMIC RArJDOM·ACCESS MEMORY
read-write/read-modify-write cycle timing
I-
Ic(rdW)
I IRAS
!\tI--
if"
II
III
~ I
r- IdlRlCA).J
1
,
IhIRA) ~
~
I
Lftsu(RA)
I·
i
I
001·
004
I,·
I
N
I
if'
I I
I
, ....- - - - - - - - - - - . . I
,
C?l:UMN
I
Vil
I
I
~
I,
I
I
I 1001.--,,;--- Iw(CH)------.·-r1
I
Ii
th(RlCA) I
•I
,.
V'H
_I
t--- Iw(RH)~
I rt-Id(CHRl)------i
Iw(CL)
r----tlsu(CA)
VIH
Vil
i '
I
I
~Hi! g~R:~,--__
I ·~ tsu(WCH) ---i9,,
•
:IIHl
thlCA) I i---ttd(CAWl)-----'
tsu(rd)!_
I
§}Ri'rW:W' i
,•
,
•
!
AOA. 2M R~W]@t
,
,
,
I
I
II
I
I --ld(RlCl)-----J
i
L
• I
'l
I ~
I .-
--I
w
12
IwlRl)
-I
1--- tsu(WRH)----i
l-td(ClWl)~ ~tW(WL)---I
N
1
I td(RlWl)
I
~HHH~ :::
-, ,.
thlD)
t--- tsu(O) ----1
I
-I
!
VALID OUT
_ _ _ _ _JO
~~~~~~~~~~~
I
I
---f
I~
I-- ta(C)
r-
,
r--ta(CA)-i
t-a1----ta(R)
-,
G -------,.xta(G)~
.1 tdis(G)
I
'\..~~~~~
VlliVOl
:
I
td(GHO)--,
/ ' " - - - - - - - - - - - - - - - - - VIH
.
Vil
TEXAS
-I.!}
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
9-15
SMJ44C256
262. 144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
enhanced page-mode read cycle timing
N. .
tw(RH)
--t---1
·-----------tWIRL)P-----------.~
I "'"I- - - - - - - - - - - - - - - - - - - - - - - - - - . ; 1 1
1
I
1.....- - -
I I
I I1
I I
td(RLCL)-----4,,~'
~ I
I I..
I
I I-t...l
tw(CL),-----r
II
I
I
"
1
I I
I I
I 1
1
I
tdIRLCH)
1
w(CH)
f\\l Yr
I
I
I
•
tsu(RA)
I
r-- thIRA)
r-
,I
"I
I
I' I
I I
\\l Jf
II
tc(P)
1
I--
td(CLRH)-----'
I
I I
IlL.th(RLCA)
I-I
I
I td(CACH)-1 I
. __ I
I I
1
I
I
Ir----il tsu(CA). 1
1
'-----I
1 ' - - - - - - - - td(CARH) I
~ I
I
~ t-" th(CA)
I
I
I
VIL
1
td(CHRL)--,
1
I I
I 1
I I
II
•I 1
I
/'V'I~~~~~~
AO-AS
COLUMN
•
tHXJOlXI" I
'£iXt I
td(RLCA)
w
001004
tsulrd)
-1
I
'\a.o.coD.£~~~~~ VIL
1
I
I
1 : - - - th(C~rd)--1
I
I
!..
•:
-I
th(RHrd)
'------I
r----+-
'
..." - - - - ta(G) - - -...·-41
~_I _ _ _ _ _
VOH
VOL
tdis(G)
1
---J
NOTES:
1S. Output may go from high impedance to an invalid data state prior to the specified access time.
19. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
20. Access time is ta(CP) or ta(CA) dependent.
TEXAS •
INSTRUMENTS
9-16
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
SMJ44C256
262,144-\-JORD BY 4-B11 DVrJArJllC RArJDOM-ACCESS MEMORY
enhanced page-mode write cycle timing
I •
--; tw(RH)r-• I I
I
tw(Rl)P
~VIH
,
II
I I1
td(RLCH)
I.
tw(CL)
I I
tc(P)
I
t\ \l k
!!
I I
tsu(CA)--t
t.....= I
I
'
I
th(RLCA)
I I~
I
I
I t - - th(RA)
I I
th(CA) I
',"IRAI
I I
I
I
1-
---!
AO-AB
Hi'r- tw(CH)~
"I
tdIRLCL)
:x
i
l - - td(RlCA)--J
!- l
tsu(WCH)
I
I a.-- tw(Wl) ~
~r"'r7"'I:~~;;;:;~~m~;1 th(RLW) -=,-1
. i
,,,,v,,n...
1
-jl
I
I
I
1.1
- .
'I
•
r
-----4
i
I
Air---..;...,+!- - i
I I
I II
I
1-
I
I
I
COLUMN
VIL
1
td(CHRl)--i
I
. - - td(CACH) --I
I.
I
I
td(CARH) I
•I
II
I
!
td(CLRH)
\ \i
~: COL~MN :~
ROW
i
.. I
I
.11
I
)@(~{N:{{{Ri~ :::
tSU(WCH)--j!-1
a.--- tsu(WRH)----'
~~"""".........~,.....,...~~
I I,,,,,v,,,,,
I
.....- - - -........
1 th(D)
,......+I---th(D) - - _•..,1 NOTE 22
I!
NOTE 22
I
1--------th(RLD)-------·~1
I
1001. _ - - tsu(D) ----1
1
I
NOTE 22
1...-----tsu(D)
I
NOTE 22
DQ1DQ4
I
I
-
I
I
I
I
I
0
r i. .
~---.:..:.::;.:..=.-=-V-A-Ll-D-D-A-T-A-IN------~....
~,..O}....:,.,..T:....C......,:.... §2""""
~
I
A
VIH
VIL
~ t-- td(GHD)
I
/
NOTES:
21. A read cycle or a read-modify-write cycle can be intermixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
22. Referenced to CAS or W, whichever occurs last.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
9-17
SMJ44C256
262,144·WORD BY 4·81T DYNAMIC RANDOM·ACCESS MEMORY
enhanced page-mode read-modify-write cycle timing
twIRH)
RAS
---I
1
I ........- - - - - - - - - - - - - - - - - - - - - - - - - - - - .
I I
I---- tc(PM) ~
1
...._ - - td(CLRH)------4•.-!I
I I_
td(RLC':U
- I
1
I
I
I
~
I I· • I tw(CH)
td(CHRL) I. I
I· 1-I I
1
I
1 I
I r--- td(RLCL)
I
I
I
I I..
thIRA)
~
I
r--
tsu(RA)~ ~I
th(RLCA)
~ ~
t~I:1
1
.;
-I
!-
I I
1
tsu(CA)
~I
I
rr--rI I ~
I_
1.1 II
I
I
I
I
~ !
OQ1OQ4
1
I
1
I
~~~~~~~
I
I
I
------..xr--
NOTES:
I
td(CLWL)
I
I
.1
I
.. I
tsu(O)--t
I
1I
I•
I
• I ta(CA)
ta(R) ~
"'1.._ - -+-1 th(O)
ta(G) - ,
I
tdis(G)
!...__----4~
1
td(GHO)
-f
I
I·
I
~
:::
1
I
I
-I
tsu(WRH)
\{I. . ___~. . I.Io I. l o.o Uo. u. .I.l~_
NOTE 18
'-- ta(C) ,
1
1
I
tsu(WCH)
M-- ta(CP) I ------I
I
I
I
II
I
VIL
I
I
•I
)@§QQf~H~Hm
COLUMN
i iLY
t-+-
I
I
1
th(CA)
I ...-{I tw(WL) 1--1
I
I
I:
I
td(RLWL) .
1
Ii
I
I..
I
I
~~~~~~~~"
i
.1
0'-,..------------
18. Output may go from high impedance to an invalid data state prior to the specified access time.
23. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write cycle timing specifications
are not violated.
TEXAS •
INSTRUMENTS
9-18
'
1
.....-+-1_ __
1: \'\
~
td(CAWL)
,-
I
~
COLUMN
1
tsu'(rd)
I
tw(CL) --, I
f\\{
II
AD-AS
I-I
~"'~.-------------tW(RL)P------------~.~ VIH
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
SMJ44C256
262,144·WORD BY 4·B11 DYfJAMIC RAfJDOM·ACCESS MEMORY
RAS·only refresh timing
-w ~::~".,~'{y"~y~VIH
~~~Vll
G_:::
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
9-19
SMJ44C256
262, 144·WORD BY 4·B11 DYNAMIC RANDOM·ACCESS MEMORY
hidden refresh cycle (enhanced page mode)
r--- REFRESH
r--MEMORY CYCLE------1
I r--tw(RLli
RAS
fiI
I
I
11{1
I I
!
I I
f-
---t ~ tsu(RA)
r--tw(RLI--'
"'i
I
¥:
I
I
I ,I
I
r--twfRHI--j
i J:
I I
I
I
I
I
CYCLE -
'
'---REFRESH CYCLE-----t
r- tW(RHI~
~
V
I I
~\
I
tdlRLCHIR
tw(CL)
\~
I
,
~
--.J
I
I
i
I
I
.
r-- th(RHrdl
, TEXAS.
INSTRUMENTS
9-20
VIL
:
I
' ~~gm~
::
~ v
ICOLI
tsu(rdl~ I
VIH
I
•I
I
:
"III': i
ROW
I
v
I
thiRAI
I II h1 r--th(CAI
VII~
,vr-I.
I
I
H r-I
ii H tsu(C~1
I.
/
•
I
I
AD-A8
\
)\'
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
IH
V
I
I
I
IL
SMJ44C256
262,144·WORD BY 4·B11 DYNAMIC RANDOM·ACCESS MEMORY
automatic (CAS-before-RAS) refresh cycle timing
1-01
.
-
-
-
-
-
-
-
-
I .
-
-
tc(rd)I-----------l.1
1
rtW(RH)~ , 1 0 0 1 - - - - - - - t W ( R L ) - - - - - - - } 1 j,1_ _ _ _
RAS
i~~--------------..:;y
--'I"
VIH
VIL
--t I----
1
tt
~ td(RHCL)R ,I!------td(RLCH)R-------.l.1
I
CAS
a
a
I
td(CLRL)R
1
'\l~1_ _ _ _ _ _ _ _ _ _ _ _ _ _~}tr-------.-
VIH
VIL
OQ1- _ _ _ _ _ _ _ _ _ _ _ _ __
OQ4
HI-Z--------------
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
9-21
SMJ44C256
262,144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
TEXAS •
INSTRUMENTS
9-22
POST OFFICE BOX 1443 •
HOUSTON. TEXAS 77001
SMJ4C1024
1,048,576·811 DYNAMIC RANDOM·ACCESS MEMORY
DECEMBER 1988 -
•
•
•
•
1,048,576 x 1 Organization
JD PACKAGE
(TOP VIEW)
Single 5·V Supply (10% Tolerance)
"
100 ns
SMJ4C 1024-12
120 ns
SMJ4C 1024-1 5
150 ns
25 ns
VSS
Vii
Q
RAS
Performance Ranges:
ACCESS ACCESS ACCESS
TIME
TIME
TIME
ta(CA)
taIR)
talC)
(tCAA)
(tRAC)
(tCAC)
(MAX)
(MAX)
(MAX)
•
0
- 55°C to 125°C Operating Temperature
Range'
SMJ4C 1024-10
REVISED DECEMBER 1989
READ
OR
WRITE
CYCLE
(MIN)
45 ns
1S0 ns
30 ns
55 ns
220 ns
40 ns
70 ns
260 ns
SMJ4C1024-Enhanced Page Mode Operation
for Faster Memory Access
- Higher Data Bandwidth than Conventional
Page-Mode Parts
- Random Single-Bit Access Within a Row
with a Column Address
TF
A9
AD
A8
Al
A7
A2
A6
A3
A5
VCC
A4
HJ AND FQ PACKAGESt
HK PACKAGE
(TOP VIEW)
(TOP VIEW)
0
VSS
Vii
Q
CAS
RAS
TF
NC
NC
A9
SMJ44C256 - 256K x 4 Enhanced Page Mode
CAS-Before-RAS Refresh
o
Long Refresh Period ... 512-Cycle Refresh in
8 ms (Max)
0
W
VSS
Q
AO
A1
CAS
NC
A9
A8
A7
RAS
TF
NC
One of TI's CMOS Megabit DRAM Family Including:
•
CAS
AD
A8
A2
A6
Al
A7
A3
A2
A6
VCC
A5
A4
A3
A5
V CC --". _ _...1-" A4
•
3-State Unlatched Output
•
Low Power Dissipation
•
Texas Instruments EPIClM CMOS Process
•
All Inputs and Clocks Are TTL Compatible
•
Packaging Offered:
- 18-Pin 300-Mil Ceramic DIP
- 20-Lead Ceramic Surface Mount Package
,
(HJ Suffix)
- 20-Terminal Leadless Ceramic Surface
Mount Package (Fa Suffix)
- 20-Lead Flat Pack (HK Suffix)
tThe packages shown here are for pinout reference only.
The HJ and FQ packages are actually 75% of the length
of the JD package.
PIN NOMENCLATURE
o High-Reliability Class B Processing
description
AO-AS
Address Inputs
CAS
Column-Addrss Strobe
D
Data In
NC
No Connection
Q
Data Out
RAS
Row-Address Strobe
TF
Test Function
W
Write Enable
VCC
5-V Supply
VSS
Ground
The SMJ4C1 024 is a high-speed, 1,048,576-bit dynamic random-access memory organized as 1,048,576
words of one bit each. It employs state-of-the-art EPIClM (Enhanced Performance Implanted CMOS)
technology for high performance, reliability, and low power at a low cost.
These devices feature maximum RAS access times of 100 ns, 120 ns, and 1 50 ns. Maximum power
dissipation is as low as 385 mW operating and 16.5 mW standby on 100 ns devices.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA documents contain information
current as of publication date. Products conform
to sP!!cifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 2:t5012 • DALLAS, TEXAS 75265
Copyright © 1988, Texas Instruments Incorporated
SMJ4C1024
1,048,576·811 DYNAMIC RANDOM·ACCESS MEMORY
The EPICllII technology permits operation from a single 5-V supply, reducing system power supply and
decoupling requirements, and easing board layout. IDD peaks are ,140 mA typical, and a -1-V input voltage
undershoot can be tolerated, minimizing system noise considerations.
All inputs and outputs, including clocks, are compatible with Series 54 TTL. All addresses and data-in lines
are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The SMJ4C1 024 is offered in 18-pin ceramic dual-in-line (JD suffix) and 20-terminal ceramic lead less carrier,
20-pin leaded carrier, and 20-pin flatpack. They are guaranteed for operation from - 55°C to 125°C.
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while
selecting random column addresses. The time for row-address setup and hold and address multiplex is
thus eliminated. The maximum number of columns that may be accessed is determined by the maximum
RAS low time and the CAS page cycle time used. With minimum CAS page cycle time, all 1024 columns
specified by column addresses AO through A9 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the
falling edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling
edge of CAS latches the column addresses. This feature allows the SMJ4C1024 to operate at a higher
data bandwidth than conventional page-mode parts, si~ce data retrieval begins as soon as column address
is valid rather than when CAS transitions low. This performance improvement is referred to as "enhanced
page mode." Valid column address· may be presented immediately after row address hold time has been
satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained after talC) max
(access time from CAS low), if ta(CA) max (access time from column address) has been satisfied. In the
event that column addresses for the next page cycle are valid at the time CAS goes high, access time
for the next cycle is determined by the later occurrence of talC) or ta(CP) (acce·ss time from rising edge
of CAS.)
address (AO through A9)
Twenty address bits are required to decode 1 of 1,048,576 storage cell locations. Ten row-address bits
are set up on inputs AO through A9 and latched onto the chip by the row-address strobe (RAS). The
ten column-address bits are set up on pins AO through A9 and latched onto the chip by the column-address
strobe (CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar
to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used' as a
chip select activating the output buffer, as well as latching the address bits into the column-address buffer.
write enable (W)
The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects
the read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard
TTL circuits without a pull-up resistor. The data input is disabled when the read mode is selected. When
W goes low prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle,
permitting common 1/0 operation.
data in (0)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling
edge of CAS or W strobes data into the on-chip data latch. In an. early write cycle, W is brought low prior
to CAS and the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayedwrite or read-modify-write cycle, CAS will already be low, thus the data will be strobed in by W with setup
and hold times referenced to this signal.
TEXAS •
INSTRUMENTS
9-24
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
SMJ4C1024
1,048,576-811 DYNAMIC RANDOM-ACCESS MEMORY
data out (0)
The three-state output buffer provides direct TTL compatibility (no pull-up resistor required) with a fanout
of two Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance
(floating) state until CAS is brought low. In a read cycle the output becomes valid after the access time
interval ta{C) that begins with the negative transition of CAS as long as ta{R) and talCAI are satisfied.
The output becomes valid after the access time has elapsed and remains valid while CAS is low; CAS
going high returns it to a high-impedance state. In a delayed-write or read-modify-write cycle, the output
will follow the sequence for the read cycle.
refresh
A refresh operation must be performed at least once every eight milliseconds to retain data. This can be
achieved by strobing each of the 512 rows (AO-AS). A normal read or write cycle will refresh all bits in
each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
thus conserving power as the output buffer remains in the high-impedance state. Externally generated
addresses must be used for a RAS-only refresh. Hidden refresh may be performed while maintaining valid
data at the output pin. This is accomplished by holding CAS at VIL after a read operation and cycling RAS
after a specified precharge period, similar to a RAS-only refresh cycle.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS [see parameter td(CLRL)R] and
holding it low after RAS falls [see parameter td(RLCH)R]. For successive CAS-before-RAS refresh cycles,
CAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated
internally. The external address is also ignored during the hidden refresh cycles.
power up
To achieve proper device operation, an initial pause of 200 JLS followed by a minimum of eight initialization
cycles is required after full VCC level is achieved.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
9-25
SMJ4C1024
1,048,576·811 DYNAMIC RANDOM·ACCESS MEMORY
logic symbol t
RAM 1024K x 1
20D10/2100
AD (5)
A1 (6)
A2 (7)
(8)
A3
A4
A5
A6
A7
A8
A9
(10)
(11)
(12)
(13)
(14)
(15)
.
A
0
1,048,575
20D19/2109
C20[ROW]
G23/[REFRESH ROW]
24[PWR OWN]
C21[COL]
G24
23C22
A,22D
A\l
(17) Q
tThis symbol is in accordance with ANSI/lEEE Std 91-1984 and lEe Publication 617-12.
The pin numbers shown are for the 18-pin dual-in·line package.
,
functional block diagram
t
IN
t
~~ TIMING AND CONTROL
~
ROW
ADDRESS
BUFFERS
(10)
t7
----...
----....
. AD
[
A3
A4
~
I---tCOLUMN
ADDRESS
BUFFERS
(10)
~
h>
COLUMN DECODE
A5
256K ,1 ROW 1 256K
ARRA Y DECODE ARRA Y
A9
r+-
DATA
OUT
REG.
1 OF 8
~
~ SELECTION
SENSE AMPLIFIERS
AS
DATA
IN
~o
REG.
1/0
~
A7
~
~ BUFFERS
r----
A6
II
TEXAS •
INSTRUMENTS
9-26
7
SENSE AMPLIFIERS
A1
A2
.
256K.1 ROW 1 256K
ARRA Y DECODE ARRAY
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
~
~
Q
SMJ4C1024
1,048,576-811 DVPJAMIC RANDOM-ACCESS MEMORY
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
Voltage range on any pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V
Voltage range on Vee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1 V to 7 V
Short circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55 °e to 125 °e
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 °e to 150 0 e
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device relaibility.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
V
2.4
6.5
V
-1
0.8
VCC Supply voltage
VIH High-level input voltage
VIL
Low-level input voltage (see Note 2)
TA
Minimum operating free-air temperature
TC
Maximum operating case temperature
NOTE 2:
-55
UNIT
V
°c
125
°c
The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet
for logic voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
PARAMETER
VOH High-level output voltage
VOL Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
ICC1
Read or write cycle current
TEST CONDITIONS
10H = -5 mA
10L = 4.2 mA
SMJ4C1 024-1 0
MIN
2.4
VI = 0 V to 6.5 V, VCC = 5 V,
All other input pins = 0 V to VCC
Vo = 0 V to Vcc, Vcc = 5.5 V,
CAS high
Minimum cycle, VCC = 5.5 V
After 1 memory cycle,
ICC2 Standby current
ICC3 Average refresh current
ICC4 Average page current
MAX
RAS and CAS high, VIH = 2.4 V
Minimum cycle. VCC = 5.5 V,
RAS cycling, CAS high
tc(P) = minimum, V CC = 5.5 V,
RAS low, CAS cycling
TEXAS
SMJ4C1024-12 SMJ4C1024-15
MIN
MAX
2.4
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
±10
±10
±10
/-LA
±10
±10
±10
/-LA
70
60
55
mA
3
3
3
mA
65
55
50
mA
45
35
30
mA
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
9-27
SMJ4C1024
1,048,576-8IT DYNAMIC RANDOM-ACCESS MEMORY
capacitance over recommended supply range and operating temperature range, f
(see Note 3)
MIN
PARAMETERt
=
1 MHz
TYP MAX
UNIT
Ci(A)
Input capacitance, address inputs
6
pF
Ci(D)
Input capacitance, data input
5
pF
Ci(RC) Input capacitance, strobe inputs
Ci(W) Input capacitance, write-enable input
7
pF
8
pF
7
pF
Co
Output capacitance
tCapacitance is sampled only at initial design and after any major change.
NOTE 3: VCC equal to 5.0 V ± 0.5 V and the bias on the pins under test is 0.0 V
switching characteristics over recommended supply voltage range and operating temperature range
(see Figure 1)
ALT.
PARAMETER
SYMBOL
SMJ4C1 024-1 0
MIN
MAX
SMJ4C1024-12 SMJ4C1024-15
MIN
MAX
MIN
MAX
UNIT
talC)
Access time from CAS low
tCAC
25
30
40
ns
talCA)
Access time from column address
tCAA
45
55
70
ns
talR)
Access time from RAS low
tRAC
100
120
150
ns
talCP)
Access time from column precharge
tCAP
50
60
75
ns
35
ns
tdislCH) Output disable time after CAS high Isee Note 4)
NOTE 4:
tOFF
0
25
tdislCH) is specified when the output is no longer driven.
TEXAS •
INSTRUMENlS
9-28
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
0
30
0
1.048.576·8IT
SMJ4C1024
MEMORY
DYr~AMIC RAr~DOM·ACCESS
timing requirements over recommended supply voltage range and operating temperature range
ALT.
PARAMETER
SMJ4C1 024-1 0
MAX
SMJ4C1024-12 SMJ4C1024-15
UNIT
SYMBOL
MIN
tc(rd)
Read cycle time (see Note 6)
tRC
190
220
260
ns
tc(W)
Write cycle time
twc
190
220
260
ns
tc(rdW)
Read-write/read-modify-write cycle time
220
265
315
ns
tc(P)
Page-mode read or write cycle time (see Note 7)
tRWC
tpc
55
65
80
ns
tc(PM)
Page-mode read-modify-write cycle time
tpCM
85
110
135
ns
tw(CH)
Pulse duration, CAS high
tcp
10
tw(CL)
Pulse duration, CAS low (see Note 8)
tCAS
25
tw(RH)
Pulse duration, RAS high (precharge)
tRP
80
tRAS
100
tRASP
100 100,000
Non-page-mode pulse duration, RAS low
twIRL)
(see Note 9)
tw(RL)P
Page-mode pulse duration, RAS low (see Note 9)
tw(WL)
Write pulse duration
tsu(CA)
MIN
MAX
30
10,000
90
10,000
120
MAX
25
15
10,000
MIN
40
ns
10,000
10,000
120 100,000
ns
ns
100
10,000
ns
150100,000
ns
150
twp
15
20
25
ns
Column-address setup time before CAS low
tASC
3
3
3
ns
tsu(RA)
Row-address setup time before RAS low
tASR
0
0
0
ns
tsu(D)
Data setup time (see Note 10)
tDS
0
0
0
ns
tsu(rd)
Read setup time before CAS low
tRCS
0
0
0
ns
tsu(WCL) W-Iow setup time before CAS low (see Note 11)
twcs
0
0
0
ns
tsu(WCH) W-Iow setup time before CAS high
tCWL
25
30
40
ns
tsu(WRH) W-Iow setup time before RAS high
tRWL
25
30
40
ns
th(CLCA) Column-address hold time after CAS low
tCAH
20
20
25
ns
tRAH
15
15
20
ns
tAR
70
80
100
ns
ns
th(RA)
Row-address hold time after RAS low
Column-address hold time after RAS low
th(RLCA) (see Note 12)
th(D)
Data hold time (see Note 10)
th(RLD)
Data hold time after RAS low (see Note 12)
th(CHrd) Read hold time after CAS high (see Note 15)
tDH
20
25
30
tDHR
70
85
110
ns
tRCH
0
0
0
ns
th(RHrd) Read hold time after RAS high (see Note 15)
tRRH
10
10
10
ns
th(CLW) Write hold time after CAS low (see Note 11)
tWCH
20
25
30
ns
th(RLW) Write hold time after RAS low (see Note 12)
twCR
70
85
100
ns
td(RLCH) Delay time, RAS low to CAS high
tCSH
100
120
150
ns
td(CHRL) Delay time, CAS high to RAS low .
tCRP
0
0
0
ns
tRSH
25
30
40
ns
1d(CLWL) Delay time, CAS low to W low (see Note 13)
tCWD
25
40
50
td(RLCL) Delay time, RAS low to CAS low (see Note 14)
tRCD
28
75
28
90
33
110
ns
td(RLCA) Delay time, RAS low to column address (see Note 14)
tRAD
20
55
20
65
25
80
ns
td(CLRH)
Delay time, CAS low to RAS high
Continued next page.
NOTES:
5. Timing measurements in this table are referenced to VIL max
and VIH min.
6. All cycle times assume tt = 5 ns.
7. To guarantee tc(P) min, ta(CAI must be observed.
8. In a read-modify-write cycle, td(CLWL) and tsu(WCH)
must be observed.
9. In a read-modify-write cycle, td(RLWL) and tsu(WRH)
must be observed.
ns
10. Before the later of CAS or W in write operations.
11. Early write operation only.
12. The minimum value is measured when td(RLCL) is set to
td(RLCL) min as a reference.
13. Read-modify-write operation only.
14. Maximum value specified only to guarantee access time.
15. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
9-29
SMJ4C1024
1,048,576·8IT DYNAMIC RANDOM·ACCESS MEMORY
timing requirements over recommended supply voltage range and operating temperature range (concluded)
ALT.
PARAMETER
SYMBOL
SMJ4C1 024-1 0
MIN
MAX
SMJ4C1024-12 SMJ4C1024-15
MIN
MAX
MIN
MAX
UNIT
td(CARH)
Delay time, column address to RAS high
tRAL
45
55
70
ns
td(CACH)
Delay time, column address to CAS high
tCAL
45
55
70
ns
Delay time, RAS low to W low (see Note 13)
tRWD
100
130
160
ns
tAWD
45
65
80
ns
td(RLCH)R Delay time, RAS low to CAS high, (see Note 16)
tCHR
25
25
30
ns
td(CLRLlR Delay time, CAS low to RAS low, (see Note 16)
tCSR
10
10
15
ns
Delay time, RAS high to CAS low
tRPC
0
0
0
Refresh time interval
tREF
td(RLWL)
Delay time, column address to W low
td(CAWL)
td(RHCL)
trf
(see Note 13)
8
8
ns
8
NOTES: 13. Read-modify-write operation only.
16; CAS-before-RAS refresh only.
17. System transition times (rise and fall) for RAS and CAS are to be a minimum of 3 ns and a maximum of 50 ns.
PARAMETER MEASUREMENT INFORMATION
v
OUTPUT
UNDER TEST
~T
IOH/IOL
1.31 V
OUTPUT - f R L = 21 B 0
UNDER
TEST
CL ~ 80pF
(a) LOAD CIRCUIT
= 80 pF
(b) ALTERNATE LOAD CIRCUIT
TEXAS •
INSTRUMENTS
9-30
T"'-
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
ms
1,048,576·811
SMJ4C1024
MEMORY
DVr~AMIC RAr~DOM·ACCESS
read cycle timing
I.
tc(rd/
_-~I ~..
NE:::
RAS
.!
iI
CAS
td(RLCA)
i1't"rSU(RA)
I
I•
I"
I\-I
-!
~d(CACH)
I·
I
td(CARH)
;.
' j.
,
I ,
I
I
t--ta(C)-----; I.
ta(CA)
- I
1
I•
~o!oa!c1g~!
~
VIL
!
t----T-th(RHrd)
- I th(CHrd)
~{O~}~C}H~
tdis(CH)
[VALID.
I
ta(R)
. . .----
J.
I.
I
I"
+ - 1 - - - t w ( C H ) - - - -..~1
VIH
~~H~H~E~. . -_________ :::
I ~th(CLCA)
h-tsu(rd)--t I
I
----!~--HI-Z
~II
I I I
1
I
I -i I
J
;hIRLCAI: : ":
COLUM,N:
I
~td(CHRL)----i
I I
I
I
I
,
Q
r--
11 .
1\1..--------- v::
' - - - t (RH)--'
I
w
,
flI ll-t-III II
l.tsu(CA)~
"!
2M RO~ ~
:
'II
-I
v
It
i'l
I I
th(RA)-.:J
~
AD·A9
td(RLCL)----l
td(RLCH)
- I
t---tw(CL)-1
I
'
1:
I--- td(CLRH/ -----I
tt--l I
I
I
-
-I
twIRL)
-I
V,H
VIL
_I
I
]>-______
VOH
VOL
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
9-31
SMJ4C1024
1,048,576·811 DYNAMIC RANDOM·ACCESS MEMORY
early write cycle timing
!rA"
1-1. - - - - - - - - - - - - - t c ( W l - - - - - - - - - - - -....·--t1
~I ~
~
!1-I rI----tt
I
1
I,
1 I·
twiRl)
.
td(RLCLI
-Vt
tl'
I
td(RLCHI
th(RLCAI
1
I ....J4-------------~
I 1
_. l--j----tw(CHI
"1I
I
~
VaH
vaL
td(CACHI
• a • I
td(CARHI
tsu(CAI
1
1
1 a l l
ft:7',";'1'i:70"0'U'l::7'O"I~~~7'O"Ii:7\. , - - - - - - - - - - - vlH
i -i
:-----r I
I
I
"":_--td(CLRHI--_·"1
----..J /r------td(CHRLI - - - ·...1
tw(CLI
1 1I
----i
I I
~( WI
tsu(RAI
.
I
I
I•
I
I
1•
I
1
. th(RAl
i
~-.---tW(RHI---·~\'-_ _ _ VaL
1
AD-A9
" - - - - - - - - - - - - VaL
IN
~~~~~~~~~-~+------~~~~OC~~~OO~~~OO~~~OO~VIL
.....-;-1-i1-tw(WLI---..
--t1
I
i •
D
th(RLDI
L-- th(DI---l
.
~t'UID~=:TA
•
I
~~:::
VOH
Q
----------------HI-Z----------------VOL
TEXAS . .
INSTRUMENTS
9-32
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SMJ4C1024
1,048,576-811 DVrdAMIC RArdDOM-ACCESS MEMORY
write cycle timing
i•
I
-I
tc(W)
I.
-I
twiRL)
--~\d
RAS
~
:IfI
I
.i :
_
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..A
!I \ ....
.
1•
---' '-- tt
I
!--td(RLCL) - - ! .
,
II II I• II
tt
tsu(CA)
th(RA)~
• I
:
I-
• I
-}
td(RLCH)
--I H- tsu(RAI
I
.1
td(CLRH)
I
tw(CL)
-I 1
I
I
I
j •
I
I
j;;. . .---I!I--_______'"'\I,
td(CARH)
td(CACH)
-
!
I I • I
I
I I
I
I I
I
AO-A92MR~W ~ COLUM~ ~Hi~HE~
;:;J" ·=rt.U~:~~~~
W
YXWX;40~;m~
I
I
I
j-
o
h(RLW)
VIL
:::
~1"'rF....n-,.,.,.'"""'"""""""'f~~iIrTTl~~iR1l'7"'1"1E~~~:::
I---:-tw(WL)~
t---th(D) ---I
I, -
I
tsu(D) ---{
th(RLD)
~ofHfH~
VIH
I"'"
I"
th(RLCA)
I
I
t---- tw(RH)---,
~td(CHRL)-----t
J.,!
I
I
1\
II .t--T-I--tw(CH)-----I1
1-
I..
I•
I
I
! L I ' VIH
I
VIL
I
I
I
-~
VALID DATA
~H{{{\R1~ :::
tdis(CH)~
j
-------------~<~__N_O_T_V_A_Ll_D_~;~-----------------:::
Q .....
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
9-33
SMJ4C1024
1,048,576-81T DYNAMIC RANDOM-ACCESS MEMORY
read-write read-modify-write· cycle timing
~
TEXAS
INSTRUMENTS
9-34
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SMJ4C1024
1,048,576-011 DYfJAMIC RAfJDOM-ACCESS MEMORY
enhanced page-mode read cycle timing
VIH
VIL
I
AO-A9~
'.
I
VIH
w
VOH
Q
VOL
NOTES:
18. A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write
timing specifications are not violated.
19. Access time is ta(CP) or ta(CA) dependent.
20. Output may go from three-state to an invalid data state prior to the specified access time.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
9-35
SMJ4C1024
1.048.576·811 DYNAMIC RANDOM·ACCESS MEMORY
enhanced page-mode write cycle timing
twlRHI--;
1.....------------twIRlIP-------~-----.l.I 1
~l
r--
1
!\.~~-------------------------------------------------------.j.III~!L
I
RAS
\.....-----tdIRLCHI - - - -.....-11
1
I"
twlCll
tdlRlCll
1
I..
.. I
1
I
tclPI
1
1 I"
1
t---r-tsulCAI
1 ..
thlRlCAI
rthlRAI ~.
I
TtsuIRAI·
II
1
I
VIH
1
Vil
• '---I tdiCHI' Rll----1
;..j. . . .- - - -
- 1 twlCHI
f\ '{ Y
!
-l
•
i----tdlclRHI--{
1
\ \l
I
1
1
/~--""'i-----:::
1
_
tdlCACHI
tdICARHI· I
!
1
I
1
I
I
17'Tl~7-n-n-n"r'J"T""",~
VIH
ROW
AO-A9
1
I
r-- tdiRlCAI----:
1
r--+---~twIWll
I~~~~~~~~~~~~----~~~~~~~~~~~~--~~~~~~~~~~Vll
1
1
1 :
I
I"
!---thIDI--t-NOTE 21
thlDI
-I NOTE 21
!.....-------LI-thIRlDI -------1_.-11
jr-..---tsuIDI
!
•
1 NOTE 22
1.----tsuIDI----~!L.-.NOTE 22
...
I
1
1
.
o ~-------------V-A-l-ID--DA-T-A--IN-------------~,.,T"r7'''flOf'T.~I''''r~.,,·irrTno~-n:~i"'E;rrno»"r7'VVIH
IH
VOH
a --------------------------------
HI-Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Val
NOTES:
21. A read cycle or a read-modify-write cycle can be intermixed with write cycles as long as read and read-modify-write timing
specifications are not violated.
W. whichever occurs last.
22. Referenced to CAS or
TEXAS •
INSTRUMENTS
9-36
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SMJ4C1024
1,048,576-011 DYNAMIC RANDOM-ACCESS MEMORY
enhanced page-mode read-modify-write cycle timing
o
1
I-
~taICA)
~----taIR)
Q
------HI-Z
• 1 talC)
---I-I
......---·-+-1 tdislCH)
1
......- - - t a I C P ) - - - - i
I
NOTE 24 (~{"'I-V-;-~-~""')
NOTE 24
<{
1
VALID
OUT
NOTES:
VOH
}-I
.VOL
23. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications
are not violated.
24. Output may go from three-state to an invalid data state prior to the specified access time.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
9-37
SMJ4C1024
1,048;576·8IT DYNAMIC RANDOM·ACCESS MEMORY
RAS only refresh timing
I..
!
tc(rd) - - - - -..
""1j
r-tw(RL)~
RAS------------------------------~I\i
-----------1\
Jif~1
I
VIH
VIL
tt--J
'--
~I
i---tw(RH)---t
VIH
VIL
VIH
ROW
VIL
w.:,:
VOH
Q
------------------------------HI-Z -----------------------------------VOL
TEXAS •
INSTRUMENTS
9-38
POST uFFICE BOX 225012 • DALLAS. TEXAS 75265
1,048,576·81T
DY~JAMIC
SMJ4C1024
RANDOM·ACCESS MEMORY
hidden refresh cycle
I - - - REFRESH CYCLE----I
I - - - MEMORY CYCLE ----t
t--- REFRESH CYCLE--1
,
,
RAS
~tw(RH)~
I--tw(RL)---i
~
'{
,
,
~tw(RH)~
Y
, rtW(RL)--i
JtT
,
,
I
\
,
,
'.
I
"
,
I
1--,
"
"
'th(CLCA)~
H-tr(R~)
--I .-.- tsu(RA) '"
I'
--r
VIH
VIL
I--
r---------1r
.,
,
I
r-
I
\
,
,
I
VIH
VIL
I
, I --; H-+tsU!CA)
+{
I
L;
tw(CL)
" til
,,
,
'I
,
td(RLCH)R
,
, ,
,
I~
I
I
I
I
AOA9~~:I,:
"
tsu(rd)
I
!~
I
I
:.1 I ---t
I
r-th(RHrd)
D~D~~~'VIH
,
I --f
'1--'" .:
,
Q
~~VIL
I
I-- talC)
ta(CA)
tdis(CH)--I
ta(R) ----,
------~(
VALID DATA
TEXAS
::
~
r :::
!
~
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265
9·39
SMJ4C1024
1,048,576·BIT DYNAMIC RANDOM·ACCESS MEMORY
automatic (CAS-before-RAS) refresh timing
i
I-I------------tc(rdl------------..;r
~ tw(RHI---'
RAS-A
I
I
~
,
. - - - - - - t w ( R L I - - - - - - -r.,
...
,
Y
y,-____
N
I . ! td(CLRLIR
\J.
L.- td(RHCLl"
--i
,
I
,
, _ _ _ _ VIH
.t-----td(RLCHIR---...........1,
I""j
f-tt
...o.-_ _ _ : : :
Q -------------- HI-Z--------------
VOL
TEXAS
~
INSTRUMENTS
9-40
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
SMJ44100
4 194304·WORD BY 1 BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040 -
• MIL-STD-BB3C, Class B, High-Reliability
Processing
JD Package
(Top View)
• Military Temperature Range ... - 55°C to
125°C
D
VSS
Q
IN
READ
RAS
Al0
AO
Al
A2
A3
TIME
TIME
TIME
OR WRITE
VCC
(tRAC>
(MAX)
(tCAC)
(MAX)
(tAA)
CYCLE
(MAX)
(MIN)
SMJ441 00-80
80 ns
20 ns
40 ns
150 ns
SMJ441 00-1 0
100 ns
25 ns
50 ns
180 ns
SMJ44100-12
120 ns
30 ns
55 ns
210 ns
• Organization ... 4194304 x 1
• Single 5-V Power Supply (±10% Tolerance)
• Performance Ranges:
ACCESS ACCESS ACCESS
JANUARY 1991
CAS
A9
A8
A7
A6
AS
A4
HR Package
(Top View)
HM and CSOJ Packages
(Top View)
D
• Enhanced Page Mode Operation for Faster
Memory Access
......: Higher Data Bandwidth than
Conventional Page-Mode Parts
- Random Single-Bit Access Within a Row
With a Column Address
IN
VSS
Q
RAS
NC
Al0
CAS
NC
A9
A8
A7
A6
AS
A4
AO
A1
A2
A3
• CAS-Before-RAS Refresh
• Long Refresh Period ...
1024-Cycle Refresh in 16 ms (Max)
VCC
• 3-State Unlatched Output
D
IN
RAS
NC
Al0
AO
Al
A2
A3
VCC
VSS
Q
CAS
NC
A9
A8
A7
A6
AS
A4
Z
0
~
:aE
a::
0
U.
Z
W
• Low Power Dissipation
(J
PIN NOMENCLATURE
AO-Al0
CAS
D
NC
• Texas Instruments EPIC ™ CMOS Process
• All Inputs/Outputs and Clocks are TTL
Compatible
Q
• Packaging Options:
- 400 mil 20/26-Leadless Ceramic SOLCC
(HM Suffix)
- 1B-Pin, 400 mil Ceramic DIP (JD Suffix)
- 20-Pin, Ceramic FLATPACK (HR Suffix)
- 20-Pin, Ceramic CSOJ
- Additional Package Options Planned
RAS
W
VCC
VSS
Z
Address Inputs
Column-Address Strobe
Data In
No Connection
Data Out
Row-Address Strobe
Write Enable
5-V Supply
Ground
~
C
«
description
The SMJ441 00 series are high-speed 4 194 304-bit dynamic random-access memories, organized as 4 194304
words of one bit each. They employ state-of-the-art EPIC™ (Enhanced Process Implanted CMOS) technology
for high performance, reliability, and low power operation.
The SMJ441 00 features maximum row access time of 80 ns, 100 ns, and 120 ns. Maximum power dissipation
is as low as 385 mW operating and 22 mW standby..
EPIC is a trademark of Texas Instruments Incorporated.
Copyright © 1991. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
9-41
SMJ44100
4 194 304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040-JANUARY 1991
All inputs and outputs, including clocks, are compatible with Series 54 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The SMJ44100 is offered in a 400 mil 20/26-leadless ceramic surface mount SOlCC package (HM Suffix),
18-pin ceramic dual-in-Iine package (JD Suffix), 20-pin ceramic flatpack (HR Suffix) and a 20-pin leaded ceramic
chip carrier (CSOJ). All packages are guaranteed for operation from - 55°C to 125°C.
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is thus eliminated.
The maximum number of columns that may be accessed is determined by the maximum RAS low time and the
CAS page cycle time used. With minimum CAS page cycle time, all 1024 columns specified by column
addresses AO through A9 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the SMJ441 00 to operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as column address is valid rather than when
CAS transitions low. This performance improvement is referred to as enhanced page mode. Valid column
address may be presented immediately after row address hold time has been satisfied, ,usually well in advance
of the falling edge of CAS. In this case, data is obtained after tCAC max (access time from CAS low), if tAA max
(access time from column address) has been satisfied. In the event that column addresses for the next cycle
are valid at the time CAS goes high, access timeforthe next cycle is determined by the later occurrence of tCAC
or tCPA (access time from rising edge of CAS).
address (AO'through A10)
Twenty-two address bits are required to decode 1 of 4 194 304 storage cell locations. Eleven row-address bits
are set up on inputs AO through A 10 and latched onto the Chip by the row-address strobe (RAS). The eleven
column-address bits are set up on pins AO through A 10 and latched onto the chip by the column-address strobe
(CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip
enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select activating
the output buffer, as well as latching the address bits into the column-address buffer.
write enable
(W)
The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driv~n from standard TTL
circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low
priorto CAS (early write), data out will remain in the high-impedance state forthe entire cycle permitting common
I/O operation.
data in (0)
Data is written during a write or read-write cycle. Depending on the mode of operation, the falling edge of CAS
or W strobes data into the on-chip data latch. In an early write cycle, W is brought low prior to CAS and the data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-write cycle,
CAS will already be low, thus the data will be strobed in by W with setup and hold times referenced to this signal.
TEXAS ~
INSlRUMENTS
9-42
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
SMJ44100
4 194 304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040 -
JANUARY 1991
data out (0)
The three-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS is brought low. In a read cycle the output becomes valid after the access time interval tCAC that begins
with the negative transition of CAS as long as tRAC and tAA are satisfied. The output becomes valid after the
access time has elapsed and remains valid while CAS is low; CAS going high returns it to a high-impedance
state. In a delayed-write or read-write cycle, the output will follow the sequence for the read cycle.
refresh
A refresh operation must be performed at least once every sixteen milliseconds to retain data. This can be
achieved bystrobing each of the1 024 rows (AO-A9). A normal read or write cycle will refresh all bits in each row
that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, thus conserving
power as the output buffer remains in the high-impedance state. Externally generated addresses must be used
for a RAS-only refresh. Hidden refresh may be performed while maintaining valid data at the output pin. This
is accomplished by holding CAS atVIL after a read operation and cycling RAS after a specified precharge period,
similar to a RAS-only refr.esh cycle. The external address is ignored during the hidden refresh cycles.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS [see parameter tCSR] and holding it
low after RAS falls [see parametertCHR]. For successive CAS-before-RAS refresh cycles, CAS can remain low
while cycling RAS. The external address is ignored and the refresh address is generated internally.
power-up
To achieve proper device operation, an initial pause of 200 fls followed by a minimum of eight initialization cycles
is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
test mode
An industry standard Design For Test (OFT) mode is incorporated in the SMJ441 00. A CAS-before-RAS cycle
with W low (WCBR) cycle is used to enter test mode. In the test mode, data is written into and read from eight
sections of the array in parallel. Data is compared upon reading and if all bits are equal, the data out pin will go
high. If anyone bit is different, the data out pin will go low. Any combination read, write, read-write, or page-mode
can be used in test mode. The test mode function reduces test times by enabling the 4 meg DRAM to be tested
as if itwere a 512K DRAM, where row address 10, column address 10, and also column address 0 are not used.
A RAS only or CBR refresh cycle is used to exit the OFT mode.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-43
SMJ44100
4 194 304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040 -
JANUARY 1991
logic symbol t
RAM 4096K x 1
9
AO
30011/3100 "
10
11
A1
A2
12
A3
A4
14
> A __O_ _
15
16
17
18
AS
A6
A7
A8
A9
A10
4194303
22
5
./"-...
3
b
b:
r-....
24
2
1
w
o
30021/31010
C30(ROW)
G33/[REFRESH ROW)
34[PWR OWN]
C31[COL]
G34
&
P 33C32
~ 33,310
""
34EN
25
A'V
A320
a
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
The pin numbers shown are for the SOLCC(HM) package.
functional block diagram
•
AO
A1
•
•
•
A10
Column
Address
Buffers
~
~
Timing and Control
1
16
8
/
Column Decode
3
128KArray
128K Array
R
128KArray
I
16
Row
Address
Buffers
0
W
•
•
•
1Q
0
e
c
/
0
-
-
'-----
11--
~
Sense Amplifiers
-I-
L
•
•
•
~
I
-±
128KArray
••
•
16
3~
d
e
128KArray
128K Array
i'
10
/
TEXAS •
INSlRUMENTS
9-44
POST OFFICE BOX 1443
•
I/O
Buffers
1 of 16
Selection
HOUSTON. TEXAS 77001
1-
H!J.
In
Reg.
+-0
~
Out
Reg.
a
SMJ44100
4 194 304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040 - JANUARY 1991
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ..................................... :........... - 1 V to 7 V
Voltage range on Vee ............................................................... -1 V to 7 V
Short circuit output current ................................................................. 50 mA
Power dissipation ........................................................................... 1 W
Operating temperature ........................................................... - 55°C to 125°C
Storage temperature range ...................................................... - 65°C to 150°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this speCification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
V
VIH
High-level input voltage
2.4
6.5
V
-1
0.8
V
125
°c
°c
VIL
Low-level input voltage (see Note 2)
TA
Min operating temperature
TC
Max operating case temprature
-55
UNIT
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
ele.ctrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
SMJ44100-80
PARAMETER
TEST CONDITIONS
MIN
MAX
SMJ44100-10
MIN
MAX
2.4
SMJ44100-12
MIN
MAX
UNIT
V
2.4
VOH
High-level output voltage
VOL
LOW-level output voltage
10L = 4.2 rnA
0.4
0.4
0.4
V
II
Input current (leakage)
VI = 0 to 6.5 V. VCC = 5.5 V.
All other pins = 0 V to VCC
±10
±10
±10
fAA
10
Output current (leakage)
Vo = OtoVCC.
VCC = 5.5 V. CAS high
±10
z10
z10
IlA
ICC1
Read or write cycle current
(see Note 3)
Minimum cycle, VCC = 5.5 V
85
80
70
rnA
ICC2
Standby current
After 1 memory cycle,
RAS and CAS high, VIH = 2.4 V (TTL)
4
4
4
rnA
ICC3
Average refresh current
(RAS-only. or CSR)
(see Note 3)
Minimum cycle. VCC = 5.5 V.
RAS cycling, CAS high (RAS-only),
RAS low. after CAS low (CSR)
85
75
65
rnA
ICC4
Average page current
(see Note 4)
50
40
35
rnA
2.4
IOH =-5 rnA
K
= minimum. VCC = 5.5 V,
RAS low, CAS cycling
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS
-IJ1
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-45
z
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SMJ44100
4 194304-WORD 8Y 1-81T
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040 -
JANUARY 1991
capacitance over recommended ranges of. supply voltage and operating temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
7
pF
Ci(D)
Input capacitance, data inputs
7
pF
Ci(RC)
Input capacitance, strobe inputs
10
pF
Input capacitance, write-enable input
10
pF
Output capacitance
10
pF
.Ci(W)
Co
NOTE 5: VCC equal to 5 V ± 0.5 Vand the bias on pins under test is 0 V. Capacitance is sampled only at initial design and after any major change.
switching. characteristics over recommended ranges of supply voltage range and operating
temperature
SMJ441 00-80
PARAMETER
l>
o
~
z
n
m
-Z
MIN
MAX
SMJ441 00-1 0
MIN
MAX
SMJ44100-12
MIN
MAX
UNIT
tM
Access time from column-address
40
50
55
ns
tCAG
Access time from CAS low
20
25
30
ns
tCPA
Access time from column precharge
45
50
55
ns
tRAG
Access time from RAS low
80
100
120
ns
tOFF
Output disable time after CAS high (see Note 6)
20
25
30
ns
NOTE 6: tOFF is specified when the output is no longer driven. The output is disabled when CAS is brought high.
II
o
JJ
s:
-~
o
z
TEXAS ~
INSlRUMENTS
9-46
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ44100
4 194 304-WORD 8Y 1-81T
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040 -
JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating temperature
SMJ441 00-80
MAX
MIN
SMJ44100-10
MIN
MAX
SMJ44100-12
MIN
MAX
UNIT
tRC
Random read or write cycle (see Note 7)
150
180
210
ns
tRWC
Read-write cycle time
175
210
245
ns
tpc
Page-mode read or write cycle time (see Note 8)
50
60
65
ns
tpRWC
Page-mode read-write cycle time
70
85
95
tRASP
Page-mode pulse duration, RAS low (see Note 9)
80
100000
100
100000
120
ns
100000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 9)
80
10000
100
10000
120
10000
ns
tCAS
Pulse duration, CAS low (see Note 10)
20
10000
25
10000
30
10000
ns
tcp
Pulse duration, CAS high
10
10
15
ns
tRP
Pulse duration, RAS high (precharge)
60
70
80
ns
Write pulse duration
15
20
25
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
tDS
Data setup time (see Note 11)
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
ns
tCWL
W-Iow setup time before CAS high
20
25
30
ns
tRWL
W-Iow setup time before RAS high
20
25
30
ns
twcs
W-Iow setup time before CAS low
(Early write operation only)
0
0
0
ns
tWSR
W-high setup time (CAS-before-RAS refresh only)
10
10
10
ns
tCAH
Column-address hold time after CAS low
15
20
20
ns
tDHR
Data hold time after RAS low
60
75
90
ns
tDH
Data hold time (see Note11)
15
20
25
ns
.twP
tAR
Column address hold time after RAS low (see Note 13)
60
75
90
ns
tRAH
Row-address hold time after RAS low
10
15
15
ns
tRCH
Read hold time after CAS high (see Note 12)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 12)
0
0
0
ns
tWCH
Write hold time after CAS low
(Early write operation only)
15
20
25
ns
twCR
Write hold time after RAS low (see Note 10)
60
75
90
ns
tWHR
W high hold time (CAS-before-RAS refresh only)
10
10
10
ns
tAWD
Delay time, column address to W low
(Read-write operation only)
40
50
55
ns
Continued next page.
NOTES: 7. All cycle times assume tT = 5 ns.
8. To assure tpc min, tASC should be greater than or equal to tcp.
9. In a read-write cycle, tRWD and tRWL must be observed.
10. In a read-write cycle, tCWD and tCWL must be observed.
11. Referenced to the later of CAS or IN in write operations.
12. Either tRRH or tRCH must be satisfied for a read cycle.
13. The minimum value is measured when tRDC is set to tRCD min as a reference.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-47
z
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SMJ44100
4 194 304~WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040 -
JANUARY 1991
timing requirements over recommended supply voltage range and operating temperature range
(concluded)
SMJ44100-80
MIN
tCHR
»
c
~
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n
m
-z
"TI
o
:IJ
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
SMJ44100-10
MAX
MIN
20
MAX
20
SMJ44100-12
MIN
UNIT
MAX
25
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
ns
tCSH
Delay time, RAS low to CAS high
80
100
120
ns
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
ns
tCWD
Delay time, CAS low to W low
(Read-write operation only)
20
25
30
ns
tRAD
Delay time, RAS low to column-address (see Note 14)
15
tRAl
Delay time, column-address to RAS high
40
40
20
50
50
20
ns
65
55
ns
tCAl
Delay time, column-address to CAS high
40
tRCD
Delay time, RAS low to CAS low (see Note 14)
20
tRPC
Delay time, RAS high to CAS low
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
20
25
30
ns
tRWD
Delay time, RAS low to W low
(Read-write operation only)
80
100
120
ns
tCLZ
CAS to output in low Z (see Note 15)
tREF
Refresh time interval
IT
Transition time (see Note 16)
50
60
25
16
55
75
ns
25
ns
90
16
16
ms
NOTES: 14. Maximum value specified only to assure access time.
15. Valid data is presented at the output after all access times are satisfied. The output may go from three-state to an invalid data state
prior to the specified access times as the output is driven when CAS goes low.
16. Transition times (rise and fall) for RAS and CAS are to be minimum of 3 ns and maximum of 50 ns.
s:
~
o
PARAMETER MEASUREMENT INFORMATION
z
vcc = 5 V
1.31 V
~
-----=±-
R ,21BQ
L
Output Unde' rest
CL=100pF
Rl = 828
Output Under Test
T
CL = 100 pF
(a) Load Circuit
(b) Alternate Load Circuit
Figure 1. Load Circuits for Timing Parameters
TEXAS ."
INSlRUMENTS
9-48
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
Q
SMJ44100
4 194 304·WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040 -
JANUARY 1991
read cycle timing
z
o
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!d:
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I
)~____________
VOH
vOL
Z
W
U
Z
i
NOTE 15: Valid data is presented at the output after all access times are satisfied. The output may go from three-state to an invalid data state
prior to the specified access times as the output is driven when CAS goes low.
~
c
!~
tCSH
I
tRAH
tRSH
·I,A
1CI
....r - - - - - tCAS
tRCO
I I~
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1 I
1 I
I I~ I
I 1 I
I I .1
....
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tcp
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- - - - - - - - - ...!I
VIL
R~W ~ COlumn: ~222§0H~CM~""--_- :::
I~
I
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I·
tos
w
J..tf
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1
JIo1
.1 tOH
.1
~nn2gH~ ~."doab
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(see Note 15),
tCLZ
Q
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1 ~tCWL
1 I..
tRWL
.1
tOFF ~
---------------------------------------------~~L;____
N_o_tV_a_li_d__
-
i'4-
VOL
TEXAS ~
INSTRUMENTS
•
~
~
0:
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w
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~
~}~-----------------------------------VOH c
NOTE 15: Valid data is presented at the output after all access times are satisfied. The output may go from three-state to an invalid data state
prior to the specified access times as the output is driven when CAS goes low.
POST OFFICE BOX 1443
z
o
HOUSTON, TEXAS 77001
9-51
«
SMJ44100
4 194 304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040 -
JANUARY 1991
read-write cycle timing
»c
~
z
("')
m
-z
"o
JJ
3:
~
o
z
NOTE 15: Valid data is presented at the output after all access times are satisfied. The output may go from three-state to an invalid data state
prior to the specified access times as the output is driven when CAS goes low.
TEXAS •
INSlRUMENTS
9-52
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ44100
4 194 304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040 -
JANUARY 1991
enhanced page-mode read cycle timing
AO-A10
z
o
-
w
~ I~~~
I
III
I
W
1
"'
I
1
1
I
1'4-- tCAC - - . l
1
1l1li
I
1141l1li1------- tRAC
tCLZ
1l1li
I
W)V
1
I'~VIH
I
VIL
1
I
l0...i i11 - - - - - tCPA ----T-I-~~I
(see Note 17)
~I
tAA
~I
~I
1
I
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~tOFF~
I
I
~
~
VOH
Q-------------------------*XXXXXX
(see Note 15)
VOL
NOTES: 15. Valid data is presented at the output after all access times are satisfied. The output may go from three-state to an invalid data state
prior to the specified access times as the output is driven when CAS goes low.
17. Access time is tCPA or tM dependent.
Z
W
()
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«
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-53
SMJ44100
4 194 304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040-JANUARY 1991
enhanced page-mode write cycle timing (see Note 19)
»
·0
~
Z
(")
m
--nz
o
:II
:s:
~
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a -----------------HI-Z ----------------VOL
NOTES: 18. Referenced to CAS or W, whichever occurs last.
19. A read cycle or a read-write cycle can be intermixed with a write cycle as long as read and read-write timing specifications are not
violated.
TEXAS
l.!1
INSTRUMENlS
9-54
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
SMJ44100
4 194 304-WORD 8Y 1-81T
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040 -
JANUARY 1991
enhanced page-mode read-write cycle timing (see Note 20)
tRP~
14
RAS
N
1
.1
1
tRASP
i
I.
tCSH I
~ tRCO -----T+!
1
_I
--.:
1
1
~ tASR
-++l ~
1 I. I
tRAO
1
I
,
,.
I
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~tCAH ~
_
+~n
N'
:
I,.
1
,
,
,
1
1
H,.
tos
1
I.
tRAC
tCLZ
(see Note 15)
tOH
.:
1
,
1
,
1
I
*- tCWL -+I
I
1
1
1
.1
I.
1
1
1
tCLZ ~
tCPA
I
~ tOFF I
:--I
I
.1
1
1
VOH
Valid Out
VOL
NOTES: 15. Valid data is presented at the output after all access times are satisfied. The output may go from three-state to an invalid data state
prior to the specified access times as the output is driven when CAS goes low.
20. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Z
U
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A __O_ _
15
16
17
A5
A6
A7
1,048,575
18
A8
5
A9
20019/2109
r--...
4
C20[Row]
~
G23/[Refresh Row]
24[Power Down]
r--...
23
3
22
1
OQ1
2
OQ2
24
25
OQ3
OQ4
C21 [Column]
G24
-~
r
&
P>
23,210
r-..... G25
23C22
24,25EN
r
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1...
A,220
V' 26
A,Z26
~
~
~
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t This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publicati.on 617-12. The pinouts illustrated are for the SOlCC package.
functional block diagram
w
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AO
A1
•
··
A9
Column
Address
BuHers
•
•
~
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16
/
Column Decode
2
~
Sense Amplifiers
~
128K Array
128KArray
R
128KArray
16<
Row
Address
BuHers
~
1
0
•
••
10
0
e
c
/
0
128KArray
10
.,
L±
128K Array
•
••
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-
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Timing and Control
8
L
•
~
16
128K Array
TEXAS
•
~
~
In
Reg.
Data
Out
Reg.
4~
OQ1-OQ4
lJ1
INSTRUMENTS
POST OFFICE BOX 1443
I/O
BuHers
4 OF 16
Selection
2_
d
e
/
9-64
~r
HOUSTON, TEXAS 77001
SMJ44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041 -
JANUARY 1991
absolute maximum ratings over operating temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 1 V to 7 V
Voltage range on Vee ................................................................ - 1 V to 7 V
Short circuit output current ................................................................ 50 rnA
Power dissipation .......................................................................... 1 W
Operating temperature
. . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
Storage temperature range ...................................................... - 65°C to 150°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute·maximum·rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage (see Note 1)
4.5
5
5.5
VIH
High·level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-0.5
0.6
V
TA
Min Operating temperature
-55
TC
Max Operating case temperature
UNIT
V
°c
125
°c
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
.
SMJ44400-80
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
10H =-5 mA
VOL
Low-level output voltage
10L = 4.2 mA
II
Input current (leakage)
10
MIN
MAX
SMJ44400-10
MIN
MAX
2.4
2.4
SMJ44400-12
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
VI = 0 to 6.5 V, VCC = 5.5 V,
All other pins = 0 V to VCC
±10
±10
±10
J.!A
Output current (leakage)
Vo = OtoVCC,
VCC = 5.5 V, CAS high
±10
±10
±10
J.!A
ICC1
Read or write cycle current
(see Note 3)
Minimum cycle, VCC = 5.5 V
85
80
70
mA
ICC2
Standby current
After 1 memory cycle,
RAS and CAS high, VIH = 2.4 V
4
4
4
mA
ICC3
Average refresh current
(RAS-only, or CSR)
Minimum cycle, VCC = 5.5 V,
RAS cycling, CAS high (RAS only),
RAS low, after CAS low (CSR)
85
75
65
mA
ICC4
Average page current
(see Note 4)
tpc = minimum, VCC = 5.5 V,
RAS low, CAS cycling
50
40
35
mA
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS
-I!I
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
9-65
z
o
-
!;:
:a:
0:
o
LL
Z
W
(J
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SMJ44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041 -
JANUARY 1991
capacitance over recommended ranges of supply voltage and operating temperature, f
(see Note 5)
MIN
PARAMETER
TYP
=1 MHz
MAX
UNIT
7
pF
Input capacitance, strobe inputs
10
pF
Ci/Wl
Input capacitance, write-enable input
10
pF
Co
Output capacitance
10
pF
Ci(A)
Input capacitance, address inputs
Ci(RC)
NOTE 5: VCC equal to 5 V ± 0,5 V and the bias on pins under test is 0 V, Capacitance is sampled only at initial design and after any major change,
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
SMJ44400-ao
PARAMETER
l>
c
~
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(')
m
MIN
MAX
SMJ44400-10
MIN
MAX
SMJ44400-12
MIN
MAX
UNIT
tAA
Access time from column-address
40
50
55
ns
tCAC
Access time from CAS low
20
25
30
ns
tCPA
Access time from column precharge
45
50
55
ns
tRAC
Access time from RAS low
80
100
120
ns
tOEA
Access time from OE low
20
25
30
ns
tOFF
Output disable time after CAS high (see Note 6)
20
25
30
ns
tOEZ
Output disable time after OE high (see Note 6)
20
25
30
ns
NOTE 6: tOFF and tOEZ are specified when the output is no longer driven, The outputs are disabled by bringing either OE or CAS high,
-z
II
o
:IJ
:s:
~
o
z
TEXAS
.IJ1
INS1RUMENTS
9-66
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ44400
1 048 576-WORD 8Y 4-811
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041- JANUARY 1991
timIng requirements over recommended ranges of supply voltage and operating temperature
SMJ44400-80
MAX
MIN
SMJ44400-10
MIN
MAX
SMJ44400-12
MIN
MAX
UNIT
tRC
Random read or write cycle (see Note 7)
150
180
210
ns
tRWC
Read-write cycle time
205
245
285
ns
tpc
Page-mode read or write cycle time (see Note 8)
ns
tPRWC
Page-mode read-write cycle time
tRASP
Page-mode pulse duration, RAS low (see Note 9)
80
100000
100
100000
120
100000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 9)
80
10000
100
10000
120
10000
ns
tCAS
Pulse duration, CAS low (see Note 10)
20
10000
25
10000
30
10000
ns
tcp
Pulse duration, CAS high
10
10
15
tRP
Pulse duration, RAS high (precharge)
60
70
80
ns
twp
Write pulse duration
15
20
25
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
tDS
Data setup time (see Note 11)
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
ns
tCWL
W-Iow setup time before CAS high
20
25
30
ns
tRWL
W-Iow setup time before RAS high
20
25
30
ns
twcs
W-Iow setup time before CAS low
(Early write operation only)
0
0
0
ns
:E
tWSR
W-high setup time (CAS-before-RAS refresh only)
10
10
10
ns
tCAH
Column-address hold time after CAS low
15
20
20
ns
tDHR
Data hold time after RAS low
60
75
90
ns
o
LL
tDH
Data hold time (see Note 11)
15
20
25
ns
ns
50
60
65
100
120
135
ns
ns
tAR
Column-address hold time after RAS low (see Note 10)
60
75
90
tRAH
Row-address hold time after RAS low
10
15
15
ns
tRCH
Read hold time after C~S high (see Note 12)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 12)
0
0
0
ns
tWCH
Write hold time after CAS low
(Early write operation only)
15
20
25
ns
tWCR
Write hold time after RAS low (see Note 10)
60
75
90
ns
tWHR
W-high hold time (CAS-before-RAS refresh only)
10
10
10
ns
tAWD
Delay time, column-address to W low
(Read-write operation only)
70
80
90
ns
Continued next page.
NOTES: 7. All cycle times assume tT = 5 ns.
B. To guarantee tpc min, tASC should be greater than or equal to tcP.
D. In a read-write cycle, tRWD and tRWL must be observed.
10. In a read-write cycle, tCWD and tCWL must be observed.
11. Referenced to the later of CAS or Vi in write operations.
12. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-67
z
o
~
CC
Z
W
o
Z
~
c
«
SMJ44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041-JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating temperature
(concluded)
SMJ44400-10
SMJ44400-80
MIN
»c
~
z
(')
m
--nz
o
:tJ
3:
~
MAX
MIN
SMJ44400-12
MAX
MIN
MAX
UNIT
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
20
20
25
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
ns
tCSH
Delay time, RAS low to CAS high
80
100
120
ns
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
ns
tCWD
Delay time, CAS low to W low
(Read-write operation only)
50
60
70
ns
tOEH
OE command hold time
20
25
30
ns
tOED
OE to data delay
20
25
30
ns
tROH
RAS hold time referenced to OE
20
25
30
ns
tRAD
Delay time, RAS low to column-address (see Note 13)
15
tRAl
Delay time, column-address to RAS high
40
50
55
ns
tCAl
Delay time, column-address to CAS high
40
50
55
ns
20
40
20
tRCD
Delay time, RAS low to CAS low (see Note 13)
tRPC
Delay time, RAS high to CAS low
0
0
tRSH
Delay time, CAS low to RAS high
20
tRWD
Delay time, RAS low to W low
(Read-write operation only)
110
tCLZ
CAS to output in low Z (see Note 14)
tREF
Refresh time inteNal
tT
Transition time (see Note 15)
60
20
50
25
75
65
25
90
ns
ns
0
ns
25
30
ns
135
160
ns
16
16
16
ms
NOTES: 13. Maximum value specified only to guarantee access time.
14. Valid data is presented at the outputs after all access times are satisfied but may go from three-state to an invalid data state prior to
the specified access times as the outputs are driven when CAS goes low.
15. Transition times (rise and fall) for RAS and CAS are to be a minimum o,f 3 ns and a maximum of 50 ns.
o
z
PARAMETER MEASUREMENT INFORMATION
1.31 V
Vcc
~ "L=2t."
Output Unde. Test
R1 == 828 Q
~
C L =100 P
Output Under Test
FT
CL
=100 pF
(a) Load Circuit
(b) Alternate Load Circuit
Figure 1. Load Circuits for Timing Parameters
TEXAS •
INSlRUMENTS
9-68
=5V
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041-JANUARY 1991
read cycle timing
z
o
.~
:a:
a:
o
LL
Z
W
(J
Z
~
C
-H10Z-:::
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-89
SMJ27C128
131 072-BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS006C -
AUGUST 1986 -
REVISED JANUARY 1991
program cycle timing
114--.--- Verify ~
114
...- - - - Program - - -•• 1
AO-A13
~---------------A-dd-r-es-s-S~ta-b-le------------~~lK~________
Address __
1
1
:
N +1
1
+
,
~ tsu(A)
01-08
1
----c~
VIH
VIL
1
1+ th(A) -+t
In SI.bl.
~>----L----C~ D~~,~U'
~ tsU(O)'
!'
,
'...
]>--______
.:
VIHNOH
VILNOH
tdls
Vpp
Vpp
Vee
Vee
Vee
Vee
VIH
VIL
VIH
VIL
VIH
VIL
TEXAS
-III
INSTRUMENlS
9-90
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ27C256
262144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS005C -
•
Military Operating Temperature Range
... - 55°C to 125°C
•
MIL-STD-883C Class B
High-Reliabillity Processing
•
•
Organization ... 32K x 8
•
Pin Compatible With Existing 128K and
256K EPROMs
•
All Inputs/Outputs Fully TTL Compatible
•
Max Access/Min Cycle Times
SMJ27C256-15
150 ns
SMJ27C256-17
170 ns
SMJ27C256-20
200 ns
SMJ27C256-25
250 ns
SMJ27C256-30
300 ns
•
•
MAY 1986 -
REVISED JANUARY 1991
J Package
(Top View)
Vpp
A12
A7
Single 5-V Power Supply
A4
A3
A2
A1
AO
01
02
03
GND
1
Vee
A14
A13
A8
A9
A11
G
A10
E
08
07
06
05
04
HVCMOS Technology
PIN NOMENCLATURE
3-State Output Buffers
AO-A14
•
400 mV Guaranteed DC Noise Immunity With
Standard TTL Loads
•
Low Power Dissipation
- Active ... 138 mW Worst Case
- Standby ... 1.7 mW Worst Case
(CMOS Input Levels)
E
G
GND
01-08
Vee
Vpp
Address Inputs
ehip Enable/Power Down
Output Enable
Ground
Outputs
5-V Power Supply
Output Enable
description
The SMJ27C256 series are 262 144-bit, ultraviolet-light erasable, electrically programmable read-only
memories. These devices are fabricated using HVCMOS technology for high speed and simple interface with
MaS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 54 TTL circuits
without the use of external pullup resistors, and each output can drive one Series 54 TTL circuit without external
resistors. The data outputs are three-state for connecting multiple devices to a common bus. The SMJ27C256
is pin compatible with 28-pin 256K ROMs and EPROMs. They are offered in a 600 mil dual-in-line ceramic
package (J suffix) rated for operation from - 55°C to 125°C.
Since these EPROMs operate from a single 5-V supply (in the read mode), they are ideal for use in
microprocessor-based systems. One other 12-13 V supply is needed for programming, but all programming
signals are TTL level. These devices are programmable by either Fast or SNAP! Pulse programming algorithms.
The Fast programming algorithm uses a Vpp of 12.5 V and a Vee of 6 V for a nominal programming time of two
minutes. The SNAP! Pulse programming algorithm uses a Vpp of 13 V and a Vee of 6.5 V for a nominal
programming time of four seconds. For programming outside the system, existing EPROM programmers can
be used. Locations may be programmed singly, in blocks, or at random.
operation
There are seven modes of operation forthe SMJ27C256 listed in the following table. Read mode requires a
single 5-V supply. All inputs are TTL level except for Vpp during programming (12.5 V for Fast, or 13 V for SNAP!
Pulse) and 12 V on A9 for signature mode.
PRODUCTION DATA documents contain Information
current IS of publication date. Products conform to
specifications per the terms of Texas tnstruments
standard warranty. Production processing does not
necessarily Include testing of all parameters.
TEXAS
~
Copyright © 1991, Texas Instruments Incorporated
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-91
SMJ27C256
262 144-BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS005C -
MAY 1986 - REVISED JANUARY 1991
MODE
FUNCTION
(PINS)
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE
MODE
(20)
VIL
VIL
VIH
VIL
VIH
VIH
VIL
G
(22)
VIL
VIH
xt
VIH
VIL
X
VIL
Vpp
(1)
Vee
Vee
Vee
Vpp
Vpp
Vpp
Vee
Vee
(28)
Vee
Vee
Vee
Vee
Vee
Vee
Vee
A9
(24)
X
X
X
X
X
X
VHt
VHt
X
X
X
X
X
X
VIL
VIH
Data Out
HI-Z
HI-Z
Data In
Data Out
HI-Z
MFG
DEVleE
97
04
E
AD
(10)
01-08
(11-13,
15-19)
eODE
t X can be VIL or VIH.
t VH
= 12 V ± 0.5 V.
read/output disable
When the outputs of two or more SMJ27C256s are connected in parallel on the same bus, the output of
any particular device in the circuit can be read with no interference from the competing outputs of the other
devices. To read the output of the selected SMJ27C256, a low-level signal is applied to the E and G pins.
All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of
these pins. Output data is accessed at pins 01 through 08.
latch up immunity
Latchup immunity on the SMJ27C256 is a minimum of 250 mA on all inputs and outputs. This feature provides
latchup immunity beyond any potential transients at the P.C. board level when the EPROM is interfaced to
industry standard TTL or MOS logic devices. Input/output layout approach controls latchup without
compromising performance or packing density.
For more information see application report SMLA001; "Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family."
powerdown
Active Icc supply current can be reduced from 25 mA to 500 IAA (TTL-level inputs) or 300 IAA (CMOS-level inputs)
by applying a high TTL signal to the E pin. In this mode all outputs are in the high-impedance state.
erasure
Before programming, the SMJ27C256 is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 A). EPROM erasure before programming is necessary to assure
that all bits are in the logic 1 (high) state. Logic Os (lows) are programmed into the desired locations. A
programmed logic low can be erased only by ultraviolet Iight.The recommended minimum exposure dose
(UV intensity x exposure time) is 15 W·s/cm 2 . A typica112 mW/cm 2 , filterless UV lamp will erase the device
in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After erasure, all
bits are in the high state. It should be noted that normal ambient light contains the correct wavelength for
erasure. Therefore, when using the SMJ27C256, the window should be covered with an opaque label.
TEXAS ."
INSlRUMENTS
9-92
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ27C256
262144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS005C -
MAY 1986 -
REVISED JANUARY 1991
SNAP! Pulse programming
The 256K EPROM can be programmed using the TI SNAP! Pulse programming algorithm as illustrated by the
flowchart in Figure 1, which can reduce programming time to a nominal of. 4 seconds. Actual programming time
will vary as a function of the programmer used.
Data is presented in parallel (eight bits) on pins 01 to 08. Once addresses and data are stable, E is pulsed.
The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (f.ts) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-f.ts
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when Vpp = 13 V, Vee = 6.5 V, G = VIH and E = VIL' More than
one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified
with Vee = Vpp = 5 V.
fast programming
The 256K EPROM can be programmed using the Fast programming algorithm illustrated by the flowchart in
Figure 2. During Fast programming data is presented in parallel (eight bits) on pins 01 to 08. Once addresses
and data are stable, E is pulsed. The programming mode is achieved when Vpp = 12.5 V, Vee = 6 V, G =VIH
and E = VIL' More than one SMJ27C256 can be programmed when the devices are connected in parallel.
Locations can be programmed in any order.
Fast programming uses two types of programming pulses: Prime and Final. The length of the Prime pulse
is 1 millisecond; this pulse is applied X times. After each Prime pulse, the byte being programmed is
verified: If the correct data is read, the Final programming pulse is applied; if correct data is not read, an
additional 1 millisecond pulse is applied up to a maximum X of 25. The Final programming pulse is 3X
long. This sequence of programming and verification is performed at Vee = 6 V and Vpp = 12.5 V.
When the full Fast programming routine is complete, all bits are verified with Vee = Vpp = 5 V (see
Figure 2).
program inhibit
Programming may be inhibited by maintaining a high level input on the E pin.
program verify
Programmed bits may be verified with Vpp
= 12.5 V when.G =VIL, and E =VIH'
. signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 (pin 24) is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by AO (pin 10); i.e.,
AO = VIL accesses the manufacturer code, which is output on 01-08; AO = VIH accesses the device code, which
is output on 01-08. All other addresses must be held at VIL' Each byte possesses odd parity on bit 08. The
manufacturer code for these devices is 97, and the device code is 04.
TEXAS
-1!1
INSlRUMENlS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
9-93
SMJ27C256
262 144·BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS005C -
MAY 1986 - REVISED JANUARY 1991
T
Program
Mode
Increment Address
Interactive
Mode
No
Yes
Final
Verification
.~
Figure 1. SNAP! Pulse Programming Flowchart
TEXAS ~
INSlRUMENTS
9-94
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ27C256
262144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS005C -
MAY 1986 -
REVISED JANUARY 1991
Yes
Increment
Address
Figure 2. FAST Programming Flowchart
TEXAS . .
INSlRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-95
SMJ27C256
262 144-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMSOO:lC -
MAY 1986 -
REVISED JANUARY 1991
logic symbol t
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
E
o \ EPROM 32 768 x 8
10
9
8
7
6
5
.
A'V
A'V
A'V
A'V
A'V
A'V
A'V
A'V
4
3
25
24
21
23
2
26
27
A_O_
32767
20
22
L::".
I',.
11
12
13
15
16
17
18
19
01
02
03
04
05
06
07
08
14
[PWRDWN]
MEN
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. - 0.6 V to 7 V
Supply voltage range, Vpp (see Note 1) ............................................. - 0.6 V to 14 V
Input voltage range (see Note 1), All inputs except A9 ................................ - 0.6 V to 6.5 V
A9 ............................................... - 0.6 V to 13.5 V
Output voltage range (see Note 1) ............................................. - 0.6 V to Vee + 1 V
Minimum operating free-air temperature .................................................... - 55°C
Maximum operating case temperature ...................................................... 125°C
Storage temperature range ........................................................ - 65°C to 150°C
*Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation ofthe device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
TEXAS
~
INSTRUMENTS
9-96
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ27C256
262 144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS005C- MAY 1986- REVISED JANUARY 1991
recommended operating conditions
PARAMETER
Read mode (see Note 2)
Vee
Supply Voltage
Fast programming algorithm
SNAP! Pulse programming algorithm
Read mode (see Note 3)
Vpp
Supply Voltage
SNAP! Pulse programming algorithm
VIH
TIL
High-level input voltage (see Note 4)
VIL
Low-level input voltage (see Note 4)
TA
Operating free-air temperature
Te
Operating case temperature
NOM
MAX
4.5
5
5.5
V
5.75
6
6.25
V
6.25
6.5
6.75
V
Vee - 0.6
Fast programming algorithm
eMOS
TIL
Vee + 0.6
12
12.5
12.75
13
V
13
V
13.25
V
2
Vee+ 1
V
Vee - 0.2
Vee + 0.2
V
-0.5
0.8
GND - 0.2
eM OS
UNIT
MIN
GND + 0.2
-55
V
V
°e
125
°e
electrical characteristics over full ranges of operating conditions
PARAMETER
TEST CONDITIONS
MIN
TYpt
MAX
UNIT
V
VOH
High-level output voltage (see Note 4)
10H= -400!lA
VOL
Low-level output voltage (see Note 4)
10L = 2.1 mA
0.4
V
II
Input current (leakage) (see Note 4)
VI = Oto 5.5 V
±1
!lA
10
Output current (leakage)
Vo = OtoVee
IpP1
Vpp supply current
Vpp = Vee = 5.5 V
IpP2
Vpp supply current; (during program pulse)
(see Note 4)
Vpp = 13 V
lee1
Vee supply curent
(standby)
ITIL-input level
Vee supply current (active) (see Note 4)
lOS
Output short circuit current (see Note 5)
35
Vee = 5.5 V,
E = Vee
Vee = 5.5 V, E = VIL,
tcycle = minimum cycle time,
outputs open
±1
!lA
100
mA
50
!lA
500
Vee = 5.5 V, E = VIH
IeMOS-input level
lee2
2.4
rIA
300
10
25
mA
100
mA
t Typical values are at T A = 25°e and nominal voltages.
; This parameter has been characterized at 25°e and is not tested.
NOTES: 2. Vee must be applied before or atthe same time as Vpp and removed after or atthe same time as Vpp. The device must not be inserted
into or removed from the board when Vpp or Vee is applied.
3. Vpp can be connected to Vee directly (except in the program mode). Vee supply current in this case would be lee + Ipp.
4. Valid during programming mode also.
5. Vpp may be one diode drop below Vee. It may be connected to Vee. Also, Vee must be applied simultaneously or before Vpp
and be removed simultaneously or after Vpp.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
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9-97
SMJ27C256
262 144-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS005C -
MAY 1986 -
REVISED JANUARY 1991
capacitance over recommended ranges of supply voltage and operating free-air temperature,
1 MHzt
f
=
PARAMETER
Ci
Input capacitance
Co
Output capacitance
TEST CONDITIONS
MIN
TYP*
MAX
6
10
pF
10
14
pF
=0, f = 1 MHz
Vo =0, f = 1 MHz
VI
UNIT
t Capacitance measurements are made on a sample basis only.
* Typical values are at T A = 25°C and nominal voltages.
switching characteristics overfull ranges of recommended operating conditions (see Notes 6 and 7)
PARAMETER
'27C/PC256-15
TEST CONDITIONS
(SEE NOTES 6 AND 7)
MIN
'27C/PC256-17
MAX
MIN
MAX
UNIT
ta(A)
Access time from address
150
170
ns
ta(E)
Access time from chip enable
150
170
ns
70
70
ns
55
ns
tenlGl Output enable time from G
tdis
Output disable time from G or E,
whichever occurs first §
tv(A)
Output data valid time after
change of address, E, or G,
whichever occurs first §
PARAMETER
(see Figure 3)
55
0
0
0
TEST CONDITIONS
(SEE NOTES 6 AND 7)
0
'27C256-20
MIN
MAX
ns
'27C256-25
MIN
MAX
'27C256-30
MIN
MAX
UNIT
ta{Al
Access time from address
200
250
300
ta(E)
Access time from chip enable
200
250
300
ns
ten (G)
Output enable time from G
75
100
120
ns
tdis
Output disable time from G
or E, whichever occurs first §
105
ns
tv (A)
Output data valid time after
change of address, E, or G,
whichever occurs first §
(see Figure 3)
0
60
0
0
60
0
§ Value calculated from 0.5 V delta to measured output level. This parameter is only sampled and not 100% tested.
NOTES: 6. For all switching characteristics and timing measurements, input pulse levels are 0.4 V to 2.4 V.
7. Common test conditions apply to tdis except during programming.
TEXAS
lJ1
INSlRUMENTS
9-98
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
0
0
ns
ns
SMJ27C256
262144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS005C -
MAY 1986 -
recommended timing requirements for programming: VCC = 6 V and Vpp
VCC = 6.5 and Vpp =13 (SNAP! Pulse), TA = 25°C (see Note 6)
tw(IPGM)
Initial program pulse duration
Fast programming algorithm
REVISED JANUARY 1991
= 12.5
V (Fast) or
MIN
NOM
MAX
UNIT
0.95
1
1.05
ms
95
100
105
~!S
78.75
ms
SNAP! Pulse programming algorithm
tw(FPGM)
Final pulse duration
tsu(A)
Address setup time
2
tsu(G)
G setup time
2
tdis
Output disable time from G
0
ten (G)
Output enable time from G
tsu(D)
Data setup time
2
~s
tsu(VPP)
Vpp setup time
2
~s
Fast programming only
2.85
~s
~s
130
ns
150
ns
tsu(VCC)
VCC setup time
2
~s
th(A)
Address hold time
0
~s
th(D)
Data hold time
2
~s
tsu(E)
E setup time
2
~s
NOTE 6: For all switching characteristics and timing measurements, the input pulse levels are 0.4 V to 2.4 V.
PARAMETER MEASUREMENT INFORMATION
2.08 V
Output
Under Test
-1r
RL=800Q
CL= 100 pF
Figure 3. AC Testing Output Load Circuit
TEXAS
-I!I
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
9-99
SMJ27C256
262 144-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS005C -
MAY 1986 -
REVISED JANUARY 1991
read cycle timing
AO·A14
~__________A_d_d_re_s_s_es_v_a_lI_d________--J]>(~_________________
I
1
1"''4---- ta(A) - - - -••:
1
~~
I
________~:____~J/1
-----~
~
Q1·Qa
-
HI •
:
Y'
i
I
-'1
z-----<<<<<<<<<
VIL
j'4- tdls ~
1'4
.1
I
1
ten(G)
VIL
VIL
1
~ ta(E) - - . :
VIH
tv(A)
»»»»)-
Output Valid
VOH
HI· Z-
VOL
program cycle timing
""1'4--- Verify ~
141'4---- Program-----,.~I
AO·A14
1
1
I
:
~------------------A-d-d-re-s-s-St-a-bl-e-------------~~J>(~
___
A_~d_:_~_s___
I
I
~ tsu(A)
Q1·Qa
-----<~
+-
j>-_____.-..._____-<~ Dt~l~ut
In Siabl.
~ tsU(O):
VPP
I
,
{ :
----..../:
1
1
,
~tsu(VPP)
,
--"HtsurJCC)
~tsU(E)
tw(IPGM)
tw(FPGM)
1'4
)>-------.1
tdls
vppt
Vee
,
1
i
~
--------~{
I
I+- th(Al ~
Vee
,
:.- th(O)
~~I~----~--~--~-------------------
\-( I.
1'4
1'4
1
.1
.1
1
i
!
.1
tsu(G)
j
1 1
1
1 1'4
., ten (G) I
I
I
'
1
-----------------------~~
;'~---------------
t 12.5-V Vpp and 6-V Vee for Fast programming, 13-V Vpp and 6.5-V Vee for SNAP! Pulse programming.
TEXAS
lJ1
INSlRUMENTS
9-100
POST OFFICE BOX 1443
•. HOUSTON, TEXAS 77001
SMJ27C512
524 288-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMSOI9A-SEPTEMBER 1987- REVISED JANUARY 1991
•
Military Operating Temperature Range
... - 55°C to 125°C
•
MIL-STD-883C Class B High-Reliability
Processing
•
Organization •.. 64K x 8
•
•
Single 5-V Power Supply
•
•
J Package
(Top View)
A15
A12
A7
A6
A5
A4
A3
A2
A1
AO
01
02
03
Pin Compatible With Existing 512K
EPROMs
All Inputs/Outputs Fully TTL Compatible
Max Access/Min Cycle Times
'27C512-20
'27C512-25
'27C512-30
200 ns
250 ns
300 ns
•
HVCMOS Technology
•
•
3-State Output Buffers
GND
3
4
5
6
7
8
9
10
11
12
13
14
26
25
24
23
22
21
A14
A13
AS
A9
A11
GNpp
A10
E
08
07
06
05
04
PIN NOMENCLATURE
Latchup Immunity of 250 mA on All Input
and Output Lines
AO-A15
E
GND
• . 400-mV Minimum DC Noise Immunity With
Standard TTL Loads
•
Vee
01-08
Vee
Low Power Dissipation
- Active ... 275 mW (Max)
- Standby .•. 1.9 mW (Max)
(CMOS Input Levels)
Address Inputs
Chip Enable/Power Down
Ground
Outputs
5-V Power Supply
GNpp
Output Enable
GND
Ground
description
The SMJ27C512 series are 524 288-bit, ultraviolet-light erasable, electrically programmable read-only
memories. These devices are fabricated using HVCMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 54 TTL circuits
without the use of external pullup resistors, and each output can drive one Series 54 TTL circuit without external
resistors. The data outputs are three-state for connecting multiple devices to a common bus. The SMJ27C512
is pin compatible with existing 28-pin 512K ROMs and EPROMs. They are offered in a 600-mil dual-in-line
ceramic package (J suffix) rated for operation from -55°C to 125°C.
Since this EPROM operates from a single 5-V supply (in the read mode), it is ideal for use in
microprocessor-based systems. One other 12-13 V supply is needed for programming, but all programming
signals are TTL level. These devices are programmable by either Fast or SNAP! Pulse programming algorithms.
Fast programming uses a Vpp of 12.5 V and a Vee of 6 Vfor a nominal programming time of two minutes. SNAP!
Pulse programming uses a Vpp of 13 V and a Vee of 6.5 V for a nominal programming time of four seconds.
For programming outside the system, existing EPROM programmers can be used. Locations may be
programmed singly, in blocks, or at random.
operation
There are seven modes of operation for the SMJ27C512 listed in the following table. Read mode requires a
single 5-V supply. All inputs are TTL level except for Vpp during programming (12.5 V for Fast, or 13 V for SNAP!
Pulse) and 12 V on A9 for signature mode.
PRODUCTION DATA documents contlln InformaHon
current .. of publlclHon dat •• Product. conform to
.peclflclHons per the terms of TUII Instrument.
~~C~~~I~II;~~~~~~' t~~o:n~~f:1I ~!;~::~~. does not
Copyright © 1991. Texas Instruments Incorporated
TEXAS •
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
9-101
SMJ27C512
524 288-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS019A -
SEPTEMBER 19B7 -
REVISED JANUARY 1991
MODE
FUNCTION
(PINS)
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE
MODE
E
(20)
VIL
VIL
VIH
VIL
VIL
VIH
VIL
GNpp
(22)
VIL
VIH
xt
Vpp
VIL
Vpp
VIL
Vee
(28)
Vee
Vee
Vee
Vee
Vee
Vee
Vee
A9
(24)
x
X
x
x
x
X
VH:j:
VH:j:
AO
(10)
X
X
X
X
X
X
VIL
VIH
01-08
(11-13,
15-19)
Data Out
HI-Z
HI-Z
Data In
Data Out
HI-Z
MFG
DEVICE
97
85
CODE
t X can be VIL or VIH.
:j: VH = 12V ± 0.5 V.
read/output disable
When the outputs of two or more SMJ27C512s are connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no interference from the competing outputs of the other devices.
To read the output of the selected SMJ27C512, a lOW-level signal is applied to the E and GNpp pins. All other
devices in the circuit should have their outputs disabled by applying a high-level signal to one of these pins.
Output data is accessed at pins 01 through 08.
power down
Active ICC supply current can be reduced from 25 mA to 500 ~A (TTL-level inputs) or 350 ~ (CMOS-level inputs)
by applying a high logic signal to the E pin. In this mode all outputs are in the high-impedance state.
erasure
Before programming, the SMJ27C512 is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 A). EPROM erasure before programming is necessary to assure
that all bits are in the logic 1 (high) state. Logic a's (lows) are programmed into the desired locations. A
programmed I<;>gic a (low) can be erased only by ultraviolet light. The recommended minimum ultraviolet
light exposure dose (UV intensity x exposure time) is 15 W·s/cm 2 . A typical 12 mW/cm 2 , filterless UV lamp
will erase the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure.
After erasure, all bits are in the high state. It should be noted that normal ambient light contains the correct
wavelength for erasure. Therefore, when using the SMJ27C512, the window should be covered with an
opaque label.
SNAP! Pulse programming
The 512K EPROM can be programmed using the TI SNAP! Pulse programming algorithm illustrated by the
flowchart in Figure 1, which can reduce programming time to a nominal of four seconds. Actual programming
time will vary as a function of the programmer used.
Data is presented in parallel (eight bits) on pins 01 to 08. Once addresses and data are stable,
E is pulsed.
The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (~s) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 1OO-~s
pulses per byte are provided before a failure is recognized.
TEXAS.
INSlRUMENTS
9-102
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
SMJ27C512
524 288·BIT UV ERASABLE PROGRAMMBLE READ·ONLY MEMORY
SGMS019A -
SEPTEMBER 1987 -
REVISED JANUARY 1991
The programming mode is achieved with G/Vpp = 13 V, Vee = 6.5 V, and E = VIL' More than one device can
be programmed when the devices are connected in parallel. Locations can be programmed in any order. When
the SNAPI Pulse programming routine is complete, all bits are verified with Vee = 5 V, G/Vpp = VIL and
E=VIL'
'
fast programming
The 512K EPROM can be programmed using the Fast programming algorithm illustrated by the flowchart in
Figure 2. During Fast programming, data is presented in parallel (eight bits) on pins 01 through 08. Once
addresses and data are stable, E is pulsed. The programming mode is achieved when G/Vpp = 12.5 V,
Vee = 6 V, and E = VIL' More than one SMJ27C512 can be programmed when the devices are connected in
parallel. Locations can be programmed in any order.
Programming uses two types of programming pulses: Prime and Final. The length of the Prime pulse is 1
millisecond; this pulse is applied X times. After each Prime pulse, the byte being programmed is verified.
If the correct data is read, the Final programming pulse is applied; if correct data is not read, an additional
1 millisecond pulse is applied up to a maximum X of 25. The Final programming pulse is 3X long. This
sequence of programming and verification is performed at Vee = 6 V. When the full Fast programming
routine is complete, all bits are verified with Vee = 5 V (see Figure 2).
program inhibit
Programming may be inhibited by maintaining a high level input on the E pin.
program verify
Programmed bits may be verified with G/Vpp and E = VIL'
signature mode
The signature mode provides access to a binary code identifying'the manufacturer and type. This mode
is activated when A9 (pin 24) is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by AO (pin 10);
i.e., AO = VIL accesses the manufacturer code, which is output on 01-08; AO = VIH accesses the device
. code, which is output on 01-08. All other addresses must be held at VIL' Each byte possesses odd parity
on bit 08. The manufacturer code for these devices is 97, and the device code is 85.
latchup immunity
Latchup immunity on the SMJ27C512 is a minimum of 250 mA on all inputs and outputs. This feature provides
latchup immunity beyond any potential transients at the P.C. board level when the EPROM is interfaced to
industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup without
compromising performance or packing density.
For more information see application report SMLA001, "Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family", available through TI Sales Offices.
TEXAS
lJ1
INSlRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-103
SMJ27C512
524 288-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS019A -
SEPTEMBER 1987 -
Vee
REVISED JANUARY 1991
l
=6.5 V ± 0.25 V, GNpp =13 V ± 0.25 V
Program
Mode
No
Interactive
Mode
No
Yes
Final
Figure 1. SNAP! Pulse Programming Flowchart
TEXAS ~
INSTRUMENTS
9-104
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ27C512
524 288-B11 UV ERASABLE PROGRAMMBLE READ-ONLY MEMORY
SGMS019A -
SEPTEMBER 1987 -
REVISED JANUARY 1991
Yes
Increment
Address
Figure 2. FAST Programming Flowchart
TEXAS ~
INSTRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-105
SMJ27C512
524 288-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS019A -
SEPTEMBER 1987 -
REVISED JANUARY 1991
logic symbol t
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
E
GNpp
EPROM
65536 x 8
o\
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
1
20
_
A _O
65535
...
Lt:,.
22
r-.,
A'V
A'V
A'V
A'V
A'V
A'V
A'V
A'V
11
12
13
15
16
17
18
19
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
151
[PWR OWN]
.----,
&
I
EN
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. - 0.6 V to 7 V
Supply voltage range, Vpp ......................................................... - 0.6 V to 14 V
Input voltage range (see Note 1), All inputs except A9 ................................ - 0.6 V to 6.5 V
A9 ............................................... - 0.6 Vto 13.5 V
Output voltage range (see Note 1) ............................................. - 0.6 V to Vee + 1 V
Minimum operating free-air temperature ............................. : ...................... - 55°C
Maximum operating case temperature ...................................................... 125°C
Storage temperature range ............................ : .......................... - 65°C to 150°C
:j: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
TEXAS •
INSTRUMENTS
9-106
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
SMJ27C512
524 288·BIT UV ERASABLE PROGRAMMBLE READ·ONLY MEMORY
SGMS019A- SEPTEMBER 1987 -
REVISED JANUARY 1991
recommended operating conditions
SM/SMJ27C512-20
SM/SMJ27C512-25
SM/SMJ27C512-30
VCC
Supply voltage (see Note 2)
NOM
MAX
Read mode
4.75
5
5.25
Fast programming algorithm
5.75
6
6.25
V
SNAP! Pulse programming algorithm
6.25
6.5
6.75
V
12
12.5
13
V
12.75
13
13.25
V
Fast programming algorithm
GNpp Supply voltage (see Note 3)
VIH
SNAP! Pulse programming algorithm
CMOS
Low-level input voltage
TA
Operating free.-air temperature
TC
Operating case temperature
TTL
VCC+l
V
VCC-0.2
VCC+l
V
0.8
V
-0.5
GND-0.2
CMOS
V
2
TTL
High-level input voltage
VIL
UNIT
MIN
GND + 0.2
-55
V
°C
125
°c
NOTES: 2. Vce must be applied before or at the same time as GNpp and removed after or at the same time as GNpp. The device must not
be inserted into or removed from the board when GNpp or Vce is applied.
3. GNpp can be connected to VCC directly (except in the program mode). Vce supply current in this case would be ICC + Ipp.
electrical characteristics over full ranges of operating conditions
TEST CONDITIONS
PARAMETER
VOH
High-level ouput voltage
10H = -400~
VOL
Low-level ouput voltage
10L = 2.1 mA
MIN
TYpt
MAX
UNIT
V
2.4
0.4
V
~
II
Input current (leakage)
VI = Oto 5.5 V
±10
10
Output current (leakage)
Vo = OtoVee
±10
~
Ipp
GNpp supply current (during program pulse)
GNpp = 13 V
70
mA
Vee = 5.5 V, E = VIH
500
~
Vce = 5.5 V, E = Vee
350
~
50
mA
ICCl
Vce supply current
(standyby)
ICC2
ITTL-input level
ICMOS-input level
VCC = 5.5 V, E = VIL,
tcycl e = minimum cycle time,
outputs open
VCC supply current (active)
t Typical values are at T A
35
35
= 25°C and nominal voltages.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz
PARAMETER
TEST CONDITIONS
MIN
TYpt
UNIT
Ci
Input capacitance
VI = 0, f = 1 MHz
6
Co
Output capacitance
Vo = 0, f = 1 MHz
8
pF
CG/VPP
GNpp input capacitance
20
pF
GNpp = 0, f = 1 MHz
pF
t Typical values are at TA = 25°C and nominal voltages.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-107
SMJ27C512
524 288-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS019A -
SEPTEMBER 1987 -
REVISED JANUARY 1991
switching characteristics overfull ranges of recommended operating conditions (see Notes 4)
PARAMETER
TEST CONDITIONS
(SEE NOTE 4)
'27CS12-20
MIN
MAX
'27CS12-2S
MIN
'27CS12-30
MAX
MAX
MIN
UNIT
ta(A)
Access time from address
200
250
300
ta(E)
Access time from chip enable
200
250
300
ns
ten (G)
Output enable time from G
75
100
120
ns
tdis
Output disable time from G
or E, whichever occurs first t
105
ns
tv (A)
Output data valid time after
change of address, E, or G,
whichever occurs first t
ns
(see Figure 3)
0
0
60
0
60
0
0
0
ns
t Value calculated from 0.5 V delta to measured level.
recommended timing requirements for programming: Vee = 6 V and Vpp = 12.5 V (Fast) or
Vee = 6.5 and Vpp =13 (SNAP! Pulse), TA = 25°C (see Note 4)
,
Fast programming algorithm
MIN
. NOM
MAX
UNIT
0.95
1
1.05
ms
95
100
105
lAS
7S.75
ms
tw(IPGM)
Initial program pulse duration
tw(FPGM)
Final pulse duration
tsu(A)
Address setup time
2
tdis(G)
Output disable time from G
0
tEHD
Data valid from E low
SNAP! Pulse programming algorithm
2.S5
Fast programming only
lAs
130
lAs
1
Ils
tsu(D)
Data setup time
2
lAs
tsu(VPP)
Vpp setup time
2
lAs
tsu(VCC)
VCC setup time
2
lAS
th(A)
Address hold time
0
lAs
th(D)
Data hold time
2
lAs
tr(PG)G
Vpp rise time
50
ns
th(VPP)
Vpp hold time
2
[IS
Vpp recovery time
2
lAs
trec(PG)
NOTE 4: For all switching characteristics and timing measurements input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V
for logic high and O.S V for logic low (reference page 9-1 09, ACtesting waveforms).
•
TEXAS
•
INSlRUMENlS
9-10S
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ27C512
524 288·BIT UV ERASABLE PROGRAMMBLE READ·ONLY MEMORY
SGMS019A - SEPTEMBER 1987 -
REVISED JANUARY 1991
PARAMETER MEASUREMENT INFORMATION
2.08 V
Output
Under Test
-!
T
RL=800Q
CL= 100 pF
Figure 3. AC Testing Output Load Circuit
AC testing input/output wave forms
2.4 V---"",){
_
0.4
v
__~
o.:~X,-
~O.:~
___
A.C. testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low.
TEXAS •
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-109
SMJ27C512
524 288-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS019A -
SEPTEMBER 1987 -
REVISED JANUARY 1991
read cycle timing
~
AO-A15
___________
Ad_d_r_es_s_es_v_a_lI_d________
~I----- ta(A)
~f><~
.,
1<011
1
\1\;,,_______..
1 ___
I
\
11
I
i
-
HI-Z
---<«««({
VIL
I
~tdls~
I
~ ten(G) ~
01-08
VIH
}:10-:- - - - - - - - - :::
I
1
--------
~jI~11
I
~ ta(E) - . I
GNpp
________________ ::
tv(A)
I~
»»»»-
.,
Output Valid
1
HI-ZVOL
program cycle timing
AO-A 15
---vr-V~---------------------------~~
Address Stable
,
I
~ tsu(A)
I
01-08
----<~
~ tsu(D)
GNpp
J>----
Data In Stable
,I
~
HI-Z
----<~
I
~I
,
1
'I,
I
,
1
1
'
1
1
~
tr(PG)G
i i
'14'4---I~~:-1 trec(PG)
'I
I
1
"\ ~
-1-..: 'L-./
,
1
I
14
,
1
1
vppt
1
- - 4 - - 1- " \ ; f
tsuNCC)
VILNOL
~ tdIS(E)t
,
,
,I
J)-----
T.
I
I
\.
~tEHD
~I
i thNPP)~14'---~~~~_ _ _~i______~______
, ~ tsuNPP)I
I 1
1
-.j
E
Data Out Valid
,
th(D)
VIL
1"IIt'4f----I~*"I- theA)
1
,,,,
I
,\Ji;. .~_ _ _ _-'
I
~I
tw(IPGM)
I
~I
tw(FPGM)
VCC
VCC
t 12.5-V Vpp and 6-V Vec for Fast programming, 13-V Vpp and 6.5-V Vee for SNAP! Pulse programming.
TEXAS •
INSTRUMENlS
9-110
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
SMJ27C512
524 288·B11 UV ERASABLE PROGRAMMBLE READ·ONLY MEMORY
SGMS019A - SEPTEMBER 1987 -
REVISED JANUARY 1991
TYPICAL CHARACTERISTICS
STANDBY SUPPLY CURRENT
STANDBY SUPPLY CURRENT
'E
1.50
~
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
I
'E
I
o
:l
..........
f'..-
Q,)
~ ~
:gc 0E
1.00
li _ 1.25
TA -
.............
r---.. ""'"--
C
I'D
en
I
0
25
50
75
-0.75
u
o
100 125
Free-Air Temperature -
0
Z
1.50
~
I
:;
4.5
°C
"8:iN
:l
~ ~ 1.00
.~ E
t)
0
vs
SUPPLY VOLTAGE
'E
1.50
~
:;
o
" "-
c..:o
a.
>-
...........
:l
:-.......
.
1.25 -
I
~ ...........
N
~ ~E; 1.00
.~
t)
~
V
0
~ ~ 0.75
I
0.50
-75 -50 -25
1.50
I
o
o
0
25
50
75
r
Free-Air Temperature -
0.50
4.25
100 125
~
~
---
.--V
4.5
°C
4.75
Vee -
vs
SUPPLY VOLTAGE
1.50
=5 V
1.25
~ ~ 1.00
':t E
./
/
/"
V
"",
V
TA -
0
25
50
TA
Q,)
E
1=:0
VI Q,)
:{l
75
Free-Alr'Temperature -
1.25
CJ
co
~
-0.75
1.00
0.50
4.25
100 125
°C
I
I
"
~
=25°C
.......
.~
:t E
I~
~
0.50
-75 -50 -25
5.75
Supply Voltage - V
FREE-AIR TEMPERATURE
/'
5.5
ACCESS TIME
Q,)
0.75
5.25
5
vs
I
Vee
~ -
V
I
ACCESS TIME
~
5.75
N
TA -
I~
5.5
TA = 25°C
f = Max
Q,)
N
E
Supply Voltage -
FREE-AIR TEMPERATURE
I
1=VI:O
VI :!l
5.25
5
ACTIVE SUPPLY CURRENT
~ ~ 0.75
8
V
vs
I
1.25
4.75
Vee -
,~
c;.
/'
/'"
0.50
4.25
=5 V
Vee
/
/
ACTIVE SUPPLY CURRENT
'E
~/
~ .~
>- co 1.00
.c
E
"0 ...
I
0.50
-75 -50 -25
I
0."0
"- -.....
~ ~ 0.75
u
o
I
=25°C
TA
o
,~
>1.25
c.._
0."0
1.50
~
:;
Vee = 5 V
:;
4.5
4.75
Vee -
TEXAS
--5
5.25
5.5
5.75
Supply Voltage - V
~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-111
SMJ27C512
524 288-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS019A -
SEPTEMBER 1987 -
REVISED JANUARY 1991
TEXAS •
INSTRUMENTS
9-112
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ27C010
1 048 576-BIT UV
ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS027B -
MARCH 1988 -
J Package
(Top View)
• Military Operating Temperature Range
... - 55° C to 125°C
•
•
o
•
•
•
Vpp
Organization ... 128K x 8
Industry Standard 32-Pin Dual-In-line
Package
All Inputs/Outputs Fully TTL Compatible
Static Operations (No Clocks, No Refresh)
Max Access/Min Cycle Time
±
10%
SMJ27C010-17
SMJ27C010-20
SMJ27C010-25
170 ns
200 ns
250 ns
8-Bit Output For Use in MicroprocessorBased Systems
•
32-Bit Programming (Four Bytes) and
Standard 8-Bit Programming
•
Vee
PGM
NC
1
6
27
7
26
8
25
A14
A13
A8
A9
A11
9
24
G
10
23
A10
28
E
08
07
06
05
04
GND
•
•
•
•
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
AO
01
02
03
Single 5-V Power Supply
Vee
REVISED DECEMBER 1990
;:
w
PIN NOMENCLATURE
AO-A16
E
G
Power Saving CMOS Technology
GND
NC
PGM
01-08
VCC
Vpp
3-State Output Buffers
400-mV Minimum DC Noise Immunity With
Standard TTL Loads
No Pullup Resistors Required
5=
w
Address Inputs
Chip Enable
Output Enable
Ground
No External Connection
Program
Outputs
5-V Supply
12.5-V Supplyt
0:
a.
I-
o
::)
c
o
a:
t Only in program mode.
description
a.
The SMJ27C010 series are 1 048 576-bit, ultraviolet-light erasable, electrically programmable read-only
memories. These devices are fabricated using CMOS technology for high speed and simple interface with MaS
and bipolar circuits. All inputs (including program data inputs) can be driven by Series 54 TTL circuits. Each
output can drive one Series 54 TTL circuit without external resistors. The data outputs are three-state for
connecting multiple devices to a common bus. The SMJ27C010 is offered in a 600-mil dual-in-line cerdip
package (J suffix) rated for operation from - 55°C to 125°C.
Since these EPROMs operate from a single-5 V supply (in the read mode), they are ideal for use in
microprocessor-based systems. One other (12.5-V) supply is needed for programming. All programming signals
are TTL level. For programming outside the system, existing EPROM programmers can be used.
PRODUCT PREVIEW Information concerns products In the
formative or design phase of developmenl Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
TEXAS
~
Copyright © 1990, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-113
SMJ27C010
1 048 576-BIT UV
ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS027B -
MARCH 1988 -
REVISED DECEMBER 1990
TEXAS ~
INSTRUMENTS
9-114
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ27C210
1 048 576-81T UV
ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMGS028A -
•
•
•
•
•
•
•
REVISED NOVEMBER 1990
J Package
(Top View)
Wide-Word Organization ... 64K x 16
Single 5-V Power Supply
Operationally Compatible With Existing
Megabit EPROMs
40-Pin Dual-in-line Package
A" Inputs and Outputs Fully TTL
Compatible
Static Operations (No Clocks, No Refresh)
Max Access/Min Cycle Time
Vee ± 10%
SMJ27C210-12
SMJ27C210-15
SMJ27C210-17
SMJ27C21 0-20
SMJ27C21 0-25
•
MARCH 1988 -
120 ns
150 ns
170 ns
200 ns
250 ns
16-Bit Output For Use in MicroprocessorBased Systems
Vpp
1
40
Vee
E
2
39
016
015
014
013
012
011
010
09
GNot
08
07
06
05
04
03
02
01
3
38
PGM
NC
A15
A14
A13
A12
A11
A10
A9
GNot
A8
A7
A6
AS
A4
A3
A2
A1
AO
G
4
37
5
36
6
35
7
34
8
33
9
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
•
32-Bit Programming (Two 16-Bit Words)
and 16-Bit Programming
•
•
16 Seconds Typical Programming Time
•
•
3-State Output Buffers
•
Latchup Immunity of 250 rnA on All Input
and Output Pins
t Pins 11 and 30 must be connected
No Pullup Resistors Required
externally to ground.
:j: Only in program mode.
•
•
~
w
5=
w
a:
a..
Io
::;:)
PIN NOMENCLATURE
AO-A15
E
Power Saving CMOS Technology
G
GND
NC
PGM
01-016
Vec
Vpp
400-mV Minimum DC Noise Immunity With
Standard TTL Loads
Low Power Dissipation
- Active ... 220 mW Worst Case
- Standby ... 1.5 mW Worst Case
(CMOS-Input Levels)
Address Inputs
ehip Enable
Output Enable
Ground
No Connection
Program
Outputs
5-V Supply
12.5-V Supply:j:
c
o
a:
a..
• Operating Temperature Range
... - 55° C to 125°C
description
The SMJ27C21 a is a 1 048 576-bit, ultraviolet-light erasable, electrica"y programmable read-only memory. This
device is fabricated using CMOS technology for high speed and simple interface with MOS and bipolar circuits.
A" inputs (including program data inputs) can be driven by Series 54 TTL circuits without the use of external
pu"up resistors and each output can drive one Series 54 TTL circuit without external resistors. The data outputs
are three-state for connecting multiple devices to a common bus. The SMJ27C210 is offered in a 600-mil
dual-in-line cerdip package (J suffix) rated for operation from - 55°C to 125°C.
PRODUCT PREVIEW Information concerns products In the
formative or design phlle of development Characteristic data and
other speclflcations ar. design goals. Texas Instruments reserves
the right to chang. or discontinue these products wHhout notice.
TEXAS
~
Copyright © 1990. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
9-115
SMJ27C210
1 048 576-BIT UV
ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMGS028A -
MARCH 1988 -
REVISED NOVEMBER 1990
,
TEXAS.
INSTRUMENTS
9-116
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
SMJ44C250
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS037 -
•
Military Operating Temperature Range
... - 55°C to 125°C
•
Class B High-Reliability Processing
•
DRAM: 262 144 Words x 4 Bits
SAM: 512 Words x 4 Bits
•
•
JD Package t
(Top View)
SC
•
Write Per Bit Feature for Selective Write to
Each RAM I/O.
•
Enhanced Page Mode Operation for Faster
Access
•
CAS-before-RAS and Hidden Refresh
Modes
•
RAM Output Enable Allows Direct.
Connection of DQ and Address Lines to
Simplify System Design
•
Long Refresh Period ... Every 8 ms (Max)
•
Up to 33 MHz Uninterrupted Serial Data
Streams
•
3-State Seriall/Os Allow Easy Multip!exing
of Video Data Streams
•
512 Selectable Serial Register Starting
Locations
•
Texas Instruments EPIC ™ CMOS Process
•
Performance Ranges:
ROW
TIME
DATA
VSS
SE
TRG
SE
DOD
D01
D03
D02
GND
CAS
DOD
D01
D03
D02
GND
CAS
Vii
NC
AD
A8
A6
A5
A4
A1
A2
A3
A7
VCC
Vii
GND
RAS
A8
A6
A5
A4
VCC
NC
AD
A1
A2
A3
A7
tThe packages shown here are for pinout reference only and
are not drawn to scale.
PiN NOMENCLATURE
AO-AS
CAS
DQO-DQ3
SE
RAS
SC
SDQO-SDQ3
W
NC
Vee
VSS
GND
•
VCC
TIME TOLERANCE
COLUMN SERIAL SERIAL
ADDRESS ENABLE
(MAX)
TIME
SC
TRG
ACCESS ACCESS ACCESS ACCESS
TIME
VSS
SD03
SD02
GND
RAS
Bidirectional Data Transfer Function
Between the DRAM and the Serial Data
Register
HJ Package t
(Top View)
SD03 SDOD
SD02 SD01
SDOD
SD01
Dual Port Accessibility - Simultaneous
and Asynchronous Access from the'DRAM
and SAM Ports
JANUARY 1991
Address Inputs
Column Enable
DRAM Data In-Out/Write Mask Bit
Serial Enable
Row Enable
Serial Data Clock
Serial Data In-Out
Transfer Register/Q Output Enable
Write Mask Select/Write Enable
No Connection
5-V Supply
Ground
Ground (Important: not connected to
internal VSS)
Packaging Options
- 28-pin CeramicSide Brazed DIP (JD suffix)
- 28-pin Ceramic Small Outline J-Leaded
Chip Carrier (HJ Suffix)
ENABLE
(MAX)
(MAX)
(MAX)
'44C250-1
ta(R)
100 ns
ta(C)
25 ns
ta(SC)
30 ns
ta(SE)
20 ns
±5%
'44C250-2
120 ns
30 ns
35 ns
25 ns
±5%
'44C250-10 100 ns
25 ns
30 ns
20 ns
±10%
'44C250-12 120 ns
30 ns
35 ns
25 ns
±10%
NOTE: All references to the SMJ44C250-10, -1 are Advance Information Only,
EPIC is a trademark of Texas Instruments Incorporated,
Copyright © 1991, Texas Instruments Incorporated
TEXAS •
INSlRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-117
SMJ44C250
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS037 -
JANUARY 1991
description
The SMJ44C250 Multiport Video RAM is a high speed, dual ported memory device. It consists of a dynamic
random-access memory (DRAM) organized as 262 144 words of 4 bits each, interfaced to a serial data register,
or Serial Access Memory (SAM), organized as 512 words of 4 bits each. The SMJ44C250 supports three basic
types of operation: random access to and from the DRAM, serial access to and from the serial register, and
bidirectional transfer of data between any row in the DRAM and the serial register. Except during transfer
operations, the.SMJ44C250 can be accessed simultaneously and asynchronously from the DRAM and SAM
ports. During a transfer operation, the 512 columns of the DRAM are connected to the 512 positions in the serial
data register. The 512 x 4 bit serial data register can be loaded from the memory row (transfer read) or else the
contents of the 512 x 4 bit serial data register can be written to the memory row (transfer write).
The SAM can also be configured in input mode, accepting serial data from an external device. Once the serial
register within the SAM is loaded, its contents can be transferred to the corresponding column positions in any
row in memory in a single memory cycle. The SAM port is designed for maximum performance. Data can be
input to or accessed from the SAM at serial rates up to 33 MHz.
.
All address lines and data-in are latched on-chip to simplify system design. All data-outs are unlatched to allow
greater system flexibility.
The SMJ44C250 employs state-of-the-art Texas Instruments EPIC'" scaled CMOS, double-level
polysilicon/polycide gate technology for very high performance combined with low cost and improved reliability.
The SMJ44C250 is offered both in a 28-pin, ceramic small-outline J-Ieaded package (HJ suffix) for direct surface
mounting in rows on 400-mil centers. It is also offered in a 400-mil, 28-pin ceramic sidebrazed dual-in-line
package (JD suffix). 80th packages are characterized for operation from - 55°C to 125°C (M suffix).
The SMJ44C250 and other SMJ44C25X multipart Video RAMs are supported by a broad line of video/graphic
processors from Texas Instruments, including the SMJ3401 0 and the SMJ34020 Graphics System Processors.
NOTE: All references to the SMJ44C250-1 0, -1 are Advance Information.
TEXAS
~
INSTRUMENTS
9-118
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ44C250
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037 -
JANUARY 1991
functional block diagram
. - 0 Vcc
. - 0 vss
000 o--HH~
Oat
002
003
Write
Per Bit
Control
B
s a
e
. - 0 AO
. - 0 At
. - 0 A2
. - 0 A3
. - 0 A4
. - 0 AS
. - 0 A6
. - 0 A7
. - 0 AS
B
e 0
u
I u
t
r n
p
e t
5 e
h r
SOOO
SOOt
SOO2
SOO3
S
e
I
n
G
T e
I n
B
me
I r
p
u
t
e
n t
e
9
0
.-0
.-0
.-0
.-0
.-0
.-0
RAS
CAS
TRG
Vi
SC
SE
Detailed Pin Description vs Operational Mode
PIN
DRAM
TRANSFER
AO-AS
Row, Column Address
Row, Tap Address
CAS
Column Enable, Output Enable
Tap Address Strobe
DOi
DRAM Data I/O, Write Mask Bits
RAS
Row Enable
SAM
Row Enable
SE
Serial-In Mode Enable
Serial Enable
Serial Clock
SC
SDOi
Serial Data I/O
TRG
a Output Enable
W
Write Enable, Write per Bit Select
Transfer Enable
Transfer Write Enable
VCC
5-V Supply (typical)
VSS
GND
System Ground
NC
Make no external connection
Device Ground
TEXAS
-III
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-119
SMJ44C250
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037 -
JANUARY 1991
operation
random access operation
Refer to Table 1, Functional Table, for Random Access and Transfer Operations. Random access operations
are denoted by the designator "R" and transfer operations are denoted by a " T"
transfer register select and DQ enable (TRG)
The TRG pin selects either register or random access operation as RAS falls. For random access (DRAM) mode,
TRG must be held high as RAS falls. Asserting TRG high as RAS falls causes the 512 storage elements of each
data register to remain disconnected from the corresponding 512-bit lines of the memory array. (Asserting TRG .
low as RAS falls connects the 512-bit positions in the serial register to the bit lines and indicates that a transfer
will occur between the data registers and the selected memory row. See ''Transfer Operation" for details.)
During random access operations, TRG also functions as an output enable for the random (0) outputs.
Whenever TRG is held high, the 0 outputs are in the high-impedance state to prevent an overlap between the
address and DRAM data. This organization allows the connection of the address lines to the data I/O lines but
prohibits the use of the early write cycle. It also allows read-modify-write cycles to be performed by providing
a three-state condition to the common I/O pins so that write data can be driven onto the pins after output read
data has been externally latched.
address (AO through AS)
Eighteen address bits are required to decode 1 of 262 144 storage cell locations. Nine row address bits are set
up on pins AD through A8 and latched onto the chip on the falling edge of RAS. Then the nine column address
bits are set up on pins AD through A8 and latched onto the chip on the falling edge of CAS. All addresses must
be stable on or before the falling edges of RAS and CAS.
RAS and CAS address strobes and device control clocks
RAS is a control input that latches the states of the row address, W, TRG, SE, and CAS, onto the chip to invoke
the various DRAM and Transfer functions of the SMJ44C25D. RAS is similar to a chip enable in that it activates
the sense amplifiers as well as the row decoder. CAS is a control input that latches the states of the column
address. CAS also acts as an output enable for the DRAM output pins.
write enable, write-per-bit enable (W)
The Vii pin enables data to be written to the DRAM and is also used to select the DRAM write-per-bit mode of .
operation. A logic high level on the W input selects the read mode and logic low level selects the write mode.
In an early write cycle, Vii is brought low before CAS and the DRAM output pins (DO) remain in the
high-impedance state for the entire cycle. During DRAM write cycles, holding W Iowan the falling edge of RAS
will invoke the write-per-bit operation.
A four-bit binary code (the write-per-bit mask) is input to the device via the random DO pins and is latched on
the falling edge of RAS. The write-per-bit mask selects which of the four random I/Os are written and which are
not. After RAS has latched the write mask on-chip, input data is driven onto the DO pins and is latched on the
falling edge ofthe later of CAS or W. If a D (low) was strobed into a particular I/O pin on the falling edge of RAS,
data will not be written to that I/O. If a 1 (high) was strobed into a particular I/O pin on the falling edge of RAS,
data will be written to that I/O.
See the corresponding timing diagrams for details.
IMPORTANT: The write-per-bit operation is invoked only if W is held Iowan the falling edge of RAS. If W is held
high on the falling edge of RAS, write-per-bit is not enabled and the write operation is identical to that of standard
x 4 DRAMs.
TEXAS ~
INSTRUMENTS
9-120
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
SMJ44C250
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS037 -
JANUARY 1991
data I/O (OQO-OQ3)
DRAM data is written during a write or read-modify-write cycle. The falling edge ofW strobes data into the on-chip
data latches. In an early write cycle, W is brought low prior to CAS and the data is strobed in by CAS with data
setup and hold times referenced to this signal. In a delayed write or read-modify-write cycle, CAS will already
be low. Thus, the data will be strobed-in by W with data setup and hold times referenced to this signal.
The three-state output buffers provide direct TTL compatibility (no pullup resistors required) with a fanout of two
Series 74/54 TTL loads. Data-out is the same polarity as data-in. The outputs are in the high impedance (floating)
state as long as CAS or TRG is held high. Data will not appear at the outputs until after both CAS and TRG have
been brought low. Once the outputs are valid, they remain valid while CAS and TRG are low. CAS or TRG going
high returns the outputs to a high-impedance state. In an early write cycle, the outputs are always in the
high-impedance state. In a register transfer operation (memory to register or register to memory), the outputs
remain in the high-impedance state for the entire cycle.
enhanced page mode
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the SMJ44C250 to operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as column address is valid rather than when
CAS transitions low. This performance improvement is referred to as enhanced page mode. Valid column
address may be presented immediately after row address hold time has been satisfied, usually well in advance
of the falling edge of CAS. In this case, data is obtained after ta(C) max (access time from CAS low), if ta(CA)
max (access time from column address) has been satisfied. In the event that column addresses for the next page
cycle are valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence
of ta(C) or ta(CP) (access time from rising edge of CAS).
Enhanced page mode operation allows faster memory access by keeping the same row address while selecting
random colUmn addresses. The time for row address setup, row address hold, and address multiplex is thus
eliminated, and a memory cycle time reduction of up to 3 x can be achieved, compared to minimum RAS cycle
times. The maximum number of columns that may be accessed is determined by the maximum RAS low time
and page mode cycle time used. The SMJ44C250 allows a full page (512 cycles) of information to be accessed
in read, write, or read-modify-write mode during a single RAS low period using relatively conservative page mode
cycle times.
refresh
A refresh operation must be performed to each row at least once every eight milliseconds to retain data. Since
the output buffer is in the high-impedance state (unless CAS is applied), the RAS-only refresh sequence avoids
any output during refresh. Strobing each of the 512 row addresses with RAS causes all bits in each row to be
refreshed. CAS can remain high (inactive) for this refresh sequence to conserve power.
CAS-before-RAS refresh
CAS-before-RAS refresh is accomplished by bringing CAS low earlier than RAS. The external row address is
ignored and the refresh address is generated internally.
GND
This pin is reserved for the manufacturer's test operation. It is an input and should be tied to system ground.
IMPORTANT: GND is not connected internally to Vss.
TEXAS
JJ1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
9-121
SMJ44C250
262 144 8Y 4·81T MULTIPaRT VIDEO RAM
SGMS037-JANUARY 1991
Table 1. Functional Table
T
y
RAS FALL
DOO-D03
ADDRESS
FUNCTION
P
Et
CAS
TRG
Vii
SE
R
L
X§
X
X
CAS
RAS
CASt:
Viit:
X
X
X
X
CAS-8efore-RAS Refresh
Tap
Point
X
X
Registe~ to Memory Transfer
(Transfer Write)
RAS
T
H
L
L
L
Row
Addr
T
H
L
L
H
Refresh
Addr
Tap
Point
X
X
Serial Write-mode Enable
(Pseudo-Transfer Write)
T
H
L
H
X
Row
Addr
Tap
Point
X
X
Memory to Register Transfer
(Transfer Read)
R
H
H
L
X
Row
Addr
Col
Addr
Write
Mask
Valid
Data
Load and use Write Mask,
Write Data to Dram
R
H
H
H
X
Row
Addr
Col
Addr
X
Valid
Data
Normal Dram Readf\Nrite
(Non Masked)
t R = Random access operation; T = Transfer operation.
t: DOO-3 are latched on the later of Vii or CAS falling edge.
§ X = Don't care.
Write Mask = 1 (high) write to I/O enabled.
random port to serial port interface
Random-access Port
Col
Col
511
o
Row
o
Memory Array
262144 Bits
DO
Row
511
Transfer
Control
Logic
512 Bit Data Register
SC
AO-AS
Figure 1. Block Diagram Showing One Random and One Serial 110 Interface
TEXAS . .
INSlRUMENTS
9-122
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ44C250
262144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS037 -
JANUARY 1991
random address space to serial address space mapping
The 512 bits in each of the four data registers of the SAM are connected to the 512 column locations of each
of the four random I/Os. Data can be accessed in or out of the SAM starting at any of the 512 data bit locations.
This start location is selected by addresses AD through AS on the falling edge of CAS during any transfer cycle.
The SAM is accessed starting from the selected start address, proceeding from the lowest to the highest
significant bits. After the most significant bit position (511) is accessed, the serial counter wraps around such
that bit Dis accessed on the next clock pulse. The selected start address is stored and used for all subsequent
transfer cycles until CAS is again brought low during any transfer cycle. Thus, the start address can be set once
and CAS held high during all subsequent transfer cycles and the start address point will not change regardless
of data present on AD through AS.
transfer operations
As illustrated in Table 1, the SMJ44C25D supports three basic transfer modes of operation:
1.
2.
3.
Write Transfer (SAM to DRAM)
Pseudo Write Transfer (Switches serial port from serial-out mode to serial-in mode. No actual data transfer
takes place between the DRAM and the SAM.)
Read Transfer (Transfer entire contents of DRAM to SAM)
transfer register select (TRG)
Transfer operations between the memory array and the data registers are invoked by bringing TRG low before
RAS falls. The states ofW and SE, which are also latched on the falling edge of RAS, determine which transfer
operation will be invoked. (See Table 2.)
During read transfer cycles, TRG going high causes the addressed row of data to be transferred into the data
register. Although the previous data in the data register is overwritten, the last bit of data appearing at SOO before
TRG goes high will remain valid until the first positive transition of SC after TRG goes high. The data at SOO
will then switch to new data beginning from the selected start, or tap, position.
transfer write enable (W)
In register transfer mode, W determines whether a read or a write transfer will occur. To perform a write transfer,
Wand SE are held low as RAS falls. If SE is high during this transition, no transfer of data from the data register
to the memory array occurs, but the SOOs are put into the input mode. This allows serial data to be input into
the SAM. To perform a read transfer operation, W is held high and SE is a Don't Care as RAS falls. This cycle
also puts the SOOs into the read mode, allowing serial data to be shifted out of the data register. (See Table 2.)
column enable (CAS)
If CAS is brought low during a control cycle, the address present on the pins AD through AS will become the new
register start location. If CAS is held high during a control cycle, the previous tap address will be retained from
the last transfer cycle in which CAS went low to set the tap address.
addresses (AO through AS)
Nine address bits are required to select one of the 512 possible rows involved in the transfer of data to or from
the data registers. The states of AD-AS are latched on the falliing edge of RAS to select one of 512 rows for the
transfer operation.
To select one of the 512 positions in the SAM from which the first serial data will be accessed, the appropriate
9-bit column address (AD-AS) must be valid when CAS falls. However, the CAS and start (tap) position need
not be supplied every cycle, only when changing to a different start position.
serial access operation
Refer to Tables 2 and 3 for the following discussion on serial access operation.
TEXAS ~
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POST OFFICE BOX 1443
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9-123
SMJ44C250
262144 BY 4-BIT MULTIPORT VIDEO RAM
SGMS037 -
JANUARY 1991
serial clock (Se)
Data (SOO) is accessed in or out of data registers on the rising edge of SC. The SMJ44C250 is designed to work
with a wide range of clock duty cycles to simplify system design. Since the data registers comprising the SAM
are of static design, there are no SAM refresh requirements and there is no minimum SC clock operating
frequency.
serial data input/output (SDQO-SDQ3)
SO and SO share a common I/O pin. Data is input to the device when SE is low during write mode and data is
output from the device when SE is low during read mode. The data in the SAM will be accessed in the direction
from least significant bit to most significant bit. The data registers operate modulo 512. Thus, after bit 511 is
accessed, the next bits to be accessed will be bits 00, 01, 02, and so on.
serial enable (SE)
The Serial Enable pin has two functions: first, it is latched on the falling edge of RAS, with both TRG and W low
to select one ofthe transfer functions (see Table 2.) If SE is low during this transition, then a transfer write occurs.
If SE is high as RAS falls, then a write mode control cycle is performed. The function of this cycle is to switch
the SOOs from the output mode to the input mode, thus allowing data to be shifted into the data register.
NOTE: All transfer read and serial mode enable (pseudo transfer write) operations will perform a memory refresh
operation on the selected row.
Second, during serial access operations, SE is used as an SOO enable/disable. In the write mode, SE is used
as an input enable. SE high disables the input and SE low enables the input. To take the device out of the write
mode and into the read mode, a transfer read cycle must be performed. The read mode allows data to be
accessed from the data register. While in the read mode, SE high disables the output and SE low enables the
output.
IMPORTANT: While SE is held high, the serial clock is NOT disabled. Thus, external SC pulses will increment
the internal serial address counter regardless of the state of SE. This ungated serial clock scheme minimizes
access time of serial output from SE low since the serial clock input buffer and the serial address counter are
not disabled by SE.
Table 2. Transfer Operation Logic
TAG
W
SE
L
L
L
L
L
H
L
H
MODE
Register to memory (write) transfer
Serial write mode enable
Memory to register (read) transfer
X
NOTE: Above logic states are assumed valid on the falling edge of RAS.
Table 3. Serial Operation Logic
LAST TRANSFER CYCLE
Serial write mode enable t
Serial write mode enable t
Memory to register
Memory to register
soa
SE
L
H
L
H
Input enable
Input disable
Output enabled
HI-Z
tPseudo transfer write.
power-up
To achieve proper device operation, an initial pause of 200 !!S is required after power-up, followed by a minimum
of eight RAS cycles or eight CAS-before-RAS cycles, a memory-to-register transfer cycle and two SC cycles.
TEXAS . .
JNSJRUMENTS
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SMJ44C250
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS037 -
JANUARY 1991
absolute ~aximum ratings over operating temperature (unless otherwise noted)t
Voltage on any pin except DO and SDO (see Note 1) ..................................... - 1 V to 7 V
Voltage on DO and SDO (see Note 1) ................................................. - 1 V to Vee
Voltage range on Vee (see Note 1) ..................................................... 0 V to 7 V
Short circuit output current (per output) ..................................................... 50 mA
Power dissipation .......................................................................... 1 W
Operating temperature range ...................................................... -55°C to 125°C
Storage temperature range ....................................................... - 65°C to 150°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation ofthe device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
ISMJ44C250-1, SMJ44C250-2
ISMJ44C250-10, SMJ44C250-12
MIN
NOM
MAX
4.75
5
5.25
4.5
5
5.5
UNIT
VCC
Supply Voltage
VSS
Supply voltage
VIH
High-level input voltage
3.5
VCC
VIL
Low-level input voltage (see Note 2)
-1.0
0.5
V
TA
Operating free-air temperature
-55
TC
Operating case temperature
125
°c
°c
0
V
V
V
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
z
o
~
~
a:
oLL
Z
W
o
Z
~
c
«
TEXAS -111
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9-125
SMJ44C250
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037 -
JANUARY 1991
electrical characteristics over full ranges of recommended operating conditions
PARAMETER
High level output voltage
10H =-5.0 mA
VOL
low level output voltage (see Note 4)
10l = 4.2 mA
Il
Input leakage current
VI = 0 to 5.8 V, VCC = 5 V,
All outputs open
10
Output leakage current (see Note 3)
Vo = 0 to VCC, VCC = 5.5 V
PARAMETER
»c
~
z
n
m
-z
."
o
:0
s:
~
o
z
MIN
TEST CONDITIONS
VOH
ICC1
Operation current tc(RW)
ICC1A
tc(SC) = Minimum
SAM PORT
=Minimum
=VCC
ICC2
Standby current, All clocks
ICC2A
tc(SC) = Minimum
ICC3
RAS-only refresh current, tc(RW) = Minimum
tc(SC) = Minimum
ICC3A
(see Note 5)
MAX
0.4
V
±1.0
~
±10
IlA
SMJ44C250-1
SMJ44C250,10
SMJ44C250-2
SMJ44C250-12
MIN
MIN
MAX
Standby
100
90
Active
110
100
Standby
15
15
Active
35
35
Standby
100
90
Active
110
100
Standby
65
60
Page mode current, tc(P) = Minimum
ICC4A
tc(SC) = Minimum
Active
70
65
ICC5
CAS-before-RAS current, tc(RW) = Minimum
Standby
90
80
ICC5A
tc(SC)
Active
110
100
ICC6
Data transfer current, tc(RW)
Standby
100
90
ICC6A
tc(SC)
Active
110
100
= Minimum
=Minimum
UNIT
MAX
ICC4
=Minimum
UNIT
V
2.4
mA
NOTES: 3. SE is disabled for SDO output leakage tests.
4. The SMJ44C250 One Mega-bit Video Ram exhibits simultaneous switching noise as described in Texas Instruments' "Advanced
CMOS logic Designer's Handbook". This phenomenon exhibits itself upon the DO pins when the SDO pins are switched and upon
the SDO pins when DO pins are switched. This may cause the VOL to exceed the data book limit for a short period oftime, depending
upon output loading and temperature. Care should be taken to provide proper termination, decoupling, and layout of the device to
minimize simultaneous switching effects.
5. ICC (standby) vs ICCA (active) denotes the following:
ICC (standby): SAM port is inactive and the DRAM port is active (except for ICC2).
ICCA (active): SAM port is active and the DRAM port is active (except for ICC2A).
ICC is measured with no load on DO or SDO pins.
TEXAS •
INSTRUMENTS
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SMJ44C250
262144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS037-JANUARY 1991
capacitance over recommended ranges of supply voltage and operating temperature,
f = 1 MHz (see Note 6)t
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
9
Ci(RC)
Input capacitance, strobe inputs
9
pF
Ci(W)
Input capacitance, write enable input
9
pF
Ci(SC)
Input capacitance, serial clock
9
pF
Ci(SE)
Input capacitance, serial enable
9
pF
Ci(TRG)
Input capacitance, transfer register input
9
pF
Co(O)
Output capacitance, SDO and DO
9
pF
pF
t Capacitance is sampled only at initial design and after any major change.
NOTE 6: VCC equal to 5 V ± 0.5 V for SMJ44C250-1 0 and SMJ44C250-12, 5 V ± 0.25 V for SMJ44C250-1 and SMJ44C250-2. The bias on pins
under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating temperature
(see Note 7)
NO.t
TEST
CONDITIONS
PARAMETER
SMJ44C250-1
ALT.
SMJ44C250-10
SYMBOL
MIN
MAX
SMJ44C250-2
SMJ44C250-12
.... , .•. 25
30
ns
50
60
ns
1
ta(C)
Access time from CAS
td(RLCL) = MAX
tCAC
2
ta(CA)
Access time from column address
td(RLCL) = MAX
tCAA
3
ta(CP)
Access time from CAS high
td(RLCL) = MIN
tCAP
4
ta(R)
Access time from RAS
td(RLCL) = MIN
tRAC
5
ta(G)
Access time of
6
ta(SO)
Access time of SO from SC high
CL = 50 pF
tSCA
7
ta(SE)
Access time of SO from SE low
CL = 50 pF
tSEA
..................
..
...
9
tdis(CH)
Random output disable time from CAS high
(see Note 8)
CL = 100 pF
tOFF
0
20
10
tdis(G)
Random output disable time from TRG high
(see Note 8)
CL = 100 pF
tOEZ
0
11
tdis(SE)
Serial output disable time from SE high
(see Note 8)
CL = 50 pF
tSEZ
0
a from TRG low
tOEA
......•...
•••
...
....
\
:'.....
•...................
MIN
UNIT
MAX
55
65
ns
100
120
ns
25
30
ns
30
35
ns
20
25
ns
0
20
ns
20
0
20
ns
20
0
20
ns
..
..
..
t Numbering scheme intentionally skips numbers to allow for additional parameters specified in the SMJ44251A and SMJ44C251 data sheets.
NOTES: 7. Switching times assume CL = 100 pF unless otherwise noted (see Figure 2).
8. Disable times are specified when the output is no longer driven.
TEXAS . .
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9-127
z
o
fi
:E
a::
o
u.
Z
W
o
Z
~
c
-------
-.I
~I
~I
ta(R)
TEXAS ~
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9-131
SMJ44C250
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037 -
JANUARY 1991
early write cycle timing
~I~-----------------------tc~)------------------------~~I
________________---.!~I
I 14-1.. - - - - - - - - - - - - tw(RL)
------~~
I
~
Y1
I I~
~I -.II ~ tW
(RH)4
I '4---------------td(RLCH) - - - - - - - - - . . 1
tT
I
1
td(CLRH)
I
~I I
I
tw(CL)
~I ~td(CHRL) ~
I ~td(RLCL) ~III
r
IT
l
r
I
I II
~
',u(RA) ---:
I4- t h(RA)
i<-l- :"U(CA) --:
~
tsu(TRG)
N'
I ,
I
!+-1- th(RLCA)
I
AO·AB
,.
-.I I4-+-
'-41 f+- th(TRG)
~ 'II.-'tsu~;:rn;
r
}11
I I I
I I
, 1111 I
~I
I
tw(CH)
I4-l,
t;~1
:co:,umn
I
I
I
,
I I I
I , I
-+I
I I
I I
I I~
1·1
th(RWM)
W
~I 14-
I~
1111
I
I
I
I
,
I
,
I
I
I :
~
I4t
I
1
I
tsu~CH)
I
I
tsu~RH)
I
th(RL.:W)
I
th(CLW)
,III
i ~tsu~CL)
~I
~I
I
~I
~:
~II
~I-T----------------------~~~~~~
'I I
,
I~ I 'tw~L)
~I
I
tsu(OCL) -.I
~
th(ROQ) ~ 14I
'III
th(CLO)
~I
tsu(OOR)...,
I
I
I
:
, .. :
th_(_R_LO_)_-:_-_-_-_-_-_-_-_-_-_-_...,~~i
1____
OO~
3
NOTE 26: See "Write Cycle State Table" for the logic state of "1", "2", and "3",
TEXAS ~
INSlRUMENTS
9-132
---+l~1
~'----'_
I I
I I
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~
I
SMJ44C250
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037 -
JANUARY 1991
delayed write cycle timing
~14-------------------------tc~------------------------~~1
I *
-----N
.. - - - - - - - - - - - - - - - - -
tw(RL) __________________~.I
0
I I..
~I
I
I 1'4---------------td(RLCH) --------------~I -.I
IT ~ ~
10+14----------- td(CLRH) -------+-1--~.I
I I+- td(RLCL) -----~>!-----------
tsu(CA) --JoiII141---.t~1
I
--.I
I
AO-AS
....____
CO_lu_m_n__
~ th(CLCA)
~~
TEXAS •
INSlRUMENTS
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SMJ44C250
262144 BY 4-81T MULTIPaRT VIDEO RAM
SGMS037 -
hidden refresh cycle timing
~ Memory Cycle
tw(RH)
14
14
-r
1 tw(RL)
.:
Refresh Cycle
~I
~I
I 14
I I
~----~ I
tw(RH)
I
4
1111
~~ Refresh Cycle--.j
1tw(RL)
I
I
Ni
th(RA) 1
AO-AS
nI I
td(RLCH)
tw(CL)
1111
~I
"~
I
I
I
I
1 I
I
l+I- th(CLCA)
~ tsu(CA)
I+-t- I I
~I
I
:
-J -.!
JANUARY 1991
~
~HX~X·~::~
t ' l I ..
1
I
~th(RHrd)
I
~II
DO
TEXAS •
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9-141
SMJ44C250
262144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS037 -
JANUARY 1991
write-mode control pseudo write transfer timing
The write-mode control cycle is used to change the SOQs from the output mode to the input mode. This allows
serial data to be written into the data register. The diagram below assumes that the device was originally in the
serial read mode.
I~"---------- tc(TW) -----------+l~1
I
I I"
I
r-
----~N
td(RLCL)
~
II
I I"
i I
CAS
~
:
AO-AB
_
:
tsu(TRG)
TRG
1
i
I
SC
11!4- tw(CL) -+-j
i
: \1 l..
th(RA)
~I
:
I
1
-'-+I
Data
Out
1
I·
~1"---1~*I-td(THRL)
I
I
~ tsu(CA) ~
i ~gr2gH~
I
I
I
~th(RWM)
I I
~~~~~~~~~~~~~~~~~~~~~~
1
I:
14
I I"\\\\\\\~
II
I I
tw(SCL)
I I
SDa
th(CLCA)
~ tw(SCH) "41
14
~:
~
I
1~_ _ _ _ _-1I_ _ _ _-
i iT
I ;
}.
~th(TRG)
I
WE~:I
td(SCRL)
~:
td(RLCH)
7 \ 1' - -_ _
I
I
~o~ ~ ~Olumn ~Dzn*g_
tsulWMR) ~
I
'"
0
I
I4-r tsu(RA)
-+--+i
~
~
~
:
:
I :
I
I
I
~I
tw(RL)
I..
~l
td(RHSC)
0
I
~
I. -,
tsu(SDS) --.j
I I
td(SESC) --+4----+1
NOTES: 31. Random-mode Q outputs remain in the high-impedance state for the entire write-mode control.
32. SE must be high as RAS falls in order to perform a write-mode control cycle.
TEXAS •
INSlRUMENTS
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POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
~
\'-----_
-
roo-- th(SDS)
I
SMJ44C250
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037 -
JANUARY 1991
data register to memory timing, serial input enabled
I"
I ,..
tw(RL)
I l . - td(RLCL) ~
, ,
'I+-
I
AO-AB
f.t
th(RA) -.l
~
th(RLCA),
I
i
I ,
,.
,
"~I
I
,
,
'Vi
,_I
,! \.
:
I
2m2M : ~ow
tsu(TRG)
~I
i 4 - tw(CL)
, ,I
~
- . J '----
1'4--- tw(RH)
td(R~CH)
'
-"I.. - ...~I: ,
I
I
"..
11
I
,
1
i ,..
tsu(RA)
~,
:
--------~~
~I
,
tc(TW)
I
,
,
tsu(CA)'
,
~I'
.:
th(CLCA)
I
I
~ Column ~HnzgH_
-":"--';~I ',1+ th(TRG)
I
-.j
~I td(THRL)
-.j
~::~
"~
-I:" ~,,'"
7.
w~ ,:
~Hn~gH~
,
,..
~'th(RWM)
I
, ,
, ,
oQ
,
,
HI-Z -------+,---------I
,
, ,
-~ldJ--~h'.. ,
td(SCRL)"
I
sc
d,su(soS)!
"
th(SoS)
SoQ
~
td(RHSC)
~I' ,'"
I.
, ,
,
,
~,,
, ,
I,:
(see
No'. 32)
'w(SCl)
~---I--"'''-I
,
tw(SCH)
,
tsu(SoS) --.:
"1"--1~.r- th(SoS)
~
:
29( o~. ~ D~~a ~
I
tsu(SE)
-+l
I
14- th(SE) ~
~ td(SESC) ---l
~,
I
/
NOTES: 33. Random mode Q outputs remain in the high-impedance state for the entire data register to memory transfer cycle. This cycle is used
to transfer data from the data register to the memory array. Every one of the 512 locations in each data register is written into the
corresponding 512 columns of the selected row. Data in the data register may proceed from a serial shift-in or from a parallel load
from one of the memory array rows. The above diagram assumes that the device is in the serial write mode (i.e., SO is enabled by
a previous write mode control cycle, thus allowing data to be shifted-in).
34. Successive transfer writes can be performed without serial clocks for applications requiring fast memory array clears.
35 ..SC transitions are not allowed between RAS low and TRG high.
36. For multiple transfer write operation; a transfer read cycle needs to be done from the same row after the first transfer write is carried
out, then do multiple transfer write for subsequent rows. See parameters tc(TW)M and tc(RL)M'
TEXAS ~
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9-143
SMJ44C250
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037 -
JANUARY 1991
memory to data register transfer timing
AO-AS
w
~~
!
tw(SCH)
I
I
----,If
SC
I
th(SHSQ)
II
.
\
I
14
*
I
~: I
I
14
I
I
14
I
I
14
~~a'h~Z~
~I
~I
td(SCTR)
J.- ta(SQ) -+l
Old Data
SDQ
~
14
~ td(CLSH)
~I
td(RLSH)
/
\
I
I
~I
td(THSC)
-.l
11:
I
14
j4- ta(SQ)
tw(SCL)
X
Old Data
th(SHSQ)
14
Old Data
t
\"---__; !
c(SC)
I
----~~I
-+l
~I I
M1I";---N-c-w-D-a-t-a---
H
L
NOTES: 37. Random mode (Q outputs) remain in the high-impedance state for the entire memory to data register transfer cycle. The memory to
data register transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register
are written into from the 512 corresponding columns of the selected row. The data that is transferred into the data registers may be
either shifted out or transferred back into another row.
3S. Once data is transferred into the data registers, the SAM is in the serial read mode (Le., the SQ is enabled), thus allowing data to be
shifted out of the registers. Also, the first bit to be read from the data register after TRG has gone high must be activated by a positive
transition of SC.
TEXAS
~
INSTRUMENTS
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262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS037 -
JANUARY 1991
serial data-in timing
tc(SC)
1111
!.-- tw(SCL) - . !
sc
SOO
~
~I tsu(SOS)
~
r--
11
----+j J
~
Valid Data:
r
'\
.1
tw(SCH) - - . :
~ th(SOS)
tw(SCL)
i
Vi
f+---- tsu(SOS) --.J ~
~
~I
t
~ h(SOS)
1
~
Valid Data
I
~td(SESC)~
\{~:----------------------------------
The serial data-in cycle (SO) is used to input serial data into the data registers. Before data can be written into
the data registers via SO, the device must be put into the write mode by performing a write mode control, or
pseudo-transfer, cycle. Transfer write cycles occurring between the write mode control cycle and the subsequent
writing of data will not take the device out of the write mode. However, a transfer read cycle during that time will
take the device out of the write mode and put it into the read mode, thus disabling the input of data. Data will
be written starting at the location specified by the input address loaded on the previous transfer cycle.
While accessing data in the serial data registers, the state of TRG is a Don't Care as long as TRG is held high
when RAS goes low to prevent data transfers between memory and data registers.
serial data-out timing
tc(SC)
1111
I
~tw(SCL)-.l
.1
I+-- tw(SCH) - . ! I
I
I
Vi
sc~
~ th(SHSO) --.I
~tw(SCL)-.!
'\
~ta(SO) ~
SOO
\.
I
i+-- ta(SO) ~
x=
2(
(
Yr
1
-+!
SE
I+-
ta(SE)
~~:_________________________________________________________________
NOTE 10:
When the odd tap is used (tap addresses can be 0-511 , and odd taps are 1,3,5 ... etc.), the cycle time for SC in the first serial data
out cycle needs to be 70 ns minimum.
The serial data-out cycle is used to read data out of the data registers. Before data can be read via SQ, the device
must be put into the read mode by performing a transfer read cycle. Transfer write cycles occurring between
the transfer read cycle and the subsequent shifting out of data will not take the device out of the read mode. But
a write mode control cycle at that time will take the device out of the read mode and put it in the write mode, thus
not allowing the reading of data.
While accessing data in the serial data registers, the state of TRG is a Don't Care as long as TRG is held high
when RAS goes low to prevent data transfers between memory and data registers.
TEXAS
-1!1
INSTRUMENTS
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SMJ44C250
262 144 BY 4-BI1 MULTIPaRT VIDEO RAM
SGMS037 -
JANUARY 1991
TEXAS
-1!1
INSTRUMENTS
9-146
POST OFFICE BOX 1443
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SMJ44C251
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS038 -
• Military Operating Temperature Range
... -55°C to 125°C
JD Package t
(Top VIew)
• Class B High-Reliability Processing
JANUARY 1991
HJ Package t
(Top View)
VSS
• DRAM: 262 144 Words x 4 Bits
SAM: 512 Words x 4 Bits
SD01
TRG
DOD
D01
• Dual Port Accessibility-Simultaneous and
Asynchronous Access from the DRAM and
SAM Ports
IN
GND
RAS
A8
A6
AS
A4
• Bidirectional Data Transfer Function
Between the DRAM and the Serial Data
Register
• 4 x 4 Block Write Feature for Fast Area Fill
Operations. As Many as Four Memory
Address Locations Written Per Cycle from
an On-Chip Color Register
VCC
14
VSS
SD03
SD02
SE
D03
D02
DSF
CAS
OSF
AD
A1
A2
A3
A7
SD01
D01
IN
RAS
A6
AS
A4
VCC
14
15
SD03
SD02
SE
D03
D02
DSF
CAS
OSF
AD
A1
A2
A3
A7
tThis illustration is for pinout reference only.
• Write Per Bit Feature for Selective Write to
Each RAM I/O. Two Write Per Bit Modes to
Simplify System Design
~
w
PIN NOMENCLATURE
AO-AS
CAS
DQO-DQ3
SE
RAS
SC
SDQO-SDQ3
TRG
• Enhanced Page-Mode Operation for Faster
Access
• CAS-before-RAS and Hidden Refresh
Modes
• RAM Output Enable Allows Direct
Connection of DQ and Address Lines to
Simplify System Design
W
DSF
QSF
• Long Refresh Period ... 8 ms (Max)
VCC
VSS
GND
• Up to 33 MHz Uninterrupted Serial Data
Streams
• Split Serial Data Register for Simplified
Realtime Register Reload
:>
w
Address Inputs
Column Enable
DRAM Data In-Out / Write Mask Bit
Serial Enable
Row Enable
Serial Data Clock
Serial Data In-Out
TransferRegister / QOutput Enable
Write Mask Select / Write Enable
Special Function Select
Split Register Activity Status
5-V Supply
Ground
Ground (Important: Not connected
to internal VSS)
a:
a.
I-
U
:::l
C
o
a:
a.
• Performance Ranges:
ACCESS ACCESS ACCESS ACCESS
• 3-State Seriall/Os Allow Easy Multiplexing
of Video Data Streams
TIME
ROW
• 512 Selectable Serial Register Starting
Locations
TIME
• Texas Instruments EPICTM CMOS Process
• Packaging
-28-Pin Ceramic Sidebraze DIP (JD Suffix)
- 28-Pin Ceramic Small Outline J-Leaded
Chip Carrier (HJ Suffix)
VCC
TIME TOLERANCE
COLUMN SERIAL SERIAL
ADDRESS ENABLE
(MAX)
TIME
DATA
ENABLE
(MAX)
(MAX)
(MAX)
'44C251-1
ta(R)
100 ns
ta(C)
25 ns
ta(SC)
30 ns
ta(SE)
20 ns
'44C251-2
120 ns
30 ns
35 ns
25 ns
:1:5%
'44C251-10 100ns
25 ns
30 ns
20 ns
:1:10%
'44C251-12 120 ns
30 ns
35 ns
25 ns
:1:10%
:1:5%
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW documents contain Information on products In
the form.tlve or design phlse of developmenlCharacterlstic data and
other Ipeclfications are design goals. Tun Instruments reserves the
right to chlnge or discontinue these products without notice.
TEXAS
~
Copyright © 1990, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-147
SMJ44C251
262 144 BY 4·81T MULTIPORT VIDEO RAM
SGMS038 -
JANUARY 1991
description
.The SMJ44C251 Multiport Video RAM is a high-speed, dual-ported memory device. It consists of a dynamic
random-access memory (DRAM) organized as 262 144 words of 4 bits each, interfaced to a serial data register,
or Serial Access Memory (SAM), organized as 512 words of 4 bits each. The SMJ44C251 supports three basic
types of operation: random access to and from the DRAM, serial access to and from the serial register, and
bidirectional transfer of data between any row in the DRAM and the serial register. Except during transfer
operations, the SMJ44C251 can be accessed simultaneously and asynchronously from the DRAM and SAM
ports. During transfer operations, the 512 columns of the DRAM are connected to the 512 positions in the serial
data register. The 512 x 4 bit serial data register can be loaded from the memory row (transfer read), or else
the contents of the 512 x 4 bit serial data register can be written to the memory row (transfer write).
The SMJ44C251 is equipped with several features designed to provide higher system-level bandwidth and
simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel draw rates can
be achieved by the device's novel 4 x 4 Block Write mode. The Block Write mode allows four bits of data present
in an on-chip color data register to be written to any combination of four adjacent column address locations. As
many as 16 bits of data can be written to memory during each CAS cycle time. Also on the DRAM port, a write
mask register provides a persistent write-per-bit mode without repeated mask loading.
On the serial register, or SAM port, the SMJ44C251 offers a split register transfer read (DRAM to SAM) option
that enables realtime register reload implementation for truly continuous serial data streams without critical
timing reqUirements. The register is divided into a high half and a low half. While one half is being read out of
the SAM port, the other half can be loaded from the memory array. This new realtime register implementation
allows truly continuous serial data. For applications not requiring realtime register reload (for example, reloads
done during CRT retrace periods), the Single-register mode of operation is retained to simplify system design.
The SAM can also be configured in the input mode, accepting serial data from an external device. Once the serial
register within the SAM is loaded, its contents can be transferred to the corresponding column positions in any
row in memory in a single memory cycle.
""D
:c
o
c
c
(")
-I
""D
:IJ
The SAM port is designed for maximum performance. Data can be input to or accessed from the SAM at serial
rates up to 33 MHz. During the split-register mode of operation, internal Circuitry detects when the last bit position
is accessed from the active half of the register and immediately transfers control to the opposite half. A separate
output, designated QSF, is included to designate which half of the serial register is active at any given time.
:E
All address lines and data-in are latched on-chip to simplify system design. All data-outs are unlatched to allow
greater system flexibility.
m
S
m
The SMJ44C251 employs state-of-the-art Texas Instruments EPIC™ scaled-CMOS, double level
polysilicon/polycide gate technology for very high performance combined with low cost and improved reliability.
The SMJ44C251 is offered in a 28-pin, ceramic small-outline J-Ieaded package (HJ suffix) for direct surface
mounting in rows on 400-mii centers. It is also offered in a 400-mil, 28-pin, sidebrazed DIP package (JD suffix).
Both packages are characterized for operation from - 55°C to 125°C (M suffix).
The SMJ44C251 and other multiport video RAMs are supported by a broad line of graphics processors and
control devices from Texas Instruments, including the SMJ3401 0 and SMJ34020 Graphics System Processors.
TEXAS •
INSTRUMENTS
9-148
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
SMJ44C251A
262144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS039 -
• Military Operating Temperature Range
... - 55°C to 125°C
HJ Package
(Top View)
JD Package
(Top View)
SC
SDOO
SD01
TRG
DOO
D01
• Class B High-Reliability Processing
• DRAM: 262 144 Words x 4 Bits
SAM: 512 Words x 4 Bits
• Dual Port Accessibility - Simultaneous
and Asynchronous Access from the DRAM
and SAM Ports
SD03
SD02
SE
D03
D02
DSF
CAS
NC
AO
A1
A2
A3
A7
W
• Bidirectional Data Transfer Function
Between the DRAM and the Serial Data
Register
• 4 x 4 Block Write Feature for Fast Area Fill
Operations. As Many as Four Memory
Address Locations Written Per Cycle From
an On-Chip Color Register
SC
SDOO
SD01
TRG
DOO
D01
VSS
GND
RAS
A8
A6
A5
A4
VCC
JANUARY 1991
VSS
SD03
SD02
SE
D03
D02
DSF
CAS
NC
AO
A1
A2
A3
A7
W
GND
RAS
A8
A6
A5
A4
VCC
• Write-Per-Bit Feature for Selective Write to
Each RAM I/O
AO-AS
CAS
DQO-DQ3
• Enhanced Page Mode Operation for Faster
Access
RAS
SC
SDQO-SDQ3
TRG
• CAS-before-RAS and Hidden Refresh
Modes
• RAM Output Enable Allows Direct
Connection of DQ and Address Lines to
Simplify System Design
W
DSF
VCC
VSS
GND
• Long Refresh Period ... Every 8 ms (Max)
• Up to 33 MHz Uninterrupted Serial Data
Streams
NC
•
• 3-State Serial 1/05 Allow Easy Multiplexing
of Video Data Streams
:2E
a:
o
u.
z
w
u
z
~
c
«
ACCESS
ACCESS
ACCESS
ACCESS
TIME
TIME
TIME
TIME
ROW
COLUMN
SERIAL
SERIAL
DATA
ENABLE
ADDRESS
ENABLE
(MAX)
(MAX)
(MAX)
(MAX)
fa(R)
fa(C)
ta(SC)
ta(SE)
• Texaslnstruments EPIC ™ CMOS Process
• Packaging Options:
- 28-pin Ceramic Sidebraze DIP (JD suffix)
- 28-pin Ceramic Small Outline J-Leaded
Chip Carrier (HJ Suffix)
!;:
Address Inputs
Column Enable
DRAM Data In-OuWJrite Mask Bit
Serial Enable
Row Enable
Serial Data Clock
Serial Data In-Out
Transfer Register/Q Output Enable
Write Mask SelecWJrite Enable
Special Function Select
5-V Supply
Ground
Ground (Important: not connected
internally to VSS)
No Connection
Performance Ranges:
• 512 Selectable Serial Register Starting
Locations
VCC
TOLERANCE
±5%
'44C251A-1
100 ns
25 ns
30 ns
20 ns
'44C251A-2
120 ns
30 ns
35 ns
25 ns
±5%
'44C251A-10 100 ns
25 ns
30 ns
20 ns
±10%
'44C251A-12 120 ns
30 ns
35 ns
25 ns
±10%
NOTE: All references to the SMJ44C251A-10, -1 are Advance
Information only.
EPIC is a trademark of Texas Instruments Incorporated.
This document contains Information on products In more
than one phase of development. The status of each device Is
Indicated on the pagels) specifying Its electrical
characteristics.
TEXAS
ll}
Copyright © 1991, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
z
o
-
PIN NOMENCLATURE
9-149
SMJ44C251A
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS039 -
JANUARY 1991
description
The SMJ44C251A multiport video RAM is a high speed, dual ported memory device. It consists of a dynamic
random-access memory (DRAM) organized as 262 144 words of 4 bits each interfaced to a serial data register,
or Serial Access Memory (SAM), organized as 512 words of 4 bits each. The SMJ44C251 A supports three basic
types of operation: random access to and from the DRAM, serial access to and from the serial register, and
bidirectional transfer of data between any row in the DRAM and the serial "register. Except during transfer
operations, the SMJ44C251 A can be accessed simultaneously and asynchronously from the DRAM and SAM
ports. During a transfer operation, the 512 columns of the DRAM are connected to the 512 positions in the serial
data register. The 512 x 4 bit serial data register can be loaded from the memory row (transfer read) or else the
contents of the 512 x 4 bit serial data register can be written to the memory row (transfer write).
The SMJ44C251A is equipped with several features designed to provide higher system-level bandwidth and
simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel draw rates can
be achieved by the device's 4 x 4 Block Write mode. The Block Write mode allows four bits of data present in
an on-chip color data register to be written to any combination of four adjacent column address locations. As
many as 16 bits of data can be written to memory during each CAS cycle time.
On the serial register, or SAM port, the SMJ44C251A offers a single register mode of operation for simplified
memory design. The SAM can be configured in input mode, accepting serial data from an external device; or
data can be accessed from the SAM at serial rates up to 33 MHz. Once the serial register within the SAM is
loaded, it's contents can be transferred to the corresponding column positions in any row in memory in a single
memory cycle.
All the address lines and data-in are latched on chip to simplify design. All data-outs are unlatched to allow
greater system flexibility.
The SMJ44C251A is offered both in a 28-pin 400-mil dual-in line ceramic sidebraze package (JD suffix) for
through-hole row insertion, and in a 28-pin ceramic small outlline J-Ieaded chip carrier package (HJ suffix) for
surface-mount applications. The L suffix device is tested for operation from O°C to 70°C. The M suffix device
is tested for operation from - 55°C to 125°C.
The SMJ44C251 A and other SMJ44C25X multiport Video RAMs are supported by a broad line of video/graphic
processors from Texas Instruments, including the SMJ3401 0 and SMJ34020 Graphics System Processors.
NOTE: All references to the SMJ44C251A-10, -1 are Advance Information only.
TEXAS
~
INSTRUMENTS
9-150
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ44C251A
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS039 -
JANUARY 1991
functional block diagram
..-0 vcc
..-0 vss
000
001
002
003
..-0
..-0
..-0
..-0
..-0
..-0
..-0
..-0
..-0
AO
A1
A2
A3
A4
AS
A6
A7
AB
OSF
e
0
f u
r n
e t
5 e
h r
sooo 0-+-1--1-.
S001
S002
S003
G
T e
I n
me
I r
a
n t
9 0
..-0 RAS
..-0 CAS
..-0 TRG
..-0 Vi
..-0 sc
..-0 SE
Detailed Pin Description vs Operational Mode
TRANSFER
DRAM
PIN
AO-AB
Row, Column Address
Row, Tap Address
CAS
Column Enable, Output Enable
Tap Address Strobe
DOi
DRAM Data I/O, Write Mask Bits
DSF
SAM
Alternate Write Transfer Enable
Block Write Enable
Color Register Load Enable
RAS
Row Enable
Row Enable
Serial-In Mode Enable
SE
Serial Enable
Serial Clock
SC
Serial Data I/O
SDOi
TRG
a Output Enable
Transfer Enable
W
Write Enable, Write per Bit Select
Transfer Write Enable
VCC
5-V Supply (typical)
VSS
GND
System Ground (Important: not connected internally to VSS)
NC
Make no external connection
Device Ground
TEXAS ~
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-151
SMJ44C251A
262144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS039 - JANUARY 1991
operation
random access operation
Refer to Table 1, Function Table (page 9-156), for random-access and transfer operations. Random-access
operations are denoted by the designator "R" and transfer operations are denoted by a " T."
transfer register select and DQ enable (TRG)
The TRG pin selects either register or random-access operation as RAS falls. For random-access (DRAM)
mode, TRG must be held high as RAS falls. Asserting TRG high as RAS falls causes the 512 storage elements
of each data register to remain disconnected from the corresponding 512-bit lines of the memory array.
(Asserting TRG low as RAS falls connects the 512-bit positions in the serial register to the bit lines and indicates
that a transfer will occur between the data registers and the selected memory row. See Transfer Operation for
details.)
During random-access operations, TRG also functions as an output enable for the random (0) outputs.
Whenever TRG is held high, the 0 outputs are in the high-impedance state to prevent an overlap between the
address and DRAM data. This organization allows the connection of the address lines to the data I/O lines but
prohibits the use of the early write cycle. It also allows read-modify-write cycles to be performed by providing
a three-state condition to the common I/O pins so that write data can be driven onto the pins after output read
data has been externally latched.
address (AD through AS)
Eighteen address bits are required to decode 1 of 262 144 storage cell locations. Nine row address bits are set
up on pins AO through A8 and latched onto the chip on the falling edge of RAS. Then, the nine column address
bits are set up on pins AD through A8 and latched onto the chip on the falling edge of CAS. All addresses must
be stable on or before the falling edges of RAS and CAS.
RAS and CAS address strobes and device control clocks
RAS is a control input that latches the states of the row address, W, TRG, SE, CAS, and DSF onto the chip to
invoke the various DRAM and Transfer functions of the SMJ44C251 A. RAS is similar to a chip enable in that
it activates the sense amplifiers as well as the row decoder. CAS is a control input that latches the states of the
column address and DSF to control various DRAM and Transfer functions. CAS also acts as an output enable
for the DRAM output pins.
special function select (DSF)
The SpeCial Function Select input is latched on the falling edges of RAS and CAS, similarly to an address, and
serves two functions.
First the DSF pin is used to load an on-chip four-bit data, or "color," register via the Load Color Register cycle.
The contents of this register can subsequently be written to any combination of four adjacent column memory
locations using the 4 x 4 Block Write feature. The Load Color Register cycle is performed using normal write
cycle timing except that DSF is held high on the falling edges of RAS and CAS. Once the color register is loaded,
it retains data until power is lost or until another Load Color Register cycle is performed.
TEXAS
lJ1
INSTRUMENTS
9-152
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ44C251A
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS039 - JANUARY 1991
After loading the color register, the Block Write cycle can be enabled by holding DSF high on the falling edge
of CAS. During Block Write cycles, only the seven most significant column addresses (A2-A8) are latched on
the falling edge of CAS. The two least significant addresses (AD-A 1) are replaced by the four DO bits, which are
also latched on the later of CAS or W falling. These four bits are used as an address mask and indicate which
of the four column address locations addressed by A2-A8 will be written with the contents of the color register
during the write cycle, and which ones will not. DOD enables a write to column address A 1 = low, AD = low; 001
enables a write to A 1 = low, AD = high; D02 enables a write to A 1 = high, AD = low; and D03 enables a write
to A 1 =high, AD =high. A logic high level enables a write and a logic low level disables the write. A maximum
of 16 bits can be written to memory during each CAS cycle (see Figure 1, Block Write Diagram).
Second, the DSF pin is used to provide an alternate method of performing a transfer write. The alternate transfer
write is described in the transfer write enable (W) paragraph of this specification.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-153
SMJ44C251A
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS039 -
JANUARY 1991
000
001
002
003
I
I
I
RAS
h
I
CAS
I
\
AD-AS
W
TRG
OSF
~~
~
BY W
I
I
Block Write Cycle
(Load and Use DO Mask)
Block Write Cycle.
(No DO Mask)
Load Color Register Cycle
I
I
\
I
I
\
•
3
W
~
I
I
I
•
~
~
t DOO-D03 (CAS) are latched on the later of W or CAS falling edge. DOO-D03 (RAS) are latched on RAS falling edge.
Legend:
1.
Refresh Address
2.
Row Address
3.
Block Address (A2-A8)
4.
Color Register Data
5.
Column Mask Data
6.
DO Mask Data
~ '" Don't Care
TEXAS .,.,
INSlRUMENTS
9-154
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
3
~
~I
I
/#II;f
000-003t
Figure 1. Block Write Diagram
Ii
\
W
/#II;f
n
\
~
~
I
I
I
~
SMJ44C251A
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS039 -
write enable, write-per-bit enable
JANUARY 1991
(W)
The W pin enables data to be written to the DRAM and is also used to select the DRAM write per bit mode of
operation. A logic level high on the W input selects the read mode and logic low level selects the write mode.
In an early write cycle, Vii is brought low before CAS and the DRAM output pins (DO) remain in the
high-impedance state for the entire cycle. During DRAM write cycles, holding Vii low on the falling edge of RAS
will invoke the write-per-bit operation.
When Vii = low on the falling edge of RAS, the write mask is reloaded. Accordingly, a four-bit binary code (the
write-per-bit mask) is input to the device via the random DO pins and is latched on the falling edge of RAS. The
write-per-bit mask selects which of the four random I/Os are written and which are not. After RAS has latched
the write mask on-chip, input data is driven onto the DO pins and is latched on the falling edge of the later of
CAS or W. If a low was strobed into a particular I/O pin on the falling edge of RAS, data will not be written to
that I/O. If a high was strobed into a particular I/O pin on the falling edge of RAS, data will be written to that I/O.
See the corresponding timing diagrams for details. IMPORTANT: The write-per-bit operation is invoked only if
W is held low on the falling edge of RAS. IfW is held high on the falling edge of RAS, write-per-bit is not enabled
and the write operation is identical to that of standard x 4 DRAMs.
data I/O (000-003)
DRAM data is written during a write or read-modify-write cycle. The falling edge of Vii strobes data into the on-chip
data latches. In an early write cycle, Vii is brought low prior to CAS and the data is strobed in by CAS with data
setup and hold times referenced to this signal. In a delayed write or read-modify-write cycle, CAS will already
be low. Thus, the data will be strobed-in by Vii with data setup and hold times referenced to this signal.
The three-state output buffers provide direct TTL compatability (no pull-up resistors required) with a fanout of
two Series 74/54 TTL loads. Data-out is the same polarity as Data-in. The outputs are in the high impedance
(floating) state as long as CAS or TRG is held high. Data will not"appear at the outputs until after both CAS and
TRG have been brought low. Once the outputs are valid, they remain valid while CAS and TRG are low. CAS
or TRG going high returns the outputs to a high-impedance state. In an early write cycle, the outputs are always
in the high-impedance state. In a register transfer operation (memory-to-register or register-to-memory), the
outputs remain in the high-impedance state for the entire cycle.
enhanced page mode
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the SMJ44C251 A to operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as column address is valid rather than when
CAS transitions low. This performance improvement is referred to as enhanced page mode. Valid column
address may be presented immediately after row address hold time has been satisfied, usually well in advance
of the falling edge of CAS. In this case, data is obtained after ta(C) max (access time from CAS low), if ta(CA)
max (access time from column address) has been satisfied. In the event that column addresses for the next page
cycle are valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence
of ta(C) or ta(CP) (access time from rising edge of CAS).
Enhanced page mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row address setup, row address hold, and address multiplex is thus
eliminated, and a memory cycle time reduction of up to 3 x can be achieved, compared to minimum RAS cycle
times. The maximum number of columns that may be accessed is determined by the maximum RAS low time
and page mode cycle time used. The SMJ44C251 A allows a full page (512 cycles) of information to be accessed
in read, write, or read-modify-write modes during a single RAS low period using relatively conseNative page
mode cycle times.
During write-per-bit operations, the DQ pins are used to load the write-per-bit mask register described above
under the W pin description.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
9-155
SMJ44C251A
262 144 BY 4-BIT MULTIPORT VIDEO RAM
SGMS039 -
JANUARY 1991
During block write operations, the DQ pins are used to load· the on-chip color register during the load color
register cycle and are also used as a write enable during Block Write cycles.
refresh
A refresh operation must be performed on each row at least once every eight milliseconds to retain data. Since
the output buffer is in the high-impedance state (unless CAS is applied), the RAS-only refresh sequence avoids
any output during refresh. Strobing each of the 512 row addresses with RAS causes all bits in each row to be
refreshed. CAS can remain high (inactive) for this refresh sequence to conserve power.
CAS-before-RAS refresh
CAS-before-RAS refresh is accomplished by bringing CAS low earlier than RAS. The external row address is
ignored and the refresh address is generated internally.
GND(PIN 8)
This pin is reserved for the manufacturer's test operation. It is an input and should be tied to system ground
to ensure proper device operation.
IMPORTANT: GND is not connected internally to
Vss.
Table 1. Function Table
T
CAS
RAS FALL
Y
P
Et
000-3
ADDRESS
FALL
CAS
TRG
W
DSF
FUNCTION
SE
DSF
RAS
CAS
RAS
CAS*
W
R
L
.X§
X
X
X
X
X
X
X
X
CAS-before-RAS refresh
T
H
L
L
X
L
X
Row
Addr
Tap
Point
X
X
Register to memory transfer
(Transfer Write)
T
H
L
L
H
X
X
~ow
Addr
Tap
Point
X
X
Alternate Transfer Write
(independent of SE)
T
H
L
L
L
H
X
Refresh
Addr
Tap
Point
X
X
Serial Write-mode enable
(pseudo-Transfer Write)
T
H
L
H
L
X
X
Row
Addr
Tap
Point
X
X
Memory to register transfer
(Transfer Read)
R
H
H
L
L
X
L
Row
Addr
Col
Addr
Write
Mask
Valid
Data
Load and use write mask,
write data to DRAM
R
H
H
L
L
X
H
Row
Addr
Col
A2-A8
Write
Mask
Addr
Mask
Load and use write mask,
Block Write to DRAM
R
H
H
H
L
X
L
Row
Addr
Col
Addr
X
Valid
Data
Normal DRAM read/write
(non masked)
R
H
H
H
L
X
H
Row
Addr
Col
A2-A8
X
Addr
Mask
Block Write to DRAM
(non masked)
R
H
H
H
H
X
H
Refresh
Addr
X
X
Color
Data
Load color register
t R = Random access operation; T =Transfer operation.
* DOO-3 are latched on the later of Wor CAS falling edge.
§ X = Don't care.
Addr Mask = 1; write to address location enabled.
Write Mask = 1; write to I/O enabled.
TEXAS -1.!1
INSTRUMENTS
9-156
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ44C251A
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS039 - JANUARY 1991
random port to serial port interface
Random-Access Port
Col
Col
511
o
Row
o
Memory Array
262144 Bits
DQ
Row
511
Transfer
Control
Logic
512 Bit Data Register
SC
AO-AB
Figure 2. Block Diagram Showing One Random and One Serial I/O Interface
random-address space to serial-address space mapping
The 512 bits in each of the four data registers of the SAM are connected to the 512 column locations of each
of the four random I/Os. Data can be accessed in or out of the SAM starting at any of the 512 data bit locations.
This start location is selected by addresses AD through A8 on the falling edge of CAS during any transfer cycle.
The SAM is accessed starting from the selected start address, proceeding from the lowest to the highest
significant bits. After the most significant bit position (511) is accessed, the serial counter wraps around such
that bit D is accessed on the next clock pulse. The selected start address is stored and used for all subsequent
transfer cycles until CAS is again brought low during any transfer cycle. Thus, the start address can be set once
and CAS held high during all subsequent transfer cycles and the start address point will not change regardless
of data present on AD through A8.
TEXAS
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transfer operations
As illustrated in Table 1, the SMJ44C251A supports four basic transfer modes of operation:
1'.
Normal Write Transfer (SAM to DRAM)
2.
Alternate Write Transfer (independent of the state of SE)
3.
Pseudo Write Transfer (switches serial port from serial out mode to serial in mode. No actual data
transfer takes place between the DRAM and the SAM.)
4.
Normal Read Transfer (transfer entire contents of DRAM to SAM)
transfer register select (TRG)
Transfer operations between the memory array and the data registers are invoked by bringing TRG low before
RAS falls. The states of W, SE, and DSF, which are also latched on the falling edge of RAS, determine which
transfer operation will be invoked. (See Table 2.)
During read transfer cycles, TRG going high causes the addressed row of data to be transferred into the data
register. Although the previous data in the data register is overwritten, the last bit of data appearing at SDO before
TRG goes high will remain valid until the first positive transition of SC after TRG goes high. The data at SDO
will then switch to new data beginning from the selected start, or tap, position.
transfer write enable (W)
In the register transfer mode, W determines whether a read or a write transfer will occur. To perform a write
transfer, Wand SE are held low as RAS falls. If SE is high during this transition, no transfer of data from the data
register to the memory array occurs, but the SDOs are put into the input mode. This allows serial data to be input
into the SAM. An alternative way to perform the transfer write cycle is by holding DSF high on the falling edge
of RAS. In this way, the state of SE is a Don't Care as RAS falls. To perform a read transfer operation, W is held
high and SE is a Don't Care as RAS falls. This cycle also puts the SDOs into the read mode, allowing serial data
to be shifted out of the data register. (See Table 2.)
column enable (CAS)
If CAS is brought low during a control cycle, the address present on the pins AO through AS will become the new
register start location. If CAS is held high during a control cycle, the previous tap address will be retained from
the last transfer cycle in which CAS went low to set the tap address.
addresses (AO through AS)
Nine address bits are required to select one of the 512 possible rows involved in the transfer of data to or from
the data registers. The states of AO-AS are latched on the faliling edge of RAS to select one of 512 rows for the
transfer operation.
To select one of the 512 positions in the SAM from which the first serial data will be accessed, the appropriate
9-bit column address (AO-AS) must be valid when CAS falls. However, the CAS and start (tap) pOSition need
not be supplied every cycle, only when changing to a different start position.
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special function input (OSF)
In the write transfer mode, holding DSF high on the falling edge of RAS permits use of an alternate mode of
transfer write. This mode allows SE to be high on the falling edge of RAS without permitting a pseudo write
transfer, with the serial port disabled during the entire transfer write cycle.
serial access operation
Refer to Tables 2 and 3 for the following discussion on serial access operation.
serial clock (SC)
Data (SDO) is accessed in or out of data registers on the rising edge of SC. The SMJ44C251A is designed to
work with a wide range of clock duty cycles to simplify system design. Since the data registers comprising the
SAM are of static design, there are no SAM refresh requirements and there is no minimum SC clock operating
frequency.
serial data input/output (SOQO-SOQ3)
SD and SO share a common I/O pin. Data is input to the device when SE is low during write mode and data is
output from the device when SE is low during read mode. The data in the SAM will be accessed in the direction
from least significant bit to most significant bit. The data registers operate modulo 512. Thus, after bit 511 is
accessed, the next bits to be accessed will be bits 00, 01, 02, and so on.
serial enable (SE)
The Serial Enable pin has two functions: first, it is latched on the falling edge of RAS, with both TRG and W low
to select one ofthe transfer functions (see Table 2). If SE is low during this transition, then a transfer write occurs.
If SE is high as RAS falls and DSF is low, then a write mode control cycle is performed. The function of this cycle
is to switch the SDOs from the output mode to the input mode, thus allowing data to be shifted into the data
register. NOTE: All transfer read and serial mode enable (pseudo transfer write) operations will perform a
memory refresh operation on the selected row.
Second, during serial access operations, SE is used as an SDO enable/disable. In the write mode, SE is used
as an input enable. SE high disables the input and SE low enables the input. To take the device out of the write
mode and into the read mode, a transfer read cycle must be performed. The read mode allows data to be
accessed from the data register. While in the read mode, SE high disables the output and SE low enables the
output.
IMPORTANT: While SE is held high, the serial clock is NOT disabled. Thus, external SC pulses will increment
the internal serial address counter regardless of the state of SE. This ungated serial clock scheme minimizes
access time of serial output from SE low since the serial clock input buffer and the serial address counter are
not disabled by SE.
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Table 2. Transfer Operation Logic
TRG
W
SE
DSF
MODE
L
L
L
L
X
L
L
X
H
L
H
L
L
H
X
L
Register to memory (write) transfer
Alternate register to memory transfer
Serial write mode enable
Memory to register (read) transfer
NOTE: Above logic states are assumed valid on the falling edge of RAS.
Table 3. Serial Operation Logic
LAST TRANSFER CYCLE
Alternate register to memory
Serial write mode enable t
Serial write mode enable t
Memory to register
Memory to register
SE
SDa
H
L
H
L
H
Input Disabled
Input Enable
Input Disable
Output Enabled
Hi-Z
tPseudo transfer write
powerup
To achieve proper device operation, an initial pause of 200 I-ls is required after power-up, followed by a minimum
of eight RAS cycles or eight CAS-before-RAS cycles, a memory-to-register transfer cycle and two SC cycles.
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absolute maximum ratings over operating free-air temperature t
Voltage on any pin except DO and SDO (See Note 1) .................................... - 1 V to 7 V
Voltage on DO and SDO (see Note 1) ................................................. - 1 V to Vee
Voltage range on Vee (see Note 1) ..................................................... a V to 7 V
Short circuit output current (per output) ..................................................... 50 mA
Power dissipation .......................................................................... 1 W
Operating temperature range ..................................................... - 55°C to 125°C
Storage temperature range ....................................................... - 65°C to 150°C
t Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
VCC
VSS
S
It
I
upp Y vo age
I SMJ44C251A-1, SMJ44C251A-2
I SMJ44C251A-10, SMJ44C251A-12
MIN
NOM
MAX
4.75
5
5.25
4.5
5
5.5
Supply voltage
UNIT
V
V
0
VIH
High-level input voltage
3.5
VCC
V
VIL
Low-level input voltage (see Note 2)
-1
0.5
V
TA
Operating free-air temperature
TC
Operating case temperature
125
°c
°c
-55
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
z
o
~
~
a::
o
LL.
Z
W
U
Z
~
c
2::;
..
30
ns
60
ns
o
LL
65
ns
120
ns
...., . . , ·····25
30
ns
......• '..•. 30
35
ns
20
25
ns
.:.
...
'
.
:E
...•... ·"'100
,
tOEZ
~
:....
20
0
20
ns
0
20
0
20
ns
20
0
20
ns
.
.. '
Serial output disable time from SE high
(see Note 8)
CL = 50 pF
0
tSEZ
.
t Numbering scheme intentionally skips numbers to allow for additional parameters specified in the SMJ44C251 data sheet.
NOTES: 7. Switching times assume CL = 100 pF unless otherwise noted (see Figure 3).
8. Disable times are specified when the output is no longer driven.
ADVANCE INFORMATION documents contain information
~~vne~;p~~~~Ct~~~!~~e~i·s~~I~na~.o~~~e~~~~~~~~~if;~:t~~~:
are subject to thange without notice.
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~
UNIT
MAX
. .•• ,:.'. . . . '.55
I. .,'
..
MIN
..,
...,. , :.,
..
tOEA
..
Z
0
9-163
a:
Z
W
U
Z
~
c
«
SMJ44C251A
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS039 -
JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating temperature t
NO.
ALT.
SYMBOL
PARAMETER
SMJ44C251A-1
SMJ44C251A-10
MIN
»c
~
z
o
m
z
."
o
-
JJ
s:
~
o
z
MAX
SMJ44C251A-2
SMJ44C251 A-12
MIN
UNIT
MAX
12
tc(rd)
Read cycle time (see Note 9)
tRC
190
220
ns
13
tc(W)
Write cycle time
twc
190
220
ns
14
tc(rdW)
Read-modify-write cycle time
tRWC
250
290
ns
15
tc(P)
Page-mode read, write cycle time
tpc
60
70
ns
16
tc(RDWP)
Page-mode read-modify-write cycle time
tRWC
105
125
ns
17
tc[[RDl
Transfer read cycle time
tRC
190
220
ns
!wc
ns
18
tc(TW)
Transfer write cycle time
18a
tc(TW)M
Transfer write cycle time, multiple transfer operation
19
tc(SC)
Serial clock cycle time (see Note 10)
tscc
20
tw(CH)
Pulse duration, CAS high
21
tw(CL)
Pulse duration, CAS low (see Note 11)
22
tw(RH)
Pulse duration, RAS high
23
tWiRL)
Pulse duration, RAS low (see Note 12)
tw(RL)M
Pulse duration, RAS low, multiple transfer write operation
23a
24
tw(WL)
Pulse duration, W low
25
tw(TRG)
Pulse duration, TRG low
26
tw(SCH)
Pulse duration, SC high
27
tw(SCL)
Pulse duration, SC low
28
tsu(CA)
Column address setup time
190
220
320
350
ns
30
35
ns
tcp
20
tCAS
25
tRP
80
tRAS
100
30
75000
30
ns
75000
75000
120
195
185
ns
ns
90
75000
ns
ns
25
ns
25
30
ns
tsc
10
12
ns
tscp
10
12
ns
tASC
0
0
ns
0
0
ns
0
0
ns
0
ns
twp
29
tsu(SFC)
DSF setup time before CAS low
30
tsu(RA)
Row address setup time
tASR
31
25
..
...
tsu(WMR)
W setup time before RAS low
tWSR
0
32
tsu(DOR)
DO setup time before RAS low (write mask operation)
tMS
0
0
ns
33
tsu(TRG)
TRG setup time before RAS low
tTLS
0
0
ns
tESR
34
tsu(SE)
SE setup time before RAS low (see Note 22)
35
tsu(SFR)
DSF setup time before RAS low
0
0
ns
0
0
ns
36
tsu(DCL)
Data setup time before CAS low
tDSC
37
tsu(DWL)
Data setup time before W low
tDSW
0
0
ns
0
0
38
tsu(rd)
Read command setup time
tRCS
ns
0
0
39
tsu(WCL)
Early write command setup time before CAS low
ns
twcs
-5
-5
40
tsu(WCH)
ns
Write setup time before CAS high
tCWL
25
30
41
ns
tsu(WRH)
Write setup time before RAS high
tRWL
25
30
42
ns
tsu(SDS)
SO setup time before SC high
tSDS
3
3
ns
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 9. All cycle times assume tt = 5 ns.
10. When the odd tap is used (tap address can be 0-511, and odd taps are 1,3,5, etc.), the cycle time for SC in the first serial data out
cycle needs be 70 ns minimum.
11. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user's transition times, this may require
additional CAS low time [tw(CL)J.
12. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user's transition times, this may require
additional RAS low time [tw(RL)J.
ADVANCE INFORMATION documenls contain Informalion
on new products in Ihe sampling or preproduction phase of
developmenl. Characlerislic dala and olher specificalions
are sublectlo change wilhout notice.
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timing requirements over recommended ranges of supply range and operating temperature
(continued)t
NO.
SMJ44C251A·1
SMJ44C251A-10
ALT.
SYMBOL
PARAMETER
43
th(CLCA)
Column address hold time after CAS low
44
th(SFC)
DSF hold time after CAS low
45
th(AA)
Aow address hold time after AAS low
46
th(TAG)
TAG hold time after AAS low
47
th(SE)
MIN
MAX
S MJ44C251 A·2
S MJ44C251 A-12
MIN
UNIT
MAX
20
20
ns
20
. 20
ns
tAAH
15
15
ns
tTLH
15
15
ns
SE hold time after AAS low (see Note 22)
tAEH
15
15
ns
tAWH
15
15
ns
tMH
15
15
ns
15
15
ns
tAA
45
45
ns
tCAH
48
th(AWM)
W hold time after AAS low
49
th(ADO)
DO hold time after AAS low (write mask operation)
50
th(SFA)
DSF hold time after AAS low
51
th(ALCA)
Column address hold time after AAS low (see Note 13)
52
th(CLD)
Data hold time after CAS low
53
th(RLD)
Data hold time after RAS low (see Note 13)
54
th(WLD)
Data hold time after W low
55
th(CHrd)
Read hold time after CAS (see Note 14)
tRCH
56
th(AHrd)
Read hold time after RAS (see Note 14)
tRRH
57
th(CLW)
Write hold time after CAS low
tWCH
tOH
20
25
ns
tDHR
45
50
ns
tOH
20
25
ns
0
0
ns
10
10
ns
30
35
ns
z
o-
58
th(ALW)
Write hold time after AAS low (see Note 13)
tWCA
50
55
ns
59
th(SDS)
SO hold time after SC high
tSDH
5
5
ns
60
th(SHSO)
sa hold time after SC high
tSOH
5
5
ns
~
a
0:
o
lJ.
61
td(RLCH)
Delay time, AAS low to CAS high
tCSH
100
120
ns
Z
62
td(CHAL)
Delay time, CAS high to RAS low
tCAP
0
0
ns
63
td(CLAH)
Delay time, CAS low to RAS high
tASH
25
30
ns
.
64
td(CLWL)
Delay time, CAS low to W low (see Notes 15 and 16)
tCWD
55
65
td(RLCL)
Delay time, RAS low to CAS low (see Note 17)
tRCO
25
65
75
25
ns
90
ns
66
td(CAAH)
Delay time, column address to AAS high
tAAL
50
60
ns
67
td(RLWL)
Delay time, RAS low to W low (see Note 15)
tAWD
130
155
ns
68
td(CAWL)
Delay time, column address to W low (see Note 15)
tAW 0
85
100
ns
69
td(ALCH)A
Delay time, AAS low to CAS high (see Note 18)
tCHA
25
25
ns
70
td{CLAL)R
Delay time, CAS low to RAS low (see Note 18)
tCSR
10
10
ns
71
td(AHCL)A
Delay time, AAS high to CAS low (see Note 18)
tAPC
10
10
ns
72
td(CLGH)
Delay time, CAS low to TAG high
tCTH
25
30
ns
73
td(GHD)
Delay time, TRG high before data applied at DO
(see Note 15)
25
30
ns
74
tdIALTH)
Delay time, AAS low to TRG high
90
95
ns
tRTH
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 13. The minimum value is measured when td(ALCL) is set to td(ALCL) min as a reference.
14. Either th(AHrd) or th(CHrd) must be satisfied for a read cycle.
15. Read-modify-write operation only.
16. TAG must disable the output buffers prior to applying data to the DO pins.
17. Maximum value specified only to guarantee RAS access time.
18. CAS-before-AAS refresh operation only.
ADVANCE INFORMATION documenls conlain Inlormalion
on new producls In Ihe sampling or preproduction phase 01
development. Characlerislic dala and olher spec iii cations
are subjecllo change wilhoul nolice.
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U
Z
~
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«
SMJ44C251A
262144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS039 -
JANUARY 1991
timing requirements over recommended ranges of supply voltage and operating temperature
(concluded)t.
ALT.
SYMBOL
PARAMETER
NO.
SMJ44C251A-1
SMJ44C251A'-10
MAX
MIN
.
»c
~
z
n
m
-z
""T1
o
:c
s:
-o~
z
SMJ44C251A-2
SMJ44C251A-12
MIN
UNIT
MAX
...
76
td(RLSH)
Delay time, RAS low to first SC high after TRG high
(see Note 19)
tRSD
130
140
ns
77
td(CLSH)
Delay time, CAS low to first SC high after TRG high
(see Note 19)
tCSD
40
45
ns
78
20
ns
-10
ns
20
ns
20
20
ns
25
30
ns
tw(RH)
ns
td(SCTR)
Delay time, SC high to TRG high (see Notes 19 and 20)
tTSL
15
79
td(JHRH)
Delay time, TRG high to RAS high (see Note 19)
tTRD
-10
80
td(SCRL)
Delay time, SC high to RAS low (see Notes 21 and 22)
tSRS
10
81
td1SCSE)
Delay time, SC high to SE high in serial input mode
82
td(RHSC)
Delay time, RAS high to SC high (see Note 22)
tSRD
83
td(THRL)
Delay time, TRG high to RAS low (see Note 23)
tTRP
84
td(THSC)
Delay time, TRG high to SC high (see Note 23)
tTSD
35
40
ns
85
td(SESC)
Delay time, SE low to SC high (see Note 24)
tsws
10 ..
15
ns
88
trflMA}
Refresh time interval, memory
tREF
..
.
tw(RH)
8
8
ms
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 19. Memory to register (read) transfer cycles only.
20. In a transfer read cycle, the state of SC when TRG rises is a Don't Care condition. However, to guarantee proper sequencing of the
internal clock circuitry, there can be no positive transitions of SC for at least 10 ns prior to when TRG goes high.
21. In a transfer write cycle, the state of SC when RAS falls is a Don't Care condition. However, to guarantee proper sequencing of the
internal clock circuitry, there can be no positive transitions of SC for at least 10 ns prior to when RAS goes low.
22. Register to memory (write) transfer cycles only.
23. Memory to register (read) and register to memory (write) transfer cycles only.
24. Serial data-in cycles only.
25. System transition times (rise and fall) are to be a minimum of 3 ns and a maximum of 50 ns.
PARAMETER MEASUREMENT INFORMATION
VSS
Figure 3. Load Circuit
ADVANCE INFORMATION documenls contain information on
new products in the sampling or preproduction phase of
developmenl Characteristic data and other specifications
are subject to change without notice.
TEXAS ~
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read cycle timing
~
RAS
tT
14
I
~ td(CLRH)
~ th(RA)
}i
I '-
::
1
I
I ~th(RLCA)
t I
-.! j'4i-
~
:
~I: if
i
l.- tw(RH)
td(RLCH)
i ~ td(RLCL) ~ tw(CL)
I
tsu(RA)
p,j
tw(RL)
-J:J !4-
-4l
~
tc(rd)
-----"Ni ~
:
-I
.---':
-.J M
I,i1
I
I
td(CHRL)
~
I
~ th(CLCA)14
~
I
I
~td(CLGH)~:
~I
!\
-.J '-____
II
II
\
: \,-_ _
I
I
t (CH) - - -..
~:
A~A8 ~ :+mn ~'-_____
tsu(SFR)
-.I rt-t
I~
~!I I
DSF~II
-.,
~th(SFR)
iJ:X'A.!
~ tsu(SFC)
I
II
14
~~I
th~
I
I I
~II
1 1
-1\-11
DQ
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SGMS039- JANUARY 1991
early write cycle timing
14
• I
1 14
~
... - - - - - - - t d ( R L C H )
~!.1 114
1 ~ td(RLCL) ~1111
::
~
1
Isu(RA)
AD-A"
~ *"-ISU(CA)~
r
1
"I
-------.
..
~
1 Ii.- tw(RH) -.11
i1~t4-tT
I .1
.1 i4--+- td(CHRL)
-.!
I:i1:~
1
~
1 14 1
: '--
tw(CH)
t~1
rt-r
:
I
r4
~
th(SFC)
I
_ _ _ _ __
...._ _ _ _ __
I I
!4-t-
I
I
#I
flfl!
~
1
1
1
1
1
1
14- tSU(WMR)
I 1 1
I
I
1
H
1
14 1 I
~
1
1
ioIIII
:
I
I
I
141
_ ~I
1
~
1
W
1
th(RWM)
I
tsu(OQR)
3
--.I
I
j4f
II
r4
th(ROQ) ~
~
~
tsu(WCH)
tSU(WRH)
~
th(RLW)
I
.1
~
th(CLW)
~tSU(WCL)
~l
I
1
I
~I~--------------------~~~~~~
1 I I
I
II1II
,
I
tW(WL)
~
1
tsu(OCL)
1411
-.I
I
:
i4-L
i4'14--- th(CLO)
.,
------~~
II ____________________
th(RLO)
~
OQ~
5
NOTE 26: See "Write Cycle State" Table for the logic state of "1 ", "2", "3", "4", and "5",
TEXAS •
INSlRUMENTS
9-168
"'1
1
~ ~SU(SFC~
tsu(TRG) --.;
TRG
1
1
~
~ :co;mn ~I...'
tsu(SFR)
OSF
i4-th(RA)
1
~ th(RLCA)
.1
td(CLRH)
tw(CL)
N:
I
lIT
tw(RL)
------~~
....
.1
tc(W)
I 14
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ44C251A
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS039 - JANUARY 1991
delayed write cycle timing
14
_ _ _~,
tc(W)
14
N
,
t-r
--.l
'.
!4
..- - - - - - - t d ( R L C H )
~
:~:
,
AO·AS
14-
-:l ~
I4--+1:i1 :
tw(CL)
Nl
1
~ th(RLCA) 1
0,j4-t
I
td(CLRH)
.14
,
.,'
~
W (RH)--.j
tT
td(CHRL)
1
~
1 14 I
~ h
~
: , t4
th(SFC)
I
I
tw(CH)
I
I
~ i::U(SFc)~,---.j
t4-t t~U(TRG)
'!XXIQI
~ I
I
II'
I
-VI
/
I
~
~I
~
1
COI~mn
I\
I
th(CLCA) I
14
I
~:
tsu(SFC) ~
~ " " " 11
I
•
h!~FC) ~
~
I
I
~
I
I
~ tW(RH~~
14- td(CL,RH)
I
0
~
/
I
I
td(CARH)
c+mn
,I
t4- td(C~RH
{
I
I
I
I
:
I
I
~
I
I I
I I
~ I
~
I
14- th(SFG,) ~I
2,
I
~~~
I
1
I
I
1
I
t Referenced to CAS or W, whichever occurs last.
NOTES: 26. See "Write Cycle State Table" for the logic state of "1 ", "2", "3", ''4:'', and "5".
29. A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing
specifications. TRG must remain high throughout the entire page-mode operation if the late write feature is used, to guarantee
page-mode cycle ti~lf the early write cycle timing is used, the state ofTRG is a Don't Care after the minimum period th(TRG) from
the falling edge of RAS.
TEXAS
JJp
INSTRUMENlS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-173
SMJ44C251A
262144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS039 -
JANUARY 1991
enhanced page-mode read-modify-write cycle timing
~
~~W
~
~
RASN
I
I
I
I
I
CAS
I
I I
~
td(RLCH).'
I
~
tc(ROWP)
I
j4-- td(RLCW ~
,
~tw(CL)~
~
~ td(CLRH)
~ tw(CH)
td(CHRW
I
~
~ tsu(CA)
I
I
A~AB ~ ~ ~column: ~
~ i4-
I
"U(SF~Hl-I-:: l,u(SFC) I
~ ':
DSF~::2
~:
tsu(WMR)
~
.. I
th(RWf';'I)
I
~
I I I
~
G
~
:
I~
rI
~
I
I
I
WI13
r~ ~I
It
AlII
~ su(OOR)
I
th(ROO)
I
I
1
:
,
1'4
.1
~
,
,
14
I
I
~
ta(CA)t
.
tsu(OWL) ~
I
14
14-
, .1
I
~III
I
tw(WL)
I
I
~I'
~
~
"U(SFC)
2
tsu(WRH)
N
-1
V
11
1I I
I 1
II
~ 14- ta(C)
.,
th(SFC)
tsu(WCH)
I
I
~
I tsu(RO)
~ td(CLWL) ------.I
I
td(CAWL)
.:
~d(RLWL)
.j
I
~
~
~olumn:
:
·~th(SFC)
th(SFR) I I
:
~
~II
.
I:
\l
0 T\\{
~h~~lh(~L~A) ':~-r:::A: :
~
: :
tsu(RA)
I
tw(RH) ~
14
\'!I
'{
I
~
~
~
~_....I;I....lo1...lo.O;..""-l,~~""
th(WLO)
I
I
t
, i 4 - t l1 (CP) ~
.r--:-:-":':'":"~
00
I
1
I
14- ta(G) -.!
_ _ _ _14---.;1 : ta(R) ~
I
~14---.!-td(GHO)
III!-_ _ _ _ _ _""'\
~ tdls(G)
I~----------_
\J
~,,"--_----,I
t Output may go from the high-impedance state to an invalid data state prior to the specified access time.
NOTES: 26. See "Write Cycle State Table" for the logic state of "1 ", "2", "3", "4", and "5".
30. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not
violated.
TEXAS . .
INSTRUMENTS
9-174
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
SMJ44C251A
262144 BY 4-B.lT MULTIPaRT VIDEO RAM
SGMS039 -
JANUARY 1991
RAS-only refresh timing
-14------ tc(rd) ------~~
1
RAS
l e t - tw(RL)
--------------------------~~
I
--~~I
I
--.I ~
I !
tT
1
Y1~
tT
I ~tW(RH)~
-.I !i4~
~
CAS
tsu(RA)
I I
I ~4---.:of-l-
I~
~ I
AO.AB~ ~o~
I ~
I
tsu(SFR)
~~~~~~~~~~~
~
.1 I
I
I I
DSF
::
14
.1 I
th(RA)
~
.11
Row
th(SFR)
=-
I ..
I~-___
.;-:-
I
tsu(TRG)
~i
th(TRG)
I
IN
DQ
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-175
SMJ44C251A
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS039 -
JANUARY 1991
CAS·before·RAS refresh
~
tc(rd)
14-- tw(RH) - . !
;':
----'
14
~
.1
I
td(CLRL)R
tw(RL) ---~~
II1II
r4
\{
td(RHCL)R
,
1
,
1
.,
}r~-----------
~ td(RLCH)R ~
V
w
DSF
TEXAS "-!1
INSlRUMENTS
9-176
.,
,
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ44C251A
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
•
SGMS039 -
JANUARY 1991
CAS-before-RAS refresh counter test timing
~~------------tc(rd) -----------~~I
I
14-- tw(RH) ~
I
A
~itd(RHC~)~~------------------J!1
ii
i ~I
I
td(CLRL)R
I
I
I
i4
\{
I I
.' I
~
tw(CH)
I~
I I
I I
11 N
I
I
tsu(SFR) ~ ~
!
I~~,
!..J_
I .14---O!~- th(SFR)
V-
I 1
I
I
I ~th(SFC)
II
DSF
I
I
"
td(RLCH)R
tw(CL)
1111
~I
1
I 1
I
I I
~~~-I I
, ,
~DgH~z~
14- tsu(WCH) ~
I I
I I
I
~tsU(WRH) ~
rca--t th(CLW) ~
i
~ th(CLD) ~
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.,..1......
1
w
liN
I I !~ 14
tsu(DWL) ~
DQ - - - - - - - - - HI·Z
---------,-<1(
tsu(CA)~
I
~
Data In
iY
2>------
.1
I
th(WLD)
I
~th(CLCA)
Column
AO·AB
:
~tW(WL)'~
~~~~~~~~l'"7
TEXAS -1!1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-177
SMJ44C251A
262 144 8Y 4-81T MULTIPaRT VIDEO RAM
SGMS039 -
JANUARY 1991
hidden refresh cycle timing
L.I_
,..-------
I
I I,.
I
I
I
I
.: I
tw(RL)
I
I
~
. : ' tw(RL)
:
I
I
1-:
I I
t-1
tw(CL)
i~
I
14
~
~
-:~
I
~ th(CLCA)
I
Iti- ~ ~S~(CA)
:
~*HfX.~:~~
t
I
I I
I
I
~--I
1'41
.1
I
th(RHrd)
I
DSF
TEXAS •
INSlRUMENTS
9-178
~I
II~i
tSU(R~Jh\;l4~
AD-A'
~
td(RLCH)
~ ~
I~
I
"
I
I
th(RA)
M ory C I
- ~ Refresh Cycle ~
em
yce~'
I
tw(RH) 14
.,
tw(RH) :4
.~ Refresh Cycle
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ44C251A
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS039 - JANUARY 1991
write-mode control pseudo write transfer timing
The write-mode control cycle is used to change the SOQs from the output mode to the input mode. This allows
serial data to be written into the data register. The diagram below assumes that the device was originally in the
serial read mode.
AO-AS
DSF
td(SCRl)
SC
~tW(SC~)~
I~
--.I
.1: :
: :\\\\\\\\\I~
l
SDa
Data
Out
tdls(SE) ~
tsu(SE) I~
SE
2m¥
14--
1
1
1
1
1
1
i
t (SCl)
w
~
·1
if
1
td(RHSC)
\ ___
.1 I
1 14-a-!- th(SDS)
1
1
1
~
NOTES: 31. Random-mode Q outputs remain in the high-impedance state for the entire write-mode control.
32. SE must be high as RAS falls in order to perform a write-mode control cycle.
TEXAS ~
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
9-179
SMJ44C251A
262 144 8Y 4·81T MULTIPORT VIDEO RAM
SGMS039 -
JANUARY 1991
data register to memory timing, serial input enabled
~
I
~~
~
~
I ~ td(RLCL) -------.!
-------,.N
:
1111
J~
I
I
~
I
I ~
~
th(RA)
~ow
~
---tl
IV
I
~!.f
I th(RLCf)
I
:
1'1
I
>@<[
~
r
tsu(TRG)
::t
--.J ' - - -
~.:
I
I
tsu(CA)
.1
~th(CLCA)
Column
I
~
I
~g~ZgH~
~ ~ th(SFR) -.!
tsu(SFR)
OSF
N
I
I ,I!
AO-AB
~ tw(RH)
J4- tw(CL)
I
tsu(RA)
11:
td(RLCH)
I:
CAS
I
1\
I
!
: I
I ~
I
.1
tw(RL)
I
I
I
:--- td(THRL) -t-I
~g~~gH~
~: ~ th(TRG) ~
TRG~::II~
~
I
~
?I
w~ ii
·~HnigH~
~
td(SCRL)
I
HI-Z - - - - - - - ! - I - - - - - - - - - - -
--lCk!I------..1 I
I
I
I I
td(RHSC)
~
.:
I 14~'---•• tw(SCH)
f-:
I I
I
I I
I I
----:Ii
~
I
I I
I I
I I
1f
~
soa
th(RWM)
I
I I
DQ
sc
~
I
tsu(WMR)
:.- tsu(SDS) :
(see Note 36)
!
\
tw(SCL)
i if
~ i
14
·1
I
~
..I
..I
~ th(SE) -.!I
'14--- td(SESC)
I
~
"--
~~_-I.~I_ th(SDS)
0;' ~ ~t.
tsu(SE)
,
Xm
3
NOTES: 33. Random mode Q outputs remain in the high-impedance state for the entire data register to memory transfer cycle. This cycle is used
to transfer data from the data register to the memory array. Every one of the 512 locations in each data register is written into the
corresponding 512 columns of the selected row. Data in the data register may proceed from a serial shift-in or from a parallel load
from one of the memory array rows. The above diagram assumes that the device is in the serial write mode (Le., SD is enabled by
a previous write mode control cycle, thus allowing data to be shifted-in).
34. See "Register Transfer Function Table" for logic state of "1" and "3".
35. Successive transfer writes can be performed without serial clocks for applications requiring fast memory array clears.
36. SC transitions are not allowed between RAS low and TRG high.
37. For a multiple transfer write operation; a transfer read cycle needs to be done from the same row after the first transfer write is carried
out, then do multiple transfer write for subsequent rows. See parameters tc(TW)M (#18a) and tw(RL)M (#23a).
TEXAS ~
INSTRUMENlS
9-180
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ44C251A
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS039 -
JANUARY 1991
register transfer function table
RAS FALL
FUNCTION
TRG
W
DSF
(1)
SE
(3)
Register to memory transfer
L
L
X
L
Register to memory transfer, alternate transfer write
L
L
H
X
L
L
L
H
L
H
L
X
Pseudo-transfer
soa control, serial input enabled
Memory to register transfer
TEXAS
-IJ1
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
9-181
SMJ44C251A
262 144 BY 4·B11 MULTIPaRT VIDEO RAM
SGMS039 -
JANUARY 1991
alternate data register to memory timing
tsu(AA)
AO-AS
OSF
soa
td(SCSE)
~
e--
.
104- td(SESC) ~
~r-~~f- tsu(SE)
I
SE
NOTES: 36. SC transitions are not allowed between AAS low and TAG high.
3? For a multiple transfer write operation; a transfer read cycle needs to be done from the same row after the first transfer write is carried
out, then do multiple transfer write for subsequent rows. See parameters tc(lW)M (#18a) and tw(RL)M (#23a).
TEXAS ~
INSlRUMENTS
9·182
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
SMJ44C251A
262144 BY 4-BITMULTIPORT VIDEO RAM
SGMS039 -
JANUARY 1991
memory to data register transfer timing
r..
~I
tc(TRO)
,
I
I
14
l}l
I
, 4
I
td(RLCH)
, :
,
14
tsu(RA) -+14'--~~
~
AO-AB
tsu(SFR)
14
_
OSF
tsu(TRG)
:
~I
I
:11
XXXXXX'>(X.
I~
~oW
w
'4
I
td(RLTH)
'I
I,
I
I
yi
:
-
I
I
~
II
~I
tsu(CA)
I
I
I
t~
1
:
,
I
~
I
1
I I
J
..,
,14
I
I
~I
14,
~
_----'lfr'":--"""":li.\
~ ta(SQ) ~
1
~I
,
I
,
I
} I
I
-
I
th(RWM):
I
I
~Hh*Z~
~,14
~
td(SCTR)
)
r..
I
I
14- td(CLS") --.I
td(THSC)
td(RLS")
11
\
i:
t4
~I
td(THRL)
~ td(THRH)
r-----:....--....:.----------------
}1'
.1
\"-_----J~
14
tc(SC)
~ ta(SQ) ~
tw(SCL)
th(SHSQ)
----O-Id-Oa-t-a--~~~I_______O_ld_O_a_t_a______J)(~
SOQ
'------
~
! rth(SFR)~~
, ,
I
I11III
~
~I
~ cot" ~g~2gH~
~
!
--lr..~__~I~
th(SHSQ)
:
I
tw(SCH)
SC
!4-r
~
~th(RA)1
----'G---Dl
tsu(WMR) -~
I
14- tw(CL)
I I
th(RLCA)
-I114.--..~1 I
X>C
1
~ ta(SE)
SE
~~________________________________________________________________
NOTE: 10. When the odd tap is used (tap addresses can be 0-511, and odd taps are 1,3,5 ... etc.), the cycle time for SC in the first serial data
out cycle needs to be 40 ns minimum.
The serial data-out (SO) cycle is used to read data out of the data registers. Before data can be read via SO,
the device must be put into the read mode by performing a transfer read cycle. Transfer write cycles occurring
between the transfer read cycle and the subsequent shifting out of data will not take the device out of the read
mode. But a write mode control cycle at that time will take the device out of the read mode and put it in the write
mode, thus not allowing the reading of data.
While accessing data in the serial data registers, the state of TRG is a Don't Care as long as TRG is held high
when RAS goes low to prevent data transfers between memory and data registers.
TEXAS •
INSlRUMENlS
9-184
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
Datapath VLSI Products
Datapath VLSI Products
SN74ACT2140A
2-WAY 4K x 18/8K x 18 CACHE DATA RAM
03291, NOVEMBER 1989-REVISEO JUNE 1990
•
Interfaces Directly with the Intel 82385
Cache Controller
•
Access Time ... 25 ns Max
•
Fast Access Time Supports 33-MHz Intel
ESCA 80386 Operation
•
•
•
•
•
FN PACKAGE
(TOP VIEW)
AD
Configurable for 2-Way or Direct Mapped
Arrays
Contains Address Latches and Byte Contol
Cascadable for Larger Caches
Byte Parity Storage Bits
Fully TTL Compatible
description
GND
GND
DOO
D01
D02
D03
GND
D04
D05
D06
DO?
10
44
11
43
12
42
13
41
14
40
15
39
16
38
17
37
18
36
19
35
A12
CE
GND
D015
D014
0013
D012
GND
D011
D010
Dog
DOB
34
2021 222324 25262728293031 3233
The 'ACT2140A is a 147,456-bitstatic RAM with PDOO
PD01
address latches and byte control that can be
()()OCXl A~
3
2
511
P=Q
14
r-;::::L/
Q
r-
19
7
B
1
r--
,
I
r
"'
-"'
-
6
27
28
15
16
~
~
I
2k
~
C1
10
"'
1
/
B
9
10
r--
B
21
13
Parity
Checker
I-J
I-J
I-J
~
f-/
•
f-/
~
~
f---
Parity
Generator
~
2k + 1
I
J
--
~
EN
'----
.J
~
~
TEXAS 1J1
INSTRUMENlS .
10-6
P
20
r-
Vi
COMP
BL
,
5
Input
Buffers
DO
RAM 512X9
R
0
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
Match
SN74ACT2151, SN74ACT2153
1K x 11 CACHE ADDRESS COMPARATORS
D3105. SEPTEMBER 1987-REVISED MARCH 1990
•
Fast Address to Match Delay
... 22 ns Max
N PACKAGE
(TOP VIEW)
•
On-Chip Address/Data Comparator
•
On-Chip Parity Generator and Checking
•
Parity Error Output, Force Parity Error
Input
•
•
Easily Expandable
•
•
RESET
A4
A3
A2
A1
AO
00
01
02
03
D9
Choice of Totem-Pole ('ACT2151) or OpenDrain (,ACT2153) MATCH Output
EPIC'" (Enhanced Performance Implanted
CMOS) 1 ,Am Process
1
U
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
Vii
12
17
PE
13
16
GNO
14
15
Fully TTL-Compatible
nvcc
oA5
A6
A7
A8
A9
010
04
05
06
07
08
MATCH
]8
description
The 'ACT2151 and 'ACT2153 cache address
comparators consist of a high-speed 1K x 11
static RAM array, parity generator, parity checker,
and 12-bit high-speed comparator. They are
fabricated using advanced silicon-gate CMOS
technology for high speed and simple interface
with bipolar TTL circuits. These cache address
comparators are easily cascadable for wider tag
addresses or deeper tag memories. Significant
reductions in cache memory component count,
board area, and power dissipation can be
achieved with these devices. The 'ACT2151 has
a totem-pole match output while the 'ACT2153
has an open-drain MATCH output for easy
AND-tying.
FN PACKAGE
(TOP VIEW)
A1
AO
00
01
02
03
09
5
4
321
0
28 27 26
6
A7
A8
23 A9
22 010
04
21
20 05
19 06
25
24
7
8
·9
10
11
12 1314 15 16 1718
If 8 is low and W is high, the cache address
comparator compares the contents of the memory
location addressed by AO-A9with the data 00-01 0
plus generated parity. An equality is indicated by a high level on the MATCH output. A lOW-level output on PE
signifies a parity error in the internal RAM data. PE is an N-channel open-drain output for easy OR-tying. During
a write cycle (8 and W low), data on 00-010 plus generated odd parity are written in the 12-bit memory location
addressed by AO-A 10. ALso during write, a parity error may be forced by holding PE low.
A reset input is provided for initialization. When RESET is taken low, all 1K x 11 RAM locations are cleared to
zero (with valid parity) and the MATCH output is forced high. If an input data word of zero is compared to any
memory location that has not been written into since reset, MATCH will be high indicating that input data, plus
generated parity, is equal to the reset memory location. PE will be high after reset for every addressed memory
location, indicating no parity error in the RAM data. By tying a single data input pin high, this bit will function as
a valid bit and a match will not occur unless data has been written into the addressed memory location. When
cascading in the width direction, only one bit must be tied high regardless of the address width.
EPIC is a trademark of Texas Instruments Incorporated.
These devices are covered by U.S. Patents 4,831,625 and 4,884,270.
PRODUCTION DATA documents contain InformaUon current as of
publication date. Products conform to specificaUons per the terms of
Texas Instruments standard warranty. ProducUon processing does not
necessarily Include tesling of all parameters.
Copyright © 1990. Texas Instruments Incorporated
TEXAS ."
INSlRUMENlS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10-7
SN74ACT2151, SN74ACT2153
1K x 11 CACHE ADDRESS COMPARATORS
03105, SEPTEMBER 1987-REVISEO MARCH 1990
These cache address comparators operate from a single 5-V supply and are offered in 28-pin 600-mil plastic
dual-in-line or PLCC packages,
The SN74ACT2151 and SN74ACT2153 are characterized for operation from O°C to 70°C.
MATCH OUTPUT DESCRIPTION
MATCH
=VOH if:
(AO-A9)
or:
RESET
or:
S=
or:
W
MATCH = VOL if:
=00-010 + parity,
=VIL,
VIH,
=VIL
(AO-A9) ~ 00-010 + parity,
with RESET = VIH,
S = VIL' and W = VIH
FUNCTION TABLE
INPUTS
Vi
5
OUTPUTS
RESET
H
L
H
L
L
H
X
H
X
X
FUNCTION
MATCH
PE
L
L
L
H
Not equal
H
L
Undefined error
Parity error
H
H
Equal
H
IN
Write
H
H
H
Device disabled
L
H
t
Memory reset
t The state of PE is dependent on inputs Wand S.
for complete data sheet
The complete version of this data sheet and application information can be found in the Cache Memory
Management Data Book, Literature #SCA0002. To obtain a copy of this data book, contact your local TI sales
representative or call the TI Customer Response Center at 1-800-223-3200.
TEXAS •
INSlRUMENlS
10-8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2152A, SN74ACT2154A
2K x 8 CACHE ADDRESS COMPARATORS
03156. DECEMBER 1988-REVISED MARCH 1990
•
N PACKAGE
Fast Address to Match Delay
25 or 25 ns Max
(TOP VIEW)
•
Common 1/0 with Read Feature
•
On-Chip AddresslData Comparator
•
On-Chip Parity Generator and Checking
o
Parity Error Output, Force Parity Error Input
•
Easily Expandable
•
Choice of Open-Drain or Totem-Pole
MATCH Output
•
EPICTM (Enhanced Performance Implanted
CMOS) 1-J-tm Process
•
Fully TTL-Compatible
RESET
A4
A3
A2
Al
AO
GNO
GNO
00
01
02
03
description
A5
A6
A7
A8
A9
Al0
VCC
04
05
06
07
MATCH
R
S
IN
PE
FN PACKAGE
The' ACT21 52A and' ACT21 54A cache address
comparators consist of a high-speed 2K x 9
static RAM array, parity generator, parity
checker, and 9-bit high-speed comparator. They
are fabricated using advanced silicon-gate
CMOS technology for high speed and simple
interface with bipolar TTL circuits. These cache
address comparators are easily cas cad able for
wider tag addresses or deeper tag memories.
Significant reductions in cache memory
component count, board area, and power
dissipation can be achieved with these devices.
The ' ACT21 52A has a totem-pole MATCH
output while the' ACT21 54A has an open-drain
MATCH output for easy AND-tying.
(TOP VIEW)
Al
AO
GNO
GNO
DO
01
02
25
24
23
22
21
20
11
19
A8
A9
Al0
VCC
04
05
06
12 13 14 15 16 17 18
8 leI: I~ I~ /CI) Q b
f0-
e:!
If S is low and Wand R are high, the cache
~
address comparator compares the contents of
the memory location addressed by AO-A 10 with
the data DO-D7 plus generated parity. An
equality is indicated by a high level on the
MATCH output. A low-level output on PE signifies a parity error in the internal RAM data. PE is an N-channel
open-drain output for easy OR-tying. During a write cycle (S and W low), data on DO-D7 plus generated
odd parity are written in the 9-bit memory location addressed by AO-A 10. Also during write, a parity error
may be forced by holding PE low.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the tarms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright
© 1990. Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10-9
SN74ACT2152A, SN74ACT2154A
2K x 8 CACHE ADDRESS COMPARATORS
A read mode is provided with the' ACT2152 and' ACT21 54, which allows the contents of RAM to be
read at the DO-D7 pins. The read mode is selected when Rand S are low, and W is high.
A reset input is provided for initialization. When RESET is taken low, all 2K x 9 RAM locations are cleared
to zero (with valid parity) and the MATCH output is forced high. If an input data word of zero is compared
to any memory location that has not been written into since reset, MATCH will be high indicating that
input data, plus generated parity, is equal to the reset memory location. PE will be high after reset for
every addressed memory location, indicating no parity error in the RAM data. By tying a single data input
pin high, this bit will function as a valid bit and a match will not occur unless data has been written into
the addressed memory location. When cascading in the width direction, only one bit must be tied high
regardless of the address width.
These cache address comparators operate from a single + 5-V supply and are offered in 28-pin 600-mil
ceramic side-brazed, plastic dual-in-Iine, or PLCC packages.
The' ACT2152 and' ACT2154 are characterized for operation from OOC to 70°C.
MATCH OUTPUT DESCRIPTION
=
MATCH
VOH if: [AO-A 10] = DO-D7
or: RESET = VIL,
or: S = VIH,
or: W = VIL
+ parity,
VOL if: [AO-A10] 1= DO-D7 + parity,
with RESET = VIH,
S = VIL, and W = VIH
MATCH
FUNCTION TABLE
INPUTS
1/0
OUTPUTS
W
R
S
RESET
MATCH
PE
00-07
H
L
L
H
L
H
Output
L
L
L
H
H
L
H
H
L
H
Input
H
H
H
Hi-Z
L
H
t
t
X
X
H
X
X
X
tThe state of these pins is dependent on inputs
c
Equal
H
IN
H
Not equal
Undefined error
H
L
Read
Parity error
Input
H
X
L
FUNCTION
Write
Device disabled
Memory reset
W, R, and S.
for complete data sheet
The complete version of this data sheet and application information can be found in the Cache Memory
Management Data Book, Literature #SCAD002. To obtain a copy of this data book, contact your local
TI sales representative or call the TI Customer Response Center at 1-800-223-3200.
TEXAS •
INSTRUMENlS
10-10
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN74ACT2155
2K x 8 BURST CACHE ADDRESS COMPARATOR/DATA RAM
D3076, NOVEMBER 1988- REVISED JUNE 1990
•
Address to MATCH Time ... 22 ns Max
•
Supports Motorola MC68030 Cache Burst
Fill with No Added Wait States
FN PACKAGE
(TOP VIEW)
Upward Compatibility for Motorola
MC68030 Speed Upgrades
•
Cache Data RAM with Parity and Internal
Burst Counter
o
6
DO
01
02
03
GNO
00
01
02
03
Dirty Bit Storage Capability for Use in CopyBack Caches
Separate 1/0 Supports Copy-Back
•
Easily Expandable in Depth and Width
•
Reliable Advanced CMOS Technology
•
co c..
::I:~o
~o.-LLU~
•
•
r--
Fully TTL Compatible
5 4
en co r-~
3
~I§
Ln'
2K x 8 BURST
CACHE COMP/DATA RAM
SN74ACT2155
6
FMHB
5
COMP7
43
RESET
18
S
W 17
16
OE
FORCE MATCHiV6
COMP D7 Q7
RESET/G1
"'- CHIP SELECT/G2
r--. WRITE/G3
r--. 1,2EN4 [EN QJ
-I- 1,2,3EN5 [EN MAT & PEJ
,.......
19
r--.
20
CBACK
21
CBREQ
22
PCLK
_f'...
STERM
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
00
01
02
03
04
05
06
07
27
28
r-...
,.....
BURST CNTRL
SYNC TERM
:~~ ICACHE BURST
PCLK
o ...
1
2
3
4
7
8
9
10
38
37
36
35
26
\"ALT 5.6Q
39
40
41
42
44
MATCH
25
BERR 5,6Q
>
I
RAM
MATHA
MATBE
ADD~
PAR ERR 5Q
PAR ERR
.......
23
W
10
0
0
IDAT~
I
DAT~4V'
7
7
12
13
14
15
32
31
30
29
QO
Q1
Q2
Q3
Q4
Q5
U6
Q7
tThis symbol is in accordance with ANSI/IEEE Std 91-1984.
for complete data sheet
The complete version of this data sheet and application information can be found in the Cache Memory
Management Data Book, Literature #SCAD002. To obtain a copy of this data book, contact your local
TI sales representative or call the TI Customer Response Center at 1-800-223-3200.
TEXAS ."
INSTRUMENTS
10-12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2156
16K x 4 BURST CACHE ADDRESS COMPARATOR/DATA RAM
D3412, APRIL 1990-REVISED JUNE 1990
•
•
Address to MATCH Time ... 20 ns Max
•
Cache Data RAM with Parity and Internal
Burst Counter
•
Dirty Bit Storage Capability for Use in
Copy-Back Caches
FN PACKAGE
(TOP VIEW)
Supports Motorola MC68030 Cache Burst
Fill with Direct Interface
•
•
•
Separate I/O Supports Copy-Back
•
Fully TTL Compatible
Easily Expandable in Depth and Width
Reliable Advanced CMOS Technology
description
wlw
Vee
Vee
A13
A12
A11
A10
GND
A9
AS
A7
A6
7 6
~ltD
co
I:::2:w
W:::2: 0 Wo,... C\J C')
LL () a: 0 0 0 0
I5: I0
5 4
3
2
1 44 4342 41 4g
9
Vee
8
38
00
9
37
10
36
01
02
11
35
03
12
34
GND
GND
MATHA
MATBE
13
33
14
32
15
31
16
30
17
29
181920 21 22 23 24 25 26 27 28
PE
Vee
The 'ACT2156 burst cache address comparator/
data RAM consists of a high-speed 16K x 5 static
RAM array, 2-bit burst counter and control
circuitry, parity generator, parity checker, and 4-bit
high-speed comparator, The 'ACT2156 is fabricated using advanced silicon gate CMOS technology for high
speed and simple interface with bipolar TTL circuits, The 'ACT2156 provides a valuable building block for
building fast efficient caches, By combining this device with programmable logic, a cache can be constructed
that specifically addresses the individual system requirements. Significant reductions in cache memory
component count, board area, and power dissipation can be achieved by using this device.
The 'ACT2156 was 'designed to be used as the tag comparator and data RAM necessary to provide a cache
that supports the burst fill requirement of'the Motorola MC68030 microprocessor, The 'ACT2156 directly
interfaces with the MC68030 providing four long words to the processor in four clock cycles. By interfacing
directly with the processor, about 10 ns in delay time is saved when comparing this solution with discrete designs.
Even though the 'ACT2156 is designed for use with the MC68030 processor, it can also be used with other
processors to implement write-through or copy-back class caches.
The SN74ACT2156 is characterized for operation from O°C to 70°C.
operation as an address comparator
The 'ACT2156 compares the contents ofthe memory location addressed by AO-A 13 with the address bits applied
at 00-03. An equality is indicated by a high level on the MATBE and MATHA outputs. A lOW-level output on PE
signifies a parity error in the addressed internal RAM data. Ouring a write cycle, address bits on 00-03 plus
generated odd parity are written in the 5-bit memory location addressed by AO-A 13. Also during write, a parity
error may be forced for diagnostic purposes by holding PE low.
operation in the burst mode
The 'ACT2156 contains burst control circuitry conSisting of a 2-bit wrap-around counter, a mux, and a Burst
Control Register (BCR). The BCR controls a mux which selects AO and A 1 from either the input terminals or the
2-bit counter. When CBREQ or CBACK is high, the BCR is asynchronously reset and inputs AO and A 1 drive
the RAM. On the next falling edge of PCLK after STERM is taken low, the SCR is set and the counter bits (CAO
This device is covered'by U.S. Patents 4,831,625; 4,858,182; 4,884,270; and additional patents pending.
PRODUCTION DATA documents contain Information current as of
publicalion dale. Products conlorm to speCifications per the terms of
Texas Inslruments standard warranty. Production processing does
not necessarily Include testing 01 all paramelers.
Copyright © 1990, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-13
SN74ACT2156
16K x 4 BURST CACHE ADDRESS COMPARATOR/DATA RAM
D3412.APRIL 199D-REVISEDJUNE 1990
and CA1) drive the RAM. At the same time that the BCR is set (STERM low and a PCLKfalling edge), the binary
value of AO and A 1 in the counter is incremented. The counter can be held at any count by taking STERM high
as long as BCR remains set. When the BCR is set, MATHA is forced high.
operation as a data RAM
The 'ACT2156 can be used as a 16K x 4 data RAM with separate 110, a four-word burst mode and parity
generation and checking. When using this device as a data RAM, the FMHB input should be tied high to prevent
MATHA and MATBE from switching.
using the 'ACT2156 with the MC68030
The 'ACT2156 interfaces with the Motorola MC68030 through use of 'ACT2156 input signals, STERM, CBREO,
PCLK, and CBACK, and output signals MATBE and MATHA. Match outputs MATBE and MATHA can be tied
directly to processor inputs BERR and HALT, respectively. As long as the requested information is in cache, the
BERR and HALT signals remain high. When a miss occurs (MATBE and MATHA low), BERR and HALT are
driven low simultaneously causing the bus cycle to be retried (rerun). A high level applied at the FMHB input
forces MATBE and MATHA high to prevent continuous rerun.
The 'ACT2156 was designed to be used as the tag comparator and data RAM necessary to provide a cache
that meets the Motorola MC68030 internal cache burst fill requirement by supplying four long words to the
processor in four clock cycles. When the MC68030 requests a burst fill, a single address is supplied. If the
requested information is in the external cache, the 'ACT2156 will indicate a hit. If STERM is low, address bits
A 1-AO (A3-A2 from the processor) will be incremented on each PCLK falling edge and the MATBE output will
indicate a hit or a miss. If a miss occurs, MATBE will drive BERR low causing the MC68030 to abort the burst
cycle and to run with the data it received. MATHA is held high during a burst by the BCA. The timing diagram
in Figure 9 shows burst mode operation.
The 'ACT2156 internal counter can also be used when writing tag and data into the cache, when the burst fill
is done from main memory. When STERM is taken high (inserting processor wait states), the 2-bit counter is
held at the present count. The counter will continue to increment on the first PCLK falling edge after STERM
returns low. When CBACK or CBREO returns high, the mux will select input pins AO and A 1 to drive the RAM.
Figure 10 shows a MC68030 bUrst request with data in main memory. For more information on using the
'ACT2156 with the MC68030, see the "SN74ACT2155/56 Cache Enhances MC68030 Processor Performance"
applications note.
cascading the 'ACT2156
The 'ACT2156 is easily cascaded in width and depth. Wider addresses can be compared by driving the AO-A 13
inputs of each device with the same index and applying the additional address bits to the 00-03 inputs. The chip
select inputs allow the 'ACT2156 to be cascaded in depth. When a device is deselected, the MATHA and MATBE
outputs are driven high. It should be noted that a decoder can be used to drive the select inputs, since the
propagation delay from select to match is much faster than from address to match. MATHA and MATBE are
open-drain outputs for easy wired logic. Through the use of the chip select inputs, the 'ACT2156 can also be
cascaded for a deeper cache data buffer. Figure 12 shows the 'ACT2156 cascaded.
for complete data sheet
The complete version of this data sheet and application information can be found in the Cache Memory
Management Data Book, Literature #SCA0002. To obtain a copy of this data book, contact your local TI sales
representative or call the TI Customer Response Center at 1-800-223-3200.
TEXAS l.!1
INSTRUMENTS
10-14
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN74ACT2157
2K x 16 CACHE ADDRESS COMPARATOR/DATA RAM
D3326, JANUARY 1990-REVISED JUNE 1990
•
Fast Address to Match Delay ... 20 ns Max
•
•
•
Totem-Pole and Open-Drain Match Outputs
On-Chip Parity Generation and Checking
•
Direct 68030 Interface
FN PACKAGE
(TOP VIEW)
o
On-Chip Address/Data Comparator
OOT'"C\JC')v
•
Reliable Advanced CMOS Technology
•
Fully TTL Compatible
>
The 'ACT2157 cache address comparator
consists of a high-speed 2Kx 18 static RAM array,
parity generators, parity checkers, and 18-bit
high-speed comparator. It is fabricated using
advanced silicon-gate CMOS technology for
high-speed and simple interface with bipolar TTL
circuits. This cache address comparator is easily
cascaded for wider tag addresses or deeper tag
memories. Significant reductions in cache
memory component count, board area, and power
dissipation can be achieved with this device.
7
5 4
2 1 44 43 4241 40
39
8
38
9
37
3
10
36
015
014
013
012
GNO
11
35
GNO
04
05
06
07
12
34
13
33
14
32
15
31
011
010
09
08
00
01
02
03
description
6
I~WID
00
LOc.oW::2:Z
<{<{<{<{<{<{<{a:ll..CJ
GNO
R
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
GNO
MATCH3
..... C\J IW 0
IWI~I~ ~ ~ ~ o~GGc.~
~~
::2:::2:
When S is low and W1, W2, and R are high, the cache address comparator compares the contents ofthe memory
location addressed by AO-A 10 with the applied 00-015 plus generated byte parity. An equality is indicated by
a high level on the MATCH 1, MATCH2, and MATCH3 outputs.
The 'ACT2157 is provided with two write inputs, W1 and W2. When S is low, bytes 00-07 are written into the
addressed location by asserting W1 (low) and bytes 08-015 are written by asserting W2 (low), By asserting
both W1 and W2 at the same time, 00-015 is written into the addressed memory location. During a write cycle,
parity is generated~and stored for each byte written,
'ACT2157 parity protection
Byte parity protection is included in the 'ACT2157 to provide a highly reliable cache directory, For any memory
location addressed by AO-A 10, PE will be low if a parity error occurs in either 00-07 or 08-015, PE is an
open-drain output for easy OR-tying, For test purposes, a parity error can be forced in byte 00-07 or 08-015
by forcing PE low when W1 or W2 are low, respectively. A parity error is forced in both bytes by forcing PE low
when both W1 and W2 are asserted,
reading the data RAM
A read mode is provided with the 'ACT2157 and allows the contents of RAM to be read at the 00-015 pins, The
read mode is selected when Rand S are low and W1 and W2 are high, When using the 'ACT2157 as a data
RAM, the FMHB input should be tied high to provide better noise immunity,
initialization
A reset input is provided for initialization. When RESET is taken low, all 2K x 18 RAM locations are cleared to
zero (with valid parity) and the match outputs are forced high. If an input at 00-015 of zero is compared to any
memory location that has not been written into since reset, MATCH1, MATCH2, and MATCH3 will be high
This device is covered by U.S. Patents 4,831 ,625; 4,858,182; 4,884,270; and additional! patents pending.
PRODUCTION DATA documents contain Information current as of
publication date. Products conform to specifications per the terms
of Texas Instruments standard warranty. Production proceSSing
does not necessarily Include testing of all parameters.
Copyright © 1990, Texas Instruments Incorporated
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-15
SN74ACT2157
2K x 16 CACHE ADDRESS COMPARATOR/DATA RAM
D3326, JANUARY 1990-REVISED JUNE 1990
indicating that 00-015 plus generated parity is equal to the reset memory location. PE will be high for every
addressed memory location after reset indicating no parity error in the RAM data. By tying a single data input
pin high, this bit will function as a valid bit and a match will not occur unless data has been written into the
addressed memory location. When cascading in the width direction only, one bit needs to be tied high regardless
of the address width.
cascading the 'ACT2157
The 'ACT2157 is easily cascaded in width and depth. Wider addresses can be compared by driving the AO-A 10
inputs of each device with the same index and applying the additional addre?s bits to the 00-015 inputs. The
select (8) input allows these devices to be cascaded in depth. When a device is deselected, the match outputs
are driven high. It should be noted that a fast decoder can be used to drive the select inputs since the propagation
delay from select to match is much faster than from address to match. MATCH1 and MATCH2 are open-drain
outputs for easy wire tying. Figure 11 shows the 'ACT2157 cascaded,
cache coherency through bus watching
When implementing cache designs, the problem of cache coherency is usually a concern. One solution to this
problem is to implement bus watching using the 'ACT2157. By storing the same tags in the bus watcher RAM
as is stored in the cache tag RAM, the bus watcher will indicate a hit every time a cached address passes down
the main address bus. If cached data is being modified in main memory, the index can be passed to the cache
tag and bus watcher RAM for invalidation. Figure 12 shows a typical bus watcher implementation.
using the' ACT2157 with the MC68030
The 'ACT2157 has two open-drain match outputs for direct interface with the Motorola MC68030. By tying the
outputs MATCH1 and MATCH2 directly to MC68030 inputs BERR and HALT, a two-cycle synchronous read may
be easily achieved. A two-cycle access can be accomplished by using control logic that assumes a cache hit
will occur every time an access is started for cacheable data. This is accomplished by asserting the MC68030
input signal STERM at the beginning of the access cycle. As long as the requested information is in cache,
the BERR and HALT signals remain high. When a miss occurs (MATCH1 and MATCH210w), BERR and HALT
are driven low simultaneously causing the bus cycle to be retried (rerun). The FMHB input of the 'ACT2157 is
provided so that MATCH1 and MATCH2 can be forced high. This function is used to prevent continuous rerun
when the processor retries an access. FMHB could also be used during noncacheable accesses (see
Figure 13).
copy-back caches
The 'ACT2157 can be used in write-through cache designs where writes to cache are immediately sent to main
memory, or in copy-back cache designs where a cache write initially only modifies the cache and can later be
copied back to main memory. Copy-back caches have an advantage in that the number of writes to main memory
are reduced, thereby reducing bus traffic. To implement a copy-back cache, a dirty bit is needed that indicates
whether or not the data is modified from that in main memory. The dirty bit is set to 1 when the cache data is
modified. Data is only copied back if the dirty bit is set, otherwise it is simply overwritten. The read feature of
the 'ACT2157 allows itto be used in copy-back cache designs, It should be noted, however, that the dirty bit must
be stored in an external RAM. Figure 14 shows the 'ACT2157 in a copy-back application.
for complete data sheet
The complete version of this data sheet and application information can be found in the Cache Memory
Management Data Book, Literature #SCA0002. To obtain a copy of this data book, contact your local TI sales
representative or call the TI Customer Response Center at 1-800-223-3200.
TEXAS •
INSlRUMENlS
10-16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2158, SN74ACT2159
8K x 9 CACHE ADDRESS COMPARATORS/DATA RAMs
03281, MAY 1990--REVISEO JUNE 1990
•
Fast Address to MATCH Delay
22 ns Max
FN PACKAGE
(TOP VIEW)
•
•
8K x 10 Internal Static RAM
•
Read Feature with Separate I/O
•
Word Reset Function for Single Entry
Invalidation
•
•
•
•
I~
W
a:WLO"
<1>
'ACT2158
CACHE ADDRESS
CaMP/DATA RAM
RESET
WRITE
RESET
W
WR
S
S
, ACT2159
CACHE ADORESS
CaMP/DATA RAM
RESET
WRITE
WORD RESET
&
SELECT
OE
AO_4_1_ 0
A1.....1L-
AO 41
A1 42
A2 43
A3 44
A4 1
AS
A6
A7
A8
A9
A10 24
A11 25
A12 26
A2~
A3~
A4_1_
A5_2_
A6~
»c
~
z
A7_2_1_
A8~
A92LA102LA112L-
A12~12
n
m
0 0 -8- 0
9
0 1 -'02-1_003-1_1_
04-1_3-
-z-n
o
:IJ
s:
-~
o
z
05~
06~
07~
08~8
00
01
02
03
04
05
06
DO
01
02
03
04
05
06
00
01
02
03
04
05
06
07
07
07
08
08
08
t These symbols are in accordance with IEEE Std 91-1984.
for complete data sheet
The complete version of this data sheet and application information can be found in the Cache Memory
Management Data Book, Literature #SCAD002. To obtain a copy of this data book, contact your local TI sales
representative or call the TI Customer Response Center at 1-800-223-3200.
TEXAS
~
INSlRUMENlS
10-18
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN74ACT2160
8K x 4 2-WAY CACHE ADDRESS COMPARATOR/DATA RAM
D3365. JANUARY 1990-REVISED JUNE 1990
•
Address to Match Time ... 17 ns Max
•
2-Way Architecture Significantly Improves
Hit Rate
•
•
•
•
Implements LRU Replacement Allgorithm
•
•
Reliable Advanced CMOS Technology
FM PACKAGE
(TOP VIEW)
Useful for Bus Watching
On-Chip Parity Generator and Checker
Easily Expandable in Depth and Width
Fully TTL Compatible
LO'
4>
CACHE ADDRESS
COMPARATOR
CACHE ADDRESS
RESET •ACT2163
RESET
READ
READ
WRITE
WRITE
SELECT
SELECT
COMPARATOR
•ACT2164
o
A4
A4
11
A5
11
A5
A10 17
18
A11
12
AS
A7 14
15
A8
16
A9
A1017
18
A11
A12
A12
12
A6
A714
RAM
MATCH
23
MATCH
ADDRESS
A8 15
16
A9
19
A13
20
A13
13
31
01.
,RAM
19
20
DO
01 30
02 28
27
03
04 26
02 28
27
03
04 26
Q
J
13
31
DO
01 30
MATCH
> ADDRESS
tThese symbols are in accordance with ANSI/IEEE Std 91-1984.
logic diagram (positive logic)
32
RST----------.-----~
-
~--------~---------------------------
2
R-----------~~-cr_~
RAM
16K.5
R
AO,A13
00
5,_8._'_0_-'_2_,_14_,2_0-+t---+-_ _1:..;4""-_ _ _ _~ 0 }
_
A __
0_
13,
C1
16383
31
30
~~~~--~~--r~4-~
27
03----~~---+~q-~
26
----------------------------------~
TEXAS . .
INSTRUMENTS
10-22
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
23
MATCH
SN74BCT2160
8K x 4 2-WAY CACHE ADDRESS COMPARATOR/DATA RAM
03512. AUGUST 1990- REVISED AUGUST 1990
•
Fast Address to Match Time ... 12 ns Max
FM PACKAGE
(TOP VIEW)
•
2-Way Architecture Significantly Improves
Hit Rate
~~~~~~O
•
•
Implements LRU Replacement Algorithm
I.{)~C")NT""OO
4
A6
A7
A8
A9
GNO
RESET
LRU-W
Useful for Bus Watching
•
•
On-Chip Parity Generator and Checker
•
Reliable Advanced BiCMOS Technology
•
Fully TTL Compatible
Easily Expandable in Depth and Width
R
WR
6
3 2 1 3231 30
29
0
28
7
27
01
02
03
8
26
Vee
9
25
10
24
11
23
12
22
MATCH1
MATCH2
GNO
PE
BANK
5
21
13
14 15 16 17 18 19 20
description
The SN74BCT2160 is a valuable building block for
implementing fast two-way set associative
caches. This device consists of two separate
8K x 5 RAMs for tag and parity storage, an 8K x 1 LRU RAM, two high-speed comparators, and the control
circuitry necessary to give the designer the freedom to determine how this device will be used. The
SN74BCT2160 also includes single-entry invalidation circuitry and parity generation and checking for ease of
design and high system reliability.
The SN74BCT2160 is fabricated using advanced BiCMOS technology for high speed and simple interface with
bipolar TTL circuits. By combining the SN74BCT2160 with programmable logic, a cache can be constructed that
specifically addresses the individual system requirements. Significant reductions in cache memory component
count, board area, and power dissipation can be achieved by using this device.
A cache memory is a small high-speed memory that is used to store a portion of the data found in the larger main
memory to achieve optimum processor performance and to reduce main memory bus traffic. Since the cache
memory is smaller than the main memory, only part of the address, the least significant bits referred to as the
index, is used to address the cache memory. The most significant address bits, called the tag, are stored along
with the cache data and are used to identify what data is stored in an indexed location. When the processor
requests data, the index portion of the processor address points to a word of data in the cache-data RAM and
to a tag in the cache tag RAM. If the upper portion of the processor address is equal to the stored tag, a cache
hit is said to occur and the cached data can be immediately sent to the processor.
In a direct-mapped or one-way set associative cache, only one data word and tag exist in cache for each index.
This means that when the processor requests data, only one cache memory location can contain the requested
data. Also, if the requested data is not in the cache and the cache is updated, the data in the indexed cache
memory location will be written over regardless of how recently it has been used.
In a two-way set associative cache, two data words and tags exist for each index. This means that the requested
data can reside in one of two cache locations. When a miss occurs and the cache is updated, the least recently
used data can be written over. As would be expected, studies have shown that the hit rate improves significantly
when using a two-way cache design over a one-way or direct-mapped cache design. Through use of the
'BCT2160, the logic complexity and parts count usually associated with a two-way cache are greatly reduced.
This device is covered by U.S. Patents 4,831,625; 4,837,743; 4,858,182; 4,860,262; 4,884,270; and additional patents pending.
TEXAS
1J1
Copyright © 1990, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
a:
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direct-mapped versus two-way set associative caches
PRODUCT PREVIEW documents contain information on products in the
formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3:
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10-23
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SN74BCT2160
8K x 4 2-WAY CACHE ADDRESS COMPARATOR/DATA RAM
03512. AUGUST 1990- REVISED AUGUST 1990
address comparison
The 'BCT2160 compares the contents of the memory location addressed by AO-A 12 with the address bits (or
tag) applied at 00-03. An equality is indicated by a high level on the MATCH1 or MATCH2 outputs. MATCH1
is high when the applied tag is equal to the stored tag in bank 1. MATCH2 is high when the applied tag is equal
to the stored tag in bank 2.
writing to the 'BCT2160
The 'BCT2160 has been designed with self-timed write circuitry. A high-to-Iow transition at the W input initiates
an internally generated write pulse. After a high-to-Iow transistion at W, W may be held low without initiating
additional write pulses. The manuallauto (MIA) input on the 'BCT2160 provides two methods of selecting which
tag bank will be written to when the write input (Vii) is taken low. When "MIA is low, the bank select input (BSEL)
selects the bank to be written to. BSEL low selects bank 1 and BSEL high selects bank 2. When "MIA is high,
the least recently used (LRU) circuitry automatically selects the bank written to when W is taken low. The BANK
output is latched when Vii goes low. This latch will return transparent when Vii returns high. When W is low the
00-03 outputs are disabled. A high-to-Iow transition at the S input when W is low will not initiate a write
(self-timed) pulse.
writing to the cache data RAMs
When a read or a write miss occurs and the cache is updated, the BANK output will indicate which bank the data
should be written to. If BANK is low, bank 1 should be written to. If BANK is high, bank 2 should be written to.
When writing a tag with "MIA low, the BANK output will not indicate which bank is being selected by the BSEL
input. BANK isthe outputofthe internal8Kx 1 LRU RAM. When a write hit occurs, the match outputs will indicate
which data bank to write to.
LRU replacement circuitry
A concept commonly referred to in cache design is the property of locality. An aspect of the property of locality
says that the information currently in use is likely to be used again soon. Based on this property, it is desirable
to replace the information that has not been used recently when writing to cache. With a set size of two, this is
easily done using one bit to indicate which of the two addressed locations is oldest or least recently used. The
'BCT2160 contains an 8K x 1 RAM and the necessary circuitry to implement the LRU replacement algorithm.
The "MIA input allows the user to choose between automatic LRU and manual replacement. When "MIA is high,
the LRU RAM output selects which bank to write to. When the LRU bit for a given address is low, a write pulse
will write 00-03 to bank 1. When the LRU bit for a given address is high, a write pulse will write 00-03 to bank 2.
The LRU RAM is updated every time a write, a match (with LRU-W signal), or a word reset occurs.
When a write occurs with "MIA high, the addressed LRU bit is inverted and written back in so that the next write
with "MIA high to that address will be to the other bank. When a write occurs with "MIA low, the bank is selected
by the BSEL input and the addressed LRU bit is adjusted so that the next write to the same address with "MIA
high will be to the other bank.
for complete data sheet
The complete version of this data sheet and application information can be found in the Cache Memory
Management Oata Book, Literature #SCA0002. To obtain a copy of this data book, contact your local TI sales
representative or call the TI Customer Response Center at 1-800-223-3200.
TEXAS -111
INSTRUMENTS
10-24
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN74BCT2141
2-WAY 8K x 18 SYNCHRONOUS CACHE DATA RAM
D3613, AUGUST 1990
•
•
•
o
•
•
•
2-Way 8K x 18 Bit Architecture
FN PACKAGE
(TOP VIEW)
Designed Specifically for the i486™
Second-Level Cache
Synchronous Read and Write Access at
50 MHz Clock Frequency
BROY
Incorporates Burst Counter for Burst-Read
(Read-Hit) Cycles or Burst-Write (Line-Fill)
Cycles
Self-Timed Write Cycle and Late Write
Capability
Fast Output Enable Time
BiCMOS EPIC™ 0.8-l-lm Process
3
2
1 5251 5049 48 446
A11
A12
ROY
9
45
GNO
10
44
GNO
000
001
002
003
11
43
12
42
13
41
14
40
0015
0014
0013
0012
GNO
15
39
GND
004
005
006
16
38
17
37
0011
0010
DO?
description
8 7 6 5 4
VCC
36
18
35
19
20
34
21 22232425 262728293031 32 33
DOg
008
VCC
The 'BCT2141 2-wa'y 8K x 18-bit synchronous
cache data RAM is designed to be used in the
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high-performance second-level cache memory
§:<9-l~~~
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system of the i486™ CPU. Synchronized read and
write cycles with the 'BCT2141 can be performed at clock rates as high as 50 MHz. The 'BCT2141 is organized
as two memory banks of 8K x 18. The 18-bit organization gives the designertwo extra bits for byte parity storage.
In addition to these features, the 'BCT2141 has address and data latches and a two-bit burst counter to support
the i486™ burst operations. The on-chip self-timed write control logic completes the write cycles once the write
cycle has been initiated. Bank A of the 2-way memory is enabled and written to by the OEA and WEA signals,
respectively, and bank B by the corresponding OEB and WEB enable signals. The byte enable of both banks
is controlled by the high-order byte enable, HBE, and the lower-order byte enable, lBE. Ultimately, the read and
write accesses of the memory are controlled by the combination of these enable signals.
0
All access cycles, regardless of burst or non-burst cycles, are initiated internally with a low level at the address
status signal (ADS), a low-to-high transition at ClK, and a high level at OEA, OEB, WEA, and WEB. The A2-A 12
address input latches are transparent when OEA, OEB, WEA, and WEB are high. A2-A 12 are latched when any
of these enable signals are low. Address inputs, AO and Ai, are loaded into the burst circuitry during initialization.
Once initialized, the assertion of an output enable signal will output the selected bank to the data outputs. The
assertion of a write enable signal, after initialization, will cause a self-timed write pulse to be generated at the
next rising clock edge provided that ROY or BRDY low, ADS high, and lBE or HBE low. Input data is latched
at the same rising clock edge. The output enable and the write enable inputs also act as burst enable Signals.
Initially, burst and non-burst access cycles are treated identically by the 'BCT2141. A non-burst memory access
cycle is terminated by the de-assertion of the output enable or the write enable signal after one memory transfer.
A burst memory access cycle, on the other hand, sequences through the memory locations on the clock rising
edge with the activation of ready (ROY) or burst ready (BRDY) when the output enable or write enable remains
active. The burst cycle is terminated either by completion of full count transfer (four read or write transfers) or
by the de-assertion of the output enable or the write enable signal. Table 1 shows the 'BCT2141 burst counter
sequences.
EPIC is a trademark of Texas Instruments Incorporated.
i486 is a trademark of Intel Corporation.
This device is covered by patent numbers
PRODUCT PREVIEW Information concerns products in the formative
or design phase of developmenl Characteristic data and other
specifications are design goals. Texas Instruments reserves the right
to change or discontinue these products without nolice.
Copyright © 1990, Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-25
3:
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SN74BCT2141
2-WAY 8K x 18 SYNCHRONOUS CACHE DATA RAM
D3613, AUGUST 1990
description (continued)
A burst read cycle is initiated by either a low-going OEA or a low-going OEB. Only one ofthe output enable signals
is allowed to be low at a time. Enabling both banks simultaneously may electrically damage the device. Typically,
the 'BCT2141 is capable of supplying one word of data perclock cycle after the initial T1 cycle ofthe i486™ during
burst mode. The 'BCT2141 is designed so that each word of data is valid to meet the setup and hold times
required by the i486™. A low BRDY input indicates to the data RAM to continue with the next word of the burst
access. Figure 9 shows a typical non-burst and burst read cycle.
Similarly, a burst write cycle is initiated by either a low-going WEA or a low-going WEB. Again only one of the
write enable signals is allowed to be low at a time. Writing to both banks simultaneously will cause the data being
written to be corrupted. For the burst write cycle, data must be supplied on the data inputs to meet the setup
and hold time requirements of the 'BCT2141. Figure 6 illustrates a typical non-burst and burst write cycle.
Assertion of ROY during a burst cycle interrupts the burst cycle of the i486™. The 'BCT2141 responds to this
interruption by ignoring the address that is supplied by the CPU since this interruption is designed for memory
devices that are not able to respond to the CPU's burst requests. The burst counter of the 'BGT2141 is disabled·'
with a low level at ADS, as provided by the i486™. Upon assertion of the next ROY or BRDY signal, and the
de-assertion of ADS, the 'BCT2141 resumes the burst access cycle with its own internal latched address.
Figure 1a shows an interrupted burst read cycle, and Figure 7 shows an interrupted burst write cycle. Figure 8
illustrates early termination of the burst write cycle with three complete write operations. Figure 11 shows early
termination of the burst read cycle with three complete read operations.
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The SN74BCT2141 is characterized over the commercial temperature range of aoc to 7aoC.
using the 'BCT2141 for other applications
The 'BCT2141 can also be used in applications other than i486™ based cache where the burst counter is not
required. The 'BCT2141 can simply be used in the non-burst mode. The ADS signal must still be used for
initialization and ROY or BRDY must be asserted for proper write operation.
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Table 1 Burst Counter Sequence
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-
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ADDRESS
A1
AO
A1
AO
A1
AO
A1
Starting
Second
Third
0
0
0
1
l'
0
1
AO
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
Fourth
1
1
1
0
0
1
0
0
for complete data sheet
The complete version of this data sheet and application information can be obtained by calling the DVP
Applications Group at 214-997-5762.
TEXAS . .
INSlRUMENlS
10-26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2163, SN74BCT2164, SN74BCT2166
16K x 5 CACHE ADDRESS COMPARATORS/TAG RAMs
D351
•
•
•
'BCT2163 has Totem-Pole Match Output
'BCT2164 and 'BCT2166 have Open-Drain
Match Outputs Tested with 75-pF Load
'BCT2166 has Input Latches
•
Self-Timed Write Circuitry
•
•
•
•
•
REVISED AUGUST 1990
SN74BCT2163, SN74BCT2164
FM PACKAGE
(TOP VIEW)
Fast Address to MATCH Delay ...12-ns Max
•
JUNE 1990 -
AD
A1
A2
A3
Common I/O with Read Feature
Vee
A4
A5
A6
NC
On-Chip Address/Data Comparator
Easily Expanded in Depth and Width
Reliable Advanced BiCMOS Technology
4
6
321 3231 30
29
0
28
7
27
8
26
11
23
GNO
02
03
04
GNO
GNO
MATCH
12
22
Vee
21
13
1415 16 171819 20
Vee
5
9
25
10
24
Fully TTL Compatible
~
Ne - No internal connection
description
The 'BCT2163, 'BCT2164, and 'BCT2166 cache
address comparators each consists of a
high-speed 16K x 5 static RAM array and a 5-bit
high-speed comparator. The 'BCT2166 has
latches at the address, data, and select inputs.
They are fabricated using advanced BiCMOS
technology for high speed and simple interface
with bipolar TTL circuits. The 'BCT2163,
'BCT2164, and 'BCT2166 address comparators
are easily cascaded for wider tag addresses or
deeper tag memories. Significant reductions in
cache memory component count, board area, and
power dissipation can be achieved with these
devices.
3:
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SN74BCT2166 ... FM PACKAGE
(TOP VIEW)
AD
A1
A2
A3
Vee
A4
A5
A6
ALEN
When S is low and Wand R are high, the cache
address comparator compares the contents of the
memory location addressed by AO-A 13 with the
applied 00-04. An equality is indicated by a high
level on the MATCH output.
4
3 2 1 3231 30
29
0
28
a:
11
23
OLEN
02
03
04
GNO
GNO
MATCH
12
22
Vee
21
13
14 15 16 17 18 19 20
Vee
5
6
7
27
8
26
9
25
10
24
>
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The 'BCT2163, 'BCT2164, and 'BCT2166 have been designed with self-timed write circuitry. A high-to-Iow
transition at the W input initiates an internally generated write pulse. After a high-to-Iow transition at W, W may
be held low without initiating additional write pulses. When W is low the 00-03 outputs are disabled. A
high-to-Iow transition at the S input when W is low will not initiate a write (self-timed) pulse. During a write cycle
the input levels on 00-04 are written in the 5-bit memory addressed by AO-A 13.
The 'BCT2163 features a totem-pole MATCH output and the 'BCT2164 and 'BCT2166 feature an open-drain
MATCH output. The 'BCT2164 and 'BCT2166 are designed to reduce the address-to-MATCH slow-down
normally associated with capacitively loaded open-drain outputs and are tested with a high capacitive load.
A read mode is provided with the 'BCT2163, 'BCT2164, and 'BCT2166 which allows the contents of RAM to be
read at the 00-04 pins. The read mode is selected when Rand S are low and W is high.
These devices are covered by U.S. Patents for 4,831 ,625; 4,858,182; 4,884,270; and additional patents pending.
PRODUCT PREVIEW documents contain Information on products In the
formative or design phase 01 development Characteristic data and other
specifications are design goals. Texas tnstruments reserves the right to
change or discontinue these products without notice.
TEXAS
lJ1
Copyright © 1990, Texas Instruments Incorporated
INSTRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-27
SN74BCT2163,SN74BCT2164,SN74BCT2166
16K x 5 CACHE ADDRESS COMPARATORS/TAG RAMs
D3513,JUNE 1990-REVISED AUGUST 1990
description (continued)
A reset input is provided for initialization. When RST is taken low, all 16K x 5 RAM locations are cleared to zero
and the MATCH output is forced high. If an input data word of zero is compared to any memory location that
has not been written into since reset, MATCH will be high indicating that input data is equal to the reset memory
location. By tying a single data input pin high, this bit will function as a valid bit and a match will not occur unless
data has been written into the addressed mer:nory location. When cascading in the width direction only one bit
needs to be tied high regardless of the address width. After power-up, these devices must be initialized by
resetting the device to ensure that all memory locations are at a known state. These devices could also be
initialized by writing to every memory location.
The 'BCT2166 is equipped with latches at the address, data, and select inputs. Input ALEN controls the latch
at the AO-A 13 and S inputs. OLEN controls the latch at the 00-04 inputs. The latches are transparent when
ALEN and OLEN are high and latched when ALEN and OLEN are low.
The SN74BCT2163, SN74BCT2164, and SN74BCT2166 are characterized for operation from O°C to 70°C.
These cache address comparators operate from a single 5-V supply and are offered in a 32-pin PLCC package.
for complete data sheet
The complete version of this data sheet and application information can be found in the Cache Memory
Management Data Book, Literature #SCA0002. To obtain a copy of this data book, contact your local TI sales
representative or call the TI Customer Response Center at 1-800-223-3200.
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TEXAS ."
INSTRUMENTS
10-28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2165
8K x 4 2·WAY CACHE ADDRESS COMPARATORS/TAG RAM
D3614 SEPTEMBER 1990
•
Address to Match Time ... 12 ns Max
•
Simlar to SN74ACT2160 and SN74SCT2160
but with:
- Latches Added
- Integrated Invalidation and Read Cicuitry
- No Manual Operation
•
•
•
•
•
•
•
FM PACKAGE
(TOP VIEW)
2-Way Architecture Significantly Improves
Hit Rate
Implements LRU Replacement Algorithm
l!)v
Ct)C\lT""O
0
««««««0
4
A6
A7
A8
A9
GNO
3 2 1 3231 30
29
0
28
7
27
01
02
03
8
26
Vee
9
25
10
24
MATCH 1
MATCH2
5
6
RESET
LRU-W
11
23
GNO
R
12
22
PE
Useful for Sus Watching
WR
On-Chip Parity Generator and Checker
21
13
14 15 16 17 18 19 20
z
0l~ 10)
0
T""
~
WT""T""
Easily Expandable in Depth and Width
...J««
BANK
C\J
~
Reliable Advanced SiCMOS Technology
Fully TTL Compatible
description
The SN74BCT2165 is a valuable building block for implementing fast two-way set associative caches. This
device consists of two separate 8K x 5 RAMs for tag and parity storage, an 8Kx 1 LRU RAM, two high-speed
comparators, and the control circuitry necessary to give the designer the freedom to determine how this device
will be used. The SN74BCT2165 also includes single-entry invalidation circuitry and parity generation and
checking for ease of design and high system reliability.
The SN7 4BCT2165 is fabricated using advanced BiCMOS technology for high speed and simple interface with
bipolar TTL circuits. By combining the SN74BCT2165 with programmable and/or ASIC logic, a cache can be
constructed that specifically addresses the individual system requirements. Significant reductions in cache
memory component count, board area, and power dissipation can be achieved by using this device.
direct-mapped versus two-way set associative caches
A cache memory is a small high-speed memory that is used to store a portion of the data found in the larger
main memory to achieve optimum processor performance and to reduce main memory bus traffic. Since the
cache memory is smaller than the main memory, only part of the address, the least significant bits referred to
as the index, is used to address the cache memory. The most significant address bits, called the tag, are stored
along with the cache data and are used to identify what data is stored in an indexed location. When the processor
requests data, the index portion of the processor address pOints to a word of data in the cache-data RAM and
to a tag in the cache tag RAM. If the upper portion of the processor address is equal to the stored tag, a cache
hit is said to occur and the cached data can be immediately sent to the processor.
In a direct-mapped or one-way set associative cache, only one data word and tag exist in cache for each index.
This means that when the processor requests data, only one cache memory location can contain the requested
data. Also, if the requested data is not in the cache and the cache is updated, the data in the indexed cache
memory location will be written over regardless of how recently it has been used.
In a two-way set associative cache, two data words and tags exist for each index. This means that the requested
data can reside in one of two cache locations. When a miss occurs and the cache is updated, the least recently
used data can be written over. As would be expected, studies have shown that the hit rate improves significantly
when using a two-way cache design over a one-way or direct-mapped cache design. Through use of the
'BCT2165, the logic complexity and parts count usually associated with a two-way cache are greatly reduced.
This device is covered by U.S. Patents 4,831,625; 4,837,743; 4,858,182; 4,860,262; 4,884,270; and additional patents pending.
PRODUCT PREVIEW documents contain Information on products In
the formative or design phase of development Characteristic data and
other specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.
Copyright © 1990, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-29
3:
-[ijw
a:
D.
tO
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c.
SN74BCT2165
8K x 4 2-WAY CACHE ADDRESS COMPARATOR/TAG RAM
D3614, SEPTEMBER 1990
address comparison
The 'BCT2165 compares the contents of the memory location addressed by AO-A 12 with the address bits (or
tag) applied at 00-03. An equality is indicated by a high level on the MATCH1 or MATCH2 outputs. MATCH1
is high when the applied tag is equal to the stored tag in bank 1. MATCH2 is high when the applied tag is equal
to the stored tag in bank 2.
writing to the 'BCT2165
The 'BCT2165 has been designed with self-timed write circuitry. A high-to-Iow transition at the W input initiates
an internally generated write pulse. After a high-to-Iow transistion at W, W may be held low without initiating
additional write pulses. The bank written at the falling edge of W is automatically selected by the output of the
LRU RAM. When the addressed LRU bit is low, bank 1 is selected; and when the addressed LRU bit is high,
bank 2 is selected. Since the bank to be written to is selected only by the LRU bit the tag should not be rewritten
during a write hit (match). The BANK output is latched when W goes low. This latch will return transparent when
Vii returns high. When W is low the 00-03 outputs are disabled. A high-to-Iow transition at the S input when W
is low will not initiate a write (self-timed) pulse. During a write cycle the input levels at 00-03 plus generated
partity are written into the 5-bit memory location addressed by AO-A 12 in the selected bank.
writing to the cache data RAMs
"'C
When a read or a write miss occurs and the cache is to be updated, the BANK output will indicate which bank
the data should be written to. If BANK is low, bank 1 should be written to. If BANK is high, bank 2 should be written
to. BANK is the output of the internal 8K x 1 LRU RAM. When a write hit occurs, the match outputs will indicate
which data bank to write to.
:D
o
C
C
(1
LRU replacement circuitry
-4
""C
A concept commonly referred to in cache design is the property of locality. An aspect of the property of locality
says that the information currently in use is likely to be used again soon. Based on this property, it is desirable
to replace the information that has not been used recently when writing to cache. With a set size of two, this Is
easily done using one bit to indicate which of the two addressed locations is oldest or least recently used. The
'BCT2165 contains an 8K x 1 RAM and the necessary circuitry to implement the LRU replacement algorithm.
:0
~
m
The LRU replacement algorithm is performed automatically in the 'BCT2165. The LRU RAM output determines
which bank is written to. When the LRU bit for a given address (AO-A 12) is low, a write pulse will write 00-03
to bank 1. When the LRU bit for a given address is high, a write pulse will write 00-03 to bank 2. The LRU RAM
is updated every time a write, a match (with LRU-W signal), or a word reset occurs.
:€
When a write occurs, the addressed LRU bit is inverted and written back in so that the next write to that address
will be to the other bank. When a match occurs (MATCH 1 high or MATCH2 high), the LRU RAM is updated when
the LRU-W input is taken low. The logic level at each match output is fed back internally to the LRU circuitry.
If MATCH1 or MATCH2 are high, the LRU-W input provides an LRU write timing signal that causes an internal
LRU write pulse to be generated. With MATCH 1 high, the LRU bit is set high so the next write to the same address
will be to bank 2. With MATCH2 high, the LRU bit is set low so the next write to the same address will be to bank 1.
When cascading these devices for wider address coverage, the MATCH 1 outputs must be wire-AN Oed together
so an LRU write will not occur unless all MATCH1 outputs are high. In the same manner, the MATCH2 outputs
(in width) must be tied together. When MATCH1 and MATCH2 are forced high during deselect, write, read, word
reset, or reset, and LRU-W is taken low, a false LRU write will not occur. When a word reset occurs, the
addressed LRU bit is updated so that the next write to that address will be to the reset (invalidated) location.
for complete data sheet
The complete version of this data sheet and application information can be obtained by calling the DVP
Applications Group at 214-997-5762.
TEXAS •
INSlRUMENTS
10-30
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TMS4500A
DYNAMIC·RAM CONTROLLER
D2674. JANUARY 1982
•
TMS4500A ... N PACKAGE
Controls Operation of 8K, 16K, 32K, and
64K Dynamic RAMs
(TOP VIEW)
•
Creates Static RAM Appearance
•
One Package Contains Address Multiplexer,
Refresh Control, and Timing Control
•
Directly Addresses and Drives Up to 256K
Bytes of Memory Without External Devices
•
Operates from Microprocessor Clock
No Crystals, Delay lines, or RC
Networks
Eliminates Arbitration Delays
•
Refresh May Be Internally or Externally
Initiated
•
Versatile
Strap-Selected Refresh Rate
Synchronous, Predictable Refresh
Selection of Distributed, Transparent,
and Cycle-Steal Refresh Modes
Interfaces Easily to Popular
Microprocessors
•
ClK
RDY
RENl
•
•
VCC
REFREQ
TWST
FSO
FSl
RA7
CA7
MA7
MA6
CA6
RA6
RA5
CA5
MA5
RA4
CA4
MA4
RA3
CA3
MA3
cs
ALE
RASO
RASl
ACR
ACW
CAS
RAO
CAD
MAO
MAl
CAl
RAl
RA2
CA2
MA2
GND
TMS4500A ... FN PACKAGE
(TOP VIEW)
Strap-Selected Wait-State Generation for
Microprocessor/Memory Speed Matching
w
.-J
•
REVISED AUGUST 1985
IVl
z>-~
w 0
....J
0
U
u~t;;o~
U w 3: Vl Vl
a:f-u...u...
1
Ability to Synchronize or Interleave
Controller with the Microprocessor System
(Including Multiple Controllers)
6 5 4 3 2
3-State Outputs Allow Multiport Memory
Configuration
Performance Ranges of 1 50 ns, 200 ns, or
250 ns
description
The TMS4500A is a monolithic DRAM system
controller designed to provide address multiplexing, timing;, control and refresh/accesss
arbitration functions to simplify the interface of
dynamic RAMs to microprocessor systems.
RASO
RASl
ACR
ACW
CAS
NC
RAO
CAO
MAO
MAl
CA 1
1 4443424140
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
RA7
CA7
MA7
MA6
CA6
NC
RA6
RA5
CA5
MA5
RA4
1819202122232425262728
The controller contains a 16-bit multiplexer that generates the address lines for the memory device from
the 16 system address bits and provides the strobe signals required by memory to decode the address.
An 8-bit refresh counter generates the 256-row addresses required for refresh.
A refresh timer is provided that generates the necessary timing to refresh the dynamic memories and assure
date retention.
The TMS4500A also contains refresh/access arbitration circuitry to resolve conflicts between memory
access requests and memory refresh cycles. The TMS4500A is offered in a 40-pin, 600-mil dual-in-line
plastic package and 44-pin, 650-mil square plastic carrier package. It is characterized for operation from
to 70
ooe
oe.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright
.
© 1985. Texas Instruments Incorporated
TEXAS"
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TeXAS 75265
10-31
TMS4500A
DYNAMIC·RAM CONTROLLER
functional block diagram
8
RAO-RA7
8
ROW
ADDRESS
lATCH
1..--+---1
t-------::~----I
MUl TIPlEXER
8
8
CAO-CA7
'\]
.....-+---t
1-----:10'---'
MAO-MA7
8
ALE------.
1-----11- RASO
CS - - - t - - t
RENl - - - - I.......
ACR - - - - - - - - - - - - - - - -......
ACW ------~-----------......
REF REQ
----...t---t~
'\]1---......-
RASl
TIMING
___t
AND
CONTROL
'" 1 - - - - . - CAS
TWST --------~~
F~ --------~~
1---___-
FSl -----------4~
ClK
R DY
-------~~------~
for complete data sheet
The complete version of this data sheet and application information can be found in the Cache Memory
Management Data Book, Literature #SCAD002. To obtain a copy of this data book, contact your local
TI sales representative or call the TI Customer Response Center at 1-800-223-3200.
TEXAS . .
INSTRUMENTS
10·32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THCT45028
DYNAMIC RAM CONTROLLER
D2989, JUNE 1987 - REVISED MARCH 1990
•
JD OR N PACKAGE
Inputs are TTL- and CMOS-Voltage
Compatible
(TOP VIEW)
•
Controls Operation of 64K and 256K
Dynamic RAMs
•
Creates Static RAM Appearance
•
One Package Contains Address Multiplexer,
Refresh Control, and Timing Control
•
Directly Addresses and Drives Up to
2M Byte of Memory Without External
Drivers
•
Operates from Microprocessor Clock
No Crystals, Delay Lines, or RC
Networks
Eliminates Arbitration Delays
•
Refresh May Be IrHernally or Externally
Initiated
•
Versatile
Strap-Selected Refresh Rate
Synchronous, Predictable Refresh
Selection of Distributed, Transparent,
and Cycle-Steal Refresh Modes
Interfaces Easily to Popular
Microprocessors
Asynchronous RESET Function Provided
in FK and FN Packages
ACW
CASO
RAO
CAO
MAO
MAl
CAl
RAl
RA2
CA2
MA2
GNO
MA3
CA3
RA3
MA4
CA4
RA4
MA5
CA5
RA5
RA6
CA6
MA6
ACR
RAS1
RASa
ALE
cs
RENO
ROY
ClK
RAS3
RAS2
CASl
GND
RENl
9
VCC
MA8
CA8
RA8
REFREQ
TWST
FSO
FSl
RA7
CA7
MA7
FK OR FN PACKAGE
(TOP VIEW)
~
0 00lgI31~1~lg
w
0>
~~~~~~~~~~~~~~@~~
10
•
•
•
•
High-Performance Si-Gate CMOS
Technology
Strap-Selected Wait State Generation for
Microprocessor/Memory Speed Matching
Ability to Synchronize or Interleave
Controller with the Microprocessor System
(Including Multiple Controllers)
3-State Outputs Allow Multiport Memory
Configuration
•
Performance Range:
11 5 ns ALE low to CAS low
•
Functionally Equivalent to TMS4500A/B and
to VTI VL4500A and VL4502
•
Available in Plastic and Ceramic Chip
Carriers in Addition to Plastic and Ceramic
DIPs
•
Dependable Texas Instruments Quality and
Reliability
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.
CAl
RAl
RA2
CA2
MA2
GNO
GNO
MA3
CA3
RA3
MA4
CA4
RA4
NC
NC
11
59
12
58
NC
ClK
13
57
RAS3
14
56
15
55
54
RAS2
CASl
GNO
RENl
16
17
53
18
52
19
51
50
20
21
49
22
48
23
47
24
46
25
45
26
44
VCC
VCC
MA8
CA8
RA8
RESET
REFREQ
NC
NC
2728 293031.32 3234 35363738 3940414243
NC - No internal connection
Copyright © 1990, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-33
THCT4502B
DYNAMIC RAM CONTROLLER
description
The THCT4502B is a monolithic DRAM system controller providing address multiplexing, timing, control
and refresh/access arbitration functions to simplify the interface of dynamic RAMs to microprocessor
systems.
The controller contains an 18-bit multiplexer that generates the address lines for the memory device from
the 18 system address bits and provides the strobe signals required by the memory to decode the address.
A 9-bit refresh counter generates up to 512 row addresses required to refresh.
for complete data sheet
The complete version of this data sheet and application information can be found in the Cache Memory
Management Data Book, Literature #SCAD002. To obtain a copy of this data book, contact your local
TI sales representative or call the TI Customer Response Center at 1-800-223-3200.
functional block diagram t
(3)
RAO
RAI
RA2
~-(9)
RA3
RA4
RA5
RAG
RA7
RAS
(5)
'V
(15)
ROW
(18)
ADDRESS
(21)
lATCH
I
v
CAl
CA2
CA3
CA4
CA5
CAG
CA7
CAS
ALE
'V
(32)
'V
'V
(14)
(IG)
(19)
(20)
(2G)
REFRESH
COUNTER
(33)
~
(45)
'V
I
(23)
t---l
.'V
I:=J
'V
I
I
MA2
MA3
MA4
MA5
(48)
ACW
(I)
(4G)
~"'''''~
t +
(30)
(29)
(28)
1
(41)
RESET (FK and FN packages only }
(34)
'V
I
'V
1
(25)
REFRESH
RATE
GENERATOR
t
1
MAG
MA7
MAS
tt
'V
AcR
(31)
TIMING
RAsO
(47)
(39)
RAS2
(40)
AND 'V
CONTROL
'V
(38)
-r
-~ CASO
'V
---+--
(42)
t
tPin numbers shown are for JD and N packages.
TEXAS . .
INSTRUMENlS
10-34
(13)
(24)
1\,
COLUMN
ADDRESS
lATCH
(17)
lATCH
ClK
'V
MUlTlPlEXER
(7)
SELECT
FSI
MAl
(IO)
(36)
FSO
(II)
(4)
RENO
TWST
~
(G)
(27)
cs (44)
(43)
RENI
'V
(22)
~
CAO
MAO
1\
1---
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ROY
SN74ACT4503
DYNAMIC RAM CONTROLLER
03132, SEPTEMBER 1988-REVISED MAY 1989
•
Inputs are TTl- and CMOS-Voltage
Compatible
JD OR N PACKAGE
(TOP VIEW)
•
Controls Operation of 641(, 2561<, and 1 M
Dynamic RAMs
•
Creates Static RAM Appearance
Q
One Package Contains Address Multiplexer,
Refresh Control, and Timing Control
•
Directly Addresses and Drives Up
to 4 Banks of Memory
•
Operates from Microprocessor Clock
No Crystals, Delay Lines, or RC
Networks
Eliminates Arbitration Delays
•
Refresh May Be Internally or Externally
Initiated
o
Versatile
Strap-Selected Refresh Rate
Synchronous, Predictable Refresh
Selection of Distributed, Transparent,
and Cycle-Steal Refresh Modes
Interfaces Easily to Popular
Microprocessors
Asynchronous RESET
Choice of ClK Polarity on
Refresh/Access Arbitration
CA6
RA7
CA7
RA8
CA8
RAg
CA9
MAg
MA8
MA7
MA6
MA5
GNO
GNO
MA4
MA3
MA2
MAl
MAO
RAO
CAO
RAl
CAl
(TOP VIEW)
High-Performance Si-Gate CMOS
Technology
•
Strap-Selected Refresh Frequencies for
Microprocessor/Memory Speed Matching
NC
NC
MAg
Ability to Synchronize or Interleave
Controller with the Microprocessor System
(Including Multiple Controllers)
MA8
MA7
MA6
MA5
GNO
GNO
MA4
MA3
MA2
MAl
9
•
3-State Outputs Allow Multiport Memory
Configuration
o
Performance Range:
100 ns ALE low to CAS low
•
Functionally Compatible with TMS4500A/B
and with THCT4502B
•
Available in Plastic and Ceramic Chip
Carriers in Addition to Plastic and Ceramic
DIPs
•
Dependable Texas Instruments Quality and
Reliability
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.
VCC
RASa
RASl
RAS2
RAS3
ACW
ACR
ALE
CS
ClK
CA4
RA4
CA3
FK OR FN PACKAGE
•
•
RA6
CA5
RA5
FSl
FSO
RESET
RENO
RENl
ROY
CASl
CASO
GNO
REFREO
8
7
6
5 4
3
2
1 6867666564 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
24
25
45
26
44
NC
NC
RENO
RENl
ROY
CASl
CASO
GNO
REFREO
VCC
RASO
RASl
RAS2
RAS3
ACW
NC
NC
2728293031323334353637383940414243
NC - No internal connection
TEXAS
l!1
Copyright © 1990, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-35
SN74ACT4503
DYNAMIC RAM CONTROLLER
description
The' ACT 4503 is a monolithic DRAM system controller providing address multiplexing, timing, control,
and refresh/access arbitration functions to simplify the interface of dynamic RAMs to microprocessor
systems.
The controller contains an 20-bit multiplexer that generates the address lines for the memory device from
the 20 system address bits and provides the strobe signals required by the memory to decode the address.
A 10-bit refresh counter generates up to 1024 row addresses required to refresh.
A refresh timer is provided to generate the necessary timing to refresh
data retention.
~he
dynamic memories and ensure
for complete' data sheet
The complete version of this data sheet and application information can be found in the Cache Memory
Management Data Book, Literature nSCAD002. To obtain a copy of this data book, contact your local
TI sales representative or call the TI Customer Response Center at 1-800-223-3200.
logic symbol t
CLOCK
•
DYNAMIC RAM
CONTROLLER
'ACT4503
~MAO
!!!!..MA1
1171 MA2
11S) MA3
(15) MA4
(121 MAS
(11) MAS
(10) MA7
(9) MA8
EXTERNAL REFRESH REQUEST
(81 MA9
Q INTERNAL REFRESH REQUEST
ALE (32)
. 9
LE
RAO (20)
RA1 (22)
RA2 (24)
RA3 (2S)
RA4 (28)
ROW
ADDRESS
RA5 (50)
RAS (52)
READY
RA7 (2)
RA8 (4)
RA9 (S)
CAO (21)
o
CA1 (23)
CA2 (25)
CA3 (27)
CA4 (29)
CAS (51)
COLUMN
ADDRESS
CAS (1)
CA7 (3)
CA8 lSI
171
CA9
tThis symbol is in accordance with ANSIIIEEE Std. 91-1984,
Pin numbers shown are for JD and N packages,
10-36
TEXAS ."
IN SJRUMENlS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75266
(44) ROY
SN74ALS6300
INPUT-SELECTABLE REFRESH TIMER
03311. DECEMBER 1989-REVISED JULY 1990
•
Supports 16 Most Popular Microprocessor
Speeds
•
Supports Distributive- and Hidden-Refresh
Operations
•
Polarity Options Available for RFC,
REFREQ, and MREF Signals
description
The 'ALS6300 input-selectable memory refresh
timer allows the user to select one of sixteen
popular divisor rates in order to generate
appropriate refresh timing control signals to a
memory timing control device. The flexible divideby rates are based on the most widely used
microprocessor clock frequencies and the most
common
dynamic
RAM
refresh
timing
requirements. In addition, this device supports
both distributive- and hidden-refresh strategy by
providing a refresh request signal (REFREQ) and
a mandatory refresh signal (MREF). For design
flexibility, the 'ALS6300 provides both active-high
and active-low refresh request outputs (REFREQ
and REFREQ), mandatory refresh outputs (MREF
and MREF), and refresh-complete inputs (RFC
and RFC).
N PACKAGE
(TOP VIEW)
~
U
ClK
80
81 [
16
Vee
2
15
3
14
82
4
13
83
5
12
NC
NC
GND
6
11
7
10
8
9
RFC
RFC
RST
REFREQ
MREF
REFREQ
MREF
1
ow PACKAGE
(TOP VIEW)
Vee
80
NC
NC
81
82
83
NC
NC
NC
GND
11
RFC
NC
NC
RFC
R8T
NC
REFREQ
NC
MREF
REFREQ
MREF
The DRAM memory refresh timer is basically a
programmable frequency divider with special
Ne - No internal connection
modifications to enhance its use as a refresh timer.
The divisor rate is selected by applying the
appropriate logic levels to the 80-S3 inputs shown
in Table 1. When the internal counter reaches the selected divisor rate, REFREQ and REFREQ will go active
(high and low, respectively) and stay active until an active level is seen on the RFC or RFC input. The 'ALS6300
will automatically generate a mandatory refresh signal, MREF and MREF, if an active RFC or RFC is not received
before 20 clock cycles before the next request. An active level on the RFC or RFC input will force REFREQ,
REFREQ, MREF, and MREF to their inactive states.
To achieve distributive refresh, either REFREQ, REFREQ , MREF, or fVi'REF can be used to activate the refresh
cycle. When using hidden refresh, an active level on either REFREQ or REFREQ indicates that a refresh cycle
should be performed immediately after the next memory access cycle. MREF or MREF is used to indicate that
an access has not occurred during the given refresh period and to force the timing controller to initiate a refresh
cycle within the next 20 clock periods.
A low level on the RST input clears the internal counter and sets the REFREQ, REFREQ, MREF, and MREF
outputs to their inactive state on the next active clock edge.
PRODUCTION DATA documents contain Information current IS of
ubliCatiOn date. Products conform to specifications per the terms of Texas
f,nslruments
standard warranty. Production processing does not necessarily
Include lesting of all parameters.
Copyright © 1990. Texas Instruments Incorporated
TEXAS •
INSlRUMENlS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10-37
SN74ALS6300
INPUT·SELECTABLE REFRESH TIMER
03311. DECEMBER 1989-REVISED JULY 1990
logic symbol t
REFRESH TIMER
'AlS6300
SO
Sl
S2
S3
ClK
RST
21:
0
3
FREQ SEl
4
5
3
1
13
REFREQ
ClK
!"-.,
RST
MREF
I
I
12
REFREQ
r--.
10
11
r--.
9
REFREQ
MREF
MREF
14
RFC
RFC
15
!"-.,
IRFC
tThis symbol is in accordance with ANSI/IEEE Std 91-1984.
:I: Pin numbers are for N package.
for complete data sheet
The complete version of this data sheet and application information can be found in the Cache Memory
Management Data Book, Literature #SCAD002. To obtain a copy of this data book, contact your local TI sales
representative or call the TI Customer Response Center at 1-800-223-3200.
TEXAS •
INSlRUMENTS
10-38
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN74ALS6310A, SN74ALS6311A
STATIC COLUMN AND PAGE·MODE ACCESS DETECTORS
03020. JUNE 1987 - REVISED DECEMBER 1989
•
•
OW OR N PACKAGE
Detects Present Row Equal to last Row
Address
(TOP VIEW)
High-Performance Compare:
'AlS6310A ClK to HSA = 18 ns
, AlS6311 A Address to HSA = 14 ns
•
Compatible with 16K to 1 M DRAMs
•
Easily Interfaced with Microprocessor and
Memory Timing Controller
•
Dependable Texas Instruments Quality and
Reliability
elK
Vee
CLKEN
HSA
HSA
83
82
81
80
A9
AS
A7
AD
A1
A2
A3
A4
A5
A6
GND
description
The ' AlS631 OA and ' AlS6311 A are highperformance address comparators designed for
implementing static column and page-mode
access cycles.
When interfaced with the memory timing controller, these devices will detect if the present row being
accessed is the same as the last row accessed. This is the fundamental requirement for implementing
static column decode or page-mode access cycles.
The' AlS631 OA features two 14-bit registers and a high-speed address comparator. The first register is
used to save the' present row address while the second register is used to save the
previous row address. On the high-to-Iow transition of CLK, the first register loads the new row address
present on AO-A9. At the same time, the second register loads the address previously saved in the first
register. The two row addresses are then compared. The High-Speed Access outputs (HSA and HSA) will
signal if the two addresses are equal.
The 80-81 inputs are provided to monitor access cycles to different banks of memory. When used in
conjunction with the' ALS2968 and' ALS6302 series DRAM controllers, the' ALS631 OA and' AlS6311 A
can monitor up to 16 banks of memory. The CLK input on the' AlS631 OA can typically be interfaced with
the microprocessor's Address latch Enable (ALE) or Address Strobe (AS) outputs. This configuration
simplifies the memory timing controller interface. Refer to the typical application diagram for further
information.
The' AlS6311 A features one 14-bit register feeding a high-speed address comparator. This architecture
offers a faster address match time, but does require the memory timing controller to generate the ClK
input. Typically, the 14-bit register would only be updated if there was a change in row or bank address.
Refer to the application diagram for further information.
More information on static column DRAM access can be found in the Texas Instruments application report
System Solutions for Static Column Decode.
The SN74AlS6310A and SN74AlS6311 A are characterized for operation from 0 OCto 70°C.
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of a" parameters.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10-39
SN74ALS6310A, SN74ALS6311A
STATIC COLUMN AND PAGE·MODE ACCESS DETECTORS
FUNCTION TABLE (' ALS631 OAI
INPUTS
FUNCTION TABLE ('ALS6311AI
OUTPUTS
OUTPUTS
INPUTS
CLKEN
CLK
AO-A9
BO-B3
HSA
HSA
CLKEN
CLK
AO-A9
BO-B3
HSA
HSA
H
~
P=Q
P=Q
H
L
H
t
X
X
H
L
H
~
P=Q
P~Q
L
H
X
X
P=Q
P=Q
H
L
H
~
P~Q
P=Q
L
H
X
Not
X
P~Q
L
H
H
~
P~Q
P~Q
L
H
X
Not
P~Q
X
L
H
X
H
X
X
HSAO HSAO
L
X
X
P~Q
L
H
L
X
X
X
HSAO HSAO
L
X
P+Q
X
L
H
P = previous address
Q = present address
logic symbols t
'ALS6310A
'ALS6311A
CLKEN
CLKEN
15C16
CLK
CLK
15C16
COMP
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
BO
Bl
B2
B3
(3)
(4)
15)
(6)
(7)
(8)
(9)
111 )
(12)
(13)
(14)
(15)
(16)
(17)
160
160
160
160
160
160
160
160
160
160
160
160
160
160
Z1
Z2
Z3
Z4
Z5
Z6
Z7
Z8
Z9
Z10
Z11
Z12
Z13
Z14
160
160
160
160
160
160
160
160
160
160
160
160
160
160
COMP
0
P
13
1
2
3
4
P=Q
P=Q
0
(19)
HSA
HSA
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
BO
Bl
B2
B3
(3)
(4)
15)
(6)
(7)
(8)
(9)
111 )
(12)
(13)
(14)
(15)
(16)
(17)
Zl/160
Z2/160
Z3/160
Z4i160
Z5/160
Z6/160
Z7/160
Z8/160
Z9/160
Z10/160
Zll/160
Z12/160
Z13/160
Z14/160
P
1
2
3
4
5
13
0
P=Q
P=Q
(19) HSA
(18) _
--HSA
5
6
7
8
9
10
11
12
13
14
0
6
Q
8
9
10
11
12
13
14
13
Q
13
tThese symbols are in accordance with ANSIIIEEE Std 91 1984 and lEe Publication 617-12.
for complete data sheet
The complete version of this data sheet and application information can be found in the Cache Memory
Management Data Book, Literature #SCAD002. To obtain a copy of this data book, contact your local
TI sales representative or call the TI Customer Response Center at 1-800-223-3200.
'I.!J
TEXAS
INSTRUMENTS
10-40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2423A,SN74BCT2424A
16·BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVER
D3305,JULY 1989- REVISED AUGUST 1990
•
•
Byte Control for Byte·Write Applications
•
Useful in NuBus™ Interface Applications
4!
Useful in Memory Interleave Applications
Multiplexed Real·Time and Latched Data
•
BiCMOS Design Substantially Reduces
Standby Current
"
•
Dependable Texas Instruments Quality and
Reliability
description
The 'BCT2423A and 'BCT2424A are a general-purpose 16-bit bidirectional transceiver with data storage latches
and byte control circuitry arranged for use in applications where two separate data paths must be multiplexed
onto, or demultiplexed from, a single data path, Typical applications include multiplexing and/or demultiplexing
of address and data information in microprocessor- or bus-interface applications. This device is also useful in
memory-interleaving applications. The 'BCT2423A and 'BCT2424A offer inverted dar? paths.
The 'BCT2423A and 'BCT2424A are designed using Texas Instruments BiCMOS process, which features
bipolar drive characte,ristics. In addition, it greatly reduces the standby power of the device when disabled. This
is valuable when the device is not performing an address or data transfer.
Three 16-bit I/O ports, A 15-AO, B15-BO, and AB15-ABO are available for address and/or data transfer. The
AENM, AENL, BENM, BENL, ABEi'JM, and ABENL inputs control the bus transceiver functions. These control
signals also allow byte-control of the most significant byte and least significant byte for each bus.
Address and/or data information can be stored using the internal storage latches. The ALE, BLE, ABLEA, and
ABLEB inputs are active low and are used to control data storage. When the latch enable input is low, the latch
is transparent. When the latch enable input goes high, the data present at the inputs is latched and remains
latched until the latch enable input is returned low.
Data on the 'P\ bus and 'B' bus are multiplexed onto the 'AB' bus via the A;BSEL control line. VYhen A;BSEL is
low, A15-AO is mapped to the AB15-ABO outputs. When A;BSEL is high, B15-BO is mapped to the AB15-ABO
outputs.
z
o
~
:E
a:
o
LL
Z
W
(.)
The 'BCT2423A and 'BCT2424A are characterized for operation from O°C to 70°C.
Z
~
c
«
NuBus is a trademark of Texas Instruments Incorporated,
ADVANCE INFORMATION documenls conlain inlormalion on new producls
in Ihe sampling or preproduclion phase of developmenl Characlerislic
data and other specificalions are subject to change without notice.
TEXAS ~
Copyright © 1990, Texas Instruments Incorporated
INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-41
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVER
03305, JULY 1989 -
REVISED AUGUST 1990
Terminal Functions
PIN
DESCRIPTION
NAME
NO,
AO
A1
A2
A3
A5
A6
A7
A8
A9
A10
A11
A12
A13
5
6
7
8
10
11
12
14
15
16
17
18
19
20
ALEN
(,SCT2166 Only)
13
00
01
02
03
04
31
30
28
27
26
Oata (tag) inputs/outputs. 00-04 are inputs during the compare and write modes. 00-04 are outputs during the
read mode.
OLEN
('SCT2166 Only)
29
Oata latch enable input. When OLEN is high the latch is transparent. When OLEN is low 00-04 are latched.
("')
GNO
1
24
25
29
Ground. (Pin 29 ground is for 'BCT2163 and 'BCT2164 only.)
""C
MATCH
23
When MATCH output is high during a compare cycle, 00-04 equals the contents of the 5-bit memory location
addressed by AO-A13. MATCH is also driven high during deselect, reset, read, and write.
R
2
Read input. When Rand S are low and W is high, addressed data is output to the 00-04 pins and the MATCH
output is forced high.
RST
32
Reset input. Aschronously clears entire RAM array to zero and forces MATCH high when RST is low.
S
4
Chip select input. Enables device when S is low. Deselects device and forces MATCH high when S is high.
VCC
9
21
22
Supply voltage.
3
Write control input. Writes 00-04 into the RAM location addressed by AO-A 13 and forces MATCH high when W
is low. Places selected device in compare mode when Wand R are high and S is low.
A4
""C
JJ
o
C
c:
-t
JJ
m
-
!S
m
:E
-
W
Address inputs. Address 1 of 16K by 5-bit RAM memory locations. Must be stable for the duration of the
write cycle.
Add~ss
and select latch enable input. When ALEN is high the latch is transparent. When ALEN is low AO-A 13
and S are latched.
for complete data sheet
The complete version of this data sheet and application information can be obtained by calling the DVP
Applications Group at 214-997-5762.
.
TEXAS
-1!1
INSTRUMENTS
10-42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LS610, SN74LS612
MEMORY MAPPERS
D2549. JANUARY 1981 -REVISED APRIL 1990
•
•
JD OR N PACKAGE
Expands 4 Address Lines to 12 Address
Lines
(TOP VIEW)
RS2
Designed for Paged Memory Mapping
•
Output Latches Provided on 'LS610
•
3-State Map Outputs
•
Compatible with TMS9900 and Other
Microprocessors
MA3
VCC
MA2
RS3
RS1
CS
MAl
STROBE
RSO
R/W
MAO
011
010
09
08
DO
01
description
Each 'LS610 and 'LS612 memory-mapper
integrated circuit contains a 4-line to 1 6-line
decoder, a 16-word by 12-bit RAM, 16 channels
of 2-line to 1-line multiplexers, and other
miscellaneous circuitry on a monolithic chip.
Each 'LS610 also contains 12 latches with an
enable control.
B~:,0~
~~
{
MAP
OUTPUTS
OATA
}
04
05
MM
BUS I/O
07
06
C (NC)t
~~~
~~~~}
{
M02
M03
M04
M05
M09
M08
M07
M06
MAP
OUTPUTS
The memory mappers are designed to expand a
microprocessor's memory address capability by
eight bits. Four bits of the memory address bus
GNO
_ _-T- ME
(see System Block Diagram) can be used to
select one of 16 map registers that contain 12
tThis pin has no internal connection on the 'LS612.
bits each. These 12 bits are presented to the
system memory address bus through the map
output buffers along with the unused memory address bits from the CPU. However, addressable memory
space without reloading the map registers is the same as would be available with the memory mapper
left out. The addressable memory space is increased only by periodically reloading the map registers from
the data bus. This configuration lends itself to memory utilization of 16 pages of 2(n - 4) registers each
without reloading (n = number of address bits available from CPU).
--~
These devices have four modes of operation: read, write, map, and pass. Data may be read from or loaded
into the map register selected by the register select inputs (RSO thru RS3) under control of R/W whenever
chip select (CS) is low. The data I/O takes place on the data bus DO thru D7. The map operation will output
the contents of the map register selected by the map address inputs (MAO thru MA3) when CS is high
and MM (map mode control) is low. The 'LS612 output stages are transparent in this mode, while the
'LS610 outputs may be transparent or latched. When CS and MM are both high (pass mode), the address
bits on MAO thru MA3 appear at M08-M011, respectively, (assuming appropriate latch control) with low
levels in the other bit positions on the map outputs.
PRODUCTION DATA documents conti in information
currant as of publicltion data. Products conform to
spacifications par the tarms of Taus Instruments
standard warranty. Production processing doe. not
necessarily include testing of all paramaters.
Copyright
© 1990.
Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
10-43
SN74LS610, SN74LS612
MEMORY MAPPERS
system block diagram
n-4
MEMORY ADDRESS BUS
MEMORY MAPPER
MAO-MA3
MOO-M011
SYSTEM
MEMORY
CPU
CONTROL
00-011
DATA AND CONTROL BUS
logic diagram (positive logic)
C
a
(INTERNAL) ALL a LOW FOR MOO-M07 - - 1 - - - ,
4
ME
I
ONLY
'LS610
HAS
LATCH
I
I
I
I
I
I
I
CS---_e-+-...-t
I
I r---'
4
MAO-MA3 --~-+__~-t
~C1
.J
RSO-RS3-;~I--c.._ _
;
~---~
4
I
STROBE-----+-~~
RNV--------L__~
MOO-M07
Moa-M011
DO-D11~~-;1~2---~~12~~~1!~~-J~-t-~--~~______~
'LS612
12
12
FEEDS
STRAIGHT
THROUGH
for complete data sheet
The complete version of this data sheet and application information can be found in the Cache Memory
Management Data Book, literature #SCAD002_ To obtain a copy of this data book, contact your local
TI sales representative or call the TI Customer Response Center at 1-800-223-3200_
TEXAS •
INSTRUMENTS
10-44
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS6328, SN74AS632
32-81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
D3396, JANUARY 1986-REVISED JANUARY 1990
•
Detects and Corrects Single-Bit Errors
•
Detects and Flags Dual-Bit Errors
•
Built-In Diagnostic Capability
•
Fast Write and Read Cycle Processing Times
•
o
N OR JD PACKAGE
(TOP VIEW)
LEDBO
ERR
Byte-Write Capability
Dependable Texas Instruments Quality and
Reliability
The ALS632B and' AS632 devices are 32-bit
parallel error detection and correction circuits
(EDACs). The EDACs use a modified Hamming
code to generate a 7-bit check word from a
32-bit data word. This check word is stored
along with the data word during the memory
write cycle. During the memory read cycle, the
39-bit words from memory are processed by the
EDACs to determine if errors have occurred in
memory.
OB30
OB2
OB29
OB28
OB27
OB26
OEBO
OB6
OEB3
OB25
OB7
OB24
GND
GNO
OBB
OB9
OEBl
OB23
OB22
OEB2
OB10
OB21
OBll
OB20
OB12
OB19
OB13
OB14
OB18
OB17
OB16
CB6
CBO
CBl
CB5
CB4
CB2
OECS
Single-bit errors in the 7-bit check word are
flagged, and the CPU sends the EDAC through
the correction cycle even though the 32-bit data
word is not in error. The correction cycle will
simply pass along the original 32-bit data word
in this case and produce error syndrome bits to
pinpoint the error-generating location.
CB3
FN PACKAGE
(TOP VIEW)
a:
N~Oa:a:
U U en en en Ia: w
I~
~
0 Cl)
uu
MMN
.
U U ~ 0 en en en u u
ZZOOOw2~»~~000zz
I
9 8
NC
OB5
13
14
15
16
OB6
OB7
5 4 3 2
1 68 67 666564 63 62 61
60
12
OEBO
7 6
[3
10
OB4
NC
59
NC
58
57
OB28
OB27
OB26
56
55
54
OEB3
OB25
GNO
17
53
OB24
GNO
18
19
52
51
50
GNO
OB23
49
48
47
46
OB20
OB8
OB9
OEBl
Diagnostics are performed on the EDACs by
controls and internal paths that allow the user
to read the contents of the DB and CB input
latches. These will determine if the failure
occurred in memory or in the EDAC.
OBl
OB15
Single-bit errors in the 32-bit data word are
flagged and corrected.
Read-modify-write (byte-control) operations can
be performed by using output latch enable,
LEDBO, and the individual OEBO thru OEB3 byte
control pins.
SO
OB31
OB5
I
Dual-bit errors are flagged but not corrected.
These errors may occur in any two bits of the
39-bit data word from memory (two errors in the
32-bit data word, two errors in the 7-bit check
word, or one error in each word). The gross-error
condition of all lows or all highs from memory
will be detected. Otherwise, errors in three or
more bits of the 39-bit word are beyond the
capabilities of these devices to detect.
OBO
OB3
OB4
description
PRODUCTION DATA documents contain information
current as of publication date. Products conform to
specifications per the terms of Texas Instruments
standard warranty. Production processing does not
necessarily include testing of all parameters.
VCC
Sl
MERR
OB10
OBll
OB12
OB13
OB14
20
21
22
23
24
25
26
GNO
OB21
45
OB19
44
OB18
2728293031323234353637383940414243
uuu~U~~~lenMN~O~~UU
zzz~zenenenuenenenen~~zz
en
o
NC
uuuwuuuuenen
0
00
No internal connection
Copyright © 1990, Texas Instruments Incorporated
TEXAS •
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
10-45
SN74ALS6328, SN74AS632
32·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS
logic symbol t
EDAC
'ALS632B
'AS632
~ t
SO
Sl
.J"-....
OEBO
r--..
OEBl
r--..
OEB2
_ _ J::,.
OEB3
r--..
.f'.,
MODE
EN (OBO·OB7)
EN (OB8·0B15)
EN (OB16·0B23)
EN (OB2~·OB31)
EN (CBO·CB6)
LEOBO
..,
r
OBO·OB7
~ IV'
OB8·0B15
1~ IV'
OB16·0B23
16
- - - 23
1'7
OB24·0B31
r-r--
ERR
MERR
241
31
~
0
....
A
CHECK
BITS
"
CBO
'7.
y
6
CB6
V'
TERMINAL FUNCTIONS
DESCRIPTION
PIN NAME
CBO·CB6
OBO-OB31
ERR
GNO
LEDBO
MERR
NC
Check Bit data port. This 7-bit I/O port is used to output check bits during write cycles and input memory check bits
during read cycles.
Data port, This 32·bit I/O port is used to input processor data during memory write cycles and used to output
corrected data during memory read cycles.
Single·Bit Error Flag. This active· low output Signals when a single-bit error has occurred. When more than two errors
occur, this output is unpredictable.
Ground
Output Latch Enable. This input controls the output data latch that stores the corrected data word. When low, data
is allowed to flow through the latch. When taken high, data present at the inputs of the output data latch is stored.
Multiple-Bit Error Flag. This active· low output signals when a double· bit error has occurred. When more than two
errors occur, this output is unpredictable.
No internal connection
Data Output Enable controls. These active· low inputs are used to enable data onto the data bus (OBO·OB31). Each
OEBO·OEB31
input controls 8·bits for byte control operations. OEBO controls OBO·OB7, OEBl controls OB8-0B15, OEB2 controls
DB 16·0B23, and OEB3 controls OB24·0B31 .
OECB
Check Bit Output Enable control. This active·low input is used to enable the check bits onto the check bit bus (CBO·CB61.
50,51
Mode Select controls. These control inputs select the mode of the EOAC. See function tables for details.
VCC
Supply voltage
for complete data sheet
The complete version of this data sheet and application information can be found in the Cache Memory
Management Data Book,. Literature #SCAD002, To obtain a copy of this data book, contact your local
TI sales representative or call the TI Customer Response Center at 1-800-223-3200.
TEXAS •
INSTRUMENTS
10-46
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AS632A
32·BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUIT
03397. JANUARY 1990
N OR JD PACKAGE
•
Detects and Corrects Single-Bit Errors
•
Detects and Flags Dual-Bit Errors
•
Built-In Diagnostic Capability
•
Fast Write and Read Cycle Processing Times
(TOP VIEW)
LEDBO
vCC
51
MERR
ERR
SO
DB31
DBa
•
•
DBl
Byte-Write Capability
Dependable Texas Instruments Quality and
Reliability
description
The AS632A device is a 32-bit parallel error
detection and correction circuit (EDAC). This
EDAC uses a modified Hamming code to
generate a 7-bit check word from a 32-bit data
word. This check word is stored along with the
data word during the memory write cycle. During
the memory read cycle, the 39-bit words from
memory are processed by the EDAC to
determine if errors have occurred in memory.
ADVANCE INFORMATION concerns new products in
the sampling or preproduction phase of development.
Characteristic data and other specifications are
subject to change without notice.
DB28
DB27
DB26
OEB3
DB6
DB25
DB7
DB24
GND
GND
DBB
DB9
OEBl
DB23
DB22
DB10
OEB2
DB21
DBll
DB20
DB12
DB19
DB13
DB18
DB14
DB15
DB17
DB16
CBO
CBl
CB6
CB5
CB4
CB2
CB3
OECB
Single-bit errors in the 7-bit check word are
flagged, and the CPU sends the EDAC through
the correction cycle even though the 32-bit data
word is not in error. The correction cycle will
simply pass along the original 32-bit data word
in this case and produce error syndrome bits to
pinpoint the error-generating location.
Diagnostics are performed on the EDAC by
controls and internal paths that allow the user
to read the contents of the DB and CB input
latches. These will determine if the failure
occurred in memory or in the EDAC.
DB3
DB4
DB5
Single-bit errors in the 32-bit data word are
flagged and corrected.
Read-modify-write (byte-control) operations can
be performed by using output latch enable,
LEDBO, and the individual OEBO thru OEB3 byte
control pins.
DB30
DB29
OEBO
I
Dual-bit errors are flagged but not corrected.
These errors may occur in any two bits of the
39-bit data word from memory (two errors in the
32-bit data word, two errors in the 7-bit check
word, or one error in each word). The gross-error
condition of all lows or all highs from memory
will be detected. Otherwise, errors in three or
more bits of the 39-bit word are beyond the
capabilities of this device to detect.
DB2
FN PACKAGE
(TOP VIEW)
9 8
NC
7 6
5 4 3 2
1 6867666564 63 62 61
M
10
59
NC
NC
DB4
DB5
12
13
58
57
DB28
DB27
OEBO
DB6
OB7
GND
14
15
16
17
56
55
54
53
DB26
OEB3
DB25
DB24
GND
DBB
18
19
52
51
GNO
GND
DB9
OEBl
20
21
50
49
DB23
DB22
DB 10
DBll
DB 12
22
23
24
48
47
46
OEB2
DB21
DB20
DB13
25
45
DB19
DB 14
26
44
DB 18
2728293031323234353637383940414243
U U U to U co en q ICIl (") N ~ 0 co r-- U U
ZZZ~Z~CIlCIlUCIlCIlCIlCIl~~ZZ
CIl
uuuwUUUUCIlCIl
o
NC
0
00
No internal connection
Copyright © 1990. Texas Instruments Incorporated
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
10-47
SN74AS632A
32·81T PARALLEL ERROR DETECTION AND CORRECTION CIRCUIT
logic symbol t
EOAC
'AS632A
'AS632
~
SO
51
OEBO
OEB1
OEB2
OEB3
r---
}
MOOE
r--r-....
EN
EN
EN
EN
r---.
EN (CBO·CB6)
r--..,
.f'-..
ERR
"-
MERR
~
(OBO·OB7)
(OB8·0B15)
(OB16·0B23)
(OB24·0B31)
LEOBO
r
L.1
OBO·OB7
~ \\7
OB8·0B15
1~ \\7
OB16·0B23
OB24·0B31
indicates a dynamic input) the 0 inputs of the ten
address registers 10 through 19. When CAS goes low, it momentarily enables (through C21) the 0 inputs of the
ten address registers 0 through 9. The outputs of the address registers are in 20 internal address lines that select
1 of 1 048 576 cells.
TEXAS
~
INSTRUMENTS
11-4
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
Logic Symbols
Refresh
RAS
~
When RAS goes low, row refresh starts. It ends when RAS goes
high. The other input signals required for refreshing are not
indicated by the symbol.
[REFRESH ROWI
Power Down
RAS
CAS
--1
--i
CAS is ANDed with RAS (through G24) so when RAS and CAS
are both high, the device is powered down.
24 [PWR OWN]
G24
Write
By virture of the AND· relationship between CAS and W
(explicitly shown), when either one of these inputs goes low with
the other one and RAS is already low (RAS is ANDed by G23),
the D input is momentarily enabled (through C22). In an
"early-write" cycle it is W that goes low first; this causes the
output to remain off as explained below.
RAS.~23
CAS
&
23C22
Iii
o
A,220
Read
24EN
A\1 - - -
The ANDed result of RAS and W (produced by G23) is
clocked into a latch (through C21) at the instant CAS
goes low. This result will be "1" if RAS is low and Wis
high. The complement of CAS is shown to be ANDed with
the output of the latch (by G24 and 24). Therefore, as
long as CAS stays low, the output is enabled. In the
"early-write" cycle referred to above, a "0" was stored in
the latch by W being low when CAS went low, so the
output remained disabled.
a
If you have any questions on the Explanation of IEEE/IEC Logic Symbols, please contact:
F.A. Mann, MS 3684
Texas Instruments Incorporated
P.O. Box 655303
Dallas, Texas 75265
Telephone: (214) 997-2489
IEEE Standards may be purchased from:
Institute of Electrical and Electronics Engineers, Inc.
345 East 47th Street
New York, New York 10017
International Electrotechnical Commission (lEG) publications may be purchased from:
American National Standards Institute, Inc.
1430 Broadway
New York, New York 10018
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Logic Symbols
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Quality and Reliability
Quality and Reliability
Quality and Reliability
MOS MEMORY QUALITY AND RELIABILITY STRATEGY
Texas Instruments is committed to providing its customers with reliable, high quality memory products. MOS
Memory management has applied a four point quality and reliability strategy to:
• Provide customers with the lowest cost of product ownership through quality, reliability, and service by:
- On-time delivery to minimize customer inventory.
- Quality performance that justifies ship-to-stock certification and eliminates the cost of component testing.
- No system manufacturing fallout.
- No warranty and service costs.
• Develop partnership relationships to service and solve customer problems and anticipate upcoming needs.
• Live quality improvement process from product creation and manufacturing through product sales via our total
quality control approach of:
- Quality Function Deployment.
- Design-in and bUild-in quality and reliability.
- In-control manufacturing.
- Leadership customer service.
• Measure Tl's performance by the customer's measurement and perception. The performance standard is continuous customer satisfaction.
Total Quality Control (TQC)
Total Quality Control at TI is a business management process encompassing all company functions. The goal
of Total Quality Control (TQC) is continuous customer satisfaction. Utilizing a process of improvement through a positive feedback cycle, TQC is deployed in the MOS Memory Division from the initial design-in Q&R stage, in-control
manufacturing, and customer service (see Figure 1).
Proper application ofthe concept of "PLAN-DO-CHECK-ACT" allows a positive feedback loop that creates continuous improvement and breakthrough, as opposed to the "FIX-FIX-FIX-FIX" results of a negative loop (see Figure 2).
Quality Function Deployment
Continuous customer satisfaction can be achieved only by fully understanding customer needs, then introducing
innovative products that satisfy those needs. Quality Function Deployment (QFD) accomplishes both purposes at TI.
QFD is a technique that systematically records the voice of the customer, identifying product and service attributes
most important to the customer. QFD then blends these needs with the talents and innovations of a TI design team
to define a manufacturable, reliable product solution for the customer.
Design-In Quality and Reliability
Quality and reliability improvements at TI start with the chip and package design. The objective of MOS Memory's
Design-In Quality and Reliability (DIR) thrust is first-pass qualification of new products, internally and at the customer.
The TI approach to DIR has been to understand customer requirements of a product, and to formalize this knowledge
into a database that incorporates both reliability modeling knowledge, and "lessons learned" from historical problems
and engineering evaluations. Before any new design is approved, the design is verified against a DIR "checklist". Design verification is planned to evolve to computer verification utilizing artificial intelligence.
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Quality and Reliability
PLAN
Understand
Customer
Care-abouts
DO
Product
Specification
Define
Requirements
Establish
Baseline
Design rules/
Package
Capability
Document/Audlt/
Control
Through
Standards/SPC
CHECK Customer
Survey
Process
Assurance
ACT
Analysls/
Improvement
Improve
Design
Measure/Assess
Through
Reliability
Testing
Product/Process
Improvement
Understand Needs
Service - On-time
Delivery,
JIT(Just In Time),
Ship-To-Stock,
Joint Qualification
Support - Field
Through Factory
Verify - Feedback
With Customer
Assessment
Figure 1, Total Ouallty Control
To Positive Loop
From Negative Loop
Figure 2. TOC Philosophy
In-Control Manufacturing
Documentation/Audit System
To assure in-control manufacturing, TI employs a hierarchical specification system. General specifications on all
aspects of quality, reliability, and customer service are written and controlled by the central Quality and Reliability
group. More detailed speCifications control the operating practices of design, manufacturing, marketing, and other
support organizations. These specifications follow guidelines set by the higher-level specifications, but concentrate
on the type of business entity.
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Quality and Reliability
Regularly scheduled audits are performed within TI to ensure compliance with all specifications. The five types
of audits performed are:
1. Self audit: An internal audit within each functional operation. This type of audit is conducted by persons within the
operation and an additional person from outside the operation.
2. Cross-audit: An audit by persons independent of the operation being audited.
3. Group audit: An audit of an operation conducted by the Semiconductor Group audits and procedures function,
which is a part of the central Quality and Reliability organization.
4. Procedures audit: An audit of lower-level specifications with respect to higher-level specifications.
5. Compliance audit: An audit of operating practices with respect to specifications.
Statistical Process Control (SPC)
Quality improvement is achieved through Statistical Process Control (SPC). SPC is applied throughout the
manufacturing operations of the MOS Memory division. The objectives of SPC are:
- Control processes on a realtime basis.
- Improve process capability (CP).
- Reduce variability to target value (CPl<).
- Eliminate "out-of-spec" lots.
- Achieve dependable delivery.
- Lower cost-of-quality.
Computer hardware and artificial intelligence software have been coupled to establish interactive control allowing
the computer to generate realtime control charts and prompt adjustments to equipment and processes
(see Figure 3).
Identify Problems and
Data Collection·
- Pareto of Defects
U
L.....----I
Training
- SPC
- Design of Experiments
Identify Source of Variation
- Multi-Variable Chart
- Fish-Bone
D
Control Charts
- Control to Target
- Reduce Variability
<.------
Capability Studies
- Process Spread
- Spec Spread
Figure 3. Computer-Aided Statistical Process Control
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Quality and Reliability
Die Fabrication Control
In addition to extensive SPC applications in our MaS fabrication centers, TI implements wafer-level quality and
reliability controls.
Wafer-level quality control focuses on reduction of variability around target values (CPK) for key functionality parameters and controls the processes that affect these parameters. For example: Column access time (tcAd is a key
DRAM parameter. One of the die manufacturing processes that affects tCAC is the photo etch. To reduce variability
of the target value of tCAC, we control polysilicon width dimension at the photo etch process.
Wafer-level reliability controls address process control of known reliability hazards. For example: Excessive phosphorus use in die processing can lead to corrosion defects in the finished device. Wafer-level reliability controls require
that phosphorus level control is built into the manufacturing process and that action is prescribed for out-of-control
material. Other wafer-level reliability controls are shown in the following table.
Table 1. Wafer Reliability Controls
PARAMETER
CONTROL
Metal
Electromigration Testing, Grain Size, Silicon Nodule Monitor
Step Coverage/Metal Necking Monitor
Stress-Induced Metal Void Testing
Protective Overcoat·
P.O. Integrity
Stress Testing
Thickness Monitor
Refraction
Corrosion
% Phosphorus In Multilevel Oxide Monitor
Gate Oxide Integrity
Breakdown Voltage
Device Assembly Control
TI has also implemented assembly level reliability controls and SPC at critical assembly points (see Table 2) to
ensure highly reliable device packaging. Each parameter has certain controls performed at appropriate frequencies
to ensure that assembly processing is at qualified levels. Controls may be added or reduced after extensive testing
has been performed. Results are carefully studied and fed back to preclude reliability problem introduction into the
assembly process. Some of the parameters and controls are shown in Table 3.
Table 2. Major Assembly Steps Using
spc/sac t
PLASTIC DEVICE ASSEMBLY
Process
Control Parameter
% Coverage of Epoxy
Mount
Bond
Bond Strength
Mold
Temperature and Molding Parameters
Trim/Form
Lead Deflection (DIP)
CERAMIC DEVICE ASSEMBLY
Bond
Bond Strength
Seal
Seal Furnace Temperature
tStatistical Process Control/Statistical Quality Control
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Quality and Reliability
Table 3. MOS Memory Assembly Level Reliability Controls
CONTROL
PARAMETER
P.O. Integrity
Contactiess Wafer Mount on Tape Die Mount System
Mold Compound Parameters
Chip/Crack
Visual Inspection
Temp Cycle
Saw Blade Conditions
Poker Pin Height
Wet Etch Monitor (EPROM)
Bond Integrity
Bond Strength Monitor
Bond Parameters
Bake/Bond Pull Monitor
Capillary Change
Package Integrity
Visual Inspection
Mold Press Parameters (Plastic)
X-Ray Inspection (Plastic)
Trim/Form (Plastic)
Package Seal (Ceramic)
Temp Cycle (Ceramic)
Hermeticity Monitor (Ceramic)
Die Mount Integrity
Die-Shear Monitor
Centrifuge Monitor
X-Ray Inspect
Leadframe Polyimide Pattern Inspect
Pick-Up Arm Force
Contamination
Visual Inspection
Product Assessment/Improvement
Reliability Control System
The MOS Memory reliability control system (Figure 4) provides closed-loop-system feedback resulting in corrective actions and ongoing product improvements. Each new product, process, or major change to an existing product
is internally qualified to industry leadership standards prior to production. This is followed by intensive monitoring during production ramp-up and routine monitoring of more than 20,000 units a month once a product achieves final production release. In 1989 almost two million memory devices were tested in all phases of the reliability control system.
Reliability Development Issues
Soft Error: TI does extensive work in all phases of device development to minimize the effects of soft errors. Soft
errors are ca~sed by alpha particles emitted by the decay of small amounts of thorium and uranium located in device
packaging materials. TI maintains an aggresive program of evaluating new mold compounds to ensure low alpha emmissivity. Certain device design and processing techniques are also applied to ensure a low soft error rate. The goal
of device design and processing is to maximize the cell capacitance by employing an oxide-nitride dielectric, as opposed to an oxide dielectric. Also, the cell capacitance increases as the dielectric thickness decreases. Testing has
shown that the trench capacitor used in dynamic RAMs has competitive soft error rates.
Channel Hot Electron: Channel hot electrons are caused by impact ionization in the drain pinch-off region.
Electrons are accelerated toward the drain, collide with positive ions, and can be trapped in the gate oxide. This
trapped charge can change the characteristics of the transistor by raising the VT (threshold voltage). One method
employed to reduce the effects of hot electrons is to add a lightly doped drain to reduce the electric field at the gate.
Testing for channel hot electrons is performed at a low temperature (-10°C) and a high drain voltage.
. Latch-up: A CMOS device can latch-up when the gain of the parasitic PNP+NPN transistors is greater than 1.
These PNP+NPN transistors act as a silicon controlled rectifier (SCR). If enough current flows through the resistors,
the transistors will turn on and the device will latch-up.
To control latch-up, the SCR gain must be controlled to less than or equal to one. Methods for improving latch-up
immunity include incorporating guard rings between P+ and N+ diffusions, and isolating P+ and N+ diffusions.
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Quality and Reliability
Latch-up testing is performed to ensure our CMOS devices meet the minimum holding current for industry
standards.
Customer Service
Quality, Reliability, Service, and the Cost of Ownership
The goal of Texas Instruments is to offer the best quality, reliability, and seNice in the semiconductor industry. The
foundation for this approach is to ship consistent quality. Consistent quality allows ship-to-stock programs that foster
the elimination of the customer's incoming inspection. Ship-to-stock quality, coupled with 100% on-time delivery to
narrow shipping windows means support of the customer's just-in-time manufacturing program. This combination of
quality, reliability, and seNice can be measured by a single index called "the cost of ownership". The "cost of ownership" is defined as being composed of the purchase price, quality adders (for incoming inspection and board rework),
inventory adders (for maintenance of a buffer inventory for suppliers who cannot meet just-in-time delivery), in-house
reliability adders (for system burn-in and rework), and field reliability adders (for warranty and post-warranty field
repairs).
For more information about the cost of ownership concept, contact your local TI sales office and request the
brochure "Texas Instruments Lowers Semiconductor Cost of Ownership", SSYB057.
Quality Improvement
Significant improvement in product quality has been achieved through:
- Better definition of customer's requirements.
- Greater emphasis on quality as a deSign criterion.
- Improved control of incoming materials.
- Intensive training of supeNisors and operators.
- Extensive use of statistical process control.
- More automation of operations to minimize operator-related defects.
QUALIFICATION
.
Baseline process
Up to 7000 units tested
# OF UNITS
DRAM EPROM
125°C Op life
1100
EFRt
2000
85/85
300
Temp. cycle
600
Press. cooker test 300
PSP/PVPl
100
Static bias/storage 250
Soft error
2000
Data ret. bake
Electromigration
150
Package integrity
470
ESD
30
Baseline process
100% reliability lot acceptance concurrent
with qualifications
3 - 6 diffusion lots
TEST
PRODUCTION RAMP LOT ACCEPT
300
1000
150
-
300
OTP
200
500
200
600
200
200
150
-
-
600
150
150
200
20
-
400
20
Review of data once sufficient lots have
been sampled
# OF lOTS
DRAM EPROM
TEST
EFRt
150
High temp. rev. bias Temp. cycle
50
Press. cooker test
50
Bake
-
100
50
50
-
50
OTP
100
50
50
50
50
t EFR (Early Failure Rate):
DRAM -125°C OPl, 80 hours
EPROM & OTP - 200°C bake, 44 hours (OTP in ceramic package)
l PSP: Pressure cooker, Sauter dip, Pressure cooker
PVP: Pressure cooker, Vapor phase, Pressure cooker
Figure 4. Reliability Control System
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FINAL PRODUCTION RELEASE
Control each package/wafer fabrication
site/device combination
Ongoing reliability monitor of 125°C op
life, data retention bake, temperature
cycle, 85/85, autoclave, package
integrity, and internal cavity moisture
Control limits for each test
Approximately 20,000 units tested each
month
Early failure rate monitor
Quality and Reliability
As is demonstrated in Figure 5, MaS Memory EPROM and DRAM outgoing quality has dramatically improved
during the last few years. This significant improvement has occurred for all TI product lines and has been recognized
publicly by many of our customers, who have given TI more than 70 major quality awards in the last three years. Included among these awards are Ford's Q-1 Award, the U.S. Naval Quality Award, and the Deming Prize, which is
Japan's most prestigious quality award.
Reliability Improvement
Low Ie failure rates are achieved through design-in reliability, computer aided design, stringent qualification testing prior to product release, routine monitoring of released products, and an extensive failure mode tracking and
feedback system for Ie failures.
Since the early '80's, MaS Memory products have exhibited a device failure rate improvement trend, which has
resulted in highly reliable memory devices (see Figure 6). Even though the memory device complexity increases in
an ongoing manner, TI's failure rate by function has improved at an even faster pace. TI continues to emphasize reliability improvement as a major factor in reducing the total cost of ownership for our customers. Reliability improvement
is reflected as a reduction in the expected field failures during system lifetime.
Up-to-date quality and reliability data for MaS Memory products is available. Please contact your local TI sales
office for information.
1500
1400
1300
1200
'0
1100
CIl
~ 1000
u-
S?
a.
~
900
800
c
~ 700
:E 600
..
CIl
a. 500
III
1::
III
a.
400
300
200
100
0
1983
1984
1985
1986
1987
1988
1989
Figure 5. MOS Memory Quality Improvement
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Quality and Reliability
650
EPROM
600
550
500
450
400
350
(J)
I-
u::
300
250
200
150
100
50
0
1983
1984
1985
1986
1987
Figure 6. MOS Memory Reliability Improvement
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1988
1989
Electrostatic Discharge Guidelines
Electrostatic Discharge Guidelines
Guidelines for Handling Electrostatic-Oischarge-Sensitive (ESOS)
Devices and Assemblies
Scope
This specification establishes the requirements for methods and materials used to protect electronic parts, devices, and assemblies (items) that are susceptible to damage or degradation from electrostatic discharge (ESD). The
electrostatic charges referred to in this specification are generated and stored on surfaces of ordinary plastiCS, most
common textile garments, ungrounded person's bodies, and many other commonly unnoticed static generators. The
passage of these charges through an electrostatic-sensitive part may result in catastrophic failure or performance
degradation of the part.
The part types for which these requirements are applicable include, but are not limited to, those listed:
1.
2.
3.
4.
5.
6.
7.
All metal-oxide semiconductor (MOS) devices; e.g., CMOS, PMOS, etc.
Junction field-effect transistors (JFET)
Bipolar digital and linear circuits
Op-amps, monolithic microcircuits with MOS compensating networks, on-board MOS capacitors, or
other MOS elements
Hybrid microcircuits and assemblies containing any of the types of devices listed
Printed circuit boards and other types of assembly containing static-sensitive devices
Thin-film passive devices
Definitions
1.
Electrostatic Discharge (ESD): A transfer of electrostatic charges between bodies at different electrostatic potentials caused by direct contact or electrostatic field induction.
2.
Conductive material: Material having a surface resistivity of 105 Q/square maximum.
3.
Static dissipative material: Material having a surface resistivity between 105 and 109 Q/square.
4.
5.
Antistatic material: Material having a surface resistivity between 109 and 10 14 Q/square
Surface resistivity: An inverse measure of the conductivity of a material and is the resistance of unit length
and unit width of a surface. Note: Surface resistivity of a material is numerically equal to the surface resistance between two electrodes forming opposite sides of a square. The size of the square is immaterial.
Surface resistivity applies to both surface and volume conductive materials and has the dimension of Q/
square.
Volume resistivity: Also referred to as bulk reSistivity. It is normally determined by measuring the resistance (R) of a square of material (surface resistivity) and multiplying this value by the thickness (T).
Ionizer: A blower that generates positive and negative ions, either by electrostatic means or from a radioactive energy source in an airstream, and distributes a layer of low velocity ionized air over a work area
to neutralize static charges.
Close proximity: For the purpose of this specification, 6 inches or less.
6.
7.
8.
Device Sensitivity per Test Circuit of Method 3015, MIL-STD-883C
1.
2.
Devices are categorized according to their susceptibility to damage resulting from electrostatic discharges (ESD).
ESD Sensitivity
Category
o V -1999 V
Class 1
2000 V - 3999 V
Class 2
Class 3
4000 V and above
Devices are to be protected from ESD damage from receipt at incoming inspection through assembly,
test, and shipment of completed equipment.
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Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS)
Devices and Assemblies
Applicable Reference Documents
The following reference documents (of latest issue) can provide additional information on ESD controls.
1.
2.
3.
4.
5.
6.
7.
8.
MIL-M-38510 Microcircuits, General Specification
MIL-STD-883 Test Methods and Procedures for Microelectronics
MIL-STD-19491 Semiconductor Devices, Packaging of
MIL-M-55565 Microcircuits, Packaging of
DOD-HDBK-263 Electrostatic Discharge Control Handbook for Protection
DOD-STD-1686 Electrostatic Discharge Control Program
NAVSEA SE 003-11-TRN-010 Electrostatic Discharge Training Manual
JEDEC Standard Publication 108
Facilities for Static-Free Workstation
The minimum acceptable static-free workstation shall consist of the work surface covered with static dissipative
material attached to ground through a 1 MQ ± 10% resistor, an attached grounding wrist strap with integral 1 MQ ±
10% resistor for each operator, and air ionizer(s) of sufficient capacity for each operator. The wrist strap shall be connected to the static dissipative material. Ground shall utilize the standard building earth ground; refer to Figure 1. Conductive floor tile/carpet along with conductive shoes may be used in lieu of the conductive wrist straps for non-seated
personnel. The Site Safety Engineer must review and approve all electrical connections at the static-free workstation
prior to its implementation.
Air ionizers shall be pOSitioned so that the devices at the static-free workstations are within a 4-foot arc measured
by a vertical line from the face of the ionizer and 45 degrees on each side of this line.
General grounding requirements are to be in accordance with Table 1.
Personal
Ground
Strap
ESO Protective
Trays, etc.
!
v
Chair
with Ground
(optional)
5~:~Fpatlve
Table
Top
Ionizer
~.----......
I
CIt
I
Other
Electronic
Equipment
..
LL/L/~////////JJ~L/J/L/~//////////~
All electrical equipment Sitting on the conductive table top must be hard grounded but must be isolated from the static disspative work surface.
NOTE: Earth ground is not computer ground or RF ground or any other limited-type ground.
Figure 1. Static-Free Workstation
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Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS)
Devices and Assemblies
Table 1. General Grounding Requirements
Treated With Antistatic
Solution or Made of
Conductive Material
Handling Equipment!
Handtools
Grounded to
Common Point
Static Dissipative
Material
X
X
Metal Parts of Fixtures and
Tools/Storage Racks
X
X
Handling Trays/Tubes
X
X
Soldering Irons/Baths
Table Tops/Floor Mats
X
X
X
X Using Wrist Strap*
Personnel
* With 1 MQ ± 10% resistor
Usage of Antistatic Solution in Areas to Control the Generation of Static Charges
The use of antistatic chemicals (antistats) should be a supplemental part of an overall organized ESD program.
Any antistatic chemical application shall be considered as a means to reduce or eliminate static charge generation
on nonconductive materials in the manufacturing or storage areas.
The application of any antistatic chemical in a clean room of class 10 000 or less shall not be permitted. Accordingly, any user of antistatic solutions must consider the following precautions:
I
1.
2.
Do not apply antistatic spray or solutions in any form to energized electrical parts, assemblies, panels,
or equipment.
Do not perform antistatic chemical applications in any area when bare chips, raw parts, packages, and/or
personnel are exposed to spray mists and evaporation vapors.
The need for initial appli~ation and frequency of reapplication can be established only through routing electrostatic
voltage measurements using an electrostatic voltmeter. The following durability schedule is a reasonable expectation.
1.
2.
3.
4.
Soft surfaces (carpet, fabric seats, foam padding, etc.): each 6 months or after cleaning, by spraying.
Hard abused surfaces (floor, table tops, tools, etc.): each week (or day for heavy use) and after cleaning,
by wiping or mqpping.
Hard unabused surfaces (cabinets, walls, fixtures, etc.): each 6 months or annually and after cleaning,
by wiping or spraying.
Company-furnished and maintained clothing and smocks: after each cleaning, by spraying or adding antistatic concentrate to final rinse water when cleaned.
The use of antistatic chemicals, their application, and compliance with all appropriate specifications, precautions,
and requirements shall be the responsibility of the area supervisor where antistatic chemicals are used.
ESD Labels and Signs in Work Areas
ESD caution signs at workstations and labels on static-sensitive parts and containers shall be consistent in color,
symbols class, voltage sensitivity identification, and appropriate instructions. Signs shall be posted at all workstations
performing any handling operations with static-sensitive items. These signs shall contain the following information
or its equivalent.
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Guidelines for Handling Eleclroslatic-Discharge-Sensilive (ESDS)
Devices and Assemblies
CAUTION
STATIC CAN DAMAGE COMPONENTS
Do not handle ESO-sensitive items unless grounding wrist strap
is properly worn and grounded. Do not let clothing or plain plastic
materials contact or come in close proximity to ESO-sensitive
items.
Labels shall be affixed to all containers containing static-sensitive items at a place readily visible and proper for
the intended purpose. Additionally, labels must be consistently placed on containers and packages at a standard location to eliminate mishandling. Use only QC-accepted and approved signs and labels to identify static-sensitive products and work areas. The use of ESO signs and labels, and their information content shall be the responsibility of the
area supervisor to assure consistency and compatibility throughout the static-sensitive routing.
Relative Humidity Control
Since relative humidity has a significant impact on the generation of static electricity, when possible, the work area
should be maintained within the 40%-60% relative humidity range.
Preparation for Working at Static-Free Workstation
A workstation with a static disspative work surface connected to ground through a 1 MQ ± 10% resistor, a grounding
wrist strap with the ground wire connected to the conductive work surface, and an ionizer constitute a static-free
workstation (Figure 1). An operator is properly grounded when the wrist strap is in snug (no slack) contact with the
bare skin, usually positioned on the left wrist for a right-handed operator. The wrist strap must be worn the entire time
an operator is at a static-free workstation. The operator should first touch the grounded bench top before handling
static-sensitive items. This precaution should be observed in addition to wearing the gounding wrist strap. If possible,
the operator should avoid touching leads or contacts even though he or she is grounded.
CAUTION
Personnel shall never be attached without the presence of the
1 MQ ± 10% series resistor in the ground wire.
An operator's clothing should never make contact or come in close proximity with static sensitive items. Operators
must be especially careful to prevent any static-sensitive items (being handled) from touching their clothing. Long
sleeves must be rolled up or covered with antistatic sleeve protector banded to the bare wrist, which shall "cage" the
sleeve at least as far up as the elbow. Only antistatic finger cots may be used when handling static-sensitive items.
Any improperly prepared person, while at or near the work station, shall not touch or come in close proximity with
any static-sensitive item. It is the responsibility of the operator and the area supervisor to ensure that the static-free
work area is clear of unnecessary static hazards, including such personal items as plastic coated cups or wrappers,
plastic cosmetic bottles or boxes, combs, tissue boxes, cigarette packages, and vinyl or plastic purses. All work-related items, including information sheets, fluid containers, tools, and part carriers must be approved for use at the static-free workstation.
General Handling Procedures and Requirements
1.
All static-sensitive items must be received in an antistatic/conductive container and must not be removed
from the container except at the static-free workstation. All protective folders or envelopes holding documentation (lot travelers, etc.) shall be made of nonstatic-generating material.
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Guidelines for Handling Eleclroslalic-Discharge-Sensilive (ESDS)
Devices and Assemblies
2.
Each packing (outermost) container and package (internal or intermediate) shall have a bright yellow
warning label attached, stating the following information or equivalent:
...~ 4>~ ELECTROSTATIC
CAUTION
~
~
~}
a
SENSITIVE
DEVICES
DO NOT OPEN OR HANDLE
EXCEPT AT A
STATIC-FREE WORKSTATION
The warning label shall be legible and easily readable to normal vision at a distance of 3 feet.
Static-sensitive items are to remain in their protective containers except when actually in use at the staticfree station.
4. Before removing the items from their protective container, the operator should place the container on the
conductive grounded bench top and make sure the wrist strap fits snugly around the wrist and is properly
plugged into the ground receptacle, then touch hands to the conductive bench top.
5. 1\11 operations on the items should be performed with the items in contact with the grounded bench top
as much as possible. Do not allow conductive magazine to touch hard-grounded test gear on bench top.
6. Ordinary plastic solder-suckers and other plastic assembly aids shall not be used.
7. In cases where it is impossible or impractical to ground the operator with a wrist strap, a conductive shoe
strap may be used along with conductive tile/mats.
8. When the operator moves from any other place to the static-free station, the start-up procedure shall be
the same as in Preparation for Working at Static-Free Workstation.
9. The ionizer shall be in operation prior to presenting any static-sensitive items to the static-free station,
and shall be in operation during the entire time period the items are at the station.
10. "Plastic snow" polystyrene foam, "peanuts," or other high-dielectric materials shall never come in contact
with or be used around electrostatic sensitive items, unless they have been treated with an antistat (as
evidenced by pink color and generation of less than ± 100 volts).
11. Static-sensitive items shall not be transported or stored in trays, tote boxes, vials, or similar containers
made of untreated plastic material unless items are protectively packaged in conductive material.
3.
Packaging Requirements
Packaging of static-sensitive items is to be in accordance with Device Sensitivity, item 1. The use of tape and plain
plastic bags is prohibited. All outer and inner containers are to be marked as outlined in General Handling Procedures
and Requirements, item 2. Conductive magazines/boxes may be used in lieu of conductive bags.
Specific Handling Procedures for Static-Sensitive Items
Stockroom Operations
1.
2.
3.
Containers of static-sensitive items are not to be accepted into stock unless adequately identified as containing static-sensitive items.
Items may be removed from the protective container (magazine/bag, etc.) for the purpose of subdividing
for order issue only by a properly grounded operator at an approved static-free station as defined in Facilities for and Preparation for Working at Static-Free Workstation.
All subdivided lots must be carefully repackaged in protective containers (magazine/bag, etc.) prior to
removal from the static-free work-station and labeled to indicate that the package(s) contain static-sensitive items. If it is suspected that a static-sensitive item is not adequately protected, do not transfer it to
TEXAS
-1!1
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
13-5
Guidelines for Handling Eleclroslatic-Discharge-Sensilive (ESDS)
Devices and Assemblies
another container, return it to the originator for disposition unless the originator is a customer. In that case,
the
engineer should contact the customer and negotiate an appropriate disposition.
It is the responsibility of the stockroom supervisor to ensure that all personnel assigned to this operation
are familiar with handling procedures as outlined in this specification. A copy of this specification is to be
posted in the vicinity so that it is accessible to the operators. Stock handlers and all others who might have
occasion to move stock are to be instructed to avoid direct contact with unprotected static-sensitive items.
ac
4.
Module and Subassembly Operations
1.
2.
3.
4.
Static-sensitive items are not to be received from a stockroom, kitting, or machine insertion area unless
received in approved static-protective packaging, and properly labeled to indicate that its contents are
static-sensitive.
All single station, progressive line manual assembly operators, and visual inspectors prior to wave soldering operations are to be properly grounded with a grounding wrist strap when handling static-sensitive
items.
.
Progressive lines used as single stations where operators will be working on a mix of boards, both staticsensitive and nonstatic-sensitive, will require that all operators working on the line be properly grounded.
This is necessary to accommodate the sliding of static-sensitive boards along the assembly bench or
across positions not engaged in the assembly of this type board.
It is the responsibility of the area supervisor to ensure that all personnel handling static-sensitive items
are familiar with this procedure and fully aware of the damage or degradation of these units in the event
of noncompliance. A periodic inspection should be made using an electrostatic voltmeter to assure that
the static-free stations are in the proper working order and to ensure that operators are wearing grounding
wrist straps properly (snugly in contact with bare skin).
Soldering and Lead-Forming Operations
1.
All soldering machines, conveyors, cleaning machines, and equipment shall be electrically grounded to
ensure that they are at the same ground potential as the grounded operators working on their stations.
No machine surfaces exposed to static-sensitive items are to be above ground potential.
2.
All processing equipment shall be grounded, including all loading and unloading stations, that is, the stations before and after each piece of processing equipment.
All nonmetalliC, static-generating components in the handling systems shall be treated to ensure protection from static.
All stations shall be identified by posting signs as outlined in ESD Labels and Signs in Work Areas.
Operators are to be properly grounded with a grounding wrist strap during any handling, loading, unloading, inspection, rework, or proximity to static-sensitive items.'
Unloading operators working at a grounded station shall place static-sensitive items into approved staticprotective bags or containers.
All manual soldering, repair, and touch-up work stations on the solder line are to be static protected. Operators are to wear grounding wrist straps when working on static-senstive items. Only ground~p-tip soldering/desoldering irons are allowed when working on static-sensitive items.
It is the responsibility of the area supervisor to ensure that all personnel handling static-sensitive items
are familiar with this procedure and fully aware of the damage or degradation of these units in the event
of noncompliance. A periodiC inspection should be made using an electrostatic voltmeter to assure that
the static-free stations are in proper working order and to ensure that the operators are wearing grounding
wrist straps properly (comfortably snug in contact with bare skin).
3.
4.
5.
6.
7.
8.
Electrical Testing Operations
1.
2.
All electrical test stations shall be static protected. Operators shall be properly ground~d when working
on these items.
Reused antistatic magazines must be monitored for maintenance of antistatic characteristics.
TEXAS ~
INSTRUMENTS
13·6
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 7700/
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS)
Devices and Assemblies
3.
Devices should be in an antistatic/conductive environment except at the moment when actually under
test.
.
4.
Devices should not be inserted into or removed from circuits or tester with the power on or with
applied to inputs to prevent transient voltages from causing permanent damage.
5.
All unused input leads should be biased if possible.
6.
Device or module repairs must be performed at static-free stations with the operator attached to a grounding wrist strap. Grounded-tip soldering irons shall be used when working on static-sensitive items.
7.
Static-sensitive items shall be handled through all electrical inspections in static protective containers.
Removal of the items from the protective containers shall be done at a static-free workstation as discussed in Preparation for Working at a Static-Free Workstation. The units must be returned to the containers before leaving the station.
8.
All such items shall be shipped with an ESD warning label affixed as listed.
9.
It is the responsibility of the area supervisor to ensure that all personnel handling static-sensitive items
are familiar with this procedure and fully aware of the damage or possible degradation of these units in
the event of noncompliance. A periodic inspection should be made using an electrostatic voltmeter to assure that the static-free stations are in proper working order and to ensure that operators are wearing
grourding straps properly (snugly in contact with bare skin).
~ignals
Packing Operations
1.
Static-sensitive items are not to be accepted into the packing area unless they are contained in a staticprotected bag or conductive container.
2.
A static-sensitive item delivered to the packer within an approved container or bag and found to be in order
regarding identification shall be packed in the standard shipping carton or other regular packaging material. Containers are to be ~abeled in accordance with General Handling Procedures and Requirements,
item 2.
3.
Any void-fillers shall be made of an approved antistatic material.
Burn-In operations
1.
2.
Burn-in board loading and unloading of static-sensitive items shall be done at a static-free station.
Shorting clips/shorted connectors shall be installed on the board plug-in tab prior to loading any units into
the board sockets. The Clip/connectors shall be taken off just prior to plugging the board into the oven
connector. The Clip/connector shall be installed immediately upon removal of the board from the oven
connector. Installation and removal of the Clip/connector shall be done by a properly grounded operator.
3.
4.
All automatic or semi-automatic loading and unloading equipment shall be properly electrically grounded.
It is the responsibility of the area supervisor to ensure that all personnel handling static-senstive items
are familiar with this procedure and fully aware of the damage or possible degradation of these units in
the event of noncompliance. A periodic inspection should be made using an electrostatic voltmeter to assure that the static-free stations are in proper working order and to ensure that operators are wearing
grounding straps properly (snugly in contact with bare skin).
Customer-Returned-Item Handling Procedure
Receipt of ESD sensitive-labeled items is to be done at a static-free workstation and handled in accordance with
applicable sections within this guideline.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
13-7
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS)
Devices and Assemblies
Quality Control Provision
Sampling
Each manufacturing, stockroom, and testing operation handling ESD sensitive devices will be audited a minimum
of once each quarter for compliance with all terms of this specification by the responsible process control or RA organization. Ground continuity and the presence of uncontrolled static voltages are considered critical and shall be
checked more frequently as specified below.
a
Ground Continuity (minimum of once a week)
Ground connections (grounding wrist strap, ground wires on cords, etc.) shall be checked for electrical continuity.
The presence of a 1 MQ ± 10% resistor in the ground connections between both the operator wrist straps to the work
surface and the work surface to ground connector must be verified.
Grounded Conditions (minimum of once a week)
A visual inspection shall be made to determine full compliance with this specification at static·free workstations
during handling of static-sensitive items, including operator being grounded as required, static-sensitive items not being handled in unprotected or unauthorized areas, and no static-generating materials at the grounded workstation.
Sleeve Protectors (minimum of once a week)
A visual check shall be made to determine that each operator wearing loose-fitting or long-sleeved clothing either
has sleeves properly rolled or covered with sleeve protectors properly grounded to the bare skin at the wrist.
Static Voltage Levels (minimum of once a week)
In addition to the visual inspections, a sample inspection using an electrostatic voltmeter will be used to check for
uncontrolled electstatic voltages at or near electrostatic-controlled work stations.
Conductive Floor Tiles (minimum of once a month)
Conductive floors must have a resistance of not less than 100 kQ from any point on the tile to earth ground. Also,
resistance from any point·to-point on the tile floor three (3) feet apart shall be not less than1 00 kQ. The test methods
to be used are ASTM-F-150-72 and NFPA 99.
Records
Written records must be kept of all these
ac audits.
Training
Training is applicable for all areas where individuals come in contact with ESD-sensitive devices. It is the responsibility of each area supervisor to make sure that his/her people receive ESD training initially and every 12 months thereafter to maintain proficiency. Training should include static fundamentals, a review of applicable parts of this specification, and actual applications in the work area.
TEXAS •
INSTRUMENTS
13-8
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
Mechanical Data
,
"
"1,4~:
~.
y
o J _..
Mechanical Data
Mechanical Data
MOS Memory Products - Commercial
Plastic Dual-In-Line Package (N Suffix)t
r®
~------
Either
Or 80th
..
------,=~~I
B Max
==r:-l-=
""~---+l~
Index Marks
M~X
~"""_U-----------------I ~
AMax
1'----''----''----''----'
~
CMax
r~050
9~~355
1- s,:,:~ g -r~~
~
jLj l
J
(0.014)
0,203 (0.008)
;-JI.-
0,533 (0.021)
0,381 (0.015)
.
D Mrn
Pin Spacing 2,54 (0.100) T.P.
1,78 (0.070)
Nom
I
0,838 (0.033) Nom
~
16
18
20
28
32
A (Max)
8,26
(0.325)
8,26
(0.325)
8,26
(0.325)
15,88
(0.625)
15,88
(0.625)
8 (Max)
22,10
(0.870)
22,86
(0.899)
25,40
(1.000)
37,21
(1.465)
41,94
(1.651)
C (Max)
6,86
(0.270)
6,86
(0.270)
6,86
(0.270)
13,97
(0.550)
13,97
(0.550)
D(Min)
3,18
(0.125)
3,00
(0.118)
3,00
(0.118)
2,92
(0.115)
3,18
(0.125)
DIM
ALL LINEAR DiMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t
Applicable MOS Memory Devices:
16-PIN
18-PIN
20-PIN
28-PIN
32-PIN
TMS4C1050
TMS4C1060
TMS4C1024
TMS4C1025
TMS4C1027
TMS4C1070
TMS44C256
TMS27PC128
TMS27PC256
TMS27PC512
TMS29F256
TMS29F258
TMS29F259
TMS27PC510
TMS29F512
TMS29F010
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
14-1
Mechanical Data
MOS Memory Products - Commercial
Ceramic Dual-In-Line Package (J Suffix)t
14------ B ------to\
N
o
C
£
0,457Min
(0.018)
IE
4,45 (0.175)
3,56 (0.140)
E~~~:i:~~~~;;;:~~~'1,8Min
(0.125)
£
~
L
A
Lens Protrusion
0,254 (0.010) Max
0,305 (0.012)
0,203 (0.008)
-r-
5,08 (0.200)
3,81 (0.150)
18,29 (0.720)
16,36 (0.644)
j
0,711 (0.028)
Min Ref
2,79 (0.110)
2,29 (0.090)
~
1,57 (0.062)
1,14 (0.045)
24
DIM
32
28
40
A (Max)
15,85 (0.624)
15,85 (0.624)
15,85 (0.624)
15,85 (0.624)
B (Max)
32,13 (1.265)
37,21 (1.465)
42,37 (1.668)
52,53 (2.068)
C(Max)
14,25 (0.561)
14,25 (0.561fl:
15,19 (0.598)§
14,25 (0.561)
14,25 (0.561)
*This dimension pertains to TMS27C128, TMS27C256, TMS27C512, and TMS87C257 only.
§ This dimension pertains to TMS29F256, TMS29F258, and TMS29F259 only.
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t
Applicable MOS Memory Devices:
28-PIN
TMS27C128
TMS27C256
TMS27C512
TMS29F256
TMS29F258
TMS29F259'
TMS87C257
32-PIN
40-PIN
TMS27C510
TMS27C210A
TMS27C010A
TMS27C240
TMS27C0210A
TMS27C040
TMS29F512
TMS29F010
TEXAS •
INSTRUMENTS
14-2
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Mechanical Data
MOS Memory Products - Commercial
20/26-Pin Plastic Small-Outline J-Lead Package (SOJ) (OJ suffix)t
17,22 (0.678):1:
17,07 (0.672)
2625242322
Index Notch
1817161514
8,64 (0.340)
8,38 (0.330)
7,65 (0.301):1:
7,49 (0.295)
2,85 (0.112)
2,62 (0.103)
0,20 (0.008) Nom
Excluding Finish
1,14 (0.045)
0,89 (0.035)
- - Seating
3,76 (0.148)
3,25 (0.128)
1,02 (0.040)
0,76 (0.030)
0,64 (0.025) Min
Plane~
0,51 (0.020)
0,41 (0.016)
jl
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t Applicable MOS Memory Devices:
20/26-PIN§
TMS4C1024
TMS4C1025
TMS4C1027
TMS44C256
TMS44100
TMS44101
TMS44400
TMS44410
TMS4C1050
TMS4C1060
TMS4C1070
:j: Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0,254 mm (0.010) from the edge of the package bottom
plastic.
§ The lead contact points are planar within 0,101 (0.004).
TEXAS ~
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
14-3
Mechanical Data
MOS Memory Products - Commercial
24/26-Pin Plastic Small-Outline J-Lead Package (SOJ) (OJ suffix)t
17,22 (0.678)*
[ - - - 17,07 (0.672)
262524232221
191817161514
~ Index Notch
2,85 (0.112)
2,62 (0.103)
0,20 (0.008) Nom
Excluding Finish
1,14 (0.045)
0,89 (0.035)
- - Seating
1,02 (0.040)
0,76 (0.030)
Plane~
0,51 (0.020)
0,41 (0.016)
3,76 (0.148)
3,25 (0.128)
jl
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t Applicable MOS Memory Devices:
24/26-PIN
TMS44C260
TMS44460
TMS48C128
TMS48C138
* Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0,254 mm (0.010) from the edge of the package bottom
plastic.
TEXAS
.J!1
INSTRUMENTS
14-4
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Mechanical Data
MOS Memory Products - Commercial
20/26-Pin Plastic Small-Outline J-Lead Package (SOJ) (OM suffix)t
17,22 (0.678)*
17,07 (0.672)
9,91 (0.390)
9,65 (0.380)
9,02 (0.355)*
8,76 (0.345)
1 234 5
2,77 (0.109)
2,62 (0.103)
0,20 (0.008) Nom
Excluding Finish
0,64 (0.025) Min
-
Seating
1,02 (0.040)
0,76 (0.030)
1,27 (0.050)
0,81 (0.032)
'IO~
Plan~
~
jl
I I
-.I
~ 1,27 (0.050) Typ
0,51 (0.020)
0,41 (0.016)
3,76 (0.148)
3,25 (0.128)
1,14 (0.045)
0,89 (0.035)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t
Applicable MOS Memory Devices:
20/26·PIN
TMS44100
TMS44101
TMS44400
TMS44410
~ Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0,125 (0.005).
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
14·5
Mechanical Data
MOS Memory Products - Commercial
,
.
.
,
.
,
.
.
,
.
,
.
.
,
n
20/26-Pin Plastic Thin Smail-Outline J-Lead Package (TSOJ) (ON Suffix)t
22 23 24 25 26
8,50 (0.335)
8,26 (0.325)
~
i\ +-I
18 17 16 15 14
Index Notch
12345
7,47 (0.294) ____
9
........................................
10 11 12 13
........................................
1
--',0,31 (0.012) x 45°
0,559 (0.022)
l
J
~
14------16.51 (0.650)
D,'5(D.D06)
--'~d--"---====-~b~
1,83 I072)
1,73 (0.068)
L
7,57 (D.298)
J
Eiiriiiiilirl------..,(ggjJjijJ
D,84 (0.033)
0,51 (0.020)
0,41 (0.016)
JL
1,27 (0.050)
Typ
0,81 (0.032)
__
0,66 (0.026) - . :'"
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t
Applicable MOS Memory Devices:
20/26-PIN
TMS4C1024
TMS4C1025
TMS4C1027
TMS44C256
TEXAS ."
INSlRUMENlS
14-6
~
POST OFFICE BOX 1443
•
HOUSTON. TEXAS nOOl
JL
Mechanical Data
MOS Memory Products - Commercial
24/28-Pln Plastic Sma"-Outline J-Iead J-Iead Package (SOJ) (OZ suffix)t
18,54 (0.730)
18,28 (0.720)
28 27 26 25 24 23
20 19 18 17 16 15
o
4- Index
Mark
11,30 (0.445)
11 ,05 (0.435)
-.II.-
0,46 (0.018)
TyP~ ~
1,27 (0.050) Typ
0,813 (0.320)
0,661 (0.260)
0,64
(0.025)
Min
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t
Applicable MOS Memory Devices:
24/28-PIN
TMS416100
TMS416400
TEXAS ~
INSlRUMENlS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
14-7
Mechanical Data
MOS Memory Products - Commercial
28-Pin Plastic Small-Outline J-Lead Package (SOJ) (OZ Suffix)t
28 ••- - - - - - - - - - - - - - - - - - - - -
~'nd.xMa'k
11,30 (0.445)
11,05 (0.435)
18,54 (0.730)
18,28 (0.720)
10,29 (0.405)
10,03 (0.395)
2,69 (0.106)
T
3,76 (0.148)
3,25 (0.128)
::~ ~'76
r~
s••
Plane
0,64 (0.025)
Min
(0.148)
(0 128)
3,
25 .
J
lO,46 (0.018) Typ
1,27 (0.050) Typ
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t
Applicable MOS Memory Devices:
28-PIN
TMS44C250
TMS44C251
TEXAS -111
INSlRUMENTS
,
.'~' ",
14-8
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
jL
Mechanical Data
MOS Memory Products - Commercial
40-Pin Plastic Small-Outline J-Lead Package (SOJ) (DZ Suffix)t
40
.4--------------
o
11,30 (0.445)
11,05 (0.435)
1 + - - - - - - 26,16 (1.030) Max - - - - - + 1
10,29 (0.405)
10,03 (0.395)
2,69 (0.106)
Ref
~
Jl
0,635 (0.025)
Min
2,083 (0.082)
Min
0,46 (0.018) Typ
jL
1,27 (0.050) Typ
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t
Applicable MOS Memory Devices:
40-PIN
TMS48C121
TEXAS 'If
INSlRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
14-9
Mechanical Data
MOS Memory Products - Commercial
32-Pin Plastic Thin Small-Outline J-Lead Package (TSOP) (DO Suffix)t
This package is under development.
1,200 (0.047)
Max
0,100 (0.004)
18,44 (0.726)
18,38 (0.724)
t
0,600 (0.024)
0,400 (0.002)
0,300 (0.012)
0,100 (0.004)
0,600 (0.024)
0,400 (0.002)
j
r--
l t '
0,900 (0.035)
0,700 (0.028)
I:
)~
J(
~:~~~ ~~:~~:~
~I
19,60 (0.772)
19,40 (0.764)
20,10 (0.791)
19,90 (0.784)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t Applicable MOS Memory Devices:
32-PIN*
TMS29F259
TMS29F512
TMS29F010
TEXAS ~
INSTRUMENTS
14-10
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Mechanical Data
MOS Memory Products - Commercial
Zig-Zag In-Line Plastic Package (ZIP) (SO suffix)t
I4-----B~l
3,00 (0.118)
2,60 (0.1 02) -!e-~
Index
I
1
j
l
0,60 (0.024)
0,40 (0.016)
1,30 (0.051) Nom
JL
1,47 (0,058)
1,07 (0.042)
0,304 (0.012)
Lead Thickness: 0
(
)
,204 0.008
Pin N
.~
DIM
A:j:
20
8,69 (0.342) Max
8,64 (0.340) Max
B:j:
26,42 (1.040) Max
36,10 (1.420) Max
C (Max)
10,16 (0.400) Max
10,16 (0.400)
D
2,79 (0.110)
2,29 (0.090)
2,79 (0.110)
2,29 (0.090)
E
3,30 (0.130)
3,00 (0.118)
3,30 (0.130)
2,00 (0.118)
28
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t Applicable MOS Memory Devices:
20-PIN
28-PIN
TMS4C1024
TMS4C1025
TMS4C1027
TMS44C256
TMS44100
TMS44101
TMS44400
TMS44410
TMS4C1050
TMS4C1060
TMS4C1070
TMS44C250
TMS44C251
:j: Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0,125 (0.005).
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 •
HOUSTON, TEXAS 77001
14-11
Mechanical Data
MOS Memory Products - Commercial
18-Pin Plastic Leaded Chip Carrier (PLCC) (FM Suffix)t
7,47 (0.294)
7,26 (0.286)
J
0,737 (0.029)
0,660 (0.026)
Seating
Plane
12,55 (0.494)
12,34 (0.486)
3,53 (0.139)
3,38 (0.133)
L~
3,28 (0.129)
3,12 (0.123)
Index Corner
6,68 (0.263)
6,53 (0.257) -+'__---l~
1,24 (0.049)
1,09 (0.043)
~J4-11--
1,27 (0.050)
Typ
£
0,53 (0.021)
0,43 (0.017)
J
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLLY IN INCHES
t Applicable MOS Memory Devices:
18·PIN
TMS29F816
TEXAS
-1!1
INSlRUMENTS
14-12
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
0,20 (0.008)
Nom
Mechanical Data
MOS Memory Products - Commercial
32-Pin Plastic Leaded Chip Carrier Package (PLCC) (FM suffix)t
~
12,57 (0.495)
12,32 (0.485)
11,51 (0.453)
13
12
11
10
9
15,11 (0.595)
14,86 (0.585)
14,05 (0.553)
t------1::~--- ~ 13'8l~~
......
Seating Plane
i t - - - - . t - - 3,56 (0.140)
3,35 (0.132)
1,24 (0.049)
1,09 (0.043)
x-----.-"
0,20 (0.008)
Nom
£
0,76 (0.030)
Typ
13,34 (0.525)
13,08 (0.515)
0,51 (0.020)
0,38 (0.015)
1,27 (0.050)
Typ
1--------£
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHICALLY IN INCHES
t Applicable MOS Memory Devices:
32-PIN
TMS27PC128 TMS27PC010A
TMS27PC256 TMS27PC040
TMS27PC510
TMS29F256
TMS27PC512
TMS29F258
TMS29F259
TMS29F512
TMS29F010
TEXAS
l{J
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
14-13
Mechanical Data
MOS Memory Products - Commercial
44-Pin Plastic Leaded Chip Carrier Package (PLCC) (FN suffix)t
4,50 (0.177)
4,24 (0.167)
2,79 (0.110)
2,41 (0.095)
r-
1,22 (0.048)
1,07 (0.042)
x 450
1,35 (0.053) x 450
1,19 (0.047)
~
0,939 (0.037) R
0,686 (0.027)
~\l
o
17,65 (0.695)
17,40 (0.685)
16,00 (0.630)
15,49 (0.610)
1,27 (0.050) T.P.
(see Note B)
16,66 (0.656)
16,51 (0.650)
(see Note A)
0,25 (0.010) R Max
3 Places
Seating Plane
(see Note C)
~______ ~1~7,~65~(~0~.6~95~)________~
17,40 (0.685)
Lead Detail
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHICALLY IN INCHES
NOTES: A. Centerline of center pin each side is within 0,10 (0.004) of package centerline as determined by this dimension.
B. Location of each pin is within 0,127 (0.005) of true position with respect to center of pin on each side.
C. The lead contact points are planar within 0,101 (0.004).
t Applicable MaS Memory Devices:
44-PIN
TMS27PC210A
TMS27PC240
TEXAS •
INSTRUMENTS
14-14
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Mechanical Data
MOS Memory Products - Commercial
30-Pin Single-Sided Single-In-Line Package (U Suffix)t
..,
89,03 (3.505)
88,77 (3.495)
141
5,33 (0.210) Max
3,175 (0.125)
Typ
Pin Spacing 2,54 (0.100) T.P.
(see Note A)
-:':8~070)TYP-.J l.-
1,37 (0.054)
1,17 (0.046)
-J I.-
3,38 (0.133) Typ
10,16 (0.400) Typ
16,64 (0.655) Max
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
Note A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
t
Applicable MOS Memory Devices:
30-PIN
TM256GU9C
TM124GU8A
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
14-15
Mechanical Data
MOS Memory Products - Commercial
30-Pin Single-Sided Single-ln-L1ne Package (AD Suffix)t
5,33 (0.210) Max
89,15 (3.510)
88,65 (3.490)
3,18 (0.125)
Typ
~I
r-~======~====~~====~--'----~f
Pin Spacing 2,54 (0.100) T.P.
(see Note A)
JL
-J I.-
10,16 (0.400) Typ
1,78 (0.070) Typ
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
Note A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
t
Applicable MOS Memory Devices:
30-PIN
TM024EAD9
TM124EAD98
TM124EAD9C
TEXAS •
INSTRUMENTS
14-16
l
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
1,37 (0.054)
1,17 (0.046)
Jl
Mechanical Data
MOS Memory Products - Commercial
30-Pin Single-Sided Single-In-Line Package (BD Suffix)t
89,15 (3.510)
14
3,18 (0.125)
Nom
·1
88,65 (3.490)
----rt
DDDDD
DDDD~
1,78 (0.070) Typ
-J I.-
l
10,16 (0.400) Typ
3,38 (0.133) Typ
1r
5,33
(0.210)
Max
~-J
l 1 ,37 (0.054)
1,19 (0.047)
2,54 (0.100) T.P.
Pin Spacing
(see Note A)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A:
t
Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
Applicable MaS Memory Devices:
30-PIN
TM4100GBDB
TM4100EBD9
TEXAS ~
INSTRUMENTS
POST OFFICE SOX 1443
•
HOUSTON, TEXAS 77001
14-17
Mechanical Data
MOS Memory Products - Commercial
72-Pin Single-Sided Single-In-Line Package (BK Suffix)t
.1
108,13 (4.257)
107,77 (4.243)
DDDDDDDD
1,37 (0.054)
1,19 (0.047)
3,18 (0.125)
Nom
++f----r
~~~~~~~~~~~~~~
1,27 (0.050) Typ
3,18 (0.125)
3,05 (0.120)
10,29 (0.405)
10,03 (0.395)
5,28 (0.208) Max
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t Applicable MOS Memory Devices:
72-PIN
TM256BBK32
TM256KBK36B
TM256KBK36C
TM124BBK32
TM124MBK36B
TEXAS -If
INSlRUMENTS
14-18
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
1It+"
~
Mechanical Data
MOS Memory Products - Commercial
72-Pin Double-Sided Single-In-line Package (BK Suffix)
I14~t-----------
108,13 (4.257)
107,77(4.243)
1,37 (0.054)
1,19 (0.047)
DDDDDDDD
3,18(0.125)
Nom
1It+~
(++t-----r
~~~~~~~~~~~--~~~
1,27 (0.050) Typ
10,29 (0.405)
10,03 (0.395)
9,40 (0.370) Max
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE A: Parts location may vary.
t Applicable MOS Memory Devices:
72-PIN
TM512CBK32
TM512LBK36B
TM512LBK36C
TM124MBK36A
TEXAS -1!1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
14-19
Mechanical Data
MOS Memory Products - Commercial
TEXI\S
l.!1
INSlRUMENTS
14-20
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Mechanical Data
MOS Memory Products - Military
MILITARY PACKAGES
The packages offered by the Military Products Division of Texas Instruments Semiconductor Group are designed to
provide the most efficient and cost-effective method of meeting military system requirements. Products are offered
in hermetic ceramic dual-in-line, ceramic flatpack, leadless ceramic chip carrier, and leaded ceramic chip carrier
packages. All packages conform to the mechanical outlines contained in Appendix C of MIL-M-3851 0 except for
package types that are not included in that specification. In the event of a conflict between dimensions contained in
MIL-M-38510 Appendix C and other TI published mechanical outlines, MIL-M-38510 will take precedence.
Physical dimensions of the packages not contained in MIL-M-3851 0 Appendix C are contained in this document.
Ceramic Packages Available
Package DeSignator
HM, HL
Description
Three-Layer Rectangle LCC - JEDEC Pinouts
J
Glass-Sealed CDIP
JD
Side-Brazed CDIP
HJ
Ceramic Small-Outline J-Iead
HK
Side-Brazed Ceramic Flatpack
HR
Ceramic Flatpack
The TI published mechanical outlines for a given package type may vary slightly from product to product. To identify
the detailed outline drawing for a particular product, refer to the specific data sheet for that product.
Mechanical Outlines
Size/Desig nator
Package Type
Applicable Specification
Typical Package
Weight In Grams
18-pin JD
Side-Brazed Dual-In-Line
MIL-M-38S10, App. C, 0-6, Config 3
1.8
20-pin JD
Side-Brazed Dual-In-Line
MIL-M-38510, App. C, 0-8, Config 3
2.0
1.2
20-pin HK
Side-Brazed Flatpack
TI Drawing
20-pad HL
Leadless Ceramic Chip Carrier
TI Drawing
1.1
20-pin HJ
Ceramic Small-Outline J-Iead
TI Drawing
1.1
20-pad HM
Leadless Ceramic Chip Carrier
TI Drawing
1.3
20-pin HR
Ceramic Flatpack
TI Drawing
1.6
5.3
28-pin JD
Side-Brazed Dual-In-Line
MIL-M-38510, App. C, 0-10, Config 3
28-pin HJ
Ceramic Small-Outline J-Lead
TI Drawing
1.5
28-pin J
Ceramic Dual-In-Line
MIL-M-38510, App. C, 0-10, Config 1
7.9
32-pin J
Ceramic Dual-In-Line
TI Drawing
8.9
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
14-21
Mechanical Data
MOS Memory Products - Military
18-Pin Ceramic Sidebrazed Dual-In-Line Package (JD suffix)
'23.114(O.910I MB.
~
10,414
(0.410)
Max
Index Mark
Pin 1
~ 10,287 ± O,38.J..i
(0.405 ± 0.015)· I
I
0,279 ± O,07~~ ~
(0.011 ± 0.003)
1,778 (0.070) Max
--y-----l--
Seating Plane
0,457 ± 0,076
(0.018 ± 0.003)
3,175 (0.125) Min
2,540 (0.100)
I~
1
,
20,320 ± 0,254 _ _ _...1
(0.800 ± 0.010)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _,::~_ _ .:;;;:,·;;:;o:m:.::J"l"'"=''''''''-;Z;;:;IT~:;;oJ'1l:;:O;;··~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
T~}(ftB ~
INSTRUMENTS
14-22
POST OFFICE BOX 1443
e
HOUSTON, TEXAS 77001
Mechanical Data
MOS Memory Products - Military
20-Pin Ceramic Sidebrazed Dual-In-Llne Package (JD Suffix)
25,908 (1.020) Mox
r
I
I
10,414 (0.410)
Max
~
3,556 (0.140)
Max
(OOO-:;'~~o%~rl--- j
=J'
I
+- 2,540 (0.100)
0,381
(0.015)
Min
10,287 ±0,381
(0.405 ±0.015)
JL
0,279 ±0,076
(0.011 ±0.003)
22,860 ±0,254
(0.900 ±0.010)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
14-23
Mechanical Data
MOS Memory Products - Military
20-Pln Ceramic Flatpack (HK Suffix)
...
l..o
.....
983
, (0387)
9,47 (0.373)
~
Pln1~
9,68 (0.381)
9,47 (0.373)
~
~
I
1 ,27 (0.50) Typ
I
L
,-
17,27 (0.680)
16,77 (0.660)
~
0,533 (0.021)
0,381 (0.015)
t
L
1
~
~
2,77 (0.109)
2,41 (0.095)
0,25 (0.01 O)~
0,10 (0.004)
I
~
I
i
,-==~i~==Ei==~~~
0,89 (0.035)
0,64 (0.025)
=:1 L
2,41 (0.095)
1,91 (0.075)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS -I!I
INSTRUMENTS
14-24
POST OFFICE BOX 1443
•
HOU'STON, TEXAS 77001
Mechanical Data
MOS Memory Pro~ucts - Military
20-Pin Small-Outline Leadless Ceramic Chip (HL Suffix)
17'39(0'685)~
16,89 (0.665)
r--------------9,07 (0.357)
8,71 (0.343)
Index
(1 of 2 Places)
r
0,89 (0.035) Ref
L __-1m~~~~--~~~~~---.Y..
2,03 (0.080) Max
~
1,40 (0.055)
.1,14 (0.045)
2,54 (0.100)
2,03 (0.080)
0,71 (0.028)
0,56 (0.022)
J.:I------~"T"'"r'r_T"T""T"T'".,..,.._r---__,_.,..,.._T"T""1'.,..ar.~
0,20 (0.008) Radius
Typ
1,27 (0.050)
Typ
1,22 (0.048)
0,71 (0.028)
15,49 (0.610)
14,99 (0.590)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS
.J!I
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
14-25
Mechanical Data
MOS Memory Products - Military
20/26-Pin Leaded Ceramic Chip Carrier (HJ Suffix)
r
E
17,39 (0.685)
17,12 (0.675)
15,49 (0.610)
14'99(0.590)~
[
1,22 (0.048)
0,71 (0.028)
TYP 4 PLACES
8,64 (0.340)
8,13 (0.320)
1
l
2,54 (0.100)
[
0,30 (0.012)
2,03 (0.080)
~ 015 (0.006)
1I . '
=====r=~~==~
jl
1,27 (0.050) Ref
1,14 (0.045)
0,89 (0.035)
££
..J \.
0,584
(o:t
0,406 (0.016)
2,29(0.090)
1,78 (0.070)
.
-j
j~CT K
7,75 (0.305)
0,89 (0.035)
6,86 (0.270)
0,64 (0.025)
1,40 (0.055)
1,20 (0.045)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS ~
INSlRUMENTS
14·26
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
3,18 (0.125)
2,67 (0.105)
R
Mechanical Data
MOS Memory Products - Military
20-Pin Leadless Ceramic Chip Carrier (HM Suffix)
111 - - - - - _18-'-,0_3_4-'-(0_.7_1---'0)'--_ _ _~~1
17,526 (0.690)
,.1
10,338 (0.407)
9,982 (0.393)
Index
(1 of 2 Places)
p~:::::=::::::::=::::::::=::::::::=:::=:;:.)U
3,175 (0.125)
2,667 (0.105)
El
0 0
0
rg II-=t
2,337 (0.092)
1,727 (0.068)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
14-27
Mechanical Data
MOS Memory Products - Military
20-Pin Ceramic Flatpack (HR suffix)
9,017 ± 0,381
(0.355 ± 0.015)
Typical
ihr-~~4~~6 ~~;~-'I
±±
I
1,27 ± (0.050) TyplcaJ
l
i
Pin 1
>..
U
0,457
(0.018
±
±
r--
~
r::
]
~
]J
0,076 =====r::~I0.003)==========::1
[
L
I
-------Z-j
17,780 ± 0,254
(0.700 ± 0.010)
]
~
==========:::1
[
L-..--~l _ _T-+-L--'
I
2,972 ± 0,407
(0.117 ± 0.016)
0,762 ± 0,127
(0.030 ± 0.005)
Measured at Ceramic
2,286 ± 0,254
(0.090 ± 0.Q1 0)
t
0,179
(0.007
±
±
t
0,076
0.003)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS •
INSTRUMENTS
14-28
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
Mechanical Data
MOS Memory Products - Military
28-Pin Ceramic Sidebrazed Dual-In-Line Package (JD Suffix)
r
28
~
IndexM.~j;;
1
4,445Max
(0.175)
36,8 (1.450) Max
15
-I
I:: :::: I: :15(~;~~)
,
14
10,688 (0.420)
~
9,652 (0.380)
---.i
3,18~~~125)
J{
=~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~l==r----
~~
0,530 (0.021)
0,380 (0.015)
2,540 (0.100) Nom.
Pin Spacing
(See Note A)
R
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