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~· XILINX

The Programmable Gate Array
:DataBook

1991

RECEiVED APR t. 5 1991

The Programmable Gate Array
Data Book

2100 Logic Drive
San Jose, California 95124
Telephone: (408) 559-7778

© Copyright 1991 by Xilinx, Inc. All Rights Reserved

Patents Pending

Contributors
Peter Alfke
Nick Camilleri
Jim Chumbley
Atsuko D'Amour
Rick Dudley
Abu Eghan
Chuck Erickson
Lee Farrell
Brad Fawcett
Chuck Fox

Dave Galli
Jim Hsieh
Clay Johnson
Steve Knapp
Dave Lautzenheiser
Mark Markham
Farid Mazouni
Bob McGrath
Bill O'Neill
George Nelson

Wes Patterson
Richard Ravel
Ed Resler
Randy Saldinger
Steve Schreifels
Robert Stransky
Mustafa Vezioroglu
Thomas Waugh
Perry Wu

Xilinx, Logic Cell, LCA, XACT, and XACTOR, are trademarks of Xilinx,
Inc. The Programmable Gate Array Company is a Service Mark of
Xilinx,lnc.
IBM is a registered trademark and PC/AT, PC/XT, PS/2, and Micro
Channel are trademarks of International Business Machines
Corporation. ABEL is a trademark and Data 110 is a registered trademark
of Data 110 Corporation. FutureNet is a registered trademark and DASH
is a trademark of FutureNet Corporation, a Data 110 Company. SimuCad
and Silos are registered trademarks and P-Silos and PIC-Silos are
trademarks of SimuCad Corporation. Microsoft is a registered trademark
and MS-DOS is a trademark of Microsoft Corporation. Logitech is a
registered trademark of LOGITECH Inc. Lotus is a registered trademark
of Lotus Development Corporation. AboveBoard and AboveBoardiPS
are trademarks of Intel Corporation. RAMpage!, SixPakPlus and
SixPakPremium are registered trademarks of AST Research, Inc.
Mouse Systems is a trademark of Mouse Systems Corporation.
Centronics is a registered trademark of Centronics Data Computer
Corporation. PAL and PALASM are registered trademarks of Advanced
Micro Devices, Inc. UNIX is a trademark of AT&T Technologies, Inc.
CUPL is a trademark of Logical Devices, Inc.. Apollo and AEGIS are
registered trademarks of Hewlett-Packard Corporation. Mentor and
IDEA are registered trademarks and QuickSim, NETED, EXPAND are

trademarks of Mentor Graphics, Inc. ValidGED and ValidSim are
trademarks of Valid Logic Systems, Inc. Sun is a registered trademark
of Sun Microsystems, Inc. SCHEMA 11+ and SCHEMA III are trademarks
of Omation Corporation. OrCAD is a registered trademark of OrCAD
Systems Corporation. VIEWlogic, VIEWsim, and VIEWdraw are
registered trademarks of VIEWlogic Systems, Inc. CASE Technology is
a trademark of CASE Technology, a division of Teradyne's Electronic
Design Automation Group. DECstation is a trademark of Digital
Equipment Corporation.
Xilinx, Inc. does not assume any liability arising out of the application or
useof any product described herein; nor does it convey any license under
its patent, copyright or maskwork rights or any rights of others. Xilinx, Inc.
reserves the right to make changes, at any time, in order to improve
reliability, function or design and to supply the best product possible.
Xilinx, Inc. cannot assume responsibility for the use of any Circuitry
described other than circuitry entirely embodied in their product. No other
circuit patent licenses are implied. Xilinx, Inc. cannot assume
responsibility for any circuits shown or represent that they are free from
patent infringement or of any other third party right. Xilinx, Inc. assumes
no obligation to correct any errors contained herein or to advise any user
of this text of any correction if such be made.

SECTION TITLES

1

Programmable Gate Arrays

2

Product Specifications

3

Quality, Testing, Packaging

4

Technical Support

5

Development Systems

6

Applications

7 Article Reprints

B Index

TABLE OF CONTENTS

1 Programmable Gate Arrays
About the Company
Introduction to Programmable Gate Arrays
A Cost of Ownership Comparison

1-1
1-3
1-11

2 Product Specifications
XC3000 Logic Cell Array Family
XC2064, XC2018 Logic Cell Arrays
Military Logic Cell Arrays
XC2018B Military Logic Cell Array
XC3020B Military Logic Cell Array
XC3042B Military Logic Cell Array
XC3090B Military Logic Cell Array
XC1736A11765 Serial Configuration PROM
Sockets

2-1
2-61
2-103
2-107
2-119
2-137
2-157
2-175
2-187

3 Quality, Testing, and Packaging
Quality Assurance and Reliability
Test Methodology
Packaging

4

3-1
3-12
3-18

Technical Support
Technical Seminars and Users' Group Meetings
Video Tapes
Newsletter
Technical Bulletin Board
Field Applications Engineers
Training Course
Technical Literature

4-1
4-2
4-3
4-4
4-6
4-7
4-8

5 Development Systems
Overview
Automatic CAE Tools Product Overview
Product Briefs
Xilinx Development System Support Agreements
LCA Macro Library Listings
Development System Hardware Requirements

5-3
5-4
5-19
5-33
5-34
5-40

6 Applications
Introduction
Estimating Size and Performance
Designing with the XC3000 Family
Designing with the XC2000 Family
Additional Electrical Parameters
LCA Performance
Delay Tracking
Start-up and Reset

6-1
6-3
6-7
6-8
6-9
6-11
6-14
6-15

TABLE OF CONTENTS

6 Applications

(Cont'dJ

Metastable Recovery
Battery Backup for Logic Cell Arrays
Compact Multiplexer and Barrel Shifter
Majority Logic, Parity
Multiple Address Decoding
Binary Adders, Subtractors, and Accumulators
Adders and Comparators
Conditional Sum Adder
Building Latches Out of Logic
Synchronous Counters, Fast and Compact
30 MHz Binary Counter Uses Less than One CLB per Bit
Up/Down Counter Uses One CLB per Bit
Loadable Up/Down Counter Uses One CLB per Bit
30 MHz Counter with Synchronous Reset/Preset
Fast Bidirectional Counters for Robotics
40 MHz Presettable Counter
Asynchronous Preset in XC3000 CLBs
Frequency/Phase Comparator for Phase-locked-Loops
Gigahertz Presettable Counter
75 MHz Frequency Counter or Programmable Delay
Serial Pattern Detectors
Serial Code Conversion Binary to BCD
Serial Code Conversion BCD to Binary
Corner Bender or 8-Bit Format Converter
100 MHz Frequency Counter
Megabit FIFO in Two Chips
State Machines
Complex State Machine in One LCA
PS/2 Micro Channel Interface
DRAM Controller with Error Correction

6-16
6-18
6-19
6-20
6-21
6-22
6-23
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-36
6-37
6-38
6-40
6-41
6-42
6-43
6-44
6-45
6-46
6-48
6-49
6-50
6-52

7 Article Reprints
Building Reconfigurable Peripheral Controllers
Accelerate FPGA Macros with One Hot Approach
Reprogrammable Missile: How an FPGA Adds Flexibility to
Navy's Tomahawk
Pivoting Monitor Increases Versatility of Workstations
Two, Two, Two Chips in One
LCA Stars in Video
Taking Advantage of Reconfigurable Logic
Faster Turnaround for a T1 Interface
Using Programmable Logic Cell Arrays In a Satellite Earthstation
Programmable Logic Betters the Odds for Bet-Slip readers
Building Tomorrow's Disk Controller Today

7-1
7-8
7-13
7-15
7-19
7-22
7-24
7-33
7-35
7-40
7-44

8 Index
Index
Sales Office Listing

8-1
8-5

The Programmable Gate Array Company

GATE ARRAYS

PROGRAMMABLE LOGIC
DEVICES

EXTENSIVE
SIMULATION

LOW
DENSITY

USER
PROGRAMMABLE

ADVANC
DEVELOPMENT
TOOLS

116201

THE PROGRAMMABLE GATE ARRAY
(LOGIC CELLTM ARRAY)

SECTION 1
Programmable Gate Arrays

1

Programmable Gate Arrays

2

Product Specifications

3

Quality, Testing, Packaging

4

Technical Support

5

Development Systems

6

Applications

7

Article Reprints

8

Index

Programmable Gate Arrays

About the Company ............................................................................ 1-1
Introduction to Programmable Gate Arrays ......................................... 1-3
Programmable Gate Array Architecture .............................................. 1-4
Development Systems ........................................................................ 1-9
Technical Support ............................................................................... 1-10
A Cost of Ownership Comparison ....................................................... 1-11
Executive Summary ............................................................................ 1-11
ROM vs EPROM Analogy ................................................................... 1-12
Who Recognizes the Costs? ............................................................... 1-13
Fixed Development Costs ................................................................... 1-13
Variable Costs ..................................................................................... 1-15
Yield to Production .............................................................................. 1-17
Cost of Ownership Analysis ................................................................ 1-18
Break-even Analysis ........................................................................... 1-19
Time to Market .................................................................................... 1-19
Product Life Cycles ............................................................................. 1-19

About the Company ...

patible with the stringent time-to-market requirements.
With Xilinx FPGAs, design engineers can bring new products to market quickly without sacrificing the benefits of
integration. Many systems can be manufactured with only
three types of standard high-volume components-microprocessors, memories and FPGAs.

Xilinx was founded in 1984 based on the revolutionary
idea, to combine the high logic density and versatility of
gate arrays with the time-to-market advantages and offthe-shelf availability of userprogrammable standard parts.
In 1985, Xilinx produced the world's first fieldprogrammable gate array (FPGA). The company holds
patents on FPGA architecture and technology, and today
is the largest supplier of devices in this IC category,
predicted to be the fastest growing segment of the
semiconductor industry in the nineties. To date, the
company has sold over 8500 development systems and
five million FPGAs to more than 3500 system
manufacturers worldwide.

Xilinx strategy is to focus its resources on creating new ICs
and development system software, on market development and creation of a diverse customer base across a
broad range of geographic and market-application segments. The company avoids the large capital commitment
and overhead burden associated with owning a waferfabrication facility by establishing a manufacturing alliance
with Seiko Epson who has manufactured all of the company's FPGA production wafers to date. In 1989, Xilinx
entered into an agreement with AT& Tlo provide additional
production capacity. Each of these manufacturers uses
the same proven CMOS processing used to manufacture
high-speed static RAMs (SRAMs). Using a standard
process is cost-effective and produces FPGAs with established reliability, and provides forearly access to advances
in CMOS technology.

Xilinx has maintained market leadership with a succession
of new products that have increased FPGA density
sevenfold, improved FPGA speed fivefold, and reduced
FPGA cost by a factor of fou r-all in less than three years.
Competitive pressures have forced manufacturers of electronic systems to bring increasingly complex products to
market rapidly. Requirements for improved functionality,
performance, reliability and lower cost are often
addressed through the integration of ever larger numbers
of transistors onto a single IC. In systems such as
computers, telecommunications systems, medical diagnostic equipment and control systems, integration results
in faster speed, smaller size, lower power consumption
and lower costs. However, the length of time required to
develop these more sophisticated systems is often incom-

The company markets its products in North America
through a network of five direct-sales offices, 65
manufacturers' rep locations and six distributors. Outside
North America, the company sells its products through
direct-sales offices in England, Germany and Japan and
through manufacturers' reps and distributors in 45 offices
in 20 countries.

1-1

III

1-2

Introduction to
Programmable Gate Arrays
Steady advances in the level of intergration in electronic
circuits have improved many equipment features, reducing
costs, power consumption, and system size, while
increasing performance and reliability. Increasing levels of
integration are most evident in microprocessor and
memory ICs. With each process generation, the
technology gap between these VLSI circuits and other
standard logic ICs has widened. To achieve comparable
densities for their proprietary logic functions, designers of
digital equipment have been forced to consider factoryprogrammed custom and semicustom Application Specific
Integrated Circuits (ASICs).

Field Programmable Gate Arrays (FPGAs), are highdensity ASICs that can be configured by the user. They
combine the logic integration benefits of custom VLSI with
the design, production, and time-to-market advantages of
standard products. Designers define the logic functions of
the circuit and revise these functions as necessary. Thus
FPGAs can be designed and verified in a few days, as
opposed to several weeks for custom gate arrays; FPGA
design changes can require as little as a few hours,
compared to several weeks for a custom array. This
results in significant cost savings by reducing the risks of
design changes, rescheduling, and eliminating nonrecurring engineering costs.

ASIC ALTERNATIVES
Application Specific ICs are the best solution for most logic functions.
The best ASIC solution depends on density requirements and production volumes.
20,000

STANDARD
CELL AND
CUSTOM

10,000

z

0
f=

()

5,000
FIELD PROGRAMMABLE
GATE ARRAYS

Z

:::J

~
w

1,000

f-

.k_ _ _ _·'_·I_EN_AB_LE_)

RESET_;l;.-"".rd"--_ _ _ _ _ _ _ _---l
'O'(INHIBIT)

t.W...V.N..~~~~~:'"

----l

RESET) - - .....-.....-.....-.....-....•-.•..--'
•.••..

N

••••••••

w •.••.• w •.••• w •.•.••••••••••••.• }

1101 03

Configurable Logic Block
The core of the LCA device is a matrix of identical Configurable Logic Blocks (CLBs). Each CLB contains programmable combinatorial logic and storage registers. The
combinatorial logic section of the block is capable
of implementing any Boolean function of its input variables. The registers can be loaded from the combinatorial
logic or directly from a CLB input. The register outputs can
drive the combinatorial logic directly via an internal
feedback path.
1-4

Input/Output Block
The periphery of the LCA device is made up of user
programmable Input/Output Blocks (lOBs). Each block
can be programmed independently to be an input, an
output with 3-state control or a bidirectional pin. Inputs can
be programmed to recognize either TTL or CMOS thresholds. Each lOB also includes flip-flops that can be used to
buffer inputs and outputs.

Vo<

3· STATE-t:'--+----=lU>--i-,

(OUTPUT ENABLE)

ollT-i---IL/

III
DIRECT IN
REGISTERED IN

j}-

-r-----t------,

-1-'---+--;

PROGRAM

o '"

CONTROLLED
MULTIPLEXER

PROGRAMMABLE INTERCONNECTION POINT or PIP
110501A

D
0

000

000

000 00
0

0

0

0

0
0

00
0

D

DO

0

0

0
0

0

0

0

0

0

0

0

D

0

0

0

0
D

0

0

0

0
0

0

0
0

1101 05

0

0

0

0

0

D

0

0

0

0

D

00

0

0
0

0

0

0

0
0

0

0

0

'"

0

a

0
0

DO
0

Do
0

DO

Interconnect
The flexibility of the LCA device is due to the programmabie resources that control the interconnection of any
two points on the chip. Like other gate arrays, the LCA
interconnection resources include a two-layer metal network of lines that run horizontally and vertically in the rows
and columns between the CLBs. Programmable switches
connect the inputs and outputs of lOBs and CLBs to
nearby metal lines. Crosspoint switches and interchanges
at the intersections of rows and columns can switch
signals from one path to another. Long lines run the entire
length or breadth of the chip, bypassing interchanges to
provide distribution of critical signals with minimum delay
or skew.

0

0
0

0

0

0

0

0

0

0

000 000 000 00 0 000 00 0 00 0

1101 02

1-5

Introduction to Programmable Gate Arrays

XC2000
Programmable Logic Cell Array Family

The XC2000 series of LCA devices was introduced in 1985.
Price reductions since that time have reflected steadily
increasing production volumes. The family includes two
compatible arrays: the XC2064 with 1200 gates, and the
XC2018 with 1800 gates.

Features

o

Fully user-programmable:

• 1/0 Functions
• Logic and storage functions
• Interconnections

o

Three performance options: 50-,70- and 100-MHz
toggle rates

o

Three package types: Dual in-line package
Plastic leaded chip carrier
Pin grid array
TTL or CMOS input thresholds

o
THE XC2000 Family Members

XC2064
Equivalent Gates

XC2018

1200

Configurable Logic Blocks

100

Combinatorial Logic Functions

128

200

Latches and Flip-Flops

122

174

58

74

I nputlOutputs

XC1736A and XC1765
CMOS Serial Configuration PROM
The Serial Configuration PROMs are companion devices that provide
permanent storage of LCA configuration programs. They can be used
whenever a dedicated device is preferable to sharing of a larger
EPROM, or to loading from a microprocessor.

Features

1800

64

o

One-Time Programmable (OTP) 36,288- or 65,536-bit serial
memory designed to store configuration programs for FPGAs

o
o
o
o
o
o

Simple interface to a Logic Cell Array requires only two 1/0 pins
Daisy-chain support for multiple devices
Cascadable for large arrays or many LCA devices
Storage of multiple configurations for a single LCA device
Low-power CMOS EPROM process
Space-efficient, low-cost 8-pin DIPs

1-6

E:XIUNX

XC3000
Logic Cell Array Family
The XC3000 series is a second generation family of
CMOS Logic Cell Arrays that includes five compatible
members with logic densities from 2000 to 9000 gates.

II

Features

0

Fully user-programmable:

0 Second generation architecture
• 5-input logic functions
• 2 flip-flops per CLBIIOB
• Enhanced routing resources
• 3-state drivers for wide ANDs

• 1/0 Functions
• Logic and storage functions
• Interconnections
0

0

Five member product family
• 2000-9000 gates
• Compatibility for ease of design
migration

0 Programmable voltage slew rates on
outputs
0 Three package types:
• Plastic leaded chip carrier
• Pin grid array
• Quad flat package

Four performance options:
·50-,70-,100- and 125-MHz
toggle rates

The XC3000 Family Members

Equivalent Gates
Configurable Logic Blocks

XC3020

XC3030

XC3042

XC3064

XC3090

2000

3000

4200

6400

9000

64

100

144

224

320

Combinatorial Logic Functions

128

200

288

448

640

Latches and Flip-Flops

256

360

480

688

928

I nputlOutputs

64

80

96

120

144

1-7

Introduction to Programmable Gate Arrays

XC4000
Logic Cell Array Family

achieve fully automated implementation of complex, highperformance designs. It is the first FPGA family to break
the 20,000-gate barrier; the first member of the XC4000
family will be sampled in late 1990.

The XC4000 series, the third-generation family of CMOS
LCA devices, combines architectural versatility, on-chip
RAM, increased speed and gate complexity with abundant
routing resources and new, sophisticated software, to

Features

0

Third generation user-programmable
gate array
Abundant Flip-Flops
Flexible function generators
On-chip fast RAM
Dedicated high-speed Carry
Propagation circuit
Fast, wide decoders
Unlimited number of logic levels
Hierarchy of interconnect lines
Internal 3-state bus capability

0

0

0

0
0

Flexible array architecture

110 blocks
·· Programmable
Programmable logic blocks
interconnects
·· Programmable
Programmable wide decoders

Sub-micron CMOS process
High speed (toggle/shift rate
>100 MHz, counters >50 MHz)
• Low power consumption
Systems-oriented features
Slew-rate limited outputs
Programmable input pull-up or pulldown resistors
Configured by loading binary file
Unlimited reprogrammability
Six programming modes
Development system runs on '386based PC and on many popular
workstations
Fully automatic placement and
routing plus optional interactive
enhancements

·

··

··
·

XC4000 Family Members

XC4002

4003

4004

4005

4006

4008

4010

4013

4016

4020

4,000

5,000

6,000

8,000

10,000

13,000

16,000

20,000

Appr. Gate Count

2,000

3,000

CLB Matrix

8x8

10 x 10 12 x 12 14x 14 16 x 16 18 x 18 20 x 20 24x24 26 x 26 30 x 30

Configurable Logic Blocks
Max RAM Bits
InputlOutpts

64

100

144

196

256

324

400

576

676

900

2,048

3,200

4,608

6,272

8,192

10,368

12,800

18,432

21,632

28,800

64

80

96

112

128

144

160

192

208

240

The XC4000 family of Logic Cell Arrays is not covered in this Data Book.

Ask for the separate XC4000 Product Description.

1-8

Development Systems
Designing with Xilinx FPGAs is similar to designing with other gate arrays.
Designers can use familiar CAE tools for design entry and simulation. The
open Xilinx development system includes a standard nellist format, the Xilinx
Nellist File (XNF), that provides a bridge between schematic editors or
simulators, and the XACT software for design implementation and real time
design verification. The Xilinx software is supported on the PC/AT and
compatibles as well as on popular engineering workstations.

II

Step 1
DS371
DESIGN
ENTRY

Design Entry Software
consists of libraries and nellist interfaces
for standard CAE software such as
FutureNet, Schema, OrCAD, VI EWlogic,
Mentor, Valid, CASE, and PALASM. Pro·
grammable gate array libraries permit
design entry with standard TTL functions,
with Boolean equations, and with user·
defined macros.

LOGIC REDUCTION
PARTITIONING AND
OPTIMIZATION
PLACE AND ROUTE

Simulation Software

Step 2

includes models and nellist interfaces to
standard simulator software, such as
SILOS and CADAT, that is used for logic
and timing simulations.

DESIGN
IMPLEMENTATION

DESIGN EDITOR
TIMING CALCULATOR
DOWNLOAD CABLE
BITSTREAM GENERATOR
DS21

Design Implementation Software
is used to convert schematic netlists and
Boolean equations into efficient designs
for programmable gate arrays. The soft·
ware includes programs that perform par·
titioning, optimization, placement and
routing, and interactive design editing.

Step 3
DESIGN
VERIFICATION

~X1l1NX
XC3020-70
PC68C
X9201MB730

XACTOR
DESIGN VERIFIER

DS26127/28

110106B

1·9

In·circuit Design Verification Tools
permit real·time verification and
debugging of a programmable gate array
design as soon as it is placed and routed.
Designers benefit from faster and more
comprehensive design verification, and
from reduced requirements to generate
simulation vectors to exercise a design.

Introduction to Programmable Gate Arrays

o
o
o
o
o

Technical Support
SOFTWARE UPDATES

Xilinx is continuing to improve the XACT development
system software, and new versions are released two or
three times per year. Updates are provided free of charge
during the first year after purchase, provided the user
returns the registration card. After the first year, users are
encouraged to purchase a Software Maintenance Agreement to continue to receive software updates.

Read files from the bulletin board
Check current software version numbers
Download files
Upload files
Leave messages for other bulletin-board users.

TECHNICAL LITERATURE

In addition to this databook, technical literature for the
Xilinx programmable gate array includes four volumes that
are delivered with every XACT development system.

TRAINING COURSES

To get up-to-speed quickly, new Xilinx users are invited to
attend comprehensive training classes. These classes
are taught by factory experts and include the latest software and hardware advances.

o

User's Guide
The User's Guide is a collection of "how to" applications
notes on such subjects as getting started with an LCA
design, Boolean equation design entry, use of the
simulator, placement and routing optimization, and
LCA configuration.

o

Reference Manuals (2 vols)
The XACT Reference Manuals include a detailed description of each Xilinx software program.

o

Macro library
The Xilinx development system includes over 100
macros, including counters, registers, and multiplexers. The macro library manual includes schematics
and documentation for each macro.

XILINX USER GROUPS

Xilinx users are invited to attend training and information
exchange sessions that are held two-to-three times per
year in various locations worldwide. These User Group
meetings are intended for experienced users of Xilinx
Programmable Gate Arrays, and they emphasize the
efficient use of the XACT development system.
FIELD APPLICATIONS
ENGINEERS

Xilinx provides local technical support to customers
through a network of Field Applications Engineers (FAEs).
For the name and phone number of the nearest FAE,
customers may call one of the Xilinx sales offices listed in
the back of this book.
APPLICA TlONS HOT LINE

Xilinx maintains an applications hot line to provide technical support to LCA users. This service is available from
7:30 am to 6:00 pm Pacific Time. Call (408) 879-5199 or
(800) 255-7778 and ask for Applications Engineering.
BULLETIN BOARD

To provide customers with up-to-date information and an
immediate response to questions, Xilinx provides 24-hour
access to an electronic bulletin board. The Xilinx Technical bulletin board provides the following services to all
registered XACT development-system customers.

1-10

A Cost of Ownership
Comparison

CONTENTS

Field Programmable
Gate Arrays (FPGAs)

Executive Summary
ROM vs EPROM Analogy
Who Recognizes the Costs?
Total Cost =Fixed Cost + (Variable Cost) (Units)
Fixed Development Costs for Gate Arrays
Simulation
Time to Design For Testability
NRE Charges
Design Iterations
Test Program Development
Second Source
Summary of Fixed Development Costs
Variable Costs
Unit Cost (Cents/Gate)
Inventory
Yield to Production
Cost of Ownership Analysis
Break-even Analysis
Time to Market
Product Life Cycles
References

Gate Arrays

Custom product
Standard product
Off-the-Shelf delivery
Months to manufacture
Fast time to market
Manufacturing delays
Programmed in the factory
Programmed by the user
NRECosts
NoNRE
No inventory risk
Design specific
User develops test
Fully factory tested
Simulation critical
Simulation useful
In-circuit design verification Not possible
NRE charge repeated
Design changes anytime
Additional cost and time
Second source exists
looks at the various categories of costs, both fixed and
variable, for devices from 2000 to 9000 gates, 80% of the
gate-array market according to most studies.
Because the gate array has fixed or up-front development
costs (NRE, extra simulation time, generating test vectors,
etc.) that the FPGA does not, its total cost of ownership is
higher until a sufficient quantity is purchased. This analysis allows the user to calculate total cost of ownership at
different quantities and derive break-even quantities the volume below which it is more cost effective to use the
FPGA (Break-even Analysis section). The overall objective is to determine the production volumes at which each
product is most cost effective.

EXECUTIVE SUMMARY
Introduction
Custom or mask-programmed gate arrays have many
hidden costs beyond the obvious unit cost and NRE (nonrecurring engineering) charges. Most of these additional
costs are due to the fact that a gate array is a custom
integrated circuit, one manufactured exclusively for a
particular customer. Compared to a standard product,
there are many hidden expenses, both during the design
phase and after purchase, beyond the direct device cost.

Conclusion
The choice between FPGA- and mask-programmed gate
arrays must take into account more than the NRE and
cents/gate unit cost. The use of a custom product entails
many other costs and risks. Because of these fixed costs,
it is less expensive at lower volumes to use a standard
product: an FPGA. Since many of the hidden costs of
using a custom gate array do not accrue to anyone
department, only the project manager can recognize the
total cost.

Field-programmable gate arrays (FPGAs), on the other
hand, are high-volume standard products-manufactured
and fully tested devices that are used by all customers.
There is no customization of the silicon.

Similar considerations have led to the widespread acceptance of EPROM memories as compared to ROMs, despite a higher EPROM cost per unit. The same factors can
be applied in the choice of a gate array.

Methodology
This analysis compares the total costs of custom gate
arrays with those of field-programmable gate arrays. It

1-11

II

A Cost of Ownership Comparison

Figure 1 shows a representative break-even graph for a
2000-gate device using 1990 data. The vertical axis
shows the total project cost-fixed costs plus unit costs
multiplied by the number of units. At lower volumes, the
custom gate array is more expensive because of fixed
costs that are incurred even if no units are purchased. The
FPGA project cost starts at zero, but rises faster because
of a higher cost per-unit. In this case the break-even
volume is between 10k and 20k units. The various
components of this analysis are discussed in the following
sections. Also, guidelines are given to help the user make
a simple calculation for a specific solution.

Several significantfactors are omitted from Figure 1. First,
the additional fixed costs (NRE, simulation) of bringing on
a custom-gate-array second source are not included.
Second, and much more important, the cost of the longer
time to market when deSigning with the mask gate array is
not included. This factor is reviewed in the Time to Market
section. Both of these factors would raise the custom gate
array curve and inc~ease the break-even quantity. In other
words, the FPGA would be more cost effective at an even
higher production volume.
ROM VS EPROM ANALOGY

There is a relevant historical precedent for the use of a
flexible standard product instead of a custom product with
a lower direct cost perunit. While EPROMs have a cost per
bit that is two to three times that of ROMs, they have
consistently captured almost half the programmable
memory market, measured in bits shipped. See Figure 2.
Many of the reasons for the use of EPROMs are the same
as those for the use of programmable gate arrays: faster
time to market, lower inventory risks, easy design
changes, faster delivery, and second sources. The higher
price per bit is offset by the elimination of inventory and
production risks.

TOTAL
PRQJECT
COST ($)

Gate arrays have even more disadvantages versus programmable gate arrays than do ROMs versus EPROMs.
The upfront design time, risk, and expense of ROMs is
minimal, while that of gate arrays is substantial. ROM test
tape generation is automatic, while that for gate arrays
requires extensive engineering effort. Therefore, FPGAs
may be even more widely used versus gate arrays than are
EPROMs versus ROMs.

L

______

~

~

L -_ _ _ _ _ _

~

~:Jg~~~
NRE }
SIMULATION TIME
DESIGNING TESTABILITY
TEST PROGRAM
DESIGN ITERAnONS

.ok

10k
PROJECT UNITS

-

CUSTOM GATE ARRAY

1102 01A

-FPGA

Figure 1. Typical Break-even Analysis 2000 Gates-1990

140
120
100

TERABITS
SHIPPED

~
~

80
60
40
20
0
1983

1984

1985

1986

1987

1988

1989

EPROM Mll.¢IBlT 10.9
ROM MIL¢!BIT 4.5

9.2
3.2

4.0
1.7

2.5
1.0

1.8
0.7

1.3
0.5

0.9
0.4

2.9

2.4

2.5

2.6

2.6

RATIO

2.4

2.3
SOURCE: DATAQUEST

Figure 2. ROM/EPROM Analogy

1-12

1102 05

WHO RECOGNIZES THE COSTS?

explicitly for computer time, an estimate would be $2,500
and 2.5 man weeks of simulation effort for a 2000-gate
array, and $5,000 and seven man weeks for a 9000-gate
array. This compares to 0.5 and 1 week forthe FPGA, with
no simulation charge.

Many of the elements of the total cost of ownership for a
gate array do not accrue to a single department, and often
are not fully recognized. For example, the additional
engineering time needed to design for testability may not
be seen by purchasing. The inventory costs of a custom
product may not be recognized by the design department.
However, these are real costs, and they influence the
profitability of the product and company. The person
making the choice between custom gate arrays and
FPGAs should consider the total costs of ownership for
each alternative.

Typically one fully burdened man week, including
computer support, costs about $2000.
2000 Gates

9000 Gates

$2.5k
2.5MW

$5k
7MW

None
O.5MW

None
1MW

Gate Array
Simulation Charge
Man Weeks

TOTAL COST = FIXED COST +
(VARIABLE COST)(UNITS)

FPGA

The total costs of using a product can be separated into
two components. The first is the fixed costs: up-front development costs that are independent of volume. Some
examples ofthese for gate arrays are the masking charge,
simulation charge, and test program development. Due to
amortization of these costs, the user's cost per unit can be
very high until a sufficient volume of units is purchased.
The second component of total cost is the variable cost,
the incremental cost per unit. Besides the obvious unit
cost, another element of variable cost is inventory cost.

Simulation Charge
Man Weeks

Time to Design for Testability
One key to getting a successful gate array the first time is to
focus on testing issues. The user must guarantee that the
device can be fully tested in a reasonable amount of time.
Since the gate array vendor's only guarantee is that the
device will pass the test program, the user must be certain
that if the IC meets the user-generated test specifications,
it will work in the circuit.

This analysis will examine costs by these two categories.
Fixed costs are summarized first, then variable costs.
They are added to produce total cost.

Spending extra time in the design phase provides insurance that the device can be tested. A Dataquest ASIC
Market Report observes that "an engineer can sit down at a
$20,000 CAE/CAD station and design a $1,000,000 test
problem." Designing in testability may also be the only way
to provide for testing of complex sequential circuitry, or
elements like long counters. Therefore the gate array designer must spend additional time in the design phase. An
estimate is one additional week for a 2000-gate array, and
two additional weeks for a 9000-gate array.

FIXED DEVELOPMENT COSTS
Simulation
With a custom product, it is critical that the device work the
first time. Otherwise, the user must pay to have the device
prototyped a second time and will incur the manufacturing
delay a second time. Custom gate arrays do not support a
conventional, iterative, modular deSign process-the
design is all-or-nothing. Simulation is a useful tool with
FPGAs, but it is a critical one with gate arrays, and the
designer can expect to spend more time simulating a
custom gate array design. The programmable gate array
designer can count on in-circuit verification and on-line
changes if necessary.

The FPGA isa standard product with no incremental test
costs. It is fully tested by Xilinx before shipment. No application-specific testing is needed.
Gate Array Incremental Cost

Gate array simulation cost includes both computer time
charges and the time of the engineer doing the simulation.
While the gate-array vendor mayor may not charge

1-13

2000 Gates

9000 Gates

1 Man Week

2 Man Weeks

II

A Cost of Ownership Comparison
NRE Charges

Test Program Development

NRE (Non-Recurring Engineering) charges cover the online vendor interface, design verification, mask charges,
prototype samples and a nominal simulation (pre- and
post-layout) time. The charges may vary with estimated
production volumes. At volumes below 50,000 units,
$10,000 to $20,000 is a competitive quote for lower density
gate arrays. At the 9000-gate level, NRE charges may be
in excess of $30,000.

As noted in the Time to Design for Testability section, testability is critical to production success for gate arrays.
Gate-array vendors rarely make production errors, but
faulty devices may not be detected because the test vectors are not comprehensive.
The estimate for test-vector development is two weeks for
a 2000-gate array, and four weeks for a 9000-gate array.
Since the FPGA is a standard product, it is fully tested at
the factory. No application-specific testing is needed.

There are no NRE charges for programmable gate arrays.
The entire design process is done by the customer. FPGA
software tools run on common workstations and personal
computers, and are much less expensive than comparable tools for custom gate arrays.

A risk that the program manager should consider involves
the level of experience or knowledge that the design team
has with test development. If the first-pass design is unsuccessful, how much time and effort will be required to
debug the problem? Both additional cost and time to market are at risk.

Typical Gate Array NRE for 10,000 to 50,000 units
2000 Gates

9000 Gates

Gate Array Incremental Cost
$10 k-$20 k

$20 k-$40 k

The phrase "We need to add this feature" is all too common to the designer of electronic equipment. Designers
often find themselves faced with the need to modify a
design during prototyping or initial customer evaluation. Changes may be required to add features or reduce
costs. As systems become more complex, "bugs" can be
more prevalent.

Second Source
If a second source is required, the gate-array deSigner
must identify a compatible vendor and resubmit the design. This involves another NRE charge and time for
translating logic and resimulation. The model used here is
the NRE charge plus one half the simulation cost.

Design iterations are almost never due to the failure of
the gate-array vendor. Rather, there are risks associated
with the choice of an inflexible technology in a very
dynamic industry.

Field-programmable gate arrays are standard products
that already have a second source.
Gate Array Incremental Cost

Industry data suggest that about half of all gate-array designs are modified before they are released to production.
When a modification is required, NRE costs are incurred
for the second pass. Since resimulation is likely to involve
less effort than the initial simulation, 25% (50% probability
times one half the effort) of the simulation cost is added.

NRE
Simulation
Charge
Man Weeks

Gate Array Incremental Cost
Probability

4 Man Weeks

2 Man Weeks

Design Iterations

SO%

9000 Gates

2000 Gates

2000 Gates

9000 Gates

$10k-$20k

$20 k-$40 k

$1.2Sk

$2.Sk

1MW

3MW

Summary of Gate Array Fixed DevelopmentCosts

(original NRE time and cost + one half of
original simulation time and cost)

The summary in Table 1 shows typical fixed costs for both
a 2000-gate and a 9000-gate array. Since assumptions
may vary, a blank column is provided as a worksheet.

1-14

1. Simulation
NRE
Man Weeks
2. Design for Testability
3. NRE Charges
4. Design Iterations @ 50% probability
NRE
Man Weeks
5. Test Program Development
6. Second Source (NRE + 50% SIM)
NRE
Man Weeks

Typical
2000 Gates

Typical
9000 Gates

$2,500
2MW
1MW
$10 k-$20 k

$5,000
7MW
2MW
$20 k-$40 k

$8,125
0.5MW
2MW

$16,250
1.5MW
4MW

$16,250
1MW

$32,500
3MW

Total Without Second Source
NRE
Man Weeks
Total With Second Source
NRE
Man Weeks

$25,625
5.5MW

$51,250
14.5MW

$41,875
6.5MW

$83,750
17.5 MW

Total Fixed Costs @ $2 klMW
Without Second Source
With Second Source

$36,265
$54,875

$80,250
$118,750

Customer
Application

II

@$-1MW

Table 1. Typical Fixed Costs

VARIABLE

COSTS

while gate arrays are in a more mature phase of the cycle.
Price comparisions should be based on projections over
the production life of the product.

Production Unit Cost (Cents/Gate)
Gate-array prices are often quoted in terms of cents per
gate. For 1.2 micron, 2000-gate arrays, at the volumes
considered in this analysis (10,000 to 30,000 units), a
figure of 0.15 - 0.20 cents/gate (without package) is
typical. At similar volumes, the cost per gate (without
package) for an FPGA is two to three times the cost of a
custom gate array. For reasons explained below, this gap
is expected to narrow over the next few years. All of the
cents/gate numbers are for die only. Since CMOS gate
arrays and FPGAs use the same packages, the package
adders are equivalent.

A standard product has more silicon content and less factory overhead than a custom product. Since all customers
buy the same product, there is more of the semiconductor
learning curve with cumulative volume. Given the profitability levels of array manufacturers, gate array prices may
decline only Slightly over time and could even rise.
1991 FPGA Unit CostsWithout Package

An important consideration in calculating the total cost of
ownership is the year during which most of the production
volume will be purchased. Since FPGAs are newer
products, their cost is declining at a steeper rate than gate
arrays. They are in the introduction phase of the life cycle,

Programmable
(Cents/Gate)

1-15

2000
Gates

4000
Gates

9000
Gates

20kOty
0.30-0.40

10kOty
0.40-0.50

10 kOty
0.50-0.60

A Cost of Ownership Comparison

Process Technology

volume applications, few gate arrays are retooled to take
advantage of process advances. The time from design
start to end of production lifetime is usually several years.
Overthis period, the FPGA will move to successively more
advanced processes, resulting in steadily decreasing
costs. By the end of the production lifetime, the FPGA will
be several processes ahead and the cost difference will be
reduced significantly.

There are also technology reasons for the steeper decline
in FPGA cost. Figure 3 shows that the processes used for
logic IGs, including gate arrays, typically lag behind those
used for memory IGs. Since the FPGA is a standard IG
built on a memory process, it can take advantage of each
new process to shrink the die and reduce costs.
With a conventional gate array, the process that is available at the time of design is usually used throughout the
production lifetime of the product. Except for very high-

Pad-Limited Die Sizes
As gate arrays and FPGAs grow in 110 pin count, a phenomenon known as "pad-limiting" is more likely to occur.
The spacing between 1/0 pads is determined by mechanical limitations of the equipment used for lead bonding. In
I/O-intensive applications the number of pads around the
outer edge of the die determines the die size, instead of the
number of gates. See Figure 4. In I/O-intensive applications, a "cost per 1/0" may be a more useful measure than
"cost per gate."
For a given 1/0 count, in the pad-limited case the FPGA
and the gate array would be the same die size. As a result,
the higher volume, standard product, FPGA could actually
be less expensive on a per-unit basis than the customproduct gate array. There would be no break-even quantity - the FPGA would have a lower cost of ownership at
all volumes.

o. , '--'---'--'---'---'---'_.l..--'---'--'--'----'_'--.l.-..J
00

m

~

~

M

~

00

~

00

00

00

~

~

~

YEAR

~

M

1'0202

Figure 3. Process Evolution

PAD-LIMITED DIE

350
300

000000000000000

250

0
0
0

0
0

o
o
o
o
o
o
o

0
0
0

o

DIE 200
WIDTH
MILS 150

100
50
0
40

o
o
o
o
o

0

0

0
0
0

000000000000000
60

80

100

120

140

160

180

NUMBER OF PADS

Figure 4. Minimum Die Size vs I/O

1-16

1102 OlA

mum economical wafer-lot quantity. Inventory is created
and costs are incurred. Moreover, there is the problem of
inventory ownership if the parts are never ordered by the
customer.

Effect of Die Cost on Total Cost
Figure 5 illustrates a third point about the capability of FPGAs to narrow the cost difference with custom gate arrays.
The chart shows the contribution to total device cost of
wafer, die, assembly and test. Wafer cost represents
about 20% to 40% of the total device cost, and die cost
about 30% to 50%. A 50% difference in die cost - between
a gate array and a FPGA - shown in the chart translates to
only a 20% difference (80 vs 100) in total cost by the time
the device has been tested. This comparison is based on
production of the FPGA in a more advanced process than
the custom gate array, as discussed in the Unit Cost
(Cents/Gate) section.

Although the safety stock reserve is a function of the cost of
the product itself, a figure of 10% is reasonable for gate
arrays that have unit costs under $25.00. In comparison,
since changes to FPGAs can be made in software in minutes, and since only one part type is widely stocked, the
comparative safety stock reserve is 0%.
Gate Array Incremental Inventory Cost

10% Additional Unit Cost

Inventory Reserves
Inventories include extra devices ordered and stocked to
cover contingencies. For a custom product, this is the only
way parts can be delivered in less than the normal production time (2-4 months). Contingencies are often thought of
in terms of negative events like a defective lot or manufacturing shortfalls.

YIELD TO PRODUCTION
Due to rapidly changing markets, many designs never go
into production. Sometimes a company will develop competing projects, with only one moving to production. Many
times the market will change, or competition will emerge,
and projects will be cancelled or redirected. Of course
each design team expects that its project will succeed, but
in the aggregate this is not true. If a company chooses gate
arrays as the primary logic technology, and starts many
deSigns, this factor will occur.

However, contingencies also include positive events like
stocking for large, upside orders or where demand is difficult to estimate. This can be especially true during a
product's introduction, when design changes and demand
spikes occur simultaneously.

According to Dataquest ASIC and Standard Logic Semiconductor Volume 1,only 50% of gate-array designs go
into production. Therefore, the true cost of the gate array
should recognize additional costs for simulation, designing for testability, and NRE. For 2000 gates, using the
numbers in the Summary of Fixed Development Costs
section, this would mean an additional ($2,500 + 3 MW +
$15,000). For9000 gates the number is ($5,000 +8 MW +
$30,000).

With a custom product it is also necessary to build inventory as the product nears the end of its life cycle. Demand
is low and difficult to forecast, and it may not be possible
to reorder a small quantity. Spares and replacements
must be stocked. A JIT(just in time) inventory system is
less practical.
Since minimum manufacturing quantities for semiconductors are determined by wafer lots, a custom product will
have excess WIP (work in process) or finished goods inventory if the deSired order quantity is less than the mini-

100

'If.

80

8

60

()

w
>

~

•

o

Gate Array Incremental Cost

Simulation Cost + Time to Design for Testability + NRE Cost

GATE ARRAY (21')
FPGA (1.21')

40

w

a:

20
0

WAFER

DIE

ASSEMBLY

TEST

Figure 5. Relative Manufacturing CO!;t by Stage of Completion

1-17

1102 04A

II

A Cost of Ownership Comparison
Table 2 is a form that can be used for calculating the total
cost of ownership at various volumes. Table 2 points tothe
"break-even quantity"-the quantity where the unit cost of
the two devices is the same-of the next section.

COST OF OWNERSHIP ANALYSIS
While gate arrays have a lower unit cost, they have incremental fixed costs that must be incurred before the first unit
is received. Example costs are shown in Table 1 (Summary of Fixed Development Costs). Therefore, at lower
unit volumes the FPGA is less expensive, until the gate
array can amortize the up-front fixed costs.

Project Quantity

1,000

5,000

Gate Array-No second source
1. Fixed costs from Table 1
2. Unit cost
3. Inventory reserves: (Line 2)(1.1)
4. Total variable cost = (Line 3)(Oty)
5. Total cost = Line 1 + Line 4
6. Unit cost =Line 5/0ty
Gate Array-second source
7. Fixed costs from Table 1
8. Second source costs
9. Total fixed costs
10. Total variable cost-Line 4 above
11. Total cost = Line 9 + Line 10
12. Unit cost = Line 11/0ty

Field Programmable Gate Array
13. Unit cost

Table 2. Total Cost vs Volume Purchased

1-18

10,000

20,000

BREAK EVEN ANALYSIS

At the 2,000 gate level, assume the gate array is used in a
$2,000 product that has 15% profit margins. For 10,000
units sold:

Figure 6 is agraphic representation of the break-even
calculation for the case of 2000 gates, 1990 pricing, and
no second source. Up to the break-even unit volume,
the programmable gate array solution has a lower total
project cost.

Lost Profit = $2,000 x 10,000x 15%x 1/3= $1.0 million or
$100 per device

At the 9000 gate level, assume the gate array is used in a
$10,000 product that has 20% profit margins. For 2000
units sold:

Similar graphs can be built for different assumptions
by filling in Table 1. For the gate array, the break-even
graph is merely line 5 or line 11 plotted versus quantity.
For the FPGA it is line 13 times the quantity plotted
versus the quantity.

Lost Profit=$10,000x 2,000x 20%x 1/3=$1.33 million or
$667 per device

Note that these catastrophic costs are not included in any
of the previous sections. They are a quantitative estimate
of the risk of using a custom product.

TOTAL
PROJECT
COST ($)

PRODUCT LIFE CYCLES
Throughout the electronics industry, the product lifetimes
are shrinking. In the personal computer industry, it is not
uncommon to find product upgrades within 6 t012 months.
This means that the volumes associated with anyone
gate- array deSign can be much smaller than anticipated,
even if the end product still exists. It also means that it is
critical to achieve a rapid design time.

~:~6~~~~ }

NRE
SIMULATION TIME
DESIGNING TESTABILITY
TEST PROGRAM
DESIGN ITERATIONS

~--------~----------~10k

20k

PROJECT UN ITS

Figure 6 shows that 2000-gate FPGAs are more economical at volumes up to 10,000 to 20,000 units. These volumes will represent an increasing number of products.

- - - CUSTOM GATE ARRAY
-

FPGA
110205

REFERENCES

Figure 6. Typical Break-even Analysis 2000 Gates-1990
1. Technology Research Group Letter, March 1986,
page 7.

2. Dataquest Inc., Gate Arrays-Product AnalYSiS,
page 3, ASIC and Standard Logic Semiconductors,
1987.

TIME TO MARKET
There are numerous examples of products that failed due
to late market entry. A study by McKinsey & Co. stated that
a product that is six months late to market will miss out on
1/3 of the potential profit over the product lifetime. If there
is any problem in simulation, or any iteration of the gate
array design, a gate array would easily add six months to a
product schedule.

3. Reinertsen, Donald G.,'Whodunit? The Search forthe
New-Product Killers," Electronic Business, July 1983,
pages 62-66.

4. Integrated Circuit Engineering Corp., ASIC Outlook,
1987.

1-19

II

The Programmable Gate Array Company

1-20

SECTION 2
Product Specifications

1

2

Programmable Gate Arrays

Product Specifications

3

Quality, Testing, Packaging

4

Technical Support

5

Development Systems

6

Applications

7

Article Reprints

8

Index

Product Specifications

XC3000 Logic Cell Array Family
Features, Description, Architecture ............................................... 2-1
Programmable Interconnect .......................................................... 2-7
Crystal Oscillator ............................ ,............... '" ............................. 2-13
Programming ................................................................................. 2-14
Special Configuration Functions .................................................... 2-21
Performance .................................................................................. 2-24
Power ............................................................................................. 2-27
Pin Descriptions ............................................................................. 2-29
Pin Assignments ............................................................................ 2-32
Electrical Parameters ..................................................................... 2-40
PGA Pinouts and Physical Dimensions ......................................... 2-51
Component Selection and Ordering Information ........................... 2-60
XC2064, XC2018 Logic Cell Arrays
Features, Description, Architecture ............................................... 2-61
Programmable Interconnect .......................................................... 2-66
Crystal Oscillator ............................................................................ 2-68
Power ............................................................................................. 2-70
Programming ................................................................................. 2-72
Special Configuration Functions .................................................... 2-77
Performance .................................................................................. 2-78
Development Systems ................................................................... 2-84
Pin Descriptions ............................................................................. 2-84
Pin Assignments ............................................................................ 2-86
Electrical Parameters ..................................................................... 2-88
Component Selection, Ordering Information,
Physical Dimensions ................................................................ 2-98
Military Logic Cell Arrays
Introduction .................................................................................... 2-103
XC2018B ....................................................................................... 2-107
XC3020B ....................................................................................... 2-119
XC3042B ...................... ,................................................................ 2-137
XC3090B ....................................................................................... 2-157
Serial Configuration PROM
XC1736NXC1765 Features, Descriptions .................................... 2-175
Electrical Parameters '" .................................................................. 2-179
Serial-PROM-Programming Support ............................................. 2-184
Physical Dimensions, Ordering Information ................................... 2-185
Sockets ............................... ,............................................................... 2-187

XC3000
Logic CelfMArray Family
Product Specification
FEATURES

The LCA user logic functions and interconnections are
determined by the configuration program data stored in
internal static memory cells. The program can be loaded
in any of several modes to accommodate various system
requirements. The program data resides externally in an
EEPROM, EPROM or ROM on the application circuit
On-chip
board, or on a floppy disk or hard disk.
initialization logic provides for optional automatic loading
of program data at power-up. Xilinx's companion XC1736
Serial Configuration PROM provides a very simple serial
configuration program storage in a one-time
programmable 8-pin DIP.

• High Performance-70-, 100- and 125-MHz Toggle
Rates
• Second Generation Field-Programmable Gate Array
• 110 functions
• Digital logic functions
• Interconnections
• Flexible array architecture
• Compatible arrays, 2000 to 9000 gate
logic complexity
• Extensive register and I/O capabilities
• High fan-out signal distribution
• Internal 3-state bus capabilities
• TTL or CMOS input thresholds
• On-chip oscillator amplifier

Basic
Array

• Standard product availability
• Low-power, CMOS, static-memory technology
• Performance equivalent to TTL SSIIMSI
• 100% factory pre-tested
• Selectable configuration modes

XC3020
XC3030
XC3042
XC3064
XC3090

• Complete XACT"M development system
• Schematic Capture
• Automatic Place/Route
• Logic and Timing Simulation
• Design Editor
• Library and User Macros
• Timing Calculator
• XACTOR In-Circuit Verifier
• Standard PROM File Interface

Logic
Capacity
( gates)

2000
3000
4200
6400
9000

Configurable
Logic
Blocks

64
100
144
224
320

1I0s

No. Program
of
Data
Pads (bits)

64
80
96
120
144

74
98
118
140
166

Max

User

14,779
22,176
30,784
46,064
64,160

The XC3000 Logic Cell Arrays are an enhanced family of
Field Programmable Gate Arrays that provide a variety of
logic capacities, package styles, temperature ranges and
speed grades.

DESCRIPTION
ARCHITECTURE

The CMOS XC3000 Logic CeWM Array (LCNM) family
provides a group of high-performance, high-density,
digital integrated circuits. Their regular, extendable,
flexible, user-programmable array architecture is
composed of a configuration program store plus three
typesofconfigurable elements: a perimeter of lOBs, acore
array of CLBs and resources for interconnection. The
general structure of an LCA device is shown in Figure 1 on
the next page. The XACT development system provides
schematic capture and auto place-and-route for design
entry. Logic and timing simulation, and in-circuit emulation
are available as design verification alternatives. The
design editor is used for interactive design optimization,
and to compile the data pattern that represents the
configuration program.

The perimeter of configurable 1/0 Blocks (lOBs) provides
a programmable interface between the internal logic array
and the device package pins. The array of Configurable
Logic Blocks (CLBs) performs user-specified logic functions. The interconnect resources are programmed to
form networks, carrying logic signals among blocks,
analogous to printed circuit board traces connecting
MSI/SSI packages.
The blocks' logic functions are implemented by programmed look-up tables. Functional options are implemented by program-controlled multiplexers. Interconnecting networks between blocks are implemented with
metal segments joined by program-controlled pass tran-

2-1

XC3000 Logic Ceil Array Family

and only read during readback. During normal operation,
the cell provides continuous control and the pass transistor
is "off" and does not affect cell stability. This is quite
different from the operation of conventional memory devices, in which the cells are frequently read and re-written.

sistors. These LCA functions are established by a configuration program which is loaded into an internal, distributed
array of configuration memory cells. The configuration
program is loaded into the LCA device at power-up and
may be reloaded on command. The Logic Cell Array
includes logic and control signals to implement automatic
or passive configuration. Program data may be either bit
serial or byte parallel. The XACT development system
generates the configuration program bitstream used to
configure the Logic Cell Array. The memory loading
process is independent of the user logic functions.

a

The memory cell outputs Q and
use ground and Vcc
levels and provide continuous, direct control. The additional capacitive load together with the absence of address
decoding and sense amplifiers provide high stability to the
cell. Due to the structure of the configuration memory

Configuration Memory

r------iJ- Q

The static memory cell used for the configuration memory
in the Logic Cell Array has been designed specifically for
high reliability and noise immunity. Integrity of the LCA
configuration memory based on this design is assured
even under adverse conditions. Compared with other
programming alternatives, static memory provides the
best combination of high density, high performance, high
reliability and comprehensive testability. As shown in
Figure 2, the basic memory cell consists of two CMOS
inverters plus a pass transistor used for writing and reading cell data. The cell is only written during configuration

,.,

"J

1.:. .:.:.:.:.;.:.:.:

0

y-

CONFIGURABLE LOGIC
BLOCKS

~

y-

y-

t-

O

4.-

o

u
p

y-

110512

Figure 2. Static Configuration Memory Cell.
It is loaded with one bit of configuration program and
controls one program selection in the Logic Cell Array.

y----------------y-

y-

-L

DATA-!!

3-STATE BUFFERS WITH ACCESS
TO HORIZONTAL LONG LINES

o

:{-Q

READor~.:n
WRITE!

CONFIGURATION
_ CONTROL

o

y-

t-

Figure 1_ Logic Ceil Array Structure. It consists of a perimeter of programmable
I/O blocks, a core of configurable logic blocks and their interconnect resources.
These are all controlled by the distributed array of configuration program memory celis.

2-2

0

cells, they are not affected by extreme power-supply
excursions orvery high levels of alpha particle radiation. In
reliability testing, no soft errors have been observed even
in the presence of very high doses of alpha radiation.

1/0 Block
Each user-configurable lOB shown in Figure 3, provides
an interface between the external package pin of the
device and the internal user logic. Each lOB includes both
registered and direct input paths. Each lOB provides a
programmable 3-state output buffer, which may be driven
by a registered or direct output signal. Configuration
options allow each lOB an inversion, a controlled slew rate
and a high impedance pull-up. Each input circuit also
provides input clamping diodes to provide electro-static
protection, and circuits to inhibit latch-up produced by
input currents.

The method of loading the configuration data is selectable.
Two methods use serial data, while three use byte-wide
data. The internal configuration logic utilizes framing
information, embedded in the program data by the XACT
development system, to direct memory-cell loading. The
serial-data framing and length-count preamble provide
programming compatibility for mixes of various LCAs in a
synchronous, serial, daisy-chain fashion.

II

PROGRAM-CONTROLLED MEMORY CELLS

OUT
INVERT

OUTPUT
SELECT

3·STATE
INVERT

SLEW
RATE

PASSIVE
PULL UP

1/0 PAD

'-----+--------- (GLOBAL RESET)
CK1

=0-

PROGRAM
CONTROLLED
MULTIPLEXER

CK2

o = PROGRAMMABLE INTERCONNECTION POINT or PIP

Figure 3. Input/Output Block. Each lOB includes input and output storage elements and I/O options selected by
configuration memory cells. A choice of two clocks is available on each die edge. The polarity of each clock line (not
each flip-flop or latch) is programmable. A clock line that triggers the flip-flop on the rising edge is an active Low Latch
Enable (Latch transparent) signal and vice versa. Passive pull-up can only be enabled on inputs, not on outputs.
All user inputs are programmed for TIL or CMOS thresholds.

2-3

110501C

XC3000 Logic Cell Array Family
buller. The 3-state control signal [lOB pin .~ can control
output activity. An open-drain-type output may be obtained by using the same signal for driving the output and
3-state signal nets so that the buffer output is enabled only
for a Low.

The input buffer portion of each lOB provides threshold
detection to translate external signals applied to the
package pinto internal logic levels. The global input-buffer
threshold of the lOBs can be programmed to be
compatible with either TTL or CMOS levels. The buffered
input signal drives the data input of a storage element,
which maybe configured as either a flip-flop or a latch. The
clocking polarity (rising/falling edge-triggered flip-flop,
High/Low transparent latch) is programmable for each of
the two clock lines on each ofthe four die edges. Note that
a clock line driving a rising edge-triggered flip-flop makes
any latch driven by the same line on the same edge Lowlevel transparent and vice versa (falling edge, High
transparent). All Xilinx primitives in the supported
schematic-entry packages, however, are positive edgetriggered flip-flops or High transparent latches. When one
clock line must drive flip-flops as well as latches, it is
necessary to compensate for the difference in clocking
polarities with an additional inverter either in the flip-flop
clock input orthe latch-enable input. I/O storage elements
are reset during configuration or by the active-Low chip
RESET input. Both direct input [from lOB pin ./] and
registered input [from lOB pin .q] signals are available for
interconnect.

Configuration program bits for each lOB control features
such as optional output register, logical signal inverSion,
and 3-state and slew-rate control of the output.
The program-controlled memory cells of Figure 3 control
the following options:
• Logic Inversion of the output is controlled by one
configuration program bit per lOB.
• Logic 3-state control of each lOB output buller is
determined by the states of configuration program bits
which turn the buller on, or off, or select the output buffer
3-state control interconnection [lOB pin.f]. When this
lOB output control signal is High, a logic one, the buffer
is disabled and the package pin is high impedance.
When this lOB output control signal is Low, a logiC zero,
the buffer is enabled and the package pin is active.
Inversion of the buffer 3-state control logic sense (output
enable) is controlled by an additional configuration
program bit.

For reliable operation, inputs should have transition times
of less than 100 ns and should not be left floating. Floating
CMOS input-pin circuits might be at threshold and produce
oscillations. This can produce additional power dissipation and system noise. A typical hysteresis of about
300 mV reduces sensitivity to input noise. Each user lOB
includes a programmable high-impedance pull-up resistor, which may be selected by the program to provide a
constant High for otherwise undriven package pins. Although the Logic Cell Array provides circuitry to provide
input protection for electrostatic discharge, normal CMOS
handling precautions should be observed.

• Direct or registered output is selectable for each lOB.
The register uses a positive-edge, clocked flip-flop. The
clock source may be supplied [lOB pin .ok] by either of
two metal lines available along each die edge. Each of
these lines is driven by an invertible buffer.
• Increased output transition speed can be selected to
improve critical timing. Slower transitions reduce
capacitive-load peak currents of non-critical outputs and
minimize system noise.

Flip-flop loop delays for the lOB and logic-block flip-flops
are about 3 ns. This short delay provides good performance under asynchronous clock and data conditions.
Short loop delays minimize the probability of a metastable
condition that can result from assertion of the clock during
data transitions. Because of the short-loop-delay characteristic in the Logic Cell Array, the lOB flip-flops can be
used to synchronize external signals applied to the device.
Once synchronized in the lOB, the signals can be used
internally without further consideration of their clock relative timing, except as it applies to the internal logic and
routing-path delays.

• A high-impedance pull-up resistor may be used to
prevent unused inputs from floating.
Summary of 1/0 Options
• Inputs
• Direct
• Flip-flop/latch
• CMOS/TIL threshold (chip inputs)
• Pull-up resistor/open circuit
• Outputs
• Direct/registered
• Inverted/not
• 3-state/on/off
• Full speed/slew limited
• 3-state/output enable (inverse)

lOB output buffers provide CMOS-compatible 4-mA
source-or-sink drive for high fan-out CMOS or TILcompatible signal levels. The network driving lOB pin .0
becomes the registered ordirect data source forthe output

2-4

~XlUNX
Configurable Logic Block

Each configurable logic block has a combinatorial logic
section, two flip-flops, and an internal control section. See
Figure 4. There are: five logic inputs [.a, .b, .C, .dand .e];
a common clock input [.k); an asynchronous direct reset
input [.rdJ; and an enable clock [. ec]. All may be driven from
the interconnect resources adjacent to the blocks. Each
CLB also has two outputs [.x and .YJ which may drive interconnect networks.

The array of Configurable Logic Blocks (CLBs) provides
the functional elements from which the user's logic is
constructed. The logic blocks are arranged in a matrix
within the perimeter of lOBs. The XC3020 has 64 such
blocks arranged in 8 rows and 8 columns. The XACT
development system is used to compile the configuration
data which are to be loaded into the internal configuration
memory to define the operation and interconnection of
each block. User definition of configurable logic blocks
and their interconnecting networks may be done byautomatic translation from a schematic capture logic diagram
or optionally by installing library or user macros.

DATA IN

Data input for either flip-flop within a CLB is supplied from
the function F orG outputs of the combinatorial logic, or the
block input, data-in [.d/]. Both flip-flops in each CLB share
the asynchronous reset [.rdj which, when enabled and
High, is dominant over clocked inputs. All flip-flops are

-i....:.:.d::,.i- - - - - - - - - - - ,

.a
.b

ox

F14+....-11------+-+---...11----1

VAR~~~~ -f~--:.:1:~;------fCo~~~~g~IAL
.e
G~+~~-----+-+----~

.x
CLBOUTPUTS

oy

ENABLECLOCK-f-·"'ec><-------------_i
"1" (ENABLE) - - - - - - I

CLOCK-t~·~k----------~
RESET
DIRECT

-t~.""rd"--

_ _ _ _ _ _ _ _ _ _ _ __i

1105 02A

Figure 4. Configurable Logic Block. Each CLB includes a combinatorial logic section.
two flip-flops and a program memory controlled multiplexer selection of function.
It has: five logic variable inputs .a, .b, .c, .d and .e.
a direct data in .di
an enable clock .ec
a clock (invertible) .k
an asynchronous reset .rd
two outputs .x and .y

2-5

XC3000 Logic Cell Array Family

;....,...... ..............., ...................,...,.......,........................'....,......',... .......... .........:!
~

g::===:::!::~
E

ANY FUNCTION
OF UPTO 4
VARIABLES

F

COUNTENABLE==1lrFr~~~~~~t=)-------

PARALLEL ENABLE
CLOCK

-',------------1/

~

i___

___,TCEORUMNITNAL

DUAL FUNCTION OF 4 VARIABLES

~=~===========t~-r--------~
....,..-------1

DO~F====~

OX

g::===:::!::~

,~

ANY FUNCTION
OF UPTO 4
VARIABLES

G

E-'i-------j,.)

5a

00

FG

FG

MODE

MODE

A-'~--------------~
B

"""', 'ox
O:(::::;:::======f1

F

01

ANY FUNCTION
OF 5 VARIABLES

G

5b

F

FUNCTION OF 5 VARIABLES

MODE

F
MODE

02

FUNCTION OF 6 VARIABLES

FGM
MODE
110503A

Figure 6. C8BCP Macro. TheC8BCP macro (moduI0-8
binary counter with parallel enable and clock enable) uses
one combinatorial logic block of each option.

Figure 5

Sa. Combinatorial Logic Option FG generates two functions of
four variables each. One variable, A, must be common to
both functions. The second and third variable can be any
choice of of B, C, Ox and Oy. The fourth variable can be
any choice of D or E.

5b. Combinatorial Logic Option F generates any function of five
variables: A, D, E and and two choices out of B, C, Ox, Oy.

5c. Combinatorial Logic Option FGM allows variable E to select
between two functions of four variables: Both have common
inputs A and D and any choice out of B, C, Ox and Oy forthe
remaining two variables. Option 3 can then implement some
functions of six or seven variables.

2-6

(as are block outputs) they are usable only for block
Input connection and not routing. Figure 8 illustrates

reset by the active Low chip input, RESET, or during the
configuration process. The flip-flops share the enable
clock [.ee] which, when Low, recirculates the flip-flops'
present states and inhibits response to the data-in or
combinatorial function inputs on a CLB. The user may
enable these control inputs and select their sources. The
user may also select the clock net input [.k], as well as its
active sense within each logic block. This programmable
inversion eliminates the need to route both phases of a
clock signal throughout the device. Flexible routing allows
use of common or individual CLB clocking.

routing access to logic block input variables, control inputs
and block outputs. Three types of metal resources are
provided to accommodate various network interconnect
requirements:
• General Purpose Interconnect
• Direct Connection
• Long Lines (multiplexed busses and wide AND gates)
General Purpose Interconnect

The combinatorial-logic portion of the logic block uses a 32
by 1 look-up table to implement Boolean functions. Variables selected from the five logic inputs and two internal
block flip-flops are used as table address inputs. The
combinatorial propagation delay through the network is
independent of the logic function generated and is spike
free for single input variable changes. This technique can
generate two independent logic functions of up to four
variables each as shown in Figure 5a, or a single function
of five variables as shown in Figure 5b, or some functions
of seven variables as shown in Figure 5c. Figure 6 shows
a modulo 8 binary counter with parallel enable. It uses one
CLB of each type. The partial functions of six or seven
variables are implemented using the input variable [.e] to
dynamically select between two functions of four different
variables. Forthe two functions of four variables each, the
independent results (F and G) may be used as data inputs
to either flip-flop or either logic block output. For the single
function of five variables and merged functions of six or
seven variables, the F and G outputs are identical. Symmetry of the F and G functions and the flip-flops allows the
interchange of CLB outputs to optimize routing efficiencies
of the networks interconnecting the logic blocks and lOBs.

General purpose interconnect, as shown in Figure 9,
consists of a grid of five horizontal and five vertical metal
segments located between the rows and columns of logic
and lOBs. Each segment is the "height" or ''width'' of a logic
block. Switching matrices join the ends of these segments
and allow programmed interconnections between the
metal grid segments of adjoining rows and columns. The
switches of an unprogrammed device are all nonconducting. The connections through the switch matrix
may be established by the automatic routing or by using
Editnet to select the desired pairs of matrix pins to be
connected or disconnected. The legitimate switching
matrix combinations for each pin are indicated in Figure 10
and may be highlighted by the use of the Show-Matrix
command in XACT.
INTERCONNECT
"PIPs"

SWITCHING
MATRIX

. .....
/: . t-· .:.
1
.: ¥ - . .

0,::,',:,::0
.. . :

~-

...

PROGRAMMABLE INTERCONNECT
Programmable-interconnection resources in the Logic
Cell Array provide routing paths to connect inputs and
outputs of the 1/0 and logic blocks into logic networks.
Interconnections between blocks are composed from a
two-layer grid of metal segments. Specially designed pass
transistors, each controlled by a configuration bit, form
programmable interconnect points (PIPs) and switching
matrices used to implement the necessary connections
between selected metal segments and block pins. Figure
7 is an example of a routed net. The XACT development
system provides automatic routing of these interconnections. Interactive routing (Editnet) is also available for
design optimization. The inputs of the logic or lOBs are
multiplexers which can be programmed to select an input
network from the adjacent interconnect segments. As the

t-· :

····:·:0
.
..

....
:

t ~.:':
CONFIGURABLE
LOGIC BLOCK

~-

'

4.: .:
INTERCONNECT
BUFFER

X119i

Figure i'. An XACT view of routing resources used to form a
typical interconnection network from CLB GA.

switch connections to block inputs are unidirectional

2-7

•

XC3000 Logic Cell Array Family

····5

t·.; .:

'::El .:

.' t- ...

0··:·····
.. '

~

t-·.:

.

0·:.· : 0:.'
...

-4-.~.~~

.. +-'

~-

': . {5 ·~I
'::·15. tt·.;.
t·.; .: .' r··.
. t-·.; .
0'".. ··0:····:·:0·
. ~O·
~
.. +.. , ..! I· ..,. . \"
.. +-'
.., ..
"-:-:-----:-rl:

CLB CONTROL INPUTS

CLB LOGIC INPUTS

CLB X OUTPUT

CLB Y OUTPUT

'\' O'
0.': . ·· .'.... 0" : \'". -4-0"
.': . : .
eo

• • • .::--

"0 :" • • .:: •• :

:

~-

-0. :" ••• :. ••

:

~":'

: :

t- . ..

0:·
...

~-

: :

:

~-":'

:

:0'.

.. .
..

t·

'::0

~

:

:

•••

..

~.

: :

.... :

r'

0':·

.. -4-

'::·0

: :

:

t- . ..

.
.
:0'
...
~-

'::El

:

..

:

:

Figure 8. XACT Development System Locations of interconnect
access, CLB control inputs, logic inputs and outputs. The dot pattern
represents the available programmable interconnection points (PIPs).
Some of the interconnect PIPs are directional. This is indicated on the XACT design editor status line:
NO is a nondirectional interconnection.
D:H->V is a PIP which drives from a horizontal to a vertical line.
D:V->H is a PIP which drives from a vertical to a horizontal line.
O:C-> T is a "T' PIP which drives from a cross of a T to the tail.
D:CW is a corner PIP which drives in the clockwise direction.
PO indicates the PIP is non-conducting, P1 is "on."

2-8

~.

X1198

--------~-

--~~-.-

E:XiUl\lX
Special buffers within the general interconnect areas provide periodic signal isolation and restoration for improved
performance of lengthy nets. The interconnect buffers are
available to propagate signals in either direction on a given
general interconnect segment. These bidirectional (bid i)
buffers are found adjacent to the switching matrices,
above and to the right and may be highlighted by the use
of the "Show BIOI" command in XACT. The other PIPs
adjacent to the matrices are access to or from long lines.
The development system automatically defines the buffer
direction based on the location of the interconnection
network source. The delay calculator of the XACT development system automatically calculates and displays the
block, interconnect and buffer delays for any paths selected. Generation of the simulation netlist with a worstcase delay model is provided by an XACT option.

interconnect to drive the .d input of the block immediately
above and the .a input of the block below. Direct intercon-

r

~~~
gz~ ~~ ~~ ~= ~~
~~~~~
~~ ~ ~~
6
~

2

3

4

5

6

7

8

9

10

11

12

13

14

15

1

Direct Interconnect
Direct interconnect, shown in Figure 11 , provides the most
efficient implementation of networks between adjacent
logic or I/O Blocks. Signals routed from block to block
using the direct interconnect exhibit minimum interconnect
propagation and use no general interconnect resources.
For each CLB, the .x output may be connected directly to
the .b input of the CLB immediately to its right and to the .c
input of the CLB to its left. The .youtput can use direct

II

16

e
III

I

17

18

19

20

110513

Figure 10. Switch Matrix Interconnection Options
for Each Pin. Switch matrices on the edges are different.
Use Show Matrix menu option in XACT

.. .. EJA :.:-:
.. ..

·:.-El
0 ······

t·

r·.; .: .' t
..
. . ......
...

.. . :

'. ··El
'.

t·

. t·.; .

'\ .

:

SWITCHING
MATRIX

'.
GRID OF GENERAL INTERCONNECT
METAL SEGMENTS

~

'

: :

Figure 9. LCA General-Purpose Interconnect.
Composed of a grid of metal segments which may be
interconnected through switch matrices to form networks
for CLB and lOB inputs and outputs.

t

~

~

. ..

a,.:

·:.-El

r·.;

: 0-: :-.'::.:
...
"'0"
..

,.. ....
......

:::~.~~a~··

:

.. ' :

: :
:

:

l:

El

Figure 11. CLB.X and.V Outputs. The.x and.y
outputs of each CLB have single contact, direct
access to inputs of adjacent CLBs.

2-9

~

X1198

II

XC3000 Logic Cell Array Family
GLOBAL BUFFER DIRECT INPUT

GLOBAL BUFFER INTERCONNECT

'UNBONDED lOBs (6 PLACES)

ALTERNATE BUFFER DIRECT INPUT

Figure 12. X3020 Die-Edge lOBs. The X3020 die-edge lOBs are provided with direct access to adjacent CLBs.

2-10

X1200

nect should be used to maximize the speed of highperformance portions of logic. Where logic blocks are
adjacent to lOBs, direct connect is provided alternately to
the lOB inputs [./] and outputs [.0] on all four edges of the
die. The right edge provides additional direct connects
from CLB outputs to adjacent lOBs. Direct interconnections of lOBs with CLBs are shown in Figure 12.

A buffer in the upper left corner of the LCA chip drives a
global net which is available to all .k inputs of logic blocks.
Using the global buffer for a clock signal provides a skewfree, high fan-out, synchronized clock for use at any or all
of the I/O and logic blocks. Configuration bits for the .k
input to each logic block can select this global line or
another routing resource as the clock source for its flipflops. This net may also be programmed to drive the die
edge clock lines for lOB use. An enhanced speed, CMOS
threshold, direct access to this buffer is available at the
second pad from the top of the left die edge.

Long Lines
The long lines bypass the switch matrices and are intended primarily for signals that must travel a long distance, or must have minimum skew among multiple destinations. Long lines, shown in Figure 13, run vertically and
horizontally the height or width of the interconnect area.
Each interconnection column has three vertical long lines,
and each interconnection row has two horizontal long
lines. Two additional long lines are located adjacent to the
outer sets of switching matrices. In devices larger than the
XC3020, two vertical long lines in each column are connectable half-length lines. On the XC3020, only the outer
long lines are connectable half-length lines.

A buffer in the lower right corner of the array drives a
horizontal long line that can drive programmed connections to a vertical long line in each interconnection column.
This alternate buffer also has low skew and high fan-out.
The network formed by this alternate buffer's long lines
can be selected to drive the .k inputs of the logic blocks.
CMOS threshold, high speed access to this buffer is
available from the third pad from the bottom of the right die
edge.

Long lines canbe driven by a logic block or lOB output on
a cOlumn-by-column basis. This capability provides a
common low skew control or clock line within each column
of logic blocks. Interconnections of these long lines are
shown in Figure 14. Isolation buffers are provided at each
input to a long line and are enabled automatically by the
development system when a connection is made.

A pair of 3-state buffers, located adjacent to each CLB,
permits logic to drive the horizontal long lines. Logic
operation of the 3-state buffer controls allows them to
implement wide multiplexing functions. Any 3-state buffer
input can be selected as drive for the horizontal long-line
bus by applying a Low logic level on its 3-state control line.
See Figure 1Sa. The user is required to avoid contention

Internal Busses

3 VERTICAL LONG LINES

t:tJ

GLOBAL

BUFFER~"
:" .••
:.::
. .' .
.:.:
. ...
..
•

•

•• '

•

•

0 ':'..tJ:. :b:.::0' ,:",:b.. :b"'.
:.:0 b tJ:.:0.
. .. 0...
..

.C"i."
. . .1 : .

. . . 1...

•

II

•

II

•

::g.;.:;: ':. ~:. :::., : . ::.:: . :':' : . :;::~: . :':' : . :;.:~.' .:.: ;.:~.
Il
•

't".....
•

II

•••

ON-CHIP
3-STATE
BUFFERS

:

.

r.:··

. 't.:"

. . . .::.~ : .;: .'::0 .':'

.....
....

I"

"

PULL-UP
:
RESISTORS<
FOR ON-CHIP
OPEN DRAIN
SIGNALS
~~~------~~-'~~--------~~~-------r~~--~----~~

::0 .

..

:

..~
6 ...
.':':
.! :

p

r·.;

e; .'. . .

2 HORIZONTAL LONG LINES

. I.
'. .. EJA :-:':
....

'::'

....:.

. ...'E1c .'::
.....
•

I":'

. 1-'.; .: .' t-·.:

.t- .;

.j8q .... :

W.·.·
. . t..:

X1243

Figure 13. Horizontal and Vertical Long Lines. These long lines provide high fan-out, low-skew signal distribution in
each row and column. The global buffer in the upper left die corner drives a common line throughout the LeA.

2-11

II

XC3000 Logic Cell Array Family

15b. Pull-up resistors are available at each end of the long
line to provide a High output when all connected buffers
are non-conducting. This forms fast, wide gating functions. When data drives the inputs, and separate signals
drive the 3-state control lines, these buffers form multiplexers (3-state busses). In this case, care must be used

which can result from multiple drivers with opposing logic
levels. Control of the 3-state input by the same signal that
drives the buffer input, creates an open-drain wired-AND
function. A logic High on both buffer inputs creates a high
impedance, which represents no contention. A logic Low
enables the buffer to drive the long line Low. See Figure

• FOUR OUTER LONG LINES ARE
CONNECTABLE H~LF-LENGTH LINES

EO
o ...
'-:1' .:' .:.:
.' ...:'- :.::
"

...-1/0 BLOCK CLOCK NETS

DO
00
~fo. DO
DC
r - l .: .:.. : :':11:- .: .: .. : :':;-'1 .: : ;
.:.:.. : :':11:- .: .: .. : :.:
LJ... ····· .. ~LJ._:.......;·LJ·.. · ....
.......... ·lJ···· ... "

(2PERDIEEDGE)

f

eJ'.,
O0
......

. ..':

(""j .. . ' .. [~): . . ' .. r \ . . . ' .. (""j ..

.. .

,::. :::::::: .. LJ:·: ,'::":

..

..

',: .-::-': LJ',: ..::.. : LJ:·:

t·

.

.

.

f·

•

4
X1244

Figure 14. Programmable Interconnection of Long Lines. This is provided at the edges of the routing area. Three-state
buffers allow the use of horizontal long lines to form on-chip wired-AND and multiplexed buses. The left two vertical long
lines per column (except 3020) and the outer perimeter long lines may be programmed as connectible half-length.

--../\I'wr-D-A-lP---,--D-e-lP---,--D-c-lP---,----(lD-~W-~-:--....---.,.oNv110504

Figure 15a.

3·State Buffers Implement a Wlred·AND Function. When all the buffer
3-state lines are High, (high impedance), the pull-up resistor(s) provide the
High output. The buffer inputs are driven by the control signals or a Low.

I if"!: if"I
T

Of

Z = DA'A +De'8 +Dc·O+ ... +DN'N

"05 04A

Figure 15b. 3·State Buffers Implement a Multlplexer_
The selection is accomplished by the buffer 3-state signal.

2-12

circuit becomes active before configuration is complete in
order to allow the oscillator to stabilize. Actual internal
connection is delayed until completion of configuration. In
Figure 17 the feedback resistor R1, between the output
and input, biases the amplifier at threshold. The value
should be as large as practical to minimize loading of the
crystal. The inversion of the amplifier, together with the
R-C networks and an AT-cut series resonant crystal,
produce the 360-degree phase shift of the Pierce oscillator. A series resistor R2 may be included to add to the
amplifier output impedance when needed for phase-shift
control, crystal resistance matching, orto limitthe amplifier
input swing to control clipping at large amplitudes. Excess
feedback voltage may be corrected by the ratio of C2/C1.
The amplifier is designed to be used from 1 MHz to one-

to prevent contention through multiple active buffers of
conflicting levels on a common line. Figure 16 shows
3-state buffers, long lines and pull-up resistors.
CRYSTAL OSCILLATOR
Figure 16 also shows the location of an internal high speed
inverting amplifierwhich may be used to implement an onchip crystal oscillator. It is associated with the auxiliary
buffer in the lower right corner of the die. When the
oscillator is configured by MAKEBITS and connected as a
signal source, two special user lOBs are also configured to
connect the oscillator amplifier with external crystal oscillatorcomponents as shown in Figure 17. A divide by two
option is available to assure symmetry. The oscillator
BIDIRECTIONAL
INTERCONNECT
BUFFERS

GLOBAL NET"

3 VERTICAL LONG
LINES PER COLUMN

/
.,....."

111
--J

1

-

t\1

+

i!10

A

I

1'llH-1

r

I

~

J

'-n-

~~.~

'-nA

L

~

~'

.0 '.

r

~ I'

~eJ

--

ti

EJeJl

E:J

'I

OSCILLATOR
AMPLIFIER OUTPUT

DIRECTINPUT OF P47
TO AUXILIARY BUFFE R

V
VI

CRYSTAL OSCILLATOR
BUFFER

~3-STATE INPUT

~

000 []
00

11

HORIZONTAL LONG LINE

3-STATE CONTROL
3-STATE BUFFER

.q.ak .

~-.....;

00

~

P

I-

HORIZONTAL LONG LINE

,/" PULL-UP RESISTOR

,/

I

W'-

-

IE¥"
ffi

I
I
I

-:~O

1

r:-

~

- -

I

-dJ Y

~u.

JO

II

IGH
.I

~
Y\,\.

-

-:-

II I

I

JI '""

r - ALTERNATE BUFFER

\ OSCILLATOR
AMPLIFIE R INPUT

Figure 16. XACT Development System. An extra large view of possible
interconnections in the lower right corner of the XC3020.

2-13

II

110 CLOCKS

X1245

XC3000 Logic Cell Array Family
half the specified CLB toggle frequency. Use at frequencies below 1 MHz may require individual characterization
with respect to a series resistance. Crystal oscillators
above 20 MHz generally require a crystal which operates
in a third overtone mode, where the fundamental frequency must be suppressed by the R-C networks. When
the oscillator inverter is not used, these lOBs and their
package pins are available for general user I/O.

ture and power supply. As shown in Table 1, five configuration mode choices are available as determined by the
input levels of three mode pins; MO, M1 and M2.
In Master configuration modes, the LCA device becomes
the source of the Configuration Clock (CCLK). The beginning of configuration of devices using Peripheral or Slave
modes must be delayed long enough for their initialization
to be completed. An LCA with mode lines selecting a
Master configuration mode extends its initialization state
using four times the delay (43 to 130 ms) to assure that all
daisy-chained slave devices, which it may be driving, will
be ready even if the master is very fast, and the slave(s)

PROGRAMMING
Initialization Phase

Table 1

An internal power-on-reset circuit is triggered when power
is applied. When Vee reaches the voltage at which
portions of the LCA begin to operate (nominally 2.5 to 3 V),
the programmable I/O output buffers are disabled and a
high-impedance pull-up resistor is provided for the user
110 pins. A time-out delay is initiated to allow the power
supply voltage to stabilize. During this time the powerdown mode is inhibited. The Initialization state time-out
(about 11 to 33 ms) is determined by a 14-bit counter
driven by a self-generated internal timer. This nominal
1-MHztimeris subject to variations with process, tempera-

MO M1 M2 Clock
0
0
0
0

0
0

1

0
0

1

Mode

active
active

Master
Master
reserved
0
1 active Master
0
reserved
1 passive Peripheral
0
reserved
passive Slave

0

Data
Bit Serial
Byte Wide Addr.

= 0000

Byte Wide Addr.

=

up

FFFF down

Byte Wide
Bit Serial

INTERNAL'! EXTERNAL

ALTERNATE
CLOCK BUFFER

I

XTAL1

D
D
SUGGESTED COMPONENT VALUES
R1 0.5-1 Mn
R2 0-1 kn
(may be required for low frequency, phase
shift andlor compensation level for crystal Q)
C1,C210-40pF
Y1 1 - 20 MHz AT·cut series resonant

IXTAL 1 (OUT)
L XTAL 2 (IN)

44 PIN
PLCC
30
26

68 PIN
PLCC
47
43

84 PIN
PLCC PGA
57
J11
53 I L11

R2

I

C1

100 PIN
PQFP
CQFP
67
82
61
I 76

132 PIN
PGA
P13
M13

160 PIN
PQFP
82
76

164 PIN
CQFP
105
99

175 PIN
PGA
T14
P15

Figure 17. Crystal Oscillator Inverter. When activated in the MAKEBITS program and by selecting an output network
for its buffer, the crystal oscillator inverter uses two unconfigured package pins and external components to
implement an oscillator. An optional divide-by-two mode is available to assure symmetry.

2-14

1105t4C

configuration program(s). The data framing is shown in
Figure 19. All LCAs connected in series read and shift
preamble and length count in on positive and out on
negative configuration clock edges. An LCA which has
received the preamble and length count then presents a
High Data Out until it has intercepted the appropriate
number of data frames. When the configuration program
memory of an LCA is full and the length count does not
compare, the LCA shifts any additional data through, as it
did for preamble and length count.

very slow. Figure 18 shows the state sequences. At the
end of Initialization the LCA enters the Clear state where
it clears the configuration memory. The active Low, opendrain initialization signal INIT indicates when the Initialization and Clear states are complete. The LCA tests for
the absence of an external active Low RESET before it
makes a final sample of the mode lines and enters the
Configuration state. An external wired-AND of one or
more INIT pins can be used to control configuration by the
assertion of the active low RESET of a master mode device or to signal a processor that the LCAs are not yet
initialized.

When the LCA configuration memory is full and the length
count compares, the LCA will execute a synchronous
start-up sequence and become operational. See
Figure 20. Three CCLK cycles after the completion of
loading configuration data the user I/O pins are enabled as
configured. As selected in MAKEBITS, the internal userlogic reset is released either one clock cycle before or after
the I/O pins become active. A similar timing selection is
programmable for the DONE/PROG output Signal.
DONEIPROG may also be programmed to be an open
drain or include a pull-up resistor to accommodate wired
ANDing. The High During Configuration (HDC) and Low
During Configuration (LDC) are two user I/O pins which
are driven active when an LCA is in its Initialization, Clear
or Configure states. They and DONE/PROG provide
signals for control of external logic signals such as reset,
bus enable or PROM enable during configuration. For
parallel Masterconfiguration modes these signals provide
PROM enable control and allow the data pins to be shared
with user logic signals.

If a configuration has begun, a re-assertion of RESET for
a minimum of three internal timer cycles will be recognized
and the LCA will initiate an abort, returning to the Clear
state to clear the partially loaded configuration memory
words. The LCA will then re-sample RESET and the mode
lines before re-entering the Configuration state. A reprogram is initiated when a configured LCA senses a High
to Low transition on the DONE/PROG package pin. The
LCA returns to the Clear state where the configuration
memory is cleared and mode lines re-sampled, as for an
aborted configuration. The complete configuration program is cleared and loaded during each configuration
program cycle.
Length count control allows a system of multiple Logic Cell
Arrays, of assorted sizes, to begin operation in a synchronized fashion. The configuration program generated by
the MakePROM program of the XACT development system begins with a preamble of 111111110010 followed by
a 24-bit 'length count' representing the total number of
configuration clocks needed to complete loading of the

User I/O inputs can be programmed to be either TIL or
CMOS compatible thresholds. At power-up, all inputs

POWER-ON DELAY IS

~:: g~gt~~ ~g~ ~~~fE~SJ6~~~Ero1 i3~om~3 ms
USER VO PINS WITH HI<;lH IMPEDANCE PULL·UP
INIT SIGNAL ~OW (XC3000)

HOC = HIGH
LDC=LOW

ACTIVE
/'P""'O"'WE=R."""D""'OW"'N"I

LOW ON DONE/PROGRAM AND RESET
CLEAR IS
-200 CYCLES FOR THE
-250 CYCLES FOR THE
-290 CYCLES FOR THE
-330 CYCLES FOR THE
-375 CYCLES FOR THE

XC3020-130 TO
XC3030-165 TO
XC3042-195TO
XC3064-220 TO
XC3090-250 TO

400 I's
500 I's
580 I'S
660 I's
750 I'S

110515A

Figure 18. A State Diagram of the Configuration Process for Power-up and Reprogram.

2-15

II

XC3000 Logic Cell Array Family

have TIL thresholds and can change to CMOS thresholds
at the completion of configuration if the user has selected
CMOS thresholds. The threshold of PWRDWN and the
direct clock inputs are fixed at a CMOS level.

Configuration Data
Configuration data to define the function and interconnection within a Logic Cell Array are loaded from an external
storage at power-up and on a re-program signal. Several
methods of automatic and controlled loading of the required data are available. Logic levels applied to mode

If the crystal oscillator is used, it will begin operation before
configuration is complete to allow time for stabilization
before it is connected to the internal circuitry.

11111111
0010
< 24·BIT LENGTH COUNT>
1111

-

DUMMY BITS·
PREAMBLE CODE
CONFIGURATION PROGRAM LENGTH
DUMMY BITS (4 BITS MINIMUM)

o < DATA FRAME #001 > 111
o < DATA FRAME #002 > 111
0< DATA FRAME #003 > 111

o < DATA FRAME#196>
o < DATA FRAME#197 >

]

HEADER

FOR XC3020

1

111
111

1111

197 CONFIGURATION DATA FRAMES

PROGRAM DATA

(EACH FRAME CONSISTS OF:
A START BIT (0)
A 71-BIT DATA FIELD
THREE STOP BITS

REPEATED FOR EACH LOGIC
CELL ARRAY IN A DAISY CHAIN

POSTAMBLE CODE (4 BITS MINIMUM)

-THE LCA DEVICES REQUIRE FOUR DUMMY BITS MIN; XACT 2.10 GENERATES EIGHT DUMMY BITS

Device

XC3020

Gates

2000

CLBs

64
(8 x 8)

11050SA

XC3030

XC3042

3000

4200

100
(10 x 10)

144
(12 x 12)

224
(16 x 14)

320
(20 x 16)

64

80

96

120

144

256

360

480

688

928

Horizontal Long Lines

16

20

24

32

40

TBUFsIHorizontal LL

9

11

13

15

17

92

108

140

172

197

241

285

329

373

14779
Program Data =
Bits x Frames + 4 bits
(excludes header)

22176

30784

46064

64160

22216

30824

46104

64200

RDWX Col

lOBs
Flip-flops

Bits per Frame
75
(including1 start and 3 stop bits)
Frames

PROM size (bits)
Program Data
+ 40-bit Header

=

14819

XC3064
6400

XC3090
9000

Figure 19_ Internal Configuration Data Structure for an LCA. This shows the preamble, length count
and data frames which are generated by the XACT Development System.
The Length Count produced by the MAKEBIT program = [(40-bit preamble + sum of program data + 1 per daisy chain device)
rounded up to multiple of 8]- (2 :5: K :5: 4) where K is a function of DONE and RESET timing selected. An additional 8 is added
if roundup increment is less than K. K additional clocks are needed to complete start-up after length count is reached.

2-16

E:XIUNX
selection pins at the start of configuration time determine
the method to be used. See Table 1. The data may be
either bit-serial or byte-parallel, depending on the configuration mode. Various Xilinx Field Programmable Gate
Arrays have different sizes and numbers of data frames.
To maintain compatibility between various device types,
the Xilinx 2000 and 3000 product families use compatible
configuration formats. For the XC3020, configuration
requires 14779 bits for each device, arranged in 197 data
frames. An additional 40 bits are used in the header. See
Figure 20. The specific data format for each device is
produced by the MAKEBITS command of the development system and one or more of these files can then be
combined and appended to a length count preamble and
be transformed into a PROM format file by the 'MAKE
PROM' command of the XACT development system. A
compatibility exception precludes the use of a 2000-series
device as the master for 3000-series devices if their DONE
or RESET are programmed to occur after their outputs
become active. The "tie"option olthe MAKEBITS program
defines output levels of unused blocks of a design and
connects these to unused routing resources. This prevents indeterminate levels that might produce parasitic

supply currents. If unused blocks are not sufficient to
complete the 'tie,' the FLAGNET command of EDITLCA
can be used to indicate nets which must not be used to
drive the remaining unused routing, as that might affect
timing of user nets. NORESTORE will retain the results of
TIE for timing analysis with QUERYNET before RESTORE returns the design to the untied condition. TI E can
be omitted for quick breadboard iterations where a few
additional milliamps of Icc are acceptable.
The configuration bitstream begins with High preamble
bits, a 4-bit preamble code and a 24-bit length count.
When configuration is initiated, a counter in the LCA is set
to zero and begins to count the total number of configuration clock cycles applied to the device. As each configuration data frame is supplied to the LCA, it is internally
assembled into a data. word. As each data word is
completely assembled, it is loaded in parallel into one word
of the internal configuration memory array. The configuration loading process is complete when the current length
count equals the loaded length count and the required
configuration program data frames have been written.
Internal user flip-flops are held reset during configuration.

r"J J' bYGI---:

POSTAMBLE

""'-;-'t.:....-..;-,1rr--

IPREAMBLE I LENGTH COUNT I

If

DATA

I ItI

START

-

j4 j

I I

J3

LENG THCOUNT'
START

nJlu..-1_---'

WEAK PULL·UP

110 ACTIVE

HIGH

DOUT LEAD DEVICE

1/2 CLOCK CYCLE
DELAY FROM DATA INPUT

PifciGRAM

IV

INTERNAL RESET \

* The configuration data consists of a composite

40-bit preamble/length count, followed by one or
more concatenated LeA programs, separated by
4-bit postambles. An additional final postamble bit
is added for each slave device and the result rounded
up to a byte boundary. The length count is two less
than the number of resulting bits.

~

Timing of the assertion of DONE and
termination of the INTERNAL RESET
may each be programmed to occur
one cycle before or after the I/O outputs
become active.

Figure 20. Configuration and Start-up of One or More LCAs.

2-17

DONE

1105 068

II

XC3000 Logic Cell Array Family

portions of the system. The state diagram of Figure 18
illustrates the configuration process.

Two user-programmable pins are defined in the unconfigured Logic Ceil array. High During Configuration (HDC)
and Low During Configuration (LDC) as weil as
DONEIPROG may be used as external control signals
during configuration. In Master mode configurations it is
convenient to use LDC as an active-Low EPROM Chip
Enable. After the last configuration data bit is loaded and
the length count compares, the user 1/0 pins become
active. Options in the MAKEBITS program ailow timing
choices of one clock earlier or laterfor the timing of the end
of the internal logic reset and the assertion of the DONE
signal. The open-drain DONEIPROG output can be ANDtied with multiple LCAs and used as an active-High
READY, an active-Low PROM enable or a RESETto other
• IF READBACK IS
ACTIVATED, A
5-1<0 RESISTOR IS
REQUIRED IN
SERIES WITH M1
DURING CONFIGURATION
THE 5 kn M2 PULL-DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL-UP.
BUT IT ALLOWS M2TO
BE USER 1/0.

~

GENERALPURPOSE
USER 110
PINS

In Master mode, the LCA device automatically loads
configuration data from an external memory device. There
are three Master modes that use the internal timing source
to supply the configuration clock (CCLK) to time the
incoming data. Serial Master mode uses serial configuration data supplied to Data-in (DIN) from a synchronous
serial source such as the Xilinx Serial Configuration
PROM shown in Figure 21. Parallel Master Low and
Master High modes automatically use parallel data sup-

. +r

I I

MO M1 PWRDWN
DOUT

-

OPTIONAL
l-+ DAISY·CHAINED
LCA.WITH

M2

,.

-

HOC

'---

Master Mode

g~~~~~~ATIONS

--< LDC
--< INIT

-

),-'

110 PINS

-

LCA

OPTIONAL

f--- ~~~J~~ICAL
-

CONFIGURATIONS

+5V

I IV

RESET - - c RESET

Vee
DIN
CCLK
LDC
DONE- I - DIP

DATA
CLK
CE

pp

SERIAL
MEMORY
CEO

XC1736A1XC1765
rOE

.

"

~

'-i
'---j
<1

CASCADED
SERIAL
MEMORY

L

,HIGH RESETS THE XC1736A1XC1765 ADDRESS POINTER)

(O~~
"~~
(OUTPUT)

1105166

Figure 21. Master Serial Mode. The one-time-programmable XC1736AIXC1765 Serial Configuration PROM supports
automatic loading of configuration programs up to 36K bits. Multiple devices can be cascaded to support additional
LCAs. An early DONE inhibits the XC1736A data output a CCLK cycle before the LCA II0s become active.

2-18

plied to the 00-07 pins in response to the 16-bit address
generated by the LCA. Figure 22 shows an example ofthe
parallel Master mode connections required. The LCA HEX
starting address is 0000 and increments for Master Low
mode and it is FFFF and decrements for Master High
mode. These two modes provide address compatibility
with microprocessors which begin execution from opposite ends of memory. For Master High or Low, data bytes
are read in parallel by each Read Clock (RCLK) and

internally serialized by the Configuration Clock. As each
data byte is read, the least significant bit of the next byte,
DO, becomes the next bit in the internal serial configuration
word. One Maste-mode LCA can be used to interface the
configuration program-store and pass additional concatenated configuration data to additional LCAs in a serial
daisy-chain fashion. CCLK is provided for the slaved
devices and their serialized data is supplied from DOUT to
DIN - DOUT to DIN etc.

USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT FROM
ALTERNATIVE CONFIGURATIONS

+5V
• IF READ BACK IS
ACTIVATED. A
5-kn RESISTOR IS
REQUIRED IN
SERIES WITH M,

OPTIONAL

5kn

DOUT

DAISY·CHAINED
LCAs WITH DIFFERENT
CONFIGURAliONS

CCLK

M2

III

HOC
A'5

GENERAL·
PURPOSE
USER 110
PINS

RCLK

A14

INIT

A13

EPROM

OR~~MER)

A12
} OTHER
110 PINS

A1'
A,O

A10
RESET

RESET
07
06

LeA

05

DONE

A9

A9

A8

A8

A7

A7

07

A6

A6

os

04

A5

A5

05

03

A4

A4

04

02

A3

A3

03

0'

A2

A2

02

DO

A'

A'

0'

AD

AD

DO

LDC

OE
CE

DiP

8
DATA BUS

(OC~p~\~ _ _ _ _.JX"-_A_D_D_R_ESS
__
::------

-~:

00-07 --N.-'-BYT-E

(OUT~ca-~
'~CCLK

-{

BYTE N

\

X"-_________

E
1

I1+________~.~~~==========~.
8 CCLKs

XXXXX"'' ' ' "KT-B-YT-E- N-+-,- - -

\'-----

CCLK~

(OUTPUT)

(OUf~UUTT

jl60lBYTEF ji70fBYTENj j)OOfBYTEN
1'105178

Figure 22. Master Parallel Mode. Configuration data are loaded automatically from an external byte wide PROM.
An early DONE inhibits the PROM outputs a CCLK before the LCA 1/0 become active.

2-19

XC3000 Logic Cell Array Family
Peripheral Mode

modes, Peripheral mode may also be used as a lead
device for a daisy-chain of slave devices.

Peripheral mode provides a simplified interface through
which the device may be loaded byte-wide, as a processor
peripheral. Figure 23 shows the peripheral mode connections. Processor write cycles are decoded from the common assertion of the active low Write Strobe (WS), and two
active low and one active high Chip Selects (CSO, CS1,
CS2). If all these signals are not available, the unused
inputs should be driven to their respective active levels.
The Logic Cell Array will accept one byte of configuration
data on the 00-07 inputs for each selected processor
Write cycle. Each byte of data is loaded into a buffer
register. The LCA generates a configuration clock from
the internal timing generator and serializes the parallel
input data for internal framing or for succeeding slaves on
Data Out (OOUT). A output High on READY/BUSY pin
indicates the completion of loading for each byte when the
input register is ready for a new byte. As with Master

CONTROL
SIG NALS

ADDRESS
BUS

Slave mode provides a simple interface for loading the
Logic Cell Array configuration as shown in Figure 24.
Serial data are supplied in conjunction with a synchronizing input clock. Most Slave mode applications are in daisychain configurations in which the data input are supplied
by the previous Logic Cell Array's data out, while the clock
is supplied by a lead device in Master or Peripheral mode.
Data may also be supplied by a processor or other special
circuits.
Daisy-Chain
The XACT development system is used to create a composite configuration for selected LCAs including: a pre-

I~

DATA
BUS

-1

Slave Mode

8
DO-7

M1PWR
DWN

DO-7

CCLK

~

r"--+5V

~

1

MO

HDC

-

LDC

:>--

DOUT
ADDRESS
DECODE
LOGIC

>----C

M2

CSO

LCA
CSl
CS2

OTHER
WS ~PINS
RDY/BUSY

~
V

REPROGRAM

CSI
CS2

00-D7

CCLK

DOUT

- f-

OPTIONAL
DAISY-CHAINED
LCAs WITH DIFFERENT
CONFIGURATIONS

GENERA LPURPOS E
USER I/O
PINS

-

INIT
D/P
RESET

mz

\\\\

1IIIIlU

\SSS
X

lill

X

• IF READBACK IS
ACTIVATED, A
5·kn RESISTOR IS
REQUIRED IN SERIES
WITH Ml

5

-

\\\\\\\\

WS
CSO

{

+5V

(INTERNAL) \../
-----------------------~

~

RDY/BUSY

Figure 23. Peripheral Mode. Configuration data are loaded using a byte·wide data bus from a microprocessor.

2-20

1105180

cycle. The internal timing generator continues to operate
for general timing and synchronization of inputs in all
modes.

amble, a length count for the total bitstream, multiple
concatenated data programs and a postamble plus an
additional fill bit per device in the serial chain. After loading
and passing-on the preamble and length count to a possible daisy-chain, a lead device will load its configuration
data frames while providing a High DOUT to possible
down-stream devices as shown in Figure 25. Loading
continues while the lead device has received its configuration program and the current length count has not reached
the full value. The additional data are passed through the
lead device and appear on the Data Out (DOUT) pin in
serial form. The lead device also generates the Configuration Clock (CCLK) to synchronize the serial output
data and data in of down-stream LCAs. Data are read in
on DIN of slave devices by the positive edge of CCLK and
shifted out the DOUT on the negative edge of CCLK. A
parallel Master mode device uses its internal timing generator to produce an internal CCLK of 8 times its EPROM
address rate, while a Peripheral mode device produces a
burst of 8 CCLKs for each chip select and write-strobe

SPECIAL CONFIGURATION FUNCTIONS
The configuration data include control overseveral special
functions in addition to the normal user logic functions and
interconnect:
•
•
•
•
•
•

Input thresholds
Readback disable
DONE pull-up resistor
DONE timing
RESET timing
Oscillator frequency divided by two

Each of these functions is controlled by configuration data
bits which are selected as part of the normal XACT
development system bitstream generation process.

+5V

*
MO

M1 PWRDWN

MICRO
COMPUTER
STRB 1----4-~ CCLK
DO I----~DIN

-

IF READBACK IS
ACTIVATED, A
5·1<0 RESISTOR IS
REQUIRED IN
SERIES WITH M1

OPTIONAL
DAISY-CHAINED
LCAs WITH DIFFERENT
CONFIGURATIONS

01

VO
PORT

02
03

GENERALPURPOSE
USER 1/0
PINS

+5V
LCA

04
OTHER {

05
06

1/0 PINS

1--+--+-' DIP

07
RESET

DIN

CCLK

DOUT
(OUTPUT)

==xI;

BITN

~

~

BITN +1

I

~
BITN-1

m

BITN

Figure 24_ Slave Mode_ Bit-serial configuration data are read at rising edge of the CCLK.
Data on DOUT are provided on the falling edge of CCLK.

2-21

1105198

II

XC3000 Logic Cell Array Family

Input Thresholds

Readback

Prior to the completion of configuration all LCA input
thresholds are TTL compatible. Upon completion of configuration the input thresholds become either TTL or
CMOS compatible as programmed. The use of the TTL
threshold option requires some additional supply current
forthreshold shifting. The exception is the threshold of the
PWRDWN input and direct clocks which always have a
CMOS input. Prior to the completion of configuration the
user 110 pins each have a high impedance pull-up. The
configuration program can be used to enable the 108 pullup resistors in the Operational mode to act either as an
input load or to avoid a floating input on an otherwise
unused pin.

The contents of a Logic Cell Array may be read back if it
has been programmed with a bitstream in which the
Readback option has been enabled. Readback may be
used for verification of configuration and as a method of
determining the state of internal logic nodes during debugging with the XACTOR In-Circuit debugger. There are
three options in generating the configuration bitstream:

+S V

.{

+S

• "Never" will inhibit the Readback capability.
• "One-time," will inhibit Readback after one Readback
has been executed to verify the configuration.
• "On-command" will allow unrestricted use of Readback.

v

CCLK

CCLK

DOOT

DIN

Skll

DIN

LCA
SLAVE #1

M2
RCLK

LeA

SLAVE lin
M2
HOC

A1S

HOC

A14

A14

LOC

A13

A13

A12

A12

Al1

A11

A10
LCA
MASTER
A9

A10

EPROM

A8

A8

06

A7

A7

OS

A6

A6

04

AS

AS

03

A4

A4

02

A3

A3

01

A2

A2

DO

A1

A1

AO

AO

DIP

LOC

OE

RESET

INIT

N."

GENERAL·
PURPOSE
USER 110
PINS

LOC
OTHER {
ItO PINS

OTHER {
I/O PINS
INIT

A9

07

DOOT

M2
A1S

OTHER
00 PINS

Skll

CCLK

DOUT

HOC
GENERAL·
PURPOSE
USERVO
PINS

MO M1 PWROWN

MO M1 PWRDWN

GENERAL·
PURPOSE
USER I/O
PINS

INIT

DiP

DiP

RESET

RESET

07
NOTE: XC2000 DeVICES 00 NOT
HAVE iR1T TO HOLD OFF A MASTER
DEVICE. REID OF A MASTER DEVICE
SHOULD BE ASSERTED BY AN EXTERNAL
TiMiNG CIRCUIT TO ALLOW FOR LCA CCLK
VARIATIONS IN CLEAR STATE TIME.

.sV

CE

5knEACH
OPEN

REPROGRAM

ca..t.ECTOR

1105 20C

SYSTEM RESET

Figure 25. Master Mode Configuration with Daisy Chained Slave Mode Devices.
All are configured from the common EPROM source. The Slave mode device 1JiJlT signals
delay the Master device configuration until they are initialized. A well defined termination
of SYSTEM RESET is needed when controlling multiple LCAs.

Any XC3000 slave driven by an XC2000 master mode device must use "early DONE and early internal RESET".
(The XC2000 master will not supply the extra clock required by a "late" programmed XC3000.)

2-22

Readback is accomplished without the use of any of the
user I/O pins; only MO, M1 and CCLK are used. The
initiation of Readback is produced by a Low to High
transition of the MO/RTRIG (Read Trigger) pin. Once the
Readback command has been given, the input CCLK is
driven by external logic to read back each data bit in a
format similar to loading. After two dummy bits, the first
data frame is shifted out, in inverted sense, on the
M 1IRDATA (Read Data) pin. All data frames must be read
back to complete the process and return the Mode Select
and CCLK pins to their normal functions.

DONEIPROG Low. Once it recognizes a stable request,
the Logic Cell Array will hold a Low until the new configuration has been completed. Even if the re-program request is externally held Low beyond the configuration
period, the Logic Cell Array will begin operation upon
completion of configuration.
DONE Pull-up
DONEIPROG is an open-drain 1/0 pin that indicates the
LCA is in the operational state. An optional internal pull-up
resistor can be enabled by the user of the XACT development system when MAKE BITS is executed. The DONEI
PROG pins of multiple LCAs in a daisy-chain may be
connected together to indicate all are DONE or to direct
them all to re-program.

The Readback data includes the current state of each
internal logic block storage element, and the state of the
[.i and .n] connection pins on each lOB. These data are
imbedded into unused configuration bit positions during
Readback. This state information is used by the XACT
development system In-Circuit Verifier to provide visibility
into the internal operation of the logic while the system is
operating. To readback a uniform time-sample of all
storage elements, it may be necessary to inhibit the
system clock.

DONE Timing
The timing of the DON E status signal can be controlled by
a selection in the MAKEBITS program to occur a CCLK
cycle before, or after, the timing of outputs being activated.
See Figure 20. This facilitates control of external functions
such as a PROM enable orholdinga system in await state.

Re-program
The LCA configuration memory can be re-written while the
device is operating in the user's system. To initiate a reprogramming cycle, the dual-function pin DONE/PROG
must be given a High-to-Low transition. To reduce sensitivity to noise, the input signal is filtered for two cycles of the
LCA internal timing generator. When re-program begins,
the user-programmable 1/0 output buffers are disabled
and high-impedance pull-ups are provided forthe package
pins. The device returns to the Clear state and clears the
configuration memory before it indicates 'initialized'.
Since this Clear operation uses chip-individual internal
timing, the master might complete the clear operation and
then start configuration before the slave has completed the
Clearoperation. To avoidthis problem, the slave INITpins
are AND-wired and used to force a RESET on the master
(see Figure 25). Reprogram control is often implemented using an external open-collector driver which pulls

RESET Timing
As with DONE timing, the timing of the release of the
internal RESET can be controlled by a selection in the
MAKEBITS program to occur a CCLK cycle before, or
after, the timing of outputs being enabled. See Figure 20.
This reset maintains all user programmable flip-flops and
latches in a zero state during configuration.
Crystal OSCillator Division
A selection in the MAKEBITS program allows the user to
incorporate a dedicated divide-by-two flip-flop in the crystal oscillator function. This provides higher assurance of a
symmetrical timing signal. Although the frequency stability of crystal oscillators is high, the symmetry of the
waveform can be affected by bias or feedback drive.

2-23

XC3000 Logic Cell Array Family
the flip-flop element. The delay from the clock source to
the output of the logic block is critical in the timing of signals
produced by storage elements. Loading of a logic-block
output is limited only by the resulting propagation delay of
the larger interconnect network. Speed performance of
the logic block is a function of supply voltage and
temperature. See Figure 29.

PERFORMANCE
Device Performance
The LCA high performance is due in part to the manufacturing process, which is similar to that used for high-speed
CMOS static memories. Performance can be measured in
terms of minimum propagation times for logic elements.
Traditionally, the toggle frequency of a flip-flop has been
used to describe the overall performance of a gate array.
The configuration for determining the toggle performance
of the Logic Cell Array is shown in Figure 26. The flip-flop
output is fed back through the combinatorial logic as Q
to form the toggle flip-flop.

Interconnect Performance
Interconnect performance depends on the routing resource used to implement the signal path. As discussed
earlier, direct interconnect from block to block provides a
fast path for a signal. The single metal segment used for
long lines exhibits low resistance from end to end, but
relatively high capacitance. Signals driven through a
programmable switch will have the additional impedance
of the switch added to their normal drive impedance.

a

Actual LCA performance is determined by the timing of
critical paths, including both the fixed timing for the logic
and storage elements in that path, and the timing associated with the routing of the network. Internal worst-case
timing values are included in the performance data to allow
the user to make the best use of the capabilities of the
device. The XACT development system timing calculator
or XACT generated simulation models should be used to
calculate worst case paths by using actual impedance and
loading information. Figure 27 shows a variety of elements
which are involved in determining system performance.
Actual measurement of internal timing is not practical and
often only the sumof componenttiming is relevant as in the
case of input to output. The relationship between input and
output timing is arbitrary and only the total determines
performance. Timing components of internal functions
may be determined by measurement of differences at the
pins of the package. A synchronous logic function which
involves a clock to block-output, and a block-input to clock
set-up is capable of higher speed operation than a logic
configuration of two synchronous blocks with an extra
combinatorial block level between them. System clock
rates to 60% of the toggle frequency are practical for logic
in which an extra combinatorial level is located between
synchronized blocks. This allows implementation of
functions of up to 25 variables. The use of the wired-AND
is also available for wide, high-speed functions.

General-purpose interconnect performance depends on
the number of switches and segments used, the presence
of the bidirectional repowering buffers and the overall
loading on the signal path at a" points along the path. In
calculating the worst-case timing for a general interconnect path the timing-calculator portion of the XACT development system accounts for a" of these elements. As an
approximation, interconnect timing is proportional to the
summation of totals of local metal segments beyond each
programmable switch. In effect, the time is a sum of R-C
time each approximated by an R times the total C it drives.
The R of the switch and the C of the interconnect is a
function of the particular device performance grade. For a
string of three local interconnects, the approximate time at
the first segment, after the first switch resistance would be
three units; an additional two units after the next switch
plus an additional unit after the last switch in the chain. The
i!lterconnect R-C chain terminates at each re-powering
buffer. The capacitance of the actual block inputs is not
significant; the capacitance is in the interconnect metal
and switches. See Figure 28.

Logic Block Performance
Logic block performance is expressed as the propagation
time from the interconnect point at the input of the
combinatorial logic to the output of the block in the
interconnect area. Combinatorial performance is
independent of the specific logic function because of the
table look-up based implementation. Timing is difierent
when the combinatorial logic is used in conjunction with
the storage element. For the combinatorial logic function
driving the data input of the storage element, the critical
timing is data set-up relative to the clock edge provided to

CLOCK

-+----1>
1105 rr7

Figure 26. Toggle Flip-Flop. This is used
to characterize device performance.

2-24

l::X1l1NX
CLOCK TO
OUTPUT

I-----

TCKO

'«~'·'~~"·~'«·"«"'·'cut~~"!.~.:

COMBINATORiAl

-I-

liLO
r.' ·"·'·~'«·'«'«CLB·"·~«I

~

l

~

~,.", "~'w.,...,.~~~~.,..w,,,w..J

,..

SETUP

~

liCK

~

~

~

["'«·'·'·'"«·'108"·'=«««_·

~~!~r'-4

~!,. ~

LOGIC

I+-- ----I
TOp

i'·""·'·~~"«=««·"·"'««««-·"~~w""«'l

r-;'~+~~

'.

~,.;

-I·

~
~

ffi

~"~"""~~~"~'~'~~""""~"""""""""""""'NN''''''

X

,,~, ~J L.~w."w,,,,,.,,,"w,,,.w....."""w...,.,(~!,.,,,,w.w,,J ~

l.w",.,..,..".'w.'w.. ..

CLOCK--~----------+---------------------~~

,
~

,~

I-70

Speed Grade
Description

Symbol

-I

TOKPO

Min

Min Max

Mi~)' ':·:Max
.:.

Logic input to Output

Combinatorial

TILO

7

9

Units

-125

-100

Max

t105 Z1A

::

":';5.5

ns

::::,:;:::::

"'.~

K Clock

TCKO

To output
Logic-input setup
Logic-input hold

7

8

TICK
TCKI

:~:#;~;:: 6

q:~;:~~~
:",:-;.:

Input/Output

ns
ns
ns

6,:.:::,:,:

7
0

8
0

Pad to input (direct)

TplD

6

4

Output to pad (fast)

T OPF

9

6

1/0 clock to pad (fast)

T OKPO

13

10

x«·:

,.! 3

~~} .~~

ns

5

ns

ili~j ~ : ~ 9

ns

r~~:~

Figure 27. Examples of Primary Block Speed Factors.
Actual timing is a function of various block factors combined with routing factors.
Overall performance can be evaluated with the XACT timing calculator or by an optional simulation.
SWITCH
._ ••••••. /MATRIX ................... .
: R2
I
I
R3
:

CLB

,,

,,

L ••• ___ ..

TIMING: INCREMENTAL
IF Rl • R2 • R3 • RAND Cl. C2 • C3 • C
THEN CUMULATIVE TIMING
Tl =3RC
.3RC

T2=3RC+2RC
.5RC

T3. 3RC + 2RC + lRC
.6RC

6RC+ BUFFER

1105 238

Figure 28. Interconnection Timing Example. Use of the XACT timing calculator
or XACT-generated simulation model provides actual worst-case performance information.

2·25

II

XC3000 Logic Cell Array Family

1.00

0.80

TYPICAL COMMERCIAL
(+ 5.0 v, 25'C)

.
•

,

0.40

TYPICAL MiliTARY

,
:

MIN COMMERCIAL

:

,
0.20

~.~5 ~

____ - - - - - -

o

-20

25

,

---------------

~--------------------

-40

~

MIN MIJ:!V'£I:! !S}_VJ - - --'

~.-- ---------------~~~~~-----------

-55

MIN}AJIJV!\:! J.4~S_Vl_ - -

A__ ~ ____ - - - - - - - - - -

M

IN

40

70

80

100

125

TEMPERATURE ('C)

X1045

Figure 29_ Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations.

GND

+ --+,, -+-- + -- + -- + --+ -- +
+- -+ --+- -+ -- +-- + -- +--+

Vee

I

I

I

I

I

"

I

I

I

I

I

I

,

I

I

I

I

I

I

I

,

I

I

I

I

I

I

I

+- -+ --+ -- +-- +--+ -- +-- +
+-- + --+ --+--+--+--+- -+
+ --+ --+ -- + --+ -- + --+ --+
+--+--+--+--+-+, --+, --+- -+ -- +-- + -- +-- +
,
,
+- -+ --+ --+--+- -+ -- +- -+
I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

"

I

I

_-t-'H"---"
I

I

GROUND AND
VeeRING FOR
1/0 DRIVERS

I

LOGIC POWER GRID

GND
110524

Figure 30. LCA Power Distribution.

2-26

POWER

In an LCA, the fraction of nodes changing on a given clock
is typically low (10-20%). For example, in a large binary
counter, the average clock cycle produces changes equal
to one CLB output at the clock frequency. Typical global
clock-buffer power is between 1.7 mW/MHz for the
XC3020 and 3.6 mW/MHz for the XC3090. The internal
capacitive load is more a function of interconnect than fanout. With a typical load of three general interconnect
segments, each CLB output requires about 0.4 mW per
MHz of its output frequency.

Power Distribution
Power forthe LCA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
Inside the LCA, a dedicated Vcc and ground ring surrounding the logic array provides power to the I/O drivers.
See Figure 30. An independent matrix of V cc and ground
lines supplies the interior logic of the device. This power
distribution grid provides a stable supply and ground for all
internal logic, providing the external package power pins
are all connected and appropriately decoupled. Typically
a 0.1-IlF capacitor connected near the VCC and ground
pins will provide adequate decoupling.

Total Power = Vee' leeo + external (de + capacitive)
+ internal (elB + lOB + long line + pull-up)
Because the control storage of the Logic Cell Array is
CMOS static memory, its cells require a very low standby
current for data retention. In some systems, this low data
retention current characteristic can be used as a method
of preserving configurations in the event of a primary
power loss. The Logic Cell Array has built in power-down
logic which, when activated, will disable normal operation
of the device and retain only the configuration data. All
internal operation is suspended and output buffers are
placed in their high-impedance state with no pull-ups.
Power-down data retention is possible with a simple battery-backup circuit because the power requirement is
extremely low. For retention at 2.4 V, the required current
can be as low as 10 j.LA at room temperature.

Output buffers capable of driving the specified 4-mA loads
under worst-case conditions may be capable of driving 25
to 30 times that current in a best case. Noise can be
reduced by minimizing external load capacitance and
reducing simultaneous output transitions in the same
direction. It may also be beneficial to locate heavily loaded
output buffers near the ground pads. The I/O Block output
buffers have a slew-limited mode which should be used
where output rise and fall times are not speed critical.
Slew-limited outputs maintain their dc drive capability,
but generate less external reflections and internal noise. A
maximum total external capacitive load for simultaneous
fast mode switching in the same direction is 500 pF per
power/ground pin pair. Four slew-rate limited outputs this
total is four times larger.

To force the Logic Cell Array into the Power-Down state,
the user must pull the PWRDWN pin Low and continue
to supply a retention voltage to the VCC pins. When
normal power is restored, VCC is elevated to its normal
operating voltage and PWRDWN is returned to a High.
The Logic Cell Array resumes operation with the same
internal sequence that occurs at the conclusion of
configuration. Internal-I/O and logic-block storage
elements will be reset, the outputs will become enabled
and the DONEIPROG pin will be released. No configuration programming is involved.

Power Consumption
The Logic Cell Array exhibits the low power consumption
characteristic of CMOS ICs. For any deSign, Figure 31
can be used to calculate the total power requirement
based on the sum of the capacitive and dc loads both
external and internal. The configuration option of TIL chip
inputthreshold requires powerforthe threshold reference.
The power required by the static memory cells that hold the
configuration data is very low and may be maintained in a
power-down mode.

When the power supply is removed from a CMOS device,
it is possible to supply some power from an input signal.
The conventional electro-static input protection is implemented with diodes to the supply and ground. A positive
voltage applied to an input (or output) will cause the
positive protection diode to conduct and drive the Vcc
connection. This condition can produce invalid power
conditions and should be avoided. A large series resistor
might be used to limit the current or a bipolar buffer may be
used to isolate the input signal.

Typically, most of power dissipation is produced by external capacitive loads on the output buffers. This load and
frequency dependent power is 25IlW/pF/MHz per output.
Another component of I/O power is the dc loading on each
output pin by devices driven by the Logic Cell Array.
Internal power dissipation is a function of the number and
size of the nodes, and the frequency at which they change.

2-27

•

XC3000 Logic Cell Array Family

500

100
90

L
IL

80
70

L

60

L

L

50

,
150

•

;'

/
100

If'

/

•

•if
/

L

1

t....

40

/

(mW)

L

,

20

L

/

•

;'

/

,

50 CLB OUTPUTS 10
(18 mW/MHz)

/

,if

V

/
5
20 CLB OUTPUTS
(7.2 mW/MHz)

;'

IL

/

/

o. 5
0.5

1/

/

8
7

L

6

5

3

V

L

V

/

V

lL

(mA)

4

/

V

.L

2

.9
.8
.7

/

L

/

10
9

L

/

2

V

V

/

V

/

3

/

L
V

L

L

.L

L

4

3020 GLOBAL CLOCK BUFFER 1
OR
ONE OUTPUT WITH 50 pF LOAD
(1.8mW/MHz)

L

IL

L

30

20

;'

/
50

40

30

.6

L
V'

.5

.4
.3

.2

.1

2

3

4

5

10

20

30

40

50

FREQUENCY MHz
ONE CLB OR lOB OUTPUT /
DRIVING THREE LOCAL
INTERCONNECTS
(0.36 mW/MHz)
110509

Figure 31. LCA Power Consumption by Element. Total chip power is the sum of Vcc·lcco plus effective internal and external
values of frequency dependent capacitive charging currents and duty factor dependent resistive loads.

2-28

E:XlUNX
PIN DESCRIPTIONS

DONE
DONE is an open-drain output, configurable with or without an internal pull-up resistor. At the completion of
configuration, the LCA circuitry becomes active in a synchronous order, and DONE is programmed to go active
High either one cycle before or after the outputs go active.

Permanently Dedicated Pins.
Vcc
Two to eight (depending on package type) connections to
the nominal +5 V supply voltage. All must be connected.

PROG
Once configuration is done, a High-to-Low transition of
this pin will cause an initialization of the LCA and start a
reconfiguration.

GND
Two to eight (depending on package type) connections to
ground. All must be connected.
PWRDWN
A Low on this CMOS-compatible input stops all internal
activity, but retains configuration. All flip-flops and latches
are reset, all outputs are 3-stated, and all inputs are
interpreted as High, independent of their actual level.
While PWRDWN is Low, Vcc may be reduced to any value
>2.3 V. When PWDWN returns High, the LCA becomes
operational with DONE Low for two cycles of the internal
1-MHz clock. During configuration, PWRDWN must be
High. II not used, PWRDWN must be tied to Vcc.

MO
As Mode 0, this input and M1, M2 are sampled before the
start of configuration to establish the configuration mode to
be used.
RTRIG
A Low-to-High input transition, after configuration is
complete, acts as a Read Trigger and initiates a Readback
of configuration and storage-element data clocked by
CCLK. By selecting the appropriate Readback option
when generating the bitstream, this operation may be
limited to a single Readback, or be inhibited altogether.

RESET
This is an active Low input which has three functions.
Prior to the start of configuration, a Low input will delay the
start of the configuration process. An internal circuit
senses the application of power and begins a minimal
time-out cycle. When the time-out and RESET are complete, the levels of the M lines are sampled and configuration begins.

M1
As Mode 1, this input and MO, M2 are sampled before the
start of configuration to establish the configuration mode to
be used. If Readback is never used, M1 can betied directly
to ground or Vcc. If Readback is ever used, M1 must use
a 5-kQ resistor to ground or Vcc' to accommodate the
RDATA output.

If RESET is asserted during a configuration, the LCA
device is re-initialized and restarts the configuration at the
termination of RESET.

RDATA
As an active Low Read Data, after configuration is
complete, this pin is the output of the Readback data.

If RESET is asserted after configuration is complete, it
provides a global asynchronous reset of all lOB and CLB
storage elements of the LCA device.
CCLK
During configuration, Configuration Clock is an output of
an LCA in Master mode or Peripheral mode, but an input
in Slave mode. During Readback, CCLK is a clock input
for shifting configuration data out of the LCA
CCLK drives dynamic circuitry inside the LCA. The Low
time may, therefore, not exceed a few microseconds.
When used as an input, CCLK must be "parked High". An
internal pull-up resistor maintains High when the pin is not
being driven.

2-29

II

XC3000 Logic Cell Array Family

RClK
During Master parallel mode configuration RCLK represents a "read" of an external dynamic memory device
(normally not used).

User I/O Pins that can have special functions.
M2
During configuration, this input has a weak pull-up resistor.
Together with MO and M1 , it is sampled before the start of
configuration to establish the configuration mode to be
used. After configuration, this pin is a user-programmable
I/O pin.

ROY/BUSY
During Peripheral parallel mode configuration this pin
indicates when the chip is ready for another byte of data to
be written to it. After configuration is complete, this pin
becomes a user programmed 110 pin.

HOC
During configuration, this output is held at a High level to
indicate that configuration is not yet complete. After
configuration, this pin is a user-programmable I/O pin.

00-07
This set of eight pins represents the parallel configuration
byte for the parallel Master and Peripheral modes. After
configuration is complete they are user programmed
I/O pins.

lOC
During Configuration, this output is held at a Low level to
indicate that the configuration is not yet complete. After
configuration, this pin is a user-programmable I/O pin.
LDC is particularly useful in Master mode as a Low enable
for an EPROM, but it must then be programmed as a High
after configuration.

AO-A15
During Master Parallel mode, these 16 pins present an
address output for a configuration EPROM. After configuration, they are user-programmable 1/0 pins.

INIT

DIN
During Slave or Master Serial configuration, this pin is
used as a serial-data input. In the Master or Peripheral
configuration, this is the Data 0 input.

This is an active Low open-drain output which is held Low
during the power stabilization and internal clearing of the
configuration memory. It can be used to indicate status to
a configuring microprocessor or, as a wired AND of several
slave mode devices, a hold-off signal for a master mode
device. After configuration this pin becomes a user programmable I/O pin.

OOUT
During configuration this pin is used to output serialconfiguration data to the DIN pin of a daisy-chained slave.

BClKIN

TClKIN
This is a direct CMOS level input to the global clock buffer.

This is a direct CMOS level input to the alternate clock
buffer (Auxiliary Buffer) in the lower right corner.

XTl1
This user I/O pin can be used to operate as the output of
an amplifier driving an external crystal and bias circuitry.

Unrestricted User 1/0 Pins.
1/0
An 1/0 pin may be programmed by the user to be an Input
or an Output pin following configuration. All unrestricted
1/0 pins, plus the special pins mentioned on the following
page, have a weak pull-up resistor of 40 to 100 kQ that
becomes active as soon as the device powers up, and
stays active until the end of configuration.

XTl2
This user I/O pin can be used as the input of an amplifier
connected to an external crystal and bias circuitry. The
I/O Block is left unconfigured. The oscillator configuration
is activated by routing a net from the oscillator buffer
symbol output and by the MAKEBITS program.
CSO, CS1, CS2, WS
These four inputs represent a set of signals, three active
Low and one active High, that are used to control
configuration-data entry in the Peripheral mode.
Simultaneous assertion of all fou r inputs generates a Write
to the internal data buffer. The removal of any assertion
clocks in the 00-07 data. In Master-Parallel mode, WS
and CS2 are the AO and A 1 outputs. After configuration,
these pins are user-programmable I/O pins.

2-30

XC3000 Family Configuration Pin Assignments

~(II

vce
Ml (HIGH
MO (HIGH
M2 llGH
HUG :HII
OW

l'WR1lW1ii(ll
vc
Ml
MO
:{t{'M2
HE

OW
OW

UW
I

PWrf1iWiiim

~m

vce
Ml uw
MO, IGH
:}:(M2 IGH
HI

PWROWNm

vcc
I
I

10
18
25

vc

M' ,HIGH
MO
\{:M2,Hi(
He

I

M' UW
Me ow
:,:,:,:,',M2,HIGH
He

iNl

RE'

•

~'(II

'(II
10~

ONE

~

ONE

(II

ONE

27
28
30

\4

vc

\4

ve

:::,::,::,:,:,:,:::,:,

vcc

OAT A:,:,:",:,:,:,:,:,: 01
;5' I
DAIA
I ':':",:,:I,',:,::,DI

I ,:,:,:",:,:,:,:,:,:,: OAl
)}':'{{{DAl

! (II:::,:,:::

'(II)){

IT
I

44
45
46
47
48
49

:::::,:::,:::::::::: 01

DOU
LK

\ 0 (II :::::':::::::,:::,:::: DAl \ 0 (II :::::{:

38

56
57
58

12
22
3'
32
33
34
36
42
43
53
54
55
56
57
58
6C
6'
6,
6,
6'
66
6,
70
72

B2
F3
J2
K2

Kl0
Jl0
K'
Jl
Hl0
FlO
G'
G'

FI
F'

E:
E'

010
Cl'
B:

29
41
52
54
56
5C
59
65
66

14
Al
26
C8
37 i B13
39 I A 14
4'
<;13
42
~14
44
U14
50 IG14
5'
112

159
20
40
42
44
45
49
59
19

76
78
80
81
82
83

6: ! M13
63
P14
65
N13
66 I M12
67
P13
68
Nl'
72
M9
N9
74
NB
76
M8
N7
7B
P6
79
M6
83
M5
84
N4
85
N2

76
99
78101
80
103
81
104
82
105
86
109
92
115
9l
16
9B
121
100 123
102
'"
103 126
lOB 131
114 137
115 138
119 143

8:
88
B9
9'
92
9:
94
98
99
100

20
42
62
64
66
6C
B'
83

B2
09
B14

i'Wl!1lWN(11

~15

RTRIG (II
VO
VO
VO
VO
.oNe

C15
014
U16
H15
J14
P15
R15
R14
N13
f14
P12

vce
Fi1lID

-=

I'RC

x:

110
OR 110
VO

VO
Rl0
H9
N9
PB
H8
H,
R5
P5
R3

~~lml"~

110
VO
VCC
YU

VO

VO
VO
VO
110

m

~

~

~~n~o

CCLK
AD
A
A2
A3
A15
A4

CCLK
AD
Al
A2
A3
15

406074A1128C
PI121145R2U;CCLK(IIWf
6175~'
5wM2124148P2
VO
~~~69'Ml~1~~

63
64
65
66
67
_.68

78
8'
82

A'
A9,
B6
B7
A:

94

C6
A6
\12

AS
Al0
A9

lB
19
20
23

12

8
9

A9

x

"INIT IS AN OPEN DRAIN OUTPUT DURING CONFIGURATION
(II REPRESENTS AN INPUT
"" PIN ASSIGNMENTS FOR THE XC30641XC3090 DIFFER FROM

4

..2~.

AS
~O

II::}:}":! REPRESENTS A 5()'kn TO l00-kn PULL-UP

G

X

x

X

x

x
X"

X
x

25
26
XX
x
,X
x
x

G'
1-2
01
U2
Bl
C2

142
147
14B
151
152
155
156

152
P'
153 N'
156 M'
157
,2
160 K2
161
K
164
2
H2
3
Hl
B
c2
9
0'
12
13
16
E:
11. .(;2

X

x

x

X

m

VO
110
110

va
VO
VO
GNe

vu
VO
110

VA
VO
VO

VO
110
XC3020
XC3030
XC3042
XC3064
XC3090

AVAILABLE 'ACK, GES

THOSE SHOWN, SEE PAGE 2-35,
""" PERIPHERAL MODE AND MASTER PARALLEL MODE ARE NOT
SUPPORTED IN THE PC44 PACKAGE, SEE PAGE 2-33,

1105 250

Note: Pin assignments of "PGA Footprint" PLCC sockets and PGA packages are not electrically identical,
Generic I/O pins are not shown,

2-31

•

XC3000 Logic Cell Array Family
XC3000 FAMILY PIN ASSIGNMENTS

Note that there is no perfect match between the number of
bonding pads on the chip and the number of pins on a
package. In some cases, the chip has more pads than
there are pins on the package, as indicated by the information ("unused" pads) below the line in the following
table. The lOBs of the unconnected pads can still be used
as storage elements if the specified propagation delays
and set-up times are acceptable.

Xilinx offers the five different devices of the XC3000 family
in a variety of surface-mount and through-hole package
types, with pin counts from 44 to 175.
Each chip is offered in several package types to
accomodate the available pc board space and manufacturing technology. Most package types are also offered
with different chips to accomodate design changes without
the need for pc board changes.

In other cases, the chip has fewer pads than there are
pins on the package; therefore, some package pins are
not connected (n.c.), as shown above the line in the
following table.

Number of Package Pins
Device

Pads

XC3020

74

XC3030

98

XC3042

118

XC3064

142

58 unused

XC3090

166

82 unused

44

68

84

164

132

30 unused

9 n.c.

XC3000 Family 44-Pin PLCC Pinouts

Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

XC3030
GND
1/0

24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

1/0
1/0
1/0

1'WRlJWIiI
TCLKIN-I/O
1/0
1/0
1/0

vee
VO
1/0
1/0
M1·Jml\TA
MO-RTRIG
M2·1/0
HDC-VO

DJC"-VO

21

1/0
II'llT-VO

22

Pin No.
23

VO

20

175

26 n.c.

6 unused
54 unused

100

XC3030
GND

VO
VO
XTL2(1N)·VO

TlE"SET
DONE·l'G"I'}
1/0
XTL 1(OUT)-BCLK-VO
1/0

VO
VO

vee
1/0

VO
VO
DIN-I/O
DOUT·I/O
CCLK

VO
1/0
1/0

VO

Peripheral mode and Master Parallel mode are not supported in the PC44 package

2-32

XC3000 Family 58-Pin PLCC, 84-Pin PLCC and PGA Pinouts

68 PLCC

XC·3020*
XC-3030, XC·3042

84 PLCC

84PGA

68 PLCC

XC·3020*
XC·3030, XC-3042

84 PLCC

84 PGA

10

I'WRI:m

12

B2

44

m:sET

54

K10

11

TCLKIN-I/O

13

C2

45

DONE-I'G"

55

J10

14

B1

46

D7-1/0

56

K11

12

1/0*
110

15

C1

47

XTL 1(OUT)-BCLKIN-I/O

57

J11

13

110

16

D2

48

D6-1/0

58

H10
H11

-

110

17

D1

-

I/O

59

14

110

18

E3

49

D5-1/0

60

F10

15

110

19

E2

50

C"SO-I/O

61

G10

16

110

20

E1

51

D4-1/0

62

G11

17

110

21

F2

-

I/O

63

G9

18

VCC

22

F3

52

VCC

64

F9

19

110

23

G3

53

D3-1/0

65

F11

-

I/O

24

G1

54

CST-I/O

66

E11

20

I/O

25

G2

55

D2-1/0

67

E10

21

I/O

26

F1

-

22

I/O

27

H1

-

110

28

H2

23

I/O

29

J1

I/O

68

E9

1/0*

69

D11

58

D1-1I0

70

D10

57

RDY /1mS'i"-m:J:R"-1/0

71

C11

24

I/O

30

K1

58

DO-DIN-I/O

72

B11

25

M1-JmATA

31

J2

59

DOUT-I/O

73

C10

26

MO-RTRIG

32

L1

60

CCLK

74

A11

27

M2-1/0

33

K2

61

AO-WS-I/O

75

B10

28

HDC-I/O

34

K3

62

A1-CS2-1/0

76

B9

29

110

35

L2

63

A2-1/0

77

A10

64

A9

30

roc· I/O

36

L3

A3-1/0

78

31

110

37

K4

1/0*

79

B8

38

L4

A8

39

J5

65

1/0*
A15-1/0

80

32

1/0*
I/O

81

B6

33

I/O

40

K5

66

M-I/O

82

B7

1/0*

41

L5

67

A14-1/0

83

A7

34

1NlT-1/0

42

K6

68

AS-I/O

84

C7

35

GND

43

J6

1

GND

1

C6

36

I/O

44

J7

2

A13-1/0

2

A6

37

I/O

45

L7

3

AS-I/O

3

A5

38

I/O

46

K7

4

A12-1I0

4

B5

39

I/O

47

L6

5

A7-1/0

5

C5

40

110

48

L8

1/0*

6

A4

41

I/O

49

K8

1/0*

7

B4

1/0*

50

L9

6

A11-I/O

8

A3
A2

1/0*

51

L10

7

AS-I/O

9

42

I/O

52

K9

8

A10-1/0

10

B3

43

XTL2(1N)-1/0

53

L11

9

AS-I/O

11

A1

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.

* This table describes the pinouts of three different chips in two different packages. The second column lists 84 of the 118 pads on the
XC3042 (and 84 of the 98 pads on the XC3030) that are connected to the 84 package pins. Ten pads indicated by an asterisk, do not
exist on the XC3020, which has 74 pads; therefore the corresponding pins on the B4-pin packages have no connections. Six pads,
indicated by a dash (-) in the 68 PLCC column, have no connections in the 68 PLCC package, but are connected in the 84-pin package.
(See table on page 2-32.)

2-33

•

XC3000 Logic Cell Array Family
XC30641XC3090 84-Pin PLCC Pinouts

PLCC
Pin Number

XC3064, XC3090

PLCC
Pin Number

12

I'Wl'!IJN

54

"RESET

13

TCLKIN-1I0

55

DONE-PG"

14

1/0
1/0

56

D7-1I0

57

XTL 1I0UTl-8CLKIN-1I0

16

110

58

D6-1/0

17

59
61

110
D5-1/0

19

1/0
1/0
1/0

61

~-I/O

20

1/0

62

D4-110

21

GND*

63

110

22

VCC

64

VCC

23

1/0

65

GN~

24

110

66

00·1/0*

25

1/0

67

CS1·1/~

26

68

D2·1/0*

27

1/0
1/0

69

110

28

1/0

70

D1·1/0

15

18

XC3064, XC3090

29

110

71

RDVtlroS'7·1ml:K·I/O

30

1/0

72

DO·DIN·I/O

31

M1-l1OATA

73

DOUT·1I0

32

MO·RTRIG

74

CCLK

33

M2·1I0

75

M·WS·I/O

34

HDC·1I0

76

A1·CS2·1/0

35

110

77

A2·1/0

36

roc·I/O

78

A3·1/0

37

110
110

79

110

80

110
A15·1/0

38
39

110

81

40

110

82

M·IIO

41

INITII/O*

83

A14·1/0

42

VCC*
GND

84

A5·1/0

1

GND

1/0
110

2

VCC*

3

A13·11O*

43
44
45

110
1/0

4

A6·1/~

5

A12·1/0*

1/0
1/0

6

A7·I/~

7

110

8

A11-1/0

51

1/0
1/0

9

AS-li~

52

1/0

10

A10-1/0

53

XTL2(IN)-1/0

11

A9-1/0

46
47
48
49
50

Unprogrammed lOBs have a default pull-up. This prevents an undfined pad level for unbonded or unused lOBs.
Programmed ouptuts are default slew-rate limited. DEVICE POWER MUST BE LESS THAN 1 WAn.

* Different pin definition than 3020/3030/3042 PC84 package

2-34

XC3000 Family 100-Pin QFP Pinouts
Pin No.

XC3020
XC3030
XC3042
GND
A13·1/0

COFP

POFP

1
2

16
17

3

18

AS·I/O

4

19

A12·1/0

5

20

A7·1I0

6

21
22
23
24

1/0*
1/0*
A11-1/0
A8-1I0
A10-1/0
A9-1/0

7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

25

26
27
28
29
30
31
32
33
34
35
36
37
36
39
40
41
42
43
44
45
46
47
48
49

VCC*
GND*

l'WRDI'I'
TCLKIN-I/O

1/0**
1/0*
1/0*
1/0
1/0
1/0
1/0
1/0
1/0
1/0
VCC
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

Pin No.

Pin No.

XC3020
XC3030
XC3042

COFP

POFP

XC3020
XC3030
XC3042

35

50

1/0*

36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67

51
52

"0*
M1-Jm

71

85
86

53

72

87

54

GND*
MO-RT

73

88

55
56
57

VCC*
M2-1I0
HDC-II0

74
75
76

89
90
91

58

110
[[l'C"-1I0

77

92

VCC
D3-1I0

78
79

93

CST-II0

94
95

68

59
60
61
62
63
64
65

70

1/0*
110*
110
110
1/0
W-II0
GND
1/0
110
110
110

71
72

110
110

66
67
68
69

COFP

POFP

69
70

84

D4-1I0
110

96

D2-1/0
110
110*

97
98
99

"0*
D1-1I0
mTI{-SOSV/RDY -110

100

DO-DIN-II0

86
87

1
2

DOUT-II0

88

3
4

VCC*

89

76

"0*
"0*
XTAL2-1I0

77

GND*

96

78
79
80
81

RESET
VCC*
DONE-!'G'
D7-1/0

97
98
99
100

82

BCLKIN-XTAL 1-1/0

83

06-110

1/0

D5-1I0
CSQ-1I0

80
81
82
83
84
85

90
91
92
93
94
95

73
74
75

"0*
"0*
1/0

CCLK

5
6

GND*
AO-WS·II0
A1-CS2-1I0

7
8
9

"0**
A2-1I0
A3-1I0

10
11
12
13
14
15

110*
"0*
A15-1I0
A4-1I0
A14-1I0
AS-1I0

Unprogrammed lOBs have a default pull-up.
This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited .
• This table describes the pinouts of three different chips in two different packges. The third column lists 100 of the 118 pads on the
XC3042 that are connected to the 100 package pins. Two pads, indicated by double asterisks, do not exist on the XC3030, which has
98 pads; therefore the corresponding pins have no connections. Twenty-six pads, indicated by single or double asterisks, do not exist
on the XC3020, which has 74 pads; therefore, the corresponding pins have no connections. (See table on page 2-33.)

2-35

II

XC3000 Logic Cell Array Family
XC3000 Family 132-Pin Ceramic and Plastic PGA Pinouts
PGAPln
Number
C4
A1
C3
82
83
A2
84
CS
A3
M
85
C6
AS
86
A6
87

XC-3042
XC·3064

PGAPln
Numb.r

XC·3042
XC·3064

PGAPln
Number

XC·3042
XC·3064

PGAPin
Numb.r

XC·3042
XC·3064

GND

813
C11
A14

M1-Jm

P14
M11
N13
M12

m:SET

M3
P1

DOUT-VO
CCLK

DONE-PG"
D7-1I0
XTAL1-1I0-8CLKIN

M4
L3
M2
N1

AO-WS-VO
A1-CS2-1I0

M1
K3
L2
L1
K2
J3

110
110
A2-110
A3-VO
110
110

K1
J2
J1

A1S-1I0
M-IIO

PWRrniI
IIO-TCLKIN

VO
VO
110*
110
110
110*
110

VO
110
110
110
110
110

C7
C8
A7

GND

88
A8
A9
89
C9
A10
810
A11
C10
811
A12
812
A13

110
110
110
110
110
110
110

C12

vee

D12
C13
814
C14
E12
D13
D14
E13
F12
E14
F13
F14
G13
G14

"0*
110
110
1/0*
110

G12
H12
H14
H13
J14
J13
K14
J12
K13
L14
L13
K12
M14
N14

1/0*
110

M13
L12

VO

GND
MO-RT

vee
M2-VO
HDC-IIO

P13
N12
P12
N11
M10
P11
N10
P10
M9
N9
P9
P8

110
110
110
[[lC-1I0
110*
110
110

VO
110
110

lJIIlT-Vo

GND

N8
P7
M8

110
110

M7
N7

VO

P6

110
110

N6
PS
Me
NS
P4
P3
MS
N4
P2
N3
N2

vee

VO
110
"0*
110
110
110
110
XTAL2(IN)-1I0

GND

vee

110
110
D6-110
110
110*
110
110
DS-IIO
CSQ-IIO
"0*
110*
D4-1I0

VO

vee
GND
D3-1I0
C"S'f-1l0
"0*
1/0*
D2-1I0
110
110
110
D1-1I0
"RC[R'-iIDSY/RDY -110
110
110
DO-DIN-IIO

H1
H2
H3
G3
G2
G1
F1

vee
GND

"0*
A14-1I0
AS-IIO

GND

vee

A13-1I0
AS-IIO

F2
E1
F3
E2
D1
D2
E3
C1
81

110*
A12-1I0
A7-1I0
110
110
A1HI0
AS-IIO
110
110
A10-1I0

C2

A9-1I0

oa

vee

Unprogrammed lOBs have a default pUll-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited .
• Indicates unconnected package pins (14) for the XC3042.

2·36

XC3000 Family 160-Pln PQFP Pinouts

PlCC
Pin Number

XC3090

PlCC
Pin Number

XC3090

PlCC
Pin Number

XC3090

PlCC
Pin Number

XC3090

1

110

41

GND

81

07-110

121

CClK

2

110

42

MO-RTRIG

82

XTAll-IIO-BClKIN

122

VCC

3

110

43

VCC

83

110

123

GND

4

110
110
110
110
110
110

44

M2-110

84

AO-WS-I/O

HOC-liD

85
86

47
48

110
110

87
88

110
110

125
126
127

Al-CS2-110

110

110
110
06-1/0

124

45
46

128

110
110
A2-1/0

49

IJJC"-I/O

89

110

129

A3-110

110
110

50

110

90

110

130

110

51

91

110

131

52

92

05-110

132

110
A15-110

M-I/O

14

110
110
110

110
110

15

110

16

110

17

110

5
6
7
8
9
10
11
12
13

20

VCC

21

110

22

28

110
110
110
110
110
110
110

29

110

30
31

110

110

53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71

32

110

33
34

18

110

19

GND

110
1/0
1/0

93

CSO-I/O

133

94

110

134

110

95

1/0

135

110
A14-110

110

96

110

136

110
110

97

110

AS-liD

98

04-1/0

137
138

lIi!lT-IIO

99

110

139

GND

110

VCC

100

VSS

140

GND

101

GND

141

VCC
A13-1/0

110
110
110
110
1/0

102
103

03-1/0

142

AS-IIO

CST-liD

110

107

110
110
110
110

143
144

110

108

02-110

148

110
110
110
110
A12-1I0
A7-1I0

110
110
110

109

110

149

110

110

150

111

110

151

1/0
110
All-liD

72

110

112

110

152

AS-IIO

110

73

110

113

110

153

110

110

74

110

114

01-110

154

110

35

110

75

1/0

115

RDY-SSY/m:I:K-IIO

155

A10-110

36

110
110

76

XTAl2-110

116

110

156

A9-110

77
78
79
80

GND

117

110

157

VCC

RESIT

110
DO-DIN-IIO

158
159

GND

VCC

118
119

l'WFIDWI'J

DONE/P"G

120

DOUT

160

TClKIN-1I0

23
24
25
26
27

37
38
39

110
110

40

Ml-l'lOJITA

104
105
106

145
146
147

Unprogrammed lOBs have a default pull-up_ This prevents an undefined pad level for unbonded or unused 10Bs_
Programmed lOBs are default slew-rate limited.

2-37

III

XC3000 Logic Cell Array Family
XC3000 Family 164-Pln PQFP Pinouts

CQFPPln
Number

XC·3090

20

l'WImfJ

CQFP Pin
Number

XC·3090

CQFP Pin
Number

XC-3090
DONE·~

110

103

CQFP Pin
Number

XC·3090

143
144

DO·DIN·IIO
DOUT·IIO
CClK

21

TCLKIN·IIO

61
62

M1·lIDJITA

104

D7·1I0

22

110

63

GND

105

145

23

110

64

MO·RTRIG

XTAL1(OUT)·
BClKIN·IIO

146

VCC

24

110

VCC

106

110

110
110

M2·1I0
HDC·IIO

107
108

27

110

67
68

I/O

28

110

69

110

109
110

110
110
[)6·110

147
148
149

GND

25
26

65
66

29

110

70

110

30

110

71

31

110

72

32

110

33

110

34
35
36
37
38

110

39

110

40

110

80
81

41

GND

42
43

VCC
110

44
45

46
47
48
49
50
51
52
53
54
55
56
57
58

AO·WS·IIO
Al·CS2·110

150
151

110

110

111

110

152

A2·110

[DC"·VO

112

110

153

A3·110

110

113

110

154

110

73

110

114

110

155

110

74

110

A15·1I0

75

110

D5·1I0
CSQ·IIO

156

VO

115
116

157

M·IIO

110

76

110

117

158

110

110

77

118

VO

78
79

110
110

110
110

119

110

159
160

110
A14·110

110

120

110

161

AS·IIO

110
lI\IlT·IIO

121
122

D4·110
110

162
163

110
110

82

VCC

123

VCC

164

GND

83

GND

124

GND

1

84

110

125

D3·110

2

VCC
A13·110

110

85

110

126

C"Sj·1I0

3

AS·IIO

VO

86

110

127

4

110

110

87

110

128

110
110

5

110

VO
VO

88

110

129

110

6

110

89

VO

130

110

7

110

110
110

90
91

110

131

D2·110

132

110

8
9

A12·110

110

110

92

110

133

I/O

10

110

110

93

110

110

94

110

110
110

11

110

134
135

12

All·IIO

110
110

95

110
110

138

110

13

137

Dl·IIO

14

AS·IIO
110

110

97

138

VO

98

RDYllIDSY·
l1crR"·110

15

110

139

110

16

Al0·1/0

140

110

17

A9·110

141

110

142

110

96

110

99

59

110

100

110
1/0
XTAl2(IN)·1/0
GND

60

110

101

m:srr

102

VCC

Unprogrammed lOBs have a default pull·up.
This Prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.

2-38

110

A7·110

18

VCC

19

GND

E:XlUNX
XC3000 Family 175·Pln Ceramic and Plastic PGA Pinouts
PGAPln
Number
B2
04
B3
C4
B4
A4
05
C5
B5
AS
C6

os
B6
A6
B7
C7
07
A7
A8
B6
C8
08

09
C9
B9
A9
Al0
010
Cl0
Bl0
All
Bll
011
C11
A12
B12
C12
012
A13
B13
C13
A14

XC·3090
J5WROf\l
TCLKIN-I/O
110
I/O
110
110
110
1/0
110
110
110
VO
VO
VO
VO
1/0
110
110
110
VO
VO

GND

vee
VO
VO
1/0
110
110
I/O
110
110
110
110
1/0
1/0
1/0
1/0

110
VO
VO
110
I/O

PGA Pin
Number
013
B14
C14
B15
014
C15
E14
B16
015
C16
016
F14
E15
E16
F15
F16
G14
G15
G16
H16
H15
H14
J14
J15
J16
K16
K15
K14
L16
L15
M16
M15
L14
N16
P16
N15
R16

PGAPln
Number
R14
N13
T14
P13
R13
T13
N12
P12
R12
T12
Pll
Nll
Rl1
Tll
Rl0
Pl0
Nl0
T10
T9
R9
P9

XC·3090
VO
Ml-ROATA

GND
MO-RTRIG

vee
M2-1/0
HOC-VO
1/0
1/0
VO
[OC-VO
1/0
VO
VO
VO
I/O
VO
110
110
1/0
lfJTr-I/O

vee

N9
N8
P8
R8
T8
T7
N7

GND
VO
VO
VO
VO

Ito

M14
P15

110
110
I/O
1/0
1/0
1/0
VO
VO
I/O
VO
XTAL2(IN)-I/O

N14
R15

I'!ESET

P14

vee

P7
R7
T6
R6
N6
P6
T5
RS
P5
NS
T4
R4
P4

GND

XC·3090
DONE-PG"
07-VO
XTALl(OUT)-BCLKIN-VO
110
1/0
I/O
1i0
D6-VO
VO
I/O
VO
110
VO
05-VO
CSli-VO
1/0
110
110
110
04-1/0

VO

vee
GND
03-VO
W-I/O
VO
110
110
110
02-VO
110
1/0
I/O
VO
VO
01-110
ROY/BUSV-RcrR"-I/O
I/O
I/O
I/O
I/O

PGAPln
Number
R3
N4
R2

P3
N3
P2
M3

Rl
N2
Pl
Nl
L3
M2
Ml
L2

L1
K3
K2
Kl
J1
J2
J3
H3
H2
Hl
Gl
G2
G3
Fl
F2
El
E2
F3
01
Cl
02
B1
E3
C2

XC·3090
DO-OIN-I/O
DOUT-VO
CCLK

vee

GND
AO-WS-VO
Al-CS2-VO
110
1/0
A2-II0
A3-II0

VO
I/O
A15-II0
M-IIO
110
110
A14-1I0
AS-I/O
110
VO

GND

vee

A13-1/0
AS-VO
110
VO
I/O
I/O
A12-1/O
A7-1I0
110
VO
Al1-1/0
AS-VO
VO
VO
A10-1i0
A9-II0

03

vee

C3

GND

Unprogrammed lOBs have a default pull-up_ This prevents an undefined pad level for unbonded or unused 10Bs_
Programmed outputs are default slew-rate limited_
Pins A2, A3, A15, A16, Tl, T2, T3, T15 and T16 are not connected_
Pin A1 does not exist

2-39

II

XC3000 Logic Cell Array Family

Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.

ABSOLUTE MAXIMUM RATINGS
Symbol

Description

Units

Vee

Supply voltage relative to GND

-0.5 to +7.0

V

VIN

Input voltage with respect to GND

-0.5 to Vee +0.5

V

VTS

Voltage applied to 3-state output

-0.5 to Vee +0.5

V

TSTG

Storage temperature (ambient)

-65 to +150

°C

TSOL

Maximum soldering temperature (10 s @ 1/16 in.)

+260

°C

Junction temperature plastic

+125

°C

Junction temperature ceramic

+150

°C

TJ

Note:

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings
conditions for extended periods of time may affect device reliability.

OPERATING CONDITIONS
Symbol
Vee

Min

Max

Units

4.75

5.25

V

-40°C to +85°C

4.5

5.5

V

-55°C to +125°C

4.5

5.5

V

Description
Supply voltage relative to GND

Commercial

Supply voltage relative to GND

Industrial

Supply voltage relative to GND

Military

O°C to +70°C

VIHT

High-level input voltage -

TTL configuration

2.0

Vec

V

VILT

Low-level input voltage -

TTL configuration

0

0.8

V

VIHC

High-level input voltage -

CMOS configuration

70%

100%

Vcc

VILC

Low-level input voltage -

CMOS configuration

0

20%

Vcc

TIN

Input signal transition time

250

ns

2-40

DC CHARACTERISTICS OVER OPERATING CONDITIONS
Symbol

Description

Min

VOH

High-level output voltage (@ 10H = -4.0 mA, Vcc min)

VOL

Low-level output voltage (@ IOL = 4.0 mA, Vcc max)

VOH

High-level output voltage (@ IOH = -4.0 mA, Vcc min)

VOL

Low-level output voltage (@ IOL = 4.0 mA, Vcc max)

VCCPD

Power-down supply voltage (PWRDWN must be Low)

ICCPD

Power-down supply current (Vcc (MAX) @ TMAX)l

'cco

Commercial

Max

3.S6

V
0.32

Industrial
Military

Units

3.76

V
V

0.37

V
V

2.3
XC3020

50

J.lA

XC3030

SO

J.lA

XC3042

120

J.lA

XC3064

170

J.lA

XC3090

250

J.lA

500

J.lA

10

mA

+10

J.lA

Quiescent LCA supply current in addition to ICCPD2
Chip thresholds programmed as CMOS levels
Chip thresholds programmed as TTL levels
-10

'lL

Input Leakage Current

CIN

Input capacitance, all packages except PGA 175
(sample tested)
All Pins except XTL 1 and XTL2
XTL 1 and XTL2

10
15

pF
pF

Input capacitance, PGA 175
(sample tested)
All Pins except XTL 1 and XTL2
XTL 1 and XTL2

15
20

pF
pF

'RIN

Pad pull-up (when selected) @ VIN = OV (sample tested)

0.02

0.17

mA

'RLL

Horizontal long line pull-up (when selected) @ logic Low

0.2

2.5

mA

Note: 1. Devices with much lower ICCPD tested and guaranteed at Vcc =3.2 V, T =25°C can be ordered with a
Special Product Code.
XC3020: SPC011 0 ICCPD =1 ~A
XC3030: SPC0104IccPD= 2 ~A
XC3042: SPC01071ccPD = 3 ~A
XC3064: SPC0108 ICCPD = 4 ~A
XC3090: SPC01 09 ICCPD = 5 ~A
2. With no output current loads, no active input or long line pull-up resistors, all package pins at Vcc or GND,
and the LCA configured with a MAKEBITS '1ie" option. See LCA power chart for additional activity-dependent
operating component.

2-41

II

XC3000 Logic Cell Array Family
CLB SWITCHING CHARACTERISTIC GUIDELINES

-J

~

CLB OUTPUT (X,Y)
(COMBINATORIAL)

CLB INPUT (A,B,C,D,E)

------F0 "W

t== ®

TICK

.'.

--y
CD :::1''------TCKI

Ir-~-----~I

CLBCLOCK

@

TCl

o

TOICK--+t..-

CLB INPUT
(DIRECT IN)

CLBINPUT
(ENABLE CLOCK) ------'I~-------t---_::::_--I ~_ _ _ __

CLBOUTPUT
(FLIP-FLOP)

CLBINPUT
(RESET DIRECT)

_ _ _ _ _ _ _..1

CLBOUTPUT
(FLIP-FLOP)
1105 26

BUFFER (Internal) SWITCHING CHARACTERISTIC GUIDELINES

Description

Speed Grade

-70

-100

-125

Symbol

Max

Max

Max

6
3

4
2

Global and Alternate Clock Distribution
Either: Normal lOB input pad to clock buffer input
Or: Fast (CMOS only) input pad to clock buffer input
Plus: Clock buffer input to any CLB/IOB clock
on XC3020
on XC3030
on XC3042
on XC3064
on XC3090

TplD
T plOC

3.2/4.5
3.4/5.1
3.7/5.7
4.1/6.6
4.6/7.9

2.9/3.9
3.1/4.3
3.3/4.9
3.6/5.5
4.0/6.4

TBUF driving a Horizontal Long line (l.l.)"
I to l.L. while T is Low (buffer active)
TJ.. to l.l. active and valid
Ti to l.l. (inactive) with single pull-up resistor
with pair of pull-up resistors

TID
TON
Tpus
TpUF

22
11

4
7
14
7

BIOI
Bidirectional buffer delay

TBIDI

4

3

.. Timing is based on the XC3020, for other devices see XACT timing calculator.

2-42

5

9

Units

ns
ns

~:~t;~

3:114:4
3;~Z§;0

3i~t~~8

~i
2.5

•••••••••••••••••••••

ns
ns
ns
ns
ns

ns
ns
ns
ns

ns

CLB SWITCHING CHARACTERISTIC GUIDELINES (Continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.

-70

Speed Grade
Description

Symbol

Combinatorial Delay
Logic Variables a, b, c, d, e, to outputs x, y
Sequential delay
Clock k to outputs x, y
Clock k to outputs x,y when Q is returned
through function generators For G to drive x, y
Set-up time before clock
Logic Variables
Data In
Enable Clock
Reset Direct inactive
Hold Time after clock k
Logic Variables
Data In
Enable Clock

Min

-125

-100

Max

Min

Max

TllO

9

7

5.5

ns

8

TCKo

8

7

6

ns

15

12

10

ns

8

7

6

TICK
TDICK
TECCK

5
7
1

5
1

3
5
7

TCKI
TCKDI
TCKEC

0
0

0
2
0

11
12

TCH
TCl
FClK

7
7
70

5
5
100

a,b,c,d, e
di
ec
rd

2

a,b,c,d,e
di
ec

Reset Direct (rd)
rd width
delay from rd to outputs x, y

Max

1

K

Clock
Clock High time'
Clock Low time'
Max. flip-flop toggle rate'

Min

Units

4

si ...,.,..
~

4!

4

4

'I

ns
ns
ns
ns

k"·'"

ri;:
I
~..,•...•.

ns
ns
ns

~ ....
f

4i I
1~~ f':""'"

ns
ns
MHz

~::,..:,.:

?"'" II. ",.

13
9

Global Reset (RESET Pad)
RESET width (Low)
delay from RESET pad to outputs x, y

TRPw
TRIO

8

TMRW
TMRQ

25

7

ns
ns

16

ns
ns

20

21
20

6

6
7

8

17

• These timing limits are based on calculations.
Note: The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than
the Data In hold time requirement (TCKDI, #5) of any CLB on the same die.

2-43

III

XC3000 Logic Cell Array Family
lOB SWITCHING CHARACTERISTIC GUIDELINES
110 BLOCK (I)

-®-TPID~-t----

t-CD-1-T-P-,C-K--------..J

VO PAD INPUT

VOCLOCK
(lK/OK)

1 + - - - - @ T,Ol---~---110 BLOCK (RI)

VOBLOCK(O)

VO PAD OUTPUT
(DIRECn

__________________f0TOKPO
VO PAD OUTPUT
(REGISTERED)

J---Ir-@-~-SON----@-~-"'j I

110 PADTS

110 PAD OUTPUT

--------~(~

__________~r__
110527C

I ~----P-RO-G-R-AM-.-CO-N-T-RO-L -E-M-OR-Y-C-E-LL-S---~
..
LE-D-...

Voc

:j

3- STATE
(OUTPUT ENABLE)
OUT

~:;:~:..--I------=JL/--t-,
.,

~~---t,,-,,

DIRECT IN ........

-----,f------,

,:-'i

REGISTERED IN

...-:,;-~
, -'-----if---i

R
.ok

.ik

'---+-------- (GLOBAL RESET)

j}- ~~. ~]:r
MUL.TIPLEXER

mmm~:

0 - PROGRAMMABLE INTERCONNECTION POINT Of PIP
2-44

110501A

lOB SWITCHING CHARACTERISTIC GUIDELINES (Continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.

Description

Symbol

Min

Propagation Delays (Input)
Pad to Direct In (i)
Pad to Registered In (q) with latch transparent
Clock (ik) to Registered In (q)

-125

-100

-70
Max

Min

Max

Min

Max

4
17
6

6
21
7

Units

3
16

5

ns
ns
ns

Set-up Time (Input)

20

Pad to Clock (ik) set-up time

17

ns
",.... """,

Propagation Delays (Output)
Clock (ok) to Pad
(fast)
same
(slew rate limited)
Output (0) to Pad
(fast)
same
(slew-rate limited)
3-state to Pad begin hi-Z (fast)
same
(slew-rate limited)
3-state to Pad active and valid (fast)
same
(slew -rate limited)

7
7
10
10

9
9
8
8

TOKPO
TOKPO
TOPF

10
27
6

13

33
9

23
8

29

Tops
TTSHZ
TTSHZ
TTSON
TTSON

8
28
14

25
12

34

29

····'·'·'···,·.'• •·9
,·,···.··'••••'• • • ·5

Ii • . •.•,'"'..··7
,·.·········.·'
;, .••.•••• 1

ns
ns
ns
ns
ns
ns
ns
ns

"""'"".f

Set-up and Hold Times (Output)
Output (0) to clock (ok) set-up time
Output (0) to clock (ok) hold time

10

9

ns
ns

7
7

5
5

ns
ns
MHz

o

o

Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate

100

70

Global Reset Delays

33

20
28

19
26

53

45

42

23

RESET Pad to Registered In (q)
RESET Pad to output pad (fast)
(slew-rate limited)

ns
ns
ns

Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (inc!. test fixture).
For larger capacitive loads, see page 6-9.
Typical slew rate limited output riselfall times are approximately four times longer.
A maximum total external capacitive load for simultaneous fast mode switching in the same direction
is 500 pF per power/ground pin pair. For slew-rate limited outputs this total is four times larger.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured
with the internal pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (.ik)
In order to calculate system set-up time, subtract clock delay (pad to ik) from the input pad set-up time value.
Input pad holdtime with respect to the internal clock (ik) is negative. This means that pad level changes immediately
before the internal clock edge (ik) will not be recognized.
For a more detailed description see the discussion on "LCA Performance" in the Applications Section.

2-45

II

XC3000 Logic Cell Array Family

GENERAL LCA SWITCHING CHARACTERISTICS

~_ _ _-;III-I_ _( 0 T R W ) - - - - - - - -

MOIM11M2

-£®'~®'~f-------~_®TPGW~

DONEIPROG

___J
____
-

[®TPGI

INIT
(OUTPUn

USER STATE

-

______C_LE_A~RI~S-TA-T-E--------JI'
II

CONFIGURATION STATE

.

\ _____--11'
r-NOTE 3-+j
Vee (VALID)

lr~t------

--------------------------------------------;\
•\.

____ 1--,:
•
VCCPD
1105 28

-70
Description
RESET (2)

DONEIPROG

PWRDWN (3)

Symbol

MO, M1, M2 setup time required
MO, M1, M2 hold time required
RESET Width (Low) req. for Abort

2
3

Width (Low) required for Re-config.
INIT response after DIP is pulled Low

5

4

6

Power Down Vcc

TMR
TRM
TMRW
TPGW
TpGI
VCCPD

Min
1
1

Max
0

6

-125

Min Max

Min Max

1
1

0
1

~s
~s
~s

6
7

2.3

0

6

6
7

2.3

0

6

6

Units

-100

~s

7
2.3

~s

V

Notes: 1. At power-up, Vee must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by holding RE"SET Low until Vee has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vee may require. a RESET pulse (High-to-Low-to-High) of >6 j.lS duration after Vee has reached 4.0 V.
2.

RE"SET timing relative to valid mode lines (MO, M1, M2) is relevant when RESET is used to delay configuration.

3. PWRDWN transitions must occur while Vcc >4.0 V.

2-46

MASTER SERIAL MODE PROGRAMMING SWITCHING CHARACTERISTICS

CCLK
(OUTPUT)

SERIAL DATA IN

SERIAL DOUT

(OUTPUT) _ _ _ _ _...1 '-_ _ _ _ _- - 1 ' - -_ _ _ _ _...1 '-_ _ _ _ _ _ __
1105 29

-70

Speed Grade
Description
CCLK3

Data In setup
Data In hold

Symbol

1
2

TDSCK
TCKDS

Min

60
0

Max

-100
Min

60
0

Max

-125
Min

60
0

Units

II

Max
ns
ns

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vcc has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vcc may require a RESET pulse (High-to-Low-to-High) of >6 ~s duration after Vcc has reached 4.0 V.
2. Configuration can be controled by holding RESET Low with or until after the TNTT of all daisy-chain slave-mode devices
is High.
3. Master-serial-mode timing is based on slave-mode testing.

2-47

XC3000 Logic Cell Array Family

MASTER PARALLEL MODE PROGRAMMING SWITCHING CHARACTERISTICS

AO-A15
(OUTPUn

ADDRESS for BYTE n

ADDRESS for BYTE n + 1

DO--D7

RClK
(OUTPUn

/

tl4-=--=--=--=--=--_"",-il-_-7 C-C-l-KS-_-_-_-_-_-_...I-r_--

CClK
(OUTPUT)
DOUT
(OUTPUn

D7
BYTE n-1
1105 30

-70
Description
RCLK

To address valid
To data setup
To data hold
RCLK high
RCLK low

Symbol

1
2
3

TRAC
TDRC
T RCD
TRCH
TRcl

-100

Min

Max

0

200

60

Min

Max

0 200

60

0

0

600
4.0

600
4.0

-125
Min

Max

0

200

60
0
600
4.0

Units

ns
ns
ns
ns
Ils

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vee has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vcc may require a RESET pulse (High-to-Low-to-High) of >611S duration after Vee has reached 4.0 V.
2. Configuration can be controlled by holding11Em:T Low with or until after the lNlT of all daisy-chain slave-mode devices
is High.

This timing diagram shows that the EPROM requirements are extremely relaxed:
EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.

2-48

E:XIUNX
PERIPHERAL MODE PROGRAMMING SWITCHING CHARACTERISTICS

7

CS2

•.

.

I
\

\

CS1/CSO

)
I
I

WS

00-07

CCLK

•

I
•

I

'\ •• • 1

•

II

I
•

I

'\ •• • 1

ROYIBUSY

I
I

- •••••••••••••••••••••• 1

OOUT

_--'x'--_--'x"-______--' . . . --'X. . . ____C
1105 lOA

-70
Description
Write

ROY

Notes:

Symbol

Min

Max

-100

-125

Units

Min Max

Min Max

Effective Write time required
(CSO • CSl • CS2 • WS)

1

TCA

100

100

100

ns

DIN Setup time required
DIN Hold time required

2
3

Toc
Tco

60
0

60
0

60
0

ns
ns

ROY/BUSY delay after end of WS

4

TWTRB

Earliest next WS after end of BUSY

5

TRBWT

0

BUSY Low time generated

6

TBUSY

2

60
0
9

60

60

2

ns

0
9

2

ns

9

CCLK
Periods

1. At power-up, Vee must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vee has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vee may require a RESET pulse (High-to-Low-to-High) of >61ls duration after Vee has reached 4.0 V.
2. Configuration must be delayed until the

TfiIlT of all LCAs is

High.

3. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and
the phase of the internal timing generator for CCLK.
4. CCLK and DOUT timing is tested in slave mode.

This timing diagram shows very relaxed requirements:
Data need not be held beyond the rising edge of WS. BUSY will go active within 60 ns after the end of WS. BUSY will stay
active for several microseconds. WS may be asserted immediately after the end of BUSY.

2-49

XC3000 Logic Cell Array Family
SLAVE MODE PROGRAMMING SWITCHING CHARACTERISTICS

~: =10'=t@'=0~~ ___-<'f*:0-'~"ro~@5
DOUT
(OUTPUT)

CCLK

----------_____B_IT_N_ __

BIT N-1

Description
To DOUT
DIN setup
DiN hold
High time
Low time (Note 1)
Frequency

Symbol

3

Teeo
Tocc
TCCD
TCCH
TCCL
Fcc

1
2

4
5

TCCl

-70
Min Max

-100
Min Max

100
60
0
0.5
0.5

-125
Min Max
100

100
60
0
0.5
0.5

5.0
1

5.0
1

"0531

60
0
0.5
0.5

5.0
1

Units
ns
ns
ns
JlS
Jls
MHz

Notes: 1. The max limit of CCLK Low time is caused by dynamic circuitry inside the LCA device.
2. Configuration must be delayed until the TJillT of all LCAs is High.
3. At power-up, Vcc must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vcc has reached 4.0 V. A very long Vcc rise time of > 100 ms, or a non-monotonically
rising Vcc may require a RESET pulse (High-to-Low-to-High) of >61ls duration after Vee has reached 4.0 V.
4. For configuration (not Readback), CCLK frequency can be increased to 5 MHz and TCCH and Tccl min reduced to
100 ns, worst case over temperature and supply voltage. This high-speed CCLK frequency will be tested, documented
and guaranteed some time in 1991. For further information on running CCLK faster than 1 MHz, contact Xilinx Product
Marketing.
PROGRAM READ BACK SWITCHING CHARACTERISTICS
DONE/PROG
(OUTPUT)

____-LI___________________________________ _

RTRIG(Mo)

CCLK(1)

RDATA
(OUTPUT)

110532A

-70
Description

Symbol

RTRIG

RTRIG high

1

TRTH

CCLK

RTRIG setup
RDATAdeiay
Low time

2

T RTCC

3
4

TCCRD
TCCL

Min

-100

Max

250

Max

0.5

Max

100
5

0.5

Units
ns

10

10
100
5

-125
Min
250

250

10
0.5

Min

100
5

ns
ns
Jls

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vcc has reached 4.0 V. A very long Vcc rise time of > 100 ms, or a non-monotonically
rising Vcc may require a RESET pulse (High-to-Low-to-High) of >61ls duration after Vee has reached 4.0 V.
2. CCLK and DOUT timing are the same as for slave mode.
3. RETRIG (MO positive transition) shall not be done until after one clock following active 1/0 pins.
4. Readback should not be initiated until configuration is complete.

2-50

PGA PIN-OUTS

1

A

2

3

4

5

6

7

8

9 10 11

@@@)@;)@~@)@;)@@8 A

A

@@@)@@(@@@@@@
@8@
~~
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00
000 TOP V~IEW O®~
8@@
008
Component
000
O~@
Side
@O
00
~@
o®
080

B

11 10 9

876

5

4

2

3

1

8@@@;)@)~@@;)@)@@ A

@@@@@(@@@@)@@
@8@ EB~O
@@ [BOTTOM VHEW 00
~®O
000
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@~O
000
O@
00
@~
080
®O
@@OOO(@OO@@O

B

B

c O~EB

c

c ~~

c

D

D

D

D

E
F

E
F

G

G

H

H

J

J

E
F
G

H

J

O@@OO~OOO~@
®O~@@OOO@@@

K
L

1

2

3

4

5

6

7

8

K

K

L

L

9 10 11

@@;)@;)0001@@~0®
11 10 9

8

7

6

5

4

7 6

5

3

2

B

E
F
G

H
J

K
L

1

EB • Index pin which mayor may not be electrically connected to pin C2
(NC)

=Pin Not Connected for XC3020. unlabeled pin. unrestricted va pin
PG84 Pln-outs-XC3042, XC3030, XC3020

I

2

3

4

5

6

7

8

14 13 12 II 10 9

9 10 II 12 13 14

"@@@)OOOOOOO@@@®
@l00000000000®@
c 0@0800890080@0
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F @~O
000

A

A

A

B

B

B

G
H

J
K

L

@~9
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Component
Side

@@O
@)OO
@@8

80~

800
000
000
80@

c

c

D

D

E

E

F

F

G

G

H

H

J

J

K

K

8

4

3

2

I

®@@)@OOOOOOO@@@ A
@®00000000000@l B
0@0800980080@0 c
9@@) D
~09
OO@' E
O@O
000
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~9

1(0

~09~OTTOIMl V~IEW 9~@

008
000
000
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8@~

Solder Side

G

H

O@@
OO@)
8@@

K

O~O®O~@®@O~O®@
@@O@O@@O~@OOO@

N
p

J

L

L

M O@)~9@®89@O9@@O

M

M O~@90®98®@9~@)O M

N
p

N
p

N
p

@@O~O@@@~O®O~O
@OOO@~O@@O@O@@
I

2

3

4

5

6

7

8

9 10 II 12 13 14

14 13 12 II 10 9

(NC) = Pin Not Connected for XC3042. unlabeled pin _ unrestricted 110 pin

PG132 Pln-outs-XC3064, XC3042-PG, -PP

2-51

8

7 6

5

4

3

2

I

L

II

XC3000 logic Cell Array Family

PGA PIN·OUTS (cont'd)
I

2

3

4

5

6

7

8

9 10 II 12 13 14 15 16

16 15 14 13 12 II 10 9

8

7

6

5

4

3

2

I

A

@@OOOOOOOOOOO@@ A A@@OOOOOOOOOOO@@
A
B 0r@00000000000®®0 B
B O®®OOOOOOOOOOO@O B
c@@900000000009@Oc c 0@900000000009@@ c
D rw09@00099000090~ D D~09000099000@90rwD
E OO@)
@JO@ E
E @O~
~OO E
F 000
O~O F
~ 8~8 TOP VHEW
~ G 000
000 G
H @~9
Component
9@0 H H 0@9 IBOTTOM V~IEW 9~@ H
900 J J 009
900 J
J 009
Solder Side
O~@ K
K @~O
Side
000 K K 000
L O@O
000 L L 000
O@O L
M @l0@
000 M M 000
@O@l M
N @09~00099000®900 N N009®00099000~90@N
p @@90~00@000@09@0 p pO@90@OOO@OO~09@@p
R O@@O@O®~®~OOO~@)O R RO@~OOO~®~®O@O@@OR
T @@@0000000@00@l@@ T
T @@@lOO@OOOOOOO@@@ T

888

I

2

3

4

5

6

7

B 9 10 II 12 13 14 15 16

16 15 14 13 12 11 10 9

(NC) _ Pin Not Connected. unlabeled pin. unrestricted 110 pin

PG175 Pln-outs-XC309O-PG, -PP

2-52

B 7 6

5

4

3

2

I

PHYSICAL DIMENSIONS
PIN #1 ID LOCATION
(EITHER POS.)

0.050TYP

~~m
0.653 ± 0.003 0.690

II

9 JA = 40-45 °CIW
= 10-11 °CIW

9 JC

~""'J
~
~10.015
0.010

14

0.620 - - - - - -

LEAD CO-PLANARITY
± 0.002
DIMENSIONS
IN INCHES

1105428

44-Pin PLCC Package

0.045 x45'
9

61

PWRDWN

CCLK
DOUT/IO

0.990
±0.005
0.94

Vee

Vee

I "U:;~r;6:;=rma=t:;= : f i'Ei"f i:;=C R~ ~

-0.954±0.004~1
1L.1+=-=--1~27
O.~

LEAD PITCH
0.050 TYPICAL
LEAD CO-PLANARITY

± 0.002
DIMENSIONS
IN INCHES

...
_ - - - - - 0 . 9 9 0 ± 0.005====:11
TOP VIEW

9 JA = 35-40 °eIW
9 Jc= 7-10 °eIW
110534C

S8-Pin PLCC Package

2-53

XC3000 Logic Cell Array Family

PHYSICAL DIMENSIONS (Continued)

L.'L,
PINNO.1

0.045

0.045

PIN NO.1 IDENTIFIER

x 450",11

75

PWRDWN

~

CCLK
DOUT/IO

P

1 .190

± 0.005

1.000

1.154
±0.004

Vee

TYP

Vee

1.120

±0.010
0.Q18

-'-T
M1
MO

-'--

~01--33

DONE
RESET
JU

cucaue

*=+=~*

0.028

41

_ _ 1.154±0.004._ _ _5-413

i"~....- - - - - - - - 1 . 1 9 0 0.005-------~1.

LEAD PITCH
0.050 TYPICAL

±

TOP VIEW
DIMENSIONS IN INCHES

8 JA = 30-35 °C/W
8 Jc =3-7 °CIW

1105 36C

84-Pin PLCC Package

0.130
±O.Q10

\'

~

1.100±0.012S

1.000±0.010

j+---t

0.100 TYP

~~

...Lb.~

'-V '-V

'-V '-V

~~

IL

~~

1-( ~ !1I~fhfj-

b.

-"'

G

0.100
TYP

b

D D

b

D-L

1.00o
±O.OI o

-"'

-"'

-(3--E

\Q

~

JEXPIN

TYP.0.Q70
D:l'08 MAX

Y

i-"

c
~

L

B

~

A

~
•

7

10

11

BOTTOM VIEW

8 JA = 30-35 °C/W

NOTE: INDEX PIN MAY OR MAY NOT BE
ELECTRICALLY CONNECTED TO PIN C2.

8 Jc = 4-7 °C/W

DIMENSIONS IN INCHES

84-Pin PGA Package

2-54

110535C

1':XILINX
PHYSICAL DIMENSIONS (Continued)

0.009 • 0.005

0.705 • 0.01 0

1 - - - - - 0.742REF-----oj

LEAD PITCH
0.0256TYP

TOP VIEW

~~

5-7.
f-...;~--------------,__r

0.57.0.006

II

"',',

""

WilllilluuummD~~~~m][m[lh=i.·O~:TINGPLANE"

"

0.031± 0.006

~
.

DIMENSIONS IN INCHES

1105391::

100-Pin PQFP Package

LEADFRAME
0.0045 MIN
0.0080 MAX

MIN

MAX

r'''[
0.145

LEAD PITCH 0.025lYPICAL
BOTTOM VIEW
(LID SIDE UP)
(DIE FACING UP)

8JA = 40-50° CIW
8JC = 5-80 CIW

MARKING

MAXJ

0.0300 to.ooso

0.0500 '0.0050
0.120

MAX

DIMENSIONS IN INCHES
SIDE VIEW
NOTES:
1. LEADS ARE SHIPPED UNFORMED IN CARRIERS IN TRAYS.
TOPSIDE UP
2. FORMING TOOL INFORMATION:
:

~f~~r%IT~I~~~~~f~~~~g7g~ ~~~ ~?WELL NJ.
1105 40C

tOO-Pin CQFP Package

2-55

XC3000 Logic Cell Array Family

PHYSICAL DIMENSIONS (Continued)
0.040 X 45'
4PLCS

1

2

3

4

5

8

1

8

9

10

11

12

13

PIN
KOVAR

,.

0000000,000000
TYP 0.070 DIA
00000000000000
±
M00000000000000
000 r - - - - + - -_____ -'-~u.:;.L+---.000
000
000
000
000
000
O. 45
1.460
+
000
• 800
000
000
000
000
0000
c 000
000000
• 000 000000
000000
p

0

N

0.005

1
0.018 ± 0.002 DIAJ

132 PLCS

L

K

J

H

±O,OOS

±O.015

F

E

0.070
±0.01 sa

I.

C±~~~ --:~~~'-P=~~:----of
1<--1.

± 0.015
BOTTOM VIEW
110538B

132-Pin PGA Package

1234567&91011121314

0000000,000000~

p

0000000000000 0
M00000000000000
000
000
000
000
000
000
N

l'-is~~gE~FFPIN)

L

K

J

£~~00

+

00~,-

000
I
000
0 0 0
BLACK ANODIZED
0 0 0
000
ALUMINUM LID
000
o 000
000
c 00000000000000
• 00000000000000

1.460

± 0.01

G

F

E

0000000000000~

A

CHAMFER
0,039 X 45°

REF

I,

[±-0.100±0.002

_ _ _ _..L

.1

1.300±0'012------oI,I
1.460±O.015-------I-.
BOTTOM VIEW

DIMENSIONS IN INCHES

0.050
± 0.004

±06~tl
0.197
0.070
1105 438

132-Pin PPGA Package

2-56

PHYSICAL DIMENSIONS (Continued)

-,

LEO~~~A~~

.... 0.0650

± 0.0050

-+11_

0.0080 MAX

DE VITREOUS
SOLDER GLASS

r-[
". ~J III ~o_

0.0300 ± 0.0050

BOTTOM VIEW
(LID SIDE UP)
(DIE FACING UP)

~~

II

~0.120MAX

•• _

SIDE VIEW

0.008 MIN
0.013 MAX

TOP VIEW

DIMENSIONS IN INCHES

(DIE FACING DOWN)
NOTES:
1. LEADS ARE SHIPPED UNFORMED IN CARRIERS IN TRAYS. TOPSIDE UP
2. FORMING TOOL INFORMATION:
- FANCORT INDUSTRIES - (201) 575·0610 WEST CALDWELL NJ.
- RISIINDUSTRIES INC. (619) 425·3970 CHULA VISTA. CA.

ElJA = 35-45 0 CfW
ElJC

= 3-5 CfW
0

1105410

164-Pin CQFP Package

2-57

XC3000 Logic Cell Array Family
PHYSICAL DIMENSIONS (Continued)
TOP VIEW

o

+----

INDEX (Al)

_-++_-+-e JA =16.4 °CIW
eJC = 0.5-1.0 °CIW

0.025 REF

WE10 METALIC HEATSINK
ELECTRICALLY CONNECTED TO VCC

PIN KOVAR
0.005 R. TYP.
0.016 REF

,,000000000000000
010000000,00000010
M0000000000000000
130000
0000
0000
110000
0000
,,0000
0000
0000
~ 0 0.--::=0~0~o--tt---+
0000
'0000
70000
0000
0000
'0000
0000
'0000
40000
·0000
'0000
'0000
15

0

0.070
± 0.005 TYP DIA

12

9

T

R

P

1.660
± 0.016 sa

0.845
± 0.009

1.

0

tors
DIELECTRIC
COAT
STAND·OFF PIN
4 PLACES

N

BOTTOM VIEW
1105 37C

175-Pin PGA Package (Ceramic)

2-58

PHYSICAL DIMENSIONS (Continued)
TOP VIEW

o
o

0.040 REF

0

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0

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0

0

0

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0

0

0

0

0

0

0

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0

0

0

0

0

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0

0

0

000

0

0

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0

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0

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rtI

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+-______

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0

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0

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0

000

000

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0

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0

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L -_ _ _ _ _ _

0

0

~

0

000

0

0

El JA =22'C/W
ElJC= 1.6'C/W

r- 0.071 ± 0.006

. . 0.070 ± 0.00

0

1,.-----------+------------, __-+-_ _

.L.

~:,~ !,"~.~.1:"rm TUb:~". 1
~

~
16@@@@@@@@@@@@@@@(et-""'1------.15 @ @ @ @ @ @ @ @ @ @ @ @ @ @ @) @
M@@@@@@@@@@@@@@@@

1.660

± 0.01650

T

R

0.070 ± 0.005
DIATYP

P

NMLKJHGFEDCBA"'-.
BOTTOM VIEW

" - - STAND·OFF PIN
4 PLACES

1991018

175·Pln PPGA Package (Plastic)

2-59

Component Selection and
Ordering Information
COMPONENT AVAILABILITY (11/90)

Xll04

XC1736A/XC1765-PDSC Plastic S-Pin Mini-DIP
-40°C to S5°C
XC1736A/XC1765-CDSM Ceramic S-Pin Mini-DIP
-55°C to 125°C

COMPATIBLE PACKAGE OPTIONS
A range of LCA devices is available in identical packages
with identical pin-outs. A design can thus be started with
one device, then migrated to a larger or smaller chip while
retaining the original footprint and PC-board layout.

LCA Temperature Options
Symbol

Description

C

Commercial
Industrial
Mil Temp
Military

I
M
B

Temperature

Examples:

O°C to 70°C
-40°C to 85°C
-55°C to 125°C
MIL-STD-883, Class B

PC 68:
PC 84:
PG84:
PO 100:
PG 132:

2064-2018-3020-3030
2018-3020-3030-30423064-3090
201 8-3020-3030-3042
3020-3030-3042
3042-3064

ORDERING INFORMATION
Example:

""';~''''
Toggle
Rate

IJ TlL
XC3020-70PC68C

Note, however, that the XC2000 and XC3000 families
differ in the position of XTL 1 as well as three parallel
address bits (6, 7 and 11) and most of the data pins used
in parallel master mode.

,~,.••"
Range

XC2018 and XC3020 are not available in PGA68, since
the PGA84 is the same size and offers more 1/0.

Number of Pins

Note that a PLCC in a socket with PGA footprint generates
a printed circuit board pin-out different from a PGA device.

Package Type

2-60

XC2064/XC201 S
Logic CeW Array
M

Product Specification
FEATURES
• Fully Field-Programmable:
• 1/0 functions
• Digital logic functions
• Interconnections
• General-purpose array architecture
• Complete user control of design cycle
• Compatible arrays with logic cell complexity equivalent
to 1200 and 1800 gates
• Standard product availability
• 100% factory-tested
• Selectable configuration modes
• Low-power, CMOS, static-memory technology
• Performance equivalent to TTL SSIIMSI
• TTL or CMOS input thresholds
• Complete development system support
• XACT Design Editor
• Schematic Entry
• XACTOR In-Circuit Emulator
• Macro Library
• Timing Calculator
• Logic and Timing Simulator
• Auto Place I Route

Part
Number

Logic
Capacity
(gates)

Conflg·
urable
Logic
Blocks

XC2064
XC2018

1200
1800

64
100

User
II0s

58
74

Conflg·
uration
Program
(bits)
12038
17878

The LCA logic functions and interconnections are
determined by data stored in internal static-memory cells .
On-chip logic provides for automatic loading of
configuration data at power-up. The program data can
reside in an EEPROM, EPROM or ROM on the circuit
board or on a floppy disk or hard disk. The program can be
loaded in a number of modes to accommodate various
system requirements.

ARCHITECTURE
The general structure of a Logic Cell Array is shown in
Figure 1. The elements of the array include three categories of user programmable elements: 1/0 Blocks (lOBs),
Configurable Logic Blocks (CLBs) and Programmable
Interconnections. The II0Bs provide an interface between
the logic array and the device package pins. The CLBs
perform user-specified logic functions, and the interconnect resources are programmed to form networks that
carry logic signals among the blocks.

DESCRIPTION
The Logic Cell™ Array (LCATM) is a high density CMOS
integrated circuit. Its user-programmable array architecture is made up of three types of configurable elements:
Input/Output Blocks, logic blocks and Interconnect. The
designer can define individual 110 blocks for interface to
external circuitry, define logic blocks to implement logic
functions and define interconnection networks to compose
larger scale logic functions. The XACTTM Development
System provides interactive graphic design capture and
automatic routing. Both logic simulation and in-circuit
emulation are available for desjgn verification.

LCA configuration is established through a distributed
array of memory cells.The XACT development system
generates the program used to configure the Logic Cell
Array which includes logic to implement automatic
configuration.
Configuration Memory
The configuration of the Logic Cell Array is established by
programming memory cells which determine the logic
functions and interconnections. The memory loading
process is independent of the user logic functions.

The Logic Cell Array is available in a variety of logic
capacities, package styles, temperature ranges and
speed grades.

2-61

II

XC2064/2018 Logic Cell Array

affected by extreme power supply excursions or very high
levels of alpha particle radiation. In reliability testing no
soft errors have been observed, even in the presence of
very high doses of alpha radiation.

The static memory cell used for the configuration memory
in the Logic Cell Array has been designed specifically for
high reliability and noise immunity. Based on this design,
which has been patented, integrity of the LCA configuration memory is assured even under adverse conditions.
Compared with other programming alternatives, static
memory provides the best combination of high density,
high performance, high reliability and comprehensive
testability. As shown in Figure 2, the basic memory cell
consists oftwo CMOS inverters plus a pass transistor used
for writing data to the cell. The cell is only written during
configuration and only read during readback. During
normal operation the pass transistor is "off" and does not
affect the stability of the cell. This is quite different from the
normal operation of conventional memory devices, in
which the cells are continuously read and rewritten.

Input/Output Block
Each user-configurable liD block (lOB) provides an interface between the external package pin of the device and
the internal logic. Each I/O block includes a programmable
input path and a programmable output buffer. It also
provides input clamping diodes to provide protection from
electro-static damage, and circuits to protect the LCA from
latch-up due to input currents. Figure 3 shows the general
structure of the liD block.
The input buffer portion of each liD block provides threshold detection to translate external signals applied to the
package pin to internal logic levels. The input buffer
threshold of the liD blocks can be programmed to be
compatible with either TIL (1.4 V) or CMOS (2.2 V) levels.

The outputs Q and Q control pass-tranSistor gates directly.
The absence of sense amplifiers and the output capacitive
load provide additional stability to the cell. Due to the
structure of the configuration memory cells, they are not

1/0 BLOCK

¢;J Q¢;J

D
CONFIGURABLE
LOGIC BLOCK~

-[}
-[}
-[}
-[}
-[}
-[}

-[}

o

0 0 0

0 01 0 0
0 OJ 0 0
0 0 0 0
..

INTERCONNECT AREA

Figure 1. Logic Cell Array Structure

2-62

~

110401

The buffered input signal drives both the data input of an
edge-triggered D flip-flop and one input of a two-input
multiplexer. The output of the flip-flop provides the other
input to the multiplexer. The user can select either the
direct input path or the registered input, based on the
content of the memory cell controlling the multiplexer. The
1/0 Blocks along each edge of the die share common
clocks. The flip-flops are reset during configuration as well
as by the active-low chip RESET input.

Configurable Logic Block

Output buffers in the 1/0 blocks provide 4-mA drive for high
fan-out CMOS or TTL-compatible signal levels. The
output data (driving 1/0 block pin 0) is the data source for

An array of Configurable Logic Blocks (CLBs) provides the
functional elements from which the user's logiC is constructed. The logic blocks are arranged in a matrix in the

the I/O block output buffer. Each 1/0 block output buffer is
controlled by the contents of two configuration memory
cells which turn the buffer ON or OFF or select 3-state
buffer control. The user may also select the output buffer
3-state control (1/0 block pin TS). When this 1/0 block
output control signal is High (a logic "1 "), the buffer is
disabled and the package pin is high-impedance.

III
READ or
WRITE
DATA

1105 12

Figure 2. Configuration Memory Cell

TS (OUTPUT ENABLE)

OUT

IN

D

Qf----'

-fI _

VOCLOCK

PROGRAM·CONTROLLED

~ - MULTIPLEXER

1104 03

Figure 3. I/O Block

2-63

XC206412018 Logic Cell Array

X

OUTPUTS

INPUTS

A
B
C

0

G

Y

COMB.
LOGIC

F

CLOCK
1104 04

Figure 4. Configurable Logic Block

center of the device. The XC2064 has 64 such blocks
arranged in an 8-row by 8-column matrix. The XC2018 has
100 logic blocks arranged in a 10 by 10 matrix.

logic block inputs and the storage element output "Q". A
third form of the combinatorial logic (Option 3) is a special
case ofthe 2-function form in which the B input dynamically
selects between the two function tables providing a single

Each logic block has a combinatorial logic section, a
storage element, and an internal routing and control section. Each CLB has four general-purpose inputs: A, B, C
and D; and a special clock input (K), which may be driven
fromthe interconnect adjacentto the block. Each CLB also
has two outputs, X and Y, which may drive interconnect
networks. Figure 4 shows the resources of a Configurable
Logic Block.
The logic block combinatorial logic uses a table look-up
memory to implement Boolean functions. This tech-nique
can generate any logic function of up to fourvariables with
a high speed sixteen-bit memory. The propagation delay
through the combinatorial network is independent of the
function generated. Each block can perform any function
of four variables or any two functions of three variables
each. The variabies may be selected from among the four
inputs and the block's storage element output "Q".
Figure 5 shows various options which may be specified for
the combinatorial logic.

F
A
ANY
FUNCTION
OF 4
VARIABLES

B

C

D

-

C

I

I

0

If the single 4-variable configuration is selected (Option 1),
the F and G outputs are identical. If the 2-function
alternative is selected (Option 2), logic functions F and G
may be independent functions of three variables each.
The three variables can be selected from among the four

OPTION 1
1 FUNCTION OF 4
VARIABLES

2-64

f--

G

merged logic function output. This dynamic selection
allows some 5-variable functions to be generated from the
four block inputs and storage element Q. Combinatorial
functions are restricted in that one may not use both its
storage element output Q and the input variable of the logic
block pin "0" in the same function.
SET

Q

F---------ID

If used, the storage element in each Configurable Logic
Block (Figure 6) can be programmed to be either an edgesensitive "0" type flip-flop or a level-sensitive "0" latch.
The clock or enable for each storage element can be
selected from:

K-':---r-.

c-:O:---l

RES
D-;':--~

• The special-purpose clock input K
• The general-purpose input C
• The combinatorial function G
The user may also select the clock active sense within
each logic block. This programmable inversion eliminates the need to route both phases of a clock signal
throughout the device.

Figure 6. CLB Storage Elememt

The storage element data input is supplied from the
function F output of the combinatorial logic. Asynchronous SET and RESET controls are provided for each
storage element. The user may enable these controls
independently and select their source. They are active

High inputs and the asynchronous reset is dominant. The
storage elements are reset by the active-Low chip RESET
pin as well as by the initialization phase preceding configuration. If the storage element is not used, it is disabled.

B

A
B
C

A
ANY
FUNCTION
OF3
VARIABLES

ANY
FUNCTION
OF3
VARIABLES

F
C

F

D

D

M
U

X

A
B
C

A
ANY
FUNCTION
OF3
VARIABLES

D

ANY
FUNCTION
OF3
VARIABLES

G
C

G

D

OPTION 2

OPTION 3

2 FUNCTIONS OF 3
VARIABLES

DYNAMIC SELECTION OF
2 FUNCTIONS OF 3
VARIABLES

Figure 5. CLB Combinatorial Logic Options
Note: Variables D and Q can not be used in the same function.

2-65

1104 05

XC206412018 Logic Cell Array
The two block outputs, X and Y, can be driven by either the
combinatorial functions, F or G, or the storage element
output Q (Figure 4). Selection of the outputs is completely
interchangeable and may be made to optimize routing
efficiencies of the networks interconnecting the logic
blocks and I/O blocks.

and then toggling the states of the interconnect points by
selecting them with the "mouse". In this mode, the connections through the switch matrix may be established by
selecting pairs of matrix pins. The switching matrix combinations are indicated in Figure 7b.
Special buffers within the interconnect area provide periodic signal isolation and restoration for higher general
interconnect fan-out and beUer performance. The repowering buffers are bidirectional, since signals must be
able to propagate in either direction on a general interconnect segment. Direction controls are automatically established by the LogiC Cell Array development system software. Repowering buffers are provided only for the
general-purpose interconnect since the direct and long
line resources do not exhibit the same R-C delay accumulation. The Logic Cell Array is divided into nine sections
with buffers automatically provided for general interconnect at the boundaries of these sections. These boundaries can be viewed with the development system. For
routing within a section, no buffers are used. The delay
calculator of the XACT development system automatically
calculates and displays the block, interconnect and buffer
delays for any selected paths.

PROGRAMMABLE INTERCONNECT
Programmable interconnection resources in the Logic Cell
Array provide routing paths to connect inputs and outputs
of the I/O and logic blocks into desired networks. All
interconnections are composed of metal segments, with
programmable switching points provided to implement the
necessary routing. Three types of resources accommodate different types of networks:
• General purpose interconnect
• Long lines
• Direct connection
General-Purpose Interconnect
General-purpose interconnect, as shown in Figure 7a, is
composed of four horizontal metal segments between the
rows and five vertical meta! segments between the columns of logic and I/O blocks. Each segment is only the
"height" or ''width'' of a logic block. Where these segments
would cross at the intersections of rows and columns,
switching matrices are provided to allow interconnections
of metal segments from the adjoining rows and columns.
Switches in the switch matrices and on block outputs are
specially designed transistors, each controlled by a configuration bit.

(t

CLB

,

I
I

_oJ SEE FIG. 7b

A

Logic-block output switches provide contacts to adjacent
general interconnect segments and therefore to the
switching matrix at each end of those segments. A switch
matrix can connect an interconnect segment to other
segments to form a network. Figure 7a shows the general
interconnect used to route a Signal from one logic block to
three other logic blocks. As shown, combinations of
closed switches in a switch matrix allow multiple branches
for each network. The inputs of the logic or I/O blocks are
multiplexers that can be program-med with configuration
bits to select an input network from the adjacent interconnect segments. Since the switch connections to block
inputs are unidirectional (as are block outputs) they are
usable only for input connection. The development system software provides automatic routing of these interconnections. Interactive routing is also available for design
optimization. This is accomplished by selecting a network

B
C

CLB

K

X

Y

0

CLB

110407

Figure 7a. General-Purpose Interconnect

2-66

AVAILABLE PROGRAMMABLE
SWITCH MATRIX INTERCONNECTIONS
OF GENERAL INTERCONNECT
SEGMENTS BY PIN

,,
,,

00
0

G 3.

Q-i
, ,

,,

0

4

• •

s.

•

3

•

7

•

7

3

4

•

5

•

3

•

3

7

•

7

4

• •

:

Q-i
, ,

0

3

a· . 0.

X

00

•

7

~
·.

a

{~

3

•

• •

0

Y

•

7

-}

, , 0
r;Jr;J0
0
0r;J
:0

_

~

4 HORIZONTAL
GENERAL PURPOSE
INTERCONNECT

7

6

,r-'

,,

II

~ ~
• •

•

3

•

3

4

7

•

5

,
I
I
I

I I I I
5 VERTICAL
GENERAL PURPOSE
INTERCONNECT
BETWEEN SWITCH
MATRICES

\

PROGRAMMABLE
INTERCONNECT POINTS
(DO NOT USE MORE THAN
ONE PER INPUT PIN)
1104 08

Figure 7b. Routing and Switch Matrix Connections

Long Lines

the global buffer for a clock provides a very low skew, high
fan-out synchronized clock for use at any or all of the logic
blocks. At each block, a configuration bit forthe K input to
the block can select this global line as the storage element
clock signal. Alternatively, other clock sources can be
used.

Long-lines, shown in Figure 8a, run both vertically and
horizontally the height or width of the interconnect area.
Each vertical interconnection column has two long lines;
each horizontal row has one, with an additional long line
adjacent to each set of I/O blocks. The long lines bypass
the switch matrices and are intended primarily for signals
that must travel a long distance or must have minimum
skew among multiple destinations.

A second buffer below the bottom row of the array drives
a horizontal long line which, in turn, can drive a vertical long
line in each interconnection column. This alternate buffer
also has low skew and high fan-out capability. The
network formed by this alternate buffer's long lines can be
selected to drive the B, Cor K inputs of the logic blocks.

A global buffer in the Logic Cell Array is available to drive
a single signal to all Band K inputs of logic blocks. Using

2-67

XC206412018 Logic Cell Array

B B
e B
B B
I

--.-..J

I

B

~

--.-..J

SWITCH
MATRIX

I

~

I

X

0 CLB

Y

SWITCH
MATRIX

TWO VERTICAL
LONG LINES

~

HORIZONTAL
LONG LINE

GLOBAL
LONG LINE

110409

Figure 8a. Long Line Interconnect

bottom of the die. Direct interconnections of I/O blocks
with CLBs are shown in Figure 8b.

Alternatively, these long lines can be driven by a logic or
I/O block on a column by column basis. This capability
provides a common, low-skew clock or control line within
each column of logic blocks. Interconnections of these
long lines are shown in Figure 8b.

CRYSTAL OSCILLATOR
An internal high speed inverting amplifier is available to
implement an on-chip crystal oscillator. It is associated
with the auxiliary clock buffer in the lower right cornerof the
die. When configured to drive the auxiliary clock buffer,
two special adjacent user I/O blocks are also configured to
connect the oscillator amplifier with external crystal oscillator components, as shown in Figure 10. This circuit
becomes active before configuration is complete in order
to allow the oscillator to stabilize. Actual internal connection is delayed until completion of configuration. The
feedback resistor R1 between output and input, biases the
amplifier at threshold. It should be as large a value as
practical to minimize loading of the crystal. The inversion
of the amplifier, together with the R-C networks and
crystal, produce the 360-degree phase shift of the Pierce
oscillator. A series resistor R2 may be included to add to

Direct Interconnect
Direct interconnect, shown in Figure 9, provides the most
efficient implementation of networks between adjacent
logic or 1/0 blocks. Signals routed from block to block by
means of direct interconnect exhibit minimum interconnect propagation and use minimum interconnect resources. For each Configurable Logic Block, the X output
may be connected directly to the C or D inputs of the CLB
above and to the A or B inputs of the CLB below it. The Y
output can use direct interconnect to drive the B input of the
block immediately to its right. Where logic blocks are
adjacent to I/O blocks, direct connect is provided to the
I/O block input (I) on the left edge of the die, the output (0)
on the right edge, or both on I/O blocks at the top and

2-68

GLOBAL
BUFFER

VERTICAL LONG LINES
(2 PER COLUMN)

HORIZONTAL LONG LINES
(1 PERROW)

II

1/0 CLOCKS
(1PER EDGE)

ALTERNATE
BUFFER

OSCILLATOR
AMPLIFIER
X1205

Figure 8b. XC2064 Long Lines, 110 Clocks, 1/0 Direct Interconnect

2-69

XC2064/2018 Logic Cell Array

the amplifier output impedance when needed for phaseshift control or crystal resistance matching or to limit the
amplifier input swing to control clipping at large amplitudes. Excess feedback voltage may be adjusted by the
ratio of C2/C1. The amplifier is designed to be used over
the range from 1 MHz up to one-half the specified CLB
toggle frequency, Use at frequencies below 1 MHz may
require individual characterization with respect to a series
resistance. Operation at frequencies above 20 MHz
generally requires a crystal to operate in a third overtone
mode, in which the fundamental frequency must be suppressed by the R-C networks, When the amplifier does not
drive the auxiliary buffer, these I/O blocks and their package pins are available for general user I/O.

POWER
Power Distribution
Power for the LCA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
For packages having more than 48 pins, two Vcc pins and
two ground pins are provided (see Figure 11), Inside the
LCA, a dedicated Vcc and ground ring surrounding the
logic array provides power to the I/O drivers, An independent matrix of Vcc and ground lines supplies the interior
logic of the device. This power distribution grid provides a
stable supply and ground for all internal logic, providing the
external package power pins are appropriately decoupled,
Typically a 0.1 j.l.F capacitor connected between the Vee
and ground pins near the package will provide adequate
decoupling,

1104 10

Figure 9. Direct Interconnect

ON-CHIP

EXTERNAL

ALTERNATE
CLOCK BUFFER

Output buffers capable of driving the specified 4 mA loads
under worst-case conditions may be capable of driving 25
to 30 times that current in a best case. Noise can be
reduced by minimizing external load capacitance and
reducing simultaneous output transitions in the same
direction. It may also be beneficial to locate heavily loaded
output buffers near the ground pads, Multiple Vee and
ground pin connections are required for package types
which provide them.

SUGGESTED COMPONENT VALUES
R1 0.5-1 Mn
R20-1Kn
(may be required for low
frequency, phase
shift and/or compensation
level for crystal 0)
C1,C210-40pF
Y1 1 - 20 MHz AT cut series
resonant

XTAL1

XTAL2

48 DIP

33

30

68 PLCC

46

43

68PGA

J10

L10

84 PLCC

56

53

84PGA

K11

L 11

110411

Figure 10. Crystal Oscillator

2-70

Power Consumption

the sum of capacitive and resistive loading of the devices
driven by the Logic Cell Array.
Internal power supply dissipation is a function of clock
frequency and the number of nodes changing on each
clock. In an LCA the fraction of nodes changing on a given
clock is typically low (10-20%). For example, in a 16-bit
binary counter, the average clock produces a change in
slightly less than 2 of the 16 bits. In a 4-input AND gate
there will be 2 transitions in 16 states. Typical global clock
buffer power is about 3 mW / MHz for the XC2064 and 4
mW / MHz for the XC2018. With a "typical" load of three
general interconnect segments, each Configurable Logic
Block output requires about 0.4 mW / MHz of its output
frequency. Graphs of power versus operating frequency
are shown in Table 1 on page 2-83.

The Logic Cell Array exhibits the low power consumption
characteristic of CMOS ICs. Only quiescent power is
required for the LCA configured for CMOS input levels.
The TTL input level configuration option requires additional
power for level shifting. The power required by the static
memory cells which hold the configuration data is very low
and may be maintained in a power-down mode.
Typically most of power dissipation is produced by capacitive loads on the output buffers, since the power per output
is 251lW / pF / MHz. Another component of I/O power is
the DC loading on each output pin. For any given system,
the user can calculate the I/O power requirement based on

II

GND

+--+--+--+--+--+--+--+
+--+--+--+--+--+--+--+
+--+--+--+--+--+--+--+
+--+--+--+--+--+--+--+
+--+--+--+--+--+--+--+
+--+--+--+--+-- , --+--+
,
,
+--+--+--+--+--+--+--+,
,
,
+--+--+--+--+--+--+--+
I

I

I

I

I

I

I

I

Vee

I
I

I
I

I

I

I

I

I

I

I

,

' I

I

I '
I
1

I
I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

GROUND AND
VeeRING FOR
1/0 DRIVERS

I

~--I-H~

LOGIC POWER GRID

GND
110412

Figure 11. LeA Power Distribution

2-71

XC206412018 Logic Cell Array

Input thresholds for user 110 pins can be selected to be
either TTL-compatible or CMOS-compatible. At powerup, all inputs are TTL-compatible and remain in that state
until the LCA begins operation. If the user has selected
CMOS compatibility, the input thresholds are changed to
CMOS levels during configuration.

PROGRAMMING

Configuration data to define the function and interconnection within a Logic Cell Array are loaded automatically
at power-up or upon command. Several methods of
automatically loading the required data are designed into
the Logic Cell Array and are determined by logic levels
applied to mode selection pins at configuration time. The
form ofthe data may be either serial or parallel, depending
on the configuration mode. The programming data are
independent of the configuration mode selected. The
state diagram of Figure 12 illustrates the configuration
process.

USER I/O PINS WITH

HII~H

Figure 13 shows the specific data arrangement for the
XC2064 device. Future products will use the same data
format to maintain compatibility between different devices
of the Xilinx p~oduct line, but they will have different sizes
and numbers of data frames. For the XC2064,

IMPEDANCE PULL-UP

HOC = HIGH
LOC = LOW

LOW ON DONE/PROGRAM AND RESET
CLEAR IS
~160 CYCLES FOR THE XC2064-100 TO 320 flS
~200 CYCLES FOR THE XC2016-125 TO 390 flS

110414

Figure 12. A State Diagram of the Configuration Process for Power-up and Re-program

11111111
0010
< 24·BIT LENGTH COUNT>
1111

a < DATA FRAME # 001>

a < DATA FRAME # 002 >
o < DATA FRAME #003 >

a

111
111
111

< DATA FRAME # 159> 111
111

a < DATA FRAME # 160 >
1111

J

DUMMY BITS (4 BITS MINIMUM), XACT 2.10 GENERATES 8 BTS
PREAMBLE CODE
CONFIGURATION PROGRAM LENGTH
DUMMY BITS (4 BITS MINIMUM)

I

CONFIGURATION
FRAMES
DATA BITS
PER FRAME

XC2018

XC2064

196

160

87

71

HEADER

PROGRAM DATA
REPEATED FOR EACH LOGIC
CELL ARRAY IN A DAISY CHAIN

POSTAMBLE CODE (4 BITS MINIMUM)

START·UP REQUIRES THREE CONFIGURATION CLOCKS BEYOND LENGTH COUNT
1104 1S

Figure 13. XC2064 Internal Configuration Data Arrangement

2-72

E:XiUNX
configuration requires 12,038 bits for each device. Forthe
XC2018, the configuration of each device requires 17,878
bits. The XC2064 uses 160 configuration data frames and
the XC2018 uses 197.

MODE PIN
MODE SELECTED

The configuration bit stream begins with preamble bits, a
preamble code and a length count. The length count is
loaded into the control logic of the Logic Cell Array and is
used to determine the completion of the configuration
process. When configuration is initiated, a 24-bit length
counter is set to 0 and begins to count the total number of
configuration clock cycles applied to the device. When the
current length count equals the loaded length count, the
configuration process is complete. Two clocks before
completion, the internal logic becomes active and is reset.
On the next clock, the inputs and outputs become active as
configured and consideration should be given to avoid
configuration signal contention. (Attention must be paid to
avoid contention on pins which are used as inputs during
configuration and become outputs in operation.) On the
last configuration clock, the completion of configuration is
signalled by the release of the DONE I PROG pin of the
device as the device begins operation. This open-drain
output can be AND-tied with multiple Logic Cell Arrays and
used as an active-High READY or active-Low, RESET, to
other portions of the system. High during configuration
(HOC) and low during configuration (LDC), are released
one CCLK cycle before DONE is asserted. In master
mode configurations, it is convenient to use LDC as an
active-Low EPROM chip enable.

MO

Ml

M2

0

0

0

MASTER SERIAL

0

0

1

MASTER LOW MODE

0

1

1

MASTER HIGH MODE

1

0

1

PERIPHERAL MODE

1

1

1

SLAVE MODE

MASTER LOW ADDRESSES BEGIN AT 0000 AND INCREMENT
MASTER HIGH ADDRESSES BEGIN AT FFFF AND DECREMENT
110413

FIgure 14. ConfIguration Mode Selection

Initialization Phase
When power is applied, an internal power-on-reset circuit
is triggered. When Vcc reaches the voltage at which the
LCA begins to operate (nominally 2.5 to 3 V), the chip is
initialized, outputs are made high-impedance and a timeout is initiated to allow time for power to stabilize. This
time-out (11 to 33 ms) is determined by a counter driven
by a self-generated, internal sampling clock that drives the
configuration clock (CCLK) in master configuration mode.
This internal sampling clock will vary with process,
temperature and power supply over the range of 0.5 to
1.5 MHz. LCAs with mode lines set for master mode will
time-out of their initialization using a longer counter (43 to
130 ms) to assure that all devices, which it may be driving
in a daisy chain, will be ready. Configuration using
peripheral or slave modes must be delayed long enough
for this initialization to be completed.

As each data bit is supplied to the LCA, it is intemally
assembled into a data word. As each data word is
completely assembled, it is loaded in parallel into one word
of the internal configuration memory array. The last word
must be loaded before the current length count compare
is true. If the configuration data are in error, e.g., PROM
address lines swapped, the LCA will not be ready at the
length count and the counter will cycle through an additional complete count prior to configuration being "done".

The initialization phase may be extended by asserting the
active-Low external RESET. If a configuration has begun,
an assertion of RESET will initiate an abort, including an
orderly clearing of partially loaded configuration memory
bits. After about three clock cycles for synchronization,
initialization will require about 160 additional cycles of the
internal sampling clock (197 for the XC2018) to clear the
internal memory before another configuration may begin.
Reprogramming is initialized by a High-to-Low transition
on RESET (after RESET has been High for at least 6~)
followed by a Low level (for at least 6 ~) on both the
RESET and the .open-drain DONEIPROG pins. This returns the LCA to the CLE~R state, as shown in Fig. 12.

Figure 14 shows the selection of the configuration mode
based on the state of the mode pins MO and M1. These
package pins are sampled prior to the start of the
configuration process to determine the mode to be used.
Once configuration is DONE and subsequent operation
has begun, the mode pins may be used to perform data
readback, as discussed later. An additional mode pin,
M2, must be defined at the start of configuration. This
package pin is a user-configurable 110 after configuration
is complete.

2-73

XC206412018 Logic Cell Array

Master Mode

significant bit of each byte, normally DO, is the next bit in the
serial stream.

In Master mode, the Logic Cell Array automatically loads
the configuration program from an external memory device. Figure 15a shows an example of the Master mode
connections required. The Logic Cell Array provides 16
address outputs and the control signals RCLK (Read
Clock), HOC (High during configuration) and LOC (Low
during configuration) to execute Read cycles from the
external memory. ParallelS-bit data words are read and
internally serialized. As each data word is read, the least

Addresses supplied by the Logic Cell Array can be selected by the mode lines to begin at address 0 and
incremented to reach the memory (master Low mode), or
they can begin at address FFFF Hex and be decremented
(master High mode). This capability is provided to allow
the Logic Cell Array to share external memory with another
device, such as a microprocessor. For example, if the
processor begins its execution from Low memory, the

r-+-------~~~-r-+5V

• IF READBACK IS
ACTIVATED. A
5-kll RESISTOR IS
REQUIRED IN
SERIES WITH M1
5kll

USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT FROM
ALTERNATIVE CONFIGURATIONS

OPTIONAL

DoUT
CCLK

M2

DAISY-CHAINED
LCAs WITH DIFFERENT
CONFIGURATIONS

HOC
A15

GENERALPURPOSE
USER 110
PINS

RCLK

AU

} OTHER
VO PINS

A13

EPROM

A12

OR~~G6ER)

A11
A1a

A1a

RESET

A9

A9

07

A6

A8

A7

A7

D5

AS

A6

D4

A5

A5

03

A4

A4

02

A3

A3

D1

A2

A2

DO

A1

A1

AO

AO

LDC

OE

D6

LeA

Dip

DONE

CE

DATA BUS

(OC~~~~ _ _ _---IX ~O~"

01

:

cd

0~D7---N--1-B-~-E~XXXXX~~~-~-~---P-R-OM~:~-----BY-T-E-N--C====XXXXX~~~--B~YT~E~N~+1-----

(OUT~~L~

1/8 CCLK

-{

f

\

I1+_________-=-;7c;;;;~====::j.
8 CCLKs

\....._---

(OUTPUT)
C C L K =

j60iBYTEF iOiBYTE0 j)OOiBYTEN

(ouf~uU~

X1011

Figure 15a. Master Parallel Mode. Configuration data are loaded automaticaly from an external byte wide PROM.
An XC2000 LDC signal can provide a PROM inhibit as the user lias become active.

2-74

Logic Cell Array can load itself from High memory and
enable the processor to begin execution once configuration is completed. The Done/PROG output pin can be
used to hold the processor in a Reset state until the Logic
Cell Array has completed the configuration process

Figure 16 shows the peripheral mode connections.
Processor Write cycles are decoded from the common
assertion of the active-Low write strobe (IOWRT), and two
active-Low and of the active-High chip selects (CSO CS1
CS2). If all these signals are not available, the unused
inputs should be driven to their respective active levels.
The Logic Cell Array will accept one bit of the configuration
program on the data input (DIN) pin for each processor
Write cycle. Data is supplied in the serial sequence
described earlier.

The Master Serial mode uses serial configuration data,
synchronized by the rising edge of CCLK, as shown in
Figure 15b.

Peripheral Mode (Bit Serial)

Since only a single bit from the processor data bus is
loaded per cycle, the loading process involves the processor reading a byte or word of data, writing a bit of the
data to the Logic cell Array, shifting the word and writing a

Peripheral mode provides a simplified interface through
which the device may be loaded as a processor peripheral.

• IF READBACK IS
ACTIVATED, A
5·kO RES ISTOR IS
REOUIRED IN
SERIES WITH M1
DURING CONFIGURATION
THE 5 kO M2 PULL·DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL·UP.
BUT IT ALLOWS M2 TO
BE USER 110.

.

.

-=i::'--

-

GENERAL·
PURPOSE
USER VO
PINS

+r

I I
MO

II

M1 PWRDWN

DOUT

OPTIONAL
___ DAISY·CHAINED
LCA.WITH

M2

---

8~~~[i,EJlJATIONS

HOC

--< LDC

-

}~"

110 PINS

-

LCA

OPTIONAL

Wfr~1~~:~ICAL

-

--- CONFIGURATIONS
+5V

RESET

-r-<

~

RESET
DIN
CCLK
LDC

DONE-

r- DIP

Vpp
Vee
DATA SERIAL
MEMORY
CLK

r

CE

CEO

~C1736A1XC1765

....
....

r- .. - .. --- .. -.--------

---i

P---~

CASCADED
SERIAL
MEMORY

:

(HIGH RESETS THE XC1736A1XC1765 ADDRESS POINTER)

"~~
'~~
(OUTPUT)
X1013

Figure 15b. Master Serial Mode. The one time programmable XC1736A Serial Configuration PROM
supports automatic loading of configuration programs up to 36 Kbits. Multiple XC1736As can be cascaded to
support additional LCAs. An XC2000 LOC signal can provide an XC1736A inhibit as the user IIOs become active.

2-75

XC206412018 Logic Cen Array

bit until all bits of the word are written, then continuing in
the same fashion with the next word, etc. After the
configuration program has been loaded, an additional
three clocks (a total of three more than the length count)
must be supplied in order to complete the configuration
process. When more than one device is being used in the
system, each device can be assigned a different bit in the
processor data bus, and multiple devices can be loaded on
each processor write cycle. This "broadside" loading
method provides a very easy and time-efficient method of
loading several devices.

LCA in the chain, and the clock is supplied by the lead
device, which is configured in master or peripheral mode.
After the configuration program has been loaded, an
additional three clocks (a total of three more than the
length count) must be supplied in order to complete the
configuration process.
Daisy Chain
The daisy-chain programming mode is supported by Logic
Cell Arrays in all programming modes. In master mode
and peripheral mode, the LCA can act as a source of data
and control for slave devices. For example, Figure 18
shows a single device in master mode, with 2 devices in
slave mode. The master mode device reads the external
memory and begins the configuration loading process for
all of the devices.

Slave Mode
Slave mode, Figure 17, provides the simplest interface for
loading the Logic Cell Array configuration. Data is supplied in conjunction with a synchronizing clock. For each
Low-to-High input transition of configuration clock (CCLK),
the data present on the data input (DIN) pin is loaded into
the internal shift register. Data may be supplied by a
processor or by other special circuits. Slave mode is used
for downstream devices in a daisy-chain configuration.
The data for each slave LCA are supplied by the preceding

ADDRESS
BUS

The data begin with a preamble and a length count which
are supplied to all devices at the beginning of the configuration. The length count represents the total number of
cycles required to load all oft he devices in the daisy chain.
After loading the length count, the lead device will load its

DATA
BUS

• IF READBACK IS
ACTIVATED. A
5-kn RESISTOR IS
REQUIRED IN SERIES
WITHMl
DIN

CCLK

WRT
DOUT

OPTIONAL
DAISY·CHANED
LCAs WITH DIFFERENT
CONFIGURATIONS

M2
ADDRESS
DECODE
LOGIC

CSO

LDC

CSl
CS2
DONE
RESET

HDC

:"1

GENERAL·
PURPOSE
USER 110
PINS

va PINS

DIP
RESET

WRT
CSO
CSI

CS2
CCLK
(OUTPUT)
DIN
DOUT
(OUTPUT)

1104 1SA

Figure 16. Peripheral Mode. Configuration data are loaded using serialized data from a microprocessor.

2-76

E:XJUNX
tion is complete to allow time for stabilization before it is
connected to the internal circuitry.

configuration data while providing a High DOUT to downstream devices. When the lead device has been loaded
and the current length count has not reached the full value,
memory access continues. Data bytes are read and
serialized by the lead device. The data are passed through
the lead device and appear on the data out (DOUT) pin in
serial form. The lead device also generates the configuration clock (CCLK) to synchronize the serial output data. A
master mode device generates an internal CCLK of
8 times the EPROM address rate, while a peripheral mode
device produces CCLK from the chip select and write
strobe timing.

SPECIAL CONFIGURATION FUNCTIONS
In addition to the normal user logic functions and interconnect, the configuration data include control for several
special functions:
•
•
•
•

Operation

Input thresholds
Readback disable
Reprogram
DONE pull-up resistor

Each of these functions is controlled by a portion of the
configuration program generated by the XACT Development System.

When all of the devices have been loaded and the length
count is complete, a synchronous start-up of operation is
performed. On the clock cycle following the end of loading,
the internal logic begins functioning in the reset state. On
the next CCLK, the configured output buffers become
active to allow signals to stabilize. The next CCLK cycle
produces the DONE condition. The length count control of
operation allows a system of multiple Logic Cell Arrays to
begin operation in a synchronized fashion. If the crystal
oscillator is used, it will begin operation before configura-

Input Thresholds
During configuration, all input thresholds are TTL level.
During configuration input thresholds are established as
specified, either TTL or CMOS. The PWRDWN input
threshold is an exception; it is always a CMOS level input.
The TTL threshold option requires additional power for
threshold shifting.

• IF READBACK IS
ACTIVATED. A
5-kn RESISTOR IS
REQUIRED IN SERIES
wrrHM1

+5V

5kn

MICRO
COMPUTER
CCLK

STRB

DIN

DO

YO
PORT

M2
DOUT

D1

HDC

D2

LDC

D3

LCA

_

OPTIONAL
DAISY-CHANED
LCAs WITH DIFFERENT
CONFIGURATIONS

GENERALPURPOSE
USER 1/0
PINS

D4
OTHER {

D5

1/0 PINS

DIP

D6
D7
RESET

DIN

=:x

BIT N

X,I

BITN+1

I~'----t"-----'-·'----------

-'I

CCLK _ _ _

"''-~_-:--__-II

DOUT--------------------::3XXX·~------(OUTPUT)
BITN-1
_
_
BrrN

11041SA

Figure 17. Slave Mode. Bit-serial configuration data are read at rising edge of the CCLK. Data on DOUr are
provided on the falling edge of CCLK. Identically configured non-master mode LCAs can be configured in parallel
by connecting DINs and CCLKs.

2-77

II

XC206412018 Logic Cell Array

Readback

guarantees that the LCA will return to the Clear state.
Either of these methods may be needed in the event of an
incomplete voltage interruption. They are not needed for a
normal application of power from an off condition.

After a Logic Cell Array has been programmed, the configuration program may be read back from the device.
Readback may be used for verification of configuration,
and as a method of determining the state of intemallogic
nodes during debugging. Three readback options are
provided: on command, only once, and never.

DONE Pull-up
The DONE I PROG pin is an open drain I/O that indicates
programming status. As an input, it initiates a reprogram
operation. An optional internal pull-up resistor maybe
enabled.

An initiation of readback is produced by a Low-to-High
transition of the MO I RTRIG (read trigger) pin. Once the
readback command has been given, CCLK is cycled to
read back each data bit in a format similar to loading. After
two dummy bits, the first data frame is shifted out, in
inverted sense, on the M11 RDATA (read data) pin. All
data frames must be read back to complete the process
and return the mode select and CCLK pins to their normal
functions. Readback data includes the state of all internal
storage elements. This information is used by the Logic
Cell Array development system In-Circuit Debugger to
provide visibility into the internal operation of the logic
while the system is operating. To read back a uniform time
sample of all storage elements, it may be necessary to
inhibit the system clock.

Battery Backup
Because the control store of the Logic Cell Array is a
CMOS static memory, its cells require only a very low
standby current for data retention. In some systems, this
low data retention current characteristic facilitates preserving configurations in the event of a primary power loss.
The Logic Cell Array has built in power-down logic which,
when activated, will disable normal operation of the device
and retain only the configuration data. All internal operation is suspended and all output buffers are placed in their
high impedance state.
Power-down data retention is possible with a simple battery-backup circuit because the power requirement is
extremely low. For retention at 2.0 V, the required current
is typically on the order of 500 nA. Screening to this
parameter is available. To force the Logic Cell Array into
the power-down state, the user must pull the PWRDWN
pin Low and continue to supply a retention voltage to the
Vcc pins of the package. When normal power is restored,
Vcc is elevated to its normal operating voltage and
PWRDWN is returned to a High. The Logic Cell Array
resumes operation with the same internal sequence that
occurs at the conclusion of configuration. Internal I/O and
logiC block storage elements will be reset, the outputs will
become enabled and then the DONE/PROG pin will be
released. No configuration programming is involved.

Re~program

The Logic Cell Array configuration memory may be rewritten while the device is operating in the user's system.
The LCA returns to the Clear state where the configuration
memory is cleared, I/O pins disabled, and mode lines resampled. Re-program control is often implemented using
an external open collector driver which pulls DON ElPROG
LOW. Once it recognizes a stable request, the Logic Cell
Array will hold DONEiPROG LOW until the new configuration has been completed. Even if the DONEI'jS"R()G pin
is externally held LOW beyond the configuration period,
the Logic Cell Array will begin operation upon completion
of configuration. To reduce sensitivity to noise, these reprogram signals are filtered for 2-3 cycles of the LCA's
internal timing generator (2 to 6 ~). Note that the Clear
time out for a Master mode re-program or abort does not
have the 4 times delay of the Initialization state. If a daisy
chain is used, an external RESET is required,long enough
to guarantee clearing all non-master mode devices. For
XC2000 series LCAs this is accomplished with an external
time delay.

PERFORMANCE
The high performance of the Logic Cell Array results from
its patented architectural features and from the use of an
advanced high-speed CMOS manufacturing process.
Performance may be measured in terms of minimum
propagation times for logic elements.

In some applications the system power supply might have
momentary failures which can leave the LCA's control
logic in an invalid state. There are two metods to recover
from this state. The first is to cycle the Vee supply to less
than 0.1 Volt and reapply valid Vcc. The second is to
provide the LCA with simultaneous Low levels of at least
6 ~ on RESET and DONEIPROG pins after the RESET
pin has been High following a return to valid Vee. This

Flip-flop loop delays for the I/O block and logic block flipflops are about 3 ns. This short delay provides very good
performance under asynchronous clock and data
conditions. Short loop delays minimize the probability of a
metastable condition which can result from assertion of

2-78

.

+5V

5kil

l+
-

1 I

+5V

MO M1 PWRDWN

CCLK

~

!----

DIN

....
t---

A14

A14

LDC

Pt---

A12

A11

A11

A10
LCA
MASTER
A9

A10
A9

~ D7

AS

AS

V--

D6

A7

A7

D7

V--

D5

AS

AS

D6

V-V-V-V--

D4

AS

AS

05

D3

A4

A4

04

D2

A3

A3

D3

D1

A2

A2

02

DO

A1

A1

D1

AD

AO

DO

LDC

OE

lr

M2
HDC

A13
EPROM

OTHER
I/O PINS

-il

_._--- A15

A12

--< RESET
D/P

L

-

5kil

A15

A13

.

I I

L

MO r,.t1 PWRDWN

DOUT
LCA
SLAVE #1

HDC

-

V--

CCLK

M2

-

+5V

I I !
MO M1 PWRDWN

DOUT

--< RCLK
GENERALPURPOSE
USER VO
PINS

T

-H-

.

CCLK

5kil

DIN

...

LCA
SLAVE #n

GENERALPURPOSE
USER 1/0
PINS

LDC

0--

-

OTHER {

GENERALPURPOSE
USER I/O
PINS

OTHER{

1/0 PINS

-

f-

-

DIP

r<

~

M2
HDC

110 PINS

-

I-

DOUT

DIP

r<

RESET

"

"
""
"
"
"
"

RESET

NOTE: R10SET OF A MASTER
DEVICE SHOULD BE ASSE RTED
BY AN EXTERNAL TIMING
CIRCUIT TO ALLOW FOR LCACCLK
VARIATIONS IN CLEAR STATETIME.
• IF READBACK IS
ACTIVATED. A
5-kil RESISTOR IS
REQUIRED IN
SERIES WITH M1

,--+5 V

CE

5kil

S
OPEN
"

REPROGRAM
SYSTEM RESET

4J

COLLECTOR

V

"
II

J

1104 2M

Figure 18. Master Mode Configuration with Daisy.Chained Slave Mode Devices.
All are configured from the common EPROM source. A well defined termination of
SYSTEM RESET is needed when controlling multiple LCAs.
Any XC3000 slave driven by an XC2000 master mode device must use "early DONE and early internal reset".
(The XC2000 master will not supply the extra clock required by a "late" programmed XC3000_)

2-79

II

XC206412018 Logic Cell Array

the clock during data transitions. Because of the short
loop delay characteristic in the LCA device, the I/O block
flip-flops can be used very effectively to synchronize
external signals applied to the device. Once synchronized
in the I/O block, the signals can be used internally without
further consideration of their clock relative timing, except
as it applies to the internal logic and routing path delays.

Logic Block Performance
Logic block propagation times are measured from the
interconnect point at the input of the combinatorial logic to
the output of the block in the interconnect area. Combinatorial performance is independent of logic function
because of the table look-up based implementation.
Timing is different when the combinatorial logic is used in
conjunction with the storage element. Forthe combinatorial logic function driving the data input of the storage
element, the critical timing is data set-up relative to the
clock edge provided to the storage element. The delay
from the clock source to the output of the logic block is
critical in the timing of signals produced by storage elements. The loading on a logic block output is limited only
by the additional propagation delay of the interconnect
network. Performance of the logic block is a function of
supply voltage and temperature, as shown in Figure 22 .

Device Performance
The single parameter which most accurately describes the
overall performance of the Logic Cell Array is the maximum toggle rate for a logic block storage element configured as a toggle flip-flop. The configuration for determining the toggle performance of the Logic Cell Array is shown
in Figure 19. The clock forthe storage elementis provided
by the global clock buffer and the flip-flop output Q is fed
back through the combinatorial logic to form the data input
forthe next clock edge. USing this arrangement, flip-flops
in the Logic Cell Array can be toggled at clock rates from
33-70 MHz, depending on the speed grade used.

Interconnect Performance
Interconnect performance depends on the routing resource used to implement the signal path. As discussed
earlier, direct interconnect from block to block provides a
minimum delay path for a signal.

Actual Logic Cell Array performance is determined by the
critical path speed, including both the speed of the logic
and storage elements in that path, and the speed of the
particular network routing. Figure 20 shows a typical
system logic configuration of two flip-flops with an extra
combinatorial level between them. Depending on speed
grade, system clock rates to 35 MHz are practical for this
logic. To allow the user to make the best use of the
capabilities of the device, the delay calculator in the XACT
Development System determines worst-case path delays
using actual impedance and loading information.

o

Q

The single metal segment used for long lines exhibits low
resistance from end to end, but relatively high capacitance. Signals driven through a programmable switch
will have the additional impedance of the switch added to
their normal drive impedance.
General-purpose interconnect performance depends on
the numberof switches and segments used, the pre-sence
of the bidirectional repowering buffers and the overall
loading on the signal path at all points along the path. In
calculating the worst-case delay for a general interconnect
path, the delay calculator portion of the XACT development system accounts for all of these elements. As an
approximation, interconnect delay is proportional to the
summation of totals of local metal segments beyond each
programmable switch. In effect, the delay is a sum of
R-C delays each approximated by an R times the total C
it drives. The R of the switch and the C of the interconnect
are functions of the particular device performance grade.
For a string of three local interconnects, the approximate
delay at the first segment, after the first switch resistance,
would be three units; an additional two delay units after the
next switch plus an additional delay after the last switch in
the chain. The interconnect R-C chain terminates at each
repowering buffer. Nearly all of the capacitance is in the
interconnect metal and switches; the capacitance of the
block inputs is not significant. Figure 21 shows an estimation of this delay.

1--_-:'-_ X,V

K-4·:-----------~

110421

Figure 19. Logic Block Configuration for
Toggle Rate Measurement

2-80

~XIIJNX

COMBINATORIAL CLB

DESTINATION CLB

o

INPUTS

D

0···················_·-

GLOBAL
CLOCK

II
1104 22

Figure 20. Typical Logic Path

SWITCH
• ___ . ___ /MATRIX ........... ___ . __ _
CLB

R1

I

:

R3

TIMING: INCREMENTAL
~

IF R1 = R2 = R3 = RAND C1 = C2 = C3 = C

+R3C3

THEN CUMULATIVE TIMING
T1 =3RC
=3RC

T2 = 3RC + 2RC

T3 = 3RC + 2RC + 1RC

=5RC

=6RC

6AC + BUFFER

110523B

Figure 21. Interconnection Timing Example. Use of the XACT timing calculator
or XACT-generated simulation model provides actual worst-case performance information.

2-81

XC206412018 Logic Cell Array

1.00

0.80

TYPICAL COMMERCIAL
(+ 5.0 v, 25'C)

•

TYPICAL MILITARY

•

0.40

I

0.20

~.~; ~

MIN COMMERCIAL
•• llIttl.M!IJ1.AFY i 4X'l ••• -:
N
MME IAL·
••• ---.
MI ••• _ _
••• - - -.
MIN MII;!'0£lY i 5"S}2 -. -.'

.---

t:::~~:·-·-·--········-55

-40

---------------

____ - - - - - - - - - - - - -

-20

o

25

40

---------------

70

80

100

125

TEMPERATURE ('G)
X1045

Figure 22. Relative Delay as a function of Temperature, Supply Voltage and Processing Variations.

2-82

100
90

L

50

/

10 0

0

/

/

/

/

/

/

/

/

/

0

V

/

/

/

L

20 CLB OUTPUTS 4

I

/

V
V
}/
/
V

./

./

.I

.I

/

1110 OUTPUT

(50pF) 0.5
0.5

V

"

1

/

V

/

V

/

II

(rnA)

L

V

/

/

/

/
2

.9

.8
.7

.6

L

.5
.4

V

/

/

10
9

./
./

/

/

GLOBAL CLOCK
BUFFER

L

./

/

2

/

/

/

/

./
./

3 LOCAL SEGMENTS
EACH 3

V

/

V

20

/

./

./

20

30

./
./

/

(mW)

V

/

./
./

./

0

(1.25 mWIMHz)

V

V

40

(3mWIMHz)

40

/

/

70
60

/
150

80

.3

V

.2

.1

10

2

20

30

40

50

FREQUENCY MHz

(0.4 mWIMHz) /
1 CLB OUTPUT
3 LOCAL
INTERCONNECT

110427

Table 1. Typical LCA Power Consumption By Element

2-83

XC2064/2018 Logic Cell Array

DEVELOPMENT SYSTEMS
PIN DESCRIPTIONS
To accomplish hardware development support for the
Logic Cell Array, Xilinx provides a development system
with several options to support added capabilities. The
XACT system provides the following:
•
•
•
•
•
•
•
•
•
•
•

Permanently Dedicated Pins.

Vee
One or two (depending on package type) connections to
the nominal +5 V supply voltage. All must be connected.

Schematic entry
Automatic place and route
Interactive design editing for optimization
Interactive timing calculations
Macro library support, both for standard Xilinx
supplied functions and user defined functions
Design entry checking for consistency and
completeness
Automatic design documentation generation
PROM programmer format output capabilities
Simulation interface support including automatic
nellist (circuit description) and timing extraction
Logic and timing simulation
In-circuit design verification for multiple devices

GND
One or two (depending on package type) connections to
ground. All must be connected.
PWRDWN
A Low on this CMOS-compatible input stops all internal
activity, but retains configuration. All flip-flops and latches
are reset, all outputs are 3-stated, and all inputs are
interpreted as High, independent of their actual level.
While PWRDWN is Low, Vcc may be reduced to any value
>2.3 V. When PWDWN returns High, the LCA becomes
operational with DONE Low for two cycles of the internal
1-MHz clock. During configuration, PWRDWN must be
High. If not used, PWRDWN must be tied to Vcc'

The host system on which the XACT system operates is
an IBM PC/AT or compatible system with DOS 3.0 or
higher. The system requires 640K bytes of internal RAM,
3 Mbyte of Extended Memory, color graphics and a
mouse. A complete system requires one parallel I/O port
and two serial ports for the mouse and in-circuit emulation.

RESET
This is an active Low input which has three functions.
Prior to the start of configuration, a Low input will delay the
start of the configuration process. An internal circuit
senses the application of power and begins a minimal
time-out cycle. When the time-out and RESET are complete, the levels of the M lines are sampled and configuration begins.

Designing with the XACT Development System
Designing with the Logic Cell Array is similar to using
conventional MSI elements or gate array cells. A range of
supported packages, including FutureNet and VI EWlogic,
provide schematic capture with elements from a macro
library. The XACT development system then translates
the schematic description into partitioned Logic Blocks
and 110 Blocks, based on shared input variables or efficient
use of flip-flop and combinatorial logic. DeSign entry can
also be implemented directly with the XACT development
system using an interactive graphic design editor. The
design information includes both the functional specifications for each block and a definition of the interconnection
networks. Automatic placement and routing is available
for either method of design entry. After routing the interconnections, various checking stages and processing of
that data are performed to insure that the design is correct.
Design changes may be implemented in minutes. The
design file is used to generate the programming data
which can be down loaded directly into an LCA in the user's
target system and operated. The program information
may be used to program PROM, EPROM or ROM devices,
or stored in some other media as needed by the final
system. Design verification may be accomplished by
using the XACTOR In-Circuit Design Verifier directly in the
target system and/or the P-SILOS logic simulator.

If RESET is asserted during a configuration, the LCA
device is re-initialized and restarts the configuration at the
termination of RESET.

If RESET is asserted after configuration is complete, it
provides a global asynchronous reset of all lOB and CLB
storage elements of the LCA device.
RESET can also be used to recover from partial power
failure. See section on Re-program under "Special Configuration Functions."
CCLK
During configuration, Configuration Clock is an output of
an LCA in Master mode or Peripheral mode, but an input
in Slave mode. During a Readback, CCLK is a clock input
for shifting configuration data out of the LCA
CCLK drives dynamic circuitry inside the LCA. The Low
time may, therefore, not exceed a few microseconds.
When used as an input, CCLK must be "parked High". An
internal pull-up resistor maintains High when the pin is not
being driven.

2-84

l::XIUNX
XTL1

DONE
DON E is an open-drain output, configurable with or without an internal pull-up resistor. At the completion of
configuration, the LCA circuitry becomes active in a synchronous order, and DONE is programmed to go active
High either one cycle before or after the outputs go active.

This user 1/0 pin can be used to operate as the output of
an amplifier driving an external crystal and bias circuitry.

XTL2
This user 1/0 pin can be used as the input of an amplifier
connected to an external crystal and bias circuitry. The
1/0 Block is left unconfigured. The oscillator configuration
is activated by routing a net from the oscillator buffer
symbol output and by the MAKEBITS program.

PROG
Once configuration is done, a High-to-Low transition of
this pin will cause an initialization of the LCA and start a
reconfiguration.

CSO,CS1,CS2,VVRT

MO

These four inputs represent a set of signals, three active
Low and one active High, that are used to control
configuration-data ehtry in the Peripheral mode.
Simultaneous assertion of all four inputs generates a
Write to the internal data buffer. The removal of any
assertion clocks in the 00-07 data. In Master mode,these
pins become part of the parallel configuration byte, 04,03,
02, 01. After configuration, these pins are userprogrammable 1/0 pins.

As Mode 0, this input and M1, M2 are sampled before the
start of configuration to establish the configuration mode to
be used.

RTRIG
A Low-to-High input transition, aiter configuration is complete, acts as a Read Trigger and initiates a Readback of
configuration and storage-element data clocked by CCLK.
By selecting the appropriate Readback option when generating the bitstream, this operation may be limited to a
single Readback, or be inhibited altogether.

RCLK
During Master parallel mode configuration RCLK represents a "read" of an external dynamic memory device
(normally not used).

M1
As Mode 1, this input and MO, M2 are sampled before the
start of configuration to establish the configuration mode to
beused. If Readback isneverused, M1 can be tied directly
to ground or Vee' If Readback is ever used, M1 must use
a 5-kQ resistor to ground or Vee' to accommodate the
RDATA output.

00-07
This set of eight pins represents the parallel configuration
byte for the parallel Master mode. After configuration is
complete they are user programmed 1/0 pins.

AO-A15
During Master Parallel mode, these 16 pins present an
address output for a configuration EPROM. After configuration, they are user-programmable 1/0 pins.

ROATA
As an active Low Read Data, after configuration is
complete, this pin is the output of the Readback data.
User 1/0 Pins that can have special functions.

DIN
During Slave or Master Serial configuration, this pin is
used as a serial-data input. In the Master or Peripheral
configuration, this is the Data 0 input.

M2
During configuration, this input has a weak pull-up resistor.
Together with MO and M1, it is sampled before the start of
configuration to establish the configuration mode to be
used. After configuration, this pin is a user-programmable
1/0 pin.

OOUT
During configuration this pin is used to output serialconfiguration data to the DIN pin of a daisy-chained slave.

HOC
During configuration, this output is held at a High level to
indicate that configuration is not yet complete. After
configuration, this pin is a user-programmable 1/0 pin.

TCLKIN
This is a direct CMOS level input to the global clock buffer.
Unrestricted User 1/0 Pins.
1/0
An I/O pin may be programmed by the user to be an Input
or an Output pin following configuration. All unrestricted
1/0 pins, plus the special pins mentioned on the following
page, have a weak pull-up resistor of 40 to 100 kQ that
becomes active as soon as the device powers up, and
stays active until the end of configuration.

LOC
During Configuration, this output is held at a Low level to
indicate that the configuration is not yet complete. After
configuration, this pin is a user-programmable 1/0 pin.
LDC is particularly useful in Master mode as a Low enable
foran EPROM, but it must then be programmed as a High
after configuration.

2-85

II

XC206412018 Logic Cell Array
r:,,.FIr.IIRATlnN MODE: 

~O:O:O;

:,~~~

I .~:; ~O~O~'

PE~f:~~~L I"~ ;,~~o,:'

, DIP IPLCC

GNC
3
4
5
6

A6 (Ol
A12 (0)
..<~~IGH~~.
A;
0)
A8 (0)
A10 (0)
A9 (D)

PWRDWI'I
9

13

~~~:~~~~.
16

:::::::::.M2

,:M1(LO""
MO (HIGH

.ow

MO

HOC HIG
,.~.

GND

15
16

12
13

USER
OPERATION

B6
A6
B5
AS
B4
A4
B3
A3

E2
E'
F2
F1
G2
G1
H2
H'
J2

•••••••••••••••••••

VC

p~

VO

110

VC

110

RTRIGiIl

110

LVW)

22
. «HIGH»
GND

:.

..
DONE,

23
24

26
27

. :,.: .•••••·I •••••. j :
31
32

. «H.I.GH~~.

0<

39
40

57
58

C11

42
43
44

60 ,B1
61 ' B10
62 'A10

46

64
65
66
6)

37

m:
I
'1.0)

AO
A'

~~HiGH

A3
A15
A4
A14
AS

',".

47

110

~.

GND

25

A9
B8
A8

11.0

va

Bl

«HIGH:>;> IS HIGH IMPEDANCE WITH A 20--50 kn INTERNAL PULL-UP DURING CONFIGURATION
11042M

Table 2a. XC2064 Pin Assignments
A PLCC in a "PGA-Footprint" socket has a different signal pinout than a PGA device,

2-86

USER
OPERATION

3

•••••••••••••••••••••••••••••

5

1

C5

I/O

(0)

•

1 A2

10

1 B3

•

1

Al

1012 1 B2
13 1 C2

15

1

,.

Dl

26

,HIGH»

26
27
2.

I

I/O

1 E3

I/O

II

~~~~~:~I
33
~34

1K2
1 K3
112_

11O

I

··.~~HIG~~'

«HIGfb,

3.

1J5

35

43

IJ6

3•

• 47

1L6
1L6

GND

I/O

110

51

. 63

52~ ~M

1G9
1

F9

! D1

I/O

60

A4
A14

I/O
"
67

80
.,

,AS
'B6
, B7.

••••••••••••••••••••••
«HIGH» IS HIGH IMPEDANCE WITH A 20-50 kn INTERNAL PULL-UP DURING CONFIGUJ'lATION

110429A

Table 2b. XC2018 Pin Assignments

2-87

XC206412018 Logic Cell Array

Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.

ABSOLUTE MAXIMUM RATINGS

Symbol Description

Units

Vee

Supply voltage relative to GND

-0.5 to +7.0

V

VIN

Input voltage with respect to GND

-0.5 to Vee +0.5

V

VTS

Voltage applied to 3-state output

-0.5 to Vee +0.5

V

TSTG

Storage temperature (ambient)

-65 to +150

°C

TSOL

Maximum soldering temperature (105 @ 1/16 in.)

+260

°C

Note:

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings
conditions for extended periods of time may affect device reliability.

OPERATING CONDITIONS

Symbol
Vec

Min

Max

Units

4.75

5.25

V

-40°C to +85°C

4.5

5.5

V

-55°C to +125°C

4.5

5.5

V

Description
Supply voltage relative to GND

Commercial

Supply voltage relative to GND

Industrial

Supply voltage relative to GND

Military

O°C to +70°C

VIHT

High-level input voltage - TIL configuration

2.0

Vee

V

VILT

Low-level input voltage - TIL configuration

0

0.8

V

VIHC

High-level input voltage - CMOS configuration

70%

100% Vce

VllC

Low-level input voltage - CMOS configuration

0

20%

Vce

TIN

Input signal transition time

250

ns

2-88

DC CHARACTERISTICS OVER OPERATING CONDITIONS

Symbol

Description

Min

=-4.0 ma Vcc min)

VOH

High-level output voltage (@ IOH

VOL

Low-level output voltage (@ IOL = 4.0 ma Vcc max)

VOH

High-level output voltage (@ IOH

VOL

Low-level output voltage (@

VCCPD

Power-down supply voltage (PWRDWN must be Low)

Icco

Quiescent operating power supply current

=-4.0 ma Vcc min)

h =4.0 ma Vcc

max)

Commercial

Max

V

3.86
0.32

Industrial
Military

Units

3.76

V
V

0.37

V
V

2.3

CMOS thresholds (@ Vcc Max)

5

mA

TTL thresholds (@ Vcc Max)

12

mA

500

IlA

+10

IlA

10
15

pF
pF

ICCPD

Power-down supply current (VCC(MAX) @ TMAX)

IlL

Input Leakage Current

CIN

Input capacitance (sample tested) All Pins except XTL 1 and XTL2
XTL 1 and XTL2

-10

2-89

II

XC206412018 Logic Cell Array

CLB SWITCHING CHARACTERISTIC GUIDELINES

x

INPUT (A,B,C,D)

x

~G)TILO~

XX

OUTPUT (X,Y)
(COMBINATORIAL)

® TITO
OUTPUT (X,V)
(TRANSPARENT LATCH)

I--- CD

TICK

CLOCK(K)

ruo

TCKI4

J

1---0

CD TCCI--II

Tlcc

CLOCK (C)

1-0

TICI

CLOCK (G)

® TclI -

J

1+-0 TCKO~
@Tcco~

@

TCIO----to

XX

OUTPUT (VIA FF)

-fI

SET/RESET DIRECT (A,D)

1.

SET/RESET DIRECT (F,G)

I

@

TRIO

@

TRLO

t:=@TCH
CLOCK (ANY SOURCE)

-/-

-----'

110430

2-90

CLB SWITCHING CHARACTERISTIC GUIDELINES (Continued)

Speed Grade
Description

-50

-100

-70

Symbol

Min Max

TllO
TITO
Tolo

Min

Max

Min Max

15
20

10
14

7.5
10

ns
ns

8

6

6

ns

7
0

ns
ns
ns

9
5
0

ns
ns
ns

Combinatorial
Transparent latch
Additional for Q
through F or G to out

1
2

To output
Logic-input setup
Logic-input hold

9
3
4

TcKO
TICK
TCKI

9
0

To output
Logic-input setup
Logic-input hold

10
5
6

Tcco
Tlcc
TCCI

8
0

Logic Input
to G Clock

To output
Logic-input setup
Logic-input hold

11
7
8

Tclo
Tici
TCII

Set/Reset direct

Input A or D to output x, y
Through F or G to output
Reset pad to output x, y
Separation of set/reset
Set/Reset pulse-width

12
13

TRIO
TRLO
TMRO
TRS
TRPW

9
9

7
7

6
6

FClK

50

70

100-

TCH
TCl

8
8

7
7

55-

Logic Input
to Output

K Clock

C Clock

Flip-flop Toggle
rate

Q through F to flip-flop

Clock

Clock High
Clock Low

Notes:

14
15

Units

15

10
7
0

19

6

13
6

0
27

4
5

20

ns
ns
ns

10
14
17

ns
ns
ns
ns
ns

2
3

3
4
22
28
25

13

16
21
20

MHz

1. All switching characteristics apply to all valid combinations of process, temperature and supply with a
nominal chip power dissipation of 250 mW.
• These parameters are for clock pulses generated within a CLB. For an externally generated pulse, derate these
parameters by 20%.

2-91

ns
ns

•

XC206412018 Logic Cell Array
lOB SWITCHING GUIDELINES

PAD
(PACKAGE PIN)

(IN)

~

J

~

OUTPUT SIGNAL

0- TTHZ J.-

I+- (DTPIO-1
INPUT
(DIRECT)

0

XXX

(1/0 CLOCK)

1

- XX

3-STATE

1

0

TpL

L

)00

(OUT)

0 Top:j

TLP
~

J

•

IG)TLW

@TLlr,::

INPUT
(REGISTERED)

\\~
0)

I+- (BTA1 ..

TAC

~
110431A

Speed Grade
Description

Symbol

-50

-100

-70

Min Max

Min

Units

Max

Min Max

6

4

ns

8

ns
ns
ns
ns
MHz

Pad
(package pin)

To input (direct)

1

TplD

I/O Clock

To input (storage)
To pad-input setup
To pad-input hold
Pulse width
Frequency

5
2
3
4

TLI
TpL
TLP
TLW

Output

To pad (output enabled)

8

Top

12

9

7

ns

Three-state

To pad begin hi-Z
To pad end hi-Z

9

TTHZ
TTON

20
20

15
15

11

13

ns
ns

RESET

Note:

To input (storage)
To input clock

8

15
8

0

6

7

TRI
TRC

5'

7
100'

70

17

25

30
25

4
0

0
9

50

10

11

6

20

14

Timing is measured at 0.5 Vcc levels with 50 pF output load.
'These parameters are for clock pulses generated within an LeA. For an externally applied clock, derate these
parameters by 20%.

2-92

ns
ns

GENERAL LCA SWITCHING CHARACTERISTIC

__--II
Vee (VALID)

MOIM11M2
OONEIPROG
(110)

USERVO

~_0TPGW=r

------~-------.~ ,----------------------------USER STATE

III

~'-IN_IT_IA_l_IZA
__
Tl_ON__
ST_A_TE_________________

J=@TeLH

~

@TeLL

CLOCK

=1__

110432

Speed Grade
Description
RESEP

DONEIPROG

CLOCK

M2. M1. MO setup
M2. M1. MO hold
Width-FF Reset
High before RESET4
Device ResetS
Progam width (Low)
Initialization
Device Reset 4
Clock (High)
Clock (Low)

-70

-50

-100

Max

Units

Min Max

Symbol

Min Max

Min

2

5
6

TMR
TRM
TMRW
TRH
TORRW

60
60
150
6
6

60
60
150
6
6

7
8
9

TpGW
TpGI
TDRDW

6
6

6

6

liS
liS
lis

TClH
TCll

8
8

7
7

5
5

ns
ns

3
4

10
11

6

6

7

ns
ns
ns
lis
liS

60
60
150
6
6

7

7

Notes: 1. At power-up, Vee must rise from 2.0 Volts to Vee min in less than 25 ms. If this is not possible, configuration
can be delayed by holding ~ Low until Vee has reached 4.0 V. A very long Vee rise time of > 100 ms, or a
non-monotonically rising Vee may require a RJ:SET pulse (High-to-Low-to-High) of >6 ~s duration after Vee has
reached 4.0 V.
2. ~ timing relative to power-on and valid mode lines (MO, M1, M2) is relevant
only when RESET is used to delay configuration.
3. Minimum CLOCK widths for the auxiliary buffer are 1.25 times the TeLH. Tell.
4. After RESET is High, RESET = DIP = Low for 6 ~ will abort to CLEAR.

2-93

XC206412018 Logic Cell Array

MASTER SERIAL MODE PROGRAMMING SWITCHING CHARACTERISTICS

CCLK
(OUTPlJT)

SERIAL DATA IN

SERIAL DOUT
(OUTPUT) _ _ _ _ _- 1

' - - _ _ _ _ _...1 ' -_ _ _ _ _- - ' ' - -_ _ _ _ _ _ __

110529

-50

Speed Grade
Description

CCLK2

Data In setup
Data In hold

Symbol

1
2

DSCK
I TTCKDS

Min
60
0

Max

-100

-70
Min
60
0

Max

Min
60
0

Units

Max
ns
ns

Notes: 1. At power-up, Vee must rise from 2.0 Volts to Vee min in less than 25 ms. If this is not possible, configuration ean be delayed by holding RESET Low until Vee has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vee may require a I1:ESI:T pulse (High-to-Low-to-High) of >6 fls duration after Vee has reached 4.0 V.
2. Master-serial-mode timing is based on slave-mode testing.

2-94

MASTER PARALLEL MODE PROGRAMMING SWITCHING CHARACTERISTICS

AO-A15
(OUTPUT)

WWVW

~_ _ _ _ _ _ _ _ _ _ _ _ _--J 14----14---~

00-D7

RClK
(OUTPUT)

CClK
(OUTPUT)

II

OOUT
(OUTPUT)

BYTE n-1
1104 33

Speed Grade
Description
RCLK

Note:

From address invalid
To address valid
To data setup
To data hold
RCLK high
RCLK low

1
2
3
4
5
6

-50

Symbol

Min

T ARC

0
200

TRAC

T ORC
T RCO

TRCH
T RCL

60
0
600
4.0

-70
Max

Min

-100
Max

0
200
60
0
600
4.0

60
0
600

Units

Min

Max

0
200

ns
ns
ns
ns
ns

IlS

1. CCLK and DOUT timing are the same as for slave mode.
2. At power-up, Vee must rise from 2.0 Volts to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vee has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vee may require a RESET pulse (High-to-Low-to-High) of >6 !J,S duration after Vee has reached 4.0 V.

This timing diagram shows that the EPROM requirements are extremely relaxed: EPROM access time can be longer than
4000 ns, EPROM data output has no hold time requirement

2-95

XC2064/2018 Logic Cell Array

PERIPHERAL MODE PROGRAMMING SWITCHING CHARACTERISTICS

CSO

CS2

CCLK (2)

(OUTPUl)

DIN

DOUT(2)
(OUTPUl)
1104 34

Speed Grade
Description
Controls 1
(CSO, CS1,
CS2, WRT)

-50

Symbol

Active (last active
input to first inactive)

1

TeA

0.25

Inactive (first inactive
input to last active)

2

Tel

0.25

CCLK2
DIN setup
DIN hold

3

Tccc
T De
TeD

4
5

Units

Min

Max

Min

Max

Min

Max

5.0

0.25 5.0

0.25

5.0

Ils

0.25

0.25
75

75
50
0

-100

-70

50
0

!lS
75

50
0

ns
ns
ns

Notes: 1. Peripheral mode timing determined from last control signal of the logical AND of (GSO, CST, GS2, WFiT) to transition to
active or inactive state.
2. GGLK and DOUT timing are the same as for slave mode.
3. At power-up, Vee must rise from 2.0 Volts to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vee has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vee may require a RESET pulse (High-to-Low-to-High) of >6 j.J.s duration after Vee has reached 4.0 V.

2-96

SLAVE MODE PROGRAMMING SWITCHING CHARACTERISTICS
DIN

ZX)(

~ CD Toee

BIT N

--.XXX

BIT N+1

@ Teco=1----;L,-:..-=----------@-5-TC-C-L=::::~:----

CClK

1+--- 8) TeCH ----1'0DOUT
(OUTPUT)

BITN

BITN-1

1104 35

Speed Grade
Description
CCLK

Symbol

3
1
2
4
5

To DOUT
DIN setup
DIN hold
High time
Low time
Frequency

Tcco
T Dcc
TCCD
TCCH
TCCl
Fcc

-70

-50
Min

Max

65
10
40
0.25
0.25

5.0
2

Min

Max

65
10
40
0.25
0.25 5.0
2

-100
Min

Units

Max

65
10
40
0.25
0.25

5.0
2

ns
ns
ns
/-ts
/-ts
MHz

Note: At power-up, Vec must rise from 2.0 Volts to Vec min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vec has reached 4.0 V. A very long Vee rise time of > 100 ms, or a non-monotonically
rising Vec may require a RESET pulse (High-to-Low-to-High) of >6 f1S duration after Vee has reached 4.0 V.

PROGRAM READ BACK SWITCHING CHARACTERISTICS
DONE/PROG
(OUTPUn

----~------------------------------------

CD

TORT

~....-@

TRTH

Ir-~~--~h-~------------------

RTRIG

CCLK(1)

RDATA
(OUTPUn
1104 36

Speed Grade
Description

Symbol

-50
Min

RTRIG

PROG setup
RTRIG high

1
2

TDRT
TRTH

300
250

CCLK

RTRIG setup
RDATA delay

3
4

T RTCC

100

Notes:

TCCRD

Max

-70
Min

Max

300
250

Min

ns
ns

100
100

100

1. CCLK and DOUT timing are the same as for slave mode.
2. DON ElPROO output/input must be HIGH (device programmed) prior to a positive transition of RTRIG (MO).
2-97

Units

Max

300
250

100
100

-100

ns
ns

•

Component Selection,
Ordering Information,
& Physical Dimensions
COMPONENT AVAILABILITY (11/90)

XC2064

XC201a

XC3020

XC3030

1--'-'+-"";;';"_

XC3042

XC3064

XC3090

X1104

XC1736A/XC1765-PD8C Plastic 8-Pin Mini-DIP
-40°C to 85°C
XC1736A/XC1765-CD8M Ceramic 8-Pin Mini-DIP
-55°C to 125°C

COMPATIBLE PACKAGE OPTIONS
A range of LCA devices is available in identical packages
with identical pin-outs. A design can thus be started with
one device, then migrated to a larger or smailerchip while
retaining the original footprint and PC-board layout.
Examples: PC 68:
2064-2018-3020-3030
PC 84:
2018-3020-3030-30423064-3090
PG 84:
2018-3020-3030-3042
PO 100:
3020-3030-3042
PG 132:
3042-3064

LCA Temperature Options
Symbol

Description

C

Commercial
Industrial
Mil Temp
Military

I
M
B

Temperature
O°Cto 70°C
-40°C to 85°C
-55°C to 125°C
MIL-STO-883, Class B

ORDERING INFORMATION

JTTL

Example:

XC2064-70PC68C

" '..

T

T,~

Toggle
Rate

T...

Note, however, that the XC2000 and XC3000 families
differ in the position of XTL 1 as weil as three parallel
address bits (6, 7 and 11) and most of the data pins used
in parallel master mode.

_w.

Range

XC2018 and XC3020 are not available in PGA68, since
the PGA84 is the same size and offers more I/O.

Number of Pins

Note that a PLCC in a socket with PGA footprint generates
a printed circuit board pin-out differentfrom a PGA device.

Package Type

2-98

l:XlUNX
PGA PIN-OUTS

I

2

3

4

(Ag \ rAlO\ rAm

A

5

6

7

8

II 10 9

9 10 II

rAm rAiS\ rA5\ rM\ 1A3'\ fAi\

A

A

0@@@@S(@@)@@8 B
c OOEB
®@ c
D 00
®~ D
0 E
E 0 0
uOlP V~l§:W
~
FOE;
80 F
Oomponent
®@ G
G 00
Side
@O H
H 00
J CIDC)
@O J

B

~~~~~~~~~

B

c
D
E

OOI/D02

K

F
G
H

J

®~~OC)OSOO@@~ K

~~~OOOOO®~

L

2

3

4

5

6

7

8

K

L

L

7

6

5

4

3

2

1

"A

fAi\ iA3\ rM\ rA5\ rAiS\ rAm rAm rAIO\ fA9\

~~~~~~~~~

8@@@)(@S@@@@0
@@
EBOO
~®
00
0 ~ 18l0uuOM V~l§:W 00
08
80
Solder
Side
®®
00
O@
00
O@
OCID
00/02

B

c
D
E

F
G
H

J

~@@OOSOOO@® K

~®OOOOO~@
11 10 9

9 10 II

8

8

7

6

5

4

3

2

8

7

6

5

4

3

2

L

EB = Index pin which mayor may not be electrically connected to pin C2
unlabeled pin = unrestricted 1/0 pin

PG68 Pln-outs-XC2064

2

3

4

5

6

7

8

9 10 11

II 10 9

A"@@@D®O(@O@@@€~

A

A

O@@@O@)O~@@@

B

B

OOEB @8@
~~
D 00
®O
E 000 uOP V~[EW OO@
F 008
800
GOOO Oomponent @O@)
H 00
Side
®O
J OCID
OSO
~O
K O@@OOOOO®@@

c

c

D

D

E
F

E
F

G

G

H

H

B

8@@@0(@0®@D@@

J

J

K

K

@@@@)O(@O@@@O
@8@ EBOO
~~
o ® 18l0uuOM V~IEW 00
@OO
000
008 Solder Side 800
@O@
000
O@
00
O~
080
(IDO
@@®OOOOO@@O

®()~OOOOOO@~ L

L

~@OOOOOO~O®

c

L

I

I

2

3

4

5

6

7

8

9 10 II

II 10 9

EEl • Index pin which mayor may not be electrically connected to pin C2
unlabeled pin - unrestricted VO pin

PG84 Pln-outs-XC2018

2-99

8

7

6

5

4

3

2

I

A

B

c
D

E
F
G

H
J
K
L

II

XC206412018 Logic Cell Array

PHYSICAL DIMENSIONS

LI+--------- 2.440±0.025-------~·1

L r160

t.600 ± 0.010j

I~

~~~~~~~~~

0.550

~I

t:::J*

0.130

f
<1.

~0.070

DIMENSIONS IN INCHES
1'04 39

48-Pin Plastic DIP Package

PIN1~

o.o~±~

I-

1

2.400 ± 0.24

0.100 ± 0.025

.,L.~-r
ct. ct.

0.610 ± 0.010

,

0.D10
±0.002

0.045 ± 0.010 0.018 ± 0.002
1'04 40

DIMENSIONS IN INCHES

48-Pin Ceramic DIP Package

2-100

PHYSICAL DIMENSIONS (Continued)

L
,L.
PIN NO. 1

0.045

PIN NO.1 IDENTIFIER

0.045 x 45' " "
9

PWRDWN

61

CCLK
DOUT/IO

0.990
±0.005
0.954
±0.004

Vcc

0.20
±0.010

Vcc

1~:

,'~ i

0.Q18

--.i..
T
0.028

11·~0.954±0.004 ~I

LEAD PITCH
0.050 TYPICAL
LEAD CO-PLANARITY
±0.002

=!==t:=I!:::::l=.--L-

[t

~0.990±0.005===:J1

III

DIMENSIONS
IN INCHES

o.045

0.100±0.010

TOP VIEW

0.175±o.o10

SJA= 35-40 °CIW
SJC= 7-10 °CIW

110534C

68-Pln PLCC Package

1.000± 0.12

1+--------1.100±O'012SO. -------~

I----

O.100TYP

t"\

rt\ rr

r

rt'l r t\r.

\.1-1 \.
G

0.100

r.

TVP

r:--. r t\r: :--'Ii :\'If. t'lil
r
\.

t\

rt\

V

r.

1.000

±O.Ot

r

\.

INDEX PIN

PINN011NOEX

A

r.
\.
r.

c

J

'-

/

h
'-

r r. r
'-

r

TYP 0.070 DlA

\.

~
'+'

r.

\.

\.

r.

r

\.

\.

10

TOPVJEW

o 095±0015

11

BOTTOM VIEW
NOTE: INDEX PIN MAY OR MAY NOT BE
ELECTRICALLY CONNECTED TO PIN C2.
DIMENSIONS IN INCHES
1104 42

68-Pln PGA Package

2-101

XC206412018 Logic Cell Array
PHYSICAL DIMENSIONS (Continued)

L

PIN NO. 1

0.045 x 45'",,11

PIN NO.1 IDENTIFIER

I'L.

PWRDWN

75
CCLK
DOUT/IO

~

P

~

1 .190

±O.005

±1010~4

Vee

Vee

~
~

~

iJ

~
~

M1
MO

DONE
RESET P.

r14----1.154±0.004_~53·!11
I14.~-------1.190
JUUUUULJU

33

LEAD PITCH
0.050 TYPICAL

± 0.005--------+1-·

TOP VIEW
DIMENSIONS IN INCHES

El JA = 30-35 °eIW
El Jc= 3-7 °eIW

'105360

84-Pin PLCC Package

1+1'------1.100 ± 0.012

so------O\'I

1----+ 0.100 TYP
!I'~

r:

1.000 ± 0.010

rhr:l:\

th ffi

0.100
TYP

'-V '-V

'-V '-V

~~

I

~~

I-E~ 3l-E~ 7
"1.00o
± 0.01 o

V

I-E~ 3-

INDEX PIN

/

TYP.0.070
DI~.08MAX

"-

r:

f::\
'-J

'-'
\J

/t:>.

10

11

BOTTOM VIEW

ElJA = 30-35 °cm

NOTE: INDEX PIN MAY OR MAY NOT BE
ELECTRICALLY CONNECTED TO PIN C2.

ElJC= 4-7 °cm

DIMENSIONS IN INCHES
1105350

84-Pin PGA Package

2-102

----------------------------------.

~XlllNX

Military Logic Celr Arrays

XC2018B, XC3020B, XC3042B, XC3090B

Product Specifications

M

INTRODUCTION
Total

Xilinx introduced the first field programmable gate array
(FPGA) in 1985. The development of the PGA was the
result of a number of technical breakthroughs and truly
represents the latest in advanced technology for microelectronic applications. Due to its density and the conven~ence of user programmability, the Logic CelJTM Array is an
Important new alternative in the ASIC market. Xilinx
continues to concentrate its resources exclusively on
expanding its growing family of programmable gate arrays
and associated development systems. See the Xilinx
Programmable Gate Array Data Book for a complete
description of the architecture of both the 2000 and 3000
series arrays.
MIL·STD·883 CLASS B INTRODUCED
Xilinx continues its leadership in field programmable gate
arrays (FPGA) by announcing the first military qualified
FPGA's. These four devices meet all requirements of
MIL·STD·883 paragraph 1.2.1

Logic
Capacity
(gates)
Device

Conflg·
urable
Logic
Blocks

User
IIOs

Program
Data
(bits)

74

17,878

XC2018B

1800

XC3020B

2000

64

64

14,779

XC3042B

4200

144

96

30,784

XC3090B

9000

320

144

64,160

100

Device

110

XC2018

74

XC3020

64

Surface Mount
Ceramic
User
QFP
110

Through Hole
Ceramic
User
PGA
110
CPGA84

74

COFP 100

64

CPGA84

64

CPGA 132

96

CPGA 175

144

XC3042

96

COFP 100

82

XC3090

144

COFP 164

142

STANDARD MILITARY DRAWINGS (SMD)
The Standard Military Drawing program (SMD) is a program initiated by the Federal government to simplify the
procurement of Integrated Microcircuits (especially the
more advanced technologies) by military contractors. The
Defense Electronics Supply Center (DESC) issues the
SMD that is consistent with the Xilinx military product
specification and test conditions. DESC assigns an SMD
specification number and releases the drawing. This
drawing is then availble for use by all departments and
agencies of the Department of Defense. The Xilinxdevice
can then be easily procured by a military contractor by
specifying the SMD# instead 01 the Xilinx part number.
This eliminates the need for a separate Source Control
Drawing (SCD) and greatly reduces paperwork.
DESC has assigned the XC2016B device SMD# 596288638, the XC3020B device SMD# 5962-89948, the
XC3042B device SMD# 5962-89713 and the XC3090B
device SMD# 5962-89823. Contact your Xilinx
representative or DESC for more information.
LCA IDEAL FOR MILITARY APPLICATIONS

MILITARY PACKAGING
Xilinx otters two military packaging altematives. In addition to the industry standard ceramic pin grid array (CPGA)
packages we offer a ceramic quad flat package (CQFP)
that meets the JEDEC standard outline drawing#MO-082.
This CQFP has 25 mil pin-to-pin spacing. It is shipped with
the leads unformed allowing selection of cavity up or cavity
down and lead forming at the point of board assembly for
better contact.

Field programmable gate arrays are taking market share
from mask gate arrays in the commercial market are
expected to be even more successful in the military market. Approximately 50% of all logic sales in the U.S.
military market are ASIC's today. That numberis expected
to grow to 70% by 1993. FPGA's offer lower costs and
more flexibility than mask gate arrays.

2-103

II

Military Logic Cell Arrays

The LCA is especially suited to military ASIC applications.
With a FPGA one specification can be written to c()ver
multiple applications. Xilinx programmable gate arrays
are "configured" by downloading software to the part - no
fuses are blown. There is no requirement for post-programming testing for fault verification. The device is never
obsolete because it can be reprogrammed many times.
Because Xilinx FPGA's are standard parts, they can be
stocked in inventory at Xilinx, at Xilinx distributors or at the
user site. One part can be stocked for multiple applications, minimizing inventory costs. Another benefit of being
a standard product is the inherent high reliability of a high
volume memory product rather than a low volume custom
circuit. Non-recurring engineering costs (NRE) are never
required for a FPGA thereby providing cost effective
solutions in military volumes and allowing very inexpensive design iterations.
For maximum security the configuration data may be
"down-loaded" from a remote site thereby eliminating the
potential of tampering with the configuration data locally.
The FPGA can be made non-volatile in this instance with
the addition of a small battery backup.
One of the most effective advantages of the Xilinx FPGA
is the ability to reconfigure some or all of the deviCe while
it remains in the circuit. This opens up entirely new
possibilities allowing the same gates to be used by different functions at different times.
IMPORTANT BENEFITS FOR MILITARY DESIGNS
Cost Containment

• Standard Product
- No overrun charges
- Simplified product qualification.
- No test vectors to write
- Simplified documentation (SMD)
Reliability
• Standard Product
- Reliability of hi-volume memory product
• Fully tested by Xilinx
- Fault coverage assured by vendor
Security
• No design information needed by manufacturer
- Secure design process. Design data held to
vendor at user site.
• Remote configuration
- Ensures secure design data capability
Flexibility
• Standard product
- An ASIC where one spec can be used for multiple
applications
- An ASIC stocked by distribution
• Reprogrammable
- Logic can be changed "on the fly"
• No FAB turnaround
- Design changes in minutes

• No NRE
- Very cost effective in military volumes
- Low cost design iterations

2-104

MIL-STD-883 CLASS 8 COMPLIANCE

MIL-STD-883 CLASS 8-METHOD 5005 QUALITY
CONFORMANCE INSPECTION (QCI) TESTING

Xilinx is now serving military customers in accordance with
MIL-STD-883 Class B paragraph 1.2.1 together wnh the
attendant requirements of MIL-M-3851 O. This includes fUll
compliance with all processing requirements of Method
5004 and all Quality Conformance Inspection (QCI)
requirements of Method 5005 (Groups A,B,C,D).
MIL-M-38510 (as invoked by MIL-STD-883)
Military Specification Microcircuits-General Specification (describes the design, processing and assembly
workmanship guidelines)
MIL-STD-883
Military Standards-Test Methods and Procedures for
Microelectronics (delineates the detailed testing and
inspection methods for military integrated circuits)
MIL-STO-B83 Class B-Method 5004 Processing Flow
METHOD CONDo
FULL TRACEABILITY

XILINX SPECIFICATION

Every lot of devices shipped to the requirements of
MIL-STD-883C is required to be qualified by four kinds of
Quality Conformance Inspection (QCI) Tests. The QCI
requirements specified by the Defense Electronics Supply
Center (DESC) undergo regular revisions. Xilinx rigorously incorporates these revisions into our QCI testing in
conformance with the requirements of MIL-STD-883C.
These are:
Group A-Electrical tests done to data sheet limits at all
three temperatures of the military temperature range, 55°C to +125°C. These are performed on a sample from
the same lot being shipped.
Group 8-Mechanical tests performed on a sample of
devices of the same device/package type assembled
within the same 6 week widow of the lot being shipped.
This group consists of upto 8 subgroups including physical
dimensions, mark permanency, solderability, internal visual/mechanical, bond strength, internal water vapor content, fine & gross leak, and ESD sensitivity.
Group c-Package related reliability tests performed on
a sample of devices made with die from the same 1 year
window. This group consists of up to 2 subgroups including (1) life testing (1000 hr at 125°C) and (2) temperature
cycling, constant acceleration, fine & gross leak, and a
visual examination.

20 1OIB

10101C

Group D-Package related reliability tests performed on
a sample of devices made in the same package within the
same 1 year window. This group consists of up to 8
subgroups: physical dimensions; lead integrity and seal;
thermal shockltemperature cycling/moisture resistance/
seallvisual; mechanical shock vibration (variable frequency)/constant acceleration/seallvisual; salt atmosphere/seallvisual; internal water-vapor content; adhesion of lead finish; lid torque.

2001/E

1014

25'C

1015

2009

SODS

1637 01

2-105

II

Military Logic Cell Arrays

2-106

XC20188
Military Logic CeWMArray
Product Specification. See Note 1.

FEATURES

Pan
Number

Logic
Capacity
(gates)

Conflgurable
Logic
Blocks

User
I/Os

Configuration
Program
(bits)

XC2018

1800

100

74

17878

• MIL-STD-883 Class B Processing.
Complies with paragraph 1.2.1
• Field-programmable gate array
• Low power CMOS static memory technology
• Standard product. Completely tested at factory
• Design changes made in minutes

in internal static memory cells. On-Chip logic provides for
automatic loading of configuration data at power-up or on
command. The program data can reside in an EEPROM,
EPROM or ROM on the circuit board or on a floppy disk or
hard disk.

• Complete user control for design cycle.
Secure design process
• Complete PC or workstation based
development system
- Schematic entry
- Auto Place/ Route (DS23)
- Design Editor (DS21)
- Logic & Timing Simulator (DS22)
- XACTOR In-circuit Verifier (DS24)

DESCRIPTION

Several methods of automatically loading the required
data are designed into the Logic Cell Array and are
determined by logic levels applied to mode selection pins
at configuration time. The form of the data may be either
serial or parallel, depending on the configuration mode.
The programming data are independent of the configuration mode selected.

The LogiC Cell™ Array (LCA) is a high density CMOS
programmable gate array. Its patented array architecture
consists of three types of configurable elements: InpuV
Output Blocks, Configurable Logic Blocks and Interconnect. The designer can define individual I/O blocks for
interface to external circuitry, define logic blocks to implement logic functions and define interconnection networks
to compose larger scale logic functions.

The XACT development system allows the user to define
the logic functions of the device. Schematic capture is
available for design entry. while logic and timing simulation, and in-circuit debugging are available for design
verification. XACT is used to compile the data pattern
which represents the configuration program. This data
can then be converted to a PROM programmer format file
to create the configuration program storage.

The Logic Cell Array's logic functions and interconnections are determined by the configuration program stored

See the XC2018 Commercial data sheet for a full description.

ORDERING INFORMATION

XC2018 - 50 PG84 B

.

33. (33 MHz TOGGLE)
50 (50 MHz TOGGLE)

TT~

-----,----J ~

70 (70 MHZ TOGGLE)

TSC0026
2-107

B.MIL.STD.883,CLASSB,FULLYCOMPLIANT
PG=CERAMIC PIN GRIO ARRAY PACKAGE.
84·LEAD

1637 02A

II

XC2018B Military Logic Cell Array

PIN ASSIGNMENTS

I/O

I/O

I/O

TSC0026

«HIGH» IS HIGH IMPEDANCE WITH A 20-50 kO INTERNAL PULL-UP DURING CONFIGURATION

2-108

1637 03

E:XIUNX
PHYSICAL DIMENSIONS - Conforms to MIL-M-38510 Appendix C, Case P-BC.

--

t o l · - - - - - - l . l 0 0 ± 0.012 SQI-------->l'1

1.ooo± 0.01
0.100TYP

ffiffi

ffirh

'V 'V

'+''+'

~~

~~

I-E~ fr
I-(~
G

I.

fr

0.100
TVP

I

L
1.000

±O.O1 o
INDEX PIN

I-E~ fr

/

TVP.O.070
D,I\08MAX

Ll'i
r:

./''l:!.

III

i":'.

'-'

_L

r.L

i":'.

'-'
5

6

7

10

11

BOTTOM VIEW
NOTE: INDEX PIN MAYOR MAY NOT BE
ELECTRICALLY CONNECTED TO PIN C2.
DIMENSIONS IN INCHES

XC2018: 84-Pin PGA Package
1105358

STATIC BURN-IN CIRCUITS

30

1.15k

1.3 k

1.3k

1.5 k

1.5 k

715
H1
H2
J1
K1
J2
L1

4.99 k

1k

.01 ~F

NOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 1/8 WATT AT1500C WITH A
BUILD TOLERANCE OF 1% AND A 5%
TOLERANCE OVER LIFE.
~ CAPACITOR HAS 10% TOLERANCE.
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTIC.
[!) 30 n RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 W AT 1500C WITH A
TOLERANCE OF 5%.

[]]

TSC0026

1637 OM

2-109

XC2018B MIlHary Logic Cell Array

TEST SPECIFICATION
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.

Absolute Maximum Ratings

Limits

Units

Vce

Supply voltage relative to GND

-0.5 to +7.0

V

VIN

I(lput voltage with respect to GNO

-0.5 to VCC +0.5

V

VTS

Voltage applied to three-state output

-0.5 to VCC +0.5

V

TSTG

Storage temperature (ambient)

-65 to +150

°C

TSOL

Maximum soldering temperature (10 sec @ 1/16 in.)

+260

°C

TJ

Maximum junction temperature

+150

°C

Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to
Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Test

Conditions
-55°C S TeS +125°C
Vee = 5.0 V ±10%

Symbol

High Level Output Voltage
Low Level Output Voltage
Quiescent Operating
Power Supply Current
Power-Down Supply Current

VOH
VOL
leeo

Leakage Current
Input High Level TTL
Input Low Level TTL
Input High Level CMOS
Input Low Level CMOS

IlL
VIHT
VILT
VIHC
VILC

ICCPD

Vee = 4.5 V, IOH = -4.0 mA
Vee = 5.5 V, IOL = 4.0 mA
CMOS Inputs, Vin = Vcc = 5.5 V
TTL Inputs, Vin = Vcc = 5.5 V
Vin=~5.5V,
PWR OW =OV
Vee = 5.5 V, Vin = Vec and 0 V
Guaranteed Input High
Guaranteed Input Low
Guaranteed Input High
Guaranteed Input Low

Group A
Subgroups

Min

1,2,3
1,2,3
1,2,3
1,2,3
1,2,3

3.7

1,2,3
1,2,3
1,2,3
1,2,3
1,2,3

-10
2.0

Max

Units

0.4
10
15
0.5

V
V
mA
mA
mA

.2Vcc

~
V
V
V
V

7

~
~

10
0.8

.7Vcc

Switching Characteristics, General LCA
DONEIPROG
Program Width (Low)
Initialization

TPGW
TPGI

PWR DWN2
Power Down Supply

VpD

TSC0026

4
5

See Fig. 3

9,10,11
9,10,11

1,2,3

Table 1. Electrical Performance Characteristics
2-110

6

3.5

V

-50
-70
Conditions
-33
-55°C ~TC ~+ 125°C Group A
Sym Vee = 5.0 V ±10% Subgroups Min Max Min Max Min Max Units

I

Test

I

I

Switching Characteristics, Peripheral Mode Programming

Controls (CS, WRT)3,4
Last Active Input to First Active TCA
First Inactive Input to Last Active TCI
CCLK5
DIN Setup
DIN Hold

1 See Figure 4
2

9,10,11 0.5
9,10,11 0.5

1.0 0.5
0.5

1.0

IlS
IlS

3
4

9,10,11
9,10,11
9,10,11

75

75

ns
ns
ns

5

50
5

50
5
......}...••..•....

Switching Characteristics, Program Readback 6

i

............ ......•.

RTRIG Setup

TRTH

CCLK,
RTRIG Setup
RDATA Delay

1 See Fig. 7

TRTCC 2
TCCRO 3

9,10,11 250

250····

250

ns

:{:::}~ ::/~

9,10,11 100
9,10,11

100

100
100

9,10,11

238

178

9,10,11

288

288

9,10,11

410

302

l°l~

.......

•...11

ns
ns

119

ns

459

ns

".,."

Benchmark Patterns7

TPID + interconnect + 10 (TILO) + T81
Top. Measured on 10 cols.
TPID + interconnect + 10 (TITO) + T82
Top. Measured on 10 cols.
TPID + interconnect + 10 (TOLD) + T83
10 (TITO) +Top.
Measured on 10 cols.
TCKO + 2 (TILO) + TICK +
interconnect
Tcia + TILO + TICI +
interconnect
Tcco + 2 (TllO) + T lcc +
interconnect
TPIO + interconnect + 10 (TRIO) +
Top, Measured on 10 rows.
TLI + 3 (TIPo) + 4 (TOP ) + T PL +
interconnect.
Tested on all lOBs.

::;:::\:

[j ~17

ns

i;

T84

9,10,11

T85

9,10,11

85

62

."

•.•'..•• .•.•,.,.42
••••••••••

ns

::;:::;:::: :::;:::;:

90

67

4'

ns

)38

ns

....•.,..'
•••••••••••

T86

9,10,11

66

49

T87

9,10,11

318

269

.;.'.:.;.:-

5

i83

ns

;:::::;::

9,10,11

T88

274

Table 1. Electrical Performance Characteristics (cont'd)

TSC0026
2-111

204

..•.••" .•.

141

:::;:::::

ns

II

XC2018B Military Logic Cell Array

Test

-50
-70
Conditions
-33
-55°C STC s+ 125°C Group A
Sym Vee = 5.0 V ±10% Subgroups Min I Max Min I Max Min I Max Units

Application Guidelines, Switching, CLB'
Logic Input to Output,
Combinatorial

TllO

1 See Fig. 1

N/A

20

15

10

ns

Transparent Latch
Additional for Q Through
For G to Out

TITO
TQLO

2

N/A
N/A

25
13

20
8

14
6

ns
ns

K Clock,
To Output
Logic-Input Setup
Logic-Input Hold

TCKO 9
TICK 3
TCKI 4

N/A
N/A
N/A

12
1

C Clock,
To Output
Logic- Input Setup
Logic-Input Hold

Tcco 10
Tlcc 5
TCCI 6

N/A
N/A
N/A

12
6

20

15
8
1

19

25
9
1

~t
~. •••.••
1:;

I;,;,)

Ii';'"

~3

I·
I'

I:~o

ns
ns
ns

ns
ns
ns

Logic Input to G Clock,
To Output
Logic-Input Setup
Logic-Input Hold

TclO
TICI
TCII

11
7
8

N/A
N/A
N/A

Set/Reset Direct,
Input A or D to Out
Through F or G to Out
Master Reset Pin to Out
Separation of Set/Reset
Set/Reset Pulse-Width

TRIO 12
TRLO 13
TMRQ
TRS
TRPW

N/A
N/A
N/A
N/A
N/A

17
12

9
9

7
7

Flip-Flop Toggle Rate,
Q Through F to Flip-Flop

FClK

N/A

33

50

70

Clock High'

TCH

14

N/A

12

8

7

ns

Clock Low'

TCl

15

N/A

12

8

7

ns

37

27
4
5

6
9

22
28
45

25
37
55

Table 1. Electrical Performance Characteristics (Continued)

TSC0026
2-112

";';';';'

~
.•.••.'."

;

'"""",

,~~
35

ns
ns
ns
ns
ns
ns
ns
ns
MHz

Test

-70
-33
-50
Conditions
-55°C ~TC ~+ 125°C Group A
Sym Vee = 5.0 V ±10% Subgroups Min Max Min Max Min Max Units

I

I

I

Application Guidelines, Switching, IOB7

Pad (Package Pin) to
Input (Direct)

TplD

See Fig. 2

N/A

I/O Clock
To Input (Storage)
To Pad-Input Setup
To Pad Input Hold
Pulse Width
Frequency

8

12

N/A
N/A
N/A

12

N/A

12

6

15

ns

N/A

33

50

ns
ns
ns
ns
MHz

Output,
To Pad (Output Enable)

N/A

15

12

ns

Three-State,
To Pad Begin hi-Z
To Pad End hi-Z

N/A
N/A

25
25

20
20

ns
ns

N/A

40

N/A

35

30
25

RESET,
To Input (Storage)
To Input Clock

20

8

o

o

9

25
20

ns
ns

100

ns
ns
ns

Application Guidelines, Switching, Slave Mode Programming 7
CCLK,
To DOUT
DIN Setup
DIN Hold
High Time
Low Time
Frequency

N/A
N/A
N/A
N/A

N/A

100

100

40
0.5
0.5

N/A

10
40

10
40

10

1.0
1

0.5
0.5

0.5..\>

1.0
1

0.$. J.O
1

f-Ls
f-Ls

MHz

Application Guidelines, Switching, Master Mode Programming 7.9
RCLK,
From Address Invalid
TARC 1 See Fig. 5
To Address Valid
T RAC 2
To Data Setup
TDRC 3
To Data Hold
T RCD 4
RCLK High
T RCH 5
RCLKLow
T RCL 6
-'Application Guidelines, Switching, General LCA7
RESET'O
M2, M1, MO Setup
M2, M1, MO Hold
Width (Low)

TSC0026

N/A

o

0

N/A
N/A

200

200

N/A
N/A
N/A

60

60

600

600

ns
ns
ns
ns
ns

4.0

4.0

f-LS

1

1
1
150

o

0

::\.,.,: .,.....

N/A
N/A
N/A

TMR
1 See Fig. 3
TRM
2
TMRW 3

1
150

Table 1. Electrical Performance Characteristics (Continued)
2-113

1
1
150

f-Ls
f-Ls

ns

II

XC2018B Military Logic Cell Array

INPUT (A,B,C,D)

x

x
~CDTllO~

XXX

OUTPUT (X,V)
(COMBINATORIAL)

® TITO

xx:CD

OUTPUT (X,V)
(TRANSPARENT LATCH)

~0TICK
CLOCK(K)

TCKI -

Jr-

~®TICC

® Tccl -

~

CLOCK (C)

~0TICI
CLOCK (G)

®TclI -

Jf-

~®TCKO@Tcco--

@

TclO

OUTPUT (VIA FF)

{

SET/RESET DIRECT (A,D)

I
SET/RESET DIRECT (F,G)

1.
I

@

TRIO

@

TRlO

@

CLOCK (ANV SOURCE)

TCl

xx:

=-1-----

Timing is measured at 0.5 Vee levels with 50 pF minimum output load.
Input signal conditioning: Rise and fail times,; 6 ns, Amplitude = 0 and 3V

Figure 1. Switching Characteristics Waveforms, CLB

TSC0026

2-114

1637 06

PAD
(PACKAGE PIN)

(IN)

OUTPUT SIGNAL

INPUT
(DIRECT)

L
(110 CLOCK)

INPUT
(REGISTERED)

II
14--~ (]) TRG

163707

Figure 2. Switching Characteristics, lOB

______I
Voc(VALlD)

\---_---11

__---II

\

J ,
•

p
'- ____ ' - - . V PD

MOIM11M2

DONEIPROG
(OUTPUT)

USER VO

CLOCK

~GTPGW=,

------~------.~
.---------------------------~'-I_N_IT_IA_Ll-ZA-T-IO-N-S-T-A-TE---------USER STATE

~

\'---_ _--JI
Figure 3. General LCA Switching Characteristics

TSC0026

2-115

16370SA

XC2018B Military Logic Cell Array

CS2

CCLK (2)
(OUTPUl)

DIN

DOUT
(OUTPUT)
1637

oe

Figure 4. Peripheral Mode Programming Characteristics

AG-A15
(OUTPUn

00-07

RCiX

(OUTPUn

CCLK
(OUTPUn

DOur

(OUTPUn

BYTE n-l
CCLK and DOUT timing are the same as for slave mode.
At power-up, Vee must rise from 2.0 V 10 Vee min. in less than 10 ms.
163710

Figure 5. Master Mode Programming Switching Characteristics

TSC0026

2-116

l::XILINX
DIN~

BITN

~ CD TDCC"I-@ TCCD

xxx
~

BITN+1

J

@TCCL

CCLK

@ TCCO"",1;::::.

G)TCCH

DOur

BITN-1

(OUTPUT)

xxx' - - - - BITN

Configuration must be delayed at least 40 ms after Vee min.
1637 11

Figure 6. Slave Mode Programming Switching Characteristics

DONEIPROG
(OUTPUT)

_----1- __________________________________ _

III

RTRIG

CCLK(l)

RDATA
(OUTPUT)

VALID
163112

Figure 7. Program Readback Characteristics

XC2018B Data Sheet Notes
Notes: 1. Xilinx maintains this specification as a controlled document. To comply with the intent of MIL-STD-883, and to assure
that you are using the most recently released device performance parameters, please request a copy of the current
revision of this Test Specification from Xilinx.
2. PWR OWN must be active before Vce goes below specified range, and inactive after Vcc reaches specified range.
3. Peripheral mode timing determined from last control signal of the logical AND of (CSO, CST, CS2, WRT) to transition
to active or inactive state.
4. Configuration must be delayed at least 40 ms after Vee min.
5. CCLK and DOUT timing are the same as for slave mode.
6. DIP' must be high before RTRIG goes High.
7. Testing of the Applications Guidelines is modeled after testing specified by MIL-M-38510/605. Devices are first 100%
functionally tested. Benchmark patterns are then used to measure the Application Guidelines. Characterization data
are taken at initial device qualification, prior to introduction of significant changes, and at least twice yearly to monitor
correlation between benchmark patterns, device performance, XACT software timings, and the data sheet.

fuE
Ilk

8. Minimum CLOCK widths for the auxiliary buffer are 1.25 times the TelH, TelL.
9. Vee must rise from 2.0 V to Vce minimum in less than 10 ms for master
mode.
PAD
10. RESET timing relative to power-on and valid mode lines (MO, Ml, M2) is
relevant only when RESET is used to delay configuration.
50 pF MIN
II.AII timings except TTSHZ and TTSON are measured at 1.5 Vcc level with
50 pF minimum load output. For input signals, rise and fall times are
less than 6 ns, with low amplitude =0 V, and high = 3 V. TTHZ is
determined when the output shifts 10% (of the output voltage swing)
from VOL level or VOH level. The following circuit is used:

k1%

1%

vee

GND
163713

~VIN

TTON is measured at 0.5 Vcc level with VIN = 0 for 3-,State to active
High, and VIN = Vcc for 3-State to active Low. The following load circuit
is used:
TSC0026

~

. . I1

1k1%

50pF MIN

163714

2-117

XC2018B Military Logic Cell Array

TSC0026

2-118

XC3020B
Military Logic

Celr Array
M

Product Specification. See Note 1.

FEATURES

Part
Number

Logic
Capacity
(gates)

Configurable
Logic
Blocks

XC3020

2000

64

• MIL-STD-883 Class B Processing.
Complies with paragraph 1 .2.1
• Field-programmable gate array
• Low power CMOS static memory technology

User

II0s

64

Configuratlon
Program
(bits)
14779

• Standard product. Completely tested at factory
• Design changes made in minutes

in internal static memory cells. On-chip logic provides for
automatic loading of configuration data at power-up or on
command. The program data can reside in an EEPROM,
EPROM or ROM on the circuit board or on a floppy disk or
hard disk.

• Complete user control for design cycle.
Secure design process
• Complete PC or workstation based
development system
- Schematic entry
- Auto Placel Route (DS23)
- Design Editor (DS21)
- Logic & Timing Simulator (DS22)
- XACTOR In-circuit Verifier (DS24)

DESCRIPTION

Several methods of automatically loading the required
data are designed into the Logic Cell Array and are
determined by logic levels applied to mode selection pins
at configuration time. The form of the data may be either
serial or parallel, depending on the configuration mode.
The programming data are independent of the configuration mode selected.

The Logic Cell™ Array (LCA) is a high density CMOS
programmable gate array. Its patented array architecture
consists of three types of configurable elements: Input!
Output Blocks, Configurable Logic Blocks and Interconnect. The designer can define individual 1/0 blocks for
interface to external circuitry, define logic blocks to implement logic functions and define interconnection networks
to compose larger scale logic functions.

The XACT development system allows the user to define
the logic functions of the device. Schematic capture is
available for design entry, while logic and timing simulation, and in-circuit debugging are available for design
verification. XACT is used to compile the data pattern
which represents the configuration program. This data
can then be converted to a PROM programmer format file
to create the configuration program storage.

The Logic Cell Array's logic functions and interconnections are determined by the configuration program stored

See the XC3000 Commercial data sheet for a full description.

ORDERING INFORMATION

TIL

XC3020 - 50 PG84 B

50 (50 MHz TOGGLE) - - - - - - - - '

B.

MIl~lD-O",

PG84

70 (70 MHz TOGGLE)

CLASS B, FULLY COMPLIANT

= CERAMIC PIN GRID ARRAY PACKAGE.
84-LEAD

cal 00 = CERAMIC QUAD FLAT PACKAGE.
100 LEAD

TSC0085

1637156

2-119

II

XC3020B Military Logic Cell Array

XC3020 CONFIGURATION PIN ASSIGNMENTS

USER
OPERATION

IIIIIII REPRESENTS A 50Kn TO 100Kn PULL-UP
• IN IT IS AN OPEN DRAIN OUTPUT DURING CONFIGURATION
(I) REPRESENTS AN INPUT
1637168

TSC0085

2-120

PIN ASSIGNMENTS (Continued)
PGAPin
Number
82
C2
81
C1
02
01
E3
E2
E1
F2

XC3020
l'WRDI'l
TCLKIN-I/O
NC
1/0
1/0
1/0
1/0
VO

I/O
I/O

vee

PGAPin
Number
K10

XC3020

J10
K11

OONE-l'G"
07-1/0

J11
H10

XTL 1(OUT)-8LCKIN-VO
OS-VO

H11
F10
G10
G11
G9

1/0
05-1/0
CSO-I/O
04-1/0
1/0

F9
F11
E11
E10
E9
011
010
C11
811
C10

03-110
C"ST-1I0
02-110
110
NC
01-VO
ROY/BOSV-ncrR'-1I0
DO-OIN-I/O
DOUT-I/O

A11
810
89

CCLK
AO-m-I/O
A1-CS2-1/0
A2-1/0
A3-1/0
NC
NC
A1S-1/0

"RESET

vee

F3
G3
G1
G2
F1
H1
H2
J1
K1
J2
L1
K2
K3

1/0
1/0
1/0
1/0
1/0
1/0
I/O
110
M1-Jmi!\TA
MO-RTRIG
M2-VO
HOC-I/O

L2
L3
K4
L4
JS
KS
LS
K6

110
IIlC"-1I0
110
NC
110
110
NC
1N1T-1/0

A10

J6
J7

GNO
1/0
1/0
1/0
liD
110
110
NC
NC
110
XTL2(IN)-1/0

C6
AS
AS
BS
CS
M
B4
A3
A2

NC
NC
A11-1I0
AS-liD

B3
A1

A10-1/0
A9-1/0

L7
K7
L6
L8
KS
L9
L10
K9
L11

A9
88
A8
86
B7
A7
C7

M-I/O

A14-1I0
AS-liD
GNO
A13-1/0
A6-1I0
A12-1/0
A7-1/0

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.

TSC0085

2-121

•

XC3020B Military Logic Call Array

XC3020 100-PIN QFP PINOUTS
Pin No.
COFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

XC3020
GNO
A13·VO
A6·VO
A12·YO
A7·VO
NC
NC
A11·VO
AS·IIO
A1Q.VO
A9·110
NC
NC

l'WRDN

VO
NC
NC
NC

YO
YO
YO
YO
YO
YO
I/O
Vee

27

I/O

28
29
30
31
32
33

YO
YO
YO
YO
VO
VO
VO

34

Pin No.
COFP

35
36
37
38
39
40
41
42
43
44
45
48
47
48
49
50
51
52
53
54
55
56
57
56
59
60
61
62
63
64
65
66
67
68

XC3020
NC
NC
M1-RO
NC

MO-RT
NC
M2·VO
HOC·VO

VO
IDC"-YO
NC
NC

VO
VO
VO
lRlT-vo
GNO
VO

VO
VO
VO
VO
VO
VO
NC
NC
XTAL2-VO
NC

"RE'SET
NC
OONE-l'G:
07-VO
XTAL1-VO

Pin No.
COFP
69
70
71
72
73
74
75
76

XC3020
NC
NC

VO
05-110
CSlr-YO
04-110
VO
Vee

n

D3-ilO

78
79
80
81
82

CSi"-YO

83
84
85
86
87
86
89
90
91
92
93
94

95
96
97
98
99
100

02-110

VO
NC
NC
01-1/0
RC[K-BOSVIROY-11O
DO-OIN-VO
DOUT-VO
CCLK
NC
NC
AO-WS-IIO
A1-CS2-VO
NC
A2-VO
AS-VO
NC
NC
A15-VO
A4-VO
A14-VO
AS·VO

D6-VO

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.

TSC0085

2-122

E:XIUNX
PHYSICAL DIMENSIONS - Conforms to MIL-M-3851 0 Appendix C, Case P-SC.

1.100±o.o12

sa

•

TOP"'EW

0.095
± 0.015

*I

f.r.f i Ti iii iT MI.:;"
I

.018.....J I.....± 0.002 DIA 11-··

0.OS5DIA

A

B

(i

G

D

C

1"1'\

(

"-

L

(

"-

, ,

LD.1 t\ (t\

(1'\ (

,

I" 1'\ I" 1'\ I" 1'\

(
""-I-' "-I-' ",t> ( D.L D.L
"-I-' "- V "- V "LD.L D.LD.
"-I-' , V "-V
INDEX PIN

,

LD.1 D.1 D.

, ,

V

!
T

'V 'V

(t\ (1:\
'I-'
(t\ ( t\ (
1.000 ± o.010

(t\ (
I-'
('t'\ (' t'\ I" t'\ (' t'\ (' 1'\ ('
'-I-' '- I-' '- "-I-' "- V "('tlL: tlL (' I'.t'\
'- V '- V '- I-' '-I-' "-I-'

L D.L:D.&

('1'\

I.

1.1'\

fi'~
~

I.

I'.D.L

'-

0.100TYP

1D.1D.1D.

CD CD

11

L

'V ' V '
'V ' V 'V
1:D....L
'V 'V

.070 DIAI.08 MAX

'V

"-v "-

M~

1"1'\ (t\
'I-' "-...,
(t> ( t\1D.
'I-' 'V
1:D.1D.

1D.1D.1D.

(t\ (

10

J

'V ' V '

1:D.1 b.1b.

(t\ ( t\ (

H

"-'"

"-v

'-I-' '\.

'\.'"

'- V

'-v

~

0.100TYP

1.000
±0.010

9JA=

BOTTOM VIEW
NOTE: INDEX PIN MAY OR MAY NOT BE
ELECTRICALLY CONNECTED TO PIN C2.

30- 35'C1W

eJC= 4

-7'CIW

DIMENSIONS IN INCHES
X1t28

TSC0085

84-Pln PGA Package (Cavity Up)

2-123

XC3020B Military Logic Cell Array

PHYSICAL DIMENSIONS (Continued)

LEADFRAME
0.0045 MIN
0.0080 MAX

r

MARKING

~[

... J il
0.0300.0.0050
BOTTOM VIEW
(LID SIDE UP)
(DIE FACING UP)

~

0.0500 OO.OOSO
0.120 MAX

81DEVIEW

1--------1.275.0.02080.---------1
0.680. 0.020 8 0 " - - - 1

DIMENSIONS IN INCHES
LEAD PITCH 0.025 TYPICAL
TOP VIEW
(DIE FACING DOWN)

8JA = 40-50' om
8JO =5-80 om

PIN SPACING 0.025 TYPICAL
NOTES:
1. LEADS ARE SHIPPED UNFORMED IN CARRIERS IN TRAYS,
TOPSIDE UP
2. FORMING TDOlINFORMATION:
- FANCORT INDUSTRIES.- (201) 575-0610 WEST CALDWELL NJ.
- RISIINDUSTRIES (619) 425-3970 CHULA VISTA, Cil
1t0540-'

TSC0085

10o-Pin CQFP Package

2-124

STATIC BURN-IN CIRCUITS

Vee

1
30 :-

1.3 k

:

1.3 k

•

8.06k

......... 18 co< 18 «
'" a~ l'"a~I
:.;:l&l~~Q'j:: 131ll~~ l3 O--:i2

:

1.3 k

'>

1.5 k ~

rmf-f,T

f--E2

rrr-

~
>-;:;;~~
G3

:

1.15 k

Ml
MO

",8

::E:z:

I§

DONEIPROG
RESET

0

liS-z
C
~C!l

-,>:: ~~ -, -, !:i{;2 ~~ ~~ ~~::
>::..J "''''
~IQ ~~ ......
..J
..J
<0 ...

rt<1T
IJio
Kl0

4.99k

.

1k •

.~ [gJ

-b
NOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 1/6 WAn AT 150·C WITH A
BUILD TOLERANCE OF 1% AND A 5%
TOLERANCE OVER LIFE.
[ ] CAPACITOR HAS 10% TOLERANCE,
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTIC.
~ 30 n RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 WAT lSO·C WITH A
TOLERANCE OF 5%.

163718

TSC0085

2-125

.XC3020B Military Logic Cell Array
STATIC BURN-IN CIRCUITS (Continued)

Vee

~

1
300
.3 k

1.3 k

300

[II

8.0Sk

MN ~ g ~Im J~U~UN ~ ~1~lml&;I$I:!lI~lgll~lo;I8
14

~
~

z

"

~
~

~
~
~

Vee

Vee

~
~

~

,l,.

~
~
~
~

~

~~='~} 1T-

NO" I§
" ""
(1!;/t
MI

0

~~:;

I

F"65

0

I~<;"~

7150

64

~ttttt ~ ~l~l~l~l~ttlml~l~t ~
4.99 k

1k

m~'

76
~
~

~
~

~
~
'""37

Uk 300

#~
~
at7QTsF-

~

~
~
>--'23
~
>----fs"
>--26

1.5 k
1.15 k

88
87
CCLK
88
DOUT
DIN 85

0

PWRDWN

1.3k

g)

,l,.
1637188

NOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 1/8 WAT 150·C WITH A
BUILD TOLERANCE OF 1% AND 5%
TOLERANCE OVER LIFE.
@] CAPACITOR HAS 10% TOLERANCE,
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTICS.
[!] 30-0 RESISTOR IS METAL OXIDE
AND IS RATED FOR 1 W AT
150·C WITH A TOLERANCE OF 5%.
4. USE ON: XC3020-XXCQI00X
5. UNLESS OTHERWISE SPECIFIED,
SOCKET SHALL BE:
ENPLAS
PART NUMBER FPQI32-0.635-01
OR
WELLS
PART NUMBER CP-10582

XC3020-CQ100

TSC0085

2-126

~_ _ _

0_00 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

TEST SPECIFICATION
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.
Absolute Maximum Ratings

Limits

Units

Vcc

Supply voltage relative to GND

-0.5 to +7.0

V

V IN

Input voltage with respect to GND

-0.5 to VCC +0.5

V

VTS

Voltage applied to three-state output

-0.5 to VCC +0.5

V

T STG

Storage temperature (ambient)

-65 to +150

°C

TSOL

Maximum soldering temperature (10 sec @ 1/16 in.)

+260

°C

TJ

Maximum junction temperature

+150

°C

Note:

II

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure
to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Test
High Level Output Voltage
Low Level Output Voltage
Quiescent Operating2
Power Supply Current

Symbol
VOH
VOL
leeo

Power-Down Supply Current

leePD

Leakage Current
Horizontal Long Line
Pull-up Current
Input High Level TIL
Input Low Level TIL
Input High Level CMOS
Input Low Level CMOS

IlL
IRLL
VIHT
V ILT
V1He
VILe

Conditions
-55°C ~ Te ~ +125°C
Vee = 5.0 V ±1 0%

Group A
Subgroups

Limits
Min
Max

1,2,3
1,2,3
1,2,3

TTL Mode, VIN = Vee = 5.5 V
VIN = Vee = 5.5 V,
PWR OWN =OV
Vee = 5.5 V, VIN = Vee and 0 V
Measured as an average

1,2,3
1,2,3
1,2,3
1,2,3

-20

Guaranteed
Guaranteed
Guaranteed
Guaranteed

1,2,3
1,2,3
1,2,3
1,2,3

2.0

Input
Input
Input
Input

High
Low
High
Low

Table 1. Electrical Performance Characteristics

TSC0085

2-127

0.4
1

V
V
mA

15
0.5

mA
mA

20
2.4

mA

3.7

Vee = 4.5 V, IOH = -4.0 mA
Vee = 5.5 V, IOL = 4.0 mA
CMOS Mode, VIN = Vee = 5.5 V

Units

0.8
.7 Vee
.2 Vee

flA
V
V
V
V

XC3020B MIlitary Logic Cell Array

Test

Conditions
-55°C ~ Tc ~ +125°C
Vcc = 5.0 V ±10%

Sym

-70

-50
Group A
Subgroup

Min

I Max

Min

I Max

Units

Switching Characteristics, General LCA
DONEIPROG
Program Width (Low)
Initialization

T pGW
TpGI

PWR DWN3
Power Down Supply

VCCPD

RESET4
M2,M1,MO Setup
M2,M1 ,MO Hold
Width (low) abort

TMR
TRM
TMRW

5 See Fig. 1
6

9,10,11
9,10,11

4

6
7

7

Ils
IlS

3.5

3.5

V

9,10,11
9,10,11
9,10,11

1
1
6

1
1

6

IlS
IlS
Ils

9,10,11
9,10,11
9,10,11
9,10,11

0.5
60
0

0.5
60
0

1,2,3

2
3

6

Switching Characteristics, Peripheral Mode Programming 5
WSLOW
DIN Setup
DIN Hold
Ready/Busy

TCA
TDC
TCD
TWTRB

1 See Fig. 4
2
3

4

IlS
60

60

ns
ns
ns

Switching Characteristics, Slave Mode Programming 5
CCLK,
To DOUT
DIN Setup
DIN Hold
High Time
Low Time
Frequency

TCCD

Tocc
TCCD
TCCH
TCCL
Fcc

9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11

3 See Fig. 5
1
2

4
5

100
60
0
0.5
0.5

Table 1. Electrical Performance Characteristics (Continued)

TSC0085

2-128

1.0
1

100
60
0
0.5
0.5

1.0
1

ns
ns
ns
Ils

IlS
MHz

E:XIUNX

Test

Sym

Conditions
-55°C ~ Tc ~ +125°C Group A
Vcc = 5.0 V ±10% Subgroups

-50
Min

-70

I Max

Min

I Max

Units

Switching Characteristics, Program Readback6 •7
RTRIG Setup

TRTH

1 See Fig. 7

9,10,11

250

CCLK,
RTRIG Setup
RDATA Delay
Clock Low
Clock High

TRTCC
TCCRO
TCCLR
TCCHR

2
3
4
5

9,10,11
9,10,11
9,10,11
9,10,11

200
0.5
0.5

250

ns

200
100
1.0

0.5
0.5

100
1.0

ns
ns
ns
ns

Benchmark Patterns8
TPIO + interconnect + 8 (TllO) +
Top, Measured on 8 eols.
TGKO + TICK + TCKI +
Interconnect
TCKO + TOlO + TILO + TOICK +
interconnect
TILO + TECCK + interconnect

TS1

9,10,11

135

86

ns

TS2

Tested on all CLBs

9,10,11

32

21

ns

TS3

Tested on all CLBs

9,10,11

53

34

ns

TS4

Tested on all CLBs

9,10,11

35

23

ns

TOK PO + Tops - TOPF + TPICK

Tss

Tested on all CLBs

9,10,11

73

53

ns

TCKO + TOLO + Tpus + TICK +
interconnect
TCKO + TOlO + Tpus + TICK +
interconnect
TCKO + TOLO + TIO + TICK +
interconnect
TCKO + TOLO + T IO + TICK +
interconnect

TS6

One long line pull-up

9,10,11

73

48

ns

TS7

The other long line
pull-up
No pull-up, lower
long lines
No pull-up, upper
long lines

9,10,11

83

55

ns

9,10,11

47

31

ns

9,10,11

57

38

ns

TB6
TSg

Table 1. Electrical Performance Characteristics (Continued)

TSC0085

2-129

•

XC3020B Military Logic Cell Array

Test

Sym

Conditions
-55°C::;; Tc::;; +125°C
Vcc = 5.0 V ±10%

-50
Group A
Subgroups

Min

I

-70
Max

Min

I

Max

Units

Application Guidelines, Switching, ClB8
Combinatorial
Reset to CLB output
Reset Direct width
Master Reset pin to CLB out
K Clock9
To CLB output
Additional for Q returning
through F or G to CLB out
Logic-input setup
Logic-input hold
Data In setup
Data In hold (1)
Enable Clock setup
Enable Clock hold
'Clock (High)
'Clock (Low)

TllO
TRIO
TRPW
TMRQ

1 See Fig. 2
9
13

N/A
N/A
N/A
N/A

TCKO
TQLO

8

N/A
N/A

TICK
TCKI
TDICK
TCKDI
TECCK
TCKEC
TCH
TCl

2
3
4
5
6
7
11
12

N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A

14
12
30

20

ns
ns
ns
ns

12
11

8
7

ns
ns

12

9
8

8

12
1
8
6
10
0
9
9

ns
ns
ns
ns
ns
ns
ns
ns

8
1
5
4
7
0
7
7

'These parameters are for clock pulses within an LCA device. For externally applied clock, increase values by 20%.
Application Guidelines, Switching, Internal Buffers8
Clock Buffer
TBUF
Data to Output
Three-state to Output
Single Pull-up
Pair of Pull-ups
Bidirectional

TGCK

N/A

9

6

ns

TIO

N/A

8

5

ns

Tpus
TpUF

N/A
N/A

34
17

22
11

ns
ns

TBIDI

N/A

6

4

ns

Table 1. Electrical Performance Characteristics (Continued)

TSC0085

2-130

Test

Conditions
-55°C::; Tc::; +125°C
Vcc =5.0 V ±1 0%

Sym

-50
Group A
Subgroups Min I Max

-70
Min

I

Max

Units

Application Guidelines, Switching, 1088•10
Pad (package pin)
To inputs TClKIN, BClKIN
To inputs DIRECT IN

TplDC
TplD

110 Clock
To 110 RI input (FF)
110 pad-input setup
110 pad-input hold
To 110 pad (fast)
110 pad output setup
I/O pad output hold
'Clock (High)
'Clock (low)

TIKRI
TplCK
TIKP1
ToKPo
TOOK
ToKO
TIOH
Tlol

4
1
2
7
5
11
12

N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A

Output
To pad (enabled fast)
To pad (enabled slow)

TOPF
Tops

10
10

N/A
N/A

15
40

9
29

ns
ns

Three-State
To pad begin hi-Z (fast)
To pad valid (fast)

TrsHz
TrsoN

9
8

N/A
N/A

18
20

12
14

ns
ns

Master Reset
To input RI
To output (FF)

TRRI
TRPO

13
14

N/A
N/A

35
50

23
33

ns
ns

See Fig. 3
3

6

N/A
N/A

5
9
11

5
6

ns
ns

7

ns
ns
ns
ns
ns
ns
ns
ns

20
0

30
0
18
15
0
9
9

13
10
0
8
8

'These parameters are for clock pulses within an lCA device. For externally applied clock, increase values by 20%.
Table 1. Electrical Performance Characteristics (Continued)

TSC0085
2-131

XC3020B Military Logic Cell Array

Test

Sym

Conditions
-55°C ~ Tc ~ +125°C
Vcc = 5.0 V ±1 0%

·50
Group A
Subgroups

Min

I

·70
Max

Min

200

0
60
0
600
4.0

I

Max

Units

200

ns
ns
ns
ns
Ils

Application Guidelines, Switching, Master Parallel Mode ProgrammingB,11
RCLK,
To Address Valid
To Data Setup
To Data Hold
RCLK High
RCLKLow

T RAC
TORC
T RCO
T RCH
T RCL

1 See Fig.6
2
3
4

5

N/A
N/A
N/A
N/A
N/A

0
60
0
600
4.0

Table 1. Electrical Performance Characteristics (Continued)

TSC0085

2·132

_---.(GTMRW)________

...-------tllI-

MO/M1/M2

DONE/PROO
(OUTPUn

-f®'~®'~f-------=1

PGW
t®T

__J_----,[0
INIT
(OUTPun

USER STATE
-

TPG1

.JI

CONFIGURE

_ _ _ _ _ _C_l_EA..;R,I-S_T_A_T_E_ _ _ _ _ _ _
II
-

\'--_-----1

______________________________________________--{r-NOTE3~

\

Vcc(VAlID)

~

____

,r"":'t-v-----

.I~

CCPD

163719

Figure 1_ General LCA Waveforms

ClB OUTPUT (X,V)
(COMBINATORIAL)

_FGl,,~J

ClB INPUT (A,B,C,D,E)
t=®T1CK

.'..

ClBClOCK

I+----@

TCl --~~

o
ClBINPUT
(DIRECT IN)

ClBINPUT
(ENABLE CLOCK)

°

®TCKI~""""'-----

11""""=-----------""'"

TDICK ---4;"""

TECCK

ClBOUTPUT
(FLIP-FLOP)

ClB INPUT
(RESET DIRECn

ClBOUTPUT
(FLIP-FLOP)
163720

Figure 2_ CLB Waveforms

TSC0085

2-133

XC3020B Military Logic Cell Array

I/O BLOCK (I)

-0-TPID~-f----

VO PAD INPUT

~-G)-l--"-PI-CK--------------

VOCLOCK ------~I
(lK/OK)

r~~----------~I

io'-----

@

TIOl

---'14----

110 BLOCK (RI)

VOBLOCK(O)

VO PAD OUTPUT
(DIRECT)

VO PAD OUTPUT
(REGISTERED)

-------------------£0 TOKPO

J~Ir-@-8r-TSON--@-9TT-,",1r-

I/O PAD TS

VO PAD OUTPUT

----------------~(~

_______________~r__
183721

Figure 3. lOB Waveforms

•.

.

CSllCSO

\

I

CS2

I

\~--------------------~!--------

..

WS

00-07

CCLK

.. . ..,,_ ,.
,,_ • • 1

RDYIBUSY

GROUP
OF8 CCLKs

..

.

-----------------------,
DOUT

_--'x'--_--'x'--____________________-' '-----'X'--_____C
163722A

Figure 4. Peripheral Mode Waveforms

TSC0085

2-134

l:XlUNX

163723

Figure 5. Slave Mode Waveforms

AO-A15

(OUTPUT)

ADDRESS n

ADDRESS n+ 1

CD

TRAC

II

BYTE n

DO-D7

RClK

(OUTPUT)

14------7CCLKs------~I----

CCLK
(OUTPUT)
DOUT
(OUTPUT)

07
BYTE n-1
163724A

Figure 6. Master Parallel Mode Waveforms

TSC0085

2-135

XC3020B Military Logic Cell Array
DONEIPROO
(OUTPUT)

----~/_-----------------------------------

RTRIG

eeLl<

v-------~t~CVT~~--~r-------

RDATA
(OUTPUT)
183725

Figure 7. Program Readback Waveforms

XC3020B Data Sheet Notes
1. Xilinx maintains this specification as a controlled document. To comply with the intent of MIL-STD-883, and to insure the
use of the most recently released device performance parameters, please request a copy of the current revision of this Test
Specification (TSC 0085) from Xilinx.
2. No output current loads, no active input or long line pull-up resistors, and with the device configured with the MAKEBITS
'1ie" option.
3. PWROWN transitions must occur during operational Vee levels.
4. RESET timing relative to valid mode lines (MO, M1, M2) is relevant only when RESET is used to delay configuration.
5. Configuration must be delayed until the INIT of all LeA's is HIGH. m cannot go active until RDV!BUSV goes HIGH.
6. Readback should not be initiated until configuration is complete.
7. DOUT timing is the same as for slave mode.
8. Testing of the Applications Guidelines is modeled after testing specified by MIL-M-38510/605. Devices are first 100%
functionally tested. Benchmark patterns are then used to measure the Application Guidelines. Characterization data are
taken at initial device qualification, prior to introduction of significant changes, and at least twice yearly to monitor correlation
between benchmark patterns, device performance, XACT software timings, and the data sheet.
9. The CLB K to Q output delay (TCKO) plus the shortest possible interconnect delay is always longer than the Data In hold
time requirement (TCKDI) on the same die.
10. VoHage levels of unused pads must be valid logic levels. Each can be configured with the internal pull-up resistor, configured as a driven output, or driven from an external source.
11. At power-up, Vee must rise from 2.0 V to V~ minimum in less than 10 ms. Otherwise, delay configuration using RESET.
12. All timings except TTSHZ and TTSON are measured at 1.5 V level with 50 pF minimum load output. For input signals, rise and
fall times are less than 6 ns, with low amplitude. 0 V, and high. 3 V.
TTSHZ is determined when the output shifts 10% (of the output voHage swing) from VOL level or VOH level. The following
circuit is used:

fuC:

vco

1k

PAD

50pF MIN

J

GND

1k
163713

12. (continued)
TTSON is measured at 0.5 Vpc level with VIN • 0 for 3-State to active High, and VIN =Vee for 3-State to active Low. The
following load circuit is usea:

~VIN

J

~ ... 1 1 k
50pF MIN

163714

TSC0085
2-136

XC30428
Military Logic CeW Array

~XILINX

M

Product Specification. See Note 1.
FEATURES

Number

Logic
Capacity
(gates)

Conflgurable
Logic
Blocks

User
I/O's

Configuration
Program
(bits)

XC3042

4200

144

96

30784

Part

• MIL-STD-883 Class B Processing.
Complies with paragraph 1.2.1
•
•
•
•
•

Field-programmable. gate array
Low power CMOS static memory technology
Standard product. Completely tested at factory
Design changes made In minutes
Complete user control for design cycle.
Secure design process

in internal static memory cells. On-Chip logic provides for
automatic loading of configuration data at power-up or on
command. The program data can reside in an EEPROM,
EPROM or ROM on the circuit board or on a floppy disk or
hard disk.

• Complete PC or workstation based
development system
- Schematic entry
- Auto Placel Route
- Design Editor
- Logic & Timing Simulator
- XACTOR In-circuit Verifier
DESCRIPTION

Several methods of automatically loading the required
data are designed into the Logic Cell Array and are
determined by logic levels applied to mode selection pins
at configuration time. The form of the data may be either
serial or parallel, depending on the configuration mode.
The programming data are independent of the configuration mode selected.

The Logic Cell™ Array (LCA) is a high density CMOS
programmable gate array. Its patented array architecture
consists of three types of configurable elements: InpuU
Output Blocks, Configurable Logic Blocks and Interconnect. The designer can define individual 1/0 blocks for
interface to external Circuitry, define logic blocks to implement logic functions and define interconnection networks
to compose larger scale logic functions.

The XACT development system allows the user to define
the logic functions of the device. Schematic capture is
available for design entry, while logic and timing simulation, and in-circuit debugging are available for design
verification. XACT is used to compile the data pattern
which represents the configuration program. This data
can then be converted to a PROM programmer format file
to create the configuration program storage.

The Logic Cell Array's logic functions and interconnections are determined by the configuration program stored

See the XC3000 Commercial data sheet for a full description.

ORDERING INFORMATION

I
TL ..
----------' L
XC3042 -50 PG132 B

Basic Part Number
50 (50 MHz Toggle)
70 (70 MHz Toggle)

T

MIL-STl).883, Clu, .,

F,'" Compl."

PG132 =Ceramic Pin Grid Array Package, 132-Lead
CQ100 = Ceramic Quad Flat Package 100-Lead
PG84 = Ceramic Pin Grid Array Package, 84-Lead

T8C0117

183726

2-137

II

XC3042B Military Logic Cell Array

PIN ASSIGNMENTS
USER
OPERATION

.... ;

I/O

I/O
I/O
I/O

I/O

IlilM REPRESENTS A 50 kn TO 100 kn PULL·UP
* INIT IS AN OPEN-DRAIN OUTPUT DURING CONFIGURATION
(I) REPRESENTS AN INPUT
Xl130

TSC0117
2-138

l':XIUNX
PIN ASSIGNMENTS (COntinued)
84PGAPln
Number
B2
C2
Bl
Cl
02
01
E3
E2
El
F2

XC3042
I'WRlm
TCLKIN-11O
VO
VO
VO
110
VO
VO
VO

84PGAPln
Number
Kl0
Jl0
Kll

Jll
Hl0
Hll
FlO
Gl0
GIl

XC3042
"RESET
OONE-PG
07-VO
XTL I(OUT)-BLCKIN-VO
D6-VO
110
05-110
CSlJ-VO
04-VO

1/0

G9

110

F3

vee

vee

G3
Gl
G2
Fl
HI
H2
Jl
Kl
J2
11
K2
K3
L2
L3
K4
L4
J5
K5
L5
K6

110

F9
Fll
Ell
El0
E9
011
010
Cll
911
Cl0
All
910
99
Al0
A9
B8
AS
B8
B7
A7
C7

J6
J7
L7
K7
Ls
LB
KB
L9
LIO
K9
Lll

110
VO
VO
VO
VO

110
110
Ml-R'OAT)(
MO-RTRIG
M2-1/0
HOC-flO

110

I:OC"-vo
VO
VO
VO
VO
VO
m-VO

GND

C6
AS
AS

VO
VO
VO

B5

110
110

C5
A4
B4
AS
A2

I/O
VO
I/O
VO
XTL2(IN)-VO

B3
AI

D3-VO

m-II0
02-110

110
VO
01-VO
ROYIBUSY-RC[R'-1I0
DO-OIN·II0
DOUT-II0
CCLK
AO-WS-VO
Al-CS2-VO
A2-1/0
AS-VO
VO
VO
AI5-VO
M-VO
AI4-VO
AS-I/O

GND
AI3-VO
AS-VO
AI2-liO
A7-VO
I/O

110
AlI-liO
AB-VO
Ala-liO
A9-1I0

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.

TSC0117
2-139

II

XC3042B Military Logic Cell Array

PIN ASSIGNMENTS (Continued)
COFP
Pin No.

PGAPIn
Number

13

C4

GNO

47

F13

14

Al

PWRON

46

15

C3

VO

16

B2

VO

17

B3

VO

B4

VO'

18

C5

VO

Function

COFP
Pin No.

COFP
Pin No.

PGA PIn

VO

81

P4

F14

VO

82

P3

VO

49

G13

VO

83

M5

01-VO

50

G14

INIT-VO

64

N4

RCLK-8USY/ROY-va

G12

vcc·

P2

VO'

51

H12

GNO

N3

52

H14

VO

PGAPln
Nu......'

Function

Number

Function
VO

VO'

85

N2

Do-OIN-VO

19

M

VO

53

H13

va

66

M3

DOUT-va

20

B5

VO

54

J14

VO

87

PI

eeLK

21

C6

VO

55

J13

va

88

M4

VCC

22

AS

VO

66

K14

VO

89

L3

GNO

23

B5

VO

57

24

AS

VO

25

B7

J12

VO

90

M2

ACl-WS-11O

K13

VO'

91

Nl

Al-CS2-VO

92

Ml

va

K3

VO'

L13

110'

C7

GNO'

SS

K12

VO

26

C6

VCC

59

M14

VO

93

L2

A2-VO

27

A7

VO

60

N14

VO

94

Ll

A3-va

28

B6

VO

61

M13

XTAL2-VO

85

K2

VO
VO
AI5-VO

VO

29

AS

VO

62

L12

GNO

96

J3

30

A9

110

63

P14

RESET

97

Kl

31

B9

VO

64

MIl

VCC

96

J2

M-va

32

C9

110

65

N13

DONE-PG

99

HI

AI4-VO

33

Al0

110

66

M12

07-va

100

H2

A5-VO

Bl0

VO'

67

P13

XTAL1-VO

1

H3

GNO

34

Cl0

va

N12

VO'

35

Bll

VO

P12

VO'

38

812

VO

NIl

68

G3

vee •

2

G2

AI3-1/O

06-VO

3

Gl

A6-1/O

F2

AI2-1/O

C12

VO'

69

Ml0

VO

4

37

; 813

Ml-RO

70

Nl0

VO

5

El

A7-VO

38

Cll

GNO

71

Pl0

VO

6

F3

VO

39

A14

MCl-RT

72

M9

05-VO

7

E2

VO

40

012

VCC

73

N9

CSCl-VO

8

01

All-I/O

41

C13

M2-VO

74

N8

D4-VO

9

D2

AB-va

42

814

HOC-VO

75

P7

VO

E3

VO'

76

M8

vee

Cl

VO'

M7

GNO'

10

Bl

Al0-1/O

N7

03-VO

11

C2

AII-VO

12

D3

vee

43

C14

VO'

E12

VO'

013

VO

77

44

014

LOC-VO

78

P6

CS1-va

45

F12

VO

78

Me

D2-VO

46

E14

VO

60

N5

va
X',01A

Unprogrammed lOBs have a default pull-up_ This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.
• Indicates unconnected bond pads for the CQFP-1 00 package

TSC0117

2-140

l:XJUNX
PHYSICAL DIMENSIONS - Conforms to MIL-M-3851 0 Appendix C, Case P-8C.

1-------l.l00±0'012

50------1'1 ,

0.130
±0.010

I--' 0.100lYP

1.000 ± 0.010

11'\ 11'\

11'\ 11'\

;t ;to

~~

fJ- 'Y

1

'Y'Y

'Y

I-Efj-E
fEfj-E ~

0.100
lYP

G

io."lf,

i-E~

fJ-

INDEX PIN

/-.e

TYI'.O.070

D~.08MAX

'p'V
-( fj-t~

II

f.:\

/'6.

8 JA -

3O-35°CIW

~

..LA

-u~

T

0.018
± 0.002 DIA
0.050
±0.010

'-".

1

I

6

7

10

11

BOTTOMYIEW
NOTE: INOEX PIN MAY OR MAY NOT BE
ELECTRICALLY CONNECTED TO PIN C2.
DIMENSIONS IN INCHES
11OS35C

84-Pln PGA Package (Cavity Up)
1--------l.27StO.020SO.--------I

LEADFRAME
0.0045 MIN
O.ooaoMAX

r"'[
0.145 MAXJ

4XO.02OR

LEAD PITCH O.025lYPICAL

MARKING

0.0300 .0.0050

0.0500 .0.0050
0.120 MAX

DIMENSIONS IN INCHES

SIDE VIEW

8JA = 40-50° CIW
8JC = 5-8° eIW

TSC0117

NOTES:
1. LEADS ARE SHIPPED UNFORMED IN CARRIERS IN TRAYS.
TOPSIDE UP
2. FORMING TOOL INFORMATION:
- FANCORT INDUSTRIES - (201) 57!H1610 WEST CALDWELL NJ.
- RISI INDUSTRIES (819) 425-3970 CHULA VISTA, CA.

100-Pln CQFP Package (Cavity Down)

2-141

110S4OC

XC3042B Military Logic Cell Array

PHYSICAL DIMENSIONS (Continued)

0.040 X 45'

1

4PLCS

:2

3

4

6

6

7

8

9

10

11

12

13

0000000,000000
N00000000000000
M00000000000000
000
000
000
000
000
000
000
+
000
008
000
000
000
000
0000
c 008
000000
000 000000
000000
p

PIN
KOVAR

14

1

0

TYP 0.070 DIA
± 0.005

0,O18± 0.002 DIA.J
132 PLCS

L

K

J

~

H

G

O. 45
± 0.006

1.460
± 0.015

F

E

B

0.070
± 0.01 SO

1-----±°iJ.gg7'--~
i+------1.300TYP------>i

1---------±104J,~5------->I

U
O.085

BOTTOM VIEW

± 0,009

1105388

132·Pin PGA Package (Cavity Down)

TSC0117

2-142

STATIC BURN-IN CIRCUITS
Vee

1
30
~>

1.3 k

<1ti3 ~ ~ ~ =t l3 :£ ~ ~ 13 ~ !< ~ 18 ~ 18 ~ ~ ~ ~I

@)
1.3 k

~ 1.15 k

> 8.06k
~~
~
~
~

c

PWRDWN

CCLI<
DOUT
DIN

z

Cl

~
~

1.5k

~.

~
~
~
~
~
I-j:g

~
~

XC3042
PG84

Vee

Vee

G9

~

715

I Gl0

~
~
~

'-'f1"""
'Itr"
"J2'
--:t1
--=-

~

~
E9

~
E2

'Fa
Ta
~
f-&-

1.3 k
All
Cl0
Bll

1.5k

II

•

Fa
f-i:ffi""
I Hl0

fjff-

Ml
MO

DONEIPROO

Ng
::E:z:

~I~

RESeT

0
J~C
-2

I§

tr
fJiO
Kl0

;i;Cl

~~ ~~ -,>:: ~~ ~t; !::i~ ~!I ~~

"''''

o~

::i

.....
::i

4.99k

1 k.,.
~

.~( [[I

-:!:NOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 118 WATT AT 150'C WITH A
BUILD TOLERANCE OF 1% AND A 5%
TOLERANCE OVER LIFE.
[gJ CAPACITOR HAS 10% TOLERANCE,
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTIC.
30 n RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 W AT 150'C WITH A
TOLERANCE OF 5%.

iII

1637t8

XC3042-PG84

TSC0117
2-143

XC3042B Military Logic Cell Array

STATIC BURN-IN CIRCUITS (COntinued)
Vee

~

1
.3k

1.3 k

30n
30n

8.(16k

rn

~ ~ Jm JJJJJN -~JJJ~JJJ8m

~~

14

~

~

PWRDWN

Cl

~

CCLK

DOUT

88

~

~
~
~

~
~
~

~
~

~

'25
~

~
~
~
~
~
~

Vee

Vee

,

~
~

I~

rn-

~

res~~~~} t"67""

~

~
~

rn~
'7ii""""

'"35

'"38

1.5k 30n

BB
87

~

~

~

1.Sk
1.15k

DIN BS

r--H-

~

~1.3k

Ng

Ml
0

::E

::El:

!Il1~ ~

~

tF-

0

18
....

liS~~0

71sn

64

~~t ~l~tl~l~l5! 0; ~ttrrr'lf8trl;;t !3

I
4.99 k

1k

rn~'

~
NOTES:
1. UNLESS OTHERWISE SPECIFIED, AlL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 1/8 W AT 150'C WITH A
BUILD TOLERANCE OF 1% AND 5%
TOLERANCE OVER LIFE.
~ CAPACITOR HAS 10% TOLERANCE,
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTICS.
~ 30-0 RESISTOR IS METAL OXIDE
AND IS RATED FOR 1 W AT
150'C WITH A TOLERANCE OF 5%.
4. USE ON: XC3020-XXC0100X
5. UNLESS OTHERWISE SPECIFIED,
SOCKET SHALL BE:
ENPLAS
PART NUMBER FPC.1 32-0.635-01
OR
WELLS
PART NUMBER CP-l0582
1637188

XC3042-CQ100

TSC0117

2-144

£XllINX
STATIC BURN-IN CIRCUITS (Continued)
Vee

I
V•• ~~I--~

4.111 •

•01""

N....

Xt129

NOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL RESISTORS ARE METAL FILM
AND ARE RATED FOR 1/8 W AT 150"0 WITH A BUILD TOLERANCE OF
1% AND 5% TOLERANCE OVER LIFE.
2. CAPACITOR HAS 10% TOLERANCE, 50 V RATING WITH AN X7R.
TEMPERATURE CHARACTERISTICS.
3. 30-0 RESISTOR IS METAL OXIDE AND IS RATED FOR 1 W AT
150'C WITH A TOLERANCE OF 5%.

XC3042-PG132

TSC0117
2-145

XC3042B Military Logic Cell Array
TEST SPECIFICATION
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.
Units

Limits

Absolute Maximum Ratings
Vcc

Supply voltage relative to GND

-0.5 to +7.0

V

VIN

Input voltage with respect to GND

-0.5 to Vee +0.5

V

VTS

Voltage applied to three-state output

-0.5 to Vee +0.5

V

TSTG

Storage temperature (ambient)

-65 to +150

°C

TSOL

Maximum soldering temperature (10 sec @ 1/16 in.)

+260

°C

TJ

Maximum junction temperature

+150

°C

Note:

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress retings only, and functional operation of the device at these or any other
conditions beyond those listed under Recommended Operating Conditions Is not implied. Exposure
to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Test

Symbol

High Level Output Voltage
Low Level Output Voltage
Quiescent Operating2
Power Supply Current

VOH
VOL
leeo

Power-Down Supply Current

leePD

Leakage Current
Horizontal Long Line
Pull-up Current
Input High Level TTL
Input Low Level TTL
Input High Level CMOS
Input Low Level CMOS

IlL
IRLL
VIHT
VILT
VIHC
VILe

Conditions
-55°C s; Te s; +125°C
Vee =5.0 V±10%

Group A
Subgroups

Vee = 4.5 V, IOH = -4.0 mA
Vee= 5.5 V, IOL = 4.0 mA
CMOS Mode, Vin = Vcc = 5.5 V

1,2,3
1,2,3
1,2,3

TTL Mode, Vi" = Vee = 5.5 V
Vln = Vee = 5.5 V,
PWRDWN=OV
Vee = 5.5 V, Vin = Vee and 0 V
Measured as an average @
Vee =5.5V
Guaranteed Input High
Guaranteed Input Low
Guaranteed Input High
Guaranteed Input Low

1,2,3
1,2,3

Table 1. Electrical Performance Characteristics

TSC0117
2-146

Limits
Max
Min
3.7
0.4
1.650
11.15
1150

1,2,3
1,2,3

-20

1,2,3
1,2,3
1,2,3
1,2,3

2.0

20
2.4

0.8
.7 Vee
.2 Vee

Units
V
V
mA
mA

ItA
ItA
mA
V
V
V
V

Test

Conditions
-55°C ~ Tc ~ +125°C
Vcc = 5.0 V ±10%

Sym

-70

-50
Group A
Subgroup

Min

1

Max

Min

1

Max

Units

Switching Characteristics, General LCA
DONEIPROG
Program Width (Low)
Initialization

T pGW
TpGI

PWR OWN"
Power Down Supply

VCCPD

RESEP
M2,M1 ,MO Setup
M2,M1 ,MO Hold
Width (low) abort

TMR
TRM
TMRW

5 See Fig. 1
6

9,10,11
9,10,11

1,2,3

2
3
4

6

6
7

7

3.5

9,10,11
9,10,11
9,10,11

1
1
6

9,10,11
9,10,11
9,10,11
9,10,11

0.5
60

V

3./?

~

Jls
Jls

::::::::

JlS
Jls
JlS

::::::::

I::

Switching Characteristics, Peripheral Mode Programming 5
WRTLOW
DIN Setup
DIN Hold
Ready/Busy

1 See Fig. 4

2
3
4

°

60

Switching Characteristics, Slave Mode Programming 5
CCLK,
To DOUT
DIN Setup
DIN Hold
High Time
Low Time
Frequency

TCCD
Tocc
TCCD
TCCH
TCCL
Fcc

3 See Fig. 5

JOt"""
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11

1
2
4
5

100

°

0.5
0.5

2-147

.•..".'.' !"""""

100

60

60

Table 1. Electrical Performance Characteristics (Continued)

TSC0117

JlS
ns
ns
ns

1.0
1

°

0.5
0.5

1.0
1

ns
ns
ns
JlS
Jls
MHz

II

XC3042B Military Logic Cell Array

Test

Sym

Conditions
-55°C S; Tc S; +125°C Group A
VCC =5.0 V ±10% Subgroups

-50
Min

-70

I Max

Min

I Max

Units

Switching Characteristics, Program Readback6•7
RTRIG Setup

TRTH

1 See Fig. 7

CCLK.
RTRIG Setup
RDATA Delay
Clock Low
Clock High

TRTCC
TCCRO
TCClR
TCCHR

2
3
4
5

9,10,11

250

9,10,11

200

!'I, 10, 11
9,10,11
9,10,11

1.2
0.5

250

ns

200
100
2.0

100
2.0

'P'

ns
ns
IlS
J.1S

1.2

O'

>

PWRDWN

R3

~

CCLK1
DOUT

~

~

~

~
~
~
~
~
~
~
~
~
~
~
~

III

rra-r-wr-m-

f-frVso
Vee

Vos
Vee

XC3090
PG 175

N9

~

~

~
rrm-

f-ffo-

rmt~

I-ffo-

I-fi'ifl

f-jifo-

rm"1ttt

fjIT-

~

r-mT
f-j5ti'tit

f-5'ji-

~

~

~

hITt
~

iiit
~
r-:m=-

~

~
~

~

fiIT"
f-&'

~

rm-fTs-em-

I-'p'T-

~

~

1.5 k

rmfir

I-fg~

fim-

~

1.15 k
715

~
r-rsr-mfTsr-rsf-i&-

~
08

r-m-

~

1.5k

DONE/PGM\

jMl

' (;,',.8

VCC\

>:;:t

R~

It:~~~

~ ~I§

0

(I)

'-j;'fa""'i';t-

f-i:m-

~

~ ~l~rr ~n~nl'~lf,l~lil~ ~ ~ ~l~l~l~l~l~rl~lil~l~l~l~l~l~tr

"'''' WCDOOO
00
1k

LLWWU.u..(!)C!'''r:r

1.3 k

1.3 k

P14
R15
4.99 k

:r~~'~~~~~~~~z~z~~~z

1.3 k

,01~Ft
I]]

.1
NOTES:
1. UNLESS OTHERWISE SPECIFIED. ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 1/8 WAT 150"C WITH A
BUILD TOLERANCE OF 1% AND A 5%
TOLERANCE OVER LIFE.
CAPACITOR HAS 10% TOLERANCE.
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTIC.
30" RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 WAT 150'CWITHA
TOLERANCE OF 5%.

ill

III

TSC0097

2-163

1637 31A

XC3090B Military Logic Cell Array

STATIC BURN-IN CIRCUITS (Continued)
Vee

30

4.02 k

!]]

NOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR liB W AT 150°C WITH A
BUILD TOLERANCE OF 1% AND A 5%
TOLERANCE OVER LIFE.
[b] CAPACITOR HAS 10% TOLERANCE,
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTIC.
[IJ 30 Sl RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 W AT 150°C WITH A
TOLERANCE OF 5%.

TSC0097

2-164

E:XJUNX
TEST SPECIFICATION
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.
Absolute Maximum Ratings

Units

Limits

Vee

Supply voltage relative to GND

-0.5 to +7.0

V

VIN

Input voltage with respect to GND

-0.5 to Vee +0.5

V

VTS

Voltage applied to three-state output

-0.5 to Vee +0.5

V

TSTG

Storage temperature (ambient)

-65 to +150

°C

TSOL

Maximum soldering temperature (10 sec@ 1116 in.)

+260

°C

TJ

Maximum junction temperature

+150

°C

Note:

II

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, and functional operation 01 the device at these or any other
conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure
to Absolute Maximum Ratings conditions lor extended periods 01 time may affect device reliability.

Test

Symbol

High Level Output Voltage
Low Level Output Voltage
Quiescent Operating2
Power Supply Current

VOH
VOL
leeo

Power-Down Supply Current

leePD

Leakage Current
Horizontal Long Line
Pull-up Current
Input High Level TTL
Input Low Level TTL
Input High Level CMOS
Input Low Level CMOS

Conditions
-55°C s Te s +125°C
Vee = 5.0 V ±10%

Group A
Subgroups

Limits
Min
Max

Vee = 4.5 V,I OH = -4.0 rnA
Vee = 5.5 V, IOL = 4.0 rnA
CMOS Mode, Yin = Vee = 5.5 V

1,2,3
1,2,3
1,2,3

TTL Mode, Yin = Vee = 5.5 V
Vln=~5.5V,

1,2,3
1,2,3

IlL
IRLL

PWRDWN=OV
Vee = 5.5 V, Yin = Vee and 0 V
Measured as an average

1,2,3
1,2,3

-20

VIHT
VILT
VIHe
VILe

Guaranteed Input High
Guaranteed Input Low
Guaranteed Input High
Guaranteed Input Low

1,2,3
1,2,3
1,2,3
1,2,3

2.0

Table 1. Electrical Performance Characteristics

TSCOO97

2-165

Unit~

0.4
3

V
V
rnA

15
2.5

rnA
rnA

20
2.4

jJA
rnA

3.7

0.8
.7 Vee
.2 Vee

V
V
V
V

XC3090B Military Logic Cell Array

Test

Conditions
-55°C ~ Tc ~ +125°C
V cc = 5.0 V ±1 0%

Sym

-50
Group A
Subgroup

Min

-70

I Max

Min

I Max

Units

Switching Characteristics, General LCA
DONEIPROG
Program Width (Low)
Initialization

T pGW
TpGI

PWR DWN3
Power Down Supply

V CCPD

RESET4
M2,M1 ,MO Setup
M2,M1 ,MO Hold
Width (low) abort

TMR
TRM
TMRW

5 See Fig. 1
6

9,10,11
9,10,11

7

7

Il s
IlS

3.5

3.5

V

9,10,11
9,10,11
9,10,11

1
1
6

1
1
6

IlS
Ils

9,10,11
9,10,11
9,10,11
9,10,11

0.5
60

0.5
60

Ils

1,2,3

2
3
4

6

6

itS

Switching Characteristics, Peripheral Mode Programming S
WSLOW
DIN Setup
DIN Hold
Ready/Busy

TCA
Toe
TCD
TWTRB

1 See Fig. 4
2
3

4

°

60

°

60

ns
ns
ns

Switching Characteristics, Slave Mode Programming S
CCLK,
To DOUT
DIN Setup
DIN Hold
High Time
Low Time
Frequency

Tcco
TDCC
TCCD
TCCH
TCCl
Fcc

9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11

3 See Fig. 5
1
2
4
5

°

0.5
0.5

Table 1. Electrical Performance Characteristics (Continued)

TSC0097

2-166

100

100
60

60

1.0
1

°

0.5
0.5

1.0
1

ns
ns
ns
itS
itS
MHz

E:XllINX

Test

Sym

Conditions
-55°C ~ Tc ~ +125°C Group A
Vcc =5.0 V ±10% Subgroups

-50
Min

-70

I Max

Min

I Max

Units

Switching Characteristics, Program Readback6•7
RTRIG Setup

TRTH

1 See Fig. 7

9,10,11

250

CCLK,
RTRIGSetup
RDATA Delay
Clock Low
Clock High

TRTCC
TCCRO
TCClR
TCCHR

2
3
4
5

9,10,11
9,10,11
9,10,11
9,10,11

200

250

ns

200
100

1.2
0.5

1.2
0.5

100
2.0

ns
ns
I1S
!1S

Benchmark Patterns8
TPf +interconnect +20 (TllO) +
OP' Measured on 8 cols.
TCKO + TICK + TCKI +
interconnect
TCKO + TOLO + TllO + TOICK +
interconnect
TllO + TECCK + interconnect

TBl

9,10,11

303

194

ns

TB2

Tested on all CLBs

9,10,11

32

21

ns

TB3

Tested on all CLBs

9,10,11

53

34

ns

T84

Tested on all CLBs

9,10,11

35

23

ns

TOKPO + Tops -TOPF + TPICK

TBS

Tested on all CLBs

9,10,11

73

53

ns

TCKO + TOlO + Tpus + TICK +
interconnect
TeKO + TOlO + Tpus + TICK +
interconnect
TCKO + TOlO + TIO + TICK +
interconnect
TCKO + TOLO + TIO +TICK +
interconnect

Too

One long line pull-up

9,10,11

73

48

ns

TS7

The other long line
pull-up
No pull-up, lower
long lines
No pull-up, upper
long lines

9,10,11

83

55

ns

9,10,11

47

31

ns

9,10,11

57

38

ns

TBB
Tag

Table 1. Electrical Performance Characteristics (Continued)

TSCOO97

2-167

II

XC3090B Military Logic Cell Array

Test

Sym

Conditions
-55°C::; Tc::; +125°C
Vcc =5.0 V ±10%

-50
Group A
Subgroups Min I Max

-70
Min \ Max

Units

Application Guidelines, Switching, ClB8
Combinatorial
Reset to CLB output
Reset Direct width
Master Reset pin to CLB out
K Clock9
To CLB output
Additional for Q returning
through F or G to CLB out
Logic-input setup
Logic-input hold
Data In setup
Data In hold (1)
Enable Clock setup
Enable Clock hold
'Clock (High)
'Clock (Low)

N/A
N/A
N/A
N/A

TllO
TRIO
TRPW
TMRO

1 See Fig. 2
9
13

TCKO
TOLO

8

N/A
N/A

TICK
TCKI
TOICK
TCKOI
TECCK
TCKEC
TCH
TCl

2
3
4
5
6
7
11
12

N/A
N/A
N/A

N/A
N/A
N/A
N/A
N/A

14
12
40

34

ns
ns
ns
ns

12
11

8
7

ns
ns

12

9
8
8

12
1
8
6
10
0

ns
ns
ns
ns
ns
ns
ns
ns

8
1
5
4
7
0
7
7

9

9

'These parameters are for clock pulses within an LCA device. For externally applied clock, increase values by 20%.
Application Guidelines, Switching, Internal Buffers8
Clock Buffer
TBUF
Data to Output
Three-state to Output
Single Pull-up
Pair of Pull-ups
Bidirectional

TGCK

N/A

9

6

ns

TIO

N/A

8

5

ns

Tpus
TpUF

N/A
N/A

46
22

38
16

ns
ns

'T8101

N/A

6

4

ns

Table 1. Electrical Performance Characteristics (Continued)

TSCOO97

2-168

Conditions
-55°C:s; Tc:S; +125°C
Vcc = 5.0 V ±10%

Sym

Test

-50
Group A
Subgroups

Min

I

-70
Max

Min \ Max

Units

Application Guidelines, Switching, 1088,10
Pad (package pin)
To inputs TClKIN, BClKIN
To inputs DIRECT IN

See Fig. 3
T ploc
T plO

3

N/A
N/A

TIKAI
TplCK
TIKPI
TOKPO
TOOK
TOKO
T IOH
T lol

4
1
2
7
5
6
11
12

N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A

TOPF
Tops

10
10

N/A
N/A

15
40

9
29

ns
ns

Three-State
To pad begin hi-Z (fast)
To pad valid (fast)

TTSHZ
TTSON

9
8

N/A
N/A

14
20

12
14

ns
ns

Master Reset
To input RI
To output (FF)

TAAI
T APO

13
14

N/A
N/A

37
53

33
47

ns
ns

1/0 Clock
To 1/0 RI input (FF)
1/0 pad-input setup
1/0 pad-input hold
To 1/0 pad (fast)
110 pad output setup
110 pad output hold
'Clock (High)
'Clock (low)
Output
To pad (enabled fast)
To pad (enabled slow)

5
9

11
30
0

5
6

ns
ns

7

ns
ns
ns
ns
ns
ns
ns
ns

20
0
18

13

15
0

10
0

9
9

8
8

'These parameters are for clock pulses within an lCA device. For externally applied clock, increase values by 20%.
Application Guidelines, Switching, Master Parallel Mode Programming8,l1
RClK,
To Address Valid
To Data Setup
To Data Hold
RClK High
RClK low

T AAC
T OAC
TACO
TACH
T ACl

1 See Fig.6
2
3
4
5

N/A
N/A
N/A
N/A

N/A

0
60
0
600
4.0

Table 1. Electrical Performance Characteristics (Continued)

TSC0097

2-169

200

0
60
0
600
4.0

200

ns
ns
ns
ns

.JlS

II

XC3090B MIIHary Logic Cell Array

MRW) - - - - - - - - - .--________I '---(8)T
...

MOIM11M2

DONEli5'ROO

---f®'~®'~f-------~0TPGW=-1

(OUTPUT)

__J__-,[0 TPG1
jjijj'f
(OUTPUT)

USER STATE

.

..I/

..

""-_ _ _ _ _ _C_LE_A...Ri!-S_TA_T_E_ _ _ _ _ _ _

-

CONFIGURE

.

,'--_ _-oJ/
j+-NOTE 3-+j
Vrx (VALID)

--------------------------~\

..

Ir~t---

:v

'-----1,

V

CCPD
16371t

Figure 1. General LCA Waveforms

CLB OUTPUT (X,V)
(COMBINATORIAL)

CLB INPUT (A,B,C,D,E)

CLBCLOCK

_F®,~3
t® TICK-~'",,....::"'------'1
@

TCL

8) T01CK
CLBINPUT
(DIRECT IN)

®

TECCK

CLB INPUT
(ENABLE CLOCK)

CLBOUTPUT
(FLIP-FLOP)

CLB INPUT
(RESET DIRECn

CLBOUTPUT
(FLIP· FLOP)
183720

Figure 2. CLB Waveforms
TSCOO97

2-170

E:XIU~~X

®"Dt t

1/0 BLOCK (I)

1/0 PAD INPUT

CD TPICK

~

.. CD

TIKPI;a:

1/0 CLOCK
(lK/OK)

@

TIOl

VO BLOCK (RI)

RESET

1/0 BLOCK (0)

III

@TOp

VO PAD OUTPUT
(DIRECT)
f0TOKPO

1/0 PAD OUTPUT
(REGISTERED)

J

VO PADTS

110 PAD OUTPUT

ir@

@TTSHz:f

TTSON

(

f-

1637 21

Figure 3. lOB Waveforms

CSi/CSO

\

I

CS2

I

\

,

.•
)

I

•

.

Ws

~

---------

00-07

CCLK

•

I

•

I

\. .... .. I

RDY/BUSY

•

GROUP
OF8 CCLKs

I
•

...... ,

I

\,

.
I

- ............................... 1

DOUT

_--"x'--_--'x'-_____

-----I

TSCOO97

'------'X"-_--"C

Figure 4. Peripheral Mode Waveforms

2-171

163722

XC3090B Military Logic Cell Array

DIN

CCLK

=t o 'OC'f@""]
l-14--~~

DOUT
(OUTPUT)

0

r-

'J'" @'=

TCCH

---_1i44~

(l)Tcco

BITN~

l--------~

BITN
1637 23

Figure 5. Slave Mode Waveforms

Ao-A15
(OUTPUT)

00-07

ADDRESS n

ADDRESS n + 1

\:

------------------~j~----~~~-----BYTE n

RCLK
(OUTPUT)
14--------7CCLKs------~~----

CCLK
(OUTPUT)
DOUT
(OUTPUT)

07
BYTE n-1
1637 24A

Figure 6. Master Parallel Mode Waveforms

TSCOO97

2-172

E:XIUNX
DONEIPROG
(OUTPUn

_--£..1. _._. _._. ___ ._._. _.___ ._._._._.___ ._

RTRIG

CVT~~--~r--------

CCLK

RDATA
(OUTPun

1G37 25

Figure 7. Program Readback Waveforms

XC3090B Data Sheet Notes
1. Xilinx maintains this specification as a controlled document. To comply with the intent of MIL-STD-883, and to insure the
use of the most recently released device performance parameters, please request a copy of the current revision of this Test
Specification (TSC 0097) from Xilinx.
2. No output current loads, no active input or long line pull-up resistors, and with the device configured with the MAKEBITS
'1ie" option.
3. PWRDWN transitions must occur during operational Vcc levels.
4. RESET timing relative to valid mode lines (MO, M1, M2) is relevant only when RESET is used to delay configuration.
5. Configuration must be delayed until the lNIT of all LCAs is High. WS cannot go active until RDY/BUS? goes High.
6. Readback should not be initiated until configuration is complete.
7. DOUT timing is the same as for slave mode.
8. Testing olthe Applications Guidelines is modeled after testing specified by MIL-M-3851 0/605. Devices are first 100%
functionally tested. Benchmark patterns are then used to measure the Application Guidelines. Characterization data are
taken at initial device qualification, prior to introduction of significant changes, and at least twice yearly to monitor correlation
between benchmark patterns, device performance, XACT software timings, and the data sheet.
9. The CLB K to Q output delay (TCKO) plus the shortest possible interconnect delay is always longer than the Data In hold
time requirement (TCKDI) on the same die.
10. Voltage levels of unused pads must be valid logic levels. Each can be configured with the internal pull-up resistor, configured as a driven output, or driven from an external source.
11. At power-up, Vcc must rise from 2.0V to Vee minimum in less than 10 ms. Otherwise, delay configuration using RESET.
12. All timings except TTSHZ and TTSON are measured at 1.5 V level with 50 pF minimum load output. For input signals, rise and
fall times are less than 6 ns, with low amplitude = OV, and high = 3V.
TTSHZ is determined when the output shifts 10% (of the output voltage swing) from VOL level or VOH level. The following
circuit is used:

~

vcc

1k

PAD

50pF MIN

11k

GND
1637 13

12. (continued)
TTSON is measured at 0.5 Vr:.c level with VIN = 0 for 3-State to active High, and VIN = VCC for 3-State to active Low. The
following load circuit is usea:

~VIN

. . I1

~

lk

50pF MIN

1637 14

TSCOO97

2-173

II

XC3090B Military logic Cell Array

TSCOO97

2-174

XC1736A/XC1765 Serial
Configuration PROM
Product Specification
vpp

FEATURES
• One-Time Programmable (OTP) 36,288 x 1 bit and
65,536 x 1 bit serial memories designed to store
configuration programs for Programmable Gate Arrays

PROGRAMMING
DATA SHIFT
REGISTER

• Simple interface to Logic Cell™ Arrays (LCA) requires
only one user 1/0 pin
• Daisy chain configuration support for multiple XC2000
or XC3000 LCAs

II

• Cascadable to support additional configurations or
future higher-density arrays
• Military XC1765R screening and quality conformance
inspection is patterned after the requirements of
MIL-STD-883, methods 5004 and 5005.
• Low-power CMOS EPROM process
• Programmable reset polarity for the XC 1765
• Available in the space-efficient 8-pin plastic or ceramic
DIP, or in 20-pin surface-mount PLCC package
• PC-based programming supported by the XILINX
DS112 and other leading programmer manufacturers
DESCRIPTION
The XC1736A1XC1765 Serial Configuration PROMs (SCP)
provide an easy-to-use, cost-effective configuration
memory for Xilinx Field Programmable Gate Arrays. Both
the XC1736A and the XC1765 are packaged in the economical 8-pin plastic DIP and are also available in the
popular 20-pin Plastic Leaded Chip Carrier. The XC1765
is also available in an 8-pin ceramic DIP that supports the
military temperature range. The XC17XX family uses a
simple serial-access procedure to configure one or more
LCA devices. The XC1765 organization (65,536 x 1)
supplies enough memory to configure one XC3090 or
multiple smaller LCAs. Multiple configurations for a single
LCA can also be loaded from the XC17XX family .. Using a
speCial feature of the XC1765, the user can select the
polarity of the reset function by programming a special
EPROM bit.
The XC1736A1XC1765 can be programmed with the
PC-based Xilinx XC-DS112 Configuration PROM Programmer or with programmers from other manufacturers.
The LCA design file is first compiled into a standard HEX
format with the XC-DS501 Development System. It can
then be transferred to the programmer through a serial port
on the PC.
2-175

1106050

Figure 1. XC1736A1XC1765 Block Diagram

DATAU8

ClK
RESET/OE
CE

2
3
4

7
6
5

VCC
vpp
CEO
GND
110604B

XC1736A/XC1765 S-Pln DIP Pin Assignments

r vee

14
9 10111213

GND

XC1736A/XC1765 20-Pin PlCC Pin Assignments

110617

XC1736A/XC1765 Serial Configuration PROM
Table 1. XC1736A1XC1765 Pin Assignments for S-Pln DIP

PlCCDIP
Pin

Pin

Name I/O

Description

DOUT
CClK

M2

DATA 0 Three-state DATA output for
reading. InpuUOutput pin for programming.

2

4

6

2

3

ClK

Clock input. Used to increment
the internal address and bit
counters for reading and programming.

ADDITIONAL
} SLAVE MODE
lCAs (OPTIONAL)

HDC
LDC
GENERAL·
PURPOSE
USER 1/0
PNS

j

ALl

OTHER
PINS

RESET/I Output Enable input. A Low level
on both the CE and RESET/OE
inputs enables the data output
driver. A High level on RESETI
OE resets both the address and
bit counters. In the XC1765, the
logic polarity of this input is programmable as either RESET/OE
or OE/RESET. This document
describes the pin as RESET/OE
although the opposite polarity is
also possible on the XC1765.

RESET

LCA

DIN
CCLK

DATA

1---->1 ClK
CE

8

4

CE

10

5

GND

14

6

CEO

Chip Enable input. Used for device selection. A Low level on
both CE and OE enables the data
output driver. A High level on CE
disables both the address and bit
counters and forces the device
into a low power mode.
Ground pin.

0 Chip Enable Out output. This
signal is asserted Low on the
clock cycle following the last bit
read from the memory. It will stay
Low as long as CE and OE are
both Low. It will then follow CE
until OE goes High. Thereafter
CEO will stay High until the entire
PROM is read again and senses
the status of RESET polarity.

17

20

7

8

Vpp

Vcc

Programming Voltage Supply.
Used to enter programming
mode (+6 V) and to program the
memory (+15 V) Must be connected directly to Vcc for normal
Read operation. No overshoot
above + 15.5 V permitted.
+5 V power supply input.

DIP 1--......-'-Y"ES"------------,

II

INCREMENT ADDRESS
COUNTER, RESETiOE
HELD lOW FOR ONE
CLOCK CYCLE

DEVICE PASSED

Figure 6. Programming Sequence (XC1765)

2-183

1t06 098

XC1736AIXC1765 Serial Configuration PROM
Stag Microsystems LTD
UK 707 332-148
US (408) 998-1118
Model System 3000
XC1736A
XC1765

SERIAL PROM-PROGRAMMER SUPPORT
Xilinx offers PROM-programmer support for the XC1736A
and XC1765 through the OS112 programmer. The latest
release of XPP is revision 3.10 which supports the
XC1736A and XC1765. The Am1736 is supported by
an update to that release: PIN 1060265 for 5-1/4" disk or
PIN 1060266 for 3-1/2" disk. Contact Customer Service
for details on availability.

Bytek Corporation
(408) 437-2414
Model 135H-U
XC1736A
XC1765
Am1736

00 not program the XC1736A with the OS81 programmer
or the XC1736 non "A" algorithm, as this stresses the
device causing potential reliability problems. Use the
OS112 with the XC1736A algorithm only!
There have been numerous Inquiries regarding other
vendor support for the serial PROM family (XC 1736A and
XC1765). Below is the latest list of PROM-programmer
manufacturers that offer support for the XC1736A,
XC1765, and the Am1736.
Data I/O
(206) 881-6444
Model 29B Unipak 2B V21
V22
Model Unisite V3.0
V3.1
Model 2900 V1.1
V1.1
V1.1

XC1736A
XC1765
XC1736A
XC1765
XC1736A
XC1765
Am1736

System General
(408) 263-6667
Model SGUP-85A V1.7
V1.7

XC1736A
XC1765

BP Microsystems
(713) 461-9606
Model EP1140 Head 40A
V1.40 XC1736A
V1.40 XC1765
V1.40 Am1736
Link Computer Graphics
(201) 994-6669
Model ClK 3100 V3.1 or greater
XC1736A
XC1765

Advin Systems
(408) 984-8600
Model SAILOR-PAUSA
SAILOR-PAUSB
PILOT 142 143 144 145
Supports XC1736A Am1736 XC1765

Xeltek
(408) 727-6995
Model Unipro
V2.13 XC1736A
V2.13 XC1765

Logical Devices
(305) 974-0967
Model AllPRO
XC1736A
XC1765 V1.51
XC1736 V1.5

Pistohl Electronic Tool Company
(408) 255-2422
Model PET 110 PET 120 PET 130
XC1736A
XC1765
Am1736

Oliver Advanced Engineering
(818) 240-0080
Model OMNI 40 and ONMI 64
XC1736A Re12.51Q
XC1765 Re12.51Q
Am1736 Rei 2.51 Q

2-184

PHYSICAL DIMENSIONS

5

8

4

rr

O.313 ± 0.0111

•

0.009

\.--- 0.325 ± 0.025~
0.018
DIMENSIONS IN INCHES

Xt066

B-Pin Plastic DIP (PDB)

0.520 ± 0.010
0.470 ± 0.010
5

I

1II.::.=e:=;==C====:;='E;;=~J

0.010

4

0.018 -t--'II~
0.110

0.010 ± 0.002

---+--+1

0.054
0.100 - - - + I
0.032 - - - - - - - + 1

DIMENSIONS IN INCHES
X1OG7

B-Pln Ceramic Sidebrazed DIP (COB)

2-185

XC1736A/XC1765 Serial Configuration PROM
PHYSICAL DIMENSIONS (Continued)
PIN 111 ID LOCATION
(EITHER POS.)

O.OSOTYP

~ NON-CUMULATIVE

0.015 CHAMFER TYP

± 0.002 LEAD
COPLANARITY

brouujf.''''J
0.005

I

I

0.015

~0.320~

1106 15A

20·Pin PLCC (PC20)

5l

8
0.025 R

0.285
PIN II 1
INDEX MARK

'--fT-'--'--'--'--'--M

J'

~0.005MIN
0.025
MIN

---i

,~Jl

0.056 ± 0.005

-.I

I.-

---p
0.125 MIN

~

X1187

-.l1.--0.018±0.002

8-Pin CerOIP (008)
ORDERING INFORMATION AND VALID ORDERING COMBINATIONS
XC17XX • PC20C
DEVICE NUMBER
XC1736A
XC1765

----.-J

PACKAGE TYPE
PC8 = 8-PIN PLASTIC DIP
DD8 = 8-PIN CERDIP
CD8 = 8-PIN CERAMIC SIDE-BRAZED DIP
PC20 =20-PIN PLASTIC LEADED CHIP CARRIER

L

OPERATING RANGE/PROCESSING
C = COMMERCIAUINDUSTRIAL (-40° TO +85OC)
M =MILITARY (-55° TO +125°)
R = MILITARY (-55° TO+125°C) WITH
MIL-STD-883 LEVEL B EOUWALENT PROCESSING

XC 1736A-PD8C
XC 1736A-PC20C
XC1736A-CD8M

2-186

X1188

XC1765-PD8C
XC1765-PC20C
XC1765-CD8M
XC1765-DD8M
XC1765-DD8R

Sockets

Below are two lists of manufactures known to offer sockets
for Xilinx package types. This list does not imply an
endorsement by Xilinx. Each user must evaluate the
particular socket type.

a compatible PGA socket with wire-wrap pins. Note that
the board-layout then differs from a PGA board layout.

There are no wire-wrap sockets for PLCCs. One solution
is to piggy-back a through-hole PLCC socket mounted in

Zero Insertion Force (ZIF) sockets, recommended for
prototyping with 132 and 175 pin PGA devices, also lack
the wire-wrap option. Piggy-back the ZIF socket in a
normal PGA wire-wrap socket.

PLCC Sockets

PGA Sockets

AMP Inc.
Harrisburg, PA 17105
(717) 564-0100
Burndy Corp.
Richards Ave.
Norwalk, CT 06856
(203) 852-8437
Garry Electronics
9 Queen Anne Court
Langhorne, PA 19047-1803
(215) 949-2300
Honda - MHOtronics
Deerfield. IL 60015
444 Lake Cook Road,
(312) 948-5600

Su~e

ITICannon
10550 Talbert Ave.
P.O.Box 8040
Fountain Valley, CA 92728
(714) 964-7400
Kycon Cable & Connector
1772 Little Orchard Street
San Jose, CA 95125
(408) 295-1110
Maxconn Inc.
1855 O'Toole Ave., 0102
San Jose, CA 95131
(408) 435-8666
Methode Electronics Inc.
1700 Hicks Road
Rolling Meadows, IL 47150
(312) 392-3500

Mill-Max Mfg. Corp.
190 Pine Hollow Road
Oyster Bay, N.Y. 11771-0300
(516) 922-6000

Advanced Interconnections
5 Energy Way
West Warwick, RI 02893
(401) 823-5200

McKenzie Technology
44370 Old Warm Springs Blvd.
Fremont CA 94538
(415) 651-2700

Precicontact Inc.
835 Wheeler Way
Langhorne, PA 19047
(215) 757-1202

AMP Inc.
Harrisburg, PA 17105
(717) 564-0100

Methode Electronics Inc.
1700 Hicks Road
Rolling Meadows, IL 47150
(312) 392-3500

Robinson Nugent
800 East Eighth Street
New Albany, IN 47150
(812) 945-0211

8

Samtec Inc.
P.O.Box 1147
New Albany, IN 47150
(812) 944-6733
3M Textool
Austin, TX
(800) 328-7732
Thomas & Betts Corp.
920 Route 202
Raritan, NJ 08869
(201) 469-4000
Wells Electronics, Inc.
1701 South Main Street
South Bend, IN 46613
(219) 287-5941
Yamaichi Electronics, Inc.
1420 Koll Circle
Suite B
San Jose, CA 95112
(408) 452-0799

Aries Electronics, Inc.
P.O.Box 130
Frenchtown, NJ 08825
(201) 996-6841

Mill-Max Mfg. Corp.
190 Pine Hollow Road
Oyster Bay, N.Y. 11771-0300
(516) 922-6000

Augat
33 Perry Ave.
P.O.Box 779
Attleboro, MA 02703
(617) 222-2202

Precicontact Inc.
835 Wheeler Way
Langhorne, PA 19047
(215) 757-1202

Bevmar Industries, Inc.
20601 Annalee Ave.
Carson, CA 90746
(213) 631-5152

Robinson Nugent
800 East Eighth Street
New Albany, IN 47150
(812) 945-0211

Bevmar Industries, Inc.
1 John Clarke Rd.
Middletown, RI 02840
(401) 849-4803

Samtec Inc.
P.O. Box 1147
New Albany, IN 47150
(812) 944-6733

Electronic Molding Corp.
96 Mill Street
Woonsocket, RI 02895
(401) 769-3800

Texas Instruments
CSD Marketing, MS 14-1
Attleboro, MA 02703
(617) 699-5206

Garry Electronics
9 Queen Anne Court
Langhorne, PA 19047-1803
(215) 949-2300

Thomas & Betts Corp.
920 Route 202
Raritan, NJ 08869
(201) 469-4000

Mark Eyelet Inc.
63 Wake lee Road
Wolcott, CT 06716
(203) 756-8847

Yamaichi Electronics, Inc.
1420 Koll Circle
Suite B San Jose, CA 95112
(408) 452-0799

2-187

•

XC1736A/XC1765 Serial Configuration PROM

2-188

SECTION 3
Quality, Testing, Packaging

1

Programmable Gate Arrays

2

Product Specifications

3

Quality, Testing, Packaging

4

Technical Support

5

Development Systems

6

Applications

7

Article Reprints

8

Index

Quality, Testing, and
Packaging

Quality Assurance and Reliability ........................................................ 3-1
Quality Assurance Program ........................................................... 3-1
Reliability Introduction .................................................................... 3-1
Outline of Testing ........................................................................... 3-1
Die Qualification ....................................................................... 3-2
Package Integrity and Assembly Qualification ......................... 3-2
Hermetic Package Integrity and Assembly Qualification .......... 3-3
Description of Tests ....................................................................... 3-4
Die Qualification ....................................................................... 3-4
Package Integrity and Assembly Qualification ......................... 3-4
Testing Facilities ............................................................................ 3-4
Summary ....................................................................................... 3-4
Data Integrity ................................................................................. 3-8
Memory Cell Design ................................................................. 3-8
Alpha Particle Sensitivity .......................................................... 3-9
Analysis .................................................................................... 3-9
Electrostatic Discharge .................................................................. 3-9
Latch up ......................................................................................... 3-10
High-Temperature Performance .................................................... 3-10
Radiation Hardness Gamma Total Dose Test ............................... 3-11
Test Methodology ................................................................................ 3-12
Testing ........................................................................................... 3-12
Testing of the Logic Cell Array ....................................................... 3-13
Testing the Speed of the Logic Cell Array ..................................... 3-15
Hardware Testing Considerations ................................................. 3-15
Packaging ........................................................................................... 3-18
Package and User 110 Availability ................................................. 3-18
Package/Speed/Temperature Selections ...................................... 3-18
Package Thermal Characterization ............................................... 3-19
Packaging Characteristics ............................................................. 3-21
Sockets .......................................................................................... 3-22

Quality Assurance
and Reliability

QUALITY ASSURANCE PROGRAM

customers' systems applications. An extensive, on-going
reliability-testing program is used to predict the field performance of our devices.

All aspects of the Quality Assurance Program at Xilinx
have been designed in compliance with the requirements
of Appendix A of M IL-M-3851 O. This program emphasizes
heavily the aspects of operator training and certification,
the use of "accept only on zero defects" lot sampling plans,
and extensive audits of both internal departments and
outside suppliers.

These tests provide an accelerated means of emulating
long-term system operation in severe field environments.
From the performance of the devices during these tests,
predictions of actual field performance under a variety of
conditions can be calculated.

Xilinx utilizes the world-class wafer fabrication facilities of
Seiko-Epson's plant in Fujimi, Suwa, Japan and the highvolume assembly resources of AN AM in Seoul, the
Republic of Korea. Periodic quality assurance audits of
these facilities to the full requirements of MIL-STD-883 are
routinely performed.

This report describes the nature and purpose of the
various reliability tests performed on finished devices.
Updated summaries are available upon request from the
Quality Assurance and Reliability Department at Xilinx.

OUTLINE OF TESTING

Xilinx calculates its outgoing component quality level,
expressed in PPM (defective parts per million devices
shipped), using the industry-standard methods now
adopted by JEDEC and published in JEDEC Standard 16.
These figures of merit are revised and published quarterly
by Xilinx Quality Assurance and are available from local
manufacturer's representatives or from Xilinx. These
summary data are available for downloading from the
Xilinx Electronic Bulletin Board at (408) 559-9327 [1200/
2400 baud; 8 data bits; no parity; 1 stop bit) supporting all
of the following communications protocols: ASCII, Kermit,
XModem, -CRC, and Telink.

Qualification testing of devices is performed to demonstrate the reliability of the die used in the device, and the
materials and methods used in the assembly of the device.
Testing methods are derived from and patterned after the
methods specified in MIL-STO-883.
Referral to the test methods of MIL-STO-883 is not intended to imply that non hermetic products comply with the
requirements of MIL-STO-883. These test methods are
recognized industry-wide as stringent tests of reliability
and are commonly used for nonmilitary-grade semiconductordevices, as well as forfullycompliant military-grade
products.

RELIABILITY INTRODUCTION
Hermetic packages are qualified using the test methods
specified in MIL-STO-883. The Group 0 package qualification tests are performed on one lot of each package type
from each assembly facility every twelve months.

From its inception, Xilinx has been committed to delivering the highest quality, most reliable programmable gate
arrays available. A strong Quality Assurance and Reliability program begins at the initial design stages and is carried
through to final shipment. The final proof of our success is
in the performance of the Logic Cell™ Array (LCA) in our

A summary of the reliability demonstration tests used at
Xilinx is contained in Table 1.

3-1

•

Quality Assurance and Reliability

DIE QUALIFICA TlON
Name of Test

Test Conditions

Lot Tolerance Percent Defective
Minimum Sample Size!
Maximum Acceptable Failures

1. High Temperature Life

1000 hr min equivalent at temperature = 125°C
Actual test temperature = 145°C
Max. rated operating voltage.
Life test circuit equivalent to MIL-STO-883

2. Biased Moisture Life

LTPO = 5, s = 105, c = 2
1000 hr min exposure
T = 85°C, RH = 85%
Max. rated operating voltage.
Biased moisture life circuit equivalent to MIL-STO-883

LTPO = 5, s = 105, c = 2

NON-HERMETIC PACKAGE INTEGRITY and ASSEMBL Y QUALIFICA TlON
Name of Test

Lot Tolerance Percent Defective
Minimum Sample Size!
Maximum Acceptable Failures

Test Conditions

3. Unbiased Pressure Pot

96 hr min. exposure
T = 121°C, P = 2 atm H20 sat.

LTPO = 5, s = 105, c = 2

4. Thermal Shock

MIL-STO-883, Method 1011, Condo C
-65°C to +150°C
100 cycles

LTPO = 5, s = 75, c = 2

5. Temperature Cycling

MIL-STO-883, Method 1010, Condo C
-65°C to + 150°C
200 cycles

LTPO = 5, s = 105, c = 2

6. Salt Atmosphere

MIL-STO-883, Method 1009, Condo A
24 hrs

s=25, c=O

7. Resistance to Solvents

MIL-STO-883, Method 2015

5=4,

c=O

8. Solderability

MIL-STD-883, Method 2003

5 = 3,

c=O

9. Lead Fatigue

MIL-STD-883, Method 2004

5 = 2,

c=O

Table 1A. Reliability Testing Sequence for Non-Hermetic Logic Cell Arrays

3-2

HERMETIC PACKAGE INTEGRITY and ASSEMBL Y QUALIFICATION

Name of Test

1. Subgroup 01 : Physical
Dimensions
2.

3.

4.

5.

6.

7.

8.

Subgroup 02
a. Lead Integrity
b. Seal (fine and gross leak)

Subgroup 03
a. Thermal Shock-15 cycles
b. Temp. cycling-1 00 cycles
C. Moisture Resistance
d. Seal (fine & gross leak)
e. Visual Examination
f. End-point electricals

Test Conditions

Lot Tolerance Percent Defective
Minimum Sample Size!
Maximum Acceptable Failures

MIL-STO-883, Method 2016

LTPO

= 15, s = 34, c = 2

LTPO

= 15, s = 34, c = 2

LTPO

= 15, s = 34, c = 2

LTPO

= 15, s = 34, c = 2

LTPO

= 15, s = 34, c = 2

MIL-STO-883, Method 2028
MIL-STO-883, Method 1014
(not required for PGA's)

MIL-STO-883, Method
MIL-STO-883, Method
MIL-STO-883, Method
MIL-STO-883, Method
MIL-STO-883, Method
Group A, subgroup 1

1011, Condo B
1010, Condo C
1004
1014
1004 and Method 1010.

Subgroup 04
a. Mechanical Shock
b. Vibration, Variable Freq.
C. Constant Acceleration
min, Y,only
(Cond. 0 for large PGAs)
d. Seal (fine & gross leak)
e. Visual Examination
I. End-point electricals

MIL-STO-883, Method 1014
MIL-STO-883, Method 1010
Group A, subgroup 1

Subgroup 05
a. Salt Atmosphere
b. Seal (fine & gross leak)
C. Visual Examination

MIL-STO-883, Method 1009, Condo A
MIL-STO-883, Method 1014
MIL-STO-883, Method 1009

MIL-STO-883, Method 2002, Condo B
MIL-STO-883, Method 2007, Cond. A
MIL-STO-883, Method 2001, Condo E

Subgroup 06:
Internal Water Vapor Content MIL-STO-883, Method 1018,5000 ppm
water at 100°C

s = 5; c = 1

Subgroup 07:
Lead Finish Adhesion

LTPO = 15, s = 34 leads,
(3 device min) c = 0

Subgroup 08:
Lid Torque

MIL-STO-883, Method 2025

MIL-STO-883, Method 2024
(for ceramic quad flat pack, CQFP only)

s = 3; c = 0 or

LTPO

= 5, S = 5, c = 0

Table 1 B_ Reliability Testing Sequence for Hermetic Logic Cell Arrays

3-3

Quality Assurance and Reliability

damage from alternate exposure to extremes of temperature or to intermittent operation at very low temperatures. The range of temperatures is -65°C to
+150°C. The transition time is longer than that in the
Thermal Shock test but the test is conducted for many
more cycles.

DESCRIPTION OF TESTS
Die Qualification
1.

High Temperature Life This test is performed to
evaluate the long-term reliability and life characteristics of the die. It is defined by the Military Standard
from which it is derived as a "Die-Related Test" and is
contained in the Group C Quality Conformance Tests.
Because of the acceleration factor induced by higher
temperatures, data representing a large number of
equivalent hours at a normal temperature of 70°C can
be accumulated in a reasonable period of time. Xilinx
performs its High Temperature Life test at a higher
temperature, 145°C, than the more common industry
practice of 125°C. For comparison, the Reliability
Testing Data Summary in Table 2 gives the equivalent
testing hours at 125°C.

6. Salt Atmosphere This test was originally designed
by the US Navy to evaluate resistance of militarygrade ship-board electronics to corrosion from sea
water. It is used more generally for non-hermetic
industrial and commercial products as a test of corrosion resistance of the package marking and finish.

7. Resistance to Solvents This test is performed to
evaluate the integrity of the package marking during
exposure to a variety of solvents. This is an especially
important test, as an increasing number of board-level
assemblies are subjected to severe conditions of
automated cleaning before system assembly operations occur. This test is performed according to the
methods specified by MIL-STD-883.

2. Biased Moisture Life

This test is performed to
evaluate the reliability of the die under conditions of
long-term exposure to severe, high-moisture
environments which could cause corrosion. Although
it clearly stresses the package as well, this test is
typically grouped under the die-related tests. The
device is operated at maximum-rated voltage, 5.5 Vd '
and is exposed to a temperature of 85°C and a relativCe
humidity of 85% throughout the test.

8. Solderability This test is performed to evaluate the
solderability of the leads under conditions of low
soldering temperature following exposure to the aging
effects of water vapor.

9. Lead Fatigue This test is performed to evaluate the

Package Integrity and Assembly Qualification

resistance of the completed assembly to vibrations
during storage, shipping, and operation.

3. Unbiased Pressure Pot This test is performed at a
temperature of 121°C and a pressure of 2 atm of
saturated steam to evaluate the ability of the plastiC
encapsulating material to resist water vapor. Moisture
penetrating the package could induce corrosion of the
bonding wires and nonglassivated metal areas of the
die [bonding pads only for LCA devices]. Under
extreme conditions, moisture could cause drive-in and
corrosion underthe glassivation. Although it is difficult
to correlate this test to actual field conditions, it provides a well-established method for relative comparison of plastiC packaging materials and assembly and
molding techniques.

TESTING FACILITIES
Xilinx has the complete capability to perform High Temperature Life Tests, Thermal Shock, Biased Moisture Life
Tests, and Unbiased Pressure Pot Tests in its own Reliability Testing Laboratory. Other tests are being performed
by outside testing laboratories with DESC laboratory suitability for each of the test methods they perform.
SUMMARY
Tables 2 and 3 testing data show the actual performance
of the Logic Cell Arrays during the initial qualification tests
to which they have been subjected. These test results
demonstrate the reliability and expected long life inherent
in the non-hermetic product line. This series of tests is
ongoing as a part of the Quality Conformance Program on
non-hermetic devices.

4. Thermal Shock This test is performed to evaluate
the resistance of the package to cracking and resistance of the bonding wires and lead frame to separation or damage. It involves nearly instantaneous
change in temperature from -65°C to +150°C.

5. Temperature Cycling

This test is performed to
evaluate the long-term resistance of the package to

3-4

Table 2. Xilinx Reliability Testing Summary
Device Types: XC2018, XC2064, XC3020, XC3030, XC3042 Processrrechnology: 1.2 Micron Double-Layer Metal CMOS
Die Attach Method: Silver Epoxy
Package Type: 68- & 84-Pin PLCC
Molding Compound: Sumitomo 6300H
Date: lQ 1990

Test

Combined
Sample

Failures

Equivalent
Mean
Hrs/Device
at TA = 125°C

High Temperature Life Test
145°C

Equivalent
Device Hrs
6,190,193

6,418

15

820

10

at TA = 85°C
696

atTA= 85°C
570,745

420

4

372

156,496

3

Mean Cycles Total Device
per Device
Cycles
514,025
328

1,026

2

Mean Cycles Total Device
Cycles
per Device
197,300
192

Salt Atmosphere Test
MIL-STD-883, Method 1009,
Cond.A

55

0

24

Resistance to Solvents Test
MIL-STD-883, Method 2105

12

0

Solderability Test
MIL-STD-883, Method 2003

12

0

Lead Fatigue Test
MIL-STD-883, Method 2004

2

0

Biased Moisture Life Test
T = 85°C; RH = 85%
Unbiased Pressure Pot Test
+121°C, 2 atm sat. steam
Thermal Shock Test

-65°C/+ 150°C
100 cycles (min)

Temperature Cycling Test
-65°C/+ 150°C
100 cycles (min)

1,566

964

Total
Device Hrs
at TA = 125°C

1,320

" Assumed activated energy 0.90 eV

3-5

Equivalent
Failure Rate
in FIT
at TJ = 70°C

36"

Quality Assurance and Reliability
Table 3. Xlllnx Reliability Testing Summary
Device Types: XC3090
Die Attach Method:
Molding Compound:

ProcesslTechnology: 1.2 Micron CMOS
Package Type: 175-Pin PPGA
Date: 2Q 1990

Combined
No. Lots

Failures

Devices
on Test

Equivalent
Mean
HrsfCycie
at TA = 125°C

High Temperature Life Test
145°C

1

0

45

260

11,700

Biased Moisture Life Test
T = 85°C; RH = 85%

1

0"

45

1,000

44,500

Unbiased Pressure Pot Test
+121°C, 2 atm sat. steam

1

0

45

96

4,320

Thermal Shock Test
-65°C/+ 150°C
100 cycles (min)

1

0

45

200

9,000

Temperature Cycling Test
-65°C/+ 150°C
100 cycles (min)

1

0

45

200

9,000

Salt Atmosphere Test
MIL-STD-883, Method 1009,
Condo A

1

0

8

24

192

Resistance to Solvents Test
MIL-STD-883, Method 2105

1

0

3

o (no rejects)

Solderability Test
MIL-STD-883, Method 2003

1

0

3

o (no rejects)

Test

'Assumed activation energy 0.90 eV
• 'Two non-85/85 anomalies were discounted

3-6

Total
Device Hrs
atTA= 125°C

Equivalent
Failure Rate
in FIT
at TJ = 70°C
0'

o (no rejects)

E:XllJt~X.
Table 4. Reliability Summary Package Qualification
Ceramic Pin Grid Array (PGA) and Ceramic Ouad Flat Pack (COFP)

PG84

Code

Test

Combined
Sample

Failures

Combined
Sample

PG132

COl 00

PG175

Failures

Combined
Sample

Failures

Combined
Sample

Failures

Dl Physical Dimension

45

0

15

0

40

0

15

0

D2 Lead Integrity
Seal

55

0

15

0

40

0

15

0

D3 Thermal Shock

75

0

25

0

59

0

25

0

Total
Mean Hrs/
Cycle/Device Device
Hours

Total
Mean Hrs/
Cycle/Device Device
Hours

Mean Hrs/
Cycle/Device

Total
Device
Hours

Total
Mean Hrs/
Cycle/Device Device
Hours

Thermal Shock
Temperature Cycle
Seal
Visual
End-Point Electrical
Parameters

15
100

1,125
7,500

15
100

375
2,500

15
100

885
5,900

15
100

375
2,500

D4 Mechanical Shock
Vibration, Var. Freqency
Constant Acceleration

75

0

25

0

69

1

25

0

55

0

25

0

40

0

15

0

9

0

5

0

10

0

5

0

13

0

3

0

6

0

3

0

10

0

Seal
Visual Examination
End-Point Electrical
Parameters
D5 Salt Atmosphere
Seal
Visual
D6 Internal Water-Vapor Content
D7 Adhesion of Lead Finish
D8 Lead Torque

3-7

II

Quality Assurance and Reliability

This explains the basic cell, but how is the LCA user
assured of high data integrity in a noisy environment?
Consider three different situations: normal operation, a
Write operation and a Read operation. In the normal
operation, the data in the basic memory element is not
changed. Since the two circularly linked inverters that hold
the data are physically adjacent, supply transients result in
only small relative differences in voltages. Each inverter is
truly a complementary pair of transistors. Therefore,
whether the output is High or Low, a low-impedance path
exists to the supply rail, resulting in extremely high noise
immunity. Power supply or ground transients of several
volts have no effect on stored data.

DATA INTEGRITY
Memory Cell Design
An important aspect ofthe LCA reliability is the robustness
of the static memory cells used to store the configuration
program.
The basic cell is a single-ended five-transistor memory
element (Figure 1). By eliminating a sixth transistor, which
would have been used as a pass transistor for the complementary bit line, a higher circuit density is achieved.
During normal operation, the outputs of these cells are
fixed, since they determine the user configuration. Write
and readback times, which have no relation to the device
performance during normal operation, will be slower without the extra transistor. In return, the user receives more
functionality per unit area.

The transistor driving the bit line has been carefully designed so that whenever the data to be written is opposite
the data stored, it can easily override the output of the
feedback inverter. The reliability of the Write operation is

v'"
CONFIGURATION DATA SHIFT REGISTER

0N_'----------IoS of-.-----io s
DR

DR

CK

CK

SEl

of-.---

READ

SEL

DATA CLOCK - - -----+---<--_t_-_+-+---<~-_t_-_+--

W~Ro-------+---~~_+-+---~~_+--

I
CLOCK I

o
CK

PRECHARGE - -

-------''-----_+---''-----_+--

WORoN - - ---------t--_+---~--_+--

CONFIGURATION

MEMORY CELL
CIRCUIT

ADDRESS

SHIFT REGISTER

o
WORD LINE
DRIVER

0

CK

WORDN + 1 - --------~---+---~---+--

BITM+ 1

Figure 1. Configuration Memory Cell

3-8

110901A

E:XIUNX
guaranteed within the tolerances of the manufacturing
process.

0.5 cm2, so less than 0.0015 alpha particles per hou r will be
captured by the XC2064in normal operation. The error rate
acceleration in this test is therefore equal to:

In the Read mode, the bit line, which has a significant
amount of parasitic capacitance, is precharged to a logic
one. The pass transistor is then enabled by driving the
word line High. If the stored value is a zero, the line is
then discharged to ground. Reliable reading of the
memory cell is achieved by reducing the word line High
level during reading to a level that insures that the cell will
not be disturbed.

5.3 x 107 particles/hour
0.0015 particles/hour

=

3.6 X 10'0

The 0.61 hours of error-free test time thus is equivalent to
2.2xl 0'0 hours or 2.5 million years of error-free operation.
Most ceramic packages are specified to emit less than 0.01
alpha particles/cm2/hrwhich is about three times morethan
the plastic compound. For an XC2064 in a ceramic package, this still results in error-free operation for almost a
million years.
The highest rate of alpha-particle emission comes from the
sealing glass used in cerdip packages and some ceramic
packages (frit lids). For instance, KCIM glass emits about
24 alpha particles/cm2/hr. Low-alphaglasses are specified
at 0.8 alpha particles/crn2/hr.

Alpha Particle (Soft Error) Sensitivity
The CMOS static memory cell was designed to be insensitive to alpha particle emissions. To verify that this design
goal was achieved, the following tests were performed.
A one-microcurie alpha-particle source (Americum 241)
was placed in direct contact with the top surface of an
XC2064 die. This allows the die to capture at least 40% of
the emissions from the radiation source. The following
sequence of tests was performed:

Because these glasses are used onlyforthe package seal,
they present a relatively small emitting cross section to the
die (less than 0.1 cm 2 ). A low-alpha glass would therefore
cause fewer than 0.8 alpha particle hits per hour. The
acceleration factor is then 6.6 x 108 , which translates to
about 46,000 years without an error.

1. A complex pattern containing roughly 50% logic ones
was loaded into the XC2064. The operating conditions
were 25°C and 5.0 V.
2. A pause of variable duration was permitted.

The LCA memory cell has been designed sothat soft errors
caused by alpha particles can safely be ignored.

3. The entire contents of the XC2064 were read back and
compared with the original data.

ELECTROSTATIC DISCHARGE

Validation tests to ensure that the test setup would detect
errors were performed before and after the alpha-particle
tests. The results are as follows:
Test

Time
Duration

Readback
Time

Total Time
Exposed

Number
of Errors

1
2
3
4

105
1205
3005
15005

705
705
705
70s

805
1905
3705
1570s

0
0
0
0

Total

Electrostatic-discharge (ESD) protection for each pad is
provided by a circuit that uses forward and reverse-biased
distributed resistor-diodes (Figure 2). In addition, inherent
capacitance integrates any cu rrent spikes. This give sufficient time for the diode and breakdown protections to
provide a low-impedance path to the power-supply rail.
Geometries and doping levels are optimized to provide
sufficient ESD protection for both positive and negative
discharge pulses.

2210 s (0.61 hours)
Vee

Analysis
A one-microcurie source emits 3. 7xl 04 alpha particles per
second. Assuming that 40% of these are captured by the
XC2064 during this experiment, this corresponds to
5.3xl0 7 alpha particles per hour.

PAD

The alpha-particle emission rate of the molding compound
used by Xilinx is specified to emit fewer than 0.003 alpha
particles per square centimeter per hour (alpha particles/
cm2/hr). The surface area of the XC-2064 die is less than

I
-=-

TO INTERNAL
CIRCUITRY

GND

Figure 2. Input Protection Circuitry

3-9

1109 02A

II

Quality Assurance and Reliability

LATCHUP

HIGH TEMPERATURE PERFORMANCE

Latchup is a condition in which parasitic bipolar transistors
form a positive feedback loop (Figure 3), which quickly
reaches current levels that permanently damage the device. Xilinx uses techniques based on doping levels and
circuit placement to avoid this phenomenon. The cross
section of a typical transistor (Figure 4) shows several
features. The beta of each parasitic transistor is minimized
by increasing the base width. This is achieved with large
physical spacings. The butting contacts effectively short
the n+ and p+ regions for both wells, which makes the VBE
of each parasitic very close to zero. This also makes the
parasitic transistors very hard to forward bias. Finally, each
well is surrounded by a dummy collector, which forces the
VCE of each parasitic almost to zero and creates a structure
in which the base width of each parasitic is large, thus
making latchup extremely difficult to induce.

Although Xilinx guarantees parts to perform only within the
specifications of the data sheet, extensive high temperature life testing has been been done at 145°C with excellent
results. In plastic packages, the maximum junction temperature is 125°C.
Vee

PAD

At elevated temperatures, 100 mA will not cause latchup.
At room temperature, the device can withstand more than
300 mA without latchup. However, continuous currents
in excess of 10 mA are not recommended.

1109038

Figure 3. SCR Model

PAD

NSUBSTRATE

DUMMY

COLLECTORS
110904

Figure 4. CMOS Input Circuit Layout

3-10

RADIATION HARDNESS-GAMMA TOTAL DOSE TEST
Outline of Testing

Testing closely followed the procedures of MIL-STD883C, Method 1019, but was not strictly in full compliance
with the requirements since the irradiation and final test
sites were in different locations. The devices were transported by air (with bias continually applied) from the
location in southern California, where they had been
exposed to the radiation, to the Xilinx test facility in San
Jose. Up to two hours elapsed, from the time of exposure
to final testing, due to air transportation.

Xilinx has conducted a series of radiation hardness tests
to demonstrate the capability of the 1.2-micron CMOS
process being used to produce both the XC2000 and
XC3000 family of devices. The test vehicle used was the
XC3020-70PC84C. Other devices in other packages are
expected to show similar results.
Four random devices taken from normal production lots
were individually subjected to gamma radiation levels
under 5V Vcc bias in power-down mode. The four radiation levels were 20, 30, 50 and 75 krads (Si). Each device
was exposed to a different radiation level. The radiation
was applied at the rate of 10 rads (Si) per second. After
exposure each device was functionally tested in a system
at the irradiation site. A device failure is defined as inability
to load configuration data and begin functional operation.
The devices were also tested at Xilinx after irradiation.
Standard dc functionality and ac parametric tests were
pertormed on the Xilinx production tester. Both the system
and the device tests showed device failure at the 75 krad
(Si) level. Test results are summarized in Table 1.

In summary, four devices were tested following exposure
to a Cobalt-60 gamma-radiation source. The data obtained from these tests indicate that devices are capable
of normal operation up to the 50 krad (Si) total dose level.
The test results suggest that Xilinx XC2000 and XC3000
devices manufactured on the 1.2-micron CMOS process
are acceptable in any application requiring a radiation
design level of 50 krad (Si) or less.
Xilinx personnel did not verify the total radiation dosage
applied the calibration of the Cobalt-60 source, or the
application of bias during irradiation. Because of these
factors, coupled with the two-hour test-time lag and the
small sample size, these tests are not fully conclusive.

Table 1
Device
Number

Gamma
Exposure
Level

System
Functional
Test

20 krad (Si)

Passed

Passed

2

30 krad (Si)

Passed

Passed

3

50 krad (Si)

Passed

Passed

4

75 krad (Si)

Failed'

Failed'

Tester
Results

, Would not reconfigure
Total Dose Level: 50 krad (Si)

3-11

II

Test Methodology

time-consuming and expensive iterations in order to reach
even 80% fauH coverage. The cost of greater coverage is
often prohibitive. In production, many gate array vendors
either limit the number of vectors allowed or charge for
using additional vectors.

Xilinx is committed to providing the highest level of quality
and reliability forthe Logic Cell (LCA) Array . Quality is best
assured by taking the necessary steps to achieve zero
defects. Comprehensive testing confirms that every LCA
device is free from defects and conforms to the data sheet
specifications. The memory-cell design assures integrity
of the configuration program.

The replacement of all storage elements with testable
storage elements, known as scan cells, improves testability. AHhough this technique can reduce the production
testing costs, it can add about 30% more circuitry, decrease performance by up to 20%, and increase design
time.

TESTING
As quality consciousness has grown among semiconductor users, awareness of the importance of testability
has also increased. Testing for standard components,
including memories and microprocessors, is accomplished with carefully developed programs which exhaustively test the function and performance of each part. For
reasons explained below, most application specific ICs
cannot be comprehensively tested. Without complete
testing, defective devices might escape detection and be
installed into a system. In the best case, the failure will be
detected during system testing at a higher cost. In the
worst case, the failure will be detected only after shipment
of the system to a customer.

Logic Cell Arrays: The testability of the LCA device is
similartoother standard products, including micro-processors and memories. This is the resuH of the design and the
test strategies:
Design strategy:
• Incorporates testability features because each functional node can be configured and routed to outside
pads
• Permits repeated exercise of the part without removing
it from the tester because of the short time to load a new
configuration program
• Produces a standard product which guarantees that
every valid configuration will work.

Testing advantages of the Logic Cell Array can be illustrated through comparison with two other application
specific ICs: Erasable Programmable Logic Devices
(EPLDs) and gate arrays.

Test strategy:
EPLDs: In order to test all memory cells and logic paths of
programmable logic devices controlled by EPROM memory cells, the part must be programmed with many different
patterns. This in turn requires expensive quartz lid packages and many lengthy programltestlerase cycles. To
save time and reduce costs, this process is typically
abbreviated.

• Performs Reads and Writes of all bits in the configuration memory, as in memory testing
• Uses an efficient parallel testing scheme in which
multiple configurable logic blocks are fully tested
simultaneously
• Is exhaustive since the circuits in every block are
identical

Gate Arrays: Since each part is programmed with metal
masks, the part can only be tested with a program tailored
to the specific design. This in turn requires that the
designer provide sufficient controllability and observability
for comprehensive testability. The design schedule must
also include time for the development of test vectors and
a test program specification. If the gate array user requires
a comprehensive test program, then he must perform
exhaustive and extensive fault simulation and test grading. This requires substantial amounts of expensive
computertime. Additionally, it typically requires a series of

The Logic Cell Array user can better appreciate the LCA
test procedure by examining each of the testing
requirements:
• All configuration-memory bits must be exercised and
then verified. This is performed using read back mode.
• All possible process-related lauHs, such as short circuits, must be detected. The Logic Cell Array is configured such that every metal line can be driven and
observed directly from the input/output pads.
3-12

Memory Cell Testing

• Alltesting configurations must provide good controllability and observability. This is possible since all configurable logic blocks can be connected to inpuUoutput pads.
This makes them easy to control by testing different
combinations of inputs and easy to observe by comparing the actual outputs with expected values.

The static memory cells have been designed specifically
for high reliability and noise immunity. The basic memory
cell consists of two CMOS inverters and a pass transistor
used for both writing and reading the memory cell data
(See Figure 1). The cell is only written during configuration. Writing is accomplished by raising the gate of the
pass transistorto Vcc and forcing the two CMOS inverters
to conform to the data on the word line. During normal
operation, the memory-cell provides continuous control of
the logic, and the pass transistor is "off" and does not affect
memory-cell stability. The output capacitive load and the
CMOS levels of the inverters provide high stability. The
memory cells are not affected by extreme power-supply
excursions.

These points bring out an important issue: the Logic Cell
Array was carefully designed to achieve 100% fault coverage. With the Xilinx testing strategy, the number of design
configurations needed to fully test the Logic Cell Array is
minimized and the test fault coverage of the test patterns
is maximized. In addition, the user's deSign time is
reduced because the designer does not have to be concerned about testability requirements during the design
cycle. The LCA concept not only removes the burden of
the test-program and test-vector generation from the user,
but also removes the question of fault coverage and
eliminates the need for fault grading. The Logic Cell Array
is a standard part that guarantees any valid design will
work. These issues are critically important in qualitysensitive applications. The designer who uses the Logic
Cell Array can build significant added value into his design
by providing higher quality levels.

ty:

. . ',' . . . . . . . . . . . . . .,. .,. . . . . . . . . . . . . . . . . . . . . . . . .

~!--'"

a

r'
:;

::........ ,"

TESTING OF THE LOGIC CELL ARRAY

CONFIGURATION

CONTROl

....::

111101

Figure 1. Configuration Memory Cell

The LCA device is tested as a standard product. Every
device is tested for: 1) 100% functionality; 2) dc parametrics; and 3) speed. This allows the end-user to design and
use the logic cell array without worrying abouttesting for a
particular application.

The memory cells are directly tested in the Logic Cell Array
with three test patterns that are equivalent to those used on
a RAM device. The first test pattern writes 95% of all the
RAM cells to a logic zero and then reads each RAM cell
back to verify its contents. The second test pattern writes
95% of all the RAM cells to a logiC one and also verifies the
contents. The third pattern is used to verify that all I/O and
configurable logic blocks can have their logic value read
back correctly. All RAM cells are thus written and verified
for both logic levels.

The strategy for testing the LCA device is to test the
functionality of every internal element. These elements
consist of memory cells, metal interconnects, transistor
switches, bidirectional buffers, inverters, decoders, and
multiplexers. If each element is functional, then the user's
design will also be functional if the proper design procedures are used.

Interconnect Testing

The static memory cells and the symmetry of the Logic Cell
Array make it 100% testable. The Logic Cell Array can be
programmed and reprogrammed with as many patterns as
required to fully test it. This is done with as many as 50
configurationltest patterns. Each configuration/te pattern
consist of: 1), A set of test vectors that configure the LCA
device with a hardware design that utilizes specific
elements; and 2), A set of test vectors that exercise those
specific elements. The symmetry of the LCA device allows
the test engineer to develop the test for one CLB or lOB
and then apply it to all others. All configuration/test
patterns are exercised at both Vcc minimum and
maximum.

The programmable interconnect is implemented using
transistor switches to route signals through a fixed two
layer grid of metal conductors. The transistor switches
"on" or "off" depending on the logic value of the static
memory cell that controls the switch. The interconnect is
tested with configurationltest patterns that: 1) Test for
continuity of each metal segment; 2) Test for shorts
between metal segments; and 3) Check the ability for each
switch to connect two metal lines. This can be
accomplished with a pattern similar to Figure 2. Each
interconnect line will be set to a logic one while the others
are set to logiC zero. This checks for shorts between
adjacent interconnects while althe same time checking for
continuity of the line.

3-13

II

Test Methodology
Print World: PATNll.LCA (2018PC84-70), XACT 2.0Sb Eng, Wed Mar 02 16:28:18 198€Print World: PATN11.LCA (2018PC84-7

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til
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1[1
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rID
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~ @~ ~m ~m rmrh]~sm rililm a®1

~--'Ir- ~

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E50 05

Figure 2. Interconnect Test Pattern

3-14

1-

~r&

rJ

0 []

I/O Block Testing

TESTING THE SPEED OF THE LOGIC CELL ARRAY

Each I/O block includes registered and direct input paths
and a programmable 3-state output buffer. The testing of
these functions is accomplished by several configuration/
test patterns that implement and test each option that is
available to the user. One method used to test the I/O
blocks is to configure them as a shift register that has a 3state control (See Figure 3). This allows a test pattern to
check the ability of each I/O block to latch and to output
data that is derived from either the previous I/O block or
from the tester. Several of these patterns are used to
exercise different input and output combinations allowed
for each I/O block. Configuration/test patterns are also
used to precondition the device to test dc parameters such
as V 1H , V 1L , V OH' VOL' TTL standby current, CMOS standby
current and input/output leakage. The V OH/VOL Test is done
while all outputs are either all Low or all High.

LCA speed is checked with configuration/test patterns
that have been correlated to data sheet ac values.
Most of these patterns are shift registers with interconnect,
lOBs and CLBs in the data path (See Figure 4). They are
designed with the idea that all elements inthe path must be
fast enough for the proper data to get to the next input of
the shift register before the next clock occurs. If any
element doesn't meet the specified ac value, then the shift
register will clock in the wrong data and fail the test. The
complexity of the logic between two shift register cells
determines the maximum frequency required for the clock
pulse input ofthe shift register. This can be used to reduce
the performance requirement of the tester in use. The
patterns used consist of a TCKO + TllO + INTERCONNECT + TICK for each shift register. This increases the
shift register clock pulse separation time to 30 to 40 ns.
The configuration of each pattern is varied so that all of the
interconnect, lOBs, and ClBs are tested at speed.

Configurable logic Block Testing
Each configurable logic block has a combinatorial-logic
section, a flip-flop section, and an internal-control section.
The combinatorial-logic section of the logic block uses an
array of RAM cells (16x1 in or 32X1 in) as a look-up table
to implement the Boolean functions. This section is tested
as an array of memory cells. Configuration/test patterns
are used to verify that each RAM cell can be logically
decoded as the output of the array. The flip-flop section of
the logic block is tested with configuration/test patterns
that configure the lCA device as shift registers. Each shift
register pattern will have different data in the look-up
tables and will have a different pin used as the input to
each shift register. Other configuration/test patterns are
used to implement and test the internal-control section.

HARDWARE TESTING CONSIDERATIONS FOR THE
LCADEVICE
Currently the logic Cell Array is being tested on Sentry
testers. The 68 and 84 pin versions can be tested on a 60pin tester with 256K of extended local memory. The 3000
series products are being tested on a 120-pin Sentry
Series 21 tester with 1 million vectors required for 3042 3090, 512K vectors required for3020 - 3030 and multiple
PMU measurement systems.

3-15

II

Test Methodology
Print World: patnOl.lca (2018PC84-70), XACT 2.05b Eng, Wed Mar 02 16:02:02 1988

'~int

World: patnOl.lca (2018PC84

~

~

U U
U
U
U
U

U U
U U
U U

U

U
U
U
U
U
U
U
U
U

U U U U U U
U U U U rl U
U U U 0 El U
U U U U U U
U U U U U U
U U U U LJ 0
U U LJ U U U
U U U U U U
U U U U U U

Figure 3. lOB Test Pattern

3-16

U
U
U

U
U
0
U
U

1:XIUNX

Figure 4. Speed Test Pattern

3-17

Packaging

PACKAGE AND USER I/O AVAILABILITY
Number of User I/O Available

XC2064

48 PIN

68 PIN

40

58

XC2018

58

XC3020

58

84 PIN

100 PIN

132 PIN

160 PIN

164 PIN

175 PIN

135

142

144

74
64

64

XC3030

74

80

XC3042

74

82

XC3064

96
110

XC3090

1112028

PACKAGE/SPEED/TEMPERATURE SELECTIONS

XC2064

XC2018

XC3020

XC3030

XC3042

XC3064

XC3090

xn04

3-18

PACKAGE THERMAL CHARACTERIZATION

Junction-to-Ambient Measurement - 9JA

Method and Calibration

9JA is measured on a 4.5" x 6.0" x .0625" (11.4 cm x
15.2 cm x 0.16 cm) FR-4 board. The data may be taken
with the package in a socket or, for packages used
primarily for surface mount, with the package mounted
directly on traces on the FR-4 board. The copper-trace
density is limited to the pads needed for the leads and the
10 or so traces required for signal conditioning and
measurement. The board is mounted in a cylindrical
enclosure and data is taken at the prevailing temperature
and pressure-between 22°C and 25°C ambient (TA). The
power application and signal monitoring proceed in the
same way as the 9JC measurement with enclosure
(ambient) thermocouple substituted for the fluid
thermocouple and two extra thermocouples brought in to
monitor room and board temperatures. The junction-toambient thermal resistance is calculated as follows:

Xilinx uses the indirect electrical method for thermalresistance characterization of packages. The forwardvoltage drop of an isolated diode residing on a special test
die is calibrated at a constant forcing current of 0.520 mA
with respect to temperature over a correlation temperature
range of 22°C to 125°C. The calibrated device is then
mounted in an appropriate environment, e.g. still air,
forced convection, FC-40, etc. Power (Pd) is applied to the
device through diffused resistors on the same thermal die;
usually between 0.5 to 4 W is applied, depending on the
package. The resulting rise in junction temperature (T)
is monitored with the forward-voltage drop of the precalibrated diode. Typically, three identical samples are
tested at each data point. The reproducibility error is close
to 6%.

TJ - TA
9JA = -----p(j

Junction-to-Case Measurement - 9JC
The junction-to-case characterization is measured in a 3M
Flourinert (FC-40) isothermal circulating fluid stabilized at
25°C. During the measurement, the Device Under Test
(OUT) is completely immersed in the fluid; initial stable
conditions are recorded, then Pd is applied. Case temperature (Tc) is measured at the primary heat-flow path of
the particular package. Junction temperature (T ) is calculated from the diode forward-voltage drop from t~e initial
condition before power is applied, i.e.

The setup lends itself to the application of various airflow
velocities from 0 - 800 Linear Feet per Minute (LFM), i.e.,
0- 4.06 mls. Since the board selection (copper trace
density, mounting distance, board thermal conductivity
etc) affects the results of the thermal resistance, the data
from these tests shall always be qualified with the boardmounting information.
Data Acquisition and Package Thermal Database
Data for a package type is gathered for various die sizes,
power levels, cooling modes (airflow and sometimes heatsink effects) with an IBM-PC based Data Acquisition and
Control System (DAS). The system controls and conditions the the power supplies and other ancillary equipment
for a hands-free data taking. Different custom-tailored
setups within the DAS software are used to run calibration,
9JA' 9JC ' fan test as well as power-effects characteristics of
a package. A package is completely characterized with
respect to the major variables that influence the thermal
resistance. A database is generated for the package.
From the database, thermal resistance data is interpolated
as typical values for the individual Xilinx devices that are
assembled in the characterized package. (See data in
following table.)

TJ - Tc
9Jc = -p(j
The junction-to-isothermal-fluid measurement 9JL can
also be calculated from the above data as follows:
TJ - TL

9JC =
where TL

-p(j

=isothermal fluid temperature.

The latter data is considered as the ideal 9JA data for the
package that can be obtained with the most efficient heat
removal scheme-airflow, copper-clad board, heat sink or
some combination of these. Since this is not a widely used
parameter in the industry, and it is not very realistic for
normal application of Xilinx packages, the data are not
published. The thermal lab keeps such data for package
comparisons.

3-19

II

Packaging
Thermal Resistance Data
Product and Package
(Socketed unless noted)

f)JAo C/W

XC1736A CD8
XC1765 CD8
XC1765 PC20

112.0
108.4
79.0

7.1
6.4
17.4

XC3030 PC44

43.6

10.7

XC2018
XC2318
XC2364
XC2064
XC3020
XC3030

PC68
PC68
PC68
PC68
PC68
PC68

40.7
42.4
42.4
42.1
40.9
39.4

8.1
9.9
9.9
9.5
8.3
7.0

XC2064
XC2018
XC3020
XC3030
XC3042
XC3064
XC3090

PC84
PC84
PC84
PC84
PC84
PC84
PC84

36.7
35.1
35.3
33.7
32.3
30.5
29.1

7.9
6.7
6.9
5.7
4.8
3.6
2.8

XC2064
XC2018
XC2020
XC3030
XC3042
XC3064

PG84
PG84
PG84
PG84
PG84
PG84

36.7
35.1
35.4
33.7
32.3
30.5

6.7
6.0
6.1
5.4
4.9
4.4

XC3020 PQ100'
XC3030 PQ100'
XC3042 PQ100'

67.6
62.7
58.2

9.3
6.8
5.0

XC3020 PQ100
XC3030 PQ100
XC3042 PQ100

75.3
71.1
68.1

XC3042 PG132
XC3064 PG132

26.5
24.1

2.5
2.0

XC3090 CQ164'
XC3090 PG175
XC3090 PP175

32.9
16.4
21.7

1.5
0.9
1.6

'Surface mounted

3-20

f)JCo C/W

PACKAGE CHARACTERISTICS

For more Information on SMT

Component Average Mass by Package Type and
Lead Count

The following organizations provide SMT consulting and
training, component part lists, and related services:

Package
Type

Lead
Count

PLCC
PLCC
PLCC
PLCC
PDIP
PDIP
Side Braze
Side Braze
PQFP
PQFP
CQFP
CQFP
CPGA
CPGA
CPGA
CPGA
PPGA
PPGA

20
44
68
84
8
48
8
48
100
160
100
164
68
84
132
175
132
175

Mass
(Grams)
0.75
1.20
4.80
6.80
0.52
7.90
0.95
8.00
1.6
5.80
3.60
8.35
6.95
7.25
11.75
28.40
8.10
10.60

o Brown Associates
(Surface Mounting Directory
and SMT: How to Get Started)
Box 43
Warrington, PA 18976
(215) 343-0123

Comment

Electronics Manufacturing
Productivity Facility (EMPF)
1417 North Norma Street
Ridgecrest, CA 93555-2510
(619) 446-7706

300 mil
600 mil

International Quality
Technologies, Inc.
4300 Stevens Creek Blvd
Suite 203
San Jose, CA 95129
(408) 246-6071

14 mmx 10 mm
28 mmx28 mm
Unformed
Unformed
11 x 11 Array
11 x 11 Array
14 x 14 Array
16 x 16 KCW10 HIS
14 x 14 Cu Slug
16 x 16 Cu Slug

National Training Center
Northhampton Area College
3835 Greenpond Rd
Bethlehem, PA 18017
(215) 861-5486
Surface Mount Council
CIO IPC
7380 N Lincoln Ave
Lincolnwood, II 60646

• Data represents average values fortypical packages with
typical devices. For accuracy between 7% to 10%, these
numbers will be adequate.
'More precise numbers (below 5% accuracy) for specific
devices may be obtained from Xilinx through a factory
representative.
Ceramic Quad Flat Pack (CQFP)
The Ceramic Quad Flat Pack (also called Quad Cerpack)
is a cavity down, pressed ceramic package. The leads are
gull-wing, on four sides, with 25-mil pitch. It is for surface
mount Commercial, Industrial, and Military (including
MIL-STD-883 Class B) applications. JEDEC has
developed a standard that Xilinx will follow.
Plastic Quad Flat Pack (PQFP)
The Plastic Quad Flat Pack is an EIAJ standard package.
The leads are gull-wing on four sides. It is for surface
mount Commercial applications.

3-21

III

Packaging

a compatible PGA socket with wire-wrap pins. Note that
the board-layout then differs from a PGA board layout.

SOCKETS
Below are two lists of manufactures known to offer sockets
for Xilinx package types. This list does not imply an
endorsement by Xilinx. Each user must evaluate the
particular socket type.

Zero Insertion Force (ZIF) sockets, recommended for
prototyping with 132 and 175 pin PGA devices, also lack
the wire-wrap option. Piggy-back the ZIF socket in a
normal PGA wire-wrap socket.

There are no wire-wrap sockets for PLCCs. One solution
is to piggy-back a through-hole PLCC socket mounted in
PLCC Sockets
AMP Inc.
Harrisburg, PA 17105
(717) 564-0100
Burndy Corp.
Richards Ave.
Norwalk, CT 06856
(203) 852-8437
Garry Electronics
9 Queen Anne Court
Langhorne, PA 19047-1803
(215) 949-2300
Honda - MHOtronics
Deerfield. IL 60015
444 Lake Cook Road, Suite 8
(312) 948-5600
ITT Cannon
10550 Talbert Ave.
P.O.Box 8040
Fountain Valley, CA 92728
(714) 964-7400
Kycon Cable & Connector
1772 Little Orchard Street
San Jose, CA 95125
(408) 295-1110
Maxconn Inc.
1855 O'Toole Ave., 0102
San Jose, CA 95131
(408) 435-8666
Methode Electronics Inc.
1700 Hicks Road
Rolling Meadows, IL 47150
(312) 392-3500

PGA Sockets
Mill-Max Mfg. Corp.
190 Pine Hollow Road
Oyster Bay, N.Y. 11771-0300
(516) 922-6000

Advanced Interconnections
5 Energy Way
West Warwick, RI 02893
(401) 823-5200

McKenzie Technology
44370 Old Warm Springs Blvd.
Fremont CA 94538
(415) 651-2700

Precicontact Inc.
835 Wheeler Way
Langhorne, PA 19047
(215) 757-1202

AMP Inc.
Harrisburg, PA 17105
(717) 564-0100

Methode Electronics Inc.
1700 Hicks Road
Rolling Meadows, IL 47150
(312) 392-3500

Aries Electronics, Inc.
P.O.Box 130
Frenchtown, NJ 08825
(201) 996-6841

Robinson Nugent
800 East Eighth Street
New Albany, IN 47150
(812) 945-0211
Samtec Inc.
P.O.Box 1147
New Albany, IN 47150
(812) 944-6733
3M Textool
Austin, TX
(800) 328-7732
Thomas & Betts Corp.
920 Route 202
Raritan, NJ 08869
(201) 469-4000
Wells Electronics, Inc.
1701 South Main Street
South Bend, IN 46613
(219) 287-5941
Yamaichi - Electronics, Inc.
1420 Koll Circle
Suite B
San Jose, CA 95112
(408) 452-0799

3-22

Mill-Max Mfg. Corp.
190 Pine Hollow Road
Oyster Bay, N.Y. 11771-0300
(516) 922-6000

Augat
33 Perry Ave.
P.O.Box 779
Attleboro, MA 02703
(617) 222-2202

Precicontact Inc.
835 Wheeler Way
Langhorne, PA 19047
(215) 757-1202

Bevmar Industries, Inc.
20601 Annalee Ave.
Carson, CA 90746
(213) 631-5152

Robinson Nugent
800 East Eighth Street
New Albany, IN 47150
(812) 945-0211

Bevmar Industries, Inc.
1 John Clarke Rd.
Middletown, RI 02840
(401) 849-4803

Samtec Inc.
P.O.Box 1147
New Albany, IN 47150
(812) 944-6733

Electronic Molding Corp.
96 Mill Street
Woonsocket, RI 02895
(401) 769-3800

Texas Instruments
CSD Marketing, MS 14-1
Attleboro, MA 02703
(617) 699-5206

Garry Electronics
9 Queen Anne Court
Langhorne, PA 19047-1803
(215) 949-2300

Thomas & Betts Corp.
920 Route 202
Raritan, NJ 08869
(201) 469-4000

Mark Eyelet Inc.
63 Wake lee Road
Wolcott, CT 06716
(203) 756-8847

Yamaichi - Electronics, Inc.
1420 Koll Circle
Suite B
San Jose, CA 95112
(408) 452-0799

SECTION 4
Technical Support

1

Programmable Gate Arrays

2

Product Specifications

3

Quality, Testing, Packaging

4

Technical Support

5

Development Systems

6

Applications

7

Article Reprints

8

Index

Technical Support

Technical Seminars and Users' Group Meetings ............................... .4-1
Video Tapes ........................................................................................ 4-2
Newsletter ........................................................................................... 4-3
Technical Bulletin Board ..................................................................... 4-4
Field Application Engineers ................................................................. 4-6
Training Courses ................................................................................. 4-7
Technical Literature ............................................................................. 4-8

Beyond the technical data in this book, Xilinx provides a
wealth of additional technical information to LeA users.
The following pages give an overview of the existing

material, beginning with Technical Seminars and ending
with detailed Technical Manuals.

Technical Seminars and
Users' Group Meetings

£,el~\(\

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Users' Group meetings are intended for experienced users of Xilinx Field Programmable Gate Arrays, and emphasize the use of the various development system tools to
generate LCA-based designs.

Xilinx sponsors technical seminars at locations throughout
North America, Europe, and Asia.
Product-oriented seminars are directed toward new and
potential users of Field Programmable Gate Arrays.
These seminars include a basic description of the Logic
Cell Array architecture and the benefits of this technology.
Experienced users will also find these seminars useful for
learning about newly released products from Xilinx.

Contact your local Xilinx sales office, sales representative,
or distributor for information about seminars in your area.

4-1

II

Video Tapes

A one-hour video tape, entitled "Programmable Gate Arrays: The Ideal Logic Device," is available from Xilinx. The
presentation is divided into three main sections. The first
portion of the video tape is an overview of the Logic Cell
Array architecture and the development system, including
some example applications. The second section contains
a description of the XiUnx product families, a more detailed
description of the XC3000 series architecture, a description of the LCA configuration modes, and a brief discussion
of programmable gate array performance in terms of

speed, density, and cost. Development systems and the
deSign methodology are discussed in the last third of the
presentation, including on-screen demonstrations of
some of the software tools. Additional video tapes covering specific details are in preparation.
VHS copies are available in NTSC, PAL, and SECAM
formats; contact your local Xilinx sales office, sales representative, or distributor.

4-2

Newsletter

II

bugs and work-a rounds. Applications ideas and user tips
and a list of relevant magazine articles make this a valuable source of information for the systems designer using
LCA devices.

In September '88, Xilinx started a quarterly technical
newsletter to supply up-to-date information to registered
Xilinx customers. This newsletter gives updates on hardware and software availability and revision levels. It also
carries information on PC-clone compatibility, software
4-3

Xilinx Technical
Bulletin Board

M)SG-SECTION

F)ILE-SECTION

B)ULLETIN

G)OODBYE

Enter this section to send and
receive messages.

The file section is divided into
several areas. Enter this
sectio~6~~~~d ~fI!~d and

Enter this section to read the
"latest and greatest" information
on the Xilinx Bulletin Board.
A list of bulletins is automatically displayed.

At this time you can leave a
message for the system
operator. See the M)SGSection for instructions on
how to send messages to
other bulletin board users.

TYPE:
E

[E)NTERJ

To send a message.

TYPE:

TYPE:

A [A)REAJ



To list the existing file areas.

To display a specific bulletin
on the screen.

After choosing a file area, you
can now list all the files in this
area.

TYPE:
F

[F)ILESJ

To display the available files,
the size of each file in bytes

~g~t:~~~df ~~~'i:'if;I~~n of the
.............
:.. :.:..:...... :.:.: ........ .

D~CR>,JDiqWN~qADJ
R

[R)EPLYJ

To reply to a mesage you've
just read.

'fodQwni9ad\:ine Q(!noreflies

1[Om l~.I:lUlietin board: ... ..

L

[L)ISTJ

To locate a file in any accessable area

:'TeCH:';':':

• Files can be uploaded from
any file area by typing:

UeCR>

[U)PLOADJ

To provide customers with up-tO-date information and an
immediate response to questions, Xilinx provides a 24hour electronic bulletin board. The Xilinx Technical Bulletin Board (XTBB) is available to all registered XACT

customers. Users with full privilege can read files on the
bulletin board, download those of interest to their own
systems or upload files to the XTBB. They can also leave
messages for other XTBB users.

4-4

New bulletin board users must answer a questionnaire
when they first access the XTBB. After answering the
questionnaire callers can browse through the bulletin and
general information file areas. Before exiting, they should
leave a message for the system operator requesting full
access. A caller with a valid XACT protection key will be
given full user privileges within 24 hours.

The XTBB is based on a bulletin board system called
FIDO. FIDO is a menu-driven system-you choose commands from menus to decide what happens next. To
choose a menu command, simply type the first letter of the
command and press return . Listed below are some
helpful hints for using the XTBB.
• To perform a sequence of commands, type the first letter
of each command, followed by a space, and press
return. For example, typing F A 1 F  [F)i1e A)rea
1 F)i1es] from the main menu will list all of the files
contained in file area 1.

The software and hardware requirements for accessing
the Xilinx Technical Bulletin Board are:
Baud Rate
1200 or 2400
Character Format 8 data bits, no parity, 1 stop bit
Phone Number
(408) 559-9327
Transfer Protocols ASCII, Kermit, Xmodem,
- CRC, Telink

• Often the user is asked a question and promped to
choose between two options (e.g. [yes NO]). The option
displayed in all capital letters is the default choice. To
select this option, simply press return. Otherwise, type
your choice and hit return.

Information contained on the XTBB is divided into three
general categories: 1. Bulletins, 2. Files and 3. Messages.

• The XTBB has an extensive help section. To get help,
type ?. If you have questions about a specific
command, type the first.letter of the command followed
by a question mark and a carriage return (e.g.F?r
i} i/
>

'i

,

Q1

;;il
I

"~ <
Ci

NOT2

<:-

ii

.. ,
<»}'<>}

}

i>

it

i

OUTPUT LOW
WHEN
COUNT =2

DECODECLB
1954 09

The merged design contains the CLBs and lOBs for the entire design.

5-8

Step 2: Translating to an LeA File
XMAKE
Shaded area indicates commands automatically
invoked by execution of XMAKE in the Design
Manager.

To Place
} - - - - - , - - -.. and Route
Page 5-10
Unrouted
Logic Cell Array
File
To Simulator
' - - - - _ (Unit-delay Simulation)

Page 5-12
1954 lOB

0 0 0 oa
{)
{) a 0 0 0 0 a 0
{I
{) 0 0 [l o 0 0 0 [l {}
a 0 0 Q0
0
Q
0
[}
iJ
{]
0 QG
{] 0 0 Q 0
[}
[}
iJ
{] 0 0 0 0 0 0 0 0 [}
[}
11
0 0 0 0 a o0 0
{J

aa
ao

~

~ 00 co

o;::J OOC:OO 00

co

~

0

0

o;j

·0

tJtJ O[

III

[
1954 11

195402

Initially (before Place and Route) the LCA design is
unrouted, and the Configurable Logic and 1/0 blocks are
put in random locations.

5-9

Design Flow

Step 2: Placing and Routing the LeA File

LCA

Unrouted
LCA File

Automatic Place
and Route Program
(APR)
and/or
XACT Design Editor

LCA

Placed and Routed
LCAFile
To Simulator
' - - - - _ Full Timing Simulation
Page 5-12

DS501

1954 128

n

o
1954 18

A simple placed and routed design (closeup of upper-left
corner of 2064PC68).

5-10

The Automatic Place and Route (APR)
program uses sophisticated algorithms to
determine the optimal placement and routing
for a design. The XACT Design Editor, an
interactive graphics-based placement and
routing tool, is available for the experienced
designer who wants to pre-place critical
portions of the design or "tweak" the output of
the APR program.

Step 2: Bitstream Generation

BIT

Configuration
Bitstream
Compiler
(MAKEBITS)

To In-Circuit
Design
} - - - - - - - - - - Verification
Page 5-14

DS501
1954 14B

The BIT file contains the binary configuration data that
programs an LCA to perlorm the design function.

1111111100100000000000111001111001001111
0011111111011111111111000101111011111101
0111111010110111011110111011111110111111
0111011101101111011111110111111101111111
0011111111111111111111111111011111111111
0111001101110111011101111011111110111111
1111111100100000000000111001110001001111

II

0011100011110111110111111111111111111111
0011111110111111111101111110111111111111
0011111111111101111111111111101111101111
0111111011101110111111101111111011111110
0111111010110111011 ...

LCA Configuration Bltstream

5-11

Design Flow

Step 3: Functional and Full Timing Simulation

LCA

XNF
Xilinx
LCA2XNF
Translator

SIM

XNF-toSimulator
Translator

CLB-Ievel
XNF File

DS501

Simulator
Nellist

Simulator
Stimulus
DefinHion

Simulator
(SILOS,
VIEWsim,
OrCAD,
Mentor QSim,
etc.)

Input
Patterns
1954 198

....
J
•.••.••••••••••••••••

CLOCK

CLOCK

00

.......

.......

1954 20

.......

Designer defines design inputs .

..•..

>t2···················

01

NOT2>1"

.....

1<

::·K<
...................................................................
OUTPUT LOW
WHEN
COUNT 2
DECODECLB

1954 09

LCA designs are simulated at the physical CLB and lOB level with worst-case
liming.

5-12

E:XIUNX
Step 3: Functional and Full Timing Simulation

Simulation provides for
design analysis under worstcase temperature, voltage, and
process conditions.

CLOCK

'--_-----'I
01

LJ

NOT2

195421

Each I/O pin and CLB output can be observed with a
simulator driven by input stimuli. The simulator displays
the logic behavior and ac performance of the design in
graphics or text form.

II

5-13

Design Flow

Step 3: Real-time, In-circuit Verification

BIT

HEX

Xilinx PROM
Format Generation
(MAKEPROM)

PROM
Pr08rammer
(Xilinx, ata 1/0, etc.)

Configuration
Bitstream File
DS501

Xilinx
Download Cable,
Provided with
XACT Design
Editor

Download Bitstream from PC or Workstation
into LCA for In-circuit Verification
(no PROM programming)

DS501

Xilinx or Data 1/0
In-Circuit
Design
Verifier

Connect Emulator Pod(s) to
TarQet System for Real-time
In-circuit Verification

DS28 or MESA
1954158

5-14

In-circuit verification lets you immediately see
how your LeA designs function ...

Program a PROM ...
TARGET SYSTEM

O

Serial or Parallel
PROM

Programmed with
Configuration
OataforLCA

1954 lSA

Use the Download Cable ...
TARGET SYSTEM
Download Cable connects to
LCA control pins on LCA
socket in your target system
Download Cable
connects to
Raralle I port of
PC or serial port
of workstation

D

LCA
1...-_ _

o
1954 17A

... Or use the Xilinx XACTOR or Data 1/0 MESA Design Verifier

The XACTOR controller (left) can control up to four
emulation pods (center). An emulation header
(right) connects each pod to an LCA socket In the
target system.

5-15

III

Xilinx Automatic CAE Tools
Product Overview

DESIGN FLOW

An important feature of the XACT Development System is
the capability to incorporate design changes, frequently
encountered during verification. Small changes can be
made to the schematics and then automatically
incorporated into the existing design with minimal impact
on existing routing and performance. Using this
"incremental design" capability, the designer can develop
"production quality" programmable gate arrays on a PC or
engineering workstation.

The Xilinx Automatic CAE Tools (XACT Development
System) use a 3-step design process:
• Step 1:

DESIGN ENTRY

• Step 2:

DESIGN IMPLEMENTATION

• Step 3:

DESIGN VERIFICATION

The Xilinx Logic Libraries and XNF Interface Products
support design entry with popular schematic logic drawing
systems supplied by multiple vendors, providing easy
entry to the XACT Development System. Logic entry from
Boolean equations or a variety of state machine language
systems is also supported in the Design Implementation phase.
Logic synthesis, partitioning, and optimization
translate the design specifications into CLBs
unique to the LCA architecture. Subsequent
perform automatic placement and routing
complete the LCA design.

PLATFORM AND ENVIRONMENT SUPPORT
The Xilinx Automatic CAE Tools, XACT, are currently
available for the following platforms:
• IBM PC/AT, PS/2, and compatibles
• Apollo DN4000 Series
• Sun-4 and SparcStation Series
• Sun-3 Series 960 and above
• DECstation 3100 Series
Xilinx and third-party vendors have developed library and
interface products compatible with a varietyof design entry
and simulation environments. Xilinx has provided a
standard interface file specification, XNF, to simplify file
transfers into and out of the XACT Development System.

programs
and lOBs
programs
(APR) to

While completely automatic implementation is desirable
for both low and high-complexity designs, the designer
may prefer an interactive process, especially in highperformance designs. This interactive editing can range
from rerouting a few previously automatically routed nets,
to prerouting critical nets or preplacing CLBs prior to
design completion using APR, to more extensive control
over logic partitioning and placement into CLBs. The
Automatic Place and Route software gives the designer an
option for direct control over specific logic mapped into
CLBs (partitioning) to provide better distribution of logic
signal routing through the LCA device. The XACT Design
Editor, XDE, is extremely versatile, ranging from design
entry to CLB and signal routing manipulations. This
combination of automatic and interactive design editing
capability is a unique feature provided by Xilinx.

Xilinx directly supports the following design environments:
• FutureNet DASH
• VIEWlogic VIEWdraw and VIEWsim
• Mentor Graphics NetED and Qsim
• OrCAD SOT and VST
• SILOS
Several other environments are supported by third-party
vendors.
A collection of over 100 TTL logic macrofunctions is
available for the schematic editors, and is included in the
appropriate packages at no charge.
The XACT Design Manager, XDM, simplifies the selection
of command-line options with pull-down menus and online help texl. Application programs ranging from
schematic capture to APR can be accessed from the XDM,
while the sequence of program commands is generated
and stored for documentation prior to execution. The
XMAKE command in the XDM automates the entire
translation, optimization, merging, and mapping process.

Logic simulation or actual in-circuit emulation provides for
functional verification, while timing analysis permits
verification of critical timing paths under worst-case
conditions. The system contains a compiler to generate
bitstream patterns to configure the LCA device according
to the deSigner's specification. The overall design flow is
illustrated on page 5-17.

5-16

r----------,

I

OTHER
I
SCHEMATIC ENTRY I
SYSTEMS
I
I MENTOR DS343-AP11
I OrCAD DS35-PC1 I
I

STEP 1

DESIGN
ENTRY

MACRO
&

FUTURENET
DASH-LCA

MSI
LIBRARIES

VlEWd rawLCA
DS390-PC1

I

I

L ___ _

I
I
I

XILINX LOGIC LIBRARY & XNF INTERFACE

r ABEL. CUPL-;- -,

I

I
LOG/IC,
I
I PGADESIGNER, I

L_-n-_-l
r-I

I'--------'

---,

PALASM

I--~-"J

I TRANSLATOR 1----.--,/1
L ______
~..J-=~====~

LOGIC REDUCTION
PARTITIONING
& OPTIMIZATION
TRANSLA TlON INTO
CLBS&IOBS

STEP 2

DESIGN
IMPLEMENTATION
08501

II
GATE LEVEL
SIMULATION
LOGIC
CELL
ARRAY

STEP 3

DESIGN
VERIFICATION

LOGIC &
TIMING
SIMULATION

IN-CIRCUIT DESIGN
VERIFIER

1956 01C

5-17

Xilinx Automatic CAE Tools Product Overview

Xilinx Automatic CAE Tools Product Options

Step
1

"

•
•
•
•
•
•
•
•

LCA Logic Synthesis Tools
OASH-LCA Editor and interface
FutureNet OASH Interface
Mentor Graphics NetEd and Qsim Interface
OrCAO SOT Interface
VIEW-LCA Schematic Editor and Interface
VIEWdraw and VIEWsim Interface
EOIF 2.0.0 Netlist Interface

OS371
OS310
OS31
OS343
0535
OS390
OS391
OS361

Step

2

• XC2000 & XC3000 Series XACT Oesign
Implementation System

OS501

•
•
•
•
•

OS22
OS290
OS351
OS112
OS28

"
Step

3

SILOS Simulator and Interface
VIEWsim Simulator and Interface
OrCAO VST Interface
Serial Configuration PROM Programmer
XACTOR In-Circuit Oesign Verifier

5-18

XC-DS310 DASH-LCA
Schematic Editor, Interface
and Library
Step 1 Option

Product Brief

FEATURES
DASH-LCA supports unlimited levels of hierarchy. The
Xilinx DASH-LCA Schematic Library provides the symbol
library and conversion utility to permit designers to enter
LCA designs with the DASH-LCA Schematic Editor. The
Xilinx library provides the logic, I/O, and macro symbols to
be used in the schematic. A Xilinx conversion utility
converts the schematic into an XNF output file.

• Xilinx only FutureNet DASH-LCA schematic editor
provides easy-to-use hierarchical LCA design
capability
• Macro library of over 100 standard logic family
equivalents derived from the XACT Macro Library
• Library of logic symbols including all two-input, threeinput and four-input AND, OR and XOR gates plus
storage, inpuVoutput and clock elements

Once partitioned, the design may be placed and routed
with the XC-DS501 XACT Design Implementation
System. The Xilinx symbol library includes symbols to flag
critical data and clock signals which the Automatic
Placement and Routing Program uses to prioritize those
signals for minimum delay.

• Additional 100 7400 TTL library elements. See
page 5-34 for a listing of TTL macros
• User control for flagging critical paths for the
Automated Placement and Routing program
• Converts schematic drawings to a Xilinx Netlist
Format (XNF) output file
• Output compatibility with XC-DS501 XACT Design
Implementation System
• Runs on PC/AT or compatible personal computers

GENERAL
Schematic entry and automatic partitioning of LCA
designs shortens logic reduction and product
development times. Complex designs can be specified
schematically and quickly implemented for in-circuit
design verification.

II

3002

5-19

~xnJXX

XC-DS31 DASH
Schematic Interface and
Library

Step 1 Option

Product Brief

FEATURES

GENERAL

• Library and translator for users of the DASH Schematic
Designer

Schematic entry and automatic partitioning of LCA
designs shortens logic reduction and product
development times. Complex designs can be specified
schematically and quickly implemented for in-circuit
design verification.

• Macro library of over 100 standard logic family
equivalents derived from the XACT Macro Library
• Library of logic symbols including all two-input, threeinput and four-input AND, OR and XOR gates pius
storage, inpuVoutput and clock elements

The Xilinx DASH Schematic Designer Library provides the
symbol library and conversion utility to permit designers to
enter LCA deSigns with the DASH Schematic Designer.
The Xilinx library provides the logic, 110, and macro
symbols to be used in the schematic. A Xilinx conversion
utility converts the schematic into an XNF output file.

• Additional one hundred 7400 MSllibrary elements. See
page 5-34 for a listing of all macros.
• User control for flagging critical paths for the
Automated Placement and Routing program
• Converts schematic drawings to a Xilinx Nellist Format
(XNF) output file

Once partitioned, the design may be placed and routed
with the XC-DS501 XACT Design Implementation
System. The Xilinx symbol library includes symbols to flag
critical data and clock signals which the Automatic
Placement and Routing Program uses to prioritize those
signals for minimum delay.

• Output compatibility with XC-DS501 XACT Design
Implementation System
• Runs on PC/AT or compatible personal computers,
Sun 3 and Sun 4

Xilinx provides ongoing support for users of the DASH
Schematic DeSigner Library. For the first year, software
updates are included. After that, the user may purchase
the XC-SC31 Annual Support Agreement to continue to
receive the latest software releases.

1964

5-20

XC-DS343 Mentor Graphics
Schematic and Simulation
Interfaces and Library
Step 1 Option

Product Brief

FEATURES

GENERAL

• Mentor Graphics certified interfaces

Schematic entry and automatic partitioning of LCA
designs shorten logic reduction and product-development
times. Complex designs can be specified schematically
and quickly implemented for full timing simulation and
in-circuit design verification.

• The IDEA" Interface Station can be used for
schematic entry and simulation of programmablegate-array designs
• Full timing simulation with post placement/routing
information

The Xilinx DS343 package provides the symbol library
and conversion utility to permit designers to enter LCA
designs with the Mentor Graphics NetED Schematic
Editor. The Xilinx library provides the logic, I/O, macro,
and TTL symbols to be used in the schematic. A Xilinx
conversion utility converts the schematic into an XNF
output file.

• Primitive library includes flip-flops, latches, AND, OR,
XOR, NAND, NOR gates
• Macro library includes over 100 standard logic
elements (counters, multiplexers, registers, etc.)
• Additional one hundred 7400 MSllibrary elements
included at no charge. See page 5-34 for a listing of
all macros (available 1H91).

Once partitioned, the design may be placed and routed
with the Apollo-based XC-DS501 XACT Design
Implementation System. The Xilinx symbol library
includes symbols to flag critical data and clock signals
which the Automatic Placement and Routing Program
uses to prioritize those signals for minimum delay.

• Xilinx Nellist Format (XNF) output is compatible with
XC-DS501 Design Implementation System
• Available on Apollo SR10.1 and Mentor IDEA V7.0
'IDEA is a registered trademark of Mentor Graphics

DESIGN
VERIACATON

DESIGN ENTRY

~

II
-------,
I
I

I
I
I
I

_______ .1

DESIGN
IMPLEMENTATION
XC.I)S501 XACT
DESIGN IMPLEMENTATION
SYSTEM

I

I
I
I
I

I
______________________________________ .1

5-21

1958026

XC-DS35 OrCAD* SDT
Schematic Entry Interface
and Design Library
Step 1 Option

Product Brief

FEATURES

Xilinx library provides the logic, I/O, and macro symbols to
be used in the schematic. A Xilinx conversion utility
converts the schematic into an XNF output file.

• Library and translator for users of the OrCAD* SDT
Schematic Editor

Once partitioned, the design may be placed and routed
with the PC-based XACT Automated Design
Implementation Program. The Xilinx symbol library
includes symbols to flag critical data and clock signals
which the Automatic Placement and Routing Program
uses to prioritize those signals for minimum delay.

• Library of over 100 standard logic macros
• Library of logic symbol primitives includes AND, OR,
NAND, NOR, and XOR gates plus storage, input/output
and clock elements
• Additional one hundred 7400 MSllibrary elements
included at no charge. See page 5-34 for a listing of
all macros (available 1 H91).

r------------------,

• User control for flagging critical paths for the
Automated Placement and Routing Program

I
I

• Converts schematic drawings to a Xilinx Netlist Format
(XNF) output file

I
I

• Output compatibility with XACT Design Implementation
System

L ______ _

_________ ...JI

r--

---------,

OrCAD SOT III

I

I
I

• Runs on a PC/AT or compatible personal computer

I
I

-----

I

I
I
I
I

GENERAL

LCA
LIBRARY

XNF
TRANSLATOR

I
L _______ _

Schematic entry and automatic partitioning of LCA
designs shorten logic reduction and product development
times. Complex designs can be specified schematically
and quickly implemented for in-circuit design verification.

XC-DS35
OrCAD
INTERFACE

I
I

_________ ...JI
XNF
NETLIST
FORMAT

The Xilinx OrCAD Schematic Entry Interface provides the
symbol library and conversion utility to permit designers to
enter LCA designs with the SDT Schematic Editor. The

To XACT XC-DS501
Design Implementation System

'OrCAD is a registered trademark of OrCAD Systems Corp.

5-22

1966019

ADVANCE INFORMATION

XC-DS361 EDIF
Netlist Interface
Product Brief

Step 1 & 3 Options
FEATURES

DESIGN
ENTRY
TooL<

• Provides Xilinx netlist interfaces to many design-entry
and verification tools that support EDIF
• Reads and writes LCA designs in EDIF v 2.0 format
netlist
• Supports all logic symbols and timing parameters
supported by XACT Design Implementation System
• Runs on all Xilinx-supported PC and workstation
platforms

DESIGN
VERIFICATION
TooL<
LCA
SIMULATION
MODELS

LCA
LIBRARY

XILINX EDIF
NETLIST
INTERFACE

GENERAL
The Xilinx EDIF Nellist Interface, used in conjunciton with
an LCA library, permits designers to enter and verify LCA
designs using popular CAE tools that support EDIF.

XNF
NETLIST
FORMAT

The design is created using an LCA library for the desired
CAE tool (available from either Xilinx or the CAE vendor).
The design is converted to an EDIF nellist using the CAE
tool, then translated into a Xilinx nellist using the Xilinx
EDIF Nellist Interface.

To XACT XC-DS501
Design Implementation System

The design is then partitioned, placed and routed using the
XC-DS501 XACT Design Implementation System to simulate the design. It is then translated back to EDIF format
- with full timing - using the Xilinx EDIF Nellist Interface.
Once in EDIF format, the design can be read into an EDI Fcompatible design environment for simulation.

.. Contact Xilinx for current list of compatible third-party CAE tools

1992018

II

5-23

XC-OS390 VIEWdraw-LCA
Schematic Editor, Interface
and Library
Step 1 Option

Product Brief

FEATURES

VIEWdraw-LCA is the Xilinx-only VIEWdraw Schematic
editor and supports unlimited levels of hierarchy. The
Xilinx VI EWdraw-LCA Library provides the symbol library
and conversion utility to permit designers to enter LCA
designs with the Xilinx-only VIEWdraw Schematic Editor.
The Xilinx library provides the logic, I/O, and macro
symbols to be used in the schematic. A Xilinx conversion
utility converts the schematic into an XNF output file.

• VIEWlogic VIEWdraw-LCA Schematic Editor provides
easy-to-use hierarchical LCA design capability
• Macro library of over 100 standard logic family
equivalents derived from the XACT Macro Library
• Library of logic symbols including all two-input, threeinput and four-input AND, OR and XOR gates plus
storage, inpuVoutput and clock elements
• Additional one hundred 7400 MSllibrary elements
included at no charge. See page 5-34 for a listing of
all macros (available 1H91).
• User control for flagging critical paths for the
Automated Placement and Routing
• Converts schematic drawings to a Xilinx Nellist
Format (XNF) output file
• Output compatibility with XC-DS501 XACT Design
Implementation System
• Runs on PC/ATor compatible personal computers

Once partitioned, the design may be placed and routed
with the PC-or workstation-based XC-DS501 XACT
Design Implementation System. The Xilinx symbol library
includes symbols to flag critical data and clock signals
which the Automatic Placement and Routing Program
uses to prioritize those signals for minimum delay.

GENERAL
Schematic entry and automatic partitioning of LCA
designs shorten logic-reduction and product-development
times. Complex designs can be specified schematically
and quickly implemented for in-circuit design verification.

5-24

XC-DS391 VIEWlogic
VIEWdraw and VIEWsim
Interfaces and Library
Step 1 and Step 3 Options

Product Brief

FEATURES

GENERAL

• Library and translator for userll of the VIEWlogic
VIEWdraw Schematic Editor and VIEWsim Simulator

Schematic entry and automatic partitioning of LCA
designs shorten logic-reduction and product -development
times. Complex designs can be specified schematically
and quickly implemented for in-circuit design verification.

• Macro library of over 100 standard logic family
equivalents derived from the XACT Macro Library
• Library of logic symbols including all 2-input, 3-input
and 4-input AND, OR and XOR gates plus storage,
inpuVoutput and clock elements

The Xilinx VIEWdraw Library provides the symbol library
and conversion utility to permit designers to enter LCA
designs with the VIEWdraw Schematic Designer. The
Xilinx library provides the logic, I/O, and macro symbols to
be used in the schematic. A Xilinx conversion utility
converts the schematic into an XNF output file.

• Additional 100 7400 TTL library elements. See
page 5-34 for listing of the TTL macros.
• User control for flagging critical paths for the
Automated Placement and Routing

Once partitioned, the design may be placed and routed
with the PC- or workstation-based XC-DS501 XACT
Design Implementation System. The Xilinx symbol library
includes symbols to flag critical data and clock signals
which the Automatic Placement and Routing Program
uses to prioritize those signals for minimum delay.

• Converts schematic drawings to a Xilinx Nellist
Format (XNF) output file
• Converts XNF files to format accepted by VIEWsim
Simulator for logic and timing simulation
• Output compatibility with XC-DS501 XACT Design
Implementation System

With the Xilinx VIEWsim Simulation Interface, designers
can use the VI EWlogic Simulation environment to perform
post-layout simulation. All post-layout timing information,
including pin-to-pin delays, is back annotated into the
VIEWlogic environment for full timing simulation.

• Runs on PC/AT-compatible personal computers,
Sun-3, Sun-4 and DECstation 3100

II

188.8ns 11111118888881888888
112.8ns 11111111888881888888
123.8ns 11111111818881888888
133.8ns 1111111181888BBBBBBB
15B.8ns B1111111B18888888888
28B.Bns 11111111818888888888
212.8ns 11111111118888888888
221. 8ns 111111111118BBBBBBB81"YI.T"·~""
258.8ns 8111111111188888B888
3BB. 8ns 1111111111188B8888881!~!~!::~S!
312.8ns 1111111181188B88BB881;
321. 8ns 1111111181818B888888IsYINTH'Dt.
358.8n8 8111111181818B888888
48B.8n811111111818188888B88

X125f

5-25

ADVANCE INFORMATION

E:XILINX

XC-DS371 LCA Logic
Synthesis Tools

Step 1 Option

Product Brief

FEATURES

The multiple-mode design is combined into the LCA architecture in the following steps. The schematic is converted
by the netlist translator to the Xilinx Netiist Format (XNF)
file. Then, the PALASM2 and Xilinx State Machine Language are translated and optimized, resulting in a second
XNF file. The design files are then merged and partitioned
into CLBs and lOBs.

XlIlnx State Machine Language
• Combines the simplicity of popular PLO languages
with the power and expressiveness of VHOL.
• Allows complex state machine implementation using a
simplified VHOL-like language.

PLO synthesis and XNF optimization will continue to be
included in the 05501 package until the OS371 becomes
available.

• Supports multiple state machines.
• External-file-reference capability and syntax-alias
capability provide versatile environment for statemachine entry.

-an example of a VHDL-State description of
a traffic light controller
- (cases omitted for readability)

Xlllnx State Machine Complier

CHIP traffic 0- 1

S,=1

c.
1

B.

A,

B,

0

x
x
x
x

x
x
x
x

0
0
0

0
0
0
0
0
0

0
0

1

0

0

1

1

1
1

x
1
1

x
0
0

1

x
1

x
0
0

x
0
0

0
0

0

x
1

1
1

x

x
x

x

1
1

x
1
1

1
1

0

x
x
C.=1

"-0

1
1

x
1
1

x

1
1
1

0
0

0
0
0

1
1

1
1
1

1
1
1
1
1
1

1
1
1
1

0
0
0
1
1
1

x
x
x
1
1

x

1

x

A,

B,

A.

B.

0

0
0

x
x
x
x

x
x
x
x

1
1

1141 04

Figure 4. Serial Adder/Subtractor

A bit-serial identity comparator detects only whether the
two operands are equal or not, without determining which
one (if any) is larger. The bit stream can come in lSB or
MSB first, the flip-flop gets set for any difference between
A and B, and stays set until the end of the word, then gets
reset before the beginning of the next word. This "difference detector" can also be implemented as a latch and
folded into the combinatorial logic.
A bit-serial magnitude comparator distinguishes between
A = B, A > B and A < B. It can operate lSB first or MSB first.
if the logic is adjusted:
lSB first: Start with both flip-flops reset
if A > B set Ox, reset Oy

Inputs
Outputs
S.=1

S,=1

C,
1

0
0

0

1

1
1

x
1

x

x

0

0
0

0
0

x

CP.=1

1
1

1
1

x

CG.=1

1

x

0
0

x

0
0

x

1
1

x
0
0

0

x

1

1
1

1
1

x

x
x
x
x
x
x
x

x

x
x

1
1

1
1

0

1

1

0

1

0

1

1

0

0
0
0
1
1
1

0
0
0
1
1
1

if A < B set Oy, reset Ox
MSB first: Start with both flip-flops reset
if A > Band Oy
if A < B and Ox

0
0
0
0
0
0

= 0:
= 0:

o
o

1

1

o

1
1

1

1

Carryn
Carryn+2

CPn

x
1

x
x
1

1

0

set Oy

1

o

A=B
AB

1

Impossible

II

1
1

1

1

1

0

0

1

1
1

0
0

0
0

1
1

A

Ox

CG n

CPn+2

CG n+2

x

1

1

x
x
x

x
x

x

x
x

0

1

1
1

x
x

Ox

B

Higher

Lower
CIN

set Ox

Result in both cases:
Qx
Qy

Inputs
Outputs

0

CLOCK _ _ _ _ _---1

1

0
0
0

x

1-----rD

Oy

Oy
CLOCK _ _ _ _---I

1

Figure 5. Serial Magnitude Comparator

6-25

114105

Conditional Sum Adder
Adds 16 Bits in 33 ns
Application Brief BY MATI KLEIN, HEWLETI·PACKARD
This circuit is based on a 1960 paper by J. Sklansky (see
page 6-22). With careful placement and routing the total
delay can be kept below 33 ns.

subscripts denote the binary position (weight), and superscripts describe the assumed input condition:
0: carrry into this position is assumed inactive
'0: carry into the position one lower is assumed inactive
1: carrry into this position is assumed inactive
'1: carry into the position one lower is assumed inactive

The block diagram below shows each CLB and its inputs
and outputs.
27 of the CLBs each generate one function of up to five
variables, 14 of the CLBs each generate two functions of
four variables. In accordance with the original paper all

This design is available from Xilinx. Call the applications
hot line 408-559-7778 or 1-800-255-7778.

r:::l _ A,B,

CoAoBo ~

CoAoBoA'B'~

~-=~----------1-~~-----------------'

Co A, BoA, B,
A,B,A, B,

A,B,A,B,

AlOBlO AllBll

1988 01

16-Bit Conditional Sum Adder

6-26

Building Latches
Out of Logic
Application Brief
Since the XC3000-series, unlike the XC2000-series, cannot configure its CLB flip-flops into latches, there must be
other ways to design latches. Obviously, the I/O block can
be configured with latches on either the input, the output,
or both. Beyond that, every CLB can form a latch.

can also have two D inputs, each with its own Enable; or
we can have two D inputs, a Select input and an Enable
input; orwecan have an Enable and three D inputs defined
in any arbitrary way. Majority gating could be one way: if
none or one is active, reset the latch; if two or three are
active, setthe latch. Or, if none is active, reset; ifoneortwo
are active, hold; if three are active; set. Or we can assign
positive or negative weights to the D inputs.

The 5-input logic structure permits an amazing diversity of
latch designs; here are several ideas:
With F fed back to close the feedback path, there are four
control inputs left. They might be called Set, Reset, Data
and Enable, defined such that Sand R are independent of
Enable, but D is activated by it. Any of these four inputs
can be defined as active High or active Low. This results
in 16 different latch designs, all with the same basic
characteristics and the same timing.

Since there are 65,536 different functions of four
variables, there are many different ways to define a
latch, not counting pin rotations and active-High/activeLow variations.
All these latches have the same timing characteristics:
propagation delay from input to output = 14/9 ns for the
50/70 MHz part. Set-up time to the end of Enable, or min.

We can also eliminate D and have two Enables, affecting
Sand R (again 16 different flavors) or we use multiple S
and multiple R, either ORed, or ANDed, or XORed. We

D
END

SET
EN SET

SET1
SET2

SET
RESET

RESET
ENRES

RES 1
RES2

D1

D1
D2
SEL
EN

EN D1
D2
END2

II

D1
D2
D3
EN
1142 01A

Figure 1. Latched Logic

6-27

Synchronous Counters,
Fast and Compact
Application Brief BY PETER ALFKE
FULLY SYNCHRONOUS 4-BIT COUNTER USES
ONLY TWO CLBS TO COUNT ANY CODE

FULLY SYNCHRONOUS 5-BIT COUNTER USES
ONLY THREE CLBS

This 4-bit counter operates synchronously and has a
Count Enable (Clock Enable) input. Count length, count
direction, and even the code sequence can be selected
through configuration. There are 15!, i.e. more than 1012
different possible sequences. All four outputs are available. This counter cannot be preset to an arbitrary value,
but it can be cleared by an asynchronous input.

Three XC3000-series CLBs can implement a modified
shift-register counter with the following features:

~~~ ~::
~:~ ~:

ANY SEQUENCE:

• Fully synchronous operation
• Count Enable Asynchronous clear
• Count-Modulus defined during configuration: 2 ... 32
• Only one meaningful output, 0 s, but with complete
freedom to define its waveform

BINARY
GRAY
BCD
X3
X3·GRAY
BIQUINARY
ETC.

00 through 04 form a linear shift register counter. The 5input combinatorial function FO determines the modulus
(there are no illegal or hang-up states). The 5-input
combinatorial function Fl decodes the counter in any
conceivable way,
synchronizes and de-glitches Fl.

as

Examples:

,.430t

Figure 1. Synchronous 4-Blt Counter in 2 ClBs
The advantage of a Gray code is its glitch-less decoding,
since only one bit changes on any code transition. A Gray
counter can also be read "on-the-f1y'~ without the wellknown problems of reading a binary counter e.g., on its
transition between 7 and 8, where any code might be read.
Decimal

Binary

Gray

X3 Binary

X3 Gray

0
1
2
3
4
5

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000

0011
0100
0101
0110
0111
1000
1001
1010
1011
1100

0010
0110
0111
0101
0100
1100
1101
1111
1110
1010

6
7
8
9

10
11
12
13
14
15

+

28 counter with output High at times
T2, 3, Tl0, T22 through T27

+

19 counter with output Low at times
T9, T12, T15, T18.

114401

Figure 2. Synchronous 5-Bit Counter In 3 ClBs

6-28

30 MHz Binary Counter Uses
Less Than One CLB per Bit
Application Brief BY PETERALFKE
The least-significant tri-bit thus stops the remaining
counter chain for seven out of eight incoming clock pulses,
allowing ample time forthe CEO-CET ripple-carry chain to
stabilize. Max clock rate is determined by the first tri-bit's
Clock-to-CEO delay (TcKO + T ILO)' plus the CEP input setup time for all other tri-bits (TICK)' plus the routing delay of
the CEP net. In a-70 device this sum can be below 32 ns.
The higher tri-bits are not speed critical if they propagate
the CET signal in less than eight clock periods, easily
achievable for counters as long as 20 tri-bits, i.e. 60 bits.

Borrowing the concept of Count-Enable Trickle/CountEnable Parallel that was pioneered in the popular 74160
TTL-MSI counter, a fast non-Ioadable synchronous binary
counter of arbitrary length can be implemented efficiently
in the XC3000 series CLBs. For best partitioning into
CLBs, the counter is segmented into a series of tri-bits.
The least significant, i.e. the fastest changing, tri-bit has a
Count-Enable Output (CEO) that is routed to all the CountEnable-Parallel (CEP) inputs of the whole counter.

The two least-significant tri-bits each have a single CE
input; they fit, therefore, in only two CLBs each. The higher
tri-bits have two Count-Enable inputs (CEP and CET) and
require three CLBs.

Each Count-Enable Output from any othertri-bit drives the
next more significant Count-Enable Trickle (CET) input.
The clock causes any tri-bit to increment if all its CountEnable (CE) inputs are active. CEO is active when all three
bits are set and CET is High. CEP does not affect CEO.

ETC

1980 OtA

30-MHz Non-Loadable Binary Counter, Expandable up to 60 Bits

I£%-'"~.-'

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198003A

198002A

All More Significant Tri-Bits Use Three CLBs

First and Second Trl-Bits Use Two CLBs Each

6-29

Up/Down Counter Uses
One CLB per Bit
Application Brief BV PETERALFKE
A fully synchronous resettable but non-Ioadable up/down
counter of arbitrary length can be implemented with only
one XC2000 CLB per bit. This design cascades the toggle
information from the least-significant toward the mostsignificant position. Such an architecture reduces the
maximum clock rate for longer counters, from 30 MHz
for 2 bits, to 10 MHz for 8 bits, down to 5 MHz for 16 bits,
assuming a -70 part. This simple design is, therefore,

not suited for high-speed clocking, but it generates
fully synchronous outputs, i.e., all flip-flops clock on the
same edge.
The better functionality of the XC3000 CLBs can cut the
cascaded toggle-control delay in half by looking at two
counter bits in parallel. This doubles the max frequency for
a given counter size. A 16-bit counter in a -70 part can
count 10 MHz, guaranteed worst case.

COUNT
J--_ _ _---'x"---+-__ ENABLE
COUNT
ENABLE - - - 4 _ - I f - - - - - - l
IN

OUT

D

Q

!--'V.......-t--,

1981 OtA

r-------------------~CEO

CEI -+--r+----.----4-----~-+_~

108t 02A

6-30

Loadable Up/Down Counter
Uses One CLB per Bit
Application Brief BY PETER ALFKE
The 5-input function generator of the XC3000 family CLBs
makes it possible to build expandable fully synchronous
loadable up/down counters of arbitrary length using only
two CLBs per two bits, i.e. one CLB per bit.

two counter bits simultaneously. This cuts the effective
ripple delay in half. A 16-bit counter in a -70 part can count
10 MHz, guaranteed worst case.
The CEP/CET speed enhancement cannot be used on updown counters that might reverse their direction of count in
any position. They can, the.refore, not guarantee a defined
number of clock periods for the ripple-carry chain to
stabilize.

The basic concept is similar to the non-Ioadable up/down
counter described on the previous page. The function
generator driving the counter flip-flop has two additional
inputs (Parallel Enable and Data). The cascaded toggle
control circuit is moved to a separate CLB which serves

CEI--~~-----------------------.

UP/DOWN

---t----t----t-----i

}-+-- CEO

~--------------------------~--------------------------~QB

II
Q

Q

PE----~--~----------------------------~
198201A

6-31

30 MHz Binary Counter with
Synchronous Reset/Preset
Application Brief

BY PETERALFKE

A shorter counter (six bits or less) drives the CEP net from
the 00 output, achieving a 40-MHz speed. A longer
counter generates a 1-in-4 duty cycle on CEP and runs at
30 MHz up to 12 bits long, or at 25 MHz up to 18 bits long
as shown below. To achieve this performance, CEP and
R must be driven by long lines.

In many applications, design modularity is more important
than highest clock speed and best space efficiency. A
counter design is described here that uses identical CLB
primitives, one CLB per bit. The Count-Enable Trickle/
Count-Enable Parallel concept, introduced by the 74160
family, is changed here to a 1-bit block size. Any block
increments only if both Count Enables are High, but the
outgoing Carry (C OUT) is not a function of CEP. The CEP
input thus prevents erroneous counts while the ripple carry
chain is settling.

Figure 3 shows a variation of the circuit in Figure 2, where
the synchronous Reset input (R) is changed to a synchronous Preset (p). Any counter chain can use a mixture of
these two circuits to preset the counter to an arbitrary
predetermined value.

ETC TO 017

RESET--~------+++-----~~-------H~------~r------+~
CLOCK--~------+-~----~~------~~------~~-----+~

0,

00

1983 01

Figure 1. Long Counter (up to 18 bits)

CEP

CEP
....

~:.:-:.:-:-~:-:-:.:.:. :-:-:·:-:-:·:·:.:·:.:-.~:·:-:-:-:·x-:·:·:·:·:·:·:·:·:..:·:·:·:·:·;.:·:.:.:.;.:.:.:.:.:.;.:-:.:.;.:.;.;.:.:.:.:.:-:.;.:.:-:.;.: :.:.:.:.:.:-:.:.:-:.:.:.:.:.:.:.:.:.~~~

COUT

Cw

I

I

COUT

i
:~

P~-------4>---~

CLOCK - - ; j r - - - - - - - - - - - - - - - - - - - - i >

CLOCK~r--------------------I>

Q

Q
1983 03

198302

Figure 2. CLB Primitive with Reset, One per Bit

Figure 3. CLB Primitive with Preset, One per Bit

6-32

Fast Bidirectional Counters
for Robotics
Application Brief
The position of a robotics arm is usually determined by
three shaft encoders consisting of up/down pulse generators and counters. At a maximum speed of 5 meters per
second and a resolution of 1 micron, these counters must
resolve 0.2-J.IS pulses and should have a capacity of at
least 2 million steps. The counters must have an easy
interface to the microprocessor so thatthe count value can
be read on-the-fly, without ambiguity.

BY PETERALFKE

Communication between these two parts of the counter is
through a carefully controlled mailbox. Whenever the 4-bit
up/down counter reaches plus or minus 8, it sets a carry or
a borrow flip-flop. The shift register counter accepts these
inputs synchronously, with a max delay of 1 J.IS.
When the microprocessor wants to read the counter, it first
disables the interaction between the two parts of the
counter. Then both parts are transferred into 24 output
registers and the counter interaction is enabled again.
This mechanism insures reliable read-out, even if the
counter is oscillating around certain critical values.

The established microprocessor peripheral counters have
severe limitations. They are too short, lack up/down control or quadrature clock inputs, and cannot be read easily.
Now Xilinx suggests a design that packs three 22-bit
counters into one LCA, the XC3020. Max count rate is
8 MHz, and the count values can easily be read on-the-fly.
The counter architecture is somewhat unconventional.
Each counter consists of two parts:

The problem of a traditional up/down counter is that it can
oscillate between two values where all (or most) counter
bits change at the incoming count rate. This makes a reliable microprocessor interface virtually impossible.
In this deSign, the most significant 20 bits of the counter do
not have this problem, and the least-significant four bits
count in a Grey code, where only one bit changes on any
clock transition. Such counters can safely be read on-thefly. This safe and compact design puts one additional
burden on the microprocessor: The two parts of the
counter must be added in software, since they have independent signs.

1. A conventional up/down 4-bit Grey-code counter with a
capacity from -8 to +7. This counter is asynchronous to
the system clock, affected only by the incoming clocks.
2. A 20-bit up/down counter in the form of a 20-bit recirculating shift register, a serial adderlsubtractor, and a
carry/borrow flip-flop. This shift register forms the most
significant part of the counter. Synchronous with the
LCA clock, it is easily synchronized to the microprocessor clock. At a 20-MHz clock rate, it recirculates once
and can be incremented, decremented, and also read
or preset, once per microsecond.

Speed can be increased to 20 MHz by changing the partitioning from 4/20 bits to 8/16 bits. The up/down count control can be implemented in several different ways.

II

HANDSHAKE
ADDRESS
1984019

Figure 1. Triple 22-Blt Up/Down Counter with Microprocessor Interface

6-33

40 MHz Presettable Counter
Application Brief
A new counter architecture, described here, is used to
implement a very high speed presettable, up-to-40-bit long
binary counter in an XC3020 LCA devices. The design can
easily be modified to implement two 20-bit counters or the
equivalent BCD counters.

CARRY PROPAGATION

Since a presettable counter only decodes one state, TC,
the decision to toggle any of the more-significant bits can
be delayed and thus pipe lined without any problem.
The counter is divided into a number of small sections,
each two bits (a di-bit) long, implemented as a synchronous presettable down-counter, with carry-in (=count enable), parallel enable and two data inputs. Terminal count
(0.0) is decoded with an additional input coming from the
next higher section. The least-significant section decodes
the state priorto TC; its output activates the parallel enable
for all counters. The carry function between sections is
pipelined. The carry flip-flop is set when carry-in is active
and the di-bit is in state 00. The carry flip-flop stays set for
only one clock period; its output drives the carry-in function
of the next higher section. As a result of this pipelining, the
counter can be made arbitrarily long without any speed
penalty. Note that each di-bit, except the first, makes its
transition n clock pulses later than required by the binary
code sequence (n is the relative position of the di-bit, n=O
for the input di-bit). This code violation has no impact on
TC decoding. This counter can be four times faster than
presently available standard microprocessor peripherals
like the 8254 and 9513. Typical applications are in
instrumentation and communications, for example, as the
frequency-determining counter in a phase-locked-loop
frequency synthesizer.

Traditional counter designs always represent a compromise between two conflicting goals: highest clock speed!
event resolution on one hand, sophisticated features (like
preset to any arbitrary value, or decode any state) on the
other hand.
Asynchronous ripple counters offer highest speed, but
cannot be decoded in one clock period, thus cannot be
made programmable.
Synchronous counters permit decoding and presetting in
one clock period, but pay for this with complex carry logic.
Carry propagation is always the limiting factor in the
traditional design of presettable synchronous counters,
since the complete carry chain must reach a steady state
before the next incoming clock edge. Brute force parallel
decoding of all previous states becomes unmanageable
beyond eight stages, but cascaded decoding introduces
additional delays. Either approach reduces the inherent
resolution of the counter.
Decoding Terminal Count (TC) to presetthe counter again
poses a similar problem. The design described here
separates the two functions of the carry chain as follows:

SUMMARY

• One propagates the carry signal from the less-significant to the more-significant bit positions, and causes the
appropriate flip-flop to toggle.
• One cascades the decoding of the terminal count of the
whole counter and generates a Parallel Enable signal

Unlike the speed of conventional synchronous counters,
the speed of this design is independent of its length. All
speed-critical paths are single level; their interconnect
delay can be kept below 9 ns, which means that even a
-70 device can count at a 40-MHz rate (worst case).

CASCADED TC DECODING

MSB

The TC decoder must receive inputs from all counter bits,
but only the LSB timing is critical; the more-significant bits
have been stable for many clock periods. TC can, therefore, be decoded in a slow gating chain that starts at the
most-significant end of the counter.

PE

c~~

;r II

40 BITS

~

TC

BY PETER ALFKE AND PERRY WU

LSB

4--

"=2

o 4)
0:0'0)

"=1
00

"=0
1
1
00 •.• .• .•. ~ • •. • 01
01
"

!~~"'"

1145 01

6-34

1145 02

E:XILINX
CI-4r---------------------------~~--~--------------------------------+_~

o,H-t~~[)

PE-----.p--J

o

CO

CARRY

I

Do------------LJ

,,--=-=__=
___=_=,,==,__=,_=«_=__==1========'='-=-:j~I'E~~8:::===:ro

n

o

CI- CARRY IN
CO_ CARRY OUT
PE _ PARALLa ENABLE (ACTIVE LOW)
TI_ TERMINAL COUNT IN
TO - TERMINAL COUNT OUT

TERM.
COUNT

1145048

Any Ol·blt Except the least Significant

f~~~~~~---'~-'---~~--~--

I

l

I'E----.,....J

0 0 1-----.1---+----<1/

Do.-----------LJ

0,

0

0,------,__"

t~--"J

l
'~~~-'~'~~~="'·=·--''''=~-~-l

'-...J-----t-------------TI

PE~ro~A~~~OI~~~~~----------------------------------------------------~~--------~-------------,

o

CE _ CLOCK ENABLE

TEAM.

I

COUNT

PRaET-------____________

~

________________________________________

RO

~---------------------+-----J

~-~~.~-

1145 05B

least Significant Ol·blt

II

PRESET
STARTtS'i'OP
HIGH
LEAST SIGNIFICANT Ol-BIT

MOST SIGNIFICANT Ol-BIT
1145 03A

Synchronous PreseHable Counter -- 40 Bits In 60 ClBs

6-35

40 MHz Presettable Counter
Since this circuit was first published in mid 1988, several
designers have used it to create fast counters.
What is the function of the TC pipeline flip-flop,
formerly called Q3?

In the unlikely case where this might cause a problem,
most TC pipeline flip-flops can be eliminated. They were
inserted to simplify modeling and because they are
available for free.
Why is the least significant dl-bit different?

The unconventional idea behind this counter design is that
Terminal Count decoding can be "rippled" from the MSB to
the LSB, i.e. against the direction of carries. This is
possible because the high order bits reached their TC long
before the LSB does.
There is, however, a potential problem when the counter
is being preset to a value with a string of LSB zeros. Let's
assume the worst case where the preset value is all zeros
except a single one in the MSB position:
When this counter reaches the all-zero Terminal Count,
PE is activated and the counter is preset. --This action
should obviously de-activate the TC decoding, but in the
given example a simple ripple decoder would have a very
long delay. It might take 400 ns for the MSB =1 condition
to ripple down through a 40-bit decoding chain. Such a
delay would defeat the concept ofthe counter, reducing its
max clock rate to 2.5 MHz. A better way must be found to
de-activate TC within 25 ns.

To achieve a 40-MHz clock rate, the PE signal must be
made as fast as possible. It has to come directly from a flipflop output so that the sum of clock-to-output delay, routing
delay, and input set-up time is kept below 25 ns.
The position of the LSB TC pipeline flip-flop is, therefore,
changed, so that it detects the TC-1 state (in a downcounter, that is state 1).
The flip-flop output is made active Low PE so that the
asynchronous clear input can be used to force the counter
into loading.
For operation below 30 MHz the least significant di-bit can
be like all the other dibits, but PE must be excluded from
the AND gate generating PE, and the user may want to
adjust the polarity of the last TC pipeline flip-flop to
facilitate the preset function mentioned above.
, Where should this design be used?

The TC pipeline flip-flop and the inclusion of PE in the AN D
gate that detects TC, reliably de-activate TC and thus PE
one clock after they have been activated. This has one
side effect, however: It makes it illegal to preset the counter
to very small numbers (less than 10 for a 20-bit counter),
since the TC-pipeline takes that many clock pulses to
become active again.

This counter design achieves high performance by using
several logic "tricks". It generates incorrect outputs when
undigested carries sit in the carry flip-flops. That makes
this design useless for any parallel application like DMA
counters.
For the intended application, timebase counters or
frequency synthesizers, this design offers the highest
possible count speed.

ASYNCHRONOUS PRESET IN XC3000 CLBS
The XC3000 CLB lacks the asynchronous preset capability available in the XC2GOO CLB. Some designers are
looking for this feature. Here are several solutions:

3. If the circuit really needs asynchronous preset and
clear (or asynchronous data transfer) in a flip-flop, the
problem must be solved on a system level.

1. If asynchronous preset is needed, but no asynchronous clear:

The design can usually be transformed into a synchronous solution where all flip-flop changes occur as a result
of the same clock edge.

Tum the flip-flop upside down, i.e. invert the D input
and the a output and consider the asynchronous clear
a preset. These inversions of D and a come for free
in a Xilinx LCA. Note that the flip-flop will now come out
of configuration in the apparent preset state.

Truly asynchronous parallel data transfer into several
clocked flip-flops simultaneously is inherently unreliable
and must be avoided. If, however, the transfer pulse is
synchronized with the clock, it should not be too difficult to
change the design to utilize the clock for loading.

2. If the circuit needs both asynchronous preset and
clear, chances are that the function can be performed
by a latch. The XC3000 CLB can implement complex
latches in its function generators (see page 6-27).

Asynchronous data transfer was popular in early TTL MSI
circuits designed in the late sixties, e.g., the 7494 and
7496. It is time to get away from the limitations of the past.

6-36

Frequency/Phase
Comparator for
Phase-Locked-Loops
Application Brief BY PETER ALFKE
A Phase-Locked-Loop (PLL) manipulates a local voltagecontrolled oscillator (VCO) so that it is in phase with a
reference signal. One popular application is a programmable frequency synthesizer for radio communications.
Here a crystal oscillator is divided down to a low reference
frequency of 5 kHz, for example.

not only to pull in a small phase error, but also to correct a
large frequency error. It may not generate false outputs
when the input is at a multiple or fraction of the desired
frequency. The well-known circuit shown in Figure 1
performs this function. It generates "pump-up" pulse when
the VCO frequency is too low, "pump-down" when its too
high. The multiple feedback network assures proper
operation even at large frequency errors.

A programmable divider scales the VCO frequency down
to the same reference frequency. The two counter outputs
are compared to generate a signal that, when required,
modifies the VCO frequency up or down until the two
comparator inputs are not only of the same frequency, but
also in phase.

Figure 2 shows this circuit implemented in two CLBs plus
two lOBs, directly driving the integrator (low pass filter)
controlling the VCO. The LCA solution has been
breadboarded at 10 MHz. It achieved a phase error of less
than 2 ns.

This frequency/phase comparator must have a wide
capture range, i.e. it must generate the appropriate output,

FROMVCO
DIVIDED BVN

FROM

DIVI~g+--t-j--~
BYN

~:........£~~JN""""""""~"~"""~""""~""''''''..............:......................................................J
FROM
REFERENCE
FREQUENCY

II
1985011\

Figure 1. Digital Frequency/Phase Detector
FROM

REFERENCE
FREQUENCY

+--+t--....I
~:

!L.:.:.~2.k!.:~»~:«*:-.....

I

:-:.;.x.:-.»:...;.»»}»;.:...:.»:.;.;.;.:....:.;.;.;.:.:-»;.:.:.;.;.........:.:.:-:..M

Tovca
+2.5V
INTEGRATOR
1985 02A

Figure 2. Frequency/Phase Detector Using Four Blocks

6-37

Gigahertz
Presettable Counter
Application Brief
Some frequency synthesizers for communications, e.g.,
cellular telephone networks, require a clock frequency of
hundreds of megahertz, up to a gigahertz. Obviously, the
LCA cannot operate quite that fast, but with the help of a
2-modulus prescaler, the LCA can implement a fully presettable ultra-fast counter, resolving time in increments of
one clock period, as small as 1 ns at 1 GHz.

BY PETER ALFKE

smart but slow counter (in the LCA) to achieve the performance of a fast and smart, fully presettable counter.
The prescaler divides by either n or n + 1, depending on
the state of the control input. In other words, it "swallows"
one additional clock pulse if told so by the control input. By
keeping the control input active forthe appropriate number
of prescaler output periods, the LCA can fine tune the total
divide ratio to any integer number.

Prescaling is the obvious method to adapt a slow device to
a high clock rate. Simple pre scaling by a fixed number,
e.g. 8,16, or64, however, reduces not only the clock rate,
but also the resolution. If, for example, the GHz clock of a
phase-locked-loop synthesizer is first divided by 64, then
the whole presettable counter is clocked at this lower rate.
For a 25 kHz channel spacing, the PLL must, therefore,
operate at 25 kHz + 64, i.e. less than 400 Hz. This results
in slow response and might produce excessive phase
jitter.

Well, there are some impossible numbers:
When the prescaler divides by either n or n + 1, then the
system cannot divide by certain numbers below n (n-1).
An 8/9 prescaler has blind spots below 56
A 64/65 prescaler has blind spots below 4,032
A 128/129 prescaler has blind spots below 16,256
This limitation is usually of no practical consequence in a
real design.

A "Pulse Swallowing" 2-modulus prescaler, originally described in 1970 by John Nichols of Fairchild Semiconductor Applications, avoids this drawback. Pulse swallowing
combines a fast but dumb counter (the prescaler) with a

The prescaler-LCA combination can divide by any integer
number higher than the values above.

INPUT

OUTPUT
0.280 ~s
0.285 ~s

200 MHz

0.290 ~s

200-MHz Counter
200 MHz clock, l2-bit
presettable time base generator
achieves 5 ns output resolution.

20.475
20.480

INPUT
450 TO

~s
~s

OUTPUT
TO 25 kHz
PHASE·LOCKED·
LOOP

1000 MHz

Gigahertz Counter
450 to 1000 MHz clock, l6-bit
presettable counter achieves
25 kHz channel spacing with a
25 kHz phase comparator frequency.

198803A

6-38

I:XilJNX

o

ori--------------------------------- TC • PE

TC

00

°2

PE
01

CLBn

°1

PE
198802
198801

3·Blt Presettable Down Counter with
Pipelined Terminal Count, Locking Up on TC

9·Blt Presettable Down Counter with
Decoded Terminal Count (TC)

6-39

II

75 MHz Presettable Counter
or Programmable Delay
Product Brief BY PETER ALFKE
__

___

~_«~

FEATURES

I

The +8/9 prescaler described on page 6-42 can also be
implemented inside an LCA. The nighest clock frequency
for a -100 part is 75 MHz, i.e. the output delay can be
programmed with a granularity of 13 ns. The +8/9
prescaler consists of a +2/3 counter followed by a +4
counter with one decoded state. Each of these counters
fits into a single CLB. The +2/3 counter divides by 2 unless
the 3-input AND is true, in which case it divides by 3. When
the DIV9 input is Low,the two counters together divide by
2+2+2+2=8. When the DIV9 input is High, the two
counters divide by 2+2+2+3=9. See page 2-42/43 for a
more detailed description of such a pulse-swallowing
counter.

JJ-;=D-D

=L)-D
j

l

To
ENABLE
CLOCK

a U.B

I>
,.. ,

DIV9

QilililliiililiiiiQiili;·i"i~"«",;

+3'

~
D

DIN

---InL-______

I

a~

I>

~D

Os _ _ _ _

a

aD

CLOCK
OUT
(RISING
EDGE)

I>

L-

+4COUNTER

'--_-!r

~I.--- +9 ---~.I+.- - - +8

aA

+ 213 COUNTER

a A ENABLE CLOCK

I

1

+3

A conventional 24-bit presettable counterwould be limited
to a clock rate of 13 MHz. This pulse-swallowing design is
six times faster.

00 J

a

I>

This design demonstrates the high performance possible
with Xilinx LCAs when the user is willing to optimize the
system design to fit the available logic. The high clock
resolution of 75 M Hz is partly due to a system '1rick" (pulseswallowing), partly due to the inherent flexibility, and high
speed of the CLB function generators.

Oc~

~._Q_.H.M

.1

Divide by Pulse-Swallowing Prescaler

X119S

X1194

DIV9
PARALLEL ENABLE

21·BIT
COUNTER

CLOCK
75 MHz

+81+9

TERMINAL
COUNT

X1196

24-Blt Frequency Division with Pulse-Swallowing Prescaler

6-40

Serial Pattern Detectors
Application Brief BY PETERALFKE
ously shifted-in pattern, using only one XC3000-seriesCLB per pattern bit. The output of the comparators are
ANDed with 3-state buffers on a long line. The desired pattern is first shifted through the DIN input into the Y-flip-flop,
and then routed to the DIN input of the next CLB.

FIXED PATTERN DETECTOR
This circuit compares a serial bit-stream against a predetermined (configured) pattem. Two bits are compared in
each XC3000-series CLB. The outputs of the comparator
are ANDed in with 3-state buffers on a long line.

When the complete pattern has been shifted in, it is transferred with one clock pulse to the X-flip-flops, using the
lower half of the function generator. Data to be detected is
then shifted inthroughthe DIN input into the Y-flip-f1op, and
from there to the DIN inputofthe next CLB. The upper half
of the function generator compares the content of Ox and
Oy, and indicates a match on the CLB output. For identity
comparison, these outputs are ANDed through 3-state
buffers driving a long line.

Data is shifted through DIN into the Y-flip-flop, then shifted
through the upper hail of the combinatorial array into the
X-flip-flop of the same CLB. From there it is routed to the
DIN input of the next CLB.
The lower hail of the combinatorial array compares the
content of the two flip-flops against data supplied on the A
and D inputs. A match is indicated on the G output and
routed to a 3-state buffer driving a long line.

This circuit can also be used as a correlator, in which case
the outputs must be summed in a Wallace-type adder.

DYNAMIC PATTERN DETECTOR OR CORRELATOR
This circuit compares a serial bit stream against a previ-

r"'. . . . . '. . . .
··~

y,... "'1

..v.........y,..................

Y,..'NhY-'N~·VA"NNo"NU>."""""V.-=y.....

j

~---.

LONG
LINE

1

~ ax

}

~

Qy

}

LONG
UNE

,}

II

~

[

~
~

l. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '. . . . . .;:

DIN

DIN
114702

114701

Figure 2. Serial Comparator Finds Pattern Match or
Correlates Patterns

Figure 1. Fixed Pattern Detector

6-41

Serial Code Conversion
Binary to BCD
Application Brief BY PETERALFKE
CONVERT/S"Hi"F't

Q'

3

114603

Figure 1, Binary to BCD (MSB First)

The LCA architecture with its powerful function generators
evenly interspersed between flip-flops lends itself very
well to serial code conversion, where data is shifted into a
register in one format, and shifted out of the same register
in a converted format.

CONVERT -+.-----;:::00--1
0,

MODIFY

°2
°3

A binary-to-BCD converter requires three CLBs for every
four bits of BCD output i.e" for every digit. Data is shifted
in serially, most significant bit first. Each shift thus doubles
the content of the register,

1----10

To remain a valid BCD number, a 4-bit number of 5 or
greater must not just be shifted, but must be converted into
the proper BCD representation of its doubled value: A one
is shifted into the next higher decade and the 5 isconverted
into a 0, a 6 into a 2, a 7 into a 4, an 8 into a 6, a 9 into an
8, When the binary LSB has been shifted in, BCD data is
available in parallel form, or it can be shifted out serially
with the conversion logic disabled.

°3

1----10

MODIFY: 5 - - 0,6-- 2, 7 _ _ 4, 8 _ _ 6, 9 - - 8
SHIFT

MODIFY

0 2 - 0 3 - 0 0 '03
O,-02-00XNORO,

° _°,-°
0

0

0'3-°3-°3
X1246

114601A

Figure 2. Binary to BCD converter. Three CLBs
per Four Bits (MSB First)

6-42

Serial Code Conversion
BCD to Binary
Application Brief

BY PETERALFKE

CONVERT/SHIFT

o·

o

1146 04

Figure 1. BCD to Binary (lSB First)

.t

The LCA architecture with its powerful function generators
evenly interspersed between flip-flops lends itself very
well to serial code conversion, where data is shifted into a
register in one format, and shifted out of the same register
in a converted format.

r"-

A BCD-to-binary converter requires three CLBs per digit.
BCD data is shifted in, least significant bit first. Once the
complete BCD word has been shifted in, the conversion
process begins, shifting out binary data, LSB first.

MODIFY

"-0
r-

["r0,--<
°2--<

,---<

"-

J;---4'-0, ....
°2 ....

5,2_6,4_7,6_8,8_9

'----

0 , - °0

r0

0,-<

This design can be made smaller and faster by starting the
conversion before the most significant BCD digit is being
shifted in. Since these converters can be laid out with very
short interconnect delays, they can operate at up to 60%
of the specified toggle frequency, I.e. 42 MHz for the -70
parts.

SHIFT

~

r-

CONVERT

Each shift divides the content by two. When the LSB of a
BCD digit is a one, shifting it one position down would give
it a weight of 8 in the lower decade instead of the weight of
5 appropriate for a 10 divided by 2. A value of 3 is therefore
subtracted from the content of the decade whenever a one
is being shifted into it.

MODIFY: 0 -

~U

r-

O'r--

-

~U

-

~U
~

MODIFY

-0,

-:J

° 2 _ ° , - ° , XOR0 2
° 3 - ° 2 - 0 3 AND(O,OR0 2 )
0 ' 0 - 0 3 - 0 3 OR(O,' 02)

114602A
X1247

Figure 2. BCD to Binary converter. Three ClBs
per Four Bits (lSB First)

6-43

II

"Corner Bender" or
8-Bit Format Converter
Application Brief BY PETERALFKE
Pulse Code Modulation (PCM) has become the dominating encoding method in digital telephony. Analog signals
are sampled at 8 kHz and represented by their 8-bit digital
equivalent, using a logarithmic encoding scheme, ~-Iaw in
the US and Japan, A-Law in the rest of the world using the
CCITT standard.

INS

..1

XC2064

ll>.S

OR

S

1/2 XC3020

These eight bits are usually transmitted serially (the T1
standard time-multiplexes 24 channels on a single wire at
1.544 MHz. The CCITT standard time-multiplexes 32
channels at 2.048 MHz.
In the central office or PBX, however, the eight bits
representing one particular sample must be routed
together. The telephone system thus uses a large number
of serial-to-parallel and parallel-to-serial converters, all
operating on 8-bit words, all running synchronously. Eight
S-P converters with eight data inputs and eight data
outputs can easily be combined in one package. Eight
serial data streams are shifted in simultaneously. After
eight clock pulses the eight serial words can be shifted out
in parallel, one word per clock pulse, and new serial bits
can be shifted in simultaneously. It is interesting to note
that the same circuit can also accept parallel words and
shift them out in eight serial streams. The difference
between S-P and PO'S is not in the circuit, but in the mind
of the beholder.

OUT

112203

New serial data can be shifted in from one side, while old
parallel data is being shifted out at the opposite side.
There is no need for any of the additional flip-flops required
by the older designs.
After eight clock pulses, the mode control is again changed
to A and old data is shifted out on the right side while new
data is shifted in from the left.
This design uses only 64 flip-flops, and a mode-control
signal derived from a divide-by-8 counter. The physical
routing of the input signals can be done on-Chip, but the
eight bottom output pins can be externally combined with
the eight right-hand outputs in a wired OR.

Such a "Corner Bender" is available as a standard part, the
Plessey MJ 1410 8-Bit Format Converter. Its drawbacks
are high power consumption (max 500 mW) and slow
speed (2.4 MHz guaranteed worst case), a result of its
NMOS heritage.

The design fits exactly into one XC2064 or into half of an
XC3020 and can run at up to 50 MHz.

The LCA implementation of a 2-dimensional shift register
is straightforward:
A common clock drives all flip-flops, organized in an 8 x 8
array. In mode A, each flip-flop receives data from its "left"
neighbor; in mode B, each flip-flop receives data from its
neighbor above.
For the first eight clock pulses, the array is in mode A,
receiving eight bit streams and right-shifting them into the
array. Forthe next eight clock pulses, the array is in mode
B, down-shifting the previously received 64 bits.

PHASE A

PHASEB
1122 02

6-44

100 MHz Frequency Counter
Application Brief BY PETER ALFKE AND NICK CAMILLERI
The high resolution of 100 MHz or 10ns is achieved by
using the divide-by-two flip flop driven by the alternate
clock buffer. This is the simplest and therefore fastest flipflop on the device.

The block diagram below describes a complete 100-MHz
frequency counter in an XC3020 PC84.
A 32,768-kHz crystal oscillator generates a time base of
two seconds. The frequency to be measured clocks an 8digit BCD counter. At the end of the measuring period of
two seconds the counter content is transferred into four
shift registers, and the counter is then reset before the
beginning of the next measuring period. The shift register
drives a 7-segment encoderthatfeeds into the LCD driving
logic, which in turn drives seven 8-bit shift registers nestled
in the lOBs.

The whole frequency counter uses 60 of the 64 CLBs in an
XC3020:
Time Base
BCD Counter
4 Shift Registers
7-Segment Encoder
Leading Zero Suppressor
Control
Segment Conversion/
LCD Driving Logic
Special Clock Generation
Miscellaneous

The oscillator uses three lOBs, since the dedicated crystal
oscillator input is already used as signal input.
The time base is generated by a 16-bit-binary counter
consisting of four asynchronously cascaded 4-bit synchronous counters. The control unit eliminates the clock ripple
delay by re-synchronizing the time base output. The eight
counter decades are cascaded asynchronously, each
decade consisting of a synchronous BCD counter.

8 CLBs
16 CLBs
16 CLBs
4 CLBs
2 CLBs
2 CLBs
4 CLBs
6 CLBs
2 CLBs

This design is available from Xilinx. Call the applications
hot line 408-559-7778 or 1-800-255-7778.

XC3020

fin
(0 ... 100 MHz)

BDIGIT
LCD
DISPLAY

LCD
DRIVING
LOGIC

P-I-_~_~~_T'~_E~-l~
~
B·BITSR
FDR'F"

I------j

Figure 1. Block Diagram

6-45

~

}

112901B

Megabit FIFO in Two Chips:
One LCA and One DRAM
App licatio n Bri ef BY PETER AlFKE AND NICK CAMillERI
A bit-serial FIFO buffer is a general-purpose tool to relieve
system bottlenecks, e.g., in LANs, in communications, and
in the interface between computers and peripherals.
Small FIFOs are usually designed as asynchronous shift
registers, but a larger FIFO with more than 256 locations
is better implemented as a controller plus a two-port RAM,
or as a controller plus a single-port RAM, either SRAM or
DRAM.

This FIFO DRAM controller consists of:

SRAMs are fast and easy to use, but at least four times
more expensive than DRAMs of equivalent size. Dynamic
RAMs offer low-cost data storage, but require complex
timing and address multiplexing, which makes them unattractive in small designs. For FIFOs with more than 256K
capacity, a DRAM offers the lowest cost solution, if the
controller can be implemented in a compact and costeffective way. An XC3020 Logic Cell Array can easily
perform all the control and addressing functions with many
gates left over for additional features.

• A 4-to-1, 1O-bit address multiplexer

DIN
IClK
DOUT
OClK

I/O
BUFFER

• An inpuVoutput buffer with synchronizing logic
• A 20-bit Write pointer (counter)
• A 20-bit Read pOinter (counter)
• A 20-bit full/empty comparator

• Control and arbitration logic
The Write pointer defines the memory location where the
incoming data is being written, the Read pointer defines
the memory location where the next data can be read. The
identity comparator signals when the FIFO is full or empty.

..

n"

Q

7

D

RDRB
(Read Ready/Busy)
WRRB
(Write ReadylBusy)
FUll
EMPTY

CONTROL
DRAM

10
MUX

WRE

AO-9

RDE

3

7~

Figure 1. Megabit FIFO Controller in an XC3020

6-46

R7iS

.~

wr

j
1130 01A

)D--\

When the Write and Read pointers become identical as a
result of a Write operation, the FIFO is full, and further
Write operation must be prevented until data has been
Read out. When the two pointers become identical as a
result of a Read operation, the FIFO is empty and further
Read operation must be prevented until new data has
been written in. With a single-port RAM, Read and Write
operations must be inherently sequential, and there is no
danger of confusing the full and empty state, a problem
that has plagued some two-port designs.

=

+--1

SHIFT-REGISTER-COUNTER

COMPARATOR

1130 02

Figure 2. Shlft-Reglster-Counter and Free Row-Column

MUX

A straightforward design would use synchronous binary
counters for the two pointers, but it is far more efficient to
use linear shift-register (LSR) counters. Such counters
require far less logic and are faster since they avoid the
carry propagation problems of binary counters. LSR
counters have two peculiarities: they count in a pseudorandom sequence and they usually skip one state, Le., a
20-bit LSR counter repeats after 22°_1 clock pulses. In a
FIFO Contro"er,both these features are irrelevant, the
address sequence is arbitrary, provided both counter
sequence identically.

takes advantage of the DRAM internal refresh counter by
using CAS-before-RAS refresh/address strobes.
Both 20-bit pointers, plus their 20-bit identity comparator,
plus the Row/Column multiplexer thus fit into only
20 CLBs; refresh timer and address multiplexer use another 10 CLBs and the data buffer plus control and arbitration logic take another 23 CLBs, for a total of 53 CLBs, an
easy fit in an XC3020.

This design fits two shift register counter bits in one
XC3000-series CLB and the identity comparator uses the
combinatorial portion of the same CLB.

This design can easily be modified for 256K DRAMs.
Other variations are: multiple para"el bits, e.g., bytepara"el operation, interrupt-driven control, multiplexed
data for multiple para"el-bit storage,and byte para"el
storage with bit-serial 110. The latter case requires special
attention when the FIFO is emptied after a non-integer
number of bytes had been entered, requiring direct communication between the input Serial-to-Para"el converter and the output PIS converter.

The RAS/CAS multiplexing of the 20-bit address is performed without any logic by tapping every other bit of the
shift register counter and using the 10 outputs before the
incrementing shift as Row address, after the incrementing
shift as Column address. (The Column address of any
position is thus identical with the Row address of the
following pOSition, but since the binary sequence of a shift
register counter is pseudo-random anyhOW, this is no
problem. It's an elegant and efficient trick).

This applications brief shows that the XC3020 can be
programmed to control one or a few DRAMs as a large
FIFO of up to a megabyte, with data rates up to 16 Mbps
serially or 2 Mbytes per second byte-para"el.

The FIFO controller permits the user to perform totally
asynchronous Read and Write operations, while it synchronizes communication with the DRAM. The design

This design is available from Xilinx. Call the applications
hot line 408-559-7778 or 1-800-255-7778 .

•

v···········w.w.·.·.•.·.....·.·.........·.·.·.·.w.....·...................w ••••••••••.•••••••••.••••••••• v1;;;-r-:;::::=========t4;+:=~~~ESS
WRITE
ADDRESS

COMPARE

r-~~~-+~~~~
BfTS

DIN

DIN

READ ADDRESS

WRITE ADDRESS

Figure 3. 2-Bit Slice of Two Counters and Comparator In Two CLBs

6-47

1130 03

State Machines
Application Brief

BY PETER AlFKE

SIMPLE STATE MACHINE RUNS AT 30 MHz

State-machine design is a methodology that defines the
contents of all flip-flops for any possible state of the design,
then defines all possible paths that can cause the design
to go from one state to another. In its simplest form this is
just a rigorous way of designing synchronous logic, like
4-bit counters. For complex designs, the state-machine
approach gives the designer a tool to investigate all
possible operating conditions and avoid overlooked hangup states or undesired transitions. LeA devices with their
abundance of flip-flops lend themselves well to statemachine designs.

This simple state machine uses only 11 CLBs. It has up to
16 states, and eight outputs, each decoding/encoding any
combination of states. It performs a 2-way branch from
any state to anyone of two freely assigned states,
(possibly including the present state) determined by
control input C. (AVOid the branch by making both
destination states equal).
This design can also perform an 8-way branch from any
state so programmed to either one of two selected
quadrants (0 .. 3, 4... 7, 8 ... 11 or 12... 15). Control inputs A,B
then determine the location within the quadrant.

SIMPLE, FAST STATE MACHINES
Using the 5-input function generator of the XC3000-70
family devices as a 32 bit ROM, a state machine with up to
32 states without any conditional jumps uses only 5 CLBs
and operates at up to 50 MHz.

Examples:
• From state@, if C=High, go to

® else go to ®

From state (]), if C=High, go to@else stay in (])

®
®, execute the truth-table below

• From state ®, unconditionally go to
The five registered CLB outputs drive the five function
generator inputs of the 5 CLBs in parallel. This implements
a fully programmable sequencer similar to the synchronous counter shown in the left column of page 6-28.

• From state

AB

~

~

10

For a smaller number of states, some inputs can be used
as conditional jump inputs. Encoding these condition
codes may require an additional level of logic which
reduces the maximum clock rate to 30 MHz.

C=High

C=Low

00

13

01

@

11

@

®
®

ACTIVE 4-WAY BRANCH

6ClBs
WITH

COMMON
INPUTS

4 CLBs
WITH

COMMON

8

INPUTS

1986 01

30-MHz State Machine, 16 States, 2-Way/S-Way Branch, S Outputs

6-48

Complex State Machine
in One LCA
Application Brief
Simple and fast state machines can easily be implemented
in an LCA, as shown on the previous page. This page
shows how an external EPROM can be the source of the
next address in a complex state machine. This look-up
table can easily be hidden in the EPROM required to store
the LCA configuration data.

BY PETER ALFKE

128 arbitrarily defined next states, controlled by the 7-bit
condition code.
This basic design uses no CLBs in the LCA, just lOBs; but
it allows a number of states and a mUlti-way branch
complexity far in excess of any normal need. The user will
usually reduce the mUlti-way branch complexity by
assigning identical values to many of the 128 possible next
states.

Assume that an XC3020 is configured in the Master
Parallel mode, where it reads its configuration data out of
a 256K (32K x 8) EPROM, starting at the top address
location 7FFF (32K) through 77FF (about 30K). The remaining 94% of the EPROM can be used as a next-state
look-up table with a capacity of 240 states.

The user has the logic resources of the LCA available to
add features like:
•
•
•
•

The state address is read out of the EPROM, then manipulated (decoded, encoded, etc.) in the XC3020 LCA. The
result is combined with incoming-control information to
generate a new EPROM address. The EPROM can be
considered as having 240 locations, each 128 bytes wide.
Each byte is a potential next-state value, only one of which
will be chosen by the 7-bit condition code.

State decoding/encoding
Stack registers
Loop counters
More sophisticated branch logic, etc.

This design is straightforward, inexpensive, compact and
very flexible. Its speed is limited by the EPROM access
time, which can be less than 100 ns. For higher speedat a higher cost-the EPROM can be shadowed by fast
SRAMS.

In the simplest case, the EPROM output data is just
latched in the LCA and is fed back as the most-significant
part of the new EPROM address. Since the top 16 address
locations are used for configuration data, the state codes
are limited to 240 different values, 0 ... 239.

STATE
OUTPUTS

The seven control inputs form the seven least-significant
EPROM address bits. For reliable operation with asynchronous control inputs, they must be synchronized in an
input register.

CONDITION

CODES
198701

III

This rudimentary state machine can thus have 240
different states, and can jump from any state to anyone of

6-49

PS/2 Micro Channel Interface
Application Brief
IBM's general-purpose microcomputer, the Personal
System 2, is available in several models, from the low-end
Model 25 to the high-end Model 80. These thirdgeneration PCs have several innovative features,
including 3-1/2 inch floppy-disk drives, high-resolution
VGA graphics, and a 20-MHz 80386 processor as
the main engine for the Model 80. Among the
most interesting features is the Micro Channel interface,
the bus specification for the interface between the
system and adapter cards. The Micro Channel's
streamlined characteristics and flexibility provide PS/2
designers and users with many advantages over previous
PC architectures.

BY ROB STRANSKY

bus adapter cards. Defined with System Configuration
Utilities, an add-on card's addressing and other optional
configuration data are established and stored in CMOS
battery-backed memory on the main board. Upon powerup, this information is loaded into Programmable Option
Select (PaS) registers residing on the adapter cards.
Figure 1 indicates one way in which a Logic Cell Array can
be used for the PaS-register section of a Micro-Channel
adapter card. The Micro-Channel interface includes logic
to decode the address, status, and control signals associated with the bus to identify the appropriate pas register
to be accessed. These signals determine if the card is
being addressed, and whether the current operation is a
Read or Write.

One key aspect of this architecture is the ability to configure the system without the need for DIP switches on the

CONTROL
READ
ENABLE

-RD

STATUS
LINES ~

READ!
WRITE
DECODE

EN

WE

GATED
WRITE
STROBES

LATCHES

CARD
SELECT

-

III

~
..-.-

POS
REGISTERS
(UP TO 8)

f- f-

1
REGISTER
ADDRESS
INPUTS ~ DECODES

III
~

r

SYSTEM
BIDIRECTIONAL
DATA BUS

N

111901A

Figure 1. Micro-Channel-Interface Block Diagram

6-50

logic must be very fast in order to grant control of the bus
to the adapter with the highest priority.

The Micro Channel specification reserves two POS registers for the upper and lower bytes of the Adapter Identification (10). Six other byte-wide POS registers can hold
additional configuration information; some of the bits
within these are specifically dedicated to channel status
information. Some applications will require the use of only
portions of these six registers.

As can be seen by the logic in Figure 2, this priority level
(ARB 10 0-3) is driven onto the bus via an open-collector
driver. The logic then turns around and accepts the driven
bus as input. The cycle may repeat a few times before the
adapter with the highest priority level actually gains control
of the bus. For properoperation each half of the cycle must
complete in 50 ns, a performance that can be achieved in
the 70-MHz LCA devices.

A second key aspect of the Micro Channel architecture is
its ability to arbitrate the bus access of multiple adapters.
The Micro Channel specification clearly defines the 10gJc
required for this arbitration. Each adapter in the system IS
assigned a priority level. These levels vary from the
highest priority "-2" to the lowest priority "F". This "-2, -1,
0, 1, 2 ... A, B, ... F" scheme defines unique priority levels.
The higher levels are primarily used for memory refresh or
error recovery. The lower levels are reserved for the
System Board processor and spares. The middle levels
are used for DNA Ports 0-7, typically used for high speed
transfers. The priority level assigned to any adapter is
stored in one of its POS register nibbles. The arbitration

Implementation of the POS registers, arbitration, logic and
control sections typically requires only 1/3 to 2/3 of a single
XC2018 or XC3020; the remainder of the LCA is available
for implementing the unique functionality of the specific
adapter card. Some Xilinx users have developed the
standard interface and stored it as a recallable macro
function in the Xilinx development system. Applications
including hard disk controllers, communication controllers, and specialized memory controllers have been developed for the PS/2 using Xilinx FPGAs.

COMPLETE LATCH
ARBBUS3

ARB ID-3

ARB ID-2

ARB ID-1

~~~~==========~~==~~b-~--ARBBUS1

•

ARB BUSO
ARB ID-O

>c~L~:~~:I~~~~=)

')
ARBI-ENT

,---- - - FOR
WONCHANNEL
COMPETITION

1119 02A

Figure 2. Local Arbiter Logic

6-51

DRAM Controller
with Error Correction and
Detection
Application Note
AN INTRODUCTION TO MEMORY CONTROL AND
ERROR CORRECTION

BY TOM WAUGH

to incorporate error detection and correction into the
memory system. This solution decreases system performance and adds the cost of redundant memory, but prevents parity errors from causing system failures.

The need to design memory controllers for systems that
have a large amount of memory is a common design
challenge that engineers must deal with today. Almost all
large memory systems use dynamic random access
memory (DRAM) because of its density and low cost.
While designing large memory systems with static random
access memory (SRAM), would make the design task
easier, the drive to produce more cost effective products
forces the engineer to deSign with DRAMs, despite their
inherent drawbacks. The memory cell of a DRAM is a
capacitor that holds achargecorresponding to the value of
the data bij. Since all capacitors leak charge, a DRAM cell
will gradually lose its charge, and its stored value, unless
it is recharged. This recharging, known as refreshing,
must typically be performed once every 2 to 4 ms depending on the DRAM. Refreshing is one of the DRAM
controller's two primary functions. The other function is to
arbitrate between requests for memory read and write
accesses from the system's central processing unit and
requirements for memory refreshes.

OPTIONS FOR DRAM CONTROLLER DESIGN

There are a number of options available to the engineer
designing a memory system that requires DRAM control.
(The following options apply to the design of error detection and correction circuits as welL) The simplest option is
a standard off-the-shelf LSI memory controller. The manufacturers of these devices provide an integrated solution to
DRAM control by combining CPU interface logic with the
necessary memory access/memory refresh arbitration on
a single Chip. However, each memory system has unique
timing and protocol requirements, and it is extremely
difficult for these standard parts to accommodate the
requirements of every system. This realization has driven
many DRAM controller manufacturers to incorporate
some degree of programmability into their parts to make
them more flexible. Unfortunately, this has made the parts
more complex, hungrier for power, and more expensive.
Even so, they simply cannot meet every system's requirements without employing external "glue logic."

In addition to its need for periodic refreshing, the DRAM
exhibits another problem that SRAM and other memory
devices do not-greater susceptibility to soft errors. A soft
error is the loss of a data bit in a memory cell in which the
memory cell is not physically damaged. Rewriting the data
in the cell corrects the error. This type of error is different
from a hard errorwhich is caused by a memory cell that has
failed permanently. Soft errors in DRAMs are usually
caused by alpha particles (helium nUClei), which are normally present in the atmosphere, but which are more often
emitted by radioactive impurities in the IC packages of the
DRAMs themselves. If an alpha particle hits a memory
cell, it can corrupt the cell's charge, causing adata bit error.
Most people believe that the likelihood of such an error is
so low that it can be safely ignored. While this may have
been true for the smaller memory systems of the past, it
may no longer be so. The size of some memory systems
today can make the likelihood of soft errors unacceptably
high. The probability of a soft error can be reduced by
device and packaging improvements and by reduction in
signal noise. Another method of dealing with soft errors is

The need to match the DRAM controller to the specific
requirements of the system has forced many engineers to
consider two options for creating their own controllers:
SSI/MSI packages or custom gate arrays. The use of SSI/
MSI is low risk, but wastes space and power; while the use
of the custom gate array provides a highly integrated
solution, but at considerable risk and expense. Nonrecurring engineering costs (NRE), testing and simulation
costs, inventory risk, and a long design cycle make the
custom gate array option unattractive for most designs.
Recent architectural advances in high-density Field
Programmable Logic Arrays have created a third option.
Xilinx's 3000 family of FPGAs brings unprecedented
density to programmable logic, with devices containihg as
many as 9000 gates. The 3000-family architecture makes
the devices particularly well-suited to memory-controller
applications.

6-52

comprising 44 256K DRAMs: 32 for data and 12 for the
correction bits. A single LCA device can serve as both the
DRAM controller and the ECC, which performs single- bit
error correction and double-bit error detection. There are
several features of the 3000-family architecture that make
this design possible. These include five inputconfigurable logic blocks (CLBs) with two storage
elements, internal buses, and flexible input/output
blocks (lOBs).

WHY IMPLEMENT A DRAM CONTROLLER WITH A
FIELD PROGRAMMABLE GATE ARRAY?

There are several reasons why one would want to design
a DRAM controller with a Logic Cell Array. First, the true
programmability of the LCA device gives the designer the
freedom to design the DRAM controller to the exact
specifications of the memory system. There is no need for
the external "glue logic" often necessary with standard
solutions, because any necessary design tweaking is
implemented internally. The LCA solution has the
advantage of the SSIIMSI or custom gate array solution in
that it can be configured to meet unique system
requirements. There is no loss in integration as with the
SSIIMSI solution, and the cost and risks of the custom gate
array solution can be avoided. Second, the density of the
3000 family of LCAs makes it possible to implement DRAM
control and error detection/correction in a single LCA
device. This is traditionally a two-chip solution using
standard parts: a DRAM controller and a separate error
correction and detection unit. It can of course be
implemented in a single custom gate array, but again with
the earlier caveats. Finally, the CMOS LCA consumes
less power than traditional standard "programmable"
controllers which are typically implemented in NMOS or
bipolar processes.

DESIGN OVERVIEW

The DRAM Controller/ECC uses a 16- MHz clock
synchronized with the processor clock, and sits between
the 8086 microprocessor with its 8288 bus controller and
the system memory (Figure 1). The 8288 decodes the
processor status lines (S2' S1' So) and tells the DRAM
Controller whether it is to perform a Read or Write access
to the memory. (It is also possible to incorporate the bus
controller logic into the larger LCAs). The DRAM
Controller then performs the appropriate access issuing
Row Address Strobe (RAS), Column Address Strobe
(CAS), and Write, if necessary. The Error Checker and
Corrector generates check bits on each Write, and checks
for and corrects errors on each Read. The controller also
signals the 8086 if the memory access requires a Wait
state or if a non-correctable error is detected.

DESIGN EXAMPLE
SYSTEM TIMING

The following deSign example shows the implementation
of a DRAM controller and an error checker/corrector
(ECC) with an LCA. The example is an 8-MHz 8086-based
system that directly addresses 1 Mbyte of memory

8284
CLOCK
GENERATOR

II

READY

~

r--

So t 51 I-52 t -

ClK
READY
RESET

BANKO
W
(512 KBYTES)
CAS H,l
6+16=22
BANK 1
256KDRAMS
(512 KBYTES)
RASO,1 ~
MRDC
READ
AMWC
WRITE
OUT 0-8 ~ AO-8
I'
CEN I-- HOLD
DATA
CHECK
DEN
BITS
BITS
DATA
BANK SELECT
BITS
BITS
A16-18
CBO-5
(CHECK BITS) k'=
--'-ENABLE
MULTI-BIT r- TO 8086 NMI
ADO-15
ERROR
LeA

8288
BUS
CONTROLLER

8086

~

I :

J:f

A19
A16-18
ADO-15

Figures 2a -2c show the timing involved in some of the
different memory cycles. The Word Write (Figure 2a)
requires no wait states as shown. The check bits from
the ECC are written to memory along with the data. The

~

r-- ,..

J

WAIT r--

-

74LS245

DATA BUS

16

1127 09A

Figure 1. System Overview of DRAM Controller with Error Correction and Detection.

6-53

•

DRAM Controller with Error Correction and Detection
T1

T2

T4

T3

8086

CLOCK

ALE

~~_________________________________________

CONTROLLER
CLOCK

RAS

CAS

W

OATAFROM
8086

------~<~----------------~)~----

112703

Figure 2a. Word Write Timing

T2

T3

TW

TW

T4

TW

8066
CLOCK

CONTROLLER
CLOCK

MS~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

'----------'I

CAS

l...--_~I

W

~

WAIT

~L.__________________________________~
ERROR DETECTED

CORRECTED DATA LATCHED

CORRECTED DATA RELEASED

112704

Figure 2b. Word Read Timing with Errors Detected.
u
8086
CLOCK

RAS

n

~---'

I

n

I

n

'-----'

TW

n

~--'

I

~

n

'-----'

I
'---

~L-____________________________________~

CAS

WAIT

DATA FROM
DRAM

IL__________________

...J

--------~<~--------------~)~-Figure 2c Word Read Timing with No Errors Detected.

6-54

112705

design, the address is latched into the lOB input flip-flop
with the 8086 ALE. The data from the 8086 can enter the
same input pin andgo directly to the ECCcircuit via the lOB
direct input-there is no need for external latches.

Read cycle (Figures 2b & 2c) requires a minimum of one
wait state. The insertion of a wait state is unavoidable
because of the time it takes the 120-ns DRAMs to output
the data. If the ECC detects no errors inthe data, the WAIT
signal is released and the Read operation is completed. If
an error is detected, the insertion of two more wait states
is required to provide time to correct the error. The
insertion of the two additional wait states affects system
performance, but this is the trade-off for having error
correction, which avoids the fatal system errors that occur
with parity-checking-only solutions.

Another feature of the lOBs is the output flip-flops with
three-state buffer enables. This feature permits bit error
correction using only one I/O pin. Figure 4 shows a bitsliced view of how the ECC is accomplished. A memory
Read cycle provides the best example for showing the
capabilities of the lOB structure. During a Read, the lOB
output is 3-stated, permitting the DRAM data on the data
bus to enter the ECC via the lOB direct input. II the ECC
detects a data bit error, it corrects the error and latches the
corrected data word into the output flip-flops of the lOBs.
The data bus is then 3-stated by turning off the DRAM
outputs. The corrected word, latched in the outputs of the
flip-flops, is then released onto the data bus by enabling
the 3-state buffer. This permits the corrected data to be
read by the 8086 at the same time it is being written back
to the DRAM.

DESIGN FOCUS
The 3000-family LCA architecture has a number of features that are essentialto the DRAM controller design. The
first such feature is the dual data input paths in the lOBs,
one registered and one direct. This structure permits the
address and data on a multiplexed bus to be latched from
the same 110 pin. Figure 3 is a bit-sliced view of an lOB
used to latch the multiplexed Address/Data bus. In this

r-------------------- ----

, - - - - - - j - - OUTPUT ENABLE

J.., r---,
r-"J-'O
0,...-----------,
I
I
,

:

I

r1>

L. ___

:

1--1-- OUTPUT CLOCK

~

DIRECT NPUT
REGISTERED INPUT

'J

CORRECTED DATA OUT

14--t-- CHECKERICORRECTOR
FROM ERROR

I

r------I-.
g~~~~~~~~ECTOR
r---,

DATA TO ERROR
CHECKEFVCORRECTOR
ADDRESS TO INTERNAL
BUS VIA 3·STATE

10

BUFFER

OL __ -

I
I

I
I

I

I

IL ___ .J~-'---------

L _______________________ _

ALE

1127 OGA

1127 07

Figure 3. Address and Data Latching

Figure 4. Data In and Out Through ECC

Latching Data off a Multiplexed Address and Data Bus.
The Input/Output block configuration shown above
illustrates how the direct and registered inputs in the
lOBs can be used to latch a multiplexed address/data
bus into the LCA. The address is latched into the lOB
flip-flop; the data flows directly into the ECC logic.

The data from the bus goes into the LCA, where it is
corrected in the ECC. The corrected data is then put
back onto the bus via the lOB output flip-flop.

6-55

II

DRAM Controller with Error Correction and Detection

Figure 5 is a block level diagram of the DRAM Controller
and ECC that reside in the LCA. A functional description
of each block follows:

by this block include the row address and column address
strobes (RAS and CAS), the WR ITE Signal, the WAIT-state
signal for the processor, the HOLD signal that isolates the
processor from the memory, the clock for the refresh
address counter, and the select control for the address
select.

The refresh timer is driven by the 16-MHz clock to provide
a signal that tells the DRAM controller that the memory
needs refreshing. Each of the 256 rows of memory in this
system must be refreshed every 4 ms. The controller
attempts to refresh eight rows every 1251JS, so that all 256
rows are refreshed in 4 ms. The refreshing technique
employed in this design is a unique combination of burst
and hidden refreshing to show the flexibility of the
LCA-based solution. There is no need to force a system to
conform to the constraints of an off-the-shelf part. The
Hidden Refresh is performed when the 8086 is doing a
Read from or Write to somewhere other than memory, like
an I/O port. This involves giving the DRAM a refresh
address from the refresh address counter via the address
selector and a RAS pulse Low from the timing generator.
The Burst Refresh is performed only if it has not received
its eight required refreshes during the 125-1JS refresh
period. When a Burst Refresh is required, the co ntroller will
isolate the memory from the 8086, insert wait states, and
provide the number of refreshes it needs to complete the
eight refreshes required during the refresh period.

The refresh address counter is an 8-bit counter that provides the 8-bit addresses necessary to refresh the DRAMs.
The address selector selects which address is sent to the
DRAM. During a Read or Write cycle, the timing generator
select control signal tells the address selector to select
the DRAM row address, strobe it with the RAS, and then
select the column address and strobe it with the CAS.
During a refresh, the address selector selects the address
from the refresh address selector and strobes it into the
DRAM with RAS.
During a Write cycle, the error checker/corrector (ECC)
generates six check bits using a modified Hamming code
for each 16-bit data word and writes them to memory along
with the data. Use of a modified Hamming code permits
single-bit data correction and double-bit error detection.
During a Read cycle, the ECC compares the check bits
read back from memory with new check bits generated
from the data read back. If the comparison yields a
correctable error, the ECC will correct it. If the error is not
correctable, it will flag the NMI on the processor.

The timing generator, a state machine triggered by Address
Latch Enable (ALE) at the beginning of the processor
cycle, produces all the timing required to perform the
memory accesses and refreshes. The signals generated

DATA BUS

'6

¢===========~====~====~TODMMD~A

REFRESH TIMER
BURST REaUES'TL.--~
HIDDEN REaUES'TL.--~
RESET
A '9

TIMING
GENERATOR
ECC
CONTROLS

BANK SELECT

00·'5

CBO-5I===~

ERROR CHECKER/
CORRECTOR
MULTI·Brr ERROR

TO DRAM DATA

TOSOS6 NMI

W
TODMM

RASo,'
CASH,L
FROM
BUS CONTROLLER

WArr
HOLD

MUX CONTROL
'6MHz

TOS088
TO BUS CONTROLLER

~==~GA~D)[D)FRiEE:SSSSr:;MiUuiXxl

INCREMENT
TO DRAM ADDRESS
REFRESH
ADDRESS
COUNTER

A,O·'S
REFRESH
ADDRESSO·7

INCREMENT
COUNTER
1127 02A

Figure 5. LCA Block Diagram
Block diagram of the DRAM controller functions implemented in the LeA.

6-56

E:X1l1NX
CONCLUSION

Perhaps the most important feature of the LCA architecture for implementing a DRAM Controller is Hs internal
three-state bus capability. The three-state buffer enables
onto the horizontallonglines allow the designer to implement an internal bus in the LCA. This feature permits the
implementation of the Addre"'ss Selector without using any
CLBs. Figure 6 shows a bH slice view. The row, column,
and refresh addresses all have access onto the internal
bus, and to the outputs that lead to the DRAMs. By
controlling the three-state enables, only one address is
allowed onto the bus at a time. This feature is essential to
this design, and has many other applications including
performing wired-AND functions and address decoding.

____

Although the bottom-up design of a DRAM controller is a
complex task, it is necessary in cases in which off-the-shelf
controllers do not meet the requirements of the system.
SSIlMSI and custom gate array solutions involve tradeoffs and compromises. Designing a DRAM controller and
ECC with an LCA is a straightforward application and a
good fit for the 3000 family architecture. The Field Programmable Gate Array offers the flexibility necessary to
match the many different memory systems,the integration
desirable for board level designs today, and the cost
effectiveness required to make a competitive product.

....,~-------IN-TE-RN..,..AL-BU-S-------"'T"-- ~g::~LlNE

ROW
ADDRESS

COLUMN
ADDRESS

REFRESH
ADDRESS

ROW
ENABLE

COLUMN
ENABLE

REFRESH
ENABLE
112708

Figure 6. Address Multiplexing Using 3-State Enables onto Internal Buses

6-57

The Programmable Gate Array Company

6-58

SECTION 7
Article Reprints

1

Programmable Gate Arrays

2

Product Specifications

3

Quality, Testing, Packaging

4

Technical Support

5

Development Systems

6

Applications

7 Article Reprints

8

Index

Article Reprints

Build Reconfigurable Peripheral Controllers ....................................... 7-1
Accelerate FPGA Macros with One Hot Approach ............................. 7-8
Reprogrammable Missile: How an FPGA Adds Flexibility
to Navy's Tomahawk ....................................................................... 7-13
Pivoting Monitor Increases Versatility of Workstations ....................... 7-15
Two, Two, Two Chips in One .............................................................. 7-19
LCA Stars in Video .............................................................................. 7-22
Taking Advantage of Reconfigurable Logic ........................................ 7-24
Faster Turnaround for a T1 Interface .................................................. 7-33
Using Programmable Logic Cell Arrays In a Satellite Earthstation ..... 7-35
Programmable Logic Betters the Odds for Bet-Slip Readers .............. 7-40
Building Tomorrow's Disk Controller Today ........................................ 7-44

DESIGN APPLICATIONS
By INCLUDING A RAM-BASED PROGRAMMABLE
LOGIC CIRCUIT, ONE CONTROL CARD CAN
READILY HANDLE MULTIPLE INTERFACES.

BUILD RECONFIGURABLE
PERIPHERAL CONTROLLERS
uring the design of a computer peripheral, such
as a printer, CRT terminal, disk drive, or other
complex subsystem, decisions are often made
regarding control logic partitioning. In some instances, the peripheral contains all of the control
circuits, and the interface to a host system is
over a standard port, such as an RS-232 or a Centronics link. However, the
limited data-transfer speed and signal-control flexibility of those ports often
causes a bottleneck when very large amounts of data must be transferred or
complex operations must be controlled.
One solution is to keep the data-intensive portion of the logic in an adapter
board that plugs into the host computer's bus and supply a custom high-speed
link to the peripheral. But using hardwired logic to implement the adapter card
limits the card's flexibility if updated versions ofthe peripherals are released, or
if a second, relatively different model is developed. Ideally, one adapter card
should be all that's needed. Simple software updates (device drivers) that can be
loaded into the card for the specific model peripheral can provide an optimized
interface.
Such a peripheral-control card can readily be developed by taking advantage
of RAM-based programmable logic circuits, such as the logic cell arrays from
Xilinx (see "RAM-based Programmable Logic''). And the card's function can
be altered in the field with just a new software driver that's loaded when the system boots.
Furthermore, if the data is RAM -based, it can be altered during system operation as well. Consequently, if the same card must control multiple printer types,
the card can be switched between printer drivers in just milliseconds by reloading the RAM-based programmable logic circuits to reconfigure the interface onthe-fly. Such a controller can be easily modified to support new peripheral devices, and it will never have to be removed from the computer system.
Programmable logic devices based on static RAM memory cells make it possible to implement "soft" hardware-that is, hardware whose functions can be
KENNETH K. HILLEN
Tektronix Inc., Mail Stop 63-356, P.O. Box 1000, Wilsonville, OR 97070;
(503) 685-3904.
BRADLY FAWCETT
Xilinx Inc., 2100 Logic Dr., San Jose, CA 95124; (408) 559-7778.

7-1

Article Reprints

FLEXIBLE PRINTER
CONTROLLER
r:--

68020

t

...

8·bHdalabus

decoder
1~
32·bH dill bus

Mtmary
RAM and
-EPROM

1

~
~

.

chip
r:--

'---

~

WIII..1ate
generalor

Pixel
coprocessor

~~ ~

IBM Pc bus

Bus
inte~ace

H
24-bil

~

Printer

. <:]rPrlnter~

IIIdpUlchip XC2018

-

512.byIe
FIFO buffer

addraaabus

~
~

ROM

CPUragiater

r-r---

t---

EEPROM

1. IT'S ONLY ASMALL PORTION of the circuitry used on the 6802&based
intelligent printer controller, but the reeonfigurable printer output chip gives the board its
ne.ibility. Two dedicated custom chips on the card handle the pixel processing and the host·
system bus interface.

changed while it resides in the system. The configuration programs
can be loaded automatically at power-up or on command at any time.
Both users and manufacturers benefit from this flexibility. Microcomputer users can easily change or upgrade peripheral devices without
purchasing a new controller or altering the internal hardware of the system. Equipment manufacturers
don't need to design a new controller
board for each new peripheral.
As a result of the improved flexibility, new peripherals can be
brought to the marketplace sooner,
and the cost of initially developing
the flexible peripheral controller
board is amortized over a larger
number of units. The ability to support future peripherals extends the
controller's product life. Field updates to the controller can be accomplished by distributing new program
disks to update the logic configuration, as opposed to requiring hardware modifications to the board.
Advanced page printers and color
thermal printers require huge

amounts of data and some special
control signals to keep their print engines busy and ensure optimum performance. Yet to have a custom
adapter card for each printer would
get very expensive, especially if two
such printers were needed. By pulling out the common control circuits
needed by either printer type and implementing those circuits in both
custom and RAM-based programmable logic, system cost can be minimized and users save one card slot in
the host system. In addition, because
the printer has a minimal amount of
logic in it, .,upgrades to the mechanism would cost less as well.

CONTROLLING PRINTERS
Consequently, by dividing the control and processing logic that a complex printer needs, the overall system can be made more flexible. The
printer would contain only the basic
machine-control circuits and the
printing control logic, while the host
computer's plug-in card would contain all of the data-processing logic.
This approach was taken by the Pha-

7-2

serCard printer controller from the
Graphics Printing and Imaging Division of Tektronix. By implementing
the system architecture in that fashion, the card helps designers make
printer changes or add new printers,
still keeping the design cycle very
short because there are less circuits
in the printer to deal with.
A key ease-of-use feature for laser
and color thermal printers would be
to have them emulate Adobe System's Postscript and Hewlett-Packard's HPGL graphics-description
languages. To do that, the host system plug-in board includes the emulation capability along with a 68000family microprocessor and a custom
chip that accelerates the computations needed to prepare an image for
printing. Furthermore, the PCI ATI
XT bus-compatible card uses one of
the smaller Xilinx programmable
gate arrays for the printer interface
logic and a mask-programmed gate
array to control the interface to the
host PC's bus (Fig. 1).
By loading the appropriate configuration program into the programmable logic chip, the controller card
can be used with any of several printers. They include monochrome laser
printers (such as the Canon LBP8),
the Tektronix 4696 (a 120-dot-perinch ink-jet color printer with a Centronics interface), the Tektronix
4693D/DX (a 300-dot-per-inch waxtransfer color printer with a Tektronix Parallel Interface-an enhanced version of the Centronics interface), and the new Tektronix
Phaser CP (a 300-dot-per-inch waxtransfer .color printer with a synchronous serial interface). The PhaserCard includes two printer interface ports so that two printers can be
connected simultaneously.
Considerable processing power is
needed in order to interpret the
graphics-description languages, perform image processing, and run the
printers. To handle the housekeeping and manage the host system interface, a 68020 32-bit processor,
running at 12 MHz with one wait
state, readily handles the control and
leaves room for program growth if
more .complex tasks must be handled. To eliminate the bottleneck of

i,l,i1 ftl·,tg;iI9,jiUilhj

FLEXIBLE PRINTER
CONTROLLER
converting the page description into
the raster image, a custom graphics
coprocessor tackles all of the computations. The chip is a full-custom I C,
and assists in image generation during line drawing, area filling, and
half-toning operations. Lines can be
drawn at 6 million pixels/so
During operation, the CPU accepts image description input
streams from the host bus, rasterizes the image into bit-map memory
(with assistance from the coprocessor), and then transfers the bit map
to the printer interface logic. All timing signals are derived from a 24.23
MHz oscillator.
The processor's code and data, and

B

ased on static RAM cells
that hold configuration
data rather than metal
wiring or some form of
nonvolatile memory, the Xilinx
programmable gate arrays are
high-density CMOS chips that
combine user-programmability
with the flexibility and extensibility of a gate-array architecture.
The general structure of the Xilinx programmable gate arrays,
also known as logic cell arrays
(LCAs), consists of a core area
containing a matrix of configurable logic blocks (see the figure).
Interspersed with the logic blocks
are channels with programmable
interconnections, and surrounding the core area is a ring of programmable I/O cells. The I/O
blocks supply an interface between the external package pin
and the internal logic. Each of the
configurable logic blocks includes
a combinatorial section, storage
elements, and internal routing
and control logic. Programmable
interconnection resources provide the routing paths that connect the 110 and logic blocks in
the desired configuration.
Similar to a microprocessor, the
LCA is a program-driven device.
The configuration program is
loaded automatically from an external memory on power-up or on

the configuration programs for the
programmable logic chip reside in
on-board RAM. That RAM would
typically be loaded from the host system's hard disk. Code updates could
thus be distributed on diskettes,
eliminating the need for a technician
or service person to replace a nonvolatile memory chip from the control
board to upgrade the card. To hold
the control code and the page description, 3 Mbytes of dynamic RAM
are included on the control card, and
an additional 5 to 8 Mbytes can be
added through a memory-expansion
connector and a daughterboard.
The on-board memory is partitioned into three I-Mbyte blocks-

one holds program code, another
serves as a data buffer, and the third
holds the bit map for A-size, 150-dpi
(dots per inch) printers. The additional memory is required for A- or Bsize, 300-dpi printers. Power-up diagnostics and the bootstrap routine for
downloading from the hard disk are
held in 64 kbytes of EPROM, while a
512-byte electrically-erasable memory holds several parameters that process Postscript files and provide
printer identification information.
A bus interface circuit (BIF), implemented with a 5000-gate maskprogrammed gate array, connects
the controller to the PC bus. The BIF
chip emulates standard LPT (paral-

THE PROGRAMMABLE GATE ARRAYS
command, or is programmed by a
microprocessor as part of system
initialization.
Designing with Xilinx programmable gate arrays is similar
to designing with other gate arrays. Users can employ familiar
CAE tools for design entry and
simulation. The Xilinx-specific
software for cell placement and
circuit configuration runs on the
PC/ AT and compatibles, as well
as on popular engineering workstations, such as the Apollo and
Sun3.
Currently, two families of compatible LCA devices are available.
The original XC2000 series includes the 1200-gate XC2064 and
1800-gate XC2018. The secondgeneration XC3000 family has

five members, ranging from the
2000-gate XC3020 to the 9OOO-gate
XC3090. A third family, the
XC4000, is now in development
and should be sampled later this
year. It will offer densities of up
to 20,000 gates.
Because chips in the XC3000 series are now readily available,
they would significantly simplify
the design of a similar printer controller card if it were being done
today. This is because they incorporate on-chip three-state buffers, offer more functionality in
each configurable logic block, and
have improved routing resources.
However, when the controller's
concept was initially started in
1988, only the XC2000 series was
available.

D QWr W

QO wQ

;~'bWi 0 0 0
D

01-00 0
7-3

Article Reprints

',IM!H'·,jijij!!q.liUl ~,

FLEXIBLE PRINTER
CONTROLLER
Output
connectort
CPU

Output
connector 2

1

2, EVEN THOUGH THE PRINTER output..ontrol chip is based on a

programmable logic circuit, off'chip functions, such as thr....tate buffers, a FIFO-buffer
memory, and a configuration register must be added. This is because the logic array can't
efficiently implement such functions on chip.

leI) and COM (serial) ports on the PC
side, making it possible for existing
applications that drive those ports to
use the printer control card as well.
One avenue to make the printer in·
terface logic flexible enough to sup·
port various output devices while oc·
cupying a minimal amount of board
space is by incorporating the 1800·
gate Xilinx XC2018 logic cell array
(LCA) chip. The chip offers enough
gates and in·system malleability to
make the logic flexible. The user·pro·
grammable aspect of the LCA also
minimizes design risk and reduces
the design cycle turnaround time. In
addition, because each configuration
program is independent of the oth·
ers, each printer can be supported
with a separate, optimal interface. In
fact, with the on·the·fly reconfigura·
bility of the LCA, two different print·
ers-one monochrome and one col·
or-could be supported simulta·
neously in near real time without duo
plicating much circuitry. The correct
configuration program for each
printer is downloaded to the LCA as
that printer is accessed.
In addition to the actual printer in·
terface implemented in the LCA
chip, several other components are
needed to flesh out the support (Fig.
2). The largest component, a 512·
word·by·9·bit first·in/first·out memo
ory, buffers the data stream be·
tween the CPU and the printer. Each
entry in the FIFO buffer includes 8
bits of data; the ninth bit marks spe·
cial conditions, such as end·of·line
(EOL).

The 68020 CPU writes data into
the FIFO buffer in bursts to mini·
mize the time its spends dealing with
data·output operations. The LCA
reads the data from the buffer, per·
forms any formatting required by
the particular type of printer being
used, and sends the data to the print·
er. As a result, the CPU can perform

other tasks while the printer receives the data at its own pace.
Signal buffers external to the LCA
are used to isolate the LCA from the
output connectors, as well as give additional drive capability and electrostatic protection for the CMOS chip.
The output signals are buffered with
dual byte-wide transparent latches.
Typically, only one byte-wide set of
latches will be transparent at one
time; the other will be left holding a
value that drives its attached printer
to a quiescent state.
Also external to the LCA chip is a
configuration register. It controls
the downloading of configuration
programs into the LCA. Directly accessible by the 68020 processor, this
register is built with two devices: an
octal flip-flop to drive signals to the
LCA and a three-state buffer to send
signals back to the processor.
The configuration process involves only three signals ..The LCA's
Done/Program input is driven low to
initiate an LCA configuration cycle.

Databuffer
from--';f--~===:::;:1.:-;-:--:-:----,
FIFO

r------....... Data to PhaserCP
FlFO·buffer
read clock -+-IO--;====~'l

t-.....- - - - - - - - - - Clock to PhaserCP
24.23 MHz

400 Hz:-----t--D

1

3, TO IMPLEMENT THE SERIAL interface required for a Phaser CP printer,
blocks such as a parallel·to-serial shift register; various divide chains; a simple state
machine composed of four flip-flops; and control, status, and interrupt registers must be
configured in the LCA.

7-4

E:XIUNX

lu£iiH ',qgIlR·lllu.tt

FLEXIBLE PRINTER
CONTROLLER
The configuration program is then
downloaded to the LCA as a serial bit
stream using one clock and one data
line. The LCA drives the Done/Pro·
gram line back to the high state to
signal the end of the configuration
process. Downloading a configura·
tion program takes less than 60 ms.
When two printers are connected
to the card, selection of the correct
configuration program is controlled
by the processor; when a printer is to
be accessed, the LCA is configured
for that particular interface. If two
different printers are connected, the
LCA is reconfigured frequently duro
ing idle (non-printing) periods to
check each printer's status.
In general, the operation of the
configured LCA chip is similar for all
printer types. The CPU writes data
to the FIFO buffer, and a state machine created in the LCA reads the
data from the buffer and sends it to
the printer. Any necessary data formatting is performed in the LCA.
For example, data bytes are convert-

ed to a serial data stream for the
Phaser CP printer.
Logic in the LCA generates all of
the required handshaking and timing signals. CPU interrupts are generated as needed, based on the status
of the printers, FIFO buffer, and the
LCA's internal state machine. Control and status registers that can be
accessed by the CPU also are implemented in the LCA.
To show how the LCA can be configured for various printers, three
specific configurations that each use
about 2/3 of the 74 user-programmable I/O pins in the LCA must be examined. The first configuration
looks at the interface to the Phaser
CP, a 300-dpi wax-transfer color
printer with a serial interface; the
second examines a parallel interface
to the 4693D/DX color printer; and
the third shows a raw video interface
to a bare-bones laser printer.
To control a serial-input printer,
such as the Phaser CP, part of the
LCA must implement a parallel-inl

Data input-------.
from FIFO buffer

~;==;;=::;:;:;tT-

Data to
4693D/DX
Data strobe

~~~~~~------- Externalcontroi
r

signals

Topr_sor .....---+----1

+----_ Statusfrom
4693D/DX

1

4. FOR APARALLEL INTERFACE to talk to the 4693D/DX printer, the LeA

must he configured to supply an input latch, a cyan-magenta-yellow-black to red-gi-een-blue
converter, severahigna! multiplexers, a simple clock divider and state machine, and various
control, status, and interrupt registers.

7-5

serial-out shift register that converts the byte-wide data from the
FIFO buffer to a serial format. The
remaining logic configured in the
LCA includes a clock divider to control the shift register, a divider to
generate the data clock to the printer, a clock divider and state machine
to generate the horizontal synchronization (Hsync) signal, and the processor interface and interrupt registers (Fig. 3). All of that logic employs
78 of the 100 logic blocks available in
theXC2018.
The data-clock generator divides
the 24.23-MHz board clock by 10 to
create the 50%-duty-cycle 2.4-MHz
clock that sends the serial data
stream to the printer. This data clock
is further divided by 8 to control the
shift register. On every eighth data
clock, the next byte in the FIFO buffer is loaded into the shift register.
A small state machine composed
of four flip-flops generates the
Hsync signal and enables clocks and
data to be sent to the printer. After
being enabled by the CPU, the state
machine waits for a 400-Hz signal
from the bus interface chip. A 12.5kHz clock is used to sequence the
state machine, which generates an 8
/Ls Hsync pulse, followed by an 8 /Ls
delay. Then the state machine can
start the data stream. The data stops
when the EOL flag (the ninth bit in
the FIFO memory word) is read from
the FIFO buffer.
With six 8-bit processor interface
registers, the CPU can write control
information and read status information. These registers are mapped
into the CPU's I/O address space;
four are write-only and two are read"
only (see the table). The three interrupt registers share the same bit assignments; bits 4 and 5 of the chipcontrol register control the transparent latches for the two printer
connectors.
Because both connectors are driven by the same pins of the LCA device, these bits force one connector's
outputs to a static state (by disabling
the transparent latch) while talking
to the other printer. Bit.7 of the printer control register is toggled to control a serial-status-readback state
machine in the printer. Using this

Article Reprints

,utiiA l,jijillhf.ilUl$'

FLEXIBLE PRINTER
CONTROLLER
control, 16 bits of status information,
identifying such conditions as paper
jams, out-of-paper, and out-of-ribbon, can be read back one at a time
through bit 2 of the printer status
register.
The parallel interface of the
4693DIDX printer requires 79 of the
LCA's logic blocks. To implement
that interface, the main functional
blocks that must be configured in the
LCA include an input-data register, a
data converter, a state machine to
control the data transfer between
the LCA and the printer, and the processor interface and interrupt registers (Fig. 4).
An 8-bit register is used to latch
the data as it comes in from the FIFO
buffer. The ninth bit, which indicates
the EOL condition, goes to the state
machine and interrupt registers. Optionally, the data can be converted
from the cyan-magenta-yellow-black
(CMYB) format generated by the
controller card to the red-green-blue
(RGB) format (some early versions
of the 4693DIDX printer accept only
the RGB format). This straightforward conversion requires only com-

binatoriallogic.
A simple six-state state machine
combined with a 3-bit counter controls the data flow and commands to
the printer. The 24.23-MHz clock is
divided to supply a clock of approximately 5 MHz to the state machine.
The state machine sends data to the
printer by reading it from the FIFO
buffer, then stores it in the input register, converts it to the RGB format
(if required, as determined by a bit in
the chip control register), and asserts the Data Strobe signal.
Data is sent in a streaming modethe machine will keep sending data
to the printer until a byte marked
with an EOL indicator is read from
the FIFO buffer. The transfer of a
command byte to the printer is triggered by loading the printer-command register and setting a bit in the
chip-control register. The state machine controls the command sent to
the printer and waits for the acknowledgement.
The six 8-bit processor interface
registers are similar in function to
those described for the Phaser CP
printer. The chip-control register in-

Datakom-----------;:===l_ _ _--,

FIFO buffer

FIFO buffer
read clock

_-:=====-I'1I--:/>_LP-=ar=all=el-=.to-~se=ri:::al=Sh::.:ifl~re:gi:::ste::.rJ

24.23 MHz

r4>r---:::-,:,:",:-:--~' T

I

L-

Divideby8

r

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f--

CIOC~

and
slate machine,

Beam Detect signal

I

M

Serial clock output
Command/Status to/
from LBP8

Shiftregisler

---1
To processor

1

Control registers

1

}l

External control signals

I Status register
I

---l

Video data
toLBP8

Status from LBP8

tnterruptregisters

5. CONTROLLING Alaser engine directly on the Canon LBP8 requires that the LCA
supply precise data and control signals. Data input still requires a parallel·to-serial shift
register, and several divider chains are needed to aoliust the clock rate. Asmall state
machine controls the data transfer and a simple bidirectional shift register.

7-6

cludes controls to clear the FIFO
buffer, start the output state machine, enable the command mode, enable the transparent latches associated with the two printer connectors,
and enable the CMYB-to-RGB converter. The printer-command register holds commands to be sent to the
printer, and the printer-status register contains status information
about the printer and the FIFO buffer. Interrupt-clear, mask, and read
registers control the generation of
interrupts to the CPU.

HANDLING VIDEO DATA
When configuring the LCA chip to
deliver the video data stream to the
Canon LBP8 laser printer, the data
from the controller card must be precisely synchronized with the laser
mechanism to ensure image accuracy. Major circuit elements in this configuration include clock dividers that
produce the data clock and control
FIFO-buffer read operations, a parallel-to-serial shift register to serialize the data, a simple state machine
to control data flow, a serial-to-paralleI shift register to collect printer
status information, and the processor interface and status registers
(Fig. 5). This configuration uses 97 of
the 100 logic blocks in the LCA.
The 24.23-MHz clock is first divided by 13 to produce the 1.863-MHz
data clock needed for the data transfer to the parallel-to-serial shift register. The data clock is further divided by eight to generate the signal
that's used to read a new byte from
the FIFO buffer and load it into the
shift register as the transmission of
the previous byte to the printer is
completed.
To ensure that the data is properly
positioned on the page, the data clock
isn't started until a Beam Detect signal is received from the printer. This
signal is sent at the start of each scan
line. Data clocks will continue to be
generated and data sent to the printer until an EOL mark is read from
the FIFO buffer. The controller then
waits for the next Beam Detect to
start again. The state machine is just
one flip-flop that's enabled by a bit in
the chip-control register, set by a
Beam Detect, and cleared when the

E:XIUNX

FLEXIBLE PRINTER
CONTROLLER
quest for vertical synchronization. InterruptRegister
Read/write
Bit assignments
clear, mask, and
read registers
Chip control
write
bit 0 - Clear FIFO buffer
bit 4 - Control transparent latch to color printer
control the genbit 5 - Control transparent latch to monochrome printer
eration of interbit 6 - Reset the printer
rupts to the
Printer control
write
bit 1- Start printer output state machine
CPU.
bit 2 - Output enable
bit 3 - Command synchronization
As with most
bit 4 - Double the vertical resolution
logic technolobit 5 - Skip to next ribbon color
gies, the controlbit 6 -load sheet of paper
bit 7 - Get next bit of printer status
ler card's design
was originally
Printer status
read
bit 0 - Printer status state machine at start
bit 1 - Printer ready for current pass
conceived
as
bit 2 - Serial status data read back
block diagrams
bit 3 - On·line indicator
bit 4 - Cable disconnected indicator
and schematic
bit5 - Power·off indicator
drawings. Early
Interrupt clear
write
bit 0 - FIFO buffer empty
in the system dewrite
Interrupt mask
bit 1 - FIFO buffer lull
sign cycle, the
Interrupt read
read
bit 2 - Printer ready slate change
portions of the
bit 3 - On·line state change
bit 4 - Printer power off
design to be imbit 5- EOL (End·ol-line)
plemented in the
LCA were deterEOL mark is encountered.
mined. State machine designs can be
The LBP8 printer uses a serial done with Mealy/Moore diagrams,
path to receive certain commands which can be translated into a set of
and send back its status. These mes- reduced next-state equations using
sages are clocked through a serial- the Abel software package from
to-parallel! paralle !'to-serial shift Data I/O Corp., Redmond, Wash.
register in the LCA, making it possiDesigning large state machines in
ble for the CPU to write commands the LCA can use up numerous interand read status information as one nal configurable logic blocks (CLBs)
byte.
very quickly because many state maThe interface to the CPU consists chines can have a dozen or more inof eight 8-bit control, status, and in- puts to the next-state equations.
terrupt registers. The chip-control However, by applying automata theregister and printer-control register oryto find common terms that can be
include controls to clear the FIFO shared by more than one equation,
buffer, start the output state ma- the number of inputs to each CLB
chine, control the transparent latch- was kept to four or less.
es of the printer connectors, reset
Furthermore, because the XC2018
the printer, synchronize the image LCAs don't have three-state outvertically, request the start of a new puts, CLBi had to be used to implepage, and notify the printer that the ment 2:1 mUltiplexers to handle incontroller is ready.
ternal-register readback. The multiOne bidirectional shift register plexers would then select which of
constitutes both the printer-com- several registers would be connectmand register and the printer-re- ed to the processor's data bus during
sponse register. The printer-com- a read operation. In most cases, the
mand register holds commands to be CLB that contained the register had
sent to the printer serially; the print- enough unused logic to implement
er responds by sending the request- the multiplexer. As a result, the need
ed information to the printer-re- for the mUltiplexers doesn't have an
sponse register. The printer-status impact on the number of CLBs availregister holds additional status in- able for the main control logic.
formation from the printer, such as
The design can now be mapped
the Beam Detect signal status, into the logic and I/O blocks of the
ready-to-print indicator, and a re- LeA device using the XACT design

REGISTER BIT
ASSIGNMENTS FOR PHASER CP

7-7

editor from Xilinx, a development
tool that allows users to manipUlate
a graphics image of the internal LCA
architecture. About three weeks are
usually needed for LCA newcomers
to enter and debug the first circuit.
Each subsequent configuration
that's generated may typically require less than one week's developmenttime.
The placement and routing of the
circuitry can be a major area of concern because a limited amount of
routing resources are available near
each CLB. That was a key concern
for the XC2018 because a large number of CLBs had to be interconnected
to create the next-state equations.
The net routings using the LCA's
general-purpose interconnections
sometimes result in surprisingly
long propagation delays. To minimize the delays, the CLBs were clustered so that the time-critical paths
were kept as short as possible. The
reprogrammable nature of the array
makes it possible for multiple whatif scenarios to be evaluated.
Because LCAs can be quickly and
easily reconfigured, special configurations can be generated for test purposes during system development.
During prototyping, a number of internal signals can be routed to the
otherwise unused 1/ 0 pins to aid in
the debugging process. A special diagnostic configuration can also be included in the final production design
to ease the power-up diagnostic routines and servicing.D
Reprinted with pennission from Electronic Design March 8,1990. © Penton
Publications.

II

Article Reprints

DESIGN APPLICATIONS
WHEN DESIGNING STATE MACHINES, A TECHNIQUE
CALLED ONE-HoT ENCODING CREATES EFFICIENT
CIRCUITS FOR TOP-PERFORMING FPGA MACROS.

ACCELERATE FPGA MACROS
WITH ONE-HoT ApPROACH
tate machines-one of the most commonly implemented functions with programmable logic-are employed in various digital applications, particularly controllers. However, the
limited number of flip-flops and the wide combinatorial logic of a PAL device favors state
machines that are based on a highly encoded state sequence. For example,
each state within a IS-state machine would be encoded using four flip-flops
as the binary values between 0000 and 1111.
A more flexible scheme-called one-hot encoding (OHE}-employs one flipflop per state for building state machines. Although it can be used with PAL-type
programmable-logic devices (PLDs), OHE is better suited for use with the fan-in
limited and flip-flop-rich architectures of the higher-gatHount field-programmable gate arrays (FPGAs), such as offered by Xilinx, Actel, and others. This is because OHE requires a larger number of flip-flops. It offers a simple and easy-touse method of generating performance-optimized state-machine designs because
there are few levels of logic between flip-flops.
A state machine implemented with a highly encoded state sequence will

STEVEN K. KNAPP
Xilinx Inc., 2100 Logic Dr.,
San Jose, CA 95124;
(408) 879-5172.

1

1. HERE, ATYPICAL STATE MACHINE BUBBLE diagram shoWlthe
operation of a seven..lale slale maehinethat reaets 10 inputs Athrough E .. "ell ..
previous-slale conditions.

E LEe T RON I C

7-8

STATE MACHINE
DESIGN

State!
I

Slate 7

I

I

IL __________ ...JI

1

2. INVERTERS ARE REQUIRED althe D iDput and the Q output of the state
flip-fiop to eDsure that it powers ... iD the proper state. CombiDatoriallogio decodes the
operations based OD the iDput oonditi...s and the state feedbaok signals. The flip-fiop will
remaiD in State l .. loDC .. the oonditi...al paths out of the state are not valid.

generally have many, wide-input logic functions to interpret the inputs
and decode the states. Furthermore,
incorporating a highly encoded state
machine in an FPGA requires severallevels of logic between clock edges
because mUltiple logic blocks will be
needed for decoding the states. A
better way to implement state machines in FPGAs is to match the
state-machine architecture to the device architecture.

LIMITING FAN·IN
A good state-machine approach
for FPGAs limits the amount of fanin into one logic block. While the onehot method is best for most FPGA
applications, binary encoding is still
more efficient in certain cases, such

as for small state machines. It's up to
the designer to evaluate all approaches before settling on one for a
particular application.
FPGAs are high-density programmable chips that contain a large array of user-configurable logic blocks
surrounded by user-programmable
interconnects. Generally, the logic
blocks in an FPGA have a limited
number of inputs. The logic block in
the Xilinx XC-3000 series, for instance, can implement any function
of five or less inputs. In contrast, a
PAL macrocell is fed by each input to
the chip and all of the flip-flops. This
difference in logic structure between PALs and FPGAs is important for functions with many inputs:
Where a PAL could implement a

State 4

RD

State 3

1

3. OF THE SEVEN STATES, thestate-tra..iti... Iocio required for State (is the
most oomplex, requiring inputs from three other state outputs .. "ell .. four of the five
COnditiOD signals (A - D).
DESIGN

7-9

many-input logic function in one level of logic, an FPGA might require
mUltiple logic layers due to the limited number of inputs.
The OHE scheme is named so because only one state flip-flop is asserted, or "hot," ata time. Using the
one-hot-encoding method for FPGAs
was originally conceived by HighGate Design-a Saratoga, Calif.based consulting firm specializing in
FPGA designs.
The OHE state machine's basic
structure is simple-first assign an
individual flip-flop to each state, and
then permit only one state to be active at any time. A state machine
with 16 states would require 16 flipflops using the OHE approach; a
highly encoded state machine would
need just 4 flip-flops. At first glance,
OHE may seem counter-intuitive.
For designers accustomed to using
PLDs, more flip-flops typically indicates either using a larger PLD or
even multiple devices.
In an FPGA, however, OHE yields
a state machine that generally requires fewer resources and has higher performance than a binary-encoded implementation. OHE has definite advantages for FPGA designs
because it exploits the strengths of
the FPGA architecture. It usually requires two or less levels of logic between clock edges than binary encoding. That translates into faster
operation. Logic circuits are also
simplified because OHE removes
much of the state-decoding logic-a
one-hot-encoded state machine is already fully decoded.
OHE requires only one input to decode a state, making the next-state
logic simple and well-suited to the
limited fan-in architecture of
FPGAs. In addition, the resulting
collection of flip-flops is similar to a
shift-register-like structure, which
can placed and routed efficiently inside an FPGA device. The speed of an
OHE state machine remains fairly
constant even as the number of
states grows. In contrast, a highly
encoded state machine's performance drops as the states grow because of the wider and deeper decoding logic that's required.
To build the next-state logic for

I

Article Reprints

STATE MACHINE
DESIGN
leading away from State 4 is
count the number of condivalid whenever the product,
tional paths leading into the
Cantig
State 2
A'B 'C, is true. Consequent·
state and add an extra path
ly, State 4 must be ANDed
if the default condition is to
State 7
remain in the same state.
with the inverse of the prodE
uct, A'B'C. In other words,
Second. build an OR'gate
Clocl<
"keep loading the flip·flop
with the number of inputs
with a high until a valid
equal to the number of con·
transfer to the next state ocditional paths that were decurs." The default path logtermined in the first step.
6. 8-R FLIP-FLOPS OFFER ANOTHER
ic uses AND-7 and shares
Third. for each input of
approach to decoding the Contig output. They can also save
the OR-gate. build an ANDthe
output of AND-6.
logic blocks. especially when an output is asserted for a long
Configuring the logic to
gate of the previous state
sequence of contiguous states.
handle the remaining states
and its conditional logic. Finally. if the default should remain in logic to perform this function is im- is very simple. State 2, for example,
the same state. build an AND-gate of plemented in the gate labeled AND-3 has only one conditional path, which
the present state and the inverse of and the logic elements that feed into comes from State 1 whenever the
all possible conditional paths leav- the inverting input of AND·3 (Fig. 2, product A'B'C is true. However, the
ing the present state.
again).
state machine will immediately
To determine the number of condi·
State 4 is the most complex state in branch in one of two ways from State
tional paths feeding State 1, examine the state-machine example. Howev· 2, depending on the value of D.
the state diagram-State 1 has one er, creating the logic for its next· There's no default logic to remain in
path from State 7 whenever the vari- state control follows the same basic State 2 (Fig. 4, top). State 3, like
able E is true. Another path is the method as described earlier. To be- States 1 and 4, has a default state,
default condition, which stays in gin with, State 4 isn't the initial state, and combines the A, D, State 2, and
State 1. As a result, there are two so it uses a normal D-type flip-flop State·3 feedback to control the flipconditional paths feeding State 1. without the inverters. It does, how- flop's D input (Fig. 4, bottom).
Next, build a 2-input OR-gate-one ever, have an asynchronous reset inState 5 feeds State 6 unconditioninput for the conditional path from put, three paths into the state, and a ally. Note that the state machine
State 7, the other for the default path default condition that stays in State waits until variable E is low in State 6
to stay in State 1 (shown as OR·1 in 4. Therefore, a four-input OR-gate before proceeding to State 7. Again,
Fig. 2).
feeds the flip-flop (OR-1 in Fig. 3).
while in State 7, the state machine
The next step is to build the condiThe first conditional path comes waits for variable E to return to true
tional logic feeding the OR-gate. from State 3. Following the methods before moving to State 1 (Fig. 5).
Each input into the OR-gate is the established earlier, an AND of State
logical AND of the previous state 3 and the conditional logic, which is A OUTPUT DEFINITIONS
and its conditional logic feeding into ORed with D, must be implemented
After defining all of the state tranState 1. State 7, for example, feeds (AND-2 and OR-3 in Fig. 3). The sition logic, the next step is to define
State 1 whenever E is true and is im- next conditional path is from State 2, the output logic. The three output
pie men ted using the gate called which requires an AND of State 2 signals-Single, Multi, and ContigAND-2(Fig.2,again).Thesecondin- and variable D (AND-4 in Fig. 3). each fall into one of three primary
put into the OR-gate is the default Lastly, the final conditional path output types:
transition that's to remain in State 1. leading into State 4 is from State 1.
1. Outputs asserted during one
In other words, if the current state is Again, the State-1 output must be state, which is the simplest case. The
State 1, and no conditional paths ANDed with its conditional path los:: output signal Single, asserted only
leaving State 1 are valid, then the ie-the logical product, A 'B'C during State 6, is an example.
state machine should remain in State (AND-5 and AND·6 in Fig. 3).
2. Outputs asserted during multi1. Note in the state diagram that two
Now/, all that must be done is to ple, contiguous states. This appears
conditional paths are leaving State 1 build the logic that remains in State 4 simple at first glance, but a few tech(Fig. 1, again).
when none of the conditional paths niques exist that reduce logic comThe first path is valid whenever away from State 4 are true. The path plexity. One example is Contig. It's
(A 'B'C) is true, which leads
asserted from State 3 to
ONE-STATE VS.
State 7, even though there's
into State 2. The second path
is valid whenever (A 'B '0 is
a branch at State 2.
BINARY ENCODING METHODS
3. Outputs asserted durtrue, leading into State 4. To
Hamberot
wont....
ing multiple, non-contigubuild the default logic, State
Ioglcbl.....
potfamI...
Method
ous states, The best solution
1 is ANDed with the inverse
One-hot
7.5
40MHz
of all of the conditional
is usually brute-force decodBinary encoding
7.0
34 MHz
ing of the active states. One
paths leaving State 1. The

1

I

I~E~E:BE~IL9~

0

N I

C

DESIGN

7-10

lu'iiH!lliijijl!h'l1i!~j

STATE MACHINE
DESIGN
OHE state machines is simple, lending itself to a "cookbook" approach.
At first glance, designers familiar
with PAL-type devices may be concerned by the number of potential illegal states due to the sparse state
encoding. This issue, to be discussed
later, can be solved easily.
A typical, simple state machine
might contain seven distinct states
that can be described with the commonly used circle-and-arc bubble diagrams (Fig. 1). The label above the
line in each "bubble" is the state's
name, the labels below the line are
the outputs asserted while the state
is active. In the example, there are
seven states labeled State 1-7. The
"arcs" that feed back into the same
state are the default paths. These
will be true only if no other conditional paths are true.
Each conditional path is labeled
with the appropriate logical condition that must exist before moving to
the next state. All of the logic inputs
are labeled as variables A through E.
The outputs from the state machine
are called Single, Multi, and Contig.
For this example, State 1, which
must be asserted at power-on, has a
doubly-inverted flip-flop structure
(shaded region ofFig. 2).
The state machine in the example
was built twice, once using OHE and
again with· the highly encoded approach employed in most PAL designs. A XilinxXC3020-1002000-gate
FPGA was the target for both implementations. Though the OHE circuit
required slightly more logic than the
highly-encoded state machine, the
one-hot state machine operated 17%

State 2
State 1
RD

State 3

Stata2

1

4. ONLY AFEW GATES are required by Stales 2 IDd 3 to form simple slate-

tr...iti.. logic deeodilll. Just two ptes are Deeded by Slale 2 (top), while four simple gates
are used by State 3 (bottom).

faster (see the table). Intuitively, the
one-hot method might seem to employ many more logic blocks than the
highly encoded approach .. But the
highly encoded state machine needs
more combinatorial logic to decode
the encoded state values.
The OHE approach produces a
state machine with a shift-register
structure that almost always outperforms a highly encoded state machine in FPGAs. The one-state design had only two layers of logic between flip-flops, while the highly en-

1

6. LOOKING NEARLY THE SAME .. a simple ahilt recister, the logic for
Stales 6, 6, aod 7 is very limple. This il because the OBE scheme e1imiDates almo.1 all
deeodllllioliclhal precedes eaeh flipoflop.
DESIGN

7-11

coded design had three. For other
applications, the results can be far
more dramatic. In many cases, the
one-hot method yields a state machine with one layer of logic between
clock edges. With one layer of logic,
a one-hot state machine can operate
at 50 to 60 MHz.
The initial or power-on condition in
a state machine must be examined
carefully. At power-on, a state machine should always enter an initial,
known state. For the Xilinx FPGA
family, all flip-flops are reset at power-on automatically. To assert an initial state at power·on, the output
from the initial-state flip-flop is inverted. To maintain logical consistency, the input to flip-flop also is inverted.
All other states use a standard, Dtype flip-flop with an asynchronous
reset input. The purpose of the asynchronous reset input will be discussed later when illegal states are
covered.
Once the start-up conditions are
set up, the next-state transition logic
can be configured. To do that, first
examine an individual state. Then

III

Article ReprInts

STATE MACHINE
DESIGN
such example is Multi, which is asserted during State 2 and State 4.
OHE makes defining outputs
easy. In many cases, the state flipflop is the output. For example, the
Single output also is the flip-flop output for State 6; no additional logic is
required. The Contig output is asserted throughout States 3 through
7. Though the paths between these
states may vary, the state machine
will always traverse from State 2 to a
point where Contig is active in either
State 3 or State 4.
There are many ways to implement the output logic for the Contig
output. The easiest method is to decode States 3, 4, 5, 6, and 7 with a 5input OR gate. Any time the state
machine is in one of these states,
Contig will be active. Simple decoding works best for this state machine
example. Decoding five states won't
exceed the input capability of the
FPGA logic block.

ADDITIONAL LOGIC
However, when an output must be
asserted over a longer sequence of
states (six or more), additional layers
of decoding logic would be required.
Those additional logic layers reduce
the state machine's performance.
Employing S-R flip-flops gives designers another option when decoding outputs over multiple, contiguous states. Though the basic FPGA
architecture may not have physical
S-R flip-flops, most macrocelllibraries contain one built from logic and
D-type flip-flops. Using S-R flipflops is especially valuable when an
output is active for six or more contiguous states.
The S-R flip-flop is set when entering the contiguous states, and reset
when leaving. It usually requires extra logic to look at the state just prior
to the beginning and ending state.
This approach is handy when an output covers multiple, non-contiguous
states, assuming there are enough
logic savings to justify its use.
In the example, States 3 through 7
can be considered contiguous. Contig is set after leaving State 2 for either States 3 or 4, and is reset after
leaving State 7 for State 1. There are
no conditional jumps to states where

Contig isn't asserted as it traverses
from State 3 or 4 to State 7. Otherwise, these states would not be contiguous for the Contig output.
The Contig output logic, built from
an S-R flip-flop, will be set with State
2 and reset when leaving State 7
(Fig. 6). As an added benefit, the
Contig output is synchronized to the
master clock. Obvious logic reduction techniques shouldn't be overlooked either. For example, the Contig output is active in all states except for States 1 and 2. Decoding the
states where Contig isn't true, and
then asserting the inverse, is another way to specify Contig.
The Multi output is asserted during multiple, non-contiguous
states-exclusively during States 2
and 4. Though States 2 and 4 are contiguous in some cases, the state machine may traverse from State 2 to
State 4 via State 3, where the Multi
output is unasserted. Simple decoding of the active states is generally
best for non-contiguous states. If the
output is active during multiple, noncontiguous states over long sequences, the S-R flip-flop approach
described earlier may be useful.
One common issue in state-machine construction deals with preventing illegal states from corrupting system operation. Illegal states
exist in areas where the state machine's functionality is undefined or
invalid. For state machines implemented in PAL devices, the state-machine compiler software usually generates logic to prevent or to recover
from illegal conditions.
In the OHE approach, an illegal
condition will occur whenever two or
more states are active simultaneously. By definition, the one-hot method
makes it possible for the state machine to be in only one state at a time.
The logic must either prevent multiple, simultaneous states or avoid the
situation entirely.
Synchronizing all of the state-machine inputs to the master clock signal is one way to prevent illegal
states. "Strange" transitions won't
occur when an asynchronous input
changes too closely to a clock edge.
Though extra synchronization
would be costly in PAL devices, the
E LEe T

7-12

flip-flop-rich architecture of an
FPGA is ideal.
Even off-chip inputs can be synchronized in the available input flipflops. And internal signals can be
synchronized using the logic block's
flip-flops (in the case of the Xilinx
LCAs). The extra synchronization
logic is free, especially in the Xilinx
FPGA family where every block has
an optional flip-flop in the logic path.

RESETTING STATE BITS
Resetting the state machine to a
legal state, either periodically or
when an illegal state is detected,
gives designers yet another choice.
The Reset Direct (RD) inputs to the
flip-flops are useful in this case .. Because only one state bit should be set
at any time, the output of a state can
reset other state bits. For example,
State 4 can reset State 3.
If the state machine did fall into an
illegal condition, eventually State 4
would be asserted, clearing State 3.
However, State 4 can't be used to reset State 5, otherwise the state machine won't operate correctly. To be
specific, it will never transfer to
State 5; it will always be held reset by
State 4. Likewise, State 3 can reset
State 2, State 5 can reset State 4,
etc.-as long as one state doesn't reset a state that it feeds.
This technique guarantees a periodic, valid condition for the state machine with little additional overhead.
Notice, however, that State 1 is never reset. If State 1 were "reset," it
would force the output of State 1
high, causing two states to be active
simultaneously (which, by definition, is illegal).o
Reprinted with pennission from Electronic Design September 13, 1990.
© Penton Publications.

RON I C

E:XlLlNX

Design In

Reprogrammable Missile:
How an FPGA Adds Flexibility
to the Navy's Tomahawk

By Kent Tallyn
Design Engineer

McDonnell Douglas
Electronic Systems Co.
St. Louis, Mo.

W

would be kept on-board in readhen the McDonnell
only memory.
Douglas Missile SysDepending on the mode of
tems Co. set out to
operation, then, the FPGA can
design the Digital Scene Matchbe configured in mid-flight ing Area Correlator IIA - an
according
to the needs
of the
upgraded guidance subsystem _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _. . system
software.
The concept
for the Navy's conventional L
will have other payoffs in the
land-attack variant of the Tomahawk Cruise Missile - we at PRDGRAMMAILEOmS:Xillftl'llllldpralrammIIlIlHCftllectureltreallldOWflllllGlllre.1:8tqOrlfll-fJDBIOCIca,
future. Five years down the
the Electronic Systems Co., Logic IUtcb, and Prql'llllmablllalercannllCts.
line, if the Navy wants to add
Dew features, they'll be able to
who were given the task,
planned to integrate the unit's logic cruise missile designed to perform stored in memory, and then com- because it's just a matter of loading
functions in a conventional gate a variety of missions. Flying at low pared by the processor to selections new flight software. Hardware need
altitudes and high, subsonic speeds, from' a library of existing pictures not be changed.
array.
That bonus is what led MeDonBut the development cost of gate the missile's range - in any weath- to match the new data to a known
arrays and the lack of hard design er, day or night - is 500 to 700 location. Based on this informa~ nell Douglas to Xilinx's LeA.
specs changed our minds. We need- miles, and it can be launched from tiOD, control signals are generated Unlike some other FPGAs, which
to guide the course of the missile.
can't be reprogrammed, these stated rapid turn~around from the time either surface ships or submarines.
That's where the FPGA, a 4,200- ic-random-access-memory-based
Key to the system's ability to
we made design changes to the
gate
Logic
Cell
_
_
_
_
_
_
_
_ _ _ _ _ parts
permit
complete
its
missions
is
the
Digital
time we had a working part. So we
changes to be
Scene Matching Area Correlator ...- Array from Xildecided to switch.
The conventional gate array plan the DSMAC IIA. That subsystem inx Inc., San
The DSMAC IlA was
made to a syswas scrapped in favor of using a receives video input from an on- Jose,
Calif.
designed to onerate in
tern's logic funcIf'
tions simply by
field programmable gate array, or board camera} digitizes it, and com- comes into the
two modes, depending on reconfiguring the
FPGA, and the payoff was immedi· pares it to pictures previously picture.
McDonnell
the mission at hand.
programmable
ate: McDonnell's engineers could stored in memory. Once a match is
logic in the sysprocess the design from the found, the missile can determine programmed the
tem.
schematic level to a working part its exact location relative to its part to generate
Like a microprocessor, the LCA is
themselves, without having to let lion-course" position and make the timing signals for the digitizer
and the address bits for storage. a program.driven device. The arcmany of the design data leave their adjustments accordingly.
sight. What's more, if initial protoThe DSMAC IIA is based on a The DSMAC lIA was designed to tecture features three rypea of usertypes didn't work or requirements Performance Semiconductor Corp. operate in either of two modes, configurable elements: an interior
changed, they wouldn't have to Mil-Std I750A microprocessor, depending on the mission at hand. array of logic blocks, a perimeter of
worry about the expense and time which first determines the proper But rather than designing aeparate I/O blocks, and programmable
involved with redoing the chip's scan ~ate and passes this informa~ logic for each mode, McDonnell interconnection resources. Configmask layer - change$ could be tion to a set of counters which gen- engineers drew on the pro· uration is established by program·
erate the timing signals for the digi- grammable gate array technology min,g intemal static memory cells
made in software alone.
The conventional land-attack tizer. The video image is passed and designed the system so the that determine the lOgic functiona
Tomahawk is a long~range Navy through a set of digital filters, operating snltware for each mode and interconnectiona. The conliguM

AprillSl90

7-13

III

Article Reprints

_ _ Design In _ _
ration programs can be
loaded automatically at
power-up or upon command at any time.

The functions of the
LeA's configurable logic
and input/output blocks eLBs and lOBs, for short and their interconnections,
are controlled by a program
stored in an on-chip memory. Each eLB contains com·
binatorial logic and storage

registers. The logic section
of the block uses its inputs,
outputs, or hi-directional
pins. Inputs can be programmed to either TTL or
CMOS thresholds. The programmable interconnect
switches connect the
inputs and outputs of eLBs

and lOBs to nearby interconnect and long lines run
the length of the part to
provide low skew paths for
critical signals.
A knowledge of the architecture, although helpful, is
not necessary for designing
with LCAs. Design imple.
mentation software provid.
ed with the system auto·
matically translates a
design into a working part,
enabling the engineer to
work at a PC or worksta·
tion.
The first step in design.
ing with programmable
gate arrays is schematic
entry. Interfaces and
libraries are available for
the most popular schematic

capture systems. Entry
through Boolean equations
or from a variety of state
machine languages is also
supported.
Simulation
Once the design is
entered, unit delay simula·
tion can be performed to
verify the design's function·
ality. Next, the design gets
partitioned into CLBs and
lOBs using a translation
program that lets the user
select the way the part is
mapped: designs can be par·
titioned for performance so that only related logic is
put together on a given cell
- or for density - so that
the maximum level of inte·

7-14

gration can be achieved.
After the design has been
mapped, an automatic
placement and routing pro·
gram determines the opti·
mal placement for the logic
blocks and routes the interconnecting nets. A manual
design editor can be used
here to pre-reroute or
reroute critical signals to
ensure that timing specifi.
cations are met. When
that's done, the part can be
simulated to show potential
performance data and then
implemented in a system.
Solution
Critical issues facing the
DSMAC II design team
included size, development

cost, and rapid turn around.
The field programmable
gate array, selected in a 25·
mil ceramic gull-wing sur·
face-mount package, solved
these problems. In addition,
the Xilinx LCA reconfigurable architecture allows
for future upgrades with no
hardware impact. ...

Reprinted with permission from
MUirary and A61fJspac. Electronics April 1990. a:a990 Sentry PublishingCo.,lnc.,Westborough,MA.

1': XiliNX

Pivoting Monitor
Increases Versatility

Of Workstations
Creating a
pivoting display
monitor requires
the seamless
integration of
mechanical design,
hardware and
solrware.

by Julien llm-Nguyen,
Terry Oyama,
and Nick Moss,
Ra9iuslnc.

ersonal computer
users spend most of
their time with two
application categories: word processing
and spreadsheet. When working with a
word processing application a portrait
display is preferred. When working
with a spreadsheet application a landscape display is preferred. To be able
to effectively use both types of applications, one can buy a larger display.
However, a larger display requires a
larger tube which is more expensive
and also requires more desk space. Another solution would be to create a
compact display which can be used ih
either portrait or landscape mode-a
pivoting monitor.
The goals for creating such a
monitor were:
• High quality display. The.display
has to be very stable (with a refresh
rate of 69 Hz), very sharp (with advanced focus control circuitry), and
gray scale capable (1, 2 or 4 bit!
pixel modes).
• Effortless rotation of the monitor
in real time. The user can easily rotate the monitor without having to
restart the computer or leave the application being used.
• Compatibility with major Macintosh applications.
Mechanics Of The Pivot Monitor
The mechanics of the display allow the monitor to change orientation
in a few seconds effortlessly without
any complicated manipulation.
Similar to the mixer of a cement
truck, the rotation of the pivot monitor
is accomplished on the rear housing.
The front and rear cylindrical sections
rest on a rotation cylinder on the inside of the monitor which turns on
tellon rollers. This rotation ~linder is

7-15

fixed to the monitor case and screen.
The monitor is balanced because the
center of gravity barely moves during
the rotation operation. Using tellon on
the rollers creates a smooth silent surface which wears evenly, outlasting the
life of the machine. The base assembly
is a tilt-swivel type that attaches to the
rear housing.
While the monitor is in portrait
position, the left hand corner of the bezel has a 45° chamfer that allows the
display to be rotated in the complete
forward tilt position.
The ventilation of the monitor has
to work in both orientations. Fans were
not used in the monitor so as to reduce
the noise factor. In order to ventilate
the monitor, the electronics were laid
out taking advantage of the convection
cooling in both orientations. All four
sides of the monitor have ventilation
slots and the bottom part of the case
is lifted off the base allowing air to
come through.
Interface Hardware Design
The image on a CIIT is displayed
by an electron heam scanning quickly
from left to right (fast scan direction),
and slowly from top to bottom, similar
to the way a TV screen works. When a
monitor pivots, the left and right, and
top and bottom references are no longer fixed. The top side in a landscape
mode becomes the left side in the portrait mode.
If the electron beams always
scanned from left to right, the picture
tube would rotate while the dellection
circuitry remained fixed. Enormous efforts would be required to control the
pixel aspect ratio, the picture dimension and position, and the beam
focusing. The advantage would be that
the standard interface board would
work without any major modifications
because the consecutive pixels are also
arranged from left to right in both
orientations.

II

Article Reprints

COMPUTER TECHNOLOGY REVIEW _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

VERTICAL
LINES

HORIZ~~
PIXELS

~

i

~

~

- - - ri~~~c~7t~

....•
----.
....

_ 90" ROTATlON

•

HORIZONTAL
PIXELS

11

FAST SCAN

OIRECTlON

II

Fig lin the Macintosh software graphics format the pixels are accessible along a horizontal line
and are numbered from left to right.

However, the better solution would
be to rotate the entire display housing.
The display electronics do not change
from one orientation to another. The
electron beam scans from left to right
in landscape orientation and bottom to
top in portrait orientation. The deflection circuitry and the picture tube
rotate as a single component causing
the picture geometry to remain the
same. This ensures the best possible
picture quality in both orientations.
The pixel data is stored in Video
RAM on the display controller in the
computer. The display controller sends
the data through the serial port in increasing address from left to right for
the landscape mode. The desired effect
is to keep the serial port along the fastest scan direction, meaning left to right
in the landscape mode and bottom to
top in the portrait mode.
In the Macintosh software graph-

ics interface the pixels are accessible
along a horizontal line and are numbered from left to rillht 0, I, 2, 3, etc.
(Fig I} In the landscape mode the pixels are arranged in the same direction
as the beam scans. In the portrait
mode the pixels are also accessed
along the horizontal lines and numbered from left to right 0, I, 2, 3however, the fast scan direction is now
changed to bottom to top.
Therefore, pixel addresses need to
be renumbered in the portrait mode.
This renumbering corresponds to a 90°
rotation of the pixel addresses. To be
compatible with the Macintosh applications this rotation must be transparent
to the software graphics interface and
performed in real time. In a 90° rotation the top left and bottom right pixel
addresses (e.g. 0 and nw -I) are preserved while the rest of the pixel
addresses are rotated. In other words

Misconvergence In Color Monitors
In a monochrome monitor, the DC component
from the earth's magnetic field can cause the picture
to shift and tilt slightly when the monitor is turned.
The solution is to build a shield around the front face
of the picture tube. However, in a color monitor the
problems caused by the earth's magnetic field are
more complicated, since there,are three electron
beams and they are traveling at a higher energy.
All beams have to land on the face of the display in such a way that the geometry of the image
remains the same. This means that the borders of
the display are straight and the image does not shift
or tilt. In a monochrome display there is only one
beam to worry about. In color display three beams
are used to create one color pixel with all three

7-16

Fall 1990

the pixel address n -I becomes w-I
and (w-I)n become (n-I)w.
The rotation circuitry is part of
the interface board which contains the
memory to store the frame buffers
(Video RAM} It also contains the control circuitry to the interface with the
data bus (1st Translation Xilinx PGA),
the control circuitry to the interface
with the video circuitry which builds
up the video stream (2nd Translation
Xilinx PGA), and the digital to analog
converter which sends the signal to the
monitor (VDAC) (Fig 2} Part of the rotation is performed when the pixels are
sent to memory, and the rotation is
completed when the pixels are sent to
the monitor. The final bit stream sent
to the monitor is at 50 MHz. The bitstream is split into two 25 MHz
substreams in the Translation circuitry.
There are six modes of operation -I, 2 and 4 bits/pixels for the various shades of gray in a portrait
orientation and I, 2 and 4 bits/pixels in
a landscape orientation. The pixel addressing for each mode is different.
The interface board must contain the
circuitry required to translate each of
the six modes. This circuitry, if implemented in a classical gate array, would
require around 6000 gates.
The solution to high density and
high speed requirements was a Field
Programmable Gate Array (FPGA). The
logic for each of the six modes fits into
an 1800-gate device. The monitor operates in one mode at a time and only
1800 gates of logic were needed for
each mode. The reprogrammability
feature of the Xilinx Logic Cell Array
(leA) allowed the monitor to operate
in these six different modes while using
only one logic device. The leA being a
reprogrammable logic device, configuration bitstream determin~s the

C~O~M~P~U~T~ER~T~E:C~H~N~O~LO~G~Y~R~EV~I~E~W~===============:;-_ _ _ _ _ _ _ _ _ _ Fall 1990
BEFORE ROTATION

~

=j

--

HOAIZONTALPIXELS

0

•

3.

1
'+1
3H+1

2
'+2
3H+2

'-3

'-2

'-1

2H-3

2H-2

2H-1

3H-3

3'-2

3H-1

VH-3

VH-2

VH-1

FAST SCAN DIRECTION
(V-1)H

I IV;~)H I (V;~)H I

AFTER ROTATION
VERTICAL PIXELS
SLOW DOWN SCAN DIRECTION

HORIZONlAL
PIXELS

Fig 2 The rotation circuitry is part of the interface board which contains memory to store the vid-

eo RAM.

functionality of the device. A position
Earth's Magnetic Field
sensitive device (somewhat like a mercury switch) is used to detect which
When designing a monitor, the
direction the monitor is in, either porearth's magnetic field has an influence
trait or landscape. An interrupt is sent
on the quality of the picture. The deto the system software to tell it that the flection inside the picture tube is based
monitor is changing direction. The sys- on an AC magnetic field. On top of the
tem software determines which of the
AC magnetic field is the earth's DC
six configuration bitstreams should be
magnetic field. When the monitor is
loaded and then automatically loads it
turned on its side the DC noise can
into the FPGA. The FPGA is reprocause the picture to shift and tilt
grammed in one msec while the softslightly. The DC component is normally
ware is updated to the new mode.
compensated for before the monitor
The LCA reduced the amount of
leaves the factory. To alleviate this
gates which needed to be used. In adproblem a silicon steel magnetic shield
dition the FPGA made the developing of is placed around the front face of the
the hardware much easier. Each of the
picture tube. This shield also contains
six modes of operation could be devel- the deflection field inside the display,
oped separately eliminating fringe
therefore minimizing radiation leakage.
effects from the clock loading from the As a consequence, interference from
other modes which allowed the circuit other displays will also be reduced.
to run at the required 25 MHz.
In color monitors the probiems
caused by the earth's magnetic field are
more complicated because there are
more electron beams traveling with a
higher energy.

Software Development
Once the monitor is rotated, the
software needs to tell the system that
the shape of the desktop has changed.
The desktop is the graphical metaphor
used by Apple to represent the computer display.. On the desktop there
are windows with applications, and
icons representing these applications
windows which are closed. Any application running on the desktop can
query the system as to the size of the
new desktop.
In addition, a cleanup is performed moving the icons on the
desktop to a location where they Can
be accessed. When the display is rotated the shape of the desktop is
changed. The system icons in the common area of rotation remain the same.
However, the system icons in the removed area must be relocated. In Fig 3
the system icon is illustrated with the
Macintosh Trashcan icon. For example,
if the monitor is in the portrait mode
and a system icon is located in the bot·
tom right of the desktop, it will be
rqpved to the upper right hand of the
screen when the monitor is rotated to

Fig 3 When the display is rotated, the system
icons in the common area of rotation remain'
the same.

II

7-17

Article Reprints

~CO,:M~PU~T':ER':.T~E::C::H~N~O,,=lO~G~Y~R~E~V~IE~W:,=================;--=:=====-=-=-==
(0)(640)

(OxO)

(Ox 884)

(OxO)

-

FL1P

(863x839)

(863)(1503)

(863)(1219)

Fig 4 Global coordinates of the other displays may also need to be updated to maintain overlapping, nOA-contiguous characters.

the landscape position allowing it to
be accessed.
Multiple Screen Support
Another complication to the software is that the Macintosh supports a
multiple monitor display mode. This is
where two or more monitors can be
placed side by side in order to provide
a contiguous drawing area (Le. there
are no gaps between the monitors allowing the user to move the mouse
freely between the displays). Each
screen has its own local coordinate
system which is translated into global
coordinates for drawing. When the operating system builds the desktop from
the available display, it assigns their
global coordinates such that the displays do not overlap and the drawing
space is continuous.
When the monitor is rotated, some
desktop area is added and some is removed. Not only do the local coordinate systems of the display change,
the assignment of the global coordi-

nates of the other displays may also
need to be updated to insure that the
display maintains their contiguous,
non-overlapping nature (Fig 4).
The rotation of the left-hand display causes the local and global
coordinates to change from (top: 0,
left: 0) and (bottom: 863, right: 639) to
(0,0) and (639,863). The right-hand
display's global coordinates change
from (0,640) and (863,1279) to (0,864)
and (863,1503).
The window on the desktop's coordinates change from (100,800) and
(700,1100) to (100,1024) and (700,1324)
after the flip.
Software Application Support
When the monitor pivots, most applications will truncate the portion of
the window that no longer exists in the
new orientation. A small number of applications which bypass the systems
software graphics interface, QuickDraw, and directly manipulate the
display's video frame buffer, render a

7-18

Fall 1990

scrambled mess on the screen.
The goal is to work with the software development community to take
advantage of the new orientation by automatically adjusting the window. This
means that when the display is rotated
the application detects the pivot,
moves and resizes the windows to take
advantage of the new screen size.
Utilizing hooks installed in the operating system, applications can query
the status of the display to detect a pivot. For each of its windows, the
application can then request a hint, a
message returned to the application
containing a location and size for the
window which makes optimum use of
the new desktop shape.
However, a vast majority of the applications work with the pivot monitor
without any modifications. The hooks
available from the operating system
will allow these applications to have
additional functionalities.
Creating a pivot display monitor
was made possible only through the
tight and seamless integration of the
mechanical design, the hardware and
the software. The mechanics of the
monitor make rotation a simple onehand operation. The reprogrammability feature of the Xilinx LCA
allowed the monitor to operate in six
different modes using only one reprogrammable logic device. The
software made the desktop dynamic,
allowing applications to take full advantage of the display space. •
Reprinted with permission from the Publisher
from the Fa1l1990 Computer Technology
Review.

FJeOO'onic Engineering

TIMES

Two, Two, Two Chips in One

By Tom Liehe, Principal Design Engineer, Test Instrument Division, Honeywell Inc., Denver, Colo.

Designers at Honeywell picked the RAM·based Xilinx
LCA for Its short development cycle, and realized
savings In board real estate through its dynamic
reprog rammabillty.

Errors on tape typically are caused by tape defects, dirt,
head clogs, etc. Because these error bursts can be
thousands of bits long, sophisticated EGC techniques are
required. Initially, two basic circuits, using Reed-Solomon
algorithms and TTL technology, were designed. These
were the ECC encoder and decoder.

Advances in one technology often lead to improvements in
other, more dated design and manufacturing practices. A
recent example of this occurred at Honeywell during the
development of a high-capacity digital tape recorder.

The write portion of the circuitry (the encoder) uses a bytewide linear feed-back shift register (LFSR) to create a
68-byte code word form each 64-byte incoming message
block. During operation, parity check bits are computed
based on the data within a block of the message to be
encoded. These check bits are appended to the block to
create the code word.

Honeywell's original objective was to design the VLDS
(very large data storage) recorder, taking maximum advantage of the available analog technology currently being
used in standard VCRs for home use. The recorder
developed under this program uses digital rotary technology to record large amounts of data on a standard VHS
video cassette. It transfers data at a rate of 4 Mbauds, and
is able to store 5.2 Gbauds of information on a single BHS
tape. Its major planned application is in capturing and
storing digital medical images, such as those produced by
a CAT scanner.

During decoding, the code words are checked for errors by
regenerating the parity bits which are then compared with
the check bits. If they match, it is assumed that no errors
have occurred. If they do not, the pattern of mis-matches
(called the syndrome of the error) is used to compute the
corrected form of the message block.

When this recorder was in the prototype stage, it became
apparent that the addition of an error-correction circuit
would significantly enhance system performance. This
requirement dictated the design of an entirely new and
major logic circuit to accomplish the desired error correction.

The ECG decoder (the read circuit) required a partial
syndrome generator and the solution of a set of simultaneous non-linear equations to determine error locations and
values. This error-determination step is performed by a
special-purpose processor with a microinstruction sequencer, a finite field arithmetic unit, two discrete registers
and an eight-word memory. The correction step is then
accomplished in circuitry whereby the error values are
exclusive-ORed with the message atthe address given by
the previously computed error locations.

Design of this circuitry would not normally be a problem,
but at this stage of development, there were several
challenges. First, the design allowed almost no circuit
board space for addition olthe error correction code (ECC)
circuitry. Second, very tight deadlines were being faced if
the promised delivery date was to be met.

Using wrapped-wire techniques, a working prototype of
the ECG circuitry was developed. However, it was quickly
recognized that the long lead time required to design and
fabricate a factory-programmed gate array to replace this
prototype TTL circuit was not practical with the tight
delivery schedule.

The entire system was housed in a 19-inch-wide by
20-inch-deep rack-mounted cabinet. The cabinet already
contained eight separate circuit boards, and there was
room enough for only one additional board to incorporate
the ECC circuitry. Space was at a premium. The goal was
to design and manufacture a 10-12 corrected bit error rate
circuit that could be contained on one circuit card. The
targeted time for completion of this work was three
months.

An option considered, but not chosen, was to design and
fabricate a conventional gate array. The considerable
design time required, together with the inherent risks
aSSOCiated with masking and manufacturing a custom
logic circuit, made this an unattractive alternative.

7-19

II

Article Reprints

XILlNX'S LCA

ANOTHER BENEFIT

Finally, the search for an alternative solution led to the
discovery of a programmable gate array known as the
logic cell array (LCA) , designed and manufactured by
Xilinx Inc. (San Jose, Calif.). The LCA is a standard, offthe-shelf device that is custom configured to the
customer's requirements by means of the Xilinx development system. This development package consists of a
personal-computer-based software system combined
with an in-circuit emulator.

Another significant benefit derived from the use of the
Xilinx LCA was reduced power consumption. The original
bipolar IC design consumed approximately 12 W of power.
Through the use of CMOS technology, the replacement
LCA consumes only 50 mW of power. It should be pointed
out that the bipolar version was capable of operating at
a much higher clock rate than the LCA. However, the clock
rate used this particular design was only.2 MHz. The
speed of the LCA was, therefore, adequate for the VLDS
application.

Use of the LCA seemed to be the ideal solution to the time
constraints. So, a Xilinx XC2064 LCA was sected. In this
device, any logic function having up to four variables can
be implemented in anyone of the 64 configurable logic
blocks (CLBs). Optionally, results can be stored in either
a latch or a flip-flop. Thus, implementation of the design
can be constrained by a fixed set of standard logic elements.

Because the required logic circuitry was already designed
and tested, the development of the configuration program
for the LCA went very smoothly. It took only two days to
configure the circuit using the Xilinx XACT LCA development system running on a standard, IBM-compatible personal computer. The primary effort involved was the
partitioning olthe logic to match the capabilities olthe LCA.

The 1/0 pins of this device also can be configured as
registered inputs. The large number of flip-flops, plus the
ability of each CLB to function as four-input exclusiveORs, made this LCA ideal for ECC circuit implementation.

For a regular, repetitive design, a small portion of the logic
was defined. This portion was then copied and minor
modifications were made to complete the design. The
byte-oriented nature of the RS ECC circuitry lent itself to
easy entry. Starting with tables showing the bits to be
exclusive-ORed, the entire circuit was entered in a few
hours.

MULTIFUNCTION CAPABILITY
One of the real benefits of this LCA is its multifunction
capability. The capability of performing a number of
functions with the same device provides optimum utilization of circuit board space. This was a real bonus with the
VLDS recorder. At any given time, the VLDS operates in
only the read or the write mode-it is never required to do
both simultaneously. Consequently, the same LCA could
be reconfigured electronically to perform one function in
the write mode, and a completely different function in the
read mode. This versatility eliminated the need for two
separate circuits, and thereby conserved space.

The software simulation capability, which enabled the
modeling of physical delays and logic functions, resulted
in a very high design confidence factor before the first
hardware checkout. The simulator provided both tabular
output and logic analyzer style waveforms, which aided
considerably in the visualization of the circuit performance. A high-level language program was used to generate expected results of the encoder, and to perform
partial syndrome generator simulations. This greatly
aided the evaluation of the simulation output.
By using the in-system emulation feature, configurations
were loaded directly from the PC to an LCA mounted in
the target system. Thus, the usual step of programming
an EPROM from which the LCA can boot itself was eliminated. Initial design checkout of the ECC circuitry was
performed using the emulator connected to the wrappedwire board containing the discrete IC version.

The LCA has a usable density of 1,000- to 1,500-gate
equivalents, and is capable of replacing up to 75 SSI/MSI
devices, five to 15 PAL-type devices, or some combination
of both. In the VLDS, the entire ECC encoder and the
partial syndrome generator portion of the ECC decoder
were replaced by the LCA. The initial encoder circuit used
eight identical PALs, each of which implemented a 1-bit
slice of the shift register, and four PROMs. The original
partial syndrome generator design used six PALs and four
74LS374 tri-state octal flip-flops to store the four syndromes. Thus, the LCA replaced a total of 14 PALs, four
256k x 8 PROMs and four 74LS374s, or a total of 22
20-pin DIPs.

There was a problem with the encoder circuit that was
delaying data for an extra byte. Correcting this problem
required removing the input flip-flops on the LCA. The
entire process of reentering the LCA editor, removing the
mouse and reloading the new configuration took no more
than five minutes.

7-20

Compared with the time required to rework any other type
of hardware, the LCA is the only way to go. Also, taking into
consideration the high costs associated with reworking a
factory-programmed gate array, or even a semi-custom
PLD, the LCA technology is an extremely cost-effective
alternative.

using equivalent discrete ICs. And finally, the ability to
perform design entry, simulation, emulation and in-system
testing through the software development system facilitated quick and easy implementation of the user's ideas.
Today, the Honeywell VLDS offer error correction as
powerful as most major computer tape subsystems. It is
ideally suited for the newly developing imaging technologies used in electronic office documents, advanced geophysical analysis and computer-aided graphic arts. Without the Xilinx logic cell array however, Honeywell could still
be waiting for a custom gate array.

In summary, the Xilinx part was well suited for our application because of its high flip-flop count and its ability to be
configured in exclusive-OR trees. Additionally, its capabilityof being electronically reconfigured while in the system
(when switching from write to read) offered significant
savings.

Reprinted with permission from Electronic Engineering
Times.

Further, power consumption was much lower than when

II

7-21

ESD:

LeA Stars in Video

THE ElectroniC System Design Magazine

by Rusty Woodbury, Interactive Educational Video, Salt Lake City, UT.

mines how to increment the counter. All of these functions,
plus logic to generate the read/modifylwrite cycle timing,
are implemented in a single LCA that replaces nine MSI
parts, four of which are PLDs.

Reprinted with permission from ESD: The Electrical System Design Magazine.
The market for tools and overlay products for video pictures generated from laser disks is in its infancy. Applications for this emerging video-based technology can require high resolution and high performance, and the wide
variety of video disk players employed means that problems associated with varied noise characteristics must be
overcome. What works with one particular brand and
model in the factory may falter with another brand in the
field.

Two more LCAs implement a three-bit ALU. This technique achieves ultra-high-speed screen writes for both
horizontal and vertical lines. For many applications, these
are the most common lines drawn, so a special control bit
is used to simultaneously modify pixels. Horizontal lines
can be written at 14 Mpixels/sec instead of the normal
2 Mpixels/sec-a seven-fold improvement. Though more
logic could be placed in these two devices, a bit-sliced logic
approach permits continuous enhancements. Moreover,
a board layout can be defined at the beginning of the
product cycle while logic enhancements are made internally in the LCA. Nearly 30 SSIIMSI devices were integrated into the LCAs.

The Xilinx Logic Cell Array (LCA) helps to solve the
problem of meeting different system requirements because the device elevates hardware to the same level of
programmability as software. Before the LCA, once a
design had been committed to hardware, revisions to the
design could only be implemented via software changes.

A fourth LCA fully implements the graphics engine. To
read out data to the screen, scan counters point to memory. A shift register serializes at a rate of 14 Mpixels/sec.
Using traditional MSI devices, these functions require
about 10 chips.

Interactive Educational Video (lEV) has implemented
three separate designs and logic replacements with the
LCA. These functions reside on IBM PC expansion cards,
where space limitations would ordinarily preclude such a
design. Although application-specific video ICs could
perform similar functions, they cost more than the LCA and
offer lower performance.

The second design fabricated by lEV is a graphics controller (Figure 6). Using an external genlock IC, the LCA
relies on an NTSC composite sync signal to generate
timing signals forthe CRT display. Instead of using PLDs,
lEV uses the LCA to implement digital counter and timers.
The result is higher performance and reduced complexity.
The previous generation board has only half the functionality and demands four times the board space. To further
reduce complexity, the same hardware can be used with
a different configuration program to match a particular
video disk player's noise characteristics. Without the LCA,
this design needs eight PALs plus 12 to 15 MSI devices.

The first application is a graphics engine that uses four
LCAs. Here, the LCAs replace over 50 SSI/MSI chips,
including four traditional programmable logic devices
(PLDs).
One LCA functions as the address generatorforthe video
memory. By relying on a pair of high-speed counters to
locate horizontal and vertical coordinates, memory write
functions (which implement line drawing) can perform at
high rates. Given the slope, starting point and length of
a line, the logic simply increments counters that point to
video memory locations. Scanning and writing to the
screen are interleaved. The data written to memory
corresponds to a particular color and, by simple incremental additions to the slope of the address pOinter counters, powerful line drawing functions are easily implemented.

In another I EV design, a PC serial port emulator integrates
a subset of the IBM PC serial port functions onto the
graphics card, making an IBM serial card unnecessary.
With the given space restrictions, this implementation
proves particularly cost-effective. Seven PLDs are required to match this design.
Reprinted with permission from ESD: The Electronic System Design Magazine.

Important to the design is the decision logic, which deter-

7-22

XC2064 LOGIC CELL ARRAY
ADDRESS
AND
CONTROL

GRAPHICS
OVERLAY
VIDEO
DOT
CLOCK

--7-.-1

COMPOSITE
SYNC
INPUT

EXTERNAL

COMP~~I~~

---=------.-----.-1

TV
CAMERA
SYNC
GENERATOR

INPUT
VD

HD

14.318 MHZ
INPUT
FROM 3301

--7---1

FROMXTAL

--7---1

1---7--HB

1---7-_BFW

1 - - - - - - . ; . -....

DATA
BUS

GVB

1---;-_ GHB

II

1148 13

Figure 6. lEV implementated an itelligent Graphics Overlay Controller microprocessor peripheral with one XC2064 Logic Cell
Array, replacing eight PALs and 12 MSI devices. The controller generates all timing for a video graphics overlay by deriving the
necessary timing from the underlying video disk signal.

7-23

Taking Advantage of
Reconfigurable Logic
An abbreviated version of this paper was published in the High
Performance Systems Programmable Logic Guide, 1989.

by Bradly K. Fawcett, Xilinx Inc., San Jose, CA

suit is smaller, more powerful, less expensive, and more
reliable systems. As an added benefit, use of reconfigurable LCAs simplifies hardware design and shortens a
product's time-to-market.

The availability of programmable logic devices based on
static memory cells now allows the implementation of
"soft" hardware-hardware whose functions can be
changed while resident in the system. When using most
current IC component technologies, hardware is indeed
"hard"; once a given logic function is implemented in
hardware, changing that logic is difficult, requiring modifications to printed circuit board traces, the addition or
replacement of components, and other costly measures.
However, with static-memory-based programmable logic,
changes can be made to a system's logic functions simply
by reconfiguring the programmable logic in the system.
This capability can lead to significant advantages for the
system designer. These include both product-related benefits, in the form of smaller, less expensive, and more
reliable systems, and design-related benefits, such as
increased design flexibility, decreased risk, and faster
design cycles.

RECONFIGURING FOR SYSTEM DIAGNOSTICS

System self-diagnostics can be implemented by using
programmable gate array configurations dedicated to testing functions. When the system is powered-up or placed in
a test mode, its programmable gate arrays are configured
with logiC functions dedicated to testing other circuitry in
the system. Once the testing is successfully completed,
another configuration program is loaded into the programmable gate array to implement the actual logic of the
particular end application intended for that system. Typically, very little additional logic is required to. add selfdiagnostic functions in this manner (usually Just some
additional memory to hold the extra configuration programs). Such self-diagnostic capabilities make products
easier to manufacture, increase system reliability, and
simplify system maintenance, with little, if any, additional
cost.

Programmable logic devices capable of being reconfigured in the system are available to system designers in the
form of programmable gate arrays from Xilinx, Inc. The
Xilinx Logic Cell Array (LCA) architecture features three
types of user-configurable elements: an interior array of
logic blocks, a perimeter of 1/0 blocks, and programmable
interconnection resources. Configuration is established
by programming internal static memory cells that determine the logic functions and interconnections. The cohfiguration programs can be loaded automatically at powerup or upon command at any time. Several available
configuration loading modes accommodate various system requirements. The benefits of a static-memory-based
device include high density, high performance, testability,
and the flexibility inherent to a device that can be programmed while resident in a system. Designers have
taken advantage of this capability in a wide range of
applications.

Designers at Tellabs Inc. (Lisle, IL) used this strategy in a
voice compression module, an optional unit for the
Crossnet 440 T1 multiplexer. The design includes two
XC2018 devices, 1800-gate programmable gate arrays
(Figure 1). During normal operation, one LCA provides all
the interface logic for the board's microcontroller, RAM,
and system backplane, arbitrating accesses to the RAM
from the controller and the main system. The second LCA
contains most of the "glue logic" for the data compression
operation. However, both LCAs can be loaded with special
diagnostic configurations. In the test mode, the first LCA
connects the microcontroller to the RAM for memory
testing, and monitors controls on the system backplane.
The second LCA can receive timing information from the
microcontroller instead of the system backplane, verify the
data paths, and check the contents of the 32K-bit EPROM
used to implement the code converter's companding algorithm. Actually, two different test configurations have been
generated, and other diagnostic LCA configurations are
planned for a future upgrade. All the configurations are
present in memory on the board; the microcontroller
handles the downloading of LCA configuration programs.

The flexibility inherent in reconfigurable Logic Cell Arrays
(LCAs) can be used to create systems that are also more
flexible and, therefore, more powerful. Often systems will
include multiple configuration programs for their LCAs,
allowing varying operations to be efficiently performed
with a minimal amount of hardware. For example, reconfigurable logic can be used to implement system selfdiagnostics, create systems capable of being reconfigured
for different environments or operations, or implement
"dual-purpose" hardware for a given application. The re-

7-24

system with logic that selects the appropriate configuration at the appropriate time. Many different types of applications benefit from this approach.

ADAPTABLE SYSTEM DESIGNS

A similar use of reconfigurable logic is the implementation
of a single hardware design that can be adapted for varying
tasks or environments. In such systems, any of a number
of potential configuration programs can be downloaded
into a system's LCAs to alter the logic for particular
applications or operations as needed. Hence, more functions are implemented with fewer components, hardware
design costs can be amortized over a greater number of
systems, and design cycle times are greatly reduced. The
manufacturer could select the configuration program to be
included in the system dependent on the intended end
application or customer, or, alternatively, all the different
LCA configuration programs could be included in the

The Freeland Medical DiviSion of Good Technologies Inc.
(Indianapolis, IN) used reconfigurable LCAs in this manner when designing a "frame grabber" board for the Cine'
View family of digital imaging systems. A mix of seven
XC2064, XC2018, and XC3020 LCAs are used on this
AT-format board, providing graphics control and interfacing a PC-compatible computer to the video output of
medical eqUipment such as ultrasound scanners and
magnetic resonance imaging systems. In order to support
different video formats from the varying types of medical
instruments, several different LCAconfiguration programs

MICROCONTROLLER

ti

"-

256 x 4

XC2018

v

"

ADDRESS + CONTROL

DATA
"-

LCA

1953 01

RAM

CHANNEL
SIGNALING

An LeA contains interface logic for the micro-controller, memory, and system backplane.

MICROCONTROLLER

rt
XC2018 LCA
TIMING
TIMESLOT
AND
CONVERSION
CONTROL

I'LAW
DATA

f1

CODE
CONVERTER
ROM

A

'"

"

LINEAR DATA

NIBBLEI
TIMESLOT
INTERCHANGE
LOGIC

1
DSP

1953 02

A second LeA implements the glue logic for the data compression circuit.

Figure 1. LeAs in a voice compression system can be reconfigured to implement internal system diagnostics.

7-25

•

Taking Advantage of Reconfigurable Logic

are available for the LCA devices in the system. When
system operation begins, the user selects the desired
video format (monochrome or RGB color, for example);
the appropriate LCA configuration program is then loaded
to match that format. Thus, one hardware design can
support virtually any video format, without having to include customized hardware for each one.

logic consists of an 8051 microcontroller and a 3000-gate
XC3030 LCA; four channels are implemented on each
card. Using a keyboard, the user can select from among
three communication protocols for each channel: a Data
Service Unit (DSU) interface, an Office Channel Unit
(OCU) interface, or a secondary-mode OCU interface
(Figure 2). A fifth 8051 processor controls the user interface and the downloading of the appropriate LCA configuration programs.

A similar scheme was used on Tellabs' channel interface
cards for the Cross net 440 T1 muHiplexer. Each channel's

r-

PARALLEL·TOSERIAL SIR

8051
PROCESSOR

I-- -

8-BIT SELFCENTERING FIFO

-

CLOCK

t - --+ DATA

XC3030 LCA

SERIAL-TOPARALLEL SIR

L--

8-BITSELFCENTERING FIFO

-

~-

CLOCK

~-

DATA

1953 03

DSU mode block diagram

~

RETURN-TOZERO
GENERATOR

BIPOLAR
VIOLATION
GENERATOR

PARALLEL-TOSERIAL SIR

8051
PROCESSOR

r----r-----

DATA +
DATA -

XC3030 LCA

i4--

SERIAL-TOPARALLEL SIR

I--

TRANSPARENT DATA AND
CONTROL CODE TRANSLATER

I+---DATA+
!---DATAI+----CLOCK

3-BIT
FIFO

I--

1953 04

OCU mode block diagram

--.,

T
8051
PROCESSOR

-

RETURN·TO·
ZERO
GENERATOR

PARALLEL-TO·
SERIAL SIR

I
I

FRAME BIT
GENERATOR

I

FRAME SYNC
RECOVERY

SERIAL·TO·
PARALLEL SIR

I

~

ff-

DATA +
DATA-

XC3030 LCA

3·BIT
FIFO

-

~ -~

Secondary OCU block diagram
Figure 2. By reconfiguring an XC3030 LCA. each channel in a multiplexer from
Tellabs can implement any of three communication protocols.

7-26

=:

DATA +
DATACLOCK

1953 05

Several other applications involving the use of Xilinx LCAs
to implement adaptable hardware have been described in
recent articles:

Reconfigurable logic can be used to adapt add-in circuit
boards to the environment of a particular computer. In
such systems, configuration programs can be downloaded by the host processor (from a floppy disk or
modem, for example), allowing simple installation procedures and easy field upgrades. Several recently announced personal computer products illustrate this capability. Buffalo Product's (Salem, OR) More Memory memory expansion card for PC/XT or PC/AT compatible systems employs a 1200-gate XC2064 LCA for the bus and
memory interface and control logic. An installation program analyzes system parameters (bus width, type of card
slot, available address spaces, etc.) and then loads the
appropriate configuration program to match the system's
requirements. Similarly, the Mach II/SE (Figure 3), an
accelerator board for the Macintosh II from Dove Computers (Wilmington, NC), uses an XC2018 LCA for all its
interface logic; different LCA configurations are used to
support different memory sizes and speeds. The
MultiScreen card from Mobius Technologies Inc. (Oakland, CAl, a monitor interface board, includes an XC2018
LCA for controlling the video output. Different LCA configurations support different monitor types, allowing for variations in timing requirements and screen resolution. As new
monitors are introduced in the market, additional LCA
configuration programs will be developed and distributed
on floppy disks.

• Tektronix Inc. (Wilsonville, OR) employed an XC2018
LCA for the printer interface logic in their Phaser Card
printer controller.l Interfaces to several different types
of printers can be implemented through reconfiguration
of the LCA.
• The FASTPACKET data multiplexer from Stratacom
Inc. (Campbell, CAl uses LCAs to incorporate its four
serial channel interfaces.2 Different communication
protocols can be accommodated through reconfiguration of the LCAs. A special configuration of the LCAs
also provides for bit error rate testing without the use of
external test equipment.
• Reconfiguring an LCA in a graphics controller for a
laser disk system from Interactive Educational Video
(Salt Lake City, UT) allowed a single hardware design
to be matched with various video disk players' noise
characteristics. 3
• GTECH Corp. (Providence, RI) designed a lottery betslip reader using LCA technology that can be reconfigured to accommodate variations in bet-slip size and
format without hardware alterations. 4

II
Figure 3. The Dove Computer Mach IIISE includes a micro-processor, floating-point co-processor, memory, bus drivers, and an
LCA that holds all the interface logic.

7-27

Taking Advantage of Reconfigurable Logic

the test patterns and the pins of the memory device being
tested. Different LCA configurations are used for testing
different types of memory devices. An extended vector
memory option uses an XC2018 LCA as a FIFO buffer
between the extended memory and the pattern control
logic. Upon command, this LCA can be reconfigured to
create a cyclic redundancy code (CRC) checker used to
verify the test patterns stored in the extended memory.

CONFIGURABLE TEST EQUIPMENT
In a similar manner, programmable gate arrays often are
used to implement configurable test equipment, wherein
different LCAconfigurations are used to program the same
hardware to perform varying types of tests.
Innovage Microsystems (Calgary, Alberta) chose programmable gate arrays for test circuitry used in the Fluke
90 Series (John Fluke Mfg. Co., Everett, WA) and Innovage Microsystems' own Tracer-4 series of microprocessor board testers. These portable test instruments facilitate the trouble-shooting of microprocessor-based
boards; testers are available for a number of popular
microprocessor types (Z80, 8086, etc.). As shown in
Figure 4, an LCA provides interface and control logic
between a resident microcontroller and the unit-under-test
interface card. An 1800-gate XC2018 LCA is used in the
8-bit series, and a 2000-gate XC3020 is used in the
16/32-bit series of testers. Different configuration programs are stored in the system's ROM during production,
dependent on the type of microprocessor targeted for that
tester, allowing the same basic hardware configuration for
all tester types. A keypad allows the user to choose from
a variety of pre-programmed trouble-shooting modes; the
microcontroller downloads one of seven different available
configuration programs to the LCA, dependent on the type
of test selected. Use of the LCA allowed Innovage
Microsystems to increase the functionality of their testers
while reducing the number of components by 49%, as
compared to previous models.

Designers of telecommunications test equipment have
also discovered the advantages of reconfigurable logic.
Three LCAs are used in the PC-based TC2000-B1
T1/PCM tester from LP Com, a Tektronix subsidiary
(Mountain View, CAl. The LCAs provide clock and timing
generationforthe receiverltransmitter, interface logic, and
bit error generation logic. The logic can be altered by
downloading different LCA configuration programs to
support several user-selected operating modes. When
analyzing DS1 lines, any standard framing mode can be
selected (D1 D, D2, D3/4, or ESF). In DS1 bit error testing
(BERT) mode, any AT&T standard or user-defined test bit
pattern can be specified. The use of reconfigurable LCAs
allowed the logic to be packed into just two boards; LP
Com engineers estimate that the design would be at least
twice as complex with traditional logic devices.
Sage Instruments (Freedom, CAl used a similar strategy
in their Model 930A Communication Test Set, a general
purpose channel access test system. Four LCAs are used
to implement data interface, channel signalling, diagnostic, and microprocessor interface functions, respectively.
The LCA that handles channel signalling has two possible
configurations to support two different signaling formats,
RBS (robbed-bit signalling) and DMI (digital multiplex
interface). The data interface and channel signalling LCAs
are both reconfigured to support bit error rate testing.

Semiconductor Test Solutions (Santa Clara, CAl included
reconfigurable logic in several optional units for their STS
6000 and 8000 series of Sentry-compatible IC testers. For
example, an optional memory test unit uses the XC2018
LCA to interface between the internal memory that holds

SYSTEM
PROCESSOR
.t.

~

XC2018

01'1
XC3020
LCA

~

UNIT·UNDER·
TEST
INTERFACE
CARD

?-

A

"

" r'-'
TEST CLIP v
'--UNIT UNDER TEST

,I

(ROM)
CONFIGURATION
FILE #1

j\

II
CONFIGURATION
FILE #2

I

•••

I

CONFIGURATION
FILE #7

MICROPROCESSOR BOARD TESTER
195306

Figure 4. In Innovage Microsystem's microprocessor board tester, an LeA is configured for the appropriate
microprocessor type and selected diagnostic test.

7-28

E:X!lINX.
By reconfiguring a 3000-gate XC3030 LCA, an errorcorrection channel designed by Wiltron Co. (Morgan Hill,
CAl can support either of two error checking and correction (ECC) formats, one for Digital Data System (DDS) and
one for Adaptive Data Port (ADP) network configurations.
The circuit is incorporated into several products, including
Wiltron's Model 9966 Digital Services Test Unit for testing
DDS-like services. Use ofthe LCA also provides insurance
against evolving standards; new LCA configuration programs can be developed if standards for ECC formats and
network configurations change.

when writing data to the tape, and then reprogrammed to
perform a different function when reading from the tape.
Honeywell's Test Instruments Division (Denver, CO) incorporated this scheme in their VLDS (Very Large Data
Storage) recorder.5 An XC2064 LCA is configured to perform error code generation in write mode, and then
reconfigured to perform error code checking and correction in read mode. This type of application is especially
cost-effective; about twice the logic would be required to
implement the same functions with traditional logic devices.
A similar strategy can be used in the design of most logic
analyzers, microprocessor in-circuit emulators, and similar test eqUipment. Each involves the monitoring and
control of nodes within the system being tested. In the
"acquisition mode", the target system is active and a
record of the target's activity is stored in a memory buffer
called trace memory. Trigger and breakpoint logic specifies when tracing begins and ends. A history of the system's operation can then be read from trace memory and
displayed to the user, the "analysis mode". In an LCAbased system, programmable gate arrays could be used
to implement the multiplexer, registers, and comparators
of the trigger and breakpoint logic, interface to the system
under test, and controlthe writes tothe trace memory while
in acquisition mode. Those same LCAs could be reconfig-

DUAL-PURPOSE HARDWARE
In the examples sited above, programmable gate arrays
are reconfigured to implement internal system diagnostics, adapt a circuit to the external environment, or completely change the functions of a system. Some logic
designers have taken this concept one step furtherprogrammable gate arrays are reconfigured as part of the
normal operation of the system.
For example, at any given time, a tape recorder can either
read or write, but it never does both simultaneously.
Consequently, a programmable gate array within a digital
tape recorder could be configured to perform one function

ADDRESS

'"
y

DATA

SYSTEM
UNDER
TEST

...

DATA
INPUT
CAPTURE
LOGIC

...

TRIGGER
AND
BREAKPOINT
LOGIC

CONTROL

MEMORY
ADDRESS
GENERATION
+
CONTROL

'"
y

TRACE
MEMORY

CONTROL",
y

CONTROL

...
CONTROLLER
y

'"

PGA
ACQUISITION MODE

ADDRESS

'"

DATA

'"
y

SYSTEM
UNDER
TEST

USER
INTERFACE
CONTROL

...

PGA

CONTROL

'"

MEMORY
ADDRESS
GENERATION
+
CONTROL

...
'"

TRACE
MEMORY
CONTROL

A

...
195307

DATA

'"

CONTROL J>.
CONTROLLER

ANALYSIS MODE

Figure 5. An LeA can be reconfigured to support both acquisition mode and analysis mode operations in a logic analyzer.

7-29

II

Taking Advantage of Reconflgurable Logic

ured to control reading trace memory and displaying its
contents when in the analysis mode (Figure 5). For example, Data I/O's MESA-1, an in-circuit verifier for LCA
designs, uses LCAs exclusively to implement its logic
(Figure 6).

RECONFIGURABLE LOGIC EASES DESIGN
While not every system requires reconfigurable logiC to
implement its digital functions, the design-related benefits
of static-memory-based programmable logic apply to all
designs. The ability to reconfigure programmable gate
arrays resident in the target system significantly eases the
debugging process, reducing overall development time
and shortening the product's time-to-market. A download
cable provided with the basic development system allows
configuration programs to be downloaded directly from a
PC to an LCA device resident in the target system; the
actual download operation requires less than 100 milliseconds. Thus, the designer can immediately check the
results of design changes in the target system. Often,
design changes can be implemented and tested in just a
few minutes time.

Intel's Development Tools Operation (Hillsboro, OR) used
a slightly different tactic when designing a series of incircuit emulators for derivatives of the 80386 processor.
The emulators contain six LCAs. Four of them comprise
the bus event recognition circuitry used to define and
detect triggers and breakpoints; three of these are largely
filled with comparators, and the fourth holds the breakpoint
state machine. When preparing for an emulation, these
four LCAs can be reconfigured in the system, dependent
on the type of breakpoints and triggers being specified. A
DMA channel is used to download the LCA configuration
programs. A fifth LCA holds the bus interface state machines; as a future product upgrade, Intel designers may
generate another optional configuration program for that
LCA to add additional tracing capabilities.

In essence, Xilinx programmable gate arrays provide a
flexible means of "breadboarding" logic designs, as well as
a cost-effective means of implementing the logic in the
final product. Temporary modifications to the logic, such
as routing an internal node to an otherwise unused I/O pad,
can be quickly implemented for debugging purposes and
then removed from the production design. Devices are
reusable simply by downloading a new configuration.
There is no lengthy wait for a custom device to be manufactured, and no waste of components as with one-time-

THE ULTIMATE RECONFIGURABLE SYSTEM
A system composed entirely of programmable gate arrays
could be configured to implement any given logic functions. This concept has been incorporated into a new ASIC
design tool that provides real-time in-circuit emulation of
complex ASIC designs. The RPM Emulation System, from
Quickturn Systems Inc. (Mountain View, CAl, is a workstation-based design verification tool that combines automatic ASIC nellist conversion software with emulation
hardware based on 9000-gate XC3090 LCAs (See
Figure 6). The RPM Emulation System can be configured
with up to four emulation modules with over thirty XC3090
LCAs each, allowing emulation of ASIC designs of up to
100,000 gates. Once the ASIC design is converted for
emulation, existing complex VLSI devices may be
internally connected to the emulation logic with
Component Adapter boards, orthe design may be plugged
into a target system with an In-Circuit Interface consisting
of cables, an active Pod, and ASIC Plug Adapters. The
nellist conversion software reads the nellist (a variety of
popular formats and libraries are supported), partitions the
design for programming each XC3090 LCA, places and
routes the design into the matrix of XC3090 LCAs, and
checks the timing to determine the maximum speed of
correct functional operation. The Control Panel user
interface on the workstation guides the deSigner through
the emulation set-up and provides the controls for the
integral Logic Analyzer and Stimulus Generator, allowing
quick access to any node in the design during debugging.
Thus, using the RPM Emulation System, a designer can
emulate and debug the logic operation of any large digital
design before committing to a custom implementation.

Figure 6. The internal logic of Data I/O's MESA-! in-circuit
debugger is implemented entirely in Xilinx programmable
gate arrays.

7-30

programmable solutions; there is not even the inconvenience of long erase times using ultraviolet lights, as with
EPROM-based logic. The designer receives nearly instantaneous feedback on the effects of design modifications.
Furthermore, since the LCA's configuration can be verified
in the target system, extensive simulation is not required;
typically, simulation is used only for critical timing path
analysis under worst-case conditions.

Buffalo Products' design of the More Memory board mentioned above. During testing of the board using various
manufacturers' PC clones, problems caused by incompatibilities in some PC models were corrected as they
were found through reconfiguration of the LCA device.

The ability to implement easily modifications to the logic
enables and encourages experimentation during the design cycle, resulting in better designs. For example, the
use of Xilinx LCAs allowed GTECH Corp. to evaluate
different image sensors during the design of a bet-slip
readerforthe lottery industry" Since there are no standard
architectures or interfaces for image sensors, different
interface logic was required for each sensor type. By
incorporating the sensor interface logic in LCAs, a single
hardware implementation could be reconfigured for each
sensortype, allowing the sensitivity and resolution of each
to be measured under identical conditions.

Similarly, field upgrades can be easily implemented
through changes to LCA configuration programs.
Andromeda Systems (Canoga Park, CAl took foil
advantage of this capability in their Storage Module Device
Controller, a disk controller for LSI-11 and MicroNAX
systems. s The configuration programs for three XC2064
devices are stored in EEPROM that can be altered using
a service port that connects directly to terminals or
modems. The interfaces to the disk, processor bus,
service port, and cache memory are implemented in the
LCAs (Figure 7). Modifications to the logic, such as
adjusting the caching algorithm to match the requirements
of a particular application, can be made without removing
the disk controllerfrom the system; new LCA configuration
programs can be sent to the controller using a modem.

The flexibility of in-circuit reconfiguration greatly reduces
design risks. The inevitable last-minute bug fixes and
specification changes can be implemented by changing
an LCA's configuration program rather than altering the
hardware. MIA-Com Telecommunications (Germantown,
MD), for example, was able to correct an error in the PCB
layout without changing the board by reconfiguring an LCA
used to implement the channel interface logic within a
satellite earthstation. 7 This flexibility proved critical during

FIELD UPGRADES SIMPLIFIED

In many cases, compatible programmable gate arrays
with a range of densities are available in identical packages. (For example, the 2000-gate XC3020, 3000-gate
XC3030, and 4200-gate XC3042 are all available in 84-pin
PLCC and PGA packages.) So if logic needs exceed the
current LCA device, during either initial design or a product

PERIPHERAL
EXPANSION
PORT

CACHE MEMORY
1M BYTE DRAM

DISK
CONTROLLER

CACHE
ADDRESS
MAPPER
Q·BUS
INTERFACE

SMD
INTERFACE

III
USER
SERVICE
PORT
STATIC
RAM

EEPROM

1953 08

Figure 7. In Andromeda Systems' SMDC disk controller, LCA configurations can be
downloaded to EEPROM through a modem port for easy field upgrades.

7-31

Taking Advantage of Reconflgurable Logic

SUMMARY

upgrade (due to the addition of new product features, for
example), a higher-density device can be placed in the
same PCB location, with no modifications required to the
circuit board.

The advent of programmable logic that can be reconfigured while resident in a system has freed the designerfrom
the "hard" nature of traditional logic ICs. With programmable gate arrays, adaptable systems that adjust to
changing environments or varying tasks can be created,
and hardware design is simplified. New system architectures that take advantage of reconfigurable logic will
continue to emerge as programmable gate array densities
and performance levels continue to increase.

The reconfigurable nature of the programmable gate array
also allows for the design of its own in-circuit debugging
tools, such as Xilinx's XACTOR and Data lID's MESA-1
(Figure 8).9 Similar in many ways to microprocessor incircuit emulators, these sophisticated verification tools
provide for easy, fast debugging and testing. Since configuration programs can be downloaded into an LCA at will,
LCA devices in the target system can be replaced or
functionally duplicated by an LCA device in an in-circuit
debugger; LCA activity can then be controlled and monitored by the user.

REFERENCES
1. Loring Wirbel, ''Tek Takes Color Printer to the Office,"
Electronic Engineering Times, Nov. 14,1988.
2. David Smith, "User-Programmable Chips Take on a
Broader Range of Applications," VLSI Systems DeSign,
July, 1988.
3. Rusty Woodbury, "LCA Stars in Video," ESD: The
Electronic System Design Magazine, Feb., 1987.
4. Cliff Dutton, "Programmable Logic Betters the Odds for
Bet-Slip Readers," ESD: The Electronic System Design
Magazine, Oct., 1987.
5. Tom Uehe, "Two, Two, Two Chips in One," Electronic
Engineering Times, Nov. 17, 1986.
6. Loring Wirbel, "Quickturn Offers ASIC Emulator,"
Electronic Engineering Times, Nov. 14, 1988.
7. Dave Farrow, "Using Programmable LogiC Cell Arrays
in a Satellite Earthstation," VLSI Systems DeSign, April,
1987.
8. Jim Reynolds, "Building Tomorrow's Disk Controller
Today," Electronic Products, Dec. 15, 1987.
9. John Novellino, "Development Tool Trouble-Shoots
PGAs in the Target System," Electronic Design, Jan. 26,
1989.

Figure 8. The reconfigurability of LeAs allows for the design
of their own in-circuit verification tools, such as the MESA-1
from Data VO.

7-32

Faster Turnaround
for a T1 Interface
THE ElectronIC System Design MagaZlne

by Carl Erite, Teltrend Inc., St. Charles, IL

design requirements-high integration, high density, high
performance, low cost, low risk and quick time-to-market.

Important design considerations for an interface system to
a digital T1 network (which carries voice, data, video and
fax traffic at rates up to 56 Kbytes/sec) include conserving
board space, improving throughput and reducing power
consumption. The user interface is achieved via a conventional four-wire loop providing independent transmit and
receive capabilities. In designs that Teletrend Inc. initially
considered for a single-user T1 interface, 5000 gates of
conventional SSI/MSI glue logic were to be integrated
using two custom gate arrays. However, a short development cycle and low market risks were also desired. This
led to a search for an alternative to th time-consuming
process of casting two gate arrays.

The Xilinx devices implement a digital phase-locked loop,
as well as the T1 transmitter and receiver. A Hitachi
microprocessor provides overall intelligence to handle T1
controls, network code manipulation and other tasks.
The dual digital phase-lock loop provides the key function
of the system. Data on the user interface is encoded with
the clock Signals, a process that may occur at various
send/receive data rates. Data extraction from the user
interface must be phase-locked and, at the same time,
data must by synchronized with the T1 network clock. A
Xilinx LCA implements the phase-locked loop that synchronizes both the interface and the T1 network.

Upon completing the initial circuit design, a breadboard
was built using CMOS SSI/MSI logic components. After
the breadboard was working, integration path decisions
were needed. Instead of hard-tooling two custom gate
arrays, designers determined that three standard, programmable Xilinx Logic Cell Arrays (LCAs) met all of the

The second LCA transmits data onto the T1 network.
Here, data transmits serially at 1.544 Mbits/sec in one of
the 24 assigned time slots. A unique data word to be

RECEIVE DATA AT BAUD RATES FROM
1.2K TO 56K ARE PHASE-LOCKED TO
THE RECOVERED BAUD RATE CLOCK
AND TO THE T1 NETWORK CLOCK.
RECEIVE DATA

STANDARD 4 WIRE
USER INTERFACE
FOR SUBSCRIBER
LOOP SERVICE

T1
TRANSMITTER

TRANSMIT
DATA
AT 1.544
MBITs/SEC

I
I
I
I
I
I
I

DUAL PHASED·
LOCKED
LOOP
FOR
RECEIVER

-------

r----

T1 NETWORK CLOCK

1

LOGIC TO
TRANSMIT
TO USER
TRANSMIT DATA

CONTROL
MICROPROCESSOR

T1 RECEIVER
WITH8·BIT
CRCERROR
CORRECTION

f---

RECEIVE
DATA
AT 1.544
MBITs/SEC
I
I

L ___ _
T1 SWITCH
WITH ONE
ASSIGNED
TIME SLOT

1148 12

Figure 7. Teltrend's digital TI interface is built around three user-programmable Xilinx Logic Cell Arrays in lieu of two conventional
gate arrays. One LCA implements a dual digital phase-lock loop around four-wire loop; other LCAs form both the transmitter and
reciever logic circuits, including error correction.
7-33

II

Article Reprints
transmitted is held in the LCA while logic synchronization
determines the start of the first time slot or the beginning
of the data frame. The assigned time slot is found by
counting time slots from the start of a complete frame.
After locating the assigned time slot, data is transmitted
onto the T1 network.

higher performance in critical timing paths and higher
overall device utilization. In all three designs, LCA logic
resource utilization exceeded 95%.
All three designs are flip-flop intensive, involving multiple
counters, shifters, registers and other memory-oriented
functions. The LCAs provide more flip-flops per device
than any other programmable logic alternative. Only a few
simple 8-bit registers were implemented externally with
octal devices. Next-generation deSigns will use Xilinx's
compatible higher density devices to achieve greater logic
density in the same socket.

A third LCA, complementary to the transmitter function,
receives data. It also furnishes complete error correction
for incoming data. Time-slot detection logic determines
the start of data for the assigned channel. Serial data
comes from the T1 network. After the LCA performs 8-bit
error correction, the data passes to the processor and user
interface.

Overall, the ability to enter the original design using the
Xilinx LCA XACT design· system ensured that all the
integrated logic functioned as desired before the part was
placed in the system. With a conventional gate array, the
design might still be waiting for silicon, since turnaround
times for production quantity gate arrays typically range
from 8 to 16 weeks (production quantities).

The first iteration of the design was extracted directly form
the CMOS breadboard schematics using the Xilinx XACT
system running on an IBM PCIAT. The working design for
the first device was completed in two weeks, with some
time-critical elements moved off the Chip. Designs for the
second and third parts took about the same time, but
additional interaction during the design process resulted in

Reprinted with permission from ESD: The Electronic Sys-

tem Design Magazine.

7-34

Using Programmable Logic
Cell Arrays In a Satellite
Earthstation
Dave Farrow, MIA-Com Telecommunications, Germantown, MD

Conventional programmable logic devices (PLDs) include
several interesting variations of latch-based AND-OR
plane architectures in various technologies, all of which
are useful for low-gate-density applications. Typically, a
PLD can replace five to ten SSI/MSI parts.

3 Mbls transmission rate. The earthstation product, called
an OPT (for On-Premises Terminal) is a "small-aperture"
satellite earthstation, permitting efficient employment in a
large number of remote locations, as illustrated in
Figure 1.

A newer digital logic technology with an array architecture
and flexible interconnection offers the programming flexibility of PLDs plus the gate density of low-end gate arrays.
Architecturally, these devices have some similarities to
gate arrays: they contain an internal matrix of logic blocks
and a ring of configurable 1/0 interface blocks. Unlike
conventional gate arrays, each part is a standard off-theshelf unit that can be programmed by the user. The
configuration program is automatically loaded into an onchip static memory at power-up from either an on-board
EPROM or an external source such as a floppy disk.

Two main components comprise the OPT: an indoor unit
and an outdoor unit. The outdoor unit includes the antenna
and associated radio-frequency equipment.
At the outset of the design process, the indoor unit was
intended to be contained in a small chassis that could
support three standard-size boards. The boards originally
planned for the system included one board each for
controlling data traffiC, transmit functions, receive functions, and demodulation. However, the chassis provided
space for only three boards.
Project goals included the use of an existing proprietary
custom chip design from a previous application. MIA-Com
also investigated whether the design could be fit on only
two boards, by using a gate array. Board design itself was
driven by three primary factors: resource availability, cost,
and schedule. Since reducing the number of required
boards would reduce design time and keep product costs
lower, MIA-Com decided to go with the gate array.

THE EARTHSTATION SYSTEM

MIA-Com recently employed one of these "programmable
gate arrays" in the design of a satellite earthstation, intended to network commercial faCSimile operations. The
network handles traffic at 56 kbls, multiplexed into 26
channels and convolution ally encoded, yielding an overall

II
EACH ON·PREMISES
TERMINAL HAS ITS OWN
TRANSMIT FREQUENCY

GROUPS OF ON·PREMISES
TERMINALS SHARE A
RECEIVE FREQUENCY

Figure 1. Satellite System

7-35

UP TO 5.000
ON-PREMISES
TERMINALS

HUB

114807

QTY.

DESCRIPTION

ITEM

3

8·BIT SHIFT REGISTER

74HCT164

6

4·BIT COUNTERS

74HCT163

4

DUAL D FLlp·FLOP

74HCT74

2

QUAD 2:1 MULTIPLEXER

74HCT157

1

QUADXOR

74HCT86

1

HEX INVERTER

74HCT04

1

QUAD NOR

74HCT02

port controller and handles base-band X.25 data. Due to
the use of semicustom and programmable technology, the
remaining three functions were all merged onto the other
board, which we call a "sate"ite channel interface" (see
Figure 2).

114808

Table 1. Standard Off·the·Shelf Equivalents to the Logic
Contained in the LCA.

We used a gate array for the transmit function, which
othelWise would have required about 70 chips. For the
receive function, we originally planned to use an existing
full-custom ASIC (previously designed by MIA-Com) for
fOlWard error correction, and an additional 25 SSIIMSI
parts for the receive logic. However, due to chassis
constraints, the high density of components would have
necessitated a multi-layer board for the initial design.
Furthermore, based on previous experience, the likelihood of changes in the design specification was too high
to risk a custom or semicustom solution for the initial
design. Therefore, we originally planned to produce the
high-density boards in quantity and to reduce the cost of
the system at a later date, by first transferring the receive
logic into a gate array and then replacing the expensive
high-density four-layer board with a two-layer board.

The completed design employs a full custom IC, a gate
array, and programmable logic, and subsists on only two
boards. On one board, an Intel processor acts as a traffic-

While the design criteria were being prescribed and boardlevel functionality was being determined, we also investigated the newer programmable gate-array technology.
The programmable part, the Xilinx Logic Cell Array (LCA),

2

QUAD OR

74HCT32

3

QUAD AND

74HCT08

1

OCTAL LATCH

74HCT374

1

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74HCT244

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1148 09

Figure 2. Block Diagram of Satellite Channel Interface.

7-36

..

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Article Reprints

UNIQUE WORD SENSE

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DEMULTIPLEXER
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TIME-DIVISION MULTIPLEXER
(SYNCRONIZATION CIRCUITS)

1148 10

Figure 3. A Schematic of the Digital Systems Incorporated into the LeA.

is architectu rally similar to a gate array and is supported by
a PC/AT-based workstation.

in-circuit emulator for debugging.
Our original schematic was based on conventional LS and
HCT parts; it included JK flip-flops and large counters
(implemented by cascading common 4-bit counters),
rather than gate-level elements. Since that method of
design was inefficient for the LCA, we redesigned the
receive circuit at the gate level and then implemented it in
software via the cell array editor.

We determined that the internal organization of the LCA
fitted the design requirements of the receive function.
Specifically, the LCA provides many more flip-flops than
other programmable logic devices, so that one chip contained enough functionality for our needs. Further, the
LCA provided the required density savings, and its reprogrammability obviated the risks associated with late engineering changes. When engineering management was
presented with the design alternatives, we decided to
prototype a reduced portion of the receive circuit and thus
evaluate the reconfigurable chip.

Using an LCA reduced the amount of hardware overhead
normally associated withLKS and HCTtechnology. It was
not necessary to waste control inputs, to cascade counters, or to determine what to do with unused bits of multiplexers. In our design, 25 SSI/MSI gate-equivalents did
not even use up all the resources available in one LCA.
Table 1 indicates the parts that we actually employed in the
present design. Putting these functions in the LCA resulted in an 88% utilization of the internal cells, and a 60%
utilization of the I/O cells. Thus it still remains feasible to
add further functionality to the system, with no PCB

To implement the design, MIA-Com acquired the Xilinx
XACT PC-based LCA development system. The system
includes a macro library, with some of the required logic
already defined. After several days of experimenting with
the design tools, it took us one day to enter and only two
hours to debug the design. We uses Xilinx's XACTOR

7-37

II

The fourth state is entered every time a unique word is
missed; the system stays in the fourth state until the unique
word is found or is missed 11 consecutive times. If the
unique word is found, the system returns to state three; if
it is not found after 11 attempts, then the first state (the
search mode) is initiated again. This method of operation
ensures that the demultiplexer will remain locked even in
the presence of random bit errors in the data stream.

changes. We plan to do so in the future. Figure 3 is a
schematic of the circuit placed in the LCA. Since the
design is not 1/0 limited, there was no necessity to multiplex any of the input or output lines; but additional logic
could have been added, should 1/0 multiplexing been
needed. Note also that the descrambling circuit can easily
be reconfigured, or made more complex. Changing the
descrambler can be achieved merely by reprogramming
the LCA.

After the unique word is detected, the receiver locks onto
the data. The LCA chip then descrambles the data stream.
The data is originally scrambled by the transmitter to place
a fairly equal number of ones and zeros into the transmitted carrier. If this is not done, the transmitted carrier may
not contain an even distribution of spectral components,
which makes it difficult for a demodulator to acquire the
carrier. The descrambling process is merely the reverse
of the 9-bit scrambling procedure.

One criticism leveled againstthe LCA is that it requires 12K
bits of storage space to program the part during power-up.
However, in our design, a 27C64 EPROM (used for a lookup table) was already on the board. A portion of this
EPROM was available to store the LCA configuration
program at no additional cost. Since the 12K bits of
storage space are used to program all the RAM cell
locations in the LCA, adding further functionality to the
LCA would not require more storage space.

A single channel is isolated from the others by demultiplexing the descrambled data stream. The demultiplexing
function is performed through a pair of counters that count
the bits between unique words and tell the demultiplexer
when data is available.

ARCHITECTURE
From the OPT, transmission is executed in the SCPC
(single channel per carrier) mode. All scrambling, encoding, and error-code generation are performed by
MIA-Com's proprietary transmit gate array. The gate array
contains registers, allowing it to be programmed to transmit in different schemes and protocols, including SCPC
mode.

Once the incoming data stream has been descrambled
and demultiplexed, it moves on to the MIA-Com proprietary convolutional decoder, a custom chip where error
detection and correction is done on a per-channel basis.
Decoded data is passed on to a microprocessor for data
extraction.

The OPT receives a TDM (time division multiplexed)
bitstream composed of 56 kb/s data channels in a modulated 3-MHz carrier. The bitstream contains a UW (unique
word), and data and parity bits for each channel in each
frame. The received carrier is demodulated by analog
circuitry on the SCI, which passes the digital bitstream to
the LCA.

TESTING THE LCA
To test the TDM synchronizer, the LCA was loaded via the
Xilinx in-circuit emulator and set into the test bed. We
tested with a satellite simulator and found one design
error. Both isolation and remedy of the fault were simple
to perform, due to the reconfigurability of the part. Fault
location was eased by chOOSing internal test nodes and
connecting them to 110 pads. This technique made it
possible to find the fault very quickly.

To isolate the UW and lock onto the data, the LCAcontains
several counters and a state machine, configured in TDM
synchronizer. The state machine controls he synchroniztion algorithm, which manipulates the frames.

By using a satellite Simulator we were able to insert errors
into the datastream. We measured the time to lose sync
and the time to acquire sync, and determined that the
ripple counterwas a little too slow forthe required function.
Since we were using an in-circuit emulator, it was very
easy to reprogram the device. After the design was
debugged, we left the simulator on-line for a week to
ensure a thorough test of the Xilinx part under operational
conditions. Our concern was how well the LCA would
retain its configuration, since this information is stored by
RAM cells. However, in our environment, it performed
flawlessly.

The TDM synchronizer moves between four states (see
Figure 4). The first state entails acquiring "sync" by
recognizing the unique word in the unsynchronized data
stream. Once the unique word is acquired without errors,
the second state occurs. The circuit verifies "sync" by
detecting the unique word again one frame later in the
bitstream. Upon second detection, the circuit is considered in sync, and the synchronizer shifts to the third statethe sync state-where data are allowed to proceed as long
as the system detects at least one unique word in every 11
frames.

7-38

Article Reprints

UNIQUE WORD
DETECT

UNIQUE WORD
MISS >1

UNIQUE
WORD MISS

UNIQUE
WORD DETECT

UNIQUE
WORD MISS

UNIQUE
WORD DETECT

114811

Figure 4. State Machine for the Time-division Multiplexer.

Late into the design cycle we began to add additional
planned functions to the LCA. Because we knew we could
add these extra features, we finished the PCB layout and
ordered PC boards without waiting for the final design.
Then the process of adding putting functions into the LCA
was begun.

basic digital circuitry. For example, designers must be
able to recognize the worst-case timing scenarios of their
networks. Delay and system-speed considerations can
now be checked with the Xilinx simulator, but at the time of
our design, the simulator was still in beta test; we calculated the circuit behavior with preliminary timing software.
Since then the simulator has been revised and its present
version would have spotted our timing error.

Normally this time would have been used to design a test
fixture. Instead, another LCA design was created to
support a test implementation. Before the PCB was
delivered, the test fixture simulating the system was built,
primarily around the second Xilinx part. In the process of
building the fixture, we discovered an error in the PCB
layout, even before it was delivered. It was possible to fix
the error by reconfiguring the LCA.

Rather than packing complete design into the front end of
an ASIC development, as is required for conventional gate
arrays, the LCA offers the flexibility to indicate roles forthe
part. Designers can specify the I/O pins for the LCA then
send the PC board to fabrication. While the board is in
fabrication, designers can build into the LCA the gate-level
logic they want and continue to make changes up until, and
even after, the PCB is delivered.

When the board was delivered, a new version of our logic
design had been implemented in the Xilinx LCA, including
the demultiplexing and descrambling functions.

After final product delivery, the on-board logic can still be
reconfigured to match specific customer needs-without
having to cast custom silicon for a few dozen units or
changing the PC artwork. Great NRE savings are passed
back to the customer. In summary, the LCA has proved to
be an extremely effiCient, useful, and cost-effective extension to our semicustom design capabilities.

OPEN-END DEVELOPMENT

CONCLUSIONS
The flexibility of the Xilinx LCA lowers design costs,
reduces project schedule risks, and reduces inventory
risks. Using the LCA does not require much design
sophistication, but rather a good general knowledge of

Reprinted with permission from VLSI System Design.

7-39

II

Programmable. Logic
Betters the Odds for
Bet-Slip Readers

THE ElectronIC System Design Magazme

by Cliff Dutton, GTECH Corp., Providence, RI

In countries throughout the world, the vitality of the on-line
lottery industry is enhanced by seasonal and special
promotional games. But new games require new bet-slips,
and bet-slip readers must be able to accommodate frequent changes in format. To accomplish this, programmable gate arrays are replacing older, less flexible architectures.

the sensor interface. Similar difficulties hindered direct
comparison of achieved resolution. To accurately evaluate these parameters, each sensor had to be designed into
prototype readers. This involved driver and frame acquisition clock signal generation.
Because lotteries have no standard bet-slip size, as many
"standards" as possible need to be accommodated. Thus,
it was necessary to maintain flexibility in the format of the
target image.

In the development of GTECH's Solid State Reader, many
existing technologies were evaluated, but they imposed
unacceptable limitations on bet-slip processing, restricting
bet-slip formats to rows and columns. Moreover, the
process of reading the coupons was dependent on complex moving parts, and the reading elements were exposed to the external environment.

PROTOTYPING A SYSTEM
The implementation of a prototype system had one goal:
to prove the feasibility of recognizing handmade marks in
an imaging system. Because the volume of readers is
potentially high, component costs were a serious issue.

To maximize flexibility and minimize board space, Xilinx's
(San Jose, CAl Logic Cell Array (LCA) was chosen for the
Solid State Reader. The LCA, touted by the company as
a "programmable gate array," represents a novel programmable logic device that is notable for its reprogrammable
architecture. This architecture provides flexibility throughout the product's life span, which allows on-line bet-slips to
be produced with marks in any arrangement. Each bet-slip
reader at every terminal can be configured on-line to read
any bet-slip from an active suite of eight different bet-slips.

BOARD 1 MAIN CPU
COMMUNICATIONS
LINK

PROCESSOR
MEMORY
CONTROL LOGIC

BOARO 3

Figure 1 shows three lottery bet-slips. Some of the
pertinent features of the European Lotto game slip (a)
include strobe marks along the top edge, the OCRB-3
characters (bottom center), and the name and address
field (bottom right). In the sample bet-slip from a lottery in
the U.S. (b), there are no OCR characters or name and
address information. However, there is an area from
which handwritten information must be extracted. Apart
from the different features, the aspect ratios of bet-slips
are not standard. Modern bet-slip processing systems
must be able to read all of the different formats in many
aspect ratios. A format that forgoes the usual row and
column arrangement (c) is also depicted.

BOARD 2
CLOCK
GENERATOR
AND DRIVER
CIRCUITS

ANALOG SIGNAL
CONDITIONING
CIRCUITS

BOARD 4
IMAGE SENSOR BOARD

PRECISION OPTICS

As there are no standard architectures or interfaces for
image sensors, GTECH evaluated many image sensor
approaches. However, direct comparison of sensor performance could not be made in the application environment. For example, comparisons of sensor sensitivity at
the pixel level were impossible due to the differences in
sensor-interface electronics. If degraded senSitivities
were evident, they could derive from either the sensor or

Figure 2. The goal of developing a prototype bet-slip processor (shown above) was to prove that handmade marks could
be recognized in an imaging system. Four boards were
initially developed for this modular design: CPU/memory,
clock-driver, analog amplifier, and sensor mounting.
7-40

First, a working model was developed. To balance development costs, a set of printed circuit boards based on TTL
logic devices was manufactured. Partitioned functionally,
the board set supported modular design changes. Four pc
boards were initially developed: a CPU/memory board, a
clock-driver board, an analog amplifier board, and a sensor mounting board (Figure 2).

In the initial design, flexibility did not exist. Even though
modularity protected the design from becoming obsolete,
significant design alterations were required to accommodate different sensors. Because sensor clock signals are
multiphase, new clock generators would be needed for
new sensors. Also, bugs were difficult to find, and circuit
board modifications were required to eradicate such bugs.

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and (b and c) the United States. Such variety in slip design must be accommodated in the developement of bet-slip readers.

7-41

Article Reprints

Semicustom and full-custom technologies would have
solved all the functional problems, but they lack flexibility.
Because the development of the reader was ongoing, the
commitment to custom implementations was out of the
question. In addition, nonrecurring engineering (NRE)
costs were prohibitive and the devices could not be
adapted to changing sensor technologies or changing betslip reading requirements.

Finally, the target image aspect ratio was fixed because
the clock generation circuits were implemented in hardware.
Aspect ratios of target images are important because only
necessary information on the image needs to be processed. If the target image is 2:1 and the imaging format is
1:1, for example, then half the image is useless. A better
solution would mirror the aspect ratio of the target image
in the Image format.

Xilinx's LCAs permit a two-board set to be designed
without sacrificing functional modularity. In addition,
counting algorithms can be implemented in the LCAs.
Finally, LeAs allow for a multiple-iteration development
cycle.

To overcome the limitations of hardwired logic and reduce
board space, several technologies were evaluated. These
included programmable logic arrays (PLAs), field programmable logic devices (FPLDs), semlcustom and
fullcustom devices, and Xilinx's Logic Cell Array (LCA).

PUTIING A BUG TO REST

Size constraints Indicated the necessity for semicustom of
full-custom integration, but traditional LSI technologies
violated the flexibility constraint. Although full-custom was
attractive, design costs were prohibitive and did not permit
Iterative development. Standard PLDs did not allowforthe
variety of register-like functions that the clock generation
logic required.

Initially, the TIL-based system was implemented infourpc
boards. However, it contained a bug. For every horizontal
line, an extra pixel pulse was be ing supplied. Although this
was confusing to the eye, it was compensated for in
firmware. Because the redesign of the clock driver board
was a significant task, the bug was allowed to live through
many Iterations of the development cycle. When the
design of the clock generation circuit was translated into
the LCA, it was a trivial matter to delete a single horizontal
clock pulse and put the bug to rest in an aftemoon.

Programmable logic arrays were attractive for some logic
functions and would have been the least costly. However,
PLAs did not allow the multiple register implementation
necessary for clock generation. Thus, the counting algorithms would have remained external to any integration of
the combinatorial logic. Also, although the PLA architecture would have saved board space, it would not have
preserved the functional modularity achieved in the first
implementation. Thus, it would have been impossible to
evolve a PLA-based system in response to changes in
sensor technology. Finally, any required changes would
have to be performed by field replacement. With over
35,000 lottery terminals installed on five continents, this
was unacceptable.

Using the LCA also provided the ability to vary the clock
generation circuitry to evaluate different sensors. Because there is no standard architecture for solid-state
digital imaging devices, clock requirements vary for different sensors. In a standard imaging application, It might be
possible to source the appropriate support chips for each
sensor from the manufacturer. But because development
of the reader involved nonstandard video speeds in a
noninterlaced mode, it was impossible to use standard
support chips. If It had been necessary to develop a clock
driver pc board for every sensor evaluated, it would have
been impossible to evaluate more than one sensor in the
development time. Because LCAs were used, varying
multiphase clocks could be generated for different sensors
under evaluation. Thus, the turnaround time for a design
change in the clock generation circuits was reduced from
one to six weeks to one day.

Field programmable logic devices, an update of the
PLA-style architecture allowing limited reprogrammability,
appeared to provide some of the flexibility needed. If the
problem were merely a straight combinatorial one, FPLDs
could have been used. However, the difficulty in supporting both registers and counting algorithms ruled out their
use.

7-42

SINGLE MAIN BOARD
PROCESSOR
MEMORY

The Solid State Reader does not rely on standard video
output. Thus, the 4:3 standard aspect ratio for broadcast
television is not a requirement. All image processing is
internal to the system. Real-time display of the image is
never required. Therefore, only those areas of the sensor
that may contain relevant information need to be required.
Information-bearing areas of a bet-slip vary with the betslip deSign, so it is helpful to redefine the area of the sensor
that is acquired for processing.

COMMUNICATIONS
LINK

ANALOG
CIRCUITS

Because the clock driver circuitry, the memory addressing
logic, and the frame-grabber logic are all implemented in
the reconfigurable LeA, it is possible to acquire only
certain areas of the image. As each sensor has different
horizontal and vertical clock pulses, this flexibility cannot
be achieved in hardwired logic.

SENSOR
BOARD
IMAGE SENSOR BOARD

PRECISION OPTICS

Figure 3 illustrates the current architecture of the Solid
State Reader. Because of the functions consolidated in
the LeA, the system was reduced from four pc boards to
two. This could have been done using other technologies,
but they would not have preserved the functional modularity of the system. The LeA-based design provides both
size reduction and functional modularity.

114808

Figure 3. GTECH's Solid State Reader uses Logic Cell
Arrays (LCAs) to maximize flexibility and minimize board
space. Frame·grabber, memory addressing, and sensor clock
driver functions are consolidated in the LCA. By reducing the
number of chips, the required number of boards shrinks from
four to two.

Reprinted with permission from ESD: The Electronic
System Design Magazine.

II

7-43

Electronic
Products

Building Tomorrow's Disk
Controller Today

",,,",,,",",,,,,j,,,,,,,,,.,,, """,',,.

Jim Reynolds, President, Dave Randall, Chief Engineer, Andromeda Systems, Canoga Park, CA

Reprogrammable logic with a flexible architecture
enables a controller to keep up with today's highcapacity, high-speed disk drives

could be surface mounted onto a 35-in.2 dual-width board.
The only answer appeared to be VLSI custom or semicustom devices like gate arrays. But gate array definition
requires absolute design accuracy, and so a prototype
must be constructed long before custom-tooled ICs can be
specified and manufactured. Paradoxically, the prototype
itself required highly integrated logic.

Computer manufacturers historically have relied on advances in CPU and semiconductor memory technology for
increasing system throughput. At the same time, they
accepted as inevitable the hardware-bound I/O bottleneck. This position is becoming untenable with recent
advances in magnetic di sk tech nologi es, which have led to
a proliferation of high-capacity, high-speed drives.

To break thatfrustrating circle, it was necessary to convert
directly from schematic capture to a silicon breadboard of
multiple electrically programmable logic devices (EPLDs).
Because many logic functions would be added to the
prototype after the initial test, EPROM-based PALs were
considered, like the EP1200 from Altera, which licenses
the technology from Monolithic Memories.

Full performance from these drives needs sophisticated
controllers like Andromeda Systems' new Storage Module
Device Controller (SMDC). With a 1-Mbyte data cache
and dynamic read-ahead algorithms, the SMDC dramatically reduces average disk access time and significantly
improves overall system performance (see box, ''The
Storage Module Device ContrOller"). The design and
performance benefitted greatly from using Xilinx's Logic
Cell Arrays (LCAs).

The EP1200 could provide the minimum functionality on
the silicon breadboard, but not the level of device integration for the production circuit board. To implement the
various state machines and other logic of the design, each
target gate array would need three EP1200s. The resulting schematic capture and simulation would then be used
to fabricate the gate arrays for the final product.

Very early in the design, it was clear that its high-performance caching scheme needed more SSI/MSI logic than

CACHE MEMORY
1-MBYTE DRAM

....

i

I
Q-BUS
INTERFACE

CACHE
ADDRESS
MAPPER

I

r

I

f--

DISK
CONTROLLER

~

...

I
LCA3

LCA.1
Q-BUS AND DMA
CONTROLLER

LCA2
CACHE
CONTROLLER

S~~~~~~5~1~~fAL

i

I

T

~

65C802 MICROPROCESSOR
STATIC
RAM

I

PERIPHERAL
EXPANSION
PORT

STORAGE
MODULE
DEVICE
INTERFACE

..

CONTROLLER

USER
SERVICE
PORT

EEPROM

1148 01

Figure 1_ On Andromeda Systems' new Storage Module Device Controller, Xilinx Logic Cell Arrays handle the Q-bus interface
and direct memory access (DMA) Control, RAM/data-cache control, and SMD and peripheral expansion port control.

7-44

Fortunately, this circuitous design path was bypassed by
using Xilinx's LCA (see box, "Xilinx's programmable gate
array"). There are two basic differences between LCAs
and other EPLDs. First, the LCA has the flexible archile(:ture of a gate array. Second, LCAs employ static memory
to hold the logic configuration data.
The LCAs brought several significant advantages to the
controller design. Since the Xilinx 2064 LCA has 64
configurable logic blocks and the EP1200 only 20, a single
LCA could replace the three target gate arrays, elimination
the fabrication delays and costs of custom tooling.
Figure 2. The user service port can create color bar graphs
that dynamically show various attributes of the data cache,
such as read times, forward block reads, and 1/0
completion rates.

Furthermore, the position of the LCAs on the board could
be determined before their internal logic configuration was
designed. Other than dedication input and output pins,
only a general idea of the function of each LCA was
needed. The board layout and the internal LCA logic
design could proceed in parallel, greatly reducing development time. Most design changes could be implemented
merely by reprogramming the LCAs. Thus, use of the
LCAs allowed the design to go directly from schematic
capture to a production board, skipping the wire-wrapped
prototype.

Aside from the LSI circuitry, the only other logic on the
SMDC board are TTL bus transceivers, SMD interface
drivers, and a few PALs.
The RAM of the data cache is in ZIPs. Most of the interface
logic was surface mounted to the board. Despite the
board's small size, these VLSI devices permit several
advanced features.

The first LCA on the SMDC is the Q-bus interface and
direct memory access (DMA) controller (see Fig. 1). All but
5 of the 64 internal logic blocks were used. The LCA holds
the DMA addressing logic, the bus registers, and the
interrupt logic.

The SMDC's user service port connects directly to terminals or moderns. No special test programs for specific
system environments are needed to communicate with the
controller. Users can define drives, assign logical units,
format drives, and do other more esoteric functions.

RAM/data-cache control is the job of the second LCA. It
controls the cache and has the interface between the disk
controll.er IC and the DMA logic. It signals cache-write
enables, multiplexes memory addresses, and enable
DMA reads and writes.

This port can monitor the operation of the controller while
the drive is in operation. The user can display color bar
graphs that dynamically show various attributes of the data
cache, such as read times, forward block reads, and I/O
completion rates. Caching parameters can be adjusted,
letting the user tune the system for optimum performance.

The third LCA controls the SMD port and peripheral
expansion port. The expansion port is just a group of
programmable 1/0 connections. Since the LCA is programmable, the control logic forthe expansion port can be
reconfigured for any desired 1/0 interface. Thus, this port
provides for future expansions (like adding a tape drive,
optical disk, or extra cache memory) at a fraction of the
cost of a separate controller. Unused logic in this LCA will
permit on-board functions to be added in future microcode
revisions to the controller.

Firmware can alter the configuration data for the LCAs,
modifying the circuit schematic and not the board. Since
the firmware is in EEPROMs, the service port can accept
microcode upgrades in the field via modem. PROM set
replacement and on-shelf obsolescence are.avoided.

II

7-45

Article Reprints

a 1-Mbyte data cache and unique caching algorithms.
Andromeda divides the cache into 1,024 granules. The
information kept for each 1-Kbyte granule depends on
select criteria, which include:

THE STORAGE MODULE DEVICE CONTROLLER

Designed for LSI-11 and MicroNAX II systems,
Andromeda Systems' Storage Module Device Controller
(SMDC) for Winchester drives supports two SMD or
SMDE drives at data rates up to 25 Mbits/s. Another
Andromeda controller, the ESDC, works with the Enhanced Small Device Interface, the ESDI, for Winchesters or floppy-disk drives. Both controllers use the standard DU device driver and work with such operation systems as RT-11, TSX+, RSX, RSX-11M, MicroRSX,
RSTS, MicroRSTS, Ultrix, DSM, Unix, and MicroVMS.

The time data is first accessed
The number of times data is read
The time of the most recent read
The size of the read.
This information is then entered into an equation that approximates how probable it is that the granule will be requested again soon. Those granules with low probabilities are designated to be overwritten by the next diskread operation. During cache accesses, a memory mapper translates logical memory addresses into the physical addresses of the appropriate granule in much the
same way that the Micro-Vax II memory management
unit would.

The SMDC achieves more performance and flexibility
than did previous generations of disk controllers. It includes data caching, high datactransfer rates, a peripheral expansion port, field-Ioadable microcode, and a
user service port. State-of-the-art VLSI components
and packaging techniques fit the entire controller within
the 35 sq in. of a dual-width Q-bus board (see figure).

PREDICTIVE CACHING

Using Digital Equipment'S Mass Storage Control Protocol (MSCP), the SMDC can partition two drives into as
many as 16 logical units with up to 32 Gbytes each. Onboard intelligence comes from a 65C802 microprocessor, and all the processor's code resides in just two
EEPROMs. The majority of the remaining logic is implemented with Xilinx programmable Logic Cell Arrays
(LCAs). Data integrity is ensured by 48-bit error detection and correction logic. An expansion port can be connected to accessory modules, allowing control of devices like tape drives, optical disks, or extra cache
memory.

In a novel departure from most caching schemes, the
SM DC caching mechanism not only looks at the past, but
tries to gaze into the future as well. As the system requests the data that has been pre-fetched into the cache,
the controller retrieves not only the requested data, but
also preemptively reads extra sequential blocks when
specific probability conditions are met. As a result, the
on-board cache's typical hit rate is over 80%. In other
words, the data being sought by the application will be
ready and waiting in the cache over 80% of the time.
Approximately 90% of the disk access time is due more
to average seek times and rotational latency than to the
actual data transfer rate. However, when a cache hit
occurs, the access time depends only on the speed of
the DMA channel responsible for sending the data to the
Q-bus.

The performance of the SM DC is greatly enhanced with

That DMA channel operates as fast as Q-bus specifications allow-to be specific, at a rate of up to 4 Mbytes/s.
Consequently, with the SMDC cache, seek time and rotationallatency are reduced to zero over80%ofthetime.
This reduces the average time for a four-block read from
27 ms to less than 6 ms.
In the majority of computer systems, mass-storage access time is undoubtedly the largest component of
throughput. In this situation, use of the SMDC enormously improves total system performance.
$$$$$
Andromeda Systems' Storage Module Device Controller is available now for $2,195. (The company's ESDI
controller is available for $1 ,995.) For more information,
call Don Talmadge at 818-709-7600, orcircle 336 forthe
SMDC and 337 for the ESDC.
7-46

1/0 BLOCK

XILlNX'S PROGRAMMABLE GATE ARRAY

The Xilinx programmable gate array, known as a Logic
Cell Array (LCA), is a high-density CMOS IC that combines
user programmability with the flexibility of a gate array
architecture and the economy and testability of standard
products. Elements of the array include three categories
of configurable elements: I/O blocks, configurable logic
blocks, and programmable interconnections (see figure).

D

Qg Q

g

Qg

CONFIGUAABLE
LOGIC BLOCK~

-{}
-{}
-{}
-{}
{I:
{I:
-{}

I/O blocks provide an interface between the external
package pin and the internal logic. Each block includes a
programmable input path and output buffer. The array of
configurable logic blocks contains the functional elements
from which the user's logic is constructed. Each array
includes a combinatorial section, storage elements, and
internal routing and control logic. Programmable interconnection resources connect the inputs and outputs of the
110 blocks and configurable logic blocks into the desire
networks.
An LCA is configured by programming static memory cells
that determine the logic functions and interconnections.
On-Chip logic provides for automatic loading of the configuration program at power-up or upon command. A
personal computer-based development software package
generates the configuration program. Other tools include
a Simulator, in-circuit, and schematic capture package.

o

0 0 0
0 oro 0
0 010 0
0 0 0 0
~

INTERCONNECT AREA---+

1148 02

Reprinted with permission of Electronic Products.

II

7-47

Article Reprints

7-48

SECTIONS
Index

1

Programmable Gate Arrays

2

Product Specifications

3

Quality, Testing, Packaging

4

Technical Support

5

Development Systems

6

Applications

7

Article Reprints

8

Index

Index

Index ................................................................................................... 8-1
Sales Office Listing ............................................................................. 8-5

Index

ac parameters .................................................. 2-42, -90

configuration memory ........................................ 2-2, -63

accu mulator ............................................................. 6-22

corner bender .......................................................... 6-44

adder .......................................... 6-22, -23, -24, -25, -26

cost analysis ............................................................ 1-11

alpha particles ............................................. 2-3, -64; 3-9

counter ........... 6-28, -29, -30, -31, -32, -33, -34, -38, -40

alternate buffer ........................................................ 2-42

crystal oscillator ............................... 2-13, -23, -70; 6-10

applications ............................................................... 6-1

daisy chain ....................................................... 2-20, -76

APR ......................................................................... 5-10

DASH ...................................................................... 5-19

architecture ............................................................... 1-4

data integrity .............................................................. 3-8

barrel shifter ............................................................ 6-19

data transfer ............................................................ 6-12

battery backup ......................................................... 6-18

dc parameters .................................................. 2-40, -89

BCD-to-binary ......................................................... 6-42

decoding .................................................................. 6-21

BIOI ......................................................................... 2-42

delay tracking .......................................................... 6-14

binary-to-BCD ......................................................... 6-43

delay variation .................................................. 2-26, -82

bitstream ................................................................. 5-11

Design Manager ........................................................ 5-4

buffer characteristics ............................................... 2-42

design entry ......................................................... 5-2, -6

bu lIetin board ............................................................. 4-4

design flow ................................................................ 5-1

burn-in circuits ........................... 2-109, -125, -143, -163

design implementation ....................................... 5-3, -27

bus .......................................................................... 2-11

design verification ............................................... 5-3, 32

capacitive loading ...................................................... 6-9

direct interconnect .............................................. 2-9, -70

carry logic ................................................................ 6-22

disk controller .......................................................... 7-44

CCLK frequency ...................................................... 6-10

DONE timing .................................................... 2-17, -23

CLB .................................................................... 2-5, -65

DRAM controller ...................................................... 6-52

CLB characteristiCS .......................................... 2-42, -90

EDIF ........................................................................ 5-23

clear ................................................................. 2-15, -72

EditNet ............................................................... 2-7, -66

comparator .............................................................. 6-23

electrostatic discharge .............................................. 3-9

component selection ............................................... 2-60

ESD ........................................................................... 3-9

configuration ............................................................ 2-79

FAE addresses .......................................................... 4-6

8-1

•

Index

FIFO ........................................................................ 6-46

memory requirements ............................................. 5-40

frames .............................................................. 2-16, -72

Mentor Graphics ...................................................... 5-21

frequency counter ................................................... 6-45

merging ..................................................................... 5-8

gate capacity ...................................................... 2-1, -63

MESA ...................................................................... 5-14

global buffer ............................................................ 2-42

metastability ............................................................ 6-16

hardware requirements ........................................... 5-40

Micro Channel ......................................................... 6-50

header .............................................................. 2-16, -72

MIL-STD-883 ................................................. 2-105; 3-1

hysteresis .................................................................. 6-9

military ................................................................... 2-103

ICE ...................................................................... :... 5-14

minimum delay ........................................................ 6-13

initialization ...................................................... 2-14, -74

modes ..................................................................... 2-14

interconnect ....................................................... 2-7, -67

multiplexer ............................................................... 6-19

interconnect delay ............................................ 2-25, -80

net list interface ........................................................ 5-23

lOB ..................................................................... 2-3, -64

newsletter .................................................................. 4-3

lOB characteristics ........................................... 2-44, -92

optimization ............................................................... 5-7

latches ..................................................................... 6-27

OrCAD ..................................................................... 5-22

latchup ..................................................................... 3-10

OrCAD simulator ..................................................... 5-30

LCA2XNF ................................................................ 5-12

ordering information ......................................... 2-60, -98

length counter .................................................. 2-16, -72

oscillator ........................................................... 2-13, -70

library ............................................................... 5-19, -34

output current ............................................................ 6-9

literature .................................................................... 4-8

output slew rate ......................................................... 6-9

logic synthesis ......................................................... 5-26

package dimensions ...................................... 2-53 to 59

long lines .......................................................... 2-11, -69

PAL ........................................................................... 5-6

macros .................................................................... 5-34

parity ....................................................................... 6-20

majority logic ........................................................... 6-20

PC-SILOS ............................................................... 5-28

MAKEBITS .............................................. 2-17, -72, 5-11

performance ............................................ 2-24, -SO; 6-11

MAKEPROM ........................................................... 5-14

peripheral mode .................. 2-14, -20, -49, -75, -77, -96

MAP2LCA ................................................................. 5-9

PGA pinou!... .................................................... 2-51, -99

mapping .................................................................... 5-7

phase comparator ................................................... 6-37

master mode ...................................... 2-14, -18, -74, -76

physical dimension .................................................. 2-53

master parallel mode ....................................... 2-48, -95

pin assignment ................................................. 2-31, -86

master serial mode .......................................... 2-47, -94

pin description .................................................. 2-29, -S4

memory cell ................................................ 2-2, -64; 3-8

pinouts ...................................................... 2-32, -51, -S6

S-2

~XIUNX
platform ................................................................... 5-16

size estimate ............................................................. 6-3

PLL .......................................................................... 6-37

slave mode .......................... 2-14, -20, -50, -76, -78, -97

postamble ........................................................ 2-17, -72

sockets .................................................................... 3-22

power consumption .................. 2-27, -28, -71, -83; 6-10

soft errors .................................................................. 3-9

power distribution ...................................... 2-26, -27, -71

speed ............................................................... 2-24, -80

power down ............................................ 2-15, -27; 6-18

standby .................................................................. 2-178

preamble .......................................................... 2-16, -72

start-up ........................................................... 2-15; 6-15

prescaler .......................................................... 6-38, -40

state machine ................ :.................................. 6-48, 7-8

printer controller ........................................................ 7-1

subtractor ................................................................ 6-22

programming .................................................... 2-14, -74

support agreement .................................................. 5-33

programming flowchart .......................................... 2-182

switching matrix ......................................................... 2-7

programming specs ............................................... 2-181

system diagnostics .................................................. 7-24

PROM programmer ................................................. 5-31

TBUF ....................................................................... 2-42

pull-up resistors ........................................ 2-12, -80; 6-9

test specifications ...................... 2-110, -127, -146, -165

pulse-swallowing .............................................. 6-38, -40

testing ................................................................ 3-1, -12

quality ........................................................................3-1

thermal resistance ................................................... 3-19

radiation hardness ................................................... 3-11

thermal shock ............................................................ 3-4

re-program ....................................................... 2-23, -78

threshold ..................................................... 2-4, -22, -77

readback ............................. 2-21, -22, -50, -77, -78, -97

tracking .................................................................... 6-14

reconfigurable logic ................................................. 7-24

training courses ........................................................ .4-7

reconfigure ....................................................... 7-15, -19

typical delays ........................................................... 6-14

reliability .................................................................... 3-1

up/down counter ....................................... 6-30, -31, -33

RESET .................................................................... 6-15

users' groups ............................................................. 4-1

RESET polarity ...................................................... 2-178

video graphics ......................................................... 7-22

RESET timing .................................................. 2-17, -23

video tape ................................................................. .4-2

schematic editor ...................................................... 5-19

VIEWdraw ............................................................... 5-24

selection .................................................................. 2-60

VIEWlogic ................................................................ 5-25

seminars .................................................................... 4-1

VIEWsim ................................................................. 5-29

serial PROM .......................................................... 2-176

weight ...................................................................... 3-21

set-up time .............................................................. 6-13

wired-AND ............................................................... 2-12

shift register counter ................................................ 6-28

workstations ............................................................ 7-15

simulator .......................................................... 5-12, -28

XACT ....................................................................... 5-27

8-3

III

Index

XACTOR .......................................................... 5-14, -32

XC4000 ..................................................................... 1-8

XC1736A ........................................................ 1-6; 2-175

XCELL ....................................................................... 4-3

XC1765 .......................................................... 1-6; 2-175

XDM .......................................................................... 5-4

XC2000 ............................................................ 1-6, 2-63

XMAKE ...................................................................... 5-4

XC2000 design .......................................................... 6-8

XNFMAP ................................................................... 5-7

XC3000 .............................................................. 1-7; 2-1

XNFMERGE .............................................................. 5-8

XC3000 design .......................................................... 6-7

xtal oscillator .................................... 2-13. -23, -70; 6-10

8-4

Sales
Offices

HEADQUARTERS

JAPAN

XILlNX, INC.
2100 Logic Drive
San Jose, CA 95124
(408) 559-7778
TWX: 510-600-8750
FAX: 408-559-7114

XILINX K. K.
Kybashi No.8
Nagaoka Bldg. 8F
20-9 Hatchobori Nichome
Chuo-ku, Tokyo t04, Japan
Tel: (03) 3297-9191
FAX: (03) 3297-9189

XILINX
SALES OFFICES

U.S. SALES
REPRESENTATIVES

NORTH AMERICA

ALABAMA

XILlNX, INC.
3235 Kifer Road
Suite 320
Santa Clara, CA 95051
(408) 245-1361
FAX: 408-245-0517

Novus Group - Huntsville
2905 Westcorp Boulevard
Suite 120
Huntsville, AL 35805
(205) 534-0044
FAX: 534-0186

XILlNX, INC.
15615 Alton Parkway
Suite 310
Irvine, CA 92718
(714) 727-0780
FAX: 714-727-3128

ARIZONA

XILlNX, INC.
61 Spit Brook Rd.
Suite 403
Nashua, NH 03080
(603) 891-1096
FAX: 603-891-0890
XILlNX, INC.
65 Valley Stream Parkway
Suite 140
Malvern, PA 19355
(215) 296-8302
FAX: 215-296-8378
XILlNX, INC.
919 North Plum Grove Road
Suite A
Schaumburg, IL 60173
(708) 605-1972
TLX: 510-601-5973
FAX: 312-605-1985
EUROPE
XILlNX, ltd.
Suite 1B, Cobb House
Oyster Lane
Byfteet
Surrey KT14 7DU
United Kingdom
Tel: (44) 932-349401
FAX: (44) 932-349499
XILlNX, G.m.b.H.
Leonhardsweg, 2
8025 Unterhaching
Munchen, West Germany
Tel: (49) 89-6110851
Fax: (49) 89-6112246

Quatra Associates
4645 S. Lakeshore Dr.,
Suite 1
Tempe, AZ. 85282
(602) 820-7050
TWX: 910-950-1153
FAX: 602-820,7054
ARKANSAS
Bonser-Philhower Sales
689 W. Renner Road
Suite 101
Richardson, TX 75080
(214) 234-8438
TWX: 214-437-0897

Norcomp
2140 Prolessional Drive
Suite 200
Roseville, CA 95681
(916) 782-8070
FAX 916-782-8073

IDAHO (Southwest)

LOUISIANA (Northern)

Thorson Company Northwest
12340 N.E. 8th Street
Suite 201
Bellevue, WA 98005
(206) 455-9180
FAX: 206-455-4185

Bonser-Philhower Sales
689 W. Renner Rd., Suite 101
Richardson, TX 75080
(214) 234-8438
TWX: 910-867-4752
FAX: 214-437-0897

COLORADO
Front Range Marketing
3100 Arapahoe Rd.,
Suite 404
Boulder, CO 80303
(303) 443-4780
TWX: 910-940-3442
FAX: 303-447-0371
CONNECTICUT
Lindco Associates, Inc.
Cornerstone Professional Park
Suite C-l0l
Woodbury CT, 06798
(203) 266-0728
FAX: 203-266-0784
DELAWARE
Delta Technical Sales, Inc.
122 N. York Road
Suite 9
Hatboro, PA 19040
(215) 957·0600
FAX: 215-957-0920
Micro Comp, Inc.
1421 S. Caton Avenue
Baltimore, MD 21227-1082
(301) 644-5700
TWX: 510-600-9460
FAX: 301-644-5707

CALIFORNIA
SC Cubed
468 Pennsfield Place
Suite lOlA
Thousand Oaks, CA 91360
(805) 496-7307
FAX: 805-495-3801

FLORIDA

SC Cubed
1786217th. 51. #207
Tustin, CA 92680
(714) 731-9206
FAX: 714-731-7801

Semtronic Assoc., Inc.
3471 N. W. 55th Street
Ft. Lauderdale, FL 33309
(305) 731-2464
FAX: 305-731-1019

Quest-Rep Inc.
9444 Farnham 51., Suite 107
San Diego, CA 92123
(619) 565·8797
FAX: 619-565-8990

Semtronic Assoc .• Inc.
1467 South Missouri Avenue
Clearwater, FL 34616
(813) 461-4675
FAX: 813-442-2234

Semtronic Assoc., Inc.
657 Maitland Avenue
Altamonte Springs, FL 32701
(407) 831-8233
FAX: 407-831-2844

Wasatch-Pro Rep Marketing
380 East 4500 South, Suite 6
Salt Lake City, UT 84107
(801) 268-3434
FAX: 801-266-9021
ILLINOIS
Beta Technology Sales, Inc.
1009 Hawthorne Drive
Itasca, IL 60143
(708) 250-9586
TWX: 62885853
FAX: (312) 250-9592
Advanced Technical Sales
1810 Craig Road,Suite213
51. Louis, MO 63145
(314) 878-2921
FAX: 314-878-1994
INDIANA
Arete Sales Inc.
2260 Lake Ave Suite 250
Fort Wayne, IN 46805
(219) 423-1478
FAX: 219-420-1440
Arete Sales Inc.
918 Fry Road Suite B
Greenwood, IN 46142
(317) 882-4407
FAX: 317-888-8416
IOWA
Advanced Technical Sales
375 Collins Road N.E.
Cedar Rapids, IA 52402
(319) 393-8260
FAX: 319-393-7258
KANSAS
Advanced Technical Sales
610 N. Mur-Len, Suite 8
Olathe, KS 66062
(913) 782-8702
TWX: 910-350-6002
FAX: 913-782-8641

GEORGIA
Novus Group - GA
6115-A Oakbrook Parkway
Norcross, GA 30093
(404) 263-0320
404-263-8946

8-5

MAINE
Mill-Bern Associates, Inc.
2 Mac Road
Woburn, MA 01801
(617) 932-3311
TWX: 710-332-0077
FAX: 617-932-0511
MARYLAND
Micro Comp, Inc.
1421 S. Caton Avenue
Baltimore, MD 21227-1082
(301) 644-5700
TWX: 510-600-9460
FAX: 301-644-5707
MASSACHUSETIS
Mill-Bern Associates,lnc.
2 Mack Road
Woburn, MA 01801
(617) 932-3311
TWX: 710-332-0077
FAX: 617-932-0511
MICHIGAN
A.P. Associates
810 E. Grand River
Brighton, MI48116
(313) 229-6550
FAX: 313-229-9356
MINNESOTA
Com-Tek
6525 City West Parkway
Eden Prairie, MN 55344
(612) 941-7181
TWX: 310-431-0122
FAX: 612-941-4322
MISSOURI

KENTUCKY
Norcomp
3350 Scot! Blvd., Suite 24
Santa Clara, CA 95054
(408) 727-7707
TWX: 510-600-1477
FAX: 408-986-1947

LOUISIANA (Southern)
Bonser-Philhower Sales
10700 Richmond, Suite 150
Houston, TX 77042
(713) 782-4144
TWX: 910-350-3451
FAX: 713-789-3072

Arete Sales, Inc.
918 Fry Road
SuiteB
Greenwood, IN 46142
(317) 882'4407
FAX: 317-888-8416

Advanced Technical Sales
601 N. Mur-Len, Suite 8
Olathe, KS 66062
(913) 782-8702
TWX: 910-350-6002
FAX: 913-782-8641
Advanced Technical Sales
1810 Craig Road, Suite 213
51. Louis, MO 63146
(314) 878-2921
FAX: 314-878-1994

•

Sales Offices
NEBRASKA
Advanced Technical Sales
601 N. Mur-Len, Suite 8
Olathe, KS 66062
(913) 782-8702
TWX: 910-350-6002
FAX: 913-782-8641
NEVADA
Norcomp

(Excluding Las Ve9as)
3350 Scott Blvd .. Suite 24
Santa Clara, CA 95054
(408) 727-7707
TWX: 510-600-1477

Gen-Tech Electronics
70 Sandoris Circle
Rochester, NY 14622
(716) 467-S016
Gen-Tech Electronics
5 Arbutus Lane
Binghampton, NY 13901
(607) 648-8833
NORTH CAROLINA
The Novus Group - NC & SC
102L Commonwealth Court
Cary, NC 27511
(919) 460-7771
FAX: 919-480-5703

NEW HAMPSHIRE
Mill-Bern Associates, Inc.
2 Mack Road
Woburn, MA 01801
(617) 932-3311
TWX: 710-332-0077
FAX: 617-932-0511
NEW JERSEY (Northern)
Parallax
734 Walt Whitman Road
Mellville, NY 11747
(516) 351-1000
FAX: 516-351-1606
NEW JERSEY (Southern)
Delta Technical Sales, Inc.
122 N. York Road
Suite 9
Hatboro, PA 19040
(215) 957-0600
FAX: 215-957-0920
NEW MEXICO
Quatra Associates
600 Autumwood Place, S. E.
Albuquerque, NM 871 23
(505) 296-6781
NEW YORK (Metro)
Parallax

734 Walt Whitman Road
Mellville, NY 11747
(516) 351-1000
FAX: 516-351-1606
NEW YORK
Gen-Tech Electronics
4855 Executive Drive
Liverpool, NY 13088
(315) 451-3480
TWX: 71 0-545-02SO
FAX: 315-451-0988
Gen-Tech Electronics
41 Burning Tree Lane
Rochester, NY 14526
(716) 381-5159
FAX: 716-381-5159'

VERMONT

Mill-Bern Associates, Inc.
2 Mac Road
Woburn, MA 01801
(617) 932-3311
TWX: 710-332-0077
FAX: 617-932-0511

Mill-Bern Associates, Inc.
2 Mac Road
Woburn, MA 01801
(617) 932-3311
TWX: 710-332-0077
FAX: 617-932-051 1

Semtronic Assoc., Inc.
Mercantile Plaza Building
Suite 816
Hato Rey, PR 00918
(809) 766-0700/0701
FAX: 809-763-0701

VIRGINA

RHODE ISLAND
Mill-Bern Associates, Inc.

Quatra Associates

(Las Vegas)
4645 S. Lakeshore Dr., Suite 1
Tempe, AZ 85282
(602) 820-70SO
FAX: 602-820-7054

PUERTO RICO

NORTH DAKOTA
Com-Tek
6525 City West Parkway
Eden Prairie, MN 55344
(612) 941-7181
TWX: 310-431-0122
FAX: 612-941-4322
OHIO
Bear Marketing, Inc.
P.O. Box 427
3554 Brecksville Road
Richfield, OH 44286-0427
(216) 659-3131
FAX: 216-659-4823
TWX: 810-427-9100
Bear Marketing, Inc.
240 W. Elmwood Drive
Suite 1012
Centerville, OH 45459-4248
(513) 436-2061
FAX: 513-436-9137
OKLAHOMA
Bonser-Philhower Sales
689 W. Renner Rd., Suite 101
Richardson, TX 75080
(214) 234-8438
TWX: 910-867-4752
FAX: 214-437-0897
OREGON
Thorson Company Northwest
6700 S.W. 105th Ave.,
Suite 104
Beaverton, OR 97005
(503) 644-5900
FAX: 503-644-5919
PENNSYLVANIA (Eastern)
Delta Technical Sales, Inc.
122 New York Road
Suite 9
Hatboro, PA 19040
(215) 957-0600
FAX: 215-957-0920

2 Mack Road
Woburn, MA 01 801
(617) 932-3311
TWX: 710-332-0077
FAX: 617-932-0511
SOUTH CAROLINA
The Novus Group - NC & SC
102L Commonwealth Court
Cary, NC 27511
(919) 460-7771
FAX: 919-460-5703
SOUTH DAKOTA
Com-Tek
6525 City West Parkway
Eden Prairie, MN 55344
(612) 941-7181
TWX: 310-431-0122
FAX: 612-941-4322
TEXAS
Bonser-Philhower Sales
8240 Me Pac Expwy.,
Suite 135
Austin, TX 78759
(512) 346-9186
TWX: 910-997-8141
FAX: 512-346-2393
Bonser-Philhower Sales
10700 Richmond, Suite 150
Houston, TX 77042
(713)782-4144
TWX: 910-350-3451
FAX: 713-789-3072
Bonser-Philhower Sales
689 W. Renner Rd., Suite 101
Richardson, TX 750BO
(214) 234-8438
TWX: 910-867-4752
FAX: 214-437-0897

WASHINGTON
Thorson Company Northwest
12340 N.E. 8th Place
Suite 201
Bellevue, WA 98005
(206) 455-9180
FAX: 206-455-9185
TWX: 910-443-2300
WASHINGTON
(Vancouver, WA only)
Thorson Company Northwest
6700 S.w. 105th Ave.,
Suite 104
Beaverton, OR 97005
(503) 644-5900
FAX: 503-644-5919
WASHINGTON D.C.
Micro Comp, Inc.
1421 S. Caton Avenue
Baltimore, MD 21227
(301) 644-5700
TWX: 510-600-9460
FAX: 301-644-5707

TEXAS (EI Paso County)
Quatra Associates

600 Autumwood Place SE
Albuquerque, NM 87123
(505) 296-67Bl

UTAH
Wasatch Pro Rep Marketing
380 East 4500 South, Suite 6
Salt Lake City, UT 84107
(801) 26B-3434

FAX: 801 -266-9021

'Activates Fax

8-6

AUSTRALIA
ACD/ITRONICS
106 Belmore Rd. North
Riverwood, N.S.w. 2210
Tel: (61) 2-534-6200
FAX: (61) 2-534-4910
ACD/ITRONICS
Unit2,17-19 Melrich Road
Bayswater VIC 3153
P.O. Box 139
Tel: (61) 3-762 7644
FAX: (61) 3-762 5446
ACD/ITRONICS
55 Noreen Street
Chapel Hill OLD 4069
Tel: OLD 8781488
FAX: OLD 8781490
ACD/INTRONICS
261 Sturt Street
Adelaide
S.A. SOOO
Tel: (61) 8-213-6505
FAX: (61) 8-231-8245
AUSTRIA
Eljapex G.m.b.H
Eitnergasse 6
A-1232Wien
Austria
Tel: (43) 1-861531
FAX: (43) 1-861531300
BELGIUM & LUXEMBURG

WISCONSIN (Western)

Lemarie Rodelco

Com-Tek
6525 City West Parkway
Eden Prairie, MN 55344
(612) 941-7181
TWX: 310-431-0122
FAX: 612-941-4322

Limburg Stirum 243
1810Wemmel
Belgium
Tel: (32) 2-460-0560
FAX: (32) 2-460-0271

WISCONSIN (Eastern)
Beta Technology Sales, Inc.
9401 Beloit, Suite 409
Milwaukee, WI 53227
(414) 543-6609

CANADA
(BRITISH COLUMBIA)
Thorson Company Northwest
12340 N.E. 8th Street
Suite 201
Bellevue, WA 98005
(206) 455-91BO

WYOMING
Wasatch Pro Rep Marketing
360 East 4500 South, Suite 6
Salt Lake City, UT 84107
(801) 26B-3434

FAX: 801-266-9021

PENNSYLVANIA (Western)
Bear Marketing, Inc.
300 MI. Lebanon Blvd.
Pittsburg, PA 15234
(412) 531-2002
FAX: 412-531-2008

Micro Comp, Inc.
Rt. 2, Box 390
Huddleston, VA 24104
(703) 297-6295

INTERNATIONAL
SALES
REPRESENTATIVES

Electro Source
3665 Kingsway, Suite 300
Vancouver, B.C_ V5R 5W2
(604) 435-B066

FAX: 604-435-BI81
CANADA (ONTARIO)
Electro Source, Inc.
340 March Road, Suite 503
Kanata, Ontario K2K 2E3
(6t3) 592-3214
FAX: 613-592-4256
Electro Source, Inc.

230 Galaxy Boulevard
Re,dale, Ontario M9W 5RB
(416) 675-4490
FAX: 416-675-6871

~
CANADA (QUEBEC)
Electro Source
6600 TransCanada Hwy
Suite 420 Point Claire
Quebec H9R 4S2
(514) 630-7486
FAX: 514-630-7421
DENMARK
Dana Tech KS
PO Box 1361
Smedeland 8
2800 Glostrup
Denmark
Tel: (45) 2-4345 47
FAX: (45) 2-4345 67
FINLAND
Field OY Instrumentarium
Niittylanpolku 10
SF -00620
Helsinki, Finland
Tel: (358) 0-7571011
FAX: (358) 0-798853
FRANCE
Reptronic
1 Bis, rue Marcel Paul
Batimen R
Z.1. de la Bonde
F-91300 Massy
Tel: (33) 1-60139300
FAX: (33) 1-60139198
R.T.F. Composant
81, Rue Pierre Semard
92320 Chatillon sis Bagneux
France
Tel: (33) 1-49652700
FAX: (33) 1-49652738
R.T.F. Sud-Ouest
Avenue de la Mairie
31320 Escalquens, France
Tel: (33) 61-8151 57
FAX: (33) 61-81 5157
R.T.F. Aquitaine
13, Rue I'Hote
33000 Bordeaux, France
Tel: (33) 56-52 99 59
FAX: (33) 56-48 1783
R.T.F. Rhone-Auvergne
Parc Club du Moulin a Vent
BAt G.33, Rue du Doeteur
Levy
69200 Venissieux, France
Tel: (33) 78-000726
FAX: (33) 78-01 2057
R.T.F Provence Cote D'Azur
Residence du Petit Bosquet
BAt. C-18
Avenue du Petit Bosquet
13012 Marseilles, France
Tel: (33) 91-060218
FAX: (33) 91-06 4782

R.T.F. Rhone-Alpes
Mini Parc - Zac des Beali~res
23, Avenue de Granier
38240 Ebbens
Tel: (33) 76-90 11 88
FAX: (33)76-41 04 09

Malhar Corporation
924 County Line Road
Bryn Mawr, PA 19010
(215) 527-5020
FAX: (215) 525-7805

GERMANY

IRELAND

Metronik
Leonhardsweg 2
8025 Unterhaching
MOnchen, Germany
Tel: (49) 89-611080
FAX: (49) 89-6116468

Memec Ireland ltd.
Innovation Centre
Enterprise House
Plassey Technological Park
Limerick
Ireland
Tel: (353) 61-330742/5
FAX: (353) 61-3318-88

New Japan Radio Trading
Co., Ltd.
Shiba-Eitaro Bldg.
4-14 Shiba-Daimon l-chome,
Minato-ku,
Tokyo, 105 Japan
Tel: (03) 3459-1521
FAX: (03) 3459-1520

ISRAEL

Okura Electronics Co., ltd.
3-6, Ginza Nichome,
Chuo-ku, Tokyo, 104 Japan
Tel: (03) 3564-6871
FAX: (03) 3564-6870

Metronik

Semerteichstrasse 92
4600 Dortmund 30
Dortmund, Germany
Tel: (49) 231-423037/38
TLX: (49) 8227082
Metronik
Osterbrooksweg 61
2000 Schenefeld
Hamburg, Germany
Tel: (49) 40-8304061
TLX: (49) 2162488
Metronik

Siemensstrasse 4-6
6805 Heddesheim
Mannheim, Germany
Tel: (49) 62-034701-03
TLX: (49) 465053
Metronik

Laufamholzstr.118
8500 NDrnberg 30
NDrnberg, Germany
Tel: (49) 911-590061/62
TLX: (49) 626205
Metronik
Lbwenstr. 37
7000 Stuttgart 70
Stuttgart, Germany
Tel: (49) 711-764033/35
TLX: (49) 7255228
GREECE
Peter Caritato and Assoc. S. A.

Ilia Iliot, 31
Athens 11743 Greece
Tel: (30) 1-9020165
FAX: (30) 1-9017024
HONG KONG
Excel Associates, Ltd.
1502 Austin Tower
22-26A Austin Avenue
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 3-7210900
FAX: (852) 3-696826

INDIA

Dia Semicon Systems, Inc.

THE NETHERLANDS

Flower-Hill Shin-Machi
East Bldg.
1-23-9 Shin-machi,
Setagaya-ku,
Tokyo, 154 Japan
Tel: (03) 3439-2700
FAX: (03) 3439-2701

Rodelco BV Electronics
Takkebijsters 2
P.O. Box 6824
4802 HV Breda
The Netherlands
Tel: (31) 76-784911
FAX: (31) 76-710029
NORWAY
8.I.T. Elektronikk SA
P.O. Box 36 Lerbyen
N-3401 Lier, Norway
Tel: (47) 3-8470 99
FAX: (47) 3-84 55 10
SOUTHEAST ASIA

E.I.M International ltd.
8 Emil ZolaSt.
P.O. Box 4000
Petach Tiqva
Israel 49130
Tel: (972) 3-92 33257
FAX: (972) 3-9244857
ITALY
ACSIS S.R.L.
Via Alberto Mario. 26
20149 Milano, Italy
Tel: (39) 2-4390832
FAX: (39) 2-4697607
Celdis Italiana S.PA
Via F.ill Gracchi N36
20092 Cinisello Balsamo
Milano, Italy
Tel: (39) 2-61 8391
FAX: (39) 2-61 73513
Celdis Italiana S.P.A.
Via Massarenti 219/4
40138 Bologna, Italy
Tel: (39) 51-533336
Celdis Italiana S.PA
Via Savelli 15
351 00 Padova, Italy
Tel: (39) 49-77 209 9
Celdis italiana S.P.A.
Via G. Pitre' 11
00162 Roma, Italy
Tel: (39) 6-428971
Celdis ltaliana S.PA
Via Mombarcaro 96
10136 Torino,italy
Tel: (39) 11-3299388
JAPAN
Okura & Co., Ltd.
6-12, Ginza Nichome
Chuo-Ku
Tokyo, 104 Japan
Tel: (03) 3566 6361
FAX: (03) 35635447

R.T.F. Ouest
3, rue de Paris
35510 Cesson Sevigne,
France
Tel: (33) 99-83 84 85
FAX: (33) 99-83 80 83

Okura Electronics Service
Co., ltd.
Kyoei Bldg.
5-3, Kyobashi 3-chome,
Chuo-ku, Tokyo, 104 Japan
Tel: (03) 3567-6501
FAX: (03) 3567-7800
Tokyo Electron Limited

P. O. Box 7006
Shinjuku Monolith
3-1 Nishi-Shinjuku 2-chome,
Shinjuku-ku,
Tokyo, 163 Japan
Tel: (03) 3340-8193
FAX: (03) 3340-8408
Towa Elex Co., ltd.
Lapore Shinjuku
2-15-2 Yoyogi,
Shibuya-ku, Tokyo, 151
Japan
Tel: (03) 5371-3411
FAX: (03) 5371-4760
Varex Co., Ltd.
Nippo Shin-Osaka No.2 Bldg.
1-8-33, Nishimiyahara,
Yodogawa-ku,
Osaka, 532 Japan
Tel: (06) 394-5201
FAX: (06) 394-5449
KOREA
Excel-Tech
410-5 Hapjeong-Dong
Mapo-Gu
Seoul, Korea
Tel: (82) 2-3357823
FAX: (82) 2-3357825

Excel Associates, ltd.
1502 Austin Tower
22-26A Austin Avenue
TSimshatsui, Kowloon
Hong Kong
Tel: (852) 3-7210900
FAX: (852) 3-696826
SPAIN
ADM Electronica SA
Menorea No.3 Entreplants
Madrid 28009
Spain
Tel: (34) 1-4094725
FAX: (34) 1-4096903
SWEDEN
DJ.P. Electronics AB
Danvik Centre
P.O. Box 15046
S-104 65 Stockholm, Sweden
Tel: (46) 8-4491 90
FAX: (46) 8-430047
SWITZERLAND
Data Comp AG
Silbernstrasse 10

CH-8953 Dietikon
Zurich, Switzerland
Tel: (41) 1-7405140
FAX: (41) 1-7413423
TAIWAN
Molecatex, Inc.
21F 258 Sec3
Nanking East Road
Taipei, Taiwan R.O.C.
Tel: (886) 2-7410400
FAX: (886) 2-7217461
Jeritron Ltd.
SlF Fu San Building
1182 Cheng-Teh Road
Taipei, Taiwan, R.O.C.
Tel: (886) 2-8823154
FAX: (886) 2-8820710
UK
Memec

17 Thame Park Road
Thame
Oxon OX93XD
England
Tel: (44) 84-4261939
FAX: (44) 84-4261678

151<9190

8-7

•

Sales Offices
Distributed in North America By
Hamilton/Avnet
locations throughout
the U.S. and Canada.
1-800-HAM-ASIC
FAX: 408-743-3003

Western Microtechnology
12900 Saratoga Ave.
Saratoga, CA 95070
(408) 725-1660
TWX: 910-338-0013
FAX: 408-255-6491

Insight Electronics
6885 Flanders Drive
San Diego, CA 92121
(619) 587-9757
TWX: 183035-UD
FAX: 619-587-1380

Marshall Industries
locations throughout
the U.S. and Canada.
(818) 459-5500
FAX: 818-459-5660

8-8

Phase 1 Technology
Corporation
1110 Rte. 109
N. Lindenhurst, NY 11757
(516) 957-4900
FAX: 516-957-4909

Nu Horizons
Electronics Corp.
6000 New Horizons Blvd.
Amityville, New York 11701
(516) 226-6000
FAX: 516-226-6262

For Further Information .. .Please check the appropriate box
o Please have a Sales Representative call me.
o I would like to borrow a copy of your Logic Cell Array
Technical Demonstration Video.
o Please add my name to your mailing list.
My application is _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
I have a new design starting in _ _ weeks _ _ months
Name_~

_ _ _ _ _ _~-- Title _ _ _ _ _ _ _ _ _ __

Company _ _ _ _ _ _ _ _ _ _ N V S - - - - - - - - - - Street Adilless _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
City _ _ _ _ _ _ _ _ _ __
State _ _ _ _ _ _ Zip _ _ __
Phone ( ____ ) _ _ _ _ _ __

The Programmable Gate Array Company

For Further Information .. .Please check the appropriate box
o Please have a Sales Representative call me.
o I would like to borrow a copy of your Logic Cell Array
Technical Demonstration Video.
o Please add my name to your mailing list.
My application is _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
I have a new design starting in _ _ weeks _ _ months
Name _ _ _ _ _ _ _ _ _ _ _ Title _ _ _ _ _ _ _ _ _ ___
Company----_ _ _ _ _ _

NVS ___________

Street Adilless _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
City _ _ _ _ _ _ _ _ _ _ __
State _ _ _ _ _ _ Zip _ _ __
Phone ( ___ ) _ _ _ _ _ __

The Programmable Gate Array Company

NO POSTAGE
NECESSARY
IF MAILED
IN THE
UNITED STATES

BUSINESS REPLY MAIL
FIRST CLASS

PERMIT NO. 8051

SAN JOSE, CA

POSTAGE PAID BY ADDRESSEE

XILINX

2100 Logic Drive
SanJose, CA 95124-9920

II Ii 1111 Ii 1111111 Ii 11111111 Ii III Ii III dlllllllid I Ii

NO POSTAGE
NECESSARY
IF MAILED
IN THE
UNITED STATES

BUSINESS REPLY MAIL
FIRST CLASS

PERMIT NO. 8051

SAN JOSE, CA

POSTAGE PAID BY ADDRESSEE

XILINX

2100 Logic Drive
San Jose, CA 95124-9920

Ildllllllllllllldlllllllllllllllllllllllllllllllll

1:XILINX
The Programmable Gate Array Company.
2100 Logic Drive, San Jose, CA 95124.

Printed in U.

Tel: (408) 559-7778 EasyLink 629 16309

1WX: 5106008750 X1L1NX UQ

FAX: (408) 559-7114

PIN 0010048
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