1991_Zilog_Datacom_ICs 1991 Zilog Datacom ICs

User Manual: 1991_Zilog_Datacom_ICs

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Table of Contents
Product Specifications

Product Number

Page

Product Migration Chart ................................................................................................................................................................................................:.1
Z16C30 CMOS USCTMUniversal Serial Controller ................................................................ Z16C3010VSCNEC/GEE ................................................. 3
Z16C311USCTMIntegrated Universal Serial Controller ........................................................... Z16C312OVSC ..............................................................77
Z16C33 CMOS MUSCTMMono-Universal Serial Controller .................................................. Z16C3310VSC ..............................................................85
Z16C35 CMOS ISCCTMlntegrated Serial Communications Controller ................................... Z16C351OVSC/16VSC ................................................167
Z16C50 DDPLLTMDual Digital Phase Locked Loop Microcontroller ...................................... Z16C5010PSC/20PSC ................................................ 225
Z5380 CMOS SCSI Small Computer System Interface ........................................................... Z53801OPSCNSC ....................................................... 231
Z85230 CMOS ESCCTMEnhanced Serial Communication Controller .................................... Z8523010PSCNSC, 20PSCNSC ............................... 267
Z8OC30/Z85C30 CMOS Z-BUS· SCCTMSerial Communication Controller .......................... Z80C3008PSCNSC, 10PSCNSC ............................... 305
Z85C3008PSC/PECNSCNEC/CEE
Z85C3010PSC/PECNSCNEC/CEE
Z85C3016PSCNSC
Z8030/Z8530 Z-BUS· SCCTMSerial Communication Controller ........................................... Z803006PSC/DSfJ\ISC ............................................... 345
Z803008PSC/DSfJ\lSC
Z0853004PSC
Z0853006PSC/DEC/DSfJ\ISC
Z0853008PSC/DSE/DEA/VSC
Z80181 CMOS SACTMSmart Access Controller ...;................................................................. Z801811OFEC/12FEC .................................................. 370
Z84013/015 Z84C13/C15IPCTMlnteUigent Peripheral Controller .......................................... Z8401306VEC/10VEC ................................................. 441
Z84C1306VEC/10VEC
Z8401506FEC/10FEC
Z84C1506/1OFEC
Z8440/Z84C40 SIO (See Ordering Information for available speeds, 'XX' replacements) ...... Z08440XXPSC/DSE .................................................... 505
Z08441XXPSC/DSE
Z08442XXPSC/DSE
Z08444XXVSC
Z844C4OXXPEC/DEE
Z84C41XXPEC/DEE
Z84C42XXPEC/DEE
Z84C43XXFEC
Z84C44XXVEC
Z85C80 SCSCITMSerial Communication and Small Computer Interface ................................ Z85C8010VSC ............................................................529

Application Notes .
Design aSerial Board to Handle Multiple Protocols ....................................................................................................................................................591
Using the Z16C30 USC Universal Serial Controller with MIL-STD-1553B ..................................................................................................................603
Datacommunications IUSC/MUSC Time Slot Assigner .................................................................................._...........................................................617
ISCC Inleaace to the ~ and 8086· .............................................................................................................................................................................................................................621
The Z180 SCC Interfaced with the SCC at 10 MHz ......................................................................................................................................................631
Using SCC with
in SDLC Protocol .................................................................................................................................................................665
SCC In Binary Synchronous C.omm~nications ...............................,............................................................................................................................677
On-Chip OSCillator DeSign ..........................................................................................................................................................................................687
Interfacing the Z8500 Peripherals to the 68000 ...........................................................................................................................................................697
Interfacing Z80tPUs to the Z8500 Peripheral Family ...:.............................................................................................................................................709

zaooo-

Additional Information
Datacom Product Support ..............................................................................:,...........................................................................................................733
Military Qualified Datacom Products ...........................................................................................................................................................................739
Quality and Reliability .............:................................................;...................................................................................................................................741
Literature Guide ...........................................................................................................................................................................................................743
Package Information ....................................................................................................................................................................................................747
Ordering Information ...................................................................................................................................................................................................751

DATACOM PRODUCTS

Z84C15

SAC

Z181

Zl80+8CC

MUSC
Z1ISC33

Mt.. c~_..
MlB.........
lIAlor 180N

IOSC
Z11SC31

_,..IIe..

. . . . Q ......

WIllI 0100 aad
lIA I,r liON

ISCC
Z18C36
2C11aa8CC
+4_

SCSI
2C11n8CC
+8C81

ESCC

USC

Z8S230

Z11SC3O

2C11nSCC
+ OH, RFOs

~ZiIill

PRODucrSPECIRCAnON

Z16C30
CMOS USC
UNIVERSAL SERIAL CONTROLLER
FEATURES
_

Transparent Bisync mode with EBCDIC or ASCII
character code; automatic CRG handling;
programmable idle line condition; optional preamble
transmission; autOmatic recognition of OLE, SYN, SOH.
ITX, ETX, ETB, EOT, ENQ and ITB.

12.5 MByte/sec (16-bit) data bus bandwidth

Extemal character sync mode for receive

Multi-protocol operation under program control with
Independent mode selection for receiver and
transmitter.

HDLC/SDLC mode with eight bit address compare,
extended address field option; 16- or 32-bit CRC,
programmable idle line condition; optional preamble
transmission and loop mode.

Async mode with one to eight bits/character, 1/16 to 2
stop bits/character in 1/16 bit increments;
programmable clock factor; break detect and
generation; odd, even, mark, space or no parity and
framing error detection Supports one Address/Data
bit and MIL STD 1553B prptocols.

DMA interface with separate request and acknowledge
for each receiver and transmitter.

Channel load command for DMA controlled
initialization.

Flexible bus interface for direct connection to most
microprocessors; user programmable for 8 or 16 bits
w.ide Directly supports 680XO family or 8X86 family
bus interfaces.

Low power CMOS

68-pin PLCC package

Two independent, 0 to 10 Mbit/sec, full duplex channels,
each with two baud rate generators and one digital
phase-locked loop for clock recovery.

32-byte data FIFO's for each receiver and transmitter

Byte oriented synchron6us mode with one to eight
bits/character; programmable idle line condition;
optional receive sync stripping; optional preamble
transmission, 16- or 32-bit CRC and transmit-tO:receive
slaving (for X.21)

Bisync mode with 2- to 16-bit programmable sync
character; programmable idle line condition; optional
receive sync stripping; optional preamble transmission;
16- or 32-bit CRC.

GENERAL DESCRIPTION
The USC Universal. Serial Controller is a dual-channel
multi-protocol data communications peripheral designed
for use with any conventional multiplexed or non-multiplexed
bus. The USC functions as a serial-to-parallel, parallel-toserial converter/controller and may be software configured to satisfy a wide variety of serial communications

applications. The device contains a variety of new, sophisticated intemal functions including two baud rate generators
per channel, a digital phase-locked loop per channel,
character counters for both receive and transmit in each
chan riel and 32-byte data FIFO's for each receiver and
transmitter.

GENERAL DESCRIPTION (Continued)
The USC handles asynchronous formats, synchronous
byte-oriented formats such as BISYNC and synchronous
bit-oriented formats such as HDLC. This device supports
virtually any serial data transfer application.
The device can generate and check CRC in any synchronous mode and can be programmed to check data integrity
in various modes. The USC also has facilities for modem
controls in both channels. In applications where these
controls are not needed, the modem controls may be used
for general-purpose I/O. The same is true for most of the
other pins in each channel.
Interrupts are supported with a daisy-chain hierarchy, with
the two channels having completely separate interrupt
structures.
High-speed data transfers via DMA are supported by a
RequesVAcknowledge signal pair for each receiver and

trarismitter. The device supports' automatic status transfer
via DMA and also allows device initialization urider DMA
control.
To aid the designer in efficiently programming the USC,
support tools are available. The Technical Manual describes in detail all features presented in this Product
Specification and gives programming sequence hints.
The Programmer's Assistant is a MS-DOS disk-l:ilased
programming initialization tool to be used in conjunction
with the TechniGal Manual. There are also available assorted
application notes and development boards to assist the
designer in the hardware/software development.
Note: All Signals with a preceding front slash, "/", are active
Low, e.g.: BIIW (WORD is active Low); IBIW (BYTE is
active Low, only); INIIS (NORMAL and SYSTEM are both
active LOW).

To Other Channel

Receive DMA
Control

Receive 0 ala

I
Receive
FIFO (32 byte)

rimaryfunction of these signals
is to perform fly-by DMA transfers from the receive FIFOs:
They may also be used as bit inputs or outputs. '
TxOA, TxDB. Transmit Data (outputs, active High, 3-state).
These signals carry the serial transmit data for each
ctiannel.

IRxREQA,/RxREQB. Receive Request(inputs or outputs,
active low). The primary function of these signals is to
request DMA transfers trom the receive FIFOs. They may
also be used as simple inputs or outputs.

RxOA, RxOB. Receive Data (inputs, active High). l'hese
signals carry the serial receive data for each channel.
fTxCA, fTxCB. Transmit Clock (inputs or outputs, active
low). These signals are used as clock inputs for any of the
functional blocks within the device. Theymay also be used
as outputs for various transmitter signals or internal clock
signals.
IRxCA, IRxCB. Receive Clock (inputs or outputs, active
low). These Signals are used as clock inputs for any of the
fuhctional blocks within the device. They may also be used
as outputs for various receiver signals or internal, clock
signals.

ICTSA, ICTSB. Clear To Send (inputs or outputs, active
low). These signals are used as enables for the respective
transmitters. They may also be programmed to generate
interrupts on either transition or used as simple inputs or
outputs.
I

IOCOA, IOCOB. Data Carrier Detect (inputs or outputs,
active low). These signals are used as enables for the
respective receivers. They may also be programmed to
generate interrupts on either transitfon or used as simple
inputs or outputs. ,

ARCtUTECTURE
The USC internal structure includes two completely indep~ndent full-duplex serial channels, eacb with two baud
rate generators, a digital phase-locked loop for clock
recovery, transmit and receive character counters and a
full-duplex DMA interface. The two serial channels share a
common bus interface. The bus interlace is designed to
provide easy interface to most microprocessors, whether

they employ a multiplexed or non-multiplexed, 8-bit or
16-bit bus structure. Each channel is controlled by a set of
thirty 16-bil registers, nearly all of which are readable and
writable. There is one additional 16-bit register in the bus
interface used to configure the nature of the bus interface.
The BCR functions are shown in Figure 4.

Address: None

ID"H~"+rIOO'OO'",'OO'i'~''''~ ~==
-

Reserved

3-State

Al' Pins

Separate Address lor 8-Bit Bus

Must be" programmed as O.

Figure 4. Bus Configuration Register

DATA PATH
Both the transmitter and the receiver in the channel are
actually microcoded serial processors. As the data shifts
through the transmit or receive shift register, the miCrocode watches for specific bit patterns, counts bits, and at

the appropriate time transfers data to or from the FIFOs.
The microcode also checks status and generates status
interrupts as appropriate.

FUNCTIONAL DESCRIPTION
The functional capabilities of the USC are described from
two different points of view: as a data communications
device, it transmits and receives data in a wide variety of
data communications protocols; as a microprocessor
peripheral, the USC offers such features as read/write
registers, a flexible bus interface, DMA interface support
and vectored interrupts.

Data Communications Capabilities
The' USC provides two independent full-duplex channels
programmable for use in any common data communication protocol. The receiver and transmitter modes are
completely independent, as are the two channels. Each
receiver and transmitter is supported.by a 32-byte deep
FIFO and a 16-bit message length counter. All modes
allow optional even, odd, mark or space· parity. Synchro- '
nous modes allow the choice of two 16-bit or one 32-bit
CRC polynomial. Selection of from one to eight bits-percharacter is available in both receiver and transmitter,
independently. Error and status conditions ale carried with
the data in the receive and transmit FtFOs to greatly reduce
the CPU overhead required to send or receive a message.
SpeCific, appropriately timed interrupts are available to
signal such conditions as overrun, parity error, framing
error, end-of-frame, idle line received, sync acquired,

transmit underrun, eRe sent, clOSing sync/flag sent, abort
sent, idle line sent and preamble sent. In addition, several
useful internal signals such as receive FIFO load, received
sync, transmit FIFO read and transmission complete may
be sent to pins for use by external circuitry.
Asynchronous Mode. The receiver and transmitter can
handle data at a rate of 1/16, 1/32, or 1/64 the ciock rate.
The receiver rejects start bits less than one-half a bit time
and will not erroneously assemble characters following a
framing error. The tranSmitter is capable of sending one,
two, or anywhere in the range of 1/16th to two stop bits per
character in 1/16 bit increments.
External Sync Mode. The receiver is synchronized to the
receive data stream by an externally-supplied signal on a
pin for custom protocol applications.
,Isochronous Mode. Both transmitter and receiver may
operate on start-stop (async) data using a 1x cioc~. The
transmitter can send one or two stop bits.
Asynchronous With Code Violations. This is similar to
Isochronous mode except that the start bit is replaced by
a three bit-time code violation pattern as in MIL-8TD
1553B. The transmitter can send zero, one or two stop bits.

FUNCTIONAL DESCRIPTION (Continued)
Monosync Mode. In this mode, a single character is used
for synchronization. The sync character can be either eight
bits long with an arbitrary data character length, or programmed to match !he data character length. The r~ceiver
is capable of automatically stripping sync characters from
the received data stream. The transmitter may be programmed to automatically send CRC on either an underrun
or at the end of a programmed message length.
Bisync Mode. This mode is identical to monosync mode
except that character synchronization requires two successive characters for synchronization. The two characters
need not be identical.

Slaved Monosync Mode. This mOd.e is available only in the
transmitter and allows the transmitter (o/J€rating as though
it were in monosync mode) to send data that is bytesynchronous to the data being received by the receiver.
HOLC Loop Mode. This mode is also available only in the
transmitter and allows the USC to be used in' an HDLC loop
configuration. In this mode, the receiver is programmed to
operate in HDLC mode so that the transmitter echos
received messages. Upon receipt of a particular bit pattern (actually a sequence of seven consecutive ones) the
transmitter breaks the loop and inserts its own frame(s).

Data Encoding
HOLC Mode. In this mode, the receiver recognizes flags,
performs optional address matching, accommodates extended address fields, 8- or 16-bit control fields and logical
control fields, performs zero deletion and CRC checking.
The receiver is capable of receiving shared-zero flags,
recognizes the abort sequence and can receive arbitrary
length messages. The transmitter automatically sends
opening and closing flags, performs zero insertion and
can be programmed to send an abort, an extended abort,
a flag or CRC and a flag on transmit underrun. The
transmitter can also automatically send the closing flag
with optional CRC at the end of a programmed message
length. Shared-zero flags are selE1cted in the transmitter
and a separate character length may be programmed for
the last character in the frame.
Bisync Transparent Mode. In this mode, the synchronization pattem is DLE-SYN, progr-ammable selected from
either ASCII or EBCDIC encoding. The receiver recognizes
control character sequences and automatically handles
CRC calculation without CPU intervention. The transmitter
can be programmed to send either SYN, DLE-SYN, CRCSYN, or CRC-DLE-SYN upon underrun and can automatically send the closing DLE-SYN with optional CRC at
the end of a programmed message length.

The USC may be programmed to encode and decode the·
serial data in any of eight different ways as shown in
Figure 5. The transmitter encoding method is selected
i~dependently of the receiver decoding method. .
NRZ. In NRZ, a. 1 is represented by a High level for the
duration of the bit cell and a 0 is represented by a Low level
for the duration of the bit cell.
NRZB. Data is inverted from NRZ.
NRZI-Mark. In NRZI-Mark, a 1 is represented by a transition at the beginning of the bit cell That is, the level present
in the preceding bit cell is reversed. A 0 is represented by
the absence of a transition at the beginning of the bit cell.
NRZI-Space. In NRZI-Space, a 1 is represented by the
absence of a transition at the beginning of the bit cell. That
is, the level present in the preceding bit cell is maintained.
A 0 is represented by a transition at the beginning of the
bit cell.
.
Biphase-Mark. In Biphase-Mark, a 1 is represented by a
transition at the beginning of the bit cell and anofher
transition at the center of the bit cell. A 0 is represented by
a transition at the beginning of the bit cell only.

NBIP Mode. This mode is identical to async except that the
receiver checks for the status of an additional addressl
data bit between the parity bit and the stop bit. The value
of this bit is FIFO'ed along with the data. This bit is
automatically inserted in the transmitter with the value that
is FIFO'ed with the transmit data.

Biphase·Space. In Biphase-Space, a 1 is represented by
a transition at the beginning of the bit cell only. A 0 is
. represented by transition at the beginning of the bit cell
and another transition at the center of the bit cell.

802.3 Mode. This mode implements the data format of
IEEE 802.3 with 16-bit address compare In this mode,
lOCO and ICTS are used to implement the carrier sense
and collision detect interactions with the receiver and
transmitter.

Data
NRZ

I
I
I

I
I
I,

NRZl-M

NRZI-S

~
I

\.
1

'/
I

NRZB

I
I

BI-PHASE-M

BIPHASE-S

BIPHASE-L
DIFFERENTIAL
BIPHASE-L

I
I

Figure 5. Data Encoding

Differential Biphase-Level. In Differential Biphase-Level,
a 1 is represented by a transition atthe center olthe bit cell,
with the opposite polarity from the transition at the center
of the preceding bit cell. A 0 is represented by a transition
at the center of the bit cell with the same polarity as the
transition at the center of the preceding bit cell. In both
cases there may be transitions at the beginning of the bit
cell to set up the level required to make the correct center
transition.

Character Counters
Each channel in the USC contains a 16-bit character
counter for both receiver and transmitter. The receive
character counter may be preset either under software
control or automatically at the beginning of a receive
message. The counter decrements with each receive
character and at the end of the receive message the
current value in the counter is automatically loaded into a
four-deep FIFO. This allows DMA transfer of data to proceed without CPU intervention at the end of a received
message, as the values in the FIFO ailow the 8PU to
determine message boundaries in memory. Similarly, the
transmit character counter is loaded either under software
control or automatically' at the beginning of a transmit
m,essage. The counter is decremented with each write to
the transmit FIFO. When the counter has decremented to

zero, and that byte is sent, the transmitter automatically
terminates the message in the appropriate fashion (usually
CRC and the closing flag or sync character) without
requiring CPU intervention.

Baud Rate Generators
Each channel in the USC contaIns two baud rate generators
Each generator consists of a 16-bit time constant register
and a 16-bit down counter. In operation, the counter
decrements with each baud rate generator clock, with the
time constant automatically reloaded when the count
reaches zero. The output of the baud rate generator
\ toggles when the counter reaches a count of one-half ofthe
time constant and again when the counter reaches zero.
A new time constant may be written at any time but the new
value will not take effect until the next load of the counter.
. The outputs of both baud rate generators are sent to the
clock multiplexer for use internally or externally. ·The baud
rate generator output frequency is related to the baud rate
generator input clock frequency by the following formula'
Output frequenoy =
Input frequency/(time constant + 1)
This allows an o!Jtp~tfrequency in the range of 1 to 1/65536
of the input frequency, inclusive.
\

.'"

""'''''I'I!"r~~----~-~-~--~

___

Digital Phase-Locked Loop
Each channel in the USC contains a Digital Phase-Locked
Loop (DPLL) to recover clock information from a data
stream with NRZI or Biphase encoding. The DPLL is driven
by a clock that is nominally 8, 16 or 32 times the receive
data rate. The DPLL uses this clock, along the data stream,
to construct a clock for the data. This clock may then be
routed to the receiver, transmitter, or both, or to a pin for
use externally. In all modes, the DPLL counts the input
clock to create nominal bit times. As the clock is counted,
the DPLL watches the incoming data stream fortransitions.
Whenever a transition is detected, the DPLL makesa count
adjustment (during the next counting cycle), to produce an
output clock which tracks the incoming bit cells. The DPLL
provides properly phased transmit and receive clocks to
the clock multiplexer.

Counters
Each channel contains two 5-bit counters, which we
programmed to divide an input clock by 4, 8, 16 or 32. The

inputs of these two counters are sent to the clock multiplexer. The counters are used as prescalers for the baud
rate generators, or to provide a stable transmit clock from
a common source when the DPLL is providing the receive
clock.
.

Clock Multiplexer
The clock multiplexer in each channel selects the clock
source for the various blocks in the channel and selects an
internal clock signal to potentially be sent to either the /RxC
or /TxC pin.

Test Modes
The USC is programmed for localloopback or auto echo
operation. In localloopback, the output of the transmitter
is internally routed to the input of the receiver. This allows
testing of the USC data paths without any external logic.
Auto echo connects the RxD pin directly to the TxD pin.
This is useful for testing serial links external to the USC.

1/0 INTERFACE CAPABILITIES
The USC offers the choice of polling, interrupt (vectored or
non-vectored) and block transfer modes to transfer data,
status and control information to and from the CPU.

six groups also have interrupt enable bits which are set for
the particular source. In addition, there is a Master Interrupt Enable (MIE) bit in each channel which globally
enables or disables interrupts within the channel.

Polling
All interrupts are disabled. The registers in the USC are
automatically updated to reflect current status. The CPU
polls the Daisy Chain Control Register (DCCR) to determine status changes and then reads the appropriate
status r(lgister to find and respond to the change in status.
USC status bits' are grouped according to function to
simplify this software action.

Interrupt
When a USC responds to an interrupt acknowledge from
the CPU, an interrupt vector may be placed on the data
bus. This vector is held in the Interrupt Vector Register
(IVR). To speed interrupt response time, the USC modifies
three bits in this vector to indicate which type of interrupt
is being requested.
Each of the six sources of interrupts in each channel of the
USC (Receive Status, Receive Data, Transmit Status,
Transmit Data, I/O Status and Device Status) has three bits
associated with the interrupt source: Interrupt Pending
(IP), Interrupt-Under-Service (IUS) and Interrupt Enable
(IE). If the IE bit for a given source is set. that source. can
request interrupts. Note that individual sources within the

The other two bits are related to the interrupt priority chain.
A channel in the USC may request an interrupt only when
no higher priority interrupt source is requesting one, e g.,
when lEI is High for the channel. In this case the channel
activates the /INT signal. The CPU then responds with an
interrupt acknowledge cycle, and the interrupting channel
places a vector on the data bus.
In the USC, the IP bit signals that an interrupt request is
being serviced. If an IUS is set, all interrupt sources of
lower priority within the channel and external to the channel
are prevented from requesting interrupts. The internal
interrupt sources are inhibited by the state of the internal
daiSy chain, while lower priority devices are inhibited by
the lEO output of the channel being pulled Low and
prQpagated to subsequent peripherals. An IUS bit is set
during an interrupt acknowledge cycle if there are no
higher priority devices requesting interrupts.
There are six sources of interrupt in each channel' Receive
Status, Receive Data, Transmit Status, Transmit Data, I/O
Status and Device Status. prioritized in that order within the
channel There are six sources'of Receive Status interrupt,
each individually enabled: exited hunt, idle line, break/
abort, code violation/end-of-transmission/end-of-frame,

parity error and overrun error. The Receive Data interrupt
is generated whenever the receive FIFO fills with data
beyond the level programmed in the Receive Interrupt
Control Register (RICR).
There are six sources of Transmit Status interrupt, each
individually enabled: preamble sent, idle line sent. abort
sent, end-of-frame/end-of-transmission sent. CRC sent
and underrun error. The Transmit Data interrupt is generated whenever the transmit FIFO empties below the level
programmed in the Transmit Interrupt Control Register
(TICR). The I/O Status interrupt serves to report transitions
on any of six pins. Interrupts are generated on either or
both edges with separate selection and enables for each
pin. The pins programmed to generate I/O Status interrupts are /RxC, /TxC, /RxREQ, /TxREQ, /DCD and /CTS.
These interrupts are independent of the programmed
function of ttie pins. The Device Status interrupt has four
separately enabled sources: receive character count FIFO
overflow, DPLl sync acquired, BRG1 zero count and
BRGO zero count.

Block Transfer Mode
The USC accommodates block transfers via DMA through
the /RxREQ, /TxREQ, /RxACK and /TxACK pins. The
/RxREQ signal is activated when the fill level of the receive
FIFO exceeds the value programmed in the RICR. The
DMA may respond with either a normal bus transaction or
by activating the /RxACK pin to read the data directly (flyby transfer). The /TxREQ signal is activated when the
empty level of the transmit FIFO falls below the value
programmed in the TICR. The DMA may respond either
with a normal bus transaction or by activating the
/TxACK pin to write the data directly (fly-by transfer). The
/RxACK and /TxACK pin functions for this mode are controlled by the Hardware Configuration Register (HCR).
Then using the /RxACK and /TxACK pins to transfer data,
no chip select is necessary; these are dedicated strobes
for the appropriate FIFO.

PROGRAMMING
The Programmers Assistant (MS DOS based) and Technical Manual are available to provide details about
programmming the USC. Also included are explanations
and features of all registers in the USC
The registers in each USC channel are programmed by the
system to configure the channels. Before this can occur,
however, the system must program the bus interface by
writing to the Bus Configuration Register (BCR). The BCR
has no specific address and is only accessible immediately
after a hardware reset of the device. The first write to the
USC, after a hardware reset. programs the BCR. From that
time on the normal channel registers may be accessed. No
speCific address need be presented to the USC for the
BCR write; the USC knows that the first write after a
hardware reset is destined for the BCA.
In the multiplexed bus case, all registers are directly
addressable via the address latched by /ASatthe beginning
of a bus transaction. The address is decoded from either
AD6-ADOor AD7-AD1. Thisis controlled by the Shift RighV
Shift Left bit in the BCR. The address maps for these two
cases are shown in Table 1. The DI/C pin is still used to
directly access the receive and transmit data registers
(RDR and TDR) in the multiplexed bus; if D//C is High the
address latched by lAS is ignored and an access of RDR
or TDR is performed.
In the non-multiplexed bus case, the registers in each
channel are accessed indirectly using the address pointer
in the Channel Command/Address Register (CCAR) in
each channel. The address of the desired register is first

written. to the CCAR and then the selected register is
accessed; the pOinter in the CCAR is automatically cleared
after this access. The RDR and TDR are accessed directly
using the D//C pin, without disturbing the contents of tile
pointer in the CCAR.
Table 1. Multiplexed Bus Address Assignments
Shift Left

Shift Right

Byte/IWord Access
Address 4
Address 3

AD?
AD6
ADS

AD6
ADS
AD4

Address 2
Address 1
Address 0
Upper/flower Byte Select

AD4
AD3
AD2
AD1

AD3
AD2
AD1
ADO

Address Signal

There are two important things to note about the USC. First.
the Channel Reset bit in the CCAR places the channel in
the reset state. To exit this reset state either a word of all
zeros must be written to the CCAR (16-bit bus) or a byte of
all zeros must be written to the lower byte of the CCAR
(8-bit bus). The second thing to note is that after reset. the
transmit and receive clocks are not connected. The first
thing that should be done· in any initialization sequence is
a write to the Clock Mode Control Register (CMCR) to
select a clock source for the receiver and transmitter.
The register addressing is shown in Table 2. and the bit
assignments for the registers are shown in Figure 6.

Reset
Any Transaction
Up To and Including
BCR Write

NoiAS

At Least One lAS

NonMultiplexed
Bus

BCR
Write
Transaclion

Multiplexed
Bus

I
BCR[2)=O
BCR[15)=1

BCR[2)=O
BCR[15)=O

8-Bit With
Separate
Address

8- Bit Without
Separate
Address

I
BCR[2)=1

BCR[2)=O
BCR[15)=1

16-Bit

8-Bit With
Separate
Address

BCR[2)=O
BCR[15)=O

8-Blt Without
Separate
Address

BCR[2)=1

~
16-Bit

Note:
,
The presence of one transaction wfth an lAS active, between reset up to
and including the BeR wrfte, chooses a multiplexed type of bus.

Figure 6. BeR Reset Sequence and Bit Assignments

Table 2. Register Address List
Address
A4-A0

Address
A4-A0

00000
00001
00010
00011

CCAR
CMR
CCSR
CCR

Channel
Channel
Channel
Channel

00110
00111
01000
01001

TMDR
TMCR
CMCR
HCR

01010
01011
01100
01101
01110
01111
1xo06
10001

Command/Address Register
Mode Register
Command/Status Register
Control Register

10010
10011
10100
10101

RCSR
RICR
RSR
RCLR

Receive
Receive
Receive
Receive

Command/Status Register
Interrupt Control Register
Sync Register
Count Limit Register

Test Mode Data Register
Test Mode Control Register
Clock Mode Control Register
Hardware Configuration Register

10110
10111
1XOOO
11001

RCCR
TCOR
TDR
TMR

Recieve Character Count Register
Time Constant 0 Register
Transmit Data Register (Write Only)
Transmit Mode Register

IVR
IOCR
ICR
DCCR

Interrupt Vector Register
I/O Control Register
Interrupt Control Register
Daisy-Chain Control Register

11010
11011
11100
11101

TCSR
TICR
TSR
TCLR

Transmit Command/Status Register
Transmit Interrupt Control Register
Transmit Sync Register
Transmit Count Limit Register

MISR
SICR
RDR
RMR

Misc Interrupt Status Register
Status InterruptControl Register
Receive Data Register (Read Only)
Receive Mode Register

11110
11111

TCCR
TC1R

Transmit Character Count Register
Time Constant 1 Register

XXXXX

BCR

Bus Configuration Register

CONTROL REGISTERS
Address: 00000

Upperl/Lower Byte Select (WO)
Address 0 (WO)
Address 1 (WO)
Address 2 (WO)
Address 3 (WO)
Address 4 (WO)
Byte/lWord Access (WO)
DMA Continue (WO)

0
0

1
1

Normal Operation
}
Auto Echo
Extemal Local Loopback
Internal local Loopback

Mode
Control

Channel Reset

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Null Command
Reserved
Reset Highest IUS
Reserved
Trigger Channel Load DMA
Trigger Rx DMA
Trigger Tx DMA
Trigger Ax & Tx DMA
Reserved
Rx FtFO Purge
Tx FIFO Purge
Rx & Tx FIFO Purge
Reserved
Reload Rx Character Count
Reload Tx Character Count
Reload Rx & Tx Character Count
Reserved
LoadTCO
LoadTCl
Load TCO & TCl
Select Serial Data LSB First *
Select Serial Data MSB First
Select Straight Memory Data * '
Select Swapped Memory Data
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

Channel
Command
(WO)

Selected
Upon Reset

Figure 7. Channel Command/Address Register

Address: 00001

IIII
0
0
0
0
0
0'
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Asynchronous

Extsmal Synchronous

0
1
0
1
0
1
0
1
0
1
0
1
0
1

Isochronous
Asynchronous with CV
Monosync
Blsync
HOLC
'Iiransparent BIsync
NB IP·
802,3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

Receiver
Mode

Ax Submode 0
Ax Submode 1·
Ax Submode 2
RxSlbmode3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Asynchronous
Reserved
Isochronous
Asynchronous with cv
Monosync'.
BIsync
HOLC
Transparent BIsync
NBIP
802,3
Reserved
Reserved
Slaved Monosync
Reserved
HOLC Loop
Reserved

"'"
Transmitter
Mode

TxSlbmodeO

TxSubmode 1
TxSubmode2
. Tx Submode 3

Fi~ure

8. Channel Mode Register

.,
16

Address: 00001

IIII
0

0
0
1
1

0
1
0
1

16X Data Rate }
32X Data Rate
64X Data Rate
Reserved

Asy nchronous} Receiver
Mode

Rx Clock
Rate

Reserved
Reserved

0
0
1
1

o o
o 1
1
t

o
1

0
1
0
1

16X Data Rate }
32X Data Rate
64X Data Rate
Reserved

One Stop Bn
Two Stop Bits
}
One Stop Bit, Shaved
Two Stop Bits, Shaved

ASYnchronouS} Transmitter
Mode

Tx Clock
Rate

TxStop
Bits

Figure 9. Channel Mode Register, Asynchronous Mode

Address: 00001

External Sync }

Receiver
Mode

Reserved

000

R
ed }
eserv

Transmitter
Mode

L.._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 'Reserved

Figure 10. Channel Mode Register, External Sync Mode

Address: 00001

I II I

I
0

lsoch

ronous

IsochronouS} Receiver
Mode

Reserved
}

1roosmhler
Mode
Reserved

Tx Two Slop Bits
Reserved

Figure 11: Channel Mode Register, Isochronous Mode

Address: 00001

I I I I
0

Asynchronous wilh CV }

Ax Extended Word
Reserved

Asynchronous wilh CV }

~::milter
CV Polarity
Tx Extended Word

o
o
1
1

o
1

OneStopBtt }
Two Stop Bits
No Slop Bh
Reserved

Tx
Slop Bits

Figure 12. Channel Mode Register, Asynchronous Mode
.
with Code Violation (MIL STD 1553)

Receiver
Mode

Address: 00001

-r--

onosync} Receiver
Mode

Ax Short Sync Character
Ax Sync Strip
Reserved

onosync

}

Transmitter
Mode
Tx Short Sync Character
Tx Preamble Enable
Reserved
Tx CRC on Underrun

Figure 13. Channel Mode Register, Monosync Mode

Address: 00001

II II
0

Bisync} Receiver
Mode

Ax Short Sync Character
Ax Sync Strip
Reserved

sync

}

Transmitter

Mode

Tx Short Sync Character
Tx Preamble Enable

o o
o 1
1
o
1

~~~/SYNI

CRC/SYNI
CRClSYNO/SYNI

}

Unde"."n
Condition

Figure 14. Channel Mode Register, Bisync Mode

Address: 00001

IIII
1 . 1

HOLC} Receiver
Mode

0
0

Disabled

1
1

One Byt&. No Control
One Byte. Plus Control }
Extended, f'II!s Control

RxAddress
Search Mode

Rx IS-BH Control
Rx logical Control Enable
1

HOLC }

Transmitter
Mode
Shared Zero Flags

Tx Preamble Enable

~1 0~ Flag
~~ed Abort } Condition
~
1

CRC/FIag

Figure 15. Channel Mode Register,

HDL~

Mode

Address: 00001

III I
0

11ransparent

BisynC} Mode
Receiver

EBCDIC
Reserved

Transparent Bisync } ;:;!"'ltter

EBCDIC
Tx Preamble Enable

~ ~ g~~SYN

}

•

CRC/sYN

lkIderrlll

CRCIDLEISYN

Condition

Figure 16. Channel Mode Register, Transparent Bisync Mode

Address: 0000,1

IIII
1

0
0
1
1

0
1
0
1

16X Data Rale }
32X Data Rate
ji4X Data Rate
Reserved

Receiver
Mode

NBI P }

Ax Clock
Rate

Rx Parity on Data
Reserved

0
0
1
1

0
1
0
1

NBIP }

Transmitter
Mode

16X Data Rate}
32X Data Rate
Tx Clock
Rate
64X Data Rate
Reserved
Tx Parity on Data
Tx Address Bit

Figure 17. Channel Mode Register, NBIP Mode

Address: 00001

I I I .I
1

802.

Receiver
Mode

Ax Address Search
Reserved

802 3 }
.

Transmiller
Mode
Reserved
Tx CRC on Underrun

Figure 18. Channel Mode Register, 802.3 Mode

Address: 00001

I
1

SlaVed Monosync }

III
1

TransmHter

Mode

Tx Shot! Sync Character
Tx Active on Received Sync
Reserved
Tx CRC on Undlll1U1

Figure 19. Channel Mode Register, Slaved Monosync Mode

Address: 00001

I
1

HOLC Loop }

IIII
1

Reserved} ReosIver

Mode

Reserved
TransmHter

Mode

Shared·Zero Flags
Tx Active on PoD

g1 0~ ~~ Abort} Condition

Tx Uncle,...,

Rag
CRClAag

Figure 20. Channel Mode Register, HDLC Loop Mode

Address: 00010

~
0
0
0
0

1
1
1
1

0
0

1
1
0

0
0

"
b }
4 Bits

1
1

SBlts
SBits
7 Bits

fTxACK (RO)

Saits
1 Bit
2 Bits

IRxACK(RO)

HOLC Tx Last
Character Length

Reserved

Loop Sending (RO)
On Loop (RO)

0
0

1
1

1
0
1

Both Edges
Rising Edge Only }
Falling Edge Only
Adjust/Sync Inhibit

OP~

Adjust!
Sync Edge
Ctock Missed Latched/Unlatch
Clocks Missed LatchedlUnlatch
OP~

in Sync/Cluick Sync

RCC FIFO Clear (WO)
RCC FIFO Valid (RO)
RCC FIFO OVerflow (RO)

Figure 21. Channel Command/Status Register

Address: 00011

I
0
0
1
1

0
1
0
1

Reserved
Wait for Rx OMA Trigger

No Status Block
}
One Word Status Block
Two Word Status Block
Reserved

Ax Status
Block Transfer

Tx Shaved Bit Length
(Async Onfy)
0
0
1
1

0
1
0

All Zeros
All Ones
}
Altemating 1 and 0
Altemating 0 and 1

TxPream~e

"'I

Pattern

> (All Sync)
0
0
1

0
1
0
1

BBits
16 Bits }
Bits
64 Bits

TxPream~e

Length

Reserved

o
o
1

o
1
o

Wait for Tx OMA Trigger

No Status Block
}
One Word Status Block
Two Word Status Block
Reserved

Tx Status
Block Transfer

Figure 22. Channel Control Register

Address: 00100

10151D14101310121D111D101 091 081 D71 osl osl 041 031 021 D1 IDOl

Reserved

Figure 23. Primary Reserved Register

Address: 00101

Reserved

Figure 24. Secondary Reserved Register

Address: 00110

Test Data <0>
Test Data <1>
Test Data <2>
Test Data <3>
Test Data <4>
Test Data <5>
Test Data <6>
Test Data <7>
Test Data <8>
Test Data <9>
Test Data <10>
Test Data <11>
Test Data <12>
Test Data <13>
Test Data <14>
Test Data <15>

Figure 25. Test Mode Data Register

00111
1015101+1310121011101°1091 OSI 071 061 OSI 041 031 021 011 DO I
Addr~ss:

f 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1

11
1
1
1
1

I I' I,

0 ,0
0 ·0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
0
1
1
1
1
1

0
0
0
0
0
0
0
0

0
0

1
1
Q

0
0

1
1

Null Address
Hgh Byte of Shifters
CRCByteO
CRCByte 1
Ax FIFO (Write)
Clock Multiplexer Outputs
CTRO and CTR1 Co~ers
Clock Muldplexer Inputs
DPLLState
Low Byte of Shifters
CRC Byte 2
CRC Byte 3
Tx FIFO (Read)
ReS8Mld
VO and Device status Latches

1
1
1

0
0
1
1

0
1

Internal

0
0

1
1

0
0

0
1
0

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Rx Cooot Holding Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

1
1
1
1
1

1
1 1
1
1

1
1
1
1
1
1

0
0

1
1

1
1
1
1

0
0

1
1
1
1
1
1

1
1

0
1

1
1
1
1
1

0
1

~aisy

Chain

Reserved

Figure 26. Test Mode Control Register

Test
Register
Address

Addiess: 01000

0
0
1
1

o o
o 1
1
o
1

0
0

1
1

0
0

1
1

0
1

0
0
0
0

0
0

1
1
1
1

0
0

1
1

0
0
0
.0

0
0
1
1

1
1
1
1

0
0

1
1

0
1
1
1
1

IAxC
Pin
Disabled
}
fTxC Pin
DPLL OUtput
BRGOOUtput
BRG10Utput
CTRO OUtput
CTR10Utput

Disabled
IAxC Pin
fTxC Pin
DPLL OUtput
BRGO OUtput }
BRG10Utput
CTRO Output
CTR1 OUtput

BRGO OUtput }
BRG1 OUtput
IAxC Pin
fTxC Pin

CTRO OUtput
CTR10Utput
IAxC Pin
fTxC Pin

CTRO OUtput }
CTR10Utput
IAxC Pin
fTxC Pin

Disabled
Disabled
}
IAxC Pin
fTxC Pin

Disabled }
Disabled
IAxC Pin
fTxC Pin

0
1

III
RSourceecelve Clock

TransmH Clock

So...:e

DPLLClock

Source

}

BRGOCIock
Source

BRG1 Clock
Source

:CIOCk

CTR1 Clock
Source

Figure 27. Clock Mode Control Register

Address: 01001

~
0
0
1
1

0
1
0
1

BRGO Enable
BRGO Single CyclelCantinuous

3-State Output
RxAcknowiedge Input }
Output 0
Output 1

IRxACK
Pin Control

BRGl Enable
BRGl Single Cycle/Continuous
0
0
1
1
0
0
1
1
0

1
0
1

1
1

0
1
0
1

3-State Output
}
Tx Acknowledge Input
Output 0
Output 1

~ml~

0
1
0

NRZlNRZI
Biphase-MarWSpace

Biphase-~evel

32x Clock Mode
16x Clock Mode }
8x Clock Mode

}

ffxAC K
PinCantral

DPLL
Mode

DPLLClock
Rate

Reserv~

Accept Code Violations,
CTRl Rate Match DPLLICTRO

o o

o
1
1

o
1

32x Clock Mode
16x Clock Mode
8x Clock Mode
4x Clock Mode

} CTROCI~
Rate

Figure 28. Hardware Configuration Register

Address: 01010

IV <0>

IV <2>
IV <3>
IV <4>

IV <6>
IV <7>

0
0
0
0
1
1
'1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

}

Device Status
VOStaIus
Transmh Data
Transmh SlalUs
Receive Data
Receive Status

IV(RO)

ModIfied
Vector (RO)

NoIUsed
IV <4> (RO)
IV <5> (RO)
IV <6> (RO)
IV <7.> (RO)

Figure 29. Interrupt Vector Register

'29

Address: 01 011

III
0
0
0
0

1
1
1
1
0
0
0
0

1
1
1
1
0
0
1
1

0
.0

1
1
0
0
1
1
0
0
1
1

o
o
1
1

0
1
0
1

0
1
0

0
1
0
1

0
1
0

1
1
0
0
1
1

1
1
0

1
0
1

3-State Output
}
Rx Request Output
Output 0
Output 1

1
0

1
0
1
0
1

~tput}

TxD Pin
Control

IRxREO
Pln Control

ITxREO
Pin Control

IDCD
Pin Control

ICTS
Pin Control

Figure 30. I/O Control Register

Input
Pin Output
}
Rx
Clock
Rx Byte Clock Output
SYNC Output
BRGO Output
BRG10utput
CTRO Output
DPLL Rx Output

Input PIn'
Tx Clock
Tx Byte Clock
Tx Complete Output
BRGOOutputput
BRG10utput
CTR10utput
DPLL Tx Out

Tx Data Output }
3-State Output ,
Output 0
Output 1

3-State Output
}
Tx Request Output
Output 0
Output 1

IDCD Input
}
IDCDI/SYNC Input
Output 0
Output 1

ICTSlnput }
ICTS Input
Output 0
Output 1

' 0
1
0
1

0
0

0
0
1
1
0
0
1

ITxC
Pin Control

.
IRxC Pin
Control

Add'ess: 01100

· Device Slatus IE

VOStatus IE
Transmh.Data IE
TransmR Status IE

ReceIve !,)ata IE
Receive Status IE

0
0
1
1

0
1
0
1

NuDCommand
NuUCommand
Reset IE
SeliE

}

IE Command

(WO)

Reserved

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

All
VO Slatus and />boNe
M
Transmit Data and />boNe }
Transmlt Status and />boNe
ReceIve Data and />boNe
ReceIve Status Only
None

VIS

Level

VIS

NV
DLC
MIE

Figure 31. InterrupJ Control Register

---_.

-.-~~-~

Address: 01101

Device Sbdus tP

ItO Status IP

Transmit Data IP
Transmit Status IP
~yeDatalP

Receive Status IP

oo
1
1

0
1
0

Null Command }
ResetlP and IuS
Reset P
SeIIP

IP Command
(WO)

Device Status IUS
ItO Status IUS

Transmit Data IUS
Transmit Status IUS

Receive Data IUS
Receive Status IUS

o
o
1
1

0
1
0
1

Null Command }
Null Command
Reset IUS
Set IUS

IUS Command
(WO) .

Figure 32. Daisy-Chain Control Register

01110 '
1015101410131012101110101091091071081 os! 041 031021 01 100 1
Address:

BRGO ZC LatchedlUniatch
BRG1 ZC LalchedlUniatch
oPLL SYNC Latched/Unlatch
RCC Ovet11ow LatchedAJnlatch
ICTS(RO)
ICTS LatchedAJnlatch
IDCo(RO)

lOCO LatchedlUniatch
rrxREQ(RO)
rrxREQ LatchedlUniatch
IRxAEQ(RO)
IRxREQ Latched/Unlatch
ITxC (RO)
ITxC Latched/Unlatch
!AxC (AO)
!AxC LatchedlUnlatch

Figure 33. Miscellaneous Interrupt Status Register

Address: 01111

BRGOZC IE
BRGl ZC IE
DPLLSYNC IE
RCC Overflow IE

1
1

0
0
1
1

o o
()

1
1

o o
o 1
o

1
1

o o
o

1
1

o
1

0
1
0
1

Disabled
}
Rising edge Only
Failing Edge Only
Both Edges

Disabled
}
Rising Edge Only
Falling Edge Only
Both Edges

0
1
0
1

IDCD
Interrupts

ITxREO
Interrupts

IRxREO
Interrupts

ITxC
Interrupts

IRxC
Interrupts

Figure 34. Status Interrupt Control Register

ICTS
Interrupts

Address: 1xOOO

RxDAT <0> (RO)
RxDAT <1> (RO)
RxDAT <2> (RO)
RxDAT <3> (RO)
RxDAT <4> (RO)
RxDAT <5> (RO)
RxDAT <6> (RO)
RxDAT <7> (RO)
RxDAT <8> (RO)
RxDAT <9> (RO)
RxDAT <10> (RO)
RxDAT <11> (RO)
RxDAT <12> (RO)
RxDAT <13> (RO)
RxDAT <14> (RO)
RxDAT <15> (RO)

Figure 35. Receive Data Register

Address: 10001

I I
0
0
1

t
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
0
1

01sable Immediately
}
Disable After Reception
E nable Without Auto-Enables
Enabla With Auto-Enables '

,. }
8 Bits
1 Bit
2 Bits

4 Bits

Ax Character
Length

5 Bits

6 Bits
7 Bits
Ax Parity Enable

0
1
1

1
0
1

Even}
Odd
Ax Parity
Space
Sense
Mark
Reserved
Ax eRC Enable
Ax CRC Preset V....e

0
0
1
1

o o o
()
o 1
o 1 o
o 1 1
1 o o
1 o 1
1 1 o
1

0
1
0
1

CRC-CCITT }
CRC-16
CRC-32
Reserved

NAZ
NRZB
NAZI-Mark
NAZI-Space
Blphase-Mark
Blphase-Space
Blphase-Level
OIH_ Biphase-Level

AxCRC
Polynomial

' Ax Data
}

Decoding

Figure 36. Receive Mode Register

Rx
Enable

Address: 10010

Rx Character Available (RO)

Ax Overrun
Parity Error
CRClFraming Error (AO)

Ax CVlEOTIEOF
Ax Break/Abort
Ax Iele
ElCited Hunt
Short FramelCV Polarity (RO)
Residue Code 0 (RO)
Residue Code 1 (RO)
Residue Code 2 (RO)

I I I I
0
0
0
0
0
0

0
0
0
0
1
1
1
1
0

0
0
1
1
0
0
1
1
0

1
1
0
1

0
0
0
1

0
0

0
1
1
0
0

0
1
0
1
0
1

0
1
0

1
0

1
0
1

Null Command
Reserved
Preset CRC
Ent&r Hunt Mode
ResOlVed
Select FIFO Status
Select FIFO Intenupt Level
Select FIFO Request Level
Reserved
Reserved
Reserved
Reserved
Reserved
ResOlVed
ResOlVed

......,

Receive
Comm and (WO)

First Byte in Error (RO)
Second Byte in Error (RO)

Figure 37. Receive Command Status Register

Address: 10011

TCOR Read CoUnVTC

RxOvenunlE
Parity Error IE

Status on Words
Rx qV/EOT/EOF IE
Rx BreakiAbort IE
Rx Ide IE
Ellited Hunt IE

Rx F;IFO Control and Status
(FiIVlntenuptIDMA Level)

Figure 38. Receive Interrupt Control Register

Address: 10100

RSYN
RSYN<1>
RSYN<2>
RSYN<3>
RSYN<4>
RSYNo>
RSYN<6>
RSYN<7>
RSYN<8>
RSYN
RSYN<10>
RSYN<11>
RSYN<12>
RSYN<13>
RSYN<14>,
RSYN<1S>

Figure 39. Receive Sync Register

Address: 10101

. RCLcO:>
RCL<1>

RCL<3>

RCLdi>

RCL<8>
RCL<9>

RCL<11>
RCL<12>
RCL<13>
RCL<14>
RCL

Figure 40. Receive Count limit Register

- I

Address: 10110

RCC (RO)
RCC<1> (RO)
RCC <2> (RO)
RCC <3> (RO)
RCC <4> (RO)
RCC <5> (RO)
RCC <6> (RO)
RCC <7> (RO)
RCC <8> (RO) ,
RCC <9> (RO)
RCC <10> (RO)
RCC <11> (RO)
RCC <12> (RO)
RCC <13> (RO)
RCC <14> (RO)
RCC <15> (RO)

Figure 41. Receive Character Count Register

Address: 10111

TCO

TCO<2>
TCO<3>
TCO<4>
TCO<5>
TCO<6>
TCO<7>
TCO<8>
TCO<9>
TCO

TCO<12>
TC0<13>
TCO <14>
TCO <15>

Figure 42. Time Constant 0 Register

Address: 1.000

TxOAT <0> (WO)
TxOAT <1> (WO)
TxOAT <2> (WO)
TxOAT <3> (WO)
TxOAT <4> (WO)
TxOAT <5> (WO)
TxOAT <6> (WO)
TxOAT <7> (WO)
TxOAT <8> (WO)
TxOAT <9:> (WO)
TxOAT <10> (WO)
TxOAT <11> (WO)
TxOAT <12> (WO)
TxOAT <13> (WO)
TxOAT <14> (WO)
TxOAT <15> (WO)

Figure 43. Transmit Data Register

Address: 11001

II
0
0
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0,
0
1
1

0,
1
0
1
0
1
0
1

0
1
0
1

8 Bits
iE!1I
2 Bits
3 Bits

4 Bits
5 Bits
6 Bits
7 Bits

Disable Immeciately
}
Disable Alter Transmission
Enable WIthout Auto-Enables

Tx
Enable

Enable WIth Auto-Enables

}

Tx Character
l.angth

Tx Parhy Enable

0
1
0
1

0
0
1
1

Space
Mark

Tx Parity
Sense

Tx CRC on EOF/EOM
Tx CRC Enable
Tx CRe Preset Value

0
0
1
1
0
0
0
1)

1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
0
1

CRC-CCITT }
CRC-i6 ,
CRC-32

TxCRC

Polynomial

ReseMKI

NRZ
NRZB
NRZI-Mark
NRZ~Space

}

Tx Data

Biphase-Mark
Blphase-Space
Biphase-Level
Din. Blphase-Level

Enccding

Figure 44. Transmit Mode Register

Address: 11010

Tx Bufler Empty (RO)
Tx Undenun
AU Sent (RO)
Tx CRC Sent
Tx EOFIEOT Sent
Tx Abort Sent
Tx Idle Sent
Tx Preamble Sent

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Alternating 1 and 0
All Zeros
AU Ones
Reserved
,
Alternating Mark and Space'
Space
Mark

Tx Idle Une
Condition

Reserved
0
0
0
0
0
0

0
0
0

1
0
1
0

1
1
0

0
0

1
1

1
1
1
1

0
0
0
0
1
1
1

1
1
0

1
1
1
1

0
1

1
0
0
1
1

1
0
1
0
1

0
1
0

1
0
1

Null Command
Reserved
Preset CRC
Reserved
Reserved
Select FIFO Status
Select Interrupt Level
Select Request Level
Send Frame/Message
Send Abort
Reserved
Reserved
Reset OLE Inhibit
Set OLE Inhibit
Reset EOF/EOM
SetEOFIEOM

Transmit
Command (WO)

Figure 45. Transmit Command/Status Register

Address: 11011

TC1 R Read CountITC
TxOv....... IE
Walt lor Send Commend
Tx CRC Sent IE
Tx EOFt!:OT Sent IE
Tx Abort Sent

Tx l
TSYN<1>
TSYN<2>
TSYN<3>
TSYN<4>

TSYN<6>
TSYN<7>
TSYN<8>
TSYN
TSYN<10>
TSYN<11>

TSYN<13>
TSYN<14>
TSYN<1S>

Figure 47.

Trans~1t

Sync Register

~---

'.'"

.-"

" "

Address: 11101

Irn~~rn~rn~rnllrn~ooloolrol~I~1~lool~lrnlool

TCl
TCl<1>
TCl<2>
TCL<3>
TCl<4>
TCL
TCl<6>
TCl<7>
TCl<8>
TCl <9>
TCl<10>
TCl <11>
TCl <12>
TCl <13>

TCl<14>

Figure 48. Transmit Count Limit Register

Address: 11110

TCC <0> (RO)
TCC<1> (RO)
TCC <2> (RO)
TCC <3> (RO)
TCC <4> (RO)
TCC <5> (RO)
TCC <6> (RO)
TCC <7> (RO)
TCC <8> (RO)
TCC <9> (RO)
TCC <10> (RO)
TCC <11> (RO)
TCC <12> (RO)
TCC <13> (RO)
TCC <14> (RO)
TCC <15> (RO)

Figure 49. Transmit Character Count Register .

Address: 11111

TC1 <1>
TC1 <2>
TC1 <3>
TC1 <4>

TC1 <6>
TC1 <7>
TC1 <8>
TC1 <9>
TC1 <10>
TC1 <11>
TC1 <12>
TC1 <13>
TC1 <14>
TC1 <15>

Figure 50. Tline Constant 1 Register

Address: None ..

RCC
RxOVellUl

Parity Error
CRC Error
Rx CVIEOTIEOF

o
o
o
,

Short FramaiCV Polarity
Residue Code 0
Residue Code 1
Residue Code 2

o
o
First Byte In Error
Second Byte in Error
..

Refer to FIgure 22 (Channel Control Register)
Bits r;. 7 for Access Method

Figure 51. Receive Status Block Register

Address: None •

I I I L,~.

0
0
0
0

0
0

1
1

1
1
1
1

0
0

0' 4 Bits

1
1

SBits
1 BH
2 Bits

1
1
1

5 Bits
6 Bits
7 Bits

Reserved

}

HOLC Tx Last
character Length

Reserved
Tx Submode 0
Tx Submode 1
Tx Submode 2
Tx Submode 3
•

Refer to Figure 22 (Channel Control Register)
B"sI5-14 for Access Method

Figure 52. Transmit Status Block Register

Address: None

1015101410131012101110101091081071061051041031 D21 01 I

Shift Right Addresses
Ooubl<>-Puise INTACK
16-BitBus

o•
Reserved
3-State All Pins
Separate Address for 8-Bit Bus

• Must be programmed as,zero.

Figure 53. Bus Configuration Register

USC TIMING
The USC interface timing is similar to that found on a static
RAM, except that it is much more flexible. Up to eight
separate timing strobe signals may be present on the
interface .. IDS, IRD', IWR, IPITACK, IRxACKA. IRxACKB,
/TxACKA and ITxACKB, Only one of these timing strobes
may be active at any time Should the, external logic

i;lctivate more than one of these strobes at the same time
the USC will enter a pre-reset state that is only exited by a
hardware reset. Do not allow overlap of timing strobes. Tile
timing diagrams, beginning on the next page, illustrate the
different bus transactions possible, wittl the necessary
setup, hold and delay times.

ABSOLUTE MAXIMUM RATINGS
Voltages on all pins
with respect to Vss .................................. -0.3 V to +7.0 V
Voltages on all iflputs
with respect to Vss ........................... -0.3V to Vcc +0.3V
Operating Ambient
Temperature ............................ See Ordering Information
Storage Temperature ............................. -65°C to + 150°C

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.

STANDARD TEST CONDITIONS
+5V

The DC Characteristics and Capacitance section below
"apply for the following standard test conditions, unless
otherwise noted. All voltages are referenced to GND.
Positive current flows into the referenced pin. Standard
conditions are as follows:

+4.5 V < Vee < +5.5 V
.
GND =OV
TA as specified in Ordering Information

Figure 54. Standard Test load

CAPACITANCE
Symbol

Parameter
Input Capacitance
Output Capacitance
Bidirectional Capacitance

Min

Max

Unit

10
15

pi
pf
pi

Condition
Unmeasured Pins
Returned to Ground

Note:
f= 1MHz, over specified temperature range.
Unmeasured pins returned to ground

MISCELLANEOUS Transistor Count - 174,000

DC CHARACTERISTICS
Z16C30
$ymbol' Parameter

Min

V...
VIl.
VOH 1
VoH 2

Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage

yO\.

Output Low Voltage
Input Leakage
Output Leakage
Vcc Supply Current

III
10\.
Icci

Typ

22
-0.3
2.4
Vcc-0.8

Max

Unit

Vcc+0 .3
0.8

V
V
V
V

0.4
±1O.00
±10.00
50

Condition

IOH= -1.6mA
IOH= -250 jJA

rnA

10\.= +2.0 rnA
0.4 < VIN < +2.4V
0.4 < VOIJf < +2.4V
Vcc=5V V...= 4.8V VIL= 0.2V

Max

jJA
jJA

Note:
Vcc= 5V ± 10% unless otherwise specified, over specified temperature range.

AC CHARACTERISTICS
Z16C30
No

Symbol

Parameter·

Min

1
2
3
4

Tcyc
TwASI
TwASh
TwDSI

Bus Cycle Time

lAS Low Width
lAS High Width
IDS Low Width

160
40

5
6
7
8

TwDSh
TdAS(DS)
TdDS(AS)
TdDS(DRa)

IDS High Width
lAS Rise to IDS Fall Delay Time
IDS Rise to lAS Fall Delay Time
IDS Fall to Data Active Delay

9
10
11
12

TdDS(DRv)
TdDS(DRn)
TdDS(DRz)
TsCS(AS)

IDS Fall to Data Valid Delay
IDS Rise to Data Not Valid Delay
IDS Rise to Data Float Delay
ICS to lAS Rise Setup Time

13
14
15
16

ThCS(AS)
TsADD(AS)
ThADD(AS)
TsSIA(AS)

17
18

Units

ns
ns
ns
ns

60
5
5
0

ns
ns
ns
ns

, 15

ns
ns
ns
ns

ICS to lAS Rise Hold Time
Direct Address to lAS Rise Setup Time
Direct Address to lAS Rise Hold Time
ISITACK to lAS Rise Setup Time

0
15
5
15

ns
ns
ns
ns

ThSIA(AS)
TsAD(AS)
ThAD(AS)
TsRW(DS)

ISIT ACK to lAS Rise Hold Time
Address to lAS Rise Setup Time
Address to lAS Rise Hold Time
R//W to IDS Fall Setup Time

5
15
5
0

ns
ns
ns
ns

21
22
23
24

ThRW(DS)
TsDSf(RRQ)
TdDSr(RRQ)
TsDW(DS)

R//W to IDS Fall Hold Time
IDS Fall to IRxREQ Inactive Delay
IDS Rise to /RxREQ Active Delay
Write Data to IDS Rise Setup Time

25
26
27
28

ThDW(DS)
TdDSf(TRO)
TdDSr(TRQ)
TwRDI

Write Data to IDS Rise Hold Time
IDS Fall to /TxREQ Inactive Delay
IDS Rise 10 /TxREQ ACtive Delay
IRD LowWidlh

85
0

60
0
30
65
0
70

ns
ns
ns
ns
ns
ns
ns
ns

Note

[ 1]
[1]

[4]

[5]

AC CHARACTERISTICS
Z16C30
No

Symbol

Parameter

Min

29
30
31
32

TwRDh
TdAS(RD)
TdRD(AS)
TdRD(DRa)

IRD High Width
lAS Rise to IRD Fall Delay Time
IRD Rise to lAS Fall Delay Time
IRD Fall to Data Active Delay

33
34
35
36

TdRD(DRv)
TdRD(DRn)
TdRD(DRz)
TdRDf(RRO)

IRD Fall to Data Valid Delay
IRD Rise to Data Not Valid Delay
IRD Rise to Data Float Delay
IRD Fall to IRxREO Inactive Delay

37
38
39
40

TdRDr(RRO)
TwWRI
TwWRh
TdAS(WR)

IRD Rise to IRxREO Active Delay
/WR Low Width
IWR High Width
lAS Rise to /WR Fall Delay Time

0
70
60
5

ns
ns
ns
ns

41
42
43
44

TdWR(AS)
TsDW(WR)
ThDW(WR)
TdWRf(TRO)

/WR Rise to lAS Fall Delay Time
Write Data to /WR Rise Setup Time
Write Data to /WR Rise Hold Time
/WR Fall to /TxREO Inactive Delay

5
30
0

ns
ns
ns
ns

[5]

45
46
47
48

TdWRr(TRO)
TsCS(DS)
ThCS(DS)
TsADD(DS)

/WR Rise to /TxREO Active Delay

ICS to IDS Fall Setup Time
ICS to IDS Fall Hold Time
Direct Address to IDS Fall Setup Time

0
0
25
5

ns
ns
ns
ns

[2]
[2]
[1,2]

49
50
51
52

ThADD(QS)
TsSIA(DS)
ThSIA(DS)
TsCS(RD)

Direct Address to IDS Fall Hold Time
ISIT ACK to IDS Fall Setup Time
lSI TACK to IDS Fall Hold Time
ICS to IRD Fall Setup Time

25
5
25
0

ns
ns
ns
ns

[1,2]
[2]
[2]
[2]

53
54
55
56

ThCS(RD)
TsADD(RD)
ThADD(RD)
TsSIA(RD)

ICS to IRD Fall Hold Time
Direct Address to IRD Fall Setup Time
Direct Address to IRD Fall Hold Time
lSI TACK to IRD Fall Setup Time

25
5
25
5

ns
ns
ns
ns

[2]
[1,2]
[1,2]
[2]

57
58
59
60

ThSIA(RD)
TsCS(WR)
ThCS(WR)
TsADD(WR)

ISITACK to IRD Fall Hold Time
ICS to /WR Fall Setup Time
ICS to /WR Fall Hold Time
Direct Address to IWR Fall Setup Time

25
0
25
5

ns
ns
ns
ns

[2]
[2]
[2]
[1,2]

61
62
63
64

ThADD(WR)
TsSIA(WR)
ThSIA(WR)
TwRAKI

Direct Address to /WR Fall Hold Time
ISITACK to /WR Fall Hold Time
IRxACK Low Width

25
5
25
70

ns
ns
ns
ns

[1,2]
[2]
[2]

65
66
67
68

TwRAKh
TdRAK(DRa)
TdRAK(DRv)
TdRAK(DRn)

fRxACK
IRxACK
IRxACK
IRxACK

ns
ns
ns
ns

69
70
71
72

TdRAK(DRz)
TdRAKf(RRO)
TdRAKr(RRO)
TwTAKI

IRxACK Rise to Data Float Delay
IRxACK Fall to IRxREO Inactive Delay
IRxACK Rise to IRxREO Active Delay
ITxACK Low Width

ISIT ACK to /WR Fall Setup Time

High Width
Fall to Data Active Delay
Fall to Daia Valid Delay
Rise to Data Not Valid Delay

Max

Note

ns
ns
ns
ns

5
5
0
85
0
20
60

0
85
0
20
60
0
70

Units

ns
ns
ns
ns

[4]

AC CHARACTERISTICS
Z16C30
No

Symbol

Parameter

Min

73
74
75
76

TwTAKh
TsDW(TAK) :
ThDW(TAK)
TdTAKf(TRQ)

ITxACK High Width
Write Data to ITxACK Rise Setup Time

60
30
0

78
79
80

TdTAKr(TRQ)
TdDSf(RDY)
TdRDY(DRv)
TdDSr(RDY)

ITxACK Rise to /TxREQ Active Delay
IDS Fall (INTACK) to IRDY Fall Delay
IRDY Fall to Data Valid Delay
IDS Rise to IRDY Rise Delay

81
82
83
84

TsIEI(DSI)
ThIEI(DSI)
TdIEI(IEO)
TdAS(IEO)

lEI to IDS Fall (INTACK) Setup Time
lEI to IDS Rise (INTACK) Hold Time
lEI to lEO Delay
lAS Rise (Intack) to lEO Delay

85
86
87
88

TdDSI(INT)
TdDSI(Wf)
TdDSI(Wr)
TdW(DRv)

89
90
91
92

Write Data t6 /TxACK Rise Hold Time

ITxACK Fall to /TxREQ Inactive Delay

Max

Units

Note

ns
ns
ns
ns,

[5]

0
40
40

ns
ns
ns
ns

60
60

ns
ns
ns
ns

IDS Fall (INTACK) to liNT Inactive Delay
IDS Fall (INTACK) to /WAIT Fall Delay
IDS Fall (INTACK) to IWAIT Rise Delay
IWAIT Rise to Data Valid Delay

200
40
200
40

ns
ns
ns
ns

TdRDf(RDY)
TdRDr(RDY)
TsIEI(RDI)
ThIEI(RDI)

IRD Fall (INTACK) to IRDY Fall Delay
IRD Rise to IRDY Rise Delay
lEI to IRD Fall (INTACK) Setup Time
lEI to fRD Rise (INTACK) Hold Time

200
40

ns
ns
ns
ns

93
94
95
96

TdRDI(INT)
TdRDI(Wf)
TdRDI(Wr)
TwPIAI

fRD Fall (INTACK) to liNT Inactive Delay
IRD Fall (INTACK) to /WAIT Fall Delay
IRD Fall (INTACK) to /WAIT Rise Delay
IPITACK Low Width

200
40
200
70

ns
ns
ns
ns

97
98
99
100

TwPIAh
TdAS(PIA)
TdPIA(AS)
TdPIA(DRa)

IPITACK
lAS Rise
IPITACK
{PITACK

60
5
5
0

ns
ns
ns
ns

101
102
103
104

TdPIA(DRn)
TdPIA(DRz)
TsIEI(PIA)
ThIEI(PIA)

IPIT ACK Rise to Data Not Valid Delay

105
106
107
108

TdPIA(IEO)
TdPIA(INT)
TdPIAf(RDY)
TdPIAr(RDY)

{PITACK
{PIT ACK
{PITACK
IPITACK

109
110
111
112

TdPIA(Wf)
TdPIA(Wr)
TdSIA(INT)
TwSTBh

IPIT ACK Fall
IPITACK Fall
{SITACK Fall
IStrobe High

113
114
115
116

TwRESI
TwRESh
Tdres(STB)
TdDSf(RDY)

{RESET Low Width
IRESET High Width
{RESET Rise to {STB Fall
IDS Fall to {RDY Fall Delay

High Width
to IPITACK Fall Delay Time
Rise to lAS Fall Delay Time
Fall to Data Active Delay

{PITACK Rise to Data Float Delay
lEI to {PITACK Fall Setup Time
lEI to IPITACK Rise Hold Time

200

60
0

0
20
60
0

Fall to lEO Delay
Fall to liNT Inactive Delay
Fall to {RDY Fall Delay
Rise to IRDY Rise Delay
to /WAIT Fall Delay
to /WAIT Rise Delay
to lEO Inactive Delay
Width

ns
ns
ns
ns

60
200
200
40

ns
ns
ns
ns

40
200
200

ns
ns
ns
ns

60
170
60
60
50

ns
ns
ns
ns

[2]
[3]

[3]

AC CHARACTERISTICS
Z16C30
No

Symbol

Parameter

Max

Units

117
118
119
120

TdWRf(RDY)
TdWRr(RDY)
TdRDf(RDY)
TdRAKf(RDY)

/WR Fall to /RDY Fall Delay
/WR Rise to /RDY Rise Delay
/RD Fall to /RDY Fall Delay
/RxACK Fall to /RDY Fall Delay

Min

50
40
50
50

ns
ns
ns
ns

121
122
123

TdRAKr(RDY)
TdTAKf(RDY)
TdTAKr(RDY)

/RxACK Rise to /RDY Rise Delay
/TxACK Fall to /RDY Fall Delay
/TxACK Rise to /RDY Rise Delay

40
50
40

ns
ns
ns

Note

Notes:
[1] Direct address is any of A/IB. DIIC or AD15-AD8 used as an address bus.
[2] The parameter applies only when fAS is not present.
[3] Strobe (/STB) is any of /OS, fRO, /WR, tpITACK, /RXACK or /TxACK.
[4] Parameter applies only if read empties the receive FIFO.
[5] Parameter applies only if write fills the transmit FIFO.

TIMING DIAGRAMS

IRESET

113

i\.
~

i\.

ISTB

115

Figure 55. Reset Timing

ISTB

Note:
fSTB is any of /OS, fRO. /WR, tpITACK, /RXACK, or /TxACK.

Figure 56. Bus Cycle Timing

/RxACK

AD15-ADO --------11+----~

IRxREQ

IWAITIIRDY
(Walt)

IWAIT/tRDY
(Ready)

Figure 57. DMA Read Cycle

ITxACK

J
13

)

AD15-ADO

-®

ITxREQ

foo~

IWAITIIRDY
(Wait)

IWAITIIRDY
(Ready)

J
J

\
\

I
22

Figure 58. DMA Write Cycle

123

'--

/CS

®-~

AllB,OllC

®-~

-®

jr-

ISITACK

®-~

--,

lAS

\
-®

'-0~
.~

7
3

RlIW

@-~

~--®

IDS

11
4

)

A015-ADO

®- ... --8 ... '"--@-

)

IRxREQ

\.
~~

IWAITIIROY
(Wait)

. 1

J
(

IWAlTIIROY

(Ready)

)
18

111

Figure 59. Multiplexed IDS Read Cycle

/CS

®-~

)

AlIB.OIIC

-®

®-~

ISITACK

-®

®-~
lAS

--,~

liJ

1-0RlIW

r--cv@H-

IDS

7
1

l~
5

)~
~--

A015-AOO

)

i1A

ITxAEQ

~+-@--

.@y
IWAITIIROY
(Wait)

IWAtTI/ROY
(Ready)

J
16

r
I

FiIJure 60. Multiplexed IDS Write Cycle

f-®r-

)~
®-I-

ICS

lK
o@)

AlIB.DIIC

@-r-

)

ISITACK

®-:..lAS

--,~

~ ~

lAD

./
2B

)

AD1S-ADO

@--

~-@

... --@33

IAxREQ

\
-®

IWAITIIRDY
(Wait)

IWAITt/RDY
(Ready)

)

:31

roof----@--

J
J

I
119

Figure 61. Multiplexed fRO Read Cycle

ICS

@-f-

) ..

AlIB,DIIC

@-f-

ISITACK

®--flAS

-'r\

~ f--%-

41
1

IWR

)

AD1S-ADO

[(

ISITACK

RlIW

\
51

®--

IDS

J
4

A015-ADO

r- --®::~

8
9

IRxREQ

ro~

--®IWAlTIIROY
(Walt)

IWAlTIIROY
(Ready)

J
J

)
~

I
I

Figure 63. Non-Multiplexed IDS Read Cycle

.K
.K

)

ICS

®-f/

AIIB,DIIC

)
®-f-

ISITACK

®-f.-.

RlIW

®-t-

IDS

)

AD15-ADO

l(
~

---®---

ITxREQ

~
IWAITI/RDY
(Wait)

IWAITI/RDY
(Ready)

J
J

\
~~

.~
Figure 64. Non-Multiplexed IDS Write Cycle

J
---®-

ICS

@--

NIB.DIIC

@--

ISITACK

®-IRD

~
57

l
28

AD1S-ADO

IRxREQ

\
.-®-

--®-/wAITIIRDY
(Wait)·

/wAIT/tRDY
(Ready)

J
J

)
~

711

-®-

Figure 65. Non-Multiplexed IRD Read Cycle

ICS

@--

AlIB, DIIC

@--

ISITACK

@--

IWR

/
39

)

AD15-ADO

)
--@--

-®----

ITxREQ

~
IWAITIIRDY
(Wait)

IWAITIIRDY
(Ready)

\
.. --®--

h9----I
Figure 66. Non-Multiplexed IWR Write Cycle

J
---@--

/'AS

ISITACK

IDS

ADl5-ADO

IWAITIIRDY
(Wait)

IWAITIIRDY
(Ready)

lEI

lEO

liNT

Figure 67. Multiplexed IDS Interrupt Acknowledged Cycle

lAS

ISITACK

IRD

AD15-ADO

IWAITIIRDY
. (Wait)

IWAITIIRDY
(Ready)

lEI
1---(92)---./

lEO

liNT

Figure 68. Multiplexed IRD Interrupt Acknowledge Cycle

lAS

IPITACK
~--------~~r---------~

ADl5-ADO

IWAITIIRDY
(Wait)

IWAITIIRDY
(Ready)

lEI

lEO

liNT

Figure 69. Multiplexed Pulsed Interrupt Acknowledge Cycle

ISITACK ..

IDS

ADl5-ADO

IWAITI/ROY
(Wait)

IWAITI/ROY
(Ready)

lEI

lEO

liNT

Figure 70. Non-Multiplexed IDS Interrupt Acknowledge Cycle

ISITACK

IRD

AD15-ADO

IWAITIIRDY
(Wait)

IWAITIIRDY
(Ready)

lEI

lEO

liNT

Figure 71. Non-Multiplexed Pulsed Interrupt Acknowledge Cycle

IPITACK

.....--------{1 , l - - - - - I H - - - - - - . - J
~D15-ADO
1-+---{II00~--t

IWAITIIRDY
(Ready)

lEI

lEO

liNT

IWAITIIRDY
(Wait)

Figure 72. Non-Multiplexed lAD Interrupt Acknowledge CYcle

lAS

IPITACK
(2-Pulse)

AD15-ADO

IWAITIIRDY
(Ready)

IWAITIIRDY
(Wait)

lEI

lEO

liNT

Figure 73. Multiplexed Double-Pulse Intack Cycle

IPITACK
(2-PUIse)

i - - - - ( ! " ' } - -. . .

A01~ADO ----------~~--------------~------_+~----_a

IWArTl/ROY
(Ready)

IWArTl/ROY
(Wait)

lEI

lEO

liNT

Figure 74. Non-Multiplexed Double-Pulse Intack Cycle

{RxC, fTxC
Receive

RxD

{DCDas
{SYNC
External

fTxC,{RxC
Transmit

TxD

{RxC

fTxC

{CTS,
{DCD

{DCDas
{SYNC
Input

>e.
\

en
~

r
r

C1LJ
C1LJ
Figure 75. Z16C30 General Timing

AC CHARACTERISTICS
Z16C30 General Timing
No

Symbol

Parameter ,

1
2
3
4

TsRxD(RxCr)
ThRxD,(RxCr)
TsRxd(RxCf)
ThRxD(RxCf)

RxD
RxD
RxD
RxD

5
6
7

TsSy(RxC)
ThSy(RxC)
TdTxCf(TxD)
TdTxCr(TxD)

lOCO as ISYNC to IRxC Rise Setup Time
lOCO as ISYNC to IRxC Rise Hold Time (x1 Mode)

8
9
10
11
12

TwRxCh
TwRxCI
TcRxC
TwTxCh

13
14
15
16

TwTxCI
TcTxC
TwExT
TWSY'

to IRxC Rise Setup Time (x1 Mode)
to IRxC Rise Hold Time (x1 Mode)
to IRxC Fall Setup Time (x1 Mode)
to IRxC Fall Hold Time (x1 Mode)

Min

Units

. Note

0
40
0
40

ns
ns
ns
ns

[1]
[1]
[1,3]
[1,3]

0
40

ns
ns
ns
ns

[1]
[1]
[2]
[2,3]

/TxC Fall to TxD Delay

50
50

ITxC Rise to TxD Delay
IRxC High Width
IRxC Low Width
IRxC Cycle Time

Max

/TxC High Width

40
40
100
40

ns
ns
ns
ns

ITxC Low Wicjth
/TxC Cycle Time
lOCO or ICTS Pulse Width
lOCO as ISYNC Input Pulse Width

40
100
70
70

ns
ns
ns
ns

IRxC,rrxC
Receive

IRxREO
Request

IRxCas
Receiver
Output

liNT

IRxC,rrxC
Transmit

rrxREO

rrxCas
Transmitter
Output

liNT

ICTS, lOCO,
rrxREO,
IRxREO

__________~K~--------------------

liNT

I
Figure 76. Z16C30 System Timing

AC CHARACTERISTICS
Z16C30 System Timing
No

Symbol

Parameter

1
2
3

TdRxC(REO)
TdRxC(RxC)
TdRxC(INT)

4
5
6

TdTxC(REO)
TdTxC(TxC)
TdTxC(INT)
TdEXT(INT)

Max

Units

Note

IRxC Rise to /RxREO Valid Delay
/TxC Rise to IRxC as Receiver Output Valid Delay
IRxC Rise to liNT Valid Delay

100
100
100

ns
ns
ns

[2]
121
[2]

/TxC Fall to ITxREO Valid Delay

100
100
100

ns
ns
ns

[?]

100

IRxC Fall to /TxC as transmitter Output Valid Delay
/TxC Fall to liNT Valid Delay

ICTS, lOCO, /TxREO, IRxREO transition
to liNT Valid Delay

Noles:

[ll/RxC is /RxC or rrxC, whichever is supplying the receive clock.
[21 rrxC is rrxC or /RxC, whichever is supplying the transmit clock.
[3) Parameter applies only to FM encoding/decoding.

Min

[2]

~ZiIill

ADVANCE INFORMATION
PRELIMINARY PRODUCT SPECIFICATION

Z16C31
IUSC INTEGRATED
UNIVERSAL SERIAL CONTROLLER
FEATURES

•
•
•
•
•
•
•

•

•
•
•

Full-duplex multiprotocol serial controller

•

Two full-capability DMA channels
Flexible adaptation to various system buses
Serial data rates to 10M bits/second
Serial modes include Asynchronous, Bisync, SDLC,
HDLC, Ethernet, 1553B, and 9-Bit.
Two baud rate generators
Digital phase-locked loop for clock recovery
Receive and Transmit Time Slot Assigners for ISDN
applications.
Eight general-purpose I/O lines plus Carrier Detect
and Clear to Send.
Transmit and receive frame-length counters,
independent of the DMA facility.
Async features include false-start filtering, stop bit
length programmable by 1/16 bit steps, parity
generation/checking, break generation/detection.

•
•
•
•
•
•
•
•
•

HDLC/SDLC features include 8-bit address checking,
extended address support, 16/32 bit CRC,
programmable idle state, auto preamble option, loop
mode.
Sync features include 2- to 16-bit sync, sync-strip
option, 16/32 bit CRC, programmable idle state, auto
preamble option, X.21 transmitter/receiver slaving.
Automatic control character recognition in Transparent
'
Bisync mode.
32-byte transmit and receive FIFOs between serial
controller and DMA channels.
DMA modes include single block, buffered, arraychained, and link-chained.
Programmable throttling of DMA bus occupancy
16/32 bit addressing, 8- or 16-bit data
Flexible interrupt and bus-arbitration modes, interrupt
and bus-acknowledge daisy-chains.
High speed, low power CMOS technology
68-pin PLCC

GENERAL DESCRIPTION
. The IUSC (Integrated Universal Serial Controller) is a
single-channel multiprotocol data communications device
with on-chip OMA designed for use with any conventionill
multiplexed or non-multiplexed bus The IUSC functions
as a serial-to-parallel, parallel-to-serial converter/controller and is software configured to satisfy a wide variety of
serial communications applications under OMA cOl)trol.
The device contains a variety of sophisticated internal
functions including two baud rate generators, a digital
phase-locked loop, character counters for both receive
and transmit, 32-byte FIFOs for both the receiver and
transmitter and a two-channel, 32-bit OMA controller.
The IUSC handles a wide variety of formats including
asynchronous, synchronous byte-oriented (e.g. BISYNC),
and synchronous bit-oriented formats such as SOLC
and HOLC.
The IUSC can generate and check CRC in any synctlronous mode and is programmed to check data integrity in
various modes The IUSC also has facilities for modem
controls. In applications where these controls are not
needed, the modem controls may be used for generalpurpose I/O

Interrupts are supported by a daisy-chain hierarchy within
the serial channel and between the serial.channel a,nd the.
OMA. There are no interrupts associated with the a-bit port.
The on-Chip OMA channels allow higll-speed data transfers for both the receiver and the transmitter, The device
supports automatic status transfer via OMA and allows
device initialization under OMA control. Each OMA channel provides for 32-bit addresses and a 16-bit transfer
length, The OMA channels may operate in any of four
modes: normal, buffered, array-chained, or linked arraychained. The OMA bus mastership time may be limited,
under program control, as to the absolute number of clock
cycles, or the number of bus transactions, or both. This
prevents the IUSC from hogging the bus.
Note: All Signals with a preceding front slash, .1", are active
Low e.g.; BIIW (WORD is active Low); IBIW (BYTE is active
Low, only); INIIS (NORMAL and SYSTEM are both
active Low).

Host
Processor

Serial Clock Logic
DPLL
Counters

BRGO, BRG1

Figure 1.IUSC Block Diagram

Receiver

VDD
AD15:0

CLK
IRESET

IUAS

ICS

lAS

DIIC

IDS

SliD

IRD

!WR
!Wait//RDY

RI!W
BI!W

IINTACK
lEI

. Z16C31
IUSC

liNT
lEO
IBUSREQ

IABORT
IBIN

IBOUT

IAxC

IRxREQ

/TxC

TxREQ
TxD

"RxD
ICTS
lOCO

Port 7:0
VSS
Figure 2. Logic Symbol

IABORT
liNT
lEI
lEO

IBIN
IBUSREQ

eLK
IBOUT

GND

vee'
ADO
AD1
AD2
AD3

AD4

vee
ADS

Z16C31
IUSC

AD9
AD10
AD11
AD12
AD13
AD14
AD15
GND

(Top View)

ADS
AD6
AD7
GND

vee

IRxREQ

~44

PORT7

Note: Power connections follow
Conventional desaiptions below
Connection

Circuit

Device

Power
Ground

Vee

Voo
Vss

GND

Figure 3. Packaging

PIN DESCRIPTIONS
IRESET. Reset (input, active Low). A low on this line will
place the IUSC in a known, inactive condition. /RESET
should be driven low as soon as possible during power-up,
and as needed thereafter when restarting the overall
system or the communications subsystem.
CLK. System Clock (input). This Signal is the timing reference for the DMA and bus interface logic. (The serial
controller section is driven solely by the selected sources
01 receive and transmit clocking.)
AD15-ADO. Address/Data Bus(3-state input/outputs). Alter
Reset. these lines carry data between the controlling
microprocessor and the IUSC, and may also carry multiplexed addresses of registers within the IUSC. Such operation, between the host processor and,the IUSC, is often

called slave mode, Once the MPU software has set up the
IUSC and placed it into operation, these lines also carry
multiplexed addresses and data between the IUSC and
system memory; such operation is called master mode.
These lines are used in a variety of ways based on the value
initially written to the Sus Configuration Register (SCR), as
described in the text.
ICS. Chip Select (input, active Low). In slave mode, a low

on this line indicates that the controlling microprocessor's
current bus cycle is targeted lor a register in the IUSC, ICS
is ignored in master mode, and also when a low on
IINTACK indicates that the current bus operation is an
interrupt acknowledge cycle. On a multiplexed bus, ICS is
latched by rising edges on lAS.

lSI/~.

SerialiDMA (input, High indicates serial). Slave
cycles with /CS low and /INTACK and this pin both high,
access registers in the serial controller section. Slave
cycles with liNT ACK high and /CS and this pin both low,
access. registers in the OMA controller section.

The IUSC can be programmed so that when it is acting as
a bus master,' it .drives this line low to indicate an array
access cycle and high to indicate a normal cycle for the
transmitter or receiver.
Ol/C. Data/Contro/(input, High indicates Data). A slave read
cycle with /CS low and all three of /INTACK, S//D, and this
pin high, fetches data from the serial controller's Receive
Data Register (FIFO). A slave write cycle with the same
conditions writes data Into the Transmit Data Register
(FIFO). Slave cycles with both /INTACK and S//D high and
both /CS and this pin low, access a serial controller
register; on a multiplexed bus the particular register is
selected by the low-order AD lines at the riSing edge of /AS;
on a non-multiplexed bus the particular register is selected
by the LSB's of the serial controller's Channel Command/
Address Register.
For slave cycles on a multiplexed bus, with /INTACK high
and both /CS and SliD low, the state of this line at the rising
edge of /AS selects between the registers of the receive
DMA channel (low) and the transmit DMA channel (high).
On a non-multiplexed bus with /INT ACK high and /CS and
SliD both low, the channel selection is taken from the DMA
controller's address pointer register. and the state of this
line does not affect the cycle.
The IUSC can be programmed so that when it is acting as
a bus master, it drives this line low to indicate a DMA cycle
for the receiver and high to indicate a cycle for the
transmitter.

lAS. Address Strobe (input/output. active Low, 3-state).
After a reset. the IUSC's bus interface logic monitors this
signal to see if the host bus multiplexes address and data
on A015-ADO. If the logic sees activity on /AS before (or as
part of) the initial write to the Bus ConfigUration Register
(BCR), then in subsequent slave cycles, the IUSC captures register selection from the low-order AD lines, S//D,
and CliO on rising edges of /AS. When the IUSC takes
control of the bus and operates as a master, it always uses
the bus in a multiplexed fashion, and drives /AS low to
indicate the presence of the least significant 16 bits of an
address on the AD15-AOO lines. External latches are used
to de-multiplex the address and data, if this is necessary
to match the characteristics of the host processor or
host bus.
For a non-multiplexed bus, this pin should be pulled up to
+5V using a resistor of about 4.7K ohms. If a processor

uses a non-multiplexed bus, yet has an output called
Address Strobe (e.g., 680xO devices), this pin should not
be tied tp the processor's output.

IUAS. Upper Address Strobe (3-state output, active Low).
When the IUSC takes control of the bus and operates as a
master, it drives IUAS low to indicate the presence of the
more significant 16 bits of an address on AD15-ADO.
External slaves or de-multiplexing latches should capture
th~ MS address at each rising edge on this line.
RlIW. Read I Write control (3-state input/output, Low signifies Write). This line is used in conjunction with the IDS
line for host processors/buses having this kind of signalling, to indicate read and write cycles on the bus. When the
IUSC has taken control of the bus and is operating in
master mode, this pin is an output that remains valid
throughout the low time of /DS. Otherwise, it is an input that
is sampled at the leading/falling edge of /OS.
OS. Data Strobe (3-state input/output, active Low). This
line is used in conjunction with the R//W line for host
processors/buses having this kind of signalling, to indicate
read and write cycles on the bus. It is an output when the
IUSC has taken control of the bus and is operating in
master mode, otherwise it is an input that is qualified by
/CS low or /INT ACK low. The R//W line remains valid
throughout the low time of this line. For slave write cycles
and master read cycles, the IUSC captures data at the
rising (trailing) edge on this line. For slave read cycles,
data is valid on the AD lines after the specified access lime
and remains valid until after the master releases this line to
high. For master write cycies, the IUSC places valid data
on the AD lines before it drives this signal to low, and keeps
the data valid until after it drives,thisJine back to high.

IRO. Read Strobe (3-state input/output. active Low). This
line is used in conjunction with the /WR line for host
processors/buses having this kind of signalling, to indicate
read and write cycles on the bus. It is an output when the
IUSC has taken control of the bus and is operating in
master mode, otherwise, it is an input that is qualified by
/CS low or /INTACK low. For master read cycles, the IUSC
captures data at the rising (trailing) edge of this line. For
slave read cycles, data is valid on the AD lines after the
specified access time and remains valid until after the
master releases this line to high.

IWR. Write Strobe (3-state input/output, active lOW). This
line is used in conjunction with the /RD line for host
processors/buses having this kind of signaling, to indicate
read and write cycles on the bus. It is an output when the
IUSC has taken control of the bus and is operating in
master mode, otherwise, it is an input that is qualified by
/CS low or /INTACK low. for slave write cycles, the IUSC
captures data at the rising (trailing) edge of this line. For

PIN DESCRIPTIONS (Continued)
master write cycles, the IUSC places valid data 9n the AD
lines before it drives this signal to low, and keeps the data
valid until after it drives this line back to high.

B/fW. Byte/Word select (3-state output, High indicates 8bit transfer). When the IUSC takes control of the bus and
operates as a master, a high on this line indicates that a
byte is to be transferred, a low indicates that 16 bits are to
be transferred. For slave cycles on a non-multiplexed bus,
the byte/word distinction is taken from bit 60f the Command/
Address register of the serial controller or DMA controller
as applicable. For slave cycles on a multiplexed bus, the
byte distinction is taken from an AD line at the rising edge
of /AS.
fWArrIlRDY. Wait, Ready, or acknowledge handshaking
(3-state input/output, active Low). This line is an input when
the IUSC has taken control of the bus and is operating in
master mode, otherwise, it is activated as an output when
the IUSC detects a cycle with /CS or /INTACK low. In both
directions, the way the line is used depends on the state of
the SliD input that the IUSC captured during the initial BCR
write. If SliD was high when the BCR was written, this line
operates as a Wail/Ready line for Zilog and most Intel
processors: the IUSC will not complete a master cycle
while this line is low, and it may assert this line low until it
is ready to complete a slave cycle.
If SliD was low when the BCR was written, this line operates
as an Acknowledge line for Motorola and some Intel
processors; the IUSC will not complete a master cycle until
this line is low, and it asserts this line low when itis ready
to complete a slave cycle.
!INT. Interrupt Request (output, aotive Low). This line is
driven low by either the serial controller and/or the DMA
controller sections, when one or more interrupt condition(s)
is(are) enabled, pending, and not being serviced by the
host processor. The IUSC can be programmed to drive this
pin either totem-pole or open-drain.
IINTACK. Interrupt Acknowledge(input, active Low). A low
on this line indicates that the host processor is performing
an interrupt acknowledge cycle. In some systems, a low on
this line may further indicate that external logic has selected
this IUSC as the device to be acknowledged, or a potential
device to be acknowledged. The initial write to the BCR
includes selection of whether this line carries a levelsensitive "status" protocol, or a single-pulse or doublepulse protocol. Depending on this programming and the
state of the /INT and lEI lines, the IUSC will respond in a
variety of ways.

lEI. Interrupt Enable In (input. active High). This Signal can
be uSed with lEO to form an interrupt-acknowledge daisychain with other devices that may request interrupts. If lEI
is high outside of an interrupt acknowledge cycle, and one
or more IUSC interrupt condition(s) is(are) enabled,
pending, and not being serviced by the host processor,
then the IUSC will request an interrupt by driving /INT low.
If lEI is high during an interrupt acknowledge cycle, and
one or more IUSC interrupt condition(s) is(are) enabled,
pending, and not being serviced by the host processor,
then the IUSC will keep the lEO line low and responds to
the cycle.
lEo'. Interrupt Enable Out (output, active High). This signal
can be used with lEI to form an interrupt-acknowledge
daisy-chain with other devices tt1at may request interrupts.
lEO is low whenever lEI is low, and/or whenever an IUSC
interrupt is under service. In addition, during an interrupt
acknowledge cycle, lEO is forced low if the IUSC is (has
been) requesting an interrupt.
IBUSREQ. Bus Request( output, active Low). This Signal is
used by the DMA controller section to request control of tl18
host bus. It is selected as an -open-drain or totem-pole
output in the initial write to the BCR. If this line is used as
open-drain, the Iuse samples the pin as an input and only
drives it low after it has sampled it 11igh.
IBIN. Bus acknowledge In (input, active Low). When the
IUSC receives a falling edge on this input, it samples
whether it has been driving (or has just begun to drive)
/BUSREQ. If so, it keeps /BOUT high and takes control of
the host bus. If not. it passes the bus grant by driving
/BOUT to low. This signal can be used with /BOUT to form
a bus-grant daisy chain for arbitration of bus control.
Alternatively, it can be connected to a direct. positive grant
from an extemal arbiter, and the /BOUT signal is ignored.

IBOUT. Bus acknowledge Out (output, active Low). As
noted above, this signal can be used with /BIN to form a
bus-grant daisy-chain for arbitration of bus control.
IABORT. Abortmaslercycle(input, active Low). The IUSC
monitors this input in master mode. A low on this line
indicates that the DMA channel terminates its activity and
enter a disabled state at the end of the current cycle. Note
that· 1) /ABORT is only effective during a DMA cycle, so
that the IUSC knows which cl1annel should be "aborted",
and 2) external logic sets /WAIT//RDY to the right state for
the cycle to complete, before /ABORT becomes effective.
RxD. Received Data(input, pOSitive logic). The serial input
data to the serial controller section.

TxD. Transmit Data (output, positive logic). The serial
output data from the serial controller section.
RxC. Receive Clock (input or output). As an input. this
signal is used as a clock signal for any of the functional
blocks within the serial controller section. Or, the IUSC can
be programmed so that this pin is an output carrying any
of several receiver or internal clock signals.
TxC. Transmit Clock (input or output). As an input. this
signal is used as a clock signal for any of the functional
bJocks within the serial controller section. Or, the IUSC can
be programmed so that this pin is an output carrying any
of several transmitter or internal clock Signals.

which is normally handled by the transmit DMA channel.
More typically, it is used as a general-purpose input or
output.

lOCO. Data Carrier Detect (input or output. active Low).
The IUSC can be programmed so that this signal enables/
disables the receiver. The IUSC can also be programmed
to request interrupts in response to transitions on this line.
The pin is also used as a simple input or output.
ICTS. Clear to Send(input or output, active Low) The IUSC
can be programmed so that this signal enables/disables
the transmitter. The IUSC can also be programmed to
request interrupts in response to transitions on this line.
The pin is also used as a simple input or output.
.

IRxREQ. Receive Request (input or output). In device
testing, or in applications not using the serial controller and
DMA controller sections together in the usual way, this pin
carries the low-active request from the receiver FIFO,
which is normally handled by the receive DMA channel.
More typically, it is used as a general-purpose input or
output.

PORTO-7. Input/output Port (inputs and/or outputs). The
IUSC can be programmed so that these lines are inputs
and/or outputs in any mixture. These lines are used for
additional status and/or control signals for a modem, or for
any other purpose. Transitions on input lines are captured
by internal latches.

ITxREQ. Transmit Request (input or output). In device
testing, or in applications not using the serial controller and
DMA controller sections together in the usual way, this pin
can carry the low-active request from the transmit FIFO,

Vee, Vss. Power and Ground. Trw inclusion of seven pins
for each power rail ensures good signal integrity, prevents
transients on outputs, and improves noise margins on
inputs.

FUNCTIONAL DESCRIPTION
The basic structure of the IUSC is shown in Figure 1. The
Bus Interface module stands between the external bus
pins and an on-chip 16-bit data bus that interconnects the
other functional modules. It includes several flexible bus
interfacing options that are controlled by the contents of
the Bus Configuration Register (BCR). The BCR is automatically the destination of the first word written by the host
processor after a Reset; thereafter, it is no longer accessible to the host software.
The Transmit DMA channel has the task of fetching data to
be transmitted from output buffers in memory on the host
processor's bus, and delivering this data to the IUSC's
Transmit First-In, First-Out (FIFO) memory. The host software can set up the Transmit DMA channel to operate in
any of four major modes. In single-block mode, the channel transfers one block Of consecutive bytes with a programmable location and length from host memory to the
Transmit FIFO. It then notifies the host processor and
stops. The processor has to reprogram the channel before
it can transfer another block, but in many applications this
is satisfactory because the Transmit FIFO is 32 bytes
deep. In ping-pong mode, there are two sets of buffer
address and length registers' the processor can be pro-

grarnming one set while the DMA channel IS using the other
set. When the channel finishes transferring one block, it
notifies the host processor and automatically switches to
transferring the block described by the other register set
In array-chained mode, the host processor programs the
Transmit DMA channel with the address of a table containing' the addresses and lengths of the actual memory
buffers. When the channel finishes transferring the data
from one memory buffer to the Transmit FIFO, it automatically fetches the next buffer address and length from the
table and begins to transfer the data in that buffer. Finally,
in link-chained mode the host programs IIle channel with
the address of the start of a linked list of buffer addresses
and lengths, wherein each entry also includes the address
of the next entry. Channel operation is similar to arraychained mode but includes the extra steps of fetching the
link addresses.
At any point in time, the Transmit FIFO can be emptyor can
contain from 1to 32 characters to be transmitted. Characters written into the FIFO automatically migrate to its other
end, where they become available to the Transmitter.

FUNCTIONAL DESCRIPTION (Continued)
While the host processor can itself write characters into the
Transmit FIFO, the best use of the IUSC is to use the
Transmit DMA channel to do so. The host can program the
IUSC so thatthe Transmit DMA channel swings into operation at varying degrees of FIFO emptiness. Selecting this
point involves balancing the probability and consequences
of under running the transmitter against the overhead for
the DMA channel to repeatedly acquire the host bus.
The serial Transmitter takes characters from the Transmit
FIFO and converts them to serial data on the TxD pin. While
this function is conceptually simple, the IUSC( supports a
good number of complex serial protocols, which increases
the complexity of the Transmitter dramatically. For example, depending on the serial mode selected, the Transmitter may do any of the following in addition to parallelserial conversion: start. stop, and/or parity bit generation,
CRC calculation and transmission, automatic generation
of opening and closing flags, encoding the serial data into
any of several fo~mats th?t guarantee transitions and carry
clocking with the data, and/or hardware flow control based
on the CTS input pin.
rinally, for ISDN and other time-multiplexed applications,
the Transmitter section includes Time Slot Assigner logic
that can be programmed to activate the Transmitter only
periodically and for certain bits within a multiple-sourced,
cyclically time-multiplexed data stream.
In general, the functions of the Receiver section are the
inverse to those of the Transmitter. The receiver monitors
the serial data on the TxD pin, recognizes its organization
according to the programmed serial mode, and converts
the data to parallel characters which it puts into the
Receive FIFO. Once again, there is much more going on
than just serial-parallel conversion - depending on the
serial mode the Receiver may have to: start bit detection
and synchronization, parity and stop bit checking, CRC
calculation and checking, detection of flag, abort and idle
sequences, control character and transparency recognition, decoding of the serial data and clock extraction from
any of several serial-encoding schemes, and/or disabling/
squelching based on the DCD input pin Based on such
checking,the Receiver generates several status bits associated with each character, and writes them into the
Receive FIFO along with the character.
The Receiver section also includes an optional Time Slot
Assigner which is used to activate the rest of the Receiver

for certain bits within a multiple-destination, cyclically
time-multiplexed data stream such as an ISDN link.
The Receive FIFO can hold up to 32 characters and their
associated status bits. As entries are written in by the
receiver, they automatically migrate to the output side
where they become available to either the host processor
or the Receive DMA channel. As for the Transmit FIFO,
there is detection logic for various degrees of fullness; it
controls when the Receive DMA channel is set into operation and/or when the host processor is interrupted. In
addition to the main Receive FIFO there is a 4-entry Frame
Status FIFO that is used to 110Id status related to entire
frames rather than to individual characters.
While the host processor can access data directly from the
Receive FIFO, the IUSC is used to best advantage when
the Receive OMA section is programmed to transfer the
received data into buller areas in memory on the host
processor's bus. As descriQed for the transmit side, the
Receive DMA channel can be programmed to operate in
single-buflermode, ping-pong mode, array-chained mode,
or link-chained mode.
.
Tile Serial Clocking Logic section makes up the clocking
signals for both the Transmitter and Receiver It can be
programmed to do this based on two internal Baud Rate
Generators or on external clocks. It includes a Digital
Phase-Locked Loop that can recover clocking from an
encoded serial stream on RxD.
The Interrupt Control section gathers the various request
lines from the Transmitter, Receiver, and the DMA channels, and handles the details of requesting host interrupts
and responding to host interrupt-acknowledge cycles or to
software equivalents. Interrupt operation is affected by
both the initial write to the Bus Configuration Register
(BCR) and by several registers in the Receiver, Transmitter,
and DMA Channels.
In addition to the Clear to Send (CTS) and Carrier Detect
(DCD) inputs, which are handled by the Transmiller and
Receiver, respectively, the I/O port section provides eight
pins that can be used for additional modem control lines or
any other purpose. Each pin can be individually controlled
as an input or output, and some of them have optional
dedicated functions.

~ZiIm

PRODUCT SPECIFICATION

Z16C33
CMOS MUSC
MONO-UNIVERSALSERIALCONTROLLER
FEATURES
•

0 to 10 MbiVsec, full-duplex channel, with two baud
rate generators and a digital phase-locked loop for
clock recovery.

32-byte data FIFO's for receiver and transmitter

•

12.5 MByte/sec (16 bit) data bus bandwidth

Multi-protocol operation under program control with
independent mode selection for receiver and
transmitter.

•

Async mode with one to eight bits/character, 1/16 to 2
stop bits/character in 1/16 bit increments;
programmable clock factor; break detect and
generation; odd, even, mark, space or no parity and
framing error detection. Supports one Address/Data
bit and MIL
1553B protocols.

•

Byte oriented synchronous mode with one to eight
bits/character; programmable idle line condition;.
optional receive sync stripping; optional preamble
transmission; 16- or 32-bitCRC and transmit-ta-receive
slaving (for X.21).
Bisync mode with 2- to 16-bit programmable sync
character; programmable idle line condition; optional
receive sync stripping; optional preamble transmission;
16- or-32 bit CRC.

T-ransparent Bisync mode with EBCDIC or ASCII
character code; automatic CRC handling;
programmable idle line condition; optional preamble
transmission; automatic recognition of OLE, SYN, SOH,
ITX, ETX, ETB, EOT, ENQ and ITB.

HDLC/SDLC mode with eight bit address compare;
extended address field option; 16- or 32-bit CRC;
programmable idle line condition; optional preamble
transmission and loop mode.

•

DMA interface with separate request and acknowledge
for the receiver and transmitter

Channel load command for DMA controlled
initialization

•

Flexible bus interface for direct connection to most
microprocessors; user programmable for 8 or 16 bits
wide. Directly supports 680XO family or 8X86 family
bus interfaces.

ISDN time slot assigner

8-bit general purpose port with transition detection

Low power CMOS

•

68-pin PLCC package

External character sync mode for receive

GENERAL DESCRIPTION
The MUSe (Mono - Universal Serial Controller) is a singlechannel multi-protocol data communications peripheral
designed for use with any conventional multiplexed or nonmultiplexed bus. The MUSC functions as aserial-ta-parallel,
parallel-to-serial converter/controller and is software configured to satisfy a wide variety of serial communications
applications. The device contains a variety of new, saphisticated internal functions including two baud rate

generators, a digital phase-locked loop, character counters
for both receive and transmit, and 32-byte data FIFO's for
both the receiver and transmitter.
The MUSC handles asynchronous formats, synchronous
byte-oriented formats (e.g. BISYNC), and synchronous
bit-oriented formats like HOLC. This device supports virtually any serial data transfer application.

GENERAL DESCRIPTION (Colltinued)
The device can generate and check eRe in any synchronous mode and is programmed to check data integrity
in various modes. The MUSe also has facil.ities for modem
controls. In applications where these controls are not
needed, the modem controls are used for general-purpose
1/0. The same is true for most of the other pins.
.

Interrupts are supported by a daisy-chain hierarchy with
the serial channel. There are no interrupts associated with
the 8-bil Port.
High-speed data transfers via DMA are supported by a
Request/Acknowledge signal pair for both receiver and
transmitter. The device supports automatic status transfer
via DMA and allows device initialization under DMA
control.

Support tools are available to aid the deSiQner Ih .efficiEmHy
programming tbe MUSe. TheTech.nlc\i1 tvjanual qesct:ibes
in detail all features presented In this Product Specification
and gives programming sequence hints. The Programmer's
Assistant Is an MS-DOS, disk-based programming initialization tool, used in conjunction with the Technical Manual.
Also, there are assorted application notes and development
boards to assist the designer in hardware/software
development.
Note: All Signals with a preceding front slash, "r, are active
Low, e.g.: 81IW (WORD is active Low); IBIW (BYTE is
active Low, only); INIIS (NORMAL and SYSTEM are both
active Low).

Receive Data

Receivel
Transmit

Clocks

cpu

Transmit Data

Figure 1. MUSe Block Diagram'

_... ...
Address!
Data
Bus

...
...
...
...

.
.
.
.
.

....
-~

...

Bus {
Timing

Interrupt {

...
...

TxD

AD1

RxD

AD2

ITxC
IRxC

AD3
AD4

ICTS

AD5

lOCO

AD6

IRxREQ

AD?

IRxACK

AD8

ITxREQ

AD9

ITxACK

AD10

liNT

AD11

lEI

AD12

lEO

AD13

PORTO

AD14

PORT 1

AD15

PORT 2

lAS

PORT 3

IDS

PORT 4

IRD

PORT 5

IWR

PORT 6

ICS
PS

PORT?

-'"'

DIIC

.
..
.

RlIW

_...

Ground

ADO

...

.....
...

... ..
... .
.
...

..
..

}

Serial
Data

}

Channel
Clocks

}

Channel

}

Channel
DMA
Interface

}

Channel
Interrupt
Interface

1/0 Port

....

...

...
...

IPITACK
ISITACK

...

VSS

IRESET
VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

...

VSS

VDD
VDD

...

IWAITIIRDY

VSS

...

Device Reset

Power
'

Figure 2. Pin Functions

Note: Power connections follow
conventional descriptions below:
Connection Circuit

,--,-""",,,"~,

-~------

Power

Vee

Ground

GND

Device

V""
Vss

(j)

IRxACK
liNT

lEI
lEO
GND
VCC

ADO
ADl
AD2
AD3
AD4
AD5
AD6
AD7
GND
VCC
IRxREQ

Muse

(Top View)

NC
NC
NC
NC
GND
VCC
ADS
AD9
AD10
AD11
AD12
AD13
AD14
AD15
GND
VCC
PORT 7

Note: Power connections follow
Conventional descriptions below
Connection

Circun

Device

Power
Ground

Vee

Voo
Vss

GND

Figure 3. Pin Assignments

PIN DESCRIPTION
~

The device contains 13 pins for channel I/O, 16 pins for
address and data, 12 pins for CPU handshake, 8 pins for
the I/O Port, and 14 pins for power and grQund,

The 8-bit bus with separate address is selected by setting
BCR bit 2 to zero and, during the BCR write, forcing AD15
to a 1 and forcing AD14-AD8 to zero,

Three separate bus interface types are available for the
device: The Bus Configuration Register (BCR), the external connection of the Protocol Select (PS) pin, and external
connections to the AD bus control selection of the
bus type,

The multiplexed bus is selected for the MUSC if there is an
Address Strobe prior to, or during, the transaction which
writes the, BCR

A 16-bit bus is selected by setting BCR bit 2 to a 1,
The 8-bit bus is selected by setting BCR bit 2 to zero and
tying AD15 - AD8 to VSS,

If no Address Strobe is present prior to or during the
transaction which writes the BCR', a non-multiplexed bus is
selected (See Figure 6),

PIN ASSIGNMENTS
IRESET. Reset(input, active Low). This signal resets the
device to a known state. The first write to the MUSC after
a reset accesses the BCR to select additional bus options
for the device.
lAS. Address Strobe (input, active Low). This signal is
used in the multiplexed bus modes to latch the address on
the AD lines. The lAS signal is not used in the nonmulliplexed bus modes and is tied to VDD in these cases.
IDS. Data Strobe (input, active Low). This signal strobes
data out 01 the device during a read and strobes an
interrupt vector out of the device during an interrupt
acknowledge cycle. IDS also strobes data into the device
depending on the state of R//W.

IRO. Read Strobe (input, active Low). This signal strobes
data out of the device during a read and ~trobes an
interrupt vector out of the device during an interrupt
acknowledge cycle.

IWA. Write Strobe (input, active Low). This signal strobes

IPfTACK. Pulsed InterruptAcknowledge(input, active Low)
This is a strobe signal indicating that an interrupt acknowledge cycle is in progress. The device is capable of
returning an interrupt vector that is encoded with the type
of interrupt pending during this acknowledge cycle.
/PlTACK is programmed to accept either single pulse or
double pulse acknowledges. This programming is performed in the BCR. The double pulse acknowledge is
compatible with 8X86 family microprocessors.
IWAITI/ROY. Wait/Data Ready (output, active Low). This
signal serves to indicate wHen the data is available during
a read cycle, when the device is ready to receive data
during a write cycle, and when a valid vector is available
during an interrupt acknowledge cycle. It is programmed
to function either as a Wait signal or a Ready signal using
the state of the PS pin during the BCR write. When PS is
High during the BCR write, this Signal functions as a wait
output and supports the .READY function of 8X86 family
microprocessors. When PS is Low during the BCR write, it
functions as a ready output and supports the DTACK
function of 680XO family microprocessors.

data into the device during a write.
RlIW. Read/Write (input). This signal determines the
direction of data transfer for a read or write cycle in
conjunction with IDS
ICS. Chip Select(input, active Low). This signal selects the
device for access and is asserted for read and write
cycles, but is ignored during interrupt acknowledge and
fly-by DMA transfers. In the case of a multiplexed bus
interface, ICS is latched by the rising edge of lAS.

PS. Protocol Select (input, active High). This input is
sampled and stored during the BCR (Bus Configuration
Register) write It selects the sense of the /WAll/tRDY
, signal appropriate for different bus interfaces. With PS
High, /WAITI/RDY functions as a /WAIT signal and with PS
Low, IWAlTl/RDY functions as a IREADY signal This selection applies to all bus transactions.
Ol/C. Data/Control Select (input) This signal, when Hig/),
provides for direct access to the RDR and TDR. In the case
of a multiplexed bus interface, DI/C High overrides the
address provided to the device.
ISfTACK. Status Interrupt Acknowledge (input, active Low).
This signal is a status signal indicating that an interrupt
acknowfedge cycle is in progress. The device is capable
of returning an interrupt vector that is encoded with the
type of interrupt pending during this acknowledge cycle.

A015-AOO. Address/Data Bus(bidirectional, active High,
3-state). The AD signals carry addresses to, and data to
and from, the device. When the 16 bit non-multiplexed bus
is selected, AD15-0 carries data to and from the device.
Addresses are provided using a pointer within the device
that is loaded with the desired register address. When the
8-bit non-multiplexed bus, without separate address, is
selected only AD7-0 is used to transfer data. The pointer is
used for addressing, and AD15-8 is unused. When the
8-bit non-multiplexed bus with separate address is selected
AD7-0 is used to transfer data, while AD15-8 is used as an
address bus. When the 16 bit multiplexed bus is selected,
addresses are latc/led from AD7 -0 and data transfers are
sixteen bits wide. When the 8-bit multiplexed bus without
:;;eparate address is selected only AD7 -0 is used to transfer
addresses and data, and AD15-8 is unused When the
8-bit multiplexed bus with separate address is selected
only AD7-0 is used to transfer data, while AD15-8 is used
as an address bus.
The non-multiplexed, 16-bit bus interface mode directly
supports 680XO family microprocessors and the multiplexed, 16-bit bus interface mode directly supports the
8X86 family microprocessors. The multiplexed, 8-bit bus
interface mode without separate address supports the
8088 family microprocessors.

PIN ASSIGNMENTS (Continued)
liNT. Interrupt Re,quest( output, active Low). Indicates that
the channel has an interrupt condition pending and is
requesting service. This output is NOT open-drain.
lEI. Interrupt Enable In (input, active High). The lEI signal
is used with the accompanying lEO signal to form an
interrupt daisy chain. An active lEI indicates that no device
having higher priority is requesting or servicing an interrupt.
lEO. Interrupt Enable Out (output, active High). The lEO
signal is used with the accompanying lEI signal to form an
interrupt daisy chain. lEO is Low if lEI is Low, an interrupt
is under service in the channel, or an interrupt is pending
during an interrupt acknowledge cycle.
fTxACK. Transmit-Acknowledge (input or output, active
Low). The primarY function ·of this signal is to perform
fly-by DMA transfers to the transmit FIFO. It also is used as
bit input or output.
IRxACK. Receive Acknowledge (input or output, active
Low). The primary function of this signal is to perform
fly-by DMA transfers from the receive FIFO. It also is used
as bit input or output.

blocks within the device. It also is used as an output for
various transmitter Signals or internal clock signals.

IRxC. Receive Clock (Input or output, active Low). ThiS
signal is used as a clock input for any of the functional
blocks within the device. It also is used as an output for
various receiver signals or internal clock signals.
fTxREQ. Transmit Request (input or output, active Low).
The primary function of this signal is to request DMA
transfers to the transmit FIFO. It also is used as a Simple
input or output.
IRxREQ. Receive Request (input or output, active Low).
The primary function of tllis signal is to request DMA
transfers from the receive FIFO. It also is used as a simple
input or output.

ICTS. Clear To Send (input or output, active Low) /CTS is
used as an enable for the· transmitter It also is programmed
to generate interrupt on either transition or used as a
simple input or output.

lOCO. Data Carrier Detect (input or output, active Low).
This signal is used as an enable for the receiver. It also is

TxD. Transmit Data (output, active High, 3-state). TxD
carries the serial transmit data for the channel.

programmed to generate an interrupt on either transition or
used as a simple input or output.

RxD. Receive Data (input, active High). RxD carries the
serial receive data for the channel.

PORT? - PORTO. Port Signals (inputs or outputs. active
High). These pins are general purpose I/O pins. They are
used as additional MODEM control lines or for other I/O
functions. When used as inputs, ttle ports capture transitions on these pins.

fTxC. Transmit Clock (input or output, activ~ Low). This
signal may be used as a clock input for anyof the functional

ARCHITECTURE
The MUSC internal structure includes a full-duplex serial
channel with' two baud rate generators, a digital phaselocked loop for clock recovery, transmit and receive
character counters and a full-duplex DMA interface. The
bus interface is designed to provide easy interface to most
microprocessors, whether they employ a multiplexed,

non-multiplexed, 8-bit or 16-bit bus structure Thechannel
is controlled by a set olthlrty-two 16-blt registers, almost all
of which are readable and writable. There is one additional
16-bit register in the bus interface used to configure the
nature.of the bus interface. The BCR functions are shown
in .Figure 4.

Address: None

Shift Right Addresses
Double Pulse INTACK
16-BitBus

0*
Reserved
3-State All Pins
Separate Address for 8-Bit Bus

* Must be programmed as O.
Figure 4. Bus Configuration Register

DATA PATH
Both the transmitter and the receiver in the channel are
actually microcoded serial processors. As the data shifts
through the transmit or receive shift register, the microcode
watches for specific bit patterns, counts bits, and at the

appropriate time transfers data to or from the FIFOs. The
microcode checks status and generates status interrupts
as appropriate.

FUNCTIONAL DESCRIPTION
The functional capabilities of the MUSC are described
from two different pOints of view: as a data communications
device, it transmits and receives data in a wide variety of
data communications protocols; as a microprocessor
peripheral, the MUSC offers such features as read/write
registers, a flexible bus interface, DMA interface support,
vectored interrupts, and an eight-bit I/O port.

signal such conditions as' overrun, parity error, framing
error, end-of-frame, idle line received, sync acquired,
transmit underrun, CRC sent, closing sync(flag sent, abort
sent, idle line sent and preamble sent In addition, several
useful intemal signals like receive FIFO load, received
sync, transmit FIFO read and transmission complete are
sent to pins for use by external circuitry.

Data Communications Capabilities

Asynchronous Mode. The receiver and transmitter handle
data at a rate of 1/16, 1/32, or 1/64 the clock rate. The
receiver rejects start bits less than one-half a bit time and
will not erroneously assemble characters following a framing
error. The transmitter is capable of sending one, two, or
anywhere in the range of 1/16ttl to two stop bits per
character in 1/16 bit increments.

The MUSC provides a full-duplex channel programmable
for use in any common data communication protocol. The
receiver and transmitter modes are completely independent. The receiver and transmitter are each supported by
a 32-byte deep FIFO and a 16-bit message length counter.
All modes allow optionai even, odd, mark or space parity.
Synchronous modes allow the choice of two 16-bit or one
32-bit CRC polynomial. Selection of from one to eight bits
per character is available in both receiver and transmitter
independently. Error and status conditions are carried with
the data in the receive and transmit FIFOs to greatly reduce
ttle CPU overhead required to send or receive a message.
Specific, appropriately timed interrupts are available to

External Sync Mode. The receiver is synchronized to the
receive data stream by an externally-supplied signal on a
pin for custom protocol applications.
Isochronous Mode. Both transmitter and receiver may
operate on start-stop (async) data using a 1x clock. The
transmitter sends one or two stop bits.

FUNCTIONAL DESCRIPTION (Continued)
Asynchronous With Code Violations. This is similar to Isochronous mode except that the start bit is replaced by a
three bit-time code violation patterri as in MIL-STO 1553B.
The transmitter sends zero, one or two stop bits.
Monosync Mode. In this mode, a single character is used
for synchronization. The sync character can be either
eight bits long with an arbitrary data character length or
programmed to match the data character length. The
receiver is capable of automatically stripping sync,characters from the received data stream. The transmitter is
programmed to automatically send CRC on either an
underrun or at the end of a programmed message length.
Bisync Mode. This mode is identical to monosync mode
except that character synchronization requires two successive characters for syncllronization. The two characters
need not be identical.

lOCO and ICTS are used to implement the carrier sense
and collision detect interactions with the receiver and
transmitter.
Slaved Monosync Mode. This mode is available only in the
transmitter and allows the transmitter (operating just as
though it were in monosync mode) to send data that is
byte-synchronous to the data being received by the
receiver.
HOLC Loop Mode. This mode is available only in the
transmitter and allows the MUSC to be used in an HOLC
loop configuration. In this mode, the receiver is programmed
to operate in HOLC mode to allow the transmitter to echo
received messages. Upon receipt of a particular bit pattern (actually a sequence of seven consecutive ones) the
transmitter breaks the loop and inserts its own frame(s).

Data Encoding
HOLC Mode. In this mode, the receiver recognizes flags,
performs optional address matching, accommodates extended address fields, 8- or 16-bit control fields and logical
control fields, performs zero deletion and CRC checking.
The receiver is capable of receiving shared-zero flags,
recognizes the abort sequence and can receive arbitrary
length messages. The transmitter automatically sends
opening and closing flags, performs zero insertion and is
programmed to send an abort, an extended abort, a flag
or CRC and a flag on transmit underrun. The transmitter
automatically sends the closing flag with optional CRC at
the end of a programmed message length. Shared-zero
flags are selected in the transmitter and a separate character
length is programmed for the last character in the frame.
Bisync Transparent Mode. In this mode, the synchronization pattern is OLE-SYN, programmable selected from
either ASCII or EBCDIC encoding. The receiver recognizes
control character sequences and automatically handles
CRC calculations without CPU intervention. The transmitter is programmed to send either SYN, OLE-SYN, CRCSYN, or CRC-OLE-SYN upon underrun and automatically
sends the closing OLE-SYN with optional CRC at the end
of a programmed message length.
NBIP Mode. This mode is identical to async except that the
receiver checks for the status of an additional addressl
data bit between the parity bit and the stop bit. The value
of this bit is FIFO'ed along with the data. In the transmitter,
this bit is automatically inserted with the value that is
FIFO'ed from the transmit data.
802.3 Mode. This mode implements the data format of
IEEE 802.3 with 16-bit address compare. In this mode,

The MUSC is programmed to encode and decode the
serial data in any of eight different ways (Figure 5). The
transmitter encoding method is selected independently of
the receiver decoding method.
NRZ. In NRZ, a 1 is represented by a High level for the
duration of the bit cell and a 0 is represented by a Low level
for the duration of the bit cell.
NRZB. NRZB is inverted from NRZ.
NRZI-Mark. In NRZI-Mark, a 1 is represented by a transition althe beginning of a bit cell, i.e., the level presentin tile
preceding bit cell is reversed. A 0 is represented by the
absence of a transition at the beginning of the bit cell.
NAZI-Space. In NRZI-Space, a1 is represented by the
absence of a transition at the beginning of a bit ceil; i.e., the
level present in the preceding bit cell is maintained. A 0 is
represented by a transition at the beginning of the bit cell.
Biphase-Mark. In'Biphase-Mark, a 1 is represented by a
transition at the beginning of. the bit ceil and another
transition at the center of the bit cell. A 0 is represented by
a transition at the beginning of the bit cell only.
Biphase-Space. In Biphase-Space, a 1 is represented by
transition at the beginning of the bit ceil only. A 0 is.
represented by a transition at the beginning of the bit cell
and another transition at the center of the bit cell.

Data
NRZ
NRZB

,
,
1
1
1

(

~
1

NRZI-S

1
1

(

NRZI-M

1
I'

BI-PHASE-M

i
BIPHASE-S

BIPHASE-l

DIFFERENTIAL
BIPHASE-L

Figure 5. Data Encoding

Biphase-Level. In Biphase-Level, a 1 is represented by a
High during the first half of the bit cell and a Low during the
second half of the bit cell. A 0 is represented by a Low
during the first half of the bit cell and a High during the
second half of the bit cell.
Differential Biphase-Level. In Differential Biphase-Level, a
1 is represented by a transition at the center of the bit cell,
with the opposite polarity from the transition at the center
of the preceding bit cell. A 0 is represented by a transition
at the center of the bit cell with the same polarity as the
transition at the center of the preceding bit cell. In both
cases, there are transitions at the beginning of the bit cell
to set up the level required to make the correct center
transition.

Character Counters
The MUSC contains a 16-bit character counter for both the
receiver and transmitter. The receive character counter
may be preset either under software control or automatically at the beginning of a receive message. The counter
decrements with each receive character and at the end of
the receive message the current value in the counter is
automatically loaded into a four-deep FIFO. This allows
DMA. transfer of data to proceed without CPU intervention
at the end of a received message, as the values in the FIFO
allow the CPU to determine message boundaries in memory.
Similarly, the transmit character counter is loaded either

under software control or automatically at the beginning of
a transmit message. The counter is decremented with
each write to ttie transmit FIFO. When the counter has
decremented to zero, and that byte is sent, the transmitter
automatically terminates the message in the appropriate
fasllion (usually CRC and the closing flag or sync character) without requiring CPU intervention.

Baud Rate Generators
The MUSC contains two baud rate generators. Eacll
generator consists of a 16-bittime constant register and a
16-bit down counter. In operation, the counter decrements
with each baud rate generator clock, and the time constant
is automatically reloaded when the count reaches zero.
The output of the baud rate generator toggles when the
counter reaches a count of one-half of the time constant
and again when the counter reaches zero. A new time
constant is written at any time but the new value does not
take effect until the next load of the counter. The outputs of
both baud rate generators are sent to the clock multiplexer
for use internally or externally. The baud rate generator
output frequency is related to the baud rate generator
input clock frequency by the following formula:
Output frequency

= Input frequency/(time constant + 1).

Note: This allows an output frequency in the range of 1 to
1/65536 of the input frequency, inclusive.

Digital Phase-Locked Loop
The MUSC contains a digital phase-locked loop (DPLL) to
recover clock information from data stream with NRZI or
Biphase encoding. The DPLL is driven by a clock that is
nominally 8, 16 or 32 times the receive data rate. The DPLL
uses this clock, along with the data stream, to construct a
clock for the data. This clock is routed to the receiver,
transmitter, or both, or to a pin for use extemally. In all
modes, the DPLL counts the input clock 10 create nominal
bit limes. As the cl()ck is counted, the DPLL watches the
incClming data stream for transitions. Whenever a transition
is detected, the DPLL makes p count adjustment (during
the next counting cycle), to produce an output clock which
tracks the incoming bit cells. The DPLL provides properly
phased transmit and receive clocks to the clock multiplexer.

Counters
The MUSC contains two 5-bit counters" which may be
programmed to divide an input clock by 4,8, 16 or 32. The

inputs of tllese two counters are sent to the clock multiplexer. the counters are used as prescalers for the baud
rate generators. They also provide a stable transmit clock
from a common source when the DPLL is providing the
receive clock. .

Clock Multiplexer
The clock multiplexer selects the clock source for the
various blocks in the channel, as well as selecting an
internal clock signal to potentially be sent to either the /RxC
or /TxC pin.
.

Test Modes
The MUSC is programmed for local loop back or auto echo
operation In Ibcalloopback, the output of the transmitter
is internally routed to the input of the receiver. Ttlis allows
testing of the MUSC data paths without any external logic.
Auto echo connects the RxD pin directly to the TxD pin.
ThiS is useful for testing serial links external to the MUSC.

1/0 INTERFACE CAPABILITIES
The MUSC offers the choice of polling, interrupt (vectored
or non-vectored) and block transfer modes to transfer
data, status and control information to ard from the CPU.

interrupt enable bits which are separately enabled. There
is a Master Interrupt Enable (MIE) bit which globally
enables or disables interrupts within the serial channel.

Polling

The other two bits are related to the interrupt priority chain.
The MUSC requests an interrupt only when no higher
priority interrupt source is requesting one, e.g., when lEI is
Higll for the channel. In this casE) the channel activates the
/INT signal. The CPU then responds with an interrupt
acknowledge cycle; and the device places a vector on tile
data bus.

All interrupts are disabled. The registers in the MUSC are
automatically updated to reflect current status. The CPU
polls the Daisy Ctlain Control Register (DCCR) to determine
status changes and then reads the appropriate status
register to find and respond to the change in status. MUSC
status bits are grouped according to function to simplify
this software action.

When a MUSC responds to an interrupt acknowledge from
the CPU, an interrupt vector may be placed on the data
bus. This vector is held in the Interrupt Vector Register
(IVR) To speed interrupt response time, tile MUSCmodifies
three bits in this vector to indicate which type of interrupt
is being requested.

In the MUSC, the IP bit signals that an interrupt request is
being serviced. If an IUS is set, all interrupt sources of
lower priority within the channel and external to the channel
are prevented from requesting interrupts'. The internal
interrupt sources are inhibited by the state of the internal
daisy chain, while lower priority devices are inhibited by
the lEO output of the channel being pulled Low and
propagated to subsequent peripherals. An IUS bit is set
during an interrupt acknowledge cycle if there are no
higher priority devices requesting interrupts.

Each of the six sources of interrupts in the MUSC (Receive,
Status, Receive Data, Transmit Status, Transmit Data, I/O
Status and Device Status) has tllree bits associated with
the interrupt source: Interrupt Pending (IP), Interrupt-UnderService (IUS) and Interrupt Enable (IE). If the IE bit for a
given source is set, then that source requests interrupts.
Note thatindivldual sources within the six groups also [lave

There are six sources of interrupt in the following priority.
Receive Status, Receive Data, Transmit Status, Transmit
Data, I/O Status and Device Status. There are six sources
of Receive Status interrupt. Each one is individually enabled'
receiver exited hunt, received idle line, received break/
abort, received code violation/end-of-transmission/endof-frame, parity error and overrun error The Receive Data

Interrupt

selects one or more lime slots within a frame, however, all
selected time slots must be contiguous. The first selected
time slot is programmable from slot 0 (the first slot) to slot
127 of the frame. The total number of concatenated slots
is programmable from 1 to 15 (total slots).

interrupt is generated whenever the receive FIFO fi,lIs with
data beyond the level programmed in the Receive Interrupt Control Register (RICR). There are six sources of
Transmit Status interrupt. Each one is individually enabled:
preamble sent, idle line sent, abort sent, end-of-frame/
end-of-transmission sent, CRC sent and underrun error.
The Transmit Data interrupt is generated whenever the
transmit FIFO empties below the level programmed in the
Transmit Interrupt Control Register (TICR). The I/O Status
interrupt serves to report transitions on any of six pins.
Interrupts are generated on either or both edges with
individual selection and enables for each pin. The pins that
are programmed to generate I/O Status interrupts are
/AxC, rrxc, IRxREQ, rrxREQ, /DCD and /CTS. These
interrupts are independent of the programmed function of
the pins. The Device Status interrupt has four individually
enabled sources: receive character count FIFO overflow,
DPLL sync acquired, BRG1 zero count and BRGO
zero count.

Block Transfer Mode
The MUSC accommodates block transfers via DMA through
the /RxREQ, rrxREQ, /AxACK and rrxACK pins. The
/RxREQ signal is activated when the fill level of the receive
FIFO exceeds the value programmed in the RICA. The
DMA responds with either a normal bus transaction or by
activating the /AxACK pin to read the data directly (fly-by
transfer). The rrxREQ signal is activated when the empty
level of the transmit FIFO falls below the value programmed
in the TICA. The DMA responds either with a normal bus
transaction or by activating the rr xACK pin to write the data
directly (fly-by transfer). The /RxACK and rrxACK pin
functions for this mode are controlled by the Hardware
Configuration Register (HCR) When using the /RxACK
and rrxACK pins to transfer data, no chip select is necess'ary; these are dedicated strobes for the
appropriate FIFO.

Time Slot Assigner
The MUSC is equipped with two time slot assigners to
support ISDN communications. There is one assigner for
the receiver and one assigner for the transmitter and the
assigners function independently. The time slot assigner

_ ..--."' .

~.-.--~-.

The time of the slot is offset an Integral number of clocks.
This offset is a delay and is programmable from
(no offset) to 7 clocks in increments of one clock (one bit
cell). This offset is used to compensate tor delays in frame
sync detection logic.

I/O Port

The Port pins are general purpose I/O pins. They are used
as additional MODEM control lines or other I/O functions.
Each port bit is' individually programmable for the threestate mode, output a logic 0, or output a logic 1 This
programming is done in the Port Control Register. When
programmed to be three-stated, the ports are used as
inputs. Whether used as inputs or outputs, the port pins
can be read at any time.
The port pins capture edge transition's input to the port.
This p(ogramming for the capture is done using the Port
Latched/Unlatch command bits in the Port Status Register.
Each port bit is individually controlled. The Latched/Unlatch
bit is used as a status signal to indicate that a transition has
occurred on the port pin and as a command to open the
latches that capture this transition Both rising edge and
failing edge transitions are detected. When a transition is
detected, the latch closes holding the post tran~ition state
of the input.
The Latched/Unlatch bit is held at 0 if no transitions occur
on the port pin; this bit is set to a 1 when rising edge or
falling edge transition is detected, or immediately after the
latch is opened if one or more transitions occurred while
the latch was closed. Writing a 0 to the Latched/Unlatch bit
has no effect on the latch. Writing a 1 to this bit resets the
status bit and opens the latch. To use the port as an input
without edge detection, a 1 would be written to the Latched/
Unlatch bit to open the latch and then the Port Status
Register would be read to obtain the current pin
input status.

PROGRAMMING
The Programmer's Assistant (MS DOS based) and Technical Manual are available to provide details about programming the MUSC. Also included are explanations and
features of all registers in the MUSC.
The registers in the MUSC must be programmed by the
system to configure the channel. Before this can occur, the
system must program the bus interface by writing to the
Bus Configuration Register (BCR). The BCR has no specific a'ddress and is only accessible immediately after a
hardware reset of the device. The first write to the MUSC,
after a hardware reset, programs the BCR. From that time
on the normal channel registers may be accessed. No
specific address need be presented to the MUSC for the
BCR write; the MUSC knows that the first Write after a
hardware reset is destined for the BCA.
In the multiplexed bus case, all registers are directly
addressable via the address latched by /AS at the beginning of a bus transaction. The address may be decoded
from either AD6 cADO or AD?-AD1. This is cont~olled by the
Shift Right/Shift Left bit in the BCR. The address maps for
these two cases is shown in Table 1. The D//C pin is still
used to directly access the receive and send data registers (RDR and TOR) in the multiplexed bus; if DIIC is High,
the address latctled by /AS is ignored and an access of
RDR or TOR is performed
Table 1. Multiplexed Bus Address Assignments

Address Signal

Shift Left

Shift Right

BytellWord Access
Address 4
Address 3

AD?
AD6
AD5

AD6
AD5
AD4

Address 2
Address 1
Address
UpperllLower Byte Select

AD4
AD3
AD2
AD1

AD3
AD2
AD1
. ADO

In the non-multiplexed bus case, the channel registers are
accessed indirectly using the address painter in the Channel Command/Address Register (CCAR). The address of
the desired register is first written to the CCAR and then the
selected register is accessed; the pointer in the CCAR is
automatically cleared after this access. Tile RDR and TOR
are still accessed directly using the DIIC pin, without
disturbing the contents of the painter in the CCAR.
There are two important things to note about the MUSC
First, the Channel Reset bit in the CCAR places the channel
in the reset state. To exit this reset state either a word at all
zeros is written to the CCAR (16-bit bus) or a byte of all
zeros is written to the lower byte of the CCAR (8-bit bus)
The second thing to note is that after reset, the transmit and
receive clocks are not connected. The first thing that
should be done in any initialization sequence is a write to
the Clock Mode Control Register (CMCR) to select a clock
source for the receiver and transmitter.
The register addreSSing is shown in Table 2 and the bit
assignm!3nts for the registers are shown in Figure 6.

Reset
Any Transaction
Up To and Including
BCRWrite

No lAS

At least One lAS

NonMuRiplexed
Bus

BCR
Write
Transaction

MURiplexed
Bus

I
BCR[2]=O
BCR[15]=1

~
8-Bit With
Separate
Address

BCR[2]=O
BCR[15]=O

BCR[2]=1

1
8-Bit Without
Separate
Address

BCR[2]=O
BCR[15]=1

16-Bit

8-BitWith
Separate
Address

BCR[2]=O
BCR[15]=O

BCR[2]=1

8-BitWithout
Separate
Address

16-Bit

Note:
The presence of one transaction with an / AS active, between reset up to

and including the BGR write, chooses a rrultiplexad type of bus.

Figure 6. BeR Reset Sequence and Bit Assignments

Table 2. Register Address List

Address
M-A0

00000
00001
00010
00011

CCAR
CMR
CCSR
CCR

Channel
Channel
Channel
Channel

00100
00101
00110
00111

PSR
PCR
TMDR
TMCR

01000
01001
01010
01011
01100
01101
01110
01111
1XOOO

Command/Address Register
Mode Register
Command/Status Register
Control Register

10001
10010
10011
10100

RMR
RCSR
RICR
RSR

Receive
Receive
Receive
Receive

Mode Register
Command/Status Register
Interrupt Control Register
Sync Register

Port Status Register
Port Control Register
Test Mode Data Register
Test Mode Control Register

10101
10110
10111
1XOOO

RCLR
RCCR
TCOR
TDR

Receive Count Limit Register
Receive Character Count Register
Time Constant 0 Register
Transmit Data Register (Write Only)

CMCR
HCR
IVR
IOCR

Clock Mode Control Register
Hardware Conf!guration Register
Interrupt Vector Register
I/O Control Register

11001
11010
11011
11100

TMR
TCSR
TICR
TSR

Transmit
Transmit
Transmit
Transmit

ICR
DCCR
MISR
SICR
RDR

Interrupt Control Register
Daisy-Chain Control Register
Misc Interrupt Status Register
Status Interrupt Control Register
Receive Data Register (Read Only)

11101
11110
11111

TCLR
TCCR
TC1R

Transmit Count limit Register
Transmit Character Count Register
Time Constant 1 Register

XXXXX

BCR

Bus Configuration Register

Mode Register
Command/Status Register
Interrupt Control Register
Sync Register

Address: 00000

Upper//lower Byte Select (WO)
Address 0 (WO)
Address 1 (WO)
Address 2 (WO)
Address 3 (Wof
Address 4 (WO)
Byte/lWoreI Access (WO)
DMA Continue (WO)

0
0
1
1

0
1
0
1

Normal Operation
}
Auto Echo
External Local Loopback
Internal Local Loopback

Mode
Control
Channel Reset

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
1
1
1
1
1
1 ,1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
6
0
1
1
0
1
1
1
1
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Null Command
RaS9fVed
Reset Highest IUS
Reserved
Trigger Channel Load DMA
Trigger Rx DMA
Trigger Tx DMA
Trigger Rx & Tx DMA
Reserved
Rx FIFO Purge
Tx FIFO P..-ge
Rx & Tx FIFO Purge
ReS9fVed
Reload Rx Character Count
Reload Tx Character Count
Reload Rx & Tx Character Count
Reserved
Load TCO
LoadTCl
Load TCO & TCl
Select Serial Data LSB First *
Select Serial Data MSB First
Select Straight Memory Oata *
Select Swapped Memory Data
Reserved
Reserved
Reserved
Raserved
RaS9fVed
Raserved
Rasorved
ReS9fVed

Channel
Command
(WO)

* Selected
Upon Reset

Figure 7. Channel Command/Address Register

Address: 00001

I I I I
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0

1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Asy nchronous
Extemal Synchronous
Isochronous
ASynchronous with CV
Monosync
Bisync
HO LC
Transparent Bisync
NBIP
802.3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Rx Submode 0
RxSubmode 1
Rx Submode 2
Rx Submode 3

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

.....,
Asynchronous
Reserved
Isochronous
Asynchronous with cv .
Monosync
Bisync
HOLC
Transparent Bisync
NBIP
802.3
Reserved

Transmitter
Mode

Reserved

Slaved Monosync
Reserved
HOLC Loop
Reserved

Tx Submode 0
Tx Submode 1
Tx Submode 2
Tx Submode 3

Figure 8. Channel Mode Register

Receiver

Mode

Address: 00001

IIII
0

0
0
1
1

0
1
0
1

Asy

16X Data Rate}
32X Data Rate
Rx Clock
64X Data Rate
Rate
Reserved
Reserved
Reserved

0
0

1
1

0
1
0
1

16X Data Rate }
32X Data Rate
64X Data Rate
Reserved

One Stop BH
}
Two Stop Bits
One Slop Bft. Shaved
Two Slop Bits. Shaved

Asynchronous }

Transmlner
Mode

Tx Clock
Rate

T~ Stop ,

Bits

Figure 9. Channel Mode Register, Asynchronous Mode

Addrass: 00001

1015101410131012101110101091 os 1071061051041 D311YZ 101 1DOl

Io I I I
0

Extemal Sync }
Reserved

000
Reserved

Figure 10. Channel Mode Register, External Sync Mode·

100

:iver

Address: 00001

-r--

I I I I

I
0

lsoch

ronous

IsochronouS} Receiver
Mode
Reserved

}

TransmiHer
Mode
Reserved
Tx Two Slop Bits
Reserved

Figure 11. Channel Mode Register, Isochronous Mode

Address: 00001

I II I
0

Asy nchronous wilh CV }

~:,~iver

Ax Extended Word
Reserved
0

Asynchronous with CV }

~:!",iller
CV Polarity

Tx Extended Word

o
o
1
1

0
1
0
1

One Slop Bit }
Two Slop Bit
No Slop Bit
Reserved

Tx
Slop Bils

Figure 12. Channel Mode Register, Asynchronous Mode
with Code Violation (MIL STO 1553)

101

Address: 00001

I I II I

-r--

Monosync} Receiver
Mode
Rx Short Sync Character
RxSync Strip
Reserved

nosync

}

Transmitter
Mode
Tx Short Sync Character
Tx Preamble Enable
Reserved

Ix CRC on Underrun
Figure 13. Channel Mode Register, Monosync Mode

Address: 00001

1015101410131012,10111010109108107

061D5 1 041 031 021 01 100J

I I I I
0

Bisy nc }

Receiver
Mode

Rx Short Sync Character
Rx SyncSlrip
Reserved

B'
}
,sync

TransrriHer
Mode
Tx Short Sync Character
Tx Preamble Enable

o
o
1
1

0
1
0
1

SYNl
}
SYNO/SYNl
CRC/SYNl
CRC/SYNO/SYNl

Tx
Underrun '
,.
Cond,Uon

Figure 14. Channel Mode Register, Bisync Mode

102

Address: 00001

Irn~rn~rn~rn~rnllrnolooloolwl~loolwlooloolrnlool

II II
0

0
0

0
1

HDLC} Receiver
Mode

Disabled
One Byte, No Control
One Byte, Plus Conlrol }
Extended, Plus Control

RxAddress
Search Mode

Rx 16·Bit Control
Rx logical Cootrol Enable

HDLC }

Transmitter
Mode
Shared Zero Flags
Tx Preamble Enable

1
1

0
1

Abort
}
Extended Abort
Flag
CRClAag

Tx
Underrun

Cond'.
I.on

Figure 15. Channel MOde Register, HOLC Mode

Address: 00001

IIII
0

Transparent BiSynC} Receiver
Mode
EBCDIC
Reserved

Transparent Bisync }

=:mitter
EBCDIC
Tx Preamble Enable

o o
o 1
o
1
1

SYN
OLEISYN
}
CRC/SYN
CRC/OLEISYN

Tx
Underrun

CondHion

Figure 16. Channel Mode Register, Transparent Bisync Mode

103

Address: 00001

I III
1

0
0
1
1

0
1
0
1

NBIP }

Receiver
Mode

16X Data Rate}
Rx Clock
32X Data Rate
64X Data Rate
Rat9
Reserved

Ax Parity on Data
Reserved

0
0
1
1

1
0
1

NBIP }

Transmitter
Mode

16X Data Rate}
32X Data Rate
Tx Clock
64X Data Rate
Rate
Reserved
, Tx Parity on Data
Tx Address Bit

Figure 17. Channel Mode Register, NBIP Mode

Address: 00001

1~~lrn~rn~rnllrn~ooloolmlmlool~lool~lrnlool

Receiver
Mode

Rx Address Search
Reserved

,
1

8023 }
.

Transnitter
Mode
Reserved
Tx CRC on Underrun

Figure 18. Channel Mode Register, 802.3 Mode

104

Address: 00001

I
1

II II
1

Reserved

Staved Monosync } =nitter
Tx Short Sync Character

Tx AcIIve on Received Sync

Reserved
Tx CRC on Undenun

Figure 19. Channel MOde Register, Slaved Monosync Mode

Address: 00001

I
1

II I I
1

Reserved} Receiver

Mode

Res...ved

HOLCLoop} Transnitter
Mode
Shared-Zero Flags
Tx Active on Poll

OOAbort
}
o 1 Extended Abort
1
0
Rag
1
1
CRCiFlag

,
Tx Underrun
Condition

Figure 20. Channel MOde Register, HOLC Loop Mode

105

Address: 00010

~
,

0
0
0
0

0
0

1
1

1
1
1

,~
8 Bits
1 en
2 Bits

4 Bits
5 Bits
6 Bits
7 Bits

IRxACK(ROj
fTxACK (ROj

}

HDLCTx Last
Character Length

Reserved
Loop Sending (ROj
On Loop (RO)

0
0

1
O.

Both Edges
Rising Edge Only
}
Falling Edge Only
Adjust/Sync Inhibn

DPLL Adjust/Sync Edge

Clock Missed Latched/Unlatch
Clocks Missed LatchedlUniatch
DPLL in SYl1c/Quick Sync
RCC FIFO Clear (WO)
RCC FIFO Valid (RO)
RCC FIFO Overflow (RO)

Figure 21. Channel Command/Status Register

106

Address: 00011

I
0
0
1
1

0
0
1
1

0
1
0
1

Reserved

Walt lor Ax DMA Trigger

No Status Block
}
One Word Status Block
TWO Word StaIu8 Block
Reserved

Ax S tatus
alock Transfer

..,
All Zeros
An Ones

}

Alternating 1 and 0
Alternaling 0 and 1

Tx Preamble
Patlem
I

0
0
1
1

0
1
0
1

n~ }

16 Bits
32 Bits
64Bns

Tx Shaved an Length
(Async Only)

(AU Sync)

Tx Preamble
Length

""
Reserved
Wall lor Tx DMA Trigger

0
1

1
1

0
1

No Status Block
}
One Word Status Block
Two Word Status Block
Reselved

Tx Status

Block Transfer

Figure 22. Channel Control Register

107

Address: 00100

IPort

Bit 0 (RO)

Port Bit 0 Latched/Unlatch

IPort Bit 1 (RO)
Port Bit 1 Latched/Unlatch

IPort Bit 2 (RO)
Port Bit 2 Latched/Unlatch

IPort Bit 3 (RO)
Port Bit 3 Latched/Unlatch

IPort Bit 4 (RO)
Port Bit 4 Latched/Unlatch

IPort Bit 5 (RO)
Port Bit 5 Latched/Unlatch
IPort Bit 6 (RO)
Port Bit 6 Latched/Unlatch
IPort Bit 7 (RO)
Port Bit 7 Latched/Unlatch

Figure 23. Port Status Register

108

Address: 00101

II
0
0
1
1
0
0
1
1
0
0
1
1

,
0
0
1
1
0
0
1
1

1
1

1
0
1

0
0

1
1

0
0

0
1
0
1

Output 0
Outpull

3-Slate OUtput
}
Frame Sync Input

OUtput 0
Output 1

3-Slate Output
}
Tx Complete OUtput
Output 0
Output 1

OUtput 0
OUtput 1

3-Slate
Reserv

OUtput 0
Output 1

3-Slate Output
}
Rx TSA Gate Output

Output 0
Output 1

3-Slate OUtput
}
Tx TSA Gate Output

3-Slate Output }
Reserved

OUtput 0
Output 1

3-Slate Output }
Reserved

Otdput 0
Output 1

3-Slate Output }
Rx Sync Output

0
1
0
1

Port Bit 0
Pin Control

Port Bit 1
PIn Control

Port Bit 2

Pin Control

Port BIt 3

Pin Control

Port Bit 4
Pin Control

Port Bit 5
Pin Control

Port BIt 6
Pin Control

Port Bit 7
Pin Control

Figure 24. pon Control Register

109

Address: 00110

1~51~41~31~21~II~olooJoolmloolool~lool~I~lool

Test Data <0>
Test Data <1>
Test Data <2>
Test Data <3>
Test Data <4>
Test Data <5>
Test Data <6>
, Test Data <7>
Test Data <8>
Test Data <9>
Test Data <10>
Test Data <11>
Test Data <12>
Test Data <13>
Test Data <14>
Test Data <15>

Figure 25. Test Mode Data Register

110

Address: 00111

1015101410131012101110101091081071061051041031021 011 DOl

I I I oI I
000
000
000
000

1 1
1
1
1
0
0
100
100
1
0
0
1
0
1
0 1
1
1
0
1
1
0 1
0
1
1
0
1
0
1
0
1 1
1
1
1
1
1 -1

Null Address

High Byte 01 Shifters
CFjC Byte 0
CRCBytel
Rx FIFO (Write)
Clock r.tJltiplexer OUtputs
CTRO and CTRI Counters
Clock Multiplexer Inputs
DPLLState
Low Byte 01 Shifters
CRC Byte 2
CRC Byte 3
Tx FIFO (Read)
Reserved
VO and Device Status Latches
Internal Daisy Chain
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Rx Count Holding Register'
Reserved
Resented
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

1
0
1
0

o 0 1 o
o 0 1 o
o 0 1 1
o 0 1 1
o 1 0 o
010 o
o 1 0 1
010 1
o 1 1 o
o 1 1 o
o
o

1
1

o
1
1

o
o
1

o
1
1

0
1
0
1

0
1
0
1
0
1
0
1
0
1
0

1
0
-1
0
1
0
1
0
1

Test
Register
Address

Reserved

Figure 26. Test Mode Control Register

•

111

Address: 01000

III
0
0
0
0
1
1
1
1
0

0
0

0
1
1
1
1
0
0
1
1

0
0
1
1
0
0

1
1
0
0
1
1

0
1
0
1

o o
o 1 Disa~ed
Disa~ed
1
o IRXC Pin
1

0
1
0
1

Dlsa~ed

}

0
1

ITxC Pin

CTROOulpUt
CTR10ulpUt }

0
1
1

0
1
0
1
0
1
0
1

}

0
1
0
1
0
1
0
1

Disabled
IRxC Pin
ITxC Pin
DPLl Output
BRGOOulpUt
BRG10u1pUt
CTAG Output
CTR10utput

BRGO Output }
BRG1 Output
/AXC Pin
ITxC Pin

CTROOuIpUt
CTR10ulpUt

IRxC Pin

IAxC Pin

Disa~ed

IRxC Pin
ITxC Pin
DPLLOutput
BRGOOulpUt }
BRG10u1pUt
CTAG Output
CTR10utput

Transmit Clock
}

DPLL Clock
Source

BRGOClock
Source

BRG1 Clock
Source

ITxC Pin

Dlsa~ed }
IRxC Pin
ITxC Pin

0
1
0
1

0
1

0
0
1
1
0

0
0
1
1
0
0
1
1

.
CTAG Clock
Source

CTRl Clock
Source

ITxC Pin

Figure 27. Clock Mode Control Register

112

Source

Receive Clock
Source

Address: 01001

BRGO Enable
BRGO Single CyclwConllnuous

o o
o 1
1
o
1

3-Stata OUtput
}
' Rx Acknowledge InpuI

OUtput 0
OUtput 1

IRxACK

Pin Control

BRG1 Enable
BRG1 Single Cycle/Continuous

o
o
1
1

o
o
1

o
o
1
1

0
1
0
1

~~%I

Biphase-Mark/Space

Biphase-Level

ITxACK

Pin Control

OUtput 0
OUtput 1

0
1
0

32>< Clock Mode }
16x Clock Mode
8x Clock Mode
Reserved

1
0
1

3-Stata Oulpul
}
Tx AcknowIedgelnpul

}

DPLL
Mode

DPLL Clock
Rate

AIlcepI Code Violations

CTR1 Rate MatCh DPWCTRO

o o
o
1
1

o
1

32x Clock Mode }
16x Clock Mode
8x Clock Mode
4x Clock Mode

CTRO Clock
Rate

Figure 28. Hardware Configuration Register

113

'I
Address: 01010

IV <2>
IV <3>

IV <5>

IV <1>

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Device Slalus

}

I/O Status
Transmft Data
Transmil Status
Receive Data
Receive Status
Not Used

IV (RO)

Modified
vector (RO)

IV <4> (RO)
IV <5> (RO)
IV (RO)
IV <1> (RO)

Figure 29. Interrupt Vector Register

114

Address: 01011

1015101410131012101110101091081071081 OSI 041 031 021011 001

I II

0
0
0
0
1

1
1
1
0
0
0
0
1
1
1
1

1
1

1
0
1

o
o
1
1

0
1
0
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

o
o

0
1

3·S1ate Output
}
Tx Request Output

0utpu1 0

0uIpu11

0
1
0

1
0
1
0
1

}

Rx Clock Output
Ax Byte Clock Output
SYNC Output
BRGO OU1pUt
BRG10utpu1
CTRO Output
DPlL Ax 0uIpu1

}

Tx Clock 0utpu1
Tx Byte Clock 0utpuI
Tx Complete OU1pUt
BRGO Output
BRG10U1pUt
CTR10utpu1
DPLL Tx Output

Tx Data OU1pUt }
3·State outpui
0utpu1 0
0uIpu11

}
3·Slale Output
Rx Request Outpu1
Outpu1 0
0uIpu11

0
0
1
1
0
0
1
1

IRxC Pin

Control

!TxC
Pin Conlrol

TxD Pin

Conlrol

IRxREQ

PIn Control

ITxREQ
Pin Control

~1 0~ ~~/~~NC
Input} lOCO
Output 0
Pin Control
1

o o
o 1
1
o
1

0utpu11

ICTS Input
ICTS Inpu1
}
Output 0
0utpu11

ICTS
Pin Control

Figure 30. I/O Control Register

115

Address: 01100

Device Status IE
110 Status IE
Transmit Data IE
Transmit Status IE
Receive Data IE
Receive Status IE

0
0
1
1

0
1
0
1

Nun Command
Null Command
Reset IE
set IE

}

IE Command
(WO)

Reserved

0
0
0
0
1
1
1
1

0
0
1

1
0
0

1
1

0
1
0
1
0
1
0
1

All

liO Status and Above
Transmit Data and Above
Transmit Status and Above
Receive Data and Above
Receive Status Only
None
"

:J.

VIS
Level

VIS
NV

DLC
MIE

Figure 31. Interrupt Control Register

116

Address: 01101

Device sIaIUS IP

va Status IP
Trarismh Dala IP

Transmh status If'
Receive Data IP
Receive SIaIUS If'

0
0
1
1

0
1
0
1

tUCommam }
ResetlP em IUS
f\es8tlP
SelIP

IPCommem

~O)'

Device Sta\US IUS

va Stalus IUS
Tl'8n8mh Dala IUS
Tl'8n8mft $latus IUS

Receive Data IUS
Receive Sta\US IUS
o
o
1
1

0
1
0
1

Null Commem }
Null Commem
ResetlUS
Set IUS

,
IUS eo",mand
,

~O)

Figure 32.

Dal~y-Chain

Control Register

117

Address: 01110

ID1SI014101SI0!210lllD10J 09 J001071061051041 J02·1 Ql 1 J..
OS

• BflGO ZC LalchediUniatch
BRG1.ZC LalchedlUnlalch
DPLL SYNC LaIched'Unialch
RCC Overflow LalchedlUnialch

ICTS (RO)

lers Lalched/Unlalch

IDCD(RO)
IDCD Lalched/Unlalch
ITxREQ(RO)
ITxREQ LatChedlUnialch
IRxREQ(RO)
IRxREQ LalchedlUnlalch '
ITxC(RO)
ITxC Lalched/Unlalch
IRxC(RO)
IRxC Latched/Unlalch

Figure 33. Miscellaneous Interrupt Status Register

118

Address: 01111

BRGOZCIE
BRGl ZCIE
DPLLSYNCIE

Rce Overflow IE

o
o
1
1

o o
o 1
o
1
1

o
o
1
1

o
1

0
1
0
1

1
0
1

1
1

0
1

Disabled
}
Rising Edge Only
Failing Edge Only
Both Edges

Disabled
}
Rising Edge Only
Falling Edge Only
Both Edges

Disabled
}
Rising Edge Only
Falling Edge Only
Both Edges
.

Disabled
}
Rising Edge Only ,
Falling Edge Only
Both Edges

Disabled
}
Rising Edge Only
Falling Edge Only
Both Edges

o
o

ICTS
Interrupts

IDCD
Interrupts

ITxREO
Interrupts

IRxREO
Inlerrupts

ITxC
Interrupts

IRxC
Interrupts

Figure 34. Status Interrupt Control Register

119

Address: 1xOOO

RxDAT <0> (RO)
RxDAT <1>,(RO)
RxDAT <2> (RO)
RxDAT <3> (RO)
RxDAT <4> (RO)
RxDAT <5> (RO)
RxDAT <6> (RO)
RxDAT <7> (RO)
RxDAT <8> (RO)
RxDAT <9> (RO)
RxDAT <10> (RO)
'FixDAT <11> (RO)

RxDAT <12> (RO)
RxDAT <13> (RO)

RxDAT <14> (RO)
RxDAT <15> (RO)

Figure 35. Receive Data Register

I·

120

Address: 10001

II
0
0
0
0

0
0
1

1
1
1
1

0
0

1
1

0
1

0
1
0
1
0
1

0
0

1
1

8 BIts
1811
2 BIts
3 BIts

4 BIts
5 Bits
6Bita
7Bits

01sabia Immediately
}
Disable After Reception
Enable Wilhoul Auto-Enables
Enable With Auto-Enables

Ax
Enabla

}

Rx Character

Length

Rx Parity Enable

0
0

1
1

~n}

Space
Mark

Rx Parity
Sensa

Reserved
Rx CRC Enabla
Ax CRC Preset Value
0
0
1
1

'0
0

1
1

O·
1
1
1
1

0
0
0
1
1

0
1
0
1

CRC-CCllT }
CRC-16
CRC-32
Reserved

NRZ
NRZB
NRZI-Mark
NRZI'Space
Biphasa-Mark
Biphasa-Space
Biphasa-Lavel
oiH. Biphasa-Lavel

AxCRC
Polynomial

}

Rx ~ata
Decoding

Figure 36. Receive Mode Register

121

Address: 10010

Im5Im~m3Im~mllm~ooloolwlooIMI~looloolml~1

Rx Charecter Available (RO)
RxOVerrun
Parity Error
CRC/Franing Error (RO)
Rx CVIEOT/EOF
Rx Break/Abort
Rx Idle
Exited Hunt

Short Frame/CV Polarity (RQ)
Residue Code 0 (RO)
Residue Code 1 (AO)
Residue Code 2 (AO)

I, 1 1 1
0
0
0
0
0
0
0
0

0
0
0
0

0
0

1
1

1
1
1

0, 0
0
1
1 0

1
1
1

0
0

1
1

0
0
0
0

1
1
1

0
0

1
1

1
1
1
1

Null Command
"'\
Reserved
PresetCRC
Enter Hunt Mode
Select TImeslot Assignmenl
Select FIFO Status
Select FIFO Interrupt Level
Select FIFO Aequest Level
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
.,)

Receive
Comrnand (WO)

First Byte in Error (RO)
Second Byte in Error (RO)

Figure 37. Receive Command Status Register

122

Address: 10011

101510141013101201110101091 osi 071 061 osl 041031 021 011 001

TCOR Read CountITC
Rx Overrun IE
Parity Errer IE

Status on Words

R. CVIEOT/EOF IE
Rx BreakiAborlIE
Rx Idle IE
Exiled Hunt IE
Rx FIFO Control and Status
(F1IVk)Ierrupt/DMA Level)

Figure 38a. Receive Interrupt Control Register

Address: 10011

I0151~I01~012I011I010109loslml06ID61041001~I01I001

TCOR Read CountITC
Rx Overrun IE
Parily Error IE

Status on Words
Rx CV/EOTIEOF IE
Rx,BreaklAborlIE

Rx Idle IE
Exiled Hunt IE

o
limeslot (0-127)

Figure 38b. Receive Interrupt Control Register

123

Address: 10011
1015J01410131012101110101 091

osl

071 061051 D4

031021011001

TCOR Read CountlTC
Rx Overrun IE
Parity Error IE
Status on Words
Rx CV/EOT/EOF IE
Rx Break/Abort IE
Rx Idle IE
Exited Hunl IE

1 (WO)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

o
o
o
o
1
1
1
1

o o
o 1
1
1

1
1

o o
o 1
1

0
0
0
0

1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

No Offset
7 Clocks Offset
6 'Clocks Offset
5 Clocks Offset
4 Clocks Offset }
3 Clocks Offset
2 Clocks Offset
1 Clock Offset

No Slot (Oisabled) ""'\
1 Slot
2 Slots
3 Slots
4 Slots
5 Slots
6 Slots
7 Slots
SSlots
9 Slots
10 Slots
11 Slots
12 Slots
13 Slots
14 Slots
15 Slots

Concatenated
Slots (WO)

Slot Offset
rNO)

Figure 3Bc. Receive Interrupt Control Register

124

Address: 10100

RSYN
RSYN <1>
RSYN <2>
RSYN<3>
RSYN<4>
RSYN<5>
RSYN<6>
RSYN <7>
RSYN<8>
RSYN<9>
RSYN <10>
RSYN <11>
RSYN <12>
RSYN <13>
RSYN <14>
RSYN <15>

Figure 39. Receive Sync Register

125

Address: 1,0101

RCL<1>
RCL<2>
RCL<3>
RCL<4>
RCL<5>
RCL <6>

RCL<8>
RCL<9>
RCL<10>
RCL<11>
RCL <12>
RCL <13>
RCL <14>
RCL<15>

Figure 40. Receive Count Limit Register

126

Address:

10110

~~~m~m2Im1Im~ooloolmloolool~loolmlmlooJ

RCC (RO)
RCC<1> (RO)
RCC<2> (RO)
RCC<3> (RO)
RCC<4> (RO)
RCC<5> (RO)
RCC<6> (RO)
RCC<7> (RO)

RCC <8> (RO)
RCC<9> (RO)
RCC <10> (RO)
RCC <11> (RO)
RCC <12> (RO)
RCC <13> (RO)
RCC <14> (RO)
RCC <15> (RO)

Figure 41. Receive Character Count Register

127

Address: 10111

TCO
TCO <1>
TCO<2>
TCO<3>

TCO<6>
TCO<7>
TCO<8>
TCO<9>
TCO<10>

TCO
TCO<13>
TCO<14>
TCO<15>

Flqure 42. Time Constant 0 Register

128

Address: 1xOOO
!

TxDAT <0> (WO)
TxDAT <1> (WO)
TxDAT <2> (WO)
TxDAT <3> (WO)
TxDAT <4> (WO)
TxDAT <5> (WO)
TxDAT <6> (WO)
TxDAT <7> (WO)
TxDAT <8> (WO)
TxDAT <9> (WO)
TxDAT <10> (WO)
TxDAT <11> (WO)
TxDAT <12> (WO)
TxDAT <13> (WO)

TxDAT <14> (WO)
TxDAT <15> (WO)

Figure 43. Transmit Data Register

129

Address: 11001

I I
0
0
1
1
0
0
0
0
1
1
1
1

0
0

1
1

0
0
1
1

0
1
0
1
0
1
0
1

0
1
0
1

8 Bits'
1 BH
2 Bits
3 Bits
4 Bits
5 Bits
6 Bits
7BHs

Dis able Immediately
}
Disable After Transmission
Enable Without Auto-Enables
Enable With Auto-Enables

x Character
ength

Tx Parity Enable

0
0
1
1

0
1
0
1

Even

~ce

}

Tx Parity
Sense

Mark

Tx CRC on EOF/EOM
Tx CRC Enable

.
0
0
1
1

o o o
o o 1
o 1 o
o
1
1
1
1

0
1
0
1

CRC-CCITT }
CRC-16
CRC-32
Reserved

NAZ
NRZB
NAZI-Mark
NAZI-Space
Biphase-Mark
Biphase-Space
Biphase-Level
Dill. Biphase-Level

TxCRC
Polynomial

}

Tx Data
Encoding

Figure 44. Transmit Mode Register

130

Tx CRC Preset Value

Tx
Enable

Address: 11010

Tx Buner Empty (RO)
Tx Underrun
AI Sent (RO)
TxCRCSent
Tx EOF/EOT Sent
Tx Abort Sent
Tx leIe Sent

0
0
0
1

1
1
1

0
0
1
1
0

0
1

0
1
0
1
0
1
0

~--.

Alternating 1 and 0
All Zeros
All Ones
Reserved
Alternating Marl< and Space
Space
Marl<

}

Tx Preamble Sent

Tx klle U ne
Condition

Reserved
0
0
0
0
0

0
0
0
0
1

0
0

1
1

0
1
1
1
1
1

1
1

0
0
0

0
1
1

1
1

0
0

1
1
0

1
0
1
0

1
1

0
0
1
1
0

0
1
1

1
0
1
0
1
0
1
0
1

Nul Command
Reserved
PresetCRC
Reserved
Select TImestot Assignment
Select FIFO Status
Select Interrupt level
Select Request Level
Send FramelMessage
Send Abort
Reserved
Reserved
Reset OLE Inhibit
Set OLE Inhibit
Reset EOF/EOM
Set EOFIEOM

TransmH
Command (WO)

Figure 45. Transmit Command/Status Register

131

Address:

11Q11
TC1R Read CountITC
Tx Overrun IE
WaH lor Send Command
Tx CRC Sen1IE
Tx EOFIEOT Senl IE

TX Abort Sen1IE
Tx Idle SenIlE
Tx Preamble

Sen1IE

Tx FIFO Conlrol and Status

(FilVlnlerruptlOMA Level)

Flgure'46a. Transmit Interrupt Control Register

Address:

11011

~+~m~m~m1Im~oojooj~I~lool~loolmlmlool

TC1R Read CountITC
Tx Underrun

Wall lor Send Command
Tx CRC Sen1IE
Tx EOFIEOT SenIlE
Tx Abort SenIlE
Tx Ille Sen1IE
Tx Preamble SenIlE

o
Tomeslol(Q-127)

Figure 46b. Transmit Interrupt Control Register

Address: 11011

TCI R Read CountfTC
Tx Undeirun IE
Wail for Send Command
Tx CRC SenIlE
Tx EOFJEOT SenIlE
Tx Abort Sent IE
Tx Idle SenIlE
Tx Preamble Senl IE
1 (WO)

0
0
0
0
0
()

0
0
1
1
1
1
1
1
1
1

o o
o o 1

o
o

1
1
1
1

1
1

o o
o 1
1
o

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

NoOHset
7 Clocks Offset
6 Clocks Offset
5 Clocks Offset
4 Clocks Offset }
3 Clocks Offset
2 Clocks Offset
1 Clock Offsel

No Slol (Disabled)
1 Slol
2SIols
3SIols
4 Slots
5SIols
6SIols
7 Slols
8SIols
9 Slols
10SIols
11 Slols
12 SlolS
13 Slols
14 SlolS
15 Slots

Concalenaled
Slols (WO)

SlolOffsel
(WO)

Figure 46c. Transmit Interrupt Control Register

133

Address: 11100

~~~lm3Im~mllmol~I~I~lool~I~I~I~lmlool'

TSYN
TSYN<1>
TSYN<2>
TSYN<3>
TSYN<4>

TSYN<6>

TSYN<8>
I

TSYN-;9>
TSYN<10>
TSYN <11>
TSYN,<12>
TSYN,,13>
TSYN<14>
TSYN<15>

Figure 47. Transmit Sync Register

134

Address: 11101

TCl
TCl<1>
TCl <2>
TCl<3>
TCl <4>
TCl <5>
Tel <6>
TCl <7>
TCl <8>
TCl <9>
TCl<10>
TCl <11>
TCl <12>
TCl <13>
TCl <14>
TCl <15>

Figure 48. Transmit Count Limit Register

135

Address: 11110

TCC <0> (RO)
TCC<1> (RO)
TCC <2> (RO)
TCC <3> (RO)
TCC<4> (RO)
TCC <5> (RO)
TCC <6> (RO)
TCC <7> (RO)
TCC<8> (RO)
TCC <9> (RO)
TCC <10> (RO)
TCe <11> (RO)
TCC <12> (RO)
TCC <13> (RO)
TCC <14> (RO)
TCC <15> (RO)

Figure 49. Transmit Character Count Register

136

• Address: 11111

1~~m3Im~m11~~oolool~loolool~loolmlmlool

Te1 <0>
Te1 <1>
Te1 <2>
Te1 <3>
Tel <4>
Tel <5>
Tel <7>
Tel <8>
Tel <9>
Tel <10>
Tel <11>
Tel <12>
Tel <13>
Tel <14>
Tel <15>

Figure 50. Time Constant 1 Register

137

......

~~~~

.~--".-.".""

.. .... ..-.""".
"

. "'~I

.I.~ "." '", ..m~'~"""""'-

, - ___

Add!:ess; None

Rx OVerrun
Parity Error
CRCError

Rx CVlEOT/EOF

o
o

o
Short Frame/CV Polarity
Residue Code 0
Residue Code 1
Residue Code 2

o
o
First Byte in Error
Second Byte in Error

Refer to Figure 22 (Chamel Control Register)
Btts 6-7 for Access Method

Figure 51. Receive Status Block Register

138

Address: None

III~
,~
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0

1
0
1
0
1

8Bi'a

1 Bi.

2 Bils

Reserved

}

HDLCTx L$SI

4 Bils
5 Bits
6 Bits
7 Bils

Character Length

Reserved
Tx Submode 0
Tx Submode 1
Tx Submode 2
TxSubmode3

Reier 10 Figure 22 (Chamei Control Regis.er)
Bi1s15-14lor Access Method

Figure 52. Transmit Status Block Register

139
__

~,,'

_ _,

"' ...............

"'T-~-,_~

___

_ _ ._ .......... - - - . . - ....

- ..J"

Address: None

10151014101310121011 0101 091 081 071 061 051 041 031 021 ~11 00 1
Shift Righi Addresses
Oouble-Pulse INTACK
IS-Bit Bus

0*
Reserved
3-State AU Pins
Separate Address for 8-Bit Bus

* Must be programmed as zero.
Figure 53. Bus Configuration Register

MUSCTIMING
The MUSC interface timing is similar to that found on a
static RAM, except that it is much more flexible Up to eight
separate timing strobe signals are present on the interface: IDS, IRD, IWR, IPITACK, IRxACKA, IRxACKB,
/TxACKA and /TxACKB. Only one of these timing strobes
may be active at any time. Should the external logic

activate more than one of these strobes at ttle same time
the MUSC will enter a pre-reset state. 1his state is only
exited by a hardware reset. Do not allow overlap of timing
strobes. The timing diagrams, beginning on the next page,
illustrate the different bus transactions possible, with the
necessary setup, hold and delay times.

ABSOLUTE MAXIMUM RATINGS
Voltages on all pins '
with respect to Vss .................................. -0.3 V to +7.0 V
Voltages on all inputs
with respect to Vss ............................ -O.3V to Vcc +0.3V
Operating Ambient
Temperature ............................ See Ordering Information
Storage Temperature ............................. -65°C to + 150°C

140

Stresses greater than those listed Under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections of these specifications is not implied. Exposure to
absoiute maximum rating conditions for extended periods
may affect device reliability.

STANDARD TEST CONDITIONS

+5V

The DC Characteristics and Capacitance section below
apply for the following standard test conditions, unless
otherwise noted: All voltages are referenced to GND
Positive current'flows into the referenced pin. Standard
conditions are as follows:

From 0UIput
Under Test

+4.5 V < Vee < +5.5 V
GND=OV
TA as specified in Ordering Information

o----1............t - - - D -.....
50pF

Figure 54. Standard Test Load

CAPACITANCE
Symbol

Parameter

Min

Input Capacitance
Output Capacitance
Bidirectional Capacitance

Max

Unit

10
15

pF
pF
pF

Condition
Unmeasured Pins
Returned to Ground

Nole:
f= 1 MHz, over specified temperature range. Unmeasured pins returned to ground.

MISCELLANEOUS Transistor Count -100,000

DC CHARACTERISTICS
Z16C33
Symbol Parameter
VH
V..
VOH 1
VOH2

Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage

VOl
III.
101.
Icc 1

Output Low Voltage
Input Leakage
Output Leakage
Vcc Supply Current

Min

Typ

2.2
-0.3
2.4
Vee-0.8

Max

Unit

Vee +0.3
0.8

0.4
+10.00
+10.00
50

!1A
!1A

Condition
V
V
IOH= -1.6mA
IOH= -250 !1A
V
101.= +2.0mA
0.4 < VIN < +2.4V
0.4 < Vour < +2.4V
mA V~=5V VIH=4.8V V'L = 0.2V

Nole:
Vor: 5V ± 10% unless otherwise specified, over specified temperature range.

_ 141

AC CHARACTERISTICS
Z16C33
1 No
Symbol
Parameter
I

1
2
3

Min

Max

Units

Tcyc
TwASI
TwASh
TwDSI

Bus Cycle Time
lAS Low Width
lAS High Width
IDS Low Width

160
40
90
70

ns
ns
ns
ns

5
6
7
8

TwDSh
TdAS(DS)
TdDS(AS)
TdDS(DRa)

IDS High Width
lAS Rise to IDS Fall Delay Time
IDS Rise to lA's Fall Delay Time
IDS Fall to Data Active Delay

60
5
5
0

ns
ns
ns
ns

9
10
11
12

TdDS(DRv)
TdDS(DRn)
TdDS(DRz)
TsCS(AS)

IDS
IDS
IDS
ICS

13
14
15
16

ThCS(AS)
TsADD(AS)
ThADD(AS)
TsSIA(AS)

ICS to lAS RiSe Hold Time .

17
18
19
20
21
22
23
24

85
15

ns
ns
ns
ns

Direct Address to lAS Rise Setup Time
Direct Address to lAS Rise Hold Time
lSI TACK to lAS Rise Setup Time

0
15
5
15

ns
ns
ns
ns

ThSIA(AS)
TsAD(AS)
ThAD(AS)
TsRW(DS)

ISITACK to lAS Rise Hold Time
Address to lAS Rise Setup Time
Address to lAS Rise Hold Time
R//W to IDS Fall Setup Time

5
15
5
0

Th~IW(DS)

TsDSf(Rf1Q)
TdDSr(RRQ)
lsDW(DS)

R//W to IDS Fall Hold Time
IDS Fall to IRxREG) Inactive Delay
IDS Rise to IRxREQ Active Delay
Write Data to IDS Rise Setup Time

25
26
27
28

ThDW(DS)
ldDSf(TRQ)
TdDSr(TRQ)
TwRDI

Write Data to DS Rise Hold Time
IDS Fall to ITxREQ Inactive Delay
IDS Rise to /TxREQ Active Delay
IRD Low Width

0
70

ns
ns
ns
ns

29
30
31
32

TwRDh
TdAS(RD)
TdRD(AS)
rdRD(DRa)

IRD High Width
lAS Rise to IRD Fall Delay Time
IRD Rise to lAS Fall Delay Time
IRD Fall to Data Active Delay

60
5
5
0

ns
ns
ns
ns

33
34
35
36

TdRD(DRv)
TdRD(DRn)
TdRD(DRz)
TdRDf(RRQ)

IRD
IRD
IRD
IRD

37
38
39
40

TdRDr(RRQ)
TwWRI
TwWRh
TdAS(WR)

IRD Rise to IRxllEQ Active Delay
IWR Low Width
IWR Higll Width
lAS Rise to IWH Fall Delay Time

0
70
60
5

ns
ns
ns
ns

41
42
43
44

TdWR(AS)
TsDW(WR)
ThDW(Wn)
TdWnt(TRQ)

/WR Hise to lAS Fall Delay Time
Write Data to /WR Hise Setup Time
Write Data to IWR Rise Hold Time
IWR Fall to {TxREQ Inactive Delay

5
30
0

ns
ns
ns
ns

142

Fall to Data Valid Delay
Rise to Data Not Valid Delay
Rise to Data Float Delay
to lAS Rise Setup Time

Fall to Data Valid Delay
Rise to Data Not Valid Delay
Rise to Data Float Delay
Fall to IRxREQ Inactive Delay

0
20

Note

[1 J
[1 J

------ns
ns
ns
ns

60
0
30
0
65

85
0
20
60

ns
ns
ns
ns

[4J

[5J

[4J

[5J

AC CHARACTERISTICS
Z16C33
No

Symbol

Parameter

Min

45
46
47
48

TdWRr(TRQ)
TsCS(DS)
ThCS(DS)
TsADD(DS)

/WR Rise to ITxREQ Active Delay

ICS to IDS Fall Setup Time
ICS to IDS Fall Hold lime
Direct Address to IDS Fall Setup Time

49
50
51
52

ThADD(DS)
TsSIA(DS)
ThSIA(DS)
TsCS(RD)

53
54
55
56
57
58
59

Units

Note

0
0
25
5

ns
ns
ns
ns

[2]
[2]
[1,2]

Direct Address to IDS Fall Hold Time·
ISIT ACK to IDS Fall Setup time
ISITACK to IDS Fall Hold Time
ICS to IRD Fall Setup Time

25
5
25
0

ns
ns
ns
ns

[1,2]
12J
[2]
[2]

ThCS(RD)
TsADD(RD)
ThADD(RD)
TsSIA(RD)

ICS to IRD Fall Hold Time
Direct Address to IRD Fall Setup Time
Direct Address to IRD Fall Hold Time
ISITACK to/RD Fall Setup Time

25
5
25
5·

ns
ns
ns
ns

[2]
[1,2)
[1,2)
[2]

ISIT ACK to IRD Fall Hold Time
ICS to /WR Fall Setup Time
ICS to /WR Fall Hold Time

ThSIA(RD)
TsCS(WR)
ThCS(WR)
TsADD(WR)

Direct Address to /Wil Fall Setup Time

25
0
25
5

ns
ns
ns
ns

[2]
[2]
[2)
[1,2)

61
62
63
64

ThADD(WR)
TsSIA(WR)
ThSIA(WR)
TwRAKI

Direct Address to /WFl Fall Hold Time
ISITACK to/WR Fall Setup Time.
ISIT ACK tb /WR Fall ~ laid Time
IRxACK Low Width

25
5
25
70

ns·
ns
ns
ns

[1,2]
[2)
[2]

65
66
67
68

TwRAKh
TdRAK(DRa)
TdRAK(DRv)
TdRAK(DRn)

IRxACK
IRxACK
IRxACK
IRxACK

ns
ns
ns
ns

69
70
71
72

TdRAK(DRz)
TdRAKf(RRQ)
TdRAKr(RRQ)
TwTAKI

JRxACK Rise to Data Float Delay
IRxACK Fall t9/RxREQ Inactive Delay
IRxACK Rise to IRxREQ Active Delay
/TxACK Low Width

73
74
75
76

TwTAKh
TsDW(TAK)
ThDW(TAK)
TdTAKf(TRQ)

ITxACK High Width
Write Data to /TxACK Rise Setup Time
Write Data to /TxACK Rise Hold Time
/TxACK Fall to /TxREQ Inactive Delay

30
0

/TxACK Rise to /TxREQ Active Delay

TdTAKr(TRQ)
TdDSf(RDY)
TdRDY(DRv)
TdDSr(RDY)

IDS Fall (Intack) to IRDY Fall Delay
IRDY Fall to.oata Valid Delay
IDS Rise to IRDY Rise Delay

81
82
83
84

TsIEI(DSI)
ThIEI(DSI)
TdIEI(IEO)
TdAS(IEO)

lEI to IDS Fall (Intack) Setup Time
lEI to IDS Rise (Intack) Hold Time
lEI to lEO Delay
lAS Rise (Intack) to lEa Delay /

85
86
87
88

TdDSI(INT)
IdDSI(Wf)
TdDSI(Wr)
TdW(DRv)

IDS Fall to liNT Inactive Delay
IDS Fall (Intack) to /WAIT Fall Delay
IDS Fall (Intack) to/WAIT Rise Delay

200
40

/WAIT Rise to Data Valid Delay

78
79

High Width
Fall to Data Active Delay
Fall to Data Valid Delay
Rise to Data Not Valid Delay

Max

0
85
0
20
60

0
70
60
65
200

40
40
60

0
60
60

200

ns
ns
ns
ns
ns
ns
ns
ns

[4]

[5)

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns '
ns
ns

143

AC CHARACTERISTICS
Z16C33
No

Symbol

Parameter

89
91
92

TdRDf(RDY)
TdRDr(RDY)
TsIEI(RDI)
ThIEI(RDI)

IRD Fall (Intack) to IRDY Fall Delay
IRD Rise to IRDY Rise Delay
lEI to IRD Fall (In tack) Setup Time
lEI to IRD Rise (Intack) Hold Time

93
94
95
96

TdRDI(INT)
TdRDI(Wf)
'rdRDI(Wr)
TwPIAI

IRD Fall (Intack) to liNT Inactive Delay
IRD Fall (Intack) to /WAIT Fall Delay
IRD Fall (Intack) to /WAIT Rise Delay

97
98
99
100

TwPIAh
TdAS(PIA)
TdPIA(AS)
TdPIA(DRa)

IPI1ACK Fall to Data Active Delay

101
102
103
104

TdPIA(DRn)
TdPIA(DRz)
TsIEI(PIA)
ThIEI(PIA)

IPITACK Rise to Data Not Valid Delay
IPIT ACK Rise to Data Float Delay
lEI to IPITACK Fall Setup Time
lEI to IPITACK Rise Hold Time

105
106
107
108

TdPIA(IEO)
TdPIA(INT)
TdPIAf(RDY)
TdPIAr(RDY)

IPITACK Fall to lEO Delay
IPITACK Fall to liNT Inactive Delay
IPITACK Fall to IRDY Fall Delay
IPITACK Rise to IRDY Rise Delay

60
200
200
40

ns
ns
ns
ns

109
110
111
112

TdPIA(Wf)
TdPIA(Wr)
TdSIA(INT)
TwSTBh

IPITACK Fall to /WAIT Fall Delay
IPITACK Fall to /WAIT Rise Delay
lSI TACK Fall to lEO Inactive Delay
/Strobe High Width

40
200
200

ns
ns
ns
ns

113
114
115
116

TwRESI
TwRESh
TdRES(STB)
TdDSf(RDY)

IRE SET Low Width
IRESET High Width
IRESET Rise to ISTB Fall
IDS Fall to IRDY Fall Delay

117
118
119
120

TdWRf(RDY)
TdWRr(RDY)
TdRDf(RDY)
TdRAKf(RDY)

121
122
123

TdRAKr(RDY)
TdTAKf(RDY)
TdTAKr(RDY)

Max

Units

200
40

ns
ns
ns
ns

200
40
200

60
0

IPITACK Low Width

ns
ns
ns
ns

IPITACK High Width

60
5
5
0

ns
ns
ns
ns

lAS Rise to IPITACK rail Delay Time
IPITACK Rise to lAS Fall Delay Time

0'
20
60
0

60
170
60
60

Note

ns
ns
ns
ns

IWR Fall to IRDY Fall Delay
IWR Rise to IRDY Rise Delay
IRD Fall to IRpy Faill)elay
IRxACK Fall to IRDY Fall Delay

50
40
50
50

ns
ns
ns
ns

IRxACK riise to IRDY Rise Delay
ITxACK Fall to IRDY Fall Delay
ITxACK Rise to IRDY Rise Delay

40
50
40

ns
ns
ns

Noles:
[1] Direct address is any of PS, DIIC or ADI5-AD8 used as an address bus.
[2] The parameter applies only when lAS is not present.
[3] Strobe (lST9) is any of IDS, IRD, /WR, tpITACK, /RxACK or /TxACK.
[4] Parameter applies only if read empties the receive FIFO.
[5] Parameter applies only if write fills the transmit FIFO.

144

Min

[2]
[3]

[3]

IRESET

t·1

~
~

ISTB
115

Figure 55. Reset Timing

ISTB

tl-----(-CDH--t~
(
~~-----------------------~CD~----~.J
Figure 56. Bus Cycle Timing

Note:

ISlB is any of the following: IDS, /RD, /WR, /pITACK,/RxACK, or /TxACK.

IRxACK
~--------~~~--------~ ~------~~r-----~

ADO-AD15

IRxREQ

IWAITIIRDY
(Wait)

IWAITIIRDY
(Ready)

Figure 57. DMA Read Cycle

145

ITxAqK

t
-5

)

AOO-A015

ITxREQ

J
~.

/wAIT/fROY
(Walt)

/wAIT/fROY

(Ready)

J
22

Figure 58. DMA Write Cycle

146

rof-®-

)

ICS

@--f-

)

PS,DIIC

@-I-

-®

)

ISITACK

@-flAS

HD=

~-@3
1

)

RlIW

@-- --@
~

IDS

J
~

foo~

@-f- -f-@ foo-@-

IRxREQ

.. -®--

IWAITIIRDY
(Walt)

IWAITIIRDY
(Ready)

)

ADO·AD15

)
116

--®--

Figure 59. Multiplexed IDS Read Cycle

147

)

ICS

)

PS,DIIC

@-~

fSlTACK

@-~

--,

lAS

f---®-

RlIW

®+-

~r.:

IDS

ADO-AD15

@--

IWAIT/IADY
(Walt)

IWAITIIRDY
(Ready)

--@-

)
16

Figure 60. Multiplexed IDS Write Cycle

148

-®-

fTxREQ

[(

--®-

ICS

@--

PS,DIIC

@--

ISITACK

®-flAS

-@)

I-&-- f-®IRD

31
1

\
28

)

ADQ-AD15

@-r-

31[

:-~4 ~

IRxREQ

~
~-®-

-®
IWAITflRDY
(Wait)

IWAITflRDY
(Ready)

.J
J

j
119

---®-

Figure 61. Multiplexed IRD Read Cycle

149

ICS

@-I-

\)l

PS,DIIC

@--I-

ISITACK

@--IlAS

~I\

I=®== HorIWR

ADO-AD15

41
1

'
"
lK

-@
IWAITIIRDY
(Wait)

IWAITIIRDY
(Ready)

--.I
--.I

+-@J

117

Figure 62. Multiplexed IWR Write Cycle

150

ITxREQ

~
39

f-@-

ICS

@--

)

PS.D/IC

®--

ISITACK

@--

-®

f\.

RlIW

@--

IDS

)

ADO-AD15

foo~

. r-=®-

IRxREQ

r-f-@-

-@-IWAIT~/RDY

(Walt)

IWAITIIRDY
(Ready)

I
--@

f--®-

Figure 63. Non-Mu!tlplexed IDS Read Cycle

151

)

ICS

@-'--

)

PS,DIIC

@-,-

ISITACK

~
-®

@-RlIW

IDS

\...
5

)

ADO-AD15

-®-- --®-

)

ITxREQ

f---®IWAITIIRDY
(Wait)

IWAITIIRDY
(Ready)

h!H
Figure 64. Non-Multiplexed IDS Write Cycle

152

-®-

lOS

@---

PS.O/IC

®--

ISITAOK

®--

IRO

29
1

ADO-A015

IRxREQ

IWAITIIROY

--./

(Ready)

f--.@

IWAITIIROY
(Wait)

~-®-

I
79

f-®-

Figure 65. Non-Multiplexed IRD Read Cycle

153

)

/CS

.®--

)

PS,DIIC

®-~

ISITACK

®--

"Il:

/wR
38

)

ADO-AD15

)
-@--

J
f-®-

ITxREQ

/wAITIIRDY
(Wail)

/wAIT//RDY
(Ready)

J
J

J\
foo~
!

I
~

Figure 66. Non-Multiplexed twA Write Cycle

154

lAS

ISITACK

IDS

ADO-AD 15

/wAITIIADY
(Wait)

/WAIT/lADY
(Ready)

11:1

lEO

liNT

Figure 67. Multiplexed IDS Interrupt Acknowledge Cycle

155
- - - -_ _ _ _ _ _
••

'.~'

__M_"_
..

+~H ..."....,.~~"

- _ _ •• "

lAS

ISITACK

IRO

AOO-A015

IWAITI/ROY
(Wail)

IWAITI/ROY
(Ready)

lEI

lEO

liNT

Figure 68. Muitilllexed IRD Interrupt Acknowledge Cycle

156

,--------

lAS

IPITACK

ADO-AD15

IWAITIIRDY
(Walt)

IWAITIIRDY
(Ready)

lEI

lEO

liNT

Figure 69. Multiplexed Pulsed Interrupt Acknowledge Cycle

157

ISITACK

IDS

ADO-AD1S

IWAITIIRDY
(Wail)

IWAITIIRDY
(Ready)

lEI

lEO

liNT

Figure 70. Non-Multiplexed IDS Interrupt Acknowledge Cycle

158

ISITACK

lAD

ADO-AD15

IWAITIlROV
(Walt)

IWAITIIRDV
(Ready)

lEI

lEO

liNT

Figure 71. Non-Multiplexed IRD Pulsed Interrupt Acknowledge Cycle

159

IPITACK
~--------400~------~~

ADO-AD15
......-----6tool-----Cf----

\_-CQ

\ ___r

--\_-h1kA"'--~\----r

---------------~
------------------~~------------------Figure 75. Z16C33

General Timing

163

AC CHARACTERISTICS
Z16C33 General Timing
No

Symbol'

Parameter

1
2
3
4

TsRxO(RxCr)
ThRxO(RxCr)
TsRxd(RxCf)
ThRxO(RxCf)

RxO
RxO
RxO
RxO

5
6
7

TsSy(RxC)
ThSy(RxC)
TdTxCf(TxO)
TdTxCr(TxO)

lOCO as ISYNC to IRxC Rise Setup Time
lOCO as ISYNC to IRxC Rise Hold Time (x1 Mode)
/TxC Fall to TxO Delay
ITxC Rise to TxO Delay

10
11
12

TwRxCh
TwRxCI
TcRxC
TwTxCh

IRxC High Width
IRxC Low Width
IRxC Cycle Time
ITxC High Width

40
40
100
40

ns
ns
ns
ns

13
14
15
16

TwTxCI
TcTxC
TwExT
TWSY

/TxC Low Width
/TxC Cycle Time
lOCO or ICTS Pulse Widlh
lOCO as ISYNC Input Pulse Width

40
100
70
70

ns
ns
ns
ns

8
9

164

to IRxC
to IRxC
to IRxC
to /RxC

Min
Rise Setup Time (x1 Mode)
Rise Hold Time (xl Mode)
Fall Setup Time (x1 Mode)
Fall Hold Time (x1 Mode)

Max

Units

Note

0
40
0
40

ns
ns
ns
ns

[1,3]
[1,3)

ns
ns
ns
ns

[ 1]
[1]
[2]
[2,3]

40
50
50

[1 )

IRxC,lTxC
Receive

IRxREO
Request

IRxC as
Receiver
Output

liNT

IRxC,lTxC
Transmit

ITxREO

ITxCas
Transmitter
Output

liNT

ICTS, lOCO,

ITxREO,
IRxREO

__________~lK~----------------------

liNT

Figure 76. Z16C33 System Timing

165

AC CHARACTERISTICS
Z16C33 System Timing
No

Symbol "

Parameter

1
2

TdRxC(REO)
TdRxC(RxC)
TdRxC(INT)
TdTxC(REQ)

IRxC Rise to JRxREQ Valid Delay
ITxC Rise to IRxC as Receiver Output Valid Delay
/AxC Rise to liNT Valid Delay

TdTxC(TxC)
TdTxC(INT)
TdEXT(INT)

IRxC Fall to /TxC as transmitter Output Valid Delay
/TxC Fall to liNT Valid Delay
ICTS, lOCO, /TxREQ, IRxREQ transition
to liNT Valid Delay

3
4

5
6
7

/TxC Fall to /TxREQ Valid Delay

NOles:
\
[I] /AxC is/AxC or {TxC, whichever is supplying the receive clock.
[2] {TxC Is (TxC or /AxC, whichever is supplying the transmit clock.
[3] Parameter applies only to FM encoding/decoding

166

Min

Max

Units

100

ns
nl?
ns
ns

[2J
[21
[2J
, l2J

100

ns
ns

[2)

100

ns'

100

100
100
100

Note

~ZiI.m

PRELIMINARY PRODUCT SPECIFICATION

Z16C35
CMOS ISCCTM INTEGRATED SERIAL
COMMUNICATIONS CONTROLLER
FEATURES

•
•

•
•
•
•

•
•
•

Sup'ports all Zilog CMOS SCC features:
Low power CMOS technology
Two general-purpose SCC channels, four OMA
channel; and a Universal Bus Interface Unit.
Software compatible to the Zilog CMOS SCC
Four OMA channels; two transmit and two receive
channels to and from the SCC.
Four gigabyte address range per OMA channel

•

Programmable OMA channel priorities

32-bit addresses multiplexed to 16-pin address/data
lines

•

8-bit data supporting high/low byte swapping
10 and 16 MHz timing
68-pin PLCC

Multi-protocol operation under program control;
programmable for NRZ, NRZI, or FM data encoding.
Asynchronous mode with five to eight' bits and one,
one and one-half, or two stop bits per character;
programmable clock factor; break detection and
generation; parity, overrun, and framing error detection.

•

Synchronous mode with internal or external character
synchronization on one or two synchronous characters
and CRC generation and checking with CRC-16 or
CRC-CCITT preset to either 1's or O's.

Independent OMA register set
A Universal Bus Interface Unit providing a simple
interface to most CPUs with a multiplexed or nonmultiplexed bus; compatible with 680xO and 8x86
CPUs.

Two independent, 0 to 4.0 Mbit/second, full-duplex
channels, each with a separate crystal oscillator, baud
rate generator, and digital phase-locked loop circuit
for clock recovery.

••

Flyby OMA transfer mode

•
•
•

•

SOLC/HOLC mode with comprehensive frame-level
control, automatic zero insertion and deletion, I-field
residue handling, abort generation and detection,
CRC generation and checking, and SOLC Loop mode
. operation.

•

Local Loopback and Auto Echo modes

•

Supports T1 digital trunk

•

Enhanced SOLC 10x19 Status FIFO for OMA support

•

Full CMOS SCC register set

GENERAL OESCRIPTION
The Z16C35 ISCC is a CMOS superlntegrated device with
a flexible Bus Interface Unit (BIU) connecting a built-in
Oirect Memory Access (OMA) cell to. the CMOS Serial
Communications Control (SCC) cell.
The ISCC is a dual-channel, multi-protocol data communications peripheral which easily interfaces to CPU's with

either multiplexed or non-multiplexed address and data
buses. The advanced CMOS process offers lower power
consumption, higher performance, and superior noise
immunity. The programming flexibility of the internal registers allow the ISCC to be configur\'ld for a wide variety of
serial communications applications. The many on-chip
features such as, streamlined bus interface, four channel

167

GENERAL DESCRIPTION (Continued)
DMA, baud rate generators, digital phase-locked loops,
and crystal oscillators dramatically reduce the need for
external logic. Additional features, including 10x19 bit
status FIFO, are added to support high speed SDLC
transfers using on-chip DMA controllers (Figure 1).

. The DMA cell consists of four DMA chaRnels; one far
transmit and one for receive to,and fr'Offl each SCC channel,
respectively. The cycle time for each DMA transfer is 400
ns for the 10 MHz version, There is no idle cycle between
DMA transfers.
.

The ISCC can ad(:lress up to four gigabytes per DMA
channel by using the IUAS and /AS signalS to strobe out
32-bit multiplexed addresses.

The DMA cell adopts a simple fly-by mode DMA transfer,
allowing easy programming of the DMA cell and yet
providing a powerful and efficient DMA access. The cell
does not support memory-ta-memory transfer.

The ISCC handles asynchronous formats, syn~hronous
byte-oriented protocols such as' IBM Bisync, and synchronous bit-oriented protocols such as HDLC and IBM
SDLC. This versatile device supports vi.rtually any serial
data transfer application (terminals, printers, diskette, tape
drives, etc.).
The device can generate and check CRC codes in any:
synchronous mode and can be programmed to check
data integrityin various modes. The ISCC also has faCilities
for modem controls in both channels. In applications
where these controls are not needed, the modem controls
can be used for general-purpose I/O.
The standard Zilog interrupt daisy chain is supported for
interrupt hierachy control. Internally, the SCC cell has
higher interrupt priority than the DMA cell.

Priorities between the four DMA channels are programmable to custom-fit user applications. Arbitration at Bus'
priority control signals between the ISCC DMkand other
system DMA's should be handled outside the ISCC.
The BI U has a universal interface to most system/CPU bus
structures and timing. ThG first write to the ISCC after a
hardware reset will confirm the bus interface type being
implemented.
Note: All Signals with a preceding front slash, "/", are active
Low, e.g.: BIIW (WORD is active Low); IBIW (BYTE is
active Low, only); INIIS (NORMAL and SYSTEM are both
active Low).

---------------------------I
I
I
I

lEI
I
I
I
I

liNT
Control Signals

AOl5-AOO

I
I
I
I
I
I
A

<.
I
I
I
I
I
I
I
I
I
I
I

lEO

r-,.

Control Signals

...

...
lEO

)
lEI

liNT

I
I
I

Request

t t

AOl5-A08

..
I
I
I
I

4 ChannelOMA
I
I

IBUSACK

...
...

I
I
I

l..-

lEO

I
I
I

__________________________ J

Figure 1. Block Diagram

ChannelB

168

Channel A

SCC

AD7-ADO
8'
I
U

lEI

. liNT

IBUSREQ

lEO
lINT
/SYNCA
mTxCA
GND
Vee
ADO
ADI
AD2

ADS

AD4

IBUSREO
PClK
/SYNCS

IRTxCB
GND
Vee
ADa

ISCC
Z16C35
(Top View)

AD5
ADa
AD7

GND
Vee
nc

AD9
AD10
ADll
AD12
AD13
AD14
AD15
GND
Vee
nc

Figure 2. Pin Assignments

PIN DESCRIPTION
The following section describes the Z16e35 pin functions.
Figures 2 details the respective pin functIons and pIn
assignments. All references to OMA are internal.

IOTRA,/OTRB. Data Termmal R~ady(outputs, active Low).
These outputs follow the state programmed into the
OTR bit.

ICTSA,/CTSB. Clear To Send(inputs, active Low). If th~se
pins are programmed as AutoEnables, a Low on the inputs
enables the respective transmitters. If not programmed as·
Auto Enables, they may be used as general-purpose
inputs. Both inputs are Schmitt-trigger buffered to accommodate slow rise-time inputs. The sec cell detects
pulses on these inputs and can interrupt the CPU on both
logic level transitions.

lEI. Interrupt Enable In (input. .active High). lEI is used with'
lEO to form an interrupt daisy chain when there is more
than one interrupt driven device. A high lEI indicates that
no other higher prioriiy device has an interrupt under
service or is requesting an interrupt. The sec cell has a
higher interrupt priority than the OMA cell.

IOCOA, IDCOB. Data Carrier Detect (inputs, active Low).
These pins function as receiver enables if they are programmed for Auto Enables; otherwise they are used as
general-purpose input pins. Both pins are Schmitt-trigger
buffered to accommodate slow rise time ,signals. The sec
cell detects pulses on these pins and can interruptthe CPU
on both logic level transitions.

lEO. Interrupt Enable Out(output, active High) lEO is High
only if lEI is High and the CPU is not servicing the Isec
(SeC or OMA) interrupt, or the Isee is not requesting an
interrupt (Interrupt Acknowledge cycle only). lEO is connected to the next lower priority device's lEI input and thus
inhibits interrupts from lower priority devices.
liNT. Interrupt(outpul, active Low). This signal is activated
when the sec or OMA requests an interrupt. Note that/INT
is pulled high and is not an open-drain output.

,,"

• 1\ ' .~\

M,,' ,

· PIN !lESCRIPTION (Continued)
IINTACK. Interrupt Acknowledge (input, active Low) This
is a strobe which indicates that an interrupt acknowledge
cycle is in progress. During this cycle, the SCC and DMA
, interrupt daisy chain is resolved. The device is capable of
returning an interrupt vector lt1at may be encoded with the
type of interrupt pending during thts acknowledge cycle
when RDor DS become high. INTACK may be programmed
to accept a status acknowledge, a single pulse acknowledge, or a double pulse acknowledge. This is programmed
in the Bus Configuration Register (BCR). The double pulse
acknowledge is compatible with 8x86 family microprocessors.
PCLK. Clock (input). This· is the master SCC and DMA
clock used to synchronize internal signals. PCLK is a TTL
level signal. PCLK is not required to have any phase
relationship with the master system clock.
RxOA, RxOB. Receive Data (inputs, active High). These
input signals receive serial data at standard TTL levels.
IRTxCA, IRTxCB: R.eceive/Transmlt Clocks (inputs, active
Low). These pins can be programmed to several modes of
operation. In each channel. RTxC may supply the receive
clock. the transmit clock. the clock for the baud rate
generator, or the clock lor the Digital Phase-Locked Loop.
These pins can also be programmed for use 'with the
respective SYNC pins as a crystal oscillator. The receive
clock may be 1, 16, 32. or 64 times the data. rate in
asynchronous modes.
IRTSA,/RTSB. Request To Send (outputs, active low)
When the Request To Send (RTS) bit in Write Register 5 is
set. the RTS signal goes Low. When the RTS bit is reset in
the Asynchronous mode and Auto Enable is on, the signal
goes High after the transmitter is empty. In Synchronous
mode or in Asynchronous mode with Auto Enable oil, the
RTS pin strictly follows the state of the RTS bit Both pins
can be used as general-purpose outputs.

In the Internal Synchronization mode (Monosync and
Bisync) with the crystal oscillator not selected, these pins
act as outputs and are active only during the part of the
receive crock cycle in which synchronous condition is not
latched These outputs are active each time a synchronization pattern is recognized (regardless of character
boundaries). In SDLC mode, the pins act as outputs and
are valid on receipt of a flag.
TxOA, TxOB. Transmit Data (outputs, active high). These
output signals transmit serial data at standard TT L levels.
ITRxCA,ffRxCB. Transmit/Receive Clocks (inputs or
outputs, active Low). These pins can be programmed in
several different modes of operation. TRxC may supply the
receive clock or the transmil clock in the input mode or
supply the output of the Digital Phase,Locked Loop. the
crystal oscillator. the baud rate generator. or the transmit.
clock in the output mode.
ICE. Chip Enable (input. active Low) This signal selects
the ISCC for a peripheral read or write operation. This
signal is not used when the ISCC is bus master.
A015-AOO. Da1a bus (bidirectional, 3-state). These lines
carry data and commands to and from the ISCC.
IRO. Read (bidirectional, active Low). When the ISCC is a
peripheral (Le. bus slave), this signal indicates a. read
operation and when the ISCC is selected. enables the
ISCC's bus drivers. As an input, IRD indicates that the CPU
wants to read from the ISCC read registers. Dunng the
Interrupt Acknowledge cycle, IRD gates the interrupt vector
onto the bus if the ISCC is the highest priority device
requesting an interrupt When the ISCC is the bus master, .
this signal is used to read data. As an oUtput. after the Isec
has taken control of the system buses. IRD indicates a
pMA-controlled read from a memory or 1/0 port address.

twA. Write (bidirectional. active Low) When the Isec is
ISYNCA, /sYNCB. Synchronization (inputs or .outputs.
active Low). These pins can act either as inputs. outputs.
or part of the crystal osqillator circuit. In the Asynchronous
Receive mode (crystal oscillator option· not selected).
these pins are inputs similar to CTS and DCD. In this mode.
transitions on these lines affect the state of the Synchronous!
Hunt status bits in Read Register 0 but have no other
function.
In External Synchronization mode with the crystal oscillator
not selected. these lines also act as inputs. In this mode.
SYNC must be driven Low to receive clock cycles aftm the
last bit in the synchronous character is received Character
assembly begins on the rising edge of the receive clock
Immediately preceding the activation of SYNC.

170

selected, this signal indicates a write operation As an
input. this indicates that the epu wants to write control or
command bytes to the Isec write registers. As an output,
after the ISCC has taken control of the system buses /WR
indicates a DMA-contrplled write to a memory or I/O port
address.
IDS. Data Strobe (bidirectional. active Low). A Low on thiS
signal indicates that the AD15-ADO bus is used for data
transfer. When the ISCC is riot in control of the system bus
and the external system is transferring information to or
from the ISCC. IDS is a timing input used by the Isec to
move data to or from the AD 15-ADO bus Data is written into
the ISCC by the extemal system on the low to High IDS
tranSition. Data is read from the ISCC by the external

system while IDS is Low There are no timing requirements
between IDS as an input and ISCC clock, this allows use
of the ISCC with a system bus wtlich does not have a
bussed clock.
During a DMA operation when the ISCC is in control of the
system, OS is an output generated by the ISCC and used
by the system to move data to or from the AD15-ADO bus
When the ISCC has bus control, it' writes to the external
systern by placing data on the AD15-ADO bus before the
High-to-Low OS transition and holds the data stable until
after the Low-to-High OS transition; while reading from the
external system, the Low-to-High transition of OS inputs
data from the AD15-ADO bus into the ISCC.

RlfW. Read/Write(bidirectional) Read polarity is High and
write polarity is Low. When the ISCC is bus master, R//W
indicates the data direction of the current bus transaction,
and is stable from when AS IS High until the bus transaction
ends When the ISCC is not In cO(ltrol of the system bus and
the external system is transferring information to or from
the ISCC, R//W is a status input used by the ISCC to
determine if data is entering or leaving on the AD15-ADO
bus during IDS time. In such a case, Read (High) indicates
that the system is requesting data from the ISCC and Write
(Low) indicates that the system is presenting data to the
ISCC. The only timing reqUirements for R//W ~s an input are
defined relative to DS When the ISCC is in control of the
system bus, R//W is an output generated by the ISCC, with
Read indicating that data is being requested from the
addressed location or device, and Write indicating that
data is being presented to the addressed location or
deVice.
IUAS, Upper Address Strobe (Output, active Low) This
signal is used if the address is more than 16-bit The upper
address, A31-A16, can be latched externally by the rising
edge of this signal. IUAS is active first before AS becomes
active. This signal and AS are used by the Dty1A cell
lAS. Lower Address Strobe (Bidirectional, active Low)
When the ISCC is bus master, this signal wh~n an output,
is used as a lower address strobe for AD 15-ADO It is used
In conjunction with UAS since the address IS 32-blts ThiS
signal and IUAS are used by the DMA cell when it is bus
master. When ISCC is not bus master, this signal is used
in the multiplexed bus modes to latch the address on the
AD lines. The lAS signal is not used in the non-multiplexed
bus modes and should be tied to Vcc in these cases.
IWAITI/RDY. Wait/Ready(bidirectional, active Low) It may
be programmed to function either as a Wait signal or
Ready Signal during the BCR write When the BCR is
written to Channel A (A 1/A//B High during the BCR write),
this Signal functions as a WAIT and thus supports the
READY function of 8X86 microprocessors family Wilen

the BCR writes to Channel R iA 1/N/B Low), ttllS signal
functions as a READY and supports the 0 rACK function of
the 680XO microprocessor family,
ThiS signal is an output when the ISCC in not bus master
In this case, the Wait/RDY signal Indicates wilen tile data.
is available during a read cycle, when the device is ready
to receive data dUring a write cycle; and when a valid
vector is available dUring an interrupt acknowledge cycle.
When the ISCC is the bus master (the DMA cell has taken
control of the bus), the IWait//RDY Signal functions as a
WAIT or READY Input. Slow memories and peripheral '
devices can assertWAI T to extend IDS during bus transfers
Similarly, memories and peripherals use READY to indicate
that its output is valid or that it is ready to latcil input data.
IBUSACK. Bus Acknowledge (input, active Low) Signals
the bus has been released to the DMA If the IBUSACK is
inactive before the DMA transfer is completed, the current
DMA transfer is aborted.
IBUSREQ. Bus Request(output, active Low) This Signal is
used by the DMA to obtain the bus from the CPU
AO/SCCI/DMA. OMA Channel/SCC Select/OMA Select
(bidirectional) When this pin is used as input, a high
selects the SCC cell and a low selects the DMA cell When
this pin is used as output, the signal on this pin IS used in
conjunction with A 11MB pin output to identify which DMA
channel is active This information can be used by the user
to determine whether to Issue a DMA abort command
AO/SCC/IDMA and A1/AI/B output encoding is
shown below

A1/A/IB

AO/SCCIIDMA

DMAchannel

1
1

RxA
TxA
RxB
TxB

o
o

A 1IA/IB. OMA Channel/Channel AlChannel B (bidirectional) This Signal, when used as input, selects the SCC
channel in which the read and write operation occurs Note
that AO/SCC//DMA pin must be held high to select this
feature. When thiS pin is used as an output, It is used in
conjunction with the AO/SCC//DMA pin output to identify
which DMA channel is active During a DMA peripheral
access, the A 1/N/B pin IS ignored.
IRESET. (input, active Low) ThiS Signal resets the deVice
to a known state 1 he first write to the ISCC after a reset
accesses the BCR to select additional bus options for the
device.

171

-~---'-"--"-----~-.'~

FUNCTIONAL DESCRIPTION
The functional capabilities of the Isee are described in
three blocks: the sec cell, the DMA cell, and Ule Bus
Interface Unit (BIU). Each of the blocks are described
independently in the following sections with the Isee

architecture shown in Figure 3. Please refer to the Isee
Technical Manual for a detailed description of the functions outlined 11ere.

DMA
}

Serial Data

} Channel Clocks

'--__-r--

ISYNC
/Wait

} Modem, DMA,
or Other
Controls

AOO-AD15
Control

Modem, DMA,
} or Other
Controls

}

111

'--_ _...r--

Serial Data

} Channel Clocks
ISync
/Wail

+5VGND PCU<

Figure 3. Block Diagra!JI of ISCC Architecture

SCC Cell Data Communications Capabilities. The Isee
provides two independent full-duplex programmable
channels for use in any common asyncllro'l0US or synchronous data communications protocol. fhe Isee is built
from Zilog's industry standard sec core and is comp8llble
with designs using Zilog's sec to receive and transmit
data (Figure 4).
Asynchronous Modes. Send and Receive can be accomplished independently on each channel with five to eight
bits per character, plus optional even or odd parity. The
transmitters can supply one, one-and-a-half, or two stop
bits per character and can provide a break output at any
time. The receiver break-detection logic interrupts the
CPU both at the start and at the end of a received break.
Reception is protected from spikes by a transient spikerejection mechanism that checks the Signal one-Ilalf a bit
time after a Low level is detected on the receive data input
(RxDA or RxDB in Figure 2). If the Low does not persist
(e.g., a transient), the character assembly process does
not start.
Framing errors and overrun errors are detected and buffered
together with the partial charilcter on Wllich they occur.

172

Vectored interrupts allow fast servicing or error conditions
using dedicated routines. Furttlermore, a built-in checking
process avoids the interpretation of a framing error as a
new start bit: a framing error results in the addition of onehalf a bit time to the point at which the search for tile next
start bit begins.
The Isee does not require symmetric transmit and receive
clock signals - a feature allowing use or tile wide variety of
crock sources. The transmitter and receiver can handle
data at a rate supplied to the receive and transmit clock
inputs. In Asynchronous modes, the SYNC pin may be
programmed as an input used for functions such as
monitoring a ring indicator.

Synchronous Modes. The Isee supports both byte-oriented and bit-oriented synchronous communication.
Synchronous byte-oriented protocols can be handled in
several modes, allowing character synchronization with a
6-bit or 8-bit synchronous character (Monosync), and 12bit synchronization pattern (Bisync), or with an external
synchronous signal Leading sync characters can be
removed without interrupting the CPU.

ToOlhar
Channel

TxD

Generator
Input

TranSlmt
Clock
RxD

DPLL

~~~f@
(O.cUlato~

SYNC

Figure 4.

Isee Data Path

_veClock
Transmit Clock
OPlLClock
BR Generator Clock

FUNCTIONAL DESCRIPTION (Continued)
Five or 7-bit synchronous characters are detected with
8- or 16-bit patterns in the ISCC by overlapping the larger

pattern across multiple incoming synchronous characters
as shown in Figure 5. .

SBKs

ISYNC

SYNcl

"-....--...

SYNC

DATA

.---..".)

Y
16

Figure 5. Detecting 5- or 7-Bit Synchronous Characters

CRC checking for Synchronous byte oriented modes i;;
delayed by one character time so that the CPU may
disable CRC checking on specific characters. This permits
the implementation of protocols such as IBM Bisync
Both CRC-16 (X16 + X15 + X2 + 1) and CCITT (X16 + X12
+ X5 + 1) error checking polynomials are supported. FHher
polynomial may be selected in all Synchronous modes.
Users may preset the CRC generator and checker to all 1's
or all O's. The ISCC also provides a feature that automatically
transmits CRC data when no other data is available for
transmission. This allows for high speed transmissions
under OMA control, with no need for CPU intervention at
the end of a message. When there is no data or CRC to
send in Synchronous modes, the transmitter inserts
6-, 8-, or 16-bit synchronous characters, regardless of the
programmed character length.
The ISCC supports Synchronous bit~oriented protocols,
such as SOLC and HOLC, by performing automatic flag
sending, zero insertion, and CRC generation. A special
command is used to abort a frame in transmission At the
end of a message, the ISCC automatically transmits the
CRC and trailing flag when the transmitter underruns The
transmitter may also be programmed to send an idle line
consisting of continuous flag characters or a steady marking
condition.

The receiver automatically acquires synchronization on
the leading flag of a frame in SOLC or HOLC and provides
a synchronization signal on the SYNC pin (an interrupt can
also be programmed). The receiver can be programmed
to search for frames addressed by a sll1gle byte (or four
bits within a byte) of a user-selected address or to a' gLobal
broadcast address. In this mode, frames not matching
either the user-selected or broadcast address are ignored.
The number ot address bytes can be extended under
software control. For receiving data, an interrupt on the first
received character, or an interrupt on every character, or
on special condition only (end-of-frame) can be selected
The receiver automatically deletes all O's inserted by the
transmitter during character assembly. CRC is also calculated and is automatically ctlecked to validate frame
transmission. At the end of transmission, the status of a
received frame is available in the status registers. In SOLC
mode, the ISCC must be programmed to use the SOLe
eRe polynomial, but the generator and checker. may be
preset to all l's or all O's. The CRC is inverted before
transmission and the receiver checks against the bit pattern 0001110100001111.
NRZ, NRZI orFM coding maybe used in any 1xmode. The
parity options available in Asynchronous modes are
available in Synchronous modes:

SOlC Loop Mode. The Isee supports SOLC Loop mode
If a transmit underrun occurs in the middle of a message,
an external/status interrupt warns the CPU of this status
change so that an abort may be issued. The ISCC may also
be programmed to send an abort itself in case of an
underrun, relieving the CPU of this task. One to eight bits
per character can be sent, allowing reception of a message
with no prior information about the character structure in
the information field of a frame.

174

in addition to normal SOLe. In an SOLG Loop, there is a
primary controller station that manages tile message traffic
flow on the loop and any number of secondary stations In
SOLC Loop mode, tile Isce performs the functions of a
secondary station wtlile an Isec operating in regular
SOLe mode acts as a controller (Figure 6).

and 5 status/error bits are stored. The byte count and
status bits are accessed through Read Registers 6 and 7.
Read Registers are only accessible when the SDLC FIFO
is enabled. The 10x19 status FIFO is separate from the 3
byte receive data FIFO.
Notes on the SOLC FIFO. When using the SDLC FIFO
enhancment in channel B, it is necessary to enable the
enhancment in channel A. There is no special requirement
to enable the enhancement in channel A only, or to use it
in both channels. DeSigns using only one channel should,
therefore, use channel A.

Figure 6. An SOLC Loop

When an SDLC frame is received with an abort condition,
the byte counter in the FIFO enhancment is not reset.
Therefore, after the abort is received, a dummy frame
consisting of a flag should be sent by the transmitter. This
resets the byte counter for the next frame. The aborted
frame has a byte count which includes the byte count of the
next dummy frame.

A secondary station in an SDLC Loop is always listening to
Baud Rate Generator. Each channel in the ISCC contains
the messages being sent around the loop and, in fact.
passes .lhese messages to the rest of the loop
a programmable baud rate generator. Each generator
consists of two.S-bit time constant registers that form a 16by retransmitting them with a one-bit-time delay. The
bittime constant. a 16-bit down counter, and a flip-flop on
secondary st.ation places its own message on the loop only
at specific times. The controller signals that secondary., the output producing a square wave. On startup, the llipstations can transmit messages by sending' a special
flop on the output-is set in a High state, the value in the time
character, called an EOP (End Of Poll), around the loop. • constant register is loaded into the counter, and the
counter starts counting down The output of the baud rate
The EOP character is the bit pattern 11111110. Because
of zero insertion during messages, this bit pattern is unique
generator toggles upon reaching 0, the value in the time
and easily recognized.
constant register is loaded into the counter, and the
process is repeated. The time constant may be changed
at any time, but the new value does not take effect until the
When a secondary station has a message to transmit and
recognizes an EOP on the line, it changes the last binary
next load of the counter.
1 of the EOP to a 0 before transmission. This has the effect
The output of the baud rate generator may be used as
of turning the EOP into a flag sequence. The secondary
station now places its message on the loop and terminates
either the transmit clock, the receive clock, or both. It can
also drive the Digital Phase-Locked Loop (see next
the message with an EOP. Any secondary stations further
down i the loop with messages to transmit appends their
section).
messages to the message of the first secondary station by
II the' receive clock or transmit clock is not programmed to
the same process. Any secondary stations without mescome from the TRxC pin, the output of the baud rate
sages to send merely echo the incoming message and are
generator may be echoed out via the TRxC pin.
prohibited from placing messages on the loop (except
upon recognizing an EOP.)
The following formula rei ales the time constant to the baud
rate where PCLK or RTxC is the baud rate generator input
SDLC Loop mode is a programmable option in the ISCC.
frequency in Hertz. The clock mode is 1, 16, 32, or 64, as
NRZ, NRZI, and FM coding may all be used in SDLC
selected in Write Register 4, bits D6 and D7. Synchronous
Loop mode
operation modes should select 1and Asynchronous should
SOLe FIFO. The ISCC's ability to receive high speed
select 1'6, 32 or 64.
back-ta-back SDLC frames is'maximized by a 1O-bit deep
PCLK or RTxC Frequency
by 19-bit wide status FIFO. When enabled (through WR 15,
bit D2), it pfovides the DMA the ability to continue to
Time Constant =
-2
2(Baud Rate)(Clock Mode)
transfer data into memory so that the CPU can examine the
message later. For each SDLC frame, a 14-bit byte count.

175

FUNCTIONAL DESCRIPTION (Continued)
Digital Phase-Locked Loop. The ISCC contains a Dig,ital
Phase-Locked Loop (DPLL) to recover clock information
from a data stream with NRZI or FM encoding. The DPLL
is driven by a clock that is nominally 32 (NRZI) or 16 (FM)
times the data rate: The DPLL uses this clock, along with
the data stream, to construct a clock for the data. This
clock is then used as the ISCC receive clock, the transmit
cloc~, or both.
For NRZI encoding, the DPLL counts the 32x clock to
create nominal bit times. As the 32x clock is counted, the
DPLL is searching the incoming data stream for edges
(either 1 to 0, orO to 1). Whenever an edge is detected, the
DPLL makes a count adjustment (during the next counting
cycle), producing a terminal count closer to the center'of
the bit cell.
For FM encoding, the DPLL still counts from 0 to 31, but
with a cycle corresponding to two bit times. When the I)PLL
is locked, the clock edges in tile data stream should occur
between counts 15 and 16 and between counts 31 and O.
The DPLt: looks for edges only during a time centered on
the 15 to 16 counting transition.

generator. The DPLL output may be programmed to be
echoed out of the ISCC via the TRxC pin (if this pin is not
being used as an input).
Data Encoding. The ISCC may be programmed to encode
and decode the serial data in four different ways (Figure 7).
In NRZ encoding, a 1 is represented by a High level and a
is represented by a Low level. In NRZI encoding, a 1 is
represented by no change in level and a 0 is represented
by a change in level In FMl (more properly, bi-phase
mark), a transition occurs at the beginning of every bit cell.
A 1 is represented by an additional transition at tile center
of the bit cell and a 0 is represented by no additional
transition at the center of the bit cell. In FMO (bi-phase
space), a transition occurs at the beginning of every bit
cell. A 0 is represented by an additional transition at the
center of the bit cell, and a 1 is represented by no
additional transition at the center of tile bit cell. In addition
to these four methods, the ISCC can be used to decode
Manchester (bi-phase level) data by using tile DPLL in the
FM mode and programming the receiver for NRZ data.
Manchester encoding always produces a transition at the
center of (,he bit cell. If the transition is 0 to 1, the bit is a O.
If the transition is 1 to 0, the bit is a 1.

The 32x clock for the DPLL can be programmed to come
from either the RTxC input or the output of the baud rate

o
Data

NRZ

\
\

NRZI

FMl

FMO

Figure 7. Data Encoding Methods

Auto Echo and Local Loopback. The ISCC is cap'able of
automatically echoing everything it receives. This feature
is useful mainly in AsynChronous modes, but works in
Synchronous and SDLC modes as well. In Auto F.cho
mode, Txl) is RxD. Auto Echo mode can be used with NnZI
or FM encoding with no additional delay because the data
,stream is not decoded before retransmission. In Auto Echo

176

mode, the ICTS input is ignored as a transmitter enable
(although transitions on this input can still cause interrupts
if programmed to do so). In this mode, the transmitter is
actually bypassed and the programmer is responsible for
disabling transmitter interrupts and /WAIT//REQUEST on
transmit.

The ISCC is also capable of local loop back. In this mode
TxD is RxD is just like Auto Echo mode. However, in local
Loopback mode the internal transmit data is tied to the
internal receive data and RxD is ignored (except to be
echoed out via TxD). The ICTS and lOCO inputs are also
ignored as transmit and receive enables. However, transitions on these inputs can still cause interrupts. Local
Loopback works inAsynchronous, Synchronous and SDLC
modes with NRZ, NRZI or FM coding of the data stream.

receive channels has a DMA channel dedicaled to it to
move data to-and-from memory. The DMA channels are
dedicated to the transmit and receive FIFO's, and therefore, can not be used for device initialization. Each DMA
has a 32-bit address and a 16-bit byte counter. The DMA
address may be incremented or decremented providing
flexibility in doing block transfers.
See the 1/0 Interface Capabilities Section for more details
on the DMA features.

DMA Core. The ISCC contains four independent lIy-by
mode DMA channels. Each of the ISCC's transmit and

BUS INTERFACE UNIT (BIU) DESCRIPTION
The ISCC contains a flexible bus interface that is compatible with a variety of microprocessors and microcontrollers.
The device is designed to work with 8- or 16-bit bus
systems and may be used with addressldata multiplexed
busses or non-multiplexed busses. The multiplexed bus is
selected for the ISCC if there is an Address Strobe prior to
or during the transaction which writes the BCR. If no
Add ress Strobe is present prior to or during the transaction
which writes the BCR, a non-multiplexed bus is selected.
When the ISCC is initialized for non-multiplexed operation,
register addressing for the ISCC cell IS (with the exception
of WRO and RRO), accomplished as follows. Programming
the write registers requires two write operations and reading
the read registers requires both a write and a read operation.
The first write is to WRO which contains four bits that point
to the selected register (note point high command). The
second write is the actual control word for the selected
register. If the second operation is a read, the selected
register is accessed. When in the non-multiplexed mode,
all of the registers in the SCC cell of the ISCC, including the
data registers, are accessed in this fashion. lhe painter
register is automatically cleared after the second read or
write operation so that WRO (or RRO) is addressed again.
Note that when the DMA is not used to address the data,
the data registers must be accessed by pointing to Register 8. This is in contrast to the Z8530 which allows direct
addressing of the data registers through the C/D pin.
When the ISCC is initialized for non-multiplexed operation,
register addressing for the DMA cell (with the exception of
CSAR) is accomplished as follows and is completely
independent of tile SCC cell register addressing.
Programming the write registers requires two write
operations and reading the read registers requires both a
write and a read operation. The first write is to the Command Status Address Register (CSAR) which contains five
bits that point tothe selected register (CSAR bits 4 - 0). The
second write is the actual control word for the selected

register. If the second operation is a read, the selected
register is accessed. When in the non-multiplexed mode,
all of the registers in the DMA cell of the ISCC may be
accessed in this fashion. The pointer bits are automatically
cleared after the second read or write operation so that
CSAR is addressed again.
When the ISCC is initialized for multiplexed bus operation,
all registers in the SCC cell .are directly addressable with
the register address occupying AD5 through AD1, or AD4
through ADO (Shift Left I Shift Right modes). Two additional
pins, AO/SCC/IDMA and A llA/IB control the channel A/B
register selection and the SCC channel IDMA selection
Referto the AO/SCC/IDMA and A l/A/1B pin descriptions for
the encoding of these signals.
The Shift Left I Shift Right modes for the address decoding
for the internal registers (multiplexed bus) are separately
programmable for the SCC cell and for the DMA cell. For
the SCC cell the programming and operation is identical to
that in the SCC; programming is accomplished through
Write Register 0 (WRO), bits 1 and 0 (Figure 9-1).
The programmlllg of the Shift Left/SMt Right modes for the
DMAcell is accomplished in the BCR, bitO. In this case, the
shift function is similar to that for the SCC cell; with Shift left,
the internal register addresses are decoded from bits AD5
through ADI and with Shift RighI. the internal register
addresses are decoded from bils AD4 through ADO.
When the multiplexed bus mode is selected, Write Register

o(WRO) takes on the form of WRO in the Z8030 (Figure 9).
All data transfers to and from the ISCC are done in bytes
even though the data can, at speCial times, occupy the
lower or upper byte of lhe 16-bit bus. When accessed as
a peripheral device(ie., when tile ISCC is not a bus master
performing DMA transfers), all bus transactions are on the
fower 8 bits of the bus with the following exception'

FUNCTIONAL DESCRIPTION (Continued)
When the Isee registers are read, the byte data is present
on both the lower 8 bits of the bus and the upper 8 bits of
the bus. Data is accepted only on the lower 8 bits olthe bus
except in certain DMA transfers.
During DMA transfers, data may be transferred to or from
the Isee on the upper 8 bits of thebus for odd or even byte
transfers. During DMA transfers to memory from the ISee,
byte data only is transferred and the data appears on both
the lower 8 bits and is replicated on the upper 8 bits of
the bus.
During DMA transfers to the Isee from memory, byte data
only is transferred and normally data is accepted only on
the lower 8 bits of the bus. However, the byte swapping

feature may be used to elect on which byte of the bus the
data is accepted. The byte swapping feature is enabled by
programming the Byte Swap Enable bit to a 1 in the
BeR. The .odd/even byte transfer selection is made by
programming the Byte Swap Select bit in the BeR. If Byte
Swap Select is a 1, then even address bytes (transfers
where the DMA address has AO equal 0) are transferred on
the lower 8 bits olthe bus and odd address bytes (transfers
where the DMA address has AO equal 1) are transferred on
the upper 8 bits of the bus. If Byte Swap Select is a 0, then
even address bytes (transfers wllere the DMA address has
AO equal 0) are transferred on the upper 8 bits of the bus
and odd address bytes(transfers where the DMA address
has AO equal 1) are transferred on the lower 8 bits of
the bus.

1/0 INTERFACE CAPAS,lITIES
The Isee offers the choice of Polling, Interrupt (vectored
or non-vectored), and DMA Transfer modes to transfer
data, status, and control information to and from the CPU.
Polling. In this mode all interrupts and the DMA's are
disabled. Three status registers in the sec are automatically updated whenever any function is performed. For
example, end-of-frame in SDLe mode sets a bit in one
of these status registers. With polling, the CPU must
periodically read a status register until the register contents
indicate the need for some CPU action to be taken Only
one register in the sec needs to be read; depending on
the contents of the register, the CPU either reads data,
writes data, or satisfies an error condition. Two biis in the
register indicate the need for data transfer. An alternative
is to poll the Interrupt Pending register to determine the
source of an interrupt. The status for both sec channels
resides in one register.
Interrupts. When the Isee responds to an Interrupt Acknowledge signat (INTAeK) from the CPU, an interrupt
vector is placed on the data bus. Both the sec and the
DMA contain vector registers. Depending on the source of
interrupt, one of these vectors is returned. either unmodified
or modified by the interrupt status to indicate the exact
cause of the interrupt.
Each onhe six sources in interrupts in the sec (Transmit,
Receive, and External/Status interrupts in both channels)
and each DMA channel has three bits associated with the
interrupt source: Interrupt Pending (IP), Interrupt Under
Service (IUS), and Interrupt Enable (IE). If the IE bit is set
for any given source of interrupt, then that source can
request interrupts. The only exception to this rule is when

178

the associate Master Interrupt Enable (MIE) bit is reset,
then no interrupts are requested. Both the sec and the
DMA have an associated MIE bit. The IE bits in the sce are
write only, but tile IE bits in the DMA are read write.
The Isce provides for nesting of interrupt sources with an
interrupt daisy chain using the lEI, lEO, and INTACK pins.
As a microprocessor peripheral, the Isce may request an
interrupt only when no higher priority device is requesting
one, e.g., when lEI is High. If the device in question
requests an interrupt, it enables the /INT signal. The CPU
then responds with /INT ACK, and the interrupting device
places the vector on the data bus.
In the ISeC, the IP bit signals a need for interrupt servicing.
When an IP bit is 1 and the lEI input is High, the /INT signal
is activated, requesting an interrupt. In the sec, if the IE bit
is not set, tllen the IP for that source can never be set. The
IP bits in the DMA are set independent of the IE bit.
The IUS bits signal that an interrupt request is being
serviced. If an IUS is set, all interrupt sources of lower
priority in the ISCC and external to the ISCC are prevented
from requesting interrupts. The internal interrupt sources
are inhibited by the state of the internal daisy chain, while
lower priority devices are inhibited by the lEO output of the
Isee being pulled Low and prop(lgated to subsequent
peripherals. Internally, the SCC is higher priority than the
DMA. An IUS bit is set during an Interrupt Acknowledge
cycle if there are no higher priority devices requesting
interrupts.
Within the SCC portion of the Isee there are three types of
interrupts' Transmit, Receive, and External/Status. Each

, interrupttype is enabled under program control with Channel A having higher priority than Channel B, and wi.th
Receive, Transmit, and External/Status interrupts prioritized
in that order within each channel. When the Transmit
interrupt is enabled, the CPU is interrupted when the
transmit buffer becomes empty. This implies that the
transmitter had a data character written into it to make it
empty. When enabled, the receiver interrupts the CPU in
one of three ways:
1. Interrupt on First Receive Character or Special Receive
Condition
2. Interrupt on All Receive Characters or Special Receive
Condition
3. Interrupt on Special Condition Only
Interrupt on First Character or. Special Condition, and
Interrupt on Special Condition Only, are typically used
when doing block transfers with the OMA. A Special
Receive Condition is one of the following: receiver overrun,
framing error in Asynchronous mode, end-of-frame in
SOLC mode and, optionally, a parity error. The Special
Receive Condition interrupt is different from an Ordinary
Receive Character Available interrupt only by the status
placed in the vector. during the Interrupt Acknowledge
cycle. In Interrupt on First Receive Character, an interrupt
occurs from Special Receive Conditions any time aiter the
First Receive Character interrupt.
The main function of the External/Status interrupt is to
rnonitor the signal transitions of the /CTS, lOCO, and
/SYNC pins; however, an External/Status interrupt is also
caused by a Transmit Underrun condition, or a zero count
in the baud rate generator, or by the detection of a Break
(Asynchronous mode), Abort (SOLC mode) or EOr (SOLC
Loop mode) sequence in the data stream. The interrupt
caused by the Abort or EOP has a special feature allowing
the ISCC to interrupt when the Abort or EOP sequence is
detected or terminated. This feature facilitates the proper
termination of the current rnessage, correct initialization of
the next message, and the accurate timing of the Abort
condition in external logic.
Each OMA in the ISCC has t'NO sources of interrupt, which
share an IP bit and an IUS bit, but have independent
enables: Terminal Count and Abort. The Abort interrupt is

generated when an active OMA channel is forced to
terminate its transfers because /BUSACK is de-asserted
during a transfer. The Terminal Count interrupt is generated when the OMA transfer count reaches zerO. The OMA
channels themselves are prioritized in a fixed order: Receive
A, Transmit A, Receive B, and Transmit B.
DMA Transfer. In this mode, the on-Chip OMA channels

transfer data directly to the transmit buffers or directly from
the receive buffers. No other transfers are possible (for
initialization, for example). The request signals from the
receivers and transmitters are hard-wired to the request
inputs of the OMA channels internally. Each OMA channel
provides a 32-bit address which is either incremented or
decremented with a 16-bit transfer length. Whenever a
OMA channel receives a request from its associated
receiver or tranSrnitter and the OMA channel is enabled,
the ISCC activates the /BUS REO signal. Upon receipt of an
active /BUSACK, the OMA channel transfers data between
memory and the SCC. This transfer continues until the
receiver or tranSmitter stoP!? requesting a transfer, until the
terrninal count is reached, or /BUSACK is deactivated. The
four OMA channels operate independently when tile Request Per Channel option is selected; otherwise, all requests
pending at the time of bus acquisition will be serviced
before the bus is released. Each OMA channel is
independently enabled and disabled.
Bus Interface. The Isce contains a flexible bus interface
that provides the resources necessary to interfClce the
ISCC to virtually any type of bus. The Isee directly supports
either an 8-bit or a 16-bit bus, although all transfers to and
from the device are limited to 8-bits at a time. The control
signals provided allow connection to either a rnultlplexed
address/data type bus or to a separate address and data
type bus. While the Isee is bus master, the upper address,
lower address, and data are multiplexed on A015-0
Interrupt Acknowledge is signaled through the /INT ACK
signal, which may be programmed as either a status input,
a pulsed input, or a double-pulsed input The Isee also
contains a /WAITI/ROY input for synchronizing CPU or
OMA and memory accesses This pin may be programmed
to act as either a /WAIT signal or a /REAOY signal The
appropriate signal is provided by the Isce when it is not
bus master, and is sampled by the Isec when it is bus
master. The ISCC requests the bus via a /BUSREO signal
and assumes bus mastership upon receipt of a /BUSAeK
signal.

179

CONTROL REGISTERS
The ISCC contains separate register sets for the SCC core
and the OMA core. Access to each set is controlled by the
AO/SCC//OMA pin. When this pin is an input, a High selects
the SCC core and a Low selects the OMA core. The first
write to the ISCC after reset is always to the Bus Configuration Register (BCR). see Figure 8. If an /AS is present
before the BCR is written to. a multiplexed bus is selected.
If no /AS is present before the BCR write. a non-multiplexed
bus is selected. The BCR cannot be changed without
resetting the ISCC.

Iwloolool~looloolrnlool

Ack~:::~;:Add~ ror D~

I Iln::o 0 Status Acknowledge
o 1 Pulsed Acknowledge
1
0 Reserved
1
1 Double-Pulsed Acknowledge

DMA eell. The OMA cell contains 17 registers (countil1g
the BCR). All of the registers are write/read except the
BCR. CCAR and ICSR. The ISCC also has two status
registers. the OMA status register (OSR) and the Interrupt
Status Register (ISR). which are addressed by reading the
CCAR and ICSR. The OMA also reserves two addresses
for future 'use and should not be addressed or should be
written with all 'zeros to prevent unexpected operation and
maintain compatibility with future products. Each OMA
channel has a 32-bit wide address register providing an
addressing range of 4 gigabytes. Each channel also has
a 16-bit count register for up to 64K byte data packet sizes
(Reference Figures 11-26 and Table 3).

Table 1. see Write Registers
Bit

Description

WRO

WR1

Reserved
Byte SWap Select
Byte SWap

Enable

Figure 8. Bus Configuration Register (BeR)
see pell. The SCC core contains 13 write registers
(14 counting the transmit buffer) and ten read registers
(11 counting the receive buffer) in each channel. Twoofthe
write registers are shared (WR2 and Wn9) and are' accessed by both channels. WR2 contains the interrupt
vector for both channels. while WR9 contains the interrupt
control bits. Table 1 is a list of the SCC write registers and
Table 2 is a list of the SCC read registers. Figures 9and 10
~f1ow the write and read register formats. Read Registers
6 and 7 are only accessible when the SOLC FWO is
enabled. When the SOLC FIFO is not enabled. Read
Registers 6 and 7 are images of Read Registers 2 and 3. ,
respectively.

180

WR2
WR3
WR4
WR5

Interrupt Vector
Receive pa~ameters and control modes
Transmit and Receive mooes and parameters
Transmit parameters and control modes

WR6
WR7
WR8
WR9

Sync Character or SOLC address
Sync Character or SOLC flag
Transmit buffer'
Master Interrupt control and reset commands

WR10
WR11
WR12
WR13

Miscellaneous transmit and receive control bits
Clock mode controls for receive and transmit
Lower byte of baud rate generator
Upper byte of baud rate generator

WR14
WR15

Miscellaneous con(rol bits
External status interrupt enable control

Write Register 0 (non-multiplexed bus mode)

Wrfte Register 1

Imlool~I~lool~lmlool

I I I

0
0

0
1
1
0

0
1
1
1
1
o

o
1
1

0
1
0
1

0
1
1

0
1

0
1
0
1
0
1

0
0
0
0

0
0

1
1

1
1
1
1
0

0
0
1
1

0
0

0
0
1
1
1
1

1
1
0
0
1
1

1
1
0
1
0
1

0
1
0
1
0
1
0
1

~~::::;~

Reglsterg
Register 10
Register 11
Register 12
Register 13
Register 14
Register 15

}

0
0

1
1

0
1
0

Parlty Is Special Condition

Rx Int Olseble
Rx Int On First Character or Special Condition
Int On All Rx Characlem or Special Condition
Rx Int On Special C ondltlon Only
WAITIDMA·Request On
Receivelrrransmit

•

Null Code
Point High
Reset EXVStalus Interrupts
Send Abort (SOLC)

Ext Int Eneble
Tx Int Eneble

IWAIT/DMA Request FUnction
WAIT/OMA Reque,1 Eneble

Write Register 2

Enable Int on Next Rx Character

Reset Tx Int Pending
Error Reset
Reset Highest IUS

NuliCode
Reset Rx CRC Checker
Reset Tx CRC Generator
Reset Tx UnderrunlEOM latch

Interrupt
Vector
V5

• With Point High Command

Wrne Register 0 (multiplexed bus mode)

Imlool~I~lool~lmlool

Write Register 3

I I

o
o

0
1

o
1

Null Code
Null Code
Select Shift Left Mode } •
Select Shift Right Mode

Rx Eneble
Sync Character load Inhibit

Address Search Mode (SOLC)

RxCRC Eneble

0
0
0
0

o
o
1
1

0
1
0
1

0
0
1
1
0
0
1
1

0 Null Code
1 Null Code
0 Reset Ext/Stalus Interrupts
1 Send Abort
0 Enable Int on Next Rx ,Character
1

Reset Tx Int Pending

Error Reset

Reset Highest IUS

Enter Hunt Mode
Auto Enables

o
o

1
1

0
1
0
1

Rx
Rx
Rx
Rx

5
7
6
8

Bits/Character
Bits/Character
Bits/Character
Bns/Character

NuliCode
Resetilx CRC Checker
Reset T x CRC Generalor
Reset T x UnderrunlEOM latch

• B Channel Only

Figure 9_ Write Register Bit Functions

181

Wr~e

TxCRC Enable

Parity Enable

RTS

Parity EVEN/IOOO

o
o
1
1

!SOLC/CRC·16
0
1
0
1

Sync Modes Enable
1 Slop BII/Character
1 112 Stop Bits/Character
2 Slop BItsICharacter

TxEnable

Send Break
o

o
1
1

0
1
0
1

8-Blt Sync Character
16-81t Sync Character
SOLC Mode (01111110 Flag)
External Sync Mode

1
1

0
1
0
1

Tx S Bots(Or Less)lChaoacter
Tx 7 Bits/Character
Tx 6 Bits/Chaoacter
Tx 8 Bits/Character
OTR

o
o
1
1

0
1
0
1

Xl Clock Mode
X16 Clock Mode
X32 Clock Mode
X64 Clock Mode

WrRe Register S

SyncS
SyncO
SyncS
Sync2
AORS
AORS

Sync7
Sync1
Sync7
Sync3
AOR7
AOR7

SyncS
SyncS
SyncS
Sync1
AORS
AOR5

Sync4
Sync4
Sync4
SyncO
AOR4
AOR4

Sync3
Sync3
Sync3
1
AOR3

Sync2
Sync2
Sync2
1
AOR2

Sync1
Sync1
Sync1
1
AORl

x·

SyncO
SyncO
SyncO
1
AORO
x

Monosync, 8 BitS
Monosync, S Bits
Bisync, 16 Bits
Bisync, 12 Bits
SOLC
SOLC (Address Range)

WrRe RegISter 7

Sync7
SyncS
,SynclS
Syncll

Sync6
Sync4
Sync14
Syncl0

SyncS
Sync3
Sync13
Sync9

Sync4
Sync2
Sync12
SyncS
1

Sync3
Syncl
Syncll
Sync7
1

Sync2 Syncl
syncO
x
Syncl0 Sync9
Sync6 SyncS
1
1

SyncO

x
SyncS
Sync4

Monosync, 8 Bots
Monosync, 6 Bots
Bisync, 16 Bit!!
Bisync, 12 Bots
SOLC

Figure 9, Write Register Bit Functions (Continued)

182

Write Register 12

Wrne Register 9

107 106 105 104 103 102 101 IDO I

VIS

TCO

TCl

OLC

TC2

MIE

TC3

Status HighllSlatus Low

TC4

TC5

Lower Byte of
Time Constant

TC6

o
o

1
1

0
1

No Reset
Channel Reset B
Channel Reset A
Force Hardware Reset

TC7

Wrne Register 13
Write Register 10

Tca
TC9

6 BiVI8 Bn Sync
TC10

Loop Mode
AborVlFlag On Underrun
MarkllFlag Idle

TCll

Upper Byte of

TC12

lime Constant

TC13

Go Active On Poll

TC14

o
o

0 NRZ
1 NRZl

1
1

0
1

TC15

FM1 (Transttion = 1)
FMO (Tran.ttion = 0)
Write Register 14
CRC Preset lifO

Wrtte Register 11
SR Generator Enable
SA Generator Source

I I

10TRIRequest Function

0
0

0 !fRxC Out = Xtsl Oulput

Auto Echo

1
1

Local Loopback

!fAx C Out =Transmit Clock
!fAx C Out = BR Generator Oulput
!fRxC Out = OPLL Oulput
!fAxC

0
0

0 Transmit Clock = fA TxC Pin

1
1

Transmit Clock = !fRxCPin
T ransmtt Clock = BR Generator Output
T ransmn Clock = 0 PLLOulput

0
0

1
1

Receive Clock

Receive Clock = OPLL Output

0
0
0
0
1
1
1
1

0
0

0
1

Null Command
Enter Search Mode

1
1
0

Reset Missing Clock

1
0
1
0
1

Disable OPLL
Set Source = SR Gener~tor
Set Source =IRTxC
SetFM Mode
SetNRZIMode

0
1
1

Receive Clock = IRTxC Pin
Receive Clock = ffRxC Pin

= SA Generator OUlput
IRTxC XtaillNo Xtal

Figure 9. Write Register Bit Functions (Continued)

183

Write Register 15

,1' 1

•

07 061 OSI 041 031 021 011 00

.~ ~eroCountlE
~
L.:::=

SOLe AFO Enable
DCOIE

SynelHunt IE
crSIE
Tx UnderrunlEOM IE
Break/Abort IE

Figure 9. Write Register Bit Functions (Continued)

Table 2.

see Read Reglst~rs

Bit

Description

RRO

Transmit and Receive buffer status and external status
Special Receive Condition status
Modified interrupt vector (Channel B only), Unmodified interrupt vector (Channel A only)
Interrupt pending bits (Channel A only)

RR1
RR2
RR3

RR6
RR10

SDLC FIFO byte counter lower byte (only when enabled) ,
SOLC FIFO byte count and status (only when enabled)
Receive buffer
Miscellaneous status bits

RR12
FjR13
RR15

Lower byte of baud rate generator time constant
Upper byte of baud rate generator time constant
External Status interrupt information

RR7

RR8

184

Read Register 0

Read Register 3

Ax Character Available

Chan'nel B ExtlStatus IP }

Zero Count

Channel B Tx IP

Tx Buller Empty

Channel B Rx IP

OCO

Channel A ExtiStatus IP

•

Channel A Tx IP

SynclHunt

Channel A Rx IP

CTS

o
o

Tx UndemmlEOM
Break/Abort
• Always 0 In B Channel
Read Register 1
Read Register 6

All Sent
Residue Code 2

BCO

Residue Code 1

BCl

Residue Code 0

BC2

Parity Error

Bea

Rx Overrun Error

BC4

CRClFraming Error

BC5

End 01 Frame (SOLC)

BC6
BC7

Read Register 2

• Can only be accessed il the SOlC FIFO enhancement
is enabled ('!VRIS bn 02 setto 1)

SOLC FIFO Status and Byte Count (LSB)
Read Register 7 •

Interrupt

vector •
BC8

BC9

BC10

BCll
BC12

• Mocfofied In B Channel

BC13
FDA: FIFO Available Status
1 = Status Reads from FIFO
FOS: FIFO Overflow Status
1 = FIFO Overflowed
0= Nonnal
• Can only be accessed il the SOlC FIFO enhancement
is enabled (WR15 bit D2 set to 1)

SOLC FIFO Status and Byte Count (MSB)

Figure 10. Read Register Bit Functions

185

Read Register 10

Read Register 13

1071061051041031 021 01 100 I
Tce

TC9
TC10
TCll

loop Senclng

TC12

TC13

Two Clocks Missing

TC14

One Clock Missing

TC15

Read Register 12

Upper Byte
of Time Constant

Read Register 15

I ~~~."

TCO
TCl

~OCDIE

TC2
TC3

lower Byte

TC4

01 TIme Constant

SyncIHunt IE

l;C5

CTSIE

TC6

Tx UnderrunlEOM IE

Te7

Break!Abort IE

Figure 10. Read Register Bit Functions (Continued)

Table 3. DMA Cell Register Description

Address

Name

Description

xxxxx
00000
00000
00001

BCR
CCAR
DSR
ICR

Bus Configuration Register
Channel Command/Addr'!ss Register (WRITE) .
DMA Status Register (READ)
Interrupt Control Register

00010
00011
00011
00100

IVR
ICSR
ISR
DER

Interrupt Vector Register
Interrupt Command Register (WRITE)
Interrupt Status Register (READ)
DMA Enable/Disable Register

00101
00110
00111
01000-01001

DCR

RDCRA

DMA Control Register
Reserved Address
Reserved Address
Receive DMA Count Register Channel A (Low-high byte)

01010-01011
01100-01101
01110-01111
10000-10011

TDCRA
RDCRB
TDCRB
RDARA'

Transmit DMA Count Register Channel A
Receive DMA Count Register Channel B
Transmit DMA Count Register Channel B
Receive DMA Address Register Channel A

10100-10111
11000-11011
11100-11111

TDARA
RDARB
TDARB

Transmit DMA Address Register Channel A
Receive DMA Address Register Channel B
Transmit DMA Address Register Channel B

186

Address: 00010

Address: 00000 (WrIte)

lool~I~I~lool~I~lool

~
L.::::: ::}
~IVO

Address 0
Address 1

Address 2
Addres83

IV4

Address 4

1V5

DMA Commands

o
o
o

o
1
1

1
1

IV3

IV6

0
0 Null Command
0
1 Reserved
1 0 Reset Highest IUS
1 1 DMA Reset
0
0 Enable Tx B DMA
0
1 Enable Rx B DMA
1 0 Enable Tx A DMA
lIEnable Rx A DMA

1V7

* Potentially modified by Interrupt condition
Figure 14. Interrupt Vector Register

Figure 11. Channel Command/Address Register
Address: 00011 (Write)

Address: 00000 (Read)
SelectTxBDMA
Select Rx B DMA

Tx B DMA AbOrt

Select Tx A DMA

Rx B DMA Abort

Select Ax A DMA

Tx A DMA Abort

ReserVed

Rx A DMA Abort
Tx B DMA Tenninal Count
Ax B DMA Temmal Count
Tx A DMA Tenninal Count
Ax A DMA Tannlnal Count

Figure 12. DMA Status Register

DMA Interrupt Commands

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

NuI.Command
ResetlP
Reset IUS
ResetlP and IUS
Reserved
SetlP
Set IUS
Set IP and IUS

Figure 15. Interrupt Command/Register

Address: 00001

Address: 00011 (Reed)

~
~

TxBDMAlntenuptEnabie
Ax B DMA Interrupt Enable
, Tx A DMA Inte"';pt Enable

TxBDMAIP
AxBDMAIP

Ax A DMA I"tenupt Enable

VIS

NV
DLe
MlE

TxADMAIP
RxADMAIP
TxBDMAIUS
Rx BDMA IUS
Tx A DMA IUS
RxADMAIUS

Figure 13. Interrupt Control Register
Figure 16. Interrupt Status Register

187

Address: 001<11

Address: 001,00

1071061051041031021011 DO I

Tx B OMA Abort Enable
Ax B OMA Abort Enable
Tx A OMA Abort Enable
Ax A OMA Abort Enable
Tx B OMA Enable
Rx B OMA Enable

o
o

Tx A OMA Enable

1
1

0
1
0
1

Tx B OMA Address Inc/IDee
Ax B OMA Address Inc/IDee
I

Tx A OMA Address Inc/IDee
Ax A OMA Address Inc/IDee

OMA Priority
Rx AlTx NAx Brrx B
Rx BfTx BlRx AlTx A
Rx NAx BfTx AlTx B
Rx BlAx AlTx BfTx A

Rx A OMA Enable

Reserved

Bus Request per Channel

Figure 17. DMA Enable Register
Figure 18. 'DMA Control Register

Ad<*'ess: 01000 (Low Byte)
01001 (High Byte)

Address: 01000 (Low Byte)
01001 (High Byte)

Ax ACntO

Rx ACn18

Ax ACntl

Rx ACnt9

Ax ACnt2

RxACnt'10

Ax ACnt3

Rx ACntll

Ax ACnt4

RxACnt12

Ax ACntS

Rx ACnt13

Ax ACnt6

Rx ACnt14

Ax ACnt7

RxACntlS

B)MSB

A)LSB

Figure 19. Receive DMA Count Register Channel A

Ad<*'ess: 01010 (Low Byte)
01011 (High Byte)

Address: 01010 (Low Byte)
01011 (High Byte)

1071061051041031021011
Dol
I
TxACntO

TXACnt8

Tx ACnt1

TxACni9

Tx ACnt2

TxACntl0

Tx ACn\3

TxACntl1

Tx ACnI4

Tx A Cnt12

Tx ACntS

Tx ACnt13

Tx ACnt6

TxACnt14
TxACntlS

Tx ACnt7

A)LSB

B)MSB

Figure 20. Transmit DMA Couht Register Channel A

188

Address: 01100 (Low Byte)
01101 (High Byte)

RxBCntO

RxBCnt8

RxBCntl

RxB Cnt9

RxB Cnt2

RxB Cntl0

RxB Cnt3

RxB Cntl1

RxB Cnt4

RxB Cnt12

RxB CntS

RxB Cnt13

RxB Cnt6

Rx B Cnt14

RxBCnt7

Rx B Cnt15

A) LSB

B)MSB

Figure 21. Receive DMA Count Register Channel B

Add"ess: 01110 (Low Byte)
01111 (High Byte)

Add-ess: 01110 (Low Byte)
01111 (High Byte)

Tx B CntO

Tx BCntS

Tx BCnI1

Tx BCnt9

Tx BCnt2

Tx B Cntl0

Tx BCnt3

Tx B Cntl1

Tx BCnt4

Tx B Cnt12

Tx BCnt5

Tx B Cnt13

Tx B Cnt6

Tx B Cnt14

Tx BCnt7

A) LSB

Tx BCnt15

B)MSB

Figure 22. Transmit DMA Count Register Channel B

189

Address: 10010 (Bits 16-23)

Address: 10000 (Bits 0-7)
"

AxAAddrO

Ax A Addr16

RXAAddrt

Ax A Addr17

AxAAddr2

Ax A Addr18
Ax A Addr19

AxAAddr3

AxAAddr20

Ax A Addr4

Ax AAddr21

Ax A AddrS

AxAAddr22

Ax A Addril

AxAAddr23

AxAAddr7

Address: 10011 (Bits 24-31)

Address: 10001 (Bits8-15)

Ax AAddrii
Ax AAddr9
Ax AAddr10

AAdd~l

Ax AAddr12

Ax A Addr25

Ax A Addr26
Ax AAddr27
Ax A Addr28

Ax A Addr13

Ax A Addr29

RxAAddr14

Ax A Addr30

Rx AAddr15

Ax A Addr31

Figure 23. Receive DMA Address Register Channel A

190

Ax A Addr24

Address: 10100 jBils 0-7}

Address: 101 01
1 07 1

osl

(B~s

Address: 10110(Bns1S-23)

Tx AAddr{)

Tx A Addr16

Tx A Addr1

Tx A Addr17

Tx A Addr2

Tx A Addr18

Tx A Actdr.3

TxAAddr19

Tx AAddr4

Tx A Addr20

Tx A AddrS

Tx A Addr21

Tx A Addr6

Tx A Addr22

Tx AAddr7

Tx A Addr23

8-15)

Address: 10111

(B~

24-31)

051 041 031 021 011 001

Tx AAddrtl

Tx A Addr24

TxAAddr9

Tx A Addr25

Tx A Addr10

Tx A Addr26

TxAAddr11

Tx A Addr27

Tx A Addr12

TxAAddr28

TxAAddr13

Tx AAddr29

Tx A Addr14

TxAAddr30

Tx A Addr15

Tx A Addr31

Figure 24. Transmit DMA Address Register Channel A

191

Adltess: 11000 (BIts 0-7)

Address: 11010 (BltoI6-23)

RlrBAddrO

Ax BAddr16

AxBAddr1

RxBAdelr17

AxBAddr2

Ax BAddr18

Ax BAdct3

Rx BAdelr19

AxBAddr4

Rx BAddr20

Ax BAddr5

Ax BAddr21

Rx BAddr6

Rx BAddr22

Rx BAddr7

AX BAddr23

Adltess: 11001 (Bits 8-15)

Address: 11011 (BIts 24-31)

Ax BAddr6

Rx BAddr24

Rx BAddr6

Ax BAddr25

Ax BAdelrl0

Rx BAddr26

Ax BAddrll

Rx BAddr27

Rx BAddr12

Ax B Addr28

Rx BAdelr13

Rx B Addr29

Rx BAddr14

Rx BAdct30

Rx B Addr15

AxBAddr31

Figure 25_ ReCeive DMA Address Register Channel B

192

Address: 11100 (BI1s 0-7)

Address: 11110 (BI1s 16-23)

TxBAddrO

Tx BAddr16

Tx BAddr1

Tx BAddr17

TxBAddr2

Tx BAddr18

Tx BAddr3

Tx BAddr19

Tx BAddr4

Tx B Addr20

TxBAddrS

Tx BAddr21

TxBAddr6

Tx B Addr22

Tx BAddr7

Tx BAddr23

Address: 11101 (Bilo 8-15)
Address: 11111 (BI1s 24-31)

Tx B AddIS
Tx B Addr9
Tx BAddr10
Tx BAddr11
Tx BAddr12
Tx BAddr13

Tx B Addr24
TxB Addr25
TxB Addr26
Tx B Addr27
TxB Addr28
Tx B Addr29

Tx BAddr14

TxB Addr30

TxBAddr15

Tx B Addr31

Figure 26. Transmit DMA Address Register Channel B

193

ABSOLUTE MAXIMUM RATINGS
Voltages on all pins,
with respect to GND ................................ -0.3 V to +7.0 V
Operating Ambient
Temperature ........................... See Ordering Information
Storage Temperature ............................... -85°C to 150°C

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to tile device. This is a stress rating only; operation of the device at
any condition above those indicated in the operational
sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.

STANDARD TEST CONDITIONS
The DC Characteristics and Capacitance section below
apply for the following standard test conditions, unless
otherwise noted. All voltages are referenced to GND.
Positive current flows into the referenced pin. Standard
conditions are as follows:
•

+4.75 V!> Vee!> 5.25 V

•

GND =OV

•

TA as specified in Ordering Information

2.0Kn

From Output
Under Test

250 ftA

':"

Figure 27. Standard Test Load

CAPACITANCE
Symbol

Parameter

Input Capacitance
Output Capacitance
Bidirectional Capacitance
Nole:
f = 1 MHz over specified temperature range.
Unmeasured pins returned to ground.

MISCELLANEOUS
Transistor Count
52,047

194

Min

Max

Unit

10
15
20

pF
pF
pF

Condition

Unmeasured Pins
Returned to Ground

DC CHARACTERISTICS
Z16C35
Symbol

Parameter

Min

VIH
Vil
VOH1
V0H2

. Input High Voltage
Input Low Voltage'
Output High Voltage
Output High Voltage

VOL
III

Output Low Voltage
Input Leakage
Output Leakage
Vcc Supply Current

10l
Iccl

Typ

2.2
-0.3
2.4
Vcc -0.8

Max

Unit

Vcc +0.3
0.8

V
V
V
V

0.4
±10.00 t.tA
±10.00 t.tA
50

Condition

= -1.6mA
= -250 t.tA
10l = +2.OmA
IOH
IOH

0.4 < V". < +2.4 V
0.4 < VOUT < +2.4 V
Vcc = 5 V. VIH = 4.8 V. Va.

=0.2 V

Nole:
Vco = 5 V ± 5% unless otherwise specified. over specnied temperature range.

AC CHARACTERISTICS
Note: See the corresponding figures following this table (Figures 28-49).
No

Symbol

Parameter

1
2
3
4

Tcyc
TwASI
TwASh
TwDSI

Bus Cycle Time
lAS Low Width
lAS High Width
IDS Low Width

5
6
7
8

TwDSh
TdAS(DS)
TdDS(AS)
TdDS(DRa)

IDS High Width
lAS Rise to IDS Fall Delay Time
IDS Rise to lAS Fall Delay Time
IDS Fall to Data Active Delay

9
10
11
12

TdDS(DRv)
TdDS(DRn)
TdDS(DRz)
TsCS(AS)

IDS Fall to Data Valid Delay
IDS Rise to Data Not Valid Delay
IDS Rise to Data Float Delay
ICS to lAS Rise Setup Time

13
14
15
16

ThCS(AS)
TsADD(AS)
ThADD(AS)
TsSIA(AS)

ICS to lAS Rise Hold Time

17
18
19

10 MHz·
Min
Max

16 MHzt
Min
Max

4TcPC
40

4TcPC

90
70

55
50

5
5
0

5
0

85
0

Direct Address to lAS Rise Setup Time
Direct Address to lAS Rise Hold Time
Status IINTACK to lAS Rise Setup Time

0
15
5
15

0
12
5
10

ThSIA(AS)
TsAD(AS)
ThAD(AS)
TsRW(DS)

Status liNTACK to lAS Rise Hold Time
Address to lAS Rise Setup Time
Address to lAS Rise Hold Time
R//W to IDS Fall Setup Time

5
15
5
0

5
10
5
0

21
22
23
24

ThRW(DS)
TdDSf(RDY)
TdDSr(RDY)
TsDW(DS)

R//W to IDS Fall Hold Time
IDS Fall to IREADY Fall Delay
IDS Rise to /READY Rise Delay

Write Data to IDS Fall Setup Time

25
26'
28

ThDW(DS)
TdRDY(DRv)
TwRDI
TwRDh

Write Data to IDS Fall Hold Time
IREADY Fall to Data'Valid Delay
IRD low Width
IRD High Width

Notes

[1i
[1]

15
40

50
40

20
0
15

195

AC CHARACTERISTICS (Continued)

Symbol

Pa~ameter

30
31
32
33

TdAS(RD)
TdRD(AS)
TdRD(DRa)
TdRD(DRv)

lAS Rise to IRD Fall Delay Time
IRD Rise to lAS Fall Delay Time

34
35
36
37

TdRb(DRn)
TdRD(DRz)
TdRDf(RDY)
TdRDr(RDY)

38
39
40
41

TwWRI
TwWRh
TdAS(WR)
TdWR(AS)

IWR Low Width
IWR High Width
lAS Rise to /WR Fall Delay Time

42
43
44
45

TsDW(WR)
ThDW(WR)
TdWRf(RDY)
TdWRr(RDY)

46
47
48
49

fRO Fall to Data Active Delay

10 MHz'
Min
Max

5
5
0
0

75
0
15
40
20

20
50
40

IRD Rise to Data Float Delay
IRD Fall to IREADY Fall Delay
IRD Rise to IREADY Rise Delay

Notes

5
5
0
85

IRD Fall to Data Valid Delay
/RD Rise to Data Not Valid Delay

16 MHzt
Min
Max

70
60
5
5

50
30
5
5

Write Data to IWR Fall Setup Time
Write Data to /WR Fall Hold Time
IWR Fall to IREADY Fall Delay
/WR Rise to /READY Fall Delay

0
25

0
15

TsCS(DS)
ThCS(DS)
TsADD(DS)
ThADD(DS)

ICS to IDS Fall Setup Time
ICS to IDS Fall Hold Time
Direct Address to IDS Fall Setup Time
Direct Address to IDS Fall Hold Time

0
25
0
25

0
15
0
15

[2]
[2]
[1,2]
[1,2]

50
51
52
53

TsSIA(DS)
ThSIA(DS)
TsCS(RD)
ThCS(RD)

Status IINTACK to IDS Fall Setup Time
Status IINTACK to IDS Fat! Hold Time
ICS to IRD Fall Setup Time
ICS to IRD Fall Hold Time

0
25
0
25

0
15
0
15

[2]
[2]
[2]
[2]

54
55
56
57

TsADD(RD)
ThADD(RD)
TsSIA(RD)
ThSIA(RD)

Direct Address to IRD Fall Setup Time
Direct Address to IRD Fall Hold Time
Status II NT ACK to IRD Fall Setup Time
Status IINTACK to IRD Fall Hold Time

0
25
0
25

0
15
0
15

[1,2]
[1,2]
[2]

58
59
60
61

TsCS(WR)
ThCS(WR)
'TsADD(WR)
ThADD(WR)

ICS to IWR Fall Setup Time
ICS to IWR Fall Hold Time
Direct Address to IWR Fall Setup Time
Direct Address to IWR Fall Hold Time

0
25
0
25

0
15
0
15

[2]

62
63
78
81

TsSIA(WR)
ThSIA(WR)
TdDSI(RDY)
TsIEI(DSI)

Status IINTACK to IWR Fall Setup Time
Status IINTACK to IWR Fall Hold Time
IDS Fall (INTACK) to IREADY Fall Delay
lEI to IDS Fall (INl ACK) Setup Time

0
25

0
15

82
83
84
85

ThIEI(DSI)
TdIEI(IEQ)
TdAS(IEO)
TdDSI(INT)

lEI to IDS Rise (INTACK) Hold Time
lEI to lEO Delay
lAS Rise or Status INTACK to lEO Delay
IDS Fall (INTACK) to liNT Inactive Delay

86
87
88
89

TdDSI(Wf)
TdDSI(Wr)
TdW(DRy)
TdRDI(RDY)

IDS Fall (IN1ACK) to IWAIT Fall Delay
IDS Fall (INTACK) to /WAIT Rise Delay

,196

/WR Rise to AS Fall Delay Time

/WAIT Rise to Data Valid Delay
IRD Fall (INTACK) to IREADY Fall Delay

40
20

50
40

[2]

[2]
[1,2]
[1,2]

250

300

[2]
[2]
[4]

0
60
60
200

40
40
170

40
300
40
300

35
175
35
175

/[4]
[4]

AC CHARACTERISTICS (Continued)
10 MHz·
Min
Max

16 MHzt
Min
Max

50
0

Symbol

Parameter

91
92
93
94

TsIEI(RDI)
ThIEI(RDI)
TdRDI(INT)
TdRDI(Wf)

lEI to /RD Fall (INTACK) Setup Time
lEI to /RD Rise (INTACK) Hold Time
IRD Fall (INTACK) to liNT Inactive Delay
IRD Fall (INTACK) to /WAIT Fall Delay

IRD Fall (lNTACK) to /WAIT Rise Delay
Pulsed IINTACK Low Width
Pulsed IINTACK High Width
lAS Rise to Pulsed IINTACK Fall Delay Time

TdRDI(Wr)
TwPIA1
TwPIAh
TdAS(PIA)

55
45
5

99
100
101
102

TdPIA(AS)
TdPIA(DRa)
TdPEA(DRn)
TdPIA(DRz)

Pulsed IINTACK Rise to lAS Fall Delay Time
Pulsed IINTACK Fall to Data Active Delay
Pulsed IINTACK Rise to Dala Not Valid Delay
Pulsed liNTACK Rise to Data Float Delay

5
0
0

103
104
105
106

TsIEI(PIA)
ThIEI(PIA)
TdPIA(IEO)
TdPIA(INT)

lEI to Pulsed IINTACK Fall Setup Time
lEI to Pulsed IINTACK Rise Hold Time
Pulsed liNTACK Fall to lEO Delay
Pulsed IINTACK Fall to/INT Inactive Delay

107
108
109
110

TdPIAf(RDY)
TdPIAr(RDY)
TdPIA(Wf)
TdPIA(Wr)

Pulsed liNTACK Fall to IREADY Fall Delay
Pulsed IINTACK Rise to /READY Rise Delay
Pulsed IINTACK Fall lo/WAIT Fall Delay
Pulsed IINTACK Fall to IWAIT Rise Delay

96
.97

200
40

170

35
175

300

50
0

'111'
113
114
115

TdSIA(INT)
TwRESI
TwRESh
TdRES(STB)

Status IINTACK Fall to IINl Inactive Delay
IRESET Low Width
IRESET High.width
IRESET Rise to IStrobe Fall

116
117
118
119

TdPC(BUSa)
TdPC(BRO)
TsBAK(PC)
ThBAK(PC)

PCLK Rise to Bus Active Delay
PCLK Rise to /BUSREO Delay
IBUSACK to PCLK Rise Setup rime
IBUSACK to PCLK Rise Hold Time

120
121
122
123

TwPCI
TwPCh
TcPC

npc

PCLK Low Width
PCLK High Width
PCLK Cycle Time
PCLK Fall Time

124
125
126
127

TrPC
TdPCr(UAS)
TwUASI
TdPCf(UAS)

PCLK Rise Time
PCLK Rise to IUAS Delay
IUAS Low Width
PCLK Fall to /UAS Delay

128
129
130
131

TdPCr(AS)
TwASI
TdPCf(AS)
TdAS(DSr)

PCLK Rise to lAS Delay
lAS Low Width
PCLK Fall to lAS Delay
lAS Rise to IDS Fall (READ) Delay

132
133
134
135

TdDS(PCr)
TwDSlr
TdPCf(DS)
TsDR(DS)

PCLK Rise to IDS Delay
IDS Lo",! Width (READ)

135

PCLK Fall to IDS Delay
Read Data to IDS Rise Setup Time

[4]

,50

Notes

60
200

50
170

300
40
40
300

200
35
35
175
200
140
40
40

60
60
40
40
10

10
20

35
35
100

26
26
61
10

10
30

5
25
25

30
30

25
25

30
30

25
25
25

90
30

25
25

[2J

[3]
35
35

[4]

200
170

[4]

[5]

[5]
[5,6]
[5]
[5J
[5,6]
[5]
[5.7]
[5]
[5,8]

[5]
[5J

197

AC CHARACTERISTICS (Continued)
10 MHz·
Min
Max

Symbol

Parameter

136
137
138
139

ThDR(DS)
TdPC(RW)
TdAS(RD)
TdPCr(RD)

Read Data to IDS Rise Hold Time
PCLK Rise to RI/W Delay
lAS Rise to IRD Fall Delay
PCLK Rise to fRD Delay

140
141
142
143

TwRDI
TdPCI(RD)
TsDR(RD)
ThDR(RD)

IRD Low Width
PCLK Fall to IRD Delay
Read Data to IRD Rise Setup Time
Re~d Data to IRD Rise Hold Time

144
145
146
147

TdPC(ADD)
TdPC(AD)
ThAD(PC)
TdPC(ADz)

PCLK Rise to Direct Address Delay
PCLK Rise to Address Delay
Address to PCLK Rise Hold Time
PCLK Rise to Address Float Delay

148
149
150
151

TdPC(ADa)
TsAD(UAS)
ThAD(UAS)
TsAD(AS)

PCLK Rise to Address Active Delay
Address to IUAS Rise Setup Time
Address to IUAS Rise Hold Time
Address to lAS Rise Setup Time

152
153
154
155

ThAD(AS)
TsW(PC)
ThW(PC)
TsRDY(pc)

Address to lAS Rise Hold rime
/WAIT to PCLK Fall Setup lime
/WAIT to PCLK Fall Hold Time
IREADY to PCLK Fall Setup Time

10
30
10

156
157
158
159

ThRDY(PC)
ThDW(PC)
TdAS(DSw)
TsDW(DS)

IREADY to PCLK Fall Hold Time
Write Data to PCLK Rise Hold Time
lAS Rise to IDS Fall (WRITE) Delay
Write Data to IDS Fall Setup Time

160
161
162
163

TwDSlw
ThDW(DS)
TdAS(Wf1)
TsDW(WR)

IDS Low Width (WRITE)
Write Data to IDS Rise Hold Time
lAS Rise to IWR Fall Delay

Write Data to /WR Fall Setup Time

164
165
166
167

TwWRI
ThDW(WR)
TdPC(WR)
TdPC(BUSz)

/WR Low Width
Write Data to IWR Rise Hold Time
PCLK Fall to /WR Delay
PCLK Rise to Bus Float Delay

Noles:
[1] Direct address is A l{AltB or AO{SCC{{DMA.
[2] The parameter applies only when {AS is not present.
[3] {Strobe is any of {DS, {RD, twR or Pulsed {INTACK.
[4] Clock-cycle dependent, 2TcPC + TwPCI + llPC + 55
[5] Parameter applies only while ISCC is bus master.
[6] Clock-cycle dependent, TwPCh + TfPC - 15.
[7] Clock-cycle dependent, TwPCl + TrPC - 15.
[8] Clock-cycle dependent, TcPC + TwPCh + TrPC - 10.
[9] Clock-cycle dependent, TcPC - 15.
[10] Clock-cycle dependent, TcPC - 10.
• Units in nanoseconds
16 MHz Timing is Preliminary

198

16 MHzt
Min
Max

0
25

25
25

135

25
0

25
40

40
0

0
45

50
40

Notes

[5]
[5]
[5,7]
[5]
[5,8J
[5]
[5]
[5]
[1,5]
[5]
[5]
[5]

20
20
20

10
10
10

[5]
[5J
[5J
[51

10
10
20
10

[5]
[5]
[5J
[5J

30
0
85
30

0
45
25

'[5]
[5]
[5,9]
[5,6J

90
30

70
25
55
25

[5,10]
[5,7]
[5,9]
[5,6]

55
25

[5,10]
[5,7)
[5]
[5J

30
30

25
40

ICS

Al/NIB
AO/SCCl/DMA

IINTACK

(Status)

lAS

RlIW

IDS

ADO-AD15
",*---'(' 8 } - - . - f

IWAITIIRDY
(Wait)

IWAITIIRDY
(Ready)

Figure 28. Multiplexed IDS Read Cycle

199

ICs

Al/NIB
AOISCClIDMA

IINTACK
(Status),

----'

lAS

RI/W

IDS

AOO-AD15

/wArrI/ROY
(Wait)

/wArT/IRDY
(Ready)

Figure 29. Multiplexed IDS Write Cycle

200

ICS

A1IA//B

AO/SCCIIOMA

IINTACK
(Status)

lAS

IRO
~--------~~I}---------~ ~----~

AOO-A015

~------~~r-------~
IWAITIIROY
(Wait)

IWAITIIROY
(Ready)

Figure 30. Multiplexed IRD Read Cycle

201

ICS

Al/NIB
AOISCClIDMA

IINTACK
(Status)

lAS

twR

~--------~~,}---------~
ADO-AD15

twAITIIRDY

(Wait)

twAITIIRDY
(Ready)

Figure 31. Multiplexed IWR Write Cycle

202

ICS

(

®-~ ~-®

Al/A1/B
AO/SCClIDMA

(

®-~ ~-®
IINTACK
(StatUS)

®-~ ~-®
RlIW

~~ ~-®
IDS

AOO-AD15

®- ..

r-------

f-~

-@-

--@liNT

-@--

(Wait)

/
f-@Figure 40. Non-multiplexed IRD Status INTACK Cycle

211

IINTACK
(Pulsed)

t-------{!

~-----t

ADO-AD15

IWAITIIRDY
(Ready)

IWAITIIRDY
(Wail)

lEI

lEO

liNT

Figure 41. Non-multiplexed Pulsed INTACK Cycle

212

t----{!97r~---'~

C/)

1=
0

>--

~f
!::'!.
~

>-oil
~~

!::

!!l

I-

213

I®

'i"'"

(i)

.......

- f+ r--@
~

IDS
131

133

@- '--

RlIW

/
I--@

~
'-./

140

@>--

139

)

Al.AO

I-~

~ ~ i-'-

151

'-./

,,--

I--@

r-.

r-~
*-

lWa~I!RDY

(Watt)

-f..@

153

/Wait/IRDY
(Ready)
ISS

,'BUSACK

IRD

AD1S-0

.)
@- I-

Figure 46. Z16C35 Memory Read

217

Tl
PCLK

IUAS

I
-

~w '"\
.

,,'

\..-...J

"~ ~~L-I \
Lp'
'-'

"
~
~~

T3
~

lAS

'--f-'

i@- ~~r--"

159

IDS

161

-I

r'-

RI/W

163

IWR

~-@

~
15
~~ ~~

K=
-

)
--@

@- ~

!WaitlIROY
(Ready)

~f-@l

153

!WaitlIROY
(Wait)
155

)

@>- I- ~ ~

Figure 47. Z16C35 Memory Write

218

'@-~

152

IBUSACK

-I

f-@ f- ~~H

)

Al.AO

AD15-O

165

PCLK

/wail/IRDY

(Ready)

/wail/IRDY

(Wait)

Figure 48. Wait and Ready Timing

219

POLK

/UAS

lAS

IDS

RlIW

IRD

IWR

Al,AO

AD15-O

Figure 49. BUS Release

220

AC CHARACTERISTICS
General Timing
PClK

IRTxC, fTAxC
(Receive)

-------'1

AxD

/SYNC
(Exlerna9

----'
TRxC, RTxC
(Transmit)

TxD

(~~
IRTxC

-~J--;_----')(~

~----~ ~_'0~_-_- -_-_~~.~~~----------------------------

_______' _________

___

\~-~

fTRxC - - - - , \ ' - -_ _

ICTS,IDCD

______________

\__.--.JI

---JI

~..----""'"'\_ _

~ ,
--'~~

~-------------------------

/SYNC
(Input)

'-----

Figure 50. Z16C35 General Timing

221

AC CHARACTERISTICS
General Timing

Symbol

Parameter
to IRxC
to /AxC
to IRxC
to IRxC

10 MHz'
Min
Max

16MHzt
Min
Max

0
150

150

-200
5TcPC
0

-100
5TcPc'
0

1
2
3
4

TsRXD(RXCr)
. ThRXD(RXCr)
TsRXD(RXCf)
ThRXD(RXCf)

5
6
7
8

TsSY(RXC)
ThSY(RXC)
TsTXC(PC)
TdTXCf(TXD)

{SYNC to {RxC Rise Setup Time
ISYNC to RxC Rise Hold Time
/TxC to PCLK Setup Time
/TxC Fall to TxD Delay (x1 mode)

9
10
11
12

TdTxCr(TXD)
TdTXD(TRX)
TwRTXh
TwRTxl

/TxC Rise t9 TxD Delay (x1 mode)
TxD to /TRXC Delay (Send Clock Echo)
IRTxC High Width
{RTxC Low Width

150
150

13
14
15
16

TcRTX
TcRTXX
TwTRXh
TwTRXI

{RTxC Cycle Time (RxD, TxD)
Crystal Oscillator Period
/TRxC High Width
/TRxC Low Width

400
100
150
150

{TRxC Cycle lime (RxD, TxD)
IDCD or ICTS Pulse Width
ISYNC Pulse Width

200

17 TcTRX
18 TwEXT
19 . TwSY

RxD
RxD
RxD
RxD

Rise Setup Time (x1 mode)
Rise Hold Time (x1 mode)
Fall Setup Time (x1 mode)
Fall Hold Time (x1 mode)

400
200

[1]
[1]
[1,51
[1,5]

o .

150

150
200

85
80

80
244
100

80
80
244
.70
70

[1]
[1]
[2,4]
[21
[2,5]
[6]
[6]

80
1000

Notes

1000

[6,7]
[3]
[6]
[6]
[6,7]

Notes:
[1) /RxC is /RTxC or (fRxC, whichever is supplying the receive clock.
. [2) (fxC is /TRxC or /RTxC, whichever is supplying the transmit clock.
[3) Both /RTxC and /SYNC have 30 pf capacitors to grownd connected to them.
.
[4J Parameter applies only if the data rate is one-fourth the PCLK rate. In all other cases, no phase relationship between /AxC and PCLK or{fxC and
PCLK is required.
.
[5] Parameter applies only to FM encoding/decoding.
[6] Parameter applies only for transmitter and receiver; DPLL and baud rate generator requirements are identical to case PCLK requirements.
[7) The maximum receive or transmit data rate is qna-fourth PCLK.
• Units in nanoseconds.
t 16MHz TIming is preliminary

r
222

AC CHARACTERISTICS
System Timing
IRTxC, ITRxC
(Receive)

ISYNC
(Output)

liNT

IRTxC,lTRxC
(Transmit)

liNT

ICTS,IDCD

ISYNC
(Input)

K
K

liNT
5

Figure 51. Z16C35 System Timing

223

AC CHARACTERISTICS
System Timing

Symbol

Parameter

TdRXC(SY)
TdRXC(INT)
TdTXC(INT)
TdSY(INT)
TdEXT(INT)

IRxC Rise to ISYNC
RxC Rise to liNT Valid Delay
nxc Fall to liNT Valid Delay

2
3
4
5

ISYNC Transition to liNT Valid Delay
IDCD or ICTS Transition to/INT Valid Delay

Notes:
[1] IAxC is /RTXC or {TRxC, whichever is supplying the receive clock.
[2] {TxC is {TRxC or IRTxC, whichever is supplying the transmit clock.

16MHz Timing is preliminary

tt Units equal to TcPc.

224

10MHz
Min
Max

16 MHzt
Min
Max

10
6
2

16
10
6
6

10
6
2

6
6

Notestt

III
[IJ

PRELIMINARY PRODUCT SPECiFICATION

~ZiIill

Z16C50
DDPLL DUAL DIGITAL PHASE LOCKED
Loop MICROCONTROLLER
FEATURES
_ Two independent Digital Phase Locked Loops in one
package.

Synchronous status output

Accept Code Violation input

_ 10 MHz and 20 MHz Clock operation
_ Implemented in 1.61! CMOS technology
-

Selectable clock rate, clock sampling edge, and data
decoding.

28-pin DIP package

GENERAL DESCRIPTION
The 16C50 DDPLL is a fully static CMOS device that packs
two independent Digital Phase Locked Loops, with separate controls for selecting the decoding mode, clock rate,
and synchronization edge, in one integrated package
(Figure 1). The only common input between the two phase
locked loops is IRESET ( I denotes active low signal).

EDGE

MODE

The DDPLL is used in many communication applications
requiring detection and extraction of clock from data. 1\
can be used together with Serial Communication Controllers to allow operation at higher data rates. The data rate
is programmable at 1/8, 1/16, or 1/32 clock rate. The
DDPLLis offered in two speed grades: 1OM Hz and 20MHz
maximum clock speed, which translates to a maximum
data rate of 1.25 Mbps and 2.5 Mbps, respectively.

RATE
VDD

IRESET

NlC

MODE1B

MODE1A

MODEOB

MODEOA

MISSEDB

MISSEOA

RATE1B

ClKOUT

ClK

RATE1A

RATEOB

RATEOA

VOO

VSS
MISSED

DATA

EOGEOB

EOOEOA

ACVB

ACVA
OATM
ClKOUTA
ACV

IRESET

EOGE1B

EOGE1A

ClKA

DATAB
CLKOUTB
ClKB
N/C

Note: Power connections follow
conventional descriptions below:
Connection Circuft

Device

Power

Vee

V""

Ground

GND

Vss

Figure 1. DDPLL Block and Pin Diagrams

225

PIN DESCRIPTION'
The following is a list of DDPLL pins and their descriplions.
"A" and "B" at the end of pin names designate the signal
connecting to the A- or B-channel of the DDPLL.
ACVA, ACVB. Accept Code Violation (input, active HIGH).
The ACV signal is used to control the response of the
DDPLL to code violations present in the received data
stream.
CLKA, CLKB Clock. Input (input, active HIGH). The Clock
runs at 8-, 16-, or 32-times the received data rate and is
used by the DDPLL to generate the CLKOUT signal.
CLKOUTA, CLKOUTB. Clock Output( output, active HIGH).
CLKOUT is the recovered clock for the receive data
stream. The receiver should use this clock to sample and
decode the received data.
DATAA, DATAB. Receive Data (input, active HIGH). The
DATA signal is the received data stream that the DDPLL is
attempting to synchronize with. The DDPLL will provide the
CLKOUTsignal for use by a receiver attempting to decode
this data stream.

select which edge is used by the DDPLL to acllieve alld
maintain synchronization.
MISSEDA, MISSEDB. Clock Missed(output, active HIGH).
MISSED signal is activated when the DDPLL detects
miSSing edge(s) in the data stream.
MODEOA, MODEOB, MODE1A, MODE1B. DDPLL Mode
Controls (input, active HIGH). MODEO and MODE1 are
used to control the mode of operation of the DDPLL with
respect to the encoded format of the incoming data.
RATEOA, RATEOB, RATE 1A, RATE1B. Clock Rate Selects (input, active HIGH). RATE inputs are used to select
the data rate divisor to generate the DDPLL clock.
{RESET. Reset (input, active LOW). This input resets the
DDPLL to a known state and must be active for at least two
cycles of the slowest CLK signal. This is the only common
input to the two Digital Phase Locked Loops.
VDD. +5V supply.
VSS. OV (GND) supply.

EDGEOA, EDGEOB, EDGE1A, EDGE1B. Adjust/Synchronize Edge Controls (input, active HIGH). These Signals

FUNCTIONAL DESCRIPTION ,
Prior to device operation, the control inputs of the DDPLL
must be set to known states corresponding to the desired
mode of operation.
Data decoding format is programmed via MODEO and
MODEl inputs. Table 1 demonstrates the truth table for
these inputs. NRZ, NRZI, FMl (biphasemark), FMO(biphase
space) and Manchester (biphase level) formats are supported. MODE1-MODEOof LOW-LOW disables the DDPLL,
setting the CLKOUT output Law. In NRZ format, a "1" is
represented by a HI<;;H level and a "0" is represented by
a LOW level. In NRZI format, a "1" is represented by no
change in level and a "0" is represented by a chanqe in
level. A MODE1-MODEO of LOW-HIGH selects the NHZ or
NRZI decoding modes

Table 1. Mode Selection Truth Table
MODEl

MODEO

Selected Mode

0
0

1
1

Disable/Sync
NRZ/NRZI
Biphase-Mark/Space
Biphase-Level

226

1
1

In both of these mopes, transitions on the input may only
occur on bit cell boundaries and the DDPLL provides
CLKOUT to match these bit cell boundaries In FM1
(biphase mark) and FMO (biphase space) formats, a
transition occurs at the beginning of every bit cell. In
addition to this, in FM1, a "1" is represented by an additional transition at the center of the bit cell and a "0" is
represented by the absence of such transition. In contrast,
in FMO, a "0" is represented by an additional transition at
the center of the bit cell and a "1" is represented by the
absence of such transition. MODE1-MODEO of HIGHLOW selects the biphase-mark (FM1) or biphase-space
(FMO) modes.
.

In Manchester (biphase level) mode, a transition occurs at
the center of every bit cell. If the bit is "1", the transition is
HIGH to LOW, and if the bit is "0", the transition is LOW to
HIGH. Additionally, a LOW to HIGH transition occurs at the
boundary of a "1" bit. A HIGH-HIGH selects the Manch-

Data

ester (biphase level) mode. Figure 2 demonstrates an
example of a seriat data stream with its corresponding
encoded waveforms in NRZ, NRZt, FM 1, FMO, and Manchester modes.

NRZ

NRZI

FM1

FMO

Manchester

Figure 2. Data Decoding Formats

Clock rate is programmed through RATE1-RI\TEO
inputs. Clock rate can be set for 8-, 16-, or 32-times the
data rate With maximum clock operation of 20MHz in 8X
mode, data rates of 2.5Mbps is achieved. Table 2 illustrates clock rate divisor's truth table. Note that RATE1RATED of HIGH-HIGH is illegal. All DDPLL inputs (with the
exception of /RESET) are sampled by the rising edge of
CLK and all outputs change state in response to the rising
edge of the CLK signal The two DPLLs are completely
independent except for the /RESET input.
Table 2. Data Rate Divisor Truth Table

RATE 1

RATEO

Data Rate Divisor

0
0

1
1

32X Clock Mode
16X Clock Mode
8X Clock Mode
Not Allowed

1
1

EDGE1 and EDGEO select the edge(s) in the receive data
stream used by the DDPLL to achieve and maintain synchronization Table 3 shows how the rising edge, the falling
edge, or both edges of the receive data stream can be

used for synchronization. A HIGH on both EDGE inputs
inhibits the DDPLL from using either edge for synchronization. As far as the DOPLL is concerned, edges that are not
used to achieve or maintain synchronization are not present. They are reported as missing edges when they occur
where an edge is expected
Table 3. Clock Edge Selection Truth Table
EDGE1

EDGEO

Selected Edge

0
0

1
1

Both Edges
Rising Edge
Falling Edge
Adjust/Sync Intlibit

1
1

The response of the DDPLL to code violations present in
the received data stream can be controlled using tile ACV
input. This signal is ignored in the NRZ/NRZI mode, where
code violations are not possible In all other modes, however, a HIGH on tile ACValiows the DDPLL to recognize an
Isolated code violation without losing synchronization.
Code violations are then used by the receiver for synchronization.
•

227

When the DDI?LL detects missing edge(s) in the data
stream, it activates the MISSED output. If the DDPLL is
configured to accept code violations, two consecutive
code violations will activate the MISSED output. If the
DDPLL is configured not to accept code violations, this
output is activated on any missing clock. MISSED will
never be activated in the NRZ/NRZI modes of operation, as
code violations are not possible in these modss. The
DDPLL re-enters the sync-up phase when the MISSED
output is activated.
'

The CLKOUT is the recovered Clock for the receive data
stream, The receiver uses this clock to sample and decode
the received data.
The only common Input between the two phase locked
loops in the DDPLL is the /RESET input. This Signal must
remain active for at least two cycles of the slowest CLK
signal and resets the device to a known state: MISSED=LOW
and CLKOUT = LOW, Synchronization attempt begins once
the /RESET signal is deactivated.

ABSOLUTE MAXIMUM RATINGS
\

Voltages on all pins
with respect to GND .",,,,,, •. ,,,,,,,,,,,,,,,,,.,,.,,-0.3V to +7.0V
Operating Ambient
Temperature """""",,,,,,,,,,,,,,,.See Ordering Information
Storage Temperature """"""""""",,,,,,,-65°C to +1500C

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rgting only; operation of the device at
any condition above those indicated in the operational
sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.

STANDARD TEST CONDITIONS
The DC Characteristics and CapaCitance section below
apply for the following standard test conditions, unless
otherwise noted (Figure 3). All voltages are referenced to
GND. Positive current flows into the referenced pin, Standard conditions are as follows:

1.73K

+4.5 V < Vee < +5.5 V
GND =0\1
TA as specified in Ordering Information

50pF

Figure 3. Standard Test Load

DC CHARACTERISTICS
,
Symbol

Parameter

Min

Max

Units

V1H
VIL
VOl.
IlL
lee
CIN
C OUT

Input High Voltage
Input Low Voltage
Output High Voltage
Input Leakage Current
Supply Current
Input CapaCitance
Output Capacitance

2,0
-0.3
2,4

Voo+0.3
08

V
V
V

±10
40
10
15

tJ.A

Notes:

I, VDD=5V ±IO% unless otherwise specified, over specified temperature range.
2. Capacitance values specified at f= '!MHz.

228

mA
pf
pf .

Conditions

10H = -1.6mA
0.4V S VIN S 2.4V
VOO =5,VIH=4.8V, VIL=0.2V
Unmeasured pins returned to GND .
Unmeasured pins returned to GND

IRESET

ClK

Control ----------------~
Inputs _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- 1

ClKOUT

Missed

Figure 4. DDPLL Timing Diagram

Figure 2 illustrates the DDPlUimings. "Control Inputs" in Figure 4 refer to MODE1-MODEO, RATE1-RATEO, EDGE1EDGEO, and ACV inputs.

AC CHARACTERISTICS

Timing

Symbol

Parameter

Z16C5010
Min
Max

Z16C5020
Min
Max

Units

T2
T3
T4

TwRESI
TsRES(ClK)
TwClKh
TwClKI

{RESET lOW Width
{RESET to ClK Setup Time
ClK HIGH Time
elK low Time

2TcC
15
40
40

2TcC
15
20
20

ns
ns
ns

T5
T6
T7
T8
T9

TcC
TsIN(ClK)
ThIN(ClK)
TdClK(OUT)
TdClK(MIS)

ClK Cycle Time
Input Valid to ClK Setup Time
Input Valid to ClK Hold Time
ClK to ClKOUT Delay Time
ClK to MISSED Delay Time

100
15
10

50
15
10
30

ns
ns
ns
ns
ns

Notes

1,2,3
1,2,3

229

230

~ZiIm

PRODUCT SPECIFICATION

Z5380 SCSI
SMALL COMPUTER SYSTEM INTERFACE
FEATURES
_

Compatible 5380 pinout

Arbitration support

Low power CMOS

•

DMA or programmed I/O data transfers

Asynchronous interface, supports 1.5 MB/s

Supports Normal or Block Mode DMA

Direct SCSI Bus interface with on-board 48 mA drivers

Memory or I/O Mapped CPU interface

Supports Target and Initiator roles

GENERAL DESCRIPTION
The Z5380 SCSI (Small Computer System Interface) controller is a 40-pin DIP or 44-pin PLCC CMOS device
(Figure 1). It is designed to implement the SCSI protocol as
defined by the ANSI X3.131-1986 standard, and is fully
compatible with the industry standard 5380. It is capable'
of operating both as a Target and as an Initiator. Special
high-current open-drain outputs enable it to directly
interface to, and drive, the SCSI bus. The Z5380 has the
necessary interface hook-ups so the system CPU can
communicate with it like with any other peripheral device.
The CPU can read from, or write to, the SCSI registers
which are addressed as standard or memorymapped I/Os.

The Z5380 increases the system performance by minimizing the CPU interventionin DMA operations which the SCSI
controls. The CPU is interrupted by the SCSI when it
detects a bus condition that requires attention. It also
supports arbitration and reselection. The Z5380 has the
proper hand-shake signals to support normal and block
mode DMA operations with most DMA controllers
available (Figure 2).
Note: All Signals with a preceding front slash, "/", are active
Low, e.g.: BIIW (WORD is active Low); IBIW (BYTE is
active Low, only); INIIS (NORMAL and SYSTEM are both
active Low).

231

IOB7-/OBO,
IOBP

Interface
Control
Logic

CPUBUSI~

____

Data
Output
Register

Data
Input
Register

____

______

~'-

________________

__- .

Imerlace ~----'-r---~~----~------~~------------------~--~

DMA
07-00

Interrupt
Logic

Logic

Control
~egisters

Figure 1. Block Diagram

07-00

IOB7-DBO, IDBP

A2.-AO

lACK
IATN

nOR.
IIOW

IBSY

ICS

IMSG

IRESET
10ACK
, 1E0P

Z5380

1110
ClIO
/REO

ORO

IRST

.REAOY

ISEL
Note: Power connections !oRow
conventional descriptions below:

IRQ

VDD

GNO

Figure 2. Logic Symbol

232

Connection Circuit
Power

Va;

Ground

GND

Device

Voo
Vas

IOB7

IOB6

IOB5

1083

10B4

1082

•

10B3

IOB1

IOB2

lOBO

!DB1

10BP

VOO

lOBO

GNO

10BP

VOO

GNO

ISEL

/lOW

IBSY

IRESET

lACK

IEOP

IATN

10ACK

IRST

1110
CliO

Z5380
(Top View)

NlC

GNO

AO
IIOW

ISEL

IBSY

IRESET

lACK

IEOP

10ACK

IATN
22 23 24 25 26 27 28

REAOY
IIOR
IRO

IMSG

ORO

IREO

ICS

Note: Power connections follow
Conventional descriptions below
Connection

Circuit

Device

Power
Ground

Vee
GND

Voo
VSS

Figure 3. Pin Diagrams

PIN DESCRIPTION
Microprocessor Bus
Figure 3 shows the pins and their respective functions for
both the DIP and PLCC.
A2-AO. Address Lines(lnput). Address lines are used with
ICS, IIOR, or IIOW to address all internal registers.

07-00. Data Lines(Bidirectional, three-state, Active High).
Bidirectional microprocessor data bus lines DO is the
Least Significant Bit of the bus. Data bus lines carry data
and commands to and from the SCSI.

IEOP. End of Process (Input, Active Low). IEOP is used to
ICS. Chip Select (Input, Active Low). This signal, in conjunction with /lOR or II OW, enables the internal register
selected by A2-AO, to be read from or written to.

terminate a DMA transfer. If asserted during a OMA cycle,
the current byte will be transferred, but no additional bytes
will be requested.

IDACK. DMA Acknowledge (Input, Active Low). 10ACK
resets ORO and selects the data registerfor input or output
data transfers. 10ACK is used by OMA controller instead
of ICS

/lOR. I/O Read (Input, Active Low). IIOR is used in con-

ORO. DMA Request(Output, Active High) ORO indicates
that the data register is ready to be read or written DRO is
asserted only if OMA mode is set in the Command Register.
DRO is cleared by 10ACK.

IIOW. I/O Write (Input, Active Low). II OW is used in conjunction with ICS and A2-AO to write an internal register.
It also selects the Output Data Register when used
with 10ACK.

junction with ICS and A2-AO to read an internal register.
It also selects the Input Data Register when used
with 10ACK.

233

PIN DESCRIPTION (Continued)
IRO. Interrupt Request (Output. Active High). IRQ alerts
a microprocessor of an error condition or an event
completion
READY. Ready (Output, Active High). Ready is used to
control the speed of Block Mode DMA transfers. This
signal goes active to indicate the chip is ready to sendl
receive data and remains Low !lfter a transfer until the last
byte is sent or until the DMA Mode bit is reset.
IRESET. Reset (I nput,' Active Low) IRESET clears all registers. It has no effect upon the SCSI IRST signal.

IOB7-/OBO, 10BP. Data Bus Bits, Data Bus Parity Bit
(Bidirectional" Open-drain). These eight data bits
(IOB7-/DBO), plus a parity bit (lDBP) form Ihe data bus.
IDB7 is the most significant bit (MSB) and has the highest
priority during the Arbitration phase. Data parity is odd.
Parity is always generated and optionally checked. Parity
is not valid during Arbitration.
1110. Input/Output (Bidirectional, Open-draJn). 1/0 is a signal driven by a Target which controls the direction of data
movement on the SCSI bus. True indicates input to Ihe
Initiator. This Signal is also used to distinguish between
Selection and Reselection phases.

SCSI Bus
The following signals are all bidirectional, active Low,
open-drain, with 48 mA sink capability. All pins interface
directly with the SCSI bus.
lACK. Acknowledge (Bidirectional, Open-drain, Active
Low). Driven by an Initiator, lACK indicates an
acknowledgement for a IREQ/IACK data-transfer handshake. In the Target role, lACK is received as a response
to the IREQ signal.
IATN. Attention (Bidirectional, Open-drain, Active Low):
Driven by an Initiator, received by the Target, IATN indicates
an Attention condition.
IBSY. Busy (Bidirectional, Open-drain, Active Low) This
signal indicates that the SCSI bus is being used and can
be driven by both the Initiator and the Target device

IMSG. Message (Bidirectional, Open-drain, Active Low).
ThiS Signal is driven by the Target during the Message
phase. This signal is received by the Initiator.
IREO. Request (Bidirectional, Open-drain, Active Low).
Driven by the Target and received by the Initiator, this
signal indicates a request for a IREQI/ACK data-transfer
handshake.
.
IRST. SCSI Bus Reset (Bidirectional, Open-drain, Active
Low). This signal indicates a S.CSI bus Reset c6nditlon.
ISEL. Select (Bidirectional, Open-drain, Active Low). This
signal is used by an Initiator to select a Target, or by a
Target to reselect an Initiator.

Power Signals:
GND. Ground (OV)

CliO. Control/Data (Bidirectional, Open-drain). Driven by
the Target and received by the Initiator, CliO indicates
whether Control or Data information is on the Data Bus
. True indicates Control.

VDD. VDD Supply (+5V)

FUNCTIONAL DESCRIPTION
The Z5380 Small Computer System Interface (SCSI) has a
set of eight registers that are controlled by the CPU. By,
reading and writing the appropriate registers, the CPU
may initiate any SCSI Bus activity or may sample and
assert any signal on the SCSI Bus. This allows the user to

234

implement all or any olthe SCSI protocol in software. These
registers are fead (written) by activating ICS with an
address· on A2-AO and then issuing an liaR (lIOW) pulse
This section describes the operation of the internal registers (Table 1),

Table 1. Register Summary
A2
0
0

Address
A1
AO

R/W

0
0 \ 0
0
1

0
1
0

R
W
R/W
R/W

Current SCSI Data
Output Data
Initiator Command
Mode

1
0
0
0

1
0
0
1

R/W
R
W
R

Target Command
Current SCSI Bus Status
Select Enable
Bus and Status

1
0
0
1
1

W
R
W
R
W

0
1
1
1

1
1
1
1

Address: 0

(Read Only)

Imloolool~loolool~lool

Start DMA Send
Input Data
Start DMA Target Receive
Reset Parity/Interrupt
Start DMA Initiator Receive

The data registers are used to transfer SCSI commands,
data, status, and message bytes between the microprocessor Data Bus and the SCSI Bus The Z5380 does not
interpret any information that passes through the data
registers. The data registers consist of the transparent
Current SCSI Data Register, the Output Data Register, and
.
the Input Data Register.
Current SCSI Data Register. Address 0 (Read Only). The
Current SCSI Data Register (Figure 4) is a read-only
register whicll allows the microprocessor to read, the active
SCSI Data Bus. This is accomplished by activating /CS
with an address on A2-AOof 000 and issuing an /IOR pulse.
II parity checking is enabled, the SCSI Bus parity is
checked at the beginning of the read cycle This register
is used during a programmed I/O data read or during
Arbitration to check for higher priority arbitrating devices.
Parity is not guaranteed valid during Arbitration.
Output Data Register. Address 0 (Write Only) The Output
Data Register (Figure 5) is a write-only register that is used
to send data to the SCSI Bus. This is accomplished by
either using a normal CPU write, or under DMA control, by
using /IOW and /DACK. This register also asserts the
proper 10 bits on the'SCSI Bus during the Arbitration and
Selection phases.

IDB2
IDB3
IDB4
IDB5
IDB6
IDB7

Figure 4. Current SCSI Data Register

Address: 0

Data Registers

lOBO
IDBl

(Write Only)

Imloolool~loolool~lool

lOBO
IDBl
IDB2
IDB3
IDB4
IDB5
IDB6
IDB7

Figure 5. Output Data Register

Initiator Command Register. Address 1 (Read/Write). The
Initiator Command Register (Figures 6 and 7) are read and
write registers which assert certain SCSI Bus signals,
monitors those signals, and monitors the progress of bus
• arbitration. Many of these bits are significant only when
being used as an Initiator; however, most can be used
during Target role operation

235

FUNCTIONAL DESCRIPTION (Continued)
Address: 1

(Read Only)

1071061051041031021011001

Assert Oata Bus
Assert/ATN
Assert/SEL
Assert/BSY
Assert/ACK

Lost Arbitration

Bit 1. AssertIATN. IATN may be asserted on the SCSI Bus
by setting this bit to a one (1) if the Target Mode bit (Mode
Register, bit 6) is False. IATN is normally asserted by the
initiator to request a Message Out bus phase. Note that
since Assert/SEL and Assert/ATN are in the same register,
a select with IATN may be implemented with one CPU
write. IATN may be deasserted by resetting this bit to zero.
A read of this register simply reflects the status of Ihis bit.
I

Bit 2. Assert ISEL. Writing a one (1) into ttlis bit position
asserts ISEL onto the SCSI Bus. ISEL is normally asserted
after Arbitration has been successfully completed. ISEL
may be disabled by resetting bit 2 to a zero. A read 01 this
register reflects the status of this bit.

Arbitration in Progress
Assert/RST

Figure 6. Initiator Command Register

Address: 1

(Wrfte Only) ,

1071061051041031021011001

~
L -_ _ _ _ _ _ _ _
L -_ _ _ _ _ _ _ _ _

Assert Data Bus
Assert/ATN
Assert/SEL
AssertlBSY
Assert/ACK

·0·
Test Mode
Assert/RST

Bit 3. Assert /BSY. Writing a one (1) into this bit position
asserts IBSY onto the SCSI Bus. Conversely, a zero resets
the IBSY SignaL Asserting IBSY indicates a successful
selection or reselection. Resetting this bit creates a BusDisconnect condition. Reading this register reflects
bit status.
Bit4. Assert/ACK Bit 4 is used by the bus initiator to assert
lACK on the SCSI Bus. In order to assert lACK, the Target
Mode bit (Mode Register, bit 6) must be False. Writing a
zero to this bit deasserts lACK. Reading this register
reflects bit status.
ait 5. "0" (Write Bit). Bit 5 should be written with a zero for
proper operation.
Bit 5. LA (Lost Arbitration - Read Bit). Bit 5, when active,
indicates that the SCSI detected a Bus-Free condition, '
arbitrated for use of the bus by asserting IBSY and its 10 on
the Data Bus, and lost Arbitration due to ISEL being
asserted by another bus device. This bit is active only
when the Arbitrate bit (Mode Register, bit 0) is active.

Figure 7. Initiator Command Register

The following describes the operation of all bits in the
Initiator Command Register:
Bit O. Assert Data Bus. This bit, when set. allows the contents of the Output Data Register to be enabled as chip
outputs on the signals IDB7 -DBO. Parity is also generated
and asserted on IDBP.
When connected as an Initiator, the outputs are only
enabled if the Target Mode bit (Mode Register, bit 6) is 0,
the received signal 11/0 is False, and the phase signals
(CliO, 1110, and IMSG) match the contents of the Assert
CI/D, Assert 1110, and Assert/MSG in the Target Command
Register.
ThiS bit should also be set during DMA send operations.

236

Bit 6. Test Mode (Write Bit). Bit 6 is written during a test
environment to disable all output drivers, effectively removing the Z5380 from the circuit. Resetting this bit returns
the part to normal operation.
.
Bit 6. AlP (Arbitration in Process - Read Bit). Bit 6 is used
to determine if Arbitration is in progress. For this bit to be
active, the Arbitrate bit (Mode Register, bit 0) must Ilave
been set previously. It indicates that a Bus-Free condition
has been detected and thai the chip has asserted IBSY
and put the contents of the Output Data Register onto the
SCSI Bus. AlP will remain active until the Arbitrate bit
is reset.
Bit 7. Assert IRST. Whenever a one is written to bit 7 of the
Initiator Command Register, the IRST signal is asserted on
the SCSI Bus. The IRST signal will remain asserted until til is
bit is reset or until an external/RESE T occurs. After ttlis bit

is set (1), IRQ goes active and all internal logic and control
registers are reset (except for the interrupt latch and the
Assert /RST bit). Writing a zero to bit 7 of the Initiator
Command Register deasserts the IRST signal. The status
of this bit is monitored by reading the Initiator Command
Register.
.
Mode Register. Address 2(Read/Write). The Mode Register controls the operation of the chip. This register determines whether the Z5380 operates as an Initiator or a
Target, whether DMA transfers are being used, whether
parity is checked, and whether interrupts are generated on
various extemal conditions. This register is read to check
the value of these internal control bits (Figure 8).
Addre~:

(ReadlWrite)

I0710SID5ID4ID31021011001

Register. The control bit Assert Data Bus (Initiator Command Register, bit 0) must be True (1) for all DMA send
operations. In the DMA mode, /REQ and lACK are automatically controlled.
The DMA Mode bit is not reset upon the receipt of an lEap
signal. Any DMA transfer is stopped by writing a zero into
this bit location; hOljVever, care must be taken not to cause
ICS and IDACK to be active simultaneously.
Bit 2. Monitor Busy. The Monitor Busy bit, when True (1 ),
causes an interrupt to be generated for an unexpected
loss of IBSY. When the interrupt is generated due to loss of
IBSY, the lower six bits of the Initiator Command Register
are reset (0) and all signals are removed from the
SCSI Bus.
Bit 3. Enable IEOP Interrupt. The enable lEap interrupt bit,
when set (1), causes an interrupt to occur when the lEap
(End Of Process) signal is received from the DMA controller logic.

Arbitrate
OMAMode

Monitor IBSY
Enable IEOP Interrupt
Enable Parity Intenupt
Enable Parity Checking

Bit 4. Enable Parity Interrupt. The Enable Parity Interrupt
bit, when set (1), will cause an interrupt (IRQ) to occur if a
parity error is detected. A parity interrupt will only be
generated if the Enable Parity Checking bit (bit 5) is also
enabled (1).

Target Mode

Bit 5. Enable Parity Checking The Enable Parity Checking
bit determines whether parity errors are ignored or saved
in the parity error latch. If this bit is reset (0), parity is
ignored. Conversely, if this bit is set (1), parity errors
are saved.

Block Mode OMA

Figure 8. Mode Register

The following describ~s the operation of all bits in the
Initiator Command Register:
Bit O. Arbitrate. The Arbitrate bit is set (1) to start the
Arbitration process. Prior to setting this bit, the Output Data
Register should contain the proper SCSI device ID value.
Only one data bit should be active for SCSI Bus Arbitration.
The Z5380 waits for a Bus-Free conpition before entering
the Arbitration phase. The results of the Arbitration phase
is determined by reading the status bits LA and AlP
(Initiator Command Register, bits 5 and 6, respectively)
Bit 1. DMA Mode. The DMA Mode bit is normally used to
enable a DMA transfer and must be set (1) prior to writing
Start DMA Send Register, Start DMA Target Register, and
Start DMA Initiator Receiver Register. These three registers are used to start DMA transfers. The Target Mode bit
(Mode Register, bit 6) must be consistent with w~ites to
Start DMA Target Receive and Start DMA Initiator Receive
Registers; i.e., set (1) for a write to Start DMA Target
.Receive Register and set (0) for Start DMA Initiator Receive

BitS. Target Mode. The Target Mode bit allows tile Z5380
to operate as a SCSI Bus Initiator or Target. With this bit
reset (0), the Z5380 operates as 'a SCSI Bus Initiator.
Setting Target Mode bit to 1 programs the Z5380 to ope
ate as a SCSI Bus Target device. If the signals
IATN and lACK are to be asserted on the SCSI Bus, the
Target Mode bit must be reset (0). If the signals CIID, lila,
IMSG. and IREQ are to be asserted on the SCSI Bus. the
Target Mode bit must be set (1).
Bit 7. Block Mode DMA. The Block Mode DMA bit controls
the characteristics of the DMA DRQ-/DACK handshake.
When this bit is reset (0) and the DMA Mode bit is active (1),
the DMA handshake uses the normal interlocked handshake, and the rising edge of IDACK indicates the end of
each byte being transferred. In Block Mode operation.
when the Block Mode DMA bit is set (1 ) and DMA Mode bit
is active (1). the end of liaR or IIOW signifies the end of
each byte transferred and IDACK is allowed to remain
active throughout the DMA operation. Ready can then be
used to request the next transfer.

237
__ ,. ____... _ _ _ _ _ ......-................. , .• ' .... .0."""'." ..... '

_r,,-,.~--

,-.-

FUNCTIONAL DESCRIPTION (Continued)
Target Command Register. Address 3(Read/Write). When
connected as a target device, the Target Command Register (Figure 9) allows the CPU to control the SCSI Bus
Information Transfer phase and/or to assert /REO by writing this register. The Target Mode bit (Mode Register, bit
6) must be True (1) for bus assertion. to occur. The SCSI
Bus phases are described in Table 2.

device can use this register to determine ttle current bus
phase and to poll /REO for pending data transfers. This
register may also be used to determine why a particular
interrupt occurred. Figure 10 describes ttie Current SCSI
Bus Status Register.
Address: 4

(Read Only)

Iwlool~I~lool~I~lool
Address: 3

(ReadlWrHe)

Iwl~I~I~lool~I~loot

Assert VIO
Assert CliO
Assert/MSG

IMSG

AssertlREO

IREO

.X"

IBSY
IRST

Figure 9. Target Command Register
Figure 10. Current SCSI Bus Status Register
Table 2. SCSI Information Transfer Phases
Bus Phase
Data Out
Unspecified
Command
Message Out

Assert

1110

Assert
CliO

Assert
/MSG

0
0
0
0

0
0
1
1

0
1
0
1

0
0
1
1

0
1
0
1

Data In
Unspecified
Status
Message In

Select Enable Register. Address 4 (Write Only) The Select
Enable Register (Figure 11) is a write-only register wtlich is
used as a mask to monitor a signal 10 during a selection
attempt. The simultaneous occurrence of the correct 10 bit,
/BSY False, and /SEL True causes an interrupt. This interrupt can be disabled by resetting all bits in this register. If
the Enable Parity Checking bit (Mode Register, bit 5) is
active (1), parity is cllecked during selection.
Address: 4

(Write Only)

1071061051041031021011001
lOBO

When connected as an Initiator with DMA Mode bit True, if
the phase lines (1110, CliO, and /MSG) do not match the
phase bits in the Target Command Register, a phase
mismatch interrupt is generated when /REO goes aclive.
To send data as an Initiator, the Assert 1/10, Assert CliO,
and Assert IMSG bits must match the corresponding bits
in the Current SCSI Bus Status Register. The Assert /REO
bit (bit 3) has no meaning when operating as an Initiator.
Bits 4,5,6, and 7 are not used.
Current SCSI BuS Status Register. Address4(ReadOnly).
The Current SCSI Bus Register is a read-only register
which is used to monitor seven SCSI Bus control signals,
plus the Data Bus parity bit. For example, an Initiator

238

IDBl

IOB2
10Ba
10B4
1.-_ _ _ _ _ _ _ _ _

IOB5
IOB6
IOB7

Figure 11. ~elect Enable Register

Bus and Status Register. Address 5 (Read Only). The Bus
and Status Register (Figure 12) is a read-only register
which can be used to monitor the remaining SCSI control
signals not found in the Current SCSI Bus Status Registers
(/ATN and lACK), as well as six other status bits. The
following describes each bit of the Bus and Status Register
individually.
Address: S

(Read Only)

10710610sI041D31D21011001
lACK
IATN
BusyEnor

Phase Match
L - _ _ _ _ _ _ Interrupt Request Active
L-_ _ _ _ _ _ _ Parity Enor

L..-________

DMA Request

' - - - - - - - - - - - End of OMA

Figure 12. Bus and Status Register
Bit o. lACK. Bit 0 reflects the condition of the SCSI Bus
control signal lACK. This signal is nO'rmally monitored by
the Target device.
Bit 1. /ATN. Bit 1 reflects the condition of the SCSI Bus
control signal/ATN. This signal is normally monitored by
the Target device.
Bit 2. Busy Error. The Busy Error bit is active if an unexpected loss of the /BSY signal has occurred. This latch is
set whenever the Monitor Busy bit (Mode Register, bit 2) is
True and /BSY is False An unexpected loss of IBSY
disables any SCSI outputs and resets the DMA Mode bit
(Mode Register, bit 1).

Bit 5. Parity Error. Bit 5 is set if a parity error occurs during
a data receive or a device selection. The Parity Error bit can
only be set (1) if the Enable Parity Check bit (Mode
Register, bit 5) is active (1). This bit may be cleared by
reading the Reset Parityllnterrupt Register.
Bit 6. OMA Request. The DMA Request bit allows the CPU ,
to sample the output pin DRO. DRO can be cleared by
asserting IDACK or by resetting the DMA Mode bit (bit 1)
in the Mode Register. The DRO signal does not reset when.
a phase-mismatch interrupt occurs.
Bit 7. End of OMA Transfer. The End olOMA Transfer bitis
set if lEap, IDACK, and either liaR or II OW are simultaneously active for at least 100ns. Since the lEap signal can
occur during the last byte sent to the Output Data Register,
the IREO and lACK signals should be monitored to ensure
that the last byte has been transferred .. This bit is reset
when the DMA Mode bit is reset (0) in the Mqde Register.
Input Data Register. Address 6 (Read Only). The input
Data Register (Figure 13) is a read-only register that is
used to read latched data from the SCSI Bus. Data is
latched either during a DMA Target receive operation
when lACK goes active or during a DMA Initiator receive
when /REO goes active The DMA Mode bit (bit 1) must be
set before data can be latched in the Input Oata Register.
This register is read under DMA control uSing liaR and
IDACK. Parity is optionally checked when the· Input Data
Register is loaded.
Address: 6

(Read Only)

1071061051041031021011001

L..-______
L..-________
L..-__________

lOBO
IDB1
IDB2

1DB3
1DB4

L -_ _ _ _ _ _ _ IDBS

Bit 3. Phase Match. The SCSI signals IMSG, CIID, and
lila, represent the current information Transfer phase. The
Phase Match bit indicates whether the current SCSI Bus
phase matches the lower 3 bits of the Target Command
Register. Phase Match is continuously updated and is only
significant when operating as a Bus Initiator. A phase
matc~ is required for data transfers to occur on the
SCSI Bus.

IDBS

1DB7

Figure 13. Input Data Register

Bit 4./nterrupt Request ACTIVE. Bit 4 is set if an enabled
interrupt condition occurs. It reflects the current stateo! the
IRO output and can be cleared by reading the Resel Parityl
Interrupt Register

239

FUNCTIONAL DESCRIPTION (Continued)

DMA Registers
Three write-only registers are used to initiate all DMA
activity They are: Start DMA Send, Start DMA Target
Receive, and Start DMA Initiator Receive. Performing a
write operation into one of these registers starts tho desired type of DMA transfer. Data presented to the Z53BO on
signals D7 -DO during the register write is meaningless and
has no effect on the operation. Prior to writing these
registers, the Block Mode DMA bit (bit 7), the DMA Mode
bit (bit 1), and the Target Mode bit (bit 6) in the Mode
Register must be appropriately set. The individual registers are briefly described as follows:
Start DMA Send. Address 5 (Write Only). This register is
written to initiate a DMA send, from the DMA to the SCSI
Bus, for either Initiator or Target role operations. The DMA
Mode bit (Mode Register, bit 1) is set prior to writing this
register.
Start DMA Target Receive. Address 6 (Write Only) This
register is written to initiate a DMA receive - from the SCSI
Bus to the DMA, for Target operation only. The DMA. Mode
bit (bit 1) and the Target Mode bit (bit 6) in the Mode
Register must both be set (1) prior to writing this register.
Start DMA Initiator Receive. Address 7 (Write Only). This
register is written to initiate a DMA receive - from the SCSI
Bus to the DMA, for Initiator operation only. The DMA Mode
bit (bit 6) must be False (0) in the Mode Register prior to
writing this register.
Reset Parityllnterrupt. Address 7 (Read Only). Reading
this register resets the Parity Error bit (bit 5), the Interrupt
Request bit (bit 4), and the Busy Error bit (bit2) in the Bus
and Status Register.
On-Chip SCSI Hardware Support
The Z5380 is easy to use because of its simple architecture. The chip allows direct control and monitoring of the
SCSI Bus by providing a latch for each signal. However,
portions of the protocol define timings which are much too
quick for traditional microprocessors to control. Therefore,
hardware support has been provided for DMA transfers,
bus arbitration, phase change monitoring, bus disconnection, bus reset. parity generation, parity checking, and
device selection/reselection.
Arbitration is accomplished using a bus-free filter to
continuously monitor /BSY If /BSY remains inactive for at
least 1.2us, the SCSI Bus is considered free and Arbitration may begin Arbitration will begin if the bus is free, /SEL
is inactive, and the Arbitrate bit (Mode Register, bit 0) is

240

active. Once arbitration has begun (/BSY asserted), an
arbitration delay of 2.2us must elapse before the Data Bus
can be examined to determine if Arbitration is enabled
This delay is implemented in tile controlling software driver.
The Z5380 is a clockwise device. Delays such as bus-free
delay, bus-set delay, and bus-settle delay are implemented using gate delays. These delays may differ be. tween devices because of inherent prOcess variations, but
are well within the proposed ANSI X3.131 - 1986 specification.

Interrupts
The Z5380 provides an interrupt output (IRQ) to indicate a
task completion or an abnormal bus occurrence. Tile use
of interrupts is optional and may be disabled by resetting
the appropriate bits in the Mode Register or the Select
Enable Register.
When an interrupt occurs, the Bus and Status Register and
the Current SCSI Bus Status Register (Figures 12 and 10)
must be read to determine whictl condition created the
interrupt IRQ can be reset simply by reading the Reset
Parity/Interrupt Register or by an external chip reset
/RESET active for 2oons.
Assuming the Z5380 has been properly initialized, an
interrupt is generated if the chip is selected or reselecled;
if an /EOP signal occurs during a DMA transfer; if a SCSI
Bus reset occurs; if a parity error occurs during a data
transfer; if a bus phase mismatch occurs; or if a SCSI Bus
disconnection occurs.
Selection/Reselection Interrupt
The Z5380 generates a select interrupt if /SEL is active (0),
its device ID is True and /BSY is False for at least. a bussettle delay If 1//0 is active, this is considered a reselect
interrupt. The correct ID bit is determined by a match in the
Select Enable Register. Only a single bit match is required
to generate an interrupt. This interrupt may be disabled by
writing zeros into all bits of the $elect Enable Register.
If parity is supported, parity should be good during tile
selection phase. Theretore, if the Enable.f>arity bit (Mode
Register, bit 5) is active, the Parity Error bit is checked to
ensure that a proper selection has occurred. 1he Enable
Parity Interrupt bit need not be set for this interrupt to be
generated.
.

The proposed SCSI specification also requires that no
more than two device ID's be active during the selection
process. To ensure this, the Current SCSI Data Register is read.
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
14 and 15, respectively.

interrupt is disabled by resetting the Enable EOP Interrupt bit.
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register for this interrupt are
shown in Figures 16 and 17.
DO

lACK
IATN

lACK

Busy Error

IATN

Phase Maroh

Busy Error

Interrupt Request Active

Phase Match

Parity Error

Interrupt Request Active

DMARequest

Parity Error

EndofDMA

DMA Request
End of DMA

Figure 16. Bus and Status Register
Figure 14. Bus and Status Register

1011111 XlXlXlOlXl
D7

I~;

lolololxlxlxlolxl

~CIID

IMSG
L.-_ _ _ _ _ _

IMSG

L.-_ _ _ _ _ _ _

IREQ

IBSY
IRST

L.-_ _ _ _ _ _ _ _ _ _

IBSY
IRST

Figure 17. Current SCSI Bus Status Register
Figure 15. Current SCSI Bus Status Register

End Of Process (EOP) Interrupt
An End Of Process signal (EOP) which occurs during a
DMA transfer (DMA Mode True) will set the End of DMA
Status bit (bit 7) and will optionally generate an interrupt if
Enable EOP Interrupt bit (Mode Register, bit 3) is True. The
IEOP pulse will not be recognized (End 01 DMA bit set)
unless IEOP, IDACK, and either IIOR or flOW are concurrently active for at least 100 ns. DMA transfers can still
occur if fEOP was not asserted at the correct time. This

The End of DMA bit is used to determine when a block
transfer is complete. Receive operations are complete
when there is no data left in the chip and no additional
handshakes occurring. The only exception to this is receiving data as an Initiator and the Target opts to send
additional data for the same phase. In this IREO goes
active and the new data is present in the Input Data
Register. Since a phase-mismatch interrupt will not occur,
IREO and lACK need to be sampled to determine that the
Target is attempting to send more data.

241

FUNCTIONAL DESCRIPTION (Continued)
For send operations, the End of DMA bit is set when the
DMA finishes its transfers, but the SCSI transfer may still be
in progress. If connected as a Target, IREO and lACK
should be sampled until both are False. If connected as an
Initiator, a phase change interrupt is used to signal the
completion of the previous phase. It is possible for the
Target to request additional data for the same phase. In
this case, a phase change will not occur and both IREO
and lACK are sampled to determine when the last byte was
transferred.

Ixlxlxlxlxlxlxlxl

I~=
~C/ID
IMSG
IREQ

SCSI Bus Reset Interrupt
The Z5380 generates an interrupt when the IRST signal
transitions' to True. The device releases all bus signals
within a bus-clear delayofthis transition. Ttlis interrupt also
occurs after setting the Assert/RST bit (Initiator Command
Register, bit 7). This interrupt cannot be disabled. (Note:
IRST is not latched in bit 7 of the Current SCSI Bus Status
Register and is not active when this port is read. For this
case, the Bus Reset interrupt is determined by default.)
The proper values for the Bus and Status Register and the
-Current SCSI Bus Status Register are displayed in Figures
18 and 19, respectively.

lACK
IATN

IBSY
IRST

Figure 19. Current SCSI Bus Status Register

Parity Error Interrupt
An Interrupt is generated for a received parity error if tile
Enable Parity Check (bit 5) and the Enable Parity Interrupt
(bit 4) bits are set (1) in the Mode Register. Parity is
checked during a read of the Current SCSI Data Register
and during a DMA receive operation. A parity error can be
detected without generating an interrupt by disabling the
Enable Parity Interrupt bit and checking tile Parity Error
flag (Bus and Status Register, bit 5).

The proper values for the Bus and Status Register and ttle
Current SCSI Bus Status Register are displayed in Figures
20 and 21 , respectively.

Busy Error
Phase Match
Interrupt Request Active
Parity Error

lACK

DMA Request

IATN

EndofDMA

Busy ElTor
Phase Match

Figure 18. Bus and Status Register

Interrupt Request Active
Parity Error
DMA Request
EndofDMA

Figure 20. Bus and Status Register

242

lACK
IATN
Busy Error
Phase Match

IMSG

Interrupt Request Active

IREO

Parity Error

IBSY

DMA Request

IRST

EndofDMA

Figure 21. Current SCSI Bus Status Register

Bus Phase Mismatch Interrupt
lhe SCSI phase lines are comprised of the signals 1//0,
CliO, and /MSG. These signals are compared with the
corresponding bits in the Target Command Register:
Assert 1//0 (bit 0), Assert C//O (bit 1), and Assert /MSG
(bit 2). The comparison occurs continually and is reflected
in the Phase Match bit (bit 3) of the Bus and Status
Register. II the OMA Mode bit (Mode Register, !;lit 1) is
active and 8 phase mismatch occurs when {REQ transitions
from False to True, an interrupt (IRQ) is generated.

Figure 22. Bus and Status Register

IMSG
IREO

A phase mismatch prevents the recognition of /REQ and
removes the chip from the bus during an Initiator send
operation (/OB7·/0BO and /OBP will not be driven even
through the Assert Data Bus bit (Initiator Command Register, bitO) is active). This may be disabled by resetting the
OMA Mode bit (Note: It is possible lor this interrupt tooccur
when connected as a Target il another device is driving the
phase lines to a different state)
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
22 and 23, respectively.

IBSY
IRST

Figure 23. Current SCSI Bus Status Register

Loss of BSY Interrupt
If the Monitor Busy bit (bit 2) in the Mode Register IS active,
an interrupt is generated il the BSY signal goes False for at
least a bus-settle delay This interrupt is disabled by
resetting the Monitor Busy bit. Register values are displayed in Figures 24 and 25.

243

FUNCTIONAL DESCRIPTION (Continued)
07

reading the Currert SCSI Bu~ Status Register; however,
this signal is not latched and may not be present when this
port is read).

101010111 l 110101
X

lACK

IATN
Busy Error

Phase Match

' - - - - - - - - Intenupl Request Active

Parity Error

~--------- OMAR~e.

SCSI Bus Reset (/RST) Issued
If the CPU sets the Assert IRST bit (bit 7) 'in the Iniliator
Command Register, the IRST Signal goes active on the
SCSI Bus and an internal reset is performed. Again, all
internal logic and registers are cleared except for the IRO
interrupt latch and the AssertlRST bit (bil 7) in the Initiator
Command Register. The IRST signal will continue to be
active until the Assert lAST bit is reset or until a hardware
reset occurs.

EndofDMA

Figure 24. Bus and Status Register
07

lolololxlxlxlolol

I~::
~~/O

!MOO

IREO
IBSY

IRST

Figure 25. Current SCSI Bus Status Register

Reset Conditions
Three possible reset situations exist with the Z5380,
as follows:
Hardware Chip Reset
When the signal lAST is active for at least 200 ns, the Z5380
device is re-initialized and all internal logic and control
registers are cleared. This is a chip reset only and does not
create a SCSI Bus-Reset condition.
SCSI Bus Reset (/RST) Received
When a SCSIIRST signal is received, an IRQ interrupt is
generated and a chip reset is performed. All internal logic
and registers are cleared, exceptforthe IRO interrupt latch
and the Assert IRST bit (bit 7) in the Initiator Command
Register. (Note: The IRST Signal may be sampled by

244

Data Transfers
Data is transferred between SCSI Bus devices in one of
four modes (Reference Figures 26-41):
1.
2.
3.
4.

Programmed 110
Normal DMA
Block Mode DMA
Pseudo DMA

The following sections describe these modes in detail
(Note:. For all data transfer operations, /DACK and ICS
should never be active simultaneously).
Programmed I/O Transfers
Programmed 1/0 is the most primitive form of data transfer
The IREO and lACK handshake signals are individually
monitored and asserted by reading arid writing the appropriate register bits. This type of transfer is nor,mally used
when transferring small blocks of data such as command
blocks or message ,and status bytes. An Initiator send
operation would begin by selting the CliO, 1/10, and IMSG
bits in the Target Command Registerto the correct state so
that a phase match exists. In addition to the phase match
condition, it is necessary for the Assert Data Bus bit
(Initiator Command Register, bit 0) to be True and the
received 1/0 signal to be False for the Z5380 to send data
For each transfer, the data is loaded into the Output Data
Register. The CPU then waits forthe IREO bit (Current SCSI
Bus Status'Register, bit 5) to become active. Once IREO
goes active, the Phase Match bit (Bus and Status Register,
bit 3) is checked and the Assert lACK bit (Initiator Command Register, bit 4) is set. The IRtO bit is sampled until
it becomes False and the CPU resets the Assert lACK bit
to complete the transfer.
Normal DMA Mode
DMA transfers are normally used for large block translers.
The SCSI chip outputs a DMA request (ORO) whenever it
is ready for a byte transfer. External DMA logic uses thjs

DRO signal to generate IDACK and an IIOR or an IIOW
pulse to the Z5380. DRO goes inactive when IDACK is
asserted and IDACK goes inactive some time after the
minimum read or write pulse width. This process is repeated for every byte. For thismode,/DACK should not be
allowed to cycle unless a transfer is taking place.
Block Mode DMA
Some popular DMA Controllers, such as the 9517A, provide a Block Mode DMA transfer. This type of transfer
allows the DMA controller to transfer blocks of data without
relinquishing the use of the Data Bus to the CPU after eaeh
byte is transferred; thus, faster transfer rates are achieved
by eliminating the repetitive access and release of the CPU
Bus. If the Block Mode DMA bit (Mode Register, bit 7) is
active, the Z5380 begins the transfer by asserting DRO.
The DMA controller then asserts IDACK for the remainder
of the block transfer. DRO goes inactive for the duration of
the transfer. The Ready output is used to control the
transfer rate. Non-Block Mode DMA transfers end when
. IDACK goes False, whereas Block Mode DMA transfers
end when IIOR or IIOW becomes inactive. Since this is the
case, DMA transfers may be started sooner in a Block
Mode transfer. To obtain optimum performance in Block
Mode operation, the DMA logic optionally uses the normal
DMA mode interlocking handshake. Ready is still available
to throttle the DMA transfer, but DRO is 30 to 40 ns faster
than Ready and is used to start the cycle sooner. The
methods described under "Halting a DMA Operation"
apply for all DMA operations.
Pseudo DMA Mode
To avoid the tedium of monitoring and asserting the request/acknowledgement handshake signals for programmed 1/0 transfers, the system can be designed to
implement a pseudo DMA mode. This mode is implemented by programming the Z5380 to operate in the DMA
made, but using the CPU to emulate the DMA handshake.
DRO may be detected by polling the DMA Request bit (bit
6) in the Bus and Status Register, by sampling the signal
through an external port, or by using it to generate a CPU
interrupt. Once DRO is detected, the CPU can perform a
read or write data transfer. This CPU readlwrite is externally decoded to generate the appropriate IDACK and
IIOR or IIOW signals.

Halting a DMA Operation
The IEOP signal is not the only way to halt a DMA transfer.
A bus phase mismatch or a reset of the DMA Mode bit
(Mode Register, bit 1) can also terminate a DMA cycle for
the current bus phase.
Using the IEOP Signal
If IEOP is used, it should be asserted for at least lOOns
while IDACK and IIOR or IIOW are. simultaneously active.
Note, however, that if liaR or IIOW is not active, an interrupt
is generated. but the DMA activity continues. The IEOP
signal does not reset the DMA Mode bit. Since the /EOP
signal can occur during the last byte sent to the Output
Data Register, the IREO and lACK signals are monitored to
ensure that the last byte has transferred.
Bus Phase Mismatch Interrupt
A bus phase mismatch interrupt is used to halt the transfer
if operating as an Initiator. Using this method frees the host
from maintaining a data length counter and frees the DMA
logic from providing the lEap signal. If performing an
Initiator send operation, the Z5380 requires IDACK to
cycle before lACK goes inactive. Since phase clianges
cannot occur if lACK is active, either IDACK must be
cycled after the last byte is sent or the DMA Mode bit must
be reset in order to receive the phase mismatch interrupt.
Resetting the DMA Mode Bit
A·DMA operation may be halted at any time simply by
resetting the DMA Mode bit. It is recommended that the
DMA Mode bit be reset after receiving an IEOP or bus
phase-mismatch interrupt. The DMA Mode bit must then
be set before writing any of the start DMA registers for
subsequent bus phases.
If resetting the DMA Mode bit is used instead of IEOP for
Target role operation, then care must be taken to reset this
bit at the proper time. If receiving data as a Target device,
the DMA Mode bit must be reset once the last DRO is
received and before IDACK is asserted to prevent an
additionallREO from occurring. Resetting this bit causes
DRO to go inactive However, the last byte received
remains in the Input Data Register and may be obtained
either by performing a normal CPU read or by cycling
IDACK and IIOR In most cases, IEOP is easier to use when
operating as a Target device.

Often, external decoding logic is necessary to generate
the Z5380 ICS signal. This same logic may be used to
generate IDACK at no extra cost and provide an increased
performance in programmed 1/0 transfers.

245

READ REGISTERS
Address: 3
1 071061051

0~10

nIY
)

'I'D~~"~

~
1 (RrO

AssertC//O
Assert/MSG
Assert/REO

10B4

·0·

IOB5
IOB6

Figure 29. Target Comm
. and Register

IOB7

Figure 26. Current SCSI 0 ata Register

osl

Address: 4
1
1
1
07
05

(Read Only)

~I~:
CliO
IMSG
IREO

...

AssertlBSY

IBSY

: Assert lACK

IRST

Lost Arbitration
Arbitration in Progress

Figure 30. Current SCSI Bus Status Register

Assert/RST

Figure 27. Initiator Comm and Register
Address' 2
1
106"
07
05

(Read Only)
• 04. 031,021011001

~Arbttrate

OMAMode
Monitor IBSY
Enable IEOP Interrupt
Enable Parity
, Interrupt

Interrupt Request Active
Partty Error
OMA Request
End of OMA

Enable Parity Check'1119
Target Mode
Block Mode OMA

Figure 28. Mode Register

246

.
Figure 31. Bus and Status Reglster

Address: 6

(Read Only)

Address: 7

107106105104103[021011001

1--_____ IDB4
1-------- IDB5

1--_______

1-----------

(Read Only)

1071061051041031021011001
1

.
"l("

X=Don'tCare

Figure 33. Reset Parityllnterrupt

10~

Figure 32. Input Data Register

WRITE REGISTERS
Address: 0

Address: 2

(Write Only)

'~1051051041031021~1001

~~
1--______

' - - - - - - IDB4
IDB5

1--_________

' - - - - - - - - - ' /DB6

~
1--______

Asse\10ataBus

AssertIATN

. Assert ISEL

Monitor IBSY
Enable IEOP Interrupt

1..-_ _ _ _ _ _ _ TaJg9tMode
' - - - - - - - - - - Block Mode OMA

Figure 36. Mode Register
(Write Only)

1071061051041031021011001

1071061051D4103102101fCK1

OMAMode

' - - - - - - Enable Parity Interrupt
Enable Parity Checking

Address: 3

(Wille Only)

Arbitrate

1087

Figure 34. Output Dala Register
Address: 1

(Write Only)

1071051051041031021011001

AssertlBSY
Assert lACK

Assert VIO
AssertClID
AssertlMSG
AssertlREO
"J("

"0"

' - - - - - - - - - Test Mode

Figure 37. Target Command Register

AssertIRST

Figure 35. Initiator Command Register

247

WRITE REGISTERS (Continued)
Address: 4

(Write Only)

Address: 6

L--_ _ _ _ _.

(Write Only)

Irolool~I04ID3I~I~IOOI

1071061051041031021011001

1'------ "X"

lOBO
10Bl
IOB2

,
Figure 40. Start DMA Target Receive

IOB3
1084

' - - - - - - - - - IOB5
IOB6

L-._ _ _ _ _ _ _ _

IOB7

Address: 7

(Write Only)

Irolool~I04I03I~I~lool
"X"

Figure 38. Select Enable Register
Figure 41. Start DMA Initiator Receive
Address: 5

(Wrfte Only)

1071061051041031021011 Dol
1

"X"

Figure 39. Start .DMA Send

ABSOLUTE MAXIMUM RATINGS
Voltages on all pins
with respeCt to GND ............................... -O.3V 10 +7.0V
Operaling Ambient Temperature .............
........ t
Storage Temperature ............................. -65°C to + 150°C
Note:

See Ordering Information

248

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at
any condition above those indicated in the operatiollal
sections of ttlese specifications is not implied Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
.

STANDARD TEST CONDITIONS
The DC Characteristics section below apply for the following standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows into
the referenced pin. Standard conditions are as follows
(Figures 42 and 43):
•
•
•

+4.5V < Vcc < +5.5V
GND =OV
TA as specified in Orderin,Q Information

From Output
Under Test

Figure 42. Switching Test Circuit
Figure 43. Standard Test Load

DC CHARACTERISTICS
Z5380
Symbol

Parameter

Voo
VIH
VIL '

Supply Voltage
High-Level Input Voltage
Low-Level Input Voltage

I'Hl

High-Level Input Current
SCSI Bus Pins
High-Level )nput Current
All Other Pins

Vfti = 5 25V
VB- =OV
VIH = 5.25V
V"- =OV

Low-Level Input Current
SCSI Bus Pins
Low-Level Input Current
All Other Pins

Vfti = 5.25V
VIL =OV
VIH = 5.2SV
VB- =OV

VOH

High-Level.Output Voltage

VOL 1

Low-Level Output Voltage
SCSI Bus Pins

IOH = -3mA
Voo = 4.75V
IOL "" 48mA
Voo = 4.75V

VOL 2

Low-Level Output Voltage
All Other Pins
Supply Current
Operating Free-Air

1.1H2
IlL 1
IIL2

100
TA

Conditions

IOL = 7mA
Voo= 4.75V
15 mA

Min

Max

Units

4.75
2,0
-0.3

5.25
5.25
0.8

V
V
V

JIA

-50

JIA

-10 JIA
2.4

0.5

249

AC CHARACTERISTICS
CPU Write Cycle Timing Diagra'm
A2-AO

ICS

/lOW

D7-DO

Figure 44.' CPU Write Cycle

AC CHARACTERISTICS
CPU Write Cycle Timing Table
No

Description

Min

1
2
3

Address Setup to Write Enable[1]
Address Hold from End Write Enable[1]
Write Enable Wldth[1]

20
20
70

ns
ns
ns

4
5
6

Chip Select Hold from End of flOW
D~ta Setup to end of Write Enable[1]
Data Hold Time form End of flOW

0
50

ns
ns
ns

Note:
(1) Write Enable is the occurrence of /tOW and /CS

250

30'

Max

Units

AC CHARACTERISTICS

CPU Read Cycle Timing Diagram
A2-AO

ICS

/lOR

07-00

Figure 45. CPU Read Cycle

AC CHARACTERISTICS

CPU Read Cycle- Timing Table
No

Description

Min

1
2

Address Setup to Read Enable[1 J
Address Hold from End Read Enable[1J

20
20

ns
ns

3
4
5

Chip Select Hold from End of IIOR
Data Access Time from Read Enable[ tJ
Data Hold Time from End of Read Enablep.j

0
130
20

ns
ns
ns

Max

Units

Nole:
[1 J Read Enable is !he occurrence of /lOR and /CS.

251

AC CHARACTERISTICS
DMA Write (Non-Block Mode) Target Send Cycle Timing Diagram

ORO

10ACK

/lOW

07-00

IEOP

IREO

lACK

IOB7-/OBO,
10BP

__________________-11

Figure 46. DMA Write (Non-Block Mode) Target Send Cycle

252

AC CHARACTERISTICS
DMA Write (Non-Block Mode) Target Send Cycle Table

Description

Min

1
2
3
4

DRO Low from IDACK Low
IDACK High to DRO High
Write Enable Width[ 1]
IDACK Hold from IIOW High

130
30

5
6
7
8

Data Setup to End of Write Enable[1]
Data Hold Time from End of IIOW
Width of lEOP Pulse[2]
lACK Low to IREO High

IREO from End of /DACK (lACK High)
lACK Low to DRO High (Target)
lACK High to IREO Low (lDACK High)
Data Hold from Write Enable
Data Setup to IREO Low (Target)

11
12
13

Max

ns
ns
ns
ns

100

40
100
25

125

150
110
150

15
20
15

Units

ns
ns
ns
ns
ns
ns
ns
ns
ns

Noles:
(1) Write Enable is the occurrence of flOW and fDACK.
(2) 1E00, /lOW, and /DACK must be concurrenUy Low for alleast T7 for proper recognition of the 1E0P putse.

253

AC CHARACTERISTICS
DMA Write (Non-Block Mode) Initiator Send Cycle Timing Diagram
ORO

10ACK

/lOW

D7eOO

IEOP

IREO

lACK

IOB7-/DBO,
10BP

----------------~
Figure 47. DMA Write (Non-Block Mode) Initiator Send Cycle

254

AC CHARACTERISTICS
DMA Write (Non-Block Mode) Initiator Send Cycle Table
,Max

Description

Min

DRO Low from /DACK Low
IDACK High to DRO High
Write Enable Width[1}
IDACK Hold from End of IIOW

130
30
100
'0

ns
ns
ns
ns

50
40

ns
ns
ns
ns

2
3
4

5
6
7

8
9

10
11
12

Data Setup to End of Write Enable[1]
Data Hold Time from End of II OW
Width of IEOP Pulse[2]
IREO Low to lACK Low
IREO High to DRO High
'/DACK High to lACK High
!IOW High to Valid SCSI Data
Data Hold from Write Enable[1]

100.
20
20
25
100

160
110

150

Units

ns
ns
ns
ns

Notes:
[11 Write Enable is the occurrence of /lOW and IDACK,
[21 /EOP,/IOW, and IDACK must be concurrently Low for at least T7 for proper recognition of the IEOP pulse,

255

AC CHARACTERISTICS
DMA Read (Non-Block Mode) Target Receive Cycle Timing Diagram
ORO

10ACK

liaR

07-00

lEap

IREO

lACK

IOB7-/OBO,
10BP

Figure 48. DMA Read (Non-Block Mode) Target Receive Cycle

256

---

----------

AC CHARACTERISTICS
DMA Read (Non-Block Mode) Target Receive Cycle Table

•
No

Description

Min

1
2
3

ORO Low from /DACK Low
IDACK' High to ORO High
IDACK Hold Time from End of IIOR
Data Access Time from Read Enable(1)

130

5
6
7

8
9
10

11
12

Max

ns
ns
ns
ns

115

Data Hold Time from End of IIOR
Width of IEOP Pulse[2]
lACK Low to ORO High
IDACK High to /REO Lo~ (lACK High)

20
100
30

110
150

lACK Low to IREO High
lACK High to /REO Low (lDACK High)
Data Setup Time to lACK
Data Hold Time from lACK

25
20

125
150

20
50

Units

ns
ns
ns
ns
ns
ns
ns
ns

Noles:
[1) Read Enable is'the occurrence of /lOR and /DACK
(2) lEap, /lOR, and /DACK must be concurrently Low for alleasl T6 for proper recognition of the lEap pulse.

257

AC CHARACTERISTICS
DMA Read (Non-Block Mode) Initiator Receive Cycle Timing Diagram

ORO

10ACK

/lOR

07-00

IEOP

/REO

lACK

IOB7-/OBO,
IDBP

Figure 49. DMA Read (Non-Block Mode) Initiator Receive Cycle

258

AC CHARACTERISTICS
DMA Read (Non-Block Mode) Initiator Receive Cycle Table
Max

Units

Description

Min

1
2

ORO Low from IDACK Low
IDACK High to ORO High
IDACK Hold Time from End of liaR
Data Access lime from Read Enable[1]

130
30
0
115

ns
ns
ns
ns

3
4

5
6
7

Data Hold Time from End of liaR
Width of lEap Pulse[2)
IREO Low to ORO High
IDACK High to lACK High (lRE9 High)

8
9

100

IREO Low to lACK Low
IREO High to lACK High (/DACK High)
Data Setup Time to IREO
Data Hold Time from IREO

10
11
12

160

160
140

15
20

ns
ns
ns
ns

Noles:
[1] Read Enable is the occurrence of IIOR and /DACK.
[2] IEOP, /lOR, and /DACK must be concurrently Low for at least T6 for proper recognition of the /EOP pulse.

259

---,,--,-~

........ "

AC CHARACTERISTICS
DMA Write (Block Mode) Target Send Cycle Timing Diagram
ORO

10ACK

IIOW

07-00

lEap

IREO

lACK
·~---\111}----'~"---\12~--t

REAOY
14"-----\.133)----~

IOB7-/OBO,
/oBP

Figure 50. DMA Write (Block Mode) Target Send Cycle

260

AC CHARACTERISTICS
DMA Write (Block Mode) Target Send Cycle Table
No

Description

Min

1
2
4

ORO Low from IDACK Low
Write Enable Width[1]
Write Recovery Time
Data Setup to End of Write Enable[ 1]

130
100
120
50

ns
ns
ns
ns

5
6
7
8

Data Hold Time from Ef1d of IIOW
Width of IEOP Pulse[2]
lACK Low to IREO High
IREO from End of IIOW (lACK High)

40
100
25
40

ns
ns
ns
ns

IREO from End of lACK (lIOW High)
lACK Low to READY High
READY High to IIOW High
IIOW High to READY Low

20
20
70

170
140

140

Data Hold from lACK Low
Data Setup to IREO Low

40
60

10
11
12

13
14

Max

125
180

Units

ns
ns
ns
ns
ns
ns

Noles:
[1) Write Enable is the occurrence of /IOW and /DACK.
[2) /EOP, /IOW, and /DACK must be concurrently Low for at least T6 for proper recognition of the /EOP pulse.

261

AC CHARACTERISTICS
DMA Read (Block Mode) Target Receive Cycle Timing Diagram
ORO

IOACK

/lOR

07-00

/EOP

IREO

lACK

READY

IOB7-1080,
IOBP

Figure 51. DMA Read (Block Mode) Target Receive Cycle

262

AC CHARACTERISTICS
DMA Read (Block Mode) Target Receive Cycle Table
No

Description

Min

1
2
3
4

DRO Low from /DACK Low
liaR Recovery Time
Data Access Time from Read Enable[1]
Data Hold Time from End of liaR

130
120
110

100
30
25

Width of lEap Pulse[2]
liaR High to /REO Low
lACK Low to IREO High
lACK High to IREO Low (lIaR High)

lACK Low to READY High

10
11
12
13

READY High to Valid Data
liaR High to READY Low
Data Setup Time to lACK
Data Hold Time from lACK

20
50
20

6
7

Max

ns
ns
ns
ns

20
50

Units

190
125
170
140
140

ns
ns
ns
ns
ns
. ns
ns
ns
ns

Noles:
[1] Read Enable is the occurrence of IIOR and /OACK.
[2] IEOP, IIOR, and /OACK must be concurrently Low for alleast T5 for proper recognition of the IEOP pulse.

263

AC CHARACTERISTICS
Arbitration
IRST

ISEL

IBSY

IOB7-0BO,
IDBP

ARBITRATE

------'

\_---

Figure 52. Arbitration

Description

Min

Max

Units

Bus Clear from /SEL Low
Arbitrate Start from /BSY High

600
1200

2200

ns
ns

Max

Units

AC CHARACTERISTICS
Reset
!RESET

Figure 53. Reset

Description

Min

Minimum Width of /RESET

200

264

Z5380 NOTES
1. Edge-triggered IRST Interrupt - If the SCSI Bus is not
terminated, the IRST interrupt is continually generated.

6. Phase Mismatch Interrupt - A phase mismatch interrupt
is not guaranteed after a reseleclion for the following
reasons:

2. True End of DMA Interrupt - The Z5380 generates an
interrupt when it receives the last byte from the DMA, not
when the last byte is transferred to the SCSI Bus.

DMA Mode bit must be set in order to receive a phase'
mismatch interrupt.

3. Return to Ready after IEOP Interrupt - When operating in
Block Mode DMA, the Z5380 does not return the Ready
signal to a Ready condition. This locks up the bus and
prevents the CPU from executing.

DMA Mode bit can not be set unless /BSY is active.

4. SCSI handshake after IEOP occurs - If an EOP occurs
when receiving data, a subsequent request will cause
lACK to be asserted even though no ORO is issued

5. Reselection Interrupt - During reselection. if the Target
Command Register does not reflect the current bus phase
(most likely Data Out), the reselectioo interrupt may get
reset.

/BSY can not be asserted until after the reselection has
occurred.
Once/BSY is asserted, the Target may assertlREO in less
than 5OOns.
The phase mismatch interrupt is generated on the active
edge of /REO. If the DMA Mode bit is not set before the
/REO goes active, the phase mismatch interrupt will not
occur.

265

266

~Zirm

PRELIMINARY PRODUCT SPECIFICATION

Z85230
Esccm ENHANCED
SERIAL COMMUNICATION CONTROLLER
FEATURES
•

Deeper Data FIFOs
- 4-byte transmit FIFO
- 8-byte receive FIFO

•

Low Power CMOS

•

New programmable features added with Write
Register 7'

Programmable FIFO interrupt levels provide flexible
interrupt response

•

Write registers: WR3, WR4, WR5, and WR10 are now
readable

Pin and Function compatible to CMOS and NMOS
Z85C30 SCC

•

Read Register 0 latched during access

Many improvements to support SDLC/HDLC transfers:
- Deactivation of /RTS pin after closing flag
- Automatic transmission of the opening flag
- Automatic reset of Tx Underrun/EOM latch
- Complete CRC reception
- TxD pin automatically forced high with NRZI
encoding when using mark idle.
- Receive FIFO automatically unlocked for special
receive interrupts when using the SDLC
status FIFO.
- Back-to-back frame transmission simplified

•

Software Interrupt Acknowledge Mode

•

DPLL counter output available as jitter -free clock source

•

/DTR/JREO pin deactivation time reduced

•

Two independent full-duplex channels, each with a
crystal oscillator, baud rate generator, and Digital
Phase Locked Loop.

•

Multi-protocol operation under program control

•

Easier interface to popular CPUs

•

Fast speeds:
- 10.0 MHz for data rates up 10 2.5 Mbit/sec.
- 16 384 MHz for data rates up to 4.096 Mbit/sec.
- 20.0 MHz for data ra1esup to 50 Mbit/sec.

Asynchronous mode with five to eight bits, and one,
one and one-half, or two stop bits per character;
programmable clock factor; break detection and
generation; parity, overrun, and framing error detection.

•

Synchronous mode with internal or external character
synChronization on one or two synchronous characters
and CRC generation and checking with programmable
CRC preset values.

•

Multiplexed Z-Bus version, Z80230, planned in
021991

•

Faster interrupt response

•

Improved SDLC frame status FIFO

GENERAL DESCRIPTION
The Zilog Enhanced Serial Communications Controller,
Z85230 ESCC, is a pin and software compatible CMOS
member ofthe SCC family introduced by Zilog in 1981. The
ESCC is a dual-channel, full-duplex data communications
controller capable of supporting a wide range of popular
protocols. The ESCC is built from Zilog's industry ~tandard

SCC core and is compatible with designs using Zilog's
SCC to receive and transmit data. It has many improvements
that significantly reduce CPU overhead. The addition of a
4-byte transmit FIFO and an 8-byle receive FIFO significantly
reduces the overhead required to provide data to, and get
. data from, the transmitters and receivers.

267

GENERAL DESCRIPTION (Continued) .
The ESCC also has many features that improve packet
handling in SOLC mode. The ESCC will automatically:
transmit a flag before the data, reset the Tx Underrun/EOM
l(itch, force the TxO pin high at the appropriate time when
using NRZI encoding, deassert the IRTS pin after the
closing flag, and better handle ABORTed frames when
using the 10x19 status FIFO. The combination of these
features along with the deeper data FIFOs significantly
simplifies SOLC driver software.

external logic to many microprocessor families while maintaining compatibility wittl existing designs. 1/0 handling of
the "[SCC is improved over the SCC with faster response
of the liNT and IOTR//REQ pins.
Tile many enhancements added to tile ESCC permits a
system design that increases overall system performance
with better data handling and less interface logic.

Note: All Signals with preceding front slash, "I", are active
Lo)IV, e.g.: BIIW (WORD is active Low); IBIW (BYTE is
active Low, only); INIIS (NORMAL and SYSTEM are both
active Low).

Hie CPU hardware interface lIas been simplified by relieving
the databus setup time requirement and supporting the
software generation of the interrupt acknowledge signal
(INTACK). These changes allow an interface with less

Tmnsmlt logic

Transmit FIFO

Channel A

4 Byte

Transmit MUX

Data Encoding & CRC
Generation

Exploded View
Receive and Transmit Clock Multipexer
Digital
Phaee-Locked
Loop

r--

~
~

Cryetal
Oecillator

Baud Rate

Generator

TxDA

fTRxCA
IRTxCA

Ampl~ier

ICTSA
ModemiControl Logic

i--

I - IDCDA

~ IRTSA
IDTRAlIREQA
ISYNCA

Receive Logic

Re<:. Status

Roc. Data

FIFO 8 Byte

FlF08Byte

SDLC Frome Status FIFO
10 x19

ReceiveMUX

~I - RxDA

CRC Checker,
Data Decode &
Sync Character
Detection

Channel A
Databus
Control

i i i

+5V

liNT
Interrupt { IINTACK
lEI
Control
lEO

Channel B

-'---~

GND PCLK

Figure 1. ESCC Block Diagram

268

I-

0 0'"

'"0 ....0

~~ :J~ en en ~
Z
w

!H~ ~~ Q ~

10TRI/REQB

Figure 3. Z85230 PLCC Pin Assignments

ICTSA

RTSB

/oCOA

ICTSB

PCLK

10COB

Figure 2. Z85230 DIP Pin Assignments
TxOA

07
06
05
OataBus

04
03

Channel
Clocks

Controls

for Modem.

OMAand
Other

00
IRO
IWR

} Data
}

AlIB
Control

Serial
Oata

}'~~

Bus Timing
and Reset

}
}

Senal

ICE

Channel
Clocks

OIiC

nNT

},-

lEI
lEO

Controls

for Modem,

OMAand

Note: Power connections follow
Conventional descriptions below
Connection

Circuit

Device

Power

Vce

VOO

Ground

GND

Vss

Other\

+5V

GNO

PCLK

Figure 4. Z85230 Pin Functions

269

PIN DESCRIPTIONS
The following section describes the Z85230 pin functions.
Figures 2 and 3 detail the pin assignments for the 40-pin
DIP and 44-pin PLCC packages. The Z85230 ESCC is
socket compatible with the Zilog Z8530 and Z85C30 as the
pin electrical characteristics and pin assignments are the
same. Any unused input pins should be pulled up to the
+5V supply.
ICTSA,/CTSB. Clear To Send (inputs, active Low).These
pins function as transmitter enables if they are programmed
for Auto Enables (WR3, 05= 1). A Low on the inputs
enables the respective transmitters. If not programmed as
Auto Enables, they may be used as general-purpose
inputs. Both inputs are Schmitt trigger buffered. to accommodate slow rise-time inputs. The ESCC detects pulses
on these inputs and can interrupt the CPU on both logic
level transitions.
IDCDA, IDCDB. Data Carrier Detect (inputs, active Low).
These pins function as receiver enables if they are programmed for Auto Enables (WR3, 05= 1): otherwise they
are used as general-purpose input pins. Both pins are
Schmitt-trigger buffered to accommodate slow rise time
Signals. The
detects pulses on these pins and can
interrupt the CPU on both logic level transitions.

rscc

IRTSA, IRTSB. Request To Send (outputs, active Low).
The /RTS pins can be used as general purpose outputs or
with the Auto Enables feature. When used with Auto
Enables ON (WR3, 05= 1) in asynchronous mode, the /RTS
pin goes high after the transmitter is empty. When Auto
Enable is OFF, the /RTS pins can be used as general
purpose outputs and, they strictly follow the inverse state
of the. RTS bit (WR5 bit 01).
In SOLC mode, the /RTS pins can be programmed to be
deasserted when the closing flag of the message clears
the TxO pin if WR1' 02 is set.
ISYNCA, ISYNCB. Synchronization (inputs or outputs,
active Low). These pins can act either .as inputs, outputs,
or part of the crystal oscillator circuit. In the Asynchronous
Receive mode (crystal oscillator option not selected),
these pins are inputs similar to CTS and OCO.ln this mode,
transitions on these lines affect the state of the Synchronous/
Hunt status bits in Read Register 0 but have no other
function.
In External Sync;hronization mode with the crystal oscillator
not selected, these lines also act as inputs. In this mode,
ISYNC must be driven Low for two receive clock cycles
after the last bit in the synchronous character is received.
Character assembly begins on the rising edge of the
receive clock immediately preceding the activation
of /SYNC.

270

In the Inlilrnal Synchronization mode (Iv!onosync and
Bisync) with the crystal oscillator not selected, these pins
act as outputs and are active only during the part of the
receive clock cycle in which synchronous condition is
latched. These outputs are active each time a synchronization pattern is recognized (regardless of character
boundaries). In SOLC mode, the pins act as outputs and
are valid on receipt of a flag. The /SYNC pins switch from
input to output wh1:ln monosync, bisync, or SOLC is programmed in WR4 and sync modes are enabled.
IOTA//REOA, IOTA//REOB. Data Terminal Ready/Request
(outputs, active Low). These pins are programmed (WR14,
02) to serve either as general purpose outputs or as OMA
Request lines. When programmed for the OTR fun,ction
(WR14, 02=0), these outputs follow the state programmed
into the DTR bit of Write Register 5 (WR5, 07). When
programmed for Request mode (WR14, 02= 1), these pins
serve as OMA Requests for the transmitter.
When used as OMA request lines, the timing for the
deactivation Request can be programmed in the added
register Write Register l' (WR7') bit 04. If this bit is set, the
/OTR//Request pin will be deactivated with the same timing
as the /WI/REO pin. If WR1' 04 is reset, the deactivation
timing of /OTRI/Req pin will be the same as in the Z85C30.
WIIREOA,/WIIREOB. WaiVRequest(outputs, open-drain
when programmed for Wail function, driven High or Low
when programmed for Ready function). These dual-pur. pose outputs may be programmed as Request lines for a
OMA controller or as Wait lines which synchronize the CPU
to the ESCC data rate. The reset state is Wait.
RxDA, RxDB. Receive Data (inputs, active High). These
input signals receive serial data at standard TTL levels.
IRTxCA,/RTxCB. Receive/Transmit Clocks (inputs, active
Low). These pins can be programmed to several modes of
operation. In each channel, RTxC may supply the receive
clock, the transmit clock, the clock for the baud rate
generator, or the clock for the Digital Phase-Locked Loop.
These pins can also be programmed for use with the
respective SYNC pins as a crystal oscillator. The receive
clock may be 1, 16, 32, or 64 times the data rate in
asynchronous modes.
TxDA, TxDB. Transmit Data (outputs, active High). These
output signals transmit serial data at standard TTL levels.
!TRxCA, !TRxCB. Transmit/Receive Clocks (inputs or
outputs, active Low). These pins can be programmed in
several different modes of operation. TRxC may supply the
receive. clock or the transmit clock in the input mode or

supply the output of the Digital Phase-Locked Loop, the
crystal oscillator, the baud rate generator, or the transmit
clock in the output mode.
PCLK. Clock (input). This is the master ESCC clock used
to synchronize internal signals. PCLK is a TTL levei signal.
PCLK is not required to have any phase relationship with
the master system clock.
lEI. Interrupt Enable In (input, active High). lEI is used with
lEO to form an interrupt daisy chain when there is more
than one interrupt driven device. A high lEI indicates that
no other higher priority device has an interrupt under
service or is requesting an interrupt.

lEO. Interrupt Enable Out,output, activEl High). tEO is High
only if lEI is High and the CPU is not servicing the ESCC
interrupt or the ESCC is noV€(ll:JE!sting aaint(drrupt (Interrupt
Acknowl.edge cyc~ only). 11"'0 is conf'l€oted to the next
lower priority device's lEi input ana thus inhibits interrupts
from lower priority devlces.
liNT. Interrupt (output, open drain, active Low). This signal
is activated when the ESCC requests an interrupt. Note
that II.NT is an open-drain output.
IINTACK. Interrupt Acknowledge (input, active Low). This
is a strobe which indicates that an interrupt acknowledge
cycle is in progress. During this cycle, the ESCC interrupt
daisy chain is resolved. The device iscapable of returning
an interrupt vector that may be encoded with the type qf

interrupt pending. During the acknowledge cycle, if lEI is
high the ESCC places the interrupt vector on the databus
when IRD goes active. liNT ACK is latched by the rising
edge of PCLK.
07-00. Data bus (bidirectional, tri-state). These lines carry
data and commands to and from the ESCC.
ICE. Chip Enable (input, active Low). This signal selects
the ESCC for a read or write operation.
IRO. Read (input, active Low). This signal indicates a read
operation and when the ESCC is selected, enables the
ESCC's bus drivers. During the Interrupt Acknowledge
cycle, IRD gates the interrupt vector onto the bus if the
ESCC is the highest priority device requesting an interrupt.

twA. Write(input, active Low). When the ESCC is selected,
this Signal indicates a write operation. This indicates that
the CPU wants to write command bytes or data to the
ESCC write registers. The coincidence of IRD and /WR is
interpreted as a reset.
NIB. Channel NChannel B (input). This Signal selects the
channel in which the read or write operation occurs. A High
selects channel A and Low selects channel B.
OIlC. Data/Control Select (input). This signal defines the
type of information transferred to or from the ESCC. A High
means data is being transferred and a Low indicates a
command.
.

271

FUNCTIONAL DESCRIPTION
-

Architecture. The architecture of the ESCC is described
from two pOints of view: as a datacommunicalions device
which transmits and receives data in a wide variety of
protocols: and as a microprocessor peripheral in which the
ESCC offers valuable features such as vectored interrupts
and DMA support.

The ESCC's peripheral and datacommunication are described in the following sections. A block diagram is shown
in Figure 1. The details of the communications betwe.en the
receive and transmit logic to the system bus is shown in
Figures 5 and 6. The features and data path for each of the
ESCC's A and B channels is identical. See the ESCC
Technical Manual for full details on using the ESCC.

Internal Data Bus

...

...>

WRS

WR7
SYNC

<.
,"

Zero
Insert

WRG

20-BitTX

TXFIFO
4 Byte

ASYNC
SYNC
SOLC

,
Transmit
MUX & 2~Bit
Delay

CRe-SOLC

CRC-Gen

------

Transmit Clock

From Receiver
Figure 5. ESCC Transmit Data Path

272

Internal TXO

FinalTX
MUX

Shift Register

To OtherChannel

NRZI
Encode

f----

TXO

CPUVO

Internal Data Bus

BRG
Input

BRG
Output

14-Bit Counter
Hunt Mode (BiSYNC)
DPLL

RXD
L-____________________~ToTnmsmt~on

L - - - -....1...-.::.:.;:=:...-..:.J

CRC Resuk

Figure 6. ESCC Receive Data Path

273

1/0 INTERFACE CAPABILITIES
System communication to and from the ESCC is done
through the ESCC's register set. There are seventeen write
registers and fifteen read registers. Many of the new
features on the ESCC are enabled through a new register
in the ESCC: Write Register 7 Prime (WRT). This new
register can be accessed if bit 00 of WR 15 is set. Table 1
lists all of the ESCC's registers and a brief desc~iption of

their functions. Throughout this document, the write and
read registers are refer~nced with the following notation:
"WR" for Write Register and "RR" for Read Register. For
example:
WR4A
RR3

Write Register 4 for channel A
Read Register 3 for either/both channels

Table 1. ESCC Write and Read Registers
Write Register

Functions

WRO
WR1
WR2

Command Register: Register POinters, CRC initialization, and'resets for various modes.
Interrupt conditions, Wait/OMA request control.
Interrupt Vector (accessed through either channel).

WR3
WR4
WR5
WR6

Receive and miscellaneous control parameters.
Transmit and Receive parameters and mpdes. '
Transmit parameters and controls.
.
Sync character or SOLC address field.

WR7
WRT
WR8
WR9

Sync character or SOLC flag.
SOLC enhancements ,enable (accessed if WR-15 00 is 1).
Transmit FIFO (4 bytes deep).
Reset commands and Master INT enable (accessed through either channel).

WR10
WR11
WR12

Miscellaneous transmit and receive controls.
Clock mode control.
Lower byte of BRG time constant.

WR13
WR14
WR15

Upper byte of f3RG time constant.
Miscellaneous controls and OPLL commaods. '
External interrupt conlro!.
'

Read Register
RRO
RR1
RR2A
RR2B

Transmit, Receive and extetnal status:
Special Receive Condition status bits.
Unmodified. interrupt vector.
'
MOdified interrupt vector. .

RR3A
RR4
RR5
RR6

Interrupt Pending bits.
WR4 status (if WRT 06=1).
W,R5 status (if WRT 06= 1).
SOLC Frame LSB Byte Count (if WR15 02=1}.

RR7
RR8
RR9
RR10
RR11
RR12
RR13
RR14

274

SOLC Frame 10x19 FIFO Status and'MSB Byte Count (if WR15 02=1).
Receive Data FIFO (8 Deep).
WR3 status (if 'f'IRT 06= 1).
, Miscellaneous status bits.
WR10 status (if WRT 06=.).
Lower Byte of BRG time constant.
Upper byte of BRG time constant.
WRT status (If WRT 06= 1).

There are three choices to move data into and out of the
ESCC: Polling. interrupt (vectored and non-vectored). and
Block Transfer. The Block Transfer mode can be implemented under CPU or OMA control.
Polling. When polling. all interrupts are disabled. Three
status registers in the ESCC are automatically updated
whenever any function is performed. For example. end-offrame in SOLC mode sets a bit in one of these status
registers. The purpose of polling is forttie CPU to periodically
read a status registet until the register contents indicate
the need for data to be transferred. Only one register
needs to be read; depending on its contents. the CPU
either writes data. reads data. or continues. Two bits in the
register indicate the need for data transfer. An alternative
is a poll of the Interrupt Pending register to determine the
source of an interrupt. The status for both channels resides
in one register.
Interrupts. The ESCC's interrupt structure supports vectored and nested interrupts. The fill levels where the
transmit and receive FIFOs interrupt the CPU are programmable. This allows the ESCC's requests for data
transfers to be tuned to the system interrupt response time.
Another enhancement to the ESCC is that the /INT pin will
respond faster to interrupting conditions than will the SCC.
Nested interrupts are supported with the interrupt acknowledge feature (lINTACK pin) of the ESCC. This allows
the CPU to recognize the occurrence of an interrupt, and

Peripheral

+5V

re-enable higher priority interrupts. Because an INTACK
cycle will release the /INT pin from the active state. a higher
priority ESCC interrupt or another higher priority device
can interrupt the CPU. When an ESCC responds to an
Interrupt Acknowledge signal (I NT ACK) from the CPU. an
interrupt vector may be placed on the data bus. This vector
is written inWR2 and may be read in RR2. To speed
interrupt response time. the ESCC can modify three bits in
this vectorto indicate status. If the vector is read in Channel
A. status is never included; if it is read in Channel B. status'
is always included.
Each of the six sources of interrupts in the ESCC (Transmit,
Receive. and External/Status interrupts in both channels)
has three bits associated with the interrupt source: Interrupt Pending (IP). Interrupt Under Service (IUS). and
Interrupt Enable (IE). Operation of the IE bit is straightforward. If the IE bitis settor a given interrupt source. then that
source can request interrupts. The exception is when the
MIE (Master Interrupt Enable) bit in WR9 is reset and no
interrupts can be requested. The IE bits are write only.
The other two bits are related to the interrupt priority chain
(Figure 7). As a microprocessor peripheral. the ESCC may
request an interrupt only when no higher priority device is
. requesting one. e.g .. when lEI is High. If the device in
question requests an interrupt. it pulls down liNT. The CPU
then responds with liNTACK. and the interrupting device
places the vector on the data bus.

Peripheral

-,lEI

07-00 liNT IINTACK lEO

lEI

07-00

liNT IINTACK lEO

IINTACK

,....

liNT IINTACK
+5V

-,-

<-.

liNT

D7-00

•

D7-DO

lEI

Figure 7. ESCC Interrupt Priority Schedule

. 275

1/0 INTERFACE CAPABILITIES (Continued)
The ESCC can also execute an interrupt acknowledge
cycle through software. In s.ome CPU environments it is
difficult to create the /INTACK signal with the necessary
timing to acknowledge interrupts and allow the nesting of
interrupts. In these cases, the /INTACK signal can be
created with a software command to the ESCC. See the
New Feature section for more details on this enhancement.
In the ESCC, the Interrupt Pending (IP) bit signals a need
for interrupt seNicing. When an IP bit is 1 and the lEI input
is High, the /INT output is pulled Low, requesting an
interrupt. In the ESCC, if the IE bit isn't set by enabling
interrupts, then the IP for that source is never set. The IP
bits are readable in RR3A.
The IUS bits signal that an interrupt request is being
serviced. If an IUS is set, all interrupt sources of lower
priority in the ESCC and external to the ESCC are prevented
from requesting interrupts. The internal interrupt sources
are inhibited by the state of the internal daisy chain, while
lower priority devices are inhibited by the lEO output of the
ESCC being pulled Low and propagated to subsequent
perip~erals. An IUS bit is set during an Interrupt Acknowledge cycle if there are no higher priority devices
requesting interrupts.
There are three types of interrupts: Transmit, Receive, and
External/Status. Each interrupt type is enabled under
program control with Channel A having higher priority than
Channel B, and with Receiver, Transmit, and External/
Status interrupts prioritized in that order within each channel.
When the Transmit interrupt is enabled (WR1 01=1), the
occurrence of the interrupt depends on the state of WRT
05. If this bit is reset. the CPU is interrupted when the top
byte of the transmit FIFO becomes empty. If WRt 05 is set.
the CPU is interrupted when the transmit FIFO is completely
empty. (This implies that the transmitter must have had a
data character written into it so that it can become empty.)
When enabled, the receiver can interrupt the CPU in one
of three ways:
•

Interrupt on First Receive Character or Special
Receive Condition.

•

Interrupt on All Receive Characters or Special
Receive Conditions.

•

Interrupt on Special Receive Conditions Only.

276

If WRT bit 03 is set. the Receive character interrupt occurs
when there are four bytes available in the receive FIFO.
This ismost useful in synchronous applications as the data
is in consecutive bytes. Interrupt on First Character or
Special Condition and Interrupt 00 Special Condition Only
are typically used with the Block Transfer mode. A special
Receive Condition is one of the following: receiver overrun,
framing error in Asynchronous mode, end-of-frame in
SOLC mode and, optionally, a parity error. The Special
Receive Condition interrupt is different from an ordinary
receive character available interrupt only by the status
placed in the vector during the Interrupt Acknowledge
cycle. In Interrupt on First Receive Character, an interrupt
occurs from Special Receive Conditions any time after the
first receive character interrupt.
The main function of the Extemal/Status interrupt is to
monitor the signal transitions of the /CTS, IDCO, and
/SYNC pins, however, an External/Status interrupt is also
caused by a Transmit Underrun condition; a zero count in
the baud rate generator; by the detection of a Break
(Asynchronous mode), Abort (SOLe mode) or EOP (SOLC
Loop mode) sequence in the data stream. The interrupt
caused by the Abort or EOP has a special feature allowing
the ESCC to interrupt when the Abort or EOP sequence is
detected or terminated. This feature facilitates the proper
termination of the current message, correct initialization of
the next message, and the accurate liming of the Abort
condition by external logic in SOLC mode. In SOLC Loop
.mode, this feature allows secondary stations to recognize
,the primary station wishes to regain control of the loop
during a poll sequence.
CPUlDMA Block Transfer. The ESCC provides a Block
Transfer mode to accommodate CPU block transfer
functions and OMA controllers. The Block Transfer mode
used the /WAIT//REQUEST output in conjunction with the
Wait/Request bits in WR1. The /WAITI/REQUEST output
can be defined under software control as a WAIT line in the
CPU Block TranSfer mode or as a REQUEST line in the
OMA Block Transfer mode.

To a OMA controller, the ESCC REQUEST output indicates
that the ESCC is ready to transfer data to or from memory.
To the CPU, the WAIT line indicates that the ESCC is not
ready to transfer data, thereby requesting that the CPU
extend the I/O cycle. The /OTAI/REQUEST line allows fullduplex operation under OMA control. The ESCC can be
programmed to deassert the /OTRI/REQUEST pin with the
same timing as the /WAITI/REQUEST pin if WRT 04 is set.

ESCC DATA COMMUNICATIONS CAPABILITIES
The ESCC provides two independe[lt full-duplex programmable channels for use in any common asynchronous
or synchronous data communication protocols (Figure 8).
Parity

!r-

Start

Marking Line

Each of the datacommunication channels has identical
features and capabilities.

Stop

II II

Data

Marking Line

Asynchronous

SYNC

Data

CRCl

CRC2

Data

CRCl

CRC2

Data

CRCl

CRC2

CRCl

CRC2

Monosync
SYNC

SYNC

Data

Signall

Bisync

.,...;.---r----Cj
Data

External Sync
Flag

Address

Control

Infonnation

Flag

SDLC/HDLC/X.25
Figure 8. Some ESCC Protocols

The ESCC has significant improvements to its data communications capacity over that of the standard SCC. The
addition of the deeper data FIFOs allows for data to be
moved in strings instead of on a byte-by-byte basis. The
ability to handle data in strings allows for significant improvements in data handling and, consequently, more
efficient use of bus bandwidth. The programmability of the
INT/DMA level of the FIFOs allows the system designer to
determine fill levels as the FIFO's request the system to
move data. The deeper data FIFOs are accessible regardless of the protocol used. They do not need to be
enabled For more details on these improvements, see the '
New Feature section of this specification.
Asynchronous Modes. Send and Receive IS accomplished
independently on each channel with five to eight bits per
character, plus optional even or odd parity. The transmitters
can supply one, one-and-a-half, or two stop bits per

character and can provide a break output at any time. The
receiver break-detection logic interrupts the CPU both at
the start and at the end of a received break. Reception is
protected from spikes by a transient spike-rejection
mechanism that checks the signal one-half a bit time after
a Low level is detected on the receive data input (RxDA or
RxDB pins). If the Low does not persist (e.g., a transient),
the character assembly process does not start.
Fram ing errors and overrun errors are detected and buffered
together with the partial character on which they occur.
Vectored interrupts allow fast servicing or error conditions
using dedicated routines. Furthermore, a built-in checking
process avoids the interpretation of a framing error as a
new start bit: a framing error results in the addition of onehalf a bit time to the point at which the search for the next
start bit begins.

277

ESCC DATA COMM.UNICATIONS CAPABILITIES (Continued)
The ESCC does not require symmetric transmit and receive clock signals - a feature allowing use of the wide
variety of clock sources. The transmitter and receiver
handle data at a rate supplied to the receive and transmit
clock inputs. In Asynchronous modes, the SYNC pin may
be programmed as an input used for functions such as
monitoring a ring indicator.
Synchronous Modes. The ESCC supports both byte-oriented and bit-oriented synchronous <;.ommunication.
Synchronous byte-oriented protocols are ha'ndled in several

modes. They allow character synchronization with a 6-bit
or 8-bitsync character (Monosync), and a 12-bit or 16-bit
synchronization pattem (Bisync), or with an extemal sync
signal. Leading sync characters are removed without
interrupting the CPU.
Five or 7-bit synchronous characters are detected with 8or 16-bit pattems in the ESCC by overlapping the larger
pattem across multiple incoming synchronous characters
as shown in Figure 9.

5 Bits

I I SYNC

SYNC

Data

I
8

Figure 9. Detecting 5- or 7-Bit Synchronous Characters

CRC checking for Synchronous byte oriented modes is
delayed by one character time so that the CPU may
d,isable CRC checking on specific characters. This permits
the implementation of protocols such as IBM Bisync.
Both CRC-16 (X16 + X15 + X2 +1) and CCITT (X16 + X12
+ X5 + 1) error checking polynomials are supported.. Either
polynomial may be selected In all Synchronous modes.
Users may preset the CRC generator and checker to all1's
or all O's. The ESCC also provides a feature that automatically transmits CRC data when no other data is available
for transmission. This allows for high speed transmissions
under OMA control, with no need for CPU intervention at
the end of a message. When there is no data or CRC to
send in Synchronous modes, the transmitter inserts 6-,8-,
or 16-bit sync characters, regardless of the programmed
character length.
SOLe Mode. The ESCC supports Synchronous bit-oriented
protocols, such as SOLC and HOLC, by performing automatic flag sending, zero insertion, and CRC generation.
A special command is used to abort a frame in transmission. At the end of a message, the ESCC automatically
transmits the CRC and trailing flag when the transmitter
underruns. The transmitter may also be programmed to
send an idle line conSisting of continuous flag characters
or a steady marking condition.

278

If a transmit underrun occurs in the middle of a message,
an extemal/status interrupt wams the CPU of this status
change so that an abort can be issued. The ESCC may also
be programmed to send an abort itself in case of an
underrun, relieving the CPU of this task. One to eight bits
per character can be sent, allowing reception of a message
with no prior information about the character structure in
the information field of a frame.
The receiver automatically acquires synchronization on
the leading flag of a frame in SOLe or HOLC and provides
a synchronization signal on the /SYNC pin (an interrupt can
also be programmed). The receiver can be programmed
to search for frames addressed by a single byte (or four
bits within a byte) of a user-selected addressor to a global
broadcast address. In this mode, frames not matching
either the user-selected or broad cast address are ignored.
ThEj number of address bytes are extended undersoftware
control. For receiving data, an interrupt on the first received
character, or an interrupt on every character, or on special
condition only (end-of-frame) can be selected. The receiver
automatically deletes all O's inserted by the transmitter
during character assembly. CRC is also calculated and is
automatically checked to validate frame transmission. At
the end of transmission, the status of a received frame is
available in the status registers. In SOLC mode, the ESCC

must be programmed to use the SOLC CRC polynomial,
but the generator and checker may be preset to all 1's or
all O's. The CRC is inverted before transmission and the
receiver checks againstthe bit pattern 000111 0100001111.
NRZ, NRZI or FM coding may be used in any 1x mode. The
parity options available in Asynchronous modes are
available in Synchronous modes.
SOLC Loop Mode. The ESCC supports SOLC Loop mode
in addition to normal SOLC. In an SOLC Loop, there is a
primary controller station that manages the message traffic
flow on the loop and any number of secondary stations. In
SOLC Loop mode, the ESCC performs the functions of a
secondary station while an ESCC operating in regular
SOLC mode acts as a controller (Figure 10). SOLC loop
mode can be selected by setting WR10 bit 01.

messages to the message of the first secondary station by
the same process. Any secondary stations without messages to send merely echo the incoming message and are
prohibited from placing messages on the loop (except
upon recognizing an EOP). In SOLC Loop mode, NRZ,
NRZI, and FM coding may all be used.
SOLC FIFO. The ESCC's ability to receive high speed
back-to-back SOLC frames is maximized by a 10- deep by
19-bit wide status FIFO. When enabled (through WR 15, bit
02), it provides the OMA the ability to continue to transfer
data into memory so that the CPU can examine the message later. For each SOLC frame, a 14-bit byte count and
5 status/error bits are stored. The byte count and status
bits are accessed through Read Registers 6 and 7. Read
Registers 6 and 7 are only accessible when the SOLC FIFO
is enabled The 10x19 status FIFO is separate from the
8-byte receive data FIFO.
Baud Rate Generator. Each channel in the ESCC contains
a programmable baud rate generator. Each generator
consists of two 8-bit time constant reDisters that form a
16-bit time consta.nt, a 16-bit down counter, and a flip-flop
on the output producing a square wave. On startup, the
flip-flop on the output -is set in a High state, the value in the
time constant register is loaded into the counter, and the
counter starts counting down The output of the baud rate
generator toggles upon reaching 0, the value in the time
constant register is loaded into the counter, and the
process is repeated. The time constant may be changed
at any time, but the new value does not take effect until the
next load of the counter.

Figure 10. An SOLC Loop
A secondary station in an SOLC Loop is always listening to
the messages being sent around the loop and, in fact,
passes these messages to the rest of the loop by
retransmitting them with a one-bit-time delay. The secondary station places its own message on the loop only at
specific times. The controller signals that secondary stations can transmit messages by sending a special character, called an EOP (End Of Poll), around the loop. The
EOP character is the bit pattern 11111110. Because of
zero insertion during messages, this bit pattern is unique
and easily recognized.
When a secondary station has a message to transmit and
recognizes an EOP on the line, it changes the last binary
1 of the EOP to a 0 before transmission. This has the effect
of turning the EOP into a flag sequence. The secondary
station now places its message on the loop and terminates
the message with an EOP. Any secondary stations further
down the loop with messages to transmit appends their

The output of the baud rate generator may be used as
either the transmit clock, the receive clock, or both It
can also drive the Digital Phase-Locked Loop (see next
section)
If the receive clock or transmit clock is not programmed to
come from the TRxC pin, the output of the baud rate
generator may be echoed out via the TRxC pin.
The following formula relates the time constant to the baud
rate where PCLK or RTxC is the baud rate generator input
frequency in Hertz. The clock mode is 1, 16, 32, or 64, as
selected in Write Register 4, bits 06 and 07. Synchronous
operation modes should select 1 and Asynchronous should
select 16, 32 or 64.

Time Constant =

PLCK or RTxC Frequency
2(Baud Rate) (Clock Mode)

-2

Digital Phase-Locked Loop. The ESCC contains a Digital
Phase-Locked Loop (OPLL) to recover clock information
from a data stream with NRZI or FM encoding The OPLL

279

ESCC DATA COMMUNICATIONS CAPABILITIES (Continued)
is driven by a clock that is nominally 32 (NRZI) or 16 (FM)
times the data rate. The DPLL uses this clock, along with
the data stream, to construct a clock for the data. This
clock is then used as the ESCC receive clock, the transmit
clock, or both. When the DPLL is selected as the transmit
clock source, it will provide a jitter free clock output that is
the DPLL input frequency divided by the appropriate
divisor for the selected encoding technique.
For NRZI encoding, the DPLL counts the 32x clock to
create nominal bit times. As the 32x clock is counted, the
DPLL is searching the incoming data stream for edges
(either 1 toO, orO to 1). Whenever an edge is detected, the
DPLL makes a count adjustment (during the next counting
cycle), producing a terminal count closer to the center of
the bit cell.
For FM encoding, the DPLL still counts from 0 to 31, but
with a cycle corresponding to two bit times. When the DPLL
is locked, the clock edges in the data stream should occur
between counts 15 and 16 and between counts 31 and O.
The DPLL looks for edges only during a time centered on
the 15 to 16 counting transition.

Manchester (bi-phase level) data by using the DPLL in the
FM mode and programming the receiver for NRZ data.
Manchester encoding always produces a transition at the
center of the bit cell. If the transition is 0 to 1, the bit is a O.
If the transition is 1 to 0, the bit is a 1.
Auto Echo and Local Loopback. The ESCC is capable of
automatically echoing everything it receives. This feature
is useful mainly in Asynchronous modes, but works in
Synchronous and SOLC modes as well. Auto Echo mode
(TxO is RxO) is used with NRZI or FM encoding with no
additional delay because the data stream is not decoded
before retransmission. In Auto Echo mode, the /CTS input
is ignored as a transmitter enable (although transitions on
this input can still cause interrupts if programmed to do so).
In this mode, the transmitter is actually bypassed and the
programmer is responsible for disabling transmitter interrupts and /WAIT//REQUEST on transmit.

o
Data

NRZ

The 32x clock for the DPLL can be programmed to come
from either the RTxC input or the output of the baud rate
generator. The DPLL output may be programmed to be
echoed out of the ESCC via the TRxC pin (if this pin is not
being used as an input).
Data Encoding. The ESCC may be programmed to encode
and decode the serial data in four different ways (Figure
11). In NRZ encoding, a 1 is represented by a High level
and a 0 is represented by a Low level. In NRZI encoding,
a 1 is represented by no change in level and a 0 is'
represented by a change in level. In FMl (more properly,
bi-phase mark), a transition occurs at the beginning of
every bit cell. A 1 is represented by an additional transition
at the center of the bit cell and a 0 is represented by no
additional transition at the center of the bit cell. In FMO (biphase space), a transition occurs at the beginning of every
bit cell. A 0 is represented by an additional transition at the
center of the bit cell, and a 1 is represented by no
additional transition at the center of the bit cell. In addition
to these four methods, the ESCC can be used to decode

280

'\-_-11

NRZI

FMl

FMO

Figure 11. Data Encoding Methods

The ESCC is also capable of localloopback. In this mode,
TxO or RxO is just like Auto Echo mode. However, in Local
Loopback mode the intemal transmit data is tied to the
internal receive data and RxO is ignored (except to be
echoed out via TxO). The ICTS and lOCO inputs are also
ignored as transmit and receive enables. However, transitions on these inputs can still cause interrupts. Local
Loopback works in Asynchronous, Synchronous and SOLe
modes with NRZ, NRZI or FM coding of the data stream.

NEW FEATURE DESCRIPTION
The following is a detailed description of the enhancements to the Z85230. ESCC from the standard SCC.
4-Byte Deep Transmit FIFO
The ESCC has a 4-byte transmit buffer with programmable
interrupt and OMA request levels. It is not necessary' to
enable the FIFO as it is always available. The user can
choose to have the Transmit Buffer Empty (TBE) interrupt
and OMA Request on Transmit be generated either when
the top byte of transmit FIFO is emptyor only when the FIFO
is completely empty. A hardware or channel reset will reset
the transmit shift register. flush the transmit FIFO. and set
WRT 05=1.
If the transmitter generates the Interrupt or OMA request
for data when the top byte of the FIFO is empty (WRT
05=0). the system can allow for a long response time to the
data request without underflowing. The interrupt service
routine can write one byte and then test RRO 02 if more
data may be written. The OMA Request in this mode will go
inactive after each data write and then go active again until
the FIFO is filled. The Transmit Buffer Empty status bit
(TBE). RRO bit 02. is set when the top byte of the FIFO is
empty. Note that this in NOT the reset state.
For applications where the frequency of interrupts is important. the transmit interrupt service routine can be optimized by programming the ESCC to generate the TBE
interrupt only when the FIFO is completely e.mpty (WRT
05=1) and then writing four bytes to fill the FIFO. When
WRT 05=1. only one OMArequest is generated (filling the
bottom of the FIFO). However. this may be preferred for
some applications where the possible reassertion of the
OMA request is not desired. The Transmit Buffer Empty
status bit (TBE). RRO bit 02. is set when the top byte of the
FIFO is empty. (Note that WRT 05=1 after a hardware or
channel reset).

By resetting WRT 03=0. applications which have a long
latency to interrupts can generate the request to read data
from the FIFO when one byte is available. and then test the
Receive Character Available bit to determine if more data
is available.
By setting WR7 03=1. the ESCC can be programmed to
interrupt when the receive FIFO is half full (4 bytes available) and. therefore. allowing the frequency of receive
interrupt to be reduced. If WRT 03 is set. the receive
character available interrupt is generated when there are
4 bytes available. Therefore. if the interrupt service routine
reads 4 bytes during each routine. the frequency of interrupts is reduced.
IfWRT 03= 1 and "Receive Interrupt on All Characters and
Special Conditions" is enabled. the receive character
available interrupt is generated when four characters are
available. However. when a character is detected to have
a special condition. a special condition interrupt is generated when the character is loaded into the top four bytes
of the FIFO. Therefore. the special condition interrupt
service routine should read RR 1 before reading the data to
determine which byte has the special condition.
Write Register 7' (7 prime)
A new register, WRT, has been added to the ESCC to
facilitate the programming of six new features. The format
of this register is shown in Figure 12.
WR 7'Prime

AutoTx Flag
Auto EOM Reset

Auto RTS Deactivation
Rx FIFO Int level

8-Byte Receive FIFO
The ESCC has an 8-byte receive FIFO with programmable
interrupt levels. The receive character available interrupt is
generated as selected by WRT bit 03. The Receive
Character Available bit, RRO ~O. is set when at least one
byte is available in, the top of the FIFO (independent of
WRT 03). It is not necessary to enable the 8-byte FIFO as
it is always available. A hardware or channel reset resets
the receive shift register and flushes th~ receive FIFO.
A OMA Request on Receive. if enabled. is generated
whenever one byte is available in the receive FIFO independent of WRT 03. If more than one byte is available in
the FIFO. the /Wait//Request pin goes inactive and then
goes active again until the FIFO is emptied.

DTR/REQ Timing Mode

Tx AFO Int level
Extended Read Enable
Not Used, Always 0

Figure 12, Write Register 7' (7 prime)
WRT is written to by first setting bit DO of Write Register 15
(WR 15 DO) to one. and then addressing WR7 as normal. All
writes to register 7 are to WRT while WR 15 DO is set. WR t 5
bit DO must be reset to 0 to address the sync character
register WR7. If bitD60f WRT is set, then WRT can be read
by doing a read cycle to RR t 4. The WRT features remain
enabled until specifically disabled or by a hardware or
software reset. Note that bit 05 is set after a reset All other
bits are reset to zerO following reset.

281

NEW FEATURE DESCRIPTION (Continued)
For applications which may use either the Zilog Z85C30 or
Z85230, these two device types can be identified in
software with the following test. Write a 01 hex to Write
Register 15. Then read Read Register 15 and if DO is re,set
it is a Z85C30 and, if DO is set it is a Z85230. Note that if the
device is Z85C30, a write to WR 15 resetting DO should be
done before proceeding. Also, if the device is Z85230, the
result in all writes to address seven will be'to WRT until
WR15 DO is reset.

transmit FIFO is completely empty. If this bit is reset. the
transmit buffer empty interrupt is generated when the top
byte of the transmit FIFO is empty. This bit is set following
a hardware or channel reset.
In OMA Request on Transmit mode, when using either the
/W//REO or /OTRI/REO pins, the request is asserted when'
the Tx FIFO is completely empty if WRT 05 is set. The
request is asserted when the top byte of the FIFO is empty
if 05 is reset.

Bit 7. Not used. This bit must always be written zero (0).
Bit 6. Extended Read Enable. Setting this bit enables the
ability t'o read WR3, WR4, WR5, WRT and WR10. These
registers are read by reading RR9 (WR3), RR4, RR5, RR14
(WRT), and RR11 (WR10), respectively.

Bit 4. /OTRI/REO timing. If this bit is set and the /DTRI/REO
pin is used forRequestmode(WR1402=1), the deactivation
of the /OTRI/REO pin will be identical to the /WI/REO pin as
shown in Figure 13. If this bit is reset. the deactivation time
is 4TcPc.

Bit 5. Transmit FIFO Interrupt Level. If this bit is set. the
transmit buffer empty interrupt is generated when the

twR

07-00

\'--_____1
~~_______T_m_n_s_m_it_D_a_m________.J;>(~

________________

WR704=1
IDTRIIREO

twAITIIREO

-----c./_ ~~~~:o___________ ,"
___I
Figure 13. PMA Request on Transmit Deactivation Timing

Bit3. Receive FIFO Interrupt Level. This bit sets the interrupt
level of the receive FIFO. If this bit is set, the receive data
available bit is asserted when the receive FIFO is half full
(4 bytes available). If the RFF bit is reset. the receive data
available interrupt is generated when a byte reaches the
top of the FIFO. See the description of the 8 byte receive
FIFO for more details.

that the ESCC should be programmed for "Flag on
Underrun" (WR1 0 02=0) for the /RTS pin to deassert atthe
end of the frame. This feature works independently of the
programmed transmitter idle state. In synchronous modes
other than SOLC, the /RTS pin will immediately follow the
state programmed into'WR5 01. When WRT 02 is reset.
the /RTS follOWS the state of WR5 01.

Bit 2. Automatic /RTS Pin Oeassertion. This bit controls the
timing of the deassertion of the /RTS pin in SOLC mode . .If
this bit is set and WR5 01 is reset during the transmission
of a SOLC frame, the de assertion of the /RTS pin is delayed
until the last bit of the closing flag clears the TxO pin. The
/RTS pin is pulled high after the rising edge of the transmit
clock cycle from the last bit of the closing flag. This implies

Bit 1. Automatic EOM Reset. If this bit is set. the ESCC
automatically resets the Tx Underrun/EOM latch and presets
the transmit CRC generator to its programmed preset state
,(per values set in WR5 02 and WR10 07). Therefore, it is
not necessary to issue the Reset Tx Underrun/EOM latch
command when this feature is enabled.

282

Bit O. Automatic Tx SOLC Flag. If this bit is set, the ESCC
will automatically transmit an SOLC flag before transmitting
data. This removes the requirement to reset the mark idle
bit (WR10 03) before writing data to the transmitter.
Modified Oatabus Timing
The ESCC's latching of the databus has been modified to
simplify the CPU Interface. The Z85C3O AC Timing parameter #29, Write Data to /WR falling minimum, has been
changed for the Z85230 to: /WR falling to Write Data Valid
maximum. See the AC Timing Characteristic section for the
specified time at each clock speed. The dafabus must be
valid no later than 20ns after the falling edge of /WR
regardless of the system (PCLK) clock rate. The databus
hold time, spec #30, remains at Ons.
Historically, the SCC has latched the databus on the falling
edge of /WA. However, as many CPUs do not guarantee
that the databus is valid when the /WR pin goes low, Zilog
has modified the data bus timing to allow a maximum delay
from the /WR signal going active low to the latching of the
databus.
Complete CRC Reception in SOLC Mode
In SOLC mode, the entire CRC is clocked into the receive
FIFO. The ESCC completes clocking in the CRC to allow it
to be retransmitted, unaltered, or manipulated in software.
In the SCC when the closing flag is recognized, the
contents of the receive shift register are immediately
transferred to the receive FIFO resulting in the last two bits
of the CRC being lost. In the ESCC, it is not necessary to
} program this feature. When the clOSing flag is detected,
the last two bits of the CRC are clocked into the receive
FIFO. In all othersynchronoOs modes, the ESCC does not
clock in the last two CRC bits (same as SCC).
TxO Forced High in SOLC with NRZI
Encoding When Marking Idle
When the ESCC is programmed for SOLC mode with NRZI
data encoding and mark idle (WR10 06=0,05=1,03=1),

Data

TXBE

Data

the TxO pin is automatically forced high when the transmitter goes to the mark idle state. There are several different
ways for the transmitter to go into the idle state. In each of
the following cases the TxO pin is forced high when the·
mark Idle condition is reached: data, CRC, flag and idle;
data, flag and idle; data, abort (on underrun) and idle;
data, abort (command) and idle; idle flag and command to
idle mark. The force high feature is disabled when ttie mark
idle bit is reset.
This feature is used in combination with the automatic
SOLC opening flag transmission feature, WRT 00=1, to
assure that data packets are properly formatted. Therefore,
when these features are used together, it is not necessary
for the CPU to issue any commands when using the force
idle mode in combination with NRZI data encoding. IfWRT
DO is reset. like in the SCC, it is necessary to reset the mark
idle bit (WR10 03) to enable flag transmission before an
SOLC packet is transmitted.
Faster Interrupt Response
The interrupt response time oltue ESCC has been improved
so that the liNT pin (regardless of the interrupt source) is
asserted low up to two clock cycles earlier than in the SCC
Improved TFcjI1smit Interrupt Handling
in Synchronous Modes
The ESCC latches the Transmit Buffer Empty (TBE) interrupt due to the CRC being loaded to the transmit shift
register even if the TBE interrupt, due at the last data byte,
has not yet been reset. Therefore, the end of a synchronous
frame is guaranteed to generate two TBE interrupts even
if a reset transmit buffer interrupt command for the data
created interrupt is issued after (time "A" in Figure 14) the
CRC interrupt had occurred. In this case, two reset TBE
commands are required. The TxlP is latched if the EOM
latch has been reset before the end of the frame.

CRCl

CRC2

Rag

--~;-\~----------~
Time "A"

TXIP Bit

___-..II
TXIPl

TXIP2

Figure 14. TxlP latching

283

NEW FEATURE DESCRIPTION (Continued)
,

DPLL Counter Tx Clock Source
When DPLL output is selected as the transmit clock source.
the DPLL counter output is the DPLL source clock divided
by the appropriate divisor for the programmed data encoding format. Therefore. in FM mode (FMO or FM1). the
DPLL counter output is the input frequency divided by 16.
DPLLCLK
Input

In NRZI mode. the DPLL counter frequency is the input
divided by 32. This feature provides a jitter-free output and
replaces the DPLL transmit clock output being available as
the transmit clock source. This has no effect on the use of
the DPLL as the receive clock source.

:: DPLL

DPLL Output to Receiver

'--:"-:....-III1...!D~P~L~L~C~o~un~t~er~_J------t~ DPLL Output to Transmitter

Input Divided by 16 (FMO or FM1)
Input Divided by 32 for NRZI

Figure 15. DPLL Outputs

Read Register 0 Status Latched During Read Cycle
The contents of Read Register zero. RRO. are latched
during a read to this register. The ESCC prevents the
contents of RRO to change while the Read cycle is active.
The SCC allows the status of RRO to change while reading
the register and. therefore. it is necessary to read RRO
twice to detect changes that otherwise may be missed.
The contents of RRO are updated after the rising edge
of/RD.
Software Interrupt Acknowledge
The Z85230 interrupt acknowledge cycle can be initiated
through software. If Write Register 9 (WR9) bit D5 is set.
reading register 2(RR2) results in an interrupt acknowledge
cycle to be executed internally. Like a hardware INTACK
cycle. a software acknowledge causes the INT pin to
return high. the lEO pin to go low and set the IUS latch for
the highest priority interrupt pending.
Similar to when the hardware INT ACK Signal can be used.
a software acknowledge cycle requires that a Reset Highest
IUS command be issued in the interrUpt service routine.
Whenever an interrupt acknowledge cycle is used. hardware or software. a reset highestiUS command is required.
If RR2 is read from channel A. the unmodified vector is
returned. If RR2 is read from channel B. then the vector is
modifieq to indicate the source of the interrupt. The Vector
Includes Status (VIS) and No Vector (NV) bits in WR9 are
ignored when bit D5 is set to 1.
When the INTACK and lEI pins are not being used. they
should be pulled up to Vcc through a resistor (10k ohm
typical).

284

Fast SDLC Transmit Data Interrupt Response
To more easily facilitate the transmission of back-lo-back
SDLC frames with a single shared flag between frames.
the ESCC allows data for a second frame to be written to
the transmit FIFO after the Tx Underrun/EOM interrupt has
occurred. This allo'{l's application software more time to
write the data to the transmitter while allowing the current
frame to be properly concluded with CRC and flag. The
SCC historically has required that data not be written to the
transmitter until a transmit buffer empty interrupt was
generated after the CRC has completed transmission If
data is written to the transmit FIFO after the Transmit
Underrun/EOM interrupt and before the transmit buffer
empty interrupt. the Automatic EOM Reset feature should
6e enabled (WRY' Dl=l), Consequently. the commands
"Reset Tx/Underrun EOM" latch and "Reset Tx CRC
Generator" should not be used.
SDLC FIFO Frame Status FIFO Enhancement
When used with a DMA controller. the Z85230 SDLC
Frame Status FIFO enhancement maximizes the ESCC's
ability to receive high speed. back-to-back SDLC messages. It minimizes frame overruns due to CPU latencies
in responding to interrupts. Additional logic was added to
the industry standard SCC consisting of a 10-deep by
19-bit status FIFO. 14-bit receive byte counter. and control
logic as shown in Figure 16. The 10 x 19 bits status FIFO
is separate from the 8-byte receive data FIFO.
When the enhancement is enabled. the status in read
register 1 (RR1) and byte count for the SDLC frame are
stored in the 10 x 19 bit status FIFO. This allows the DMA
controller to transfer the next frame into memory while the
CPU verifies that the message was properly received.

Summarizing the operation; data is received, assembled,
and loaded into the eight byte FI FO before being transferred
to memory by the OMA controller. When a flag is received
althe end of an SOLC frame, the frame byte countfrom the
14-bit counter and five status bits are loaded into the status
FIFO for verification by the CPU. The CRC checker is
automatically reset in preparation for the next frame which
can begin immediately. Since the byte count and status
are saved for each frame, the message integrity is verified
at a later time. Status information for up to 10 frames is
stored before a status FIFO overrun can occur.
If a frame is terminated with an ABORT, the byte count is
loaded to the status FIFO and the counter reset for the next
frame.
FIFO Detail. For a better understanding of details of the
FIFO operation, refer to the block diagram in Figure 16.
Enable/Disable. This FIFO is implemented so that it is
enabled when WR15, bit 02, is set and the ESCC is in the
SOLC/HOLC mode. Otherwise, the status register contents
bypass the FIFO and go directly to the bus interface (the
FIFO pOinter logic is reset either when disabled or via a
channel or power-on reset). When the FIFO mode is
disabled, the ESCC is completely downward compatible
with the NMOS Z8530. The FIFO mode is disabled on
power-up (WR15 02 is set to 0 on reset). The effects of
backward compatibility on the register set are that RR4 is
an image of RRO, RR5 is, an image of RR 1, RR6 is an image
of RR2 and RR7 is an image of RR3. For the details of the
added registers, refer to Figure 18. The status of the FIFO
Enable signal is obtained by reading RR15, bit 02. If the
FIFO is enabled, the bit will be set to 1; otherwise, it will
be reset
Read Operation. When WR15 bit 02 is sel ane the FIFO is
not empty, the next read to status register RRl or the
additional registers R'R7 and RR6, are from the FIFO.
Reading status register RR 1 causes one location of the
FIFO to be emptied, so status is read after reading the byte
count. otherwise the count is incorrect. Before the FIFO
underflows, it is disabled. In this case, the multiplexer is
switched to allow status to read directly from the status
register and reads from RR7 and RR6 contain bits that are
undefined. Bit 06 of RR7 (FIFO Oata Available) is used to
determine if status data is coming from the FIFO or directly
. from the status register, since it is set to 1 whenever the
FIFO is not empty.

The sequence for proper operation of the byte count and
FIFO logic is to read the registers in the following order:
RR7, RR6, and RR1 (reading RR6 is optional). Additipnal
logic prevents the FIFO from being emptied by multiple
reads from RR1. The read from RR7 latches the FIFO
empty/full status bit (06) and steers the status multiplexer
to read from the ESCC megacell instead of the status FIFO
(since the status FIFO is empty). The read from RR1 allows
an entry to be read from the FIFO (if the FIFO was empty,
logic was added to prevent a FIFO underflow condition).
Write Operation. When the end of an SOLC frame (EOF)
has been received and the FIFO is enabled, the contents
of the status and byte-count registers are loaded into the
FIFO. The EOF signal is used to increment the FIFO. If the
FIFO overflows, the RR7 bit 07 (FIFO Overflow) is set to
indicate the overflow. This bit and the FIFO control logic is
reset by disabling and re-enabling the FIFO control bit
(WR 15 bit 02). For details of FIFO controltimirTg during an
SOLC frame, refer to Figure 17.
SOLe Status FIFO Anti-Lock Feature. When the Frame
Status FIFO is enabled and the ESCC is programmed for
"Special Receive Condition Only" (WRl 04,;,03= 1), the
data FIFO is not locked when a character with End of
Frame status is read. When a character with the EOF status
is at the top of the FIFO, an interrupt with a· vector for
receive data is generated. The command "Reset Highest
IUS" must be issued at the end of the interrupt service
routine regardless if an interrupt acknowledge cycle had
been executed (hardware or software). This allows a OMA
to complete transfer of the received frame to memory and
then interrupt the CPU that a frame has been completed
without locking the FIFO. Since in the "Receive Interrupt on
Special Condition Only" mode the interrupt vector for
receive data is not used, it is used to indicate that the last
byte of a frame has been read out the receive FIFO. This
eliminates having to read the frame status (CRC and other
status is stored in the status FIFO with the frame byte
count).
When a character with a special receive condition other
than EOF is received (receiver overrun, or parity), a special
receive condition interrupt is generated after the character
is read from the FIFO and the receive FIFO is locked until
the "Error Reset" command is issued.

Since not all status bits are stored in the FIFO, the All Sent,
Parity, and EOF bits bypass the FIFO. The status bits sent
through the FIFO are Residue Bits (3), Overrun, and
CRC Error.

.285

NEW FEATURE DESCRIPTION (Continued)
q,

Frame Status FIFO Circuitry

RR1

.
..

. . - - - ' Reset on Flag Detect

SCC Status Reg
Residue Bits(3)
Overrun, CRC Error

Byte Counter

I
...-------1

5 Bits

14 Bits

FIFO Array
10 Deep by 19 Bits Wide

Increment on Byte DET,
Enable Count in SDlC
End of Frame Signal - - - ,
Status Read Comp
Tail Pointer
4-Bit Counter
Head Pointer
4-Bit Counter
4-Bit Comparator

5 Bits

Over

EOF=1

Equal

6 Bits '" 8 Bits

~"'---.. ,,-J-~L
' " 6-Bit MUX " . . . . . f - - - - - - - t - - - - + - - f EN 1 - - - - t - - - - ; - - .

2 Bits

~ 6 Bits

Bi!7 Bi:6

RR1

Bits 5-0

RR6

Interfage
toSCC

IRR7
D5-DO + RR6 D7 - DO
Byte Counter Contains 14 bits
for a 16 KByte maximum count.
RR7D6
FIF,O Data available status bit Status Bit set to 1
When reading from FIFO.
RR7D7
FIFO Overflow Status Bit
MSB pf RR(7) is set on Status FIFO overflow

In SDlC Mode the following definitions apply.
" All Sent bypasses MUX and equals contents of SCC Status Register.
- Parity Bits bypasses MUX and does the same.
- EOF is set to 1 whenever reading from the FIFO.
Figure 16. SOlC Frame Status FIFO

286

FIFO Enable

WR(15) Bit 2
Set Enables
Status FIFO

Internal Byte Strobe
Increments Counter

Don't Load
Counter On
1st Rag
Reset Byte
Counter Here

Internal Byte Strobe
Increments Counter
Reset
Byte Counter
Load Counter
Into FIFO and
Increment PTR

Reset
Byte Counter
Load Counte,
Into FIFO And
Increment PTR

Figure 17. SDLC Byte Counting Detail

PROGRAMMING
The ESCC contains write registers in each channel that are
programmed by the system separately to configure the
functional uniqueness of the channels.
In the ESCC. the data registers are directly addressed by
selecting a High on the Ol/C pin. With all other registers
(with the exception of WRO and RRO), programming the
write registers requires two write operations and reading
the read registers requires both a write and a read operation. The first write is to WRO and contains three bits that
point to the selected register. The second write is the
actual control word for the selected register, and if the
second operation is read, the selected read register is
accessed. All of the ESCC registers, including the data
registers, may be accessed in this fashion. The pointer bits
are automatically cleared after the read or write operation
so that WRO (o~ RRO) is addressed again.
Initialization. The system program first issues a series of
commands to initialize the basic mode of operation. This is
followed by other commands to qualify conditions within
the selected mode. For example, in the Asynchronous
mode, character length, clock rate, number of stop bits,
and even or odd parity should be set first. Then the
interrupt mode is set. and finally, the receiver and transmitter
are enabled.

Write Registers. The ESCC contains 16 write registers (17
counting the transmit buffer) in each channel. These write
registers are programmed separately to configure the
functional "personality" of the channels. There are two
registers (WR2 and WR9) shared by the two channels that
are accessed through either of them. WR2 contains the
interrupt vector for both channels, while WR9 contains the
interrupt control bits and reset commands. A new register,
WR7', was added to the ESCC and may, be written to if
WR15 00 is set. Figure 18 shows the format of each write
register.
Read Registers. The ESCC contains ten read registers
(eleven, counting the receive buffer (RR8) in each channel). Four of these may be read to obtain status information
(RRO, RR1, RR1O, and RR15). Two registers (RR12 and
RR13) are read to learn the baud rate gEme'rator time
constant. RR2 contains either the unmodified interrupt
vector (Channel A) or the vector modified by status information (Channel 8). RR3 contains the Interrupt Pending
(IP) bits (Channel A only). RR6 and RR7 contain the
information in the SOLC Frame Status FIFO, butis only read
when WR15 02 is set. If WRT 06 is set. Write Registers
WR3, WR4, WR5, WRT, and WR10 can be read as RR9,
RR4, RR5, and RR14, respectively.

287

, CQNTROL REGISTERS
Write Register 0 (norHnullplexec! bUs mode)

1071061051041031021011 DO

Write Register 2

I I I

0
0
0
0
1

1
1
1

0
0

1
1

0
0
1

0
0

1
1

0
0
0
1
1
1
1
0
0
0
0
1
1
1
1 .

1
1
0
0

1
1

1 Register 1
Register 2
Register 3

0
1
0

1 RegisterS
0
1
0
1
0
1
0
1
0
1

RegisterS

=::=;~

}

Interrupt
Vecklr

VS
V6

Write Register 3

Null Code
Point High
Reset ExtISta1us Interrupts
,
Send Abort (SOlC)
Enable Int on Next Ax Character
Reset Tx Int Pending
EnorReeet
Reset Highest IUS

Ax Enable
Sync Character lDad Inhibit
Address SeaJCh Mode (SOLC)

Ax CRC Enable

o
o

0
1
0
1

1
1

Enter Hunt Mode

NUIlCode
Reset Ax ORC Checker
Reset Tx CRC Generator
Reeet Tx UndelTunlEOM l.aIch

Auto Enables

o
o

Wlh Point High Command

1
1

0
1
0
1

Ax S BltslCharacter
Rx 7 BltslCharacter
Rx 6 BItBICharacter
Rx 8 BitBlCharacter '

Write Register 1
WrRe Register 4

~
0
0
1
1

0
1
0
1

Ext Int Enable
Tx Int Enebie

Parity Enable

Parity Is Special Condition

Parity EVEWIOOO

Ax Int Disable
Rx Int On First Character or Special Condition
Int On AM ,Rx Characters or Special Condition
Ax Int On Special CondItion Only

o
1
1

0
1
0
1

Sync Modes Enable
1 Slop Bft/Character
1 112 Slop Bits/Character
2 Slop 8itBICharacter

WAITIDMA ~uest On
IWAITIDMA Request Function

o
o
1

0
1
0

WAITIDMA Request Enable

Receive/fTransmR

8-Bit Sync Character
16-Blt Sync Character
SOLC Mode (01111110 Flag)
External Sync MOde

o
o

0 XI Clock Mode
1 X16 Clock Mode

1
1

0
1

X32 Clock Mode
X64 Clock Mode

Figure 18. Write Register Bit Functions

288

Write Register 5

Tx CRC Enable
RTS
ISDlC/CRC-16
Tx Enable

SendBrsak

o
o

0 Tx 5 BIIs(Or L968)/Charac:ter
1 Tx 7 BIIBICherac:ter
0 \Tx 6 Bils/Character
1 'Tx 8 BIIBICharacter

1
1

DTR

Write Register 6

Sync7
Sync1
Sync7
Sync3
ADR7
ADR7

Sync6
SyncO
SyncS
Sync2
ADR6
ADR6

Sync5
SyncS
Sync5
Sync1
ADR5
ADRS

Sync4
Sync4
Sync4
SyncO
ADR4
ADR4

Sync3
Sync3
Sync3
1
ADR3
x

Sync2
Sync2
Sync2
1
ADR2
x

Syncl
Sync1
Sync1
1
ADR1

SyncO
SyncO
SyncO
1
ADRO
x

Monosync, 8 Bits
Monosync, 6 Bits
Bisync, 16 Bits
Bisync, 12 Bits
SDlC
SDLC (Address Range)

Write Register 7

Sync7
SyncS
Sync15
Sync11

Sync6
Sync4
Sync14
Sync10

SyncS
Sync3
Sync13
Sync9

Sync4
Sync2
Sync12
Sync6
1

Sync3

Sync2 Sync1
Sync1
x
SyncO
Sync11 Sync10 Sync9
Sync7 Sync6 SyncS

SyncO

x
SyncS
Sync4

Monosync, 8 Bits
Monosync, 6 Bits
Bisync, 16 Bits
Bisync, 12 Bits
SDLC

Figure 18_ Write Register Bit Functions (Continued)

289

CONTROL REGISTERS (Continued)
Write, Register 10 ,

WR7'Prime

L,.

L.=

6-8iW8·B~ Sync

AutoTxFIag

Auto EOM Reeet

Loop Mode

AuloRTSD_n

AborlilFlag On Unclerrun
MarkilFlag Idle

Ax FIFO Int Level

Go ActIve On Poll

DTRlREQ Tlmlng Mode
Tx FIFO Int Level

Extended Read Enable

Not Used, Always 0

o
o
1
1

0 NRZ
1 NAZI
0 FMl (Transition = 1)
1 FMO (Transition = 0)
CAC Preset 1110

Wille Reglsl8r 9
Write Register 11

I I
0
0
1
1

NoReseI

o
1

1
0

Channel_ B
Channel Reoet A

fTAx C Oul. Xlal OUtpul
fTRx C Out • Trensmft Clock
fTRx C OUt = BR Generator Output
fTAx C Oul. DPLL Outpul
fTRxCo/l

Sottwa...INTACK Enable

0
1
0
1

0
0
1
1

l I F o.... Hardw.... Resel

0
0
1
1

0
1
0
1

0 TrensmkClock= iRTxC Pin
1 Transm~ Clock. fTRxCPIn
0 Transmft Clock. BR Generator Output
1 Trensmft Clock = DPLLOutpuI

Aecelve Clock ./RTxC Pin
Aecelve Clock = ITAxC Pin
Aecelve Clock • BR Generalor OUtput
Aecelve Clock • DPLL OUtput
IRTxC XtaIIlNo Xtal

Figure 18. Write Register Bit Functions (Continued)

290

Wrtte Register 12

Write Register 14

TCO

BR Generator Enable

TCl

BR Generator

TC2

IDTRlRequest Function

TC3

TC4

Sour""

Auto Echo

Lower Byte of
Time Constant

LocaII.oopback

TC5

a a a
a a 1
a 1 a
a 1 1
1
a 0
1
a 1
1
a
1

TC6
TC7

Write Register 13

NuRCommand
Enter Search Mode
Reset Missing Clock
Disable DPLL
Set Source = BR Generator
Set Source =IRTxC
SetFMMode
Set NAZI Mode

Write Register 15

TC8
TC9

TCla

WR7' SOlC Feature Enable

TCll

Upper Byte of

TC12

lime Constant

TC13

TC14
TC15

Zero .Count IE

SOLC FIFO En,abIe
DCOIE
Sync/Hunt IE
CTSIE
Tx Underrun/EOM IE
B",al"r,,,.,,,, ''', , .. I

"' .. ,,....,IiI1l'

,-,'.

;,"

'~""""""''''',''

",'

Z85230 TIMING
The ESCC generates internal control signals from the /WR
and IRO that are related to PCLK. Since PCLK has no
phase relationship with /WR and IRO, thecircuitry generating the internal control signals provides time forrnetastable
conditions to disappear. This gives rise to a recovery time
related to PCLK. The recovery time applieS only between
bus transactions involving the ESCC. The recovery time
required for proper operation is specified from the falling
edge of /WR or IRO in the first transaction involving the
ESCC to the falling edge of /WR o~ IRO in the second
NIB.O//c

nNTACK

Read Cycle Timing. Figure 20 illustrates Read cycle timing.
Addresses on Al/B and O//C and the status on IINTACK
must remain stable throughout the cycle. If ICE falls after
IRO falls, or if it rises before IRO rises, the effective IRO is
shortened.

________')(~_____________~
___
es_s_vM_'_d_______________~

\~--

ICE

07-00

transaction involving the ESCC. This time must be at least
4 PCLKs regardless of which register or channel is being
accessed.

----------------------«"'____..IX .

Data Valid

fRO

»).----------

___--'I

Figure 20. Read Cycle Timing

Write Cycle Timing. Figure 21 illustrates Write cycle timiflg.
Addresses on Al/B and O//C and the status on IINTACK
must remain stable throughout the cycle. If ICE falls after
/WR falls, or if it rises before /WR rises, the effective /WR is
shortened. Because many popular CPUs do not guaran-

NIB,OIlC

IINTACK

ICE

07-00

IWR

tee that the databus is valid when IWR is driven low, the
i::Jatabus timing requirements of the ESCC have been
modified so that the databus does not have to be valid
when the /WR pin goes low. See AC Characteristic #29 for
details.

V-X- - - - -~ress
----"----Valid

----'

\~-

Add
__r_e_sS_V_al_id____

_ _ _ _-..1

Figure 21. Write Cycle Timing

294

..I:>).-------

------------------------~<:"'____

Interrupt Acknowledge Cycle Timing. Figure 22 illustrates
Interrupt Acknowledge cycle timing. Between the time
/INTACK goes Low and the falling edge of /RD, the internal
and external lEI/lEO daisy chains settle. If there is an
interrupt pending in the ESCC and lEI is High when /RP
falls, the Acknowledge cycle is intended for the ESCC. In
this case, the ESCC may be programmed to respond to
/RD Low by placing its interrupt vector on D7-DO. It then

IINTAct<

IRD

D7'[)O

sets the appropriate Interrupt-Under-Service latch internally. If the external daisy chain is not used, then AC
parameter #38 is required to settle the interrupt priority
daisy chain internal to the ESCC. If the external daiSy chain
is used, the user should follow the equation in AC Characteristics, Note 5, for calculating the required daisy-chain
settle time.

~/F------------1/
u

' _____1

---------J./J.,.. ------t(...___IX

Vector

»)0-----

Figure 22. Interrupt Acknowledge Cycle Timing

OTHER ZILOG DATA C9MMUNICATIONS PRODUCTS
SIO Family
Z84C4DSI0
Z84C131PC
Z84C151PC

Dual channel multiprotocol USART.
Z8D CPU with integrated SIO, CTC and WDT.
Z8D CPU with integrated SIO, CTC, WDT and PIO.

SCCFamily
Z08530SCC
Z08030SCC

Z85C3DSCC
Z80C3DSCC
Z16C351SCC
Z80181 SAC

NMOS SCC Low cost with speeds up to 8 MHz.
NMOS SCC for multiplexed busses.
CMOS SCC at speeds up to 16 MHz. NMOS compatible.
CMOS SCC for multiplexed busses.
SCC with 4 channel DMA and advanced CPU interface.
Z180 CPU with integrated single channel SCC.

USC family
Z16C30 USC
Dual channel high performance multi-protocol data communications up to 10 Megabits/second
Z16C33 MUSC Single channel USC w/ISDN Time Slot Assigner.
Z16C31 IUSC . MUSC with high perfon:nance dual channel DMA (available Q1/91).
Z16C50 DDPLL Dual channel DPLL cell from the USC.

295

ABSOLUTE MAXIMUM RATINGS
Vee Supply Voltage range .......................... -O.3V to +7.0V
Voltages on all pins
with respect to GND .............................. -3V to Vee +O.3V
Operating Ambient
Temperature ..................'.......... See Ordering Information
Storage Temperature ............................. -65°C to +150°C

Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.

STANDARD TEST CONDITIONS
The DC Characteristics and capacitance sections below
apply for the following standard test conditions, unless
otherwise noted. All voltages are referenced to GND.
Positive current flows into the referenced pin.

Standard conditions are as follows:

•
•
•

+4.50 V ~ Vee ~ + 5.50 V
GND = OV
TA as specified in Ordering Information

+5V
+5V

2.1 K
2.2K
From Output
Under Test

0 - - - -....- ..........- - 0 - - 4
From Output

100p!

50 pI

Figure 24. Open-Drain Test Load

FI.gure 23. Standard Test Load

CAPACITANCE
Symbol, Parameter
Input Capacitance
Output Capacitance
Bidirectional Capacitance
Note:

! = 1 MHz, over speci/ied temperature range.
Unmeasured pins returned to Ground.

MISCELLANEOUS
Gate Count - 6800

296

Min

Max

Unit

10
15

pF
pF
pF

Test Condition
Unmeasured Pins
Returned to Ground

DC CHARACTERISTICS
Z85230
Symbol

Parameter
Input High Voltage
Input Low Voltage
Output High Voltage
Oytput High Voltage
Output Low Voltage
Input Leakage
Output Leakage
Vcc Supply Current

Iccase

Crystal OSC Ourrent

Min

Typ

2.2
-0.3
2.4
Vcc-0.8

Max

Unit

Vcc+0.3
0.8

V
V
V
V
V

0.4

5
7
9
6

±10.0
±10.0
12 (10 MHz)
1'5 (16MHz)
20 (20 MHz)

J.IA
J.IA
mA
mA
mA
mA

Condition

10H
10H
10l

= -1.6mA
= -250J.IA
+ 2.0mA

0.4 V1N+2.4V
0.4 Vout +2.4V
Vcc=5V V1H =4.8 V,l=0.2V
Crystal Oscillators off
I

Current for each osc.
in addition to ICCl

Notes:
[1] Voc = 5V ± 10% unless otherwise specified, over specified terrperature range.
[2] Typical Icc was measured with oscillator off.
[3] No Icc(ose) max is specified due to dependency on the external circuit.

297

AC CHARACTERISTICS
Z85230 Read and Write Timing Diagram

PCLK

fCE

~ ~

(

.~
flNTACK

---

---®-

,,!..

AlIB.OI/C

0:J
.
r-

fo---.o. -0

t---(9)

r'L
"

f--®

-®-

~
Read

@-J'

'22'
.~

*'k

Active

k®-l

Valid

®25

"ii'

~l@

J-I

!WR
~

07-00
Write

~ -®- f---!WfIREO
Wait

"'"
=

!WI/REO
Request
fOTRtfREO
Request

+-@~

I
~

liNT

fait

Figure 25. Z85230 Read and Write Timing Diagram

Figure 26. Reset Timing Diagram

298

f-I.@

-'LJ

fRO

07-00

....... ~

PCLK

IINTACK

IRO

D7~ --------------~~--------_++__G

lEI

lEO

liNT

Figure 27. Interrupt Acknowledge Timing Diagram

ICE

IRDorlWR

Figure 28. Cycle Timing Diagram

AC CHARACTERISTICS
Z85230 Read and Write Timing Table
No

Symbol

Parameter

1
2

TwPCI
TwPCh
TfPC
TrPC
TcPC

PCLK Low Width
PCLK High Width
PCLK Fall Time
PCLK Rise Time
PCLK Cycle Time

TsA(WR)
ThA(WR)
TsA(RO)
ThA(RO)
TsIA(PC)

Address to /WR Fall Setup Time
Address to /WR Rise Hold Time
Address to IRO Fa" Setup Time
Address to IRO Rise Hold Time
liNTACK to PCLK Rise Setup Time

4
5
6
7

8
9

10 MHz
16 MHz
20 MHz
Min
Max Min
Max Min
Max

1000 26
1000 26
10
10
2000 61

1000 22
1000 22
5
5
2000 50

50
0

0
15

40
40
100

Notes

1000
1000
5
5
2000

299

AC CHARACTERISTICS
Z85230 Read and Write Timing Table
No

Symbol,

Parameter

11
12
13
14
15
16

TsIAi(WR)
ThIA(WR)
TsIAi(RD)
ThIA(RD)
ThIA(PC)
TsCEI(WR)

liNTACK to /WR Fall Setup Time
IINTACK to /WR Rise Hold Time
IINTACK to IRD Fall Setup Time
IINTACK tolRD Rise Hold Time
liNTACK to PCLK Rise Hold Time
ICE Low to /WR Fall Setup Time

17
18
19
20
21
22

ThCE(WR)
TsCEh(WR)
TsCEI(RD)
ThCE(RD)
TsCEh(RD)
TwRDI

ICE to (:NR Rise Hold Time
ICE High to /WR Fall Setup Time
ICE Low to IRD Fall Setup Time
ICE to IRD Rise Hold Time
ICE High to IRD Fall Setup Time

23
24
25
26
27
28

TdRD(DRA)
TdRDr(DR)
T.dRDI(DR)
TdRD(DRz)
TdA(DR)
TwWRI

IRDlow Wi,dth

IRD Fall to Read Data Active Delay
IRD Rise to Data Not Valid Delay
IRD Fall to Read Data Valid Delay
IRD Rise to Read Data Float Delay
Addr to Read Data Valid Delay
/WR Low Width
/WR Fall tb Write Data Valid Delay
Write Data to /WR Rise Hold Time
'twR Fall to Wait Valid Delay
IRD Fall to Wait Valid Delay
/WR Fall to /WI/REO Not Valid Delay
IRD' F~II to /WI/REO Not Valid Delay

29
30
31
32
33
34

JdWR(DW)
ThDW(WR)
TdWR(W)
TdRD(W)
TdWRf(REO)
TdRDf(REO)

35a
35b
36
37
38
39

TdWRr(REO) /WR Fall to /DTRI/REO Not Valid
TdWRr(REO) /WR Fall to /DTR//REO Not Valid
TdRDr(REO) IRD Rise to IDTRI/REO Not Valid Delay
TdPC(INT)
PCLK Fall to liNT Valid Delay
TdIAi(RD)
IINTACK to IRD Fall (Ack) Delay
TwRDA
IRD (Acknowledge) Width

40
41
42
43
44

TdRDA(DR)
TsIEI(RDA)
ThIEI(RDA)
TdIEI(IEO)
TdPC(IEO) ,

IRD Fall(Ack) to Read Data Valid Delay

TdRDA(INT)
TdRD(WRO)
TdWRO(RD)
TwRES
Trc

IRD Fall to liNT Inactive Delay
IRD. Rise to /WR Fall Delay for No Reset
twR Rise to IRD Fail Delay for No Reset
twR and IRD low for Reset

46
47
48
49

lEI to IRD Fall (Ack) Setup Time
lEI to IRD Rise (Ack) Hold Time
lEI to lEO Delay Time
PCLK Rise to lEO Delay

Valid Access Recovery Time

10MHz
16 MHz
20 MHz
Min
Max
Max Min
Max Min
70
'0
70
0
15
0

130
0
130
0
30

a
a
50
a

0
50
125

a
a

65
0

[1 J

0
30
0
0
30
70

25
65

[1 J
[1]
[1 J
[lJ

a
15
a
a
25
a
a

0
• 70
20
100

120
35
180
125

65
20

90
65

75
20,

a
100
100 '
120
120

20
0
50

50
50
70
70

NA
320
125

45
65

120
95

60
45

200

320

15
15
100
4TcPc

10
10
75
4TcPc

4TcPc
65
NA

[6J

[5]

40
70

45
80

175

[6J

50
75

(4]
[4]

4TcPc
70
NA
175

4TcPc
100

Notes

180
10
10
65
4TcPc

[4]

[3J

Notes:
[1) Parameter does not apply to Interrupt Acknowledge tral)sactions.
[3) Parameter applies only between transactions involving the ESCC.
[4) Open-drain output, measured with open-drain test load.
[5) Parameter is system dependent. For any ESCC in the daisy chain, TdIAi(RD) must be greater than the sum of TdPC(IEO) for the highest priority
device in the daisy chain. TsIEI(RDA) for the ESCC and TdIEI(IEO) f9r each device separating them In the daisy chain.
[6) Parameter applies to enhanced Request mode only (WA7' 04=1)

300

AC CHARACTERISTICS
Z85230 General Timing Diagram
PCLK

IWIIREQ

Request

IW/IREQ

W~ __________________~------------------------I

IRTxC. ITRxC

ReceIve ___________"1

RxD

/SYNC

External

1TRxC.IRTxC

Transmit

~
TxD

~~_X-_----'lX~-

~----- @_'3~_-_-_--~~l<--------------------------

_----'
___________

IRTXC~

/TRxC

' ___....II

~'---'b4d-----'~----Jr

--c=bd

lCTS,tDCD

--~

/sYNC

Input

{-----

Figure 29. Z85230 General Timing Diagram

301

_ _ ......"~"~""_J'

•

'r,........"..· _ _ ·_"_·J·'·, .. ,~ _ _ _ _ _ "_,~~..... ,......"',"",Ir",

.....

"".J"""-.-~I~;-r-l_',,'

,'~'·"'·I""""""

AC CHARACTERISTICS
Z85230 General Timing Table (Preliminary)
10 MHz
Min
Max

16 MHz
Min
Max

20 MHz
Min
Max

200

80
180
NA

70
170
NA

Symbol

Parameter

1
2
3
4

TdPC(REQ)
TdPC(W)
TsRXC(PC)
TsRXD(RXCr)

/PCLK toW/REQ Valid
/PCLK to Wait Inactive
/RxC to /PCLK Setup Time
RxD to /RxC Setup Time

NA
0

5
6
7
8

ThRXD(RxCr)
TsRXD(RXCf)
ThRXD(RXCf)
TsSY(RXC)

RxD to /RXC Hold Time
RxD to /RXC Setup Time
RXD to /RXC Hold Time
/SYNC to /RxC Setup Time

125
0
125
-150

50
0
50
-100

·90

9
10
11
12

ThSY(RXC)
TsTXC(PC)
TdTXCf(TXD)
TdTxCr(TXD)

/SYNC to/RXC Hold Time
/TxC to IPCLK Setup Time
/TxC to TxD Delay
/TxC to TxD Delay

5TcPc
NA

13
14
15
·16a

TdTXD(TRX)
TwRTXh
TwRTXI
TcRTX

TxD to TRxC Delay
RTxC High Width
TRxC Low Width
RTxC Cycle Time

120
120
400

16b
17
18
19

TxRX(DPLL)
TcRTXX
TwTRXh
TwTRXI

DPLL Cycle Time Min
Crystal Osc. Period
TRxC High Width
TRxC Low Width

50
100
120
120

20
21
22

TcTRX
TwEXT
TwSY

TRxC Cycle Time
DCD or CTS Pulse Width
SYNC Pulse Width

400
120 '
120

300
NA

NA
0

150
150

45
0

70
70

31
61
80
80

70
70

244
70
70

[6]
[6]
[6,7]

200
1000

[1]
[2.4]
[2]
[2,5]

80
80
80
244

[1.4]
[1]
[1]
11,5]
[1,5]
[1]

80
80

140

.1000

NA
0

Notes

31
61
70
70

200

1000

[7,8]
[3]
[6]
[6]
[6,7]

Noles:
[1) RxC is /RTxc or (TAxC, whichever is supplying the receive clock.
(2) TxC is {TRxC or /RTxC, whichever is supplying the transmit clock.
[3] Both /RTxC and /SYNC have 30 pF capacitors to ground connected to them.
[4] Synchronization of AxC to PClK is eliminated in divide by four operation.
[5] Parameter applies only to FM encoding/decoding.
[6] Parameter applies only for transmitter and receiver; DPLl and baud rate generator timing requirements are identical to case PCLK requirements.
[l} The maximum receive or transmit data rate Is 1/4 PClK.
[8] Applies to DPLl clock source only. Maximum data rate of 1/4 PCLK still applies. DPLl clock should have a 50% duly cycle.

302

AC CHARACTERISTICS
Z85230 System Timing Diagram (Preliminary)
IRTxC, ITRxC
Receive

!W/REO
Request

!W/REO
Wait

-----------------------+-----------'

t-----<..2:>-----1~

ISYNC
Output

IlNT

IRTxC, ITRxC
Transmit

!WI/REO
Request

!WI/REO
Wan ________________________~-------------J
....--46i)---~

IDTRl/REO
Request

liNT

ICTS,
lOCO

ISYNC
Input

K.
~-

liNT

If'"

Figure 30_ Z85230 System Timing

303

AC CHARACTERISTICS
Z85230 System Timing Table (Preliminary)

Symbol

Parameter

1
2
3
4

TdRXC(REQ)
TdRXC(W)
TdRXC(SY)
TdRXC(INT)
TdTXC(REQ) .

IRXC to /WI/REO Valid
IRxC to /Wait Inactive
IRxC to ISYNC Valid
IRxC to liNT Valid
/TxC to /w/IREQ Valid

TdTXC(W)
TdTXC(DRO)
TdTXC(INT)
TdSY(INT)
TdEXT(INT)

/TxC to /Wait Inactive
/TxC to /DTR/lREQ Valid
/TxC to liNT Valid
ISYNC to liNT Valid
lOCO or ICTS to liNT Valid

5
6
7
8

9
10

10 MHz
Min
Max

4
10

12
12
7
16

5
5

8
8

4
6
2
2

~"':."!~:

(1) Open drain-output, measured with open-draln test load.
(2) /RxC is /RTxC or /TRXC, whichever is supplying the receive clock.
(3) /TxC is /TRXC or /RTxC, whichever is supplying the transmit clock.

16 MHz
Min
Max

20 MHz
Min
Max

4
10

12
14
7
16

4
10

12
14
7
16

11
7
10

11
7
10
6
6

4
6
2
2

7
10
6
6

6
6

8
8

4
6
2
2

8
8

Notes
[2] .
[1,2]
[2]
[1,2]
[3]
[1,3]
[3]
[1,3]
[1]
[1]

~Zirm

PRODUCT SPECIFICATION

Z80C30/Z85C30

CMOS Z-BUS@ SCC"IM
SERIAL COMMUNICATION CONTROLLER

FEATURES
•

Low power CMOS

•

Pin compatible to NMOS versions

•

Two independent, 0 to 4.1 Mbit/second, full-duplex
channels, each with a separate crystal oscillator, baud
rate generator, and Digital Phase-Locked Loop (DPLL)
for clock recovery.

•

Multi-protocol operation under program control;
programmable for NRZ, NRZI, or FM data encoding.

•

Asynchronous mode with five to eight bits and one,
one and one-half, or two stop bits per character,
programmable clock factor, break detection and
generation; parity, overrun, and framing error detection.

•

Synchronous mode with internal or external character
synchronization on one or two synchronous characters
and CRC generation and checking with CRC-16 or
CRC-CCITT preset to either 1s or Os.

•

SDLC/HDLC mode with comprehensive frame-level
control, automatic zero insertion and deletion, I-field
residue handling, abort generation and detection,
CRC generation and checking, and SDLC Loop.

•

Software Interrupt Acknowledge feature

•

Local Loopback and Auto Echo modes

•

Supports T1 digital trunk

•

Enhanced DMA support
10 x 19-bit status FIFO
14-bit byte counter

•

Fast speeds:
10.0 MHz for data rates up to 2.5 Mbyte/sec.
16.384 MHz for data rates up to 4.096 Mbyte/sec.

GENERAL DESCRIPTION
The Zilog Serial Communications Controller, Z80C30/
Z85C30 SCC, is a pin and software compatible CMOS
member of the SCC family introduced by Zilog in 1981. It
is a dual channel. multi-protocol data communications
peripheral that easily interfaces to CPU's with either mUltiplexed or non-multiplexed address/data buses. The advanced CMOS process offers lower power consumption,
higher performance, and superior noise immunity, The
programming flexibility of the internal registers allows the
SCC to be configured to satisfy a wide variety of serial
communications applications. The many on-chip features
such as baud rate generators, digital phase locked loops,
and crystal oscillators dramatically reduce the need for
external logic. Additional features including a 10 x 19-bit
status FIFO and 14-bit byte counter were added to support
high speed SDLC transfers using DMA controllers.
The SCC handles asyn'chronous formats, synchronous
byte-oriented protocols such as IBM Bisync, and synchro-

nous bit-oriented protocols such as HDLC and IBM SDLC.
This versatile device supports virtually any serial data
transfer application (casette, diskette, tape drives, etc.)
The device can generate and check CRC codes in any
synchronous mode and can be programmed to check
data integrity in various modes. The SCC also has faCilities
for modem controls in both channels. In applications
where these controls are not needed, the modem controls
can be used for general-purpose I/O.
The daisy-chain interrupt hierarchy is also supported as is
standard for Zilog peripheral components.
Note: All Signals with a preceding front slash, "/", are active
Low, e.g.: BIIW (WORD is active Low); IBIW (BYTE is
active Low, only); INIIS (NORMAL and SYSTEM are both
active Low).

305

Transmit Logic

TransmitMUX

'Transmit FIFO

BUffer'

Data Encoding & CRC
Generation

TxOA

•

Channel A
Exploded View

Receive and Transmit Clock Multipexer

fTRxCA
IRTxCA

Digital
Phase-Locked

Crystal
Oscillator
AmplHler

Baud Rate

Generator

Loop

ICTSA
IDCDA
ModenVContrmLog~

ISYNCA

IRTSA
IDTRAl/REQA

Receive Log~
Rae. Status

Reo. Data

FIFO 3 Byte

RF03Byte

SOLC Frame Status AFO
10x 19

RecelveMUX

RxDA

CRC Checker.
Data Decode &
Sync Character
Detection

Channel A
Databus
CPU & OMA VL--...I
Bus
Interface IV--...,

Control
Interrupt
Control

{/lN~lEI
lEO

ChannelS
~-~

_ _--'

Figure 1.

306

L.===~

SCC BioCk Diagram

AD1

ADO

A03

A02

A05

A04

A07

ADS

lINT

IRO

lINT

lOS

lEO

IWR

lEO

lAS

lEI

Al/B

lEI

IINTACK

ICE

+5V

OIlC

+5V

IWIIREQA

GND

IWIIREQA

ISYNCA

IWIIREQB

IRTxCA
RxOA
ITRxCA

ISYNCA

IWIIREQB
ISYNCB

IRTxCB

RxOA

IRTxCB

ITRxCA

RxOB

TxOA

ITRxCB

10TRlIREQA

TxOB

IRTSA

CS1
GNO

ISYNCB

ITRxCB

10TRl/REQA

ICSO

IRTxCA

RxOB

TxOA

RlIW

IINTACK

10TRl/REQB

TxOB

IRTSA

10TRl/REQB
IRTSB

ICTSA

RTSB

ICTSA

10COA

ICTSB

10COA

ICTSB

PCLK

10COB

PCLK

IOCOB

Figure 2. Z85C30 DIP Pin Assignments

Figure 3. Z80C30 DIP Pin Assignments

lEO

AlIB

lEI

ICE

IINTACK

OIIC

+51/
IWIIREOA

NC
GNO

Z85C30

ISYNCA
IRTxCA

IWIIREOB
ISYNCB

RxDA

IRTxCB

IfRxCA

RxDB

TxOA

IfRxCB

TxOB

~C§ ~ ~«
w

t;S
IE -e

"'m
..... Q
00
Q.

RlIW
ICSO
CS1

lEO
lEI
nNTACK

+5V
fWllREQA
ISYNCA
IRTxCA

NC
GND
fWllREOB
/sYNCB

Z80C30

RxDA

IRTxCB

IfRxCA
TxDA

RxDB
IfRxCB
TxDB

ffl ffl B 0z
b~w
~

- -e

Figure 4. Z85C30 PLCC Pin Assignments

Figure 5. Z80C30 PLCC Pin Assignments
Note Power connections follow
conventional descriptions below:
Connection Circuit

Power

V",

Ground

GND

DeVice

V""
V§

307

Data Bus

Bus Timing
and Reset

Control

TxOA

RxOA

!TRxCA

IRTxCA

ISYNCA

IWIIREQA

10TRl/REQA

IRTSA
ICTSA

IRO
IWR

Z85C30

IDCDA

Al/B

TxOB

ICE

RxDB

Dl/C

!TRxCB

liNT

IRTxCB
ISYNCB

IINTACK

IWIIREQB

lEI

10TRl/REQB

lEO

IRTSB
ICTSB

}
}

Serial
Data
Channel
Clocks

CH-A

Controls
for Modem,
OMA and
Other

}
}

Serial
Data
,Channel
Clocks

}~-

CH-B

Controls
for Modem,
OMA and
Other

10COB

Figure 6_Z85C30 Pin Functions

Address/Data Bus

Bus TiRing
and Reset

Control

AD7

TxDA

AD6

RxDA

ADS

!TRxCA

AD4

IRTxCA

AD3

ISYNCA

A02

IWIIREOA

A01

IOTRl/REQA

ADO

IRTSA

lAS

ICTSA

IDS

IOCOA

Z80C30

RlIW

TxDB

CS1

RxOB

CSO

!TRxCB

liNT

IRTxCB

IINTACK
lEI
lEO

ISYNCB
IWIIREOB
IOTRl/REQB

IRTSB
ICTSB
IOCOB

Figure 7. Z80C30 Pin Functions

308

}
}

Serial
Data
Channel
Clocks

CH-A

Controls
for Modem,
OMAand
Other

}
}

Serial
Data
Channel
Clocks

}~~

Controls ,
for Modem,
OMA and
Other

'CH-B

PIN DESCRIPTION
The following section describes the pin functions common
to the Z85C30 and the Z80C30. Figures 2 and 3 detail the
respective pin functions and pin assignments.

RxDA, RxDB. Receive Data (inputs, active High). These
signals receive serial data at standard TTL levels.

ICTSA,ICTSB. Clear To Send(inputs, active Low). l!these
pins are programmed for Auto Enables, a Low on the
inputs enables the respective transmitters. If not programmed as Auto Enables, they may be used as generalpurpose inputs. Both inputs are Schmitt-trigger buffered to
accommodate slow rise-time inputs. The SCC defects
pulses on these inputs and can interrupt the CPU on both
logic level transitions.

IRTxCA,/RTxCB. Receive!Transmlt Clocks(inputs, active
Low). These pins can be programmed in several different
modes of operation. In each channel, /RTxC may supply
the receive clock, the transmit clock, the clock for the baud
rate generator, or the clock for the Digital Pilase-Locked
Loop. These pins can also be programmed for use with the
respective /SYNC pins as a crystal oscillator. The receive
clock may be 1, 16, 32, or 64 times the data rate in
Asynchronous modes.

IDCDA, IDCDB. Data Carrier Detect (inputs, active Low).
These pins function as receiver enables if they are programmed for Auto Enables; otherwise, they are used as
general-purpose input pins. Both pins are Schmitt-trigger
buffered to accommodate slow rise-time signals. The SCC
detects pulses on these pins and can interrupt the CPU on
both logic level transitions.

IRTSA, IRTSB. Request To Send (outputs, active Low).
When the Request To Send (RTS) bit in Write Register 5
(Figure 11) is set, the /RTS signal goes Low. When the RTS
bit is reset in the Asynchronous mode and Auto Enable is
on, the signal goes High after the transmitter is empty. In
Synchronous mode it strictly follows the state of the RTS bit.
Both pins can be used as general-purpose outputs.

IDTRl/REQA,/DTRl/REQB. Data Terminal Ready/Request
(outputs, active Low). These outputs follow the state programmed into tile DTR bit. They can also be used as
general-purpose outputs or as Request lines for a DMA
controller.

ISYNCA, ISYNCB. Synchronization (inputs or outputs,
active Low). These pins can act either as inputs, outputs,
or part of the crystal oscillator circuit. In the Asynchronous
Receive mode (crystal oscillator option not selected),
these pins are inputs similar to /CTS and /DCD In this
mode, transitions on these lines affect the state of the
Synchronous/Hunt status bits in Read Register 0
(Figure 10) but have no other function.

lEI. Interrupt Enable In (input, active High). lEI is used with
lEO to form an interrupt daisy-chain when there is more
than one interrupt driven device. A high lEI indicates that
no other higher priority device has an interrupt under
service or is requesting an interrupt.
lEO. Interrupt Enable Out (output, active High). lEO is High
only if lEI is High and the CPU is not servicing the SCC
interrupt or the SCC is not requesting an interrupt (Interrupt
Acknowledge cycle only). lEO is connected to the next
lower priority device's lEI input and thus inhibits interrupts
from lower priority devices.
liNT. Interrupt Request (output, open-drain, active Low).
This signal is activated when the SCC requests an interrupt.
IINTACK. Interrupt Acknowledge (input, active Low) This
. Signal indicates an active Interrupt Acknowledge cycle.
During ttlis cycle, the SCC interrupt daisy chain settles.
When /RD or /DS becomes active, the SCC places an
interrupt vector on the data bus (if lEI is High). /INT ACK is
latched by the rising edge of PCLK.

In External Synchronization mode with the crystal OSCillator
not selected, these lines also act as inputs. In this mode,
/SYNC must be driven Low for two receive clock cycles
after the last bit in the synchronous character is received.
Character assembly begins on the rising edge of the
receive clock immediately preceding the activation
of /SYNC.
.
In the Internal Synchronization mode (Monosync and
Bisync) with the crystal oscillator not setected, these pins
act as outputs and are active only during the part of the
receive clock cycle in which synchronous characters are
recognized. This synchronous condition is not latched, so
these outputs are active each time a synchronization
pattern is recognized (regardless of character boundaries) .
In SDLC mode, these pins act as outputs and are valid on
receipt of a flag.
TxDA, TxDB. Transmit Data (outputs, active High). These
output signals transmit serial data at standard TTL levels.

PCLK. Clock (input). This is the master SCC clock used to
synchronize internal signals. PCLK is a TTL level signal.
PCLK is not required to have any phase relationship with
the master system clock.

309

PIN DESCRlfJTION (Continued)
fTRxCA, /TRxCB. Transmit/Recei'lte Clocks (inputs or
outputs, active low). These pins-can be programmed in
several different modes of operation. TRxe may supply the
receive clock Qr the transmit clock in the input mode or
supply the output of the Digital Phase-Locked loop, the
crystal oscillator, the baud rate generator, or the transmit
clock in the output mode.
twliREOA,twIlREOB. Walt!Request(outputs, open-drain
when programmed for a Wait function, driven High or Low
when programmed for a Request function). These dualpurpose outputs may be programmed as Request linos for
a DMA controller or as Wait lines to synchronize the epu
to the see data rate. The reset state is Wait.

cycle, this signal.gates the interrupt vector onto the bus
ii the see is the highest priority device. requesting an
interrupt.

twA. Write (input, active Low). When the see is selected, .
this signal indicates a write operation. The coincidence of
IRD and twR is interpreted as a reset.

Z80cao
AD7-ADO. Address/Data Bus (bidirectional, active High,
3-state) These multiplexed lines carry register addresses
to the see as well as data or control information.
lAS. Address Strobe (input, active Low). Addresses on
AD7-ADO are latched by the rising edge of this signal.

Z85C30
NIB. Channel AlChannel B (input) This signal selects the
channel in which the read or write operation occurs.
'ICE. Chip Enable (input, active Low). This signal selects
the see for a read or write operation.

1050. Chip Select 0 (Input, active Low). This signal is
latched concurrently with the. addresses on AD7-ADO and
must be active for the intended bus transaction to occur.

07-00. Data Bus (bidirectional, 3-state) These lines carry
data and command to and from the see.

1051. Chip Select 1 (input, active High). This second select signal must also be active before the intended bus
transaction can occur. eS1 must remain active throughout
the transaction.

OIlC. Data/Control Select (input). This signal defines the
type of information transferred to or from the see. A High
means qata is transferred; a low indicates a command.

IDS. Data strobe (input, active Low) This signal provides
tlming.forthe transfer of data into and out of the see. If lAS
and IDS coincide, tl:lis is interpreted as a reset.
'

IRO. Read(input, active Low). This signal indicates a read
operation and when the see is selected, enables the
See's bus drivers. During the Interrupt Acknowledge

Rltw. Read/Write(input). 'fhis signal specilies whether the
operation to be performed is a read or a write.

FUNCTIONAL DESCRIPTION·
The architecture of the see is·described from two points
of view: as a datacommunications device which transmits
and receives data in a wide variety of protocols; as a
microprocessor peripheral in which the see offers valu- .
able features such as vectored interrupts and DMA
support.

310

The see's peripheral and datacommunication are described in the following sections. A block diagram is shown
in Figure 1. The details of the communications between the
receive and transmit logic to the system bus is shown in
Figures 8 and 9. The features and data path for each of the
see's A and B channels is identical. See the see Technical Manual for full details on using the see.

Internal Data Bus
To other Channel

TXFIFO
1 Byte
TXD

Transmit

1----...::::='-"1 MUX & 2-Bit I--i~-I'"

r---~L-__D~el~aY~-l

~~----~

'---------+
Transmit Clock

From Receiver

Figure 8.

see Transmit Data Path
CPUVO

I~~-I

In!ernal Data Bus

BRG

BRG
Output

Input

Hunt Mode (BISYNC)
,- - - - - - - ---I

DPLJ.
IN

RXD

'-_ _ _ _ _ _ _ _---<~

To Transmit Section

Figure 9.

See Receive Data Path

311

FUNCTIONAL DESCRIPTION (Continued)
1/0 Interface Capabilities

There are three choices to move data into and out of the
. SCC: Polling"interrupt (vectored and non-vectored), and
Block Transfer. 'The Block Transfer mode can be impleSystem communication to and from the SCC is done
mented under CPU or OMA control.
through the SCC's register set. There are sixteen write
registers and eight read registers. Table 1 lists all, of the
SCC's registers and a brief description of their lunctions.
Polling
Throughout this document, the write and read registers are
When polling, all interrupts are.disabled. Three status
registers in the SCC are automatically updated whenever
referenced with the following notation' "WR" for Write
. any function is performed For example, End-Ol-Frame in
Register and "RR" for Read Register. For example:
SOLe mode sets a bit in one of these s,tatus registers. The
purpose of polling is lor the CPU to periodically read a
WR4A
Write Register 4 for channel A
status register until the register contents indicare the need
RR3
Read Register 3 loreitherlboth channels
for data to be transferred. Only one register needs to be
read; depending on its contents, the CPU either writes
Table 1. see Read and Write Registers
data, reads data, or continues. Two bits in the register
Read Register Functions
indicate the need for data transler. An alternative is a poll
of
the Interrupt Pending register to determine the source of
RRO
TransmiVReceive buffer status and External status
an interrupt. The status for both channels resides in one
RRl
Special Receive Condition status
register.
, RR2
Modified interrupt vector (Channel B only)
Unmodified interrupt vector (Channel Aonly)
Interrupts
The SCC's interrupt structure supports vectored and nested
Interrupllilndlng bits (Channel Aonly)
RR3
interrupts. Nested interrupts are supported with the interRRB
Receive Buffer
rupt acknowledge feature (lINTACK pin) of the SCC. This
RRlO
Miscellaneous status
allows the CPU to recognize the'occurrence of an interrupt,
RR12
lower byte 01 baud f\lte generator time constant
and re-enable higher priority interrupts. Because an INTACK
RR13
Upper byte 01 baud rate generator lime constant
cycle will release the liNT pin from the active state, a higher
RR15, External/Status interrupt information
priority SCC interrupt or anotherlligher priority device can
interrupt the CPU. When an SCC responds to an Interrupt
Acknowledge signal (INTACK) from the CPU, an interrupt
vector can be placed on the data bus. This vector is written
.Write Register Functions
in WR2 and may be read in·RR2. To speed interrupt
response time, the SCC can modify three bits in this vector
WRO
CRC initialize, initialization commands for the various modes,
to indicate status. If the vector is re?d in Channel A, status
Register'Pointers.
is never included; if it is read in Channel B, status is always
WRl
TransmiVReceive interrupt and data transfer mode definition
included.
.
WR2
Interrupt vector (accessed through either channel) ,
Receive parameters and control '
WR3
Each of the six sources of interrupts in the SCC (Transmit,
WR4
TransmiVReceive miscellaneous parameters and modes
Receive, and Extemal/St~tus interrupts in both channels)
has three bits associated with the interrupt source: InterWR5
Transmit parameters and controls
rupt Pending (IP), Interrupt Under Service (IUS), and
WR6
Sync characters or SOlC address field
Interrupt Enable (IE). Operation of the IE bit is straightforWR7
Sync character or SOle flag
ward. lithe IE bitis settor a given interrupt source, then that
source can request interrupts. The 'exception is when the
WRB
Transmit buffer
MIE (Master Interrupt Enable) bit in WR9 is reset and no
WR9
Master interrupt control and reset (accessed through
interrupts can be requested. The IE bits are write only.
either channel)
WRl0
WR11
WR12

Miscellaneous transmitter/receiver control bits
Clock mode control
lower byte of baud rate generator time ~onstant

WR13
WR14
WR15

Upper byte of baud rate generator time constant
Miscellaneous control bits
External/Status interrupt control

312

The other two bits are related to the interrupt priority chain
(Figure 10). As a microprocessor peripheral. the SCC may
request an interrupt only when no higher priority device is
requesting one, e.g., when lEI is High. If the device in
question requests an interrupt, it pulls down II NT. The CPU
then responds with liNTACK, and the interrupting device
places the vector on the data bus.

Peripheral

Peripheral
nNT nNTACK
+5V

07-00
liNT

C:===--'=~=~====~=~=::::====:J

+------+---1---------+---1---------4---1---1

IINTACK

Figure 10.

see Interrupt Priority Schedule

The SCC can also execute an interrupt acknowledge cycle
through software. In some CPU environments it is difficult
to create the /INTACK signal with the necessary timing to
acknowledge interrupts and allow the nesting of interrupts.
In these cases, the /INT ACK signal can be created with a
software command to the SCC.
In the SCC, the Interrupt Pending (IP) bit signals a need for
interrupt servicing. When an IP bit is 1 and the lEI input is
High, ttle /INT output is pulled Low, requesting an interrupt
In the SCC, if the IE bit isn't set by enabling interrupts, then
the IP for that source is never set. The IP bits are readable
in RR3A.
The IUS bits signal that an interrupt request is being
serviced. If an IUS is set, all interrupt sources of lower
priority in the SCC and external to the SCC are prevented
from requesting interrupts The internal interrupt sources
are inhibited by the state of the internal daisy chain, while
lower priority devices are inhibited by the lEO output of the
SCC being pulled Low and propagated to subsequent
peripherals. An IUS bit is set during an Interrupt Acknowledge cycle if there are no higher priority devices requesting
interrupts.
There are three types of interrupts: Transmit, Receive, and
External/Status. Each interrupt type is enabled under
program control with Channel A having higher priority than
Channel B, and with Receiver, Transmit, and External/
Status interrupts prioritized in that order within each channel.

Interrupt on First Character or Special Condition and
Interrupt on Special Condition Only are typically used with
the Block Transfer mode. A special Receive Condition is
one of the following: receiver overrun, framing error in
Asynchronous mode, end-of-frame in SOLC mode and,
optionally, a parity error. The Special Receive Condition
interrupt is different from an ordinary receive character
available interrupt only by the status placed in the vector
during the Interrupt Acknowledge cycle. In Interrupt on
First Receive Character, an interrupt occurs from Special
Receive Conditions any time after the first receive character
interrupt.
The main function of the External/Status interrupt is to
monitor the signal tranSitIons of tile /CTS, /OCO, and
/SYNC pins,. however, an External/Status interrupt is also
caused by a Transmit Underrun condition; a zero count in
the baud rate generator; by the detection of a Break
(Asynchronous mode), Abort (SOLC mode) or EOP (SOLC
Loop mode) sequence in the data stream. The interrupt
caused by the Abort or EOP has a special feature allowing
the SCC to interrupt when the Abort or EOP sequence is
detected or terminated. This feature facilitates the proper
termination of the current message, correct initialization of
the next message, and the accurate timing of the Abort
condition in external logic in SDLC mode. In SOLC Loop
mode, this feature allows secondary stations to recognize
the primary station wishes to regain control of the loop
during a poll sequence.

Software Interrupt Acknowledge
When enabled, the receiver can interruplthe CPU in one
of three ways:
1. Interrupt on First Receive Character or SpeCial
Receive Condition.
2. Interrupt on All Receive Characters or Special
Receive Conditions.

The SCC interrupt acknowledge cycle can be initiated
through software. If Write Register 9 (WR9) bit 05 is set,
Read Register 2 (RR2) results in an interrupt acknowledge
cycle to be executed internally. Like a hardware INT ACK
cycle, a software acknowledge causes the INT pin to
return high, ttle lEO pin to go low and set the IUS latch for
the highest priority interrupt pending.

3. Interrupt on Special Receive Conditions Only.

313

FUNCTIONAL DESCRIPTION (Continued)
Request bits in WR 1. The /WAIT//REQU~ST output can be
defined under software control as a WAIT line In the CPU
Block Transfer mode or as a REQUEST line in the OMA
Block Transfer mode.

Similar to when the hardware INTACK signal can be used,
a software acknowledge cycle requires that a Reset f Jighest IUS command be issued in the interruptservice,routine,
Whenever an interrupt acknowledge cycle is used, hardware or software, a reset highest IUS command is required. If RR2 is read from channel A, the unmodified
vector is retumed. If RR2 is read from channel B, then the
vector is modified to indicate the source of the interrupt.
The Vector Includ~s Status (VIS) and No Vector (NV) bits
in WR9 are ignored when bit 05 is set to 1.

To a OMA controller, the SCC REQUEST output indicates
that the SCC is ready to transfer data to or from memory.
To the CPU, the WAIT line indicates tllat the ESCC is not
ready to transfer data, thereby requesting that the CPU
extend the I/O cycle. The /DTR//REQUEST line allows fullduplex operation under OMA control.

When the INTACK and lEI pins are not being used, they
should be pulled up to Vee through a resistor (10 kohm
typical).

sec Data Communications Capabilities
see

The
provides two independent full-duplex programmable channels for use In any common asynchronous or ;
synchronous data communication protocols (Figure 11).
Each of the datacommunication channels has Identical
features and capabilities.

CPUlOMA Block Transfer. The SCC provides a Block
Transfer mode to accommodate CPU block transfer lunctions and OMA Controllers The Block Transfer mode used
the /WAIT/IREQUEST output in conjunction with the Wait!
Parity

Slart

Marking Una

Data

Slop

II II
i

Data

II II

Data

Marking Una

Asynchronous

SYNC

Data

CRCl

CRC2

Data

CRCl

CRC2

Data

CRCl

CRC2

CRCl

CRC2

Monosync
SYNC

SYNC

Data

Signall

Bisync
Data

External Sync
Rag

I·

Address

Inlonnation

Inlonnalion

SOLC/HDLC/X.25
Figure 11. Some SCC Protocols

314

Flag

Asynchronous Modes
Send and Receive is accomplished independently on
each channel with five to eight bits per character, plus
optional even or odd parity. The transmitters can supply
one, one-and-a-half, or two stop bits per character and can
provide a break output at any time. The receiver breakdetection logic interrupts the CPU both at the start and at
the end of a received break. Reception is protected from
spikes by a transient spike-rejection mechanism that checks
the signal one-half a bit time after a Low level is detected
on the receive data input (RxDA or RxDB pins). If the Low
does not persist (e.g., a transient), the character assembly
process does not start.

The SCC does not require symmetric transmit and receive
clock signals - a feature allowing use of the wide variety of
clock sources. The transmitter and receiver handle data at
a rate supplied to the receive and transmit clock inputs. In
Asynchronous modes, the SYNC pin may be programmed
as an input used for functions such as monitoring a ring
indicator.
Synchronous Modes
The SCC supports both byte-oriented and bit-oriented
synchronous communication. Synchronous byte-oriented
protocols are handled in several modes. They allow character synchronization with a 6-bit or 8-bit sync character
(Monosync), and a 12-bit or 16-bit synchronization pattern
(Bisync), or with an external sync signal. Leading sync
characters are removed without interrupting the CPU.

Framing errors and overrun errors are detected and buffered together with the partial character on which they
occur. Vectored interrupts allow fast servicing or error
conditions using dedicated routines. Furthermore, a builtin checking process avoids the interpretation of a framing
error as a new start bit: a framing error results in the
addition of one-half a bit time to the point at which the
search for the next start bit begins.

Five or 7-bit synchronous characters are detected with
8- or 16-bit patterns in the SCC by overlapping the larger
pattern across multiple incoming synchronous characters
as shown in Figure 12.

7Bils

SYNC

I. I

SYNC

Oala

Data

I
8

Figure 12. Detecting 5- or 7-Bit Synchronous Characters

CRC checking for Synchronous byte oriented modes is
delayed by one character time so that the CPU may
disable CRC checking on specific characters. ThiS permits the implementation of protocols such as IBM Bisync.
Both CRC-16 (X16 + X15 + X2 + 1) and CCITT (X16 + X12
+ X5 + 1) error checking polynomials are supported. Fither
polynomial may be selected in all Synchronous modes.
Users may preset the CRC generator and checker to all 1's·
or all O's. The SCC also prov)des a feature that automatically transmits CRC data when no other data is available
for transmission. This allows for high speed transmissions
under DMA control, witt), no need for CPU intervention at
the end of a message. When there is no data or enc to
send in Synchronous modes, the transmitter inserts 6-,8-,
or 16-bit'sync characters, regardless of the programmed
character length.

SOLe Mode
The SCC supports Synchronous bit-oriented protocols,
such as SDLC and HDLC, by performing automatic flag
sending, zero insertion, and CRC generation. A special
command is used to abort a frame in transmission. At the
end of a message, the SCC automatically transmits the
CRC and trailing flag when the transmitter underruns. The
transmitter may also be programmed to send an idle line
consisting of continuous flag characters or a steady marking
condition.
If a transmit underrun occurs in the middle of a message,
an external/status interrupt warns the CPU of this status
change so that an abort can be issued. The SCC may also
be programmed to send an abort itself in case of an
underrun, relieving the CPU of this task. One to eight bits
per character can be sent, allowing reception of a message with no prior information about the character structure in the information field of a frame.

315

'~'h,"

FUNCTIONAL DESCRIPTION (Continued)
The receiver automatically acquires synchronization on
the leading flag of a frame in SOLC or HOLC and provides
a synchronization signal on the /SYNC pin (an interrupt can
also be programmed). The receiver can be programmed
to search for frames addressed by a single byte (or four
bits within a byte) of a user-selected address or to a global
broadcast adClress. In this mode, frames not matching
either the user-selected or broadcast address are ignored.
The number of address bytes are extended under software
coritrol. For receiving data, an interrupt on the first received
character, or an interrupt on every character, or on special
condition only (end-of-frame) can be selected. The receiver
automatically deletes all O's Inserted by the transmitter
during character assembly. CRC is also calculated and is
automatically checked to validate frame transmission. At
the end of transmission, the status of a received frame is
available in the status registers. In SOLC mode, the SCC
must be progra(l1med to use the SOLC CRC polynomial,
but the generator and checker may be preset to all 1's or
aILO's. The CRC is inverted before transmission and the
receiver checks againstthe bit pattern 000111 01 00001111.
NRZ, NRZI or FM coding may be used in any 1x mode. The
parity options available in Asynchronous modes are available in Synchronous modes.
SOLe Loop Mode. The SCC supports SOLC Loop mode in
addition to normal SOLC. In an SOLC Loop, there is a
primary controller station that manages the message
traffic flow on the loop and any number of secondary
stations. In SOLC Loop mode, the SCC performs the
functions of a secondary station while an SCC operating in
regular SOLC mode acts as a controller (Figure 13). SOLC
loop mode can be selected by setting WR10 bit 01.

A secondary station in an SOLC Loop is always listening to
the messages being sent around the loop and, in fact,
passes these messages to the rest of the loop by
retransmitting them with a one-bit-time delay. The secondary station places its own message on the loop only at
specific times. The controller signals that secondary stations can transmit messages by sending a special character, called an EOP (End Of Poll), around the loop The EOP
character is the bit pattern 11111110. Because of zero
insertion durillg messages, this bit pattern IS unique and
easily recognized.
When a secondary station has a message to transmit and
recognizes an EOP on the line, it changes the last binary
1 of the EOP to a 0 before transmiSsion. This has the effect
of turning the EOP into a flag sequence. The secondary
station now places its message on the loop and terminates
the message with an EOP. Any secondary stations further
down the loop with messages to transmit appends their
messages to the message of the first secondary station by
the same process. Any secondary stations without messages to send merely echo the incoming message and are
prqhibited from placing messages on tile loop (except
upon recognizing an EOP). In SOLC Loop mode, NRZ,
NRZI, and FM coding may all be used.
The SCC's ability to receive high speed back-ta-back
SOLC frames is maximized by a 10- deep by
19-bil wide status FIFO. When enabled (through WR 15, bit
02), it provides the OMA the ability to continue to transfer
data into memory so that the CPU can examine the message later. For each SOLC frame, a 14-bit byte count and
5 status/error bits are stored. The byte count and status
bits are accessed through Read Registers 6 and 7. Read
Registers 6 and 7 are only acceSSible when the SOLC FIFO
is enabled. The 10x19 status FIFO is separate from the
3-byte receive data FIFO.
Baud Rate Generator
Each channel in the SCC contains a programmable baud
rate generator. Each generator consists of two 8-bit time
constant registers that form a 16-bit time constant, a 16-bit
down counter, and a flip-flop on the output producing a
square wave. On startup, the flip-flop on the output is set
in a High state, the value iri the time consrant register is
loaded into the counter, and the counter starts counting
down. The output of the baud rate generator toggies upon
reaching 0, the value in the time constant register is loaded
into the counter, and the process is repeated. The time
constant may be changed at any time, but tile new value
does not take effect until the next load of the counter.

J Figure

316

13. An SOLe Loop

The output of the baud rate generator may be used as
either the transmit clock, the receive clock, or both. It can
also drive the Digital Phase-Locked Loop (see next
section).
If the receive clock or transmit clock is not programmed to
come from the TRxC pin, the output of the baud rate
generator may be echoed out via the TRxC pin.
The following formula relates the time constant to the baud
rate where PCLK or RTxC is the baud rate generator input
frequency in Hertz. The clock mode is 1, 16, 32, or 64, as
selected in Write Register 4, bits D6 andD7. Synchronous
operation modes should select 1 and Asynchronous should
select 16, 32 or 64.
Time Constant

PCLK or RTxC Frequen~y

-2

2(Baud Rate)(Clock Rate)
Digital Phase-Locked Loop
The SCC contains a Digital Phase-Locked Loop (DPl L) to
recover clock information from a data stream with NRZI or
FM encoding. The DPLL is driven by a clock that is
nominally 32 (NRZI) or 16 (FM) times the data rate The
DPLL uses this clock, along with the data stream, to
construct a clock for the data. This clock is then used as the
SCC receive clock, the transmit clock, or both. When the
DPLL is selected as the transmit clock source, it will
provide a jitter free clock output that is the DPLL input
frequency divided by the appropriate divisor for the selected encoding technique.
For NRZI encoding, the DPLL counts the 32x clock to
create nominal bit times. As the 32x clock is counted, the
DPLL is searching the incoming data stream for edges
(either 1 toO, orO to 1). Whenever an edge is detected, the
DPLL makes a count adjustment (during the next counting
Data

cycle), producing a terminal count closer to the cenler of
the bit cell.
For FM encoding, the DPLL still counts from 0 to 31, but
with a cycle corresponding to two bit times. When the DPLL
is locked, the clock edges in the data stream should occur
between counts 15 and 16 and between counts 31 and 0
The DPLL looks for edges only during a time centered on
the 15 to 16 counting transition.
The 32x clock for the DPLL can be programmed to come
from e.ither the RTxC input or the output of the baud rate
generator. The DPLL output may be programmed to be
echoed out of the SCC via the TRxC pin (if IIlis pin is not
being used as an input).
Data Encoding
The SCC may be programmed to encode and decode the
serial data in four different ways (Figure 14). In NRZ encoding, a 1 is represented by a High level and a 0 is
represented by a Low level. In NRZI encoding, a 1 is
represented by no change in level and a 0 is represented
by a change in level. In FM1 (more properly, bi-phase
mark), a transition occurs at the beginning of every bit cell
A 1 is represented by an additional transition at the center
of the bit cell and a 0 is represented by no additional
transition at the center of the bit cell. In FMO (bi-phase
space), a transition occurs at the beginning of every bit
cell. A 0 is represented by an additional transition at the
center of the bit cell, and a 1 is represented by no
additional transition at the center of the bit cell. In addition
to these four methods, the SCC can be used to decode
Manchester (bi-ptJase level) data by uSing the DPLL in the
FM mode and programming the receiver for NRZ data.
Manchester encoding always produces a transition at the
center of the bit cell: If the transition is 0 to 1, the bit is a O.
If the transition is 1 to 0, the bit is a 1.

NAZ

NAZI

\
\

FM1

FMO

Manchester

Figure 14. Data Encoding Methods

317

FUNCTIONAL DESCRIPTION (Continued)
Auto Echo and Local Loopback
The SCC is capable of automatically echoing everything it
receives. This feature is useful mainly in Asynchronous
modes, but· works in Synchronous and SOLC modes as
well. Auto Echo mode (T xO is RxO) is used with NRZI or FM
encoding with' no additional delay because the data stream
is not decoded before retransmission. In Auto Echo mode,
the ICTS input is ignored as a transmitter enable (although
transitions on this input can still'cause interrupts if programmed to do so). In this mode, the transmitter is actually
bypassed and the programmer is responsible for disabling transmitter interrupts and /WAIT/JREQUEST on
transmit.

checker is automatically reset in preparation for the next
frame which can begin immediately. Since the byte count
and status are saved for each frame, the message integrity
is venfied at a later time. Status inlormation for up to 10
frames is stored before a status FlrO overrun can occur.
If a frame is terminated with an ABORT, the byte count is
loaded to the status FIFO and the counter reset for the next
frame.
FIFO Detall
For a better understanding of details of the FIFO operation,
refer to the block diagram in Figure 15.

The SCC is also capable of localloopback. In this mode;
Enable/Disable
TxO or RxO is just like Auto Echo mode. However, in Local
This FIFO is implemented so that ifis enabled when WR15,
Loopback mode the internal transmit data is lied to' the , bit 02, is set and the SCC is in the SOLC/HOLC mode.
internal receive data and RxO is ignored (except to be
Otherwise, the status register contents bypass the FIFO
and go directly to the bus interface (the FIFO pointer logic
echoed out via TxO). The ICTS and lOCO inputs are also
ignored as transmit and receive enables. However, transiis reset either when disabled or via a channel or power-on
reset). When the FIFO mode is disabled, the SCC is
tions on these inputs can still cause interrupts. Local
Loopback works in Asynchronous, Synchronous and SOLC
completely downward compatible with the NMOS Z8530.
modes with NRZ, NRZI or FM coding of the data stream.
rhe FIFO mode is disabled on power-up (WR15 02 is set
to 0 on reset). The effects of backward compatibility on the
SOLe FIFO Frame Status FIFO Enhancement
register set are that RR4 is an image of RRO, RR5 is an
The SCC's ability to receive high speed back-ta-back
image of RR 1, RR6is an image of RR2 and RR7 is an image
of RR3. For the details of the added registers, refer to
SOLC frames is maximized by a 10- deep by
19-bit wide status FIFO. When enabled (through WR 15, bit
Figure 18. The status of the FIFO Enable signal is obtained
by reading RR15, bit 02. lithe FIFO is enabled, the bit will
02), it provides the OMA the ability to continue to transfer
be set to 1; otherwise, it will be reset.
data into memory so that the CPU can examine the message later. For each SOLC frame, a 14-bit byte count and
5 statuslerror bits are stored. The byte count and status
Read Operation
bits are accessed through Read Registers 6 and 7; I{ead
When WR 15 bitD2 is set and the FIFO is not empty, the next
read to status register RR 1 or the additional registers RR7
Registers 6 and 7 are only accessible when the SOLC FIFO
is enabled. The 10x19 status FIFO is separate from the
and RR6, are from the FIFO. Reading status register RR1
3-byte receive data FIFO.
causes one location of the FIFO to be emptied, so status
is read after reading the byte count, otherwise the count is
When the enhancement is enabled, the status in read
incorrect. Before the FIFO underflows, it is disabled. In this
register 1 (RR 1) and byte count for the SOLC frame are
case, the multiplexer is switched to allow status to read
stored in the 10 x 19 bit status FIFO. This allows' the DMA
directly from the status register and reads from RR7 and
controller to transfer the next frame into memory while the
RR6 contain bits that are undefined. Bit 06 of RR7 (FIFO
Oata Available) is used to determine if status data is
CPU verifies that the message was properlyreceived.
coming from the FIFO or directly from the status register,
since it is set to 1 whenever the FIFO is not empty.
Summarizing the operation; data is received, assembled,
and loaded into the eight byte FIFO before being transferred to memory by the OMA controller. When a IIag is
Since not all status bits are stored in the FIFO, the All Sent,
received at the end of an SOLC frame, the frame byte count
Parity, and EOF bits bypass the FIFO. The status bits sent
through the FIFO are Residue Bits (3), Overrun, and
from the 14-bit counter and five status bits are loaded into
CRC'Error.
the status FIFO for verification by the CPU. The CRC

318

Frame Status FIFO Circuitry

RRl

~ Reset on Flag Detect

SCC Status Reg
Residue Bits(3)
Overrun; CRC Error

Byte Counter

~ Increment on Byte Detection

~ Enable Count in SOLC

I
5 Bits

10-

End 01 Frame Signal
Status Read Comp

14 Bits

FIFO Array
10 Deep by 19 Bits Wide

Tail Pointer
4-Bit Counter

+--

Head Pointer
4-Bit Counter

r---

4-Bit Comparator

5 Bits

Jnteriace
toSCC

•

2 Bits

Over

S-Bit MUX

EOF = 1

10- SBits

10- SBIIs

...---.

/£

.. SBits
RRl

Equal

'EN

L-..

Bil7 Bi:S

Bi,+5-0

RR7 OS-DO + RRS 07 - DO
Byte Counter Contains 14 bits
lor a lS KByte maximum count.

Rffi11.

WR(15) Bit 2
Set Enables
Status FIFO

RR7DS
FIFO Data available status bit Status Bit set to 1
When reading from FIFO.
RR7D7
FIFO Overflow Status Bit
MSB pi RR(7) is set on Status FIFO overflow

...

In SOLC Mode the follOWing definitions apply.
- All Sent bypasses MUX and equals contents of sec Status Register.
- Parity Bits bypasses MUX and does the same.
- EOF is set to 1 whenever reading from the FIFO.

Figure 15. SOLe Frame Status FIFO

319

FUNCTIONAL DESCRIPTION (Continued)
1 he sequence for proper operation of the byte count and
FIFO logic is to read the registers in the following order:
RR?, RR6, and RR1 (reading RR6 is optional). Addilional
logic prevents the FIFO from being emptied by multiple
reads from RR 1. The read from RR? latches the FIFO
empty/full status bit (06) and steers the status multiplexer
to read from the see megacell instead of the status FIFO
(since thestatlJs FIFO is empty). The read from RR1 allows
an entry to be read from the FIFO (if the FIFO was empty,
logic was added,to prevent a FIFO underflow condition).

Internal Byte Strobe
Increments Counter

Intemal Byte Strobe
Increments Counter
Oon't Load
Counter On
1st Flag
Reset Byte
Counter Here

Write Operation .
When the end of an SOLe frame (EOF) has been received
and the FIFO is enabled, the contents of ttle status and
byte-count registers are loaded into the FIFO. Tile EOF
signal is used to increment the FIFO. If the FIFO overflows,
the RR? bit 07 (FIFO Overflow) is set to indicate the
overflow. This bit and the FIFO control logic is reset by
disabling and re-enabling the FIFO control bit (WR15 bit
02). For details of FIFO control timing during an SOLe
frame, refer to Figure 16.

Reset
Byte Counter
Load Counter
Into FIFO and
Increment PTR

Reset
Byte Counter

Reset

Byte Counter
Load Counter
Into FIFO And
Increment PTR

Figure 16. SDLC Byte Counting Detail

PROGRAMMING
The see contains write registers in each channel that are
programmed by the system separately to configure ttle
functional personality of the channels.

Z85C30
In the see, the data registers are directly addressed by
selecting a High on the D//e pin. With all other registers
(except WRO and RRO), programming the write registers
requires two write operations and reading the read registers
requires both a write and a read operation. The first write
is to WRO and contains three bits that point to the selected
register. The second write is the actual control word for the
selected register, and if the second operation is read, the
selected read register is accessed. AU of the see registers, including the data registers, may be accessed in this
fashion. The painter bits are automatically cleared aftar the
read or write operation so that WRO (or RRO) is addressed
again.

Z80C30
All see registers are directly addressable. How the see
decodes the address placed on the address/data bus at
the beginning of a Read or Write cycle is controlled by a
command issued in WROB. In the Shift flight mode the

320

cllannel select AlB is taken from ADO and tile state of AD5
is ignored. In the Shift Left mode the cllannel select AlB is
taken from AD5 and the state of ADO is ignored AD? and
AD6 are always ignored as address bits and the register
address itself occupies AD4-AD1.
Z85C30/Z80C30 Setup
Initialization. The system program first issues a series of
commands to initialize the basic mode of operation. This is
followed by other commands to qualify conditions within
the selected mode. For example, in the Asynchronous
mode, character length, clock rate, number of stop bits,
and even or odd parity should be set first. Then the
interrupt mode is set. and finally, the receiver and transmitter are enabled.

Write Registers. The see contains 15 write registers
(16 counting the transmit. buffer) in each channel. Tilese
write registers are programmed separately to configure
the functional "personality" of the channels. There are two
registers (WR2 and WR9) shared by the two channels that
are accessed through either of them. WR2 contains the
interrupt vector for both channels, while WR9 contains the
interrupt control bits and reset commands. Figure 1?
shows the format of each write register.

Write Register 0 (non-muftlplexed bus mode)

Write Register 3

1~loolool~lool~lmlool

I I I
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

o
o
1
1

0
1
0
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

AX Enable

=~:::;~

Sync Character Load Inhlb~
Add_ search Mode (SOLC)
RxCACEnable
Enter Hunt Modo

}

Auto Enables

•

o
o

1
1

0
1

Rx
Rx
AX
AX

5 Bits/Character
7 BalCharactor
6 Bits/Character
8 BltslCharacter

Write Register 4

0
0
0 Null Code
0
0
1 PolnlHlgh
0
1
0 Resel ExI/SIaIus Internlp'"
0
1
1 send Abort (SOLC)
1
0
0 'Enable Int on Next Rx Character
1
0
1 Resel Tx Inl Pendlng
1
1
0 Error Reset
1
1
1 Reset Highest IUS
NuliCode
Reset Rx CRC Checker
Reset Tx CRe Generator
Reset Tx UndernlnlEOM Latch

Parity Enable
Parity EVEN/IODD

o
o

0
1

0 1 112 Slop BltslCharacter
1 2 Slop BitslCharacter

Sync Modes Enable
1 Slop Bit/Character

• With Point High Command

1
0

~
0
0
1
1

0
1
0
1

Ext Int Enable
Tx Int Enable

o
o
1
1

8-8it ~ync Character
16-B~ Sync Character
SOLC Modo (01111110 Flag)
Extomal Sync Modo

~ ~16C~~

o
1

X32 Clock Modo
X64CIoc:kModo

ParIty Is SpecIal Cond~lon

AX Int Disable
Rx Int On First Ch aracter or Special Condition
Int On All Rx Characters or Special Condition
AX Int On Special Condltlon Only

Write Regisler5

WAITIDMA Request On

Tx CAC Enable

Recelvelrrransm~

RTS

IWArTlDMA Request FUnction

ISDLCICRC-16

WAITIDMA Request Enable

Tx Enable
sendB",ak

Write Register 2

o
o
1
1

0 Tx 5 BiIs(Or less)ICharacter
1
0
1

Tx 7 BitslCharacter
Tx 6 BitslCharacler
Tx 8 BitslCharacbor

DTR

Internlpt
Vector

V5
V6

Figure 17. Write Register Bit Functions

321
--~~---------------

.............. '_.

PROGRAMMING (Continued)
Write Register 6

Sync7
Sync1
Sync7
Sync3
ADR7
ADR7

Sync6
SyncO
Sync6
Sync2
ADR6
ADR6

SyncS
SyncS
SyncS
Sync1
ADRS
ADRS

Sync4
Sync4
Sync4
SyncO
ADR4
ADR4

Sync3
Sync3
Sync3
1
ADR3

Sync2
Sync2
Sync2
1
ADR2

Sync1
Sync1
Sync1
1
ADR1

SyncO
SynoO
SyncO
1
ADRO

Monosync, 8 Bits
Monosync, 6 Bits
Bisync, 16 Bits
Bisync, 12 Bits
SDlC
SDlC (Address Range)

Write Register 7

Syno7 SyncS SyncS
SyncS Sync4 Sync3
Sync1S Sync14 Sync13
Sync11 Sync10 Sync9

Sync4
Sync2
Sync12
SyncS

Syn03 Sync2 Sync1
Sync1
SyncO
x
Sync11 Sync10 Sync9
Sync7 SyncS SyncS

SyncO
x
SyncS
Sync4

Monosync, 8 Bits
Monosync, 6 Bits
Bisync, 16 Bits
Bis~ync, 12 Bits
SDlC

Write Register 9

Software INTACK Enable

1
0
1

1
1

No Reset
Channel Reset B
Channel Reset A
Foroe Hardware Reset

Figure 17. Write Register Bit Functions (Conlinlled)

322

Wr~e Register 10

o
o
1
1

Write Register 13

6-Bitl/8-Btt Sync

TC8

Loop Mode

TC9

AbortllFlag On Under",n

TC10

MarkllFlag Idle

TC11

Go Active On Poll

TC12

Upper Byte of
Time Constant

TC13
0
1
0
1

NAZ'
NAZI
FMl (Transttion = 1)
FMO (Transttion = 0)

TC14
TC15
CRC Preset 1110
Write Register 14

Write Register 11
SR Generator Enable

I I
0
0
1
1

0
1
0
1

SR Generator Source

rrRxCO/1
0
0
1
1
0

0
1
1

0
1
0
1

IOTR/Request Function

fTRx C Out = Xtal Output
fTRxC Out = Transmit Clock
fTRx C Out = BR Genemtor Output
fTRx C Out =DPLL Output

Transmit Clock =IR TxC Pin
Transmit Clock =rrRxC Pin
Transmit Clock == BR Generator Output
Transmit Clock =D PLLOutput

Receive Clock = IRTxC Pin
Receive Clock =rrRxC Pin
Receive Clock = BR Genemtor Output
Receive Clock =DPLL Output

Auto Echo
Local Loopback

1
1
0
0

0
1
1
1
1

1
0
1

0
1

Null cOmmand
Enter Search Mode
Reset Missing Cloek
Disable DPLL
Set Source ... SR Generator
Set Source ... IRTxC
SetFM Mode
Set NAZI Mode

Wrne Raglster 15

IRTxC XtailiNo Xtal

~
~
~

Write Register 12

TCO

:erocountlE
SDLC FIFO Enable
DCDIE

TCI

SynclHunt IE

TC2

CTSIE

TC3

lower Byte of

Tx UnderrunlEOM IE

TC4

Time Constant

Break/Abort IE

TC5

TC6
TC7

Figure 17. Write Register Bit Functions (Continued)

323

PROGRAMMING (Contin'ued)
Read Registers. The SCC contains ten read registers
(eleven, counting the receive buffer (RR8) in each chanmil). Four of these may be read to obtain status information
(RRO, RR1, RR1O, and RR15). Two registers (RR12 and
RR 13) are read to learn the baud rate generator time
constant. RR2 contains either the unmodified interrupt
Read Register 0

vector (Channel A) or the vector modified by status.information (Channel B). RR3 contains the Interrupt Pending
(IP) bits (Channel A only). RR6 and RR7 contain the
information in the SOLC Frame Status FIFO, butis only read'
when WR 15 02 is set (Figure 18).

Read Register 3

Rx Character Available

Channel B ExtlStatus IP }

Zero Count

Channel B Tx IP

Tx Buffer Empty

Channel B Rx IP

OCO

Channel A Ext/Status IP

Sync/Hunt

Channel A Tx IP

CTS

Channel A Rx IP

Tx UnderrunlEOM

Break/Abort

o
• Always 0 In B Channel

Read Register 1 ,

Read Register 10

All Sent
Residue Code 2
Residue Code 1
Residue Code 0
Parity Error

Rx Overrun Error
CRClFramlng Error

End of Frame (SOLC)

Two Cloc;ks Missing

One Clock Missing
Read Register 2
Read Register 12

Interrupt

Vector *
LowerByIe

of lime Constant

V5
V6

TC5

TC6
TC7

• Modified In B Channel

Figure 18. Read Register Bit Functions

324

•

Read Register 13

Read Register 15

~
,

II ~~-.

TC8
TC9

~="

TC10
TC11

Upper Byte
of TIme Constant

TC12

SyncIHunt tE

TC13

CTSIE

TC14

Tx UnderrunlEOM IE

TC15

Break/Abort IE

Figure 18. Read Register Bit Functions (Continued)

Z85C30 Timing
The SCC generates internal control signals from the IWR
and IRO that are related to PCLK. Since PCLK has no
phase relationship with /WR and IRO. the circuitry generating the internal control signals provides time for metastable conditions to disappear. This gives rise to a recovery
time related to PCLK. The recovery time applies only
between bus transactions involving the SCC 1 he recovery
time required for proper operation is specified from the
falling edge ol/WR or IRO in the first transaction involving
the SCC to the falling edge of /WR or IRO in the second

Al/B,DIIC

IINTACK

ICE

IRD

07-00

__________

transaction involving tile SCC This time must be at least
4 PCLKs regardless of Wllich register or channel is being
accessed.
Read Cycle Timing
, Figure 19 illustrates Read cycle timing. Addresses on
Al/B and OIlC and the status on IINTACK must remain
stable throughout the cycle. If ICE falls after IRD falls. or if
it rises before IRD rises. the effective/RD is shortened.

J~~_________________A_d_d_re_s_S_v_a_lid____________________J~~______

\_I

_ _ _ _ _ _--J

---------------------------c(,,_________

Data Valid

»0---------------

Figure 19. Read Cycle Timing

325

PROGRAMMING (Continued)
Write Cycle Timing
Figure 20 illustrates Write cycle timing. Adpresses on AlIB
and DIIC and the status on IINTACK (nust remain stable
throughout the cycle. If ICE falls after IWA falls, or if it rises

AlIB,OIlC

IINTACK

ICE

before NJA rises, the effective NJR is shortened. Data must
be valid before the falling edge of NJR.
\

Address Valid

\
\

IWR

(

07-00

)

Data Valid

Figure 20. Write Cycle Timing

Interrupt Acknowledge Cycle Timing
Figure 21 illustrates Interrupt Acknowledge cycle timing.
Between the time./INTACK goes Low and the falling ~dge
of IRD, the internal and externallEl/lEO daisy chains settle.
If there is Iln inter~upt pending in the SCC and lEI is High
when IRD falls, the Acknowledge cycle is intended for the
SCC. In this case, the SCC may be programmed to
respond to IRD Low by placing its interrupt vector

IINTACK

~1
Jf

IRO

07-00

on 07-00. It then sets the appropriate Interrupt-UnderService latch internally. If the external daisy cilain is not
used, then AC parameter #38 is required to settle the
interrupt priority daisy chain internal to the SCC If the
external daisy chain is used, the user should follow the
equation in AC Characteristics, Note 5, for calculating the
required daisy-chain settle time.

/
/

\
(

Vector

Figure 21. Interrupt Acknowledge Cycle Timing

326

)

Z80C30 Timing
The SCC generates internal control signals from lAS and
IDS that are related to PCLK. Since PCLK has no phase
relationship with lAS and IDS, the circuitry generating
these internal control signals must provide time for metastable conditions to disappear This gives rise to a recovery
time related to PCLK. The recovery time applies only
between bus transactions involving the SCC. The recovery
time required for proper operation is specified from the
falling edge of IDS in the first transaction involVing the SCC
to the falling edge of IDS in the second transaction involvi~g the SCC.

Read Cycle Timing
Figure 22 illustrates Read cycle timing. The address on
A07-AOO and the state of ICSO and IINTACK are latched
by ttle rising edge of lAS. R//W must be High to indicate a
Read cycle CS1 must also be High for the Read cycle to
occur The data bus drivers in the SCC are then enabled
while IDS is Low.

lAS\, I
ICSO

IINTACK

AD7-ADO

RlIW

CS1

IDS

7
X

I
\

Address)

('-_____-.lX

Data Valid

7
7
\--_ _ _--1
Figure 22. Read Cycle Timing

327

PROGRAMMING (Continued)
Write Cycle Timing
Figure 23 illustrates Write cycle timing. The address on
A07-ADO and the state of ICSO and IINTACK are latched
by the rising edge of lAS. R//W must be Low to indicate a

ICSO

IINTACK

AD7-ADO

RlIW

CS1

IDS

Write cycle. CS1 must be High for the Write cycle to occur.

IDS Low strobes the data into the SCC.

.\"'____________________

___x >CX. . ._______________>C
Data

Address

__----'I

\_---------'I
Figure 23. Write Cycle Timing

Interrupt Acknowledge Cycle Timing
Figure 24 illustrates Interrupt Acknowledge cycle timing.
The address 'On A07-AOO and the state of ICSO and
IINTACK are latched by the rising edge of lAS. However,
if IINTACK is Low, the address and ICSOare ignored.,The
state of the R//W and CS 1 are also ignored for the duration
of the Interrupt Acknowledge cycle. Between the rising
edge of lAS and the falling edge of IDS, the internal and

328

externallEl/lEO daisy chains settle. If there is an interrupt
pending in the SCC, and lEI is High when, IDS fails, the
Acknowledge cycle was intended forthe SCC. In this case,
the SCC is programmed to respond to RO Low by placing
its interrupt vector on 07-DO and then internally set the
appropriate Interrupt-Under-Service latch.

lAS

ICSO

IINTACK

AD7-ADO

(Ignored)

)

C)(

Vector

{
IDS

Figure 24. Interrupt Acknowledge Cycle Timing

OTHER ZILOG DATA COMMUNICATIONS PRODUCTS
SIO Family
Z84C40 SIO
Z84C131PC
Z84C151PC

Dual channel multiprotocol USART.
Z80 CPU with integrated SIO, CTC and WDT.
Z80 CPU with integrated SIO, CTC, WDT and PIO.

SCC Family

Z08530 SCC
Z85130 ESCC
Z16C351SCC
Z80181 SAC

NMOS SCC Low cost with speeds up to 8 MHz.
Enhanced SCC with 4-byte Tx and 8-byte Rx FIFOs and many other new features.
SCC with 4 channel DMA and advanced CPU interface.
Z180 CPU with integrated single channel SCC

USC Family
Z16C30 USC
Z16C33 MUSC
Z16C311USC
Z16C50 DDPLL

Dual channel high performance multi-protocol data communications up to 10 Megabits/second.
Single channel USC w/ ISDN Time Slot Assigner.
MUSC with high performance dual Cllannel DMA (available Q1/91).
Dual channel DPLL cell from the USC

329

ABSOLUT~

MAXIMUM RATINGS

Vee Supply Voltage range.~ ........................ -0.3V to +7.0V
Voltages on aU pins
with respect to GND ................................ -3V to Vee +0.3V
Operating Ambient
Temperature ............................ See Ordering Information
Storage Temperature ............................. -65°C to + 1500C

Stresses greater than those listed 'under Absolute Maximum Ratings may cause permanent damage to the device.
'This Is a stress rating only; operation of the device at any
condition :above those indicated in the operational sections of these specifications is not implied, Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.

SrANDARD TEST CONDITIONS
The DC Characteristics and capacitance sections below
apply for the following standard test conditions, unless
otherwise noted. All voltages are referenced to GND.
Positive current flows into the referenced pin.

•
•
•

+4,50 V S; Vee S; + 5.50 V
GND=OV
Til as specified in Ordering Information

+5V

2.1 KO

FromOutpul
Under Test

From output

Figure 25. Standard Test Load

330

2.2K

Figure 26. Open-Drain Test Load

CAPACITANCE
Symbol

Parameter

CIN
COUT
ClIO

Input Capacitance
Output Capacitance
Bidirectional Capacitance

Min

Max

Unit

pF
pF
pF

15
20

Test Condition
Unmeasured Pins
Returned to Ground

Notes:
f = 1 MHz, over specified temperature range.
Unmeasured pins returned to Ground.

MISCELLANEOUS
Gate Count 6800

DC CHARACTERISTICS
Z80C30/Z85C30
Symbol

Parameter

Min

VIH
VIL
VOHl

Input High Voltage'
Input Low Voltage
Output High Voltage

-0.3
2.4

VOH2
V~L
IlL

Output High Voltage
Output Low Voltage
Input Leakage

101..
Iccl

Output Leakage
Vcc Supply Current [2]

Iccosc

Crystal OSC Current [3]

Typ

2,2

Max

Unit

Vcc + 0.3
0.8

V
V
V

Vee- 0 .8
0.4
±10.0
7

±10.0
12(10 MHz)
15(16 MHz)

V
V

IlA
IlA

rnA
rnA
rnA

Condition

IOH=-1.6rnA
IOH = -250 IlA
101.. = +2.0 rnA
04 VIN + 2.4V
0.4 VOUT + 2.4V
Vcc= 5VVIH = 4.8 VIL = 0
Crystal Oscillator off
Current for each OSC
in addition to Iccl

Notes:
[1] Vee = 5V±10% unless otherwise specffied, over specified temperature range.
[2] Typical Icc was measured with oscillator off.
[3] No Icc (OSC) max is specified due to dependency on external circuit and fTeqency

of oscillation.

331

AC CHARACTERISTICS
Z85C30 Read/Write Tming DIagrams

POLK

AlIB,OI/C

IINTACK

ICE

, ------®2!
~

~ ..- ~

-f-®

r----®--

....

Active

- ®I-

Valid

®-

.!p

:!-@

HP-

/WR

1'"
~

07-DO

Write

~ ,-® f-IWIIREQ
Wait

\
~
~

IWIIREQ
Request,
10TRIIREQ

Request

I
=-@- f---

'-J

liNT
~

"'"

Figure 27. Z85C30 ReadIWrlte Timing Diagram

332

~U'

4---@-

&
~

-'U

IRO

07-00
Read

.... ~

PCLK

IINTACK

IRO

07-00

---------+-----+-H

lEI

lEO,

liNT

Figure 28. Z85C30 Interrupt Acknowledge Timing Diagram

ICE

IRD or /WR

Figure 29. Z85C30 Cycle Timing Diagram

/wR

IRD

Figure 30. Z85C30 Reset Timing Diagram

333

AC CHARACTERISTICS
Z85C30 Read/Write Timing Table
8.5 MHz

10MHz
Min
Max

16 MHz
Min
Max

Symbol

Parameter

Min

Max

1
2
3
4

TwPCI
TwPCh

45
45

1000
1000
10
10

40
40

1000
1000
10
10

26
26,

TrPC

PCLK
PCLK
PCLK
PCLK

1000
1000
5
5

5
6
7
8

TcPC
TsA(WR)
ThA(WR)
TsA(RD)

PCLK Cycle Time
Address to /WR Fall Setup Time
Address to IWR Rise Hold Time
Address to IRD Fall Setup Time

118
66
0
66

2000

100
50
0
50

2000

61
35
0
35

2000

9
10
11
12

ThA(RD)
TsIA(PC)
TsIAi(WR)
ThIA(WR)

Address to IRD Rise Hold Time
liNT ACK to IPCLK Rise Setup 1 ime
liNT ACK to IWR Fall Setup Time
liNTACK to IWR Rise Hold Time

0
20
140
0

0
20
130
0

0
15
75
0

13
14
15
16

TsIAi(RD)
ThIA(RD)
ThIA(PC)
TsCEI(WR)

IINTACK to IRD Fall Setup Time
IINTACK to IRD Rise Hold Time
liNTACK to IPCLK Rise Hold Time
.ICE Low to IWR Fall Setup Time

140
0
38
0

130
0
30
0

75
0
15
0

17
18
19
20

1hCE(WR)
TsCEh(WR)
TsCEI(RD)
ThCE(RD)

ICE to /WR Rise Hold Time
ICE High to /WR Fall Setup Time
ICE Low to IRD Fall Setup Time
ICE to IRD Rise Hold Time

0
58
0
0

0
50
0
0

0
30
0
0

21
22
23
24

TsCEh(RD)
TwRDI
TdRD(DRA)
TdRDr(DR)

ICE High to IRD Fall Setup Time
IRD Low Width
IRD Fall to Read Data Active Delay
IRD Rise to Read Data Not Valid Delay

58
145
0
0

50
125
0
0

30
70
0
0

25
26
27
28

TdRDI(DR)
TdRD(DRz)
TdA(DR)
TwWRI

IRD Fall to Read Data Valid Delay
IRD Rise to Read Data Float Delay
Address to Read Data Valid Delay
/WR Low Width

145

125

29
30
31
32

TsDW(WR)
ThDW(WR)
TdWR(W)
TdRD(W)

Write Data to IWR Fall Setup Time
IWrite Data to IWR Rise Hold Time

10
0

33
34
35
36

TdWRf(REQ) IWR Fall to /WI/REO Not Valid Delay
TdRDf(REQ) IRD Fall to /WI/REO Not Valid Delay
TdWRr(REO) IWR Fall to IDTR/IREO Not Valid
TdRDr(REO) IRD Rise to IDTR/IREO Not Valid

37
38
39
40

TdPC(INT)
TdIAi(RD)
TwRDA
TdRDA(DR)

npc

Low Width
High Width
Fall Time
Rise Time

Notes

[ 1]
[ 1]

[1]
[ 1]
.-

334

/WR Fall to Wait Valid Delay
IRD Low to Wait Valid Delay

IPCLK Fall to liNT Valid Delay
liNT ACK to IRD Fall (Ack) Delay
IRD (Acknowledge) Width
IRD Fall (Ack) to Read Data Valid

'120
35
180

135
38
210

[1]
[ 1]

65
20
100

168
168

160
160

80
80

168
168
4TcPc
NA

160
160
4TcPc
NA

80
80
4TcPc
NA

450

500
145
145
135

175
75
70

125
125
120

[4]
[4J

[5]
70

AC CHARACTERISTICS
Z85C30 Read/Write Timing Table (Continued)

. 41
42
43
44
45
46
47
48
49

Symbol

Parameter

TsIEI(RDA)
ThIEI(RDA)
TdIEI(IEO)
TdPC(IEO)

lEI to /RD Fall (Ack) Setup Time
lEI to IRD Rise (Ack) Hold Time
lEI to lEO Delay Time
IPCLK Rise to lEO Delay

TdRDA(INT)
TdRD(WRQ)
TdWRQ(RD)
TwRES
Tre

IRD Fall to liNT Inactive Delay
IRD Rise to /WR Fall for No Reset
/WR Rise to IRD Fall for No Reset
/WR.& IRD Low for Reset
Valid Access Recovery Time

8.5 MHz
Min
Max

10MHz
Min
Max

16 MHz
Min
Max

95
0

50
0

95
195

90
175

50
80

320

480
15
15
145
4TcPc

15
15
100
4TcPe

Notes

200
10
10
75
4TcPc

[4]

[3]

NOTES:
[1] Parameter does not apply to Interrupt Acknowledge transactions.
[3) Parameter applies only between transactions involving the sec.
[4] Open-drain output, measured with open-drain test load.
[5] Parameter is system dependent. For any sec in the daisy chain, TdIAi(RD) must be greater than the sumofTdPC(IEO) for the highest priorily device
in the daisy chain, TsIEI(RDA) for the sec, and TdIEIf(IEO) for each device separating them in the daisy chain.

335

AC CHARACTERISTICS
Z80C30 Read and Write Timing Diagrams
lAS

/CSO

CSl

~--------------~14~----------------~
nNTACK

RlIW
Read

_ _ _-++-_..1

RlIW

------~-H~------,

Write

------~------~~--------------+-~---------+--

IDS

AD7-AOO
Write

AD7-ADO
Read

~--r-------~~~--r---------~

IWIIREO
Walt

IWIIREO

R~_t

________~~------------~-------'

IDTRlIREO

R~Mt

________

~~------------~--------~-----------------'

I1NT

PCLK'

Figure 31. Z80C30 Read/Write Timing Diagram

336

lAS

IINTACK

IDS

AD7-ADO ------------------------~~--------------~--~

lEI

lEO

liNT

~r_-_--_-_~~6:~~~~~~

________________________________________ __

Figure 32. Z80C30 Interrupt Acknowledge Timing Diagram

lAS

IDS

Figure 33. Z80C30 Reset Timing Diagram

337

AC CHARACTERISTICS .
Z80C30 Read/Write Timing Table
-8 MHz

10 MHz
Max
Min

Symbol

Parameter

Min

1
2
3
4

TwAS
TdDS(AS)
TsCSO(AS)
ThCSO(AS)

lAS Low Width
IDS Rise to lAS Fall Delay
ICSO to lAS Rise Setup Time
ICsa to lAS Rise Hold Time

35
15
0
30

30
10
0
20

5
6
7

TsCS1(DS)
ThCS1(OS)
TsIA(AS)
ThIA(AS)

CS 1 to IDS Fall Setup Time
CS 1 to IDS Rise Hold Time
IINTACK to lAS Rise Setup Time
liNTACK to lAS Rise Hold Time

65
30
10
150

50
20
10
125

9
10
11
12

TsRWR(DS)
ThRW(DS)
TsRWW(DS)
TdAS(DS)

R//W (Read) to IDS Fall Setup Time
R//W to IDS Rise Hold Time
R//W (Write) to IDS Fall Setup -rime
lAS Rise to IDS Fall Delay

65
0
0
30

50
0
0
20

13
14
15
16

TwDSI
TrC
TsA(AS)
ThA(AS)

IDS Low Width

150
4TcPC
10
25

125
4TcPC
10
20

17
18
19
20

TsDW(DS)
ThDW(DS)
TdDS(DA)
. TdDSr(DR)

Write Data to IDS Fall Setup Time
Write\Data to IDS Rise Hold Time
IDS Fall to Data Activ(:l Delay
IDS Rise to Read Data Not Valid Delay

15
0
0
0

10
0
0
0

21
22
23
24

TdDSf(DR)
TdAS(DR)
TdDS(DRz)
TdA(D~)

IDS Fall to Read Data Valid Delay
lAS Rise to Read Data Valid Delay
IDS Rise to Read Data Float Delay
Address Required Valid to Read Data Valid Delay

25
26
27
28

TdDS(W)
TdDSf(REQ)
TdDSr(REQ)
TdAS(INT)

IDS Fall to Wait Valid Delay
IDS Fall to /WI/REO Not Valid Delay "IDS Fall to 101 RI/REO Not Valid Delay
lAS Rise to liNT Valid Delay

29
30
31
32

TdAS(DSA)
TwDSA
TdDSA(DR)
TsIEI(DSA)

lAS Rise to IDS Fall (Acknowledge) Delay
IDS (Acknowledge) Low Width
IDS Fall (Acknowledge) to Read Data Valid Delay
lEI to IDS Fall (Acknowledge) Setup Time

33
34
35
36

ThIEI(DSA)
TdIEI(IEO)
TdAS(IEO)
TdDSA(INT)

lEI to IDS Rise (Acknowledge) Hold Time
lEI to lEO Delay
lAS Rise to lEO Delay
IDS Fall (Acknowledge) tollNl Inactive Delay

37
38
39
40

TdDS(ASO)
TdASO(DS)
TwRES
TwPCI

IDS Rise to lAS Fall Delay for No Reset
lAS Rise to IDS Fall Delay for No Reset
lAS and IDS Coincident Low for Reset

338

Valid Access Recovery Time
Address to lAS Rise Setup Time
Address to lAS Rise Hold Time

PCLK Low Width

Max

[1 J
[1)

[2)

[1)
[1)

120
190
35
210

170
170
4TcPC
500

160
160
4TcPC
500
225
125

140

[3)
[4) ..

[4)
[5J

120

80
0

0
90
200
450

15
20
150
50

[1 J
[1)
[ 1)

140
250
40
260

250
150

Notes'

1000

90
175
450
15
15
100
40

[6J
(4)

[7)
1000

AC CHARACTERISTICS
,
Z80C30 Read/Write Timing Table (Continued)

Symbol

Parameter

41
42
43
44

TwPCh
TcPC
TrPC
TfPC

PCLK
PCLK
PCLK
PCLK

High Width
Cycle Time
Rise Time
Fall Time

8 MHz
Min
Max
50
125

1000
2000
10
10

10MHz
Min
Max
40
100

Notes·

1000
2000
10
10

NOTES:
[1] Parameter does not apply to interrupt Acknowledge transactions,
I
[2] Parameter applies only between transactions involving the sec,
[3] Float delay is defined as the time required for a ±Q,5V change in the output with a maximum DC load and a minimum Ae load,
[4] Open-drain output, measured with open-drain test load,
[5] Parameter is system dependent. For any z-sce in the daisy chain, TdAS(DSA) must be greater than the sum of TdAS(IEO) for the highest priority
device in the daisy chain, TsIEI(DSA) for the z-sec, and TdIEIf(IEO) for each device separating them in the daisy chain,
[6] Parameter applies only to a Z-SCC pulling INT Low at the beginning of the Interrupt Acknowledge transaction,
[7] Internal circuitry allows for the reset provided by the ZB to be recognized as a reset by the z-sce, All timing references assume 2,QV for a logic
·1· and Q BV for a logic .0",
• Units in nanoseconds(ns),

339

AC CHARACTERISTICS
Z85C30/Z80C30 General Timing Diagram
POLK

IW/IREQ
Request

IW/IREQ

Walt
~~~C.

RTxC
Receive

RxO

/SYNC
Extemal
~~~C.

RTxC
Transmit

TxO

~!'I------

_X_ _ _X_"_

~~~c ------'------~-------------@~~~~~~~1~~~---------------------------------------------outp~t ____________________~

iRTxC

~~rrRxC

~~rrRxC.

/OCO

/SYNC

Input

--~
------~~------------Figure 34. Z85C30/Z80C30 General Timing Diagram

340

AC CHARACTERISTICS
Z85C30/Z80C30 General Timing Table'
8.5 MHz
Min
Max

10MHz
Min
Max

16 MHz
Min
Max

250
350
NA

2pO
300
NA

110
180
NA

Symbol

Parameter

1
2
3
4

TdPC(REO)
TsPC(W)
TsRXC(PC) •
TsRXD(RXCr)

/PCLK Low to W/REQ Valid
/PCLK Low to Wait Inactive
/RxC High to /PCLK High Setup Time
RxD to /AxC High Setup Time

5
6
7
8

ThRXD(RxCr)
TsRXD(RXCf)
ThRXD(RXCf)
TsSY(RXC)

RxD to /AxC High Hold Time
RxD to /AxC Low Setup Time
RxD to /RxC Low Hold Time
SYNC to /AxC High Setup Time

9
10
11
12

ThSY(RXC)
TsTXC(PC)
TdTXCf(TXD)
TdTxCr(TXD)

SYNC to /RxC High Hold Time
/TxC Low to /PCLK High Setup Time
/TxC Low to TxD Delay
/TxC High to TxD Delay

13
14
15
16a

TdTXD(TRX)
TwRTXh
TwRTXI
TcRTX

TxD to TRxC Delay
RTxC High Width
TRxC Low Width
RTxC Cycle Time

130
130
472

16b
17
18
19

TxRX(DPLL)
TcRTXX
TwTRXh
TwTRXI

DPLL Cycle Time Min
Crystal Osc. Period
TRxC High Width
TRxC Low Width

59
118
130
130

TRxC Cycle Time
DCD or CTS Pulse Width
SYNC Pulse Width

472
200
200

20. TcTRX
21
TwEXT
TwSY
22

NA
0

125
0
125
-150

0
60
-100

5TcPc
NA

190
190

150
150
120
120
400
100
120
120
400
120
120

1000

[1)
[2,4)
[2)
[2,5)

80
[6)
16]
[6,7)

80
80
244

qO
1000

85
85

140

200

[1,4]
[1)
[1)
[1,5)
[1,5)
[1)

150
0
150
-200

Notes·

31
100
80
80
244
70
70

1000

[7,8]
[3]
[6]
(6)
[6,7)

Noles:

[11' RxC is /RTxC or /TRxC, whichever is supplying the receive clock.
[2)
[3)
[4)
[5)
[6)
(7)
[8)

TxC is {TRxC or /RTxC, whichever is supplying the transmit clock.
Both /RTxC and /SYNC have 30 pf capacitors' to ground connected to them.
Synchronization of AxC to PCLK is eliminated in divide by four operation.
Parameter applies only to FM encoding/decoding.
Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to case PCLK requirements.
The rnaxirrum receive or transmit data rate is 1/4 PCLK.
Applies to DPlL clock source only. Maximum data rate of 1/4 PCLK still applies. DPLL clock should have a 50% duty cycle .

• Units in nanoseconds (ns).

341

AC CHARACTERISTICS
Z85C30/Z80C30 System Timing Diagram
IRTxC, ITRxC
Receive

/wIIREO
Request

/wIIREO
Wait

/SYNC
Output

liNT

ITRxC, IRTxC
Transmit

/WI/REO
Request

/wIIREO
Wait
~----~6)------~

IDTRl/REO
Request

liNT

ICTS,/DCD

ISYNC
Input

K
K
~-

liNT

tfi'

Figure 35. Z85C30/Z80C30 System Timing Diagram

342

AC CHARACTERISTICS,
Z85C30/Z80C30 System Timing Table
8.5 MHz
Min Max

10 MHz
Min Max

Symbol

Parameter

1
2
3
4a

TdRXC(REQ),
TdRXC(W)
TdRdXC(SY)
TsRXC(INT), Z85C30

IRxC High 10 W/REO Valid
IRxC High to Wait Inactive
IRxC High 10 SYNC Valid
IRxC High to INT Valid

8
8
4
10

12
14
7
16

8
8
4
10

12
14
7
16

TdRXC(INT), Z80C30

IRxC High 10 INT Valid

5
6

TdTXC(REQ)
TdTXC(W)

/TxC Low to W/REO Valid
/TxC Low 10 Wait Inactive

8
2
5
5

12
3
8
11

8
2
5
5

12
3
8
11

TdTXC(DRO)
Td rXC(lNT), Z85C30
TdTXC(INT), Z80C30

/Txc Low to DTR/REO Valid
ITxC Low 10 liNT Valid
ITxC Low 10 liNT Valid

4
6
4
2

7
10
6
3

4
6
4
2

2
2
2
2

6
3
6
3

2
2
2
2

8a
8b
9a
9b
lOa
10b '

TdSY(INT)
TdSY(INT)
TdEXT(INT), Z85C30
TdEXT(lNT), Z80C30

SYNC 10 INT Valid
SYNC 10 INT Valid
lOCO or ICTSlo liNT Valid

16MHz
Min Max

Notes'

12
14
7
16

[2)
[1,2)
(2)
[1,2)

5
5

8
11

[1,2)
(4)
l3)
[1,3)

7
10
6
3

4
6

7
10

6
3
6
3

8
8
4
10

[3)
[1,3)
[1,3)

(4)
[1]
[1.4]
[1]
[1,4]

Notes:
[1] Open drailKJUtput, measured with open-drain test load.
[2] JRxC is /RTxC or {TRxC, whichever is supplying the receive clock.
, [3] {TxC is {TRxC or IRTxC, whichever is supplYing the transmit clock.
[4] Units equal to lAS .
• Units equal to TcPc.

343

344

PRODUCT SPECIFICATION

Z8030/Z8530
Z-BUS SCC SERIAL
COMMUNICATION CONTROLLER

Features

• Two independent, a to 2M bit/second, fullduplex channels, each with a separate crystal
oscillator, baud rate generator, and Digital
Phase-Locked Loop for clock recovery.
• Multi-protocol operation under program
control; programmable for NRZ, NRZI, or
FM data encoding.
• Asynchronous mode with five to eight bits
and one, one and one-half, or two stop bits
per character; programmable clock factor;
break detection and generation; parity,
overrun, and framing error detection.

synchronous characters and CRC generation and checking with CRC-16 or
CRC-CCITT preset to either Is or as.
• SDLCIHDLC mode with comprehensive
frame-level control, automatic zero insertion
and deletion, I-field residue handling, abort
-generation and detection, CRC generation
and checking, and SDLC Loop mode
operation.
• Local Loopback and Auto Echo modes.
• Supports Tl digital trunk.

• Synchronous mode with internal or external
character synchronization on one or two

General
Description

The SCC Serial Communications Controller
is a dual-channel, multi-protocol data communications peripheral designed for use with conventional non-multiplexed buses and the Zilog
Z-BUS.- The SCC functions as a serial-to-parallel,
parallel-to-serial converter/controller. The SCC
can be software-configured to satisfy a wide variety of serial communications applications. The

DATA.U.

CH·A

device contains a variety of new, sophisticated
internal functions including on-chip baud rate
generators, Digital PhaseLocked Loops, and
crystal oscillators that dramaticaily reduce the
need for external logic.

ADOU'"
DATA.U.

BUS (
TIMING
ANDR••ET

'·RIAL
DATA

CONTROL

CHANNIL
CLOCKS
CHANN.L
CONTROLS

FOR MODEM,

DMA,OR
OTHIR

CH·B

INTERRUPT

I
I

SERIAL
DATA

CHANNIL
CLOCKS
CHANN.L
CONTROLS

PORMOD. .,
DMA,OR
OTHBR

+5V GND PCLK

Flgme la. PID FuDdioDs. _

Flgme lb. PID FuuctIoDs. zaoao

345

__________, .,. . _Q _ _"'_m,__

M~'~
~~~

...

·'""I"~_

·""~"~'

.. ,' ,"

The see handles asynchronous formats,
Gen~tral
Description Synchronous byte-oriented protocols such as
(Continued)
IBM Bisync, and Synchronous bit-oriented protocols such as HDLe and IBM SDLe. This versatile device supports virtually any serial data
transfer application (cassette, diskette, tape
drives, etc.).
'
The device can generate and check eRe
codes in any Synchronous mode and can be
programmed to check data inteqrity in various

modes. The see also has facilitiesfor
modem controls i~ both ~hannel~. In'appli-"
, cations where these controls are ncrt"needed,
the modeIJ;l controls can beused fOf
general-purpose 1/0.,
The daisy-chain interrupt hierarchy is also
supported-as is standard for Zilog peripheral
components.

....

.
D,

AD,

ADs

Do
AD
Wi\
Ali

AD,

'II

RIW

iNiiCK

iiifACi

CSii

+5V
W/REQA

GND

iiiT
'EO
'II

iiif

D/C

RTiCi

SYNci
iffiCi

RxOA

Q' Q'>

Aifi

lEI 8

36,
37

CE
ole

SVNCA 12

zauo
(Top View)

GND

WliiEQB

iYNCii

RxDA

fRiCA

:i1

RxDB

llcDA

'I'IIil:I!

llcDB

lffiiCA 13

PCLK

DCDS

~ ~~o·~o·~'~·~~·~~ ~

'EO 7

WfIm}A

DCiiA

FIgure 2b. DIP P1D AsslgnmeDts. Z8030

~ ?' <:>" 4i> ~

+5V 10

DTiiiiiEcii
Rlsa

1 44 43 42 41 40

INTACK 9

TxDB

RTsA

DTiiiiiEcii
RTS~

FIgure 2a. DIP PlD AulgDD1ents. Z8530

TRxCB

DTRlREQA

ffii
DCoi

4:' e::::
\'--I

\
\~

___--,I

Do-D? ------------------~(C:::::J'X DATAVAUD )
Figure 12. Read ~le TImlDg

Write Cycle Timing. Figure 13 illustrates

Write cycle timing. Addresses on AlB and ole
and the status On INTACK must remain stable
_ throughout the cycle. If CE falls after WR falls
~'~

or if it rises before WR rises, the effective ~ is
shortened. Data must be valid before the falling
edgeofWR.

>e::::

________J)(~_____________A_DD_.__
US V_~_D_____________

\~--

\ _ _ _ _ _..J

Do-D7---------------«::::~DA:U~V:AU~D~::::J)~------Figure 19. Wrtte Cycle TImIDg

Interrupt Acknowledge Cyc:le Timing_ Figure

14 illustrates Interrupt Acknowledge cycle
timing. Between the time INTACK goes Low
and the falling edge of RD, the internal and
external IEIIIEO daisy chains settle. If there is
an interrupt pending in the SCC and lEI is High
~~~

when 1m falls, the Acknowledge cycle is
intended for the SCC. In this case, the SCC
may be pr~rammed to respond to RD Low by
placing its interrupt vector on 00-07 and it then
sets the appropriate Interrupt-UnderService '
latch internally.

______~/.~'____________________..Jlr-----

...JI

I~_ _ _ _

Do-D7 - - - - - I h . }--~(===_-=:;)(C::VE~CT'"'::»--Figure 14. IDtemapt Acbowleclge Cycle TlmlDg

359

Z8030 TimiDg'

The see generates internal' control sigrials
from"AS and DS that are related to PCLK.
Since' PCLK has no phase relationship with
AS and DS, the circuitry generating these
internal control signals must provide time for
metastable conditions to disqppear. This gives
rise to a recovery time related to PCLK. The
recovery time applies only between bus transactions involVing the SCC. 'the recovery time
required for proper operation is speCified from
the falling edge of DS in the first transaction

Cio=-'
I

\~----------~---------

--'XC~AD~D.~.:SS~»-:'---(:::::X

II/W _ _ _ _ _ _ _

cs,

Read Cycle Timing. Figure 15 illustrates
Read cycle timi~ The a~n ADo-AD7
and the state of CSo and INTACK are latched
by"the rising edge of AS. RIW must be High to
indicate a Read cycle. CSj must also be High
for the Read cycle to occur. The data bus
drivers in the SCC are then enabled while
DS is Low.

.NTACK _ _ _ _ _

ADo-AD7 _ _

involving the see to the fC\lhng edge'of DS in
the second transaction involving the SCC.

DATA VALID )--

..J!

-----'

iii

,__________--:--____r--

Figure 15. Read Cycle Timing

Write Cycle Timing. Figure 16 illustrates
Write cycle timing. The address on ADo-AD7
and the state of CSo and INTACK are latched
by the ~ising edge of AS. RIW must be Low to

CiO=-'

--.-J

INTACl~
ADo-AD7

=::x:

ADDRESS

indicate a Write cycle. CSt must be High for the
Write cycle to occur. OS Low strobes the data
into the SCC.

x::x"'"'--________________x::
__
DATA

II/W _ _ _ _ _ _ _ _~,~_ _~_ _~_ _ _ _ _ _ _ _~r=

cs, _ _ _ _ _....
iii

,_________________r--

FIgure 16. Write Cycle TimiDg

360

Interrupt Acknowledge Cycle Timing. FIgure
17 illustrates Interrupt Acknowledge cycle
tim~. The address on ADo-AD7 and the state
of CSo and INTACK are latched by the rising
edge of AS. However, if INTACK is Low, the
address and CSo are ignored. The state of the
R/W and CSI are also ignored for the duration
of the Interrupt Acknowledge cycle. Between
the rising edge of AS and the falling edge of

Ci~

=::x:

(IGNORED)

DS, the internal and external IEIIIEO daisy
chains settle. If there is an inte!!!Y't pending in
the SCC and lEI is High when DS falls, the
Acknowledge cycle was intended for the SCC.
In this case, the SCC may be programmed to
respond to,RD Low by placing its interrupt
vector on Do-D7 and it then internally sets the
appropriate Interrupt-Under-Service latch.

v---:

~~---------------------

r---'-1--'- - - - -

'-----.,;
ADO-AD,

=::X::!(IG~N:O:AE~Dl=»--"""'()'l'---C:X

VECTOR

iii

F"agure 17. iDterrupt AcIuIowiedge Cycle Timing

Absolute
Maximum
Ratings

Standard
Test
Conditions

Voltages on all pins with respect
to GND ................... - 0.3V to +7.0V
Operating Ambient
Temperature ........ See Ordering Information
Storage Temperature ........ -65°C to + 150°C
The DC characteristics and capaCItance section beloW apply for the follOWing standard test
conditions, unless otherwise noted. All voltages
are referenced to GND. Positive current flows
into the referenced pin.
Standard conditions are as follows:

Stresses greater than those hsted under Absolute Maximum Ratings may cause permanent damage to the device.
Th,s Is a stress rating only; operation of the deVIce at any
condition above those indicated In the operational sections
of these specdlcahons IS not llDphed. Exposure to absolute
maxImum rating conditions for extended per~ods llllIY affect
device reliability.

• +4.75 V :S Vee :S +5.25 V
• GND = OV
• TA as specified in Ordering Information
All ac parameters assume a load capacitance
of 50 pF max.

+5V

21<

+5V

FROM OUTPUT
UNDER TEST

~ 22K
I'OP'

Standard Test Load

OpeD-Drain Test Load

361

Symbol

Characteristic:s

VIH
VIL
VOH
VOL
IlL
IoL
Ice

vee = 5 V
Capacitance

Symbol'

Parameter '

MID

Max

Unit',

Input'High Voltage
Input Low Voltage'
Output High Voltage
~tput Low Voltage
Input Leakage
Output Leakage
Vee Supply Current

2.0
-0.3
2.4

Vee +0.3
0.8

V
V
V
V

± 5% unless

otherwl~

0.4
:1:10.0
±1O.0
250

Parameter

Min

,.A
,.A
rnA

Max

Unit

CIN

Input CapaCitance
Output CapaCitance

10
15

COUT
CliO

Bidirectional Capacitance

= 1 MHz, over specUled tempeI:ature range.
Unmeasured pms returned. to ground.

362

IoH =
IoL'=
0.4 s
0.4 S

Gate Count

- 250 ,.A
+ 2.0 rnA
VIN S +2.4V
Your S +2.4V

specified, over specified temperature range.

Miscellaneous

Condition

6000

Test Condition
Unmeasured Pins
Returned to Ground

Z8530 AC CHARACTERISTICS

Number Symbol

1
2
3
4
5

4MHz
Min
Max

Parameter

105
105

TwPCI

PCLK Low Width

TwPCh

PCLK High Width

TfPC

PCLK Fall Time

TrPC

PCLK Rise Time

TcPC

PCLK Cycle Time

6
7
8
9
10

TsA(WR)

Address to WR

ThA(WR)

Address to WR

t Hold Time

TsA(RD)

Address to l1i5 ~ Setup Time

ThA(RD)
TsIA(PC)

Address to m5 t Hold Time
i"f\i'TACK to PCLt< t Setup Time

11
12
13
14
15

TsIAI(WR)

~ to WR ~ Setup Time

ThIA(WR)

INTACK to WR

250

Setup Time

t Hold Time

TsIAi(RD)

~ to RD ~ Setup Time

ThIA(RD)

~ to RD

ThIA(PC)

INTACK to PCLK t Hold Time

TsCEI(WR)

ThCE(WR)

18
19
20

TsCEh(WR)
TsCEI(RD)

C'E Low to WR ~ Setup Time
CE to WR t Hold Time
CE High to WR ~ Setup Time
CE Low to RD ~ Setup Time

ThCE(RD)

CE to RD t Hold Time

21
22
23
24
25
26

TsCEh(RD)

CE High to m5 ~ Setup Time

TwRDI

RD Low Width

TdRD(DRA),

TdRDr(DR)

t to Read Data Not Valid Delay

TdRDf(DR)

TdRD(DRz)

m5 t to Read Data Float Delay

2000
2000
20
20
4000

Hold Time

to Read Data Active Delay

6 MHz

Min

Max

70
70

1000
1000
10
10
2000

165

8MHz
Min
Max

50
50

125

80
0
80
0
10

70
0
70
0
10

200
0
200
0
100

160
0
160
0
100

145
0
145
0
85

0
0
100
0
0

0
0
70
0
0

0
0
60
0
0

100
240
0
0

70
200
0
0

60
150
0
0

250
70

to Read Data Valid Delay

180
45

Notes

1000
1000
10
10
2000

140
40

NOTES

1, Parameter does not apply tb Interrupt Acknowledge transactions
2 Float delay IS defined as the time reqUired for a ± 0 5V change at the output w~h a maximum de load and minimum ac load
tUnM In nanoseconds (ns),

Reset
Timing

Z8530

C-

u~
Cycle
Timing

Ci\

Z8530
iii) .. Wli

---{

J
'

I
\

L
363

'~~~-~-----'''''''''-'''''''''''-'

.... ".'''"'-...;."...,...,. ....

Z8530 AC CHARACTERISTICS (Continued)

Number Symbol

4MHz
Min
Max

Parameter

TdA(DR)

Address Required Valid to Read Data
Valid Delay

TwWRI

WR Low Width
~

6MHz
Min
Max

300

8MHz
Min
Max

280

Notes

220

240

200

150

TsDW(WR)

Write Data to WR

ThDW(WR)

Write Data to, WR t Hold Time

TdWR(W)

to Wait Valid Delay

240

200

170

Wait Valid Delay

240

200

170

240

200

170

Setup Time

TdRD(W)

TdWRf(REQ)

WR ~ to W/REQ Not Valid Delay

TdRDf(REQ)

RD ~ to W/REQ Not Valid Delay

TdWRr(REQ)

TdRDr(REQ)

RD t to DTR/REQ Not Valid Delay

TdPC(IND

PCLK ~ to INT Valid Delay

TdIAi(RD)

INTACK to RD

TwRDA

RD (Acknowledge) Width

TdRDA(DR)

RD ~ (ACknowledge) to Read Data
Valid Delay

TsIEI(RDA)

lEI to RD ~ (Acknowledge) Setup
Time

ThIEI(RDA)

lEI to RD t (Acknowledge) Hold Time

TdIEI(IEO)

lEI to lEO Delay Time

120

100

TdPC(IEO)

PCLK t to lEO Delay

250

200

TdRDA(INT)

TdRD(WRQ)

RD t to WR

TdWRQ(RD)

WR t

to RD ~ Delay for No Reset

TwRES

WR and RD Coincident Low for Reset

250

200

150

Trc

Valid Access Recovery Time

4TcPC

DTR/REQ Not Valid Delay

(Acknowledge) Delay

Delay for No Reset

200

170

4TcPC

500

250

200

150

250

200

150

250

180

120

100

to INT Inactive Delay
~

240
4TcPC

140
95
0

500

500
30

450

NOTES:
3. Parameter applies only between transactions involving the SCC.
4 Open-drain output, measured with open-drain test load.
5. Parameter IS system dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of TdPC(IEO) for the highest priority device In the daisy chain, TsIEI(RDA) for the SCC, and TdIElf(IEO) for each device separating them In the daisy chain.
tUnits in nanoseconds (ns).

364

PCLK

""'--'

Z8530

C\-~
-!,.

::)

~ ~r::-::~
J(

'i' ~

-!,.

- ~ I-- r
ReAD

-----.Jl

®-I-

\.~--------------

W_Q
WAIT

~ --------------------------

1-_ _ _ _-+___.1"~I

WIlUEQ _ _ _ _ _
REQUEST

,1!-

DTRlREQ
REQUEST

. ,NT

II
-----r-----"1:::=====:::;:;;:21;:::=====:~~1

~----~D~----~--------------------------PCLK

366

Z8030 AC CHARACTERISTICS

Number Symbol

4MHz
Min
Max

Parameter

6MHz
Min
Max

8M,Hz
Min
Max

TwAS

AS Low Width

TdDS(AS)

TsCSO(AS)

ThCSO(AS)

t to AS ~ Delay
CSo to AS t Setup Time
CSo to AS t Hold Time

TsCS1(DS)

CS1 to OS

100

ThCS1(DS)

CS1 to OS t Hold Time

TsIA(AS)

INTACK to AS

ThIA(AS)

t
INTACK to AS t

250

200

150

100

Setup Time

Setup Time
Hold Time

TsRWR(DS)

RfW (Read) to OS ~ Setup Time

ThRW(DS)

RfW to OS

'TsRWW(DS)

t Hold Time

RfW (Write) to OS ~ Setup Time
AS

t to OS ~ Delay

0,
60

TdAS(DS)

TwDSI

OS Low Width

240

200

150

TrC

Valid Access Recovery Time

4TcPC

TsA(AS)

Address to AS t Setup Time

ThA(AS)

Address to AS t Hold Time

TsDW(DS)

Write Data to OS

Setup Time

ThDW(DS)

Write Data to OS

Hold Time

TdDS(DA)

OS ~ to Data Active Delay

TdDSr(DR)

OS t

TdDSf(DR)

to Read Data Valid Delay

250

180

140

TdAS(DR)

t to Read Data Valid Delay

520

300

250

\0 Read Data Not Valid Delay

Notes

NOTES'

1, Parameter does not apply to Interrupt Acknowledge transactions,
2, Parameter applies only beiween transactions involving the see
tUnrts In nanoseconds (ns),

367

za030 AC CHARACTERISTICS (Continued)

Number Symbol

Parameter

4MHz
Min
MII X

6MHz
Min
Max

8MHz
Min
Mal'

40
260

Notes

TdDS(DRz)

DS t to Read Data Float Delay

TdA(DR)

Address Required Valid to Read Data
Valid Delay

570

310

TdDS(W)

DS ~ to Wait Valid Delay

240

200

170

TdDSf(REO)

DS ~ to ViiiREO Not Valid Delay

240

200

170

TdDSr(REO)

DS ~ to i5i'R/REO Not Valid Delay

4TcPC

TdAS(INT)

AS t to iNf Valid Delay

TdAS(DSA)

AS t to DS

TwDSA

DS (Acknowledge) Low Width

TdDSA(DR)

DS ~ (Acknowledge) to Read Data
Valid Delay

TsIEI(DSA)

lEI to DS

ThIEI(DSA)

lEI to OS t (Acknowledge) Hold Time

TdIEI(IEO)

lEI to lEO Delay

120

100

TdAS(IEO)

AS i to lEO Delay

250

200

TdDSA(INT)

DS ~ (Acknowledge) to INT Inactive
Delay

450

TdDS(ASO)

DS t to AS

Delay for No Reset

TdASO(DS)

AS t to DS

Delay for No Reset

TwRES

AS and DS Coincident Low for Reset

250

TwPCI

PCLK Low Width

105

2000

TwPCh

PCLK High Width

105

2000

1000

TcPC

PCLK Cycle Time

250

4000

165

2000

125

TrPC

PCLK Rise Time

TfPC

PCLK Fall Time

500

(Acknowledge) Delay

(Acknowledge) Setup Time

500

250

390

200

150

250
120

180
100

4
5

140

500

200
70

500

150
1000

NOTES:
3. Float delay is defined as the time required for a ± O.SV change in the output with a maximum dc load and a minimum ac load.
4. Open-drain output, measured with open-drain test load.
5. Parameter,is system dependent. For any l-See in the daisy chain, TdAS(DSA) must be greater than the sum of TdAS(IEO) for the highest priority
device In the daisy chain, TsIEI(DSA) for the l-See, and TdIElf(IEO) for each device separating them in the daisy chain.
6. Parameter applies only to a l-See pulling INT Low at the beginning of the Interrupt Acknowledge transaction.
7. Internal circuitry allows for the reset provided by the lS to be recognized as a reset by the l-See.
All timing references assume 2.0V for a logic "1" and O.SV for a logic "0".
tUnits in nanoseconds (ns).

368

(

Interrupt
Ac:knowledge
Timing

~
-----""

Z8030
iii

A~-AD·------------------t-------------~~~~~~~tit:------@

.B. __

______

J~-+

________

______

'BO

369

PRELIMINARY PRODUCT SPECIFICATION

Z80181
Z181 SAC
SMART ACCESS CONTROLLER
FEATURES
•

ZOO1OOCoinpatibie MPU Core with 1channelofZ85C30
SCC, Z80 GTC, two 8-bit general purpose parallel
ports, and two chip select signals.

•

High speed operation (10/12.5 MHz)

•

Low power consumption in two operating modes:
(TBO) mA Typ. (Run mode)
(TBO) mA Typ. (STOP mode)

•

Wide operational voltage range (5V ±10%)

•

nUCMOS compatible

•

Clock Generator

•

One channel of Z85C30 Serial Communication Controller
(SCC)

•

Z100 Compatible MPU core, which has:
Enhanced ZOO CPU core
Memory Management Unit (MMU) enables access
to 1MB of memory
Two Asynchronous channels
Two OMA channels
Two 16-bit Timers
Clocked serial I/O Port

•

Z84C30CTC

•

Two 8-bit general purpose parallel ports

•

Memory configurable RAM and ROM chip select pins

•

100-pin QFP Package

GENERAL DESCRIPTION
The Z80181 SAC Smart Access Controller (hereinafter,
referred to as Z 181 SAC) is a CMOS 8-bit microprocessor.
It is integrated with the Z100 compatible MPU (Z181 MPU),
one channel of Z85C30 Serial Communication Controller
(SCC), Z80 CTC, two 8-bit general purpose parallel ports,
and two chip select signals, all into a single 100-pin QFP
(Quad Flat Pack) package. This high-end superintegrated
intelligent peripheral controller is targeted for a broad
range of intelligent communication control applications,
i.e., terminals, printers, modems, and slave communica-

370

tion processors for 8-, 16- and 32- bit MPU based systems.
Also included are enhancemenVcost reductions of existing' hardware using ZOO/ZJOO with Z8530/Z85C30 applications. Figure 1 shows the block diagram of the ZOO181.

or,

Note: All Signals with a preceding front slash,
are active
Low e.g.; 8IIW (WORD is active Low); IBIW (BYTE is active
Low, 0r1y); INIIS (NORMAL and SYSTEM are both
active Low).

07-00

Z80180
Compatible
Core

Control

A19-AO

SCC
(1 Channel)

A19-A12

/RAMeS

Modem/Control
Signals

CTC

Glue
Logic

L-..-

Rx Data
~

1
/ROMes

Tx Data

Address
Decode
Logic

PIA1

Bit Programmable
Bi-directional 110
or 110 Pins of eTe

PIA2

Bit Programmable
Bi-directiooal 110

,
ZS0181 = Z180 + SCC + CTC + PIA

Figure 1. Z80181 Block Diagram

.371

-~~".~.~,
".~~.-.~,
."-.~"~-,,~,

"-_....

PIN DEFINITIONS
The pin assignment is shown on Figure 2. Following is the
description on each pin.

nNTl
nNT2
ST
AO
A1
A2
A3
A15
A4
A5
A6
A7
AS
A9
Al0
All
A12
GND
A13
A14
A16
DO
Dl
D2
D3

100

85
80

0
5

10
70

TxAO

Z80181
100-PIN QFP

ICTSO
fRTSO
65

20
60

25
55

D5
D6
D7

Al8fTOUT
A19
GND
lEI
fROMeS
lEO
GND
IOCD
ICTS
fRTS
IDTRlfREO
TxD
fTRxC
RxD

IWlfREO

30
35

Figure 2. Z80161 Pin-out Assignment

372

TxAl
CKAOflDREOO
RxAO
IDCDO

fRAMCS

fTENDl
IDRE01
CKS
Rxs/ICTS1
TxS
CKAlffTENDO
RxAl
TEST

CPU SIGNALS
,I

Pin Name

Pin Number

Input/Output, 3-State

Function

A19 - AO

4-17,19-21,
64,65,91

I/O, Active 1

Address Bus. A 19 - AO form a 20-bit address bus which
specifies I/O and memory addresses to be accessed
During the refresh period, addresses for refreshing are
output. The address bus enters a high-impedance state
during Reset and external bus acknowledge cycles. The
bus is an input when the external bus master is accessing
the on-chip peripherals. Address line A 18 is multiplexed
with the output of PRT Channel 1 (TOUT, selected as
address output on Reset).

00-07

22-29

I/O, .i\ctive 1

8-bit bidirectional data bus. When the on-chip CPU is accessing on-chip peripherals, tllese lines are outputs and
110Id the data to/from the on-chip peripllerals.

/RO

I/O, Active 0

Read signal. CPU read signal for accepting data from
memory or I/O devices. When an external master is accessing the on-chip peripherals, it is an input signal.

/WR

I/O, Active 0

Write Signal. This signal is active when data to be stored
in a specified memory or peripheral device is on tile MPU
data bus. V)Jhen an external master is accessing the onchip peripherals, it is an input signal.

/MREQ

I/O, 3-State, Active 0

Memory request signal. When an effective address for
memory access is on the address bus, /MREQ is active.
This signal is analogous to the /ME signal of the Z64 180.

/IORQ

I/O, 3-State, Active 0

I/O request signal. When addresses for I/O are on tile lower
8 bits (A7-AO) of the address bus In the I/O operallon, "0"
is output In addition, the /IORQ signal is output willI the
/M1 signal during the interrupt acknowledge cycle to
inform peripheral devices that the interrupt response vector
is on the data bus. This signal is analogous to the /IOE
signal of the Z64180.

/M1

Out, 3-State, Active 0

Machine cycle "1". /MREQ and /M1 are active together
during lhe operation code fetch cycle /M1 is output for
every opcode fetch when a two byte opcode is executed
In the maskable interrupt acknowledge cycle, HIlS Signal is
output together with /IORQ It is also used with /HALT and
ST signal to decode the status of the CPU Machine cycle.
This signal is analogous to the /LiR signal of the Z64180.

/RFSH

Out, 3-state, Active 0

The Refresh signal. When the dynamic memory refresh
address is on the low order 8-bits of the address bus (A7
- AO), /RFSH is active along with the /MREQ signal This
signal is analogous to the /REF signal of the Z64180

373

CPU SIGNALS (Continued)
Pin Name

Pin Number

Input/Output. 3-State

Function

IINTO

100

Wired-OR 1/0. Active 0

Maskable Interrupt Request O. Interrupt is generated by
peripheral devices. This signa( is accepted if the interrupt
enable Flip-Flop (IFF) is set to "1 ". Internally, the SCC and
CTC's interrupt signals .are connected to this line, and
require an external pull-up resistor.

IINT1,
IINT2

1,2,

In, Active 0

Maskable Interrupt Request 1 and 2. This signal is generated by external peripheral devices. The CPU 11Onors
these requests at the end of current Instruction cycle as
long as the INMI, IBUSREO and liN TO signals are inactive.
The CPU will acknowledge these interrupt requests with an
interrupt acknowledge cycle. Unlike the acknowledgement for IINTO, during this cycle, neither IM1 or !lORO will
become active.

INMI

In, Active 0

Non-maskable interrupt request signal. This interrupt request has a higher priority than the maskable interrupt
request and does not rely upon the state of the interrupt
enable Flip-Flop (IFF).

IHALT

Out, 3-State, Active 0

Halt Signal. This signal is asserted after the CPU has
executed either the HALT or SLP instruction, and is waiting
for either non-maskable interrupt maskable interrupt before operation can resume. It is also used with the IM1 and
ST signals to decode the status 01 the CPU machine cycle.

IBUSREQ

In, Active 0

BUS request signal. This signal is used by extemal devices
(such as a OMA controller) to request access to the system
bus. This request has higher priority than INMI and is
always recognized at the end of the cl1rrent macl11ne cycle
This signal will stop the CPU from executing further instructions and place the address bus, data bus, IMREO, /IORO,
fRO and /WR signals into the high impedance state.
/BUSREO is normally wired-OR and a pull-up resistor IS
externally connected.

/BUSACK

Out, Active 0

Bus Acknowledge signal. In response to IBUSREO signal,
/BUSACK informs a peripheral device that the address
bus, data bus, /MREO, /IORO, /RO and jWR signals have
been placed in the high impedance state.

/WAIT

Wired-OR I/O, Active 0

Wait signal. /WAIT informs the CPU that the specified
memory or peripheral is not ready for a data transfer. As
long as/WAIT signal is active, the MPU is continuously kept
in the wait state. Intemally, the /WAIT signal from lile SCC
interface fogic is connected to ttllS hne, and requres an
external pull-up resistor.

374

PERIPHERAL SIGNALS
Pin Name

Pin Number

Input/Output, 3-State

Function

RXAO,RXA1

70. 74

In. Active 1

ASCI Receive data 0 and 1. These signals are the receive
data to the ASCI channels.

TXAO,TXA1

69. 72

Out, Active 1

ASCI Transmit data 0 and 1. These signals are the receive
data to the ASCI channels. Transmit data changes are with
respect to the falling edge of the transmit clock

/RTSO

Out, Active 0

Requestto send O. This is a programmable modem control
signal for ASCI channel O.

/DCDO

In. Active 0

Data Carrier Detect O. This is a programmable modem
control signal for ASCI channel O.

/CTSO

In, Active 0

Clear To Send O. Th!s is a programmable modem control
signal for ASCI channel O.

/CTS1/RXS

In. Active 0

Clear To Send O/Clocked Serial Receive Data. lhis is a
programmable modem control signal for ASCI channel O.
Also. this Signal becomes receive data for the CSIO
channel under program control. On power-on Reset, this
pin is set as RxS.

CKAO//DREOO

I/O, Active 1

Asynchronous ClockO/DMACO request. This pin is the
transmit and receive clock for the Asynchronous channel
O. Also, under program control, this pin is used to request
a DMA transfer from DMA channel O. DMAO monitors tilis
input to determine when an external device is ready for a
read or write operation. On power-on Reset. this pin is
initialized as CKAO.

CKA 1//TENDO

I/O, Active 1

Asynchronous Clock1/DMACO Transfer end. This pill is the
transmit and receive clock for the Asynchronous "hannel
1. Also, under program control, this pin becomes
/TENDO and is asserted during the last write cycle of the
DMAO operation and is used to indicate the end of the
block transfer. On power-on Reset, tllis pin initializes
as CKA1.

/TEND 1

Out. Active 0

DMAC1 Transfer end. This pin is asserted during the last
write cycle of the DMA 1 operation and is used to indicate
the end of the block transfer.

CKS

I/O. Active 1

CSIO clock This line is the clock for the CSIO channel.

TXS

Out. Active 1

CSIIO Tx Data. This line carries the transmit data from the
CSIO channel.

/DREQ1

In. Active 0

DMAC1 request. This pin is used to request a DMA transfer
from DMA channel 1. DMA 1 monitors this input to determine when an external device is ready for a read or write
operation ..

375

sec SIGNALS
Pin Name'

Pin Number

Input/Output, 3-State

Function

/W//REQ

Active 0

Wait/Request. Open-drain when programmed for a Wait
fUljlction, driven" 1" or "0" when programming for a Request
function. Used as /WAIT or /REQUEST depending upon
SCC programming. When programmed as /WAIT, this
signal is asserted to alert the CPU that addressed memory
or I/O devices are not ready and that the CPU should wait.
When programmed as /REQUEST, this signal is asserted
when a peripheral device associated with a DMA port is
ready to read/write data. After reset, this pin becomes
"/WAIT".

/SYNC

I/O, Active 0

Synchronization. This pin can act either as input, output, or
part of the crystal oscillator circuit. In asynchronous receive mode (crystal oscillator option not selected), this pin
is an input similar to /CTS and /DCD. In this mode, transitions on this line affect the state of the Sync/Hunt status bit
in Read Register 0 but has no other function.
In external sync mode with crystal oscillator option not
selected, this line also acts as an input. In this mode,
/SYNC must be driven "0" two receive clock cycles after
the last bit in the synchronous character is received.
Character assembly begins on the rising edge of the
receive clock immediately preceding the activation
of /SYNC.
In internal sync mode '(Monosync and Bisync) with the
crystal oscillator option not selected, this line acts as
output and is active only during the part ofthe receive clock
cycle in which a synchronous cllaracter is recognized
(regardless of character boundaries). In SDLC mode, this
pin acts as an output and is valid on receipt of a flag

RxD

In, Active 1

Receive Data. This input signal receives serial data at
standard TTL levels.

/RTxC

In, Active 0

Receiverrransmit clock. This pin can be programmed 'in
several different modes of operation. /RTxC may supply
the receive clock, the transmit clock, the clock for the Baud
Rate Generator, or the clock for the Digital Phase-Locked
Loop. This pin can also be programmed for use with the
/SYNC pin as a crystal OSCillator The receive clocks can be
1, 16,32, or 64 times the data transfer rate in Asynchronous
mode.

376

see SIGNALS (Continued)
Pin Name

Pin Number

Input/Output, 3-State

Function

/TRxC

1/0, Active 0

Transmit/Receive Clock. This pin can be programmed in
several different mO.des of operation ./TRxC can supply the
receive clock or the transmit clock in the input mode. Also,
it can supply the output of the Digital Phase-Locked Loop,
the crystal oscillator, the Baud Rate Generator, or the
transmit clock in the output mode.

TxD

Ou\, Active 1

Transmit Data. This Output signal transmits serial data at
standard TTL level.

IDTRI/REQ

Ou\, Active 0

Data Terminal ReadylRequest. This output follows the state
programmed into the DTR bit. It can also be used as
general purpose output or as Request line for a DMA
controller

IRTS

Out, Active 0

Request To Send. When the RTS bit in Write Register 5 is
set, the IRTS signal goes kJw. When the RTS bit is reset in
Asynchronous mode and auto enable is on, the signal
goes high after the transmitter is empty. In synchronous
mode or in Asynchronous mode, with Auto Enable off, the
IRTS pin follows the state of the RTS bit. This pin can be
used as a general purpose output.

ICTS

In, Active 0

Clear To Send. If this pin is programmed as auto enable,
a "0" on the input enables the transmitter. If not programmed as Auto Enable, it may be used as a general
purpose input. This input is Schmitt-trigger buffered to
accommodate inputs with slow rise times. The SCC detects pulses on this input and can interruptthe CPU on both
logic level transitions.

lOCO

In, Active 0

Data Carrier Detect. This pin functions as receiver enable
if it is programmed for auto enable. Otherwise, it may be
used as a general purpose input. This input is Schmitttrigger buffered to accommodate slow rise-time inputs
The SCC detects pulses on this input and can interrupt the
CPU on both logic level transitions.

377

PIA/CTC SIGNALS
Pin Name

Pin NlJmber

Input/Output, 3-State

Function

PIA 17-PIA 14

35-38

I/O

Port 1 Data 7-Port 1 Data 4 or CTC zcrr03 - zcrroo.
These lines can be configured as inputs or outputs on a
bit -by-bit basis. Also, under program control, these bits
become Z80 CTC's ZC/T03 - ZC/TOO, and in either timer
or counter mode, pulses are output when the down counter
has reached zero. On reset, these signals function as
PIA17-14 and are inputs.

PIA13-PIA10

31-34

I/O

Port 1 Data3-Port1 DataOorCTCCLKlTRG3-0. These lines
can be configured as inputs or outputs on a bit by bit basis
Also, under program control, these bits become Z80
CTC's CLK/TRG3-CLK/TRGO, and correspond to four
Counter/Timer Channels. In the counter mode, each active
edge causes the downcounter to decrement by one. In
timer mode, an active edge starts the timer It is program
selectable whether the active edge is rising or falling. On
reset, these signals are set to PIA 13-1 0 as inputs.

PIA27-20

41-48

I/O

Port 2 Data. These lines are configured as inputs or outputs on a bit-by-bit basis. On reset, they are inputs.

SYSTEM CONTROL SIGNALS
Pin Name

Pin Number

Input/Output. 3-State

Function

Out, Active 1

Status. This signal is used with the IM1 and IHAL T output
10 decode the status of the CPU machine cycle. Note that
the /M 1 output is affected by the status of the M 1E bit in the
OMCR register. The following table shows the status while
M1E=I.

ST IHALT

IM1
0

0
0
1

378

X
0
0

1
0
1

Operation
CPU Operation
(1st Op-code fetch)
CPU Operation
(2nd and 3rd Op-code fetch)
CPU Operation
(MC other than Op-C'ode letch)
DMA operation
HALT mode
SLEEP mode
(Inct. System STOP mode)

SYSTEM CONTROL SIGNALS (Continued)
Pin Name

Pin Number

Input/Output, 308tate

Function

In, Active 1

Interrupt enable input signal. lEI is used with the lEO talorm
a priority daisy chain when there is more than one interruptdriven peripheral.

lEI

lEO

Out, Active 1

The interrupt enable output signal. In the daisy-chain
interrupt control, lEO controls the interrupt of external
peripherals. lEO is active when lEI is "1" and the CPU-iS not
servicing an interrupt from the on-chip peripherals.

/ROMCS

Out, Active 0

ROM Chip select. Used to access ROM. Refer to "Functional Description" on chip select signals for further explanation.

/RAMCS

Out, Active 0

RAM Chip Select. Used to access RAM. Refer to "Functional Description" on chip select signals for further explanation.

/RESET

In, Active 0

Reset signal./RESET signal is used lor initializing the MPU
and other devices in the system. It must be kept in the
active state for a period of at least 3 system clock cycles.

EXTAL

In, Active 1

Crystal oscillator connecting terminal. A parallel resonant
crystal is recommended. If an external clock source is
used as the input to the Z180 Clock Oscillator unit, supply
the clock into this terminal.

XTAL

Out

Crystal oscillator connecting terminal.

PHI

Out, Active 1

System Clock. Single-phase clock output from Z181 MPU

Out, Active 1

Enable Clock. Synchronous Machine cycle clock output
during a bus transaction.

TEST

Out

Test pin. Used in the open state.

Vee

39,82

Power Supply. +5 Volts

Vss

18,40,59,
63, 92

Power Supply. 0 Volts

379

FUNCTIONAL DESCRIPTION
Functionally, the on-chip Z181 MPU, SCC, and CTC are
the same as the discrete devices (Figure 1). Therefore, for
a detailed description of each individual unit, refer to the

Product Specification!Technical Manual of each discrete
product. The following subsections describe each individual functional unit of the SAC.

Z181 MPU
This unit provides all the capabilities and pins of the Zilog
Z180 MPU. Figure 3 shows the Z181 MPU block diagram.
This allows 100% software compatibility with existing Z180
(and Z80) software. Note that the on-chip I/O address

A1SfTOUT

TxS
RxSIICTS
CKS

should not be relocated to the I/O address (from OCOh to
OFFh) to avoid address conflicts. The following is an
overview of the major function'll units of the Z 181.

Timing
Generator

CPU

16-Bit
Programmable
Reload Timers
(2)

IDREQ1
fTEND

Clocked
Serial 110
Port

TxAO
CKAO IDREQO
RxAO
IRTSO

ICTSO

'"
J

!Xl

IDCDO

'tl

::l

TxA1

MMU

CKA1 fTENDO
RxA1

A19-AO

D7-DO

Figure 3. Z181 MPU Block Diagram

380

~-----

---~~-----

t
FUNCTIONAL DESCRIPTION (Continued)
Z181 CPU
The Z181 CPU has 100% software compatibility with the
ZOO CPU. In addition. the Z181 CPU has the following
features:
Faster execution speed. The Z181 CPU is "fine tuned"
making execution speed. on average. 10% to 20% faster
than the ZOO CPU.
Enhanced DRAM Refresh Circuit. Z181 CPU's DRAM refresh circuit does periodic refresh and generates an
8bit refresh address. It can be disabled or the refresh period
adjusted. via software control.
Enhanced Insiruction Set. The l181 CPU has seven additional instructions to those of the ZOO CPU which include
the MLT (Multiply) instruction.
'
HALT and Low Power Modes of Operation. The Z181 CPU
has HALT and low power modes of operation. which are
ideal for the applications requiring low power consumption
like battery operated portable terminals.
System Stop Mode. When the Z181 SAC is in SYSTEM
STOP mode. it is only the Z181 MPU which is in STOP
mode. The on-chip CTC and SCC continue their normal
operation.
Instruction Set. The instruction set of the Z181 CPU is
identical to the Z180. For more details about each transactIon. please refer to the Data Sheet[fechnical Manual for
the Z1OO/Z80 CPU.
Z181 CPU Basic Operation
Z181 CPU's basic operation consists of the following
events. These are identical to the Z100 MPU. For more
details about each operation. please refer to the Data
'Sheet/Technical manual for the Z1OO.
•

Operation code fetch cycle.

•

Memory Read/Write operation.

•

InpuVOutput operation.

•

Bus requesVacknowledge operation.

•

Maskable interrupt request operation.

•

Trap and Non-Maskable interrupt request operation.

•

HALT and low power modes of operation.

•

Reset Operation.

Memory Management Unit (MMU)
The Memory Management Unit (MMU) allows the user to
"map" the memory used by the CPU (64K bytes of logical
addressing space) into 1M bytes of physical addressing
spa,ce. The organization of the MMU allows object code
compatibility with the Z80 CPU while offering access to an
extended memory space. This is accomplished by using
an effective "common area-banked area" scheme.
DMA Controller
The Z181 MPU has two DMA controllers. Each DMA
~ontroller provides high-speed data transfers beiween
memory and I/O devices. Transfer operations supported
.are memory to memory. memory to/from I/O. and I/O to
I/O. Tral)sfer modes supported are request. burst. and
cycle steal. The DMA can access the full 1M bytes addressing range with a block length up to 64K bytes and can
cross over 64K boundaries.
Asynchronous Serial Communication Interface (ASCI)
This unit provides two individual full-duplex UARTs. Each
channel includes a programmable baud rate generator
and modem control signals The ASCI channels also
support a multirJrocessor communication format.
Programmable Reload Timer (PR f)
The Z181 MPU has two separate Programmable Reload
Timers. each containing a 16-bit counter (timer) and count
reload register. The time base for the counters is system
clock divided by 20. PRT channel 1 provides an optional
output to allow for waveform generation.
Clocked Serial 110 (CSI/O)
The CSI/O channel provides a half-duplex serial transmitter and receiver. This channel can be used for simple highspeed data connection to another CPU or MPU.
Programmable Wait State Generator
To ease interfacing with slow memory and I/O devices. the
Z181 MPU unit has a programmable wait state generator.
Byprogramming the DMA/WAI r Control Register(DCNTL).
up to three wait states are automatically inserted in memory and I/O cycles. This unit also inserts wait states during
on-chip DMA transactions

Z85C30 Serial Communication Controller Logic Unit
This logic'unit provides the user with a multi-protocol serial
I/O channel that is completely compatible with the two
. - channel Z85C30 see with the following exceptions

381

•
Their' basic functions as serial-to-parallel and parallel-toserial converters can be programmed by the CPU for a
broad range of serial communication'! applications. This

Baud Rate
Generator

logic unit is capable of supporting all common asynchronous and synchronous protocols (Monosync, Bisync, and
SDLC/HDLC, byte or bit oriented - Figure 4).

1/1.-------.
1'.--------.

} Serial Data
} Channel Clocks
{SYNC

Internal
Control

10 X 19

Channel
Registers

'--_ _ _..r--- /Wait
Modem, DMA,
} or Other
Controls

Interrupt {
Control
Lines

Interrupt
Control
Logic

Figure 4.

see Block Diagram

On the discrete version of the SCC (dual channel version),
there are two registers shared between channels A and B,
and two registers whose functions are different by channel. These are: WR2, WR9(shared registers), and RR2 and
RR3 (different functionality).
Following are the differences in functionality:
•

RR2 - Returns Unmodified Vector or modified vector
depends on the status of "VIS" (Vector Include Status)
bit in WR9.

•

RR3 - Returns IP status (Ch.A side).

•

WR9 - Ch.B Software Reset command has no effect.

The PCLK for the SCC is connected to PHI (System clock),
the /INT signal is connected to /INTO signal internally
(requires external pull-up resistor) and SCC is reset when
/RESET input becomes active Interrupt from the SCC is
handled via Mode 2 interrupt. During the interrupt acknowledge cycle, the on-chip SCC interface circuit inserts.
two wait states automatically

382

Z84C30 CounterlTimer Logic Unit
This logic unit provides the user with four individual 8-bit
Counter/Timer Channels that are compatible with the
Z84C30 CTC (Figure 5). The Counter/Timers are programmed by the CPU for a broad range of counting and
timing applications. Typical applications include 'event
counting, interrupt and interval counting, and serial baud
rate clock generation.
Each of the Counter/Timer Channels, designated Channels 0-3, have an 8-bit prescaler (when used in timer
mode) and its own 8-bit counter to provide a wide range of
count resolution. Eac.h of the channels have their own
Clock/Trigger input to quantify the counting process and
an output to indicate zero crossing/timeout conditions
These Signals are multiplexed with the Parallel Interface
Adapter 1 (PIA 1). With only one interrupt vector programmed into the logic unit, each channel can generate a
unique interrupt vector in response to the interrupt acknowledge cycle.

FUNCTIONAL DESCRIPTION (Continued)

Internal
Control
Logic

Data
Control

CPU
BUS

Interrupt
Logic

110

liNT
lEI
lEO

ZCITO

}

CLKlTRG

Mutiplexed
with PIA1

{RESET
}

Figure 5. CTC Block Diagram

Parallel Interface Adapter (PIA)
The SAC has two 8-bit Parallel Interface Adapter (PIA)
Ports. The ports are referred to as PIA 1 and PIA2. Each port
has two associated control registers; a Data Register and
a register to determine each bit's direction (input or output). PIA 1 is multiplexed with the CTC I/O pins. When the
CTCI/O feature is selected, the CTC I/O functions override
the PIA 1 feature Mode Selection is made through the
System Configuration Register (Address. EDh, Bit DO).
PIA 1 has Schmitt-trigger inputs to have a better noise
margin. These ports are inputs after reset.

C1
XTAL •
Crystal
Inputs
EXTAL •

I
I

c=:::J
C2

Clock Generator
The SAC uses the Z181 MPU's on-chip clock generator to
supply system clock. The required clock is easily generated by connecting a crystal to the external terminals
(XTAL, EXTAL). The clock output runs at half the crystal
frequency. The system clock inputs of the SCC and the
CTC are internally connected to the PHI output of the
Z181 MPU.

Figure 6. Circuit Configuration For Crystal

383

Recommended characteristics of the crystal and the values for the capacitor are as follows (the values will change
with crystal fr9(!uency).

Type-of crystal: Fundamental, parallel type crystal

These two signals f,)~e geoerate.d by decoding address
lil/es A 19-A 12. Note that glitches may be observed on the
/RAMCS and fROMCS signals because the address decoding logiC decodes only A 19-A 12, without any control
signals.

(AT cut is recommended).

Frequency tolerance: Application dependent.
CL, Load capacitance: Approximately 22 pf
(acceptable range is 20-30 pf)

Rs, equivalent-series resistance: s; 30 Ohms
Drive level:10mW (for s; 10 MHz crystal) 5mW
(for ~ 10 MHz crystal)

Bit 05 of the System Configuration Register allows the
option of disabling the /ROMCS signal This feature is used
in systems which, for example, have a shadow RAM.
However, prior to disabling the /ROMCS signal, the ROMBFl
and RAMLBR registers must be re-initialized from their
. default values.
For more detailS, please refer to "Programming section"

CIN = COIJT = 15 - 22pF.
ROM I;:mulator Mode

Chip Select Signals
The SAC has two chip select (fRAMCS, fROMCS) pins.
/ROMCS is the chip select signal for ROM and fRAMCS is
the chip select Signal for RAM. The boundary value for
each chip select signal is 8 bits wide allowing all memory
accesses with addresses less than or equal to this boundary value. This causes assertion of the corresponding /CS
pin. These features are controlled via the RAM upper
boundary address register (I/O address EAh), RAM lower
boundary address register (I/O address EBh) and ROM
upper boundary address register (I/O address ECh).

To ease development, the SAC has a mode to support
"FlOM emulator" development systems. In this mode, a
read data from on-chip registers (except Z181 MPU onchip registers) are available (data bus direction set to
output) to make data visible from the outside, so that a
ROM EmulatorlLogic Analyzer can monitor internal.transactions. Otherwise, a read from an internal transaction is
not available to the outside (data bus direction set to Hi-Z
status). Mode selection is made through the 01 bit in the
System Configuration Register (110 Addres~: EOh).

PROGRAMMING
The following subsections explain and define the parameters for I/O Address assignments, I/O Control Register
Addresses and all pertinent Timing parameters.

1/0 Address Assignment
The SAC has 78 internal 8-bit registers to control on-chip
peripherals and features. Sixty-four registers out of 78
registers are occupied by the Z181 MPU control registers;

384

two for SCC control registers, four for PIA control registers,
four for the Counter/Timer, three for RAM/ROM configuration (memory address boundaries) and one for SAC's
system control. The SAC's I/O addresses are listed in
Table 1. Thes~ registers are assigned in the SAC's I/O
addressing space and the I/O addresses are fully decoded from A7-AO and have no image

PROGRAMMING (Continued)
Table 1. 1/0 Control Register Address
Address

OOh
t03Fh
EOh
E1h

Z181 MPU Control Registers
(Relocatable to 040h-07Fh, or 080h-OBFh)
PIA 1 Data Direction Register (P1 DDR)
PIA 1 Data Port (P1 DP)

E2h
E3h
E4h
E5h

PIA2 Data Direction Register (P2DDR)
PIA2 Data Register (P2DP)
CTC Channel 0 Control Register (CTCO)
CTC Channel 1 Control Register (CTC1)

E6h
E7h
E8h
E9h

CTC Chllnnel 2 Control Register (CTC2)
CTC Channel 3 Control Register (CTC3)
SCC Control Register (SCCCR)
SCC Data Register (SCCDR)

EAh

RAM Upper Boundary Address Register
(RAMUBR)
RAM Lower Boundary Address Register
(RAMLBR)

Z181 MPU Control Registers
The If0 address for these registers can be relocated in 64
byte boundaries by programming of the I/O Control Register (Address xx 111111 b).
Do not relocate tllese registers to address from OCOh since
this will cause an overlap of the Z180 registers and tile 16
registers of the Z181 (address OEOh to OEFh).
Also, the OMCR register (Address: xx111101b) has to be
pmgrammed as OxOxxxxxb (x: don't care) as a part of the
initialization procedure. The M 1E bit (Bit 07) of this register
must be programmed as 0 or the interrupt daisy chain is
corrupted. The flOC bit (Bit 05) of this register is programmed as 0 so that the timing of tt16 fRO and flORQ
signals are compatible with Z80 peripherals.
For detailed information, referto the Z180 Technical Manual.

EBh

ECh
EDh
EEh
EFh

ROM Address Boundary Register (ROMBR)
System Configuration Register (SCR)
Reserved
Reserved

385

ASCI CHANNELS CONTROL REGISTERS
CNTLAO
Bit

AddrOOh
MPBRI
MOD2 MOD1 MODO
EFR

MPE

RIW

RlW

RIW

R/W

Upon RESET

RIW
-

IRTSO

- - -r- -r- -r-

0
0
0
1
1
1
1

I
0
0
1
1
0
0
1
1

I MODE Selection

0 Start + 7-Bit Data + 1 Stop
1 Start + 7-Bit Data + 2 Stop
0 Start + 7-Bit Data + Parity + 1 Stop
1 Start + 7-Bit Data + Parity + 2 Stop

0 Start + a-Bit Data + 1 Stop
1 Start + a-Bit Data + 2 Stop
0 Start + a-Bit Data + Parity + 1 Stop
1 Start + a-Bit Data + Parity + 2 Stop
Read - Multiprocessor Bit Receive
Write - Error Flag Reset
Request To Send
Transmit Enable
Receive Enable
Multiprocessor Enable

Figure 7.

~SCI

Control Register A (Ch. 0)

Addr 01h

CNTLA1
Bit
Upon RESET

RIW

CKA1D MPBRI MOD2 MOD1 MODO

MPE

RIW

-r--

-r-- -

r-- -

EFR

I I I

0
0
0
1
1
1
1

0
0
1
1

0
1
0
1
0
1
0
1

MOD E Selection
Start + 7-Bit Data
Start + 7-Bit Data
Start + 7 -Bit Data
start + 7 -Bit Data
Start + a-Bit Data
Start + B-Bit Data
start + B-Bit Data
Start + B-Bit Data

+ 1 Stop
+ 2 Stop
+ Parity + 1 Stop
+ Parity + 2 Stop
+ 1 Stop
+ 2 Stop
+ Parity + 1 Stop ,
+ Parity + 2 Stop

Read - MuHiprocessor Bit Receive
Write - Error Flag Reset
CKA 1 Disable
Transmit Enable
Receive Enable
Multiprocessor Enable

Figure 8. ASCI Control Register A (CI1. 1)

386

ASCI CHANNELS CONTROL REGISTERS (Continued)
CNTLBO

Addr 02h

Bit

MPBT

Upon Reset

Invalid

RIW

leTS!

PEO

----TTT

SS2

SSl

' 1
RIW

SSO

RIW

Clock Source and Speed Select
Divide Ratio
Parity Even or Odd
Clear To Send/Prescale
Multiprocessor
Multiprocessor Bit Transmit

ICTS· Depending on the condition of ICTS pin.
PS • Cleared to O.

General
Divide Ratio

ps=o

PS = 1

(Divide Ratio"; 10)

(Divide Ratio = 30)

SS,2, 1,0

DR = 0 (x16)

DR = 1 (x64)

DR = 0 (x16)

000

001
010
011
100
101
110

0+ 160
0+ 320
0+ 640
0+ 1280
0+2560
0+5120
0+10240

0+640
0+ 1280
0+ 2580
0+5120
0+10240
0+20480
0.+ 40960

0+ 480
0+ 960
0+1920
0+ 3840
0+ 7680
0+ 15360
0+ 30720

111

External Clock (Frequency < 0 + 40)

.DR = 1 (x64)

0+1920
0+ 3840
0+7680
0+15360
0+ 30720
0+61440
0+ 122880

Figure 9. ASCI Control Register B (Ch. 0)

387

CNTLBl
Bit
Upon Reset

RJW

Addr03h

MPBT . MP

leTSI

PEO

SS2

SSl

Invalid

RJW

RIW

----TTT

SSO

Clock Source and Speed Select
Divide Ratio
Parity Even or Odd
Read· S1atus of ICTS pin
Write· Select PS
Multiprocessor
Multiprocessor Bit Transmit

General
Divide Ratio

P8=0
(Divide Ratio = 10)

88,2,1,0

DR = 0 (x16)

DR = 1 (x64)

DR = 0 (x16)

DR = 1 (x64)

000
001
010
011
100
101
110

0+ 160
0+ 320
0+ 640
0+ 1280
0+ 2560
0+ 5120
0+10240

0+ 640
0+ 1280
0+ 2580
0+5120
0+ 10240
0+ 20480
0+ 40960

0+
0+
0+
0+
0+
0+
0+

0+ 1920
0+ 3840
0+7680
0+ 15360
0+ 30720
0+ 61440
0+122880

111

External Clock (Frequency < 0 + 40)

P8 = 1
(Divide Ratio = 30)

Figure 10. ASCI Control Register 8 (CI1. 1)

388

480
960
1920
3840
7680
15360
30720

ASCI CHANNELS CONTROL REGISTERS (Continued)
STATO
Bit

Addr04h

RDRF CVRN

RIE

IDCoo TORE

t' . tt

Upon Reset

RIW

-~-----~----

TIE
0
RIW

Transmit Interrupt Enable
Transmit Data Register
Empty
Data Carrier Detect
Receive Interrup~ Enable
Framing Error
Parity Error
Over Run Error
Receive DIlIa Register Full

t
tt

IDCoo - Depending on the condition of (DCCO Pin.

ICTSo Pin

L
H

TORE

1
0

Figure 11. ASCI Status Register

STAT1
Bit

Addr05h

RDRF CVRN

RIE

CTS1E TORE

Upon Reset

RIW

-----~-----~

TIE

RIW

Transmit l',lterrupt Enable
Transmit Data Register
Empty

(CTS1 Enable
Receive Interrupt Enable
F'lImlng Error
Parity Error

•

Over Run Error
Receive Data Register Full

Figure 12. ASCI Status Register(Ch 1)

389

TORO

TSRO
Addr OSh

Write Only

Read Only

I 71 s 151 41312111 01

Addr 08h

Ixlxlxlxlxlxlxlxl

Transmit Data

Figure 13. ASCI Transmit Data Register (Ch, 0)

Received Data

Figure 15. ASCI Receive Data Register (Ch, 0)

TOR1

TSR1

Write Only

Addr 07h

Read Only

171s15141312111 0 1

Addr 09h

Ixlxlxlxlxlxlxlxl

Transmit

Dat~

Figure 14. ASCI Transmit Data Register (Ch, 1)

Received Data

Figure 16. ASCI Receive Data Register (Ch 1)

CSI/O REGISTERS

Bit
Upon Reset
RIW

CNTR
EF

AddrOAh

EIE

SS2

RfW

RIW

RfW

-~--TT

SSl

SSO

Speed Select

Transmit Enable
Receive Enable
End Interrupt Enable
End Flag

882,1,0

Baud Rate

882,1,0

Baud Rate

000
001
010
011

0+
0+
0+
0+

100
101
110
111

0+ 320
0+ 640
0+1280

20
40
80
100

•

Figure 17. GSI/O Control Register

390

External Clock
(Frequency < 0 + 20)

CSI/O REGISTERS (Continued)
TRDR
ReadIWrlte

Addr OBh

17161514131211101
1

Read - Received Data
Write - Transmit Data

Figure 18. CSI/O Transmit/Receive Data Register

TIMER REGISTERS
Timer Data Registers

TMDROl
Read/Write

TMDROH
ReadlWrlte

Addr OCh

17161514131211101

When Read. read Data Register L
before reading Data Register H.

Figure 19. Timer 0 Data Register L

Figure 21. Timer 0 Data Register H
TMDR1H
ReadlWrite

TMDR1L
ReadlWrlte

Addr ODh

115 114113112111110191 8 1

Addr 15h

11511411311211111019181

Addr 14h

17161514131211101

When Read. read Data Register L
before reading Data Register H.

Figure 22. Timer 1 Data Register H

Figure 20. Timer 1 Data Register L

TIMER RELOAD REGISTERS

RLDROL
ReadIWrlte

RLDR1L '
ReadIWrlte

Addr OEh

17161514131211101

Addr 16h

17161514131211101
Figure 24. Timer 1 Reload Register L

Figure 23. Timer 0 Reload Register L

391
~~~

_____

~~_"""""""·',"""f,~_-,-~_·-r_--r-"'----··

___

••••

'm' •• -

_ _ _ _ ........ , .............. ' ..

_~~

__
" ..._ _"""
_......
__

M~:;;:4A~""_,.......,.~_~_

RLDROH
ReadIWrite

RLDR1H
ReadIWrite

Addr OFh

115114113112111110191sl

Addr 17h

11511411311211111019181
Figure 26. Timer 1 Reload Register H

Figure 25. Timer 0 Reload Register H

TIMER CONTROL REGISTER
TCR

Addrl0h

TIF1

TIFO

TIEl

TIEO

TOCl

Upon Reset

RIW

Bit

TOCO TDE1

TDEO

. Timer Down Count Enable 1,0
Timer Output Control 1,0
Timer Interrupt Enable 1,0
Timer Interrupt Flag 1,0

TOC1,O
00
01
10
11

A1SffOUT
Inhibited
Toggle
0
1

Figure 27. Timer Control Register

FREE RUNNING COUNTER

FRC
Read Only

Addr lSh

17161514131211101
Figure 28. Free Running Counter

392

DMA REGISTERS
SAROL
ReadIWrite
SA7

DAROL
Read/Wrlte
DA7

Addr20h
SAO

I I

I I
SAROH
ReadIWrite
SA15

Addr24h
DAB

SAROB
ReadIWrite

DAROB
Read/Wrlte

Addr22h
SA19
SA16

I -I -I -I -I I

DA19

A19. A18.

x
x
x
x

A17.

A16

0
0
1
1

0
1
0
1

Addr 25h
DA16

'-1-1-1-1

Bits 0-2 (3) are used for DAROB

Bits 0-2 (3) are used for SAROB

x
x
x
x

DAROH
ReadIWrite
DA15

Addr 21h
SAS

I I

Addr 23h
DAO

DMA Transfer Request
IDREaO (external)
RDRO (ASCIO)
TORO (ASCI1)
Not Used

Figure 29. DMA 0 Source Address Registers

A19. A18.

x
x
x
x

A17.

A16

0
0
1
1

0
1
0
1

DMA Transfer Request
IDREOO (external)
RDRO (ASCIO)
TDRO (ASCI1)
Not Used

Figure 30. DMA 0 Destination Address Registers

393

BCROt.
ReadIWriie
BC7

Addt 2Sh
BCO

I· 1 1 "I 1 1 1 I

BCROH
ReadIWrite
BC1S

I 1 I I

Addt27h
BCS

I I I I

Figure 31. DMA 0 Byte Counter Registers

MAR1l
ReadlWrlte
MA7

I I I

Addr2Sh

MAO

I I I I I

. MAR1H
ReadIWrlte
MA1S

1 1

Addt·29h
. MAS

I I

MAR1B
ReadlWrite
MA19

1 I

Addt 2Ah
MA1S

I - I -I - I -I II I I
Figure 32. DMA 1 Memory Address Registers

394

IAR1L
ReadlWrite
IAT

I 1 I
IAR1H
ReadlWrite
IA1S

I 1

I I

Addr2Bh
IAQ

1 1 1 I
Addr2Ch
lAS

I 1

I I

Figure 33. DMA 1 110 ACldress Registers

BCR1L
ReadIWtite
BC7

I I I I
BCR1H
ReadIWtite
BC1S

I I I I

Addt2Eh
BCO

I I I I
Addt2Fh·
BCS

I I I I

Figure 34. DMA 1 Byte Count Registers

DMA REGISTERS (Continued)
DSTAT
Bit
Upon Reset

RIW

Addr30h

DE1

DEO

RIW

OlEO

RIW

/DWE1 /DWEO DIE1

DIME
0
R

DMA Master Enable
DMA Inllerrupt Enable 1, 0
DMA Enable Bit Write Enable 1, 0
DMA Eneble Ch 1, 0

Figure 35. DMA Status Register

DMODE

Addr31h

Bit

DM1

DMO

SM1

SMO

MMOD

Upon Reset

RIW

I.
DM1,O, Destination

00
01
10
11

M
M
M
I/O

MemOry MODE Select
Ch 0 Source Mode 1, 0

Ch 0 Destination Mode 1, 0

Address

SM1,O

Source

Address

DARO+1
DARO-1
DARO Fixed
DARO Fixed

00
01
10
11

M
M
M
I/O

SARO+1
SARO-1
SAROFixed
SARO Fixed

MMOD

Mode

0
1

Cycle Steal Mode
Burst Mode

Figure 36. DMA Mode Registers

395

DCNTL
Btt
Up<>n Reset

RftN

Addr32h

MWl1

MWIO

IWl1

IWIO

DMS1

DMSO

DIM1

RftN

RN'{

RftN

RNY

RftN

RNY

DIMO

DMA Ch 1 1/0 Memory
Mode Select
IDREQi Select, i = 1, 0
1/0 Wait Insertion
Memory Wait Insertion

MW11,0

No. of Watt States

IWI1, 0

No. of Wan States

00
01
10
11

0
1
2
3

00
01
10
11

0
2
3

DMSi

sense

Edge Sense
Level Sense

DM1,O

Transfer Mode

00
·01
10

M -1/0
M -1/0
I/O-M
IIO-M

Address Increment/Decrement
MAR1+1
MAR1-1
IAR1 Fixed
IAR1 Fixed

IAR1 Fixed
IAR1 Fixed
MAR1+1
MAR1-1

Figure 37. DMAIWAIT Control Register

396

MMU REGISTERS

CBR
Bit
Upon Resel

ANI

Addr 38h

CB7

CB6

CBS

CB4

CB3

CB2

CBl

RIW

ANI

CBO

MMU Conmon Base
Register

Figure 38. MMU Common Base Register

BBR
Bit
Upon Reset

RIW

Addr39h

BB7

BB6

BB5

BB4

BB3

BB2

BBl

BBO

RIW

MMU Bank Base Register

Figure 39. MMU Bank Base Register

CBAR
Bit
UponResel

RIW

Addr3Ah

CA3

CA2

CAl

RIW

CAO

BA3

BA2

BAl

BAO

MMU Bank Area Register
MMU Common Area Register

Figure 40. MMU Common/Bank Area Register

397

SYSTEM CONTROL REGISTERS

--:: I~ I! I~ I

Addr33h

I I I I I
0

Interrupt Vector Low

Figure 41. Interrupt Vector Low Register

ITC

Bit
Upon Reset

RIW

Addr34h

TRAP

UFO

ITE2

ITE1

RIW

\TEO

liNT Enable 2, 1, 0
Undefined Fetch Object
TRAP

Figure 42. INT/TRAP Control Registe~

RCR

Bit
Upon Reset

RIW

REFE REFW
1

RIW

.
1

Addr36h

CYC1

RIW

CYCO

Cycle Select
Refresh Wait State
Refresh Enable

CYC1,O

Interval of Refresh Cycle

00
01
10
11

10 states
20 states
40 states
80 states

Figure 43. Refresh Control Register

398

SYSTEM CONTROL REGISTERS (Continued) .

OMCR

Addr3Eh

I/O Compatibility
1M1 Temporary Enable
1M1 Enable
Note: This register has to be programmed as OxOxxxxxb{x:don't care) as a part of Initialization,

Figure 44, Operation Mode Control Register

ICR

8ft
Upon Reset
RIW

IOA7

Addr3Fh

10M 10STP

RIW

I/O Stop
I/O Address
Combination of 11
Is reserved

Figure 45, 1/0 Control Register

399

eTC CONTROL REGISTERS
Channel Control Word
This word sets the operating modes and parameters as
described below. Bit DO must be a "1" to indicate that this
is a Control Word (Figure 46).

For more detailed information, refer to the CTC Technical
Manual:
.

Addr: E4h (Ch 0)
E5h (Ch 1)
E6h(Ch2)
E7h (Ch3)

-r-

~-r--r--

Control or Vector
Vector
1 Control Word

Reset

Continued Operation

1 Software Reset
Time Constant
No Time Constant Follows
1 Time Constant Follows

Time Trigger·
Automatic Trigger When
Time Constant is Loaded
1 CLKlTRG Pulse Starts Timer

CLKlTRG Edge Selection
Selects Failing Edge
1 Selects Rising Edge

Prescaler Value·
1 Value of 256
Value of 16

Mode
o Selects Timer Mode
1 Selects Counter Mode
Interrupt
1 Enables Interrupt
Disables Interrupt

• Timer Mode Only

Figure 46. CTC Channel Control Word

This register has the following fields:

Bit 04. Clock/rrigger Edge Selector. This bit selects the
active edge of the CLK[TRG input pulses.

Bit 07. Interrupt Enable. This bit enables the interrupt logic
so that an internallNT is generated at zero count Interrupts
are programmed in either mode and may be enabled or
disabled at any time.

Bit 03. Timer Trigger. This bit selects the Irigger mode for
timer operation. Either automatic or external trigger may be
selected.

Bit 06. Mode Bit. This bit selects either Timer Mode or
Counter Mode.

Bit 02. Time Constant. This bit indicates that the next word
programmed is time constant data for the downcounter.

Bit 05. Prescaler Factor. This 'bit selects the prescaler
factor for use in the timer mode. Either divide-by-16 or
divide-by-?56 is available.

Bit 01. Software Reset. Wnting a "1" to thiS bit indicates a
software reset operation, which stops counting activities
until another time constant word is written.

400

eTC CONTROL REGISTERS (Continued)
Time Constant Word
Before a channel can start counting, it must receive a time
constant word. The time constant value may be anywhere
between 1 and 256, with "0" being accepted as a count of
256 (Figure 47).

Interrupt Vector Word
If one or more of the CTC channels have interrupt enabled,
then the Interrupt Vector Word is programmed. Only the
five most significant bits of this word are programmed, and
bit DO must be "0". Bits 02-Dl are automatically modified
by the CTC channels after responding with an interrupt
vector (Figure 48).
Addr: E4h

-r-r-r--~
TCO
TCl

TC2

Channel Identifier
(Automatically Inserted

TC4
!

Interrupt Veclor Word

1 Control Word

TC3

byCTC)

TC5
TC6

o
o

0
1
1 0
1 1

TC7

Channel 0
Channell
Channel2
Channel3

Supplied By User

Figure 47. CTC Time Constant Word
Figure 48. CTC In~errupt Vector Word

sec REGISTERS
For more detailed information, please refer to the Z8030/
Z8530 SCC Technical Manual.
Note:
The Address for the Control/Status Register is E8h. The
Address for the Data Register is E9h.

Read Registers
The SCC contains eight read registers. To read the contents of a register (rather than RRO). the program must first
initialize a pOinter to WRO In exactly the same manner as a
write operation The next I/O read cycle will place the
contents of the selected read registers onto the data bus
(Figure 49).

Table 2. SCC Read Registers
Bit

Description

Bit

Description

RRO

Transmit and Receive buffer status
and external status.
Special Receive Condition status.
Interrupt vector (modified if VIS Bit in WR9 is set).
Interrupt pending bits.
SOLC FIFO byte counter lower byte
(only when enabled).

RR7

SOLe FIFO byte count and status
(only when enabled).
Receive buffer.
Miscellanous status bits.
Lower byte of baud rate.
Upper byte of baud rate generator time constant.
External Status interrupt information.

RRl
RR2
RR3
RR6

RR8
RR10
RR12
RR13
RR15

401

Read Register 0

Read Register 2

Ax Character Available
Zero

--------~

Count

VO
Vl

Tx Buffer Empty

DCD

, InterJUpt

SynclHunt

Vector *

CTS

Tx UnderlUnlEOM

Break/Abort

* Modfiod HVIS bit In Write regi_ 910 ..t.
a)

Read Register 1

Read Register 3

Iml~I~I~loolool~lool

-,... -,... -'r-,..

All Sent
Residue Code 2
Residue Code

---~

Residue Code 0

Ext/Status IP

TxlP

Parity Error

Ax OverlUn Error

RxIP

CRClFraming Error

End of Frame (SDLC)

Figure 49.

402

o
o
o

see Read Register Bit Functions

see REGISTERS (Continued)
Read Register 6

Read Register 10

---'~

BOO

BCI
BC2
BC3

Loop Sending

BC4
B05

0-,

B06

Two Clocks Missing

BC7

One Clock MISsing

Can only be accessed if the SOLC FIFO enhancement
is enabled (WR15 bit 02 set to I)

e) SDLC FIFO Status and Byte Count (LSB)
Read Register 12

Read Register 7 *

1~loolool~looloolrnlool
rBe8
Be9

Bel 0
Bell

L...._ _ _ _ _ _ _ _ ,

- ,-

TOO
TCI
TC2
TC3

Lower Byte

TC4

of Time Constent

Bel2

TCS

Bel3

TC6

FDA: FIFO Available Stetus
I Stetus Reads from F1FO

TC7

FOS: FIFO Overflow Status
I FIFO Overflowed
Normal

o
*

Can only be accessed if the SDLC FIFO enhancement
is enabled (WR15 bit 02 set to I)

f) SDLC FIFO Status and Byte Count (MSB)

Figure 49. SCC Read Register Bit Functions (Continued)

403

Read Register 13

Read Register 15

IWI~I~I~IOOIOOI~IOOI

Iwloolool~loolool~lool

r-'

r-r--~T"L

-r

Tca

l'CS

ZeroCountlE

TC10
TC11
TC12

DCDIE

Upper Byte
of TIme Constant

Sync/Hunt IE

TC13

CTI1'E

TC14

Tx UndemmlEOM IE

TC15

Break/Abort IE

Figure 49.

see Read Register Bit

Write Registers
The SCC contains fifteen write registers that are programmed to configure the operating modes of the channel. With the exception of WRO, programming the write
registers is a two step operation, The first operation is a

Table 2.

Functions (Continued)

pointer written to WRO that points to the selected register.
The second operation is the actual control word that is
written into the register to configure the SCC channel
(Figure 50).

see Write Registers

Bit

Description

Bit

WRO
WR1
WR2

Register Pointers, various initialization commands
Transmit and Receive interrupt enables,
WAIT/OMA commands
Interrupt Vector

WR8
Transmit buffer
WR9
Master Interrupt control and reset commands
WR10 Miscellaneous transmit and receive control bits
WR11 Clock mode controls for receive and transmit

WR3
WR4
WR5
WR6
WR7

Receive parameters and control modes
Transmit and Receive modes and parameters
Transmit parameters and control modes
Sync Character or SDLC adcjress
Sync Character or SOLC Ilag

WR12
WR13
WR14
WR15

404

Description

Lower byte of baud rate generator
Upper byte of baud rate generator
Miscellaneous control bits
External status interrupt enable control

see REGISTERS (Continued)
Wrfte Register 0 (non-muftiplexed bus mode)

Write Register 1

Imlool;lwlool~I~lool

TTT
o 0 o
0
1
1

1
1
1

0
0
1

.' 1

1
0

i~!:}*

o
o
o

1
1
1
1

0
0
1
1

o
1
1

0
1

0
0
0
0

0
0

1
1
1
1

0
0

1
1

RegisterO
Register 1
Register2
Register3
Register4
Register 5
Register6

o
o
o

0
1

o
1

Ext Int Enable
Tx Int Enable
Parity is Special
Condition

0
1

Rx Int Disable
Rx Int On First Character or
Special Condition
Int On All Rx Characters or
Special Condition
Ax Int On Special Condition Only
WAIT/oMA Request
On ReceivellTransmft

IWAITIDMA Request
Function
WAIT/oMA Request
Enable

Null Code
1 Point High
0 Reset Ext/Status Interrupts
1 Send Abort (SOle)
0 . Enable Int on Next Rx Character
t Reset Tx Int Pending
0 Error Reset
1 Reset Highest IUS

NuilCode
Reset Rx CRC Checker
Reset Tx CRC Generator
Reset Tx UnderrunlEQM Latch

Wfth Point High Command

Write Register 2

Imlool~l;lool~I~lool

Tl!i=~
~V3
V4

Interrupt
Vector

V5
V6

Figure 50. Write Register Bit Functions

405

Wri~ Register 3

ill=L

1071061051041031021011 I,
DO

- - -I"" -I"" -

~.
,

AxEnable

Sync C~aracIer Lo~ Inhibit
, Address Seerot. Mode (SOLC)
Ax CRC Enable
Enter Hunt Mode
Auto E"ables

o
o
1
1

0
1
0
1

Ax 5 BitslCharatter
Ax 7 ails/Character
Ax 6 Bils/Chara¢ler
Ax 8 ails/Characler

Write Register 4

Write Register 5

Perity Enable

Tx CRC Enable

Perity EVEN//ooO

o
o
1
1

0
1
0
1

RTS
ISOLClCRC-16

Sync Modes Enable
1 Stop IlIVCharacler
1 112 Stop BlltllCharacler
2 Stop BlltllCharacler

8-81t Sync Character
16-Bit Sync Character
SOLe Mode (01111110 Flag)
External Sync Mode

TxEnable

Send Break

o
o
1
1

0
1
0
1

Tx 5 Bits(Or Less)/Cheracter
Tx 7 Bils/Character
Tx 6 Bils/Character
Tx 8 Bils/Character

OTR

o
o
1
1

0
1
0
1

XI Clock Mode
X16 Clock Mode
X32 Clock Mode
X64 Clock Mode

Figure SO. Write Register Bit Functions (Continued)

406

see REGISTERS (Continued)

Sync7
Syncl
Sync7
Sync3
AOR7
AOR7

Sync6
SyncO
Sync6
Sync2
AOR6
AOR6

Sync5
Sync5
Sync5
Syncl
ADR5
AOFl5

Sync4
Sync4
Sync4
SyncO
ADR4
AOR4

Sync3
Sync3
Sync3
1
AOR3

Sync2
Sync2
Sync2
1
ADR2

Sync 1
Sync 1
Syncl
1
AORI

SyncO
SyncO
SyncO
1
AORO

Monosync. 8 B~s
Monosync. 6 B~
Bisync. 16 B~
Bisync. 12 B~
SOLe
SOLe (Address Range)

Wrfte Register 7

Sync7
SyncS
Sync15
Syncll

Sync6
Sync4
Sync14
Syncl0
1

SyncS
Sync3
Sync13
Sync9
1

Sync4
Sync2
Sync12
Sync8
1

Sync3
Sync1
Syncll
Sync7

Sync2 Sync1
SyncO
x
Sync10 Sync9
Sync6 Sync5

SyncO

x
Sync8
Sync4

Monosync. 8 B~s
Monosync. 6 Bfts
Bisync. 16 Bits
Bisync. 12 B~
SOLe

Figure 50. Write Register Bit Functions (Continued)

407

Write Register 11

1071061051041031 021 O~I.0~,
'"'I-l T T
"T" ........ "T"'

"T"

~
~ ~

ITRxC Out '
ITRxC Out '
ITRxC Out '
ITRxC Out '

Xtal Output
TransrTit ClockOutput
BR Generator
OPLL Output

ITRxCOIi

I
I I
Pin
o o TransrTit Clock ,/RTxC
Pin
o 1 Trans~t CI::: : ITRxC
BR
Generator
Output
1
o
Trans~t CI
, OPLL Output
1 Transmt Clock
1

o
o o
1

NoReset
Reserved
Channel Reset A

Force ,Hardware Re~

o o
o
1
1
1 o

. Clock ,/RTxC Pin
ReceIve Clock ,ITRxC Pin
Receive ock . BR Generator Output
R&ee!ve ~ • OPLL Output

1 R9C9Ive

IRTxC XtaI//No Xtal

6 BitlIS Bit Sync
Loop Mode
TCO

AbortllFlag On Undenun

TCI
TC2

Markl/FIag Idle
Go Active On Poll

o
o
1
1

TC3

I
o NRZ
1

TC4

NRZI
FMl ffransition = 1)
FMO (Transition = 0)

TCS
TC6

TC7

CRC Preset 11/0

,
B't
Figure 50, Write Register
I Functions (Continued)

408

Lower Byte
lime Constant

see REGISTERS (Continued)
Write Register 13

Write Register 14

Iwl~I~I~looloolmlool

r- r~TLTC8

BR Generator Enable

~\TC9

BR Generator Source
IOTRiRequest Function

TCIO
TCII
TCI2

Auto Echo

Upper Byte of
lime Constant

Local Loopback

TCI3

0
0
0
0
1
1
1
I

TCI4
TCI5

0
0
I
I
0
0

0
I
0
I
0
I
0
I

NuJlCommand
Enter Search Mode
Reset Missing Clock
Disable OPLL
Set Source =BR Generator
Set Source =IRTxC
Set FM Mode
Set NRZI Mode

Write Register 15

Iwl~I~I~looloolmlool

-r-r r

r-~TL

0
Zero Count IE
SOLC FIFO Enable
OCOIE
SynclHuntlE
CTSIE
Tx Undenun/EOM IE
BreakiAborllE

Figure 50. Write Register Bit Functions (Continued)

409

PIA CONTROL REGISTERS
PIA 1 Data Direction Register (P1 DDR, I/O Address I:Oh),
PIA 1 Data Port (P1DP, I/O address E1 h), PIA2 Data Direction flegister (P2DDR', I/O 'Address E2h) and PIA2 Data
Register(P2DP,I/0 Address E3h) These four registers are

EOH

shown In Figures 51-54. Note that if the CTC/PIA bit in the
System Configuration Register is set to one, the CTC I/O
functions override the PIA 1 function, and programming of
P1DDR is ignored.

E2H

1 -Input
0- Output

1 - Input
0- Output

1 -Input
O· Output

0- Output

1 -Input

1 -Input
0- Output

1 -Input

0- Output

o -.Output

1 -Input
o -Output

0.- Output

1 -Input
0- Output

0- Output

1 -Input
1 -Input

1 -Input

1.-lnput
0- Output

0- Output

Figure 51, PIA 1 Data Direction Register

Figure 53, PIA 2 Data Direction Register

E1H

E3H

I 71615 1413 12 11 10I
1

17161514131211101
PIA 1
110 Data

PIA 2
1/0 Data

Figure 52, PIA 1 Data Register

Figure 54, PIA 2 Data Register

The Data Port is the register to/from the 8-bit parallel port.
At power on Reset. they are initialized to 1.

a" 1", the bit becomes an input, otllerwise it is an output On
reset, these registers are Initialized to 1, result'ing in all lines
being inputs

The Data Direction Register has eight control bits Individual bits specify each bit's direction. When the bit is set to

410

REGISTERS FOR SYSTEM CONFIGURATION
There are four registers to determine system configuration
with the Z181. These registers are: RAM upper boundary
address register (RAMUBR, I/O address EAh), RAM lower
boundary address register (RAMLBR, I/O address EBh),
ROM address boundary register (ROMBR, I/O address
ECh) and System Configuration Register (SCR, I/O address EOh).
ROM Address Boundary Register
(ROMBR, I/O Address ECh)
This register specifies the address range for the /ROMCS
signal. When accessed memory addresses are less than
or equal to the value programmed in this register, the
/ROMCS signal is asserted (Figure 55).
The A 18 signal from the CPU is obtained before it is
multiplexed with "TOUT". This signal can be forced to "1"
(inactive state) by setting Bit 05 of the System Confiquration Register, to allow the usertooverlay the RAM area over
the ROM area. At power-up reset. this register contains all
1s so that /ROMCS is asserted for all addresses
RAM Lower Boundary Address Register (RAMLBR, I/O
Address EBh) and RAM Upper Boundary Address
Register (RAMUBR, I/O Address EAh)
These two registers specify the address range for the
/RAMCS Signal. When accessed memory addresses are
less than or equal to the value programmed in the RAMUBR
and greater than or equal to the value programmed in the

EAH

RAMLBR, /RAMCS is asserted. (Figure 13) The A 18 signal
from the CPU is taken befpre it is multiplexed with "TOUT".
In the case that these register are programmed to overlap,
/ROMCS takes priority over /RAMCS (fROMCS is asserted
and /RAMCS is inactive).
Chip Select Signals are going active for the address range:
fROMes: (ROMBR);O: A 19-A 12;0: 0
/RAMCS: (RAMUBR) ;0: A 19-A 12 > (RAMLBR)
These registers are set to "FFh" at power-on Reset. and the
boundary addresses of ROM and RAM are tile following:
ROM lower boundary address
(fixed) = oooOOh
ROM upper boundary address
(ROMBR register) OFFFFFh

RAM lower boundary address
(RAMLBR register) OFFFFFh

RAM upper boundary address
(RAMUBR register) = OFFFFFh
Since /ROMCS takes priority over fRAMCS, the latter will
never be asserted until the value in the ROMBR and
RAMLBR registers are re-initialized to lower values.

EBH

,..
A12
A13
A14
A15
A16

A12
A13
A14
A15
A16

A17

A18

A19

Figure 55. RAM Upper Boundary Register

Figure 56. RAM Lower Boundary Register

411

ECH

A12
A13
A14
A15
A16
A17

Ala
A19

Figure 57. ROM Boundary Register

EDH

PIAlfCTIO
1 PIAl Functions as CTC's VO Pins
o PIAl Functions as If0 Port
Reserved - Program as 0
ROM Emulator Mode (REME)
1 Data Bus in ROM Emulator Mode
o Data Bus in Normal Mode
Reserved - Program as 0
Reserved - Program as 0
Disable fROMCS
1 fROMCS is Disabled
o fROMCS is Enabled
Daisy Chain Configuration
1 lEI Pin-CTC-SCC-IEO Pin
lEI Pin-SCC-CTC-IEO Pin

. Reserved - Program as 0

Figure 58. System Configuration Register

412

REGISTERS FOR SYSTEM CONFIGURATION (Continued)
System Configuration Register (I/O address EDh)
This register is to determine the functionality of PIA 1 and
the Interrupt Daisy-Chain Configuration (Figure 13). This
register has the following control bits:

Bit 05. Disable /ROMCS. When this 'bit is set to "1",
/ROMCS is forced to a "1" regardless of the status of the
address decode logic. This bit's default (after Reset) is 0
and /ROMCS function is enabled.

Bit 07. Reserved and should be programmed as "0" .

Bit 04-03. Reserved and should be programmed as "00".

Bit 06. Daisy-Chain Configuration.
arrangement'of the interrupt priority daisy chain.

Bit 02. ROM Emulator Mode Enable. When this bit is set to
a 1, theZ181 isin "ROM emulator mode". In this mode, bus
direction for certain transaction periods are set to the
opposite direction to export internal bus transactions outside the Z80181. This allows the use of ROM emulators/
logic analyzers for .applications development. This bit's
default (after Reset) is O.

.
Determines the

When this bit is set to "1", priority is as follows:
fEI pin - CTC - SCC - lEO pin
When this bit is "0", priority is as follows:

Bit D1. Reserved and shall be programmed as "0".
lEI pin - SCC - CTC - lEO pin
This bit's default (after Reset) is O.

Bit 00. CTC/PIA 1. When this bit is set to "1", PIA 1 functions
as the CTC's I/O pins. This bit's default (after Reset) is O.

413

... - - -•• - - .............. ,.........,',""~" ....""""."...." .... ,,.

",·.'·~··I"''iT',...-r;'I:'"-;-"··''-·!'"''-,'"''

DATA BUS DIRECTION
Table 3 shows the state of the SAC's data bus for the
condition thatlhe SAC is bus master.

Table 3. Data Bus Direction (Z181 Is Bus Master)
1/0 And Memory Transactions
I/O
Write To
On-Chip
Peripherals
(SCC/CTC/
PIA1/PIA2)

I/O
Read From
On-Chip
Peripherals
(SCC/CTC/
PIA1/PIA2)

I/O
Write To
Off-Chip
Peripheral

I/O
Read From
Off-Chip
Peripheral

Write
To
Memory

Read
From
Memory

Refresh

Z80181
Idle
Mode

Z80181 Data Bus
(REME Bit =0)

Out

Z80181 Data Bus
(REME Bit = 1)

Out

Interrupt Acknowledge Transaction
Intack For
On-chip
Peripheral
(SCC/CTC)

Intack For
Qff-chip
Peripheral

Z80181 Data Bus
(REME Bit = 0)

Z80181 Data Bus
(REME Bit = 1)

Out

414

DATA BUS DIRECTION (Continued)
Table 4 shows the state of the SAC's ·data bus for the
condition that the Z80181 is NOT bus master.

Table 4. Data Bus Direction for External Bus Master (Z0181 Is Not Bus Master)
1/0 And Memory Transactions
110

110

•110

110

Read From
On-Chip
Peripherals
(SCCICTC/
PIA1/PIA2)

Write To
On-Chip
Peripherals
(SCC/CTC/
PIA1/PIA2)

Read From
Off-Chip
Peripheral

To
Off-Chip
Peripheral

Z80181 Data Bus
(REME Bit = 0)

Out

Z80181 Data Bus
(REME Bit ~ 1)

Out

Write
From
Memory

Read

Refresh

Ext•
BusMaster
Is Idle

Memory

Interrupt Acknowledge Transaction
IntackFor
On-chip
Peripheral
(SCC/CTC)

Intack For
Off-chip
'Peripheral

Z80181 Data Bus
(REME Bit = 0)

Out

Z80181 Data Bus
(REME Bit = 1)

Out

The word "OUT" means thatthe Z181 data bus direction is
in output mode, "IN" means input mode, and "HI-Z" means
high impedance.
.

''REME'' stands for "ROM Emulator Mode" and is the status
of 02 bit in the System Configuration Register

415

ABSOLUTE MAXIMUM RATINGS
Voltage on Vcc with respect to Vss ........... -0.3V to +7.0V
Voltages on all inputs
with respect to Vss .............................. -0.3V to Vcc+0.3V
Operating Ambient
Temperature ............................ See Ordering Information
Storage Temperature ..... I ...................... -65°C to + 150°C

Stresses greater than those listed under AbSolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at
any condition above those indicated in the operational
sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.

+5V

2.1 K

Available operating t~mperature range is:
E = -40°C to 100°C
Voltage Supply Range:
+4.50V ~ Vcc ~ + 5.50V
All AC parameters assume a load capacitance of 100 pI.
Add 10 ns delay for each 50 pf increase in load up to a
maximum of 150 pf for the data bus and 100 pf for address
and control lines. AC timing measurements are referenced
to 1.5 volts (except for clock, which is referenced to thE1
10% and 90% points). Maximum capacitive load for ClK
is 125 pI.
'
The Ordering Information section lists temperature ranges
and product numbers. Refer to the Literature List for
additional documentation.

416

From Oulput
Under Test

U-----+---'t---J.J---"/

100 pI

Figure 59. Standard Test Circuit

DC CHARACTERISTICS
Z80181
Symbol

Parameter

V'Hl

Input "H" Voltage
/RESET, EXTAL, /NMI
Input "H" Voltage
Except /RESET, EXTAL, /NMI
Input "L" Voltage
/RESET, EXTAL, /NMI
Input "L" Voltage
Exc'ept /RESET, EXTAL, /NMI

V'H2

V'L1
VK.2

VOH
VOl.

I'L

In.
Iee '

Output "H" Voltage
All outputs.
Output "L" Voltage
All outputs.

Min

Typ

Max

Unit

Vee -0.6

Vee +0.3

2.0

Vee +0.3

-0.3

0.6

-0.3

0.8

2.4
Vee -1.2

Input Leakage
Current All Inputs
ExceptXTAL,EXTAL
Tri-State Leakage Current
Power Dissipation'
(Normal Operation)
Power Dissipation'
(SYSTEM SlOP mode)
Pin Capacitance

• V,HMin=Vee·l.0V,
vee = 5.00v

V~Max=O.8V(alioutputterminalsareat

Condition

IOH = -200 (.lA
IOH = -20 (.lA
101. = 2.2 rnA

0.45

(.lA

V'N = 0.5 - Vee -0 5

(.lA

V'N = 0.5 - Vee -05

100

1= 12.5 MHz
1= 10 MHz
1= 12.5 MHz
f=10MHz

6.3

50
40
12

V'N = OV, f = 1 MHz
TA = 25°C

noload.)

417

AC CHARACTERISTICS
Z180 MI?U Timing
Figures 60-68 show the timing for the Z181 MPU and the referenced parameters appear in Table A.
T2

'"
Address

fROMCS
fRAMCS

!WAIT

IMREO

fRO

fM1

++-____________-++_____+ ____

flORO _ _ _ _

twR
Data In

fRESET

Figure 60a. Op-code Fetch Cycle

418

AC CHARACTERISTICS (Continued)
Z180 MPU Timing
T1

Twa

Address

fROMCS
fRAMCS

/WAIT

flORO

IRD

/wR

Data IN

Data OUT

1"--_ _ _ _ _ _ _ _ _ _..11 ,

[1)

"H"
ST
[1) Output buffer is off at this point.
[2) Memory Read/Write cycle timing is the same as this figure, except there is
no automatic wait status (Twa), and fMREO is active instead of fIORO.

Figure 60b. I/O Read/Write, Memory Read/Write Timing

419

IINTI

INMI

IINTSCC(4]

IMI(I]

IIOROtl]

IDataIN(I]

IMREO(2]

IRFSH(2]

IBUSREO

IBUSACK

Address
Data/MREQ,
IRD,twR,
IIORO

-----------11--,,1

IHALT
Notes:
[I] During IINTO acknowledge cycle
[2] During refresh cycle

(3] Output buffer is off at this point
(4] Refer 10 Table C, parameter 7

Figure 61, CPU Timing
(lINTO Acknowledge Cycle, REjfresh Cycle, BUS RELEASE Mode
HALT Mode, SLEEP Mode, SYSTEM STOP Mode)

420

AC CHARACTERISTICS (Continued)
Z180 MPU Timing
VO Read Cyde
T1

110 Write Cyde

1"3

fZ)

Address

IIORO

IRD

IWR

Figure 62. CPU Timing (flOC = 0)
(I/O Read Cycle, I/O Write Cycle)

421

IDREQi
(At level
sense)

IDREQi
(At edge
sence)

fTENDi

ST
DMA Control Signals
[1) tORas and tORaH are specified for the rising edge of clock followed by T3.
[2) tORas and tORaH are specified for the rising edge of clock.
[3) OMA cycle starts.

[4) CPU cycle starts.

Figure 63. DMA Control Signals

422

AC CHARACTERISTICS (Continued)
Z180 MPU Timing
Tl

E
(Memory
ReadlWrite)

E
(110 Read)

D7-DO

==>
a) E Clock Timing
(Memory Read/Write Cycle, I/O Read/Write Cycle)

o
BUS RELEASE Mode
E { SLEEP Mode
SYSTEM STOP Mode

b) E ClOCk Timing
(BUS RELEASE Mode, SLEEP Mode, SYSTEM STOP Mode)

Figure 64. E Clock Timing

423

... ,
E
(Example:
I/O ReadOp-code
Fetch)

E
(VOWrlte)

Figure 65. E Clock Timing
(Minimum timing example of PWEL and PWEH)

A181T0UT

Figure 66. Timer Output Timing

424

AC Ct,tARACTERISTICS (Continued)

Zi80 MPU Timing
SLP Instruction Fetch
T3

Next Op-code Fetch

IINTi

INMI

A18-AO

IMREQ,/Ml
IRO

IHALT

Figure 67. SLP Execution Cycle

425

CSIIOClock

Transmit Data
(Internal Clock)

Transmit Data
(External Clock)

Receive Data
(Internal Clock)

Receive Data
(External Clock)

Figure 68. CSI/O ReceivelTransmit Timing

Table A. Z180 CPU & 180 Peripherals Timing
No

Symbol

Parameter

Z8018110
Max
Min

Z8018112
Min
Max

1
2
3
4
5
6

tcyc
tCHW
tCLW
tcl
tcr
tAD

Clock Cycle Time
Clock Pulse Width (High)
Clock Pu.lse Width (Low)
Clock Fall Time
Clock Rise Time
Address Valid Irom Clock Rise

100
40
40

80
30
30

7
8

tM1Dl

Address Valid to fMREO, flORO Fall
Clock Fall to fMREO Fall Delay
Clock Fall to fRO Fall (fIOC=l)
Clock Rise to IRD Fall (fIOC=O)
Clock Rise to IMl Fall Delay

tAS
tMEDl
tRDDl

426

2000

10
10
70

10
10
40

ns
ns
ns
ns
ns
ns

45
45
50
50

ns
ns
ns
ns
ns

2000

10
50
50
55
60

Unit

Note

AC CHARACTERISTICS (Continued)
Z180 MPU Timing
Table A. Z180 CPU & 180 Peripherals Timing (Continued)
No

Symbol

Parameter

tAH

12
13
14
15

tMED2
tRDD2
tM1D2
tDRS

Address Hold Time
(/MREO./IORO./RD. /WR)
Clock Fall to /MREO Rise Delay
Clock Fall to IRD Rise Delay
Clock Rise to IM1 Rise Delay
Data Read Setup Time

16
17
18
19
21

tDRH
tSTDl
tSTD2
tWS
tWH
tWDZ

Data Read Hold Time
Clock Fall to ST Fall
Clock Fall to ST Rise
/WAIT Setup Time to Clock Fall
/WAIT Hold time from Clock Fall
Clock Rise to Data Float Delay

22
23
24
25

tWRDl
tWDO
IWRD2
IWRP

Clock Rise to /WR Fall Delay
/WR fall to Dala Oul Delay
Clock Fall 10 /WR Rise
/WR Pulse Widlh
(Memory Wrile Cycles)
/WR Pulse Widlh (1/0 Write Cycles)

25a
26
27

tWDH
1I0Dl

1I0D2

Write Data Hold Time from /WR Rise
Clock Fall 10 IIORO Fall Delay.
(lIOC=l)
Clock Rise to IIORO Fall Delay
(lIOC=O)
Clock Fali/lOOR Rise Delay

29
30
31
32
33
34

1I0D3
liNTS
tlNTH
INMIW
tBRS
IBRH

IMl Fall 10 IIORO Fall Delay
liNT Setup Time to Clock Fall
liNT Hold Time from Clock Fall
INMI Pulse Width
/BUSREO Setup Time to Clock Fall
/BUSREO Hold Time from Clock Fall

35
36
37
38
39
40

IBAD1
lBAD2
IBZD
tMEWH
IMEWL
tRFD1

Clock Rise 10 /BUSACK Fall Delay
Clock Fall to IBUSACK Rise Delay
Clock Rise 10 Bus Floating Delay rime
IMREO Pulse Width (High)
IMREO Pulse Widlh (LOW)
Clock Rise to IRFSH Fall Delay

41
42
43
44
45
46

tRFD2
tHAD1
IHAD2
tDROS
tDROH
tTED1

Clock Rise to IRFSH Rise Delay
Clock Rise to IHALT Fall Delay
Clock Rise 10 IHALT Rise Delay
IDJ;lEOi Setup Time to Clock Rise
IDREOi Hold Time from Clock Rise
Clock Fall 10 /TENDi Fall Delay

Z8018110
Min
Max
10

ZJK)18112
Min
Max
10

50
60

25
0

60
60

20
20

30
30
60

50
10
50

30
10
45.

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

110

.os
ns
ns
ns

210

165

200
30
30

10
45

ns
ns

160
20
20
60

30
30

20
20

60
80
70
80

ns
ns'
ns
ns
ns
ns
50
50
60

60
60

.40
30

50
50

20
20

30
30
50

Note

ns
45
45
50

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
'ns
ns

427
----~~.~.~

..,..

AC CHARACTERISTICS (Continued)
Z 180 MPU Timing
Table A. Z180 CPU &180 PeripheralS Timing (Conti'nued)
No

Symbol

Parameter

47
48
49
50
51
52

tTED2
tED1
tED2
PWEH
PWEL
tEr

Clock Fall to /TENDi Rise Delay
Clock Rise to E Rise Delay
Clock Edge to E Fall Delay
E Pulse Width (High)
E Pulse Width (Low)
Enable Rise Time

53
54
55

tEt
tTOD
tSTDI

tSTDE

Enable Fall Time
Clock Fall to Timer Output Delay
CSIIO lx Data Delay Time
(Internal Clock Operation)
CSI/O Tx Data Delay Time
(External Clock Operation)

tSRSI

tSRHI

tSRSE

Z8018110
Min
Max

Z8018112
Min
Max

50
60
60

ns
ns
ns
ns
ns
ns

20
150
150

10
120
120

ns
ns
ns

55
110

50
40
40

Unit

45
90

7 .5tcyc+ 120 ns

7.5tcyc+150

CSI/O Rx Data Setup Time
(Internal Clock Operation)
CSI/O Rx Data Hold Time
. (Internal Clock Operation)
CSIIO Rx Data Setup Time
(External Clock Operation)

tcyc
tcyc
lcyc

---

·tSRHE

61
62
63
64
65

tRES
tREH
tOSC
tEXr
tEXt

66
67
68

tRr
tRI
!lr

tlf

TdCS(A)

428

CSI/O Rx Data Hold 1ime
(External Clock.Operation)
/RESET Setup Time to Clock Fall
/RESET Hold Time tram Clock Fall
Oscillator Stabilization Time
External Clock Rise Time (EXT AL)
External Clock Fall Time (EXT AL)
/RESET Rise Time
/RESET Fall Time
Input Rise Time
(Except EXTAL, /RESET)
Input Fall Time
(Except EXTAL, /RESEf)
Address Valid to /ROMCS,
Valid Delay

/f~AMCS

tcyc

20
25
25

20
20
20

ns
ns
ms
ns
ns

50
50
100

50
50
80

ns
ns
ns

100

80
50

60
45

Nole

AC CHARACTERISTICS (Continued)
CTC Timing
Figure 69 shows the timing for the on-chip Cl C, Parameters referred to in this figure appear in Table B,

Clock

CLKlTRG
Counter _ __

CLKlTRG

Timer

----f#'

zcrro

liNT

Figure 69. eTe Timing

Table B. eTe Timing Parameters
No

Symbol

Parameter

Z8018110
Min

1
2

TdCr(INTI)
TsCTRr(Cr)c

TsCTR(Ct)

Clock Rise to /INT Fall Delay
ClK/TRG Rise to Clock Rise
Setup Time for Immediate Count
ClK/IAG Rise to Clock Rise
Setup Time for Enablmg of Prescalor
On Following Clock Rise

6
7

TdCTRr(INTI) CLK/lRG Rise to /INT Fall Delay
TsCTR(C) Satisfied
TsCTR(C) Not Satislied
TcCTR
CLK/TRG Cycle Time
TwCTRh
CLK/TRG Width (low)
TwCTRI
ClK{TRG Width (High)

8
9
10
11

TrCTR
TlCTR
TdCr(ZCr)
TdCf(ZCf)

ClK(I RG Rise Time
CLK{TRG Fall Time
Clock Rise to ZCfro Rise Delay
Clock Fall to ZC/TO Fall Delay

Max

Z8018112
Min

(TcC+100)

Unit

Note

[B1]

Max
(TcC+80)

[B2]

[B1]

ns
ns
ns
ns
ns

[B2]
[82]
[B3]

(1)+(3)
TcC+(1)+(3)
(2TcC)
DC
90
DC
90
DC
30
30
80
80

(1)+(3)
TcC+( 1)+(3)
(2TcC)
DC
DC
90
DC
90
30
30
80
80

ns
IlS

ns
ns

Notes lor Table B:
[81 J TImer Mode
[821 Counter Mode
[831 Counter Mode Only; When using a cycle time less than 3TcC, parameter #2 must be met.

429

AC CHARACTERISTICS (Continued)
SCC Timing
Figure 70 shows the AC characteristics for the on-chip
SCC. Parameters referred to in this figure appear in
Table C.

!WR

/r-

IRO
1

!WI/REO
Wait
2

!WI/REO

Request
3

".-

IOTRl/REO
Request
5

liNT
6

Figure 70. SCC AC Parameters

Table C. SCC Timing Parameters (85C30 AC Characteristics)
No Symbol

Parameter

1
2
3
4

TdWR(W)
TdWR(W)
TdWRf(REO)
TdRDf(REO)

/WR Fall to Wait Valid Delay
/RD Fall to Wait Valid Delay
/WR Fall to /W//REO Not Valid Delay
/RD Fall to /W//REO Not Valid Delay

5
6

TdWRr(REO)
TdPC(INT)
TdRDA(INT)

/WR Rise to /DTR//REO Not Valid Delay
Clock to /INT Valid Delay
/M1 Fall to /INT Inactive Delay

Note for Table C:
[C 1) Open-drain output,

430

mea~ured

with Open-drain test load.

28018110
Min
Max

28018112
Min.
Max

Unit

Note

[C1]
[C1]

180 + TcC
180
180 + TcC
180

125 + TcC
125
125 +TcC
125

ns
ns
ns
ns

5TcC
500
TBS

ns
ns
ns

[C1]
[C1]

AC CHARACTERISTICS (Continued)
SCC General Timing
Figure 71 shows the general timing for the on-chip SCC. Parameters referred to in this figure appear in Table D.

PCLK

!WI/REO
Request

!WflREO
Walt

IRTxC, ITRxC
Receive

RxO

/SYNC

External

-~. i?:i~1

-.£:::3--

ITRxC, IRTxC
Transmit

TxO
1----{11}---~

ITRxC
Output

IRTXC\

~------. ~~

\__---.Jr

{;d£3 \_----.lr

ITRxC \ . ' - - - - - - -....

ICTS,IDCO

/SYNC

Input

-------------

---~
Figure 71.

see General Timing
431

AC CHARACTERisTICS (Continued)
SCC General Timing
Table D.
No

Symbol

see General Timing Parameters

Parameter

Z8018110

Min
1
2
3
4

TdPC(REO)
TdPC(W)·

5
6
7

Max

Z8018112

Min

Unit

Note

Max

ThRXO(RXCr)

Clock Fall to /WI/REO Valid
Clock Fall to Wait Inactive
RxO to IRxC Rise Setup Time
RxO to IRxC Rise Hold Time

0
125

0
100

ns
ns
ns
ns

TsRXD(RXCI)
ThRXO(RXCf)
TsSY(RXC)
ThSY(RXC)

RxO to IRxC Fall Setup Time
RxO to IRxC Fall Hold Time
ISYNC to IRxC Setup Time
ISYNC to IRxC Hold Time

0
125
-150
5TcC

0
100
-125
5TcC

ns
ns
ns
ns

[01.4]
[01,4]
[01]
[01]

9
10
11
12

TdTXCf(TXO)
TdTXCr(TXO)
TdTXO(TRX)
TwRTXh

ITxC Fall to TxO Oelay
/TxC Rise to TxO Oelay
TxO·to/TRxC Oelay
IRTxC High Width

ns
ns

[02]
[02.4]

13
14
15
16

TwRTXI
TcRTX
TcRTXX
TwTRXh

IRTxC Low Width
IRTxC Cycle Time (RxO, TxO)

17
18
19
20
21

TwTRXI
TcTRX
TwEXT
TwSY
TxRx(OPLL)

TsRXO(R~Cr)

Xtal OSC Period
/TRxC High Width

ITRxC Low Width
ITRxC Cycle Time
lOCO or ICTS Pulse Width
ISYNC Pulse Width
OPLL Cycle Time

200
300

120
220

150
150
140

130
i30
120

120

100

120
400
100
120

100
320
80
100

120
400
120
100
50

1000

100
320
100
70
40

Notes to Table 0:
[01] /RXC is /RTxC or /TRxC, whichever is supplyinR the receiver clock.
[02] /TXC is {lRxC or /RTxC, whichever is supplying the transmitter clock.
[03] Both /RTxC and /SYNC pin has 30pf Capacitors (to ground).
[04] Parameter applies only to FM encoding/decoding.
[OS] Parameter applies only to transmitter and receiver; baud rate generator timing requirements are different.
[06] The maximum receive or transmit data rate is 1/4 TcC.
[07] Applies tei OPLL clock source only. Maximum data rate of 1/4 TcC still applies.

432

[01]

IlS
IlS

[05J

[05]
[05,6]
[03]
[05]

IlS

1000

[01]

ns
ns
ns
ns
ns

[05]
[05,7]

IlS
IlS

[06,7J

AC CHARACTERISTICS (Continued)
SCC System Timing
Figure 72 shows the system timing for the on-chip SCC. Parameters referred to in this figure appear in Table E.

IRTxC,lTRxC
Receive

/WI/REO
Request

/WI/REO
Wait

ISYNC
Output

liNT

IRTxC,lTRxC
Transmit

/WI/REO
Request

/WI/REO
Wait

IDTRI/REO
Request

liNT

ICTS, lOCO

ISYNC
Input

liNT
10

Figure 72.

see System Timing
433

AC CHARACTERISTICS (Continued)
SCC System Timing
Table E.
No

1
2
3
4

5
6
7

8
9
10

Symbol

see System Timing Parameters

Parameter

IRxC
IRxC
IRxC
IRxC

TdRxC(REQ)
TdRxC(W)
TdRxC(SY)
TdRxC(INT)
TdTxC(REQ)

to /WI/REO Valid
to Waft inactive
to ISYNC Valid
to liNT Valid
/TxC to /w//REQ Valid

TdTxC(W)
TdRxC(DRQ)
TdTxC(INT)
TdSY(INT)
TdEXT(INT)

/TxC to Wait inactive
/TxC to /DTRI/REQ Valid
/TxC to liNT Valid
ISYNC to liNT Valid
IDCD or ICTS to liNT Valid

Notes for Table E:
[El) Open-drain output, measured with Open-drain test load.
[E2) /RXe Is /RTxC or {TRxC, whichever Is supplying the receiver clock.
[E3) [TXC is {l'Fixe or IRTxC, whichever is supplying the transmitter clock.

434

Z8018110

Z8018112

Unit

Note

12
14
7
16

8 (

TeC
TeC
TeC
;reC
TeC

[E2]
[El,2]
[E2]
[El,2]
[E3]

11
7
10
6
6

TeC
TeC
TeC
TeC
TeC

[El,3}
[E3]
[El,3]
[El)
[El)

Min

Max

Min

Max

8
8

4
10

12
14
7
16

4
10

11
7
10
6
6

4
6
2
2

AC CHARACTERISTICS (Continued)
PIA General Purpose I/O Port Timing
Figure 73 shows the timing for the PIA ports. Parameters referred to in this figure appear in Table F.

/lORO,IRD

PIA Input

PIA Output

Figure 73. PIA Timing
Table F. PIA General Purpose 1/0 Timing Parameters

Symbol

Parameter

Z8018110
Min

TsPIA(C)
TdCr(PIA)

PIA Data Setup time to Clock Rise
Clock Rise to PIA Data Valid Delay

Max

Z8018112
Min
10

Unit

Note

Max

ns
ns

435

Interrupt Daisy-Chain Timing
Figure 74

show~

the interrupt daisy-chain timing Parameters referred to in ttlis figure appear in Table G.

eLK

1M1

nORa

Dma __

+-__

____________

lEI

lEO

liNT

(see)

iWPJT

Figure 74. Interrupt Daisy-Chain Timing

Table G. Interrupt Daisy-Chain Timing Parameters
No

Symbol

Parameter

Z8018110
Min
Max

Z8018112
Min
Max

1
2

TsM1(Cr)
TsM1(10)INTA

/M1 Fall to Clock Rise Setup Time
/M1 Fall to /IORO Fall Setup Time
(During INTACK Cycle)

2TcC

2TcC
0
0

3
4
5

Th
TdM1r(DOz)
TdCr(DO)

Hold Time
/M1 Rise to Data Out Float Delay
Clock Rise to Data Out Delay

0
0

TsIEI(TW4)
TdIElf(IEOf)
TdIElr(IEOr)

lEI to TW4 Rise Setup Time
lEI Fall to lEO Fall Delay
lEO Rise to lEO Rise Delay

TdM1f(IEOf)
TdCWA(f)INIA
TdCWA(r)INTA

/M1 Fall to lEO Fall Delay
Clock Rise to /WAI r Fall Delay
Clock Rise to /WAI r Rise Delay

7
8
9

10
11

436

100

120
80
20
140

20
120

140
30
30

120
25
25

AC CHARACTERISTICS (Continued)
Read Write External BUS Master Timing

eLK

Address

flORa

lAD

Data

----1---0{

Data

Data IN

Figure 75. ReadIWrite External BUS .Master Timing

Table H. External Bus Master Interface Timing (Read/Write Cycles)

Symbol

Parameter

Z8018110
Min

Max

Z8018112
Min

1
2
3

TsA(Cr)
TsIO(Cr)
Th

Address to ClK Rise Setup Time
flORO Fall to ClK Rise Setup Time
Hold Time

20
20

4
5
6

TsRD(Cr)
TdRD(DO)
TdRlr(DOz)

fRO Fall to ClK Ri~e Setup rime
fRO Fall to Data Out Delay'
fRO, flORO Rise to Read Data Float

20
0

TsWR(Cr)
TsDi(WRf)
ThWlr(Di)

/WR Fall to ClK Rise Setup Time
Data in to /WR Fall Setup Time
flORO, /WR Rise to Data 1[1 Hold Time

20
0
0

TsA(IOROf)
TsA(RDf)
TsA(WRf)

Address to flORO Fall Setup Time
Address to tRDf'all Setup Time
Address to /WR Fall Setup Time

50
50
50

40
40
40

8
9
10

11
12

. Max

20
20
0

·20
120

100

437

see External BUS Master Timing
Valid sec
Addr*IORO

IROar

IWR
OTR/REO

Request

-------------------------------------------------'
Figure 76.

see External BUS Maste'r Timing

Table I. External Bus Master Interface Timing (SCC Related Timing)

No Symbol

1
2

TrC
TdRDr(REQ)

Parameter

Valid Access Recovery Time ,
/RD Rise to /DTR//REQ Not Valid Delay

(1) Applies only between transactions involving the

438

sec.

Z8018110

Z8018112

Min

4TcC
4TcC

Max

4TcC
4TcC

Unit

Note

nS
nS

[1]

Max

AC CHARACTERISTICS (Continued)
Note for Interrupt Acknowledge Cycle and Daisy Chain
When using the interrupt daisy chained device( s) for other
than the Z181, these are the following restrictions/notes
(without, external logic ).
The device(s) has to be connected to the higher prtority
location (Figure 77).
The device(s) lEI-lEO delay has to be less than two clock
cycles.
The Z 181 on-chip interface logic inserts another three wait
states into the interrupt acknowledge cycle to meet the onchip SCC and the Z80 CTC timing requirements. (Total of
5 wait states; includes the automatic inserted two wait
states).
Tomeetthe timing requirements, the Z181 'son-chip circuit
generates interface signals for the SCC and CTC.
Figure 78 has the timing during the interrupt acknowledge
cycle, including the internally generated signals.

Case 1 - SCC: The SCC /INTACK signal goes active on the
T1 clock fall time. The settle time is from
/INTACK
active until the SCC /RD signal goes active on the fourth
rising wait state clock.

sec

Case 2 - CTC: 1he settle time for the on-chip /IORO is
between the fall of /M1 until the internal CTC /IORO goes
active on the rise of the fourth wait state (the same time as
SCC IRD goes active).
Case 3 - OFF-chip Z80 Peripheral: The settle time for the
off-chip l80 peripheral is from the fall of /M1 until CTC
/IORO goes active. Since the Z181 's external/IORO signal
goes active on the clock fall of the first automatically
inserted wait state (TWA)' the external daisy-chain device
has to be connected to the upper chain location. Also, it
must settle within two clock cycles.
If any peripheral is connected externally with a lower daisy
chain priority than Z181 peripherals, /IOAO has to be
delayed by external logic as shown in Figure 79

1 he following are three separate cases for the daisy-chain
. settle times:

Vee
-r-

IEl

Peripheral
Oevice(s)

lEO

lEI

CTC

lEO

lEI

SCC

lEO

Z80181

Figure 77. Peripheral Device as Part of the Daisy Chain

439
~---------"-

-_.. ""'"

, TW

ClK
, (seUle lime lor
OII-chip zao
Peripherals

fM1

S"Ule Time lor

On-chip CTC

/lORa

SCC
flNTACK

Setllelime
lorSCC

/
/WAIT
I

/WAIT Signalgeneraled
by interlace circuit

SCC
fRO

CTC
flORa

Figure 78. Interrupt Acknowledge Cycle Timing

Vee
-r-

IEl

CTC

lEO

lEI

SCC

lEI

lEO

-flORO
Z80181

External
Logie to
Extend
flORO
Signal

Figure 79. Peripheral Device as Pan of the Daisy Chain

440

Peripheral
Deviee(s)

lEO

~ZiIm

PRELIMINARY PRODUCT SPECIFICATION

Z84Q13/015
Z84C13/Z84C15
IPC INTELLIGENT PERIPHERAL CONTROLLER
FEATURES
•

Z84COO Z80 CPU with Z84C30 CTC, Z84C4X SIO,
CGC, Watch Dog Timer(WOT). In addition, Z84C15
and Z84015 have Z84C20 Pia.

•

High speed operation (6/10 MHz).

•

Low power consumption in four operation modes'
(TBO) mA Typ. (Run mode)
(TBO) mA Typ. (ldle1 mode)
(TBO) mA Typ. (ldle2 mode)
(TBO) J1A Typ (Stop mode)

•

Wide operational voltage range (5V ±10%).

•

TTL/CMOS compatible.

•

Z84013 features'
Z84COO Z80 CPU
On-chip two channel SIO (Z80 SIO).
On-chip four channel Counter Timer Controller
(Z80 CTC).

Built-in Clock Generator Controller (CGG).
Built-in Watch Dog Timer (WOT).
Noise filter to CLKnRG inputs of the CTC.
84-pin PLCC package.
•

Z84015 features'
All Z84013 features, plus on-chip two 8-bit ports (Z80
Pia) and 100-pin QFP package.

•

Z84C13/Z84C15 enhancements to Z84013/Z84015:
Power-on reset.
Addition of two chip select pins.
32-bit CRC for Channel A of SIO.
Wait state generator
Simplified EV mode selection.
Schmitt-trigger inputs to transmit and receive clocks
of the SIO.
Crystal divide-by-one-mode.

GENERAL DESCRIPTION
The Intelligent Peripheral Controller(IPC) is a series of
highly superintegrated devices with four versions. The
Z84C13 and the Z84C15 are upward compatible versions
of the Z84013 and the Z84015. The Z84015 is a CMOS 8bit microprocessor integrated with the CTC, SIO, CGC,
WDT and the Pia into a Single 1~O-pin Quad Flat Pack(QFP)
package. The Z84013 is the Z84015 without Pia, and is
housed in a 84-pin PLCC package. The Z84C13 is the
Z84013 with enhancements and the Z84C 15 is the Z84015
with enhancements. These high-end superintegrated intelligent peripheral controllers are targeted for a broad

range of applications ranging from error correcting modems to enhancement/cost reductions of existing hardware using Z80-based discrete peripllerals. Figures 1 and
2 show the difference between the Z84013/015 and the
Z84C13/Z84C15.
Hereinafter, use the word IPC on the description covering
all versions (Z84C13/Z84C15 and Z84013/Z84015). Use
Z84C13/C15 on the description that applies only to the
Z84C13 and Z84C15, and use Z84013/015 on the descrip. tion that applies only to the Z84013 and Z84015.

441

Z84015

Z84013
CPU

sib

CGC
WDT

eTC

CPU
SIO
CTC
PIO

CGC
WDT

Figure 1. Z84013/015 Version
Z84C13

CPU
SIO
CTC

CGC
WDT

Enhancement

Z84C15
CPU
SIO
CTC
PIO

CGC
WDT

Enhancement

Figure 2. Z84C13/C15 Version

A4
A3
A2

CLKfTRG 1
CLKfTRG 2
CLKfTRG 3

AI
A0

ZCfTO 3
ZCfTO 2
ZCfTO 1

1Ml
IBUSREO
NI/lJT
NlR
AORO

Z84013
Z84C13
84-PIN PLCC
(Top View)

vss
IMREO
NC
ANT
IRFSH

ZCfTO 0
CLKII'I
CLKOUT
NC
XTAL2
XTAL1

VSS
NlOTOUT
lEI

NC
IRESET
IBUSACK

lEO
EV
NC

IRD

INMI
A7RF
Nl/IROYB

!HALT
Nl/IROYA

Note: Power connections follow
Conventional descriptions below
• ICTforihe Z84013

Figure 3. Z84013/Z84C13 Pin-out Assignments

442

Connection

Circuit

Device

Power
Ground

Vce

Voo
Vss

GND

~8o~SC!i:g:g:.:;§
AS
M
A3
A2
A1

1.
100

CLKlTRG3
ZCfT03
ZCIT02

M
IRFSH

lEI
lEO
A7RF

CLKIN
CLKOlJT
81
XTAL2
XTAL1

/BUSACK
IWR
IRO
/IORO

Z84015
Z84C15
100-PIN QFP

vss

VSS

IMREO
/HALT

HAl
BROY

nNT
AROY
IASTB
PA7
PAG
PAS
PM

ZCfT01
ZCITOO
IWOTOlJT

1M1
IRESET
/BUSREO
IWAIT

CLKfTRG1
CLKlTRG2

20
60

/BSTB
PB7
PBS
PBS
PB4

-25

==:J PB3

55-

PA3
PA2
PA1

PB2
PB1

POO

PM
IW/IROYA

IW/IROYB
ISYNCB

Note: Power connections foHow
conventional desc",tions below:

• ICTfor the Z84015

Connection Circuit

Figure 4. Z84015/Z84C15 Pin-out Assignments

Device

Power

Vex;

Voo

Ground

GND

V..

PIN DEFINITIONS
The pin assignment for each device is shown in Figures 3
and 4. Following is the description on each pin. For the
description and the pin number, if stated as "x13" or "x15",

lilat applies to both Z84C13/Z84013 or Z84C15/Z84015.
Otherwise, C13 for Z84C13, C15 for Z84C15, 013 for
Z84013 and 015 for Z84015.

443

CPU SIGNALS
Pin Name

Pin Number

InputtOutput, 3-5tate

Function

AO-A15

1-16(x13),
1-6, 91-100(x15)'

I/O

16-bit address bus. Specifies I/O and memory
addresses to be accessed. During the refresh
period, addresses' for refreshing are output. The
bus is an input when lhe external master is
accessing the on-chip peripherals.

00-07

76-83(x13),
82-89(x15)

I/O

8-bit bidirectional data bus. When the on-chip
CPU is accessing on-chip peripherals, these
lines are set to output and hold the data to/from
on-chip peripherals.

/RD

3O(x13), 14(x15)

I/O

Read signal. CPU read signal for accepting
data from memory or I/O devices. When an
external master is accessing the on-chip
peripherals, it is an input signal.

/WR

2O(x13),13(x15)

I/O

Write Signal. This signal is output when data, to
be stored in a specified memory or peripheral
LSI, is on the MPU data bus. When an external
master is accessing the, on-chip peripherals, it is
an input signal.

/MREQ

23(x13), 17(x15)

I/O,3-State

'Memory request signal. When an effective address lor memory access is on the address bus,
"0" is output. Wheo an external master IS
accessing the on-chip peripherals, it is an tristate signal.
.

/IORO

21(x13), 15(x15)

I/O

I/O request signal. When addresses for I/O are
on the lower 8 bits (A7-AO) of the address bus in
the I/O operation, ·0" is output. In addition, the
/IORO signal is output with the /M1 signal at the
time of interrupt acknowledge cycle to inform
peripheral' LSI 01 the state of the interrupt
response vector is when put on the data bus.
When an external master is accessing the onchip peripherals, it is an input signal.

/M1

17(x13),8(x15)

I/O

Machine cycle "1". /MREO and "0" are output
together In the operation code fetch cycle. /M1
is output for every opcode fetch when a two
byte opcode is executed. In the maskable
interrupt acknowledge cycle, this signal is
output together with /IORO. It is 3-stated in EV
mode.

444

CPU SIGNALS (Continued)
Pin Name

Pin Number

Input/Output. 3-State

Function

IRFSH

26(x13). 7(x15)

Out. 3-State

The refresh signal. When the dynamic memory
refresh address is on the low order byte of the
address bus. IRFSH is active along with IMREO
signal. This pin is 3-stated in EV mode.

liNT

25(x13). 19(x15)

Open drain

Maskable interrupt request signal. Interrupt is
generated by peripheral LSI This signal IS
accepted if the interrupt enable Flip-Flop (IFF) is
set to "1". The liNT signal of on-chip peripherals
is internally wired - OR without pull-up resistors
and requires external pull-up. Also. interrupts
from on-Chip peripherals go out from this pin.

INMI

56(x13).63(x15)

Non-maskable interrupt request signal This
interrupt request has a higher priority than the
maskable interrupt request and does not rely
upon the state of the interrupt enable Flip-Flop
(IFF).

IHALT

31(x13).81(x15)

Out. 3-State

Halt signal. Indicates that the CPU has executed
a HALf instruction. Thi~ signal is 3-stated in EV
mode.

IBUSREO

18(x13). 1O(x 15)

BUS request signal. IBU$REO requests placement of the address bus. data bus. IMREO.
IIORO. IRD and /WR signals into the high
impedance state./BUSREO is normally wiredOR and a pull-up resistor is externally
connected.

IBUSACK

29(x13). 12(x15)

Out (013/015).
OuV3-State

Bus Acknowledge signal. In response to
IBUSREO signal. IBUSACK informs a peripheral
LSI that the address bus. data bus./MREO.
IIORO. IRD and /WR signals have been placed
in' the high impedance state

(C13/C15)

Note: For the Z1!4013/015 the /BUSACK signal will not be 3-stated during EV mode. For the Z84C 13{C 15 the /BUSACK will be 3-stated during EV mode.

/WAIT

19(x13). 11(x15)

.In(0131015).
I/O(C13/C15)

Wait signal. /WAIT informs the CPU that
specified memory or peripheral is not ready for
data transfer. As long as /WAIT signal is active.
MPU is continuously kept in the wait stale.
I

No,e: For the Z84C13/C15. the /WAIT pin becomes an output to bring out on-chip wait state generator during the EV mode.

445

CPU SIGNALS (Continued)
Pin Name

Pin Number

Input/Output, 3-State

Function

A7RF

55(x13),70(x15)

Out

1-bit auxiliary address bus. Output is the same
as bit-7 (A7) of the address bus. However,
during a refresh cycle, ttlis pin outputs ttle
address which is the most significant bit of the
8-bit refresh address signal linked to the low
order 7 bits of the address bus.

CTCSIGNALS
3~tate

Pin Name

Pin Number

Input/Output,

Function

ClK/TRGO ClK/TRG3

72-75(x13), 78-81(x15)

External clock/trigger input. Tl1ese four ClK/
TRG pins correspond to four Counter/Timer
Channels. In the counter mode, each active
edge will cause the downcounter to decrement
by one. In timer mode, an active edge will start
the timer. It IS program selectable wheti1er tile
active edge is rising or falling.

ZC/TOOZC/T03

68-71(x13), 74-77(x15)

Out

Zero count/timer out signal. In eittler timer or
counter mode, pulses are output when the
down-counter has reached zero.

SIOSIGNALS
Pin Name

Pin Number

Input/Output, 3-State

Function

/W//RDYA,
/W//RDYB

32,54(x13),30,52(x15)

Out

Wait/Ready signal A and Wait/Ready signal
B. Used as /WAIT or /READY depending upon
SIO programming. Wilen programmed as /WAIT
they go active at "0", alerting the CPU that
addressed memory or I/O devices are not ready
by requesting the CPU to wait. When
programmed as /READY, they are active at "0"
which determines when a peripheral device
associated with a DMA port is for read/write
data.

/SYNCA,
/SYNCB

33,53(x13), 31 ,51(x15)

I/O

Synchronous signals. In asynchronous
receive mode, they act as /CTS and /CDC In
external sync mode, these signals act as inputs.
In internal sync mode, they act as outputs.

RxDA, RxDB

34,52(x13), 32,50(x15)'

Serial receive data signal.

446

SIO SIGNALS (Continued)
Pin Name

Pin Number

Input/Output, 3-State

Function

/RxCA, /RxCB

35,51(x13), 33,49(x15)

Receive clock signal. In the asynchronous
mode, the receive clocks can be 1, 16, 32, or 64
times th.e data transfer rate.
•

/TxCA, (fxCB

36,50(x13), 34,48(xI5)

Transmitter clock signal. In the asynchronous
mode, the transmitter clocks can be 1, 16, 32, or
64 times the data transfer rate.

TxDA, TxDB

37,49(x13), 35,47(x15)

Out

Serial transmit data signal.

/DTRA, /DTRB 38,48(x13), 36,46(xI5)

Out

Data terminal ready signal. When ready,
these signals go active to enable the terminal
transmitter. When not ready they go Inactive to
disable the transfer from the terminal.

/RTSA, /RTSB

39,47(x13), 37,45(xI5)

Out

Request to send signal. "0" when
transmitting serial data. They are active when
enabling their receivers to transmit data.

/CTSA, /CTSB

40,46(x13), 38,44(xI5)

Clear to send signal. When "0", after transmitting these signals the modem is ready to receive
serial data. When ready, these signals go active
to enable terminal transmitter. When not ready,
these signals go inactive to disable transfer from
the terminal.

/DCDA,
/DCDB

41,45(x13), 39,43(x15)

Data ,carrier detect signal. When "0", serial
data can be received. These signals are active
to enable receivers to transmit.

SYSTEM CONTROL SIGNALS
Pin Name

Pin Number

Input/Output, 3-State

Function

lEI

6O(x13),72(x15)

Interrupt enable input signal. lEI is used with the
lEO to form a priority daisy chain when there is
more Ulan one interrupt-driven peripheral.

lEO

59(x13),71(x15)

Out

The interrupt enable output signal. In the daiSY
chain interrupt control, lEO controls the interrupt
of external penpherals. lEO is active when lEI is
"1" and the CPU is not servicing an interrupt
from the on-chip peripherals.

Out

Chip Select O. Used to access external
memory or I/O devices. This pin has been
assigned to "ICT" pin on Z84013/015. This
signal is decoded only from A 15-A 12 without
control signals Refer to "Functional Description"
on-chip select signals for further explanation.

/CSO
42(C13),40(CI5)
(C13/C15 only)
,

447

SYSTEM CONTROL SIGNALS (Continued)
Pin Name

Input/Output. 3-State

Function

/CS1
40(x13).42(x15)
(C13/C15 onl~)

Out

Chip Select 1. Used to access external
memory or I/O devices. This pin has been
assigned to "ICT" pin on Z84013/015. This
signal is decoded only from A 15-A 12 without
control signals. Refer to "Functional Description"
on-chip select signals for further explanation.

/WDTOUT

61(x13),73(x15)

Out(013/015),
Open Drain(C13/C15)

Watch Dog Timer Output signal. Output pulse
width depends on the extemally conflected pin.

/RESET

28(x13),9(x15)

Input(013/015),
I/O (Open Drain)
{C13/C15)

Reset signal. /RESET signal is used for
initializing MPU and other devices in the system.'
Also used to return from the steady state in the
STOP or IDLE modes.

Pin Number

Nole: For the Z84013/Z84015 the /RESET must be kept in active state for a period of at least three system clock cycles.
Nole: For the Z84C131Z84C15, during the power-up sequence, the/RESET becomes an Open drain output and the Z84C131C15 will drive this pin
to "0' for 25 to 75 msec after the power supply passes through approx. 2,2V and then reverts to input. If it receives the IRESET signal after poweron sequence, it will drive /RESET pin for 16-processor clock cycles depending on the status of Reset Output Disable bit in Misc Control Register If
this Reset output is disabled, it must be kept in active state for a period of alleast three system clock cycles Note, that IT using Z84C 13/C15 in a Z840 13( ,
015 socket, modification may be required on the reset circuit since this pin is "pure input pin" on the Z840131015 Also, the /RESET pin doesn't have
internal pull-up resistors and therefore requires external pull-ups For more details on the device, please refer to "Functional Description."

XTAl1

63(xI3),65(x15)

Crystal oscillator connecting terminal. A parallel
resonant crystal is recommended If external
clock source is used as an input to the CGC
unit, supply clock goes into this terminal. If
external clock is supply to ClKIN pin (without
CGC unit), this terminal must be connected to
"0" or "1".

XTAl2

63(x13),66(x15)

Out

Crystal oscillator ,connecting terminal.

ClKIN

67(x13),69(x15)

Single-phase System Clock Input.

ClKOUT

66(x13),68(x15)

Out

Single-phase clock output from on-chip Clock
Generator/Controller.

58(x13),67(x15)

Evaluator signal, When "1" is applied to this
pin, IPC is put in Evaluation mode

Nole: For the Z84013/015, together with /BUSREO, the EV signal puts the IPC into the evaluation mode When this signal becomes active, the status
of /M1, /HALT and /RFSH change to input. When using Z84013/015 as an evaluator chip, the CPU is electrically disconnected, after one machine cycle
is executed with the EV signal "1" and the /BUSREO signal "0". It follows the instructions from the other CPU (of ICE), Upon receiving /BUSREO; A 15AO, /MREO, /lORa, /RD and /WR are changed to input and 07-00 changes its direction, /BUSACK is NOT 3-stated so it should be disconnected by
an externally connected circuit. For details, please refer to "Functional DeSCription" on EV mode.

448

SYSTEM CONTROL SIGNALS (Continued)
Note: For the ZB4C13/C15, to access on-chip resources from the CPU (e.g., ICE CPU), the CPU is electrically disconnected; A 15-AO, IMREQ,/IORQ,
/RO and twR are changed to input; 07-DO changes its direction; 1M 1, /HALT and /RFSH are put into the high impedance state when the EV pin is
set to "1". Also, /BUSACK IS 3-stated. For details, please refer to "Functional Description" on EV mode.

Pin Name

Pin Number

Input/Output, 3-State

Function

ICT

42,44(013), 40,42(015):
Not with C13/C15

Out

Test pins. Used in the open state.

24,27,57,65(x13),
Not with x15

VCC

43,84(x13),41,90(x15}

Power Supply

+5 Volts

VSS

22, 62(x13), 16,64(x15)

Power Supply

o Volts

Not connected.

PIO SIGNALS (for the Z84x15 only)
Pin Name

Pin Number

Input/Output, 3-State

Function

/ASTB

21(x15)

Port A strobe pulse from a peripheral device.
The signal is used as tile h,andshake between Port
A and external circuits. The meaning of this signal
depends on the mode of operation selected for
Port A (see "Pia Basic Timing").

/BSTB

61(x15)

Port B strobe pulse from a periplleral device.
This signal is used as the Ilandsllake between Port
B and external circuits. Tile meaning of this signal
is the same as /ASTB, except when Port A is in
mode 2 (see "Pia Basic Timing").

ARDY

20(x15)

Out

Register A ready signal Used as ttle handshake
between PortA and extemal circuits. The mej3ning
of this signal depends on the mode of operation
selected for Port A (see "Pia Basic Timing").

BRDY

62(x15)

Out

Register B ready signal Used as the handsllake
between Port B and external circuits. The meaning
of this signal is the same as ARDY except when
Port A is in mode 2 (see "Pia Basic Timing")

PA7-PAO

22-29(x.15)

I/O, 3-State

Port A data signals. Used for data transfer
between Port A and external circuits.

PB7-PBO

53-60(x15)

I/O, 3-State

Port Bdata signals. Used for transfer between
Port B and external circuits.

449

The following pins have different functions between 0131015 and C13101.5
Pin Name

Pin # X13

Pin # X15

/RESET
/WAIT
EV
/WDTOUT

28
19
58
61

9
15
67
73

ICT
TxCA, TxCB,
RxCA and RxCB
/BUSACK

40,42
35,36,50,51

42, 40
33,34,48,49

(Test pin) on Z84013/015; /csa and /CS1 on Z84C13/15,
On Z84C13/15; these signals have Schmitt-triggered Inputs.

In EV mode, 3-stated on Z84C13/15; remains active on
Z84013/015.

Punction
Functionality is different.
Functionality is different.
Functionality is different.
, Push-pull output on Z84013/015, Open drain on Z84 C13/C15

FUNCTIONAL DESCRIPTION
Figure 5(a) shows the functional block diagram of the
Z84013/015 and Figure 5(b) shows the functional block
diagram ofthe Z84C13/C15. As described earlier, the only
difference between the Z84x13 and the Z84x15 is the PIO
not being available on the Z84x13.
Functionally, the on-chip SIO, PIO (not available on Z84x 13),
CTC, and the ZOO CPU are the,same as the discrete
devices. Therefore, for detailed description of each individual unit, refer to the Product SpecificationlTechnical
Manual of each discrete product.
The following subsectiqns describe each individual functional unit of the IPC.
Z84COO/01 Logic Unit
The CPU provides all the capabilities and pins of the Zilog
Z80 CPU. This allows 100% software compatibility with
existing ZOO software . .In addition,. ii has the pin called
"A7RF" to extend DRAM refreSh address to B-bits. Refer to
'Z84C01 Z80 CPU with CGC" Product Specification.

Z84C20 ParailellnputlOutput Logic Unit (Z84x15 Only)
This logic unit provides both TTL- and CMOS- compatible
interfaces between peripheral devices and a CPU through
the use of two B-bit parallel ports (Figure 6). The CPU
configures the logic to interface to a wide range.of peripheral devices with no external logic. Typical devices tha,t are
compatible with this interface are keyboards, printers, and
EPROM/PAL programmers,

The parallel ports (designated PortA and.Port B) are byte
wide and completeiy compatible with the Z84C20 PIO.

450

These two ports have several modes of operation; input.
oulput. bi-directional, or bit control mode. Each port has
two handshake signals (RDY and /STB) which are used to
control dala transfers. The RDY (ready) indicates that the
port is ready for data transfer while /STB (strobe) IS an input
to the port that indicates when data transfer has occurred.
Each of Ihe ports can be programmed to interrupt the CPU
upon the occurrence of speCified status conditions, and
generate unique interrupt vectors when the CPU responds
(for more information on the operation of this portion of the
logic, please refer to the Z84C20 PIO Product Specification and Technical Manual).
Z84C30 Countermmer Logic Unit
This logic unit provides the user with four individual 8-bit
Counter/Timer Channels that are compatible with the
Z84C30 CTC (Figure 7). The Counter/Timers can be programmed by the CPU for a broad range of counting and
tim'ing applications. Typical applications include event
counting, interrupt and interval counting, and serial baud
rate clock generation.

Each of the Counter/Timer Channels, deSignated Channels 0-3, have an 8-bit prescaler (when used in timer
mode) and its own 8-bit counter to provide a wide range of
count resolution. Each of the channels have their own
Clock/Trigger input to quantify the counting process and
an output to indicate zero crossing/timeout conditions.
With only one interrupt vector programmed into the logic
unit, each channel can generate a unique interrupt vector
in response to the interrupt acknowledge cycle.

XTALI

XTAll

MSI

1M!

/HAlT

IM1
INMI

Controller

CLK

IMREO

I--

IWAIT

CPU

IBUSREO IBUSACK

l l t

CGC INMI
IRESET

IRESET

!HALT CLKOUT CLKIN

CLK
!HALT

MSZ
INMI-

IM1

IRESET

.:: 11m

00.07

eLK

·zcrro 3 .... " -

"ds

IRO nORa IWR IRFSH

CLKlTRGO' CLKlTRG3 _

-,::=

00.07

no~g

CTC

lI-

IRESET

lEI
lEO

IMI
ICE

f---<

CSz

r-- 0

CS 1

[rl

f-... r-

."";
AROY

O' PB 7

rv"

BROY .... IBSTB -

"~
f--

lEI
lEO

,~~

[

I-- a:.

IASTB -

•

I-

C--w=

I--

~ffi I--

-v8

CLK

11m

00 .07

PIC
(284015
ONLY)

IRO
!lORa

IMI

q
~

CLK
ICE

f- a:
W

CIID

~ 0

=:>ffi!-

~ 0

lI-

IMI
lEI
lEO
ICE

TXOB

~- IRXCB

f-1---

IL..

•~I

Do, 07 1M! IRESET :~~ IWR IRFSH

CLK

#F4

~- rrXCB

PIIA

I----

f-f-f--

IWIROYA
/sYNCA
RXOA
IRXCA
rrXCA
TXOA

SIO

CliO

#Fl

I-

11m

#FO

IRESET

gi0
w

BlA

I----

CLK 00.07 1R0nORQ

IRFSH
IWR
IRO
!lORa
ICTSA
IDCOA
IRTSA
IDTRA

WATCHDOG
TIMER
AND REGISTERS

IM1·IRESET

MSl.MSZ

RXOB
/SYNCS
1W1I10YB

IDTRB
IRTSB
ICTSS
IDCOB

f-----

IWOTOUT

f--

A7RF

f--

IEI
IEO

f-----

7< 7

Figure 5(a). Block Diagram for 84013/0151PC

451

Power
On
RESET

XTALI

XlAl2

~
-~

MS2

Controller

IRESET

/HALT
IMI
/llN1

lINT

,
- . IMREO

1--

Cll(

~'--k

IBUSREO IBUSACK

l l i

CGCl1It.ll

IRESET

IIW.TCll(OUT Cll(IN

Cll(
/HALT ~IMI

MSI

jNM)-

IMI

IRESET

WAIT
STATE
GEN,ERATOR

lINT

DO' 07
lINT

ClJ(

ZCIfOO,ZCIfO 3 ... I--

IRD /IORO NIR IRFSH

DO' 07
ClJ(IfR~

-CU (03-00 of CSBR)
(Where CSBR is the contents of Chip
Register.)

Sele~t Boundary

There is also a separate /CS enable bit./CSO IS enabled on
power-up with a boundary value of "F" causing /csa \0 go
active for ,all memory accesses. /CS1 is disabled on

power-up, and boundary address is undefined. These
features are controlled vi-a the I/O control registers located
at I/O address EEh and EFh. Note that a glitch may be observed on these pins because address decode logic is
decoding only A 15-A 12, without any control signals. For
more detail, please refer to the "Programming section."
Other functional features (Z84C13/C15 Only)
For more system design flexibili ty, the Z84C 13/C 15 llas the
following unique features. These features are controlled by
MCR (Misc. Control Register) which is indirectly accessed
via the System Control Register Pointer (SCRP, I/O address EEh), and System Control Data Port (SCDP, I/O
address EFh). For more details, please refer to the "Programming" section.
•

Clock Divide-by-one option

•

Reset Output Disable

•

32-bit CRC Generation/Checking

Clock Divide-by-One Option. This feature is programmed
through Bit D4 of MCR. Upon Power-On reset. the Clock
from on-chip CGC is passed through a divide-by-two
circuit. By setting this bit to one, the divide-by-two circuit
is bypassed so the clock on the ClKOUT pin is equal to
X'tal input. If the clock is applied to the ClKIN pin from
extemal clock source, the status of this bit is ignored. Upon
Power-on Reset. itis .cleared to O. For details, please refer
to "Programming" section.
Reset Output Disable. This feature is programmed tJy Bit
D3 of MCR. If this bit is cleared to "0", The /RESU·pin
becomes "Open-drain output" and is driven to "0" for 16clock cycles from the falling edge of /RESET input. This
feature is for the cases where /RESET is used to get out
from the "HALT" state If this bit is set to one, the on-chip
reset circuit will not drive /RESET pin.
32-bit CRC Generation/Checking. This feature IS programmed by Bit D2 of MCR By setting this bit to one,
Channel A of SIO is set to use the 32-bit CRC generator/
checker instead of the original 16-bit CRC generator/
checker in synchronous communication modes. The polynomial to be used in this mode is the one for the protocols

such as V.42, and is (X32 + X26 + X23+ X22 + X16 + X12
+X11 + X10+ X8+ X7 + X5+ X4+ X2+ X+ 1). Upon Poweron Reset, this bit is cleared to O.
Evaluation Mode
The IPC has a bUilt evaluation (or development) mode
feature which allows the users to utilize standard Z80
development systems conveniently. This mode virtually
replaces the on-chip Z80 CPU Wiltl the external CPU. In
this mode, the on-chip CPU is electrically disconnected
from internal bus and all 3-state signals (A 15-0, D7 -0,
/MREO, /IORO, /RD, M'R, /HALl, /M1 and /RFSH; forC13/
C15, /BUSREO as well) are tri-stated, or changed to input.
This allows the development system CPU to take over and
use the internal I/O registers of the IPC exactly as ifltle CPU
was on-Chip.
.
Z84013/015 Only. When this signal IS actlve,tlle /M1,
/HAl T and /RFSH pins are put in the high-impedance
state. In using the Z84013/015 as an evaluator chip, the
CPU is electrically disconnected (put in high-impedance
state) after one machine cycle is executed with the EV
signal being "1" and the /BUSREO signal being "0". Then,
on-chip resources can be accessed from the outSide.
/BUSACK is disconnected by an externally connected
circuit.
Z84C13/C15 Only. If the EV pin is tied to Vcc on Power-up,
the Z84C13/C15 enters into an evaluation mode. In this
mode, the internal CPU is immediately disconnected from
the internal bus and all 3-state signals mentioned above
are tri-stated, or changed to input. Note that the /WAIT pin
became the OUTPUT pin in EV mode, and the Wait State
Generator generates wait states Dnly as programmed. If
the target application board has a separate wait state
generator, modification of the target may be required.
/BUSACK is 3-stated in this mode.
The Z84C13/C15 behaves similarly to the situation where
in regular operation, the /BUSREO signal is asserted by an
external master causing all 3-state signals to be tri-stated
by the Z84C13/C15 during T1 of the following machine
cycle. The /BUSREO approach was not used for the
evaluation mode to avoid significant external circuitry to
work around the time period before the external CPU uses
the bus for Z84C13/C15 accesses.

PROGRAMMING
I/O address assignm~nt I
The IPC 's on-chip peripherals' I/O addresses are listed in
Table 1. They are fully decoded from A7-AO and have no
image.The registers with Z84C13/C15 located at I/O

Address EEh and EFh are the registers to control enhanced features to Z84013/015, and not assigned on
. Z84C013/015.

457

Table 1. I/O'Control Register Address
Address

Device

Channel

10h
11h
12h
13h

CTC
CTC
CTC
CTC

ell 0
Ch 1
Ch2
Ch 3

Control
Conlrol
Control
Control

18h
19h
1Ah
1Bh

SIO
SIO
SIO
SIO\

Ch.A
Ch.A
Ch. B
Ch B

Data Regisler
Conlrol Register
Data Register
Control Register

1Ch
1Dh
1Eh
1Fh

PIO
PIO
PIO
PIO

Port A
PortA
Port B
Port B

Data Register (Not with Z84x13)
Command Register (Not with Z84x13)
Data Register (Not with Z84x13)
Command Register (Not with Z84x13)

FOh
F1h
F4h

Watch-Dog Timer
Watch-Dog Timer
Interrupt Priority Register

Master Register (WDTMR)
Control Register (WDfCR)

System Control Register Pointer (SCRP)
(Not with Z84013/015)
System Control Data Port (SCDP) (Not
with Z84013/015)

EEh
EFh

'Through SCRP and SCDP

Control Register 00 - Wait State Control
register (WCR)
Control Register 01 - Memory Wait state
Boundary Register (MWBR)
Control Register02 - Chip Select Boundary
Register (CSBR)
Control Register03- Misc, Control Register
(MCR)

PIO REGISTERS
For more detailed information, please refer to the PIO
Technical Manual. These registers are not in theZ84x13.
Interrupt Vector Word
The PIO logic unit is designed to work with the ZOO CPU in
interrupt Mode 2, The interrupt word must be programmed
if interrupts are used. Bit DO must be a zero (Figure 11).

Iwlwlwl~I~lwl~lwl

identifies Interrupt
Vector
User Supplied Interrupt
Vector

Figure 11. PIO Interrupt Vector Word

458

Mode Control Word
Selects the port operating mode, This word is required and
is written at any time (Figure 12),

this logic function, Bit 06 sets the logic function, bit 05 sets
the logic level, and bit 04 specifies a mask control word to
follow (Figure 14),

~MSK

Identnles MODE
Control Word

Don't Care
Mode Select

a a MODE a

MODEl
10 MODE 2
1 1 MODE3

Figure 12. PIO Mode Control Word

I/O Register Control Word
When Mode 3 is selected, the Mode Control Word is
followed by the I/O Register Control Word This word
configures the I/O register, which defines which port lines
are inputs or outputs, A "1" indicates input while a "0"
indicates output. This word is required when in Mode 3
(Figure 13),
'

1/10

aSets Bn to OUlput

II---I1 -

Identifies Inlets to be cleared.
[2] The port interrupt is not enabled until the interrupt function enabkt
is followed by an actIVe IM1.

Figure 14. Interrupt Control Word

Mask Control Word
This word sets the mask control register, thus allowing any
unused bits to be masked off, If any bits are to be masked,
then bit 04 of the interrupt Control Word is set. When bit 04
of the interrupt Control Word is set, then the next word
programmed is the Mask Control Word, To mask an Input
bit, the corresponding Mask Control Word bit is a "1"
(Figure 15),

1 Sets Btl to Input

Figure 13. I/O Register Control Word
MBO-MB7 Mask Bits, A Bft is
Monftomd for an IntelTUpt II
is Defined as an Input and the
Mask 8ft Is Set to

Interrupt Control Word
In Mode 3 operation, handShake signals are not used
Interrupts are generated as a logic function of the input
signal levels, The Interrupt Control Word sets the logic
conditions and the logic levels required, for generating an
interrupt. Two logic conditions or functions are available:
ANO (if all input bits change to the active level, an interrupt
is triggered), OR (if anyone of the input bits change to the
active logic level, an interrupt is triggered), The user can
program which input bits are to be considered as part of

Figure 15. Mask Control Word

Interrupt Disable Word
This word can be used. to enable or disable a port's
interrupts without changing tile rest of the port's interrupt
conditions (Figure 16).

459

Bit 06. Mode Bit. This bit selects either Timer Mode or
. Counter Mode.
ldentmes Interrupt
Disable Word
Don't COr"
07 = 0 Interrupt Disable
07 • 1 Interrupt Enable

Figure 16. Interrupt Disable Wor~

Bit 05. Prescalor Factor. This bit selects the prescalor
factor for .use in the timer' mode Either divide-by-16 or
divide-by-256 is available.
Bit 04, Clock!Trigger Edge Selector. This bit selects the
active edge of the CLKlTRG input pulses.
Bit 03. Timer Tngger. This bit selects the trigger mode for
timer operation. Either automatic or external trigger maybe
selected.

CTC CONTROL REGISTERS
For more detailed information, refer to the CTC Technical
Manual.
Channel Control Word
This word' sets the operating modes .ahd
parameters as described below. Bit DO is a "1" to indicate
that this is a Control Word (Figure 17).

Bit 02. Time Constant. This bit Indicates that the next word
programmed is time constant data for the downcounter.
Bit 01, Software Reset. Writing 1 to this bit indicates a
software reset operation, which stops counting activities
until another time constant word is written.
Time Constant Word
Before a channel starts counting, it must receive a time
constant word The time constant value is anywhere betwe('ln 1 and 256, with "0" being accepted as a count of 256
(Figure 18). .

Control or Vector
0 .. Vedor
1 _ Control Word
Reset

o=Continued Operation
1 = Software Reset

Time Constant
-0 • No TIme COnstant Follows
1 = TIme Constant Follows
TIme Trigger'

TCO

TCl
TC2

o= Automatic Trigger When

TC3

Time COnstant Is loaded
1 = ClKITRG Pulse Starts Timer

TC4

ClKlTRG Edge Selection
Sete<;ts Failing Edge
1 Selects Rising Edge

TCS
TC6

TC7

Prescaler Value·

1 =Value of 256
0= Value of 16

Mode

Figure 18. CTC Time Constant Word

o Selects TImer Mode
1 Seleets Counter Mode
tnterrupt
1 Enables Interrupt
o Disables IntelTupt

• TImer Mode Only

Figure 17. CTC Channel Control Word

Bit 07. Interrupt Enable. This bit enables the interrupt logiC
so that an internal INT can be generated at zero count.
Interrupts are programmed in either mode and may be
enabled, or disabled at any time.

460

Interrupt Vector Word
If one or more of the CTC channels have interrupt enabled,
then the Interrupt Vector Word must be programmed Only
the five most significant bits of this word are programmed,
and bit DO must be "0". Bits 02-01 are automatically
modified by the CTC channels when it responds with an
interrupt vector (Figure 19).

Read Register 1 t

0= Interrupt Vector Word
1 = Control Word

Channel Identifier

AlISant
,. field Bft In

1 FI!>Id 8ft

(Automatically Inserted

in PreY~ Second Previous,

by CTC)

o 0 ~ Channel 0
o 1 =Channel 1
1 0 = Channel 2
1 1 = Channel 3
Supplied By User

Figure 19. CTC Interrupt Vector Word

I¥e

Byte
3
4
5
6

0
1
0
1
0

1
1
,0

0
0

0
1

8
8

Parity'Error
Ax Overrun Error

SIOREGISTERS

CRClFoaming Error
End of F_,(SDLC)

For more detailed informatidn. refer to the SIO Technical
Manual.
Read Registers. The SIO channel B contains three read
registers while channel A contains only two that are read to
obtain status information, To read the contents of a register
(rather than RRO). the program must first write a pointer to
WRO in exactly the same manner as a write operation, The
next I/O read cycle will place the contents 01 the selected
read registers onto the data bus (Figure 20a. b. c),

• Residue data for eight Ax bitslcha_erprogoammed

Used with special receive condftion mode

Figure 2Ob, 810 Read Register 1
Read RegIster 2 (Channel B Only)

Read Register 0

Rx Character Availab6e

}

~:~~::~n~OM
• Used Wdh "ExtemaVStatus Interrupt' Modes

Figure 20a. SIO Read Register 0

V2t
,V3t
V4

Interrupt
'Vector

V6
,V7

Tx Buffer Empty

Break/Abort

Vlt

INT Pending (Ch. A Only)

OeD

t Variable W"Slatus Affects Vector" is programmed

•

Figure 20c. 510 Read Register 2
Write Registers. The SIO Channel B contains eight write
registers while Channel A contains only seven that are
programmed to configure the operating mode characteristics of each channel. With the exception of WRO. programming the write registers is a two step operation, The
firstoperalion is a pointer written to WROwhich points to the
selected register. The second operation is the actual
control word that is written into the register to configure the
SIO channel (Figure 21)

461

WrRe, Register 1

Iwl~I~I~looloolrnlool

EXTINT Enable
TxlNTEnabie

Status Affects V
Ax

(Ch. B only)

ector

Ax :~ Disable
INT On On First Charilcte
All Rx Che
r
}
IVector)
NT On All Rx Cherecters
raeters (Parity
(Parity Alleets Vector)
Does Not Affect

~lster7

NuUCOde

•

:'nd Abort (SDt.C)
esetEXTISTA
C,t>annel Reset TUS Interrupts

_ _ _ _ _ _ _ _ _~

E_INTonN
Reset TxlNT P~ Ax Cherecter

Error Raset

o o
1
1
1

FlIT

M/aitJReady Function

Return from
, tNT (Ch.AOniy)

M/altlReadyon

•

Or on special

cond~"",

M/aitJReady Enable

NunCode

Ax CRC Check
TxCRCG
er
enenllor

AaseIT. Underru nlEOMLatch
Write Register 3

Iwl~I~lwlooloolrnlool

I ~::=-~...

Address Search Mode (SDLC)
Rx CRC Enable
Enter Hunt Phese

Interrupt

Auto Enables

Vector

o o
o o1
1
1

Ax 5 BItsIC
Ax 7 BUsICheracter
Ax 6 BilslCheracter
Ax 8 BlisiCheracter
heracter

Figure 21. 510 W rite
. Registers

462

Write Register 4

Write Register S

1~lool~I~lool~lrnlool

Parity Enable

o
1

0
1
0

o
o
1
1

1
1

1
0
1

0
1

Sync Modes Enable
1 Slop BitICharacter
1 1/2 Stop BltslCharacter
2 Slop BltslCharacter

TxCRCEnable

/sOlC/CRC 16
Tx Enable

Send Break

8 Bft Sync Charact';"
16 Bft Sync Character
SOlCMode(OIIIII10Rag)
External Sync Mode

0
1

1
1

Tx S BMs (Or less)ICh...acter
Tx 7 BftsiCharacter
Tx 6 BnsICh...acter
Tx 8 Bits/Character
OTR

XI Clock Mode
X16 Clock Mode
X32 Clock Mode
X64 Clock Mode

Write Register 7

Write Register 6

~RTS

Pa1ty Eveni/Odcl

SyncB.O

Sync Bit 8

SyncB.l

Sync Bit 9

SyncBk2

Sync Bit 10

SyncBft3

Sync Bit 11

Sync Bft 4

Sync Bit 12

Sync Bft S

Sync Bit 13

SyncB.6

Sync Bit 14

Sync Bft 7

SyncBll15

•

Also SOlC Address Reid

For SOLC II must be programmed 10 "01111110· for neg racognnlon

Figure 21. SIO Write Registers (Continued)

WATCH DOG CONTROL REGISTERS
There are two registers to control Watch Dog Timer operations. These are Watch Dog Timer Master Register (WDTMR;
I/O Address FOh) and the WOT Command Register
(WOTCR; I/O Address F1 h).Watch Dog Timer Logic has a
"double key" structure to prevent the WOT disabling error,
which may lead to the WOT operation to stop due to
program runaway. Programming the WOT follows this procedure. Also, these registers program the power-down
mode of operation The "Second key" is needed when
turning off the Watch Dog Timer.

EnablingtheWDT. TheWOT is enabled by setting the WOT
Enable Bit (07:WOTE) to "1" and the WOT Periodic field
(05,06:WDTP) to the desired time period. These command bits are in the Watch Dog Timer Master Register
(WDTMR; I/O Address FOh).
Disabling the WDT. The WOT is disabled by clearing WDT
Enable bit (WOTE) In the
MR to "0" followed by writing
"B1h" to the WDT Command Register (WDTCR; I/O Address F1h).

463

Clearing the WOT. The WaT can be cleared by writing
"4Eh" into the WDTCR.
Watch Dog Timer Master Register (WOTMR;l/O address
FOh). This register controls the activities of the Watch Dog
Timer a~d selects power-down mode of operation
(Figure 22):
W01MR (ReadlWrite)
11 11 1 \ 11 11 1 0 11 11

1(VaJue on Power·on Reset)

HALT Mode (HAL1M)
1 0 - STOP Mode
1 1- RUN Mode

~O~~~".1~ ~s~~,r~:fJ)
o

1 - Period Is (ToC x 2 18 )
1 O· Period Is (ToC x 220)
1 1 - Period Is (ToC x 222)

Watch Dog Timer Enable (WOTE)
1 - Enable

1•

Disable

Figure 22. Watch Dog Timer Master Register

Bit 07. Watch Dog Timer Enable (WDTE). This bit controls
the activities of Watch Dog Timer. The WDT can be enabled by setting this bit to "1 ". To disable WDT, write "0" to
this bit followed by writing "B 1h" in the WDT Command
Register. Watch Dog Timer Logic has a "double key" structure to prevent the WDT disabling error, which may lead to
the WDT operation to stop, due to progmm runaway. Upon
Power-on reset, this bit IS setto" 1" and the WDT is enabled.
Bit 06-05. WDr Periodic field (WDTP). This two bit field
determines the desired time period. Upon Power-on reset,
this field sets to "11".

4p4

is
is
is
is

(T cC
(TcC
(TcC
(TcC

* 2 16 )
* 2 18 )
* 220 )
* 222)

00 - IDLE 1 Mode
01 - IDLE 2 Mode
10 - STOP Mode
11 - RUN Mode

Should be "011"

o o· IOLE1 Mode
o 1 - 1DlE2 Mode

00 - Period
01 - Period
10 - Period
11 - Period

Bit 04-03. HAL T mode (HAL TM). This two bit field specifies one of four power-down modes. To change this field,
write "DBh" to the WDT command register, followed by a
write to this register. For detailed descriptions of this field,
please refer to the section "Mode of operations." Upon
Power-on Reset. this field is set to 11, which speCifies
"RUN mode."

Bit 02-00. Reserved. Tl1ese three bits are reserved and
should always be programmed as "011". A read to these
bit returns "011".
Watch Dog Timer Command Register (WOTCR; I/O address Flh). In conjunction with the WDTMR, this register
works as a "Second key" for the Watch Dog Timer. This
register is write only (Figure 23).
Write Blh after clearing WDTE to "0" - Disable WDT.
Write 4Eh - Clear WDT.
Write DBh followed by a write to HALTM - Change
Power-down mode.

WOTCR (Write Only)

o
o

1
0

000

(Bl h) - Disable WOT
(Aher Clearing WOTE)

(4Eh) - Clear WOT

(OBh) - Change HALT Mode
(Followed by setting HAL1M)

Figure 23. Walch Dog Timer Command Register

-----,----~-~~~

INTERRUPT PRIORITY REGISTER
(INTPR; I/O address F4h)
This register (write only) is provided to determine the
interrupt priority for the CTC, SIO and the PIO (Figure 24).
IPR(WrileOnIy)

Ix Ix Ix Ix Ix I I I I
I I I
o
0

01
02 0
o 0
o 1
o 1
1
0
1
0
1
1
1
1

0
00
1
0
1
0
1
0
1

(Value on Powe'-on ReseQ

ZB4X15
High-Low
CTC-SIO-PIO
SIO-CTC-PIO
CTC.pIO-SIO
PIO-SIO-CTC
PIO-CTC-SIO
SIO-PIO-CTC
R...erved
Reeerved

ZB4X13
High-Low
CTC-SIO
SIO-CTC
Reserved
R.....rved
R.....rved
R.....rved
Reeerved
Reeerved

Inl8rlupt
PrIoIIly

Unused

accessed" to the System Control Register Pointer (SCRP,
I/O address EEh), and then accesses the target register
through the System Control Data Port (SCDP, 1/0 address
EFh), The pointer which writes into SCRP is kept until modified.
System Control Register Pointer (SCRP, I/O address EEh)
This register stores the pointer to access System Control
Registers (WCR, MWBR, CSBR and MCR). This register is
Read/Write and it holds the pointer value until modified,
Upon Power-on Reset, all bits are cleared to zero. The
pOinter value, other than OOh to 03h is reserved and is not
written. Upon Power-on Reset, this register is set to "OOh" .
(Figure 25).

SCAP(_rlle)
07
, 0

Figure 24. Interrupt Priority Register

o
o
o

10 10 1 0 1 0 1 0 1 0 1 0 I (ValueonPower-onReset)
0
0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

(OOh) Point ID WCR
(Olh)PoIntIDMWBR
(02h)PolntIDCSBR
(03h) PoIntlD MeR

Bit 07-03. Unused

Figure 25. System Control Register Pointer
Bit 02-00. This field specifies the order of the interrupt daisy chain, Upon Power-on Reset, this field is set to
"000".

000
001
010
OIl
100
101
lID
111

Z84C15
High- Low

Z84C13
High- Low

CTC-SIO-PIO
SIO-CTC-PIO
CTC-PIO-SIO
PIO-SIO-CTC
PIO-CTC-SIO,
SIO-PIO-CTC
Reserved
Reserved

CTC-SIO
SIO-CTC
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

REGISTERS FOR SYSTEM
CONFIGURATION
(The following registers are not available on Z84013/015,)
There are four indirectly accessible registers to determine
System configuration with tre Z84CJ3/C15. These indirectly accessible registers are: Wait State Control Register
(WCR, Control Register OOh), Memory Wait Boundary
Register(MWBR, Control RegisterOlh), Chip Select Boundary Register (CSBR, Control Register 02h) and Misc.
Control Register (MCR, Control Register 03h). To access
these registers, Z84C 13/C 15 writes "register number to be

System Control Data POrt (SCOP, 110 address EFh)
This register is to access WCR, MWBR, CSBR and MCR
(Figure 26).

SCOP (AeadlWrlte)
07

1 ·1
ReadlW,Ke the Reglste,

Pointed by SCPR

Figure 26. System Control Data Port

Wait State Control Register (WCR, Control Register OOh)
This register can be accessed through SCDP with the
pointer value OOh in SCRP (Figure 27). To maintain compatibilitywith the Z8401 3/01 5, the Z84C13/CI5 inserts the
maximum number of wait states (set all bits of this register
to one) for fifteen IMI cycles after Power-on Reset. It
automatically clears the contents of this register (move to
no-wait state insertion) on the trailing edge of the 16th 1M 1
signai unless software has programmed a value. If automatic wait state insertion is needed, the wait state is
programmed within this time period. A read to WCR during
this period will return FFh, unless programmed,

465

WCR (ReadlWrite)

For fifteen /M 1 cycles from Power..on Reset, bits 7-6 are set
to "11" . They clear. to "00" on the trailing edge of tile 16th
/M1 signal unless programmed.

I1I1

ill

I0 I0

01 0

11 11

16 -1M1 Cycles After Power·on Reset Unless Programmed

I0 I0 I

IIOWd
o 0 No Wan Stale
o 1 Two Wd Stales
1 0 Four Wait States
1 1 Six Wait States
Memory Wan
o 0 No Wait Stale
o 1 One Wan Stale
1 0 Two Wan StaleS
1 1 Three Waij Stales
Op-code Fetch Extension
0: No Additional Wait On
Opde Fetch Cycle
1: Add 1 More Wait to
Op-Code Fetch Cycle
Interrupt Vector Wait
/0: No Wait
1: One Waij Stale
Interrupt Daisy Chain Wait
Interrupt
Acknowledge Cycle
o 0 OWanStale
o 1 2 Wait Stales
1 '0 4 Waij Stales
1 1 6 Waij Stales

REl1
Cycle
0 WaitStale
0 Wait Stale
2 Wait Stales
4 Wait Stales

Bit 5. Interrupt Vector Wait. While this bit is set to one, the
wait state generator inserts one wait state after the /IORO
signal goes active during the Interrupt acknowledge cycle.
This gives more time for the vector read cycle. While this bit
is cleared to zero, no wait state is inserted (standard
timing). ror fifteen /M1 cycles from Power-on Reset, this bit
is set to "1", then cleared to "0" on the trailing edge of the
16th /M1 signal, unless programmed.
Bit 4. Opcode retch Extension. If this bit is set to "1", one
additional wait state is inserted during the Op-code fetch
cycle in addition to the number of wait states programmed
in the Memory Waitfield. For fifteen 1M 1 cycles from Poweron Reset, this bit is set to "1", then cleared to "0" on tile
trailing edge of the 16th /M1 signal, unless programmed.
Bit 3-2. Memory Wait States. This 2-bit field specifies the
number of wait states to be inserted during memory Read/
Write transactions.

00 01 10 11 -

No Wait states
1 Wait states
2 Wait states
3 Wait states

Figure 27. Wait State Control Register

This register has ttle following fields:
Bit 7-6. Interrupt Oaisy Chain Wait, This 2-bit field speCifies
the number of wait states to be inserted during an Interrupt
Daisy Chain settle period of the'lnterrupt Acknowledge
cycle, which is/IORO falls after the settling period from 1M 1
going active "0". Also, this field controls the number of wail
states inserted during the RETI (Return From Interrupt)
cycle. ·If specified to insert 4 or 6 wait states during
Interrupt Acknowledge cycle, the Wait state generator also
inserts wait states during RETI fetch sequence. This sequence is formed with two op-code fetch cycles (Op-code
is EOh followed by 40h). It inserts 1 wait state if op-code
followed by EOh is NOT 40h, and inserts 2 or 4 wait states,
respectively, if the following op-code is 40h.

466

Interrupt Acknowledge

RETI cycle

00 - No Wait states
01 - 2 Wait states
10 - 4 Wait states
11 - 6 Wait states

No Wait states
No Wait states
2 Wait states
4 Wait states

For fifteen /M1 cycles from Power-on Reset, these bits are
set to "11", tilen cleared to "00" on the trailing edge of
the16th /M1 signal, unless programmed.
Bit 1-0. I/O Wait states. This 2-bit field specifies the number
of wait states to be inserted during I/O transactions.

00 - No Wait states
01 - 2 Wait states
10 - 4 Wait states
11 - 6 Wait states
For fifteen /M1 cycles from Power-on Reset, these bits are
set to "11", then cleared to "00" on the trailing edge of
the 16th /M 1 signal, unless programmed. For the accesses
to the on-chip I/O registers, no Wait states are inserted
regardless of the programming of this !.ield.
Memory Wait Boundary Register
(MWBR, Control Register 01 h)
This register specifies the address range to insert memory
wait states. When accessed memory addresse$ are within
this range, the Memory Wait State generator inserts Memory
Wait States speCified In the Memory Wait field of WCR
(Figure 28).

MWBR (ReadlWri\e)

I I I I I
0

(Value on Power..,n Reset)

Memory Wait low Boundary
Specifies Lower Boundary
Address (A15-A12) for
Memory Wait Insertion
Memory Watt High Boundary
SpecWies High Boundary
Address (AI5-A12) for
Memory Watt Insertion

03-00. ICSO Boundary Address. Tl1ese bits specify tile
boundary address range for /GSO. /GSO is asserted if tile
address lines A 15-12 l1ave an address value less tl1an or
equal to tile programmed boundary value. Tile /GSO enable bit in the MGR must be set to 1. Upon Power-up reset,
these bits come up as all 1's so tl1at /Gsa is asserted for
all addresses.
Cl1ip Select signals a,re active for tile address range:
/CSO: (03-00 of CSBR) ~ A 15-A 12 ~ 0
/CS1: (07-04 of CSBR) ~ A 15-A12 >
(03-00 of CSBR)

Figure. 28. Memory Wait Boundary Register

Bit 07-04. Memory Wait High Boundary. Tl1is field specifies A 15-A 12 of tile upper address boundary for Memory
Wait.
Bit 03-00. Memory WaitLow Boundary. Tl1is field specifies
A 15-12 of tile lower address boundary for Memory Wait.

Tl1is register is set to "xxxx1111b'" on Power-on Reset,
whicl1 speCifies the address range of /Gsa for "000011 to
FFFFI1'" (all Memory location) and /CS1 "undefined."
Mise Control Register (MCR, Control Register 03h)
This register specifies miscellaneous options on this device (Figure 30),
MCR (ReadlWrite)

Memory Wait states are inserted for tile address range:
(07-04 of MWBR)

A 15-A 12 ~ (q3-DD of MWBR)

This register is set to "FOil'" on Power-on Reset, wl1icl1
specifies tile address range lor Memory Wait as "000011 to
FFFFh'".
Chip Select Boundary Register
(CSBR, Control Register 02h)
Tl1is register speCifies tile address range lor eacl1 cl1ip
select signal. Wilen accessed memory addresses are
witllin this range, chip select signals are active (Figure 29).

1 0 1 0 10 1 0 I 0

I 0

I (Value on Power-on Reset)
ICSO Enable

0= Disable
1 =Enable
ICS1 Enable

0= O.sable
1 = Enable

32-B~ CRC Enable
0= Disable
1 = Enable
Reset Output Disable

o =Reset Output is Enabled
1 == Reset Output is Disabled

Clock Divide-by-one Option

CSBR (ReadlWrite)

o = Oivide-by-two

Ix Ix Ix Ix I I
1

I I
1

1 = Oivide-by-one
(Value on Power..,n Reset)

ICSO Boundary' (A 15-A12 S)

Should Program as ·000·

Figure 30. Mise Control Register

ICS I Boundary

(AI5-A12';; and >/CSO
Boundary)

Bit 07-05. Reserved. These tl1ree bits are reserved and
are always programmed as "000'",

Figure 29. Chip Select Boundary Register

07-04_ ICSt Boundary Address. Tl1ese bits specify tile
boundary address range for /GS1. Tile bit values are
ignored on power-up as tile /GS1 enable bit is off, Tile /GS1
is asserted if tile address lines A15-1211ave an address
value gfeater tl1an the programmed value for /GSO, and
less til an or equal to tile programmed value in these bits.

Bit 04. Clock Divide-by-one option. "O'"-oisable, "l'"-enable. On-chip CGG unit has divide-by-two circuit. By
setting this bit to one, this circuit is bypassed and ClKOUT
is equal to X'tal oscillator frequency (or external clock input
on the XT Al 1 pin), This bit has no effect when the on-chip
CGC unit is not in use and the external system clock is fed
from ClKIN pin. Upon Power-on Reset; this bit is cleared
to 0 and the clock is divided by two,

467

Bit 03. Reset Output'Disable, "0·-Reset'output is enabled,
"1" -Reset output is disabled. This bit controls the /RESET
signal and is driven out when reset input Js used to take the
Z84C13/C15 out of the "Halt" state, The reset pulse is
driven out for 1&cloCk cycles from the falling edge of
/RESET input, unless this bit is set Upon Power-on reset,
this bit is cleared to 0,
Bit 02. 32-Bit GRG enable, "0" -NorlJlal mode (16-bit CRG)
"1 "-32-bit CRC generation/Checking is \lnabled on SIO
Channel A. This bit determines if the 32-bit CRC feature is
enabled on Channel A of the SIO. If this bit is 0, the SIO is
in 'a normal mode of operation, If this bit is set to 1, a normal
CRC generator/checker is replaced with a 32-bit CRC
generator/checker- Upon Power-on Reset, this bit is clear
to "0",
Bit 01. IGS1 Enable, ·O"-Disable, ''1''-Enable, This bit
enables /CS 1 output While this bit is "0", /CS 1 is forced to
"1", While this bit is "1", /CS1 carries the address range
specified in the CSBR upOn Power-on Reset, this bit is
cleared to "0".
Bit 00. IGSO Enable. ·O"-Disable, "t'-Enable. This bit enables /CSO output. While this bit is "0", /CS1 pin is forced

to" 1". While this bit is "1", the /CSO carries address range
specified in the CSBR Upon Power-on Reset. this bit is set
to "1",
Operation modes
There are four kinds of operation modes available for the
IPC in connection with clock generation; RUN Mode,
IDLE1/2 Modes and STOP Mode.
The Operation mode is effective when the HALT instruction
is executed, Restart of the MPU from the stopped state
under IDLE1/2 Mode or STOP mode is affected by inputting either /RESET or interrupt (/NMI or"/INT). The mode
selection of these power-down modes is made by progra~ming the HALTM field (Bit D4-3) of WDTMR.
Setting Halt Mode
Duplicate control is provided to prevent the stopping of the
WDT operation caused by the halt mode setting an error
due to program runaway. As described in the programming section, changing the Halt Mode field of WDTMR is
in two steps. First, write "DBh" to WDTCR followed by a
write to the WDTMR with the value in HALTM. Table 2 has
descriptions of each mode, and Table 3 has device status
in the Halt state.

Table 2. Power-down Modes
(When using on-chip CGC unit; CLKOUT and CLKIN are tied together)

Operation Mode

WDTMR
Bit 04

,BIt 03

RUN Mode

The IPC continues the operation and continuously supplies a clock to
the outside,

IDLE1 Mode

IDLE2Mode

STOP Mode

468

Description at HALT State

The internal oscillator's operation is continued, Clock output (CLKOUT)
as well as internal clock to the CPU. PIO. SIO, CTC and the Watch Dog
Timer is stopped at "0" level of T4 state in the halt instruction operation
code fetCh cycle.
The internal oscillator and the CTC's operation continues and supplies
clock to the outside on the CLKOUT pin continuously, But the internal
clock to the CPU. PIO. SIO and the Watch Dog Timer is stopped at "0"
level of T4 state in the halt instruction operation code fetch cycle.

All operations of the internal oscillator. clock (CLK) output. internal
clock to the CPU. PIO. CTC. SIO and the Watch Dog Timer are stopped
at "0" level of T4 ~tate in the halt instruction operation code fetch cycle.

Table 3. Device status In Han state
(When using on-chip CGC unit; CLKOUT and CLKIN are
tied together)
Mode

CGC CPU CTC PIO

SIO

WDT CLKOUT

IDLE1
IDLE2
STOP
RUN

0
0

X
X
X

X
X

X
X
X

All of the operating modes listed here are valid with crystal
input (Crystal connected between XTAL 1/2 or extemal
clock input on XTAL 1). For the external clock on the CLKIN
pin, only the IDLE2 and RUN modes are applicable.

X
X

O' Operating

X: Stop

TIMING
Basic Timing
The basic timing is explained here with emphasis placed
on the halt function relative to the clock generator The
following items are identical to those for the Z84COO. Ilefer
to the data sheet for the Z84COO.
•

Operation code fetch cycle

•

Memory Read/Write operation

•

Input/Output operation

•

Bus request/acknowledge operation

•

Maskable interrupt request operation

•

Non-Maskable interrupt request operation

•

Reset Operation

RUN Mode (HALTM = 11). Shown in Figure 31 is the basic
timing when the halt instruction is executed in RUN Mode

M1 cycle

"
CLKOUT

Operation When HALT Instruction is Executed. When the
CPU fetches a halt ir;Jstruction in the operation code fetch
cycle, /HALT goes active (Low) in synch with the failing
edge of 14 state before the peripheral LSI and CPU stops
the operation. After this, the system clock generation
differs depending upon the operation mode (RUN Mode.
IDLE 1/2 Mode or STOP Mode). If the internal system clQck
is running, the CPU continues to execute NOP instruction
even in the halt state.

M1 Cycle

IHALT

1M1
HALT OP.Codel
Fetch Cycle... ...

NOP execution

Figure 31. Timing of RUN Mode
(at Halt Instruction Command Execution)

469
.,lJ."."

'''''':.~'.~' .~-"-l'I""""1""I."I~-","",-

_ _ _ '''I-~¥----

In RUN Mode, output from the CGC unit (CLKOUT) is not
stopped and the internal system clock (0) continues even
after ttie halt instruction Is executed. Therefore, until the
halt state is released by the interrupt signal (lNMI or liNn

or IRESETsignal, MPU continu'es to execute HALT il1structions (intemally executing NOP instructions).
IDLE1 Mode (HALTM=OO). Stlown in Figure 32 is the basic
timing when the halt instruction is executed in IDLE 1 Mode.

T4
CLKOUT

0
(Internal
System
Clock)

IHALT

IM1

~L---------t:t---MPU Operation STOP

"1"

HALT Instruction Operation
Code Fetch Cycle

... 1

------Figure 32. IDLEl Mode Timing
(At Halt Instruction Execution)

In IDLE1 Mode, the internal oscillator continues to operate,
but clock output (CLKOUT) is stopped at T4 Low state of
HALT instruction execution. Then all components in the
MPU stop their operation. This mode is not supported

when the CGC unit is inactive and the external clock is fed
from CLKIN pin; CLKOUT should be connected to CLKIN.
IDLE2 Mode (HALTM=01). Shown in Figure 33 is ttle basic
timing when the halt instruction is executed in IDLE2 Mode.

T4
CLKOUT

0
(Internal
System
Clock)

IHALT

IM1

CPU Operation STOP

"1"

HALT Instruction Operation
Code Fetch Cycle

... 1

-------Figure 33. IDLE2 Mode Timing
(At Halt Instruction Execution)

470

tn IDlE2 Mode, tile internal oscillator and clock output
(ClKOUT) continue to operate. The internal system clock,
fed from ClKIN to tile components otller til an CTC is
stopped at tile T4 low state of HALT instruction execution.

STOP Mode (HALTM= 10). Sllown in Figure 34 is the basIc
timing wilen tile Ilalt instruction is executed in STOP Mode

ClK Output STOP

ClKOUT

(Internal
System
Clock)

.._ _ _ _
M_p_U_Op_er_at_io_n_S_T_O_P_ _ __

IHALT

1M1

HALT Instruction Operation
Code Fetch Cycle

Figure 34. STOP Mode Timing
(At Halt Instruction Execution)

In STOP Mode, tile on-cllip CGC unit is stopped at T4 low
state of HALT instruction execution. Tllerefore, clock output (CLKOUT), operation of Watch Dog Timer, CPU, PIO,
CTC, SIO are stopped.
Release from Halt State. The halt state of tile CPU is
released when "0" is input to the IRESET signal and the
MPU is reset or an interrupt request is accepted An
interrupt request signal is sampled at the leading edge of
tile last clock cycle (T 4 state) of NOP instruction. In case
of tile maskable interrupt. interrupt will be accepted tlY an
active liNT signal (,,0" level). Also, tile interrupt enable flip-

flop is set to "1". Tile accepted interrupt process is started
from tile next cycle.
Further, wilen tile internal system clock is stopped (IDLE11
2 Mode, STOP Mode), it is necessary first to restart the
internal system clock. Tile internal system clock is restarted wilen IRE SET or interrupt signal (lNMI or liNT) is
asserted.
RUN Mode (HAlTM=11). The Ilalt release operation is
enabled by interrupt request in RUN Mode (Figure 35).

. 471

HALT Instruction
Execution

·I~

CLKOUT

o
(Internal
System
Clock)

IHALT

NOP Instruction Execution

:I~

Interrupt Process

IM1

I
_____ .L __
I

I
~

cpu Internal
Latch for NMI

IM1

II
Interrupt Sample Timing

Figure 35. Halt Release Operation Timing
By Interrupt Request Signal in RUN Mode

In RUN Mode the internal system clock is not stopped. If
the interrupt signal is recognized on the rising clock edge
of T4 of the continued NOP instruction, CPU will execute
the interrupt process from the next cycle.
The halt release resets CPU in RUN Mode (Figure 36). After
reset, CPU will execute an instruction starting from address OOOOH. However, in order to reset the CPU it is nec-

472

essary to keep /RESET signal at "0" for at least 3 syslem
clock cycles. (For Z84C13/C15: 3 clock cycles if f'leset
output is disabled.) In addition, if jRESET signal becomes
"1", after the dummy cycle for at least two T slates, CPU
executes an instruction from address OOOOH.

Execute Instruction
Address 0000 H

HALT Instruction
Execution

-I

CLKOUT

(Internal - .
System.
~
Clock)

II_II II n.
Y.f-l ~ ~ y.

IHALT

IM1

IRESET

-~--In$------.---'-iG~
Figure 36. Halt Release Operation Timing
By Reset in RUN Mode

IDLE1 Mode (HALTM=OO),IDLE2 Mode (HALTM=01). The,
halt release operation by interrupt signal in IDLE1 Mode is

shown in Figure 37 (a) and in IDLE2 Mode in Figure 37 (b).

473

NOP Instruction Exerution

CLKOUT

(Internal
System
Clock)

IHALT

1M1

INMI

__________

___ t«--

MPU Internal
latch for NMI

liNT

Interrupt S8fll>Iing TIRing

(a) IDLE1 Mode

NOP Command Exerution

CLKOUT

(Internal
System
Clock)

IHALT

~~~----------~

IMl

INMI

_ -5J- - - - - - - - - - - - - -,- - _...r-- MPU Internal
I

liNT

I
I

Interrupt Sa"",ling TiRing

Figure 37. Halt Release Operation Timing By Interrupt
Request Signal in IDLE1/2 Mode

474

Latch for NMI

When receiving /NMI or liNT signals, the stopped internal
system clock starts to feed. In IDLE1 Mode, the IPC starts
clock output on CLKOUT at the same time.
The operation stop of CPU in IDLE2 mode is taking place
at "0" level during T4 state in the halt instruction op-code
fetch cycle. Therefore, after being restarted by the interrupt signal, CPU executes one Nap instruction and samples
an interrupt signal at the rise of T4 state during the
execution of this Nap instruction, and executes the interrupt process from next cycle.

If no interrupt signal is accepted dl,Jring the execution of
the first Nap instruction after the internal system clock is
restarted, CPU is not released from the hall state. It is
placed in IDLE1/2 Mode again at "0" level during T4 state
of the Nap instruction, stopping the internal system clock.
If liNT signal is not at "0" level at the rise of T4 state, no
interrupt request is accepted.
The hall release operation resets the IPC in IDLE1 Mode
(Figure 38a) and in IDLE2 Mode (Figure 38b).

Execution lns1ruction Irom
Address OOOOH

CLKOUT

IZJ
(Internal

Syslem
Clock)

/HALT

1M!

!RESET

(a) IDLE1 Mode
Execution Instruction from
Address OOOOH

CLKOUT

IZJ
(Intema!
System

Clock)

!HALT

L....-_---Ir-

1M!

IRESET

(b) IDLE2 Mode
Figure 38. Halt Release Operation Timing
By Reset in IDLE1/2 Mode

475

When /RESET signal at "0" level is input into the IPC, the
internal ,system clock is restarted and the IPC will exocute
an instruction stored in address OOOOH.

Halt release in STOP Mode (HALTM=1 0) by interrupt. The
halt release operation by interrupt signal in STOP Mode IS
shown in Figure 39.

At time of /RESET signal input, it is necessary to take the
same care as that in resetting the IPC in RUN Mode.

T4
CLKOUT

0
(Internal
System
Clock)

IHALT

NOP Command Execution

IM1

INMI

J
_ -Jf- - - - - - - - - - - - - -

I
_.1 - I

_..r--- MPU Intemal

Latch for NMI

I
I

liNT

Interrupt Sampling Timing

Figure 39. Halt Release Operation Timing By Interrupt
Request Signal in STOP Mode

When the IPC receives an interrupt signal, the internal
oscillator is restarted. To obtain stabilized oscillation,
CLKOUT (and the internal system clock) are started after
. a start-up time of (214+2.5) TcC (TcC' Clock Cycle) by the
internal counter.
CPU executes one NOP instruction after the internal system clock is restarted. At the same time, it samples an
interrupt signal at the rise of T4 state during the execution
of this NOP instruction If the interrupt signal is accepted,
CPU executes the interrupt process operation from the
next cycle.

476

.During interrupt signal input, it is necessary to take tile
same care as the interrupt signal input in IDLE1/2 Mode.
Halt release in STOP Mode (HALTM=10) by IRESET.
When /RESET at "0" level is input into the IPC, the internal
oscillator is restarted. However, the internal clock counter
for warm-up does not operate. Therefore, tile operation is
not carried out properly due to unstable clock oscillation.
It is necessary to hold /RESET at "0" level for sufficient lime.
The halt release operation by the IPC resetting in STOP
Mode is shown in Figure 40.

Z84C13/C15 Only. The fRESET pulse is stretched to
minimum of 16 cycles and driven out ofthe Z84C 13fC15 on
the fRESET pin if Reset output is enabled (bit D3 of MCR is
cleared to "0"). Setting bit 03 disables the driving out of

fRESET. The values in the control registers (WOTMR,
SCRP, WCR, MWBR, CSBR and MCR) are initialized to U18
default value on fRESET.

Executive Instruction from
Address OOOOH

T1
CLKOUT

0
(Internal
System
Clock)

~
IJ

IHALT

1M1

IRESET

Figure 40. Halt Release Operation Timing
By Reset in STOP Mode

Start-up Time at Time of Restart (STOP Mode). When the
MPU is released from the halt state by accepting an
interrupt request, it executes an interrupt service routine
Therefore, when an interrupt request is accepted, it starts
generating clock on the CLKOUT pin, after a start-up time,
by the internal counter [(214+2 5) TcC (TcC'Clock Cycle»).
This obtains a stabilized oscillalton for operation.
Further, in case of restart by the fRESET srgnal, the internal
counter does not operate.

Evaluation operation. Each of the CPU signals (A 15-0,
07-0, fMREO, flORO, fRO, /WR, fHALT, fM1, /RFSH) can
be 3-stated by activating the EV pin. The Z84C13/C15 enhances the counter part by eliminating the requirement of
/BUSREO to go active
Instruction set. The instruction setofthe IPC is the same for
the Z84COO. For details, refer to the data slleet of tile
Z84COO Technical Manual.

ACTIMING
The following section describes the timing of the IPC
The numbers appearing in the figures refer to the parameters on Table A-F.
·CPUTiming
Parameters referenced in Figure 41 tllrough Figure 48
appear in Table A.
The IPC's CPU executes instructions by proceeding through
.
the following specific sequence of operations.

Memory read or write
I/O device read or write
Interrupt acknowledge
The basic clock period is referred to as a Time or Cycle and
three or more Tcycles make upa machine cycle (e.g, MI,
M2 or M3). Machine cycles are extended either by the CPU
automatically inserting one or more Wait states or by tile
insertion of one or more Wait states by the user.

477

Instruction Op-code Fetch. The CPU places the contents of
the Program Counter (PC) on ~he address bus at the start
of the cycle (Figure 41). Approximately one-half clock
cycle later, iMREQ goes active. When active, fRD indicates that the memory data can be enabled onto the CPU
data bus.

·The CPU samples the /WAIT input with the falling edge of
clock state T2. During clock states 1"3 and T4 of an M1
cycle,· dynamic RAM refresh can occur while the CPU
starts decoding and executing the instruction.

IClock

A1S-AO

IMREQ

IRD

fWAIT

IM1
~

External

Memory
Access,
Data in

IRFSH

((« ~I-----I

_____--Ir·

Figure 41. Instruction Op-code Fetch
(See Table A)

478

Memory Read or Write Cydes. Figure 42 shows the timing
of memory read or write cycles other than an Op-code
fetch (/M1) cycle. The /MREQ and fRO signals function like
the Op-code fetch cycle.

In a memory write cycle, fMREQ also becomes active
when the Address Bus is stable. The NJR line·is active
when the Data Bus is stable, so that it can be used directly
as an RNJ pulse to most semiconductor memories.

Clod<

A1S-AO

IMREQ'

/WAIT

...._+-(13

lAO
Read
Operation

07-00
Oataln

---------+----------~~ ~~------~:311}_------~ w-~-------/wR
Write
Operation

07-00

OataOut

______

~~~~;~~-oa-tao-m---

Figure 42. Memory Read or Write Cycle
(See Table A)

479

Input or Output Cydes.. Figure 43 shows the timir1Q for an
I/O read or I/O write operati'on During I/O operations, the
CPU automatically inserts a single Wait state (TWA)' This
extra Wait state allows sufficient time for an I/O port to
decode the address from the port address lines.

When the CPU is accessing the on-chip I/O registers (PIO,
CTC: SIO and system control registers), the data from/to
these registers also appears on the data bus, or data bus
is output during I/O cycle.

Clock

A7-AO

. /lORa

/WArT

lAD
External
VORead
Operation

07-00
Data In

/wR

VOWrite
Operation

07-00
Data In

Read

.
07-00

Operation

Internal {

. Data Out

OUtput Valid
Floating

Note: TWA

=One waR cycle automatically inserted by CPU
Figure 43. Input or Output Cycle
(See Table A)

480

Interrupt Request/Acknowledge Cycle. The CPU samples·
the interrupt signal with the rising edge of the last clock
cycle at the end of any instruction (Figure 44). When an
interrupt is accepted, a special /M1 cycle is generated.

During this /M1 cycle, /IORO becomes active (instead of
/MREO) to indicate that the interrupting device can place
an 8-bit vector on the data bus. The CPU automatically
adds two Wait states to this cycle.

Clock

nNT

A15-AO

1M1

nORO

~--------~~.r---------~ ~--~~'}------+~--~~

/WAIT

07-DO

--_®:c

)----------t(~«<

NOTE: 1) T U
2) TWA

= Last state of any instruction cycle
= Wait cycle automatically inserted by CPU

Figure 44. Interrupt Request/Acknowledge Cycle
.
(See Table A)

481

Non-Maskable Interrupt Request CYcle./NMI is sampled at
the same time as the maskable interrupt input/I NT , but has
higher priority and cannot be disabled under software
control. The subsequent timing is similar to that of a normal

memory read operation except that data put on the bus by
the memory is ignored, The CPU instead executes a restart
(RST) operation and jumps to the /NMI service routine
located at the address 0066H (Figure 45),

- - .... uCycIe - - - t - - - - - - ' - - - - - - - - U 1 - - - - - - - - - - - - - - t

Clock

n
'l1

INMI

A15·AO

---

----------------------------------------- - - - -' -- - - - -------- -' - - ---------PC

1M1

IMREQ

IRO

* Although INMI is an asynch~s input, 10 guarantee its being recognized on the loIlowing machine cycle, INMl's laMing edge
must occur no later than the rising edge 01 the dock cycle preceding the last state 01 any Instruction cycle (T u ),

Figure 45. Non-Maskable Interrupt Request Operation
(See Table A)

482

Bus Request/Acknowledge Cycle. The CPU samples
IBUSREO with the rising edge of the last clock period of
any machine cycle (Figure 46) If IBUSREO is active, the
CPU sets its address, data, and IMREO to Inputs, and
IIORO, IRD and twR lines set to an input for on-chip

peripheral access from an external bus master with the
rising edge of the next clock pulse. At that time, any
external device can take control of these lines, usually to
transfer data b~tween memory and 1/0 devices.

Clock

IBUSREQ

IBUSACK

A15-AO

D7-DO
IMREQ
IRD,IWR
IIORQ,1M1
/HALT, IRFSI:I

Notes:

1) TLM = last state of any M cycle
2) TX = An arbitrary clock cycle used by requesting device

Figure 46. BUS Request/Acknowledge Cycle
(See Table A)

483

Halt acknowledge cycle. Figure 47 shows the timing for
Halt acknowledge cycle.

- - - - - - Ml------_.~I.~-----------------Ml--------------------~.~I••-------- Ml-------~

Clock

IHALT

Halt instruction Received

INMI

~ ~

----------~~~--------~• Although INMI is an asynchronous input, to guarantee its being recognized on the following machine cycle, INMl's falling
edge must occur no later than the rising edge of the clock preceding the last state of any instruction cycle (TLI ).

Figure 47. Han Acknowledge
(See Table A)

Reset Cycle. /RE~ET must be active for at least three clock
cycles for the CPU to properly accept it. As long as /RESET
remains active, the address and data buses float, and the
control outputs are inactive.
Once LRESET goes inactive, two internal T cycles are
consumed before the CPU resumes normal processing
operation. /RESET clears the PC register, so the first
op-code fetch location is OOOOH (Figure 48).

484

Z84C13/C15 Only. If Reset output is disabled, /RESET
must be active for at least three clock cycles for the CPU
to properly accept it. Otherwise, /RESET must be active for
at least two clock cycles and the on-chip reset circuit
extends /RESET Signal to at least a minimum of 16-clock
cycles.

~~-----M1-------

Clock

/RESET

External
/RESET

Input

* /RESET
0u1pUl

(Open drain)

~--------~Y~--------~
Al5-AO

Floating

07-00

~1'

________________

L~!------~--------~~_________

IMREQ

:1~-----------t-Z~~Z~Z~Z~7~------------------~\-~~~~====
I1-iALT

84013115 Only Reset Output Is Enabled

Figure 48_ Reset Cycle
(See Table A)
.

485
" ..".~'" .•.,,-...-.............. ---'''-''-~

"'''''''''~I'''''

..".,." ...." .... ' •. ,," ,' ..-,-",r;-~,'I'"

CGC TIMING
Figure .49 to Figure 52 StlowS the liming related CGC and
Power-On Reset circuit.

Parameters referenced in Figure 49thru Figure 52 appear
in Table B.

2.2V±O.4V

Voo

IAESET

~------~59~------~

Figure 49. Reset on Power-up (Applies only for Z84C13/C15)
(See Table B)

Clock

liNT

INMI

Figure 50. Clock Restart Timing by liNT, INMI (STOP Mode)
(See Table'B)

486

Clock
(IDLE1 Mode)

Clock
(IDLE2 Mode)

INMI

(a) Clock Restart Timing by liNT, INMI (IDLE1/2 Mode)

CLKOUT

!RESET

(b) Clock Restan Timinq by IRES~T (IDLE1/2 Mode)

figure 51. Clock Restart Timing (IDLE1/2 Mode)
(See Table 8)

487

IXTAL1
(For External
Clock Input)

(a) XTAL 1 Timing for External Clock Input

(b) CLKOUT Timing

Figure 52. Clock Timing
(See Table B)
On-chip peripheral access from External Bus master.
The timing for the on-chip I/O device access from the
T 1

TWA

external bus master is shown in Figure 53 This timing also
applies to the liming during EV mOdf' of operation.
T 3

Clock

Address

llORO

IRO

} ~ead

Cycle

07-00

lRO

Valid Data

07-00

1)-------

Ir---t---II---t---------~________ }~ft
,,-

Ir---t---II-----~I)__---------------}~,

tWR.
llORO

07-00

SIO
IWR/(ROY
(WAIT
Mode)
SIO
IWR/IROY
(Ready
Mode)

~
(a) On-chip peripheral 1/0 a<;cess from External Bus master
.
(See Tables C and F)
Figure 53. On-Chip Peripheral Timing from External Bus master

488

SIO

Clock

IM1

IIORO

07-00

lEI

lEO

, (b) Interrupt Acknowledge Cycle Timing for On-chip peripheral from External Bus master
(See Table C)
T1

Clock

1M1

IRD

07-00

lEI

lEO

Figure 53_ On-chip Peripheral Timing from External Bus master (Continued)

489

PIOtiming

(Not applicable on Z84x13) Figure 54 shows the timing for
.
on-chip PIO.

Clock

1I0RO,

IRO

ROY

1818

__________________________

~----------------------_+~

~2 ______________________________~

liNT

Figure 54. PIO Timing
(See Table D)

490
t

CTCTiming
Figure 55 shows the timing for on-chip CTC.

Clock

CLKlTRG

Counter

CLKlTRG

Timer

zcrro

liNT

Figure 55. Countermmer Timing
(See Table E)

491

SIOTiming
Figure 56 shows the timing for on-ctlip SIO.

ICTS, lOCO,
ISYNC

__-.-II

ITxC

ITxD

IWTIIRDY

lINT·

IRxC

RxD

IWTIIRDY

liNT

ISYNC
(External
Sync Mode)

ISYNC
(Output
Mode)

Figure 56. SIO Timing
(See Table F)

492

Watch-Dog Timer Timing
Figure 57 shows the timing for Watch-dog Timer.

elKIN

IWDTOUT

Figure 57. Watch-dog Timer Timing
(See Table H)

PRECAUTIONS
(1) To release the HALT state by IRESET signal in STOP
Mode, hold the IRESET signal at "0" until the output from
the internal oscillator stabilizes.

Z84013/015 Only. To reset MPU, it is necessary to hold
IRE SET Signal input at "0" level for at least three clocks.
Z84C13/C15 Only. If Reset output is disabled, IRE SET
must be active for at least three clock cycles for the CPU
to properly accept it. Otherwise, the on-chip reset circuit
extends IRESET signal to at least a minimum of 16-clock
cycles.

(2) Releasing the MPU from the HALT state by the interrupt
signal in IDLE1/2 Mode and STOP Mode, depends upon
the HALT state and the internal system clock. They will stop
unless an interrupt signal is accepted duCing the execution
of NOP instruction, even when the internal system clock is
restarted by the interrupt signal input. In particular, care
must be taken when liNT is used.

Other precautions are identical to those for the Z84COO.
Refer to the data sheet for the Z84COO.

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings
Voltage on Vcc with respect to Vss ........... -0.3V to + 7.0V
Voltages on all inputs
with respect to Vss .............................. -0.3V to Vcc+0.3V
Operating Arnbient
Temperature ............................ See Ordering Information
Storage Temperature .......................... -65°C to + 150 °C

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at
any condition above those indicated in the operational
sections of these speCifications is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.

493

STANDARD TEST CONDITIONS
The DC Characteristics and capacitance sections below
apply for the following standard test conditions, unless
otherwise noted. AU voltages are referenced to GND (OV).
Positive current flows into the referenced pin.

+5V

2.1 K

Available operating temperature range is:
E = -40°C to 100°C
Voltage Supply Range:
+4.50V ~Vcc ~ + 5.50V

From Output

Under Test o----1~~t---n----4

All AC parameters assume a load capacitance of 100 pf.
Add 10 ns delay for each 50 pf increase in load up to a
maximum of 150 pffor the data bus and 100 pf for address
and control lines. AC timing measurements are referenced
to 1.5 volts (except for clock, which is referenced to the
10% and 90% points). Maximum capacitive load for ClK
is 125 pf.
The Ordering Information section lists temperature ranges
and product numbers. Package drawings are in the Package Information section. Refer to the Literature List for
additional documentation.

CAPACITANCE
Guaranteed by design and characterization

Symbol

494

Parameter

Min

Max'

Clock Capacitance
Input Capacitance
Output Capacitance

35
5
15

pF
pF
pF

Unit

l00pF

Figure 58. Standard Test Load

DC CHARACTERISTICS

Vcc =5.0V ± 10%, unless otherwise specified
Symbol

Parameter

Min

Va.e
V<:JriC
V,HC

Vee-0.6

V'Le

Clock Output High Voltage
Clock Output Low Voltage
Clock Input High Voltage
Clock Input Low Voltage

V,H
V,L
Va.
VOH1

Input High Voltage
Input Low Voltage
Output Low Voltage
Output High Voltage .

2.2
-0.3
2.4

V
V
V
V

Vr:1rl2
Icc1

Output High Vottage
Power Supply Current
XTALIN =10MHz
XTALIN = 6MHz

Vee-0.8 [5]

Max

0.4
Vee-0.6
0.4
Vee
0.8
0.4 [5]

Power Supply Current (IDLE2 Mode)
XTALIN =10MHz
XTALiN = 6MHz
Input Leakage Current

1004

SYNC pin Leakage Current
3-state Output Leakage Current in Float
Darlington Drive Current
(Port Band CTC ZC{fO)

IL(sy)
ILO
IOHO

mA
mA

IJA

6
4

mA
mA

-10

TBD [1]
TBD [1]
10 [4)

-40
-10

10
10 [2]

IJA
IJA

-1.5

. Condition

V
V
V
V

50
30

Power Supply Current (STOP Mode)
Power Supply Current (IDLE1 Mode)
XTALIN =10MHz
XTAUN = 6MHz

1002
Icca

Unit

-2.0mA
+2.OmA

ILO=2.0mA
IOH=-1.6mA
IOH =-25OIJA
Vee=5V
v...,=Vee-0.2V
V,L=02V
Vee=5V
Vee=5V
VIH=Vee-O 2V
Vu..=0.2V
Vee=5V
VIH=Vee-0.2V
Vu..=0.2V
V,N=O 4V 10 Vee

IJA

Va.Jf=OAV to Vee
VQU1=O 4V to Vee
VOH=1.5V
REXT = 390 Ohms

Notes:
(1) Measurements made with outputs floating.
(2) A 15-AO, 07-DO, IMREO, /IORO, /RO and twA
(3) Icc. Standby Current is guaranteed when the /HALT pin is low in STOP mode.
(4) All Pins except XTALI, where ILI =±25tJA.
(5) A 15-AO, 07-DO, IMREO, /lORO, /RO, /WR, /HALT, IM1 and /BUSACK.

. . . -.-_

••• - - - _ . _ . . _

___

_ ..... _ _ _ • _ _ _ _ _ _

" ••••"

'Ow

... "

___

495
_ _ _ _ _ _ _ _ '" . . .

AC CHARACTERISTICS
Table A. CPU Timing (See Figure 41 to 48)

Z84x1306
Z84x1506

Z84x1310
Z84x1510

Symbol

Parameter

Min

Max

Min

Max

Unit

Note

1
2
3
4
5

TcC
TwCh
TwCI
TIC
TrC

Clock
Clock
Clock
Clock
Clock

162'*
65
65

DC
DC
DC
20

100**
40
40

DC
DC
DC
10
10

nS
nS
nS
nS
nS

[Al]
[Al]

6
7
8
9
10

TdCr(A)
TdA(MREOI)
TdCI(MREQf)
TdCr(MREOr)
TwMREOh

Address valid from Clock Rise
Address valid to /MREO Fall
Clock Fall to /MREO Fall delay
Clock Rise to /MREO Rise delay
/MREO pulse width (High)

nS
nS
nS
nS
nS

11
12
13
14
15

TwMREOI
TdCI(MEROr)
TdCI(RDf)
TdCr(RDr)
TsD(Cr)

/MREO pulse width (low)
Clock Fall to /MREO Rise delay
Clock Fall to /RD Fall delay
Clock Rise to fRO Rise delay
Data setup time to clock Rise

16
17
18
19
20

ThD(RDr)
TsWAIT(Cf)
ThWAIT(Cf)
TdCr(M1f)
TdCr(Mlr)

Data hold time after /RD Rise
/WAIT setup time to Clock Fall
/WAIT hold time alter Clock Fall
Clo~k Rise to /Ml Fall delay
Clock Rise to /Ml Rise delay

21
22
23
24
25

TdCr(RFSHf)
TdCr(RFSfjr)
TdCI(RDr)
TdCr(RDI)
TsD(CI)

Clock Rise to /RFSH Fall delay
Clock Rise to /RFSH Rise delay
Clock Fall to /RD Rise delay
Clock Rise to /RD Fall delay
Data setup to Clock Fall during
M2, M3, M4 or M5 cycles

Cycle time
pulse width (high)
pulse width (low)
Fall time
Rise time

26
27
28
29
30

TdA(IOROI)
TdCr(IOROI)
TdCf(IOROr)
TdD(WRf)Mw
TdCI(WRI)

Address stable prior to /IORO Fall
Clock Rise to /IORO Fall delay
Clock Fall to /IORO Rise delay
Data stable prior to /WR Fall
Clock Fall to /WR Fall delay

31
32
33
34
35

TwWR
TdCf(WRr)
TdD(WRf)IO
TdCr(WRI)
TdWRr(D)

/WR pulse width
Clock Fall to /WR Rise delay
Data stable prior to /WR Fall
Clock Rise to /WR Fall delay
Data stable from /WR Fall

36
37
38
39
40

TdCf(HALT)
Clock Fall to /HAL T "0" or "1"
TwNMI
/MNI pulse width
TsBUSREO(Cr) /BUSREQ setup time to Clock Rise
ThBUSREO(Cr) /BUSREO hold time after Clock Rise
TdCr(BUSACKf)
Clock Rise to /BASACK Fall delay

496

90
0**

35**
70
70

55
55
30**

65**
132**

75**
70
80
70

55
65
55

0
60
10

0
20
80
80

65
65

nS
nS
nS
nS
nS

110
100
70
70

80
80
55
55

nS
nS
nS
nS

10'

107**

50**

22**
70

55
75**

70
-55**

55
-10**

50
10**

30**

[A2]

[/\2]

nS
50
55

40**

132**

[Al]
[Al]

65
70

260
60
50
10

nS
nS
nS
nS·
nS

[/\ 1]

90
60
30
10
90

its
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
75 nS

Table A. CPU Timing (Continued)

Symbol

41
42
43
44

TdCf(BUSACKr) Clock Fall to /BASACK Rise delay
TdCr(Dz)
Clock Rise to Data Float delay
TdCr(CTz)
Clock Rise to Control Outputs Float Delay
(lMREO, /IORO, /RD and /WR)
TdCr(Az)
Clock Rise to Address Float delay

TdCTr(A)

46
47
48

TsRESET(Cr)
ThRESET(Cr)
TsINTf(Cr)

Address Hold time from
/MREO, !lORO, /RD or /WR
/RESET to Clock Rise setup time
/RESET to Clock Rise Hold time
/INT Fall to Clock Rise Setup Time

49
50
51
52
53

ThINTr(Cr)
TdM1f(IOROf)
TdCf(IOROf)
TdCf(IOROr)
TdCf(D)

/INT Rise to Clock Rise Hold 1 ime
/M1 Fall to /IORO Fall delay
Clock Fall to /IORO Fall delay
Clock Rise to /IORO Rise delay
Clock Fall to Data Valid delay

54
55
56

TRDf(D)
TMI(D)
TwRESET

/RD Fall to Output Data Valid
/IORO Fall to output data valid
/RESET Pulse Width
013/015, or C13/C15 with RESET
output disabled

TwRESEToe

TwRESETdo

TwRESETpor

. Parameter

/RESET Pulse Width
C13/C15 Only, RESET output Enabled
/RESET drive duration
C13/C15 Only; RESET output Enabled
/RESET drive duration on Power-on
sequence C13/C15 only

Z84x1306
Z84x1506
Min
Max

Z84x1310
Z84x15-10
Min
Max

Unit

90
80

75
65

nS
nS

70
80

65
75

nS
nS

35**

20**

60
10
70

40
10
50

nS
nS
nS

10
359**

10
220"
70
70
130

55
55
110

nS
nS
nS
nS
nS

TBD
TBD

60
70

nS
nS

Note

3TcC

[A3)

2TcC

[A3)

16TcC

[A3)

Notes:

...

For clock period other than the minimum shown, calculate parameters using the formula on Table H.

[A 1) These parameters apply to the external Clock input on ClKIN pin For the cases where external Clock is fed from XTAll,
please refer to Table B.
[A2) For loading >= 5OpF, decrease width by IOnS for each additional 50pF.
[A3) Apply to Z84CI3/C 15 only

497

Table H. Footnote to Table A.

Symbol

Parameter

Z84x1306
Z84x1506

TwCh + TwCl + TrC + TIC
TwCh + TIC
TwCh + TIC
TeC

-50

-20
-30

-20

TeC
TdA(MREOf)
TwMREQh
TwMREQI

26
29
31
33

TdA(IORQf)
TdD(WRf)
TwWR
TdD(WRf)

TeC
TeC
TeC
TwCI + TrC

TdWRr(O)
-TdCTr(A)
TdM1f(IORQf)

TwCl + TrC
TwCI + TrC
2TeC + TwCh + TIC

7
10

45
50

498

-55
-140

Z84x1310

Z84x1510

-25

-30

-50
-60
-25

-140

-60

-55
-50
-50

-30

-40
-30

Table B. CGC Timing (See Figure 49 to 52)

Z84x1306
Z84x1506
No

(Typ )214+ 2.5T cC

(Typ)214+2.5TcC

Clock Restart Time by /NMI

(Typ)214+2.5TcC

Clock Restart Time by /INT
(IDLE Mode)
Clock Restart Time by /NMI
(IDLE Mode)

2.5TcT

ncc

Min

TRST(INT)S
(STOP Mode)
TRST(MNI)S
(STOP Mode)

Clock Restart Time by /INT

TRST(MNI)I

TRST(RESET)I

TfCLKOUT
TrCLKOUT

TcXl

Unit

Parameter

TRST(INT)I

Z84x1510
Min
Max

Symbol

TwlXl

TwhXl

TrXl

TfXl

Z84x1310

Clock Restart Time by /RESET
(IDLE Mode)
CLKOUT Rise Time
CLKOUT Fall time

15
15

XTAL 1 Cycle Time (for External
Clock input on XTAL 1)
Divide-by-two mode
Divide-by-one mode
XT AL 1 Low pulse width
(lor External Clock input
onXTAL1)
Divide-by-two mode
Divide-by-one mode
(CI3/15 only)
XT AL 1 f-!igh Pulse Width
(for External Clock input
on XTALt)
Divide-by-two mode
Divide-by-one mode
(CI3/15 only)
XT AL 1 Rise Time
(for External Clock input
on XTAL1)
XTAL 1 Fall lime
(for External Clock input
on XTAL1)

Max

10
10

Note

nS
nS

81
162

50
100

nS
nS

[82]

35
65

20
40

hS
nS

[B2J

35
65

20
40

nS
nS

[Bl]

Notes:
[81] If parameters 8 and 9 are not met, adjust parameter 11 and 12 to satisfy parameter 8 and 9.
[82] Does not apply to Z84013/015.

499

Table C. Timing for onjchlp peripheral access from external bus master
and daisy chain timing (See Figure 53)

Symbol

Parameter

1
2
3
4
5

TsA(RIf)
TsRI(Cr)
Th
TdCr(DO)
TdRlr(DOz)

Address Setup Time to IRD, IIORO Fall
IRD, IIORO Rise to Clock Rise Setup
Hold time for Specified Setup
,
Clock Rise to Data out delay ,
IRD, IIORO Rise to Data Out float Delay

6
7
8

ThRDr(D)
TsD(Cr)
TdIOf(DOI)

ThIOr(D)'

IM1, /RD, IIORO Rise to Data Hold
Data In to Clock Rise Setup Time
ltORO Fall to Data Out Delay
(INTACK cycle)
IIORO Rise to Data Hold

10
11

ThIOr(A)
ThWlf(Cr)

ThWRr(Cr)

13
14

TsM1f(Cr)
TsMlr(Cf)

TdM1f(IEOf)

16
17
, 18

TsIEI(IOf)
TdIElf(IEOf)
TdIElr(IEOr)

TsIEI(Cr)

20
21

TdCf(IEOr)
TdCf(IEOf)

IIORO Rise to Address Hold
IIORO, IWR setup time to Clock Rise
New parameter
Clock Rise to IJORO, /WR Rise hold lime
New parameter
IM1 Fall to Clock Rise Setup Time
IM1 Rise to Clock Rise Setup Time
(/Ml cycle)
~
IM1 Fall to lEO Fall delay
(Interrupt Immediately Preceding
IMl Fall)

Z84x1310
Z84x1510
Min
Max

40
50
15

60
15
100
75
15

15 .
25

30
95

Unit

Note

nS
nS .
nS
nS
nS
nS
nS
nS

[Cl]

15
20

nS
nS

[C2]

40
-15

nS
nS

140

160

lEI to Clock Fall Setup
(For 4D Decode)
Clock Fall to lEO Rise Delay
Clock Fall to lEO Rise Delay

, 290

[CI) For 110 write to Pia, CTC and SIO.
[C2] For 110 Write to system control registers.
[C3] For daisy chain timing, please refer to the note on page 63.

80
60

lEI to IIORO Fall Setup Time
(INTACK cycle')
lEI Fall to lEO Fall delay
lEI Rise to lEO Rise Delay
(After ED decode)

Noles:

500

Z84x1306
Z84x1506
Min
Max

120

100

n.8

[C3]

nS
nS

[C3]
[C3]

150

[C3]

nS
nS

50
90

Table D. PIO Timing (Z84x15 only) (See Figure 54)

Z84x1506
Min
Max

Symbol

Parameter

TsIOr(Cr)

IIORO Rise to Clock Fall Setup Time
(To Activate RDY on Next Clock Cycle)
Clock Fall to RDY Rise delay
Clock Fall to RDY Fall delay
IS16 Pulse Width

100

2
3
4

TdCf(RDYr)
TdCf(RDYf)
TwSTB

TsSTBr(Cr)

6
7
8

TdIOr(PD)
TsPD(STBr)
ThPD(STBr)

IST8 Rise to Clock Fall Setup Time
(To Activate RDY on Next Clock Cycle)
IIORO Rise to Port Data Stable Delay (Mode 0)
Port Data to ISTB Rise Setup Time (Mode 1)
Port Data to ISTB Rise Hold Time (Mode 1)

9
10
11
12

TdSTBf(PD)
TdSTBr(PDz)
TdPD(INTf)
TdSTBr(INTf)

ISTB Fall to Port Data stable (Mode 2)
ISTB Rise to Port Data Float Delay (Mode 2)
Port Data Match to liNT Fall Delay (Mode 3)
ISTB Rise to liNT Fall Delay

Z84x1510
Min
Max

Unit

Note

nS
nS
nS
nS

[D2]
[D2]
[Dl]

100
115
115

100
100
100

100

100
140

140
15

120
75
15

150
140
250
290

120
120
200
220

nS
nS
nS
nS

[D2]
[D2]

nS
nS
nS
nS

[D2]

Unit

Note

Noles:
[Dl] For Mode 2: TwSTB > TsPD(STB).
[D2] Increase these values by 2nS for lOpF increase in loading up to l00pF Max.

Table E. CTC Timing (Figure 55)

Symbol

Parameter

1
2

TdCr(INTf)
TsCTRr(Cr)c

Clock Rise to liNT Fall delay
CLK/TRG Rise to Clock Ril>e
Setup time for Immediate Count

TsCTR(Ct)

TdCTRr(lNTf)

Z84x1306
Z84x1506
Min
Max
(TcC+l00)

CLK/TRG Rise to Clock Rise
Setup time for enabling of
Prescalor on following Clock Rise
CLK/TRG Rise to liNT Fall Delay
TsCTR(C) satisfied
TsCTR(C) not satisfied

5
6
7

TcCTR
TwCTRh
TwCTRI

CLK/TRG cycle time
CLK/TRG Width (Low)
CLK/TRG Width (High)

8
9
10
11

TrCTR
TfCTR
TdCr(ZCr)
TdCf(ZCf)

CLK/TRG Rise Time
CLK/TRG Fall Time
Clock Rise to ZC/TO Rise Delay
Clock Fall to ZC/TO Fall Delay

Z84x1310
Z84x1510
Min
Max

[E2]

[El]

nS
nS

[E2]
[E2]

nS
nS
nS

[E3]

(36)+(38)
(1)+(36)+(38)
i

[El]

(TcC+80)

(2TcC) DC
DC
90
DC
90

30
30
80
80

(36)+(38)
(1 )+(36)+(38)
(2TcC) DC
90
DC
DC
90
30
30
80
80

nS
nS
nS
nS

Noles:
[El] TImer Mode.
[E2f Counter Mode.
[E3] Counter Mode Qnly; when using a cycle time less than 3TcC, parameter #2 must be met.

501

--~"""'i"""

'·-~"'''''''''''''''''--~'-'"!l.....-.-rn'!r."::;rll';W, ....~~ .. ,:",.~1''''"'''~~''~'''''''~''''''''''_ _~_'''f'I'''_''''~'''''~IM_1iII'

_"_f4. . . . . . .

....

"'l'".,~,I""' "'::·n,,,'~I'

Table F. 510 Timing (See Figures 53(a) and 56}

Symbol

Parameter

Z84x1306
Z84x1506
Min
Max

1
2
3
4
5

TwPtl '
TwPI
TcTxC
TwTxCI
TwTxCh

Pulse Width (High)
Pulse Width (Low)
/TxC Cycle Time
/TxC Width (High)
/TxC Width (Low)

150
150
250
85
85

6
7
8
9

TrTxC
TfTxC
1 dTxCf(TxD}
TdTxCf(W/RRf}

/TxG Rise Time
/TxC Fall Jime
/TxC Fall to TxD Delay
/TxC Fall 10jIN//RDY Fall Delay
(Ready Mode)

10
11
12
13
14

TdTxCf(INTf}
TcRxC
TwRxCh
TwRxCI
Trr1XC

/TxC Fall to /INr'Fall Delay
/RxC Cycle 1 ime
/RxC Widlh (High)
IRxC Width (Low)
/RxC Rise Time

15
16

TfRxC
TsRxD(RxCr}

TIlRxCr(RxD}

/RxC Fall Time
RxD to /RxC Rise Setup lime
(Xi mode)
/RxC Rise to RxD Hold Time
(Xl Mode)

18 . TdRxCr(W/RRf}
19
20

T.dRxCr(INTf}
TdRxCr(SYNCf}

TsSYNCf(RxCr)

TdIOf(W/Rf}

TdCr(W/Rf)

TdCf(W/Rz)

5
250
85
85

Note

120
120
200
80
80

nS
nS
nS
nS
nS

[Fl]

5
200
80
80

/SYNC Fall to /RxC Rise Setup
(External Sync Modes)
/IORQ Fall or valid address to
/W//RDY Delay (Wait Mode)

60
60
120
9

nS
nS
nS
TcC

TcC
nS
nS
nS
nS

nS
nS

TcC

13
7

10
4

13
7

TcC
TcC

-100

Clock Rise to /WI/RDY Delay
(Ready Mode)
Clock Fall to /W//RDY Float Delay
(Wait Mode) l

Notes:
[Fl] In All Modes, the System Clock rate must be at least five times the maximum data rate.
[F2] Para':"9ters 22 to 24 are on Figure 53(a).

502

Units

/RxC Rise to /WI/RDY Fall Delay
(Ready Mode)
/RxC Rise to /INT Fall Delay
/RxC Rise to /SYNC Fall Delay
(Output Modes)

. 60
60
160
9

Z84x1310
Z84x1510
Min
Max

-100

[F1]

[F2]

130

110

[F2]

Table G. Watch Dog Timer Timing (See Figure 57)
No

Symbol

Parameter

1
2
3

TdC(WDTI)
TwPI
TcWDT

Clock Rise to /WDTOUT Fall Delay
Clock Rise to /WDTOUT Rise Delay
/WDTOUT Cycle Time
WDTP=OO
WDTP = 01
WDTP = 10
WDTP = 11

Min

Max

Min

160
165
(lyp)2'6TcC
(Typ)2'8TcC
(Typ)220TcC
(Typ)222TcC

(Typ)2'6TcC
(T yp )2'8 rcC
(Typ)220TcC
(Typ)222TcC

Max

160
165

nS
nS

nS
nS
nS
nS

Noles:
•

In All Modes. the System Clock rate must be at least five times the maximum data rate.
RESET must be active a minimum of one complete clock cycle.
[1] Units equal to System Clock Periods.
[2] Units in nanoseconds (nS).

Additional information for note [e3]
Parameter #15.16.17 and 18 of Table C. These parameters are daisy chain timing and calculated values, and vary
depending on the inside daisy chain configuration, which
is specified in the Interrupt Priority Register. Inside the IPC,
the daiSY chain can be figured as follows:

lEO

Figure 59. Internal Daisy Chain Configuration

10MHz

6MHz
No

Parameter

15
16

TdM1(IEO)
TsIEI(IO) (PIO at #3)
(CTC at #3)
(SIO at #3)
TdIEI(IEOf)
TdIEI(IEOr)

17
18

To calculate IPC daisy chain timing, it can be treated as if
there are Z80 PIO, CTC and SIO with Input buffer and look
ahead circuit on the chain Following are the calculation
formulas:
Parameter #15, /M1 falling to lEO delay
TsM1 (lEO) = Max[ TdM1 (10)#1 "TdM1 (10)#2, TdM1 (10)#3]
+ (look-ahead gate Delay)
Parameter #16, lEI to /IORO falling setup time
TsIEI(IO) = TdIEI(IEO)#1 + TdIEI(IEO)#2 + TsIEI(10)#3 +
(Input Buffer delay)

Min

Max

Min

Max
100nS

160nS
140nS
160nS
160nS

230nS
280nS
290nS
120nS
290nS

70nS
150nS

Parameter #18, lEI rising to lEO rising delay (Alter ED
decode)
TdIEI(IEOr) = TdIEI(IEOr)pIO+ TdIEI(IEOr)CTC +
TdIEI(IEOr)SIO + (Input Buffer delay) + (look-ahead gate
Delay)
* Where TdIEI(IEO) is worse number between TdIEI(IEOr)
and TdIEI(IEOf)
Numbers to calculate these parameters lor the above
formulas are on the next page.

Parameter #17, lEI falling to lEO falling delay
TdIEI(IEOf) = Max[TdIEI(IEOI)PIO, TdIEI(IEOI)CTC,
TdIEI(IEOf)SIO] + (Input Buffer delay) + (look-ahead gate
Delay)

503

6MHz
Min
Input Buffer delay
Look ahead gate delay

10nS
10nS

6MHz

PIO part
Min

TdMl(IEO)
TsIEI(IO)
TdIEI(IEOf) .
TdIEI(IEOr)

10MHz

Max

10nS
10nS

Max

PIO part

Max
60nS
SOnS
SOnS
SOnS

If using an interrupt from only a portion of the IPC, these
numbers are smaller than the values shown above. For
more details about the "Z80 Daisy Chain Structure," please

504

10MHz
Min

CTCpart
Min

90nS
90nS
lOOnS
130nS

Min
TdMl(IEO)
TsIEI(IO)
Tr.JiEI(IEOf)
TdIEI(IEOr)

Max

SIO part

Max

Min

150nS
70nS
50nS
SOnS

130nS
lOOnS
90nS
90nS

CTC part
Min

Max

SIO part

Max
60nS
70nS
SOnS
SOnS

Min

Max
90nS
SOnS
30nS
.30nS

refer to the Application Note "Z80 Family Interrupt Structure" included in the Z80 Data book.

~ZiIill

PRODUCT SPECIFICATION

Z8440/1/2/4,
Z84C40/1/2J3/4
1SERIAL

INPUT/OUTPUT CONTROLLER

FEATURES
• Two independent full·duplex channels, with separate
control and status lines for modems or other devices.

• Data rate in the x1 clock mode of 0 to 1.6M bits!
second with a 8.0 MHz clock.
• NMOS version for high cost performance solutions,
CMOS version for' the designs requires low power
, consumption.
• NMOSZ0844x04-4 MHzZ0844x06- 6.17 MHz (Where
x is the designator for the boncfmg option; 0,1,2 or 4)
• CMOS Z84C4x04 - DC 4 MHz Z84C4x06 - DC to 6.7
MHz Z84C4xOa - DC to a MHz (Where x is the designator for the bonding option; 0, 1, 2 or 3, 4)
• 6 MHz version supports 6.144 MHz CPU clock operation.

• Asynchronous protocols: everything necessary for
complete messages in 5, 6, 7, or 8 bits/character.
Includes variable stop bits and several clock-rate
multipliers; break generation and detection; parity;
overrun and framing error detection.
• Synchronous protocols: everything necessary for
complete bit- or byte-oriented messages in 5, 6, 7, or 8
bits/character, including IBM Bisync, SOLC, HOLC,
CCITT-X,25 and others. Automatic CRC generation/
checking, sync character and zero insertion/deletion,
abort generation/detection, and flag insertion,
• Receiver data registers quadruply buffered, transmitter
registers doubly buffered.
•

Highly sophisticated and flexible daisy·chain interrupt
vectoring for interrupts without ex~ernallogic.

GENERAL DESCRIPTION
The zao SIO (here in after referred to as the zao SIO or,
SIO). Seriallnput/Output Controller is a dual-channel data
communication interface with extraordinary versatility and
capability. Its basic functions as a serial-to-parallel, para!lel-to-serial converter/controller can be programmed by a
CPU for a broad range of serial communication applications.
The device supports all common asynchronous and
synchronous protocols, byte· or bit·oriented, and performs
all of the functions traditionally done by UARTs, USARTs,
and synchronous communication controllers combined,
plus additional ,functions traditionally performed by the
CPU. Moreover, it does this on two fully-independent

channels, with an exceptionally sophisticated Interrupt
structure that allows very fast transfers.
Full interfacing is provided for CPU or OMA control. In
addition to data communication, the circuit can handle
virtually all types of serial 1/9 With fast, or slow, penpheral
devices. While designed primarily as a member of the Z80
family, its versatility makes It well suited to many other CPUs.

The Z80 SIO uses a single +5V power supply and the
standard zao family single-phase clock: The SIOIO, SIOI1,
and SIO/2 are packaged in a 4G-pin DIP, the S10/4 is
packaged in a 44-pin PCC and the SI0I3 is packaged in a
44-pin QFP. Note that SIO/3 is only available in CMOS and
in QFP package.

PIN DESCRIPTION
Figures 1 through 6 illustrate the three 40'pin configurations
(bonding options) available in the Z80C SID (hereafter
referred to as SID or Z80 SID). The constraints of a 40-pin
package make it impossible to bring out the Receive
Clock (RxC), Transmit Clock (TxC), Data Terminal Ready
(OTR) and Sync (SYNC) signals for both channels. There·
fore, either, Channel B lacks a signal or two signals are
bonded together:
• Z80 S10/2 lacks SYNCB
• Z80 S10/1 lacks OTRB

• Z80 SIO/O has all four signals, but TxCB and RxCB are
bonded togefher

The 44-pin package, the zao SIO/4 for PLCC package, and
zao S10/3 for QFP, has all options (Figure 7a and 7b).
The first bonding option above (SI0/2) is the preferred
version for most applicatibRs. The pin descriptions are as
follows:

B/A. Channel A or B Select (input, High selects Channel B).
This input defines which channel is accessed dunng a data
505

CPU
DATA
BUS

CONTROL
FROM
CPU

-----

--'--

RxDA

RxCA

TxDA

TxCA

SYNCA

W,Ri'5YA

0,
RTSA

CTSA

zao

51012

CHANNEL A

...

~}~

iffi!A _
DCDA

lORa

RxDS

RxeB

lEI

CONTROL

CIO

B/A

IORO

lEO

BIA

CIO

W/AOVA
$VNCA

Ail
GNO
W/ADYB

RxDA

RxDS

RxCA

Rxes

TxCB

TxCA

TxCB

W/ROYS

TxOA

Tx08

DTRA

DTRB

Tx08

RlSB

INTERRUPT
CONTROL

+5V

INT

RESET

.....{
CHAIN

CHANNEL B

~}.~

INT

CTSB

lEI

_
DTRB

lEO

DCDS

CONTROL

RT$A

Am!

CTSA

CTse

DeoA
ClK

OCOB
RESET

l l t

+5V

GNO

ClK

Figure 2. 40-pin Dual-In-Line Package (DIP),
Pin Assignments

Figure 1. Pin Functions

CPU
DATA
BUS

CONTROL
FROM
CPU

~'''l

CHAIN
INTERRUPT
CONTROL

--------

RxDA

RxCA

TxOA

TxCA

SYNCA

W/RDYA

0,
0,

RTSA

zao

CE
RESET

51011

-- }

eTSA DTAA
DCDA

CHANNEL A

lEI

lORD

lEO

alA

c/o

'+5V

Ail

RxDS

W/RDVA

lORD

RxeB

SYNCA

TxOB

RxDA

TxCB

RxCA

AxOS

SYNCB

TxCA

Rxes

TxDA

TxCB

CIO

WIROYB

B/A

Alsa

iNT

erss

' _ lEI

:--

, OCOB

CHANNELB

}~...

CONTROL

lEO

l t

GNO

GNO
WlROYB
SYNCa

DTRA

TxDB

RTSA

RfID'j

CTSA

crsa

OCOA

DCOS

ClK

+5V

RESET

ClK

Figure 3. Pin Functions

Note: Power connections follow
conventi9nal descriptions below:
Connection Circuit

506

iNf

MODEM
CONTROL

Device

Power

V""

Voo

Ground

GND

Vss

Figure 4. 40-pin Dual-In-Line Package (DIP),
Pin Assignments

_D,
D~~~
BUS

D,
_D,

_D,
_D,

D, •

_D,

iNf

10RO

;:e

. lEI

_CE
_

RESET

_81l1

INTE:::~

1
-

CONTROL

liD
GND

SYNCA

AD
------. C/O

DAISY

CID

WI/llIVlI

_iORa

CPU

B/A

iil
+5V

- - - . . M1
CONTROL
FROM

lEO

iNT
lEI
lEO

WIRDY8

RxDA

SYNC8

RxCA
TxCA

RxlXCB

AxOB

TxDA

TxOS

DTRA

DTR8

IIfSl\

RfSB

CTSl\

CTS8

DCDA

DCDa
RESET

CLK

'--""'I'"'""--r-r--....
+5V

Figure 5. Pin Functions

Figure 6. 40-pln Dual-In-Llne Package (DIP).
Pin Assignments

~ 6allja"aaoDW,§DfO~l~

•

lEI
leO

BlA
clI5

iii

AD
36

+5V

W'1iiiYA

GND

RxDA

iii
+5V

ZS4C43
C-MOS ZSO

51014

(TOp View)

RiCA
TxCA

lEI
lEO

W/RDVA

zao

SYNCA

-33

6 5 4 3 2 1 4443424140

510/3
(Top View)-

RxDA

RiCA

TxCA

TxDB

TxDA
NC

TxDA

18192021222324 25262728

I~ ~~i ~lal~lllm~
Figure 7a. 44-pin Chip Carrier,
Pin Assignments

Figure7b. 44-pin Quad Flat Pack
Pin Assignments

transfer between the CPU and the SIO. Address bit Ao from
the CPU is often used for the selection function.

C/O. Control or Data Select (input, High selects Control).
This input defineslhe type of information transfer performed
between the CPU and the SIO. A High at this input during a
CPU write to the SIO causes the information on the data bus
to be interpreted as a command for the channel selected by
BfA. A Low at cii5 means that the information on the data
bus is data. Address bit A, is often used for this function.

~~~~~--~-'

_____

"'-"~"''''''''''''''-.''"~''''"":-

CEo Chip Enable (Input, active Low). A Low level aUhis input
enables the SIO to accept command or data input from the
CPU during a write cycle, or to transmit data to the CPU
during a read cycle.
ClK. SyStem Clock (input). The SIO uses the standard zac
System Clock to synchronize internal signals. This is
single-phase clock.

507
-,

---.-.---"--~-----~--~----~~

...--,:",,- ..'

CTSA, CTSB. Clear To Send (inputs, active Low). When
programmed as Auto Enables, a Low on these inputs
enables the respective transmitter. If not programmed as
Auto Enables, these inputs may be programmed as
general-purpose inputs. Both inputs are Schmitt-trigger
buffered to 'accommodate slow-risetime signals. The SIO
detects pulses on these inputs and interrupts the CPU on
both logic level transitions. The Schmitt-trigger buffering
does notguarantee a specified noise-level margin.

00.07. System Data Bus (bidirectional, 3-state). The system
data bus transfers data and commands between the CPU
SIO. Do is the least significant bit.
and the

zao

DCDA, DCDB. Data Carrier Detect (inputs, active Low).
These pins function as receiver enables if the SIO is
programmed for Auto Enables; otherwise they may be used
as general-purpose input pins. Both pins are Schmitt-trigger
buffered to accommodate slow-risetime signals. The SIO
detects pulses on these pins and interrupts the CPU on both
logic level transitions. Schmitt-trigger buffering does not
guarantee a specific noise-level margin.
DTRA, DTRB. Data Terminal Ready (outputs, active Low).
These outputs follow the state programmed into the
SIO. They can also be programmed as general-purpose
outputs.

zao

In the

zao 810/1 bonding option, OTRB is omitted.

lEI. Interrupt Enable In (input, active High). This signal is
used with lEO to form a priority daisy chain when there is
more than one interrupt-driven device. A High on thiS line
indicates that no other device of higher priority is being
serviced by a CPU interrupt service routine.

lEO. Interrupt Enable Out (output, active High). lEO is High
only if lEI is High and the CPU is not servicing an interrupt
from this SIO. Thus, this signal blocks lower priority devices
from interrupting while a higher priority device is being
serviced by its CPU interrupt service routine.
INT. Interrupt Request (output, open drain, active Low).
When the SIO is requesting an interrupt, it pulls INT Low.

. IORQ. Input/Output Request (inpu~rom~PU, active Low).
10ROis used in conjunction with BIA, CIO, CE, and RD to
transfer commands and data between the CPU and the SIO.
When CE, RD, and 10RO are all active, the channel selected
by BIA transfers data to the CPU (a read operation). When
CE and 10RO are active, but RO is inactive, the channel
selected by BIA is written to by the CPU ~ith either data or
control information as specified by C/O. As mentioned
previously, if 10RO and M1 are active simultaneously, the
CPU is acknowledging an interrupt and the SIO
automatically places its interrupt vector on the CPU data bus
if it is the highest priOrity device requesting an interrupt.

zao

M1. Machine Cycle One(input from
CPU, active Low).
When M 1 is active and RD is also active, the
CPU is
fetching an instruction from memory; when M 1 is active

50a

zao

while 10RO (s active, the SIO accepts M 1 and 10RO as an
interrupt acknowledge if the SIO is the highest priority
device that has interrupted the

zao cpu.

RxCA, RxCB. Receiver Clocks (inputs). Receive data is
sampled on th.e rising edge of RxC. The Redeive Clocks
may be 1, 16,32, or 64 times the data rate in asynchronous
CTC
modes. These clocks may be driven by the
Counter Timer Circuit for programmable baud rate
generation. Both inputs are Schmitt-trigger buffered; no
noise level margin is specified.

zao

In the
SIOIO bonding option, RxCB is bonded together
with TxCB.
RD. Read Cycle Status (input from CPU, active Low). If RO is
active, a memory or 110 read operation is in progress. RD is
used with BIA, CE, and 10RO to transfer data from the SIO
to the CPU.
RxDA, RxDB. Receive Data (inputs, active High). Serial
data at TTL levels.
RESET. Reset (input, active Low). A Low RESET disables
both receivers and transmitters, forces TxOA and TxOB
marking, forces the modem controls High, and disables all
interrupts. The control registers must be rewritten after the
SIO is reset and before data is transmitted or received.
RTSA, RTSB. Request To Send (outputs, active Low).
When the RTS bit in Write Register 5 (Figure 14) is set, the
RTS output goes Low. When the RTS bit is reset in the
Asynchronous mode, the output goes High after the
transmitter is empty. In Synchronous modes, the RTS pin
strictly follows the state of the RTS bit. Both pins can be used
as general-purpose outputs.
SYNCA, SYNCB. Synchronization (bidirectional, active·
Low). These pins can act either as inputs or outputs. In the
asynchronous receive mode, they are inputs similar to CTS
and OCO. In this mode, the transitions on these Hnes affect
the state of the SynclHunt status bits in Read Register 0
(Figure 13), but have no other function. In the External Sync
mode, these lines also act as inputs. When external
synchronization is achieved, SYNC must be driven Low on
the second rising edge of RxC after that rising edge of RxC
on which the last bit of the sync character was received. In
other words, after the sync pattern is detected, the external
logic must wait for two full Receive Clock cycles to activate
the SYNC inRut. Once SYNC is forced Low, it should be kept
Low until the CPU informs the external synchronization
detect logic that synchronization has been lost or a new
message is about to start. Character assembly begins on
the rising edge of RxC that immediately precedes the falling
edge of SYNC in the External Sync mode.
In the internal synchronization mode (Monosync and
Bisync), these pins act as outputs that are active during the
part of the receive clock (RxC) cycle in which sync
characters are recognized. The sync condition is not
latched, so these outputs are active each time a sync pattern

is recognized, regardless of character boundaries.
In the Z80 SI0/2 bonding option, SYNCB is omitted.

lXCA, lXCB. 7i'ansmitter C/ooks (inputs). In asynchronous
modes, the Transmitter Clocks may be 1, 16,32, or 64 times
the data rate, however, the clock multiplier must be the same
for the transmitter and the receiver. The Transmit Clock
inputs are Schmitt-trigger buffered for relaxed 'rise- and
fall-time requirements; no noise level margin is specified.
Transmitter Clocks may be driven by the Z80 CTC Counter
Timer Circuit for programmable baud rate generation.

In the Z80 SIOIO bonding option, TxCB is ,bonded together
with RxCB.

TxOA, TxOB. 7i'ansmit Data (outputs, active High). Serial
data at TTL levels. TxD changes from the falling edge of TxC.

W/ROYA, iN/ROYB. WaitiReady(outputs, open drain when
programmed for Wait function; driven High and Low when
programmed for Ready function). These dual-purpose
.outputs may be programmed as Ready lines for a DMA
controller or as Wait lines that synchronize the CPU to the
SIO data rate. The'reset state is open drain.

509

FUNCTIONAL DESCRIPTION
The functional capabilities of the l80 SIO can be described
from two different points of view: as a data communications
device, it transmits and receives serial data ih a wide variety
of data-communication protocols; as a l80 family
peripheral,it interacts with the l80 CPU and other
peripheral circuits, sharing the data, .address and control
buses, as well as being a part of the l80 interrupt structure.
As a peripheral to other microprocessors, the SIO offers
valuable features such as non-vectored interrupts, polling,
and simple handshake capability. Figure 8 is a block
diagram.
DATA

Figure 9 illustrates the conventional devices that the SIO
replaces.
-

CONTROL

The first part of the following discussion covers SIO
data-communication capabilities; the second part
describes interactions between the CPU and the SIO.

SERIAL
I DATA
ICHANNEL
CLOCKS

INTERRUPT {
CONTROL
LINES

SYNC
WAIT/READY

Figure 8_ Block Diagram

UART

CHANNEL
A
SYNCHRONOUS
COMMUNICATIONS
CONTROLLER

MICROPROCESSOR {
INTERrACE

...0----1

UART

CHANNEL
B
SYNCHRONOUS
COMMUNICATION
CONTROLLER

MICROPROCESSOR
INTERFACE
--

zaG
SIO

CHANNEL
A
CHANNEL
B

Figure 9_ Conventional Devices Replaced by the Z80 SIO

510

DATA COMMUNICATION CAPABILITIES
The SIO does not require symmetric transmit and receive
clock signals, a feature that allows It to be used with a Z80
CTC or many other clock sources. The transmitter and
receiver can handle data at a rate of 1, 1/16, 1/32, or 1/64 of .
the clock rate supplied to the receive and transmit clock
Inputs.

The SIO provides two independent full-duplex channels that
can be programmed for use in any common asynchronous,
or synchronous data-communication protocol. Figure 10a
illustrates some of these protocols. The following is a short
descnption of them. A more detailed explanation of these
modes can be found In the zao SIO Technical Manual
(03-3033-01 ).

In asynchronous modes, the SYNC pin may be
programmed as an inputthat can be used for functions such
as monitoring a nng indicator.

Asynchronous Modes. Transmission and reception can
be done independently on each channel with five to eight
bits per character, plus optional even or odd panty. The
transmitters can supply one, one-and-a-half, or two stop bits
per character and can provide a break output at any time.
The receiver break-detection logiC interrupts the CPU both
at the start and end of a received break. Reception is
protected from spikes by a transient spike-rejection
mechanism that checks the signal one-half a bit time after a
Low level is detected on the receive data Input (RxDA or
RxDB in Figure 5). If the Low does not persist, as in the case
of a tranSient, the character assembly process IS not started.

Synchronous Modes. The SIO supports both byteoriented and bit-orien~ed synchronous communication.
Synchronous byte-oriented protocols can be handled in
several modes that allow character synchronization with an
8-bit sync character (Monosync), any 16-bit sync pattern
(BI!;ync), or with an external sync signal. Leading sync
characters can be removed without interrupting the CPU.
Flve-, six-, or seven-bit sync characters are detected with 8or 16-bit patterns in the SIO by overlapping the larger
pattern across multiple incoming sync characters, as shown
in Figure 10b.

Framing errors and overrun errors are detected and
buffered together with the partial character on which they
occurred. Vectored interrupts allow fast serVicing of error
conditions uSing dedicated routines. Furthermore, a built-in
checking process avoids Interpreting a framing error as a
new start bit: a framing error results in the addition of
one-half a bit time to the point at which the search for the
next start bit IS begun.

CRC checking for synchronous byte-oriented modes is
delayed by one character time so the CPU may disable CRC
checking on speCific characters. This permits implementation of protocols such as IBM Bisync.

Figure 10a. Some ZSO SIO Protocols
PARITY

~rp

STr

""MA"'"RK""'IN""G""U""'NE=----.II.--OA-T-A"T\I.rI':"I:II=-='oA-='T-A:ul"TI"TI-'11

Ol\TA

III

, MARKING LINE

ASYNCHRONOUS

DATA

SYNC

DATA

CRe,

CRC,

DATA

CRe,

CRC,

DATA

CRe,

CRC2

CRC,

CRC2

MONOSYNC

SYNC

:':

DATA
SIGNAL

+
DATA

BISYNC

EXTERNAL SYNC
FLAG

ADDRESS

INFO~M;TlON

. FLAG

SDLC/HDLC/X.2S

Figure 10b. Six-Bit Sync Character Recognition
5 BITS
~

SYN~

SY.NC

DATA

' - - -.....v""-----'
16

Figure 1 O. Data Communication

511

Both CRC-16 (X 16 + X15 + X2 + 1) and CCITT(X16 + X12
+ X5 + 1) error checking polynomials are supported. In all
non-SOLC modes, the CRC generator is initialized to Os; in
SOLC modes, it is initialized to 1s. The SIO can be used for
interfacing to peripherals such as hard-sectored floppy
disks, but it cannot generate or check CRC for
IBM-compatible soft-sectored disks. The SIO also provides
a feature that automatically transmits CRC data when no
other data is available for transmission. This allows very
high-speed transmissions under OMA controllwith no need
for CPU intervention at the end of a message. When there is
no data or CRC to send in synchronous modes, the
transmitter Inserts 8- or 16-blt sync characters regardless of
the programmed character length.
"

TheSIO supports synchronous bit-oriented protocols such
as SOLC and HDLC by performing automatic flag sending,
zero insertion, and CRC generation. A special command
can be used to abort a frame'in transmission. At the end o'a
message the SIO automatically transmits the CRC and
trailing flag when the transmit buffer becomes empty. If a
transmit underrun occurs In the middle of a message, an
external/status interrupt warns the CPU of this status change
so that an abort may be issued. One to eight bits per
character can be sent, which allows reception of a message
with no prior information about the character structure in the
information field of a frame.

The receiver automatically synchronizes on the leading flag
of a frame in SOLC or HDLC, and provides a
synchronization signal on the SYNC pin; an Interrupt can
also be p~ogrammed. The receiver can be programmed to
search for frames addressed by a single byte to only a
specified user-selected address or to a global broadcast
address. In this mode, frames that do not match either the
user-selected or broadcast address are Ignored. The
number of address bytes can be extended under software
control. For transmitting data, an interrupt on the first
received character or on every character can be selected.
The receiver automatically deletes all zeroes Inserted by the
transmitter during character assembly. It also calculates and
automatically checks the CRC to validate frame
transmission. At the end of transmission, the status of a
received frame is available in the status registers.
The SIO can be conveniently used under DMA control to
provide high-speed reception or transmission. In reception,
for example, the SIO can interrupt the CPU when the first
character of a message IS received. The CPU then enables
the DMA to transfer the message to memory. The SIO then
issues an end-of-frame interrupt and the CPU can check the
status of the received message. Thus, the CPU is freed for
other service while the message is being received.

1/0 INTERFACE CAPABILITIES
The SIO offers the ch,oice of polling, vectored or
non-vectored interrupts and block-transfer modes to
transfer data, status, and control information to, and from,
the CPU. The block-transfer mode can also be implemented
under DMA control.

Polling. Two status registers are updated at appropriate
times for each function being performed (for example, CRC
error-status valid at the end of a message). When the CPU is
operated in a polling fashion, one of the SIO's two status
registers is used to indicate whether the SIO has some data
or needs some data. Depending on the contents of this
register, the CPU will either write data, read data, or just go
on. Two bits in the register indicate that a data transfer is
needed. In addition, error and other conditions are
indicated. The second status register (special receive
conditions) does not have to be read in a polling sequence,
until a character has been received. Alrinterrupt modes are
disabled when operating the device in a polled
environment.
Interrupts. The SIO has an elaborate interrupt scheme to
pro\ilide fast interrupt' service in real-time applications. A
control register and a status register in Chanpel B contain
the interrupt vector. When progra.mmed to do so, the SIO
can modify three bits of the Interrupt vector in the status
register so that it points directly to one of eight interrupt
service routines in memory, thereby servicing conditions in
both channels and eliminating most of the needs for a
status-analysis routine.
Transmit Interrupts, receive interrupts, and external/status
interrupts are the main sources of interrupts. Each interrupt

512

source is enabled under program control,with Channel A
having a higher priority than Channel B, and with receive,
transmit, and external/status interrupts prioritized in that
order within each channel. When the transmit Interrupt is
enabled, the CPU is interrupted by the transmit buffer
becoming empty. (This implies that the transmitter must
have had a data character written Into It so It can become
empty.) The receiver can interrupt the CPU in one of two
ways:
• Interrupt on first recei'{ed character
• Interrupt on all received characters
Interrupt-on-first-received-character is typically used with
the
block-transfer
mode.
Interrupt-on-all-receivedcharacters has the option of modifying the interrupt vector in
the event of a parity error. Both of these interrupt modes will
also interrupt under special receive conditions on a
character or message basis (end-of-frame interrupt in
SDLC, for example). This means that the special-receive
condition can cause an interrupt only if the
interrupt-on-first-received-character or Interrupt-on-allreceived-characters mode is selected. In interrupt-on-firstreceived-character, an Interrupt can' occur from
special-receive conditions (except parity error) after the
first-received-character Interrupt (example' receive-overrun
interrupt).
The main function of the external/status Interrupt is to
monitor the signal transitions of the Clear To Send (CTS),
Data Carrier Detect (DCD), and Synchronization (SYNC)
pins (Figures 1 through 7). In additlol\, an external/status

SYSTEM
BUSES

interrupt is also caused by a CRC-sending condition, or by
the detection of a break sequence (asynchronous mode) or
abort sequence (SDLC mode) in the data: stream. The
interrupt caused by the break/abort sequence allows the
SIO to interrupt when the break/abort sequence is detected
or terminated. This featur1l faCilitates the proper termination
of the current message, correct initialization of the next
message, and the accurate timing of the break/abort
condition in external logic.

~
~

V
DMA

CPU

-INT

iNT-

In a Z80 CPU environment (Figure 11), SIO interrupt
vectoring is "automatic": the SIO passes its internallymodifiable 8-blt Interrupt vector to the CPU, which adds an
additional 8 bits from its interrupt-vector (I) register to form
the memory address of the interrupt-routine table. This table
contains the address of the beginning ofthe interrupt routine
Itself. The process entails an indirect transfer of CPU control
to the Interrupt routine, so that the next instruction executed
after an Interrupt acknowledge by the CPU IS the first
instruction of the interrupt routine itself.

- + ROY
lEI

+sv

T
lEI
ZC/TO,

CTC

iNr

ZC/T02

iEO

CPUlOMA Block Transfer. The SIO's block-transfer mode

lEI

accommodates both CPU block transfers and DMA
controllers (Z80 DMA or other designs). The block-transfer
mode uses the Wait/Ready output signal, which is selected
with three bits in an internal control register. The Wait/Ready
output signal can be programmed as a WAIT line In the CPU
block-transfer mode or as a READY line in the DMA
block-transfer mode.

RxCA

iNT

TxCA

lEO

RxCB

TxCB

WiiiiiYA
W/RDYB

lEO

iNT
~

lEI

ROY

DMA

SIO

To a DMA controller, the SIO READY output indicates that
the SIO is ready to transfer data to, or from, memory. To the
CPU, the WAIT output indicates that the SIO is not ready to
transfer data, thereby requesting the CPU to extend the I/O
cycle.

Figure 11. Typical zao Environment

INTERNAL STRUCTURE
The internal structure of the deVice Includes a Z80 CPU
interface, internal control and Interrupt logic, and two
full-duplex channels. Each channel contains ItS own set of
control and status (write and read) registers, and control and
status logic that provi,des the Interface to modems or other
external deVices
The registers for each channel are designate€! as follows:
WRO-WR7 - Write Registers 0 through 7
RRO-RR2 - Read Registers 0 through 2

Table 1. Register Functions
Read Register Functions

RRO

Transmit/Receive buffer status, Interrupt status and
external status

RR1

Special Receive Condition status

RR2

Modified Interrupt vector (Channel B only)
Write Register Functions

The register group Includes five 8-blt control registers, two
sync-character registers and two status registers. The
Interrupt vector is written into an additional 8-bit register
(Write Register 2) in Channel B that may be read through
another 8-bit register (Read Register 2) in Channel B. The bit
assignment and functional grouping of each register is
configured to Simplify and organize the programming
process. Table 1 lists the functions assigned to each read or
write register.
The logiC for both channels' prOVides formats,
synchronization, and validation for data transferred to and
from the channel Interface. The modem control inputs, Clear
To Send (CTS) and Data Carrier Detect (DC D), are

WRO

WR1

Transmit/Receive interrupt and data transfer mode
definition.

WR2

Interrupt vector (Channel B only)

WR3

Receive parameters and control

WR4

Transmit/Receive miSQellaneous parameters and modes

WR5

Transmit parameters and controls

WR6

Sync character or SOLC address field

WR7

Sync character or SOLC flag

513

monitored by the external control and status logic under
program control. All external control-and-status-Iogic
signals are general-purpose in natUfe and can be used for
functions other than modem control.

Data Path. The transmit and receive data path illustrated for
Channel A In Figure 12 is identical for both channels. The
receiver has three 8-bit buffer registers in a FIFO
arrangement, In addition to the 8-bit receive shift register.
This scheme creates additional time for the CPU to service
an interrupt at the beginning of a block of high-speed data.

Incoming data IS routed through one of several paths (data
or CRC) depending on the selected mode and-in
asynchronous modes-the character length.
The transmitter hasan 8-bit transmit data buffer register that
is loaded from the internal data bus, and a 20-bit transmit
shift register that can be loaded from the sync-character
buffers or from the transmit data register. Depending on the
operational mode, outgol~g data is routed through one of
four main paths before it is transmitted from the Transmit
Data output (TxD).

I
CPU 1/0

~ft·

TxDA

Figure 12.Transmit and Receive Data Path (Channel A)

514

PROGRAMMING
The system program first issues a series of commands that
initialize the basic mode of operation and then issues other
commands that qualify conditions within the selected mode.
For example, the asynchronous mode, character length,
clock rate, number of stop bits, even or odd parity might be
set first; then the interrupt mode; and finally, receiver or
transmitter enable.
80th channels contain registers that must be programmed
via the system program prior to operation. The channelselect input (8/A) and the control/data (C/O) are the
command-structure addressing controls, and are normally
controlled by the CPU address bus. Figures 15 and 16
Illustrate the timing relationships for programming the write
registers and transferring data and status
Read Registers_ The SIO contains three read registers for
Channel 8 and two read registers for Channel A (RRO-RR2
In Figure 13) that can be read to obtain the status
information; RR2 contains the internally-modifiable interrupt
vector and is only in the Channel 8 register set. The status
Information includes error conditions, interrupt vector, and
standard communications-interface signals.

WRO is a special case in that all of the basic commands can
be written to it w'lth a single byte. Reset (internal or external)
Initializes the pointer bits 00-02 to point to WRO. This implies
that a channel reset must not be combined with the pOinting
to any register.
READ REGISTER 0

III ~II

IL..::=
L-RxCHARACTERAVAILABLE
INT PENDING (CH. A ONLy)
}

SYNC/HUNT

CTS

Tx UNDERRUN/EOM
BREAK/ABORT
*Used With "External/Status Interrupt" Modes

READ REGISTER 1t

I~I~I~I~I~I~I~I~I
L-ALLSENT
I FIELD BITS

I FIELD BITS IN

BYTE
0
0
0
0
0
0
1
2

BYTE
3
4
5
6
7
8
8
8

IN PREVIOUS SECOND PREVIOUS

To read the contents of a selected read register other than
RRO, the system program must first write the pointer byte to
WRO in exactly the same way as a write register operation.
Then, by executing a read Instruction, the contents of the
addressed read register can be read by the CPU.
The status bits of RRO and RR1 are carefully grouped to
simplify status monitoring. For example, when the interrupt
vector indicates that a Special Receive Condilion interrupt
has occurred, all the appropriate error bits can be read from
a single register (RR1).

~~~UFFER EMPTY

1
1

o
o
1
1

-====

0
0
0
1
1
1
1
0

}

' - - PARITY ERROR

Rx OVERRUN ERROR

CRC/FRAMING ERROR
END OF FRAME (SDLC)

*Aesldue data for eight Ax bits/character programmed
tUsed with speCial receive conditIon mode

READ REGISTER 2 (Channel B only)

Write Registers_ The SIO contains eight write registers for
Channel 8 and seven write registers for Channel A
(WRO-WR7 In Figure 14) that are programmed separately to
configure the functional personality of the channels; WR2
contains the Interrupt vector for both channels and is only In
the Channel 8 register set With the exception of WRO,
programming the write registers requires two bytes. The first
byte IS to WRO and contains three bits (0 0-02) that point to
the selected register, the second byte is the actual control
word that is written into the register to configure the SIO.

I~I~I~I~I~I~I~I~I

III ~I
~~~t}
~~l

V4
V5

INTERRUPT
VECTOR

va
V7

tVarfable If "Status Affects Vector" is programmed

Figure 13. Read Register Bit Functions

515

WRITE REGISTER 4

WRITE REGISTER 0

I~I~I~I~I~I~I~I~I
I I I
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER

0
1
2
3
4

SYNC MODES ENABLE
1 STOP BIT/CHARACTER
1 Y2 STOP BITS/CHARACTER
2 STOP BITS/CHARACTER

5
6
7

8 BIT SYNC CHARACTER
16 BIT SYNC CHARACTER
SDLC MODE (01111110 fLAG)
EXTERNAL SYNC MODE

NULL CODE
SEND ABORT (SDLC)
RESET EXT/STATUS INTERRUPTS
CHANNEL RESET

X1 CLOCK MODE
X16 CLOCK MODE
X32 CLOCK MODE
X64 CLOCK MODE

ENABLE INT ON NEXT Rx CHARACTER
RESET TxlNT PENDING
ERROR RESET
RETURN FROM INT (CH·A ONLY)
NULL CODE
RESET Ax cae CHECKER
RESET Tx CRe GENERATOR
RESET Tx UNDERRUNfEOM LATCH

WRITE REGISTER 5

WRITE REGISTER 1

I~I~I~I~I~I~I~I~I

III
<

L____

EXT INT ENABLE

Tx INT ENABLE
~:r~~~~~~CTS VECTOR

Rx INT DISABLE
}
Rx INT ON FIRST CHARACTER
INT ON ALL Rx CHARACTERS (PARITY AFFECTS VECTOR)
INT ON ALL Rx CHARACTERS (PARITY DOES NOT AFFECT
VECTOR)

Tx
Tx
Tx
Tx

5 BITS (OR LESS)/CHARACTER
7 BITS/CHARACTER
6 BITS/CHARACTER
8 BITS/CHARACTER

DTR

WAIT/READY ON R/T
WAIT/READY FUNCTION
'-----WAIT/READY ENABLE
"'Oron speCial condition

WRITE REGISTER 6

WRITE REGISTER 2 (Channel B only)

I~I~I~I~I~I~I~I~I

IIIII1 ~~}
~~

V4
V5
V6
V7

III III

INTERRUPT
VECTOR

l:=!i:m:)
SYNC BIT 3
SYNC BIT 4

...

.~M5

SYNC BIT 6
SYNC BIT 1

* Also SOLe address held

WRITE REGISTER 7

WRITE REGISTER 3

[III

CHARACTER LOAD INHIBIT
I~:YNC
L-., ..""
AODRESS SEARCH MODE (SDLC)

Ax CRe ENABLE
.

Rx
Rx
Rx
Rx

5
7
6
8

BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER

ENTER HUNT PHASE
AUTO ENABLES

IIIII1

SYNC
SYNC
SYNC
SYNC
SYNC

BIT
BIT
BIT
BIT
BIT

11
12
13
14
15

...

*For SOle It must be programmed to '01111110" for flag recognition

Figure 14. Write Register Bit Functions

516

L:::::!mmt)

TIMING
The SIO must have the same clock as the CPU (same phase
and frequency relationship, not necessarily the same
driver).
.
Read Cycle. The timing signals generated by a Z80 CPU
Input instruction to read a data or status byte from the SIO
are illustrated in Figure 15.
Write Cycle. Figure 16 illustrates the timing and data
signals generated by a Z80 CPU output instruction to write a
data or control byte into the SIO.
;'
Interrupt-Acknowledge Cycle. After receiving an
interrupt-request signal from an SIO (I NT pulled Low), the
Z80 CPU sends an interrupt-acknowledge sequence, M1
Low and 10RO Low, a few cycles later (Figure 17).
The SIO contains an internal daisy-chained interrupt
structure for prioritizing nested Interrupts for the various
functions of its two channels, and this structure can be used
within an external user-defined daisy chain that prioritizes
several peripheral circuits.
The lEI of the highest-priority device is terminated High. A
device that has an interrupt pending or under service forces
its lEO Low. For devices with no interrupt pending or under
service,IEO=IEI.
To insure stable conditions in the daisy chain, all interrupt
status signals are prevented from changing while M1 is Low.
When 10RO is Low, the highest priority interrupt requestor
T,

(the one with lEI High) places its interrupt vector on the data
bus and sets its internal interrupt-under-service latch.
Return From Interrupt Cycle. Figure 18 illustrates the
return from interrupt cycle. Normally, the Z80 CPU issues a
Return From Interrupt (RET I) instruction at the end of an
interrupt service routine. RETI is a 2-byte opcode (EO-40)
that resets the interrupt-under-service latch in the SIO to
terminate the interrupt that has just been processed. This is
accomplished by manipulating the daisy chain in th~
following way.
The normal daisy-chain operation can be used to detect a
pending interrupt; however, it cannot distinguish between
an interrupt under service and a pending unacknowledged
interrupt of a higher priority. Whenever EO is decoded, the
daisy chain is modified by forcing High the lEO of any
. interrupt that has not yet been acknowledged. Thus the
daisy chain identifies the device presently under service as
the only one with an lEI High and an lEO Low. If the next
opcode byte is 40, the interrupt-under-service latch is reset.
The ripple time of the interrupt daisy chain (both the
High-to-Low and the Low-to-High transitions) limits the
number of devices that can be placed in the daisy chain.
Ripple time can be improved with carry-look-ahead, or by
extending the interrupt-acknowledge cycle. For further
information about techniques for increasing the number of
daisy-chained devices, refer to the Z8400 Z80 CPU Product
Specification (00-2001-04).

CLOCK

.j.JI

iii1 ~'__ _ _ _ _ _

CE, C/i), ali
IORO

IORO
iii)

iii)

DATA

Figure 15. Read Cycle
T,

\====:

------- __ ~~--~I~

lEI _ _ _ _ _ _ _ _ _

iii1

----------------------1-1--------1

-------------------<8>-----Figure 17. Interrupt Acknowledge Cycle

CLOCK

CE, C/i), Bli _ _ _.1'\,+-_ _ _ _ _1-_ _..;;;1

iii)

---------------t-----------IEI------

Ml-------------------~-----------

>8:)(....._______

DATA _________________

Figure 16. Write Cycle

------,/

lEO _ _ _ _ _ _.....J--I
'

r---

Figure 16. Return from Interrupt Cycle
517

ABSOLUTE MAXIMUM RATINGS
Voltages in Vee with respect to Vss
.-0.3Vto +0.7V
- Voltages on all inputs with respect
'
... - 0.3V to Vee + 0.3V
toVss Storage Temperature.
. - 65°C to + 150°C

Stresses greater than those listed under Absolute Maximum Ratings may
cause permanent damage to the device ThiS IS a stress rating only,
operation of the device at any condition above these Indicated In the
operational sections of these specifications IS not Implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability

STANDARD TEST CONDITIONS
+5V

The characteristics below apply for the follOWing test
conditions, unless otherWise noted. All voltages are
referenced to GND (OV). Positive current flows Into the
referenced pin Available operating temperature range IS .

• S = OOC to +700C, Vee Range
NMOS: +4.75V < Vee <'+5.25V
CMOS: +4.50V < Vee < +5.50V
• E = -400C to 1000C, =4.50V < Vee < +5.50V

518

2.1K

DC CHARACTERISTICS
l84C40 CMOS l80 SIO, l84C40/41/42/43/44 DC CHARACTERISTICS
Vee =5.0V ± 10%, unless otherwise specified
Symbol

V'Le
V,HC
V,L
V,H
VQ

Parameter

Clock Input Low Voltage
Clock Input High Voltage
'Input High Voltage
Input Low Voltage
Output Low Voltage

Min

Max

-0.3
Vee-0.6
2.2
-0.3

+0.45
Vee +0.3
Vee
O.B
0.4

VQHI
V0H2
III
ILO
IL(SY)

Output High Voltage
Output High Voltage
Input Leakage Current
3-state Output Leakage Current in Float
SYNC Pin Leakage Current

2.4
Vee-O.B
-10
-10
-40

leel

Power Supply Current - 4MHz
-6MHz
-BMHz
- 10MHz

10 [1)
10 [1)
12 [1)
15 [1)

1CC2

Standby Supply Current

Typ

Unit

Condition

V
V
V
V
V

ILo =2.0rnA

V
V
'JLA
JLA
JLA

10
10
10

7
7
B
TBO

IQH=-1.6rnA
IQH=-250JLA
V,N =0.4V to Vee
Vour =O.4V to Vee

rnA
rnA
rnA
rnA

Vee=5V
CLK=4,6,B,10MHz
V'H=Vee- 0 .2V
V,L=0.2V

JLA

Vee=5V
CLK=(O)
V,H=Vee-0.2V
V,L=O.2V

Note:
[1] Measurements made with outputs floating.

CAPACITANCE
Symbol

Parameter

C
CIN
COUT

Clock Capacitance
Input Capacitance
Output Capacitance

Min

Max

7
5
10

Unit

pI
pf
pf

Over specified temperature range; f = 1 MHz.
Unmeasured pinS returned to ground.

519

AC CHARACTERISTICS *

Z84C40/41/42/43/44 AC CHARACTERISTICS

No Symbol

• Parameter

1
2
3
4
5

TcC
TwCh
TIC
TrC
TwCI

Clock
Clock
Clock
Clock
Clock

T$AD

ICE,BIIA,CIID to Clock

7
8

TsCS(C)
TdC(DO)

Rise Setup Time
IIORO, IRD to Clock Rise
Clock Rise to Data Out
Delay

TsDI(C)

10 TdRD(DOz)

Cycle Time
Pulse Width (High)
Fall Time
Rise Time
Pulse Width (Low)

Data In to Clock Rise
Setup Time
(Write or IM1 Cycle)
IRD Rise to Data Out
Float Delay

11 TdIO(DOI)

IIORO Fall to Data Out

12 TsM1(C)

Delay (lINTACK Cycle)
IM1 to Clock Rise Setup
Time

13 TsIEI(IO)

lEI to IIORO Fall Setup
Time (lINTACK Cycle)
M1 Fall to lEO Fall Delay
(Interrupt Before 1M 1)

Z84C4X04
Min
Max

Z84C4X06
Min
Max

Z84C4X08
Min
Max

Z84C4X10
Min
Max

250
105

162

125
55

100
42

105

DC
DC
30
30
DC

145

DC
DC
20
20
DC

115

35
.100

150

DC
DC
10
10
DC

60
220

DC
DC
10
10
DC

110

160

120

. 140

120

190

160

130

100

100
200

70
150

60
120

50
100

18 TdIO(W/RWf) IIORO or ICE Fall to
/WI/ROY Delay (Wait Mode)
120
19 TdC(W/RR) Clock Rise to IWI/RDY
Delay (Ready Mode)

210

175

130

110

20 TdC(W/RWz) Clock Fall to /WI/ROY
Float Delay (Wait Mode)
When Setup is Specified
21 Th
Any Unspecified Hold

130

14 TdM1(IEO)

15 TdIEI(IEOr)
16 TdIEI(IEOf)
17 TdC(INT)

lEI Rise to lEO Rise Delay
(After ED Decode)
IM1 Fall to lEO Fall Delay
Clock Rise to liNT
Fall Delay

Note:
• Units in nanoseconds (nS).

520

100

110

Note

AC CHARACT~RISTICS TIMING

(Z84C4X CMOS Z80 SIO)

eLK

Ci, CID,ali

--------------------~

lEI

lEO

521

AC CHARACTERISTICS TIMING (Z84C4X CMOSZ80 SIO; Continued)

0~--~~~_____________

TxO

RxO

W/ROY,

I.-----~@~-----.I

522

AC CHARACTERISTICS

(Z84C4X CMOS Z80 SIO; Continued)

Z84C40/41/42/43/44 AC CHARACTERISTICS
Parameter

Z84C4X04
Min Max

Z84C4X06
Min Max

Z84C4X08
Min Max

Z84C4X10
Min Max

Note

No Symbol
1
2
3
5

TwPh
TwPI
TcTxC
TwTxCI
TwTxCh

Pulse Width (High)
Pulse Width (Low)
ITxC Cycle Time
/TxC Width (Low)
ITxC Width (High)

200
200
400
180
180

200
200
330
100
100

150
150
250
85
85

150
150
200
80
80

[2)
[2)
[2)
[2)
[2]'

6
7

TdTxC(TxD)
TdTxC(W/RRf)

TdTxC(INT)
TcRxC

/TxC Fall to TxD Delay
/TxC Fall to /W//RDY
Fall Delay (Ready Mode)
/TxC Fall to liNT Fall Delay
IRxC Cycle Time

5
400

5
330

5
250

5
200

10 TwRxCI
11 TwRxCh
12 TsRxD(RxC)

IRxC Width (Low)
IRxC Width (High)
RxD to IRxC Setup Time

180
180
0

100
100
0

85
85
0

80
80
0

[2)
[2]
[2)

13 ThRxD(RxC)

IRxC Rise to RxD Hold

140

100

[2]

300

160

220

120

[2]
[1)
[1]
[2]

(X1 Mode)
Time (X1 Mode)
14 TdRxC(W/RRf)
15 TdRxC(INT)
16 TdRxC(SYNC)

17 TsSYNC(RxC)

IRxC Rise to /W//RDY Fall
Delay (Ready Mode)
IRxC Rise to liNT Fall Delay
IRxC Rise to ISYNC Fall
Delay (Output Modes)
{SYNC Fall to IRxC
Rise Setup
(External Sync Modes)

[1)

10
4

13
7

10
4

13
7

10
4

13
7

10
4

13
7

[1]
[1]

-100

[2]

• In All Modes, the System Clock rate must be at least five times the maximum data rate.
/RESET must be active a minimum of one complete clock cycle.
Notes:
[1] Units equal to System Clock ~eriods.
[2] Units in nanoseconds (nS).

523

DC CHARACTERISTICS (Z844X I NMOS Z80 SIO)
Symbol
VILe
VIHe
VIL
VIH
VOL
VOH1
VOH2
III
ILO
IL(SY)
ICC1

Parameter

Max

Min'

- Clock Input Low Voltage
Clock Input High Voltage
Input Low Voltage
Input HlgK Voltage
Output Low Voltage
Output High Voltage
Output High Voltage ,
Input Leakage Current
3-State Output LeakaQ\e Current In Float
SYNC Pin Leakage Current
Power Supply Current

-0.3
Vee- 0.6
-0.3
+2.0

Unit

Test Condition

V
V

+0.45
Vee+ 0.3
+0.8

Vee '
+0.4 .

V
V
V

+2.4

IOL = 2.0 rnA

±10
±10

",A

IOH = - 250 ,..A
VIN = 0 4 to Vee
VOUT = 0.4 to Vee

+101-40
, 100

,..A

Oty
DCD
SynclHunl

VO
Vl
V2

ln1arrupt

Vealor *

CTS
Tx UndarNnlEOM

_Abort

Modified In B Channal

Read Register 1

Read Register 3

AlISen1
Channel B ExtlStatus IP }
Channel B Tx IP

Residue Coda 2
Residue Coda 1

Channel B Rx IP

Residue Code 0

Channel A ExtlStatus IP

Parity Error

Channal A Tx IP

Rx Overrun Error

Channel A Rx IP

CRClFraming Error

o
o

End 01 Frame (SOLC)

Always 0 In B Channal

Figure 9. Read Register BH Functions

547

PROGRAMMING (Continued)
Read Register 10

Read Register 13

'~~':
L.=

TCl0
TCll

Loop Sending

TC12

1"C13

Two Clocks Msslng

TC14

On" Clock Mssing

TC15

Upper Byte
of nme Constant

Read Register 15

I~~_.

Lower Byte
TC4

"'llrne Constant

L::=

DC(}.IE
Sync/Hunt IE

CTSIE

TC5
TCB

Tx UnderrunlEOM IE

TC7

BresklAbort IE

Figure 9. Read Register Bit Functions (Continued)

Write Registers. The SCC contains 13 write registers
(14 counting WR8. the transmit buffer) in each channel.
These write registers are programmed separately fo configure the functional "personality" of the channels. In addition. there are two registers (WR2 and WR9) shared by

548

the two channels that may be accessed through either of
them. WR2 contains the interrupt vector for both channels.
while WR~ contains the interrupt control bits. Figure 10
shows the format of each write register.

Write Register 0 (non-rnuftlplexed bus mode)

Write Register 2

Iml~I~I~lool~I~lool

I I I
0
0
0
0
1
1
1
1

0
0
1
1

0
1
1

0
0
0
1
1
1
1

0,
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

==::;~

}

Interrupt
Vector

Write Register 3
0

0
0
0
1
1
1
1
o
o
1
1

0
1
0
1

0
0
1
1
0
0
1
1

0
~1
0
1
0
1
0
1

Null Code
Point High
Reset ExtIStaIus Interrupts
Send Abort (5 OLC)
Enable Int on Next Rx Character
ResetTx Int Pending
Error Reset
Reset Highest IUS

Rx Enable
Sync Character Load Inhlbtt
Addre.. Search Mode (SOLC)
Rx CRC Enable

NuilCode
Reset Rx CRC Checker
Reset Tx CRC Generator
Reset Tx Underrun/EOM Latch

Enter Hunt Mode
Auto Enable.
o
o
1
1

Wfth Point High Command

0
1
0
1

Rx 5 Bits/Character
Rx 7 Bits/Character
Rx 6 Bits/Character
Rx 8 Bits/Character

Write Register 1

~
0
0
1
1

0
1
0
1

Write Register 4

Ext Int Enable
Tx Int Enable
Parity is Special

Partty Enable

Cond~ion

Parity EVEN/1000

Rx Int Disable
Rx Int On First Character or Special Cond~n
Int On All Rx Characters or Special Condition
Ax Int On Special Cond~ion Only

o
o
1
1

WAITIDMA Request On
ReceivellTransmit

0
1
0
1

Sync Modes Enable
1 Stop BIVCharacter
1 112 Slop Bits/Character
2 Stop Bits/Character

0 8-8ft Sync Character
OilS-8ft Sync Character
1
0 SOLC Mode (01111110 Flag)
1
1 External Sync Mode

fWAITIDMA Requast Function
WAITIDMA Request Enable

o
o
1
1

0
1
0
1

XI Clock Mode
X16 Clock Mode
X32 Clock Mode
X64 Clock Mode

Figure 10. Write Register Bit Functions

549

PROGRAMMING (Continued)

Tx CRC, Enable
RTS

ISOLCICRC-16 '

Tx Enable
Send Break

o
1
1

0 Tx 5 Bits(Or lAss)/Character
1 Tx 7 BitslCharacter
0 Tx 6 BitslCharacter
1 Tx 8 BitslCharacter

OTA

Writ~

Sync7
Syncl
Sync7
Sync3
ADA7
ADA7

Sync6 . Syn~5
SyncO Sync5
Sync6 Sync5
Sync2 Syncl
ADA6 ADA5
ADR6 AOA5

Synt4
Synt4
Synt4
SyncO
AOR4
ADR4

Sync3
Sync3
Sync3
1
ADA3

Sync2
Sync2
Sync2
1
ADR2

Syncl
Syncl
Syncl
1
ADRl

SyncO
SyncO
SyncO
1
ADAO

Monosync. 8 Bits
Monosync. 6 Bits
Bisync. 16 Bits
Bisync. 12 Bits
SDLC
SDLC (Adchss Rsnge)

SyncO

Monosync, 8 Bits
Monosync. 6 Bits
Bisync. 16 Bits
Bisync. 12 Bits
SOLC

Write Register 7

Sync7
SyncS
Syoo15
Syncll

SyncS'
Synt4
Sync14
Syncl0

SyncS
Sync3
Sync13
Sync9

Synt4
Sync2
Syne12
SyncS

Sync3
Syncl
Synoll
Sync7

Sync2 Syool
SyncO
x
Syncl0 Sync9
Sync6 SyncS

x
SyncS
Sync4

Figure 10. Write Register Bit Functions (Continued)

550

Write Register 9

Wrfte Register 12

Imlool~I~loolmlrnlool

ll§~_~

TCO
TCl
TC2
TC3

TC4

Softw..... INTACK Enable

o
o

0
1

1
1

0
1

TC5
TC6

No Reset
Channel Raset B
Channel Reset A
Fo_ Hardware Raset

TC7

Write Register 13

Write Register 10

6 Bili/8

Sync

;

Loop Mode

;

AbortilAeg On Underrun
Ma!WlFlag Idle

Go Active On Poll

o
o
1
1

0
1
0
1

Lower Byte of
Time Constant

NRZ
NAZI
FMl (Transklon
FMO (Transilion

TGS
TC9

TC10
TCll

Upper Byte of

TC12

Time Constant

TC13

TC14

= 1)
=0)

TC15
CRC P",set 1110

Write Register 11

Write Register 14

I I
0
0

1
1

BR Generator Enable
flR xC Out = Xlal OUlput
flRx C Out =Transm~ Clock
flRx C Out = BR Generator OUlput
flRxC Out = DPLL OulpUt

8R Generator Source

lDTRIRequest Function
Auto Echo

fTRxCOn

0
0

1
1

0
0

1
1

Transmit Clock =IRTxCPln
Transmit Clock =fT RxCPln
Clock = B R Generator OUlpUt
TransmR Clock = 0 PLLOUlput

Transm~

Receive Clock =IRTxC Pin
Receive Clock = fTRxC Pin
Receive Clock = BR Generato rOulpul
Receive Clock = DPLL OUlput

Local Loopback

0
0
0
0

0
0

1
1

0
0

1
1

1
1
1
1

Null Command
Enter Search Mode
Raset Missing Clock
Disable DPLL
Set Source - BR Generator
Set Source .IRTxC
SetFMMode
Set NAZI Mode

IRTxC XlalllNo Xlal

Figure 10. WrHe Register Bit Functions (Continued)

551

PROGRA",MING (Continued)
, Write Register ,IS

~
~
L.::=

:eroCounllE
SOLC FIFO Enable

DCOIE
SynclHunllE
ClSlE

Tx UnderrunlEOM IE
BreekiAborllE

Figure 10. Write Register Bit Functions (Continued)

TIMING
The SCC generates internal control signals from twR and

transaction involving the SCC to the falling edge of twR or

IRb that are related to PCLK, Since PCLK has no phase
relationship with IWR and IRD, the circuitry generating

IRD in the second transaction involving the SCC. This time

these internal control signals must provide time for metastable conditions to disappear- This gives rise to a recovery time related to PCLK. The recovery time applies only
between bus transactions involving the SCC. The recovery
·time applies only between bus transactions involving the
sec. The recovery time required for proper operation is
specified from the falling edge of twR or IRD in the first

552

must be at least 4 PCLK regardless of which register or
channel is being accessed.

Read Cycle Timing. Figure 11 illustrates Read cycle timing.
Addresses on NIB and DIIC and the status on IINTACK
must remain stable throughout the cycle. If ISCCCS falls
after IRD falls or if it rises before IRD rises, the effective IRD
is shortened.

AIIB,OIlC

IINTACK

________

-J~~_________________A_dd_r_es_s_V_a_li_d___________________I~~

ISCCCS

\_/

IRO

07-00

______

" ' _ . _ _ _ _._J

--------------------------c(~______

»)0----------

Oata Valid

Figure 11. Read Cycle Timing

Write Cycle Timing. Figure 12 illustrates Write cycle timing.
Addresses on Al/B and DIIC and the status on IINTACK
must remain stable throughout the cycle. If ISCCCS falls

AIIB,OIlC

IINTACK

ISCCCS

07-00

_______

after IWR falls or if it rises before IWR rises, the effective
twR is shortened. Data must be valid before the falling
edge of twR.

J~~______________Ad_d_re_s_s_V_a_lid_________________J~~_____

\_I

-----~

------------------~<:~·__________

._J:»-------------

o_a_la_V_a_li_d__________

Figure 12. Write Cycle Timing

553

TIMING (Continued)
Interrupt Acknowledge Cycle Timing. Figure 13 illustrates
Interrupt Acknowledge cycle timing.

IINTA"CK

IRD

07-00

'-----uI

I
I

(

Vector

)

Figure 13. Interrupt Acknowledge Cycle Timing

FIFO
The following text explains the functional operations of
the FIFO.
FIFO Enhancements. When used with a OMA controller,
the Z85C30 FIFO enhancement maximizes the SCC's
ability to receive high speed back-to-back SOLC messages while minimizing frame overruns due to CPU latencies
in responding to interrupts.
Additional logic was added to the industry standard NMOS
SCC consisting of a 10 deep by 19 bit status FIFO, 14-bit
receive byte counter, and control logic as shown in Figure
14. The 10 x 19 bit status FIFO is separate from the existing
three byte receive data FIFO.
When the enhancement is enabled, the status in read
register 1 (RR 1) and byte count for the SOLC frame will be
stored in the 10 x 19 bit status FIFO. This allows the OMA
controller to transfer the next frame into memory while the
CPU verifjes the message was properly received
Summarizing the operation, data is reCeived, assembled,
loaded into the three byte rec.eive FIFO before being
transferred to memory by the OMA controller. When a flag
is received at the end of an SOLC frame, the frame byte
count from the 14-bit counter and five status bits are
loaded into the status FIFO for verification by the CPU.

554

The CRC checker is automatically reset in preparation for
the next frame which can begin immediately. Since the
byte count and status are saved for each frame, the
message integrity can be verified at a later time. Status
information for up to 10 frames can be stored before a
status FIFO overrun could occur.
FIFO Detail. For a better understanding of details of the
FIFO operation, refer to the block diagram contained in
Figure 14.
EnablelDisable. This FIFO is implemented so that it is
enabled when WR 15 bit 2 is set and the SCC is in the SOLCI
HOLC mode, otherwise the status register contents bypass
the FIFO and go directly to the bus interface (the. FIFO
pointer logic is reset either when disabled or via a channel
or power-on reset). When the FIFO mode is disabled, the
SCC is conipletely downward-compatible with the NMOS
8530. The FIFO mode is disabled on power-up (WR15 bit
2 is settoOon reset). The effects of backward compatibility
on the register set are 'that RR4 is an image of RRO, RR5 is
an image of RR1, RR6 is an image of RR2 and RR7 is an
image of RR3 For the details of the added registers, refer
to Figure 16. The status of the FIFO Enable signal can be
obtained by reading RR15 bit 2. If the FIFO is enabled, the
bit will be set to 1; otherwise, it will be reset.

Frame Status FIFO Circuitry

RR1

SCC Status Reg
Residue Bits(3)
Overrun, CRC Error

Byte Counter

4--

Reset on Flag Detect

4-4--

Increment on Byte DET

'----"'T""'-----'

I
.--------1

5 Bits

•

14 Bits

Enable Count in SDLC

End of Frame Signal - - - - ,
Status Read Comp

AFOArray
10 Deep by 19 Bits Wide

Tail Pointer
4-Bit Counter
Head Pointer
4-Bit Counter

f""'"

4-Bit Comparator

5 Bits

Over

EOF=1

•

SBits.

Equal

8 Bits

" " 6-Bit MUX //L
......- - - - - + - - - + - I 1 L E _ N J - - - - - I - - - - t - - - ,

Interface
toSCC

•

2 Bits

" 6 Bits
RR1
A

-'
. IRR7 Ds.oO

+ RR6 07 - DO
Byte Counter Contains 14 bits
for a 16 KByte maximum count

WR(1!) Bit 2
SeiEnaDies
Status FIFO

RR7D6
FIFO Data available status bit Status Bit set to 1
When reading from FIFO.
RR7D7
FIFO Overflow Status Bit
MSB pf RR(7) is set on Status FIFO overflow

In SDLC Mode the following definitions apply
- All Sent bypasses MUX and equals contents of SCC Status Register.
- Parity Bits bypasses MUX and does the same.
- EOF is set to 1 whenever reading from the FIFO..

Figure 14. SCC Status Register Modifications

555

FIFO (Continued)
Read Operation. When WR15 bit2is set and the FIFO is not
empty, the next read to any of status register RR1 or the
additional registers RR7 and RR6 will actually be from the
FIFO. Reading status register RR1 causes one location of
. the FIFO to be emptied, so status should be read after
reading the byte count. otherwise the count will be incorrect. Before the FIFO underflows, it is disabled. In this
case, the multiplexer is switched to allow status to read
directly from the status register, and reads from RR7 and
RR6 will contilin bits that are undefined. Bit 6 of RR7 (FIFO
Oata Available) can be used to determine if status data is
coming from the FIFO or directly from the status register,
since it is set to 1 whenever the FIFO is not empty.
Since not all status bits must be stored in the FIFO, the All
Sent. Parity, and EOF bits will bypass the FIFO. The status
bits sentthrough the FIFO will be Residue Bits (3), Overrun,
and CRC Error.

The sequence for prop~r operation of the byte count and
FIFO logic is to read the registers in the following order:
RR7, RR6, and RR1 (reading RR6 is optional). Additional
logic prevents the FIFO from being emptied by multiple
reads from RR1. The read from RR7 latches the FIFO
empty/full status bit (bit 6) and steers the status multiplexer
to read from the SCC megacell instead of the status FIFO
(since the status FIFO is empty). The read from RR1 allows
an entry to be read from the FIFO (if the FIFO was empty,
logic is added to prevent a FIFO underflow condition).
Write Operation. When the end of an SOLC frame (EOF)
has been received and the FIFO is enabled, the contents
of the status and byte-count registers are loaded into the
FIFO. The EOF signal is used to increment the FIFO. If the
FIFO overflows. the MSB of RR7 (FIFO Overflow) is set 10
indicate the overflow. This bit and the FIFO contrpllogic is
reset by disabling and re-enabling Ihe FIFO control bit
(WR15 bit 2). For details of FIFO control timing during an
SOLC frame, refer to Figure 15 .

••••
Internal Byte Strobe
Increments Counter

Internal Byte Strobe
Increments Counter
Don' Load
Counter On
1stAag
Reset Byte
Counter Here

Reset
Byte Counter
Load Counter
IntoAFOand
Increment PTR

Reset
Byte Counter

Reset
Byte Counter
Load Counter
Into FIFO And
Increment PTR

Figure 15. SOLe Byte Counting Detail

Byte Counter Detail. The 14-bit byte counter allows for
packets up to 16K bytes to be received. For a better
understanding of its operation refer to Figures 14 and 15.
Enable. The byte counter is enabled in the SOLC/
HOLCmode.
Reset. The byte counter is reset whenever an AOLC flag
character is received. The reset is timed so that the
contents of the byte counter are successfully written into
the FIFO.

556

Increment. The byte counter is incremented by writes to
the data FIFO. The counter represents the numberof bytes
received by the SCC, rather than the number of bytes
transferred from-the SCC. (These counts may differ by up
to the number of bytes in the receive data FIFO contained
in the SCC).

RR7
7

0
FDA,

TT
FOY

BC
13

BC
12

BC
11

BC
10

BC
9

FIFO Data Available Status
1 Status Reads WII Come From FIFO
o Status Reeds wnl Come From sec
FIFO OveIflow Status
1 FIFO OverfIowad During Operation
o Normal

RR6
7

Be
7

]

BC
4

BC
3

BC
1

Be
2

WR15
7

Read From FIFO
LSB Byte Count

Be
0

o
*

FEN

T
*

Read From FIFO
MSB Byte Count

BC
8

No change From NMOS sec

Status FIFO Enable Control BIT
1 Status and Byte Count Will Be
Held in the Status FIFO Until Read
o Status Will Not Be Held (sec
Emulation Mode)

DFN
Figure 16.

see Additional Registers'

SOFTWARE INTERRUPT ACKNOWLEDGE
The SCC can do im interrupt acknowledge cycle through
software. In some CPU environments it is difficult to cre,ate
the liNTACK signal with the necessary timing to acknowledge interrupts and allow the nesting of interrupts. In these
cases, it would be desirable to create this Signal in software.
If bit 5 of Write Register 9 (WR9) is set, reading register 2
(RR2) will result in an interrupt acknowledge cycle to be
executed internally. Like a hardware INTACK cycle, a
software acknowledge will cause the liNT pin to
return high.

Similarly to when the IINTACK signalis used, when a
software acknowledge cycle is sued, a Reset Highest IUS
command must be issued in the interrupt-service routine.
If the RR2 is read from channel B, the modified vector will
be returned, If the RR2 is read from channel A, then the
vector will be returned unmodified. The Vector Includes
Status (VIS) and no vector (NV) bits (WR9) and are ignored
when bit 5 is set to 1.
When the IINTACK is not being used, itshould be pulled up
to VDD through a resistor (10K ohm typical).

557

SCSI FUNCTIONAL DESCRIPTION
General. The Small Computer System interface (SCSI)
device has a set of eight registers that are controlled by the
CPU. By reading and writing the appropriate registers. the
CPU may initiate any SCSI Bus activity or may sample and
assert any signal on the SCSI Bus. This allows the user to
implement all or any of the SCSI protocol in software. These
registers are read (written) by activating /SCSICS with an
address on A2-AO and then issuing a/RD (/WR) pulse. This
section describes the operation of the internal registers
(Table 2).

Address: 0

(Read Only)

107106105104103102101100 1
lOBO

10Bl
IOB2
IOB3

10B4
IOB5

Table 2. Register Summary

IOB6

Address
A2
A1
AO

R!W

0
0
0

0
0

R
W
R/W

Current SCSI Data
Output Data
Initiator Command

0
0

1
1

R/W
R/W
R

Mode
Target Command
Current SCSI Bus Status

0
0
0

O'
1
1

W
R
W

Select Enable
Bus and Status
Start DMA Send

0
0

R
W
R
W

Input Data
Start DMA Target Receive
Reset Parity/Interrupt
Start DMA Initiator Receive

1
1

Data Registers. The data registers are used to transfer
SCSI commands. data. status. and message by1es between
the microprocessor Data Bus and the SCSI Bus. The SCSI
does not interpret any information that passes through the
data registers. The data registers consist of the transparent
Current SCSI Data Register. the Output Data Register. and
the Input Data Register.

IOB7

Figure 17. Current SCSI Data Register

Output Data Register. Address O(Write Only). The Output
Data Register (Figure 18) is a write-only register that is
used to send data to the SCSI Bus. This is accomplished
by either using a normal CPU write. or under DMA control.
by using /WR and /DACK. This register also asserts the
proper ID bits on the SCSI Bus during the Arbitration and
Selection phases.

Address: 0

(Write Only)

1071061051041031021011001

lOBO
lOBI
IOB2
IOB3

'-------- 1DB4
' - - - - - - - - - IOB5

IOB6

Current SCSI Data Register. Address O(Read Only). The
Current SCSI Data Register (Figure 17) is a read-Only
register which allows the microprocessor to read the active
SCSI Data Bus. This is accomplished by activating
/SCSICS with an address on A2-AO and issuing a /RD
pulse. If parity checking is enabled. the SCSI Bus parity is
checked at the beginning of the read cycle. T;his register
is used during a programmed I/O data read or during
Arbitration to check for higher priority arbitrating devices.
Parity is not guaranteed valid during Arbitration.

558

' - - - - - - - - , - - - - . . . . . ; . . lOB7

Figure 18. Output Data Register

Input Data Register. Address 6 (Read Only). The input
Data Register (Figure 19) is a read-only register that is
used to read latched data from the SCSI Bus. Data is
latched either during a DMA Target receive operation

when lACK goes active or during a OMA Initiator receive
when IREQ goes active. The OMA Mode bit (Mode Register bit 1) must be set before data can be latched in the
Input Oata Register. This register is read under OMA
control using IRO and 10ACK. Parity is optionally checked
when the Input Oata Register is loaded.

Address: 1

(Write Only)

ID'I"I"I"I~
Assert Data Bus
Assert/ATN
AssertlSEL

Address: 6

(Read Only)

Assert/BSY

1071061051041031021011 Dol

Assert lACK

"0"

IDBO

Test Mode

10Bl
Assert/RST

IDB2

10B3
10B4

Figure 21. Initiator Command Register
(Register Write)

IOB5
IOB6
IOB7

Figure 19. Input Data Register

Initiator Command Register. Address 1 (rea\jfwrite). The
Initiator Command Register (Figures 20 and 21) are read
and write registers which assert certain SCSI Bus sig!lals,
monitors those signals, and monitors the progress 01 bus
arbitration. Many of these bits are significant only when
being used as an Initiator; however, most can be used
during Target role operation.
Address: 1

(Read Only)

Bit O. Assert Data Bus. The ASSERT OAT A BUS bit, when
set, allows the contents of the Output Oata Register to be
enabled as chip outputs on the signals IOB7-/OBO. Parity
is also generated and asserted on 10BP.
'When connected as an Initiator, the outputs are only
enabled if the TARGETMOOE bit (Mode Register, bit 6) is
FALSE, the received signal 11/0 is FALSE, and the phase
signals CliO, 1//0, and IMSG match the contents of the
ASSERT CliO, ASSERT 1//0 and ASSERT IMSG in the
Target Command Register.
This bit should also be set during OMA send operations.

1071061051041031021011001

The following describes the operation of all bits in the
Initiator Command Register.

Assert Data Bus
Assert/ATN
AssertlSEL
Assert/BSY
Assert lACK

Lost A1bitration
Arbitration in Progress
Assert IRST .

.Flgure 20. Initiator Command Register
(Register Read)

Bit 1. ASSERT/A TN/A TN. Bit 1 may be asserted on the SCSI
Bus by setting this bit to a one (1) if the TRAGETMOOE bit
(Mode Register, bit 6) is FALSE IA TN is normally asserted
by the initiator to request a Message Out bus phase. Note
that since ASSERTISEL and ASSERTIA TN are in the same
register, a select with IATN may be implemented with one
CPU write IATN may be deasserted by resetting this bit to
zero. A read on this register simply reflects the status of
this bit.
Bit 2. ASSERT/SEL. Writing a one (1) into this bit position
asserts ISEL onto the SCSI Bus. ISEL is normally asserted
after Arbitration has been successfully completed ISEL
may be disabled by resetting bit 2 to a zero. A read of this
register reflects the status of this bit.

559

SCSI FUNCTI9NAL DESCRIPTION (Continued)
Bit 3. ASSERT/BSY. Writing a one (1) into this bit position
asserts /BSY onto the SCSI Bus. Conversly, a zero resets
the IBSY signal. Asserting IBSY indicates a successful
selection or reselection. Resetting this bit creates a BusDisconnect condition. Reading this register reflects
bit status.
Bit 4. A SSERT/ACK. Bit 4 is used by the bus initiator to
assert lACK on the SCSI Bus. In order to assert lACK, the
TARGETMODE bit (Mode Register, bit 6) must be FALSE.
Writing a zero to this bit deasserts lACK. Reading this
register reflects bit status.
Bit 5. "0" (Write Bit). Bit 5 should be written with a zero for
proper operation.
Bit 5. LA (Lost Arbitration - Read Bit). Bit 5, when active,
indicates thaI the SCSI detected a Bus-Free condition,
arbitrated for use of the bus by asserting /BSY and its 10 on
the Data Bus, and lost Arbitration due to /SEL being
asserted by another bus device. This bit is active only
when the ARBITRATE bit (Mode Register, bit 0) is active.
/

Bit 6. TEST MODE (Write Bit). Bit 6 is written during a test
environment to disable all output drivers, effectively removing the Z53C80 from the circuit. Resetting this bit
returns the part to normal operation.
Bit 6. AlP (Arbitration in Process - Read Bit). Bit 6 is used
to determine if Arbitration is in progress. For this bit to be
active, the ARBITRATE bit (Mode Register, bit 0) must
have been set previously. It indicates that a Bus-Free
condition has been detected and thatthe chip has asserted
IBSY and put the contents of the Output Data Register onto
the SCSI Bus. AlP will remain active until the ARBITRATE
bit is reset.
Bit 7. ASSERT/RST. Whenever a one is written to bit 7 of the
Initiator Command Register, the IRST signal is asserted on
the SCSI Bus. The IRSTsignal will remain asserted until this
.bit is reset or until an external/RESET occurs. After this bit
is set (1), IRQ goes active and all internal logic and control
registers are reset (exc~pt for the interrupt latch and the
ASSERT/RST bit). Writing a zero to bit 7 of the Initiator
Command Register deasserts the /RST signal. The status
of this bit is monitored by reading the Initiator Command
Register.
Mode Register. Address 2 (Read/Write). The Mode RegiS,ter controls the operation of the chip. This register determines whether the SCSI operates as an Initiator or a
Target, whether DMA transfers are being used, whether

560

parity is checked, and whether interrupts are generated on
various extetnal conditions. This! register is read to check
the value of these internal control bits (Figure 22).
Address: 2

(ReadlWrRe)

Iml~I~I~lool~I~lool

ArbHrate
DMAMode
Monitor IBSY
Enable IEOP Interrupt
Enable Parity Interrupt
Enable Parity Checking
Target Mode

·0·

Figure 22. Mode Register
Bit O. ARBITRATE. The ARBITRA TE bit is set (1) to start the
Arbitration process. Prior to setting this bit. the Output Data
Register should contain the proper SCSI device 10 value.
Only one data bit should be active for SCSI Bus Arbitration.
The SCSI waits for a Bus-Free condition before entering
the Arbitration phase. The results of the Arbitration phase
is determined by reading the status bits LA and AlP
(Initiator Command Register, bits 5 and 6, respectively).
Bit 1. DMA MODE. The DMA MODE bit is normally used to
enable a DMA transfer and must be set (1) prior to writing
Start DMA Send Register, .Start DMA Target Receive
Register, and Start DMA Initiator Receiver Register. These
three registers are used to start DMA transfers. The
TARGETMODE bit (Mode Register, bit 6) must be consistent with writes to Start DMA Target Receive and Start DMA
Initiator Receive Registers [i.e., set (1) for a write to start
DMA Target Receive Register and set (0) for a write to Start
DMf\ Initiator Receive Register]. The control bit ASSERT
DATA BUS (Initiator Command Register, bit 0) must be
TRUE (1) for all DMA send operations. In the DMA mode,
/REQ and lACK are automatically controlled.
The DMA MODE bit is not reset upon the receipt of an IEOP
signal. Any DMA transfer is stopped by writing a zero into
this bit location; however, care must be taken not to cause
ISCSICS and /DACK to be active simultaneously.
Bit 2. MONITOR BUSY. The MONITOR BUSY bit, when
TRUE (1), causes an interrupt to be generated for an

unexpected loss of /BSY. When the interrupt is generated
due to loss of IBSY, the lower six bits of the Initiator
Command Register are reset (0) and all signals are removed from the SCSI Bus.
• Bit 3. ENABLE/EOP interrupt. The enable lEap interrupt,
when set (1), causes an interrupt to occur when the lEap
(End of Process) signal is received from the DMA
controller logic.
Bit 4. ENABLE PARITY INTERRUPT. Tthe ENABLE PARITY
INTERRUPT bit. when set (1), will cause an interrupt (IRO)
to occur if a parity error is detected. A parity interrupt will
only be generated.if the ENABLE PARITY CHECKING bit
(bit 5) is also enabled (1).
Bit 5. ENABLE PARITY CHECKING. The ENABLE PARITY
CHECKI NG bit determines whether parity errors are ignored
or saved in the parity error latch. If this bit is reset (0), parity
is ignored. Conversely, if this bit is set (1), parity errors
are saved.
Bit 6. TARGETMOOE. The TARGETMODE bit allows the
SCSI to operate as either a SCSI Bus Initiator, bit reset (0),
or as a SCSI Bus Target device, bit set (1). If the signals
IATN and lACK are to be asserted on the SCSI Bus, the
TARGETMODE bit must be reset (0). If the signals CIID,
1//0, IMSG, and IREO are to be asserted on the SCSI BuS,
the TARGETMODE bit must be set (1).
Bit 7. "a". Bit 7 should be written with a zero for proper
operation.
Target Command Register. Address 3 (ReadtWrite ). When
connected as a target device, the Target Command
Register (Figure 23) allows the CPU to control the SCSI Bus
Information Transfer phase and/or to assert/REO by writing
this register. The TARGETMODE bit (Mode Register, bit 6)
must be TRUE (1) for bus assertion to occur. The SCSI Bus
phases are described in Table 3.
Table 3. SCSI Information Transfer Phase
Bus Phase

ASSERT"

1110

ASSERT
CIID

ASSERT
IMS

Data Out
Unspecified
Command

0
0
0

0
0

0
1
0

Message Out
Data In
Unspecified

0
1
1

1
0
0

1
0
1

.Status
Message In

0
1

When conneCted as an Initiator withDMA MODE TRUE, if
the phase lines 11/0, CIID, and /MSG do not match the
phase bits in the Target Command Register, a phase I
mismatch interrupt is generated when /REO goes active.
To send data as an Initiator, the ASSERT II/a, ASSERT
CIID, and ASSERT IMSG bits must match the corresponding
bits in the Current SCSI Blois Status Register. The ASSERT
IREO bit (bit 3) has no meaning when operating as an
Initiator.
Bits 4, 5, and 6 are not used.
Bit 7. LAST BYTE SENT (Read Only). The END OF DMA
TRANSFER bit (Bus and Status Register, bit 7) only indicates when the last byte was received from the DMA
controller. The LAST BYTE SENT bit can be used to flag
that the last byte of the DMA send operation has been
transferred on the SCSI Data Bus.
Address: 3

(ReadIWrile)

Iwl~I~I~loolool~lool
Assert VIO
Assert ClIO .
AssertlMSG
AssertlREO
oJ("

Last Byte Sent

Figure 23. Target Command Register

Current SCSI Bus Status Register. i'lddress4(Read Only).
The Current SCSI Bus Register is a read-only register
which is used to monitor seven SCSI Bus control signals,
plus the Data Bus parity bit. For example, an Initiator
device can use this register to determine the current bus
phase and to poll IREO for pending data transfers. This
register may also be used to determine why a particular
interrupt occurred. Figure 24 describes the Current SCSI
Bus Status Register.
Select Enable Register. Address 4 (Write Only). The Select
Enable Register (Figure 25 ) is a write-only register which is
used as a mask to monitor a signal ID during a selection
attempt. The simultaneous occurrence of the correctlD bit,
IBSY FALSE, and ISEL TRUE will cause an interrupt. This
interrupt can be disabled by resetting all bits in this
register. If the ENABLE PARITY CHECKING /:lit (Mode
Register, bit 5) is active (1), parity is checked during
selection.

561

SCSI FUNCTIONAl. QESCRIPTION (Continued)
Address: 4

(Read Only)

1071061051041031021011001

AsIdress: 5

(Read Only)

Iml06ID5I04I03I~I~lool

~
' - - - - - - - !MSG

' - - - - - - - - - - - ~y

Figure 24. Current SCSI B",s Status Regl_r

Address: 4

(Write Only)

1~1D51D5I04I03I02I~lool

' - - - - - - - 1DB4
~------- ID~

'-----~---- ID~
' - - - - - - - - - - - IDB7

Figure 25.

~elect

Enable Register

Bus and Status Register. Address 5 (Read OnJy). The Bus
and Status Register (Figure 26) is a read-only register
which can be used to monitor the remaining SCSI control
signals not found in the Current SCSI Bus Status Registers
(tATN and lACK), as well as six other status bits. The'
following describes each bit of the Bus Status Register
individually.

Bit O. lACK. Bit 0 reflects the condition of the SCSI Bus
control signal/ACK. This signal is normally monitored by
. the Target device.
Bit 1. IA·TN. Bit 1 reflects the condition of the SCSI Bus
control sigoal/ATN. This signal is normally monitored py
the Target device.
!

,562

IATN

Busy Error
(

Phase Match

Interrupt Request Ame
Parity Error

~-----~,~EQ

' - - - - - - - - - - - ' - - IRST

lACK

DMARequest

EndofDMA

Figure 26. Bus and Status,Reglster

Bit 2. BUSY ERROR. The BUSY ERROR bit is active if an
unexpected loss of the /BSY signal has occurred. This
latch is set whenever the MONITOR BUSY bit (Mode
Regi'ster, bit2) is TRUE and /BSYis FALSE. An unexpected
loss of IBSY disaIJles any SCSI outputs and, resets the DMA
MODE bit (Mode Register, bit 1).
Bit 3. PHASE MATCH. The SCSI signals/MSG, CliO, and
11/0, represent the current information Transfer phase. The
PHASE MATCH bit indicates whether the current SCSI Bus
phiise matches the lower 3 bits of the Target Command
Register. PHASE MATCH is continuously updated and is
only significant when operating as a Bus Initiator. A phase
match is required for data transfers to ,occur on the
SC$I Bus.
Bit 4. INTERRUPT REQl)EST ACTIVE. J;3it 4 is set if an
enabled interrupt condition occurs. It reflects the current
state of t~e IRO output and can be cleared by reading the
Reset Parity/lnterrupt Register.
Bit 5. PARITY ERROR. Bit S is set if a parity error occurs
during a data receive or device selection. The PARITY
ERROR bit can only be set (1) if the ENABLE PARITY
CHECK bit (Mode Register, bitS)is active (1). This bitmay
be cleared by reading the Reset Parlty/lnterrupt Register.

Bit 6. DMA REQUEST. The DMA REQUEST bit allows the
CPU to sample the output pin ORO. DRQ can be cleared
by asserting IDACK or by resetting the DMA MODE bit
(bit '1 ) in the Mode Register. The ORO signal does not reset
when a phase-mismatch interrupt occurs.

Bit 7. END OF DMA TRANSFER. The END OF DMA
TRANSFER bit is set if /EOP, IDACK, and either /RD or /WR
are simultaneously active for at least 1oons, Since the
IEOP signal can occur during the last byte sent to the
Output Data Register, the IREQ and lACK signals should
be monitored to ensure that the last byte has been transferred, This bit is reset when the DMA MODE bit is reset (0)
ill the Mode Register.
DMA Registers. Three write-qnly registers are used to
initiate all DMA activity, They are: Start DMA Send, Start
DMA Target Receive, and Start DMA Initiator Receive,
Performing a write operation into one of these registers
starts the desired type of OM transfer. Data presented to
the SCSI on signals 07-00 during the register write is
meaningless and has no effect on the operation. Prior to
writing these registers, the DMA MODE bit (bit 1), and the
TARGETMODE bit (bit 6) in the Mode Register must be
appropriately set. The individual registers are briefly described as follows:
Start DMA Send. Address 5 (Write Only), This register is
written to initiate a DMA send, from the DMA to the SCSI
Bus, for either Initiator or Target role operations, The DMA
MODE bit (Mode Register, bit 1) is set prior to writing this
register.
Start DMA Target Receive. Address 6 (Write Only). This
registeris written to initiate a DMA receive - from the SCSI
Bus to the DMA, for Target operation only, The DMA MODE
bit (bit 1) and the TARGETMODE bit (bit 6) in the Mode
Register must both be set (1) prior to writing this register.
Start DMA Initiator Receive. Address 7 (Write Only). This
register is writt~n to initiate a DMA receive - from the SCSI
Bus to the DMA, for Initiator operation only, The DMA
MODE bit (bit 6) must be FALSE (0) in the Mode Register
prior to writing this register.
Reset Parity/Interrupt. Address 7 (Read Only), Reading
this register resets the PARITY ERROR bit (bit 5), the
INTERRUPT REQUEST bit (bit 4), and the BUSY ERROR bit
(bit 2) in the Bus and Status Register,
On-Chip SCSI Hardware Support. The SCSI is easy to use
because of its simple architecture, The Chip allows direct
control and monitoring of the SCSI Bus by providing a latch
for each signal. However, portions of the protocol define
timings which are much too quick for traditional microprocessors to control. Therefore, hardware support has
been provided for DMA transfers, bus arbitration, phase
change monitoring, bus disconnection, bus reset, parity
generation, parity checking, and device selectionl
res election .

Arbitration is accomplished, using a Bus-Free filter to
continuously monitor /BSY, If /BSY remains inactive for at
least 4oons, the SCSI is considered free and Arbitration
may begin, Arbitration will begin if the bus is free, /SEL is
inactive, and the ARBITRATE bit (Mode Register, bit 0) is
active, Once arbitration has begun (/BSY asserted), an
arbitration delay of 2,21JS must elapse before the Data Bus
can be e~amined to determine if Arbitration is enabled,
This delay is implemented in the controlling software
driver.
The Z53C80 is a clockwise device. Delays such as busfree delay, bus-set delay, and bus-settle delay are
implemented using gate delays. These delays may differ
between devices because of inherent process variations,
but are well within the proposed ANSI X3,131 - 1986.
specification.

INTERRUPTS. The Z53C80 provides an interrupt output
(IRQ) to indicate a task completion or an abnormal bus
occurrence. The use of interrupts is optional and may be
disabled by resetting the appropriate bits in the Mode
Register or the Select Enable Register.
When an interrupt occurs, the Bus and Status Register and
the Current SCSI Bus Status Register (Figures 26 and 24)
must be read to determine which Condition created the
interrupt. IRQ can be reset simply by reading the Reset
Parity/Interrupt Register or by an external chip reset
IRESET active for 1oons,
Assuming the Z53C80 has been properly initialized, an
interrupt will be generated if the chip is selected or
reselected, ilan /EOP signal occurs, if a parity error occurs
during a data transfer, if a bus phase mismatch occurs, or
if a SCSI Bus disconnection occurs.

Selection Reselection. The Z53C80 generates a select
interrupt if SEL is active (0), its device 10 is TRUE and 18S"
is FALSE for at least a bus-settle delay, If 11/0 is active, this
is considered a reselect interrupt The correct 10 bit is
determined by a match in the Select Enable Register. Only
a single bit match is required to generate an interrupt. This
interrupt may be disabled by writing zeros into all bits of the
Select Enable Register.
If parity is supported, parity should be good during the
selection phase, Therefore, if the ENABLE PARITY bit
(Mode Register, bit 5) is active, the PARITY ERROR bit is
checked to ensure that a proper selection has occurred,
The ENABLE PARITY INTERRUPT bit need not be set for
this interrupt to be generated.

563

SCSI FUNCTIONAL DESCRIPTION (Continued)
The proposed SCSI specification also requires that no
more than two device ID's be active during the selection
process. To ensure this, the Current SCSI Data Register
is read.
07

The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
27 and. 28, respectively.

10lol0111xl0lxl01

I~:. .

lolololxlxlxlolxl

I~;
~~ro

LSPhauMakm

~---------- ~G

Intanupl Request ActIve

~------------ f~O

Perity Error

~--------------L -_________________

DMA Request

~SY
ffiST,

Erld of OMA

Figure 27. Bus and Status Register

End of Process (EOP) Interrupt. An End Of Process signal
(EOP) which occurs-during a DMA transfer (DMA MODE
TRUE) will set the END OF DMA Status bit (Bus and Status
Register bit 7) and will optionally generate an interrupt if
ENABLE EOP INTERRUPT bit (Mode Register, bit 3) is
TRUE. The lEap pulse will not be recognized (END OF
DMA bit set) unless lEap, IDACK, and either IRD or /WR
, are concurrently active for at least 50 ns. DMA transfers
07

can still occur if lEap was not asserted at the correct time,
Thi.s interr\Jpt is disabled by resetting the ENABLE EOP
INTERRUPT bit
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register for this interrupt are
shown in Figures 29 and 30.

Ill ololll olololxl

Ill=~::
~
~

BusyEnor

PhaseMakm

~--------- I~nupt Request Active
~-:--------- Perity Error
~------------- DMA'Request
~---------------- End of OMA

Figure 29. Bus and Status Register

564

Figure 28. Current SCSI Bus Status Register

"l olllll xlxlxlolxl

I~;
~~ro

~---------- !MSO
~--------- fREO

~--------------- ~y
~-------------- fRST

Figure 30. Current SCSI Bus Status Register

The END OF DMA bit is used to determine when a block
transfer is complete. Receive operations are complete
when there is no data left in the .chip and no additional
handshakes occurring. The only exception to this is
receiving data as an Initiator and the Target opts to send
additional data for the same phase. In this IREO goes
active and the new data is present in the Input Data
Register. Since a phase-mismatch interrupt will not occur,
IREO and lACK need to be sampled to determine that the
Target is attempting to send more data.
For send operations, the END OF DMA bit is set when the
DMA finishes its transfers, but the SCSI transfer may still be
in progress. If connected as a Target, IREO and lACK
should be sampled until both are FALSE. If connected as
an Initiator, a phase change interrupt is used to signal the
completion of the previous phase. It is possible for the
Target to request additional data for the same phase.
07

In this case, a phase change will not occur and both IREO
and lACK are sampled to determine when the last byte was
transferred.
SCSI Bus Reset. The SCSI generates an interrupt when the
IRST signal transitions to TRUE. The device releases all
bus signals within a b~s-clear delay of this transition. This
interrupt also occurs after setting the ASSERT IRST bit
(Initiator Command Register, bit 7). This interrupt cannot
be disabled. (Note: IRST is not latched in bit 7 of the
Current SCSI Bus Status Register and is not active when
this port is read. For this case, the Bus Reset interrupt is
determined by default.)
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
31 and 32, respectively.

Ixlxlxlxlxlxlxlxl
lACK
IATN

Busy Error
Phase Match
Interrupt Request Active

Parity Error

I~=
~~/O
IMOO
IREO

OMA Request

IBSY

End of OMA

IRST

Figure 31. Bus and Status Register

. Figure 32. Current SCSI Bus Status Register

Parity Error. An interrupt is generated for a received parity
error it the ENABLE PARITY CHECK (bit 5) and the
ENABLE PARITY INTERRUPT (bit 4) bits are set (1) in the
Mode Register. Parity is checked during a read of the
Current SCSI Data Register and during a DMA receive
operation. A parity error can be detected without generating an interrupt by disabling the ENABLE PARITY INTER-

RUPT bit and checking the PARITY ERROR flag (Bus and
Status Register, bit 5)The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
33 and 34, respectively.

565

SCSI FUNCTIONAL DESCRIPTION (Continued)

lACK
IATN
Busy Error
Phase Match
Interrupt RequeSt Active

IMSO

ParityEm>r

IREO

OMA Request

/BSY

........- - - - - - - - - EndofOMA

IRST

Figure 33. Bus and Status Register

Figure 34. Current SCSI Sus Status Register

Bus Phase Mismatch. The SCSI phase lines have the
signals 1110, CIID, and/MSG. These signals are compared
. with the corresponding bits in the Target Command Register: ASSERT 1//0 (bit 0), ASSERT CIID (bit 1), and
ASSERT IMSG (bit 2). The comparison occurs continually
and is reflected in the PHASE MATCH bit (bit 3) of the Bus
and Status Register. If the DMA MODE bit (Mode Register,
bit 1) is active and a phase mismatch occurs when IREO
tranSitions from FALSE to TRUE, an interrupt (IRO) is
generated.

operation (lDB7-/DBO and IDBP will not be driven even
through the ASSERT DATA BUS bit (Initiator Command
Register, bitO) is active). This may be disabled by resetting
the DMA MODE bit (Note: It is possible for this interrupt to
occur when connected as a Target if another device is
driving the phase lines to a different state).
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
35 and 36, respectively

A phase mismatch prevents the recognition of /REO and
removes the chip from the bus during an Initiator send
,

lololol11ololxlol

~:~

,Phase Match
Interrupt Request Active

IMSO

Parity Error

IREO

OMA Request

IBSY

EndofOMA

IRST

Figure 35. Bus and Status Register

566

Figure 36. Current SCSI Bus Status Register

Loss of BSY. If the MONITOR BUSY bit (bit 2) in the Mode
Register is active. an interrupt is generated if the BSY
signal goes FALSE for at least a bus-settle delay. This

interrupt is disabled by resetting the MONITOR BUSY bit.
Register values are displayed in Figures 37 and 38.

lACK
IATN

lolololxlxlxlolol
I L/OBP
~/SEL

Busy Error

VlO

Phase Match

CliO

Interrupt Request Active

IMSO

Parity Error

' - - - - - - - - - IREO

OMA Request

IBSY

End of OMA

IRST

Figure 37. Bus and Status Register

Reset Conditions. Three possible reset situations exist with
the Z85C80, as follows:
Hardware Chip Reset. When the signal RST is active for at
least 100 ns, the Z53C80 device is re-initialized and all
internal logic and control registers are cleared. This is a
chip reset only and does not create a SCSI Bus-Reset
condition.
.
SCSI Bus Reset (/RST) Received. When a SCSI /RST
signal is received, an IRO interrupt is generated and a chip
reset is perforrned. All internal logic and registers are
cleared, except for the IRO Interrupt latch and the ASSERT
/RST bit (bit 7) in the Initiator Cornrnand Register. (Note:
The /RST signal rnay be sarnpled by reading the Current
SCSI Bus Status Register, however, this signal is not
latched and rnay not be present when this port is read).
SCSI Bus Reset (/RST) Issued. If the CPU sets the ASSERT/RST bit (bit 7) in the Initiator Command Register, the
/RST signal goes active on the SCSI Bus and an internal
reset is performed. Again, all internal logic and registers
are cleared except for the IRO interrupt latch and the
ASSERT/RST bit (bit 7) in the Initiator Command Register.
The /RST signal will continue to be active until the ASSERT/
RST bit is reset or until a hardware reset occurs.
Data Transfers. Data is transferred between SCSI Bus
devices in one of four modes. 1) Programmed I/O, 2)
Normal DMA, 3) Block Mode DMA, or 4) Pseudo DMA. The
following sections describe these modes in detail (Note:
for all data transfer operations /DACK and /SCSICS should
never be active sirnultaneously).

Figure

3~.

Current SCSI Bus Status Register

Programmed 1/0 Transfers. Prograrnmed I/O is the most
primitive form of data transfer The /REO and /ACK handshake signals are individually monitored and asserted by
reading and writing the appropriate register bits. This type
of transfer is normally used when transferring srnall blocks
of data such as command blocks or message and status
bytes. An Initiator send operation would begin by setting
the CIID, 1//0, and /MSG bits in the Target Command
Register to the correct state so that a phase match exists.
In addition to the phase match condition, it is necessary for
the ASSERT DATA BUS bit (Initiator Cornmand Register,
bit 0) to be TRUE and the received I/O signal to be FALSE
for the Z53C80 to send data. For each transfer, the data is
loaded into the Output Data Register. The CPU then waits
for the /REO bit (Current SCSI Bus Status Register, bit 5) to
become active. Once/REO goes active, the PHASE MATCH
bit (Initiator Command Register, bit 4) is set. The /REO bit
is sampled until it becomes FALSE and the CPU resets the
ASSERT /ACK bit to complete the transfer.
Normal DMA Mode. DMA transfers are normally used for
large block transfers. The SCSI chip outputs a DMA
request (DRO) whenever it is ready for a byte transfer.
External DMA logic uses this ORO signal to generate
/DACK and a /RD or a /WR pulse to the Z53C80. DRO goes
inactive when IDACK is asserted and /DACK goes inactive
some time after the minimum read or write pulse width. This
process is repeated for every byte. For this mode, /DACK
should not be allowed to cycle unless a transfer is
taking place.

567

SCSI FUNCTIONAL DESCRIPTION (Continued)
Pseudo DMA Mode. To avoid the tedium of monitoring and
asserting the requesVacknowledgement handshake signals for programmed I/O transfers. the system may be
designed to implement a pseudo DMA mode. This mode
is implemented by programming the Z53C80 to operate in
the DMA mode. but using the CPU to emulate the DMA
handshake. DRQ may be detected by pOlling the DMA
REQUEST bit (bit 6) in the Bus and Status Register. by
sampling the signal through an external port. or by using
it to generate a CPU interrupt. Once DRQ is detected. the
CPU can perform a read or write data transfer. This CPU
readlwrite is externally decoded to generate the appropriate IDACK and /RD or twR signals.
Often. external decoding logic is necessary to generate
the ISCSICS signal. This same logic may be used to
generate IDACK at no extra cost and provide an increased
performance in programmed 1/0 transfers.,
Halting a DMA Operation, The EOP signal is not the only
way to halt a DMA transfer. A bus phase mismatch or a
reset of the DMA MODE bit (Mode Register, bit 1) can also
terminate a DMA cycle for the current bus phase.
Using the IEOP Signal. If lEap is used, it should be
asserted for at least 50 ns while IDACK and IRD or twR are
simultaneously active. Note, however, that if /RD or twR is
not active, an interrupt is generated, but the DMA activity
continues. :rhe lEap signal does not reset the DMA MODE
bit. Since the lEap signal can occur during the last byte
sent to the Output Data Register, the IREQ and lACK
signals are monitored to ensure that the last byte has
transferred.

568

Bus Phase Mismatch Interrupt. A bus phase mismatch
interrupt is used to halt the transfer if operating as an
Initiator. Using this method frees the host from maintaining
a data length counter and frees the DMA logic from
providing the lEap signal. If performing an Initiator send
operation, the Z53C80 requires IDACK to cycle before
lACK goes inactive. Since phase changes cannot occur if
lACK is active, either IDACK must be cycled after the last
byte is sent or the DMA MODE bit must be reset in order to
receive the phase mismatch interrupt.
Resetting the DMA MODE Bit. A DMA operation may be
halted at any time simply by resetting the DMA MODE bit.
It is recommended that the DMA MODE bit be reset aiter
receiving an lEap or bus phase-mismatch interrupt. The
DMA MODE bit must then be set before writing any of the
start DMA registers for subsequent bus phases.
If resetting the DMA MODE bit is used instead of lEap for
Target role operation, then care must be taken to reset this
bit at the proper time. If receiving data as a Target device,
the DMA MODE bit must be reset once the last DRQ is
received and before IDACK is asserted to prevent an
additional /REQ from occurring. Resetting this bit causes
DRQ to go inactive. However, the last byte received
remains in the Input Data Register and may be obtained
either by performing a normal CPU ",ead or by cycling
IDACK and IRD. In most cases, lEap is easier to use when
operating as a Target device.

. READ REGISTERS

1071061051041 031 ~:i:1 ~~i
I~/OBO
Address: 0

1071061 051 041D31~~:11:1
Address: 3

I~
~::::

~/0.e1

IDB2

Assert/MSG

10B3

Assert/REO

1DB4

·0·

IOB5

Last Byte Sent

IOB6
IOB7

Figure 42. Target Command .Reglster

Flgure39. Current SCSI Data Reglster

Address: 1

I071 osl.05 1.04 1.Da 1.02.
(Re1ad
011001
Only)

AssertOataBus
Assert/ATN
AssertlSEL

IMSG

Assert/BSY

IREO

Assert lACK

IBSY

Lost ArbRration

IRST

Arbitration in Progress
Assert/RST

Figure 40. Inltiator Comm and Register

107 106 105 104 1031~:i:~ r:i
~Arbitrate
Address: 2

OMAMode

Figure43. Current SCSI Bus Status Register

10710sI051041D31~:i~~r::i
Address: 5

~:,~

Phase Match

Monijor/BSY

Interrupt Request Active

Enable IEOP Interrupt

Parity Error

Enable Parity Interrupt

OMARequest

Ena,ble Parity Checking

End of OMA

TargetMod~
·0·

Figure 44. Bus and Status Register

Figure41. Mode Register

569

READ REGISTERS (Continued)
Address: 6

(Read Only)

Address: 7

(Read Only)

Imloolool~loo(~I~lool

1,071061051041031021011001

I~::

~
~/OB2

·X·

~=Oon1Care

1DB3

10B4

Figure 46. Reset Parity/Interrupt

IOB5

10B6
IOB7

Figure 45. Input Data Register

WRITE REGISTERS
Address: 0

Write Only)

Address: l'

1071061051041031021011001

L -_ _ _- ' -_ _

IDBO
IDBl
IOB2

IDB3
1DB4

' - - - - - - - - - IOB5

IDB6
L -_ _ _ _ _ _ _......._

IDB7

Figure 47. Output Data Register

570

(Wrile Only)

Imloolool~lool~I~lool

Assert Data Bus
Assert/ATN
AssertlSEL
Assert/BSY
Assert lACK

·0·
Tesl Mode
Assert/RST

Figure 48. Initiator Command Register,

WRITE REGISTERS (Continued)
Add(ess: 2

(Write Only)

Address: 5

loolool~I~IOOlool~IOOI

1071061051041031001011001

~:::.
~
L-=:

1 .
"X"

Figure 52. Stan DMA Send

Monitor /BS'f

Enable 1E0P In\enupt

......- - - - - Enable Parity Interrupt
Enable Parity ClJeddng

L..-______
L..-_ _ _ _ _ _ _

T~ModIt

1,---------

Address: 6
"0"

1071061~1~lool~101Iool

Figure 49. Mode Register

Address: 3

(Write Only)

& . . . 1_ _ _ _

'X'

Figure 53. Stan DMA Target Receive

1071~1051~looI00101Iool

~=::
L-=:
~

Assert/MSG

L..-_ _ _ _ _ _

AssertlREQ

Address: 7

"X"
.

L -_ _ _ _ _ _ _ _

(Wri\e Only)

I071oslo51~lool00lo1lool
L . . I_ ' _ _ _

"X"

Last'By\eSeni

Figure 54. Stan DMA Initiator Receive
Figure SO. Target Command Register

(Write Only)

Address: 4

107Iosl05I~looI02101Iool

~
!

IDBO
IDB1

1DB2

IDB3
IDB4
/085

IDB6
/DB7

Figure 51. Select Enable Register
Note: X = Don't care

571

ABSOLUTE MAXIMUM RATiNGS
Voltages on all pins with
respect to GND ........................................ -O.3V to +7.0V
Operating Ambient
Temperature ........................... See·Ordering Information
Storage Temperature ............................. -65°C to + 150°C

Stresses greater than those. listed under Absolute Maximum Ratings may cause permanent damage to this device. This is a stress rating only; operation of the device at
any condition above those indicated in the operational
sections of these specifications is not implied. Exposure to
absolute maximUm rating conditions for extended periods
may affect device reliability.

STANDARD TEST CONDITIONS
The DC characteristics and capacitance section below
apply for the following standard test conditions, 'unless
otherwise noted. All voltages are referenced to GND.
Positive current flows into the referenced pin. Standard
conditions are as follows:
•

+4.5V!'> Vee!'> +5.5V

•

GND = OV

•

TA as specified in Ordering Information

2.2K

From Output

50 pf
+5V

2.1 Kn

Figure 56. Open-Drain Test Load
From Output
Under Test

lOOp!

Figure 55. Standard Test Load

572

2.4 _ _ _

0.4

2.0

X>P:~~~<:: )(
0.8

0.8

Figure 57. Switching Test Waveform

~~~---

----~---

DC CHARACTERISTICS
Symbol

Parameter

Voo
V1H
V1L
IIH 1

Supply Voltage
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
SCSI Bus Pins

V1H = 5.5V
V1L = OV

High-Level Input Current
All Other Pins
Low-Level Input Current
SCSI Bus Pins
Low-Level Input Current
All Other Pins

V1H = 5.5V
V1L = OV
V1H = 5.5V
Vu. =OV
V1H = 5.5V
V1L = OV

High-Level Output Voltage
High-Level Output Voltage
Low-Level Output Voltage
SCSI Bus Pins
Low-Level Output Voltage
All Other Pins

IOH = -3mA
IOH = -250 pA

11H2
III1
I'L2
VOH 1
VoH2
VOL 1
VOL2

100
CIN
COUT
Cuo
TA

Supply Current
Input Capacitance
Output Capacitance
Bidirectional Capacitance
Operating Free-Air Temperature

Condition

Min

Max

Units

4:5
2.0
-0.3

5.5
5.5
0.8

V
V
V

-50

-10

2.4
Voo-0.8

IOL = 48mA

0.5

IOL = 7 mA

0.5

40
10
15
20
70

mA
pI
pI
pI
°C

573

AC CHARACTERISTICS
General Timing
PCLK

IWIIREO
Request

IWIIREO
Wait

ICTSlrrRxC,
RTxC
Receive

RxO

ISYNC

External
ICTSlrrRxC,
RTxC
Transmit

,,' ?:'r----X---X-~
@------t

ICTSlrrRxC
Output

IRTxC

ICTS/ITRxC

ICTSlrrRxC,
IDCO

ISYNC

Input

--C=bd
--~

{-----

Figure 58. General Timing

574

AC CHARACTERISTICS (Continued)
Z85C80 General Timing
Notes t

Symbol

Parameter

1
2
3

TdPC(REQ)
TdPC(W)
TsRXC(PC)

PCLK FALL to NJI/REO Valid Delay
PCLK FALL to Wait Inactive Delay
IRxC Rise to PCLK Rise Setup Time

N/A

4
5
6

TsRXD(RXCr)
ThRXD(RXCr)
TsRXD(RXCf)

RxD to IRxC Rise Setup Time
RxD to IRxC Rise Hold Time
RxD to/RxC FALL Setup Time

0
125
0

[ 1)
[1)
[1,5)

7
8
9

ThRXD(RXCf),
TsSY(RXC)
ThSY(RXC)

RxD to IRxC FALL Hold Time
ISYNC to IRxC Rise Setup Time
ISYNC to /RxC Rise Hold Time

125
-150
5TcPc

[1,5)
[ 1)
[1)

10
11
12

TsTXC(PC)
TdTXC(TXD)
TdTxCr(TXD)

ITxC FALL to TxD Delay
ITxC Rise to TxD Delay

13
14
15

TdTXD(TRX)
TwRTXh
TwRTXI

IRTxC High Width
IRT xC Low Width

120
120

[6)
[6)

16a
16b
17

TcRTX
TxRX(DPLL)
TcRTXX

IRTxC Cycle Time
DPLL Cycle Time
Crystal Oscillator Period

400
50
100

[6,7)
[7,8)
[3)

18
19
20

TwTRXh
TwTRXI
TcTRX

ITRxC High Width
/TRxC Low Width
ITRxC Cycle Time

120
120
400

21
22

TwEXT
TwSY

IDCD or ICTS Pulse Width
ISYNC Pulse Width

120
120

/TxC FALL to PCLK Rise Setup Time

Min

Max
200
300

N/A

N/A
150
150

TxD to /TRxC Delay

[1.4)

[2.4)
[2)
[2,5)

140

1000

[6)
[6)
[6,7)

Noles:
[1] /RxC is /RTxC or TRxC, whichever is supplying the receive clock.
[2] /TxC is {l'RxC or RTxC, whichever is supplying the transmU clock.
[3] Both /RTxC and /SYNC have 300 pi capacitors to ground connected to them.
[4] Synchronization ol/RxC to PCLK is eliminated in divide by four operation.
[5] Parameter applies only to FM encoding/decoding.
[6] Parameter applies only for transmitter and receiver; DPLL and baud rate timing requirements are identical to case PCLK requirements
[7] The maximum receive or transmit data is 1/4 PCLK
[8] Applies to DPLL clock source only Maximum data rate of 1/4 PCLK stili apphes. DPLL clock should have a 50% duty cycle.

Units in nanoseconds (ns)

575

AC CHARACTERISUCS
Z85C80 System'Timing
ICTSlITRxC
Receive

IWIIREO
, Request

IWIIREO
Wait

/sYNC

Output

liNT

IRTxC
Transmit

IWI/REO
Request
1---<.5i)-----4~

IWIIREO
Walt

IDTRl/REO
Request

liNT
14---(8)----t
ICTSlITRxC,

lOCO

/SYNC

Input

K
K
~

liNT
10

Figure 59. System Timing

576

AC CHARACTERISTICS (Continued)
Z85C80 System Timing
Min

Max

Notes t

IRxC Rise to /VV//REQ Valid
IRxC Rise to Wait Inactive
/RxC Rise to ISYNC Valid

8
8

12
14

[2]
[1,2]
[2]

TdRXC(INT)
TdTXC{REQ)
TdTXC{W)

IRxC Rise to liNT Valid Delay

/TxC Fall to /VV//REQ
/TxC Fall to Wait Inactive

5
5

8
11

TdTXC(DRQ)
TdTXC{INT)
TdSY{INT)
TdEXT{INT)

/TxC Fall to IDTR//REQ Valid
/TxC Fall to liNT Valid
ISYNC to liNT Valid
IDCD or ICTS//TRxC to liNT Valid

4
6
2
2

10
6
6

Symbol

Parameter

1
2
3

TdRXC(REQ)
TdRXCW)
TdRXC(SY)

5
6
7

8
9
10

[1,2]
[3]
[1,3]
[3]
[1,3]
[1]
[1]

Noles:
[1] Open-drain output measured with open-drain test load.
[2] /RxC is /RTxC or /CTS//TRxC, whichever is supplying the receive clock.
[3] /TxC is /CTS//TRxC or RTxC, whichever is supplYing the transmit clock.

t Units equal to TcPC

577

AC CHARACTERISTICS
Z85C80 Additional Timing

'H:1rr-----w

.---

PCLK

~
AlIB,OI/C

ISCCCS

IRO

-®-----

)

Active

Valid

@- H

~f-®

'27>

-@-

"'"

)
J

IWR

b
07-00
Write

@-I/WI/REO
Watt

+-----@

/WI/REO

10TRl/REO
Request

-I-@

~ f-----

\
.J3'lI
'=

Request

=4-@- f-----

)

"'"

""''=

liNT
37

Figure 60. ReadIWrite Timing

578

®-Ll'

'""-

@I-

i"-"

~
'2'"

~
~K-J

--..@

-66l----o

....

07-00
Read

~-.

--' ~,
8-BIt '

Static RAM'
4 KbltsX8

Ethernet DrIVers

16-Blt
16-Blt
CPUZSOO2
Microcontroller

Direct Memory
Access
Direct Memory
Access

16-Bit Bus

~
~

Direct Memory
Access

2......

Communications
Controller
(USC Z16C30)

8- or
16-Blt
Dual-Port RAM
(System FIFO)

~ ~

~ 8- or 16-Blt

8-BIt

Dip Switches

General 1/0
(Test, LED, LCD)

Receive
Driver

Channel A

Conn~or

Transmit
Driver

Receive
Driver

I-Connector

Transmit
Driver

I-Channel B

Main Bus Connector

Figure 1. Dual-Channel Communications 'Board for an tBM 80386 PC consists of four main sections: The
communications controller (a Z16C30 Universal Serial Controller), an interface to the PC's bus, buffer memory,
and two communications channels. In this application, Channel A drives an Ethernet Interface and Channel BI
drives a laser printer through an RS-232 pon.

592

To Other C~annel

Receive DMA
Control

Receive Data

I
I

!!l

Receive'
FIFO
(32 byte)

I
I

'iii

...£

:;;

~
a

Interrupt
Control

m
CPU ~

r--

~
L.....-

Channel
Conttol

Transmit
FIFO
,(32 byte)

Receiver

~
J

VOAnd
Device
Status

t--

Clock MUX
1...1. DPLL
2. Counters
3. BRGO
4. BRG1

Receivel
Transmit
Clocks

Transmitter

Transmit
DMAControl

TransmitData

Figure 2. At The Heart of the dual-channel communications board is the Z16C30 Universal Serial Controller chip,
which supports 10 different protocols and eight encoding formats. In the upper portion ofthe diagram, serial data
from the receiver is placed In a 32-byte FIFO buffer prior to being placed onto the 16-bit internal bus under DMA
control. Similarly, data to be transmitted from the bus is placed in the FIFO transmit buffer and then sent in serial
form by the transmitter.

The software is arranged to have the CPU execute from the
ROM (minimum of 8K bytes) by first checking the two
different protocol settings in the DIP switches which have
been set for these particular protocols (Ethernet and RS232). The protocol initialization procedures are then executed from ROM.
The Dual Port RAM (or System FIFO) buffers the syscom
transactions with the IBM 386 PC host system via the Main
Bus connector. The size (byte depth) qesign of the Dual
Port RAM (hereinafter referred to as DPR) depends on the
difference in speeds between the host and syscom. The
greater the speed difference, the larger the byte buffering
needed. In this case, 32 each of transmit and receive
buffering are enough to handle the 80386's 12 MHz speed.

One of the main features of a global system network
arrangement is the varying amount of host/slave (source!
target) dissimilar nodes (IBM PCs or their clones, MACs,
Work Stations, printers, modems, terminals, etc) communicating with each other. Based on design complexity
(state of the art speed, distance between nodes, data
crunching needs, etc.), the systems' communication
board(s) can carry 4,8, 16, or even 32 channels ... AND
with differing protocols and formats all working simultaneously. As the number of channels increases, the speed
and bandwidth of the serial controller plays an increasingly
important role in helping the syscom's CPU by reducing
bus impact which translates to keeping data throughput
from being derated.

593

TWO CHANNEL COMMUNICATIONS OPERATION
The following example'demonstrates and illustrates a two
channel design for data throughput events. This hypothetical example uses an IBM 386 PC as the host system which
is communicating over a network to a slave Work Station
via syscom 'and an IEEE 802.3 Ethernet protocol (via
channel A) using a synchronous serial port. At the same
time, the host is multitasking by se(lding data through the
syscom (via channel B) to an RS232 asynchronous port to
a laser printer (Figure 3). The syscom board is the interfacing
link for control and data movement between the host
and slaves.
Before starting the dynamic interchange of data, all initialization procedures of the syscom are accomplished.
These. include Power-On reset, reading the setting of the
DIP switches for the 802.3 Bhernet protocol, and writing to
the USC's Clock Mode Control Register to select a clock
source for the receiver and transmitter.
While the host performs its normal application functions,
the syscom remains in an open mode waiting for either the
network device or the host to request its services. In this
example, the IBM 386 PC becomes the host by requesting
data from the Work Station. At the same time it's sending
data to the laser printer. The first part of the scenario
begins with the Work Station (slave) responding to the
host's request. The second part explains how the host
sends data to the laser printer while simultaneously receiving data from the Work Station (throughout this article
reference Figure 1 and the timing diagrams in
Figure 3 ~nd 4).

594

Part"1. Channel A
After initialization procedures, which included the host
having control and requesting data from the Work Station,
the scenario begins with channel A receiving serial data
from the network. When the network has a message from
the Work Station, the network alerts the syscom CPU that
it has data for the target host. The syscom CPU alerts the
host. that a message is coming frolT) the network and then
acknowledges the request from the network (Figure 4).
The network begins to send the IEEE 802.3 raw data (ones
and zeros) from the target system.

Ethernet ReceivefTransmit Driver Interface
The 802.3 mode implements the data format with a 16-bit
address compare. In this mode, DCD (Data Carrier Detect)
and CTS (Clear To Send) implement the carrier sense and
collision detect interactions with the receiver and transmitter. Figure 3 shows this hardware interface and related
timing.
Bit combination 1001 selects Ethernet 802.3 mode via the
channel mode register where each message is preceded
by a preamble (protocol) and a start bit of one and is
terminated with CRC (Cyclic Redundancy CheCk), withoui
any trailing delimiter. To meetthe 802.3 standard, biphaseliwel (BIPHASE-L) data encoding must be programmed in
the Transmit Mode Register(TMR). An idle line condition of
mark or space, selected in the TCSR, will allow external
logic to terminate the transmit signal due to the absence of
mid-bittransition. In this mode, the CTS input is then used
to signal a collision detect to the CPU and disable the
transmitter.

--~---

-----

IlPBKlWDTD
Communications
Controller
(USC Z16C30)

N.C.

Mode 1

S.8K

Ethernet
Driver
(SEEQ) 8023

DI-A

Rx+

DI-B

AxReceive and
Transmit Clock (/RxC)

AxC

Receive Data (RxD)

'AxD

Clear to Send (/CTS)

20.2
±1%
Tx+

CSN

Data Carrier

DO-A
243
±1%

DO-B

Tx-

To Connectors
and Cable

COll

Detect (lOCO)

Transmit Complete
(lTxC)

TxC

TransmH Data
(TxD)

TxD

CI-A

COll+

COll-

TxEN
Mode 2

20.2
±1%

+5
(a)
Transmit Clock
(USC)

Transmission:
Transmit
Clock (SEEQ)
sample

Transmit
Enable _ _ _ _ _ _ _ _ _ _ _ _ _ _......

Note: /Transmit clock Pin of USC Is Programmed to be used as a SIgnal to Flag the End olTransmlL

(b)

Figure 3. The Ethernet Interface consists of an ethernet driver, which connects to the communications controller
through clock and data lines (a). All that's required to change to another communications protocol Is replacing
the receive and transmit drivers, connectors,. and cable. Transfer of Ethernet data to the driver is controlled by
the communications controller (b). Serial data on the TxO pin is sent on the falling edge of the TxC.

595

ICS

X. .____

A lIB, OIlC

ISITACK

lAS

~"'_ _ _

-J

Read I/Write

IRO or IDS

-'X,,_. . .__

Address _ _ _ _

...I

Figure 4. The USCIEthernet Interface handles reading and writing of data through the two serial channels. Here,
after the controller acknowledges a network request, raw IEEE 802.3 data is read from an Ethernet serial link.

Biphase Encoding
The USC can be programmed to encode and decode the
serial data in any of the following seven ways; NRZ, NRZIM, NRZI-S. BIPHASE-M. BIPHASE-S. BIPHASE-L. and
DIFFERENTIAL BIPHASE-L. The transmitter encoding
(TMR) method is selected independently of the receiver
, encoding method (RMR). The DPLL (Data Phase-Locked
Loop) is used to decode the receiving di:l!a

DPLL. Each channel in the USC contains a Digital PhaseLocked Loop to recover clock information from a data
stream with NRZI or Biphase encoding. The DPLL is driven
by a clock that is nominally 8. 16. or 32 times the receive
data rate. The DPLL uses this clock. along the data stream,
to construct a clock for the data. This clock is then routed
to the receiver. transmitter. or both. or to a pin for external
use. In all modes. the DPLL counts the input clock to create
nominal bit times.

596

As the clock is counted. the DPLL monitors the incoming
data stream for transitions. Whenever a transition is detected. the DPLL makes a counter adjustment (during the
next counting cycle). to produce an output clock which
tracks the incoming bit cells. The DPLL provides properly
phased transmit and receive clocks to the clock multiplexer.
Now. the data is examined by the USC for the Ethernet
protocol preamble of binary bit stream 0101 ... 01011. Any
other combination is not recognized. Once recognized.
the preamble is stripped off and the USC looks for a 16-bit
address which is matched against a preprogrammed
address in the USC. When matched. the USC proceeds to
accept the rest of the data (If no match. data is not
recognized). The first word of the address is stripped off
and the following data is stored in the USC's 32 byte
receive FIFO buffers.

As the data shifts through the Receive Shift Register, the
USC code watches for specific bit patterns, counts bits,
and at the appropriate time, transfers data to the receive
FIFO. Also, the microcode checks status and generates
status interrupts when appropriate.
USC Receiver
The receiver performs all of the functions necessary to
convert serial data back to parallel for the processor. Serial
data on the RxD is sampled on the rising edge of the /RxC
(receive clQck) pin for all formats and encoding modes,
except for Biphase encoding modes where both )RxC
edges are used for data sampling. The serial data is
received with the LSB (Least Significant Bit) first. The data,
however, can be stored in LSB or MSB first format in the
output FIFO's (LSB after reset). It is controlled by the CCAR
D15-11. In addition, the serial receiver can read the serial
data as words and put the byte first received in bits 15-8 of
the word and the byte which followed to occupy bits 7-0 of
the same word (default setting after reset). This order can
be swapped, and both arrangements are controlled by the
CCAR D15-11.
Error and status conditions are carried with the. data in the
receive (and transmit) FIFOs to greatly reduce the syscom
CPU overhead required to receive (or send) a message.
Specific, appropriately timed interrupts are available to
signal such conditions as overrun, parity error, framing
error, end-of-frame, idle-line-received, sync acquired,
transmit underrun, and others. Such internal signals as
receive FIFO load, received sync, transmit FIFO read and
transmission complete, can be sent to pins for use by
external circuitry.
Interrupts
The Master Interrupt Enable (MIE) bit in the ICR D15
globally enables or disables interrupts within a channel.
When the USC responds to an interrupt acknowledge from
the CPU, an interrupt vector is placed on the data bus, The
vector is held in the Interrupt Vector Register (IVR). To
speed interrupt response time, the USC can modify three
bits in this vector to indicate which type of interrupt is being
requested (IVR). These three bits are maskable by the
vector and includes the Status Level Control Field (ICR).
Each of the six sources of interrupts in each USC channel
(Receive Status, Receive Data, Transmit Status, Transmit
Data, I/O Status and Device Status) has three bits associated with the interrupt source: Interrupt Pending (IP).
Interrupt Under Service (IUS) and Interrupt Enable (IE).
If the IE bit for a given source is set. then that source can
request interrupts. Note that individua.1 sources within the
six groups also have interrupt enable bits which must be
set (ICR D7-0). Even though the IE bits can be reset. it will
not affect the IP bit being set by the interrupt condition.

The other two bits are related to the interrupt priority chain.
A channel in the USC may request an interrupt only when
no higher priority interrupt source is requesting one, e.g.,
when lEI is High for the channel. In this case, the channel
activates the /INT signal. The CPU then responds with an
interrupt acknowledge cycle and the interrupting channel.
places a vector on the data bus.
DMAControl
At the trigger point of the USC Receive FIFO buffers
(preprogrammed anywhere from 1 to 32 bytes), a DMA
request is generated. The DMA controller then requests,
through a standard requesVacknowledge protocol, the
syscom CPU for the 16-bit bus. Once recognized, the DMA
controller begins sending data to the StatiC RAM or the
DPR (system FIFO) in "Flyby Transfer" mode (all 32 bytes
sent in one burst).
Interrupt Acknowledge Handshake
USC interrupts occur asynchronously, and to allow time for
the internal prioritization. of interrupts during an interrupt
acknowledge, the USC responds to the interrupt acknowledge with the /IVACK signal when this prioritization
is complete. Two differentlypes of response on /IVACK are
available, selected by bit one in the BCR. When this bit is
reset toO, the /IVACK signal operates as a/READY signal.
When it is set to 1, the /IVACK acts as a /WAIT signal.
The DMA activates the RxACK signal for the Flyby mode.
If the SRAM is full, data can go directly to the DPR. If Flyby
mode is not required, normal flow-through transfers can
be used.
Syscom CPU/Host Handshake
After the syscom CPU acknowledges (and releases) the
DMA request for the 16-bit bus, the CPU then requests the
host to receive data. When the host receives the request.
it sends interrupt acknowledgement back to the CPU and
enables its own bus and memory for data reception.
During this time, the syscom SRAM has been loading the
DPR, which when enabled, transfers data to the host
memory.
This chain of events continues uninterrupted (except for
Non-Maskable Interrupts) until the Work Station has
completed its message to the host. When the host receives
the postamble data decoded by the USC, to produce the
terminate transmission signal, the host acknowledges the
termination and frees the syscom CPU. Practically, this
puts channel A on the syscom board back to an idle mode
for any new receive/transmit messages.

597

USC Bus Interface
The USC is unique in that the bus interface for the device
provides the resources necessary to interface the USC to
virtually any type of bus. The USC directly supports either
a 16-bit bus or an 8-bit bus, but may be easily connected
to a 32-bit bus as well. The control signals provided allow
connection to either multiplexed address/data type bus
or to a separate (non-multiplexed) address and data type
bus. Interrupt acknowledge is signaled either throutjh a
status line br via a dedicated interrupt acknowledge strobe
signal. In addition, fly-by DMA transfers are supported"for
both receive and transmit.

Multiplexed Transactions. During a read transaction the
/DS (or IRD) Signal, along with R//W selecting a read,'
strobes the data out of the USC. The register address is
latched by the riSing edge of the lAS signal, along with an
active ICS (Chip Select) and an inactive /SITACK (Status
Interrupt Acknowledge) signal.

It is important to note that the USC does not have a clock
input The USC "looks" like a memory rather than a traditional peripheral device. All bus timing information is
carried in the control signals for the bus and interrupt. DMA
requests are generated asynchronously.

There are three different Signals available to strobe (read)
multiplexed interrupt acknowledge ,vector transactions
from the USC. Signals /DS or /RD read the vector' from the
USC and set the 'IUS (Interrupt under Service) bit in the
interrupt section. The third Signal, IPITACK (dedicated
interrupt acknowledge strobe), performs this same function. The kind of interrupt acknowledge function needed
determines which one of the three strobes'are used.

Multiplexed Case, The multiplexed address/data bus carry
16-bit addresses and data to and from the USC (16-bit
case). The addresses on AD7-0 are latched into the USC
on the rising edge of the /AS signal along with chip select
and the Interrupt Acknowledge, status on th~ /SITACK
signal. Because the register address is latched on every
bus transaction, all of th~ registers in the USC are directly
accessible. This bus interface provides the hig,hest bus
bandwidth capability for the USC.

Ttw 8-bit multiplexed bus is the same as the

16-bit bus
except that AD7-0 carry addresses to the USC and 8-bit
data to and frolT) the USC (AD 15-8 is not used). Fly-by data '
transfers are 8-bits in this case.
Non-Multiplexed Case. AD15-0 carry 16-bit data to and
from the USC. Orily the receive and transmit data registers
and the Channel Command/Address Register (CCAR) are
directly accessible, with all other registers being accessed
by first writing a register address to the CCAR and then
accessing the desired register. This bus interface provides
the same high bUll bandwidth as the multiplexed 16-bit
bus when accessing either the transmit or receive data
registers. These registers are still accessed directly in this
case using the D/C signal, or via fly-by DMA transfers using
ITXACK or IRXACK.
The non-multiplexed 8-bit case enables AD7-0 to carry
8-bit data to and from the USC with AD15-8 unused. The
rest of the explanation is the same as in the 16-bit case
except that fly-by DMA transfers are 8-bits.
USC Bus Transactions
The following multiplexed and non-multiplexed bus'
transactions are described in a general· sense without
referring to 8- or 16-bit address/data size.

598

During a write transaction the IDS (or /WR), along with the
R//W selecting a write, strobes the data into the USC. The
register address is latched by the rising edge of the lAS
signal, along with an active ICS and an inactive ISITACK
signal.

, Non-Multiplexed Transactions. During a non-multiplexed
read transaction, the IDS (or IRD) signal, along with R//W
selecting a read, strobes the data out of the USC. The
leading edge of the strobe Signal latches both an active
ICS and an inactive ISITACK signal.
During a non-multiplexed write transaction, the IDS (or
IWR) signal, along with R//Wselecting a write, strobes the
data into the USC. The leading edge of the strobe signal
latches both an active ICS and an inactive lSI TACK signal.
In both the multiplexed and non-multiplexed cases of DMA
fly-by transactions of reads and writes, the ICS and
ISITACK signals are inactive.
Prior to this transmission example, when the host had
requested the message from the Work Station, the exact
reverse chain of events took place. The host had established
the handshake with the syscom CPU, which in turn requested the DMA controllers. the DMA controllers then
requested the USC, which enabled its Transmit FIFO
buffers and the data was received and encoded by the
USC into the 802.3 protocol and sent out (transmit) to the
Work Station via the Ethernet.
USC Transmitter. The transmitter performs all of the necessary functions to convert parallel data from the processor
into the appropriate serial bit stream (Figure 3b)" Serial
data on the TxD pin is sent on the falling edge of the IT xC
(transmit clock) pin for all formats and encoding modes
except for Biphase encoding mode where both ITxC
edges are used for data transmission. The serial data is
transmitted with the LSB first. The data, however, can be

stored in LSB or MSB first format in the input FIFO's (LSB
after reset). It is controlled by the CCAR 015-11. Also, the
transmitter can be programmed to shift bits 15-8 of a word
first (after reset), followed by byte 7-0 of the same word, or
vice versa. This function is controlled by the CCAR 015-11.
Now, let's look at what channel B was doing during channel
A's flowthrough or Flyby.

PART II. Channel B

status interrupts have four individually enabled sources;
receive character count FIFO overflow, DPLL (Digitally
Phased Locked Loop) sync acquired, plus BRG! and
BRG2 zero count.
Transmission Preparation
Two other areas of data manipulation by the USC, needed
to prepare for network transmission, are parallel 'to serial
conversion and encoding the data for asynchronous transmission.

The multitasking host required laser printing while it was
When the data is ready, the USC sends it to the channel B
communicating with the Work Station. Whenever the host . transmit driver which is set for RS232 asynchronous mode.
is ready to send the message to be printed, it interrupts the
The RS232 has the proper voltage levels and transmits the
serial data onto the network. The laser printer queue's the
syscom CPU. The syscom CPU acknowledges the interdata in its buffers. If the printer buffers are full, an error
rupt and enables the DPR receive buffer latches. The host
message is sent back to the USC. The USC can either
'loads the DPR via the main bus connector. When the DPR
periodically continue to send the data or wait for a buffer's
is full (or when the host sends a finished message signal)
and the USC is ready, the CPU enables the DPR data out
empty Signal from the printer.
latches and the message is put onto the IS-bit bus in either
The USC's Programming Particulars
byte or word format.
The registers in each USC channel must be programmed
Now, the DMA controller accepts the data and enables the
by the syscom CPU to configure the channels. Before this
happens, syscom program's the bus interface by writing to
USC transmit FIFO buffers to store up to 32 bytes. The FIFO
the Bus Configuration Register (BCR) shown in Figure 5.
byte level is programmed into the Transmit Interrupt Control
Each channel is controlled by a set of thirty IS-bit registers
Register (TICR) which generates a DMA request whenever
which are almost all readable and writable. The BCR is the
the level drops below this predetermined mark. The USC
then performs the necessary functions of preparing the
IS-bit register in the bus interface which configures the
data to be transmitted out channel B to the network. The
type of bus interface. It has no specific address and is only
accessible immediately after a hardware reset of the
preparations include transmit status interrupts, 1/0 status
device.
interrupts (which are independent of the programmed
functions), and the device status interrupts. The device
Address: None

Shift Right Addresses
Double Pulse INTACK
16-Blt Bus

0*
Reserved
3-State All Pins
Separate Address for 8-Bit Bus

* Must be programmed as O.
Figure 5. Bus Configuration Register (BeR)

599

Non-Multiplexed Bus

USC registers (Table 1) are accessed explicitly, directly, or
indirectly, depending on the bus type and the specific
control signals used. In all cases, the BINI signal selects
between a byte access (BINI high) and a word access
(BINI low). When an 8-bit bus is selected, the BINI signal
is always forced to a 1, selecting a byte access. The UI/L
signal chooses between the upper byte (UI/L high) and the
lower byte (UI/L low) in the case of a byte access. UI/L is
always low for a word access.

In the non-multiplexed bus case, the registers in each
channel are accessed indirectly using the address pOinter
in the Channel Command/Address Register (CCAR) of
each channel. The address of the desired register is first
written to the CCAR and then. the selected register is
accessed; the pointer in the CCAR is automatically cleared
after this access. The RDR and TDR are still accessed
directly using the D/C pin, without disturbing the contents
of the pointer in the CCAR.

Only three registers in the USC have explicit addressing;

Polling

1 hese are the BCR, for the first write after a hardware reset;
the RDR, either via a read with the DIIC signal high, or by

Polling is a software method of avoiding interrupts and is
the simplest mode to implement. In this mode, the software
must poll the USC to determine when data is to be written
or read to or from the USC. All interrupts have to be
disabled (lCR D15). The registers in the USC are automatically updated to reflect current status. The CPU polls
the Daisy-Chain Control Register (DCCR) to determine
status changes and then reads the appropriate status
register to find and respond to the change in status. USC
status bits are grouped according to function to simplify
this software action.

,a fly-by DMA read; and the TDR, either by a write with the
DI/C signal high, or by a fly-by DMA write:
In the non-multiplexed bus case, only the CCAR is accessed directly, while in the multiplexed bus case all USC
registers are accessed directly. Further, when a separate
address bus is, used, all registers are directly addressed.
The first write to the USC, after a hardware reset, programs
the BCR. After that, the normal channel registers are
accessed.

MuHiplexed Bus

In the multiplexed bus case, all registers are directly
addressable, via the address latched by the Address
Strobe (AS) at the beginning of a bus transaction. The
address is decoded from either AD6-ADO (Shift Right) or
AD7-AD1 (Shift Left). This is controlled by the Shift RighV
Shift Left bit in the BCR. The D/C pin is still used to directly
access the receive and transmit data registers (RDR and
TOR) in the multiplexed bus; if D/C is High, the address
latched by AS is ignored and an access of RDR orTDR is
performed.
Multiplexing data and address onto the same lines makes
more efficient use of pins and facilitates expanSion of the
number of data and address bits. Multiplexing also allows
straight-forward addressing of a peripheral's internal
registers, which greatly Simplifies I/O programming.

600

Two Important Points
There are two important points to note about the USC. First,
the Channel Reset bit in the CCAR places the channel in
the reset state. To exit this reset state, either a word or all
zeros is written to the CCAR (16-bit bus) or a byte of all
zeros is written to the lower byte of the CCAR (8-bit).
Secondly, after reset, the transmit and receive clocks are
not connected. Therefore, upon initialization, a write to the
Clock Mode Control Register (CMCR) establishes a clock
source for the receiver and transmitter.
Register addresses are shown in Table 1 and the bit
assignments for the registers are shown in Figure 6.

Reset
Any Transaction
Up To and Including
BCRWrite

No lAS

At least One lAS

NonMultiplexed
Bus

BCR
Write
Transaction

Multiplexed
Bus

I
BCR[2)-O
BCR(15)=1

8-BitWlth
Separate
Address

BCR[2)-O
BCR(15)=O

I
BCR[2]-1

BCR[2)-O
BCR(15)-1

J
8-BIt Without
Separate
Address

16-Bit

8-BItWlth
Separate
Address

BCR[2)-O
BCR(15)-O

S-Brt Without
Separate
Address

BCR[2)-1

+
16-BIt

Note:
The presence of one transaction wkh an lAS active, between reset up to
and Including the BCR write, chooses a multiplexed type of bus.

Figure 6. BeR Reset Sequence and Bft Assignments

Table 1. Register Address List
Address

Address

A4-A0

A4-A0
10010
10011
10100
10101

RCSR
RICR
RSR
RClR

Receive
Receive
Receive
Receive

Test Mode Data Register
Test Mode Control Register
Clock Mode Control Register
Hardware Configuration Register

10110
10111
1XOOO
11001

RCCR
TCOR
TDR
TMR

Recieve Character Count Register
Time Constant 0 Register
Transmit Data Register (Write Only)
Transmit Mode Register

IVR
IOCR
ICR
DCCR

Interrupt Vector Register
I/O Control Register
Interrupt Control Register
Daisy-Chain Control Register

11010
11011
11100
11101

TCSR
TICR
TSR
.TClR

Transmit Command/Status Register
Transmit Interrupt Control Register
Transmit Sync Register
Transmit Count Limit Register

MISR
SICR
RDR
RMR

Mise Interrupt Status Register
Status Interrupt Control Register
Receive Data Register (Read Only)
Receive Mode Register

11110
11111

TCCR
TC1R

Transmit Character Count Register
Time Constant 1 Register

XXXXX

BCR

Bus Configuration Register

00000
00001
00010
00011

CCAR
CMR
CCSR
CCR

Channel
Channel
Channel
Channel

00110
00111
01000
01001

TMDR
TMCR
CMCR
HCR

01010
01011
01100
01101
01110
01111
1XOOO
10001

Command/Address Register
Mode Register
Command/Status Register
Control Register

Command/Status Register
Interrupt Control Register
Sync Register
Count Limit Register

601'

602

~ZiIm

ApPLICATION NOTE

USING THE Z16C30
UNIVERSAL SERIAL
CONTROLLER
WITH MIL-STD-1553B

INTRODUCTION
Zilog's Z16C30 Universal Serial Controller (USC) is a dualchannel multi-protocol data communications peripheral
that supports virtually any serial data transfer application.
However. because the USC is so flexible. it may be

confusing to a user interested in a particular application of
the device. This Application Note will describe the use of
the USC in a MIL-STO-15538 environment.

MIL-STD-15538
MIL-STD-15538 defines a serial data bus that was originally intended for use in aircraft. However. several attributes
of 1553B make it suitable for not only other military systems.
but industrial and process-control environments as well.
Chief among these attributes is employment of a command!
response protocol This guarantees a response within a
certain amount of time. Other attractive attributes include
high noise immunity and provision for redundant buses

Messages on the bus must be acknowledged within a
fixed amount of time which is an attractive feature of
1553B. A typical sequence could be: First. the Be sends
a command word. which contains the destination address
and a byte count of the .data words to follow; then it sends
the data words. The RT responds with a status word
showing proper receipt of the data. within a fixed amount
of time.

Devices attached to a 1553B, bus can operate as either a
Bus Controller (BC). a Remote Terminal (RT)or Bus Monitor
(BM). Both the BC and RT are capable of receiving a'nd
transmitting on the bus. while the BM is a receive-only
device Allowed transfers on the bus are BC-to-RT. RT-toRT. RT -to-Be and broadcast. All transfers on the bus occur
at the request of the current bus controller. even though the
Be may not be the source or destination of the data (as in
an RT-to-RT transfer).

The 1553B. uses a unique word format (Figure 1). Each
word on the bus is 20 bits long. The first three bits are
synchronization bits. which also identify the word as either
command. status. or data. The next 16 bits carry the actual
information. followed by a parity bit in bit position 20.
Because 1553B uses Manchester encoding. shown in
Figure 2. the sync patterns are unique and easily identifiable
by a receiver Both the receiver and the transmitter in the
use explicitly support this' word format and data
encoding.

The standard allows either a single bus controller or
multiple bus controllers. although only one may be active
at anyone time. Control transfer from one bus controller to
another is done either by polling. where the current bus
controller polls other potential bus controllers before transferring mastership. or in a round-robin fashion. Roundrobin means bus mastership passes from BC to BC in a
predetermined fashion after a fixed amount of time.

Note: All Signals with a preceding front slash, "/", are active
Low, e.g.: BIIW (WORD is active Low); (BIW (BYTE is
active Low, only); INIIS (NORMAL and SYSTEM are both
active Low).

603

Parity
Terminll' Status
Bus A Shutdown

Data
C~nt

Bus B Shutdown

Word

Dedicated Function Received

Broadcasrt Function Received

Addressing Error

Response Error

SubAddressf
Mode

Data Quantity

Data

Data Quality

Instrumentation

TIR

Instrumentation

Terminal
Address

Terminal Address

6
5

Sync

Command Word

Data Word

Status Word

Figure 1. Message Fonnats

Clock

Data

Biphase-L

Figure 2.

604

Ma~hester

II (Biphase-Level) Data Encoding

.... -- ..

~~~~~----,

-~---

-------------

USC Initialization for 1553B Operation
Before the USC can be initialized. it is properly connected
to the remainder of the system and the bus interface
programmed appropriately. While this Application Note
does not cover the' hardware interfacing aspects of the
USC. it is easily interfaced to either multiplexed or nonmultiplexed 8-bit, 16-bit or 32-bit systems. This, document
assumes a multiplexed 16-bit interface.
After hardware reset. the USC watches the bus interface to
determine whether it is multiplexed or non-multiplexed.
A multiplexed bus interface is selected when an Address
Strobe (lAS) is detected. After a hardware reset. the first
write to the USC accesses the Bus Configuration Register
(BCR) to select the bus width. addressing method. and
Wait or Ready function. This is the only time that the BCR

may be accessed. and once the BOR is programmed the
remainder of the USC may be configured.
Both hardware reset and software reset clear all of the
registers in the USC. One byproduct of this is that the
clocks are disconnected from both, the receiver and
transmitter. so the first thing that should be programmed is
the clock sources in the Clock Mode Control Register
(CMCR). The CMCR should be programmed (Figure 3).
with the RxC pin feeding CTR1 and the DPLL. which in turn
feed the transmitter and the receiver. respectively. All
unused functional blocks (CTRO. BRGO and BRG1) are
either disabled or programmed with static clock sources to
minimize power dissipation.

•

L..._ _ _ _ _ _ _

Receive Clock Source
DPLL Output
Transmit Clock Source
CTR10utput
DPLL Clock Source
RxCPin
SRGO Clock Source
CTROOutput
BRG1 CloCk Source
CTROOutput
CTRO Clock Source

Disabled
CTR1 Clock Source
RxCPin

Figure 3. Clock MOde Control Register

605

Once the clocks are connected the remainder of the
hardware interface should be programmed. this includes
the DMA interface, with the /RxREQ, /TxREQ,/RxACK and
/TxACK signals, and the /RxC and /TxC pirls. The lower
byte of the Hardware Configuration Register (HCR) con-

trois the/RxACK and /TxACK signals, while the I/O Control
Register (IOCR) controls /RxREQ, /TxREQ, /RxC, /TxC and
TxD signals. Both ofthese registers contain bits that are not
used in this application; these are programmed with zeros
as shown in Figures 4 and 5.

BRGO Enable
BRGO Single Cycle/ Continuous
RxACK Pin Control
Rx Acknowledge Input
BRG1 Enable
BRG1 Single Cycle/ Continuous
TxACK Pin Control
Tx Acknowledge Input

DPLL Mode
Biphase-Level
DPLL Clock Rate
/8x Clock Mode .
Accept Code Violations
CTR1 Rate Match DPLUCTRO
CTRO Clock Rate
8x Clock Mode

Figure 4. Hardware Configuration 'Register

606

RxC· Pin Control'
Input Pin
L -_ _ _ _ _ _ _

TxC· Pin Control
Tx· Complete Output
TxO Pin Control
Tx Oata Output
RxREO· Pin Control
Tic Request Output
TxREO· Pin Control
Tx Request Output
OCO· Pin Control
DCO·lnput
CTS· Pin Control
CTS·lnput

Figure 5. 110 Conlrol Register

Figure 5 also showsthat the upper byte ofthe HCR controls.
the DPLL. In this example the DPLL and CTR1 will both
operate in 8X mode, requiring an 8.000MHz clock to be
supplied to the jRxC pin. This gives the required 1.000
MHz 1553B data rate. The DPLL is configured to operate
in Biphase-Level mode, with the Accept Code Violations
option enabled because of the code violations inherent in
the 1553B sync patterns. Design considerations for the
DPLL are discussed in a later section.
Once the clocks are configured, the receiver and transmitter
may be programmed, but not enabled. First, the Receive
Mode Register (RMR) and Transmit Mode Register (TMR)

should be written as shown in Figures 6 and 7, respectively. These registers control data encoding, parity, and
character length. Note that a character length of 8 bits is
selected; this will be extended to 16 bits by a control bit in
the Channel Mode Register (CMR) - Figure 8. Tile CMR is
where the receiver and transmitter modes are actually
selected. Note that the 15538 sync polarity for transmit' is
controlled by bit 12 of the CMR (the CV Polarity bit). The
state of this bit is FIFO'ed with the data by the transmitter
and may be automatically loaded with the data as part of
the transmit status block. This is explained later when the
transmitter operation is covered in more detail.

007

11 11 10 I 0 101
-r--

10 I 0 10 10 11 10 10 10 1~ 10 1

Rx Enable
Disable Immediately
Rx CI1ar length
8 Bits
Rx Parity Enable
Rx Parity Sense
Even
Reserved
Rx CRC Enable
Rx CRC Preset Value
Rx CRC Polynomial
CRC-CCITI
Rx Data Decoding
Biphase-Level

Figure 6. Receive Mode Register

Tx Enable
Disable Immediately
Tx Char length
8 Bits
Tx Parity Enable

Tx Parity Sense
Even
Tx CRC On EOF/EOM

Tx CRC Enable
Tx CRC Preset Value
Tx CRC Polynomial
CRC-CCITI
Tx Data Encoding
Biphase-Level

Figure 7. Transmit Mode Register

608

111011101010111110101011101011111

'
IL-________

L.- - - -

Receiver Mode
Async with CV
Rx Extended Word

L-_________
L-___________
L-____________.

Unused
Unused
Unused

L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Transmitter Mode
Async with CV

L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

CV Polarity
Tx Extended Word

' - - - - - - - - - - - - - - - - - - - - - - - - - Tx Stop Bits
No Stop Bits

Figure 8. Channel Mode Register

101010101010101010101010111111101

TCOR Read Count rrc
Rx Overrun IE
Parity Error IE
Status on Words
Rx CV IEOT IEOF IE
Rx Break IAbort IE
Rx Idle IE
,Existed Hunt IE
Rx FIFO Control and Status
(Fill /Interrupt IDMA Level)

Figure 9. Receive Interrupt Control Register

609

At this pOintthe interrupt and DMA details are programmed.
Data transfer via DMA is assumed in this document, but
some interrupts are still enabled for error conditions. In the
receiver, Parity Error and Overrun Error status interrupts
are enabled to collect receive errors on a word-by-word
basis. In the transmitter, no status interrupts are enabled
and the Wait For Send Command option is not enabled:
This means that the DMA controls the data flow, as the USC
is always requesting data to fill the transmit FIFO.
15

Alternatively, with Wait For Send Command enableq, the
CPU controls the data flow since the USC only requests
data after this command is issued and until a word marked
as EOF is written tothe FIFO. The Transmit Interrupt Control
Register selects thes~ options (Figure 10). The transmitter
automatically idles with continuous ones, but because of
the Biphase-Level data encoding it is preferred to have the
transmitter idle with a marking line. This is controlled by bits
in the Transmit Command/Status Register (Figure 11):

101010101010101010101010101010101

TC1 fl Re,ad Count rrc
Tx Underrun IE
Wait for Sent Command
Tx CRC Sent IE
Tx EOF IEOT Sent IE
Tx Abort Sent IE
Tx Idle Sent IE
Tx Preamble Sent IE
Tx FIFO Control and Status
(Fillllnterrupt IDMA Level)

Figure 10. Transmit Interrupt Control Register
15

101010101011111110101010101010101

TX Buffer Empty (RO)
Tx Underrun
All Sent (RO)
TxCRC Sent
Tx EOF IEeT Sent
Tx Abort Sent
Tx Idle Sent
Tx Preamble Sent
Tx Idle Line Condition
Mark
Reserved
Transmit Command (WO)
Null Command

Figure 11. Transmit Command/Stlltus Register

610

The only remaining task is to write the Interrupt Vector
Register with the interrupt vector and enable the interrupts,
the receiver and the transmitter. Interrupts are enabled in
the Interrupt Control Register (ICR) shown in Figure 12.
Note that both the individual Interrupt Enable (IE) and the
Master Interrupt Enable (MIE) bits must be set. In this
example the Vector Includes Status (VIS) option will not be

enabled because only receive status interrupts are enabled. The receiver is enabled by setting bit1 in the RMR
and the transmitter is enabled by setting bit 1 in the TMR.
The lOCO and ICTS pins may be used as enables for the
receiver and transmitter respectively, by setting bit 0 in the
RMR orTMR.

15
0
111010101010101011111110101010101
-.--

Device Status IE
VOStatus IE
Transmit Data IE
Transmit t>tatus IE
Receive Data IE
Receive Status IE
IE Command (WO)
SeliE
Reserved
VIS Level

All
VIS

NV
DLC
MIE

Figure 12. Interrupt Control Register

611

The USC provides for both byte and bit shuffling within the
receiver and transmitter to allow easy interface to any
processor bus. The four options are shown in Table 1,

These options are changed by commands in the CCAR as
shown in Figure 13. Note that the default (reset) case is
straight and LSB firsi.

Table 1. CPU Bus to Transmit and Receive Bit Ordering
Last Sent/Received
(15538 bit 19)

First Sent/Received
(15538 bit 4)

lSB First Straight

ADS

MSB First Straight

AD15 AD14 AD13 AD12 ADll AD10 AD9

lSB First Swapped

ADO

ADl

AD2

AD3

AD4

AD5

MSB First Swapped

AD7

AD6

AD5

AD4

AD3

AD2

AD9

AD10 AD11 AD12 AD13 AD14 AD15 ADO

ADl

AD2 AD3

AD4

AD5

AD6 AlP

AD2

ADl ADO

ADS

AD7

AD6

AD5 AD4

AD3

AD6

AD7

ADS

AD9

ADl0 AD11

AD12 AD13 AD14 AD15

ADl

ADO

AD15 AD14 AD13 AD12 AD11 AD10 AD9 ADS

1110111xlxlololololololololololol
--

Upper!Lower Byte Select (WO)
Address 0 (WO)
Address 1 (WO)
Address 2 (WO)
Address 3 (WO)
Address 4 (WO)
ByteiWord Access (WO)

DMA Continue (WO)
Mode Control
Nllrmal opration
Channel Reset

• Select Upon Reset

Channel Command (WO)
Select Serial Data LSB First"
Select Serial Data MSB First
Select Straight Memory Data"
Select Swapped Memory Data

Figure 13. Channel Command/Addres,S Register

612

Transmitter: Detailed Operation
The polarity of the transmitted sync signal is controlled by
bit 12 in the CMR. The state of this bit is FIFO'ed along with
the data so the full depth of the transmit FIFO is available
for buffering. Note that this bit need not be written with
every word transmitted; the 'current value is FIFO'ed with
the data written to the FIFO. The sync polarity may be
written by the CPU, either with or without the DMA transfer
of data, or the USC may be configured so that the DMA
transfers this information to the USC with the data. With this
method, the DMA can either transfer a word at a time or a
block with the same sync polarity at a time. The method
takes advantage of the send character counter and the
transmit status block features of the USC.
The send character counter keeps track otbytes written to
the transmit FIFO by counting down from a programmed
value. This works even when a 16-bit bus is employed. The
byte written to the FIFO with a count of zero is marked in the
FIFO as the "End-Of-Frame". While this has no meaning in
a 1553B protocol, it does tell the logic in the USC to fetch
another send status block before asking for any more data.
In fact, the DMA request is deactivated until this "last byte"
is extracted from the FIFO by the transmitter. This is
important because it directly influences bus activity and
the availability of the transmit FIFO.
If the sync polarity bit is written (in the traQsmit status block)
with every word, the transmit FIFO is effectively not available. Thus, the preferred method of operation is to use one
transmit status block for sequential words of the same type
(command or data) To do this, a two word transmit status
block must be selected in the CCR with the send data
organized in memory. The first word of the transmit status
block contains the sync polarity, and as a byproduct of the
design, controls the number of stop bits to be sent. The
second word is the byte count of the words to be sent.

Further, the transmitter normally idles, sending continuous
ones which are encoded. This application has programmed
an idle line condition of marking ones. In addition, the rrxc
pin is programmed to provide the Transmit Complete
signal output. Transmit Complete will be active (High) for
those bit times where the transmitter is sending the idle line
condition. This allows external logic to create a doubleended signal for transformer drive from the single-ended
transmit data output.

Receiver: Detailed Operation
The polarity of the received sync pattern is reported in bit
8 of the Receive Command/Status register (RCSR). A zero
in this bit indicates a data sync, while a one in this bit
indicates a command/status sync. The state of this bit is
FIFO'ed along with the receive data so the full depth of the
receive FIFO is available for buffering. The sync polarity is
read by the CPU, either with or without DMA transfer of
data, or the USC is'configured so the DMA transfers this
information to memory with the data. With this,method, the
DMA transfers a word (plus status) at a time. Note that this
is necessary to meet the response time restrictions of
1553B. Only a single-word receive status block should be
used because the second word is meaningless in this
word-oriented protocol.
The second byte of each received word is marked as EndOf-Frame in the receive FIFO. As in the transmitter case,
this designatipn has no meaning in the 1553B protocol but
tells the logiC in the USC to transfer a receive status block
to memory. The received data will be organized in memory.
Note that because each word is marked in the FIFO as
End-Of-Frame, the status for the received word may be
read from the·RCSR after the data is read from the FIFO.
Thus, when transferring data under CPU control, the data
may be read first followed by a read of the RCSR to
determine command/status/data as well as parity error
information.
..

Transmit Data Memory Organization
Receive Data Memory Organization
1. Transmit Status Block First Word (Sync Polarity).
2. Transmit Status Block Second Word (Number of bytes
to be sent)
3. First Word for Transmission.
4. Second Word for Transmission

•••

Note: it is probably best to send status word replies (when
acting as an RT) under CPU control because they are so
short.

1.
2.
3.
4.

First Word Received
First Receive Status Block (Sync Polarity).
Second Word Received.
Second Receive Status Block (Sync Polarity).

••
•

Timing reqlJirements for the receiver are shown in Figure
14, for both start-up and end of a word.

613

Start-up

Command
IStatus

Data

rx::xx:x

\
/

DC)()()(

Clock

Bit Times

Termination

Data

)()(J()()("'"-_________________

Clock

Bit Times

FIFO Write
Figure 14. Receiver Clocking Requirements

DPLL: Detailed Operation
The Digital Phase Locked Loop (DPLL) in the USC is used
to generate a clock for the receiver. As mentioned before,
the DPLL must be programmed in Biphase-Level mode,
accepting code violations. In this mode, the DPLL generates
a clock which is properly phased to sample the receive
data. Also, it persists in time long enough to transfer
received data to memory (Figure 17).
The one case that is not handled well by the DPLL is startup after an idle line. The DPLL assumes that the first edge
that it sees when it is in search mode (waiting to sync up)
is a valid clock edge. In Biphase-Level the val id clock edge

614

is at the center of the bit cell, but notice that the first edge
in the sync pattern is a code violation at the bit-cell
boundary. Thus, if the DPLL uses this first edge to sync up,
the DPLL output is 90 degr.ees out of phase.
The solution is to create, externally, a fake mid-bit change
which precedes the sync pattern into the Receiver/DPLL
combination. The required waveforms are shown in
Figure 15. The desired waveform is created with a simple
state machine running off the 8X clock and using the
differential receive Signals from the 1553B transceiver.

Command
/Status

---11

v- _ _ _ _ _

\----~
DPll Clock
Out _ __

Data

v+ _ _ _ _ _

---11

Data

\~_----JI

Clock

Figure 15. DPLL Idle Line Stan·up Requirements

CONCLUSION
The USC provides a cost-effective, single-chip solution for
1553B communication by providing Manchester encoding
and decoding, sync pattern recognition and generation,
and parity generation and checking. The DMA transfer of
both data and status is supported, along with block data

transfers and 32-byte FIFOs. The flexible bus interface and
both bit and byte shuffling allow connectiOn to any type of
system bus. Connection to a Z16COO' is shown In
Figure 16.

615

AD15-0

AD15-0
IRESET

IRESET

lAS

IDS

RlIW

USC

IRESET

lAS

RlIW

IRD

VDD

IWR

VDD

IPITACK

VDD

ISITACK
lElA

VDD

Interrupt
Ack.
Decode

Z8000 CPU
ST4-0,

IEOA
IEIB
IEOB

N.C.

IINTA

IINTB
AlIB
DIIC

VDD

IWAITIIRDY

IWAIT

Chip
Select
Decode

ICS

}

DMA

* CMOS Z8000 family CPU
Figure 16. USC to Z8000 CPU Connection (Example)

616

ApPLICATION NOTE

~ZiIm

DATACOMMUNICATIONS

IUSC/MUSC
TIME SLOT ASSIGNER
Use the IUSC/MUSC for ISDN and Fractional T1 in High Speed,
Time-Multiplexed Datacommunications
INTRODUCTION
In applications such as ISDN and Fractional T1, a high
speed link is time-multiplexed among a set of independent
voice and data streams. The IUSC can send and/or receive such a data slream with the aid of its Transmit and
Receive Time Slot Assigner logic (TTSA and, RTSA).
To use the IUSC in such an application, external logic must
determine the start point of (or at least a consistent point in)
each cycle during the overall data stream. Then, the
external logic signals the IUSC when this point occurs,
using a pulse on the PORT6/FSYNC pin that is low for one
period of RxCLK and/or TxCLK. This pulse is used by both
the Receive and Transmit Time Slot Assigners. Note that if
both the Receiver and Transmitter are operating simulta-

neously in such an application, the IUSC assumes that
they are both operating in (different parts of) the same
overall data stream. This means that RxCLK and TxCLK is
selected from the same source.
Figure 1 shows how the Time Slot Assigners determine
when to start receiving and/or transmitting in each cycle.
After sens(ng the /FSYNC pulse, the RTSA waits for a
number of RxCLK cycles (bit times) that are determined by
the values programmed into the RTSASlot and RTSAOff
fields in the Receive Interrupt Control Register (RICR). The
number of RxCLK cycles (bits) waited is eight times the
value in RTSASlot, plus the value, in RTSAOff.

RxCLK or
r-\.
r-\.
TxCLKJ
~
~

r-----~Sr----------------~SSr---------------

IFSYNC
(PORTS)

1st Bit Received

or Xmitted

xTSAOIf>O
xTSASlot=O

1+~(,-xT..SA,-O_II)...:...;;.B;..;itS_~1( 1st Bit Received

xTSAOIf= 0
xTSASlol>0

1+_ _ _ _ _
B...;.*(x_T_SA_S_Io-'t):..B_its
_ _ _ _ _-IIA !~~~~eived

xTSAOIf> 0
xTSASlol>0

1+_(:..XT_SA_OII)-"-B_its_-e_J-------B-*(:..XT-S-A-S-lot..;.)_Bi_ts_ _ _ _ _-I!K. 1st Bit Received

RxDor

orXmitted

TxD

orXmitted

Figure 1. Stan of Received or Transmitted Data in a TSA Application

617

After blocking RxCLKs to the Receiver for this number of
bits (or right after the FSYNC pulse if both fields contain
zero), the RTSA allows RxCLK to reach the Receiver forthe
number of consecutive bytes/octets/slots programmed
into the RTSACntfieid in RICA. That is, it allows 8(RTSACnt)
RxCLKs to reach the Receiver (Figure 2). (If the RTSACnt
field is zero, the whole RTSA feature is disabled). Now, the

RTSA again blocks RxCLKs to the Receiver until after the
next pulse on /FSYNC.
Note: All Signals with a preceding front slash, "/", are active
Low, e.g.: BIIW (WORD is active Low); IBIW (BYTE is
active Low, only); INIIS (NORMAL and SYSTEM are both
.'
active Low).

RxCLKor
TxClK

IFSYNC
(Port 6)

Sf
8* (xTSACnt) Bits

..
RxOor

TxD

XmltGate
(Port 4) or
Received
Gate (Port 3)

1sl BR Received

or Xmltted

!
n

last Bit Received
or Xmltted

Figure 2. Length of Received or Transmitted Data in a TSA Application

The net result of this clock gating is that the IUSC can
receive up to 15 consecutive bytes/octets out of each
cycle on the serial link, starting at any point within the (first)
128 octets of each cycle. It also allows for possible delays
in sensing and signalling the frame sync.
In ISDN circles it is common parlance to refer to the 128
octets in each frame as "siots" whi'ch are numbered from
through 127. Given this definition of slot number, if the
frame sync detection logic allows /FSYNC to be sampled
low in the bit time before RxD is sampled for the first bit of
the first slot, then RTSAOff is programmed with zero;
RTSASlot is programmed with the slot number of the first
octetthatis received. Otherwise, call the FSync delay, one,
if /FSYNC is sampled low in the same bit time that the first
bit of the first slot is available on RxD; two, if /FSYNC is low
in the bit time after the first bit appears on RxD; and so on
up through the maximum value of seven, i.e., if /FSYNC is
low six bit times after the first bit of the first slot appears on
RxD. In cases where the first slot cannot be received,
program the RTSAOff field with eight minus the FSync
delay; program RTSASlot with the slot number of the first
octet that is received, minus one.

Figure 1 applies equally to the transmit side. The TTSA
blocks TxCLKs to the Transmitter for a number of TxCLK
cycles that are determined from the TTSASlot and TTSAOff
fields in the Transmit Interrupt Control Register (TICR).

618

After blocking TxCLKs for 8(TTSASlot) + (TTSAOff) bits,
the TTSA allows TxCLK to reach the Transmitter for the
number of consecutive bytes/octets/slots programmed
into the TTSACnt field in the Transmit Interrupt Control
Register (TICR). That is, it allows 8(TTSACnt) TxCLKs to
reach the Transmitter (Figure 2 - on the receive side, if tile
TTSACnt field contains zero, the whole TTSA feature is
disabled). The TTSA again blocks TxCLKs to the Transmitter
until after the next pulse on /FSYNC.
Thus, symmetrically with the receive side, the IUSC transmits up to 15 consecutive bytes/octets/slots in each cycle
on the serial link. This occurs while starting at any point
within the (first) 128 octets of each cycle, plus allowing for
possible delays in sensing and signalling the frame sync.
Since the IUSC maintains output drive on TxD throughout
each cycle 'on the serial link, an external driver with an
enable/disable input is needed to transmit in this kind of
time-multiplexed environment. The IUSC provides the required Transmit Gate signal on the PORT 4 pin. This signal
goes low while the TTSA is enabling the Transmitter in each
frame. There is also a similar facility whereby the RTSA's
low-active Receive Gate signal can be output on the PORT
3 pin, but the application of this signal is less obvious. As
already noted in the 'section on the PORT pins, these
options are enabled by programming the P4 MODE and/
or P3 MODE fields of the Port Control Register (PCR9-8
and/or PCR7 -6, respectively) as 01.

PROGRAMMING THE TIME SLOT ASSIGNERS
There is an intentional vagueness in the preceding description of the Time Slot Assigner control fields as being
"in" the Receive and Transmit Interrupt Control Registers
(RICR and TICR). These two registers are somewhat more
complex than other IUSC registers- this section describes
how to access the TSA fields.

The other options are discussed in subsequent chapters;
for our purposes it is sufficient to note that TSA data is read
and written as x1CR15-8, if the 0100 command has been
written to xSCR15-12 more recently than 0101, 0110, or
0111. The IUSC resets to read the Current FIFO level in
both the RICR and TICR.

The less-significant byte (bits 7-0) of both the RICR and
TlCR contains fixed data, but any of five different intemal
registers can be selected as the more-significant byte of
each register (Figure 3). At the first level of data structure,
the contents of RICR 15-8 are selected by means of four Of
the commands that are written to the RCMD field of the
Receive Command/Status Register (RCSR15-12); the
contents of TICR 15-8 are selected by four of the commands
written to the TCMD field of the Transmit Command/Status
Register (TCSR 15-12). The encoding pf both sets of
commands is the same:

Figure 3 also shows how a second level of data structuring
determines the meaning of TSA data. For write operations,
the destination of the data is determined by the LSBit of the
MSByte of data written:

xCMD

Contents of x1CR15-8

0100
0101
0110
0111

xTSA data
Current xFIFO Level
xFIFO Level for Interrupt
xFIFO Level for DMA Request '

xlCR8value

Destination of x1CR15-9

x1CR15-9 -> xTSASlot
xICR15-13-> xTSAOff
x1CR12-9 -> xTSACnt

1
1

Reading TSA data from RICR or TICR always yields the
xTSASlot value, with the LSBit of the MSByte equal to zero.

(where "x" stands for either "R" or "T").

619

RICRor TICR

...... ~~

~~I--------~I~------~
-----------

If the last value in the range 01 00-0111 written to the
command field of RCSR or TCSR was:

Then the following data can be accessed in the
~S byte of RICR or TICR:

0100

Read or write TSA data

I
I

0101

0110

I
I
I

0111

Read the # of empty entries in the TxFIFO or •
the # of received bytes in the RxFIFO
Read the # of empty TxFIFO or • the # of received
characters in the RxFIFO to request an interrupt

Read the # of empty TxFIFO or • the # of received
characters in the RxFIFO to request a DMA Transfer

I
I
I
If the lSB of the TSA
data written is:

\
\
\
\
\

\
\
\
\
\
\
\

Then the r~t of the TSA data written
is as follows:
RTSASlot OR TTSAlot

RTSAOffor
TTSAOff

RTSACntor
TTSACnt

I-

Reading TSA data always yields this byte -

Figure 3. Structure of RICR and TICR

SUMMARY
To set up xTSA, first write the 0100 command to the xCMD
field of the xSCR; write the xTSASlot value to the MSByte of
xlCR with the LSBit of the byte equal to 0; write the xTSAOff

620

and xTSACnt values to the MSByte of xlCR with the LSBit
of the byte equal to 1.
.

~ZiIill

ApPLICATION NOTE

ISCC INTERFACE TO. ,
THE 68000 AND 8086
INTRODucnON
The ISCC uses its flexible bus to interface with a variety of
microprocessors and microcontrollers; included are the
68000 and B086.
The Z16C35 ISCC is a Superintegration form of the
85C30/BOC30 Serial Communications Controller (SCC).
Super integration includes four DMA channels, one for
each receiver and transmitter and a flexible Bus Interface
Unit (BIU). The BIU supports a wide variety of buses

including the bus types of the 680xO and the B086 families
of microprocessors.
This Application Note presents the details of BIU operation
for both slave peripheral and DMA modes, Included are
application examples of interconnecting an ISCC to a
68000 and a 8086 (These examples are currently
under test).

ISCC BUS INTERFACE UNIT (BIU)
The following subsections describe and illustrate the functions and parameters of the ISCC Bus Interface Unit

Overview
The ISCC contains a flexible bus interface that is directly
compatible with a variety of microprocessors and
microcontrollers. The bus interface unit adds to the chip by
allowing ease of connection to several standard bus
configurations; among others are the 68000 and the B086
family microprocessors. This compatibility is achieved by
initializing the ISCC after a reset to the desired bus configuration.
The device also configures to work with a variefy of other
8- or 16-bit bus systems and'is used with address/data
multiplexed or non-multiplexed buses, In addition, the
wait/ready handshake, the interrupt acknowledge, and the
bus high byte/low byte selection are all programmable.
Separate read/write, data strobe, write, reiid, and address
strobe signals are available for direct system interface with
a minimum of external logic.

Modes Description

registers with their own unique hardware addresses. By
contrast, in the non-multiplexed mode, all registers access
through an internal pointer which first loads with the register address, Loading of the pointer is done as a data
write, In either case, there are some external addressing
\ signals.
Chip Enable (CE) allows external selection through the
decode of upper order address bits like accessirig separate
chips. A separate input (not part of the AD15-O bus
and DMA
connection) selects between the internal
sections of the chip, This input is AO/SCC/DMA and provides direct transfers to the appropriate chip subsystem;
either multiplexed or non-multiplexed bus mode.

sec

A second separate input (not part of the AD15-0 bus
connection) provides for a selection between the internal
SCC; both channels A and B (Table A-l). This input is
A1/NB and provides direct transfers to the appropriate
SCC channel when AO/SCC/DMA selects the SCC; either
multiplexed or non-multiplexed bus mode, Note that these
two Signals, A 1/NB and AO/SCC/DMA, are inputs when the
ISCC is a slave peripheral; they become outputs when the
ISCC is a bus master during DMA operations,

There are basically two bus modes of operation: multiplexed
and non-multiplexed. In the multiplexed bus mode, the
ISCC internal registers are directly accessible as separate

621

Table A-1. Accessing the ISCC Registers
AO/SCC/DMA

A1/NB

1
1

ACCESS
SCC Channel A
SCC Channel B
DMA

The following discussions assume knowledge of the SCC
Serial Communications Controller opertions and refer to
internal register designations. For a detailed explanation,
refer to the SCC Technical Manual.

Non-multiplexed Bus Operation
When the ISCC initializes for non-multiplexed operation,
Write Register 0 (WRO) takes on the form of WRO in the
Z8530, Write Register Bit Functions (Figure A-1). Register
addressing for the SCC section is (except for WRO and
RRO) accomplished as follows. Programming the write
registers requires two write operations. Reading the read
registers requires both a write and a read operation.

The first write is to WRO which contains three bits that point
to the selected register (note the point high command).
The second write is the actual control word forthe selected
register. If the second operation is a read, the selected
register is accesSed. When ih the non-multiplexed mode,
all registers in the SCC section of the ISeC, including the
data registers, access this way.
The pOinter register automatically clears after the second
read or write operation so WRO (or RRO) addresses again,
There is no direct access to the data registers, They are
addressed through the pointer (this is in contrast to the
Z8530 which allows direct addressing of the data registers
through the C/D pin).

622

When the ISCC starts for non-multiplexed operation, register addressing for the DMA section is (except for CSAR)
accomplished as follows. It is completely independent of
the SCC section register addressing. Programming the
write registers requires two write operations and reading
the read registers requires both a write and a read operation.
The first write is to the Command Status Address Register
(CSAR) which contains five bits that point to the selected
register (CSAR bits 4 - 0). The second write is the actual
control word for the selected register. lithe second operation
is a read, the selected register is accessed. The pOinter
bits automatically clear after the second read or write
operation so CSAR addresses again. When in the
non-multiplexed mode, all registers in the DMA section of
the ISCC are accessed,

Multiplexed Bus Operation
When the ISCC initializes for multiplexed bus operation, all .
registers in the SCC section are directly addressable with
the register address occupying AD5 through AD1 or AD4
through ADO (Shift Left/Shift Right modes).
The Shift Left/Shift Right modes for the address decoding
of the internal registers (multiplexed bus) are separately
programmable for the SCC and DMA sections For the
SCC section, the programming and operation is the same
as the SCC; programming occurs through Write Register
(WRO), bits 1 and 0 , and Write Register Bit Functions
(Figure A-2). The programming of the Shift Left/Shift Right
modes for the OMA section occurs in the BCR, bit O. In this
case, the shift function is similar to the SCC section; with
Left Shift, the internal register addresses decode from bits
AD5 through AD1. In Right Shift, the internal register
addresses decode from bits AD4 through ADO,

During multiplexed bus mode selection, Write Register 0
(WRO) becomes WRO in the Z8030, Write Register Bit
Functions (Figure A-2).

WrI1e Register 0 (non-multiplexed bus mode)

Write Register 0 (multiplexed bus mode)'

1071061051041031021011001

TTT
'0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
0

0
0
1
O. 1 .
1 0
1. 0
1 1
1 1

o
o
*

0
1
o
1

0
1
0
1
0
1
0
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
0
1
1

RegisterS
Register 9

10
12
13
14
15

Null Code
Point High
ResetExtIStatus Interrupts
Send Abo rt(SOLC)
Enable Int on Nex1 Rx Character
ResetTx Int Pending
Error Reset
Reset Highest IUS

Null Code
Reset Rx CRC Checker
Reset Tx CRC Generator
Reset Tx UnderrunlEOM Latch

Null Code
Null Code
Saleet Shift Left Mode } *
Select Shift Right Mode

0
1
0
1

o
o
1
1

0
1
0
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Null Code
Null Code
Reset ExVStatus Interrupts
Send Abort
Enable Int on Next Rx Character
Reset Tx Int Pen ding
t:rror Reset
Reset Highest IUs

Null Code
Reset Rx CRC Checker
Reset Tx CRC Generator
Reset Tx Underrun/EOM Latch

* B Channel Only

Figure A-2. Write Register 0 Bit Functions
(Multiplexed Bus Mode)

With Point High Command

Figure A-1. ""rite Register 0 Bit Functions
(Non-Multiplexed Bus Mode)

BUS DATA TRANSFERS
All data transfers to and from the Isee are done in bytes
regardless of whether data occupies the lower or upper
byte of the 16 bit bus. Bus transfers as a slave peripheral
are done differently from bus transfers when the Isee is
the bus master during DMA transactions. The Isee is
fundamentally an 8-bit peripheral butsupports 16-bitbuses
in the DMA mode. Slave peripheral and DMA transactions
appear In the next sections.

Data Bus Transfers as a Slave Peripheral
When accessed as a peripheral device (when the Isee is
not a bus master performing DMA transfers), only 8 bits
transfer. During Isee register read, the byte data present
on the lower 8 bits of the bus is replicated on the upper 8
bits of the bus. Data is accepted by the Isee only on the
lower 8 bits of the bus.

ISCC DMA Bus Transfers
During DMA transfers, when the Isee is bus master, only
byte data transfers occur. However, data transfers to or
from the Isee on the upper 8 bits of the bus or on the lower
8 bits of the bus. Moreover, odd or even byte transfers
activate on the lower or upper 8 bits of the bus. This is
programmable and explained next.
During DMA transfers.to memory from the ISee, only byte
data transfers occur. Data appears on the lower 8 bits and
replicates on the upper 8 bits of the bus. Thus, the data is
written to an odd or even byte of the system memory by
address decoding and strobe generation.
During DMA transfers to the Isee from memory, byte data
only transfers. Normally, data appears only on the lower 8

623

bits of the bus. However. the byte swapping feature
determines which byte of the bus data is accepted. The
byte swapping feature activates by prbgramming the Byte
Swap Enable bit to a 1 in the BCR. The odd/even byte
transfer selection occurs by programming the Byte Swap
Select bit in the BCR. If Byte Swap Select is a 1. then even
address bytes (transfers where the DMA address has
AO = 0) are accepted on the lower 8 bits of the bus. Odd
address bytes (transfers where the DMA address has
AO = 1) are accepted on the upper 8 bits of the bus. If Byte
Swap Select is a O. then even address bytes (transfers
where the DMA address has AO = 0) are accepted on the
upper 8 bits of the bus. Odd address bytes (transfers
where the DMA address has AO =1) are accepted on the
lower 8 bits of the bus.

Bus Interface Handshaking
The ISCC supports data transfers by either a data strobe
(OS) combined with a read/write (RIW) status line. or
!separate read (RD) and write (WR) strobes. These transactions activate via chip enable (CE).
ISCC programming. generates interrupts upon the occurrence of certain internal events. The ISCC internally prioritizes its own interrupts. therefore. the ISCC presents one
interrupt to the processor even though lower priority internal
interrupts may be pending. Interrupts are individually
enabled or disabled. Refer to the sections on the
SCC core.
Interrupt Acknowledge (INTACK) is an input to the ISCC
showing that an interrupt acknowledge cycle is progressing.
INTACK is programmed to accept status acknowledge.
a single pulse acknowledge. or a double pulse acknowledge. This programming activates in the BCR. The double
pulse acknowledge is compatible with 8X86 family microprocessors and the status acknowledge is compatible
with 68000 family microprocessors.

During an interrupt acknowledge cycle. the SCC and DMA
interrupt priority daisy chain internally resolves. Thus. the
highest priority internal interrupt is presented to the CPU.

The ISCC can return an iflterrupt vector that encodes with
the type of interrupt pending enabled during this. acknowledge cycle. The ISCC may request an interrupt but
not return an interrupt vector [note that the no vector bit(s)
in the SCC section (WR9 bit 1) and in the DMA section (ICR
bit 5) individually control whether or nOt an interrupt vector
returns by these cores]. The interrupt vector can program
to include a status field showing the internallSCC source
of the interrupt. During the interrupt acknowledge cycle.
the ISCC returns the interrupt vector when INTACK. RD or
DSgo active and lEI is high (if the ISCC is not programmed
for the no vector option).
During the programmed pulsed acknowledge type (whether
Single or double). INTACK is the strobe for the interrupt
vector. Thus when INTACK goes active. the ISCC drives
the bus and presents the interrupt vector to the CPU. When
. the status acknowledge type programs. the ISCC dnves
the bus with the interrupt vector when RD or OS are active.
WAITRDY programs to function either as a WAIT signal or
a READY signal using the BCR write. When programmed
as a wait signal. it supports the READY function of 8X86
family microprocessors. When programmed as a ready
signal. it supports the DTACK function of 680xO family
microprocessors.
The WAIT/ROY Signal functions as an output when the
ISCC is not a bus master. In this case. this signal serves to
indicate when the data is available during a read cycle:
when the device is ready to receive data during a write
cycle. and when a valid vector is available during an
interrupt acknowledge cycle.
When the ISCC is the bus master (DMA section has taken
control of the bus). the WAIT/RDY signal functions as a
WAIT or RDYinpul. Slow memories and peripheral devices
use WAIT to extend the data strobe (IDS) during bus
transfers. Similarly. memories and peripheral devices use
ROY to indicate valid output or that it is ready to latch
input data.

CONFIGURING THE BUS
The bus configuration programming is done in two separate steps (actually it is one operat.ion). to enable the write
to the Bus Configuration Register (BCR) . The first operation
that accesses the ISCC after a device reset must be a write
to the BCR since this is the only time that the BCR is
accessible. Before and during the write. various external
signals are sampled to program bus configuration
parameters. During this write. the A0/SCCIIDMA pin must
be Low.

624

Address strobe programs multiplexed/non-multiplexed
selection. In a non-multiplexed bus environment. address
strobe (as an input) is not used but tied high through a
suitable pull-up resistor. Thus. no address strobe is present
before the BCR write. Then. when write to the BCR takes
place. the non-multiplexed mode is programmed because
there is no address strobe before this first write to the
device, Note that address strobe becomes an output
during DMA operations so it is not tied directly to Vcc.

During the write operation to the BCR. the A 1/A/B input is
sampled to select the function of the WAIT/ROY pin
(Table A-2). When the BCR Write is to the SCC Channel A
(A 1/AIIB High during the BCR write). the WAIT/ROY signal
functions as a wait. When the BCR Write is to Channel B
.(A 1/AIIB Low during the BCR write). the WAIT/ROY signal
functions as a ready.
Table A-2. Signals Sampled During the BCR Write
A1/NIB

WAIT/ROY Function
WAIT (8086 ROY compatible)
READY (68000 DTACK compatible)

. This programming affects the function of the WAIT/ROY
signal both as an input. when the ISCC is bus master
during DMA operations. and as an output when the ISCC
is a bus slave.

The Status Acknowledge remains active throughout the
interrupt cycle and is directly compatible with the 680xO
family interrupt handshaking. The Status Acknowledge
signal latches with the rising edge of AS for multiplexed
bus operation. It latches by the falling edge of the strobe
(RD or OS) for non-multiplexed bus operation. The Pulsed
Acknowledges are timed to be active during a specified
period in the interrupt cycle. The Double Pulsed Acknowledge is directly compatible with the 8x86 family interrupt
handshaking. Refer to the timing diagrams in the ISCC
Product Specification for details on the Acknowledge
signal operation.
Reserve bits 3. 4. and 5 of the BCR program as zeros. Bits
6 and 7 of the BCR control the byte swap feature (Table A4). Byte swap is applicable only in DMA transfers when the
ISCC is the bus master and only affects ISCC data acceptance (transfers from memory to the ISCC).
Table A-4. Byte Swap Control

With this programming. the ISCC is immediately configured
to function successfully on this first and subsequent bus
transactions. The remaining bus configuration options are
programmed by the value written to the BCA.
Bit 0 of the BCR controls the Shift Left/Shift Right address
decoding modes for the DMA section. In this case. the shift
function is similar to the SCC section. During Left Shift. the
internal register addresses decode from bits AD5 through
AD1. During Right Shift. the internal register addresses are
decode from bits AD4 through ADO. This function is only
applicable in the rnultiplexed bus mode.

Enable (BCR bit 7)

DMA Data Read by the ISCC

lower 8 bits of bus only
upper or lower 8 bits of bus

Swap Select"

DMA Data read by the ISCC

o
o

1
1

0
1

upper 8 bits of bus
lower 8 bits of bus
lower 8 bits of bus
upper 8 bits of bus

Bits 1 and 2 of the BCR control the interrupt acknowledge
type as shown in the Table A-3.
• SCR bit6

Table A-3. BCR Control of Interrupt Acknowledge
BeR bit 2

o
o
o
1

BCR bit 1 Interrupt Acknowledge

o
1
1
1

Status Acknowledge
Pulsed Acknowledge (single)
Reserved (action not defined)
Double Pulsed Acknowledge

625

APPLICATIONS EXAMPLES
The following application examples explain and illustrate
ttie methods of interfacing the ISCC to a Motorola 68000
and an l'1tel8086.

external bus arbitration circuit. This circuit performs bus
arbitration for multiple bus master requests and generates
bus grant acknowledge (BGACK) which controls certain
bus drive signal sources.

68000 Interface to the Isce
Figure A-3 shows a connection of the ISCC to a 68000
microprocessor. The 68000 data bus connects directly, or
through bus transceivers, to the ISCC address/data bus.
R/W and RESET also directly connect In this example, the
ISCC is on the lower half of the bus; OS of the ISCC
connects to LOS of the 68000. The processor address
lines decode to produce a chip enable for the ISCC. In
addition, processor addresses A 1 and A2 connect to
AO/SCC/OMA and A 1/A/B, respectively, through a tri-state
driver.

The driver is normally ON (enabled) but tums OFF by
BGACK to grant the bus to ISCC for OMA transfers. This is
done since the AO/SCC/OMA and A1/A/B pins become
outputs during OMA transfers and should not drive the
system address bus. RO and WR tie high through independent pull-ups. They are not 'used in this application but
become active outputs during OMA transfers and are not
tied directly to Vcc.
Although not shown in Table A-5, the AO/SCC/OMA and
A1/A/B pins may be decoded during OMA transfers to
identify the active OMA channel.

When the ISCC becomes the bus master, a 32-bit address
generation by the OMA section is output on the ISCC
address/data bus. The lower 16 bits of tllis address store
in an external latch by AS (Address Strobe). Also, the
upper 16 bits of this address store in an external latch by
UAS (Upper Address Strobe). With BGACK low (active)
and with the processor address lines tri-stated, the latch
outputs drive the system address bus.
AS is pulled high by an external resistor. This pull-up
insures an inactive AS (at a logic high level) when the ISCC
is not driving this signal. Therefore, on power up or after a
RESET, AS is inactive and programs the non-multiplexed
bus mode on BCR write.
In this application, the outputs of the address latches are
connected to the address bus so that A 1 through A23 of
the ISCC drives the system address bus (the ISCC provides
a total of 32 address lines). AD from the address latch is
diverted to logic which generates UOS and LOS bus
signals from the ISCC data strobe (OS). UOS is generated
when AO is low and LOS is generated when AD is high. The
lower and upper data strobes are applied to the system
bus through tri-state drivers which are enabled only when
BGACK is active. Bus direction is now controlled by the
ISCC R/W signal which is now an output.

Table A-5. DMA AlB Channel Decode

A1/NB

AO/SCC/DMA

1
1
0

1
0
1

DMAChannel
Receiver Channel A
Transmitter Channel A
Receiver Channel B
Transmitter Channel B

External logic can use this information to abort a OMA in
progress.

For initialization, the BCR write (the first write to the ISCC
after RESET) is done with A2 = 0 (A 1/A/B ISCC input at
logic low). This selects the ready option of the WAIT/ROY
signal to conform to the 68000 bus style. The AS signal
programming of the non-multiplexed bus has already.
been discussed. The BCR is written with COh to enable
byte swapping. It also selects the sense of byte swapping
with respect to AO appropriate to this bus style and selects
the STATUS type of interrupt acknowledge.

8086 Interface with the Isee
For normal slave device bus interaction, a OTACK is
generated. WAIT/ROY is programed 'for ready operation
and INTACK programs for the status type. WAIT/ROY
generates a OTACK for normal data transfers and interrupt
responses. Additional logic may be required when other
interrupt sources are present.
Ouring OMA transfers, the ISCC becomes bus master.
Becoming bus master is done through the BUSREQ output
and BUSACK input signals of the ISCC. They connect to an

626

Figure A-4 shows the connection of the ISCC to an 8086
microprocessor and companion clock state generator. In
this application, the ISCC connects for multiplexed address
access to the internallSCC registers. A015 through ADO
of the 8086 connect directly, or through a bus transceiver,
to the corresponding AD15 through ADO address/data
ISCC bus pins. RD and WR are directly compatible and tie
together to form the read and write bus signals.

IRESET
IUDS

IUDS

ILDS

~
JI

IDS

r-<
V~

-"M-

~AA

IBGACK
IDTACK

IRESET

·VVY

IWR
WAITIRDY

015-0

AD15-ADO
IBGACK

6
IOE

A23-16
A23-1

0 f-Latch

68000
.

IRD

---

IOE
Latch

A15-1

.--

Q-

'v~

{
~ ~

A61-"'1

Chip
Select
Decode

ICS

16C35
IUAS

V
A19-A16

HOLD
*/RDIIGTor
HLDA

Q
latch
IDE

Q
System
Address
Bus Upper
Order Bits

latch
IDE

Vcc

R/W

Vcc

-JVVv-

IDS
IBUSREQ

BUS Arbitration and Timing
Synchronization

IINTR

IBUSACK

IINTA
RDY

RDYTiming
Synchronizer

* maximum mode

Figure A-4. Isee Interface to an Intel 8086 Microprocessor

628

liNT
IINTACK
WAIT/RDY

When the Isee becomes a bus master during DMA
operations, RD and WR of the 8086 are tri-stated which
allows the corresponding Isee signals to control the bus
transactions. The sense of RESET reverses, so .the Isee
RESET signal inverts from the reset applied to the 8086
from the clock state generator.
RD/WR and DS of the Isee are inactive in this application
and tie high. They tie high through independent pull-ups
since these signals become active when the Isee is bus
master during DMA transactions.
Assuming other devices in the system, the Isee chip
enable input (eE) activates from a decode of the address.
In this example, the Isec internally decodes addresses A 1
through A5 and uses A6 and A7, externally. Thus, the
address decode circuitry decodes address lines AO and
A8 and above. The decode of AO for chip enable places
the Isee as an 8-bit peripheral on the lower byte ofthe bus.
AO and the upper level address lines (including A6 and A7)
demultiplex from the 8086 address/data bus through a
latch strobed by ALE.
The demultiplexed addresses A6 and A7 connect to
AO/See/DMA and A1/NB, respectively, of the Isee to
control seleCtion of the DMA and see channels A and B.
This connects through the tri-state drivers. They enable
when the 8086 is the bus master and disable when the
Isee is bus master. This prevents the Isee from improperly
driving the system address bus since AO/See/DMA and
A1/NB become active outputs when the Isee is the bus
master.
The address map for the Isee appears in Table A-6 for this
application.

Table A-5.
AO A1-A5
1
0
0
0

x
0
1

x
x
1
0

Isec Address Map
Registers Addressed
lsee not enabled
DMA Registers per A 1 - A5
see eore ehannel A Registers
see eore ehannel B Registers

Since AO specifies the lower byte of the bus and includes
the chip enable decode, the, internal lsee register addresses decode without AO. Thus, Table 6 implies that the
Left Shift address decode selection is made for both the
see and DMA sections of the Isee. The left shift selection
is the default selection after reset. Left/Righi Shift selection
programming is discussed later.
The ALE signal of the 8086 applies to AS of the Isee
through an inverting tri-state buffer. The buffer disables
when the Isee be~omes a bus master during DMA

transactions. This prevents conflicts since ALE remains
active even when the 8086 is in the HOLD mode during
DMA transfers. Now, the Isee AS is an active output. .The
address strobe for the demultiplexing latch of addresses
AO through A 15 connects on the Isee side of the ALE tristate buffer. This allows the latch to serve two functions; to
hold either the 8086 or the lsee address when it is bus
master.
After reset. ALE is active and the tri-state buffer enabled.
This supplies address strobes to the Isee. The presence
of one of these address strobes, before writing to the BeR,
programs the Isee to the multiplexed bus mode of operation. The Isec chip enable (eE) can be inactive and
still recognize an address strobe (AS) before the BeR write
(Figure ~ shows open latches when the input strobe is low).
When the Isee is bus master during DMA transactions,
BHE generates from AO. This is done from the output of the
lower order address latch through an inverting tri-state
driver. This driver enables only when the Isee is the bus
master. Whole word transfers are not done by the Isee
DMA, thus,: BHE generated for the Isee is always the
inverse of AD.
The upper bus system address lines demultiplex from the
8086 and the Isee in separate latches. Like the 68000
example, high order address lines from the Isee latch via
UAS (upper address strobe). The separate latches drive
the same upper order address lines. A 16 from the Isee
connects to the corresponding A 16 address bus line as
derived from the 8086. The output of the two latches
alternately enable depending upon bus mastership.
The diagram shows INT fron the Isee connected to the
8086 INTR input via an inverter since these signals are of
opposite sense. In actual practice, the Isee interrupt
request is first processed by an interrupt priority circuit.
INTA (Interrupt Acknowledge) of the 8086connects directly
to the INTAeK input of the Isee. eonforming to the 8086
style of interrupt acknowledge, the Isee is programed to
the Double Pulse Interrupt Acknowledge type. When this
selection occurs, the Isee responds to two interrupt
acknowledge pulses. The first pulse is recognized but no
action follows. The second pulse causes the Isee to go
active on the data bus and return the interrupt vector to the
epu. This action also takes place with the Single Pulse
Interrupt Acknowledge type selection, except that the bus
.goes active with the first and only interrupt acknowledge
pulse.
To start, the BeR write (first write to the Isee after RESET)
is done with A7 = 1 (A 1/AIB Isee input at logic high) This
selects the wait option of the WAIT/RDY signal to conform
to the 8086 bus style. The AS signal programming of the
multiplexed bus was covered earlier. The BeR is written

629

" .",.- , ..................."""""-•• 1""""' .. "..........""""'.-........ ~ ""'w,, '~:""""r ......... ,,'"'_"._ ...,. ,";'i,1" • ,'"

"tI ''i'.n,,'~

with 86h to enable byte swapping; select the sense of the
byte swapping with respect to AO (appropriate to this bus
style), and select the Double Pulse type of interrupt
acknowledge.
When the ISCC begins DMA transfers, it communicates
requests for the bus through BUSREO and BUSACK. The
8086 rfolc~ives and grants bus requests through HOLD and
HLDA'inthe minimum mode and through RO/GT in the
maximum mode. Depending upon the system requirements, there could be more than one potential bus master.
Therefore, there is a requirement for a bus arbitration
circuit.

630

The minimum mode connection is relatively straigh\Wrward. The maximum mode configuration requires,'~a
translation of the ISCC BUSREO and BUSACK sign~s
into/from the 8086 RO/GT timed pulse style of handshake.
Refer to the information on the 8086 for detailed application information.
.The ISCC WAIT/RDY output is compatible with the 8086
clock generator. ROY input except that one edge of the
signal must· be synchronous with the 8086 clock. The
synchronization occurs through external circuitry. Refer to
the information on' the 8086 for detailed application
information.

~-----.--

... - .. -

ApPLICATION NOTE

,THE Z180 INTERFACED
WITH THE sec AT 10 MHz
INTRODUCTION
Build a simple system to prove and test the Z100 MPU
interfacing the sec at 10 MHz.
This Application Note describes the design of a system
using a ZOO 100 MPU (Microprocessor Unit) and a Z85C30
SCC (Serial Communications Controller), both running at
10 MHz. Hereinafter, all references are to the Z180
and SCC.
The system board is a vehicle for demonstration and
evaluation of the 10 MHz interface and includes the following parts:
•

Z801OO10VSC Z100 MPU 10 MHz, PLCC package

•

Z85C3010VSC C-MOS Z8530 SCC Serial
Communication Controller, 10 MHz, PLCC package

•

27C256 EP-ROM

•

55257 Static RAM

The Z100 is a ZOO compatible High Integration device with
various peripherals on board. Using this device as an
alternative to the ZOO CPU, reduces the number of parts
and board space. However, processing speed and reliability increase.
The serial communication devices on the Z100 are: two
asynchronous channels and one clocked serial channel.
This means handling synchronous serial communications

protocols requires an off-chip ':multi-protocol serial communication controller." The SCC is the ideal device to meet
the requirements.
Zilog's SCC is the multi-protocol (@ 10 MHz) universal
serial communication controller which covers most serial
communication applications including Monosync, Bisync
and SDLC at 2.5M bits/sec speeds. Further, the wide
acceptance of this device by the market ensures it is an
"industrial standard" serial communication controller. Also,
the Z180 has special numbers for system clock frequencies of 6.144 - and 9.216 MHz which generate exact baud
rates for on-chip asynchronous serial communication
channels. This is due to the sec's on-chip, 16-bit wide
baud rate generator for asynchronous ASCI communications.
The following 10 MHz interface explanation defines how
the interrupt structure works. Also included is a discussion
of the hardware and software considerations involved in
running the system's communication board. This Application Note assumes the reader has a strong working
knowledge of the Z100 and sec; this is not a tutorial for
each device.
Note: All Signals with a preceding front slash, "I", are active
Low, e.g.: BIIW (WORD is active Low); IBIW (BYTE is
active Low, only); INIIS (NORMAL and SYSTEM are both
active Low).

631

INTERFACES
The following subsections explain the interfaces
between the:
•

Z180 and Memory

•

Z180and I/O

•

Z180and SCC

•

Using EPLD for glue wherever'possible

•

Expandability

The design method for EPLD is using TTLs (74HCT) and
then translating them into EPLD logic. This design uses
TTLs and EPLDs. With these goals in mind, the discussion
begins with the Z180-to-memory interface.
.

Basic goals of this system design are:

Z180 to Memory Interface

•

System clock up to 10 MHz

•

UsingtheZ8018010VSC(Z18010MHzPLCCpackage)
to take advantage of 1M byte addressing space and
compactness (DIP versions' addressing range is half;
512K bytes)

The memory access cycle timing of the Z180 is similar to
the Z80 CPU memory access cycle timing. The three
classifications are:

•

Using Z85C3010VSC (CMOS SCC 10MHz PLCC
package)

•

Minimum parts count

•

Worst case design

•

Op-code fetch cycle (Figure 1)
\

Memory read cycle (Figure 2)

•

Memory write cycle (Figure 3)

Table 1 shows the Z180's basic timing elements for the opcode's fetch/memory read/write cycle.

Address

IMREQ

IRD

Dam

----r-------------------~

IMI

Figure 1. Z180 Op-code Fetch Cycle Timing (One Wait State)

632

.~~~-

.. -------.

Table 1. Z8018010 Timing Parameters for Op-code Fetch Cycle (Worst Case: Z180 10 MHz)

Symbol

Parameter

Min
100
40
40

1
2
3
4

tcyc
tCHW
tCLW
tcf

Clock Cycle Period
Clock Cycle High Width
Clock Cycle Low Width
Clock Fall Time

tAD
tMED1
tRDD1
tAH

Clock High to Address Valid
Clock Low to IMREO Low
Clock Low to IRD Low
Address Hold Time

12
15
16
22

tMED2
tDRS
tDRH
tWRD1

Clock Low to 1M REO High
Data to Clock Setup
Data Read Hold Time
Clock High to /WR Low

8
9

23
24
25
26
27

tWDD
IWDS
tWRD2
IWRP
IWDH

Max

Units

ns
ns
ns
ns

50
50
10
50
25
0
50

Clock Low 10 Wrile Data Delay
Write Dala Selup 10 /WR Low
Clock Low lo/WR High
/WR Pulse Widlh
/WR High 10 Dala Hold Time

15
50
110
10

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Nole:
Parameter numbers In this table are In the Z180 technical manual.

III

Address

IMREQ

IRD

Data

----------------------------~

Figure 2. Z180 Memory Read Cycle Timing (One Walt State)

633

EP-ROM Interface
During an Op-coEle fetch cycle, data sampling of the bus
is on the rising'PHI clock edgeofT3 and on the falling edge
of T3 during a memory read cycle. Op-code fetch cycle
data sample timing is half a clock cycle earlier. Table 2
shows how a memory read cycles' timing requirements are
easier than an op-code fetch cycle by half a PHI cycle time.

II the timing requirements for an Op-code fetch cycle meet
specifications, the design satisfies the timing requirements
. '
for a memory read cycle.
Table 2 has some equations for an op-code fetch, memory
read/Write cycle.

Table 2. Parameter Equations (10 MHz) Op-code Fetch/Memory Read/Write Cycle
Value

Units

2( 1+w)tcyc-tAD-tDRS
2( 1+w)tcyc+ tCHW+tcf-tAD-tDRS
(1+w)tcyc+tCLW-tMED1-tDRS

105+ 1OOw min
155+100wmin
55+100wmin

ns
ns
ns

(2+w)tcyc-tMED 1-tDRS
(1 +w)tcyc+tCLW-tRRD1-tDRS
(2+w)tcyc-tRRD1-tDRS
tWRP+w*tcyc

105+100wmin
55+100wmin
105+ 100w min
110+ 100w min

ns
ns
ns
ns

Parameters

Z180 Equation

Address Valid to Data Valid (Op-code Fetch)
Address Valid to Data Valid (Memory Read
IMREQ Active to Data Valid (Op-code Fetch)
IMREQ Active to Data Valid (Memory Read)
fRO Active to Data Valid (Op-code Fetch)
IRD Active to Data Valid (Memory Read)
Memory Write Cycle /WR Pulse Width
Nole:
• w is the number of wait states.

The propagation delay for the decoded add ress and gates
in the previous calculation is zero. Hence, on the real
design, subtracting another 20-30 ns to pay for propagation delays, is possible. The 27C256 provides the EP-ROM
for this board. Typical timing parameters for the 27C256
are in Table 3.
'
Table 3. Ep·ROM (27C256) key Timing Parameters
(Values May Vary 'Depending On, Mfg.)

Parameter
Addr Access Time
fE to Data Valid
fOE to Data Valid

Access Time
170ns 200ns 250ns
Max
Max
Max
170
170
75

200
200
75

250
250
100

Nole:
Table 3 shows "Access lime" as applying IE to data valid. "fOE active to
data valid" is shortet than "address access time". Hence, the interface
logic for the EP-ROM is: Realize a 170ns or faster EPROM access time by
adding one watt state (using the on-chip wail stale generator of the Zl80).
A 200ns requirement uses two wait'states for memory access.

SRAM Interface
Table 4 has timing parameters for 256K bit SRAM for
this design.

634

Table 4. 256K SRAM Key Timing parameters
(Values May Vary Depending On Mfg.)

Parameter

85nS
Min

Access Time
100nS 150nS
Min
Min

Read Cycle:

IE to Data Valid
IG to Data Valid

85
45

100
40

150

Write Cycle:
Write Cycle Time
Addr Valid to End of Write
Chip Select to End of Write
Data Select to End of Write
Write PulSe Width
Addr Setup Time

85
75
75
46
60
0

100
80

150
100
100
60

80
40

,,0

SRAM Read Cycle. An SRAM read cycle shares the
same considerations as an EPROM interface.
Like EPROM, SRAMs' "aqcess time" applies IG to data
valid, and "IE active to data valid" is shorter than "access
time." This design allows the use of a 150ns access time
SRAM by adding one wait state (using the on-chip wait
state generator of the Z180). The circuit is common to the
EPROM memory read cycle.

No wait states are necessary if there is a 85ns; or faster,
access time by using SRAMs. Since the Z180 has on-chip
MMU with 85ns or faster SRAM just copy the contents of
EPROM (application program starts at logical address
OOOOh) into SRAM after poweron. Set up the MMU to SRAM
area to override the EPROM area and stop inserting wait
states. With this scheme, you can get the highest performance with moderate cost.

SRAM Write Cyde. During a Z 180 memory write cycle, the
Z180 write data is stable before the falling edge of {WR
(Z180 parameter #24; 15ns min at 10 MHz). It is stable
throughoutthe write cycle (Zt80 parameter #27; 10nS min
at 10 MHz). Further, the address is fixed before the falling
edge of {WR. As long as the {WR pulse width meets the
SRAM's spec, there is no problem (reference Table 2).

Address

IMREQ

IWR

Dam --------+-----~

Figure 3. Z180 Memory Write Cycle Timing (One Wait State)

Memory Interface Logic
The memory devices (EPROM and SRAM) for this design
are 256K bit (32K byte). There are two possible memory
interface designs:
Connect Address Decode output to IE input. Put the signal
generated by IRD and IMREO ANDed together to iOE of
EPROM and SRAM. Put the signal generated by {WR and
IMREO ANDed together to the IWE pin of SRAM
(Figure 4a).
Connect the signal Address ANDed together with inactive
IIORO to the IE input. Connect IRD to 10E of EPROM and
SRAM, and /WR to {WE pin of SRAM (Figure 4b).
Using the second method, there could be a narrow glitch
on the signal to the IE-pin during 1/0 cycles and the
Interrupt acknowledge cycle. During 1/0 cycles, IIORO
and IRD or {WR go active at almost the same time. Since
the delay times of these signals are similar there is no

"overlapping time" between ICE generated by the address
(II ORO inactive), and {WR or IRD active. During the Interrupt Acknowledge cycle,lWR and IRD signals are inactive.
To keep the design simple and flexible, use the second
method (Figure 4b). To expand memory, decode the
address A15 NANDed with IUSRRAMIIUSRROM and
IIORO to produce ICSRAM or ICSROM. These are chip
select inputs to chips 55257 or 27C256, respectively.
This either disables or enables on-board ROM or RAM
depending upon selection control.
The circuit on Figure 4b gives the physical memory address
as shown on Figure 5.
If there are no Z80 peripherals and 1M 1 is enabled (M 1E bit
in Z180 OMCR register set to 1), active wait states occur
only during op-code fetch cycles (Figure 6). If the M1 E bit
is cleared to 0, IM1E is active only during the Interrupt

635

. Acknowledge cycle and Return from Interrupt cycle. This
case depends on the propagation delay of the address
deco - - - - - + l H

ICSRAM To 55257 ICE Pin

A~ >-~----r+~-'

IUSRROM

>--+-=---~~-,

ICSROM To 27C256ICE Pin

. Figure 4B. Memory Interface Logic

636

FFFFFH

S-RAMlmage
F8000H

---------

1M1

EP-ROM Image
FOOOOH

'74

---------

'74
CK

CK
PR

Image can be
killed trhrough
/uSRRAMand
/uSRROM

--------S-RAM Image
28000H

---------

~---I.

1M1 /WAIT

IEP-ROM Image
20000H

18000H

--------S-RAMlmage
---------

Figure 6. Wait State Generator Logic
(Extends Op-code Fetch Cycle Only; Not Working in Z
Mode of Operation)

EP-ROM Image
10000H

256KSRAM
08000H

EP-ROM
27C256

OOOOOH

Figure 5. Physical Memory Address Map

Z180 TO I/O INTERFACE
The Z180 I/O read/write cycle is similar to the Z80 CPU if
you clear the /IOC bit in the OMCR register to 0 (Figures
T1

7 and 8). Table 5 shows the Z180 key parameters for an
I/O cycle.
T3

Address

/lORO

IRD

Dam

--------------------------------~
Figure 7. Z180 1/0 Read Cycle Timing (/IOC

= 0)
637

Address

1I0RO

IWR

Dam --------~--_G

Figure S. ZlS0 1/0 Write Cycle Timing

Table 5. ZSOl80l0 Timing Parameters for 1/0 Cycle (Worst Case)
No

Symbol

Parameter

Min

1
2·
3
4

tcyc
tCHW
tCLW
tcl

Clock Cycle Period
Clock Cycle High Width
Clock Cycle Low Width
Clock Fall Time

100
40
40

6
9
11
13

tAD
tRDD1
tAH
tRDD2

Clock High to,AddreSs Valid
Clock High to /RD Low 10C=0
Address Hold Time
Clock Low to /RD High

15
16
21
22

tDRS
tDRH
tWDZ
tWRD1

Data to Cloc-k Setup
Data Read Hold Time
Clock High to Data Float Delay
Clock High to twR Low

23
24
25
26a

tWDD
tWOS
tWRD2
tWRP

Clock Low to Write Data Delay
Write Data Setup to twR Low
Clock Low to twR High
twR Pulse Width (I/O Write)

27
28
29

tWDH
tlOD1
IIOD2

twR High to Data Hold Time
Clock High to /IORO Low 10C=0
Clock Low to/IORO High

Nole:
Parameter numbers in this mble are the numbers in the Zl80 technical manual.

638

Max

Units

ns
ns
ns
ns

70
55
50

ns
ns
ns
ns

60
50

ns
ns
ns
ns

10
25
0

60
15
50
210
10
55
50

ns
ns
ns
ns
ns
ns
ns

If you are familiar with the Z80 CPU design, the same
interfacing logic applies to the Z180and 1/0 interface (see
Figure 9a). This circuit generates IIORD (Read) or lORD
(Write) for peripherals from inputs IIORO, !RD, and /WA.
The address decodes the Chip Select signal. Note, if you
peripherals, the decoder logic decodes only
have
from addresses (does not have IIORO). The Z180 signals
IIORO, IRD, and /WR are active at about the same time
(Param #9, 22, 28). However, most of the Z80 peripherals
require ICE to IRD or /WR setup time.

zao

Since the Z180 occupies 64 bytes 011/0 addressing space
for system control and on-chip peripherals, there are no
overlapping 1/0 addresses for off-chip peripherals. In this
design, leave the area as default or assign on-chip registers
at 1/0 address Ooooh to 003Fh.
Figure 9 shows a simple address decoder (the required
interface signals, other than address decode outputs, are
discussed later).

HCT138
A6

1Y9

50 -

A17

IG2A

1Y6

58 -

IG2B

1Y5

54-

1Y4

50 -

1Y3

40-

1Y2

48-

1Y1

44-

IYO

40 -

IIORO
IRD

twR

Chip Select Signals
for Peripherals

IIORD To Each

Peripherals' IRD

IIOWR To Each
F'eripherals' twR

Figure9A. 1/0 Interface Logic (Example)

4.7KO

IUSRRAM
A7

>:===~=:rl
>

AS >------~HCT10

lessee
(To sec Interface Logic)

Figure 9B. 1/0 Address Decoder for this Board

When expanding this board to enable other peripherals,
the decoded address A6/A7 is NANDed with USRIO to
produce the Chip Enable (CSSCC) output signal (HC10).
The SCC registers are assigned from address xxCOh to
xxC3h; with image, they occupy xxCOh to xxFFh. To add
wait states during 1/0 transactions, use the Z180 on-chip
wait state generator instead of external hardware logic.

If there is a Z80 PIO on board in a Z-mode of operation (that
is, clear 1M 1E in OMCR register to zero) and after enabling
a Z80 PIO interrupt. zero is written to MHE in the OMCR
register. Without a zero, there is no interrupt from the Z80
PIO. The Z80 PIO requires /M1 to activate an interrupt
circuit after enabling interrupt by software.

639

Z180 TO SCC INTERFACE
The following subsections discuss the various parameters
between the Z180/SCC interface: CPU hardware, I/O opinterrupt daisyeration (read/write), SCC interrupts,
chain operation, SCC interrupt daisy-chain 'operation, I/O
cycles.

Interrupt Control
IINTACK. Interrupt Acknowledge (input, active low). This
signal shows an Interrupt Acknowledge cycle which
combines with /RO to gate the interrupt vector onto the
data bus.

CPU Hardware Interfacing

liNT. Interrupt request (output, open-drain, active low).

The hardware interface has three basic groups of signals:
Oata bus, system control, and interrupt control. For more
detailed signal information, refer to Zilog's Technical
Manuals, and Product Specifications for each device.

lEI. Interrupt Enable In (input, active high).

zao

lEO. Interrupt Enable Out (Output, active high).
These lines control the interrupt daisy chain for the peripheral interrupt response.

Data Bus Signals
07-00. Data bus (Bidirectional, 3-state). This bus transfers
data between the Z180 and SCC.

see I/O Operation
The SCC generates internal control Signals from /RO or
/WR. Sihce PCLK has no required phase relationship to
/RO or /WR, the circuitry generating these signals provides
time for meta stable conditions to disappear.

System Control Signals
AlIB, CIID. Registerselectsignals(lnput). These lines select
the registers.

ICE. Chip enable (Input, active low). ICE selects the proper
peripheral for programming. ICE is gated with /IORQ or
/MREQ to prevent false chip selects during other machine
cycles.

The SCC starts the different operating modes by programming the internal registers. Accessing these internal
registers occurs during I/O Read and Write cycles, described below.

IRO+. Read (input, active low). /RO activates the chip-read
circuitry and gates data from the chip onto the data bus.

Read Cycle Timing
Figure 10 illustrates the SCC Read cycle timing. All register
addresses and /INTACK are stable throughout the cycle.
The timing specification of SCC requires that the ICE signal
(and address) be stable when /RO is active.

IWR+. Write (Input, active low). /WR strobes data from the
data bus into the peripheral.
Chip reset occurs when fRO and /WR are active simultaneously.

Address

IINTACK

ICE

IRO

07-00

\
I

\
(

Figure 10. SCC Read Cycle Timing

640

Address Valid

OalaValid

)

Write Cycle Timing
Figure 11 illustrates the SCC Write cycle timing, All register
addresses and liNT ACK are stable throughout the cycle.
The timing specification of the SCC requires that the ICE

Address

IINTACK

signal (and address)be'stable when IRO is active. Data is
available to the SCC before the falling edge of /WR and
remains active until /WR goes inactive ..

Address Valid

ICE

\
\

L
/

twR

07-00

OataValid

)

Figure 11. SCC Write Cycle Timing

SCC Interrupt Operation
Understanding SCC interrupt operations requires a basic
knowledge of the Interrupt Pending (IP) and Interrupt
Under Service (IUS) bits in relation to the daisy chain. The
Zl80 and SCC design allow no additional interrupt requests during an Interrupt Acknowledge cycle, This permits the interrupt daisy chain to settle, ensuring proper
response of the interrupt device,
The IP bit sets in the SCC for CPU intervention requirements (that is, buffer empty, character available, error
detection, or status changes). The interrupt acknowledge
cycle does not reset the IP bit. The IP bit clears by a
software command to the SCC, or when the action that
generated the interrupt ends, for example, reading a
receive character for receive interrupt. Others are, writing
data to the transmitter data register, issuing Reset TX
interrupt pending command tor Tx buffer empty interrupt,
etc.), After servicing the interrupt, other interrupts
can occur,
. The IUS bit means the CPU is servicing an interrupt The
IUS bit sets during an Interrupt Acknowledge cycle if the IP
bit sets and the lEI line is High. If the IEllfne is low, the IUS
bit is not set This keeps the device from placing its vector
onto the data bus.

The IUS bit clears in the Z80 peripherals by decoding the
RETI instruction, A software command also clears the IUS
bit in the Z80 peripherals. Only software commands clear
the IUS bit in the SCC,

Z80 Interrupt Daisy-Chain Operation
In the Z80 peripherals, both IP and IUS bits control the lEO
line and the lower portion of the daisy chain. When a
peripheral's IP bit sets, the lEO line goes low This is true
regardless of the state of the lEI line, Additionally, if the
peripheral's IUS bit clears and its lEI line is High, the liNT
line goes low,
The Z80 peripherals sample for both IM1 and IIORO active
(and IRO inactive) to identify an Interrupt Acknowledge
cycle, When IM1 goes active and IRO is inactive, the
peripheral detects an Interrupt Acknowledge cycle and
allows its interrupt daisy chain to settle. When the IIORO
line goes active with IM1 active, the highest priority interrupting peripheral places its interrupt vector onto the data
bus. The IUS bit also sets to show that the peripheral is now
under service, As long as the IUS bit sets, the lEO line
remains low, This inhibits any lower priority devices from
requesting an interrupt.

641

When the Z180 CPU executes the RETI instruction, the
peripherals check the data bus and the highest priority
device under service resets its IUS bit.

interrupt status. Table u shows the truth .table for the sce
interrupt daisy chain control signals during certain cycles.
Table 7 shows the interrupt state diagram for the see.

SCC Interrupt Daisy-Chain Operation

Table 6.

In the SCC, the IUS bit normally controls the state ofthe lEO
line. The IP bit affects the daisy chain only during an
Interrupt Acknowledge cycle. Since the IP bit is normally
not part of the SCC .interrupt daisy chain, there is no need
to decode the RETI instruction To allow for control over the
daisy chain, the SCC has a Disable Lower Chain (OLC)
software command that pulls lEO low. This selectively
deactivates parts of the daisy chain regardless of the

Table 7.

sec Daisy Chain Signal Truth Table

During Idle State
lEI
IP
IUS
0
1
1
1

X
X
X
0

X
0
1
0

During INTACK Cycle
lEO lEI
IP
IUS lEO
0
1

0
1

0
1
1

X
1

X
X

0
0
0

sec Interrupt Status Diagram

Interrupt Condition

Wait For CPU
IINTACK Cycle

Return To Main Program

The sec uses /INTACK (Interrupt Acknowledge) for recognition of an interrupt acknowledge cycle. This pin, used
.with /RO; allows the SCC to gate its interrupt vector onto the
data bus. An active/RO signal during an interrupt acknowledge cycle performs two functions. First, it allows the

highest priority device requesting an interrupt to place its
vector on the data bus. Secondly, it sets the IUS bit in the
highest priority device to show the device is now under
service.

INPUT/OUTPUT CYCLES
Although the sec is a universal design. certain timing
parameters differ from the Z180 timing. The following
subsections discuss the I/O interface for the Z180 MPU
and SCC.

642

Z180 MPU to SCC Interface
Table 8 shows key parameters of the 10 MHz sec for I/O
read/write cycles.

Table 8. 10 MHz SCC Timing Parameters for 1/0 ReadlWrlte Cycle (Worst Case)
No

Symbol.

6
7
8
9

TsA(WR)
ThA(WR)
TsA(RO)
ThA(RO)

16
17
19
20

TsCEI(WR)
ThCE(WR)
TsCEI(RO)
ThCE(RO)

fCE
fCE
fCE
fCE

22
25
27
28
29
30

TwROI
TdROf(OR)
TdA(OR)
TwWRI
TsOW(WR)
TdWR(W)

fRO Low Width
fRO Low to Read Data Valid
Address to Read Data Valid
/WR Low Width
Write Data to fWR Low Setup
Write Data to fWR High Hold

Parameter

. Address
Address
Address
Address

to fWR Low Setup
to fWR High Hold
to fRO Low Setup
to fRO High Hold

Low to fWR Low Setup
to /WR High Hold
Low to fRO Low Setup
to fRO High Hold

Min

Max

Units

50
0
50
0

ns
ns
ns
ns

0
0
0
0

ns
ns
ns
ns

125
120
180
125
10
0

ns
ns
ns
ns
ns
ns

SCC I/O Read/Write Cycle
Assume that the Z100 MPU's flOC bit in the OMCR (Operation Mode Control Register) clears to 0 (this condition is
a ZOO compatible timing mode for flORO and fRO). The
following are several design points to consider (also see
Table 3).
.
I/O Read Cycle
Parameters 8 and 9 mean that Address is stable 50ns
before the falling edge of fRO and until fRO goes inactive.

Parameters 19 and 20 mean that fCE is stable at the falling
edge of fRO and until fRO goes inactive.
Parameter 22 means the fRO pulse width is wider
than 125ns.

1/0 Write Cycle
Parameters 6 and 7 mean that Address is stable 50ns
before the falling edge of /WR and is stable until /WR goes
inactive.
Parameters 16 and 17 mean that fCE is stable at the falli1l9
edge of /WR and is stable until /W goes inactive.
Parameter 28 means /WR pulse width is wider than 125ns.
Parameters 28 and 29 mean that Write data is on the data
bus 10ns before the falling edge of /WR It is stable until the
riSing edge of /WA.
Tables 9 and 10 show the worst case SCC parameters
calculating Z180 parameters at 10 MHz.

Parameters 25 and 27 mean that Read data is available on
the data bus 120ns later than the falling edge of fRO and
180ns from a stable Address.

643

Table 9. Parameter Equations Worst Case (Without Delay Signals· No Walt State)

see
. Parameters

Z180

Equation

Value'

Units

TsA(RD)
TdA(DR)
TdRDf(DR)

tcyc-tAD+ tROD 1
3tcyc+tCHW+tcf-tAD-tDRS
2tcyc+tCHW+tcf-tRDD1-tDRS

30 min
245 min
160 min

ns
ns
ns

TwRDI
'TsA(WR)
TsDW(WR)
TwWRI

2tcyc+tCHW+tcf-tDRS+tRDD2
tcyc-tAD+ tWRD 1
tWOS
tWAP

185 min
30 min
15 min
210 min

ns
ns
ns
ns

Value

Units

241 min

184 min

Table 10. Parameter Equations
Z180

see

Parameters

Equation

tORS

Address
3tcyc+tCHW-tAD-TdA(DR)
RD
2tcyc+tCHW-tRDD1-TdRD(DR)

I/O Read Cycle
These tables show that a delay of the falling edge of IRD
satisfies the SCC TsA(RD) timing requirement of 50ns min.
The Z180 calculated value is 30ns min for the worst case.
Also, Z180 timing specification tAH (Address Hold time) is
10ns min. The SCC timing parameters ThA(RD) (Address
to IRD High Hold} and ThCE(RD) {ICE to /AD High HOld}
are minimum at Ons. The rising edge of /AD is early to
guarantee these parameters when considering address
decoders and gate propagation delays.

I/O Write Cycle
Delay the falling edge of twR to satisfy the SCC TsA(/WR)
timing requirement of 50ns min. The Z180 calculates 30ns

644

min worst case. Further, the Z 180 timing specifications tAH
(A,ddress Hold time) and tWDH (twR high to data hold
time) arE! bOth 10ns min. The SCC· timing parameters
ThA(WR) {Address to twR High Hold}', ThCE(WR) {ICE to
twR High Hold} and TdWR(W) {Write data to twR High
hold} are a minimum of 0 ns. The riSing edge of twR is early
to guarantee these parameter requirements,
This Circuit 'depicts logic for the 1/0 interface and the
Interrupt Acknowledge Interface for 10 MHz clock of
operation. Fjgure 12 is the I/O readlwrite timing chart
(discussions of timing considerations on the Interrupt
Acknowledge cycle and the circuit using EPLD
occur later).

To
85C30
ICE

ICSSCC
!WR
HCT74
HCT164
0

/cLR

HCT27

HCT04
CK

HCT27

To
85C30
!WR
To
85C30
fRO

HOT04

06
07
IRO

HCT04

'RESET
HCT164

1M REO

1M1

CLR

02
03

To 85C30
IINTACK

To
Z180
!WAIT

05
06
97

4.7K
Intemal
!WAIT

Input

Figure 12. SCC I/O ReadlWrite Cycle Timing

If you are running your system slower than 8 MHz. remove
the HCT7 4, O-Flip/Flop in front of HCT164. Connect the
inverted CSSCC to the HCT164 B input. This is a required
Flip/Flop because the Z180 timing specification on 11001
(Clock High to /IORO Low, 10C=O) is maximum at 55ns.
This is longer than half the PHI clock cycle. Sample it using
the rising edge of clock, otherw(se, HCT164 does not
generate the same signals.
The RESET signal feeds the SCC /RO and twR through
HCT27 and HCT02 to supply the hardware reset signal. To
reduce the gate count, drop these gates and make the
SCC reset by its software command. The SCC software

reset - OCOh to Write Register 9, "Hardware Reset command" has the same effect as hardware reset by
"Hardware. "

Interrupt Acknowledge Cycle Timing
The primary timing differences between the Z180 and SCC
occur In the Interrupt Acknowledge cycle. The SCC timing
parameters that are significant during Interrupt Acknowledge cycles are in Table 11. The Z180 timing parameters
are in Table 12. The reference numbers in Tables 11 and
12 refer to Figure 14.

645

Table 11. 10MHz SCC Timing Parameters for Interrupt Acknowledge Cycle
No

Symbol

Parameter

Min

13
14
15
38

TsIAi(RD)
ThIA(RD)
ThIA(PC)
TwRDA

IINTACK Low to IRD Low Setup
liNTACK High to IRD High Hold
IINTACK to PCLK High Hold
liNTACK Low to IRD Low Delay
(Acknowledge)

130
0
30
125

39
40

TwRDA
TdRDA(DR)

IRD (Acknowledge) Width
IRD Low (Acknowledge) to

125

TsIEI(RDA)

Read Data Valid Delay
lEI to IRD Low (Acknowledge)
Setup Time

ThIEI(RDA)

TdIEI(IEO)

Interrup~

Symbol

Parameter

10
14
15

tM1D1
tM1D2
tORS

Clock High to IM1 Low,
Clock High to IM1 High
Data to Clock Setup

16
28
29
30

tDRH
11001
11002
11003

Data Read Hold Time
Clock LOW to IIORO Low
Clock LOW to IIORO High
1fv11 Low to IIORO Low Delay

Units
ns
ns
ns
ns

120

lEI to IRD High (Acknowledge)
Hold Time
lEI to lEO Delay

Table 12. Z180 Timing Parameters

Max

ns
ns

ns
175

Acknowledge Cycles (Worst Case Z180)
Min

Max

Units

60
60

ns
ns
ns

25
0
50
50
200

ns
ns
ns
ns

Note:
Parameter numbers in this table are the numbers in the Z180 technical manual.

During an Interrupt Acknowledge cycle, the SCC requires
both IINTACK and IRD to be active at certain times. Since
the Z180 does not issue either IINTACK or IRD, external
logic generates these Signals.
The Z180 is in a Wait condition until the vector is valid.
I,f there are other peripherals added to the interrupt priority
daisy chain, more Wait states may be necessary to give it
time to settle. Allow enough time between IINTACK active
and IRD active for the entire daisy chain to settle

646

There is no need of decoding the RETI instruction used by
the Z80 peripherals since the SCC daisy chain does not
use IP, except during Interrupt Acknowledge. The SCC
and other Z8500 peripherals have commands that reset
the individual IUS flag.
External Interface for Interrupt Acknowledge Cycle: The
bottom half of Figure 13 is the interface logic for the
Interrupt Acknowledge cycle.

Twl

I
..ffi

lOOns

rc-

Address

~+---------+--------------+----~-----~----
10 ns min
~70nsmax

,_ !--®

nOAO

ISCCSEl _ + - -_ _ _+--""'_-+-..,nsmj

50nsmax

~=!>-t Ii

JI-~~-----I--I-fl--f.- _

20nsmax _

20 ns max

HC74 10
10nsmax
HCT164/ClA

-n

HCTl64 ClK

IOns max-

~""---I-+------+----H.\

.....--~ll0nsmax ~II.--

_
HCTl64 00

~10nsmax

f.-

-------f-----+---_--+'- I.--

20nsmax

~20nsmax

~ 20 ns max

I
20nsmax'"

lAD (or. twA)

\JI-+-------+---+')

55nsmax

AD> 01
>SCCSEl

f---

c-- 15 ns max

-------------Ir-.-t--h.

f--Data (AD)

....

HCT164 01

ISCCAOI\(AO>
101> SCCSEl)
+ AESET]

f4--10nsmax

......

~ 15nsmax

~ 30n5(>On5)
~200 ns typo (> 125 ns)

-------------1----0(.
120nsmax

55 ns max

- 1I
f4-

15 ns max

15nsmax

_>~ns

scc
X Valid Data }>-----------l1~~:,:,:::~,,",;:::~~~~.1 ~f- >25ns

ISCCWA

~------------------~

Oata(AO) _ _ _ _ _ _ _ _ _ _ _-()

SCC

~ 15nsmin
=
210ns

Figure 13. Z180 to

see Interface Logic (Example)

~Onsmin
4-@>On5

647

The primary chip in this logic is the Shift register (HCT164),
which generates/INTACK, /SCCRD and /WAH. During I/O
and normal memory access cycles, the Shift Register
(HCT164) remains clegred because the /M1 signal is
inactive during the op-code fetch cycle. Since the Shift
Register output is Low, control of /SCCRD and /WAIT is by

other system logic and gated through the NOR gate
(HCT27). During 'I/O and normal memory access cycles,
/SCCRD and /SCCWR are generated frbm the system /RD
and /WR signals, respectively. The generation is by the
logic at the top of Figure .14. .
.

1M1

/lORa

IINTACK

/WAIT

ISCCRD

sec
VECTOR

SCC

-----------------------------------------G
120 ns max J4----Q9):---J4---<..!§>--

Figure 14. SCC Interrupt Acknowledge Cycle Timing

648

Norma"y, an Interrupt Acknowledge cycle appears from
the Z180 during IM1 and IIORO active (which is detected
on the third rising edge of PHI after T1 ). To get an early sign
of an Interrupt Acknowledge cycle, the Shift register decodes an active IM1. This is during the presence of an
inactive IMREO on the rising edge of T2.
During an Interrupt Acknowledge cycle, the IINTACK
signal is generated on the rising edge ofT2. Since it is the
presence of lINTACK and an active SCCRD that gates the
interrupt vector onto the data bus, the logic also generates
ISCCRD at the proper time. The timing parameter of
concern here is TdIAi(RD) [IINTACK to/RD (Acknowledge)

Low delay]. This time delay allows the interrupt daisy chain
to settle so the device requesting the interrupt places its
interrupt vector onto the data bus.
The Shift Register allows enough time delay from the
generation of IINTACK before it generates /SCCRD. During this delay, it places the Z180 into a Wait state until the
valid interrupt vector is placed onto the data bus. If the time
between these two Signals is not enough for daisy chain
settling, more time is added by taking /SCCRD and /WAIT
from a later position on the Shift Register. If there is a
requirement for more wait states, the time is calculated by
PHI cycles.

USING EPLD
Figure 15a and Figure 15b show the logic using either
EPLD or the circuit ofthis system. The EPLD is ALTERA 61 0
which is a 24-Pin EPLD. The method to convert random

gate logic to EPLD is to disassemble MSls' logic into SSI ,
level, and then simplify the logic.

649

WR@3~
lIP

RES@2~IM
lIP

IORQ@21 ~

IIP

SCC@ll ~
IIP

CLK@l'~

~
•

D Q

~0UTr-J~0R2~SCCW@19

~ ~
IN

OUT

D 0

SCCR@20

, ,D

lIP

CLK@13~

RD@4~
IIP

_Q123:-1
XWAIT@5

--lIP

c::: .~- :~
,

~_ OUf

D0R2

R __

IILOG
12/3/88

Sl80-BeC
BUSLOGIC
DPF

El'tD. 1'610

iii

Ml@14

OUT

PIM

IIP

f?=Ul rRJl iRJl

~;S
~
..

CLIt

iCC

Cili

mu!

iiiH'

Figure 15a. EPLD Circuit Implementation

lACK!l8
WAIT@17

Ul
DO
01
D2
D3
D'
D5
D6
D7
4x7

vee . .

DeDO
eTSO
RTSO

NMI
K2

~......ll-,

1
I

49
48
47
46
45

RXAl

53
51
5.

RXS
TXS
CI.«hl»
db

oo1101ooB

?&?r
db

000001ooB+(?&?rAND 7) SHL 3

db
db

011oo100B
?r

else
ifdef
else

endif
end if
endm
.list
end

657

Table 15 lists a program example fortne Z180/SCC DMA
transfer test.

Table 15. Test Program - Z180/SCC DMA Transfer

Test program for 180 DMAlSCC
Test 180's DMA function with SCC
.*
180 dma - dmaO for scc rx data
.*
dma1 for scc tx data
;* async, X1 mode, 1 stop, speed = pclk/4
;*
self loop-back
.*
Connect W/REO to DREOO of 180
.*
DTR/REO to DRE01 of 180
B reg'ister returns status info:
Bit DO set: Tx DMA end
01 set: Rx DMA end
02 set: Data doesn't match

.z800
;Read in Z180 register names and
;macro fI?r Z180 new instructions

*include 180macro.lib
;SCC Registers
scc_ad:
scc_ac:
scc_bd:
scc_bc:

equ
equ
equ
equ

OC3h
OC2h
OC1h
OCOh

;addr of scc
;addr of scc
;addr of scc
;addr of scc

scc_a:

equ

DOh ,

;if test ch. a, set this to Offh
;for ch.b, set this to OOh

equ

1DOOh

;transfer length

org

09000h

;top of user ram area

Id
Id
Id
Id
autO

sp,tx_buff
a,(high z180vect) and Offh
i,a
a,OOh
(iI),a

;initsp
;init i reg

if
scc_cont:
scc_data:

ch
ch
ch
ch

a - data
a - control
b - data
b - control

scc_a
equ
equ

else
scc_cont:
scc_data:

equ
equ
end if

length:

sccdma:

658

;init il

im
call
call
call
Id

2
filLmem
initscc
initdma
b,O

;Set interrupt mode 2
;initialize tx/rx buffer area
;initialize scc

Id
out

a,OOh
(scc_data),a

;Ioad 1st data to be sent

Id
outO

a,ll00ll00b
(dstat),a

;enable dmac and int from DMAO

Id
out
Id
out

a,05h
(scc_cont),a
a,01101000b
(scc_cont),a

;selectWR5

;init status

;start tll

;wait here for completion

bit
ir

1,b
z,loop

;rx dma end?
;not, then loop again

bc
bC,length
de,tx_buff
hi ,rx_buff

;save bc reg
;compare Ix data with rx data

good:

push
Id
Id
Id
a,(de)
cpi
ir
ip
inc
ir
pop
set
ir
pop

nz,bad_data
v,good
de
chkloop
bc
2,b
enddma
bc

enddma:

;tx/rx completed
;you can put breakpoint here

filLmem:

d
Id
Id
Id
Idi
ip
dec
inc
ir

hl,temp
bC,length
de,tx_buff
(hl),OOh

; prepare data to be sent
; set length

Id
Id
Id
Idi
ret

bC,length
de ,rx_buff
(hl),OOh

loop:

chkloop:

bad_data:

filUoop:

filLOO:

fill_OOI:

;restore bc
;set error flag
;restore bc

nv,filLOO
hi
(hi)
filUoop
; 'clear rx buffer area to zero

659

initscc:
initO:

dec
jr

hi
filLOOI

Id·
Id
cp
ret
out
inc
Id
out
inc
jr

hl,scctab
a,(hl)
Offh
z
(scc_cont),a
hi
a,(hl)
(scc_cont),a
hi
initO

; initializa scc

Id
Id
Id
otimr
Id
outO
Id
outO

hl,addrtab
c,sarOI
b,dstat - sa,rOI

;initialize DMA

a,OOOOii00b
(dmode),a
a,0100i000b
(dcntl),a

;dmacO - i/o to mem++

;intialize zi80's scc

initdma:

; 1 mem wait, no i/o wait,
;EDGE trigger, mem ++ to i/o
;should be EDGE for Tx DMA
;NOT level
;- because of DTR/REQ timing

ret
txend:

Id
outO
set
ei
ret

a,00010100b
(dstat),a
O,b

;isr for dma1 int-complete tx
;disable dma1
;set status

rxend:

Id
outO
set
ei "
ret

a,00100000b
(dstat),a
1,b

;isr for dmaO int
;disable dmaO
;set status

;initialization data table for scc
;table format - register number, then value for the register
;and ends with Offh - since scc doesn't have
;register Offh ...
scctab:

09h

;selectWR9

10000000b

;reset ch a

01000000b

;Reset Ch B

db
db

04h
00000100b

;selectWR4
;async,x 1,1 stop, parity off

if scc_a
else
endif

660

db
db

01h
01100000b

;select WR1
;REOon Rx'

db
db

02h
OOh

;selectWR2
;OOh as vector base

db
db

03h
11000000b

;selectWR3
;Rx 8biVchar

db
db

05h
01100000b

;selectWR5
;tx 8biVchar

db
db

06h
OOh

;selectWR6

db
db

07h
OOh

;selecl WR7

db
db

09h
000OOOO1b

;selectWR9
;stat low, vis

db
db

Oah
OOOOOOOOb

;select WR10
;set as default

db
db

Obh
01010110b
0
1010
110

;select WR11

db
db

Och
OOh

;selectWR12
;BRTC Low

db
db

Odh
OOh

;select WR12
;BR TC high

db
db

Oeh
00010110b
000
1
0
1
1
0

;select WR14

Oeh
00010111b
000
1
0
1
1
1

;select WR14

03h
11000001b

;selectWR3
;rx enable

db
db

Noxtal
TxC,RxC from BRG
TRxC = BRG output

nothing about DPLL
Local loopback
No local echo
DTR/REO is req
BRG source = PCLK
Not enabling BRG yet

nothing about DPLL
Local loopback
No local echo
DTR/REO is REO
BRG source = PCLK
Enable BRG

661

db
db

01h
11100000b

;select WR1
;enable DMA

db
db

Ofh
OOOOOOOOb

;select WR15
;don't use any of exVstat int

db
db

10h
10h

;reset ext/stat twice

db
db

01h
11100000b

,select WR1
;no int

db
db

09h
oo001001b

;selsct WR9
;enableint

Offh

;end of table

db
db
db

scc_data
OOh
OOh

;dmacO source

dw
db

rx_buff
OOh

,dmacO dist

length

,byte count

dw
db

tx_buff+ 1
OOh

;mar

db
db

scc data
OOh

;iar

OOh

;dummyl

length-l

;byte count

org
.block
.block
.block
.block
dw
dw
block
.block
block

sccdma + 200h
2
2
2
2
rxend
txend
2
2
2

;180 int1 vect 00000
; 180 int2 vect 00010
; 180 prtO vect 00100
;180 prt1 vect 00110
;180 dmacO vect 01000
;180 dmacl vect 01010
180 csi/o vect 01100
180 asciO vec! 01110
180 asci1 vect 10000

org
.block
.block
block

sccdma + 1000h
length
length
1

;source/dist addr table for Z180's dma
addrtab:

;interrupt vector table
z180vect:

tx_buff:
rx_buff:
temp:

end

662

First, this program (Table 15) initializes the SCC by:
Async, X1 mode, 8-bit 1 stop, Non-parity.
Tx and Rx clock from BRG, and BRG set to
PCLK/4.Self Loopback
Then, it initializes 4K bytes of memory with a repeating
pattern beginning with OOh and increases by one to FFh
(uses this as Tx buffer area). Also, it begins another 4K
bytes of memory as a Rx buffer with all zeros. After starting,
DMA initialization follows:
DMACO: For Rx data transfer: I/O to Mem, Source addressfixed,Destination address-increasing. Edge sense mode:
Interrupt on end of transfer.

DMAC1: For Tx data transfer: Mem to I/O, Source addressincreasing, Destination address- fixed. Edge sense mode:
Interrupt on end of transfer.

Now, start sending with DMA.
On completion of the transfer, the 2180 DMAC1 generates
an interrupt. Then, wait for the interrupt from DMACO which
shows an end of receive. Now, compare received data
with sent data. If the transfer was successful (source data
matched with destination), OOh is left in the accumulator. If
not successful, OFFh is left in the accumulator.
This program example speCifies a way to initialize the SCC
and the Z180 DMA.

CONCLUSION
This Application Note describes only one example of
implementation, but gives you an idea of how to design the
system using the Z180 and SCC.

For further design assistance, a completed board together
with the Debug/Monitor program and the listed sample
program are available. If interested, please contact your
local Zilog sales office.

663
___

~,~

_____

,"""~""'L",,,,."

..........

~r~~'~."~,~~"''"'i'T'---'''''''''I'''~,

•• -,.,........,-.--,...,,,

664

ApPLICATION NoTE •

~ZiIill

USING' SCC WITH Z8000
IN SQLC PROTOCOL

This application note describes the usa of the
Z8030 Serial Communications Controller (Z-SCC)
with the ZBOOO™ CPU to i""lement a communicationa controller in a Synchronous Data Link
In thia
Control (SOLC) mode of operation.
appliclltion, the ZB002 CPU acts as a controller
for the Z-SCC. This application note also applies
to the non-multiplexed ZB~30.

signal, the Z-SCC introduces extrs wait cycles
in order to synchronize the data transfer
between a controller or DMA and the Z-SCC.
The exa""le given here uses the block mode of data
transrer in, its tranamit and receive routinea.

SOle PROTOCOl

•

Dne channel of the Z-SCC communicstes with the
remote ststion in Half Duplex mode st 9600
bits/second.' To test this applicstion, two ZBOOO
Dsvelopment Modules sre used. Both are loaded with
the same software routinea for initialization and
for transmitting and receiving meaaages. The main
program of one module requests the transmit
routine to send a message of the length indicated
by the 'COUNT' parameter. The other ayatem
receives the _incoming data stream, storing the
message in ita resident memory.

DATA TRANSfER IDlES

The Z-SCC system interface supports the following
data transfar modes:
•

•

Polled tbIe. The CPU periodically polls the
Z-SCC stlltus registers ~o determine if a
received character is available, if a character
is needed for transmission, and if any errors
heve been detected.
Interrupt tbIe. The Z-SCC interrupts ths CPU
when certain previouely defined conditions are
met.

Data communicationa today require a communications
protocol that can transfer data quickly and
reliably.
(he such protocol, Synchronous Data
Link Control (SOLC), ia the link control uaed by
tha IQM Systems Network Architectura (SNA)
communications psckage. SOLC ia a subset of the
International Standards Organization (ISO) link
control called High-Level Data Link Control
(HOLC) , which is used for international data
communicstions.
SOLC is a bit-oriented protocol (80P).
It
differs from byte-control protocols (BCPs), such
as Bisync, in that it uaes only a few bit
patterns for control functions instead of aeveral
special character sequences. The sttributes of
the SOLC protocol are poaition dependent rather
than character dependent, so the data link control
is determined by the poaition of the byte aa well
as by the bit pattern.
A character in SOLC ia aent as an octet, a group
of eight bits. Sevsral octets combine to form a
meesage frsme, in which each Octet be longs to a
particular field. Each message containa: opening
flag, addreas, control, information, frame Check
Sequence (fCS), end closing flag (figure 1).

• ,Block/llM !tide. Using the Wsit/Request (W!REQ~

665

I - - - - - - Z E R O INSERTION/DELETION

------10--11

I _ - - - - C R C ACCUMULATION - - - ' - -. . .
ZERO OR MORE
8·BIT
CHARACTERS
FLAG
(BEGINNING
OF MESSAGE
FRAME)

ADDRESS

Figure 1.

CONTROL

INFORMATION

FCS

FLAG
(END OF
MESSAGE
FRAME)

Fields of the SOLC Tr.-iBBion Fr_

Both flag fields contain a unique binsry pattern,
01111110, which indicates the beginning or the end
of,the message frame. This pattern simplifies the
hardwara intarface in receiving devices so that
multiple devices connected to a common link do not
conflict with one another. The receiving'devices
respond only after a valid flag character has been
detected. Once communication is established with
a ,particular device, the other devices ignore the
measage until the' next flag character is detected.
The address field contains one or lmore octets,
which are used to se lect a particular station on
the data'link. An address of eight 1s is a global
address code that selects all the devices on the
data link. When a primary' station sends a frame,
the address field is used to select are of several
secondary atations;
When a secondary station
s~n~~ a me~sage to the primary station, the
address fiald contains the secondary station
address, i.e." the source of the message.
The control field follows the address field and
contains information about the type of frame
being sent.
The control field consists of one
octet that is always present.
any
sctusl
The information field contains
transferred dsta. This field msy be empty or it
may contain an unlimited number of octets.
However, becsuse of the limitations of the

error-checking algorithm used in the frame-check
sequence, however, the msximum recommended block
size is approximately 4096 octets.
.
The frsme check sequence field follows the
information or control field. 'The res is a 16-bit
Cyclic Redundancy Check (CRC) of the bits in the
address, control, and information fields. The FCS
is based on the CRC-CCI TT code, which uses the
polynomial (x 16 + x 12 + x 5 + 1). The lBmO Z-SCC
contains the circuitry necessary to generate and
check the rcs field.
Zero insertion and deletion is a feature of SOLC
that' allows any dat'a pattern to be sent.
Zero
insertion occurs when five consecutive 1s in the
data pattern are transmitted. After the fifth 1, a
o ia i'nserted before the' next bit 'is sent. The . ,
extra 0 'does not affect the data in any way and is
deleted by the receiver, thua restoring the
original data pattern.
Zero insertion and deletion insures that the data
stream will not contain a flag character or abort
sequence.
Six 1s preceded and followed by Os
indicate' a flag sequence character.
Seven to
fourteen 1s signify an abort; 15 or more 1s
indicate an idle (inactive) line.
lklder these
three conditions, zero insertion and deletion are
inhibited. Figure, 2 illustrates the various line
conditions.

A. ZERO INSERTION
FLAG

ADDRESS

CONTROL

FLAG

01111110

I DATA
ACTUAL
STREAM

ZERO INSERTION
ADDRESS
CONTROL

=' 10101011
= 01111111

B. ABORT CONDITION

---

•••xlllllll0llllll0 ........
ABORT

FLAG

C. IDLE CONDITION

xxxx111111111111111 ........

Figure' 2.

666

Bit Pattems for Various Line Conditions

•

The SOLC protoco 1 differs from other synchronous
protocols with respect to frame timing. In Bisync
mode, for exa~ Ie, a host computer might
temporarily interrupt transmission by sending sync
characters instead of data.
This suspended
condition continues as long as the receiver does
not time out. With SOLC, however, it is invalid to
send flags in the middle of a frame to idle the
line. Such action causes an error condition and
disrupta orderly operation.
Thus, the transmitting device must send a co~lete frame without
interruption. If a message cannot be transmitted
co~letely, the primary station sends an abort
sequence and restarts the message transmission at
a later time.

SYSTEM INTERFACE
The lS002 Development M:!dule consists of a la002
CPU, 16k words of dynamic RAM, 2k words of EPROM
monitor, a lSQA SID providing dual serial ports, a
lS01
CTC peripheral device providing four
counter/timer channels, two laOA PIO devices
providing 32 programmable I/O lines, and wire wrap
area for prototyping.
The block diagram is
depicted in figure 3. Each of the peripherals in
the development module is connected in a
prioritized daisy chain configuration. The Z-SCC
is included in this configuration by tying its lEI
line to the iEO line of another device, thus
making it one step lower in interrupt priority
co~ared to the other device.

FlS·232C
SERIAL
CHANNELS
(2)

RESET
SWITCH

NMI
SWITCH

Z8000
CPU

CONTROL
INPUTS

EXT~~~~~
~:::::::::::::::::~/I
INIOUT \I

Figure ,.

Block Diagr_ of If!OOO OM

667

Two zeooo Development Modules containing Z-SCCs
are connected as shown in Figure 4 snd Figure S.
The Transmit Dsta pin of one is connected to the
Receive Date pin of the other and vice versa. The
Ze002 is used as a host CPU fo~ loading the
modules' memories with software routines.

_.ifuF
_ _ -_ -_'f'Iiic
_
R~ _ _ .!!'I!..

• LOCAL

Figure..

AlDG

T'~ - - iifx'e
ffii"

8
zaooll
z·acc

zaooll
Z·8CC

.
REMOTE'

Block

Di9. of Tw Z8000 CPUa

The le002 CPU csn addre~s either of the two bytes
contained in 16-bi t words. "the CPU. uses an even
address (16 bita) to access the most significant
byte of a word and an odd addreas for the least
significant byte of a word.
When the Ze002 CPU uses the lower half of the
ActdressiData bus (ADO-AD7 the least significant
byte) for byte read and write transactions during
1/0 oilerationa, these transactions are performed
between the CPU and 1/0 ports located at odd 1/0
addresses. Since the I-SeC is ettached to the CPU
on the lower half of the A/D bus, its registers
must appear to the CPU at odd 1/0 addresses. To
achieve this, the Z-SCC can be programmed to
select
its internal registers
using
lines
AD1-ADS.
This is done either automaticslly with
the force Hardware Reset commsnd in WR9 or by
sending a Select Shift Left Mode commsnd tb WROB
in channel B of the Z":SCC. for, this application,
the Z-SCC registers are located at I/O port
address 'fExx'. The Chip Select signal (CSO) is
derived by decoding I/O address 'fE' hex from
linea ADe-AD1S of the controller.
To select the read/write registers sutomatically,
the Z-SCC decodes linea AD1-ADS in Shift Left
mode. The register map'for the Z-SCC is depicted
in Table 1.

lable 1.
Adckess.
(hex)
fE01
fE03
fEDS
fE07
FE09
FEDB
FEOD
FEDF
fE11
fEB
FE1S
fE17
FE19
fE1B
FpD
ft1f
FE21
FEi3
fE25
FE27
fE29
FE2B
fE2D
ft2F
FEJ1
FE.n
fE3S
FEJ7
FE:39
FE3B
fOD
FEJF

Write Register

Read Register

WRI)8
WR1B
WR2
WIUB
WR48
WRSB
WR6B
WR7B
B DATA

RRDe
RR1B
RR2B
RR3B

WR108
WR11B
WR12B
WR13B
WR148
WR1SB
",ROA
WR1A
WR2
WR3A
WR4A
WR5A
WR6A
WR7A
A DATA
WR9
WR10A
WR11A
WR12A
WR13A
WR14A
WR1SA

RR108

WR9

B DATA

RR12B
RR13B
RR1SB
RROA
RR1A
RR2A
RR3A

A DATA
RR10A
RR12A
RR13A
RR15A

INITlAlIZATilW
The I-SCC can be initialized for use in different
modes by setting various bits in its write
registers.
First, a hardwsre reset must be

La
24'

.--I A D 1 S § B 8 ••
lAD,.

IA013

IAD12

28
18

.. 18

81'D"

+6V

:I: II :I: :

::j""

~
1'3~

-t::

.. .,;

.---

IAD1'~
•••
38

IAO'0
IAD9

lAD,

3 • AD"

3A1-!.

:1: II

.---

IAD7~' ••
IAD6
38

lADs

lAD.

-i

ST,
5T2
ST,
ST,

"20
21

13
15

1A03

IA02
lAD,
IADo

-----"::'"1
.5V

;~~

•

- ~ I;

:r:-:
I ,.. II-!.!..:~+I

NIS

IRIW
,-I- - IHIS

Z8002

~
l' ~'3

AD3

AD2

28
18

2A
1A

AD,
ADo

BUSACK

....
...

-'"
- ...

~
1'3~

"D"~

4.7 KU

lAD,.

III

~'T

1A013

..""~
IAD'0

"0,

Y1.
"0,

mfl:

13~ REftf'
mfl

4MHz

CLOCK

8l
<.0
Figure 5.

Z8OO2 With

sec

-1I

YIACK
IADo

IA~
IA~

-t::
--t

40
1
39

-INTACK
ADo
AD,
A1>2

IAD3

AD3

lAD.

AD.

lADs

ADs

lADs

IADr

-4

ADr

iNi

4MHz

+5V

lEO

iAS

iDS

AS
Os

IRIW

RiW

+5V

CSt

CSO

1A012

NV.

RESET

zaoao
Y7

24.

i:. ~

Y-L.

r---

~'8::~::::::::==:J:±:::t::
1~.~+------r=r=r==~--.----------=--.. ~

La
~

~I~:
~

AD'0

+------+---.. iAS

iDS

ADa

PCLK

lEI

•

T,D'

RxDA

~
14

lR.CA

10
12

MiCA

WAIT

performed by setting bits 7 and 6 of WR9 to one;
the rest of the bits are disabled by writing a
10g1c zero.
SOLC protocol is eatabliahed by selecting a SOLC
mode, sync mode enable, and a x1 clock in WR4. A
data rate of 9600 baud, NR1 encoding, and a
character length of eight bits are among the other
options that are selected in this example (Table

2).
Note that WR9 is accessed twice, first to perform
a hardwsre reset and again at the ~nd of the
initialization sequence to enable interrupts. The
programming
bequence
depicted
in
Table
2
establishes the necesssry parameters for the
receiver and tranamitter so that they are ready to
perform communication tasks when enabled.

Enable (VIE) bita aet.
The Program Status Area
Pointe'r (PSAP) is loaded with the address %4400
using the Load Control instruction (LOCTL). If the
.1BOOO Development Ibdule is intended to be usild,
the PSAP need not. be loaded by the progr':lmmer
because the development module' a monitor loads, it
automatically after the NMI button is pressed.
Since VIS and Status Low are selected in WR9, the
vectora listed in Table 3 will be returned during
the Interrupt Acknowledge cycle.
Of the four
interrupt's listed, only two, Ch A Receive
Character Available ~nd Ch A Special Receive
Condition, are used ini the example given here.

Table 3.

(hex)

PS
Addreaa*
(hex)

2B
2A
2C
2E

446E
4472
4476
447A

Vect~

Table 2. Progr-mg Sequance
for Initialization

Value
Register

(hex)

WR9
WR4

CO
20

WR11l
WR6
WR7
WR2
WR11

BO
AB
7E
20
16

WR12

WR1J
WR14

0
03

WR1S
WRS

00
60

WR3

WR1

WR9

Effect
Hardware reset
x1 'clock, SOlC mode, sync mode
enable
NR1, CRC pre,set to one
Any station address e.g. "AB"
SOLC flag (01111110) = "7E"
Interrupt vector "20"
Tx clock from BRG output, TRxC
pin = BRG out
Lower byte of time constant =
"CE" for 9600 baud
~per byte = 0
BRG source bit = 1 for PCLK as
input, BRG enable
External Interrupt Disabla
Tra~smit B bits/character SOlC
CRC
Rx' B bits/character, Rx enable
(Automatic Hunt mode)
Rdnt on 1st char & sp. cond.,
ext into disable
HIE, ,VIS, statua, Low

The 18002 CPU must be operated in System mode to
execute privileged ,I/O instructions. So the flag
and Control Wor'd (fCW) should be loaded with
system normal (S/N) , and the Vectored Interrupt

670

Interrupt Vectors

Interrupt
Ch
Ch
Ch
Ch

A Transmit Buffer Empty
A External Status Change
A Receive Char. Available
A Special Receive Condition

*Assuming that PSAP has been aet to 4400 he«, "PS
Adc!ress" refers to the location in the Program
Status Area where the service routine address is
stored'for that particular interrupt.

TRANSMIT OPERATION
To tranamit a block of data, the main program
calls .1 up the transmit data routine.
With this
routine, each messsge block to be transmitted is
stored in memory, beginning with location 'TBUf'.
The number of characters contained in each block
is determined by the value aSSigned to the 'COUNT'
parameter in the main module.
To prepare for transmission, the routine enables
the transmitter and selects the Wait On Transmit
function; it 'then enables the wait functi0l,l. The
Wait On Transmit function indicates to the CPU
whether or nat the 1-SCC ·is ready to accept data
from the CPU. If the CPU attempta to send data to
the Z-SCC when the transmit buffer is full, the
Z-SCC ~sserts its Wait line and keeps it Low u~til
the buffer is empty~ In response, the CPU extends
itS' I/O cycles until the Wait line goes inactive,
indicating that the Z-SCC is ready to, receive
data.

The CRC generator is reset and the Transmit CRC
bit is enabled before the first character is sent,
thus inc luding all the characters sent to the
I-SCC in the CRC calculation.
The I-SCC's transmit underrun/EOM latch must be
reset sometime after the first character is
transmitted by writing a Reset Tx Underrun/EOM
command to WRO.
When this latch is reset, the
Z-SCC automatically appends the CRC characters to
the end of the message in the case I, of an underrun
condition.
finally', a three-character delay is introduced at
the end of the transmission" which allows the
Z-SCC sufficient time to transmit the last data
byte and two CRC characters before disabling the
transmitter.

RECEIVE OPERATIII'
33t0
0076

LDA

RO,REC

Rl(n76) ,RO

0016
0018
001A
001C
OOlE
0020
0022
0024
0026

7600
OOPA'
3310
007A
5FOO
0034'
5FOO
008C'
E8FP

LOA

RO,SPCOND

0028
0029
002A
002B
002C
0020
002E
002F
0030
0031
0032
0033

0034

48
45
4C
4C
4F
20
54
48
45
52
45

Rl(n7A) ,RO

CALL

INIT

CALL

TRANSMIT

I INTERRUPTS I
IEXT. STATUS SERVICE ADDR. AT '4476 INI
IPSAI
ISP.COND.SERVICE ADDR AT '447A IN PSAI

JR
TBUP,

BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL

"AB

END

MAIN

'H'
'E'

I STATION ADDRESS I

'L'
'L'

'0'
'T'

'H'
'E'
'R'
'E'

673

I ******.****.* •••• * INITIALIZATION ROUTINE FOR Z-SCC

GLOBlIL
ENTRY

0034
0034
0036
0038
003A
003C
003E
0040
0042
0044
0046
0048
004A
004C
004E

2100
OOOF
7602
OOU'
2101
FB21
0029
A920
3A22
0018
8D04
EEF8
9E08
12
oon CO
0050 08
0051 20
0052 14
0053 80
0054
0055
0056
0057
0058
0059
005A
005B
005C
005D
005E
005F
0060
0061
0062
0063
0064
0065
0066
0067
0068
0069

lILOOP,

RO,H5

INO.OF PORTS TO WRITE TOI

LDA

R2,SCCTAB

IADDRESS OF DIITA FOR PORTSI

Rl,'WROA

lIDDB
INC
ooTIB

RL1,@R2
R2
@R1,@R2,RO

IPOINT TO WROA,WRlA ETC TRRO LOOPI

RO
NZ,lILOOP

lEND OF LOOP?I
INO,KEEP LOOPINGI

2*9
'CO
2*4
UO
2*10
\80

BVlIL
BVlIL
BVlIL
BVlIL
BVlIL
BVlIL
BVlIL
BVlIL
BVlIL
BVlIL
BVlIL
BVlIL
BVlIL
BVlIL
BVlIL
BVlIL
BVlIL
BVlIL
BVlIL
BVlIL
BVlIL
BVlIL

16
18
CE
1A
00
1C
03
lB

00
OA
60
06
C5
02
08

00611 12
006B 09
006C

TEST
JR
RET
SCCTAB. BVlIL
BVlIL
BVlIL
BVlIL
BVlIL
BVlIL

OC
AB
OE
71!:
04
20

END

*.****************.**** I

INIT PROCEDURE

2*6
'AB
2*7
UE
2*2
'20

2*11

U6
2*12
tCE
2*13

2*14

'03
2*15
\00

2*5
\60

2*3
\C5
2*1
'08

BVlIL
BVlIL
INIT

2*9

'Og

1 ****************** RECEIVE ROUTINE

IWR9-HlIRDWARB RBSETI
IWR4-X1 CLK,SDLC,SYNC MODEl
IWRlO-CRC PRESET ONE,NRZ,FLAG ON IDLE,I
IFLIIG ON UNDERRUNI
IWR6-

lIDDRESS FOR SDLC STATION I

IWR7-SDLC FLIIG CHARI
IWR2-INT VECTOR '201
IWRl1-Tx CLOCK , TRxC OUT-BRG OUTI
IWRl2- LOWER TC-CEI
IWRl3- UPPER TC-OI
IWRl4-BRG ON,BRG SRC-PCLII
IWRl5-EXT INT. DISABLE I
IWRS-Tx 8 Bl!S/CHAR, SDLC CRCI
IWRl-lIDDR SRCH,REC ENABLE I
IWRl-ax INT ON 1ST' SP COND,I
IEXT INT DISABLEI
IWR9- MIE, VIS, STATUS LOlli

************************************ I

RECEIVE II BLOCK OF MESSAGE
GLOBlIL
ENTRY

006C
006C
DOn
0070
0072
0074
0071i
0078
00711
007C
007E
0080
0082
0084
0086
0088
00811
008C

674

C828
31186
FE23
6008
00118
3A86
FE23
2101
FEll
2102
OOOE
2103
5400
31118
0230
9£08

RECEIVE PROCEDURE
LDB
OUTB

RLO,n28
WROll+2, RLO

111111'1' ON RECV. I

LDB

RLO,'A8

OUTB

WROII+2,RLO

Rl, 'RROA+16

R2,'COUNT+2

ICOUNT+2 CHARACTERS TO RElIDl

Rl,'RBUP

IRECEIVE BUFPER IN MEMORY I

INDRB

@R3,@R1,R2

IREAD THE ENTIRE MESSAGE I

RET
END RECEIVE

IENABLE WIlIT rNC. SP. CONDo INTI

1****************
I
I

GLOBAL
ENTRY

008C
008C
008E
0090
0092
0094
0096
0098
009A
009C
009E
OOAO
00A2
00A4
00A6
00A8
OOM
OOAC
OOAE
OOBO
00B2
00B4
00B6
00B8
OOBA
OOBC
OOBE
OOCO
00C2
00C4
00C6
00C8
OOCA
OOCC
OOCE
0000
0002
0004
0006

2102
0028'
C8U
JA86
PE2B
C800
JA86
1'E2J
C888
JA86
PE2J
C880
JA86
PE21
2101
FEJ1
2100
0001
C869
JA86
PE2B
JA22
0010
C8CO
JA86
PE2l
2100
OOOB
JA22
0010
2100
OJ9E
F08l
C800
JA86
FE2B
9E08

DEL.

0006 9JPJ
0008 9JF2
OODA 9JF1
00DC~9JFO

OODE
00£0
00E2
00E4
00E6
00E8
OOEA
OOEC
OOE£
001'0
00F2
001'4
001'6
001'8
OOFA

JA94
FE21
A690
E602
51'00
006C'
C8J8
3AS6
PE2l
97FO
97F1
971'2
971'3
7BOO

SEND A BLOCK OF EIGHT DATA CHARACTERS
THE BLOCK STARTS AT LOCATION TBUF

I
I

TRANSMIT PROCEDURE
LD

R2,ITBUP

IPTR TO START OF BUFFER I

LOB
OUTH

RLO,U68
WROA+lO, RLO

I ENABLE TRANSMITTER I

LOB
OUTH

RLO,nOO
WROA+2,RLO

IWAIT ON TRANSMIT I

LOB
OUTB

RLO, n88
WROA+2,RLO

IWAIT ENABLEI

LOB
OUTH

RLO,n80
WROA,RLO

IRESET TxCRC GENERATOR I

Rl,IWROA+16

IWR8A SELECTED I

RO,1l

LOB
OUTH

RLQ,n69
WROA+lO,RLO

ISDLC CRCI
IWRSA-TxCRC ENABLE I

OTIRB

@R1,@R2,RO

ISEND ADDRESS I

LOB
OUTB

RLo,nCO
WROA,RLO

I RESET TxUND/EOM LATeBI

RO,ICOUNT-1

OTIRB

@R1,@R2,RO

I SEND MESSAGE I

RO,U26

ICREATE DELAY BEFORE DISABLING I

DJNZ
LOB
OUTB

RO ,DEL
RLO,IO
WROA+l 0, RLO

ITRANSMITTER SO THAT CRC CAN BEl
ISENTI
IDISABLE TRANSMITTERI

RET
END TRANSMIT

J*************

0006

TRANSMIT ROUTINE ************************ .. *********** t

RECEIVE INT. SERVICE ROUTINE ************************* J

GLOBAL REC PROCEDURE
ENTRY
PUSH
@R15,R3
PUSH
@R15,R2
PUSH
@R1S,R1
PUSH
@R1S,RO
RL1,RROA
INB

RESET.

IREAD STATUS REG RROAI

BITH
JR
CALL

RL1,10
Z,RESET
RECEIVE

ITEST IF Rx CHAR SETI
IYES CALL RECEIVE ROUTINE I

LOB
OUTH

RLO,I\38
WROA,RLO

IRRSET HIGHEST IUSI

POP
POP
POP
POP
IRET

RO,@R15
Rl,@R15
R2,@R15
R3 ,@R15

END REC

675

I············
OOPA
OOPC
OOPE
0100

93PO
3A84
P823
A687

0102
0104
0106
0108
010A
010C
010E

E603
C820
3A86
F821
C830
3A86
FE21
C808
3A86
F£23
C838
3A86
FE21
97FO
7BOO

0110

0112
0114
0116
0118
011A
011C
011E
0120

SPECIAL CONDITION INTERRUPT SERVICE ROUTINE

PUSH
INB

@R15,RO
RLO,RROA+2

IREAD ERRORS I

BITB
RLO,'7 '
I END OF PRAME ? I
IPROCESS OVERRUN,FRAMING ERRORS IF ANYI
JR
Z,RESE
LDB
RLO,H20
OUTB
WROA,RLO
I YES,ENABLE INT ON NEXT REC CHARI
RESEI

LDB
OUTB

RLO,H30
WROA,RLO

IERROR RESETI

LDB
OUTB

RLO,n08
WROA+2,RLO

IWAIT DISABLE,RxINT ON 1ST OR SP COND.I

LDB
OUTB

RLO,n38
WROA,RLO

IRESET HIGHEST IUSI

POP
IRET

RO,@R15

END SPCOND
END SDLC

676

············.··1

GLOBAL SPCOND PROCEDURE
ENTRY

OOPA

~ZiIro

ApPLICATION NOTE

SCC IN BINARY
SYNCHRONOUS
COMMUNICATIONS

October 1982
Block/DMA Made. USlng the Walt/Request (W/REQ)
slgnal, the Z-SCC 1ntroduces extra walt cycles
to synchronize data transfer
between
a
CPU or DMA controller and the Z-SCC.

Zllog's Z8030 Z-SCC Serial Communlcatlons Controller lS one of a family of components that are
Z-8US· compatible with the Z8000· CPU. Comblned
with a Z8000 CPU (or other eXlsting 8- or 16-blt
CPUs with nonmultiplexed buses when using the
Z8530 SCC), the Z-SCC forms an integrated data
communlcatlons controller that lS more cost effective and more compact than systems lncorporat lng
UARTs, baud rate generators, and phase-locked
loops as separate entities.

•

The approach examined here 1mplements a commUnlcations controller in a Binary Synchronous mode of
operation, wlth a Z8002 CPU actlng as controller
for the Z-SCC.

Three varlatlons of character-oriented synchronous
commulllcations are supported by the Z-SCC: Monosync, Blsync, and External Sync (Figure 1).
In
Monosync mode, a slngle sync character lS transmltted, wh~ch lS then compared to an ldentical
sync character in the recelver. When the receiver
recognlzes thlS sync character, synchronlzatlon is
complete; the recelver then transfers subsequent
characters lnto the recelver FIFO ln the Z-SCC.

One channel of the Z-SCC lS used to communicate
wlth the remote statton 1n Half Duplex mode at
9600 bits/second.
To test thlS application, two
Z8000 Development Modules are used.
Both are
loaded with the same software routines for 1111t1allzation and for transmlttlng and recelvlng
messages. The main program of one module requests
the transmlt routine to send a message of the
length indicated in the 'COUNT' parameter. The
other system receives the lncomlng data stream,
storlng the message ln its resident memory.

The example glven here uses the block mode of data
transfer in lts transmlt and recelve routlnes.

SYNCHRONOUS ID)[S

DATA

SYNC

CRC1

CRC21

DATA

CRC1

CRC21

DATA

CRC1

CRC21

a. MONOSYNC MODE

SYNC

DATA

b. BISYNC MODE
EXTERNAL
SYNC SIGNAL

DATA TRANSFER ID)[S

The Z-SCC system lnterface supports the followlng
data transfer modes:
•

•

Polled Mode. The CPU penodlcally polls the
Z-SCC status reg1sters to determlne the avallabllity of a received character, lf a character
is needed for transmisslOn, and }f any errors
have been detected.
Interrupt Mode. The Z-SCC lnterrupts the CPU
when certaln previously defined condltlOns are
met.

c. EXTERNAL SYNC MODE

Figure 1.

Synchronous Mbdes of c.-mication

Blsync mode uses a 16-blt or 12-blt sync character
in the same way to obtaln synchrolllzatton. E.xternal Sync mode uses an external signal to mark the
beglnlllng of the data held; l.e.,. an external
lnput pln (SYNC) indicates the start of the lnformatlOn held.'

\
In all ,synchronous modes, two Cyclic Redundsncy
Check (CRC) bytes csn be concetensted to, the messsge to 'detect dsts transmIssion errors. The CRC
by tes ' lnserted in the transmltted message are ,compared to the CRC bytes computed to the rece 1 vet.
Any dIfferences found are held in the receive
error FIfO.

SYSTEM INTERFAa:

The Za002 Development Module consIsts of e Za002
CPU, 16K words of dynamlc RAM, 2K words of EPROM

Two zaooo Development Modules contaIning I-SCes
are connected as shown In' figure 3 and F:lgure 4.
rhe Transmit Data pIn of qne is col'lnected to the
ReceIve Oats pIn of the other and vlce versa. The
Za002 is used as a host CPU for loadlng the
modules' memories with software routInes.
The ZaODO CPU can address either of the two bytes
cont81ned in 16-blt words. The CPU uses an even
address (16 bits) to access the IIIlst-slgnlf1cant
byte of a word and an odd address for the leastsignlflcant byte of a word.

"'2m
SERIAL
CHANNELS
(2)

RESET

NON MASKABLE
INTERRUPT

ZIOOO
CPU

CONTROl.
INPUTS

EXT~~~~
(;:::::::::::::::~~
INfOUT '\I

figure 2.

Block Diagr_ of Z8000 lit

monitor, a ZaOA SID prov1ding dual serlal ports, a
ZaOA CTC perIpheral devlce prOVIding four counter/
tImer channels, two ZaOA PIO devices providl~g 32
programmable I/O hnes, aDd wire wrap srea for
prototyping.
The block 'd18gram is deplct'ed in
figure 2. Each of the perIpherals in the development module is connected in a prIoritized deisy-chain confIguration. The Z-SCC IS Included 1n thIS
conflgurallon ,by tY1ng its lEI line to the lEO
llne 011 another device, thua makIng it one step
lowt;r in Interrupt pnonty compared t~ the other
deVIce.

678

Z8001

Z·ICC

...!''!!!.G

_!!D__
_ ~x.!L __RT-!.C
_~--~
_R!!! __ .!!''L

--.-...II

Z·ICC

REMOTE

LOCAL

figure 3.

Z8001

Block Diagr_ of TIIO Z8000
Davel~ Modules

La
243
1"015

ADu

IAD,.

AD,.

"Dn

1"0'3

I"D12

+5V

"D'2

.---

IAD11~' .B
38

1"0'0

IAOtt

10
11

IADa

28
18

4A~

OAD

~
•

AD'0

Ao,
ST,
ST,
ST,
ST,

ADa:

~
.---

lADs

.....

IADn

IAD'2

I.D"~

r igure

-J>o

l8002 with

sec

Jk
-t:

.. AD7
5ii1f

. .Hz

+5V

lEI

•
35

.-'l
~

lAO,

IADz

""-

lAO,

CLOCK

RxDA

V14

TxDA

lAD,

IAD'0

4MHz.-

AD1

IADa

~IT
~ R!m
NMJ

ADo

ADs

.AD,4

13
14

lAO,

IAo,,§

NMJ :
iiESEf

lADe

lADs

INTACK

lAD.

4.7KU

III

ViiCK

243

+5V

Eli

zaoao

t---t:r=E=±::=iAS

iAS
iDS
IRIW
+5V

PCLK

lEO

ANi

CSI

When the ZB002 CPU uses the lower half of the
Address/Data bus (ADO-AD7 the least slgmflcant
byte) for byte read and wnte transachons dUrlng'
I/O operations, these transachons. are performed
between the CPU and I/O ports located at odd I/O
addresses. Slnce the Z-SCC lS attached to the CPU
on the lower half, of the A/D bus, lts reglsters
must appear to the CPU at odd I/O addresses.
To
achleve thls, the Z-SCC can be programmed' to
select
ltS
internal
reglsters
uSlng
llnes
A01-A05'
ThlS is done elther automahcally wlth
,the Force Hardware Reset command In WR9 or by
Sendlng a Select Shl ft Left Mode command to WROB
In channel B of the Z-SCC. For thlS appllcatlon,
the Z-SCC reglsters are located at I/O port
address 'FExx'.
The ChlP Select Slgnal (CSO) is
denved by decodlng I/O address 'FE' hex from
hnes ADB-AD15 of the controller. The Read/Wnte
reglsters are automahcally Be leded by the Z-SCC
when lnternally decodlng hnes AD1-AD5 In Shlft
Left mode.
To select the Read/Wnte reglsters
automat1cally, the Z-SCC decodes llnes AD 1-AD 5 In
Shl ft Left mode. The reglstet map for the Z-SCC
lS deplcted In Table 1.

INITIALIZATIIJoI
The Z-SCC can be'lnltlallzed for use ,In different
modes by settlng vanous blts in'lts Wnte registers. Fust, a hardware reset must be performed
by setting bltS 7 and 6 of WR9 to one; the rest of
the blts are dlsabled by wrltlng a IOglC zero.
Bisync mode lS estabhshed by se lechng a 16-bl t
sync character, Sync Mode Enable, and a X1 clock
In WR4. A data rate of 9600 baud, NRZ encodlng,
and a data character length of elght bits are
among the other optlons that are selected In thlS
example (Table 2).
Note that WR9 is accessed twice, flrst to perform
a hardware reset and agaln at the end of the lnltlalizatlon sequence to enable the lnterrupts.
The programmlOg aequence" depicted In Table 2
estabhshes the necessary parameters for the
recelver and the transmltter' so that, when
enabled, th~y are ready, to perform commumcahon
tasks. To avold lnternal race and false lnterrupt
condltlons, lt lS lmportant'to lnlt1allze the reglsters 1n the sequence deplcted In thlS apphcatlOn note.

680

Table 1.
Address
(hex)

FE01
FE03
FE05
FE07
FE09
FEOB
f.EOD
FEOF
FE11
FEU
FE15
FE 17
FE19
FE1B
FE1D
FE1F
FE21
FE23
FE25
FE27
FE29
FE2B
FE2D
FE2F
FE31
FE33
FE35
FE37
FE39
, FE3B
FOD
FEY

Write Regiater
WROB
WR1B
WR2
WR3B
WR4B
WR5B
WR6B
WR7B
B DATA
WR9
WR10B
WR11B
WR12B
WRUB
WR14B
WR15B
WROA
WR1A
WR2
WR3A
WR4A
WR5A
WR6A
WR7A
ADATA
WR9
WR10A
WR11A
WR12A
WRUA
WR14A
WR15A

Read Regiater
RROB
RR1B
RR2B
RR3B

B DATA
RR10B
RR12B
RRUB
RR15B
RROA
RR,1A
RR2A
RR3A

A DATA
RR10A
RR12A
RR13A
RR15A

The ZB002 CPU mu!3t be operated In System mode In
order to execute prlVlleged I/O lnstruchons, so
the Flag Control Word (FCW) should be loaded wlth
System/Normal (SiN), and the Vectored Interj.'upt
Enable (VIE) bltS set.
The Program Stalus Area
POlnter '(PSAP) lS loaded wlth address %4400 uSlng
the Load Control lnstructlon (LDCTL). If the ZBOOO
Development Module lS lntended to be used, the
PSAP n~ed not be loaded by the programmer as the
development modules monltor loads lt automatlcally
after the NMI button is pressed.

Table Z. Progr-mg Sequence
for Initialization
Value
Register

Effect

(hex)

WR9
WR4

CO
10

WR10
WR6
WR7
WR2
WR11

0
AB
CD
20
16

WR12

WR13
WR14

0
03

WR15
WR5
WR3

00
64
C1

WR1

WR9

Hardware reset
x1 clock, 16-bl.t sync, sync rode
enable
NRZ, CRC preset to zero
Any sync character "AB"
Any sync character "CD"
Interrupt vector "20"
Tx clock from BRG output, TRxC
pl.n = BRG out
Lower byte of time constant =
"CE" for 9600 baud
Upper byte = 0
BRG source bl.t = 1 for PCLK as
l.nput, BRG enable
External l.nterrupt disable
Tx 8 bits/character, CRC-16
Rx 8 bl.ts/ch"racter, Rx enable
(Automatic Hunt rode)
RxInt on 1st char' &: sp. cond.,
ext., l.nt. dl.sable)
HIE, VIS, Status Low

Since VIS and Status Low are selected l.n WR9, the
vectors listed l.n Table 3 will be returned durl.ng
the Interrupt Acknowledge cycle.
Of the four
lnterrupts ll.sted, only two, Ch A Recelve Character Available and Ch A Speclal Recel.ve COndl.tlon,
are used in the example gl.ven here.

Table 3.

(hex)

PS
Address*
(hex)

28
2A
2C
2E

446E
4472
4476
447A

Vector

Interrupt Vectors

Interrupt
Ch
Ch
Ch
Ch

A Transm1t Buffer Empty
A External Status Change
A Receive Char. Ava1lable
A Special Recelve Cond1t1on

To transm1 t a block of data, the m81.n program
calls up the transm1t data routine.
Wlth this
rouhne, each message block to be transmitted 1S
stored ln memory, beginOlng with ldcahon 'TBUF'.
The number of characters conta1ned 1n each block
lS determlned by the value asaigned to the 'COUNT'
parameter in the maln-module.
To prepare for transm1ssion, the rouhne enables
the tranamitter and ,selects the Walt On Transmit
funct10n; it then enables the walt functl.on. The
Walt On Transml.t function 1ndlcates to the CPU
whether or not the Z-SCC 1S ready to accept data
from the CPU. If' the 'CPU attempts to send data to
the Z-SCC when the transmit buffer is full, the
Z-SCC asserts its Walt Ilne and keeps it Low untll
the buffer lS empty. In response, the CPU extends
1ts I/O cycles unhl the WBlt hne goes inactive,
indicahng that the z-sec lS ready to receive
data.
The CRC generator lS reset and the T-t'ansmit CRC
b1t 1S enabled before the flrst character lS
sent, thua includlng all the characters sent to
the Z-SCC ln the CRC calculat10n, until the Tranam1t CRC bl.t ia dlsabled. CRC generatJ.on can be
d1sabled f'or a partlcular character by reaettlng
the TxCRC blt wlth1n the transm1t rouhne.
In
th1S application, however, the Transmlt CRC b1t is
not d1sabled, so that all characters sent to the
z-see are 1ncluded 1n the eRe calculat10n.
The z-see's transm1t underrun/EOH latch must be
reset sometlme after the f1rst character is transm1tted by wr1t1ng a Reset Tx Underrun{EDM command
to WRO. When th1S latch 1S reset, the z-see automatically appends the eRe characters to the end of
the message in the case of an underrun condltion.
FJ.nally, a flve-character delay is 1ntroduced at
the end of the transm1ss1on, which allo~s the
z-see sufflc1ent tlme to transm1t the last data
byte, two eRe characters, and two sync characters
before dlsabl1ng the transmltter.

REa:IVE IPERATIIW

* lIPS Address" refers to the 10catJ.on in the Program Status Area where the serV1ce raut1ne
address 1S stored for thst part1cular 1nterrupt,
assumlng that PSAP has been set to 4400 hex.

Once the z-see lS 1nltlalized, lt can be prepared to receive data.
hrst, the rece1ver 1S
enabled, plac1ng the z-sec 1n Hunt mode and thus

681

setting the Sync/Hunt bit in statua register RRO
to 1. In Huh!: mode, the rece1ver 1S 1dle except
that it searches the 'incoming data stream for a
sync character match. When a match is d1scovered
between the incoming data stream snd the sync
characters stored'1n WR6 and WR7, the receiver
ex ita the Hunt mode, resetting the Sync/Hunt bit
in status reg1ster RRO and establishing the
Receive Interrupt On Fuet Character mode. Upon
detection of the receive interrupt, the CPU generates an Interrupt Acknowledge cycle.
The Z-SCC
sends to the CPU vector ~2C, which points to the
l~cstion in the Program Statua Area from which the
rece1ve ihterrupt service'routine is sccessed.
The recelVe data routine is called from within
,the receive interrupt service rout1ne.
Whlle
'expecting a block of (jata, the Wa1t On Receive
function is enabled. Rece1ve data buffer RR8 is
read, end the charactere are etored in memory
locations starting at RBUF.
The Start of Text
(~02) character is discardad. After the End of
Transmission character (~04) is received, the two
CRe bytes ,are read. The result of the eRe check
becomes v~11d two characters later, at which time,
RR1 is read and the CRC error 'bit 1a checked. If
the bit is zero, the message received can be
assumed correct; if the bit is 1, an error in the
tran~miss1on is 1ndicated.

682

Before leaving the interrupt service routine,
Reaet H1ghest IUS '(Interrupt Under
Service),
Enable InterruPt on Next Recieve Character, and
Enter Hunt Mode commands are 1ssued to the Z-SCC.
If a rece1ve over~un error is made, a special condition 1nterrupt occurs. The 'Z-SCC presents the
,vector ~2E to the CPU, anc! the service routine
located at sddr~ss ~447A is eXecuted. The Special
Receive Condition register RR1 is read to determine which error occurred. Appropriate action to
correct the error should be take~ by the user at
this point.
Error Re~et and Reset Highest IUS
commands are given to the z-see before returning
to the main program so that the other lower priority interrupts can occur.

SOfTWARE

Software routines are presented in the follOWing
pages. These routines cen be, modif1ed to include
various versions of Bisync protocol, euch as
Traneparent and Nontransparent modee.
Encoding
meth~ds other thah NRZ (e.g., NRZI, FMO, FM1) can
also be used by modifY1ng WR1Q.

Appeadlx
Software Routines
plz....

LOC

1.3
OBJ CODE

S'l:MT SOURCE STATEMENT
1

BISYIIC NODULE
$LISTON $'1"lY
CONSTANT
WROA
UE2l
RROA
U£2l
RBUP
'5400
PSAKBA
U400
COUNT
12
GLOBAL MAIN PROCEDURB
BHTRY
LOA
Rl,PSAREA

,.,.,.
,.,.

0000
0000 7601
0002 4400
0004 ·7D1D
0006 2100
0008 5000
OOOA 3110
- OOOC OOlC

LDC1L
LD

PSAPOrr,Rl
RO,nsOOO

Rl(tUC) ,RO

7600
OOP4'
3110
0076

LDA

RO,RBe

Rl("76) ,RO

0016 7600
0018 011E'
OOlA 3310
OOlC 007A
001E'5FOO
0020 0034'
0022 SFOO
0024 00A6'
0026 E8rr
0028 02
0029 31
002A 3
002B 33
002C 34
002D 35
002B 36
002F 37
0030 38
OOll 39
0032 30
0033 II
0034

LOA

RO,SPCOND

OOOE
0010
0012
0014

TaUP,

Rl (t.,A),RO

CALL

INIT

CALL

TRANSMIT

JR
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BHD

'02

'1'

'2'
'3'
'4'

I BASB ADDUSS FOR WRO CHANNEL AI
I BASE ADDRESS FOR RRO CHANNEL AI
IBUFPER ARIA FOR aBCEIVE CHARACTER I
ISTART ADDRBSS FOR PROGRAM STAT ADAI
INO. OF CHAR. FOR TRANSMIT ROUTINE I

ILOAD PSUI
IrcH VALUE('5000) AT '441C FOR VBCTOREDI
I INTERROPTS I
IEXT. STATUS SBRVICE ADDR. AT '4476 INI
IPSAI
ISP.COND.SIRYICE ADDR AT U47A IN PSAI

I START OP TIXT I
I BVAL NEAlIS BYTE VALUE. IIBSSAGI CHAR. I

'5'

'6'
'7'
'8'
'9'
'0'
'1'
MAUl

683

I ••••••••••••••• ••• INITIALIZATION ROUTINE FOR I-SCC **** ••• ****************,
GLOBAL
ENTRY

0034
0'034
0'0'36
0'0'38
OD3A
D03C
OD3E
0'0'_0'
0'0'42
0'0'44
0'0'46
0'0'48
DD4A
OD4C
0'0'41
DD4P
0'0'50'
00'51
00'52
0053
00'54
00'55
00'56
00'57
00'58
00'59
OD5A
DDSB
OD5C
GD5D
DOSE
OD5P
0'060'
0061
0'062
0'063
0064
. 0'065
0'066
0'067
0'068
00'69

210'0'
DDDP
760'2
0'048'
210'1
PE2l
00'29
A920
3A22
0'0'18
8D04
IEP8
9£0'8
12
CD
08
10'
14

ALOOP.

INIT PROCEDURE
LD

RD,US

INO.OF PORTS TO WRITE TOI

LOA

R2,SCCTAII

IADDRESS OP'DATA POR PORTSI

al,'WRDA

ADDB
INC
OIiTIB

RLl,@R2
R2
@Rl,@R2,RD

IPOINT TO WRDA,WRlA ETC THRO LOOPI -

RD
IIZ,ALOOP

I END OP LOOP? I
INO,KEEP LOOPING I

00
lC
0'3
11
00
DA
64
0'6
Cl
0'2
08

TEST
'JR
RST
SCCTAI. BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAI.
BVAL
BVAL
BVAL
BVAL
BVAL
BYAL
BVAL
BVAL

2·10
0
2·6
,AI
2·7
'CD
2*2
'20
2*U
' U6
2*12
'CB
2*13
0'
2*14
'03
2*15

GG6A 12
G06B 0'9
G06C

BVAL
BVAL
END INIT

2·9
'09

DO'

DC
AI .
DE
CD
04
20'
16
16
18
C£
11.

2·9
'CO
2·4
nO'

'DO'

2*5
"4
2*3
'Cl
2·1
'08

1****************** RECIIVE ROUTINE

IWR9-HARDWARE RESETI
IWR4-Xl CLI,16 BIT SYNC MODBI
IWR1D-CRC PRESET.llRO,NRI,16 BI'1' SYNCI
IWR6-ANY SYNC CHAR 'All
IWR7-ANY SYNC CHARR 'CDI
IWR2-INT VICTOR nO' I
IWall-TxCLOCK , TRxC OUT-BRG OUTI
IWal2- LOWER TC-'C£I
IWR13- UPPER TC-DI
IWal4-BRG ON, ITS SRC-PCLKI
IWal5-NO EXT lilT EN.I
IWR5- TX 8 BITS/CHAR, CRC-HI
IWal-ax 8 BITS/CHAR,' REC ENAILE I
IWal-RxINT ON 1ST OR SP CONDI
EXT INT DISABLII
I
IWR9- MIB,VIS,STATUS LOWI

***-_._._----_ ... _----------_._._---,

RECEIVE A BLOCK OP MESSAGB
THB LAST CHARACTER SHOULD BE EOT('D4)
GLOBAL
ENTRY

OD6C

DOIIC
0'068
0070
0072
00'74
0076
00'78
007A
OD7C
0071
0080
0082
0084
0086
0088
008A
008C
OD8B
0'0'90
00'92
0094
0096
00'98
009A
009C

C828
3A86
PII23
600'8
00A8
lA8.
PB23
2101
PBll
3C18
C8C9
3A86
PB27
2103
5400
3C18
2838
AI3D
DA08
040'4
EEPA
3C18
3Cl8
3AS4
FE23

00'91
OOAO
OOAl
00A4
OOAII

ClOD
3A86
PE27
9B08

READ.

RECBIVE PROCEDURE
LDB
OUTII

RLO,'U8
WROA+2,RLO

LOB

RLO,tA8

OUTB

WROA+2,RLO

al, 'RROA+16

INS
LDB
OUTII

RLO,@Rl
RLO,nC9
WROA+6,RLO

al,'RBUF

INB
LDB
DBC
CPB

RLO,@al
@R3,RLD
al,U
RLO,ltD4

JR
INB
INB
INS

NI,READ
RLO,@~l

RLO,@Rl
RLO,RROA+2

IWAIT ON RECV. I

IBKABLI WAIT 1ST CHAR,SP.COND. INTI
IRBAD STX CHARACTER I
IRx CRC ENABLE I
IRBAD MBSSAGII
I STORE CHARACTER IN RlUP I
lIS IT BND or TRANSMISSION ?I
IRBAD PADlI
IREAD PAD21
IRBAD CRC 8TATU81

PROCESS cac BRROR IP ANY, AND GIVE ERROR RBSET COMMAND IN WRDA
RLO',.o
LDB
IDlSABLI RBCIIVBRI
OUTII
WROA+6,RLO
RET

END RECEIVB

I
I

*------_._._-_ ..
GLOBAL
ENTRY

00A6
00A6
00A8
OOM
OOAC
OOAE
OOBO
00B2
00B4
00B6
00B8
OOBA
OOBC
OOBE
OOCO

2102
0028'
CS6C
3A86
PE2B
CSOO
3A86
PE23
C888
3AS6
PE2J
C880
3A86
PE21
FE31
CS6D
JA86
PE2B
2100
0001
JA22
0010
C8CO
3A86
FE2l
2100
OOOB
3A22
0010
C804
3E18
2100
0686
F081
C800
JA86
FE2B
9£08

00P4
93FO
JA84
FEn
M84
EE02
5FOO
006C'
C808
3A86
FE2J
C8D1
JA86
PE27
C820
3A86
FE21
C8J8
JA86
FE2l
97FO
7BOO

I
I

TRANSMIT PROCEDURE
R2,.TBUF

I PTR TO START OP BUFFERI

RLO,'UC
WROA+10,RLO

IENABLE TRANSMITTER I

LOB
OUTS

RLO,nOO
WROA+2,RLO

IWAIT ON TRANSMIT I

LOB
OUTB

RLO,n88
WROA+2,RLO

IWAIT ENABLE,INT ON 1ST • SP CONDI

LOB
OUTS

RLO,n80
WROA,RLO

IRESET TxCRC GENERATOR I

Rl,'WROA+l6

IWR8A SELECTED I

LOB
OUTB

RLO, '%60
WROA+lO,RLO

I Tx CRC ENABLE I

RO,Il

LOB
. OUTS

DEL.

OTIRB

@Rl,@R2,RO

ISEND START OP TEXTI

LOB
OUTB

RLO,nCO
WROA,RLO

IRESET TxUND/EOM LATCHI

RO,.COUNT-1

OTIRB

@R1,@R2,RO

ISEND MESSAGEI

LOB
OUTB
LD

RLO,n04
@R1,RLO
RO,Il670

ISEND END OP TRANSMISSION CHARACTER I
ICREATE DELAY BEPORE DISABLING I

DJNZ
LOB
OUTS

RO,DEL
RLO,'O
WROA+10,RLO

IDISABLE TRANSMITTER I

RET
END TRANSMIT

s*••

00F4
00F6
00F8
OOFA
OOFC
OOFE
0100
0102
0104
0106
0108
010A
010C
010E
0110
0112
0114
0116
0118
OllA
OllC
OllE

SEND A BLOCK OF DATA CHARACTERS
THE BLOCK STARTS AT LOCATION TBUF

OOCl 2101

00C4
00C6
00C8
OOCA
OOCC
OOCE
0000
0002
0004
0006
0008
OODA
OOOC
OODE
OOEO
00E2
00E4
00E6
00E8
OOEA
OOEC
OOEE
OOFO
00F2
00P4

TRANSMIT ROUTINE ****.***.*******.***********~******* 1

**~*******

RECEIVE INT. SERVICE ROUTINE *tt_ ••• __________ * __ ._. __ 1

GLOBAL REC PROCEDURE
ENTRY
PUSH
@R1S,RO
INB
RLO,RROA

RESET.

END REC

IREAD STATUS PROM RROAI

BITB
JR
CALL

RLO,I4
NZ,RESET
RECEIVE

ITEST IF SYNC HUNT RESET I
IYES CALL,RECEIVE ROUTINEI

LOB
OUTS

RLO, n08
WROA+2,RLO

IWAIT DISABLE I

LDB
OUTB

RLO,nDl
WROA+6,RLO

IENTER HUNT MODEl

LOB
OUTB

RLO,n20
WROA,RLO

IENABLE INT ON NEXT CHARI

LDB
OUTB

RLO,n38
WROl',RLO

IRESET HIGHEST IUSI

POP
IRET

RO,@RlS

685

I.·..·.....··
011E 93PO
0120 3A84
0122 PB23
0124
0126
0128
012A
012C
012B
0130
0132
0134
0136
0138
013A
013C
013E

SPECIAL 'CONDITION INTERRUPT SERVICE ROUTINE

C830
3A86
PB21
C808
3A86
PE23
C8Ul
3AB6
FE27
CB3B
3AB6
FE2l
97FO
7BOO

0140

PUSH
INB

Assembly complete

@R15,RO
RLO,RROA+2

I READ ERRORS I

IPROCESS ERRORS I
LOB
RLO,'t30
OUTB
WROA,RLO

I ERROR RESET I

LOB
OUTS

RLO,'tOB
WROA+2,RLO

IWAIT DISABLE,RxlNT ON 1ST OR SP COND.I

LOB
OUTB

RLO,nDl
WROA+6,RLO

IHUNT MODE,REC. ENABLE I

LOB
OUTB

RLO,'t38
WROA,RLO

IRBSET HIGHEST IUSI

POP
IRET

RO,@R15

END SPCOND
END BISYNC

o errors

686

···············1

GLOBAL SPCONU PROCEDURE
ENTRY

011E

ApPLICATION NOTE

~ZiIm

ON-CHIP OSCILLATOR
DESIGN

ESIGN AND BUILD RELIABLE, COST-EFFECTIVE,ON-CHIP OSCILLATOR CIRCUITS THAT
ARE TROUBLE FREE. PUTIING OSCILLATOR THEORY INTO A PRACTICAL DESIGN
MAKES FOR A MORE DEPENDABLE CHIP.

INTRODUCTION
This Application Note (App Note) is written for designers
using Zilog Integrated Circuits with on-chip oscillators;
circuits in which the amplifier portion of a feedback oscillator
is contained on the IC. This App Note covers common
theory of oscillators, and requirements of the circuitry (both
internal and external to the IC) which comes from the
theory for crystal and ceramic resonator based circuits.

Purpose and

Ben~fits

The purposes and benefits of this App Note include:

2. To eliminate field failures and other complications resulting from an unawareness of critical on-Chip oscillator
design constraints and requirements.

Problem Background
Inadequate understanding of the theory and practice of
oscillator circuit deSign, especially concerning oscillator
startup, has resulted in an unreliable design and subsequent field problems (See on page 10 for reference materials and acknowledgements).

1. Providing designers with greater understanding of how
oscillators work and how to deSign them to avoid
problems.

OSCILLATOR THEORY OF OPERATION
The circuit under discussion is called the Pierce Oscillator
(Figures 1,2). The configuration used is in all Zilog on-chip
oscillators. Advantages of this circuit are low power consumption, low cost, large output signal, low power level in

the crystal, stability with respect to Vee and temperature,
and low impedances (not disturbed by stray effects). One
drawback is the need for high gain in the amplifier to
compensate for feedback path losses.
Ie

Vo
I

XTAL

4P----tD 1 - - -....
B

Figure 1. Basic Circuit and Loop Gain

Figure 2. Zilog Pierce Oscillator

687

OSCILLATOR THEORY OF OPERATION, (Continued)
Pierce Oscillator (Feedback Type)
The basic circuit and loop gain'is shown in Figure 1. The
concept is straightforward; gain of th~ amplifier is
A = VoNL The gain of the passive feedback element is
B ViNo. Combining these equations gives the equality
AS = 1. Therefore, the total gain around the loop is unity.
Also, since the gain factors A and B are complex numbers,
they have phase characteristics. It is clear that the total
phase shift around the loop is forced to zero (i.e., 360
degrees), since VIII must be in phase with itself. In this
circuit, the amplifier ideally provides 180 degrees of phase
shift (since it is an inverter} Hence, the feedback element
is forced to provide the other 180 degrees of phase shift.

Additionally, these gain and Phase characteristics of both
the amplifier and the feedback element vary with frequency. Thus, the above relationships must apply at the
frequency of interest. Also, in this circuit the amplifier is an
active element and the feedback element is passive. Thus,
by definition, the gain of the amplifier at frequency must be
greater than unity, if the loop gain is to be unity.
The described oscillator amplifies its own noise at startup
until it settles at the frequency which satisfies tl'Je gain!
phase requirement AB = 1. This means loop gain equals
one, and loop phase equals zero (360 degrees). To do this,

the loop gain at points around the frequency of oscillation
must be greater than one. This aChieves an average loop
gain of one at the operating frequency.
The amplifier portion oftheoscillator provides gain> 1 plus
180 degrees of phase shift. The feedback element provides
the additional 180 degrees of phase shift without attenuating the loop gain to < 1. To do this the feedback element
is inductive, Le., it must have a positive reactance afthe
frequency of operation. The feedback elements discussed
are quartz crystals and ceramic resonators.

Quartz Crystals
A quartz crystal is a piezoelectric device; one which
transforms eleotrical energy to mechanical energy and
vice versa. The transformation occurs at the resonant
frequency of the crystal. This happens when the applied
AC electric field is sympathetic in frequenCY with the
mechanical resonance of the slice of quartz. Since this
characteristic can be made very accurate, quartz crystals
are normally used where frequency stability is critical.
Typical frequency tolerance is .005 to 0.3%.
The advantage of a quartz crystal in this application is its
wide range of positive reactance values (Le., it ,looks
inductive) over a narrow ran!ile of frequencies (Figure 3).

z
Region of Parallel
Operation

INDUCTIVE

2Yf

CAPACITIVE

* fs - fp is very small (approximately SOO parts per million)

Figure 3. Series VS. Parallel Reso!lance

688

However, there are several ranges of frequencies where
the reactance is positive; these are the fundamental (desired frequency of operation), and the third and fifth
mechanical overtones (approximately 3 and 5 times the
f.undamental frequency). Since the desired frequency range
in this application is always the fundamental, the overtones
must be suppressed. This is done by reducing the loop
gain at these frequencies. Usually, the amplifier's gain roll
off, in combination with the crystal parasitics and load
capacitors, is sufficient to reduce gain and prevent oscillation at the overtone frequencies. .
The following parameters are for an equivalent circuit of a
quartz crystal (Figure 4):
L - motional inductance (typ 120 mH@4 MHz)
C - motional capacitance (typ .01 pf@ 4 MHz)

Quartz Equivalent CircuH

0----1101-1--

Symbolic Representation
Figure 4. Quanz OSCillator

R - motional resistance (typ 36 ohm @ 4 MHz)
Cs - shunt capacitance resulting from the sum of the
capacitor formed by the electrodes (with the quartz as a
dielectric) and the parasitics of the contact wires and
holder (typ 3 pf @ 4 MHz).
The series resonant frequency is given by:
Fs = 1/(2lt x sqrt of LC),
where Xc and XI are equal.
Thus, they cancel each other and the crystal is then R
shunted by Cs with zero phase shift.
The parallel resonant frequency is given by:

Series vs. Parallel Resonance. There is very little difference between series and parallel resonance frequencies
(Figure 3). A series resonant crystal (operating at zero
phase shift) is desired for non-inverting amplifiers. A parallel
resonant crystal (operating at or near 180 degrees of
phase shift) is desired for inverting amps. Figure 3 shows
that the difference between these two operating modes is
small. ,Actually, all crystals have operating pOints in both
serial and parallel modes. A series resonant circuit will
NOT have load caps C1 and C2. A data sheet for a crystal
designed for series operation does not haye a load cap
spec. A parallel resonant crystal data sheet specifies a
load cap value which is the series combination of C 1 and
C2. For this App Note discussion, since all the circuits of
interest are inverting amplifier based, only the parallel
mode of operation is conSidered.

Fp = 1/[2lt x sqrt of L (C CtlC+Ct)],
where: Ct = CL + Cs

,689

OSCILLATOR THEORY OF OPERATION

Ceramic Resonators

Figure 5 shows reactance vs. frequency and Figure 6
shows the equivalent circuit.

Ceramic resonators are similar to quartz crystals, but are
used where frequency stability is less critical and low cost
is desired. They operate on'the same basic principle as
quartz crystals as they are piezoelectric devices and have
a similar equivalent circuit. The frequency tolerance is
wider (0.3 to 3%), but the ceramic costs less than quartz.

Typical values of parameters are L = .092 mHo C = 4.6 pf,
R =7 ohms and Cs =40 pf, all at SMHz. Generally, ceramic
resonators tend to start up faster but have looser frequency
tolerance than quartz. This means that external circuit
parameters are more critical with resonators.

Impedance 100000
(Ohm)

10000

1000

100

o~--~--~----~--~--~----~--~----~--~--~
2000

4000

6000

8000

10000

Frequency (KHz),

Figure 5. Ceramic Resonator Reactance

690

Power
Supply

RTxCB(SCC)

SYNCB(SCC)

EXTAl (Z180)

XTAl(Z180)
I.C.

470 pf
Probe (in) _ _. .

Under Test
(All Unused
Inpllts: 10kCl To Vee)

Frequency
Generator
1VP-P/Sine

Probe
(out)

Figure 6. Gain Measurement

Load CapaCitors
The effects/purposes of the load caps are:
Cap C2 combined with the amp output resistance provides a small phase shift. It also provides some 'attenuation
of overtones.
Cap C1 combined with the crystal resistance provides
additional phase shift.
These two phase shifts place the crystal in the parallel
resonant region of Figure 3.
Crystal manufacturers specify a load capacitance number. This number is the load seen by the crystal which is the
series combination of C1 and C2, including all parasitics
(PCB and holder). This load is specified for crystals meant
to be used in a parallel resonant configuration. The effect
on startup time; if C1 and C2 increase, startup time
increases to the point at which the oscillator will not start.
Hence, for fast and reliable startup, over manufacture of
large quantities, the load caps should be sized as low as
possible without resulting in overtone operation.

Open Loop Gain lis. Frequency over lot, vce, Processs
Split, and Temp. Closed loop gain must be adequate to
start the oscillator and keep it running at the desired
frequency. This means that the amplifier open loop gain
must be equal to one plus the-gain required to overcome
the losses in the feedback path, across the frequency
band and up to the frequency of operation. This is over full
process, lot, Vcc' and temperature ranges. Therefore,
measuring the open loop gain is not sufficient; the losses
in the feedback path (crystal and load caps) must be
factored in.
Open loop Phase vs. Frequency. Amplifier phase shift at
and near the frequency of interest must be 180 degrees
plus some, minus zero. The parallel configuration allows
for some phase delay in the amplifier. The crystal adjusts
to this by moving Slightly down the reactance curve
(Figure 3).
Internal Bias. Internal to the IC, there is a resistor placed
from output to input of the amplifier. The purpose of this
feedback is to bias the amplifier in its linear region and to
provide the startup transition. Typical values are
1M to 20M ohms.

Amplifier Characteristics
The following text discusses open loop gain vs. frequency,
open loop phase V$. frequency, and internal bias.

691

PRACTICE: CIRCUIT ELEMENT AND LAY OUT CONSIDERATIONS
The discussion now applies prior theory to the practical
application.

Amplifier and Feedback Resistor
The elements of the circuit, internal to the IC, include the
amplifier, feedback resistor, and output resistance. The
amplifier is modeled as a transconductance amplifier with
a gain specified as lourNIN (amps per volt).
Transconductance/Gain. The loop gain AB = gm x Z1,
where gm is amplifier transconductance (gain) in amps/
volt and Z1 is the load seen by the output. AB must be
greater than unity at and about the frequency of operation
to sustain oscillation.

Gain Measurement Circuit. The gain of the amplifier can be
measured using the circuits of Figures 6 & 7. This may be
necessary to verify adequate gain at the frequency of
interest and in determining design margin.
Gain Requirement vs. Temperature, Frequency and Supply Voltage. The gain to start and sustain oscillation
(Figure 8) must comply with;
gm > 41t'! f2 Rq CIN Court x M
where: M is a quartz form factor =(1 + Cour/C IN + Cour/Courf
Output Impedance. The output impedance limits power to
the XTAL and provides small phase shift with load cap C2.

DC Bias
Vb

.-----1 DC Bias 1--.--;

V in

1---,

Vout
lout = (V out - V~ /33)

Figure 7. Transconductance (gm) Measurement

VIN

...----1

VOUT

Quartz
CIN . - - - - ;

Rq, f

COUT

I-

* Inside chip, feedback resistor biases the amplifier in the high gm region.
** External components typically: CIN = COUT = 30 to 50 pf (add 10 pf pin cap).
Figure 8. Quanz Oscillator Configuration

692

Load Capacitors
In the selection of load caps it is understood that parasitics
are always included.
Upper Limits. If the load caps are too large, the oscillator
will not start because the loop gain is too low at the
operating frequency. This is due to the impedance of the
load capacitors. Larger load caps produce a longer startup.
Lower Limits. If the load caps are too small, either the
oscillator will not start (due to inadequate phase shift
around the loop), or it will run at a 3rd, 5th, or 7th overtone
frequency (due to inadequate suppression of higher
overtones).
Capacitor Type and Tolerance. Ceramic caps of ±10%
tolerance should be adequate for most applications.
Ceramic vs. Quartz. Manufacturers of ceramic resonators
generally specify larger load cap values than quartz cry.stals. Quartz C is typically 15 to 30 pf and ceramic
typically 100pf.
Summary. For reliable and fast startup, capacitors should
be as small as possible without resulting in overtone
operation. The selection of these capacitors is critical and
all olthe factors covered in this note should be considered.

Feedback Element
The following text describes the specific parameters of a
typical crystal:
Drive Level. There is no problem at frequencies greater
than 1 MHz and Vee = 5V since high frequency AT cut
crystals are designed for relatively high drive levels
(5-10 mw max).
A typical calculation for the approximate power dissipated
in a crystal is:
P = 2R (x x f x C x Vee'f
Where. R = crystal resistance of 40 ohms, C = C1 + Co =
20 pf. The calculation gives a power dissipation of 2 mW
at 16 MHz.

The external components have a negligible effect (0.5%)
on frequency. The external components (C1 ,C2) and layout are chosen primarily for good startup and reliability
reasons.
Frequency Tolerance (initial temperature and aging). Initial
tolerance is typically ±.01 %. Temperature tolerance is
typically± .005% overthe temp range (-30 to + 100 degrees
C). Aging tolerance is also given, typically
±.OO5%.
Holder. Typical holder part numbers are HC6, 18,
25,33,44.
Shunt Capacitance. (Cs) typically <7 pt.
Mode. Typically the mode (fundamental, 3rd or 5th overtOile) is specified as well as the loading configuration
(series vs. parallel).
The ceramic resonator equivalent circuit is the same as
shown in Figure 4. The values differ from those specified in
the theory section. Note that the ratio of LlC is much lower
than with quartz crystals. This gives a lower Q which allows
a faster startup and looser frequency tolerance (typically
±0.9% over time and temperature) than quartz.

Layout
The following text explains trace layout as it affects the
various stray capacitance parameters (Figure 9).
Traces and Placement. Traces connecting crystal,caps,
and the IC oscillator pins should be as short and wide as
possible (this helps reduce parasitic inductance and resistance). Therefore, the components (caps and crystal)
should be placed as close to the oscillator pins of the IC
as possible.
Grounding/Guarding. The traces from the oscillator pins of
the IC should be guarded from all other traces (clock, Vee'
address/data lines) to reduce crosstalk. This is usually
accomplished by keeping other traces away from the
oscillator circuit and by placing a ground ring around the
traces/components (Figure 9).

Measurement and Opservation
Series Resistance. Lower series resistance gives better
performance but costs more. Higher R results in more
power dissipation and longer startup, but can be compensated by reduced C1 and C2. This value ranges from 200
ohms at 1 MHz down to 15 ohms at 20 MHz.

Connection of a scope to either of the circuit nodes is likely
to affect operation because the scope adds 3-30 pf of
capacitance and 1M-1 OM ohms of resistance to the circuit.

Frequency. The frequency of oscillation in parallel resonant circuits is mostly determined by the crystal (99.5%).

693

PRACTICE: CIRCUIT ELEMENT AND LAY OUT CONSIDERATIONS (continued)

Indications of an Unreliable Design
There are two major indicators whiCh are used in working
designs to determine their reliability over full lot and temperature,variations. They are:
Start Up Time. If start up time is excessive, or varies widely
from unit to unit, there is probably a gain problem. C1/C2
needs to be reduced; the amplifier gain is not adequate at
frequency, or crystal Rs is too large.

Output Level. The signal at the amplifier output should
swing from ground to Vcc' This indicates there is adequate
gain in the amplifier. As the oscillqtor starts up, the. signal
amplitude grows until clipping occurs, at which point, the
loop gain is effectively reduced to unity and constant
oscillation is achieved. A signal of less than 2.5 Vp-p is an
indication that low gain may be a problem. Either C1/C2
should be made smaller or a low R crystal should
be used.

XTAL

c::J

CL'

ZS0180

EXTAL

2
Clock Generator Circuit

30------'

Z80180
SignalsA B
,

(Parallel Traces
Must Be Avoided)
;

I
I
I
I

Board Design Example
(Top View)

Signal C ---;-";:-'--1•

To prevent induced noiea, the crystal and load
capacitors should be physically located as
close to the LSI as possible. ,

•

Signal lines should not run parallel to the clock
oscillator Inputs. In particullar, the clock input
circuitry and the system clock output (pin 64)
should be separated as much as possible.

•

Vee power lines should be separated from the
clock oscillator input cirCUitry.

ZS0180

• 'Resistivity between XTAL or EXTAL and the
other pin should be greater than 10 MO

Figure 9. Circuit Board Design Rules

694

SUMMARY
Understanding the Theory of Operation of OSCillators,
combined with practical applications, should give designers enough information to design reliable oscillator circuits. Proper selection of crystals and load capacitors,

along with good layout practices, results in a cost effective,
trouble free design. Reference the following text for Zilog
products with on-chip oscillators and their general/
specific requirements.

ZILOG PRODUCT USING ON-CHIP OSCILLATORS
Zilog products that have on-chip oscillators:
Z8® Family: All
Z80®:C01,C11,C13,C15,C50,C90, 180, 181,280
Z8000®: 8581
Communications Products: SCCTM, ISCCTM , ESCCTM

ZILOG CHIP PARAMETERS
Z8000 Family (8581 only)

The following are some recommendations on values/parameters of components for use with Zilog on-chip oscillators. These are only recommen'dations; no guarantees are
made by performance of components outside of Zilog ICs.
Finally, the values/parameters chosen depend on the
application. This App Note is meant as a guideline to
making these decisions. Selection of optimal components
is always a function of desired cost/performance tradeoffs.

Crystal cut: AT cut, parallel resonant, fundamental mode.
Crystal Co: < 7 pf for all frequeQcies.
Crystal Rs: < 150 ohms for all frequencies.
Load capacitance: 10 to 33 pf.

Note: All load capacitance specs include stray capacitance.

Z80 Family

Z8 Family

General Requirements:

Crystal cut: AT cut, parallel resonant, fundamental mode.
Crystal Co: < 7 pf for all frequencies.
Crystal Rs: < 60 ohms for all frequencies.
Load capaCitance: 10 to 22 pf.

Crystal Cut: AT cut, parallel resonant, fundamental mode.
Crystal Co: < 7 pf for all frequencies.
Crystal Rs: < 100 ohms for all frequencies.
Load Capacitance: 10 to 22 pf, 15 pf typical.
Specific Requirements:
8604: xtal or ceramic, f = 1 - 8 MHz.
8600/10: f = 8 MHz.
8601/03/11/13: f = 12.5 MHz.
8602: xtal or ceramiC, f = 4 MHz.
8680/81/82/84/91: f = 8,12,16, MHz.
8671: f = 8 MHz.
8612: f = 12, 16 MHz.
86C08/E08: f = 8, 1'2 MHz.
86C09/19: xtal/resonator, f = 8 MHz, C = 47 pf max.
86COO/10/20/30: f = 8, 12, 16 MHz.
86C11/21/91/40/90' f = 12, 16,20 MHz.
86C27/97: f = 4, 8 MHz.
86C12: f = 12, 16 MHz.
Super8 (all): f = 1 - 20 MHz.

General Requirements:

Specific Requirements:
84C01: C1 = 22 pf, C2 = 33 pf (typ); f = DC to 10 MHz.
84C90: DC to 8 MHz.
84C50: same as 84C01.
84C11{13/15: C1 = C2 = 20 -33 pf; f = 6 -10 MHz
80180: f = 12, 16, 20 MHz (Fxtal = 2 x sys. clock).
80280: f = 20 MHz (Fxtal = 2 x Fsysclk).
80181: TBD.

695

ZILOG CHIP PARAMETERS (Continued)

Communications Family
General Requirements:

Specific Requirements:

Crystal cut: AT cut, parallel resonant, fundamental mode.
Crystal Co: < 7 pf for ali' frequencies.
Crystal Rs: < 130 ± 15% ohms for all frequencies.
Load capacitance: 20 to 33 pf.
Frequency: cannot exceed PC!-K.

8530/85C30/SCC: f= 1-6MHz(10MHzSCC), 1-8.5MHz
(8 MHz SCC).
85130tESCC (16/20 MHz), f = 1-16.384 MHz.
16C35/ISCC: f = 1 -10 MHZ.

REFERENCES MATERIALS AND ACKNOWLEDGEMENTS
Intel Corp., Application Note AP-155, "Oscillators for Micro
Zilog, Inc., Steve German; Figures· 4 and 8.
Controllers" , order #230659-001 , by Tom Williamson, Dec.
1986.
.
• Zilog, Inc., Application Note, "Design Considerations Using Quartz Crystals with Zilog Components" - Oct. 1988.
Motorola 68HC11 Reference Manual.
Data Sheets; CTS Corp. Knights Div., Crystal Oscillators.
National Semiconductor Corp., App Notes 326 and 400.

696

ApPLICATION NOTE

~Zilill

INTERFACING THE Z8500
PERIPHERALS TO THE 68000

INTRODUCf ION
This ,application note discusses interfacing
Zilog 's Z8~00 family of peripherals to the 68000
microprocessor.
The Z8~00 peripheral family
includes the Z8~36 Counter/Timer and Parallel I/O
Unit (CIO), the Z8038 FIFO Input/Output Interface
Unit (flO), and the Z8~30 Serial Communications
Controller (SCC).
This document discusses the
Z8~OQ/68000 interfaces and presents hardware examples and verification techniques.
One of the
three hardware examples given in this application
note shows how to implement the Z8~00/68000 inter~
face using a single-chip programmable logic array
(PAL).
'

•

GENERAL Z8500 FAMILY OCSCRIPTIIIN

Z8036 Z-CIO/Z8~36 CIO Technical Manual (document number 00-2091-01)

The Z8~00, family is made up of programmable
peripherals that can interface easily to the bus
of any nonmultiplexed CPU microprocessor, such as
the 68000. The three members of this family, the
CIO, SCC, and flO, can solve many design probThe periphersls' operating modes can be
lems.
programmed simply by writing to their internal
registers.

Z8038 Z-FIO Technical Manual (document number

Progra.ing the Operating Mode&

This application note about interfac~ng supplements the following documents, which discuss the
individual components of the interface.
•

the Z8~00 interface itself. It shows how the different Z8~00 control signals are generated from
the 68000 signals and summariZes the critical timinga for the three types of bus cycle. The third
section shows three examples of implementing the
68000-to-Zilog-peripheral interface.
The fourth
section suggests methods of verifying the interface design by checking the three different types
of bus cycle: Read, Write, and Interrupt Acknowledge.

00-ZO~1-01)

•

Z8030/Z8~30

ber
•

•

SCC Technical Manual (document num-

00-ZO~7-01)

Motorola 16-Bit Microprocessor User's Manual
3rd ed. Englewood Cliffs, N.J., Prentice-Hall,
Inc. 1979.
Monolithic Memories Bipolar LSI 1982 Databook

This application note is divided into four sections. The first section gives a general description of the Z8~00 family and discusaes pin functions, interrupt structures, and the programming
of operating modes. The second section discusses

The CPU can access two types of register: Control
and Data. Depending on the peripheral, registers
are selected with either the AO' A1' A/B, or D/f
function pins.
Peripheral operating modes are initialized by
programming internal registers.
Since these
registers are not directly addressable by the CPU,
a two-step procedure using the Control register is
requirad: first, the address of the internal register is written to the Control register, then the
data is written to the Control register. A state
machine determines whether an address or data ia
being written to the Control register. Reading an
internal regiater follows s similar two-step

697
• __'M__AA"_""''''''__'''''''''''___
'~

-""""',, -,.,..,...,.

''''_~'·_'._~''''''''''''''''~~'

procedure:
first, the address is written, then
the data is read.

be 'connected to the 6BOOo., ~l
lilies.

The Data registers that are fIlls,t frequently
accessed, for example, the SCC's transmit and
receive buffer, can be addressed directly by the
CPU with a single read or write OIleration. This
reduces overhead in data' transfers between the
peripheral' and CPU.

CE.

~nd

AZ Address bus

Each periphera 1 h!l!i' an,' aqti ve /-ow Chip
Enable that can be derived by ANDing the selected
address decode and the 68000's Address Strobe
(AS). The active Low AS guarantees that the 68000
addresses are valid.
00-07.
The ZB~OO Data bus can be directly connected to the lowest byte (00-07) of the 68000
Data bus.

G£t£RATlNG l8500 CONTROl SIGNALS
This section shows how to generate the ZB~OO control signals.
To simplify the discussion, the
section is divided into two parts. The first part
takes each individual ZB~OO signal and shows how
it is generated from the 6BOOO signals.
The
second part discusses the ZB~OO timing that must
be met when generating the control AignalA.

lEI and lEO. The peripherals use these pins to
decide the interrupt priority.
The highest
priority device should have its lEI tied High.
Its 1[0 should be connected to the lEI. pin of the
next highest priority device.
This pattern
continues
with
the
next
highest
priority
peripheral,
until
the peripherals are all
connected, as shown in Figure 1.

l8500 Signal Generation

INT. The interrupt request pins for each periph~
eral in the daisy chain can be wire-ORed and connected to the 68000'i. IU'n pins.
The 68000 has
seven interrupt levels that can be encoded into
the ILPO' ILP1' and ILP 2 pins.
Multiple 68000
ilJterrupt leve Is can be implemented by using a
multiplexer like the 74LS148.

The right-hand side of Table 1 lists the ZB~OO
Aignals that must be generated.
Each 0 f these
signals is discussed in a separate p~ragraph.

An. A1' ~. DIC. These pins are used to select
the peripheral's Control and Data regif.ters that
program the different operating modes.
lIiey can
Table 1.

l8500 ani! 68000 Pin Fmctions

l8500 Signals

68000 Signals

MneaJnic
A1-AZ3

CLK
DO-Dl~

lmiEK
FCO-FC2
ILPO-ILP2
R/W

\iRA
VPA

Fmction

Fooction
Address bus
Address Strobe
68000 clock (8 MHz)
Data bus
Data Transfer Acknowledge
Processor status
Interrupt request
Read/Write
Valid Memory Address
Valid Peripheral Address

AO,A1,A/!!,0/C*
C£

00-07
lEI ,lEO

IFf
IN TACK
PCLK
RD
WR

Register select
Chip Enable
Data bus
Interrupt daisy chain
control
Interrupt Request
Interrupt Acknowledge
Peripheral Ctock
Read strobe
Write strobe

* The register select pins on each peripheral have different names.

698

INTACK.
The INTACK pin signa Ifl the peripheral
that an Interrupt Acknowledge cycle is occurring.
The follOWing equation deflcribes how INfACK - is
generated:

The Read strobe timing must meet both the Read
timing and Interrupt Acknowledge timing diRcussed
in the following section. In addition to enabling
the Data bus drivers, the falling edge of RD sets
the Interrupt Under Service (IUS) bits during an
Interrupt Acknowledge cycle.

The 68000 fCO-fC2 are status pins that indicate an
Interrupt Acknowledge when they are all High.
They should be ANDed with inverted AS to guarantee
their validity.
The INIACK signal must be synchronized with PClK to guarantee set-up and ho Id
times. This can be accomp Hshed by changing the
state of INTACK on the fa lUng edge of I'ClK.
If
the INTACK pin iq not used, it must be tied High.

WH. This signal fltrobes data into the peripheral.
A data-to-write setup time requires that
data be va I id before WR goes acU ve low.
The
equation for generating the WR st robe is made up
of two compo'1ents: an act.ive reset and a normal
Write cycle, as shown in the following equation:

POLK.
fhe SCC and CIO require a clock for
internal synchronization.'
The clock can be
generated by dividing down the 6BOOO ClK.

forCing R5 and WR simultaneously low resets the
periphera Is.

WR = [(R/W)o{AS) + RESEr]

Z8500 TDoing Cycles

RD.

The Read strobe goes active low under three
conditions:
hardware reset, normal Read cycle,
and an Interrupt Acknowledge cycle. The following
equation describes how R5 is generated:

RD = [(R/W)"{AS)

+ RESEf]

This sect ion discusses the timing parameters that
must be met when generating the control signals.
The ZBSOO family uses the control signals to
communicate with the CPU via three types of bus
cycle:
Read, Write, and Interrupt Acknowledge.

+5V

I-------I'E~

lEO

lEi

lEO 1 - - - - - - 1 lEI

Z8500

Z8100

(FIRST)

(MIDDLE)

PERIPHERAL

(LASl)

LOWEST
PRIORITY
PERIPHERAl

HIGHEST
PRIORITY

PCLK

lEO

z••oo

__________________________--Jr--,'-____r--1s_(NS)
PERIPHERAL
(4MHz)

ARST

ClO
FlO

...
360

sec

Figure 1.

2267-001

...

MIDDLE
'50
'50
'20

LAST

'00
'00
'20

Peripheral Interrupt Daisy Olain

699

The discussion that follows pertains t.o the 4 MHz
peripherals, but the 6 MHz devices have simi lar
timing con!'lidprations.
Although the peripherals have a standard CPU
interface, some of their particular / timing
requirements vary. The worst-case parameters are
shown below; the timing can be optimized if only
one or two of the lBSOO family devices are used.
Read

Write Cycle
The Write cycle transfers data from the CPU to the
peripheral. It begins by selecting the. peripheral
and addressing the desired register. A setup timl~
of BO ns from regiflter select stahle to the
fa llillg edge of WR is required. The data must be
valld prior to the falling edge of Wll.
The WR
pulse width is specified at 400 ns. Write cycle
timing ifl shown in Figure 2.

C~le

Interrupt Acknowledge Cycle
The Read cycle transfers data from· the peripheral
to the I;PIJ. It begins by selecting the peripheral
and appropriate register (Data or Control). The
data is gated onto the bus with the .RD line.
A
setup time of BO ns from the time the register
select inputs (AlB, C/O, AO' A1) are stable to the
falling edge of RD guarantees that the proper register is accessed. The access time specification
is usually measured from the falling edge of RO to
valid data and varies between. peripherals.
The
SCC specifies an additional register select to
va lid data time. The Read cycle timing is shown
in Figure 2 •.

The lB,)OO peripheral interrupt atructure offers
the designer :nany options. In the simplest case,
the Z8,00 peripherals can be po \led with interrupts dil~abled.
If using int.errupts, the timing
shown in· Figure 2 should be observed. (Detailed
discussions of the interrupt processing can be
found in the Zilog Data Book, document number
00-2034-02.) An interrupt sequence begins with an
INT going active because of an interrupt condition. The CPU acknowledges the interrupt with an
I'll TACK signal.

ADA

ReAD
CYCLE

WRIT. {

CYCLI!

DATA IN

"""--_-+-_ _ _~I

INTERRUPT
ACKNOWLEDGE
CYCLI!

DATA IN

Figure 2.

700

Z8500 Interface lUling (4 lliz)

2267-002

A daisy-chain settle time (dependent upon the number 0 f devices in the chain) ensures that the
interrupts are prioritized. The falling edge of
iffi causes the IUS bit to be set and enables a
vector to go out on the bus.

lil~g's 4 MHz 18S00 peripherals to on 8 MHz
68000. faster CPUS or peripherals can be used by
These examples
modifying aome of the timing.
suggest possible ways of implementing the interface but may require some modifications to operate
properly. They were chosen because they give the
URer a variety of interface deaign ideas.
The
first examp Ie uses a minimum amount of TTL logic
'to implement the interface because the Valid
Peripheral Address (VPA) cycle meets the l8500
timing requirements.
In this mode the 68000
accepts only nonvectored interrupts.
The second
example uses the Data Transfer Acknowledge (DTACK)
pin. This interface allows faster operation and
makes
use
of
the 18500's' 8-bit vectored
interrupts. The third example also uses a DIACK
cycle and is similar to the second, except the
external logic is integrated into a Ring Ie chip,
the PALZOX10 programmable array logic.

The tab Ie gi ven in Figure 1 can be. used to ca lculate the amount of sett ling time required by a
daisy chain. Even if there is only one peripheral
in the chain, a minimum settling time is still
required bec~use of the internal daisy chain. The
first column specifies the amount of settling time
fOf only one peripheral. If there are two peripherals, the time is computed by adding together the
times shown in the firat and the laat columns.
For each additional peripheral in the chain, the
time specified in the middle COIU~1 is added.
Recovery TDe
The read/write recovery time specifies a minimum
amount of time between Read or Write cycles to the
same peripheral. The recovery time differs among
peripherals and is summarized in figure J.
In
most cases, this parameter is met because of the
time required for instruction fetches. The recovery time specificstion does not have to be met if
C[ Lq deselected when Read or Write occurs.

EXAMPlE 1:

The 68000 has a special input pin, Valid
Peripheral Address (VPA). that can be activated by
the 18S00 chip se lect logic at the beginning of
the cycle to indicate to the 68000 that a peripheral is being accessed. This generates a special
Read/Write cycle that meets the peripheral timing
requirements. This cycle allows the l8500 control
signals to be generated easily.
The 68000
responds to interrupts using an autovector and the
l8500 can be programmed not to return a vector.

68000 INTERfACE EXMI'lES

This section shows three examples, presented in
increasing order of complexity, for interfacing

iiiilWR

A TTL Interf_ Using a VPA Cycle

FlO

sec
NOTE. The dlagnlm showS tMt the recovery time I, .....IUNd between
and wrHet only It the peripheral I. . .Iacted

Recovery Time

Peripheral
(' MIbj
CfO

......... /

Ore..... than 3 peLK cyct.. Of 1DOOns

_than1_
G""""' .... 4P01.K . . . . coRsecutlve re_

Figure ,.

Recovery TDe

'701

F:igure 4 shows how the hardware can be imple-'
mented.
PClK is generated by 01 victing down the
68000, ClK.
RO, WR, and lr>!TACK are simply ANDed
68000 signals. The worst-case daisy-chain settle
time is 4S0 ns. Connecting lNT to IPL O generates

a level 1 interrupt. The internal regis'ters are
accessed by AO' A1' O/C, and A~, which can be the
68000 lowest order addresses. The tiniing is shown
in Figure 5.

VPA
FCo
Fe,
Fe,

...'"
An-An
8.000

-"
....

r--

r "'

of--

----

•

L.r"\,

Cl!

Ao-Dle
A1-AlB

-I Jo---

_to..

....

2:8500
Peripheral

U
L

IP,",

liD

elK

IPL,

...'"

R/W

WI!

r--

Qr--

PCLK

elK

~~
!liT

IPLo'

figure 4.

Interrace Using the VPA Cycle

eLK

________________________________ __________ _________________________ __________
~

~r---

I~·------------>~--------------·II;·==========>~~========~·I

.~~--------------------~I
\~

figure S.

702

_______________________
\~ ________________~r---

VPA Cyde Tilling

~r---

Functional Description
VPA is pulled Low at the beginning of the cyc Ie
and the CPU automat ically inserts Wait states
unti 1 E is synchronized,
VPA

= [(AS)'(CE)]

= [(CE)'(VMA)'(R/W)]

INTACK

ExAMPLE

EXAIoPLE J:

= [(rCO)'(rC1)'(rC2)'(AS)]
Z:

register (74LS164) is used to generate the proper
timing,
At the beginning of each cycle, QA
(Figure 7) is set High for one PCLK cyc Ie and then
reset,
This pulse is shifted through the
QA-QH outputs and if! used to generate RD, WR,
and DIACK signals, Some of the extra Wail states
can be eliminat.ed by tapping the Shift register
sooner (e,g" QC)'

A TTL Interface Using DTACK Cycles

Usihg the 68000 Data Transfer Acknowledge (DIACK)
cycle is a second way of interfacing to the l8500
peripherals. The 68000 inserts Wait states until
the DTACK input is strobed Low to complete the
transfer.
In addition to qenerating the control
signa Is, the interface logic must also generate
DTACK.
The timi~g shown in Fiqure 6 can be generated by
the hardware shown in Figure 7.
fhe 8-bit Shift

Single-Chip Pal Interface

This example illustrates how to interface the 4
MHz Z8500 peripherals to the B MHz 68000 using a
PAL20Xl0 device to generate all the required control >ligna1". The PAL reduces the required interface logic to a >lingle chip, thu>l minil1)izing board
space. Thi>l interface offers flexibility because
the interna 1 logic can be reprogrammed without
changing the pin functions,
The PAL uses 68000
signals to generate Read, Write, and Interrupt
,Acknowledge cycles. In addition to generating the
l8500 control signals, the PAL also generates a
DTACK to inform the 68000 of a completed data
transfer cycle. This allows the 68pOO to use the
peripheral's vectored interrupts.

eLK

PCLK

L-

rr-

ii'iiIWR

l>fiCI{

I"TACK

\
Figure 6.

Tilling for DTACK Interface

703

+5V

vp~W·
RJW
A"
An
A"
AlO

}o-

08000

-•
-

R
ILP,

........

B
elK

...

111

:---

....E;L'l

Z8600
PERIPHERAL

ON'

+5V

tr~v

FC,

Wl!

01-74LS74

PCLK

INT

tLPo

FC,

::0-

•

-<> elR

.....

1fI!

r---

00
74LS184 0,
Q,

.....

0.
Oe

74LS74

elR

1LP2

(lA

elR

vee

ll- A

A"
A"

elK

74 •• 7.

=L.Jo--

---t

-•

FC,

0
74LS74

DTACK

Do-07

Figure 7.

IN'fACj(

r-- 0,-"

Hardware Oiagra. for OTACK Interface

Functional Description
Figure 8 shows the PAL's pin functions.
The PAL
generates five control s~gnals, of which four (WR,
RD, CO, and INT_ACK) go to the l8500 and one
(DTACK) goes to the 68000. The remaining signals
are used internally to generate these outputs.

ClK
C§"

NC
TEST

R
RIW

FC,
FC,
FCO

The PAL uses a 4-bit dowllcounter to generate the
proper placement of the control signals where Co
is the least-significant bit and C3 is the

Vee

=
WI!
1fI!

iffA'CK
!Ie
1:Yl:

a>
l;1

RESET

GN'

Figure 8.

704

Timing diagrams for the Read, Write, and Interrupt
Acknowledge cycles are shown in Figure 9.

PAl Pinout

most-significant bit.
All of the PAL is clocked
with the rising edge of the 68000'''' ClK.
The
counter toggles between counts 14 and, 15 and
starts counting down when AS goes active.
The
counter goes back to toggling when' AS goes

inacti ve.
Cye goes active low at the same time
the cOllnter starts counting down.
The equations
in Figure 10 can be entered into a development
board to program the PAL.

CLK

All

co
c,
c.
C3

DTACK

liD

DTACK
INTERRUPT
ACKNOWLEDGE
CYCLE

INTACK

liD

705

PAL20X10
P7089 (10)
MC68000 TO ZILOG PERIPHERAL INTERFACE
MMI, SUNNYVALE, CA
CLK /CS NC TESI /AS RW
FC2 FC1 FCO /RESET NC GNO
JOE /C3 /C2 /C1 /CO /CYC
NC /DTK /RD /WR /ACK VCC

CO
Cl

..:+:

.:+:

DTK

CYC

:+:

.+
:+:
+

.+
:+:

ACK

PAL DESIGN SPECIFICATION

/CO*/TEsr

COUNT/HOLD (LS8)

/RES[J*AS*Cl
/RESET*AS*CO

HOLD
DECREMENT

/RESET*AS*C2
/REsn*AS*CO*Cl

HOLD
DECREMENT

/RESET*AS*C3
/RESET*AS*CO*Cl*C2

HOLD
DECREMENT

/RESET*/ACK*CYC*C3*/C2*/Cl* CO*CS
/RESET* ACK*CYC*C3*/C2* Cl*/CO

DTACK FOR RD/WR .CYCLE
DTACK FOR INTERRUPT
OPERATION

/RESET*AS*/CYC*CO
/RESET*AS* CYC
/RESET*CYC*DTK

NEW CYCLE STARTED
PROCESSING OF CYCLE
nil OF CYCLE

/RESET*CYC*/ACK*RW* C3*/C2*CS
/RESET*CYC*/ACK*RW*/C3*C2*Cl*CO*CS
/RESEI*CYC* ACK*RW* C3
RESET

NORMAL READ OPERATION
NORMAL READ OPERATION
READ DURING OPERA lION

/RESET*CYC*/ACK*/RW* C3*/C2*CS
/RESET*CYC*/ACK*/RW*/C3* C2*Cl*CO*CS
RESET

WRITE
WRITE

/RESET*FCO*F~1*FC2*AS*

/RESET*FCO*FC1*FC2*CYC

INTERRUPT ACKNOWLEDGE
INTERRUPT ACKNOWLEDGE

CYC*/CO

Figure 10. PAl Equatioos

Hardware Diagraa

The hardware diagram of the PAL ipterface is sho,",n
in Figure 11. The 68000 signals CLK, CS, ~, R/W,
rcO' FC 1, and FC2 are uRed to generate the Z8500
control signals.
The control signals are synchronous with the rising edge of the 68000's CLK.
TES T and OI must be grounded.
CS iA used to

706

enable Dl ACK, RD, and WR as shown in the equations. The Z8500 INT is connected to ILPO' which
geTleratef3 a 68000 leve 1 1 interrupt. The per ipherals are memory-mapped into the highest 64K byte
block of memory, wlwre .A17-A23 equa Is "FF H".
Addresses A4-A6 afe uRed to select the peripheral;
A, -A 3 se lect the interna 1 registers.
Tab Ie 2
shows the peripheral's me!nory map.

+5V
VPA

A1S-A23

r+QV

As 34
As 33
...

,.vee

+5V

r-r-;c·.,
4

.2A

YO 15

.2.
e

Y2 13

B 74138

GND

•-=-

A'h
A,

08000

DTACK

elK

DTACK

elK

:co
~
5
XW· •

RJW9

FCo

Fe,

28
27

Fe,

ViR

RJW

FCo

Fe,

vee

e" ~

• AS 2::~O Ro
8

+5V

2. +5V

OE~

Do-D,
1LPo
ILP,

pelK

Alii

}SE:IAl
PORTS

lEI

GND

•

+5V

~
~

[,'NTACK 25

I~
Do-Dr
lIlT

~ DI~

TEST

I'INTACK 8 INTACK

+5V _,_a RESET

Z8530

lEO

elo

fi1j

Z8131

PORTS

PIO
Z803.

+5V
.~
• 2

~ DIe

pelK

171

~ CE
~ Ill)
~ WR

,~ TATlI'eK

INTACK

Do-Dr
lIlT

lEI

}~RT2

vee
} 3 PARAllEL

GND

lEO

181

+sv---1!

Do-D,

lIlT

lEI

GND lEO

Tori

TO
NEXT
PERIPHERAL

~+5V

ILP2

r igure 11. PAl Hardware Diagraa

~ A,

31r I
GND

+5V
40

vee

sec

fi1j

~ WR

liI'IEK ~

Fe,

+5V
23

Table 2.
Peripheral

Peripheral Memory Map
Regbter

Hex Address

SCC (Z8530)
Channel
Channel
Channel
Channel

B Control
B Data
A Control
B Data

FF0020
FF0022
FF0024
FF0026

CIO (Z8536)

FlO

Port C's Data Register
Port B's Data Register
Port A's Data Register
Control Register

FF0010
FFOO12
FF0014
FFOO16

Data Regif'ters
Control Registers

FFOOOO
rFOOO2

~Z8038)

INTERfACE VERIFICATION TECHNIQUES
This section suggests possible ways of verifying
the Read, Write, and Interrupt Acknowledge cycles.
Read Cycle Verification
The Read cycle should be checked first because it
is the simplest operation.
The Z8500 should be
hardware reset by simultaneously pulling RD and WR
low. When the peripheral is in the reset state,
the Control register containing the reset bit can
be read without writing the pointer. Reading back
the FlO or CIO Control register should, yield a

Interrupt Acknowledge Cycle Verification
Verifying an Interrupt Acknowledge (INTACK) cycle
consists of several ~teps. First, the peripheral
makes an Interrupt Request (INT) to the CPU. When
the processor is ready to service the interrupt,
it initiateS an Interrupt Acknow-Jedge (INTACK)
cyc Ie. The peripheral then puls an 8-bit vector
on the bus, and the 68000 uses that vector to, get
to the correct service routine. This test checks
the simplest case.
First, load the Interrupt Vector register with a
vector, disable the Vector Includes Status (VIS),
and enab Ie interrupts (IE = 1, MIE = 1, lEI = 1).
Disabling VIS guarantees that only one vector is
put on the bijs. The address of the service rOutine corresponding to the 8-bit vector number must
be loaded into the 68000's vector table.
Initiating an interrupt sequence in the F [Q and
CIO can be accomplished by setting one of the
interrupt pending (rip) bits and seeing i f the
68000 jumps to the service routine (setting a
breakpoint at the beginning of the service routine
is an easy way to check if this has happened).
Initiating an interrupt sequence in the sec is not
quite as simp Ie because the IP bits are not as
accessible to the user.
An interrupt can be
generated indirect I y via the CT S pin by enab ling
the following:
CTS [E (WR15 20), EXT INT EN
(WR1 01), and MIt: (WR9 08). Any transition on the
CTS pin can initiate the interrupt sequence. The
interrupt can be re-enabled by RESET EXT /S TAT US
IN r (WRO 10) and RESET HIGHEST IUS (WRO 38).

01H'
The SCC' s Read cyc Ie can be verified by read ing
the bits in RRO. Bits D2 and D6 are set to 1 and
bits DO' D1' and D7 are O. Bits D3-D5 reflect the
input pins DCD, SYNC, and CTS, respectively.
Write Cycle Verification
The Write cycle can be checked by writing to a
register and reading back the results. Both the
eIO and FIO must have their reset bits cleared by
writing DOH to their Control registers and
reading back the result.
The SCC can be checked
by writing and reading to an arbitrary read/~rite
register, for example, the Time Constant register
(WR12 or WR13).

708

CONCLUSION
liloq's
Z8500
family
of
nOllmultiplexed
Address/Data bus peripherals can interface easily
with the 68000 and prov ide a 11 the s,!pport
required in a high-performance microprocessor system. lhe many features offered by the SCC, FlO,
and CIO solve many system design problems by making interfacing to the external world easy. These
intelligent periphera Is also great ly enhance the
system performance by relieving the CPU of many
burdensome overhead tasks.
Additionally, the
powerful illterrupt 'structure allows the 68000 to
use vectors and reduce interrupt response time.

~ZiJffi

ApPLICATION NOTE

INTERFACING Z80
CPUS TO THE Z8500
PERIPHERAL FAMILY

INTRmUCTIIJI

Data Bus Signala

The Z8500 Family consists of un1versal peripherals
that can 1nterface to a variety of mIcroprocessor
systems thst use a non-multiplexed address and
data bus. Though SImIlar to Z80 per1pherals, the
Z8500 perIpherals dIffer 1n the way they respond
to I/O and Interrupt ACKnowledge cycles.
In
addItIon, the advanced features of the Z8500
peripherals enhance system performance and reduce
processor overhead.

07-00

Syatt. Cootrol Signals
An-Ao

To deSIgn an effectIve Interface, the user needs
an understandIng of how the zao Fam1ly Interrupt
structure works, and how the Z8500 peripherals
1nteract with this' structure.
ThIS application
note prov1des basic informstIon on the l,nterrupt
structures, as well, as a discussion of the
hardware and softwsre consIderatIons Involved 1n
InterfaCIng the Z8500 per1pherals to the Z80
CPUS.
DIscussions center around each of the
follOWIng situations:
•
•
•
•

Z80A 4
Z80B 6
Z80H a
Z80H, 8

MHz
MHz
MHz
MHz

CPU
CPU
CPU
CPU

to
to
to
to

Z8500 4 MHz per1pherals
Z8500A 6 MHz peripherals
Z8500 4 MHz per1pherals
Z8500A 6 MHz peripherals

ThlS applicatIon note assumes the reader has a
strong worklng knowledge of the ZB500 per1pherals;
It is not Intended as a tutorial.

Address Select Lines (optional).
lines select the port and/or
registers.

These
control

Ch1P Ensble (input; active Low). '~ is
used to select the proper peripheral for
programmIng. ~ ahould be gated with ~
or 'RR'£lJ to prevent spurious chip aelects
durIng other machine cycles.
Read (input, active Low). 1m activates the
circuitry and gates data from the
chip onto the data bus.
chip-r~ad

iR*

Write (Input, aCtive Low). WR" strobes data
from the data bus into the peripheral.

*Chip reset occura when 1m IIfId WR" are active
aimultaneously.

Interrupt Control
~

CPU HARDWARE INTERfACIt«;
The hardware inte,rface cons1sts of three bas1c
groups of signals: data bus, system control, and
Interrupt control, deSCrIbed below.
For more
detailed signal information, refer to Zilog's
Data Book, Universal Per'lpherals.

Data Bus (bIdirectional, 3-state).
This
bus transfers data between the CPU and the
perIpherals.

Interrupt Acknowledge (input, active Low).
This
s1gnal
indIcates
an
Interrupt
Acknowledge cycle and 1S used with 1m' to
gate the interrupt vector onto the data
bus.
Interrupt Request
active Low).

(output,

open-draln,

709

ADDA

ADDRESS VALID

------'. "._-----------...;.------------":"''''':''--',,,---''.....'--

;\"--f

\ ______f
D:~~ ----------------------1(~____________D_A_TA__VA_L_ID____________~)~----------figure 2.

Z8500 Peripheral

The IUS bit ind1cates that an interrupt 1S
currently being serviced by the CPU. The IUS bit
is set' during an Interrupt Acknowledge cycle 1 f
t.he IP bit is set and the lEI line is High.
If
the lEI line is Low, the lUS bit is not set, and
the device is inh1bited from plsc1ng it!! vector
onto the dsta bua.
In the ZBO peripherals, the
IUS bit is normally cleared by decoding the RETI
instruct~on~ but can alsQ be ~leared by a software
commsnd (510). In the ZB500 peripherals, the IUS
b1t is cleared only by softwsre commands.

zoo

Interrupt Daisy-Chain Operation

In the ZBO peripherals, both the IP and lUS bits
control the lEO line and t.he lower portion of the
daisy chain.
When a peripheral's IP b1t is set, 1ts lEO line is
forced Low. This is tru~ regardless of the stat.e
of the lEI line. 'Additionally, 1 f t.he peripheral's lUS bit is clear and its lEi line High, the
TIlT line is also forced Low.
The Z80 peripherals sample for, both m; and TI!RQ"
active, and 1l!l inact ive to identi fy an Interrupt
Acknowledge cycle. When m; goes active and ~ is
inactive, 'the peripheral detects an Interrupt
Acknowledge cycle and allows its interrupt daisy
cha1n to settle. When the TI!RQ" 11ne goes active
wHh m; ~ctive, the highest' priority 1nterrupt.ing
peripheral places its interrupt vector onto the
data bus.
The lUS bit is also set to indicate
that the penpheral is currently under ser:vice.
As long as the lUS bit is set, the lEO hne is
forced Low.
This inhibits any lower priorit.y
devices from requesting an interrupt.

710

I/o Write Cycle Tilling

When the ZBO CPU executes the RET! instruction,
the periphersls moritor the data bus and the h1ghest prionty device under service resets 1tS lUS
bit.

Z8500 Int~rrupt Daisy-Chain Operation
In the Z8500 peppherals, the lUS blt normslly
controls the stale of the lEO hne. The IP b1t
affects the daISY cha1n only durmg an Interrupt
Acknowledge cycle. S1nce the IP b1t is normally
not part of the ZB500 perrpheral lnterru~t da1sy
chal 11 , the~e 1S ro need to decode the RE fl 1nstructlOn.
To allow for control over the dalsy
chaJn, ZB500 peripherals have a Dlsable Lower
Chaln (DLC) software command that ~ulls lEO Low.
Thls qm be used to se.lectlvely deactlvate parts
of the dalsy chaln regardless of the lnterrupt
status.
Table 1 shows' the truth tabl~s for the
ZB500 lnterrupt daisy-cha1n control slgnals during
certaln cycles. Table 2 shows the lnterrupt state
dlagram for the Z8500 peripherals.

T~le 1. Z8500 Daisy-Chain Control SlgnalS
Truth Table for
Daisy Chain Signals
During Idle State
lEI IP IUS lEO

X
X

Truth Table for
Daisy Chain Slgna19
During iNiACK Cycle
lEI

IUS

lEO

lEI

Interrupt Enable In (lnput, actlve Hlgh).

Write Cycle Tilling

lEO

Interrupt
High) •

Flgure 2 lllustrates the ZB500 Wute cycle
tlmlng.
All reglSter addresses and ~ must
If rr goes
remaln stable throughout the cycle.
active after W goes active, or lf rr goes inact1Ve before W goes wactive, then t.he effectlve
Wrlte cycle lS shortened. Data must be available
to t.he peupheral pnor to the fall1ng edge of W.

Enable

Out

(output,

actlve

These I1nes, control the interrupt d81sy
chaln
for
the
peripheral
lnterrupt
response.

Z850D I/O OPERATION

PERIPHERAL INTERRUPT OPERATION

The Z8500 penpherals generate internal control
signals from ~ snd W.
Slncel PCLK has no
requued phase. relabonship to 1m" or W, the
circultry generabng these slgnals provides bme
for metastable conditions to disappear.

Underst.anding
peupheral
interrupt
operation
requlres a basic knowledge of the Interrupt
Pendlng (Ip) and Interrupt Under Service (IUS)
bltS in relation to the daisy chain. Both ZBO and
ZB500 peripherals are designed in such a way that
no addlt10nal interrupts can be requested during
an Interrupt Acknowledge cycle.
This allows theinterrupt. daisy chain to settle, and ensures
proper response of the interrupting device.

The ZB500 peupherals are ln1tiahzed for dlfferent operabng modes by programming the lnternal
registers. These lnternal reglsters are accessed
during 1/0 Read and Write cycles, WhlCh are
described below.

The IP bit is set in the peripheral when CPU
lntervention is required (such condittpns as
buffer empty, character available, error detection, or status changes).
The, Interrupt Acknowledge cycle does not necessarily reset the IP
bit. This bit is cleared by a software command to
the pedpheral, or when the action that generat.ed
the interrupt 1S completed (i.e., reading a
character, writing data, resett1ng errors, or
changing the status). When the interrupt has been
serviced, other interrupts can occur.

Read Cycle Tilling

Figure 1 111ustrates the ZB500 Read cycle timlng.
All reglster addresses and ~ must remaln
stable th-coughout the cycle.
If rr goes act.1ve
after ~ goes active, or lf rr goes lnactlve
before ~ goes wact1Ve, then the effective Read
cycle lS shortened.

AD DR ________J)(~

_____________________

A_DD_R_E_S_S_V_AL_I_D________________

~)(~________

\_---/

R D \_________/
D~:A

________________________________________~(~___D_A_T_A_V_A_LI_D___)~--------------

Figure 1.

Z8500 Peripheral I/o Read Cycle Tillling

711

Tllble Z.

Z8500 Interrupt State Diagr_

Interrupt, Cond:s,hon

Interface.
Flgures 4 and 7 deplct some of the
logIC used to lnterface the ZaOH CPU to the Z8500
and Za500A perIpherals for the I/O and Interrupt
Acknowledge interfaces.
The logic required fdr
adding addItional Wait states into the timing flow
is not discussed In, the folowing sections.

lEI HIgh?
Z8DA CPU to Z8500 Peripherals

<------>
INT ACK

lEI

Walt for CPU INTACK Cycle

* RD

CPU Read, WrIte, or Reset IP

lEO HIgh?

Return to maIn program,

The Z8500 perIpherals use INTACK (Interrupt
Acknowledge) for recognItIon of an Interrupt
Acknowl!,dge cycle. [hIS pIn, used In conjunctlOn
WIth RD, allows the Z8500 perIpheral to gate Its
Interrupt vector onto the data bus. An actlve R5
sIgnal durIng an Interrupt Acknowledge cycle
,performs two functlons.
Fust, It allows the
hIghest prIorIty device requesting an Interrupt to
place ItS Interrupt' vector on the data bus.
Secondly, It sets the IUS blt In the hIghest
pnorIty devIce to lIldlcate that the device lS
currently under serVIce.

INPUT/OOTPUT CYCLES

Although Z8500 perIpherals are desIgned to be as
unlversal as posslble, certain timlng parameters
dl ffer from the standsrd Z80 tlmlng.
The
followlng sect lons dlSCUSS the I/O lnterface for
each of t.he Z80 CPUs and the Z8500 per ipherals.
Flgure 5 deplcts 10glC for the Z80A CPU to ZB500
penpherals (and zaoe CPU to Za500A perIpherals)
I/O lnterface as well as the Interrupt Acknowledge

712

No additional Wait st,ates are necesssry during .the
I/O cycles, ~lthough additional Wait states can be
inserted to compensate for timing delays that are
inherent, in a system.
Although the ZaOA timing
parameters indicate a negative value for data
valid pr ior to WR', this is a worse than "worst
case" value.
This parameter is based upon the
longest (worst case) delay for data available from
the, falling edge of t.he CPU clock minus the
shortest (best case) delay for CPU clock High to
WR' Low. The negative value resulting from these
two parameters does not occur because the worst
case of one parameter and the best case of the
other do not occur wlthlll the same device. This
indicates that the value for data available prior
to WR' will always be greater than zero.
All setup and pulse widt,h times for the Z8500
peripherala are met by the standard ZaOA timing.
In 'determining the interface necessary, the 'CE'
signal to the Z8500 peripheralS is assumed to be
the decoded addreas qualified with the 1TImr
signal.
Figure 3a shows the minimum Z80A CPU to Z8500
peripheral interface timing for 1/0 cycles.
If
additional Wait st,ates are needed, the same number
of Wait 'states can be inserted for both I/O Read
and Write cycles to simplify interface logic.
There are several ways to place the Z80A CPU into
a Wait condition (such as counters or shift
registers to count system clock pulses), depending
upon whether or not the user wants to place Wait
states in all I/O cycles, or only during Z8500 I/O
cycles. Tables 3 and 4 liat the Z8500 peripheral
and the Z80A CPU timing parameters (respectively)
of concern during the I/O cycles. Tables 5 and 6
list the equations used In determining if these
parameters are satisfied.
In generating these
equations and the values obtained from them, the
required number of Wait st ates was taken into
account. The reference numbers in Tables 3 and 4
refer to the timing diagram In Figure 3a.

Table 1. Z8500 Tilling Par-':era I/O' Cyclea
Worst C-

Min
6.
1.
2.

4.
8.
1.

Address to iiii Low Setup
Address to RO Low Setup
Address to Read Data Vslid
CE Low to WR Low Setup
CE Low to RO Low Setup
RO Low Width
Wii Low Width
AD Low t~ Read Data Valid
Write Data to WR Low Setup

TsA(WR)
TaA(RD)
TdA(DR)
" TsCEl(WR)
TaCEl(RD)
TwRDI
TwWRI
TdRDf(DR)
TsDW(WR)

Table 4..

Max

80
80

!)Uta
na
ns

590
0
0
390
390

na
ns
rlS

255
0

ns
ns
ns
liS

Z80A Tilling Par-':ers I/O Cycles

Worst CMin

TcC
TwCh
rrc
rdCr(A)
TdCr(RDf)
TdCr (IORQf)
TdCr(WRf)
TsD(Cf)

Clock Cycle Period
Clock Cycle High Width
Clock Cycle raIl Time
Clock High to Address Valid
Clock High to RD Low
Clock High to IORQ Low
Clock High to WR Low
Data to Clock Low Setup

Max

250
110

!)Uta
liS

ns
30
110
85
75
65

liS

ns
liS

ns
ns

(

Table 5. Psr-':er Equations
Z8500
Psr~er

Z80A

Equatioo

TsA(RD)
TdA(DR)
TdRDf(DR)
TwRDI
TsA(WR)
TsDW(WR)
TwWRI

Value

TcC-TdCr(A)
3TcC+TwCh-TdCr(A)-TsD(Cf)
2TcC+TwCh-TsD(Cf)
2TcC+TwCh+TFC-TdCr(ROf)
TcC-TdCr(A)
2TcC+TwCh+TfC-TdCr(WRf)

Table 6.

Z80A
Psr.ater
TsD(Cf)

Par~er

140
800
460
525
140
>0
560

min
min
mjn
min
min
min
min

(kIita

ns
ns
liS

ns
liS

ns
ns

Equations

Z8500
Equatioo

Value

Address
3TcC+TwCh-TdCr(A)-TdA(DR)

!)Uta

160 min

135 min

RO
2rcC+TwCh-TdCr(RDf)-TdRD(DR)

713

CLOCK

ADDR

CPU
DATA IN

CPU
DATA OUT

figure Ja.

VALID DATA

Z80A CPU to Z8500 Peripheral Minima I/O Cycle TDii,.g

Z80B CPU to Z8500A Peripherals
No additional Wait states are necessary during I/O
cycles, although Wait states can be inserted to
cpmpensate for /lny system de lays.
Al tHough the
ZaOB timing parameters indicate a negative value
for data valid prior to WI!", this is a worse than
"worst case" value. This parameter is based upon
the longest (worst case) delay for data available
from the fall ing edge of the CPU c lock minus the
shortest (best case) delay for CPU clock High to
WI!" Low. The negative value resulting from these

714

two parameters does ,not occur because the worst
case of OIie parameter and the best case of the
other do not occur within the same device. ThlS
indicat.es that the value for dat.a available prior
to WI!" will always be greater than zero.
All setup and pulse width times' for the Z8500A
peripherals are met by the standard ZBOB timing.
In det.ermining the interface necessary, the
signal to the ZB500A peripherals is assumed to be
the decoded address qualified with the ~
signal.

Figure 3b shows the minimum ZBOB CPU to Z8500A
peripheral interface timing for I/O cycles.
If
addltional Wait stat.es are needed, the same number
of Wait states can be inserted for both 1/0 Read
and 1/0 Write cyc les in order to simpli fy interfac!" logic. There are several ways to place the
l80B CPU int.o a Wait condition (such as counters
or shlft registers to count system clock pulses),
depending upon whether or not the user wants to
place Wait states in all 1/0 cycles, or only

during lB500A I/O cycles. Tables 7 and B list. the
lB500A peripheral
and t.he l80B CPU timing
parameters (respectively) of concern during the
I/O cycles.
Tables 9 and 10 list t.he equations
used In.determining if these parameters are satisfied.
In generating these equations and the
values obtained from them, the required number of
Wait states was t.aken into account. The reference
numbers in Tables 7 and B refer to the timing
diagram of Figure 3b.

CLOCK

ADDR

CPU

DATA IN

CPU
DATA OUT

---+-------------CI VALID DATA

-------f

figure 3b.

VALID DATA
_ _ _ _ _ _- - - J

l80S CPU to l8500A Peripheral Minimum I/O Cycle Timing

715

Table 7.

Z8500A TiM1ng Parameters I/O Cycles

IIorst Case

6.
1-

4.
8.
3.
7.

Min

Address to WR Low Setup
Address to Ro Low Setup
Address to Read Data Val1d
BE Low to WR Low Setup
BE Low to RD Low Setup
RD Low Width
WR Low Wldth
RD Low to Read Data Valld
Wrlte Data to WR Low Setup

TsA(WR)
TsA( RD)
TdA(DR)
TsCU(WR)
TsCEl(RD)
TwRDI
TwWRl
TdRDf(DR)
TsDW(WR)

Table 8.

80
80
420
0
0
250
250
180
0

lkIits

ns
ns
ns
ns
ns
ns
ns
ns
ns

Z80B TiMing Parameters I/O Cycles

Worst Case

fcC
TwCh
TfC
fdCr(A)
TdCr(R'of)
fdCr( IORQf)
TdCr(WRf)
TsD(Cf)

Max

Min
~lock Cycle PerIod
Clock Cycle Hlgh W1dth
Clock Cycle Fall T1me
Clock Hlgh to Address Valid
Clock Hlgh to RD Low
Clock Hlgh to IORQ Low
Clock Hlgh to WR Low
Data to Clock Low Setup

Table 9.

165
65
20
90
70
65
60
40

lkIits

ns
ns
ns
ns
ns
ns
ns
ns

Parameter Equations

Z8500A
Parameter

Z80B
Equation

TsA(RD)
TdA(DR)
TdRDf(DR)
fwRDI
TsA(WR)
TsDW(WR)
fwWRI

fcC-TdCr(A)
3TcC+TwCh-TdCr(A)-TsD(Cf)
2TcC+TwCh-:[sl)(Cf)
2TcC+TwCh+TfC-TdCr(RDf)
TcC-TdCr(A)

Value

2fcC+TwCh+ffC-TdCr(WRf)

Table 10.

Max

>75
430
345
325
75
>0
352

mln
mIn
mln
mIn
mIn
mlll
mIn

lkIits

ns
ns
ns
ns
ns
ns
ns

Parameter Equations

Z80B
Par_ter

Z8500A
Equation

Value

TsD(Cf)

Address
3fcC+fwCh-fdCr(A)-TdA(DR)

lkIits

m1l1

75 mln

RD
2TcC+TwCh-TdCr(RDf)-TdRD(DR)

716

l8011 CPU to Z8500 Peripherals
During an I/O Relld cycle, there are three l8500
parameters that must be satisfied. Depending upon
t.he loading characteristics of the mi signal, the
designer may need to delay the leading (falling)
edge of, mi t.o satisfy the .lS500 timing parameter
TsA(RD) (Address Valid to mi Setup). Since lSOH
timing parameters indicate that the mi signal may
go Low after the falling edge of T2 , it is
recommended that the riSing edge a f the system
clock be used to delay ~ (if necessary). The CPU
must also be placed into a Wait condition long
enough to satisfy TdA(DR) (Address Valid to Read
Data Valid Delay) and TdRDf(DR) (~Low to Read
Data Valid Delay).
During an I/O Write cycle, there are three other
lS500
parameters
that
must
be
satisfied.
Depending upon the loading characteristics of the
WI!" signal and the data bus, the designer may need
to delay the leading (falling) edge of WI!" to
satisfy the l8500 timing parameters TsA(WR)
(Address Valid to WR" Setup) and TsDW(WR) (Data
Valid Prior to WI!" setup).
Since lBOH timing
parameters indicate that the WI!" signal may go Low
after the falling edge of TZ' it is recommended
that the rising edge of the system clock be used
to delay WI!" (if necessary)..
This delay will
ensure that both parameters are satisfied.
The
CPU must also be placed into a Wait condition long

Table 11.

TcC
TwCh
TfC
TdCr(A)
TdCr(RDf)
Td Cd lORQ f)
TdCdWRf)
TsD(Cf)

enough to satisfy TwWRl em\" Low Pulse Width).
Assuming that the WI!" signal is delayed, only two
additional Wait states are needed dur ing an I/O
Write cycle when Interfacing the lSOH CPU to the
l8500 peripherals.
To simplify the I/O interface, the designer can
use the same number 0 f Wait states for both I/O
Read and I/O Write cycles.
Flgure 3c shows the
minimum lBOH CPU to lB500 peripheral interface
.timing for the I/O cyc les (assuming that the same
number of Wait states are used for both cycles and
that both mi and WI!" need to be delayed). Figure
4 shows two ~ircuits t.hat can be used to delay the
leading (falling) edge of either the ~ or the WI!"
signals. There are several ways to place the l80A
CPU into a Wait condition (such as counters or
shl ft registers to count system clock pulses),
depending upon whether or not the user wants to
place Wait states in all 1/0 cycles, or only
during l8500 I/O cycles. Tables 4 and 11 lIst the
l8500 p.hlpheral and the l80H CPU tImIng
parameters (respectIvely) of concern dUrIng the
I/O cycles. Tables 14 and 15 llst the equatlOns
used In determlnlng If these parameters are
satlsfled. In generatlng these equatlons and the
values obtalned from them, the requlred number of
Walt states was taken wto account. The reference
numbers In Tabl es 4 and 11 refer to the tlming
dlagram of FIgure 3c.

l80H Timing Paraaeter I/O Cycles

Equation

Min

Clock Cycle Perlod
Clock Cycle Hlgh Wldth
Clock Cycle Fall T1me
Clock Hlgh to Address Valid
Clock Hlgh to lID Low
Clock HIgh to IORQ Low
Clock H1gh to WR Low
Data La Clock Low Setup

1Z5
55

Table 12.

10
80
60
55
55
30

lkIits
ns
ns
ns
ns
ns
ns
ns
ns

Parameter Equations

l8500
Paraneler

l80H
Equation

TsA(RD)
TdA(DR)
TdRDf(DR)
TwRDI
TsA(WR)

ZTcC-TdCr(A)
6TcC+TwCh-TdCr(A)-TsO(Cf)
4TcC+TwCh-TsD(Cf)
4TcC+TwCh+TfC-TdCr(RDf)
WR - delayed
ZTcC-TdCdA)

TsDW(WR)
TwWRI

Max

Value
170
695
523
503

min
mln
mIn
mIn

ns
ns
ns
ns

170 mln
mln
563 mIn

ns
ns
ns

>0
4TcC+TwCh+TfC

1kI1ts

717

CLOCK

ADDR

IORQ

WAIT

RDD

READ

CPU
DATA IN

WRITE ----------------------~

CPU
DATA OUT

VALID DATA

Figure Jc.

718

l800 CPU to l8500 Penpheral Mini_

I/o Cycle Tilling

Z80H CPU to l8SOOA Peripherals
Dur ing an 1/0 Read cycle, there are three l8500A
parametera that must be satisfied. Depending upon
the loading characteristics of the 1m" signal, the
designer may need to delay the leading (falling)
edge of 1m" to satisfy the lB500A timing parameter
TsA(RD) (Address Valid to 1m" Setup). Since lBOH
timing parameters ind~cate that the 1m" signal may
go Low after the falling edge of 12 , it is
recommended that the rising edge of the system
clock be used to delay ~ (if necessary). The CPU
must slso be placed into a Wait condition long
enough to satisfy TdA(DR) (Address Valid to Read
Data Valid Delay) and TdRDf(DR) (1m" Low to Read
Data Valid Delay). Assuming tha~ the 1m" s~gnal is
delayed, then only one additional Wait state is
needed during an I/O Read cycle when interfacing
the lBOH CPU to the lB500A per~pherals.
During an 1/0 Write cycle, there are three other
ZB500A parameters that have to be satisfied.
Depending upon the loading characteristics of the
W signal and the data bus, the designer may need
to delay the leading (falling) edge of W to
'satisfy the ZB500A timing parameters TsA(WR)
(Address Valid to W Setup) and TsDW(WR) (Data
Valid Prior to WR' Setup).
Since, ZeOH timing
parameters indicate that the WR' signal may go Low
after the falling edge of T2' it is recommended
that the rising edge of the system c lock be used

Table

'to delay W (if necesssry).
This delay w~ll
ensure that both parameters are satisfied.
The
CPU must also be placed into a Wait condition long
enough to satisfy TwWRl (W Low Pulse Width).
Assuming that the W signal lS delayed, then only
one additional Wait state is needed during an I/O
Write cycle when interfacing the ZBOH CPU to the
ZB500A peripherals.
Figure 3d shows the minimum ZBOH CPU to ZB500A
peripheral interface timing for the 1/0 cyclea
(assuming that the same number of Wait states are
used for both cycles and that both 1m" and W need
to be delayed). Figure 4 showa two circuits that
may be used to delay the leading (falling) edge of
eit.her the 1m" or the WR' signal s.
There are
several methods used to place the ZBOA CPU ~nto a
Wait condition (such as counters or shift
registers to count system clock pulses), depend~ng
upon whether or not the user wants to place Wait
states 1n all 1/0 cycles, or only during ZB500A
I/O cycles.
Tables 7 and 11 hst the ZB500A
per~phersl snd the
ZBOH CPU tlmlng psrameters
(respectlvely) of concern dUring the I/O cycles.
Tables 14 and 15 llst the equatlons used ln
determlnlng ~f these parameters are sstlsfled. In
generatlng these equatlons and the values obtalned
frbm them, the reqUired number of Walt states was
taken Into account.
The reference numbers ln
Tables 4 and 11 refer to the tlm~nq dlagram of
figure 3d.

Par_ter Equahoos

Z8500
Equation
TsD(Cf)

Value

Address
6TcC+TwCh-TdCr(A)-TdA(DR)
iID - delayed
4TcC+TwCh+TfC-IdRD(DR)

Table 14.

8'11 ts

135 mln

300 mw

Value

lkIits

Par_ter Equations

l8111
Equation
TsA(RD)
TdA(DR)
TdRDf(DR)
IwRDl
TsA(WR)
TsOW(WR)
IwWRI

2[cC-TdCr(A)
6TcC+TwCh-TdCr(A)-TsD(Cf)
4TcC+TwCh-TsD(Cf)
4TcC+TwCh+TfC-TdCr(RDf)
WR - delayed
2TcC-TdCr(A)

170
695
525
503

mIn
min
mIll
mw

ns
ns
ns
ns

170 mw
mln
313 mw

liS

>0
2TcC+ TwCh+ HC

ns
ns

719

CLOCK

J - - -.....-~.---~INTACK

CLR

74LS04

Q3
Qs
CLOCK

-------11>

74LS04

Q6
Q7

74LSOO

74LS11

.....- - - - - - - - _ WAIT'
Figure 5.

Z8OA!Z808 CPU to Z8500/Z850OA Peripheral I'1terrupt Acknowledge Interface logic

During I/O and normal memory accellll cycles, the
Shift register remains cleared becaulle the Hf
signal is inactive.
During opcode fetch cycles,
a.Lso, the Shift register remains cleared, because
only Os can be clocked through the register.
Since Shift register outputs are low, ~,
WlITIT, and
are controlled by other system
logic and gated through the AND gates (74lS II).
During I/O and normal memory access cycles, ~
and VlIITTE" are active as a result of the sYlltem l'!li
and ~ signals (respectively) becoming active.
If system logic requires that the CPU be placed
into a Wait condition, the
signal controls
the CPU.
Should it be necessary to reset the
system, ~ causes the interface logic to
gen~rate both ~ and WRTTr (the Z8500 peripheral
Reset condition).

vnur

vnur·

Normally an
Interrupt
Acknowledge cycle is
indicated' by the Z80 CPU when Hf and ~ are both
active (whi.ch can be detected on the third rising
clock edge after T'I)' To obtain an early indication of an Interrupt Acknowledge cycle, the Shift
register decodes ~n active Hf in the presence 0 f
an inactive ~ on the rising edge of T2 •
During an Interrupt Acknowledge cycle, the ~
signal is generated on the rising edge 0 f T2'

Since it is the presence of TN"i'ACI( and an active
that gates the interrupt vector onto the data
bus, the logic must also generate 'RrAIT at the
proper time. The timing parameter of concern here
is TdIAi(RD) [TN"i'ACI( to mi (Acknowledge) low
Delay].
This time delay allows the interrupt
daisy chaw to setUe so that
the device
requesting the interrupt can place its interrupt
vector onto the dat a bus.
The Shift regist.er
allows a sufficient time delay from the generation
of 1liIT1iCK before it generates m:Ali. During this
de lay, i t places the CPU into a Wait state unti L
the valid interrupt vector can be placed onto the
data bus.
1f the time between these two signals
is insufficient for daisy chain settling, more
time can be added by taking 'RrAIT and iiAIT from a
later posi tion on the Shi ft register.

Figur<: 6 illustrates Interrupt Acknowledge cycle
timlng resul ting from the Z80A CPU to Z8500
peripheral and the Z808 ~PU to Z8~00A peripheral
interface.
This timing comes from the logic
illustrated in Figure 5, which can be used for
both lnterfaces.
Should more Wait. stat.es be
requued, the additional time can be calculated in
term,; of system clocks, since the CPU clock and
PCLK are the same.

723

T':.

Twa

CLOCK

----------------------------------------------------f
~

DATA
VECTOR

Figure 6.

zaowZ8111 CPU to Z8500/Z85OOA Peripheral Interrupt Acknowledge Interr_ n.ing

Z80H CPU to Z8S00!18500A Peripherals

Figure 7' depicts logic that can' be used in interfacing the ZBOH CPU to the ZB500/l8500A peripherals.
This logic is the same as that shown in
Figure 5, except that a synchronizing flip-flop is
used to recognize an Interrupt Acknowledge cycle.
Since lB500 peripherals do not rely upon PClK
except du~ing Interrupt Acknowledge cycles,
synchronization need occur only at that time.
Since the CPU and the periphera~s are running at
different. spe~ds, ~ and 1m" , muat be
synchronized to the lB500 peripherals clock.
During, I/O and normal memory access cycles, the
synchronizing flip-flop and the Shift register
remain cleared because the ~ signal is inactive.
During opcode fetch cycles, the flip-flop and the
Shift register sgain remain cleared, but this time
because the
signal is active. The synchronizing flip-flop allows an Interrupt Acknowledge
t·y .. J e lobe recognized on the rising edge of T2
will''' Mf 1S active and 'ARm is inactive, generating
I'"' TNTA signal. When INTA is active, the Shift
""J!"',n. ean clock and generate ~ to the
'''"' I "h'" aJ
and 'WAIT to the CPU.
The 91i ft
ro"J!'Ii 1'" delays the generation of ~ to the
,,,., I ,,' II" "J
unl11 the daisy chain settles.
The

724

____________
J
VECTOR DATA

WlITT signal is removed when sufficient time has
been allowed for the interrupt vector data to be
vaUd.
Figure Ba illustrates Interrupt Acknowledge cycle
timing for the ZBOH CPU to lB500 peripheral interface. Figure Bb illustrates Interrupt Acknowledge
cycle timing for the lBOH CPU to ZB500A peripheral
interface. These t1mings result. from the logic in
Figure 7. Should more Wait states be required,
t.he needed time should be calculated in terms of
PClKa, not CPU clocka.
Z80 CPU to Z80 and Z8S00 Peripherals

In a ZBO system, a combination of ZBD peripherals
and ZB500 peripherals can be used compstibly.
While there is no restriction on the placement of
the ZB500 peripherals in the daisy qhain, it is
recommended that they be placed early in the chain
to minimize propagation delays during RETI cycles.
Durio;tg an Interrupt Acknowledge cycle, the lEO
line from the ZB500 peripherals changes to reflect
the interrupt status. Time should be allowed for
this change to ripple through the remainder of the
daisy chain before activat.ing IORQ' to the ZBO
peripherals, or Tl'E:lm' to the ZB500 peripherals.

74LS11

WR ~----------------------------------------~~r-~} - - .

RESET .-----------------------------------------~~r_~--.
RD ~------------------------------------------~
74LS74

MREQ - - - - - - ,
INTA

CLOCK

~--------------+_~

74LS164
A

74LS04
Qo

~------IN-T-A-C-K------+_.__i~~~~INTACK
74LS04

IREAD

CLR

PCLK

74LS04

Qs
Q7

74LS11

74LSOO

WAIT ~------------------------------_f
~------------------~WAIT'

figure 7.

Z80H to Z8500/Z8500A

Peripheral Interrupt Acknowledge Interface Logic

Dudng the RETl cycles, the lEO line from the
Z8500 peripherals does not change state as in'the
Z80 peripherals.
As long as the peripherals are
at the top of the daisy chain, propagation delays
are minimized.

Figure 9.
This logic delays the generation of
lORQ' to the Z80 peripherals by the same amount of
time necessary to generate 'RE'Jij) for the Z8500
peripherals.
Timing for this logic during an
Interrupt Acknowledge cycle is depicted in
Figure 10.

The logic necessary to create the control signals
for both Z80 and Z8500 peripherals is shown in

725

Twa

CLOCK

IORQ

INTA

PCLK

INTACK

WAIT

READ

VE~!~:

'"
Figure 8a.

Z80H CPU to Z8500 Peripheral Interrupt Acknowledge Interface TiMing

0--i
VECTOR DATA

)--

CLOCK

Twa

r--'\.

IORQ

IN"fA

PCLK

INTACK

WAIT

READ

VECTOR
DATA

VECTOR DATA

Figure Db.

Z80H CPU to Z8500A Peripheral Interrupt klcnoirledge Interface Tilling

74LS11

WRITE

RESET

.-----------~.

READ

RD
74LS04

IORQ'

IORQ
74LS164
74LS04

MREQ

A
74LS04

INTACK

74LS04 _ _

IREAD

02
03

CLR

CLOCK

04
05

74LS04

07
74LSOO

74LS11

WAIT ..

L----------------------------cc
Figure 9.

lao

and l8500 Peripheral Interrupt Acknowledge Interface logic

WAIT'

Twa

CLOCK

IORQ

INTACK

WAIT

READ

IORQ'
~

figure 10.

41.

Z80 and Z85011 PeripheJ;el Interrupt klcnowledge Interface THIing

SOfTWARE CONSIDERATIONS -- POlLED OPERATION
There are several options available for
interrupts on the Z8500 peripherals.
vector or IP registers can be read at
software can be used to emulate the Z80

servicing
Since the
any time,
interrupt

response. The interrupt vect9r read reflects the
interrupt status condition even i f the device is
programmed to return a vector t.hat does not
reflect the status change (SAVor VIS is not,
set). The code below is a simple software routine
th'at emulates the Z80 vector response operatwn.

lao Vector Interrupt Response, Emulation by Software

;This code emulat.es the Z80 vector interrupt
;operation by reading the device interrupt
;vector and forming an address from a vector
;t.able. It then executes an indirect jump to
;the int.errupt. service routine.

INDX:

VECTAB:

730

LD
OUT
IN
INC
RET
AND
LD
LD
LD
ADD
LD
INC
LD
I..D
JP

A,CIVREG
(CTRL) ,A
A,(CTRL)
A
Z
00001110B
E,A
D,O
HL,VECTAB
HL,DE
A,(HL)
HL
H,(HL)
L,A
(HL)

DEFW
DEFW
DEFW
DEFW
DEFW
DEFW
DEFW
DEFW

INT1
INT2
INT3
INT4
INT5
INT6
INT7
INTB

;CURRENT INf. VECf. REG.
,WRITE REG. PTR.
;READ VECT. REG.
;VALID VECTOR?
;NO INT - RETURN
;MASK orHER BITS
,FORM INDEX VALUE
;ADD VEcr. TABLE ADDR.
; GET LOW BYTE
;GET HIGH BYTE
;FORM ROUTINE ADDR.
;JUMP TO IT

A SIMPLE l80-l8500 SYSTEM
The ZB500 devices interface easily to 'the ZBO CPU,
thus providing a system of considerable flexibility.
Figure 11 illustrates a simple system
using the ZBOA CPU and the ZB536 Counter/Timer and
Parallel I/O Unit (CIO) in a mode 1 or noninterrupt environment.
Since interrupt vectors
are not used, the 1l'Jl'liIT line is tied High and no
additional logic is needed.
Because the ClO can

be used in a polled interrupt environment, the TNT
pin is connected to the CPU.
fhe ZBO should not
be set for mode 2 interrupts s~nce the CIO will
never place a vector onto the data bus. Instead,
the CPU should be placed into mode 1 interrupt
mode and a global interrupt service routine can
poll the CIO to determine what caused the
interrupt to occur. In this system, the software
emulation procedure described above is effective.

+5V
+5V

INT

8
07-00
RD

INT
07- 0 0

t-------------~ RD

Z80

Z8536

CPU

CIO
WR

A7- Ao

lORa

RESET ~------~~

ClK WAIT

F1gure 11.

PClK

l80 to Z8500 S1aple System Mode 1 Interrupt or Non-Interrupt Structure

Add,t,onal Information - Zllog Publicatlons
I. filii 1'1'11 lechnlcal Manual
filii IIMII I echnl cal Manual
filii 1'111 I <,chili cal
I.

Manual
cal Manual
'1111 '.10 I('('hllical Manual
'111111 I I'll III' fharact.ensttcs

filii I'll' I .. chlll

(05-0029-01)
(00-2013-AO)
(0 3-000B-0 1)
(03-0036-02)
(03-3035-01)
(00-2293-01)

7. ZBO Faffill~ Interrupt Structure
(611-1B09-0003)
Tutorial
(00-2057-01)
B. ZB530 SCC Technlcal Manual
(00-2091-01)
9. ZB536 CIO Techmcal Manual
(00-2051-01)
10. ZB03B flO Techmcal Manual

731

SUPPORT PRODUCTS SUMMARY

Z8000® Datacommunications

733

Z85C3000ZCO
PRODUCT SPECIFICATION
KIT CONTENTS
Z85130 Evaluation Board

CMOS Z85130 ESCC and Z85C30 SCC
4.9152 MHz Crystal
RS-232C and RS-422 line drivers
0825 connector

, Software (I.M-PC Platform)

SUPPORTED n .. "III" .....
Z8530,Z85C30,Z85130

DESCRIPTION
The kit contains an assembled PC/XT/AT
circuit board with one high speed serial
port, selectively driven by RS-232C or RS422 line drivers. The kit also contains
software and documentation to support
software and hardware development for
Zilog's SCC and ESCCTM devices.
The board illustrates the use of Zilog's
SCC and ESCC devices in a variety of communication applications such as SOLC/
HOLC, and high speed ASYNC.

Source and executable codes to run SCC or
ESCCTM Controller in SOLC/HOLC and
ASYNC modes using OMA, Interrupt and
. polling methods. All codes are written in C
and compiled using the Microsoft®* Quick
C compiler.
.

Documentation
Z85C30 and Z85130 Product Specifications
Z85C30 and Z85130 Technical Manuals
Z85C3000ZCO Kit User Guide
, SEALEVEL User's Manual

ORDERING INFORMATION
Part No: Z85C3000ZCO

SPECIFICATIONS
Power Requirements
+5 Vdc@.5A

Dimensions
Width: 4 in. (10.16 em)
Length: 5 in. (12.70 cm)

Serial Interface
A 0825 port selectively driven by RS-232C
or RS-422 at selectable baud rates.

• Microsoft IS a registered trademark of Microsoft Corporation.

734

Z16C0100ZCO
PRODUCT SPECIFICATION
KIT CONTENTS
Z16C01/20/30 Evaluation Board

SUPPORTED DEVICES
Z16C01,Z16C20,Z16C30

CMOS Z16C01 CPU
CMOS Z16C20 GLU
CMOS Z16C30 USC
20 MHz Crystal USC Clock
20 MHz System Oscillator
Two (64K)/8K x 8 EPROMs
(programmed with Debug Monitor)
Two 32K1(8K) x 8 STATIC RAM
RS-232C PC Interface
Z16C01 Expansion Bus Connector

Cables
25-Pin RS-232C Cable

DESCRIPTION
The kit contains an assembled circuit board
software and documentation to support
'
software, and hardware development for the
Z16C01 CPU, Z16C20 General Logic Unit
and Z16C30 Universal Serial Controller.
The supplied cross C compiler, assembler
and link/loader package allows full C and
assembly language programming support.
A board resident debug monitor program
and its PC based counterpart allow object
code to be down-loaded and subsequently
debugged.

SPECIFICATIONS
Power Requirements
+5 Vdc@.5A

Dimensions
Single Euro Card Format
Width: 3.94 in. (10 cm)
Length: 6.30 in.(16 cm)

Software (IBM-PC Platform)
Z8000 Cross C Compiler
Z8/Z80/Z8000 Cross Assembler
MOBJ Link/Loader
Resident Debug Monitor Source Code
Host Package Source Code·
Z16C20 Example Software

Documentation
Z8000 CPU Technical Manual
Z8000 CPU Programmer's Pocket Guide
Z16C20 GLU Product Specification
Z16C30 USCTM Controller Technical Manual
Z16C0100ZCO Kit User Manual
CC8K C Compiler User Guide
Z8000 Cross Assembler User Guide
MOBJ Link/Loader User Guide

ORDERING INFORMATION
Part No: Z16C01 OOZCO

Serial Interface
RS-232C @ 9600 baud

735

Z16C3001ZCO
,

PRODUCT SPECIFICATION
KIT CONTENTS"
Z16C30/Z16C33 Evaluation Board
CMOS Z16C30 USC and Z16C33 MUSC
20 MHz Crystal
RS-232C and RS-422 line drivers
OB9 and OB25 Interfaces

Software (IBM-PC Platform)

SUPPORTED DEVICES
Z16C3D,Z16C33

DESCRIPTION
The kit contains an assempled PC/XT/AT
circuit board with two high-speed serial
connections, OB9 and OB25 connectors
selectively driven by RS-232 or RS-422 line
drivers. The kit also contains software and
documentation to support software and '
hardware development for Zilog's USC and
MUSC devices.
The board illustrates the, use of Zilog's
USC and MUSC devices in a variety of communication applications such as ASYNC,
SOLC/HOLC and high-speed ASYNC.

SPECIFICATIONS
Power Requirements
+5 Vdc@.5A

Dimensions
Width: 4.5 in. (11.43 cm)
Length: 6.5 in. (16.51 cm)

Serial Interface
OB9 and OB25 connectors selectively
driven by RS-232C or RS-422 at selectable
baud rates.
736

Source and executable cQdes to run the
USC or MUSC in SOLC/HOLC or ASYNC
mode. All codes are written in C and
compiled using the Microsoft C 5.1 compiler.

Documentation
Z16C30 and Z16C33 Product Specifications
Z16C30/Z16C33 Technical Manual
Z16C3001ZCO Kit User Guide

ORDERING INFORMATION
Part No: Z16C3001ZCO

-.--~~~

"_.

''".-,.~~

~-~"-------~,----~-~.--.~-,"-

--~-------

-~--

-------

Z16C3000ZCO
PRODUCT SPECIFICATION
KIT CONTENTS
usc /68000 Evaluation Board

SUPPORTED DEVICES
Z16C30,Z85C30

CMOS Z16C30 USC
CMOS Z85C30 SCC
MC68000 CPU
MC68450 DMAC
4 MHz Crystal SCC CLock
20 MHz SYstem Oscillator
Two (64K)/8K x 8 EPROMs
programmed with Debug Monitor)
Two 8K x 8 STATIC RAM
RS-232C. PC Interface
Prototype Wire Wrap Area

Cables

DESCRIPTION

25-Pin RS-232C Cable

The kit contains an assembled circuit board,
software and documentation to support
software and hardware development for the
Zilog Z16C30 Universal Serial Controller
and Z85C30 Serial Communication Controller devices in a Motorola 68000 environment.
A board resident debug monitor program
allows object code to be down-loaded and
subsequently debugged.

Software (IBM·PC Platform)

SPECIFICATIONS
Power Requirements
+5 Vdc@ .75 A

Resident Debug Monitor Source Code
Z16C30 Example Software

Documentation
Z16C30 USC Product Specification
Z16C30 USC Technical Manual
Z85C30 SCC Product Specification
Z8530 SCC Technical Manual
Z16C3000ZCO Kit User Manual
Z16C3000ZCO Kit Note to User

ORDERING INFORMATION
Part No: Z 16C3000ZCO

Dimensions
Width: 6.5 in. (16.5 cm)
Length: 9.8 in. (24.9 cm)

Serial Interface
RS-232C

9600 baud

737

",,,,,

Military Qualified Datacom Products
Zilog PIN

Description

Speed

package

883C

SMDPIN

JAN PIN

Z0803004CMB
Z0803004LMB
Z0803006CMB
Z0803006LMB

Z-BUS SCC
Z-BUSSCC
Z-BUSSCC
Z-BUS SCC

.4MHz
4 MHz
6 MHz
6 MHz

4Q-Pin DIP
44-Pin LCC
4Q-Pin DIP
44-Pin LCC

Qualed
Qualed
Qualed
Qualed

5962-8551802QA
5962-8551802YA
5962-8551801QA
5962-8551801YA

N/A
N/A
N/A
N/A

Z0853004CMB
Z0853004LMB
Z0853006CMB
Z0853006LMB

Z8530SCC
Z8530 SCC
Z8530 SCC
Z8530SCC

4 MHz
4 MHz
6 MHz
6 MHz

4Q-Pin DIP
44-Pin LCC
4Q-Pin DIP
44-Pin LCC

Qualed
Qualed
Qualed
Qualed

5962-8752702QA
5962-8752702YA
5962-8752701QA
5962-8752701 YA

N/A
N/A
N/A
N/A

Z85C3006CMB
Z85C3006LMB
Z85C3008CMB
Z85C3008LMB
Z85C3010CMB
Z85C3010LMB

Z85C30 CMOS SCC
Z85C30 CMOS SCC
Z85C30 CMOS SCC
Z85C30 CMOS SCC
Z85C30 CMOS SCC
Z85C30 CMOS SCC

6 MHz
6 MHz
8 MHz
8 MHz
10MHz
10MHz

4Q-Pin DIP
44-Pin LCC
4Q-Pin DIP
44-Pin LCC
4Q-Pin DIP
44-Pin LCC

Qualed
Qualed
Qualed
Qualed
Qualed
Qualed

5962-8868901 QA
5962-8868901YA
5962 -8868902QA
5962 -8868902YA
Q1 '91
Q1 '91

M3851 0/48601 BQA
N/A
M38510/48602BQA
N/A
N/A
N/A

Zl6C3010GMB

CMOS USC

10MHz

68-Pin PGA

Qualed

Q1 '91

N~A

Z8523010CMB
Z8523010LMB
Z8523016eMB
Z8523016LMB

CMOS ESCC
CMOS ESee
CMOS Esee
CMOS ESeC

10MHz
10MHz
16.0 MHz
16.0 MHz

4Q-Pin DIP
44-Pin Lee
4Q-Pin DIP
44-Pin LeC

Q1
Q1
Q1
Q1

Q2
Q2
Q2
Q2

N/A
N/A
N/A
N/A

'91
'91
'91
'91

739

~ZiIm
Zilog's Quality and
Reliability Program
Introduction

QUALITY AND RELIABILITY
Process Template is the profile
displayed by the process evaluation
parameters which are automatically
recorded from the test patterns on
wafers as they proceed through the
production line. These parameters are
translated into the design technology
file attributes such that every product
design bears a key and lock relationship to the process.

Zilog has an excellent reputation for
the quality and reliability of its products.
Zilog's Quality and Reliability
Program is based on careful study of
the principles laid down by such
pioneers as w.E. Deming and J.M.
Juran and, perhaps even more
2. Training
important, observation of the practical
Product Design and Processing are
implementation of those principles in
people dependent. Zilog training
emphasizes the fundamentals inJapanese, European and American
volved in design for quality and
manufacturing facilities.
, reliability.
The Zilog program begins with
Customer Service, an important
employee involvement. Whether the
judgement of our performance is
aspect of Zilog's quality performance
based on perfection in incoming
as a vendor, also depends upon our
people clearly understanding their
inspection, trouble free service in the
field or timely and accurate customer
jobs, and our obligations to our
service, we recognize that our emcustomers. This too is part of the
training curriculum administered by
ployees ultimately control these
factors. Hence, our Quality Program is Zilog.
broadly shared throughout the organization.
3. Order Acknowledgement

Policy
1. Harmony Between Design
and Process
High product quality and reliability
in VLSI products is possible only if
there is structural harmony between
product design and the manufacturing process. Great care is taken to
assure that the statistical process
control limits observed within the
manufacturing plants properly
guardband the design technology
used to configure the circuit and
layout in Zilog's automated design
methodology.
Through use of a technique which
we call Process Templating, the
technology file in the automated
design system is periodically updated
to assure that product design parameters fall within the statistical control
limits with which the process is
actually operated. In simple terms, the

One definition of vendor quality
performance is that the vendor "does
what he promises or acknowledges."
Reliability and quality warranties can
be met only if Zilog and the customer
are in agreement on product and
delivery specifications. Zilog makes
an extra effort to assure that the
customer is fully informed by providing documents with its purchase order
acknowledgements that clearly state
what Zilog understands the specifications to be.

4. Test Guardbanding
No phYSical attribute is absolute.
Customers' test methods may differ
from Zilog's due to variations in test
equipment, temperature or specification interpretation. To assure that
every Zilog product performs to full
customer expectations, Zilog uses a

"waterfall" methodology in its testing.
The first electrical tests made on the
circuit, at the wafer probe operations,
are guard banded to the final test
specifications. The final test specifications, in turn, are guardbanded to the
quality control outgOing sample The
quality control outgoing sample is
guard banded to the customer procurement or data sheet specifications.
This technique of "waterfall" guardbanding assures that circuits which
may be marginal to the customer's
expectations are eliminated in the
manufacturing process long before
they get to the shipping container.

5. Probe at Temperature
Semiconductor devices tend to
exhibit their most limited performance
at the highest operating temperature.
Therefore, it is Zilog's policy that all
chips are tested at high temperature
the very first time they are electrically
screened, at the wafer probe station.
The circuits are tested again at their
upper operating temperature limit in
the 100% final test operation.

6. Process Characterization
Before release to production, every
process is thoroughly characterized
by an exl1austive series of pilot
production runs and tests which
identify the statistical, electrical, and
mechanical limits of which that
particular process regime is capable.
This documentation, which fills a large
loose leaf binder for each process, is
maintained as the historical record or
"footprint" for that particular regime
Process recharacterization is done
any time there is a major process or
manufacturing Site change, and the .
resulting documentation is then
added to the characterization history.
Once the process is fully characterized, the frequent test site evaluation
and process template data demonstrates that the process remains in
speCification.

741

'~ZiIro
7. ' Product Characterization
Every Zilog product design is
evaluated over extremes of operating
temperature, supply voltage and
clock frequencies, prior ,to release to
production, This information permits
the proper guardbanding of the test
program waterfall and identification of
many marginal "corners" in design
tolerances,
A product characterization report,
.which summarizes the more important
tolerances identified in the process of
this exhaustive product design
evaluation, is available to Zilog's
customers.

8. Process Qualification
Zilog also qualifies every process
prior to production by an exhaustive
stress sequence performed on test
chips and on representative products.
Once a process regime is qualified', a
process requalification is performed
any time there is a major process
change, or whenever the process
template statistical quality limits ilre
significantly exceeded or adjusted.

9. Product Qualification
In addition to characterization, every
new Zilog product desigr;J is fully
qualified by a comprehensive series
of life, electrical, and environmental
tests before release to production,
Again, a qualification report is available to our customers which summarizes certain key life and environmental data taken in the course of these
evaluations. Whenever posSible,
industry standard environmental and
life tests are employed.

10. PPM Measurement, Direct
and Indirect
It is frequently said that if you want
to improve something, you need to
put a measure on it. Therelore, Zilog
measures its outgoing quality "parts
per million" by the maintenance of
careful records on the statistical

742

QU,ALITYAND RELIABILITY
sampling of production lots prepared
for shipment This information is then
translated by our statisticians to a
statement of our, parts per million (or
parts per billion) outgoing quality
performance.
Of course, it is one thing for Zilog to
think it is doing, a good job in outgoing
product quality and it is another for a
cl,lstomer to agree. Therefore, we ask
certain key customers to provide us
with their incoming inspection data
which helps us calibrate our outgoing
performance in terms of the actual
results in the field. The fact that Zilog
has been awarded "ship to stock"
status by many customers testifies to
our success in this area.
'

11. FIT Measurement Direct
and Indirect
Just as Zilog records its outgOing
quality in terms of parts per million, it
also measures its outgoing product
reliability in terms of "FITS" or failures
per billion device hours, using the
results of weekly operating life test
measurements on the circuits, performed in accordance with the
standard specifications.

12. Field Quality Engineers
It is frequently said that, "the
customer is always right" If the
customer has an application quality or
reliability problem while using a Zilog
product, whether it is Zilog's responsibility or not, we believe that we have a
responsibility to resolve it Therefore,
Zilog maintains a force of skilled
Applications Engineers who are also
trained as field quality engineers and
are available on immediate call to'
consult at th~ customer's locations on
any problems they may be experiencing with Zilog product performance.

13. Product Analysis
As noted' earlier, we feel that a
customer problem is a Zilog problem.
Accordingly, Product Analysis facili-

ties, staffed by experienced professionals, exist at each Zilog site to
provide rapid evaluation of in-proce~s
and in-field rejects to determine the
cause and provide cmrective action
through a feedback loop into the
production, design, and applications
process. Zilog is pleased to share
product analysis reports on specific
products with the customer upon
request.

14. Test Site Step·Stress·
The process evaluation test sites on
the wafer are packaged and subjected to step-stress testing. Any drift
in parameters under severe conditions of stress outside the norm is
taken as an indication of possible
process contamination or variation.

15. Statistical Process Control
Zilog employs Statistical Process
Control at all critical process steps,
Deviations from norms must be
evaluated by a QIR review board,

16. Perfection Plus Program
Zilog employees actively participate
in meetings in which methods which
will enable a department to do its job
more perfectly are proposed, reviewed, and adopted. Employees who
have made suggestions proudly wear
the Zilog Perfection Plus pin,
17~ Zilog Vendor of the Year
Award

Zilog is proud of the many quality
and performance awards it has
received from its customers. In turn,
Zilog makes an annual award to the
vendor who has done the best overall
job for Zilog.

Zilog's Quality and Reliability
Summary
Zilog is proud of its Quality and
Reliability programs and is pleased to
share this data with its customers, For
further information, contact Zilog's
Director of R/QA.

~ZilO]

LITERATUREGUIDE

Z8®/SUPER8™ MICROCONTROLLER FAMILY
Handbook

Part No

Z8 Design Handbook (includes the following documents)

DC-8275-03

ZB NMOS MCU Mlcrocontroller
Z8600 Z8 MCU 2K 28-Pin Product Specification
Z8601/03/11/13 Z8 MCU 2K/4K Prod. Specification and Protopak
Z8671 MCU with Basic/Debug Interpreter
Z8681/82 Z8 MCU ROMless Product Specification
Z8691 Z8 MCU ROMless Product Specification
Super8 MCU ROMless Product Specification
ZB CMOS MCU Mlcrocontroller
Z86C08 MCU 2K 18-Pin Product Specification
Z86COO/Cl0/C20 MCU 4K/8K 28-Pin OTf'TMProduct Specification
Z86Cll/ MCU 4K Product Specification
Z86C21/Z86E21/C12 BK/OTP Product Specification
Z86C91 MCU ROM less Product Specification
ZB Application Notes and Technical Articles
Memory Space and Register Organization
A Programmer's Guide to the ZB MCU
Z8 Subroutine library

Unit Cost

5.00

A Comparison of MCU Units
Z86xx Interrupt Request Registers
Z8 Family Framing

ZB MCU Technical Manual
SuperB MCU MlcrocontrollerTechnlcal Manual
Z8800/01 MCU ROM less
Z8820MCU8K
Z8822 MCU BK Protopak
SuperB Application Notes and Technical Articles
Gelling Started with the Zilog SuperB
Polled Async Serial Operations with the Super1l '
Using the SuperB Interrupt Driven Communications
Using the SuperB Serial Port with DMA
Generating Sine Waves with Super8
Generating DTMF Tones with Super1l
ASimple Serial Parallel Converter Using the SuperB

ZS Product Specifications, Technical Manuals and Users Guides

Part No

Unit Cost

)

Z8671 Single Chip Basic Interpreter Basic Debug Software Reference Manual
ZB Universal Object File Utilities User's Guide
asm SB Super 8/ZB Cross Assembler User's Guide
Z86C21/E21 CMOS ZB 8K ROM Preliminary Product Specification
Z86C30 CMOS ZB B-Bit MCU Microcontroller Preliminary Product Specification
Z86C40/90 ROM/ROMless CMOS ZB B-Bit Microcontroller Preliminary Product Specification
Z86C08 CMOS ZB B-Bit Microcontroller Preliminary Product Specification
Z86EOB CMOS ZB 8-Bit Microcontroller Preliminary Producl Specification
Z86C09/C19 CMOS ZB 8-Bit Microcontroller Product Specification
Z8602 NMOS ZB 8-Bit MCU Microcomputer Keyboard Controller Preliminary Product Specification
Z8604 NMOS ZB B-Bit Microcontroller Preliminary Product Specification

DC-3149-03
DC-8236--04
DC-8267-05
DC-2512-01
DC-2509-01
DC-251D-01
DC-2527-02
DC-2542-01
DC-2506--01
DC-2525-01
DC-2524-02

ZS Application Notes and Technical Articles

Part No

The Z8 MCU In Telephone Answering Systems Applications Note
Z8602 Controls A101/102 PC/Keyboard Application Note
The ZB MCU Dual Analog Comparator Application Note
Z86C09/19 low ~ost ZB MCU Emulator Application Note
ZB Applications for VO Port Expansions Application Notp
Z86E21 Z8 low Cost Thermal Printer Application Note

DC-2514-01
DC-2521-01
DC-2516--01
DC-2537-01
DC-2539-01
DC-2541-Dl

3.00
3.00
3.00
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
Unit Cost

N/C
N/C
N/C
N/C
N/C
N/C

(Additional Application Notes are contained in the above Design Handbook)

743

~ZiIrr7

LITERATURE GUIDE

Z80®/Z180™ /Z280™ MICROPROCESSOR FAMILY'
Data Book

Part No

zao Family Data Book (includes the following documents)

DC-248Q-01

Z80 NMOS/CMOS
Z84COO NMOS/CMOS zao CPU Prelim, Product Specification
Z84COl zao CPU w/CGC Product Specification
Z84Cl0 NMOS/CMOS zao DMA Product Specification
Z84C20 NMOS/CMOS zao PIO Product Specification
Z84C30 NMOS/CMOS Z80 CTC Product Specification
Z8440/1 /2/4 NMOS Z80 SIO Product Specification
Z84C40/1/2/3/4 CMOS Z80 SIO Product Specification
Z84CSO RAM ao Preliminary Product Specification
Z8470 Z8QTMDART Product Specification
Z84Cao CMOS zao GLU Product Specification
Z84C90 CMOS zao KIOTMProduct Specification
Zao180 Zlao MPU Product Specification
Z280 MPU Preliminary Product Specification

Part No

Z80 Family Data Book Addendum

DC-2518-01

Z801Z180/Z280 Product Specifications, Technical Manuals and Users Guides

Part No

zao CPU Central ProcesSing Unit Technical Manual
zao Family Programmer's Reference Guide
Z80 DMA Direct Memory Access Technical Manual
zao PIO Parallellnpul/Output Technical Manual
zao CTC Counter/Timer Circuit Technical Manual
zao SIO Serial I/O Technical Manual
Zao181 Z180 MPU Microprocessor Unit Technical Manual
Z280 MPU Microprocessor Unit Technical Manual
Zao181 Z181 SACTMSmart Access Controller Preliminary Product Specification
Z84013/15, Z84C13/C15 CMOS IPCTMlntelligent Peripheral Controller PreliminaryiProduct Specification
Z84011/Cll PIO Parallel I/O Controller Product Specification
Z84COO 20 MHz Z80 CPU Central Processing Unit Preliminary Product Specification
Z84C50 zao RAM 80 Z80 CPU/2K SRAM Preliminary ProduclSpecification

DC-0029-03
DC-0012-04
DC-2013-AO
DC-0008-02
DC-0036-02
DC-3033-01
DC-8276-02
DC-8224-03
DC-2519-02
DC-2507-02
DC-2526-02
DC-2523-01
DC-2498-01

Z801Z180/Z280 Application Notes

Part No

Z180/SCCTMSerial Communications Controller Interface at 10 MHz Application Note

744

5,00

Z80 Application Notes and Technical Articles
zao Family Interrupt Structure
Using the zao SIO in Async Communications
Using the zao SIO with SOlC
Binary Synchronous Comm Using the Z80 SIO
Serial Communication with the Z80A DART
Timing in Interrupt-Based System with Z80 CTC
Interfacing Z80 CPUs to the Z8500 Peripheral Family
Serial Clock Generation using the Z8536CI
AZao-Based System Using the DMA with the SIO
Zilog Quality and Reliability Report
Package Information
Ordering Information
literature list
Package Information

Addendum

(Additional Application Notes are contained in the above Oatabook)

Unit Cost

, DC-252Q-Ol

Unit Cost

N/C
Unit Cost

3,00
3,00
3,00
3,00
3,00
3,00
3,00
3,00
N/C
N/C
N/C
N/C
N/C
Unit Cost

N/C

~ZiI.m

LITERATURE GUIDE

Z8000®/80,OOO MICROPROCESSOR FAMILY
Data Book

Pan 1'10

ZOOOO Family Data Book (includes the following documents)

DC-2488-01

18000/80,000 NMOS/CMOS Microprocessors
Z160 CPU Product Specification
Z5300 CMOS SCSI Product Specification
Z7220A HPGD Product Specification
Z765A FOC Product Specification
Z800l®/Z8002® CPU .Product Specification
ZOOl0 MMU Product Specification
ZOO16 Z-DTCTMProduct Specification
Z16C20 CMOS Z-BUS® GLU Preliminary Product Specification
ZOOC30/Z85C30 CMOS SCCTMProduct Specification
ZOO30/8530 SCC Product Specification
ZOO36/Z8536 CIO Product Specification
ZOO38/8538 FlO fiFO Product Specification
Z8060/8560 FIFO Product Specification
Z8068/Z95l8 Z-DCP Product Specification
Z8516/Z95l6 DMA (DTC) Product Specification
Z8581 Clock Generator Controller Product Specification

Un" Cost

5.00

Appllcallon Notes and Technical Articles
Interfacing Z80® CPUs to Z8500 Peripheral Family
Interfacing the Z8500 Peripherals to the 68000
Design Considerations Using Quartz Crystals
with Zilog's Components
Using Z858l Clock Stretches in Z80® CPU Applications
Interfacing Z-BUS Peripherals to the V20N30/8086/OO88
Interfacing the Z-BUS Peripherals Articles Reprint
Using SCC with Z8000 in SDLC Protocol
SCC in Binary Synchronous Communications
Z8000 Development Support
Zilog Quality and Reliability Report
Literature Guide
Ordering Information
Package Information

Z8000 Product Specifications, Technical Manuals and Users Guides

Pan No

ZOOOO CPU Central Processing Unit Technical Manual
ZOOl0 MMU Memory Mapping Unit Technical Manual
ZOO30/Z8530 SCC Serial Communications Controller Technical Manual
Z8036 Z-CIO/Z8536 CIO Counter/Timer and ParaliellnpuVOutput Technical Manual
ZOO36 Z8000 Z-CIO Counter/Timer and ParaliellnpuVOUtput Product Specification
Z8536 CIO Counter/Timer and ParaliellnpuVOutput Product Specification
ZOO38 Z8000 HID FIFO tnpuVOutput Interface Technical Manual
Z8000 CPU Central Processing Unit Programmer's Pocket Guide
Z5380 SCSI Small Computer System Interface Preliminary Product Specification
Z80C30/Z85C30 CMOS SCC Serial Communications Controller Product Specification
Z85C80 SCSCITMSerial Communications and Small Computer Interface Preliminary Product Specification
Z16C01/2/3 CPU Central ProceSSing Unit Preliminary Product Specification
Z16C20 CMOS ZBUS GLU General Logic Unit Preliminary Product Specification
Z16C30 CMOS USCTMUniversal Serial Controller Preliminary Product Specification
Z16C30/Z16C33 CMOS USC/MUSCTMUniversal Serial Controller Technical Manual
Z16C30/Z16C33 CMOS USC/MUSC Universal Serial Controller Addendum
Z16C3l IUSC Integrated Universal Serial Controller Advanced Information Specification
Z16C33 CMOS MUSC Mono-Universal Serial Controller Preliminary Product Specification
Z16C35 CMOS ISCCTMlntegrated Serial Communications Controller Product Specification
Z16C35ISCC Integrated Serial Communications Controller Technical Manual
Z16C35 ISCC Integrated Serial Communications Controller Addendum
Z16C50 ODPLL™Oual Digital Phase Locked Loop Preliminary Product Specification
Z85l30 ESCCTMEnhanced Serial Communications Controller Preliminary Product Specification
Z16C30 USing the USC in Military Applications Application Note
Z16C35 ISCC Interface to Intel and Motorola Microprocessors Application Note

DC-201D-06
DC-2015-AO
DC-2057-06
DC-209l-02
DC-20l4-02
DC-202l-03
DC-205l-Ql
DC-0122-03
IiC-2477-0l
DC-2442-04
DC-2534-02
DC-2504-02
DC-2505-02
DC-2492-Q2
DC-8285-01
DC-8285-01 A
DC-2544-01
DC-2517-02
DC-25l5-03
DC-8286-01
DC-8286-01A
DC-254D-Ol
DC-2543-0l
DC-2536-01
DC-2522-0l

Unit Cost

3.00
3.00
3.00
3.00
N/C
N/C
3.00
3.00
N/C
N/C
N/C
N/C
N/C

N/C
3.00
N/C
N/C
N/C
N/C
3.00
N/C
N/C
N/C
N/C
N/C

745

~ ZiIill

LITERATURE GUIDE

COMPONENTS MILITARY LITERATURE
Military PrOducts Binder

Part No

Zilog Military Products Binder (includes the following documents)

DC-5498-01

Military Specifications

Part No

Z8681 ROMless Microcomputer Military Product Specification
Z8001/8002 Military Z8000 CPU Central Processing Ul'JiI Military Product Specification
Z8581 Military CGC Clock Generator and Controller Military Product Specification
ZOO30 Military Z8000 Z-SCC Serial Communications Controller Military Product Specification
, Z8530 Military SCC Serial Communications Controller Military Product Specification
ZOO36 Military Z8000 HIO Counter/Timer Controller and Parallel VO Military Electrical Specification
ZOO38/8538 Military FlO FIFO InpUVOutput Interface Unit Military Product Specification
Z8536 Military CIO Counter/Timer Controller and Parallel VO Military Electrical Specification
Z8400 Military ZOO CPU Central Processing Unit Military Electrical Specification
Z8420 Military PIO Paraliellnput/Output Controller Military Product Specification
Z8430 Military CTC Counter/Timer Circuit Military Electrical Specification
Z8440/1/2/4 ZOO SIO SeriallnpuVOutput Controller Military Product Specification
ZOOC30/85C30 Military CMOS
Serial Communications Controller Military Product Specification
Z84COO CMOS ZOO CPU Central Processing Unit Military Product Specification
Z84C20 CMOS ZOO PIO ParaliellnpuVOutput Military Product Specification
Z84C30 CMOS ZOO CTC Counter/Timer Circuit MilitarY Product Specification
Z84C40/1/2/4 CMOS Z80 SIO SeriallnpUVOutput Military Product Specification
Z16C30 CMOS
Universal Serial Controller Military Preliminary Product Specification
Zl6C01/2 CPU Central Processing Unit Military Product Specification
ZOO180 Z180 MPU Microprocessor Unit Military Product Specification

sec

use

DC-2392-DZ
DC-2342-D3
DC-2346-Q1
DC-2388-Q2
DC-2397-02
DC-2389-01
DC-2463-D2
DC-2396-Q1
DC-2351-02
DC-2384-D2
DC-2385-01
DC-2386-Q2
DC-2478-D2
DC-2441-D2
DC-2384-Q2
DC-2481-D1
DC-2482-D1
DC-2531-D1
DC-2532-D1
DC-2532-D1

Unit Cost

8.00
Unit Cost,

N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/e
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C

Note: Mililary Product Specifications may be ordered individually at no charge.

GENERAL LITERATURE
Catalogs, Handbooks and Users Guides

Part No

Superintegration Shortform Catalog 1991
Quality and Reliability Report
Superintegration Products Guide
The Handling and Storage of Surface Mount Device's User Guide
Support Products Summary

DC-5472-06
DC-2475-Q6
DC-5499-Q3
DC-55()(}.02
DC-2545-02

746

Unit Cost

N/C
N/C
N/C
N/C
N/C

PACKAGE INFORMATION
20

.--,062 RAD

.sa!

L~~~~
l2'.

---- - - - - 2 0 7 0 - - - - - - - - 1

mo.

~~
~ ~O!O
~~l~

]§QJ
090

100

,010

I-'.m

TYP

MIN

40-Pin Plastic Dual In-Line Package (PDIP)

~~":

1--'1.~-1

1___-

:;-~,

00
-OR·8E'

-----l

~~d:~~
o.CMO

~-ml
~

:-1

0085 1

0.125
MIN

0.010

, ,
II

-J l

0.050
~ ..15 BOTH ENDS

0100
~ 010 TYP

0.01'
%

003 TYP

irnii

4O-Pin Ceramic Package

2020 MAX

710 MAX""';

-:-

~SO:D20

=:€il·ISSMIl)l.
lf1nTIfIn{lmrrnnrrr¥l~ 125 MIN
I !',
- --l
I
-lL
__

.100 •.010 TyP

015

.Ol~

.021

.06~

40-Pln Ceramic Dual In-Line Package (DIP)

747

PACKAGE INFORMATION (Continued)

i
.G';)3

tJ53 :t.OOS
!

.O~5~

. - -_ _ jl--_ _ _ _ _ _---,,-~i

OO~

J ___~
I

.000S

44-Pin Plastic Chip Carrier

rI~::::: ~ :::::::::::::::::1~.
I

I-

2 470

!
I

48-Pin Plastic Dual-In Line Package (PDIP)

748

PACKAGE INFORMATION (Continued)
.045 X 4SoMAX
.010 X45°

WlX3Pl

PIN'I
IDENT.

"Ill
.ll53
f.003

t.OIO

i ..

.045 X 45°

68-Pin Plastic Chip carrier (PLCC)

r- ~::sq'l ~1 r.145

.100Typ .

I
I

.018±.OO2Dia
I t (88PLCS)

I
I

Ptn1

i(!3-1

.035 R

f - - - - - - - - 1 ; 1 2 0 :!:'O05-----~
(FROM CNTR TO

TYP

CNTP. OF HAD!)

84-Pin Plastic Chip Carrier (PLCC)

182: 3

f----~---2'

2' 3 - - - - - - - - 4

100-Pin Quad Flat Pack (QFP)

750

J '
27t.1

IS:Jli

DIMENSIONS IN

ORDERING INFORMATION
Z85C30

Z16C30
68-pinPLCC
Z16C3010VSC
Z16C3010VEC

68-pin PGA
Z16C3010GEE

Z16C31
68-pin PLCC
Z16C3l20VSC

Z16C33

'40-pin DIP
Z0803006PSC
Z0803006DSE
Z0803008PSC
Z0803008DSE

Z16C35
68-pin PLCC
Z16C3510VSC
Z16C3516VSC

28-pin P-DIP
Z16C5010PSC
Z16C5020PSC

Z5380 1.5MB/Sec
44-pin PLCC
Z05380l0VSC

44-pin PLCC
Z8513010VSC
Z85l30l6VSC

Z85230
44-pin PLCC
Z8523010VSC
Z8523016VSC

Z80C30
40-pin DIP
Z80C3008PSC
Z80C3010PSC

4o-pinDIP
Z0853004PSC
Z0853006PSC
Z0853006PEC
Z0853006DSE
Z0853008PSC
Z0853008DSE
Z0853008DEA

44-pinPLCC
Z0853006VSC
Z0853008VSC

Z85C80

Z85130

4O-pin P-DIP
Z8523010PSC
Z8523016PSC

44-pin PLCC
Z0803006VSC
Z0803008VSC

Z8530

Z16C50

40-pin P-DIP
Z8513010PSC·
Z8513016PSC

44-pinPLCC
Z85C3008VSC
Z85C3008VEC
Z85C3010VSC
. Z85C3010VEC
Z85C3016VSC

Z8030

68-pin PLCC'
Z16C3310VSC

40-pin P-DIP
Z0538010PSC

4o-pin DIP
Z85C3008PSC
Z85C3008PEC
Z85C3008CEE
Z85C3010PSC
Z85C3010PEC
Z85C30l0CEE
Z85C30l6PSC

44-pin PLCC
Z80C3008VSC
Z80C3Ql0VSC

Noles:
For military grade devices and the package Iypes other than listed above,
please contact your local Zilog sales office.
Please check the availabilily before placing order.

68-pin PLCC
Z85C80l0VSC

Z80181
10o-pin QFP
Z8018110FEC
Z8018112FEC

Z84013/C13 & Z84015/C15
84-pin PLCC
Z8401306VEC
Z8401310VEC
Z84C1306VEC
Z84C1310VEC

l00-pin QFP
Z8401506FEC
Z8401510FEC
Z84C1506FEC
Z84C1510FEC

ORDERING INFORMATION (Continued)
Z~440/1/2/4

& Za4C4011/2/3/4 zao SIO NMOS/CMOS

$10/0
NMOS 40-pin DIP
Z0844004DSE
Z0844004PSC
Z0844006DSE
Z0844006PSC

CMOS 40-pin DIP
Z84C4004DEE*
Z84C4004PEC*
Z84C4006DEE
Z84C4006PEC
Z84C4008DEE
Z84C4008PEC
Z84C4010DEE
Z84C4010PEC

810/1
NMOS 40-pin DIP
Z0844104DSE
Z0844104PSC
Z0844106DSE
Z0844106PSC

CMOS 40-pin DIP
Z84C4104DEE*
Z84C4104PEC*
Z84C4106PEC
Z84C4108PEC
Z84C4110PEC

SI0/2
NMOS 40-pin DIP
Z08442004DSE
Z0844204PSC
Z0844206DSE
Z0844206PSC

CMOS 40-pin DIP
Z84C4204DEE*
. Z84C4204PEC*
Z84C4206DEE
Z84C4206PEC
Z84C4208DEE
Z84C4208PEC
Z84C4210DEE
Z84C421 OPEC

, Notes:
• 4 MHz CMOS SIOwili be phased out and updraded to 6 MHz in 1991.
Please contact Zilog for availability
For military grade devices and the package types other than listed above,
please contact your local Zilog sales office.
Please check the availability before placing order.

?52

SI0/3
CMOS 44-pln QFP
Z84C4306FEC
Z84C4308FEC
Z84C4310FEC

810/4
NMOS 44-pin PLCC
Z084440VSC
Z0844406VSC

CMOS 44-pin PLCC
Z84C4404VEC*
Z84C4406VEC
Z84C4408VEC
Z84C4410VEC

ORDERING INFORMATION (Continued)
CODES
Package
Preferred
P =. Plastic DIP
V = Plastic Leaded Chip Carrier

Longer Lead Time
D = Cerdip
C = Ceramic
F = Plastic Quad Flat Pack
G = Ceramic PGA (Pin Grid Array)
L = Ceramic LCC

Temperature

:3 = O°C TO

+70°C (Standard)
E = -40°C TO +85°C (Extended)
M = -55°C TO + 125°C (Military)

Environmental
C = Plastic Standard
E = Hermetic Standard'
A = Hermetic Stressed
B = 833 Class B Military
D = Plastic Stressed
J = Jan 38510 Military

Example: Z16C3010VSC is a USC, 10 MHz, Plastic PLCC, O°C to +70°C, Plastic Standard Flow.

16C30

Environmental Flow
Temperature
~ackage

Speed
Product Number
Zilog Prefix

753

•

ZlLOG DOMESTIC SALES OFFICES
AND TECHNICAL CENTERS

INTERNATIONAL SALES OFFICES

CALIFORNIA
Agoura ... ........ .................... ... ....... 818-707-2160
Campbell ........................... ........... 408-370-81 20
Tustin
............................. 714-838-7800

CANAOA
Toronto ........ .......... .......... ..... 416-673-0634

COLORAOO
Bou lder ........ .............. .................. 303-494-2905
FLORIDA
Largo ........ ................................... 813-585-2533
GEORGIA
Norcross ..... ........ ........... .. . .404-448-9370
ILLINOIS
Schaumburg ................. ,.... .......... 708-517-8080
NEW HAMPSHIRE
Nashua .......... ..... .. ........................603-888-8590
NEW JERSEY
Clark
................ .... .................. 201-382-5700
NORTH CAROLINA
Raleigh ...
.......... ....... ......... 919-790-7706
OHIO
Independence
PENNSYLVANIA
Ambler .. ........ ........
TEXAS
Dallas ..........

GERMANY
Munich .................. ...... ........ .. 49-89-672-045
Sbmmerda .................................. 37-626-23906
JAPAN
Tokyo ............. . ....................... .. .81 -3-587-0528
HONG KONG
Kowloon
KOREA
Seoul .

.........852-7238979
. . ... .... ........... .82-2-552-5401

SINGAPORE
Singapore ........ ......... ....... ............ 65-2357155
TAIWAN
Taipei .... . ........ . ........ ..
UNITEO KINGDOM
Maidenhead .............

.886-2-741 -3125
...... 44-628-392-00

... . ..... .... 216-447-1480
. 215-653-0230
........214-987-9987

document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change
without notice. Devices sold by Zilcg, Inc. are covered by
warranty and patent indemnification provisions appearing
inZilog, Inc. Terms and Conditions of Sale only. Zilog, Inc.
makes no warranty, express, statutory, implied or by

description, regardingthe information set forth herein or
regarding the freedom of the described devices from
intellectual property infringement. Zilog, Inc. makes no
warranty of merchantability or fitness for any purpose . .
Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment to update or keep currenl the information contained
in this document.

Zitog , Inc . 210 E. Hacienda Ave ., Campbell , CA 95008-6600 , Tel : (408) 370-8000 , FAX: 408-370-8056/8027

DC-2S03-02

Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:08:20 18:07:16-08:00 Modify Date : 2013:08:21 06:44:35-07:00 Metadata Date : 2013:08:21 06:44:35-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:c4fa3644-dcd7-604a-8971-6257e85fe541 Instance ID : uuid:09174d72-4f11-1042-ab79-4cd74a17ce2b Page Layout : SinglePage Page Mode : UseNone Page Count : 758
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