1992_ACT_Family_Field_Programmable_Gate_Array_Databook 1992 ACT Family Field Programmable Gate Array Databook

User Manual: 1992_ACT_Family_Field_Programmable_Gate_Array_Databook

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ACT™Family
Field Programmable

Gate Array
DATABOOK

ACT™ Family
Field Programmable Gate Array
Databook

April 1992

ACT, Action Logic, Activator, Actionprobe, ALES, and PLICE are trademarks of Actel Corporation.
386, Apollo, LCA, Mentor Graphics, NETED, OrCAD, OrCAD/SDT, OrCADNST, PAL, QuickSim, Sun, Sun-4, SYMED, Valid, ValidGED. VaJidSIM.
Viewdraw. Viewlogic, Viewsim, and Workview are all trademarks or registered trademarks of their respective manufacturers.

Actel Corporation reserves the right to make changes to any products or services herein at any time without notice. Actel does not assume any
responsibility or liability arising out of the application or use of any product or service described except as expressly agreed to in writing by Actel.

© 1992 Actel Corporation

ii

ACTTM Family
Field Programmable Gate Arrays

Product Data
Development Tools
Test and Reliability Reports
Article Reprints
General Information

iii

This databook introduces you to Actel's Field Programmable Gate Arrays (FPGA) and the Action Logic System
(ALS) design environment. In this book, you will find device specifications, reliability data, and
ordering information for systems and devices.
Refer to The FPGA Design Guide for practical design examples using Actel's FPGAs and for tools to help you
estimate design requirements for your FPGA application.
For current availability and prices, contact your local Actel representative. A complete sales office listing is
provided at the end of this book.
If you need to speak to a Technical Support engineer, call Actel's Technical Support Hotline: 800-262-1060.

iv

ACTTM Family
Field Programmable Gate Array
Databook

Order
of

Contents

Section 1: Product Data
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1

ACT 1 Field Programmable Gate Arrays ...........................................................

1-3

ACT 2 Field Programmable Gate Arrays ...........................................................

1-35

ACT 3 Field Programmable Gate Arrays (Advance Information) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-111
ACT 1 and ACT 2 Military Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-117
A10M20A Mask Programmed Gate Array (Preliminary) ................................................ 1-195
Section 2: Development Tools
Software Product Selector Guide

2-1

Action Logic System FPGA Design Environment ....................................................

2-3

Action Logic System on 386 PC Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-5

Action Logic System for Mentor Graphics Design System.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . .

2-7

Action Logic System for Valid Logic Design System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-9

Action Logic System for Viewlogic/Sun Design System ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

2-11

Activator 2 ProgrammerlTester/Debugger ..........................................................

2-13

Using Actionprobe Diagnostic Tools ..............................................................

2-15

Using the Actel Debugger as a Functional Tester

2-17

Section 3: Test and Reliability Reports
ACT Family Reliability Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .
Testing and Programming the A1 010/1 020

3-1
3-17

Section 4: Article Reprints
AR-3:

An Architecture for Electrically-Configurable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1

AR-4:

Dielectric-Based Antifuse for Logic and Memory ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-7

AR-9:

Oxide-Nitrate-Oxide Antifuse Reliability .....................................................

4-13

AR-10: An FPGA Family Optimized for High Densities ...............................................

4-21

Section 5: General Information
Metastability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-1

Three-Stating A1010/1020 Designs ...............................................................

5-3

Socket Selector Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-5

Technical Support Services .....................................................................

5-7

v

vi

Product Data

Product Data

Product Selector Guide ...................................................................................

1-1

ACT 1 Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .

1-3

ACT 2 Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

1-35

ACT 3 Field Programmable Gate Arrays (Advance Information) ................................................... 1-111
ACT 1 and ACT 2 Military Field Programmable Gate Arrays ...................................................... 1-117
A10M20A Mask Programmed Gate Array (Preliminary) .......................................................... 1-195

Product Selector Guide

Product Selector Table
Gates

Equlv. Pkgs.

Speed Option(2)

Temp.(3)

User 1/0

Gate
Array

PLD
Equiv.

Flip-Flops
(max)

TTLs

20-Pin
PALS

Std,
Std,
Std,
Std,

-1, -2
-1, -2
-1,-2
-1

C,I
C,I
C,I
C,M,S

34
57
57
57

1,200
1,200
1,200
1,200

3,000
3,000
3,000
3,000

147
147
147
147

34
34
34
34

12
12
12
12

44
68
84
100
84
44
68
84
84

Std,
Std,
Std,
Std,
Std,
Std,
Std,
Std,
Std,

-1,
-1,
-1,
-1,
-1
-1
-1
-1
-1

C,I
C,I
C,I
C,I
C,M,S
C,M,S
C,M,S
C,M,S
C,M,S

34
57
69
69
69
34
57
69
69

2,000
2,000
2,000
2,000
2,000
2,000
2,000
2,000
2,000

6,000
6,000
6,000
6,000
6,000
6,000
6,000
6,000
6,000

273
273
273
273
273
273
273
273
273

53
53
53
53
53
53
53
53
53

17
17
17
17
17
17
17
17
17

PO
PG

100
100

Std, -1
Std, -1

C,I
C

83
83

2,500
2,500

6,250
6,250

382
382

70
70

23
23

A1240

PO
PG

144
132

Std, -1
Std, -1*

C,I
C,M,S

104
92

4,000
4,000

10,000
10,000

514
514

105
105

34
34

A1280

PO
CO
PG

160
172
176

Std, -1
Std
Std, -1*

C,I
C,M,S
C,M,S

124
140
140

8,000
8,000
8,000

20,000
20,000
20,000

998
998
998

210
210
210

69
69
69

Device

Pkg.(1)

A1010A

PL
PL
PO
PG

44
68
100
84

A1020A

PL
PL
PL
PO
CO
JO
JO
JO
PG

A1225

*

# Pins

-2
-2
-2
-2

Only Commercial Temperature Devices offered in -1 Speed

Notes:
1. Package '!ypes:

CQ
JQ
PG
PL
PQ

Ceramic Quad Flatpacks
J-Leaded Cerquad Chip Carriers
Ceramic Pin Grid Arrays
Plastic J-Leaded Chip Carriers
Plastic Quad Flat Packs

2. Speed Options:

Std
-1
-2

Standard Speed
Standard + 15% Speed
Standard + 25% Speed

3. Temperature Range:

C
I
M
B

Commercial Thmperature (0 to +75°C)
Industrial (-40 to + 85°C)
Military (-55 to + 125°C)
MIL-SID-883C

©

I

1992 Actel Corporation

April 1992

1-1

1-2

ACTTM 1
Field Programmable
Gate Arrays
Features

Description

• up to 2000 Gate Array Gates
(6000 PLD/LCATM equivalent gates)

The ACT™ 1 family offield programmable gate arrays (FPGAs)
offers a variety of package, speed, and application combinations.
Devices are implemented in silicon gate, 1.2-micron or 2-micron
two-level metal CMOS, and they employ Actel's PLICE™ antifuse
technology. The unique architecture offers gate array flexibility,
high performance, and instant turnaround through user
programming. Device utilization is typically 95% of available logic
modules.

•
•
•
•
•
•
•
•
•

Replaces up to 53 TTL Packages
Replaces up to 17 2O-Pin PAL™ Packages
Design Library with over 250 Functions
Gate Array Architecture Allows Completely Automatic Place
and Route
Up to 547 Programmable Logic Modules
Up to 273 Flip-Flops
Flip-Flop Toggle Rates to 100 MHz
Two In-Circuit Diagnostic Probe Pins Support Speed Analysis
to 50 MHz
Built-In High Speed Clock Distribution Network

• I/O Drive to 4 rnA
• Nonvolatile, User Programmable
• Logic Fully Tested Prior to Shipment

Device

A1010A

A1020A

1200
3000
34
12

2000
6000
53
17

Logic Modules

295

547

Flip-Flops (maximum)

147

273

22
13
112,000

22
13
186,000

57

69

44 PLCC
68 PLCC

84 CPGA

44 PLCC
68 PLCC
84 PLCC
100 PQFP
44JQCC
68JQCC
84 JQCC
84 CQFP
84 CPGA

95 MHz
40 MHz

95 MHz
40 MHz

1.2pm

1.2pm

Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Column
PLICE Antifuse Elements
User I/Os (maximum)
Packages

The Action Logic System

100 PQFP
44 JQCC
68JQCC

Performance
Flip-Flop Toggle Rate (maximum)
System Speed (maximum)
CMOS Process

The user-definable I/Os are capable of driving at both TTL and
CMOS drive levels. Available packages include plastic and ceramic
J-Ieaded chip carriers, ceramic and plastic quad f1atpacks, and
ceramic pin grid array.
A security fuse may be programmed to disable all further
programming and to protect the design from being copied or
reverse engineered.

Product Family Profile

Capacity
Gate Array Equivalent Gates
PLD/LCA Equivalent Gates
TIL Equivalent Packages
20-Pin PAL Equivalent Packages

ACT 1 devices also provide system designers with unique on-chip
diagnostic probe capabilities, allowing convenient testing and
debugging. Additional features include an on-chip clock driver with
a hardwired distribution network. The network provides efficient
clock distribution with minimum skew.

The ACT 1 device family is supported by Actel's Action Logic™
System (ALS), allowing logic design implementation with
minimum effort. The ALS interfaces with the resident CAE system
to provide a complete gate array design environment: schematic
capture, simulation, fully automatic place and route, timing
verification, and device programming. The Action Logic System is
available for 386™ PC and for ApolloTM and Sun™ workstations
and for running Viewlogic®, Mentor Graphics®, Valid™, and
OrCADTM.

Note:
1. See Product Plan on pages 1-6 for package availability.
©

1992 Actal Corporation

April 1992

1-3

I

Figure 1. Partial View of an ACT 1 Device

ACT 1 Device Structure
A partial view of an ACT 1 device (Figure 1) depicts four logic
modules and distributed horizontal and vertical interconnect
tracks. PLICE antifuses, located at intersections of the horizontal
and vertical tracks, connect logic module inputs and outputs.
During programming, these antifuses are addressed and
programmed to make the connections required by the circuit
application.

The Actel Logic Module
The Actel logic module is an 8-input, one-output logic circuit
chosen for the wide range of functions it implements and for its
efficient use of interconnect routing resources (Figure 2).
The logic module can implement the four basic logic functions
(NAND, AND, OR, and NOR) in gates of two, three, or four
inputs. Each function may have many versions, with different
combinations of active-low inputs. The logic module can also
implement a variety of D-Iatches, exclusivity function, AND-ORs,
and OR-ANDs. No dedicated hardwired latches or flip-flops are
required in the array since latches and flip-flops may be constructed
from logic modules wherever needed in the application.

Figure 2. ACT 1 logic Module

1-4

ACT 1 FPGAs

I/O Buffers

ACT 1 Array Performance

Each I/O pin is available as an input, output, three-state, or
bidirectional buffer. Input and output levels are compatible with
standard TTL and CMOS specifications. Outputs sink or source
4 mA at TTL levels. See Electrical Specifications for additional I/O
buffer specifications.

Temperature and Voltage Effects
Worst-case delays for ACT 1 arrays are calculated in the same
manner as for masked array products. A typical delay parameter is
multiplied by a derating factor to account for temperature, voltage,
and processing effects. However, in an ACT 1 array, temperature
and voltage effects are less dramatic than with masked devices.
The electrical characteristics of module interconnections on
ACT 1 devices remain constant over voltage and temperature
fluctuations.

Device Organization
ACT 1 devices consist of a matrix oflogic modules arranged in rows
separated by wiring channels. This array is surrounded by a ring of
peripheral circuits including I/O buffers, testability circuits, and
diagnostic probe circuits providing real-time diagnostic capability.
Between rows of logic modules are routing channels containing
sets of segmented metal tracks with PLICE antifuses. Each channel
has 22 signal tracks. Vertical routing is permitted via 13 vertical
tracks per logic module column. The resulting network allows
arbitrary and flexible interconnections between logic modules and
lIO modules.

As a result, the total derating factor from typical to worst case for a
standard speed ACT 1 array is only 1.19 to 1, compared to 2 to 1 for
a masked gate array.

Logic Module Size
Logic module size also affects performance. A mask programmed
gate array cell with four transistors usually implements only one
logic level. In the more complex logic module (similar to the
complexity of a gate array macro) of an ACT 1 array,
implementation of multiple logic levels within a single module is
possible. This eliminates interlevel wiring and associated RC
delays. The effect is termed "net compression."

Probe Pin
ACT 1 devices have two independent diagnostic probe pins. These
pins allow the user to observe any two internal signals by entering
the appropriate net name in the diagnostic software. Signals may
be viewed on a logic analyzer using Actel's Actionprobe™
diagnostic tools. The probe pins can also be used as user-defined
lIOs when debugging is finished.

I

Ordering Information
A1010

A

-

PL

2

84

c

I

Appneation (Tempe""",,, Range)
C=
I =
M=
B=
E =

Commercial (0 to + 75°C)
Industrial (-40 to +85°C)
Military (-55 to + 125°C)
MIL-STD-883
Extended Flow

Package Lead Count
Package Type
PL = Plastic J-Leaded Chip Carriers
PQ = Plastic Quad Flatpacks
CQ = Ceramic Quad Flatpack
JQ = J-Ieaded Cerquad Chip Carrier
PG = Ceramic Pin Grid Array
Speed Grade
Std = Standard Speed
-1
Standard + 15% Speed
-2 = Standard + 25% Speed
Die Revision
Part Number
A1010A = 1200 Gates
A 1020A = 2000 Gates

1-5

Product Plan
Speed Grade*

Application

Std

-1

-2

C

",

",

",

",

",

",

",

",

",

",

",

",

",

",

",

",

",

",
",
",
",
",
",
",
",
",

",

M

B

",

",

",
",
",
",
",

",
",
",
",
",

E

A 101 OA Device
44-pin Plastic Leaded Chip Carrier (PL)
68-pin Plastic Leaded Chip Carrier (PL)
1DO-pin Plastio Quad Flatpaok (PQ)
84-pin Ceramic Pin Grid Array (PG)

",

A 1020A Device
44-pin Plastic Leaded Chip Carrier (PL)
68-pin Plastio Leaded Chip Carrier (PL)
84-pin Plastic Leaded Chip Carrier (PL)
1DO-pin Plastio Quad Flatpack (PQ)
84-pin Ceramic Pin Grid Array (PG)
84-pin Ceramic Quad Flatpack (CQ)
44-pin J-Ieaded Cerquad Chip Carrier (JQ)
68-pin J-Ieaded Cerquad Chip Carrier (JQ)
84-pin J-Ieaded Cerquad Chip Carrier (JQ)

Applications: C
I
M

B
E

Commercial
Industrial
Military
M IL-STD-883
Extended Flow

User I/Os
Logic
Modules

Gates

44-pln

68-pln

84-pln

1~O-pin

A1D10A

295

1200

34

57

57

57

A1020A

547

2000

34

57

69

69

1-6

",
",

",
",
",
",
",

Availability: ", = Available
P = Planned
- = Not Planned

Device Resources
Device
Series

",

",
",
",
",

",
",
",
",
",
",

",
",
",

",
",
",

",

• Speed Grade: -1 = 15% faster than Standard
-2 = 25% faster than Standard

",

ACT 1 FPGAs

Probe A (Output)

Pin Description
CLK

Clock (Input)

TTL Clock input for global clock distribution network. The Clock
input is buffered prior to clocking the logic modules. This pin can
also be used as an I/O.

DCLK

Diagnostic Clock (Input)

TTL Clock input for diagnostic probe and device programming.
DCLK is active when the MODE pin is HIGH. This pin functions
as an I/O when the MODE pin is Law.

The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic pin is
used in conjunction with the Probe B pin to allow real-time
diagnostic output of any signal path within the device. The Probe A
pin can be used as a user-defined I/O when debugging has been
completed. The pin's probe capabilities can be permanently
disabled to protect the programmed designs confidentiality. PRA is
active when the MODE pin is HIGH. This pin functions as an I/O
when the MODE pin is Law.
PRS

Probe B (Output)

I/O pin functions as an input, output, three-state, or bidirectional
buffer. Input and output levels are compatible with standard TTL
and CMOS specifications. Unused I/O pins are automatically
driven LOW by the ALS software.

The Probe B pin is used to output data from any user-defined
design node within the device. This independent diagnostic pin is
used in conjunction with the Probe A pin to allow real-time
diagnostic output of any signal path within the device. The Probe B
pin can be used as a user-defined I/O when debugging has been
completed. The pin's probe capabilities can be permanently
disabled to protect the programmed design's confidentiality. PRB
is active when the MODE pin is HIGH. This pin functions as an
I/O when the MODE pin is Law.

MODE

SOl

GND

Ground (Input)

Input LOW supply voltage.

I/O

Input/Output (Input, Output)

Mode (Input)

The MODE pin controls the use of multi-function pins (DCLK,
PRA, PRB, SDI). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is Law, the pins
function as I/O.

NC

No Connection

This pin is not connected to circuitry within the device.

Serial Data Input (Input)

Serial data input for diagnostic probe and device programming.
SDI is active when the MODE pin is HIGH. This pin functions as
an I/O when the MODE pin is Law.

Vee

Supply Voltage (Input)

Input HIGH supply voltage.
Vpp

Programming Voltage (Input)

Input supply voltage used for device programming. This pin must
be connected to Vee during normal operation.

1-7

I

Absolute Maximum Ratings
Recommended Operating Conditions

Free air temperature range
Symbol

Parameter

Limits

Units

Parameter

-0.5 to +7.0

Volts

Temperature
Rangel

Vee

DC Supply Voltage 1

VI

Input Voltage

-0.5 to Vee + 0.5

Volts

Vo

Output Voltage

-0.5 to Vee +0.5

Volts

11K

Input Clamp Current

±20

mA

10K

Output Clamp Current

±20

mA

10K

Continuous Output Current

±25

mA

TSTG

Storage Temperature

-65 to +150

°C

Commercial

o to

Power Supply
Tolerance

+70

Industrial

Military

-40 to +85 -55 to +125
±10

±5

±10

Units
°C
%Vee

Note:
1. Ambient temperature (TN used for commercial and industrial; case
temperature (Tc) used for military.

Stresses beyond those listed under '~bsolute Maximum Ratings" may
cause permanent damage to the device. Exposure to absolute maximum
rated conditions for extended periods may affect device reliability. Device
should not be operated outside the Recommended Operating Conditions.
Note:
1. V pp = Vee, except during device programming.

Electrical Specifications
Industrial

Commercial
Parameter
Min.
(IOH = -4 mA)
VOH l

Max.

Min.

Max.

1
I

Military
Units
Min.

Max.

3.84

V

3.7

(IOH = -3.2 mA)

3.7
0.40

V

Vil

-0.3

0.8

-0.3

0.8

-0.3

0.8

V

VIH

2.0

Vee + 0.3

2.0

Vee + 0.3

2.0

Vee + 0.3

V

0.33

(Iol = 4 mA)

VOll

0.40

V

500

500

500

ns

CIO I/O Capacitance2. 3

10

10

10

pF

Standby Current. lee4

10

20

25

mA

Input Transition Time tR. tF2

Leakage

Current5

los Output Short
Circuit Currents

-10

10

-10

10

-10

10

pA

(Vo = Vee)

20

140

20

140

20

140

mA

(Vo = GND)

-10

-100

-10

-100

-10

-100

mA

Notes:
1. Only one output tested at a time. Vee = min.
2. Not tested, for information only.
3. Includes worst-case 84-pin PLCe package capacitance. VOUT = 0 V; f = 1 MHz.
4. 'lYpical standby current = 3 mAo AIl outputs unloaded. AIl inputs = Vee or GND.
5. Yo, VIN = Vee or GND.
6. Only one output tested at a time. Min. at Vee = 4.5 V; Max. at Vee = 5.5 V.

1-8

ACT 1 FPGAs

Package Thermal Characteristics

Maximum junction temperature is 150°C.

The device junction to case thermal characteristic is ajc, and the
junction to ambient air characteristic is aja. The thermal
characteristics for aja are shown with two different air flow rates.

A sample calculation of the maximum power dissipation for an
84-pin plastic leaded chip carrier at commercial temperature is as
follows:

Max. junction temp. (0C) - Max. commercial temp. (0C)

150°C -70°C

aja (OC/W)

44°C/W

Package Type
Plastic J-Ieaded Chip Carrier

Pin Count

alc

aja
Still air

44
84

15
13
12

52
45
44

68

1.82 W

aja
300 ft/min.

Units

40
35
33

°C/W
°C/W
°C/W

Plastic Quad Flatpack

100

13

55

47

°C/W

Ceramic Pin Grid Array

84

8

33

20

°C/W

Ceramic Quad Flatpack

84

5

40

30

°C/W

J-Ieaded Cerquad Chip Carrier

44
68
84

8
8
8

38
35
34

30
25
24

°C/W
°C/W
°C/W

Power Dissipation

Sample A 1020 Device Power Calculation

rhe following formula is used to calculate total device dissipation.

To illustrate the power calculation, consider a large design
operating at high frequency. This sample design utilizes 85% of
available logic modules on the AlO20-series device (.85 x 547 = 465
logic modules used). The design contains 104 flip-flops (208 logic
modules). Operating frequency of the design is 16 MHz. In this
design, the CLKBUF macro drives the clock network. Logic
modules and I/O modules are switching states at approximately
10% of the clock frequency rate (.10x 16 MHz = 1.6 MHz). Sixteen
outputs are loaded with 50 pR

rotal Device Power (m W) = (0.20 x N x F1) + (0.085 x M x F2) +
:0.80 x P x F3)
Where:

= Average logic module switching rate in MHz
= CLKBUF macro switching rate in MHz
F3 = Average I/O module switching rate in MHz
M = Number of logic modules connected to the CLKBUF
F1

F2

Total number of logic modules used in the design
(including M)

To summarize the design described above: N == 464; M = 208;
F2 = 16; F1 = 4; F3 = 4; P == 16. Total device power can be
calculated by substituting these values for variables in the device
dissipation formula.

Number of outputs loaded with 50 pF

Total device power for this example

macro
N

=

P ==

\.verage switching rate of logic modules and of I/O modules is
orne fraction of the device operating frequency (usually
:LKBUF). Logic modules and I/O modules switch states (from
ow-to-high or from high-to-Iow) only if the input data changes
vhen the module is enabled. A conservative estimate for average
ogic module and I/O module switching rates (variables F1 and F3,
espectively) is 10% of device clock driver frequency.

=

(0.20 x 465 x 1.6) + (0.085 x 208 x 16) + (0.80 x 16 x 1.6) == 452 mW

f the CLKBUF macro is not used in the design, eliminate the
econd term (including F2 and M variables) from the formula.

1-9

•

Functional Timing Tests
AC timing for logic module internal delays is determined after
place and route. The ALS Timer utility displays actual timing
parameters for circuit delays. ACT 1 devices are AC tested to a
"binning" circuit specification.

modules are distributed along two sides of the device, as inverting
or non-inverting buffers. The modules are connected through
programmed antifuses with typical capacitive loading.
Propagation delay [tpD = (tpLH
AC test specifications.

+ tpHL)/2] is tested to the following

The circuit consists of one input buffer + n logic modules + one
output buffer (n=16 for AIOIOA; n=2B for AI02OA). The logic

Output Buffer Performance Derating
Source

Sink
10

10

/,

/
,
,

/"
2
0.2

/

V
, , ,"

,~

~'

"

,,"

2

0.3

0.4

0.5

0.6

4.0

3.6

Veil (Volts)

3.2

2.8

VOH (Volts)
Military, worst-case values at 125°e, 4.5 V.
Commercial, worst-case values at 70 o e, 4.75 v.

Note:
The above CUIVes are based on characterizations of sample devices and are
not completely tested on all devices.

1-10

V

/

2.4

2.0

ACT 1 FPGAs

Timing Derating
Operating temperature, operating voltage, and device processing
conditions, along with device die size and speed grade, account for
variations in array timing characteristics. These variations are
summarized into a derating factor for ACT 1 array typical timing
specifications. The derating factors shown in the table below are

based on the recommended operating conditions for ACT 1
commercial, industrial, and military applications. The derating
curves show worst-to-best case operating voltage range and
best-to-worst case operating temperature range.

Timing Derating Factor (x typical)
Industrial

Commercial
Device

Best-Case

Worst-Case

Best-Case

0.45
0.45
0.45

1.54
1.28
1.13

0.40
0.40
0.40

A1010A, A1020A
Standard Speed
-1 Speed Grade
-2 Speed Grade

Military

Worst-Case

Best-Case

Worst-Case

0.37
0.37
0.37

1.79
1.49

1.65
1.37
1.20

1.32

Note:

"Best-case" reflects maximum operating voltage, minimum operating
temperature, and best-case processing. "Worst-case" reflects minimum
operating voltage, maximum operating temperature, and worst-case

processing. Best-case derating is based on sample data only and is not
guaranteed.

Voltage Derating Curve

Temperature Derating Curve

1.20

1.40

1.15

1.30
1.20

0

0

.f

1.05

........

.......

1.00

~

0.95

.9

~
u.

~" .........

,

1.10

~

1.00
~

0.00

0.00

0.80

0.85
0.80
4.5

4.75

5.0

5.25

0.70
-60

5.5

Vee (Volts)

•

~~

1.10

i'"

~~

,~

~'

10-""'"

-40 -20

0

20

40

60

80

100

120

Junction Temperature (0C)

Output Buffer Delays

D

To AC test loads (shown below)

GND
tPZL

1-11

AC Test Loads

Load 2
(Used to measure rising/failing edges)

Load 1
(Used to measure propagation delay)

GND

Vee

•

To the output under test

)>------'l

T

•

50PF

R to Vee for tpLZ/tpZl
R to GND for tpHZ/tpZH
To the output under test

'>----.

R = 1 kO
SOPF

T
Input Buffer Delays

Module Delays

=£f

Fan-out = 2

A

Y

B

Vee
S,~VSO%
soo/:--~__G_N_D
_ _ _ _ __
Vee
Out

'r-o..SO%

/VSO%

GND
t pHL

tpLH
Out

Vee

SO~"

GND

tpHL

Sequential Timing Characteristics
Flip-Flops and Latches

GND

/~O%

tpLH

D~Q
c~~
(Positive edge triggered)

D1 _____~><~

~

______________________

~ tsuo

--+I

tweLKA

tHO

I--

~><~----------------

1OOIII1_1---~·1

ClK _____________;-1---:.._______1

~tSUENAj._

~I-~---~ ------·~I

I

~_

1

__II

I+- tWeLK -+/
I

E _______________________~I

Q ________________________________--J><------><~

I-

-I

~

PRE,ClR --------~~I_~_U_AS_Y_N________________________________II
Notes:
1. D represents all data functions involving A, B, and S for multiplexed flip-flops.
1-12

t po

+/

_______

~I_____________

I" tWASYN -I

ACT 1 FPGAs

Timing Characteristics
and critical (speed-sensitive) nets are given below. Most nets will
fall into the "typical" category.

Timing is design-dependent; actual delay values are detennined
after place and route of the design using the ALS Timer utility. The
following delay values use statistical estimates for wiring delays
based on 85% to 90% module utilization. Device utilization above
95% will result in perfonnance degradation.

Less than 1% of all routing in a design requires the use of "long
tracks." Long tracks, long vertical or horizontal routing paths, are
used by the autorouter only as needed. Delays due to the use oflong
tracks range from 15 ns to 35 ns. Long tracks may be used to route
the least critical nets in a given design.

With ALS place and route programs, the user can assign criticality
level to a net, based on timing requirements. Delays for both typical

Logic Module Timing
Vcc = 5.0 V: TJ

= 25°C:

Process

= Typical: tpD = 3.0 ns @

FO

=0

Single Logic Module Macros

(e.g., most gates, latches, multiplexors)1
Output Net

Parameter

FO

=1

FO

=2

FO = 3

FO = 4

FO

=8

Units

tpD

Critical

5.4

5.8

6.2

8.5

Note 2

ns

t pD

Typical

6.3

6.7

7.7

8.6

10.8

ns

Dual Logic Module Macros
(e.g., adders, wide input gates)1

=4

=8

Parameter

Output Net

FO = 1

FO = 2

FO = 3

tpD

Critical

9.2

9.6

10.0

12.3

Note 2

ns

tpD

Typical

10.2

10.6

11.6

12.5

14.6

ns

FO

FO

Units

Sequential Element Timing Characteristics
Fan-Out
Parameter
FO

=1

FO = 2

FO = 3

FO

=4

FO = 8

Units

tsu

Set Up Time, Data Latches

3.5

3.9

4.2

4.5

4.8

ns

tsu

Set Up Time, Flip-Flops

3.9

3.9

3.9

3.9

3.9

ns

tH

Hold Time

0

0

0

0

0

ns

tw

Pulse Width, Minimum3

7.7

8.5

9.2

10.0

14.0

ns

teo

Delay, Critical Net

5.4

5.8

6.2

8.5

Note 2

ns

teo

Delay, Typical Net

6.3

6.7

7.7

8.6

10.8

ns

Notes:
1. Most flip-flops exhibit single module delays.
2. Critical nets have a maximum fan-out of six.
3. Minimum pulse width, tw, applies to CLK, PRE, and CLR inputs.

1-13

•

I/O Buffer Timing
vee = 5.0 V; TJ = 25°C; Process = Typical
INBUF Macros
Parameter

From - To

FO

=1

=2

FO

FO

=3

FO

=4

FO

=8

Units

Pad to Y

6.9

7.6

8.9

10.7

14.3

ns

Pad to Y

5.9

6.5

7.7

8.4

12.4

ns

CLKBUF (High Fan-Out Clock Buffer) Macros
Parameter

FO

= 40

FO

= 160

FO

= 320

Units

9.0

12.0

15.0

ns

9.0

12.0

15.0

ns

Notes:
1. A clock balancing feature is provided to minimize clock skew.

2. There is no limit to the number of loads that may be connected to the
CLKBUF macro.

OUTBUF, TRIBUFF, and BIBUF Macros1
CL = 50 pF

CMOS

TTL

Units

3.9

4.9

ns

7.2

5.7

ns

3.4

ns

6.5

4.9

ns

6.9

5.2

ns

4.9

5.9

ns

Parameter

From - To

t pHL

D to Pad

tpLH

D to Pad

tpHZ

E to Pad

5.2

tPZH

E to Pad

tpLZ

E to Pad

tPZL

E to Pad

Change In Propagation Delay with Load Capacltance 2
Parameter

From - To

CMOS

TTL

Units

tpHL

D to Pad

0.03

0.046

ns/pF

tpLH

D to Pad

0.07

0.039

ns/pF

tpHZ

E to Pad

0.08

0.046

ns/pF

t PZH

E to Pad

0.07

0.039

ns/pF

tpLZ

E to Pad

0.07

0.039

ns/pF

t pZL

E to Pad

0.03

0.039

ns/pF

Notes:
1. The BIBUF macro input section exhibits the same delays as the INBUF
macro.

1-14

2. Load capacitance delay delta can be extrapolated down to 15 pF
minimum.
Example:
Delay for OUTBUF driving a 100-pF TIL load:
tpHL = 4.9 + (.046 x (100-50)) = 4.9 + 2.3 = 7.2 ns
tpLH = 5.7 + (.039 x (100-50)) = 5.7 + 2.0 = 7.7 ns

ACT 1 FPGAs

Soft Macro Library Overview
Macro Name

Description

Modules Required

Levels of Logic

Counters
CNT4A

17

4-bit loadable binary counter with clear

4

CNT4B

15

4-bit loadable bin counter wi clr, active low carry in & carry out

4

UDCNT4A

24

4-bit upldown cntr wi sync active low load, carry in & carry out

6

Decoders
2 to 4 decoder

DEC2X4

4

DEC2X4A

4

2 to 4 decoder with active low outputs

DEC3X8

8

3 to 8 decoder

DEC3X8A

8

3 to 8 decoder with active low outputs

1

DEC4X16A

20

4 to 16 decoder with active low outputs

2

DECE2X4

4

DECE2X4A

4

2 to 4 decoder with enable
2 to 4 decoder with enable and active low outputs

DECE3X8

11

3 to 8 decoder with enable

2

DECE3X8A

11

3 to 8 decoder with enable and active low outputs

2

Latches and Registers
DLC8A

8

Octal latch with clear

DLE8

8

Octal latch with enable

DLM8

8

•

Octal latch with mulitplexed inputs

REGE8A

20

Octal register with preset and clear, active high enable

2

REGE88

20

Octal register with active low clock, preset and clear, active high enable

2

Adders
One bit full adder

3

FADD8

FA1

37

3

8-bit fast adder

4

FADD12

62

12-bit fast adder

5

FADD16

78

16-bit fast adder

5

FADD24

120

24-bit fast adder

6

FADD32

160

32-bit fast adder

7

Comparators
ICMP4

5

4-bit identity comparator

2

ICMP8

9

8-bit identity comparator

3

16-bit magnitude comparator

5
3

MCMP16

93

MCMPC2

9

2-bit magnitude comparator with enables

MCMPC4

18

4-bit magnitude comparator with enables

4

MCMPC8

36

8-bit magnitude comparator with enables

6

Multiplexors
MX8

3

8 to 1 multiplexor

2

MX8A

3

8 to 1 multiplexor with an active low output

2

MX16

5

16 to 1 multiplexor

2

Multipliers
SMULT8

235

8 x 8 two's complement multiplier

Varies

1-15

Soft Macro Library Overview (continued)
Macro Name

Description

Modules Required

Levels of logic

Shift Registers
SREG4A

8

4-bit shift register with clear

2

SREG8A

18

8-bit shift register with clear

2

2

TTL Replacements
TA138

12

3 to 8 decoder with 3 enables and active low outputs

TA139

4

2 to 4 decoder with an enable and active low outputs

1

TA151

5

8 to 1 multiplexor with enable, true, and complementary outputs

3

TA153

2

4 to 1 multiplexor with active low enable

2

TA157

1

2 to 1 multiplexor with enable

1

TA161

22

4-bit sync counter wi load, clear, count enables & ripple carry out

3

TA164

18

8-bit serial in, parallel out shift register

1

TA169

25

4-bit synchronous up I down counter

6

TA181

31

4-bit ALU

4

TA194

14

4-bit shift register

TA195

10

4-bit shift register

1

TA269

50

8-bit upldown cntr wi clear, load, ripple carry output & enables

8

TA273

18

Octal register with clear

1

TA280

9

Parity generator and checker

4

TA377

16

Octal register with active low enable

Super Macros
MC

102

DRAM Controller

Varies

DMA

225

Direct Memory Access Controller

Varies

SINT

180

SCSI Interface Controller

Varies

1-16

ACT 1 FPGAs

Hard Macro Library Overview
[he following illustrations show all the available Hard Macros.

2-lnput Gates (Module Count = 1)

~ ~ ~
~ ~NAN~ ~NAND~
~ ~ ~
~ ~ ~
I-Input Gates (Module Count

= 1, unless indicated otherwise)

•
®

Indicates 2-module macro

... Indicates extra delay input

~

~AND~
~NAN~

~ ~ ~
~ t)NO~ ~

ijNO~

1-17

4-lnput Gates (Module Count = 1, unless indicated otherwise)

®

Indicates 2-module macrc

... Indicates extra delay inpul

~
~ [)NO~
~-y

XOR Gates

XOR-OR Gates

XOR-AND Gates

(Module Count = 1)

(Module Count = 1)

(Module Count = 1)

~&

c

c

~&

~

c

AND-XOR Gates
(Module Count = 1)

1-18

c

ACT 1 FPGAs

AND-OR Gates (Module Count = 1)

® Indicates 2-module macro
... Indicates extra delay input

•

A

B

c

A
B

A

C
D

B
C
D

1 19

OR-AND Gates (Module Count = 1)

®

Indicates 2-module macro

... Indicates extra delay input

1-20

ACT 1 FPGAs

Buffers (Module Count = 1)

I/O Buffers (I/O Module Count = 1)

D

•

D

Multiplexors (Module Count = 1)

A

A

B

B

DO
D1
D2

Y

D3

C

DO
D1

D

A

D2
D3

B

S

1-21

Latches (Module Count

= 1)

---n-----r::+--D-- ---G---t:J ---t:J -u -t:J
D-Latches with Clear (Module Count = 1)

Q

D

OLCA
G

G

CLR

CLR

D-Latches with Enable (Module Count

=

Q

D

OLC

1)

n-D-D- D=0 --D TI n
Mux Latches (Module Count

= 1)
OLME1A

A

n

Q

B
OLMA

S
G

Adders (Module Count = 2)

U

A

CO

HA1

A

A
B

B

B

B

CO

CO
S

S

S

HA1A

A
B
CI

CO

HA1B

A
B
CI

AS
FA1A

FA1B

HA1C

AD
A1
CO

B

CO

AS

CI

AS

FA2A

Macros FA1A, FA1 B, and FA2A have two level delays from the inputs to the S outputs, as indicated by theA

1-22

ACT 1 FPGAs

0-Type Flip-FlOps (Module Count

= 2)

-G--G--D--G-0 -0 -0 -U
0-Type Flip-Flops with Clear

a

D

a

D

a

D

DFC1

DFC1A

DFC1B

CLR

CLR

CLR

ON
DFC1C

D

a

a
DFC1D

D

aN
DFC1E

D

CLR

0

aN
DFC1F

CLR

ON
DFC1G

D

CLR

CLR

I

CLR

0-Type Flip-Flops with Preset

PRE

PRE
a

D

DFP1

PRE
D
a
DFP1D

a
DFP1A

PRE
a
DFP1B

D

D

PRE
D
aN
DFP1E

D
aN
DFP1F

PRE
D
Q
DFPC

PRE
D
Q
DFPCA

CLR

CLR

PRE

PRE
ON
DFP1C

D

PRE
aN
DFP1G

D

0-Type Flip-Flops with Preset and Clear

1-23

0-Type Flip-Flops with Enable (Module Count

= 2)

~~~

D

TI-U

JK Flip-Flops (Module Count

PRE

PRE

PRE
D

D

Q

D
E

Q

E DFEB

E DFEC

ClR

ClR

ClR

= 2)

~

TI
Mux Flip-Flops (Module Count

PRE
Q

J

JKFPC

K

ClR

= 2)
DFME1A

~=rc:t­

=t:J=£J
CLKBUF Interface Macros (Module Count

A

Q

B

DFMB

fi
Q

B

~ ClK

S

= 1)

DO
D1

y
D2
D3

1-24

Q
DFED

ACT 1 FPGAs

Package Pin Assignments
(Top View)
o
z

39
38
37
36
35
34
33
32
31
30
29

GND

44-PIN
PLCC

Vee
Vpp

PRB or I/O
PRA or I/O
DClKor I/O
SDI or I/O

Vee

GND
GND

MODE
ClK or I/O
GND

68-PIN
PLCC

Vee

1819202122232425262728

0

z

z

(!l

9 8 7 6 5 4 3 2 1 686766 6564636261

6 5 4 3 2 1 4443424140

(!l

0

0

~

(!l

0

~

Vpp

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

PRB or I/O
PRA or I/O
DClK or I/O
SDI or I/O

Vee

MODE

ClKor I/O
GND

2728293031323334353637383940414243

o

z

(!l

•

g
o

I~

1110 9 8 7 6 5 4 3 2 1 848382 81 8079 78777675

NC

GND
GND

84-PIN
PLCC

Vee
Vee

Notes:
1. Vpp must be tenninated to Vee, except during device programming.
2. MODE must be tenninated to circuit ground, except during device
programming or debugging.

74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54

PRA or I/O
DClKor I/O
SDI or I/O

Vee
Vee

MODE
ClK or I/O
GND
GND

3. Unused 110 pins are designated as outputs by ALS and are driven low.
4. All unassigned pins are available for use as 1I0s.

1-25

Package Pin Assignments (continued)
(Top View)
o

uuuu
zzzz

NC
NC

GND
GND

R:uuuu u

z

>zzzzz

(!)

80797877 7675747372717069686766656463626160595857565554535251

820
~

49
Q

M

Q

~

~

~

~
~

«
Al0l0A
100-Pin
PQFP

MODE

Vee
Vee

NC
NC
NC

0

SDI or I/O
PRA or I/O

NC
NC
NC

%

ClK or I/O

DClK or I/O

W

100

1 2 3 4 567 8 9101112131415161718192021222324252627282930

uuuuuo
zzzzz:::::

0

~

z

(!)

0

38
37
36
35
34
33
32
31

Vee
Vee

GND
GND
NC
NC
NC

uuuu
zzzz

I~
uuu
zzz

0

z

0

~

(!)

R:uuu u u

>zzzzz

81 807978777675747372717069686766656463626160595857565554535251 W

820

49
Q
Q

~

M

GND
GND

~
~
~

~

%

«

ClK or I/O
MODE

Vee
Vee

38
37
36
35

SOl or I/O

DClK or I/O
PRA or I/O

100

O

o

1 23 456 7 8 9101112131415161718192021222324252627282930

u u UU U 0

zzzzz:::::

o
I~

Notes:
1. V pp must be terminated to Vee, except during device programming.
2. MODE must be terminated to circuit ground, except during device
programming or debugging.

1-26

Vee
Vee

Al020A
100-Pin
PQFP

o

z

(!)

GND
GND

;~
32
~

uu
UU
zzzz

3. Unused liD pins are designated as outputs by ALS and are driven low.
4. All unassigned pins are available for use as liDs.

ACT 1 FPGAs

Package Pin Assignments (continued)

Cl

Cl

Z

Z

c:l

c:l
6 5 4

9 8 7 6 5 4 3 2 1 686766 656463 6261

3 2 1 444342 41 40
39
38
37
36
35
34
33
32
31
30
29

GND
44-PIN

JQCC

Vee
Vpp

PRS or I/O
PRA or I/O
DClKor I/O
SDI or I/O

Vee

GND
GND

MODE
ClK or I/O
GND

68-PIN

JQCC

Vee

18 19 20 21 22 2324 25 2627 28
Cl
Z

Cl

PRS or I/O
PRA or I/O
DClK or I/O
SDI or I/O

~

Vpp

55
54
53
52
51
50
49
48
47
46
45
44

Vee

MODE

ClK or I/O
GND

lln~W~~~~$~~~W~~Q~

II
~
Cl
Z

c:l

0

I~
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54

NC

GND
GND

84-PIN

JQCC

Vee
Vee

PRA or I/O
DClKor I/O
SDI or I/O

Vee
Vee
MODE
ClK or I/O
GND
GND

3334353637383940414243444546474849 50515253
0.
0.

>

o

z

c:l

Notes:
1. V pp must be terminated to Vee, except during device programming.
2. MODE must be terminated to circuit ground, except during device
programming or debugging.

3. Unused 110 pins are designated as outputs by ALS and are driven low.
4. All unassigned pins are available for use as 1I0s.

1-27

Package Pin Assignments (continued)

2

3

4

5

6

7

8

9

10 11

00000000000
00000000000
cOO.
000
00
D
0 0
00
000
E
000
84-PIN
F
000
000
CPGA
000
GOOO
H 0 0
00
JOO
00000
KOOOOOOOOOOO
L
00000000000
A

B

• Orientation Pin (C3)

Signal

A 101 O-Serles Devices

A 1020-Series Devices

A11

A11

B10

B10
E11

MODE

E11

SDI

B11

B11

DClK

C10

C10

Vpp

K2

K2

ClK or I/O

F9

F9

GND

B7, E2, E3, K5, F10,G10

B7, E2, E3, K5, F10, G10

Vee

B5, F1,G2, K7, E9, E10

85, F1,G2, K7, E9, E10

N/C (No Connection)

B1, B2,C1,C2, K1,J2, l1,J10, K10, K11,C11, D10,D11

B2

Notes:
1. Vpp must be terminated to Vee, except during device programming.
2. MODE must be terminated to circuit ground, except during device
programming or debugging.

1-28

3. Unused 110 pins are designated as outputs by ALS and are driven low.
4. All unassigned pins are available for use as 1I0s.

ACT 1 FPGAs

Package Pin Assignments (continued)

o

z

CJ

Pin #1
Index

NC

64 63 62 61 60 79 76 77 76 75 74 73 72 71 70 69 66 67 66 65 64

1

•

63

r

62
61
60

PRA or I/O
DClK or I/O
SDI or I/O

59
56

GND
GND

57

7

56

6

55
10

54

84-PIN
CQFP

11

VDO
VDO
MODE

53
52

12
13

51

VOO14

50

VOO15

49

16

46

17

47

16

46

19

45

20

44

21

43

elK or I/O

I

GND
GND

22 23 24 25 26 27 26 29 30 31 32 33 34 35 36 37 38 39 40 41 42
~

~

a
0

Notes:
1. Vpp must be terminated to Vee, except during device programming.
2. MODE must be terminated to circuit ground, except during device
programming or debugging.

0

~

3. Unused 110 pins are designated as outputs by ALS and are driven low.
4. All unassigned pins are available for use as 1I0s.

1-29

Pac ka9 e Mechanical Details (continued)
Plastic Quad Flatpack
Dimensions in millimeters

2.71 ± .06

~~ 1 2;95±.,5
10.'8±0::·~JfI
~r-d
0.80 ± .15

I. f--I._

20.00 ± .05

23.20 ± .10

1

-----r

14.00 ± .05
17.20 ± .10

18.85 ± .13

1-30

ACT 1 FPGAs

Package Mechanical Details
J-Leaded Cerquad Chip Carrier

.023" min.

* FJ.J~J...L1.J....L..L..L...I....L~-?"""",
_---±--f~_--.-Pin

1

.050" BSC

-~

~~===:t:= I ~

1 Index Chamfer

0.007"
0.011"

--1

E1

E

~JJl
Lead Count

44

D,E

D1, E1

.690" ± .005"

.650" ± .008"

68

.990" ± .005"

.950" ± .008"

84

1.190" ± .005"

1.150" ± .008"

I

Plastic J-Leaded Chip Carrier

o

D1

D

~m
-.j I-- .029" ± .003"

.175" ± .010"
Lead Count

44

D,E

.690" ± .005"

D1, E1

.655" ± .005"

68

.990" ± .005"

.955" ± .005"

84

1.190" ± .005"

1.155" ± .005"

1-31

Package Mechanical Details (continued)
Ceramic Pin Grid Array

I- .050" ± .010"
II (4 pies)

--j
Pin #1

~

~

.018" ± .002"

_____L
.100" typo

-----r

~

1.100" ± .020" square

--1

jJ
.080"

.110"

00000000000-1-r00000000000
00
000
00
00
00
000
000
o 0 0 1.000 SSC
000
000
000
00
00
00.
000
00
00000000000
(j000000000G-1-~
•

1-32

Orientation Pin

120

I~
1. "

ACT 1 FPGAs

Package Mechanical Details (continued)
Ceramic Quad Flatpack

M

0.058" ± .010"

Pin #1

~

0.085/1 ± .010/1

.010/1 ± .002/1

,-, ~

r,

l
r

.025/1 ± .005/1

H

E1

1
1

~

'-.:

N

.050/1 ± .010/1

---.l.....E--

0.006/1 ± .002/1

0.350/1 ± .025/1

lZ
I

r------D1
D

lead Count

O,E

01, E1

84

1.350" ± .030"

0.650/1 ± .010/1

.1

E

I

I

I

.1

1-33

1-34

ACT™ 2
Field Programmable
Gate Arrays
Features
• up to 8000 Gate Array Gates
(20,000 PLD/LCA™ equivalent gates)
•
•
•
•
•
•

Replaces up to 210 TTL Packages
Replaces up to 69 2O-Pin PAL Packages
Design Library with over 250 Macros
Single-Module Sequential Functions
Wide-Input Combinatorial Functions
Up to 1232 Programmable Logic Modules

•
•
•
•

Up to 998 Flip-Flops
16-Bit Counter Performance to 85 MHz
16-Bit Accumulator Performance to 33 MHz
Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 50 MHz
• Two High-Speed, Low-Skew Clock Networks

•

• I/O Drive to 10 rnA
• Nonvolatile, User Programmable
• Logic Fully Tested Prior to Shipment

Product Family Profile
A1280

A1240

A1225

Capacity
Gate Array Equivalent Gates
8,000
PLD/LCA Equivalent Gates
20,000
TIL Equivalent Packages
210
20-Pin PAL Equivalent Packages
69

4,000
10,000
105
34

2,500
6,250
70
23

1,232
624
608

684
348
336

451
231
220

998

565

382

36
15
750,000

36
15
400,000

36
15
250,000

104

83

Device

Logic Modules
S-Modules
C-Modules
Flip-Flops (maximum)
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Column
PLlCE@ Antifuse Elements
User I/Os (maximum)
Packages 1

Performance2
16-8it Counters
16-8it Accumulators
CMOS Process

140
176 CPGA
160 PQFP
172 CQFP

132 CPGA 100 CPGA
144 PQFP 100 PQFP
84 PLCC
84 PLCC

55 MHz
30 MHz

75 MHz
33 MHz

85 MHz
33 MHz

1.2}Jm

1.2}Jm

1.2}Jm

Figure 1. A 1280 176·Pln CPGA

Description
The ACT™ 2 family represents ActeI's second generation of field
programmable gate arrays (FPGAs). The ACT 2 family presents a
two-module architecture, consisting ofC-Modules and S-Modules.
These modules are optimized for both combinatorial and
sequential designs. Based on Actel's patented channeled array
architecture, the ACT 2 family provides significant enhancements
to gate density and performance while maintaining upward
compatibility with the ACT 1 design environment. The devices are
implemented in silicon gate, l.2-}Jm, two-level metal CMOS, and
employ Actel's PLICE antifuse technology. This revolutionary
architecture offers gate array design flexibility, high performance
and fast time-to-production through user programming. The ACT
2 family is supported by the Action Logic™ System (ALS), which
offers automatic pin assignment, validation of electrical and design
rules, automatic placement and routing, timing analysis, user
programming, and debug and diagnostic probe capabilities. The
Action Logic System is supported on the following platforms:
386/486 PC and Sun®, Hp® and Apollo® workstations. It provides
CAE interfaces to the following design environments: Valid™,
Viewlogic®, Mentor Graphics®, HP DCS and OrCADTM.

Note:
1. See product plan for package availability.
2. Performance is based on a -1 speed graded device at commercial
worst-case operating conditions.

©

1992 Actel Corporation

April 1992

1-35

similar for all devices in the family, differing only in the number of
rows, columns, and IJOs.

ACT 2 Architecture
This section of the datasheet is meant to familiarize the user with
the architecture of ACT 2 family devices. A generic description of
the family will be presented first, followed by a detailed description
of the logic blocks, the routing structure, the antifuses, and the
special function circuits. Diagrams for the Al280, A 1240, and
A1225 are provided at the end of the datasheet. The additional
circuitry required to program and test the devices will not be
covered.

Table 1. Array Sizes

Array Topology

1611

I

I

I

I

I

I

10
I

I

I

I

I

I

I

1

20
1

I

Rows

Columns

Logic

I/O

18

82

1232

140

A1240

14

62

684

104

A1225

13

46

451

83

The Logic and I/O modules are arranged in a two-dimensional
array (Figure 2). There are three types of modules: Logic, I/O, and
Bin. Logic and I/O modules are available as user resources. Bin
modules are used during testing and are not available to users.

The ACT 2 family architecture is composed of five key elements or
building blocks: Logic modules, I/O modules, Routing Tracks,
Global Clock Networks, and Probe Circuits. The basic structure is

o
171 I
o

Device

A1280

I

I

I

I

I

I

I

30
I

I

70
I

I••• 1 I I

I

I

I

I

I

80

I

I I

10

20

30

70

80

10

20

30

70

80

1Ilslslclclslslclclslslclclslslclclslslclclslslclclslslclclslsl ••• lslslclclslslclclslslclcl I1I1

•••
o

81 I1Ilslslclclslslclclslslclclslslclclslslclclslslclclslslclclslsl ••• lslslclclslslclclslslclcl I1I1
o
10
20
30
70
80
71 I IIlslslclclslslclclslslclclslslclclslslclclslslclclslslclclslsl ••• lslslclclslslclclslslclcl III I
o
10
20
30
70
80
61

I IIlslslclclslslclclslslclclslslclclslslclclslslclclslslclclslsl ••• lslslclclslslclclslslclcl I III

o
511

10

20

30

70

80

IllslslclclslslclclslslclclslslclclslslclclslslclclslsIclclslsl ••• lslslclclslslclclslslclcll II I

o
10
20
30
70
80
41 I IIIslslclclslslclclslslclclslslclclslslclclslslclclslslcIclslsl ••• lslslclclslslclclslslclcl II II
o
10
20
30
70
80
31 I IIlslslclclslslclclslslclclslslclclslslclclslslclclslslclclslsl ••• lslslclclslslclclslslclcl I II I
o
211

o
11

20

30

70

80

10

20

30

70

80

I IIIslslclclslslclclslslclclslslclclslslclclslslclclslslcIclslsl ••• lslslclclslslclclslslclcl III I

o
01 I I I I I I
s

10

IllslslclclslslclclslslclclslslclclslslclclslslclclslsIclclslsl ••• lslslclclslslclclslslclcll II I

10

1

III

I

IIIII

I

I

20

I

I

I

I

I

I

I

I

I

30

I

I

I

= Sequential Module. C = Combinatorial Module. I = I/O Module

Figure 2. A 1280 Simplified Floor Plan

1-36

70

1••• 1 I I

I

I

I

II

I

I

80

I

III

ACT 2 FPGAs

Logic Modules
Logic modules are classified into two types: combinatorial
C-modules and sequential S-modules (see Figures 3 and 4). The
C-module is an enhanced version of the Act 1 family logic module
optimized to implement high fan-in combinatorial macros, such as
5-input AND, 5-input OR, etc. The S-module is designed to
implement high speed flip-flop functions within a single module.
S-modules also include combinatorial logic, which allows an
additional level of logic to be implemented without additional
propagation delay. C-modules and S-modules are arranged in pairs
called module-pairs. Module-pairs are arranged in altematingpairs
(shown in Figure 2) and make up the bulk of the array. This
arrangement allows the placement software to support two-module
macros of four types (CC, CS, SC, and SS). I/O-modules are
arranged around the periphery of the array.
The combinatorial module (shown in Figure 2) implements the
following function:

Z

= !Sl * (DOO * ISO + DOl * SO) + Sl * (D1O * ISO + Dll * SO)

where:
SO = AO*BO
Sl = A1 + B1

000

y

010

OUT

Up to 8-input function

Figure 3. C-Module Implementation

The sequential module implements this same function Z, followed
by a sequential block. The sequential block can be configured to
implement either a D-type flip-flop or transparent latch. It can also
be fully transparent so that S-modules can be used to implement
purely combinatorial functions. The function of the sequential
module is determined by the macro selection from the design
library of hard macros. Allowable S-module implementations are
shown in Figure 4.

000

ClR

001

y

010

001
OUT

ClK

011

S1

000
001

y

010
011

so

OUT

GATE

so

Up to 7-input function plus O-type flip-flop with clear

Up to 7-input function plus latch

000
00
01

ClR

001

y

OUT

GATE

011
S1

Up to 4-input function plus latch with clear

y

010

OUT

SO

Up to 8-input function (same as C-Module)

Figure 4. S-Module Implementations

1-37

•

II0s
The I/O architecture consists of pad drivers located near the
bonding pads and I/O modules located in the array. Topibottom
I/O modules are located in the top and bottom rows respectively.
Side I/O modules occupy the leftmost two columns and the
rightmost two columns of the array. The function of all I/O
modules is identical, but the top/bottom I/O modules have a
different routing interface to the array than the side I/O modules.
I/Os implement a variety of user functions determined by library
macro selection.

SELECT

OUTEN
(global)

EN

SIEW

- - - - - - 1 - - - " \ -.....>-_ _-,

Special Purpose II0s

SEL

Certain I/O pads are temporarily used for programming and
testing the device. During normal user operation, these special I/O
pads are identical to other I/O pads. The following special 1/0 pads
and their functions, are shown in Table 2.

DATAOUT - - - - - ; DO

Y t------i

D1

Table 2. Special 1/0 Pads
SDATA

SDI

Serial Data In

SDIO

Serial Data Out

BININ

Binning Circuit In

BINOUT

Binning Circuit Out

DCLK

Serial Data Clock In

PRA

Probe A Output

PRB

Probe B Output

Two other pads, CLKA and CLKB, also differ from normal I/Os in
that they can be used to drive the global clock networks. Power,
Ground, and Programming pads are not considered 1/0 functions.
Their function is summarized as follows:

DATAIN

Figure 5. I/O Pad Signals

1/0 Modules
There are two types of I/O modules: side and top/bottom. The I/O
module schematic is shown in Figure 6. In the side 1/0 modules,
there are two inputs supplying the data to be output from the chip:
U01 and U02. (UO stands for user output). Two are used so that
the router can choose to take the signal from either the routing
channel above or the routing channel below the 1/0 module. The
top/bottom I/O modules interact with only one channel and
therefore have only one UO input.
TO TRACKS

VCCA, VCCQ, VCCI

Power

GNDA, GNDQ, GNDI

Circuit Ground

VSV, VKS

Programming Pads

MODE

Program/Debug Control

1/0 Pads
1/0 pads are located on the periphery of the die and consist of the
bonding pad, the high-drive CMOS drivers, and the TTL
level-shifter inputs. Each 1/0 pad is associated with a specific 1/0
module. Connections form the I/O pad to the 1/0 module are
made using the signals DATAOUT, DATAIN and EN (shown in
Figure 5).

EN

TO PAD BUFFER

------------------I.~

SLEW

EN

• SLEW

j
r--.-----..

(regiO::: ~

~

_ _ _ ::

y

DATAOUT

~EL
GOUT-------J

Y..----~_1

DATAIN

GIN--------'
INEN
(global)

Figure 6. I/O Module
1-38

ACT 2 FPGAs

The EN input enables the tristate output buffer. The global signals
INEN and OUTEN (Figure 5) are used to disable the inputs and
outputs during certain test modes. Latches are provided in the
input and output path. When GOUT is low, the output signal on
UOl/U02 is latched. When it is high, the latch is transparent. The
latch can be used as the second stage of a rising-edge flip-flop as
described in the Applications note accompanying this data sheet.
GIN is the reverse of GOUT. When GIN is high, the input data is
latched; when it is low, the input latch becomes transparent.
The output of the module, Y, is used for data being input to the
chip. Side I/O modules have a dedicated output segment for Y
extending into the routing channels above and below it (similar to
logic modules). Side I/O modules may also connect to the array
through nondedicated Long Vertical Tracks (LVTs). Top/Bottom
I/O modules have no dedicated output segment. Signals coming
into the chip from the top or bottom must be routed using F-fuses
and LVTs (F-fuses and LVTs are explained in detail in the routing
section). As a result, I/O signals connected to I/O modules on
either the top or bottom of the array may incur a slight delay
penalty ( -InS) over signals connected to I/O modules on the sides.

Hard Macros
Designing within the Actel design environment is accomplished
using a building block approach. Over 250 logic function macros
are provided in the ACT 2 design library. Hard macro logic
functions range from simple SSI gates such as AND, NOR, and
Exclusive OR to more complex functions such as flip-flops with 4: 1
Multiplexed Data inputs. Hard macros are implemented in the
ACT 2 architecture by using one or more C-modules or S-modules.
Over 150 of the macros are implemented in a single module, while
several two-module macros are also available. Two-module hard

macros always utilize a module-pair, either SS, CC, es, or Sc.
Because one- and two-module macros have small propagation
delay variances, their performances can be predicted very
accurately. Hard macro propagation delays are specified in the
datasheet. Soft macros are comprised of multiple hard macros
connected together to form complex functions. These functions
range from MSI functions to 16-bit counters and accumulators. A
large number of TTL equivalent hard and soft macros are also
provided. Soft macro delays are not specified in the datasheet.

Routing Structure
The ACT 2 architecture uses Vertical and Horizontal routing
tracks to interconnect the various logic and I/O modules. These
routing tracks are metal interconnects that may either be of
continuous length or broken into pieces called segments. Segments
can be joined together at the ends using antifuses to increase their
lengths up to the full length of the track.

Horizontal Routing
Horizontal channels are located between the rows of modules and
are composed of several routing tracks. The horizontal routing
tracks within the channel are divided into one or more segments.
The minimum horizontal segment length is the width of a
module-pair, and the maximum horizontal segment length is the
full length of the channel. Any segment that spans more than
one-third the row length is considered a long horizontal segment.
A typical channel is shown in Figure 7. Nondedicated horizontal
routing tracks are used to route signal nets. Dedicated routing
tracks are used for the global clock networks and for power and
ground tie-off tracks.

MODULE ROW

CLKO
NVCC
TRACK-

0

f

SIGNAL

f

SEGMENT----~======================================________________________

0
0

0

I
I

0
0

0

HF-

0

0

0
0

SIGNAL
(LHT)

0

I
I
I
I
I
SIGNAL
NVSS
CLK1

MODULE ROW

Figure 7. Horizontal Routing Tracks and Segments

1-39

I

Vertical Routing
Other tracks run vertically through the modules. Vertical tracks are
of three types: input, output, and long. Vertical tracks are also
divided into one or more segments. Each segment in an input track
is dedicated to the input of a particular module. Each segment in an
output track is dedicated to the output of a particular module. Long
segments are uncommitted and can be assigned during routing.
Each output segment spans four channels (two above and two
below), except near the top and bottom of the array where edge
effects occur. LVTs contain either one or two segments. An
example of vertical routing tracks and segments is shown in Figure 8.

An antifuse is a "normally open" structure as opposed to the
normally closed fuse structure used in PROMs or PAL®s. The use
of antifuses to implement a Programmable Logic Device results in
highly testable structures as well as efficient programming
algorithms. The structure is highly testable because there are no
pre-existing connections, therefore temporary connections can be
made using pass transistors. These temporary connections can
isolate individual antifuses to be programmed as well as isolate
individual circuit structures to be tested. This can be done both
before and after programming. For example, all metal tracks can be
tested for continuity and shorts between adjacent tracks, and the
functionality of all logic modules can be verified.

Antlfuse Structures

:::> LVTs

c

C-MODULE

S-MODULE

V~.

...
"II

VERTICAL INPUT
SEGMENT C

MODULE ROW

C

CHANNEL

XF

.
S-MODULE

4.

FF
C-MODULE

Figure 8. Vertical Routing Tracks and Segments

Antifuse Connections
Four types of antifuse connections are used in the routing structure
of the Act 2 array. (The physical structure of the antifuse is identical
in each case, only the usage differs.) The four types are:
XF

Cross connected antifuse

Most intersections of horizontal and vertical tracks have an XF that connects the
perpendicular tracks.

HF

Horizontally connected antifuse

Adjacent segments in the same horizontal track are connected end-to-end by an HF.

VF

Vertically connected antifuse

Some long vertical tracks are divided into two segments. Adjacent long segments
are connected end-to-end by a VF.

FF

"Fast-Fuse" antifuse

The FF connects a module output directly to a long vertical track.

Examples of all four antifuse connections are shown in Figures 7 and 8.

1-40

ACT 2 FPGAs

Antifuse Programming
The ACT 2 family uses the PLICE™ anti fuse developed by Actel.
The PLICE element is programmed by placing a high voltage ( - 20
V) across the element and supplying current (-5 rnA) for a short
duration « lms). In the ACT 2 architecture, most antifuses are
programmed to - 500 ohms resistance, except for the F-fuses which
are programmed to - 250 ohms. The programming circuits are
transparent to the user.

Clock Networks

1. externally from the CLKA pad
2. externally from the CLKB pad

The clock modules are located in the top row ofI/O modules. Clock
drivers and a dedicated horizontal clock track are located in each
horizontal routing channel.

eLKB

CLKINB]

CLKA

CLKINA ~
SO
S1

I

r-L-

Vertical tracks span the vertical height of the array. The tracks
dedicated to module inputs are segmented by pass transistors in
each module row. During normal user operation, the pass
transistors are inactive (off), which isolates the inputs of a module
from the inputs of the module directly above or below it. During
certain test modes, the pass transistors are active (on) to verify the
continuity of the metal tracks. Vertical input segments span only
one channel. Inputs to the array modules come either from the
channel above or the channel below. The logic modules are
arranged such that half of the inputs are connected to the channel
above and half of the inputs to segments in the channel below
(Figure 10).

Module Output Connections

~~~~~~L

CLKO(17)
CLOCK
DRIVERS

Connections to Logic and I/O modules are made through vertical
segments that connect to the module inputs and outputs. These
vertical segments lie on vertical tracks that span the entire height of
the array.

Module Input Connections

3. internally from the CLKINA input
4. internally from the CLKINB input

FROM
PADS

The clock input pads may also be used as normal IIOs, by-passing
the clock networks.

Module Interface

Two low-skew, high fan-out clock distribution networks are
provided in the ACT 2 architecture (Figure 9). These networks are
referred to as CLKO and CLK1. Each network has a clock module
(CLKMOD) that selects the source of the clock signal and maybe
driven as follows:

E

The user configures the clock module by selecting one of two clock
macros from the macro library. The macro CLKBUF is used to
connect one of the two external clock pins to a clock network, and
the macro CLKINT is used to connect an internally generated
clock signal to a clock network. Since both clock networks are
identical, the user does not care whether CLKO or CLKl is being
used.

CLKO(16)

CLKO(15)

Module outputs have dedicated output segments. Output segments
extend vertically two channels above and two channels below,
except at the top or bottom of the array. Output segments twist, as
shown in Figure 10, so that only four vertical tracks are required.

LVT Connections
Outputs may also connect to non-dedicated segments (LVTs).
Each module pair in the array shares three LVTs that span the
length of column as shown in Figure 9. Any module in the column
pair can connect to one of the LVTs in the column using an FF
connection. The FF connection uses anti fuses connected directly
to the driver stage of the module output, by-passing the isolation
transistor. FF antifuses are programmed at a higher current level
than HF, VF, or XF antifuses to produce a lower resistance value.

CLKO(2)

Antifuse Connections

CLKO(1)

In general every intersection of a vertical segment and a horizontal
segment contains an unprogrammed anti fuse (XF-type). One
exception is in the case of the clock networks.

CLOCK TRACKS

Figure 9. Clock Networks

1-41

•

I

~ Y+2

J

yr

I

I
Y+2 Y+1

I
I

I I

81
A1

I I

80

001 000

D10 011

AO

III

~

I

j'Y /

/

I

I

I Y-1

~Y-21

I

Y-2

LVTs
S-MODULES

C-MODULES

Figure 10. Logic Module Routing Interface

Clock Connections
To minimize loading on the clock networks, only a subset of inputs
has fuses on the clock tracks. Only a few of the C-module and

S-module inputs can be connected to the clock networks. To further
reduce loading on the clock network, only a subset of the horizontal
routing tracks can connect to the clock inputs of the S-Module.
Both of these are illustrated in Figure 11.

MODULE
C1

C2

CLKO
Clock
} Tracks

CLK1

}

Anti Fuses
Deleted

Figure 11. Fuse Deletion on Clock Networks

1-42

Normal
Routing
Tracls

ACT 2 FPGAs

registers surrounding the array. Data is clocked into these registers
using the DCLK pin. The registers are connected as a long series of
shift registers as shown in Figure 12. The Mode register determines
the test or programming state ofthe device. Many of the test modes
are used during wafer sort and final test at the factory. Other test
modes are used during programming in the Activator® 2, and some
of the modes are available only after programming. The
Actionprobe® function is one such function available to users.

Programming and Test Circuits
The array of logic and I/O modules is surrounded by test and
programming circuits controlled by the external pins: MODE, SDI,
DCLK. The function of these pins is summarized below. When
MODE is low (GND), the device is in normal or user mode. When
MODE is high (VCC), the device is placed into one of several
programming or test states. The SDI pin (when MODE is high) is
used to input serial data to the Mode register and various address

MODE REGISTER

~----r----~

SDI

~DCLK

~-~

Y1

Y1 REGISTER

Y1

Y2

Y2 REGISTER

Y2

~MODE

...V1\

...1\

X

C\I

V

X

I
II:

~

a
w

II:
W

MODULE ARRAY

II:

tn

a
w

II:

X

C\I

X

1\

1\

o

V

o

X

C\I

SDO~------~

V
X

OTHER REGISTERS

Figure 12. ACT 2 Shift Register

Actionprobe
If a device has been successfully programmed and the security fuse
has not been programmed, any internal logic or I/O module output
can be observed using the Actionprobe circuitry and the PRA
and/or PRB pins. The Actionprobe Diagnostic system provides the
software and hardware required to perform real-time debugging.
The software automatically performs the following functions.

A pattern of "Is" and "Os" is shifted into the device from the SnI
pin at each positive edge transition of DCLK. The complete
sequence contains 10 bits of counter, 21 bits of Mode Register, n
bits of zeros (filler of unused fields, where n depends on the
particular device type), R bits ofX2, C bits ofY2, R bits of XI, C bits
of Yl, and a stop bit ("0" or "1"). After the stop bit has been shifted
in, DCLK is left high (see definitions below). Xl and Yl represent
the (X,Y) location in the array for the Actionprobe output, PRA.

1-43

and the selected row and column is "high." The timing sequence is
shown in Figure 13. The recommended frequency is 10 MHz with
10 nS setup and hold times allowing for SDI and DCLK transitions.
The selected module output will be present at the PRA or PRB
output approximately 20 nS after the stop-bit transition.

X2 and Y2 represent the (X,Y) location in the array for the
Actionprobe output, PRB. Rand C are the row and column size as
defined in Table 1. The filler bits, counter pattern, and Mode
register pattern are shown in Table 3. Addressing for rows and
columns is active high, i.e. unselected rows and columns are "zeros"
Table 3. Bit Stream Definitions for Actlonprobe Diagnostics
Device

Probe_Mode

Filler (n)

Counter Pattern

Mode_Register Pattern

# of clocks

A1280

Probe A only

443

0011011111

000000110001111100000

675

A1280
A1280

Probe B only

0011011111
0011011111

000000101001111100000

675

Probe A and B

443
443

000000111001111100000

675

A1240

Probe A only

361

1111000001

000000110001111100000

541

A1240

Probe B only

361

1111000001

000000101001111100000

541

A1240

Probe A and B

361

1111000001

000000111001111100000

541

A1225

Probe A only

308

1101011010

000000110001111100000

458

A1225

Probe B only

308

1101011010

000000101001111100000

458

A1225

Probe A and B

308

1101011010

000000111001111100000

458

For Example: Selecting PRA for A1280 results in the following bit stream:
0011011111 000000110001111100000
{443 zerosLX2<0> ... X2< 17> _Y2<81 > ... Y2<0> _X1 <0> ... X1 <0> ... X1 <17> _Y1 <0> ... Y1 <81 > _0,
where "_" is used for clarity only.

I--

LOAD COUNTER

-+-

FILLER ZEROS
LOAD MODE REG

I
--II--

X. Y ADDRESS

MODE~

Figure 13. Timing Waveforms

1-44

--l s~~p I--

PROBING

--l rJfo ~

ACT 2 FPGAs

Ordering Information
A1280

-

PG

1

C

176

I

I

Applle",,,,,

Package Lead Count

Package Type

Speed Grade

Die Revision
(future)

I

Product Plan
Application

Speed Grade
Std

-1*

C

I

v'
v'
v'

v'
v'

v'
v'
v'

v'

P

v'
v'
v'

v'
v'
v'

v'
v'
v'

v'
v'

v'
v'
v'

v'
v'
v'

v'
v'
v'

v'
v'

M

B

E

A1280 Device
176-pin Ceramic Pin Grid Array (PG)
160-pin Plastic Quad Flatpack (PQ)
172-pin Ceramic Quad Flatpack (CQ)

v'

v'

v'

v'

v'

v'

A 1240 Device
132-pin Ceramic Pin Grid Array (PG)
144-pin Plastic Quad Flatpack (PQ)
84-pin Plastic Leaded Chip Carrier (PL)
A 1225 Device
100-pin Ceramic Pin Grid Array (PG)
100-pin Plastic Quad Flatpack (PQ)
84-pin Plastic Leaded Chip Carrier (PL)

Applications: C
I
M
8
E

*

Speed Grade:

Commercial
Industrial
Military
8838
Extended Flow

Availability: v'= Available
P
Planned
Not Planned

-1 = 15% faster than Standard

Device Resources
User IIOs
CPGA
Device
Series

Logic
Modules

Gates

176-pin

A1280

1232

8000

140

A1240

684

4000

A1225

451

2500

132-pin

PQFP
100-pin

160-pin

144-pin

100-pln

PLCC

CQFP

84-pin

172-pin

125

140
104

104
83

72
72

1-45

Pin Description
ClKA

Clock A (Input)

TTL Clock input for clock distribution networks. The Clock input
is buffered prior to clocking the logic modules. This pin can also be
used as an I/O.

ClKB

Clock B (Input)

TTL Clock input for clock distribution networks. The Clock input
is buffered prior to clocking the logic modules. This pin can also be
used as an I/O.

DClK

Diagnostic Clock (Input)

TTL Clock input for diagnostic probe and device programming.
DCLK is active when the MODE pin is HIGH. This pin functions
as an I/O when the MODE pin is LOW.

GND

Ground (Input)

Input LOW supply voltage.

I/O

Input/Output (Input, Output)

I/O pins function as an input, output, three-state, or bidirectional
buffer. Input and output levels are compatible with standard TTL
and CMOS specifications. Unused I/O pins are automatically
driven LOW by the ALS software.

MODE

Mode (Input)

The MODE pin controls the use of multi-function pins (DCLK,
PRA,PRB,SDI,SDO). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is LOW, the pins
function as I/Os.

pin can be used as a user-defined I/O when debugging has been
completed. The pin's probe capabilities can be permanently
disabled to protect programmed design confidentiality. PRA is
active when the MODE pin is HIGH. This pin functions as an I/O
when the MODE pin is LOW.

PRB

Probe B (Output)

The Probe B pin is used to output data from any user-defined
design node within the device. This independent diagnostic pin is
used in conjunction with the Probe A pin to allow real-time
diagnostic output of any signal path within the device. The Probe B
pin can be used as a user-defined I/O when debugging has been
completed. The pin's probe capabilities can be permanently
disabled to protect programmed design confidentiality. PRB is
active when the MODE pin is HIGH. This pin functions as an I/O
when the MODE pin is LOW.

SDI

Serial Data Input (Input)

Serial data input for diagnostic probe and device programming.
SDI is active when the MODE pin is HIGH. This pin functions as
an I/O when the MODE pin is LOW.

SDO

Serial Data Output (Output)

Serial data output for diagnostic probe. SDO is active when the
MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.

Vee

Supply Voltage (Input)

Input HIGH supply voltage.

VKS

Programming Voltage (Input)

Input supply voltage used for device programming. This pin must
be connected to GND during normal operation.

NC

No Connection

This pin is not connected to circuitry within the device.

PRA

Probe A (Output)

The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic pin is
used in conjunction with the Probe B pin to allow real-time
diagnostic output of any signal path within the device. The Probe A

1-46

V pp

Programming Voltage (Input)

Input supply voltage used for device programming. This pin must
be connected to Vee during normal operation.

Vsv

Programming Voltage (Input)

Input supply voltage used for device programming. This pin must
be connected to Vee during normal operation.

ACT 2 FPGAs

Recommended Operating Conditions

Absolute Maximum Ratings
Free air temperature range
Symbol

Parameter

Units

-0.5 to +7.0

Volts

Vee

DC Supply Voltage l .2.3

VI

Input Voltage

-0.5 to Vee + 0.5

Volts

Vo

Output Voltage

-0.5 to Vee + 0.5

Volts

11K

Input Clamp Current

±20

mA

10K

Output Clamp Current

±20

mA

±25

mA

-65 to +150

°C

10K

Continuous Output Current

TSTG

Storage Temperature

Commercial

Parameter
Limits

Temperature
Rangel

o to

Power Supply
Tolerance

+70

Industrial

Military

Units

-40 to +85 -55 to +125
±10

±5

±10

°C
%Vcc

Note:
1. Ambient temperature (fA) used for commercial and industrial.
Case temperature (fe) used for military.

Stresses beyond those listed above may cause permanent damage to the
device. Exposure to absolute maximum rated conditions for extended
periods may affect device reliability. Device should not be operated
outside the Recommended Operating Conditions.
Notes:
1. V pp = Vee, except during device programming.
2. Vsv = Vee, except during device programming.
3. V KS = GND, except during device programming.

Electrical Specifications
Military

Industrial

Commercial

Units

Parameter
Min.
(IOH = -10 mA)2
VO Hl

(IOH = -6 mA)

Max.

Max.

Min.

Max.
V

2.4

V

3.84
3.7

3.7

(IOH = -4 mA)
VOl l

Min.

(IOl = 10 mA)2

0.5

(IOl = 6 mA)

0.33

V
0.40

VIL

-0.3

0.8

-0.3

VIH

2.0

Vee + 0.3

2.0

0.8
Vce

+ 0.3

0.40

V

-0.3

0.8

V

2.0

Vee + 0.3

V

500

ns

500

500

Input Transition Time tR, tF2

V

CIO I/O Capacitance2. 3

10

10

10

pF

Standby Current, lec4

10

20

25

mA

10

}JA

Leakage Currents

-10

10

-10

10

-10

Notes:
1. Only one output tested at a time. Vee = min.
2. Not tested, for information only.
3. Includes worst-case 176 CPGA package capacitance. V OUT = 0 V, f = 1 MHz.
4. All outputs unloaded. All inputs = Vee or GND, typical lee = 1 rnA.
5. Va, V IN = Vee or GND.

1-47

I

Package Thermal Characteristics
The device junction to case thermal characteristic is Ojc, and the
junction to ambient air characteristic is Oja. The thermal
characteristics for Oja are shown with two different air flow rates.

Maximum junction temperature is 150°C.
A sample calculation of the maximum power dissipation for a
CPGA 176-pin package at commercial temperature is as follows:

Max. junction temp. (0C) - Max. military temp. (0C)

=4.0W

Oja (OCIW)

Pin Count

Oje

Oja
Stili air

Oja
300 ft/mln.

Units

CPGA

100
132
176

5
5
2

35
30
20

17
15
8

°C/W
°C/W
°C/W

PQFP1

100
144
160

13
15
15

55
35
33

47
26
24

°C/W
°C/W
°C/W

PLCC

84

12

44

33

°C/W

Package Type

Note:
1. Maximum Power Dissipation for PQFP Package = 2.0 Watts

Power Dissipation
P = [Icc

+

lactive] •

Vee

+

10L·Vou N

+

10H·(Vee-V oH).M

Where:
Icc is the current flowing when no inputs or outputs are changing.
lactive

is the current flowing due to CMOS switching.

unprogrammed antifuses, module inputs, and module outputs plus
external capacitance due to PC board traces and load device inputs.
An additional component of active power dissipation is due to
totem-pole current in CMOS transistor pairs. The net effect can be
associated with an equivalent capacitance that can be combined
with frequency and voltage to represent active power dissipation.

10L' 10H are TTL sink/source currents.
VOL, V OH are TTL level output voltages.
N equals the number of outputs driving TTL loads to VOL.
M equals the number of outputs driving TTL loads to V OH.
An accurate determination of Nand M is problematical because
their values depend on the design and on the system I/O. The
power can be divided into two components: static and active.

Static Power
Static power dissipation is typically a small component of the
overall power. From the values provided in the Electrical
Specifications, the maximum static power (commercial) dissipation is:
10 rnA x 5.25 V = 52.5 mW
The static power dissipated by TTL loads depends on the number
of outputs that drive high or low and the DC lead current flowing.
Again, this number is typically small. For instance, a 32-bit bus
driving TTL loads will generate 42 mW ATT with all outputs
driving low or 140 mW with all outputs driving high. The actual
dissipation will average somewhere between as lIOs switch states
with time.

Active Power
The active power component in CMOS devices is frequency
dependent and depends on the user's logic and the external I/O.
Active power dissipation results from charging internal chip
capacitance such as that associated with the interconnect,

1-48

Equivalent Capacitance
The power dissipated by a CMOS circuit can be expressed by
Equation 1.
Power (}JW)

= CEQ. V ee2 • f

(1)

Where:
CEQ is the equivalent capacitance expressed in pF.
Vee is power supply in volts.
f is the switching frequency in MHz.
Equivalent capacitance is calculated by measuring Iactive at a
specified frequency and voltage for each circuit component of
interest. The results for ACT 2 devices are:
CEQ(PF)
Modules
Input Buffers
Output Buffers
Clock Buffer Loads

7.7
18.0
25.0
2.5

To calculate the active power that is dissipated from the complete
design, you must solve Equation 1 for each component. In order to
do this, you must know the switching frequency of each part of the
logic. The exact equation is a piece-wise linear summation over all
components, as shown in Equation 2.
Power

= [(m. 7.7. f1) +

(n • 18.0 • f2)

+ (q. 2.5 • t)] • V ee2

+ (p.

(25.0

+

C L). f3)
(2)

ACT 2 FPGAs
Estimated Power

Where:
n = Number of logic modules switching at frequency f1
m

Number of input buffers switching at frequency f2

p

Number of output buffers switching at frequency £3

q

Number of clock loads on the global clock network

The results of estimating active power are displayed in Figure 14.
The graphs provide a simple guideline for estimating power. The
tables may be interpolated when your application has different
resource utilizations or frequencies.

Frequency of global clock
Average logic module switching rate in MHz
Average input buffer switching rate in MHz
£3

A1240
3.0

/

2.0

Average output buffer switching rate in MHz

C L = Output load capacitance

A/
1.0

II

/ / V/

/

/

./

Determining Average Switching Frequency

[n order to determine the switching frequency for a design, you
must have a detailed understanding of the data input values to the
~ircuit. The following rules will help you to determine average
;witching frequency in logic circuits. These rules are meant to
represent worst-case scenarios so that they can be generally used
:Or predicting the upper limits of power dissipation. These rules are
is follows:

//

/

/

/

V //
/ / /
V
/ /

/

0.1

Module Utilization = 80% of combinatorial modules

./

/

/

/

A1225

./

/

Average Module Frequency = F/l0
Inputs = 1/3 of I/O

//

V

/

Average Input Frequency = F/5
Outputs = 2/3 of I/Os
Average Output Frequency = FIlO

1.0

10.0

100.0

MHz

Clock Net 1 Loading = 40% of sequential modules
Clock Net 1 Frequency = F

Figure 14. ACT 2 Power Estimates

Clock Net 2 Loading = 40% of sequential modules
Clock Net 2 Frequency = F/2

1-49

•

Parameter Measurement
Output Buffer Delays

D

To AC test loads (shown below)

Vee

Vee
GND

GND

GND

Vee
PAD

PAD

PAD
GND

VOL
tDLH

tDHL

teNZL

t ENZH

teNLZ

teN HZ

AC Test Loads
Load 1
(Used to measure propagation delay)

Load 2
(Used to measure rising/failing edges)
GND

Vee

)>--------'l

T

•

•

To the output under test

OOPF

R to Vee for tpLZ/tpZL
R to GND for tpHZ/tPZH

To the output under test

>----.

T
Input Buffer Delays

R = 1 kQ
SOPF

Combinatorial
Macro Delays

Vee

y

...... VSO%

------

...... I\.. 50%

GND

y

Vee

SO~"

GND

tpHL
tlNYH

1-50

tlNYL

GND
tpLH

...... "'50%

ACT 2 FPGAs

Sequential Timing Characteristics
Flip-Flops and Latches

PRE

D

Q

E

ClK

ClR
(Positive edge triggered)

--I

tHO

I-

Dl ____~)(~______________________)(~-------------

I--- --I

I.

tsuo

ClK ______________~-1---~~

t

WCLKA

-I

______~

--I

tSUENA

r-

I----

I. .·f-----

I
tWCLKI

tA ----1--11

~____~~

---1

HtHENA

E

--------------------------------~

I

I

I-tco-/
Q------------------------------~)(------)(~--------______--,1 .. tsuASYN-1
PRE,ClR

r-

I~------------------------------~I

t

po

.,

~I___________

I.. tWASYN .. I
Notes:
1. D represents all data functions involving A, B, and S for multiplexed flip-flops.

1-51

Sequential Timing Characteristics (continued)
Input Buffer Latches

IBDL

CLK

X

PAD

G

X

~

tlNH

I

~

I-

tlNSU

~

tHEXT

I

CLK

rr-

~

tSUEXT

Output Buffer Latches

:~OOOLHSr__

~x~

~

________________
toUTSU

I-

----------------~~I
~

1-52

~x~

___

_______________
toUTH

ACT 2 FPGAs

Long Tracks

Timing Characteristics
Timing characteristics for ACT arrays fall into three categories:
family dependent, device dependent, and design dependent. The
output buffer characteristics are common to all ACT 2 family
members. Internal module delays are device dependent. Internal
wiring delays between modules are design dependent. Design
dependency means actual delays are not determined until after
placement and routing of the users design is complete. Delay values
may then be determined by using the ALS Timer utility or
performing simulation with post-layout delays.
The macro propagation delays shown in the Timing Characteristics
tables include the module delay plus estimates derived from
statistical analysis for wiring delay. This statistical estimate is based
on fully utilized devices (90% module utilization).
Critical Nets and Typical Nets

Propagation delays are expressed for two types of nets: critical and
typical. Critical nets are determined by net property assignment before
placement and routing. Up to 6% of the nets in a design may be
designated as critical, while 90% of the nets in a design are typical.
Fan-Out Dependency

Pl'opagation delays depend on the fan-out (number ofloads) driven
by a macro. Delay time increases when fan-out increases due to the
capacitive loading of the macro's inputs, as well as the
interconnect's resistance and capacitance.

Some nets in the design use long tracks. Long tracks are special
routing resources that span multiple rows or columns or modules,
and are used frequently in large fan-out (> 10) situations. Long
tracks employ three and sometimes four antifuse connections. This
increased capacitance and resistance results in longer net delays for
macros connected to long tracks. Typically up to 6% of the nets in a
fully utilized device require long tracks. Long tracks contribute an
additional 10 ns to 15 ns delay.

Timing Derating
Operating temperature, operating voltage, and device processing
conditions, along with device die size and speed grade, account for
variations in array timing characteristics. These variations are
summarized into a derating factor for ACT 2 array typical timing
specifications. The derating factors shown in the table below are
based on the recommended operating conditions for ACT 2
applications. The derating curves in Figure 15 show worst-to-best
case operating voltage range and best-to-worst case operating
temperature range. The temperature derating curve is based on
device junction temperature. Actual junction temperature is
determined from Ambient Temperature, Power Dissipation, and
Package Thermal characteristics.

Timing Derating Factor (x typical)
Commercial

Industrial

Military

Best-Case

Worst-Case

Best-Case

Worst-Case

Best-Case

Worst-Case

0.40

1.40

0.37

1.50

0.35

1.6

Note:
"Best-case" reflects maximum operating voltage, minimum operating
temperature, and best-case processing. "Worst-case" reflects minimum
operating voltage, maximum operating temperature, and worst-case

processing. Best-case derating is based on sample data only and is not
guaranteed.

Voltage Derating Curve

Temperature Derating Curve

1.20

1.40

1.15

1.30

1.10
1.20

.90

~

1.05

~

1.00

........

j

~

f" . . .

0.95

~

1.10

~

1.00

.........

~

0.90

0.90

I

0.80
4.5

4.75

5.0

5.25

0.70
-60

5.5

Vee (Volts)

~"

~~

~ ....

",'"

0.80

0.85

~~

~

-40 -20

0

20

40

60

80

100 120

Junction Temperature (0C)

Figure 15. Operating Curves

1-53

•

~
A 1280 Timing Characteristics
Propagation Delays Ncc
Parameter

= 5.0 V; TJ = 25°C;

Description

Process

= Typical; Derating Required)

Output Net

FO

=1

FO

=2

FO

=3

FO

=4

tp01

Single Module

Critical

4.5

5.0

5.5

6.0

t p01

Single Module

Typical

5.7

6.2

6.7

8.2

t p02

Dual Module

Critical

7.5

8.0

8.5

9.0

t p02

Dual Module

Typical

8.7

9.2

9.7

11.2

teo

Sequential Clk to Q

Critical

4.5

5.0

5.5

6.0

teo

Sequential Clk to Q

Typical

5.7

6.2

6.7

8.2

~o

Latch G to Q

Critical

4.5

5.0

5.5

6.0

~o

Latch G to Q

Typical

5.7

6.2

6.7

8.2

t po

Asynchronous to Q

Critical

4.5

5.0

5.5

6.0

tpo

Asynchronous to Q

Typical

5.7

6.2

6.7

8.2

FO

=8

Units
ns

11.7

ns

14.7

ns

ns

ns
11.7

ns
ns

11.7

ns
ns

11.7

ns

Sequential Timing Characteristics (Over Worst-Case Recommended Operating Conditions; No Further Derating Required)

Parameter

Description

Commercial
Min.
Max.

tsuo

Flip-Flop (Latch) Data Input Setup

0.4

0.5

1.0

ns

tSUASYN

Flip-Flop (Latch) Asynchronous Input Setup

1.0

1.5

2.0

ns

tHO

Flip-Flop (Latch) Data Input Hold

tSUENA

Flip-Flop (Latch) Enable Setup

tHENA

Flip-Flop (Latch) Enable Hold

t WCLKA

Flip-Flop (Latch) Clock Active Pulse Width

tWASYN

Flip-Flop (Latch) Asynchronous Pulse Width

tA

Flip-Flop Clock Input Period

tlNH

Input Buffer Latch Hold

tlNsU

Input Buffer Latch Setup

toUTH

Output Buffer Latch Hold

toUTSU

Output Buffer Latch Setup

fMAX

Flip-Flop (Latch) Clock Frequency

0.0
1.0

Military
Min.
Max.

0.0

0.0

0.0
2.0

1.5

4.0

0.0
4.5

ns

4.5

5.0
22.0
2.5

-3.0
0.0

0.4
48.0

ns
2.5

-3.5
0.0

0.5

ns
ns

0.0

ns

39.0

MHz

1.0
43.0

ns
ns

20.0

-2.5

ns
ns

0.0

4.0

2.0

Units

5.0

18.0

Notes:
1. Data applies to macros based on the sequential (S-type) module. Timing
parameters for sequential macros constructed from C- type modules can
be obtained from the ALS Timer utility.

1-54

Industrial
Min.
Max.

ns

2. Setup and hold timing parameters for the Input Buffer Latch are
defined with respect to the PAD and the G input. External setuplhold
timing parameters must account for delay from an external PAD signal
to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.

ACT 2 FPGAs

A 1280 Timing Characteristics (continued)
I/O Buffer Timing 0Icc

= 5.0 V; TJ = 25°C; Process = Typical; Derating Required)

=1

=2

=3

=4

=8

Units

Parameter

Description

tlNYH

Pad to Y High

6.7

7.2

7.7

8.2

11.7

ns

t lNYL

Pad to Y Low

6.6

7.1

7.6

8.1

11.5

ns

tlNGH

G to Y High

6.6

7.2

7.7

8.2

11.7

ns

t lNGL

GtoYLow

6.4

6.9

7.5

8.0

11.4

ns

FO

Global Clock Network 0Icc

FO

FO

FO

FO

= 5.0 V; TJ = 25°C; Process = Typical; Derating Required)

= 32

= 128

Parameter

Description

FO =384

Units

tcKH

Input Low to High

9.1

10.1

12.3

ns

tcKL

Input High to Low

9.1

10.2

12.5

ns

tpWH

Minimum Pulse Width High

4.0

4.5

5.0

ns

tpWL

Minimum Pulse Width Low

4.0

4.5

5.0

ns

FO

FO

tcKSW

Maximum Skew

0.5

1.0

2.5

ns

tsuEXT

Input Latch External Setup1

0.0

0.0

0.0

ns

tHEXT

Input Latch Extemal Hold 1

7.0

8.0

11.2

ns

tp

Minimum Period

13.3

14.3

15.3

ns

fMAX

Maximum Frequency

75.0

70.0

65.0

MHz

•

Note:
1. Derating does not apply to this parameter.
Output Buffer Timing 0Iec
Parameter

Description

= 5.0 V; TJ = 25°C; Process = Typical; Derating Required)
TTL

CMOS

Units

tOLH

Data to Pad High

4.6

6.7

ns

tOHL

Data to Pad Low

6.5

4.9

ns

tENZH

Enable Pad Z to High

8.3

8.3

ns

tENZL

Enable Pad Z to Low

5.5

5.5

ns

tENHZ

Enable Pad High to Z

4.5

4.5

ns

tENLZ

Enable Pad Low to Z

6.0

6.0

ns
ns

fQLH

G to Pad High

4.6

4.6

fQHL

G to Pad Low

6.5

6.5

ns

d TLH

Delta Low to High

0.06

0.11

ns/pF

d THL

Delta High to Low

0.11

0.08

ns/pF

1-55

A 1280-1 Timing Characteristics
Propagation Delays 01cc = 5.0 V; TJ = 25°C; Process

= Typical; Derating Required)

Output Net

=1

=2

=3

=4

Parameter

Description

tp01

Single Module

Critical Net

3.9

4.3

4.8

5.3

tp01

Single Module

Typical Net

4.9

5.3

5.7

7.0

FO

FO

FO

FO

t p02

Dual Module

Critical Net

7.5

8.0

8.5

9.0

t p02

Dual Module

Typical Net

7.9

8.3

8.7

10.0

too

Sequential Clk to Q

Critical Net

3.9

4.3

4.8

5.3

too

Sequential Clk to Q

Typical Net

4.9

5.3

5.7

7.0

too
too

Latch G to Q

Critical Net

3.9

4.3

4.8

5.3

Latch G to Q

Typical Net

4.9

5.3

5.7

7.0

tpo

Asynchronous to Q

Critical

3.9

4.3

4.8

5.3

tpo

Asynchronous to Q

Typical

4.9

5.3

5.7

7.0

FO

=8

Units
ns

10.0

ns
ns

13.0

ns

10.0

ns

10.0

ns

10.0

ns

ns

ns

ns

Sequential Timing Characteristics (Over Worst-Case Recommended Operating Conditions; No Further Derating Required)
Commercial

Industrial
Min.
Max.

Military
Min.
Max.

Parameter

Description

Min.

tsuo

Flip-Flop (Latch) Data Input Setup

0.4

0.5

1.0

tSUASYN

Flip-Flop (Latch) Asynchronous Input Setup

1.0

1.5

2.0

tHO

Flip-Flop (Latch) Data Input Hold

tSUENA

Flip-Flop (Latch) Enable Setup

Max.

0.0
1.0

0.0
1.5

Units
ns
ns

0.0
2.0

ns
ns

tHENA

Flip-Flop (Latch) Enable Hold

tWCLKA

Flip-Flop (Latch) Clock Active Pulse Width

4.0

4.5

5.0

ns

tWASYN

Flip-Flop (Latch) Asynchronous Pulse Width

4.0

4.5

5.0

ns

tA

Flip-Flop Clock Input Period

tlNH

Input Buffer Latch Hold

tlNSU

Input Buffer Latch Setup

toUTH

Output Buffer Latch Hold

toUTsU

Output Buffer Latch Setup

fMAX

Flip-Flop (Latch) Clock Frequency

0.0

15.0

18.0
2.0

-2.5
0.0

20.0

0.0

ns
ns

0.0
1.0

60.0

ns

ns
2.5

-3.5

0.5
65.0

0.0

2.5
-3.0

0.4

Notes:
1. Data applies to macros based on the sequential (S-type) module. Timing
parameters for sequential macros constructed from C-type modules can
be obtained from the AI.S Timer utility.

1-56

0.0

ns
ns

50.0

MHz

2. Setup and hold timing parameters for the Input Buffer Latch are
defined with respect to the PAD and the G input. External setuplhold
timing parameters must account for delay from an external PAD signal
to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.

ACT 2 FPGAs

A 1280-1 Timing Characteristics (continued)
1/0 Buffer Timing 01cc

= 5.0 V; TJ = 25°C;

Parameter

Description

Process = Typical; Derating Required)
FO = 1

FO = 2

FO = 3

FO = 4

FO = 8

Units

tlNYH

Pad to Y High

6.1

6.5

5.9

7.4

10.5

ns

t lNYL

Pad to Y Low

5.9

6.4

6.8

7.3

10.4

ns

t lNGH

G to Y High

tlNGL

GtoYLow

6.1

6.5

5.9

7.4

10.5

ns

5.9

6.4

6.8

7.3

10.4

ns

Units

Global Clock Network 01cc = 5.0 V; TJ = 25°C; Process = Typical; Derating Required)
Parameter

Description

FO = 128

FO =384

tcKH

Input Low to High

7.8

8.7

10.4

ns

tcKL

Input High to Low

7.8

8.8

10.6

ns
ns

FO = 32

t pWH

Minimum Pulse Width High

4.0

4.5

5.0

tpWL

Minimum Pulse Width Low

4.0

4.5

5.0

ns

tcKSW

Maximum Skew

0.5

1.0

2.5

ns

tsuEXT

Input Latch External Setup 1

0.0

0.0

0.0

ns

7.0

8.0

11.2

ns

tHEXT

Input Latch External Hold 1

tp

Minimum Period

11.4

12.0

13.0

ns

fMAX

Maximum Frequency

89.0

83.0

77.0

MHz

•

Note:
1. Derating does not apply to this parameter.
Output Buffer Timing 01cc = 5.0 V; TJ = 25°C; Process = Typical; Derating Required)
Parameter

Description

tDLH

Data to Pad High

4.6

6.7

ns

tDHL

Data to Pad Low

6.5

4.9

ns

tENZH

Enable Pad Z to High

8.3

8.3

ns

t ENZL

Enable Pad Z to Low

5.5

5.5

ns
ns

TTL

CMOS

Units

tENHZ

Enable Pad High to Z

4.5

4.5

tENLZ

Enable Pad Low to Z

6.0

6.0

ns

~LH

G to Pad High

4.6

4.6

ns

~HL

G to Pad Low

6.5

6.5

ns

d TLH

Delta Low to High

0.06

0.11

ns/pF

d THL

Delta High to Low

0.11

0.08

ns/pF

1-57

PRELIMINARY DATA

A 1240 liming Characteristics
Propagation Delays

01cc = 5.0 V; TJ = 25°C;

Process

= Typical; Derating Required)

Output Net

=1

=2

FO

=3

FO

=4

Parameter

Description

tpOl

Single Module

Critical Net

3.9

4.3

4.8

5.3

tpOl

Single Module

Typical Net

4.9

5.3

5.7

7.0

FO

FO

tp02

Dual Module

Critical Net

7.5

8.0

8.5

9.0

t p02

Dual Module

Typical Net

7.9

8.3

8.7

10.0

teo

Sequential Clk to Q

Critical Net

3.9

4.3

4.8

5.3

teo

Sequential Clk to Q

Typical Net

4.9

5.3

5.7

7.0

~o

Latch G to Q

Critical Net

3.9

4.3

4.8

5.3

~o

Latch G to Q

Typical Net

4.9

5.3

5.1

1.0

tpo

Asynchronous to Q

Critical

3.9

4.3

4.8

5.3

tpo

Asynchronous to Q

Typical

4.9

5.3

5.7

1.0

FO

=8

Units
ns

10.0

ns

13.0

ns

10.0

ns

10.0

ns

10.0

ns

ns

ns

ns

ns

Sequential Timing Characteristics (Over Worst-Case Recommended Operating Conditions; No Further Derating Required)
Industrial

Commercial
Max.

Min.

Description

Min.

tsuo

Flip-Flop (Latch) Data Input Setup

0.4

0.5

1.0

tSUASYN

Flip-Flop (Latch) Asynchronous Input Setup

1.0

1.5

2.0

tHO

Flip-Flop (Latch) Data Input Hold

tsuENA

Flip-Flop (Latch) Enable Setup

tHENA

Flip-Flop (Latch) Enable Hold

0.0
1.0

Max.

Military

Parameter

Min.

0.0
1.5

0.0

Max.

ns
ns
0.0

ns

0.0

ns

2.0
0.0

Units

ns

tWCLKA

Flip-Flop (Latch) Clock Active Pulse Width

4.0

4.5

5.0

ns

tWASYN

Flip-Flop (Latch) Asynchronous Pulse Width

4.0

4.5

5.0

ns

tA

Flip-Flop Clock Input Period

~NH

Input Buffer Latch Hold

tlNSU

Input Buffer Latch Setup

taUTH

Output Buffer Latch Hold

taUTsU

Output Buffer Latch Setup

fMAX

Flip-Flop (Latch) Clock Frequency

15.0

-2.5

20.0
2.5

-3.0
0.0

0.4

Notes:
1. Data applies to macros based on the sequential (S-type) module. Timing
parameters for sequential macros constructed from C-type modules can
be obtained from the ALS Timer utility.

1-58

18.0
2.0

-3.5
0.0

0.5
66.0

ns
2.5

ns
0.0

ns
ns

1.0
55.0

ns

50.0

MHz

2. Setup and hold timing parameters for the Input Buffer Latch are
defined with respect to the PAD and the G input. External setuplhold
timing parameters must account for delay from an external PAD signal
to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.

ACT 2 FPGAs

PRELIMINARY DATA

A 1240 Timing Characteristics (continued)
1/0 Buffer Timing Nee = 5.0 V: TJ = 25°C: Process = Typical: Derating Required)
Parameter

Description

FO = 1

FO = 2

FO = 3

FO = 4

FO = 8

t lNYH

Pad to Y High

6.1

6.5

5.9

7.4

10.5

ns

t lNYL

Pad to Y Low

5.9

6.4

6.8

7.3

10.4

ns

t lNGH

G to Y High

6.1

6.5

5.9

7.4

10.5

ns

5.9

6.4

6.8

7.3

10.4

ns

Units

t lNGL

GtoYLow

Global Clock Network Nee

= 5.0 V: TJ = 25°C:

Process

Units

= Typical: Derating Required}

Parameter

Description

FO = 128

FO =256

tcKH

Input Low to High

9.1

10.1

11.2

ns

tcKL

Input High to Low

9.1

10.2

11.3

ns
ns

FO = 32

tPWH

Minimum Pulse Width High

4.0

4.5

5.0

t PWL

Minimum Pulse Width Low

4.0

4.5

5.0

ns

tcKSW

Maximum Skew

0.5

1.0

2.5

ns

tsuEXT

Input Latch External Setup 1

0.0

0.0

0.0

ns

tHEXT

Input Latch External Hold 1

7.0

8.0

11.2

ns

tp

Minimum Period

11.1

11.5

11.8

ns

fMAX

Maximum Frequency

90.0

87.0

85.0

MHz

Note:
1. Derating does not apply to this parameter.
Output Buffer Timing Nee
Parameter

Description

= 5.0 V: TJ = 25°C:

Process

= Typical:
TTL

I

Derating Required)
CMOS

Units

tOLH

Data to Pad High

4.6

6.7

ns

tOHL

Data to Pad Low

6.5

4.9

ns

t ENZH

Enable Pad Z to High

8.3

8.3

ns

t ENZL

Enable Pad Z to Low

5.5

5.5

ns

tEN HZ

Enable Pad High to Z

4.5

4.5

ns

tENLZ

Enable Pad Low to Z

6.0

6.0

ns

toLH

G to Pad High

4.6

4.6

ns

toHL

G to Pad Low

6.5

6.5

ns

d TLH

Delta Low to High

0.06

0.11

ns/pF

d THL

Delta High to Low

0.11

0.08

ns/pF

1-59

~
PRELIMINARY DATA

A 1240·1 Timing Characteristics
Propagation Delays 01cc

= 5.0 V; TJ = 25°C; Process = Typical; Derating Required)
Output Net

=1

=2

=3

Description
Single Module

Critical Net

3.5

3.9

4.3

4.8

tp01

Single Module

Typical Net

4.4

4.8

5.1

6.3

tp02

Dual Module

Critical Net

7.5

8.0

8.5

9.0

t p02

Dual Module

Typical Net

7.4

7.8

8.1

9.3

teo
teo
too
tao

Sequential elk to Q

Critioal Net

3.5

3.9

4.3

4.8

Sequential Clk to Q

Typioal Net

4.4

4.8

5.1

6.3

!Po
tpo

FO

FO

FO

FO

=4

Parameter
t po1

Latch G to Q

Critical Net

3.5

3.9

4.3

4.8

Latch G to Q

Typical Net

4.4

4.8

5.1

6.3

Asynchronous to Q

Critical

3.5

3.9

4.3

4.8

Asynchronous to Q

Typical

4.4

4.8

5.1

6.3

FO

=8

Units
ns

9.0

ns
ns

12.0

ns

9.0

ns

9.0

ns

ns

ns

ns
9.0

ns

Sequential Timing Characteristics (Over Worst-Case Recommended Operating Conditions; No Further Derating Required)

Parameter

Description

Commercial
Min.
Max.

tsuo

Flip-Flop (Latch) Data Input Setup

0.4

0.5

1.0

tSUASYN

Flip-Flop (Latch) Asynchronous Input Setup

1.0

1.5

2.0

tHO

Flip-Flop (Latch) Data Input Hold

tsuENA

Flip-Flop (Latch) Enable Setup

tHENA

Flip-Flop (Latch) Enable Hold

tWCLKA

Flip-Flop (Latch) Clock Active Pulse Width

4.0

4.5

5.0

tWASYN

Flip-Flop (Latch) Asynchronous Pulse Width

4.0

4.5

5.0

ns

tA

Flip-Flop Clock Input Period

13.0

15.0

18.0

ns

~NH

Input Buffer Latch Hold

tlNSU

Input Buffer Latch Setup

touTH

Output Buffer Latch Hold

toUTSU

Output Buffer Latch Setup

fMAX

Flip-Flop (Latch) Clock Frequency

0.0
1.0

1.5

2.5
-3.0

0.0
0.4

0.5
75.0

ns
0.0

ns

0.0

ns

ns

ns

2.5
-3.5

0.0

ns
ns

0.0

ns

55.0

MHz

1.0
66.0

Units
ns

2.0
0.0

2.0
-2.5

Military
Min.
Max.

0.0

0.0

Notes:
1. Data applies to macros based on the sequential (S-type) module. TIming
parameters for sequential macros constructed from C-type modules can
be obtained from the ALS Timer utility.

1-60

Industrial
Min.
Max.

ns

2. Setup and hold timing parameters for the Input Buffer Latch are
defined with respect to the PAD and the G input. External setuplhold
timing parameters must account for delay from an external PAD signal
to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.

ACT 2 FPGAs
PRELIMINARY DATA

A 1240-1 Timing Characteristics (continued)
I/O Buffer Timing 0/cc

= 5.0 V; TJ = 25°C;

Process

= Typical; Derating Required)
FO

=1

FO

=2

FO = 3

FO = 4

FO = 8

Units

Parameter

Description

t lNYH

Pad to Y High

5.5

5.9

5.3

6.7

9.5

ns

t lNYL

Pad to Y Low

5.3

5.8

6.1

6.6

9.4

ns

tlNGH

G to Y High

5.5

5.9

5.3

6.7

9.5

ns

5.3

5.8

6.1

6.6

9.4

ns

Units

t lNGL

GtoYLow

Global Clock Network 0/cc
Parameter

= 5.0 V; TJ = 25°C;

Process

= Typical; Derating Required)
FO = 32

Description

FO = 128

FO =256

8.7

9.3

ns

tcKH

Input Low to High

7.8

tcKL

Input High to Low

7.8

8.8

9.4

ns
ns

tPWH

Minimum Pulse Width High

4.0

4.5

5.0

t pWL

Minimum Pulse Width Low

4.0

4.5

5.0

ns

tcKSW

Maximum Skew

0.5

1.0

2.5

ns

tsuEXT

Input Latch External Setup 1

0.0

0.0

0.0

ns

tHEXT

Input Latch External Hold 1

7.0

8.0

11.2

ns

tp

Minimum Period

fMAX

Maximum Frequency

9.1

19.5

10.0

ns

110.0

105.0

100.0

MHz

I

Note:

1. Derating does not apply to this parameter.
Output Buffer Timing 0/cc

= 5.0 V; TJ = 25°C;

Process

= Typical; Derating Required)

Parameter

Description

TTL

tOLH

Data to Pad High

4.6

6.7

ns

tOHL

Data to Pad Low

6.5

4.9

ns
ns

CMOS

Units

t ENZH

Enable Pad Z to High

8.3

8.3

tENZL

Enable Pad Z to Low

5.5

5.5

ns

tENHZ

Enable Pad High to Z

4.5

4.5

ns

tENLZ

Enable Pad Low to Z

6.0

6.0

ns

loLH

G to Pad High

4.6

4.6

ns

loHL

G to Pad Low

6.5

6.5

ns

d TLH

Delta Low to High

0.06

0.11

ns/pF

dTHL

Delta High to Low

0.11

0.08

ns/pF

1-61

PRELIMINARY DATA

A 1225 Timing Characteristics
Propagation Delays C'lcc = 5.0 V; TJ = 25°C; Process = Typical; Derating Required)
Parameter

Description

FO = 1

FO = 2

FO = 3

FO = 4

tpDl

Single Module

Critical Net

3.9

4.3

4.8

5.3

t pD1

Single Module

Typical Net

4.9

5.3

5.7

7.0

Output Net

tpD2

Dual Module

Critical Net

7.5

8.0

8.5

9.0

tpD2

Dual Module

Typical Net

7.9

8.3

8.7

10.0

teo

Sequential Clk to

teo

Sequential Clk to

~o

Latch G to

~o

a
Latch G to a

tpD

Asynchronous to

t PD

Asynchronous to

a
a
a
a

Critical Net

3.9

4.3

4.8

5.3

Typical Net

4.9

5.3

5.7

7.0

Critical Net

3.9

4.3

4.8

5.3

Typical Net

4.9

5.3

5.7

7.0

Critical

3.9

4.3

4.8

5.3

Typical

4.9

5.3

5.7

7.0

FO = 8

Units

10.0

ns

13.0

ns

ns

ns

ns
10.0

ns

10.0

ns

10.0

ns

ns

ns

Sequential Timing Characteristics (Over Worst-Case Recommended Operating Conditions; No Further Derating Required)
Industrial

Commercial
Parameter

Description

Min.

tSUD

Flip-Flop (Latch) Data Input Setup

0.4

0.5

tSUASYN

Flip-Flop (Latch) Asynchronous Input Setup

1.0

1.5

tHD

Flip-Flop (Latch) Data Input Hold

tSUENA

Flip-Flop (Latch) Enable Setup

tHENA

Flip-Flop (Latch) Enable Hold

Max.

Min.

0.0
1.0

Max.

ns
ns
0.0

ns

0.0

ns

1.5
0.0

Units

ns

tWCLl «I> ClKorG, ,  ClR,  PRE)

< !>

Optional Inversion

ClK

Flip-Flop Clock Pin

G

Latch Gate Pin

CLR

Asynchronous Clear Pin

PRE

Asynchronous Preset Pin

Notes:
1. A space between the 'N. and 'B' in the equation
Y = ABmeansAANDB.
2. Order of operators in decreasing precedence is: NOT, AND, XOR,
and OR.
3. Signals expressed in bold have a dual module delay.

ACT 2 Macro Selections
I/O Macros
No. of Modules

Macro Name
1/0

Description
Clock

INBUF

Input

IBDL

Input with Input Latch

BBDLHS

Bidirectional with Input Latch and Output Latch

BBHS

Bidirectional

BIBUF

Bidirectional

CLKBIBUF

Bidirectional with Input Dedicated to Clock Network

CLKBUF

Input for Dedicated Clock Network

OBDLHS

Output with Output Latch

OBHS

Output

OUTBUF

Output

TBDLHS

Three State Output with Latch

TBHS

Three State Output

TRIBUFF

Three State Output

Note:
The following are functionally identical:
OBHS and OUTBUF; TRIBUFF and TBHS; BBHS and BlBUE

1-66

ACT 2 FPGAs

TTL Macros
No. of Modules
Macro Name

Description

Logic Levels
Seq.

TAOO
TA02
TA04
TA07
TA08
TA10
TA11
TA20
TA21
TA27
TA32
TA40
TA42
TA51
TA54
TA55
TA86
TA138
TA139
TA150
TA151
TA153
TA154
TA157
TA160
TA161
TA164
TA169
TA174
TA175
TA190
TA191
TA194
TA195
TA269
TA273
TA280
TA377
TA688

2-input NAND
2-input NOR
Inverter
Buffer
2-inputAND
3-input NAND
3-inputAND
4-input NAND
4-input AND
3-input NOR
2-input OR
4-input NAND
4 to 10 decoder
AND-DR-Invert
4-wide AND-DR-Invert
2-wide 4-input AND-DR-Invert
2-input exclusive OR
3 to 8 decoder with enable and active low outputs
2 to 4 decoder with enable and active low outputs
16 to 1 multiplexor
8 to 1 multiplexor with enable and active low outputs
4 to 1 multiplexor
4 to 16 decoder
2 to 1 multiplexor
4-bit decode counter with clear
4-bit binary counter with clear
8-bit serial in, parallel out shift register
4-bit up/down counter
Hex D-type flip-flop with clear
Quadruple D-type flip-flop with clear
4-bit up/down decode counter with up/down mode
4-bit up/down binary counter with up/down mode
4-bit shift register
4-bit shift register
8-bit up/down binary counter
Octal register with clear
Parity generator and checker
Octel register with active low enable
8-bit identity comparator

Comb.

1
2
1
1
2
10
2
5
3

1
2
2
1
2

12
4
6

3
3
2
2
4
3
1

6

5
2
22
4
4
8
4

12
10
14

6
1
7
7
1
8
1
4
1
3

4
4
4
4
4
8
8

31
30
4
1
28

9
8
9

1-67

•

~
Soft Macros
No. of Modules
Logic Levels

Function

Description

Macro Name

Counters

4-bit binary counter with load, clear
4-bit binary counter with load, clear, carry in, carry out
4-bit up/down counter with load, carry in, and carry out
very fast 16-bit down counter
2-bit down counter, prescaler
2-bit down counter, most significant bit
4-bit down counter, middle bits
4-bit down counter, low order bits

CNT4A
CNT4B
UDCNT4A
VCNT16C
VCNT2CP
VCNT2CU
VCNT4C
VCNT4CL

2 to 4 decoder
2 to 4 decoder with active low outputs
3 to 8 decoder
3 to 8 decoder with active low outputs
4 to 16 decoder with active low outputs
2 to 4 decoder with enable
2 to 4 decoder with enable and active low outputs
3 to 8 decoder with enable
3 to 8 decoder with enable and active low outputs

o EC2X4
o EC2X4A
o EC3X8
oEC3X8A

Registers

octal latch with clear
octal latch with enable
octal latch with multiplexed data
4-bit shift register with clear
8-bit shift register with clear

DLC8A
DLE8
DLM8
SREG4A
SREG8A

Adders

8-bit adder
9-bit adder
10-bit adder
12-bit adder
16-bit adder
2-bit sum generator
very fast 16-bit adder

FADD8
FADD9
FADD10
FADD12
FADD16
SUMX1A
VADD16C

Comparators

4-bit identity comparator
8-bit identity comparator
2-bit magnitude comparator with enable
4-bit magnitude comparator with enable
8-bit magnitude comparator with enable

ICMP4
ICMP8
MCMPC2
MCMPC4
MCMPC8

2
3
3
4
6

Multiplexors

8 to 1 multiplexor
8 to 1 multiplexor with active low outputs
16 to 1 multiplexor

MX8
MX8A
MX16

2
2
2

Decoders

1-68

DEC4X16A
DECE2X4
DECE2X4A
DECE3X8
DECE3X8A

4
4

5

Seq.

Comb.

4
4
4
34

8
7
13
31
2
3
8
7

5
2
4
4

4
4
8
8
20
4
4
11
11

1
2
1
2
2
8
8
8
4
8
3
3
3
4

5

44
49
56
69
97

2
3

97

5
5
5
9
18
36
3
3

5

ACT 2 FPGAs

Combinable Hard Macros 1 (for DF1, DF1 B, DFC1 B, DFC1 D, DL1, DL1B, DLC, and OLCA)
No. of Modules
Description

Macro Name

Equation(s)

2-input

AND2
AND2A
AND2B
AND3B

Y
Y
Y
Y

AND-OR

A01A
AOm

Y = «!A) B) + C
Y = (!A !B) + C

AND-OR Invert

AOlm

Y = !((!A !B) + !C)

Buffers and
Inverters

BUF
BUFA
INV
INVA

Y=A
Y = !(!A)
Y =!A
Y =!A

Clock Net
Interface

GAND2
GNOR2
GOR2

Y=AG
Y = !(A + G)
Y=A+G

2:1

MX2

Y = (A IS) + (B S)

2-input

NAND2A
NAND2B

Y = !(!AB)
Y = !(!A !B)

3-input

NAND3C

Y = !(!A !B !C)

2-input

NOR2
NOR2A
NOR2B

Y = I(A + B)
Y = !(!A + B)
Y = !(!A +!B)

Function

AND

Multiplexor

NAND

NOR

Seq.

Comb.

= AB
= IA B
=!A!B
= !A!B C

3-input

NOR3A

Y = !(!A + B + C)

OR-AND

OA1

Y = (A + B) C

2-input
OR

OR2
OR2A

Y=A+B
Y = !A + B

3-input

OR3

Y=A+B+C

I

1-69

Combinable Hard Macros 2 (for DF1, DF1 B, DFC1 B, DFC1D, DL1, and DL1B)
No. of Modules
Description

Macro Name

Equatlon(s)

3-input

AND3
AND3A
AND3C

Y=ABC
Y = !A B C
Y = !A!B!C

4-input

AND4B
AND4C

Y = !A!B CD
Y = !A!B!C 0

AND-OR

A01
A01B
A01C
A01E
A011
A02
A02A
A02B
A02C
A02D
A03
A03B
A03C
A04A
A05A

Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y

=
=
=
=
=
=
=
=
=
=
=
=
=
=
=

(A B) + C
(A B) + (!C)
((!A) B) + (!C)
(!A !B) + !C
A B + ((A + B) C)
((A B) + C + D)
((!A B) + C + D)
(!A !B) + C + D
(!A B) + !C + 0
(!A !B) + !C + D
(!A B C) + D
(!A !B C) + D
(!A !B !C) + D
(!A B C) + (A C D)
(!A B) + (A C) + D

AND-OR Invert

AOl1A
AOl1B
AOl1C
AOI2A
AOl3A

Y
Y
Y
Y
Y

=
=
=
=
=

!((!A B) + C)
!((A B) + !C)
!((!A !B) + C)
!((!A B) + C + D)
!((!A !B !C)+(!A !D)

AX1B

Y = (!A !B) " C

CS2
CY2B

Y = !((A + S) B) C + ((A + S) B) D
Y = A1 B1 + (AO+BO) A1 + (AO+BO) B1

Function

AND

Exclusive OR

XNOR. AND-XOR

Boolean

GNAND2
GXOR2

Y = (DO ISO !G) + (01 !G SO)
+ (D2 G ISO) + (D3 SO G)
Y = !(AG)
Y=A"G

MAJ3

Y = (A B) + (B C) + (A C)

MX2A
MX2C

Y = (!A IS) + (BS)
Y = (!A IS) + (!BS)

MX4

Y = (DO ISO !S1) + (D1 SO !S1)
+ (D2 ISO S1) + (D3 SO S1)

2-input

NAND2

Y = !(AS)

3-input

NAND3A
NAND3S

Y = !(!A B C)
Y = !(!A !BC)

4-input

NAND4C
NAND4D

Y = !(!A !S !C D)
Y = !(!A !S !C !D)

3-input

NOR3
NOR3S
NOR3C

Y = !(A + S + C)
Y = !(!A + !S + C)
Y = !(!A + !S + !C)

4-input

NOR4A
NOR4S

Y = ! (!A + S + C + D)
Y = !(!A + !S + C + D)

GMX4

Clock Net
Interface

AND-OR

Multiplexor
4:1

NAND

NOR

1-70

Seq.

Comb.

ACT 2 FPGAs

Combinable Hard Macros 2 (continued) (for DF1, DF1 B, DFC1 B, DFC1 D, DL1, and DL1B)
No. of Modules
Function

Macro Name

Equatlon(s)

OA1A
OA1B
OA1C
OA2
OA2A
OA3
OA3A
OA4
OA4A
OA5

Y
Y
Y
Y
Y
Y
Y
Y
Y
Y

OAI1
OAI2A
OAI3A

Y = !«A + B) C)
Y = !«A + B + C) !D}
Y = !«A + B) !C ID )

3-input

OR3A
OR3B

Y = !A + 8 + C
Y = IA + 18 + C

4-input

OR4
OR4A

Y=A+B+C+D
Y = IA + B + C + D

XOR

XOR
X01
X01A

Y=A"8
Y = (A " B) + C
Y = I(A A 8) + C

XNOR, AND-XOR

XNOR
XA1
XA1A

Y = !(A A 8)
Y = (A A 8) C
Y = !(A " 8) C

Description

OR-AND

OR-AND Invert

OR

Exclusive OR

=
=
=
=

=
=
=
=

=
=

Seq.

Comb.

(!A + 8) C
(A + B) (!C)
(!A + 8) (!C)
(A + 8) (C + D)
(!A + 8)(C+ D)
«A + 8) CD)
«A + 8) !C D)
(A + 8 + C) D
«A + B + !C) D)
(A+B+C)(A+D)

I

1-71

Non-Combinable Hard Macros
No. of Modules
Function

Description

Macro Name

Equatlon(s)

4-input

AND4
AND4A
AND4D

Y=ABCD
Y = (!A BCD)
Y =!A!B!C!D

AND

Seq.

5-input

AND5B

Y = !A!B C DE

2-input

OR2B

Y = !A + !B

3-input

OR3C

Y = !A + !B + !C

4-input

OR4B
OR4C
OR4D

Y = !A + !B + C + D
Y = !A + !B + !C + D
Y = !A + !B + !C + !D

OR

5-input

OR5B

Y = !A + !B + C + D + E

3-input

NAND3

Y = !(A B C)

4-input

NAND4
NAND4A
NAND4B

Y = I(ABCD)
Y = !(!A BCD)
Y = !(!A !B C D)

5-input

NAND5C

Y= !(!A !B !C D E)

4-input

NOR4
NOR4C
NOR4D

X = I(A + B + C + D)
Y = !(!A + !B + !C + D)
Y = !(!A + !B + !C + !D)

5-input

NOR5C

Y = !(!A + !B + !C + D + E)

XNOR, AND-XOR

AX1
AX1A
AX1C

Y = (!A B) A C
Y = !(!A B) A C
Y = (A B) A C

AND-OR

A02E
A03A
A06
A06A
A07
A08
A09
A010

Y = (!A !B) + !C + !D
Y = (A B C) + D
Y=AB+CD
Y = A B + C!D
Y=ABC+D+E
Y = (A B) + (!C !D) + E
Y = (A B) + C + D + E
Y = (A B + C) (D + E)

AND-OR Invert

AOl1
AOl2B
AOl4
AOl4A

Y = !(A B +
Y = !«!A B)
Y=!«A B) +
Y = !(A B +

OR-AND

OA3B

Y = «!A + B) !C D)

OR-AND Invert

OAI3

Y = !«A + B) CD)

MX2B

Y = (A IS) + (!BS)

NAND

NOR

Exclusive OR

Multiplexor

1-72

2:1

C)
+ !C + D)
(C 0»
!C D)

Comb.
1
1
2

1
2

2

2

2

1
2

ACT 2 FPGAs

Non-Combinable Hard Macros (continued)
No. 01 Modules
Function

Description

Macro Name

Equatlon(s)

HAl

CO=AB
S=A'" B

2

HA1A

CO=IA B
S=I(A'" B)

2

HA1B

CO=I(A B)
S=I(A'" B)

2

HA1C

CO=I(A B)
S=(A'" B)

2

Seq.

Comb.

half

Adders

CO=(C/!B IA) + (A!B) + (B CI A)

S = (B IA ICI) + (CO IA CI) + (CO A ICI)
+ (BACI)

2

FA1B

CO=IA(!B + BCI) + A(IBCI)
S = IA(ICI CO + CI B) + A(ICI B + CI CO)

2

FA2A

CO=(CI IB I(AO+Al)) + (IB (AO+Al))
+ (B CI (AO+Al))
S= (B I(AO+Al) ICI) + (CO !(AO+Al) CI)
+ (CO(AO+Al) !CI) + (B(AD+Al)CI)

2

Y = !(A + S B) C + D (A + S B)
Y = Al Bl + AD BO Al + AD BO Bl
Y=(!S1 (!SOA DO) + (SOA 01»
+ (Sl (!SOB D2 + SOB D3»
Y= !(!S A + S B) C + (!S A + S B) D

2

FA1A

full

CSl
CY2A
Boolean

MXT
MXCl

(ClK, D, -,-)
ON == !(ClK, D, -. -)
o = (!ClK. 0, -, -)
ON == !(!ClK, D,- .-)

with clear

DFCl
DFC1A
DFC1B
DFC1D
DFC1E
DFC1G

0= (ClK, D. ClR.-)
O=(!ClK. D. ClR.-)
o = (ClK. D. !ClR. -)
o = (!ClK. D. !ClR. -)
ON == !(ClK. D. !ClR. -)
ON = !(!ClK. D. !ClR. -)

with enable

DFE
DFE1B
DFE1C
DFE3A
DFE3B
DFE3C
DFE3D
DFEA

O=(ClK. IE 0 + ED. -, -)
O=(ClK.!E D + EO. -.-)
O=(!ClK. D!E + 0 E. -.-)
O=(ClK. 0 E + 0 !E. !ClR.-)
O=(!ClK. D E + 0 !E. !ClR.-)
0= (ClK. D IE + 0 E. IClR.-)
O=(!ClK. D !E + 0 E. !ClR.-)
O=(!ClK. !E 0 + ED. -. -)

D-type
Flip-Flops

2

o=

DFl
DF1A
DF1B
DF1C

1-73

•

Non-Combinable Hard Macros (continued)
No. of Modules
Description

Macro Name

Equatlon(s)

with multiplexed data

DFM
DFM1B
DFM1C
DFM3
DFM3B
DFM3E
DFM4C
DFM4D

DFMA
DFMB
DFME1A

a = (CLK, A !S + B S, -, -)
aN = !(CLK, A!S + B S, -,-)
aN = !(!ClK, A !S + B S, -, -)
a={CLK, A!S + B S, CLR,-)
a = (!CLK, A !S + B S, !CLR, -)
a = (!CLK, A !S + B S, CLR, -)
aN = !(ClK, !A !S + !B S, -, !PRE)
aN = !(!CLK, A !S + B S, -, !PRE)
a = {ClK, (DO ISO !S1 + D1 SO !S1
+ D2 ISO S1 + D3 SO Sl), !CLR, -)
a = {!CLK, (DO ISO !S1 + D1 SO !S1
+ D2 ISO Sl + D3 SO Sl), !CLR, -)
a = {CLK, !ClR, (DO ISO + D1 SO) !(S10 + S11) 1
+ (D2 ISO + D3 SO) (S10 + S11))
a = {!ClK, !ClR, (DO ISO + D1 SO) !(S10 + S11)
+ (D2 ISO + D3 SO) (S10 + S11))
a = (!CLK, A!S + BS, -,-)
a = (ClK, A !S + B S, !ClR, -)
a = (ClK, !E A !S + !E B S + E a, -, -)

with preset

DFP1
DFP1A
DFP1B
DFP1C
DFP1D
DFP1E
DFP1F
DFP1G

a = (ClK, 0, -, PRE)
a = (!ClK, D, -, PRE)
a = (CLK, D, -, !PRE)
aN = !(ClK, D, -, PRE)
a = (!CLK, D, -, !PRE)
aN = !(CLK, D, -, !PRE)
a = (!CLK, 0, -, PRE)
aN = !(!ClK, D, -, !PRE)

with clear
and preset

DFPC
DFPCA

a = (ClK, 0, CLR, PRE)
a = (!CLK, D, !CLR, PRE)

JK Flip-Flops

JKF
JKF1B
JKF2A
JKF2B
JKF2C
JKF2D

a={CLK,!a J + a K, -,-)
a={!ClK, !a J + a K, -,-)
a = (ClK, !a J + a K, !ClR, -)
a = (!CLK, !a J + a K, !CLA. -)
a={CLK, !a J + a K, ClR,-)
a= (!CLK, !a J + a K, ClR, -)

T-type Flip-Flops

TF1A
TF1B

a = (CLK, T !a + !T a, !CLR, -)
a = (!ClK, T !a + !T a, !ClR, -)

DL1
Dl1A
DL1B
Dl1C

a

Function

DFM6A
DFM6B
DFM7A
D-type
Flip-Flops
(continued)

Data Latch

DFM7B

DL2A
Dl2B
Dl2C
Dl2D

1-74

= (G, D, -, -)
aN = !(G, 0, -,-)
a = (!G, 0, -, -)
aN = !(!G, D, -, -)
a = (G, D, !CLR, PRE)
aN = !(!G, D, CLR, PRE)
a = (!G, D, !CLR, PRE)
aN = !(G, 0, CLR, !PRE)

Seq.

Comb.

2
2
2

1

2

2
2

2
2
2
2

ACT 2 FPGAs

Non-Combinable Hard Macros (continued)
No. of Modules
Function

Description

Macro Name

Equation(s)

with clear

DlC
DlC1
DlC1A
DlC1F
DlC1G
DlCA

a = (G, D, !ClR, -)
0= (G, D, ClR, -)
0= (!G, D, ClR, -)
ON = !(G, D, ClR, -)
ON = !(!G, D, ClR, -)
a = (!G, D, !ClR, -)

with enable

DlE
DLE1D
DlE2A
DlE2B
DLE2C
DlE3A
DlE3B
DlE3C
DlEA
DlEB
DlEC

0= (G, a !E + D E, -, -)
ON = !(!G, !E !D + EON, -, -)
a=(!G, a !E + DE, ClR, -)
a=(!G, D!E + a E, !ClR,-)
a=(!G,!E D + a E, ClR,-)
a=(!G, ED + a !E, -, PRE)
a=(!G, !E D + a E, -, PRE)
a=(!G,!E D + a E, -, !PRE)
0= (G, a E + D !E, -, -)
a=(!G, a!E + DE, -,-)
a=(!G, a E + D !E, -,-)

DlM
DlM2A

DLMA

a = (G, A !S + B S, -, -)
a=(!G, A!S + B S, ClR,-)
a = (G, DO ISO !S1 + D1 SO !S1 + D2 ISO S1
+ D3S0S1, -,-)
a = (!G, DO ISO !S1 + D1 SO !S1 + D2 ISO S1
+ D3S0S1, -,-)
a = (lG, A !S + B S, -, -)

with multiplexed data
and enable

DlME1A

0= (!G, A !S !E

with preset

DlP1
DlP1A
DlP1B
DLP1C
DlP1D
DlP1E

a=(G, D, -, PRE)
0= (!G, D, -, PRE)
a=(G, D, -, !PRE)
0= (!G, D, -, PRE)
ON = !(G, D, -, !PRE)
ON = !(!G, D, -, !PRE)

Data latch
(continued)

with multiplexed data

DlM3
DlM3A

Seq.

Comb.

1
2

•

+ B S !E + E a, -, -)

Clock Net Interface

ClKINT

clock
modules = 1

Tie-Off

VCC
GND

modules = a
modules = 0

1-75

Hard Macro Symbols
1/0 Buffers
(I/O Module Count = 1)

D

D

1/0 Buffers with Latches

D

OBDLHS
G

D

Q

D

Q

TBDLHS

BBDLHS

G

G

Q

D~----I

Gn-------

1-76

ACT 2 FPGAs

2-lnput Gates
(Module Count = 1)

~

~

B-x

~NAND~

~
~

~
~

~

~
~

•

3-lnput Gates
(Module Count = 1)

~

fi AND~

!§ AND3~

~AND~

~

~

~

f)NO~

ijNO~

SNAN~

~
~

1-77

4-lnput Gates
(Module Count

=

1)

~~

~~

~~

~~

~~

~~

~~

~~NAND~

i~

~~

~~

~~

i~

~~

~~

~&

~~

~~

i~

~~

~~

~~

(Module Count

= 2)

~~fAN~
.A. Indicates extra delay input
5-lnput Gates
(Module Count

=

1)

~~
Buffers
(Module Count = 1)

1-78

ACT 2 FPGAs

XOR Gates (Module Count

~ND-XOR

= 1)

XOR-OR Gates (Module Count

= 1)

XOR-AND Gates (Module Count

= 1)

Gates

[Module Count

= 1)

:Module Count

= 2)

•

1-79

AND-OR Gates
(Module Count

= 1)
A
B

c
o

A
B

A

A

c

B

B

o

c-----v'~

c--------{
0-------------;

A
B

A
B

c-------(

A

0-------------;

B
c--------~

c
o

y
A

D--------J

o ------------~

B

c --------------(
o ------------~

A
B
c------~

A
B

A

c

B
D------~

A

c

B

D--------i

c
o

1-80

ACT 2 FPGAs

~ND-OR

Gates, continued

Module Count = 1)

A

A

B

B

c---~c.L_,..,

c------{

•
Module Count = 2)

A
B
C

D

A
B

c:--------I
D-------l

A
B

C

E-------I

1-81

OR-AND Gates
(Module Count

1-82

= 1)

ACT 2 FPGAs

Multiplexors
(Module Count

= 1)

A

A

DO
D1

B

B

D2

Y

D3

(Module Count = 2)
C

DO
D

D1

A

D2

I

B

D3

S

Latches
(Module Count = 1)

-G- --G-

---0

--0

----D-

--t:J

----G-

--t:J

1-83

D-Latches with Clear
(Module Count = 1)

a

D

a

D

aN

D

DLC1F

aN

D

DLC1G
G

G

CLR

CLR

PRE

PRE

a

D

DLP1

D
a
DLP1A
G

G

CLR

CLR

PRE

PRE

PRE

a

D

G

CLR

CLR

a

D

DLC1A

DLC1
G

G

G

a

D

DLCA

DLC

DLP1B
G

a
D
DLP1C

D

G

G

PRE

aN

DLP1D

D
aN
DLP1E
G

(Module Count = 2)

PRE

PRE

a

D

D

DL2A
G

PRE
D

DL2C
G

CLR

PRE

a

D

DL2B
G

CLR

1-84

aN

aN
DL2D

G

CLR

CLR

ACT 2 FPGAs

D-Latches with Enable
(Module Count = 1)

~

~

~

TI

TI

-D

=--0

D-

E DLE1D

E DLE2B

E DLE2C

PRE
D
a
E DLE3B

G

G

G

G

D

aN

a

D

PRE
D
a
E DLE3C
G

CLR

CLR

:Module Count

a

D

= 2)
D
a
E DLE2A

PRE
D
a
E DLE3A

G

G

•

CLR

Mux Latches
:Module Count

= 1)

fi
; OLM

DO
a
D1
D2
D3
DLM3
SO
S1
G

DO
a
D1
D2
D3
DLM3A
SO
S1
G

DLME1A

A

B
DLMA
S
G

a

n

Module Count = 2)
A
B

a

1-85

Adders
(Module Count = 1)

C----------------~

B1

B1
D----------------~

Y

A1 CY2A

A - - - - -.....

BO

Y

A1 CY2B

80

0

1

AO

AO
B
S

(Module Count

= 2)

13=
B

A

A

A

B

8

B

CO

HA1

co
S

S

S

HA1A

co
S

HA1B

HA1C

A

A
8

CI

co

B

CO
AS

CI

FA1A

A1

CO
AS

B
CI

FA1B

CO
AS

FA2A

Macros FA1A, FA1B, and FA2A have two level delays from the inputs to the S outputs, as indicated by theA

D-Type Flip-Flops
(Module Count = 1)

-fo:1-~-D---G-

-0

1-86

-0

-t:J

-0

ACT 2 FPGAs

0-Type Flip-Flops with Clear
(Module Count = 1)

D
0
DFC1B

D

0

DFC1D

o
CLR

CLR

= 2)

(Module Count

o
DFC1

ON
DFC1A

CLR

CLR

D

D

ON
DFC1E

D

ON
DFC1G

D

0-Type Flip-Flops with Preset

= 1)

(Module Count

PRE
D

•

PRE

ON

DFP1E

D

ON

DFP1G

(Module Count = 2)

PRE

PRE
0

D

DFP1

PRE
0

D

DFP1A

DFP1B

PRE
D

PRE
0

D

D

ON

DFP1C

PRE
0

DFP1D

D
ON
DFP1F

)-'TYpe Flip-Flops with Preset and Clear
Module Count

= 2)
PRE

PRE

o

D

o

D

DFPC

DFPCA

CLR

CLR

1-87

0-Type Flip-Flops with Enable
(Module Count = 1)

~D-~

-0
D

Q

E DFE3A

-0
D

Q

E DFE3B

-0
D

Q

E DFE3C

o

Q
E DFE1C

ClK

o

Q

E DFE3D

CLK

ClK

ClK

eLK

ClR

ClR

ClR

ClR

JK Flip-Flops
(Module Count = 1)

£+-

-D

JKF1B

J

Q

JKF2A

J

ClK

Q

ClK
K

ClR

ClR

(Module Count = 2)
JKF2C

Q

JKF2D

Q

J

ClK

ClK
K

K

ClR

ClR

Toggle Flip-Flops
(Module Count

= 1)
T

Q

TF1A

1-88

Q

ClK

K

K

J

JKF2B

J

T

Q

TF1B

ACT 2 FPGAs

Mux Flip-Flops
(Module Count = 1)

=f:t-

A

a

B

=0

DFMB
S

DFM7B

DFM7A

a

Q

A

a

B

DFME1A

s
E

CLK

A
B

ON

DFM1B

A
B

ON

A
B

a

A
B

DFM1C

S

DFM4C

S

ClK

(Module Count

S

CLK

ClK

A
B

I

DFM4D
S

ClK

= 2)
a

A

a

A

B

B

DFM3
S

ClK
ClR

CLKBUF Interface Macros
(Module Count = 1)

DO
D1

y

A

D2
D3

I> Indicates clock input for connection to the global clock networks.
1-89

Package Pin Assignments: 176-Pin CPGA
(Top View)
1

2

3

4

5

6

7

8

9 10 11

12 13 14 15

AOOOOOOOOOOOOOOOA
BOOOOOOOOOOOOOOOB
cOOOOOOOOOOOOOOOc
00000000000000000
EOOOO
OOOOE
FOOOO
OOOOF
OOOOG
GOOOO
176-Pln
OOOOH
HOOOO
CPGA
OOOOJ
JOOOO
OOOOK
KOOOO
LOOOO
OOOOL
MOOOOOOOOOOOOOOOM
NOOOOOOOOOOOOOOON
pOOOOOOOOOOOOOOOP
ROOOOOOOOOOOOOOOR
2

3

4

5

6

7

8

9 10 11

12 13 14 15

Signal

Pin No.

Location

PRA or I/O

152

C9

PR8 or I/O

160

D7

MODE

2

C3

SDI or I/O

135

814

SDOor I/O

87

P13

DClK or I/O

175

83

ClKA or I/O

154

A9

ClKB or I/O

158

88

GND

1,8,18,23,33,38,45,57,67,77,89,
101,106,111,121,126,133,145,156,165

D4, E4, G4, H4, K4, l4, M4, M6, M8, M10, M12,
K12,J12, H12,F12, E12,D12, D10, C8,D6

Vee

13,24,28,52,68,82,112,116,140,155,170

F4, H3, J4, M5, N8, M11, H13, G12, D11, D8, D5

Vpp

110

J14

Vsv

25,113

H2,H14

VKS

109

J13

Notes:
1. Unused 110 pins are designated as outputs by AlS and are driven low.
2. All unassigned pins are available for use as 1I0s.
3. MODE = GND, except during device programming or debugging.

1-90

4. V pp = Vee, except during device programming.
5. Vsv = Vee, except during device programming.
6. V KS = GND, except during device programming.

ACT 2 FPGAs

Package Pin Assignments: 132-Pin CPGA
(Top View)

1

2

3

4

5

6

7

8

9

10

11 12 13

AOOOOOOOOOOOOOA
e00000000000008

cOOOOOOOOOOOOOc
00000

000

EOOO
FOOOO
GOOOO
HOOOO
JOOO
K

0000

OOOE
000 0
132-Pln
CPGA

0 0 0

F

OOOOG
OOOOH
000
000

000

J
K

LOOOOOOOOOOOOOL
MOOOOOOOOOOOOOM
NOOOOOOOOOOOOON
2

Signal

3

4

5

6

Pin No.

7

8

9

10 11

Location

PRA or I/O

113

88

PRB or I/O

121

C6

MODE

2

A1

SDI or I/O

101

812

SDO or I/O

65

N12
C3

DCLKor I/O

132

CLKA or I/O

115

B7

CLKB or I/O

119

86

GND

9,10,26,27,41,58,59,73,74,92,93,
107, 108, 125, 126

E3, F4, J2, J3, L5, M9, L9, K12, J11, E12, E11,
C9, 89, 85,C5

Vee

18,19,49,50,83,84,116,117

G3,G2, L7, K7, G10,G11, 07, C7

Vpp

82

G13

Vsv

17,85

G4, G12

VKS

81

H13

Notes:
1. Unused liD pins are designated as outputs by ALS and are driven low.
2. All unassigned pins are available for use as liDs.
3. MODE = GND, except during device programming or debugging.

I

12 13

4. Vpp = Vee, except during device programming.
5. Vsv = Vee, except during device programming.
6. VKS = GND, except during device programming.

1-91

Package Pin Assignments: 100-Pin CPGA
(Top View)

2
A

B
C
D

E
F
G

H

J
K
L

4

5

6

7

8

9 10 11

l~

2

Signal

3

00000000000
00000000000
00000000000
000
0
0000
000
000
Pin
0000
0000
CPGA
000
000
000
000
0
00000000000
00000000000
00000000000
3

4

5

6

7

8

A

B
C
D
E

F

G
H

J
K
L

9 10 11

Pin No.

Location

PRAor I/O

85

A7

PR8 or I/O

92

A4

MODE

2

C2

SDI or I/O

77

C8

SDOor I/O

50

J9

DCLK or I/O

100

C3

CLKA or I/O

87

C6

ClKB or I/O

90

D6

GND

7,20,32,44,55,70,82,94

E3,G3,J5,J7,G9,D10,C7,C5

Vee

15,38,64,88

F3, K6, F9, 86

Vpp

63

F10

Vsv

14,65

G1, E11

VKS

62

F11

Notes:
1. All unassigned pins are available for use as liDs.
2. Unused 110 pins are designated as outputs by ALS and driven low.
3. MODE = GND, except during device programming or debugging.

1-92

4. Vpp = Vee, except during device programming.
5. Vsv = Vee, except during device programming.
6. V KS = GND, except during device programming.

ACT 2 FPGAs

Package Pin Assignments: 172-Pin CQFP
(Top View)
Pin #1
Index

137136135134133132131130

172171170169168167166165164

1
2

~

•••

~
/'

129

'\

128

3

127

4

126

5

125

6

124
123

7

122

8

•
•
•

•
•
•

172-PIN
CQFP

35

95

36

94

37

93

38

92

39

91

40

90

41

89

42

88

43

~

~

./,)

I

87

V
•••

44 45 46 47 48 49 50 51 52

79 80 81 82 83 84 85 86

Signal

Pin Number

MODE
GNO

1
7,17,22,32,37,55,65,75,98,103,108,118,123,141,152,161
12,23,27,50,66,80,109,113,136,151,166
24,110
106
107
85
131
148
156
150
154
171

Vee
Vsv
VKS
Vpp
SOD or I/O
SOl or I/O
PRA or I/O
PRS or I/O
ClKA or I/O
ClKS or I/O
OClK or I/O

Notes:
1. Vpp must be terminated to Vee, except during device programming.
2. MODE must be terminated to circuit ground, except during device
programming or debugging.

3. Unused 110 pins are designated as outputs by ALS and are driven low.
4. All unassigned pins are available for use as 1I0s.

1-93

Package Pin Assignments: 160-Pin PQFP
(Top View)

DClK or 1/0
Vee

GND

PRB or 1/0

ClK or 1/0
Vee
ClK or 1/0
PRA or 1/0

GND

Vee
SDI or 1/0

GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

160-Pln
PQFP

29

30
31
32
33

GND

1/0
1/0

Vee

GND

GND
Vee

90

89
88
87
86
85

34

35
36
37
38
39
40

Notes:
1. Unused liD pins are designated as outputs by ALS and are driven low.
2. All unassigned pins are available for use as liDs.
3. MODE = GND, except during device programming or debugging.

1-94

120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91

GND
Vee

84

83
82
81

4. Vpp = Vee, except during device programming.
5. Vsv = Vee, except during device programming.
6.

VKS =

GND, except during device programming.

I/0orSDO

ACT 2 FPGAs

Package Pin Assignments: 144-Pin PQFP
(Top View)

w

000

000

zzz

zzz

CH!l

Notes:
1. Unused liD pins are designated as outputs by ALS and are driven low.
2. All unassigned pins are available for use as liDs.
3. MODE = GND, except during device programming or debugging.

888

4. V pp = Vee, except during device programming.
5. Vsv = Vee, except during device programming.
6. VKS = GND, except during device programming.

1-95

I

Package Pin Assignments: 100-Pin PQFP
(Top View)

o

5
en

o
z

g

C!l

in 8 8:

»»

oz

~

C!l

o

en

g

ooro~n~~Mnnnrooo~~oo~~~~~oow~~~~~~~~

50

81
82
83

GND
PRBA.I/O
ClKA.I!O
Vee

84

0

49
48
47

85

46

86
87

45
44

88

43
42

89

100-Pln
PQFP

90

41

elKB. I/O

91
92
93
94

38

PRBB. I/O

95

36

GND

40
39

35

97

34

99
100

Vee

37

96
98

GND

0

0
1

2

~

....I
()

0

3

4

w

0
0
::2

5

6

7

8

GND

33
32
31

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

0

Z

C!l

in

»

0
0

0

Z

C!l

gg
~5

:2:9
iiiz
iii

Notes:
1. V pp must be terminated to Vee. except during device programming.
2. MODE must be terminated to circuit ground, except during device
programming or debugging.

1-96

3. Unused I/O pins are designated as outputs by ALS and are driven low.
4. All unassigned pins are available for use as 1I0s.

ACT 2 FPGAs

Package Pin Assignments: 84-Pin PLCC
(Top View)

...J

m
m

~

;2

0

a.

0

0

~

a:

0

0

g
11

10

g

z

<.!l
9

6

m

...J

...J

0
0

g

>

g

«
m
a:

is
en

a.

g

g

5

MODE

GND

I

Vee

84-PIN
PLCC

Vsv

Vpp

VKS

Vee

GND

49

g g
~-

z

f-"

I

::::>
0

m zI
m

Notes:
1. V pp must be terminated to Vee, except during device programming.
2. MODE must be terminated to circuit ground, except during device
programming or debugging.

g

>

0

z

<.!l

50

51

g
ci
0
en

3. Unused 110 pins are designated as outputs by ALS and are driven low.
4. All unassigned pins are available for use as 1I0s.

1-97

Package Mechanical Details: 176-Pin CPGA

~lf-

Pin#11D

.132"

I

=={=

.018" ± .002"

____L

----r

.100" Bse

~

1.570" ± .015" squ,""

--1

.050" ± .005"

(4 Places)

00000000000000
0@00000000000@0
000000000000000
000000000000000
0000
0000
0000
0000
0000
0000
0000
0000 1.400" Bse
0000
0000
0000
0000
0000
0000
000000000000000
000000000000000
0@00000000000@0
6>0 0 0 0 0 0 0 000 000 l:;t+-----'L--

1-98

-l

ACT 2 FPGAs

Package Mechanical Details: 132-Pin CPGA

~l
.110"

Pin #1 10

~

~.

~
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0

o

@

@

do

0
0
0
0
0
0
0
0
0
0
0
0

1.360" ± .015"

sq""'"

--1

-.JI

.100"

Bse

I

.120"
.140"

0 0 0 0
0 0 0 0
0 0 0 0
0 0

0 0 0 0 000 0 0 0 o 0
0 0 0 0 0 0
0
0 0 0
0 0 0
0
0 0 0 0
0
0 0 0 0
0
0 0 0 0
0 0 0
0 0 0
0 0 0
0 0 0 0 0 0 0 o 0 0
0 0 0 0 0 0 0 o 0 0
0 0 0 0 0 0 0 0 000

tJ

__ L

- --r

.050" ± .010"
(4 Places)

018" -.
+ 002"

•

1.200 "

BSe

• Orientation Pin

1-99

Package Mechanical Details: 100-Pin CPGA

~l
.110"

Pin#11D

.018" ± .002"

__ L

~

•

1-100

1.100" ± .015" square

---1

0

0

0

0

0

0

0

0

0

0

"....,

0

«l>

0

0

0

0

0

0

0

«l>

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

•

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

«l>

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0
0

Orientation Pin

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

«l> 0

0

0

-

"

.050" ± .010"
(4 Places)

--.1I

tJ

.100"

--r
.120"
.140"

1.000 " ase

ase

ACT 2 FPGAs

Package Mechanical Details: 172-Pin CQFP
4-2.300 ± 0.010

1r

0.035 ± 0.005

4-1.500 ± 0.015
-

2-4>0.100 ± 0.002

J-----~~~mIDnTnruTnmIDnTmnTnrnTnmInmIDrnTnrnTn~~~==~~----l'

NCTB
(alumina 90%)

ALLOY 42 /

0.105 ± 0.012

ALUMINA
(90% BLACK)

8o

,
,

"

"

+1

~

N

It)lt)

80
00
+1

g

I

N
1

C\I

0.090 ± 0.010
±

0006 +0.002
.
-0.001

0.025TYP

0.018 TYP

4-4>0.060 REF

2.140 ± 0.005

Notes:
1. All exposed metalized areas and leads are
gold plated 100 microinches (2.5 }J mm) min.
thickness over 80 to 350 microinches 2.0 to
8.9 }J mm) thickness of nickel.
2. Seal ring area is connected to GNDA.
3. Die attach pad is connected to GNDA.
4. GNDQ (4 PLS) is connected to GNDA.
S. Tolerances unless otherwise specified: ± 1%
N.L.T. ±O.OOS.

HEAT SINK -r--+---

0.067 ± 0.010 sa.

1

BOTTOM VIEW

1-101

Package Mechanical Details: 160-Pin PQFP

I'~I"-

Dimensions in millimeters

frio

31.90 ± .25

Pin#11D

t~ 0.30TYP

28.00 ± .10 0.65 BSe

~ 4.07 MAX
0.18 ± .05~
~ I- .80 ± .13

3.42±.251

0.38 ± .13

1-102

ACT 2 FPGAs

Package Mechanical Details: 144-Pin PQFP
1 + - - - - - - - - 31.20 ± .25

Dimensions in millimeters

-------___+1

~~~:::::::':::'::'::':2~8:::.00::':::'::±:'::':.~10:::iiiiJ

Pin#11D

~

f

0.30lYP

28.00 ± .10 0.65

esc

I
3.42±.25!

~~ 4.07 MAX

0.18 ± .05"0.38 ± .13

r-

.80 ± .13

1-103

· I Details: 100-Pin PQFP
Package Mechanlca
Dimensions in millimeters

1..------

1-104

18.85± .13 - - - - - - - - 1

ACT 2 FPGAs

Package Mechanical Details: 84-Pin PLCC

_1_
-1-

o

.050" ± .005"
D1

.020" min.

D

~JJl

I

--J ~ .029"

± .003"

.175" ± .010"
Lead Count

44

D,E
.690" ± .005"

I

01, E1
.655" ± .005"

68

.990" ± .005"

.955" ± .005"

84

1.190" ± .005"

1.155" ± .005"

1-105

1-106

Fast Clock to Out with
ACT 2 I/O Latches

Applications
Note

Two level-sensitive latches can be combined, as shown in Figure 1,
to create a positive edge-sensitive flip-flop.

Introduction
In ACT™ 2 device designs, latched I/O buffer macros can be used
to improve clock input to registered output performance.
Flip-flops, developed from these I/O latch macros, can improve
performance up to 34% over traditional approaches. This
applications note compares the use of traditional approaches with
the use of I/O latch macros in ACT 2 designs.

Where:
Tco = tCQ2
T su = tCLKL - tCQl - tNET > tS02
tS02 = minimum setup time for slave

Master-Slave Flip-Flops

Slave

Master

DATA

-

D

r<:

Q

Q1

D2

G

~

Q f - OUT

D

•

G

ClK

DATA

ClK

Q1

D2

OUT

+
,-

tsul

-I,-

teLKL

teal

-I

~
~
I-

Tsu

-,-

Tco

f

Figure 1. Master-Slave Flip-Flop

The clock to output delay of the resulting flip-flop is determined by
the clock to output delay of the slave latch. The clock period low
time (tcLKL) must be greater than the clock to output delay of the

©

1992 Actal Corporation

master latch (tcQl) plus the net delay from the master latch output
(tNET) plus the setup time of the slave latch (tS02).

April 1992

1-107

out delay for an A1280-1 under worst-case commercial conditions
is 29.0 ns.

Constructing Registered Outputs
You can construct a registered output by combining a flip-flop
macro with an output buffer as depicted in Figure 2. The clock to

01------1

50PF

I
""1.1----Teo

= (tcLK +

tea

OUTBUF

DFI

CLKBUF
tcLK

""1·---

----·~IIooI.I---- tea

- - -.....

toUT

---~·I

+ toUT) = (12.7 + 7.9 + 8.4) ns = 29.0 ns

Figure 2. Conventional Registered Output

I/O Latch Flip-Flops
You can also construct a registered output as a master-slave
flip-flop, using a latch from the macro library and a latched I/O as

shown in Figure 3. In this case, the clock to out delay for an A1280-1
device under commercial worst-case conditions is 21.1 ns. In both
cases, the loading on the global clock network is assumed to be
equal to 200.

r-------------,

I
I

I
I

O~----~I~D

I
I

G

G

I

I
I
_ _ _ _ _ _ _ _ _ .JI
OBDLHS
IL _ _ _ _
DL1B
CLKBUF

r---

teU(L

200 loads

- - - - - 1..-101.·
. -

""1·---------

te01 -

·""1·-- ---1

...

tNET

" 1..·------ ------+1·1

teLK - - - - - - - - -.....

Teo = (tcLK + toUT) = (12.7 + 8.4) ns = 21.1 ns

Tsu

= teLKL -

te01 - tNET > tSU2

Figure 3. Master-Slave Registered Output

1-108

I

toUT

50PF

Fast Clock to Out with ACT 2 I/O Latches

Dual Clock Approach
Sub-20 ns clock to out can be achieved by utilizing the second global
clock network as an 110 clock. In this configuration, shown in
Figure 4, CLKA drives the synchronous circuitry on the device and

CLKB drives the I/O master-slave latches. Both clock networks are
operating at the same frequency and must be connected together
external to the device. In this case, a 19.1 ns clock to out delay can
be achieved.

r-------------..,

I
I
l
Q a-------r-f D

D

I
I
I

G

1
14---------- tcLK

50PF

1.------ -------.t·1

- - - - - - - - -......

toUT

~>200loads
~

Teo = (tcLK

•

. . ~. . . . . . . .

+ toUT)

= (10.7

+ 8.4) ns

= 19.1 ns

Figure 4. Dual Clock Master-Slave Registered Output

Alternately, an Inbuf can be used to drive the 110 latch, taking care
to keep fan-out on the Inbuf less than four to achieve similar
performance.

Implementation Rules
Actel strongly suggests following these rules when constructing
flip-flops with the I/O latches.

1. Do not put combinatorial macros in the data path between
master and slave latches. Added delay may prevent the
flip-flop from operating properly.
2. Do not connect the master latch output to any loads except
the 110 latch D input.

3. Use a latch made from a sequential module for the master
stage. Sequential module latches have better timing
characteristics. They also allow combining to take place that
can improve the performance of the data being registered.
The transparent-low sequential-module latches available are
DLlB and DLlC.
4. Use net criticality to insure that the net delay does not
violate the setup requirements of the slave latch (as defined
in Figure 1). Verify the timing conditions after place and
route is complete. Note that an asymmetrical duty cycle on
the clock signal (>50% low time) will provide more tolerance
on the allowable net delay between latches.
5. Design to combine. The Action Logic™ System (ALS) will
automatically combine combinatorial logic into the D input
of the DLlB latch if the combiner rules are met.

1-109

1-110

ACT™ 3 Field
Programmable
Gate Arrays
Features
• Gate Capacities from Less than 1,000 to Greater than 10,000
Gate Array Gates
• Gate Capacities from Less than 2,500 to Greater than 25,000
PLD/LeA™ Equivalent Gates
• Replace from 30 to 340 TTL Packages
• User I/Os from Less than 100 to Greater than 200
• I/O Performance of 10 ns Clock-to-Out
• 16-bit Counter Performance in Excess of 125 MHz
• System-Level Performance to 75 MHz
• Single-Module Sequential Functions
• Wide-Input Combinatorial Functions
• Two In-Circuit Diagnostic Probe Pins Support Speed Analysis
to 50 MHz
• Four High-Speed Clock Networks
• I/O Drive to 12 mA
• Nonvolatile, User Programmable
• PQFP, PLeC and CPGA Packages

User I/0s
Performance
System Speed
16-bit Counters
CMOS Process

From

To

<1,000
<2,500
30

> 10,000
>25,000
340

<100

>200

75 MHz
>125 MHz

0.8 )lm double-metal CMOS

)escription
rhe ACT™ 3 family, with devices spanning capacities from less
han 1,000 gates to more than 10,000 gates, represents Actel's third
~eneration of field programmable gate arrays. The ACT 3 family
)rovides a group of high performance system solutions, delivering
.6-bit counter designs in excess of 125 MHz operation, and
upporting system performance of up to 75 MHz operation. The
\.CT 3 family offers an abundance ofI/Os ranging from less than
.00 pins to over 200 pins (see Figure 1). The devices are
mplemented in a silicon gate, 0.8 )lm, scaled double-metal CMOS
)rocess, and employ Acte1's patented PUCE® antifuse technology.

~ 1992 Actel Corporation

Based on Actel's patented channeled array architecture, the ACT 3
family provides significant enhancements to gate density and
performance while maintaining upward compatibility with the
ACT 1 and ACT 2 design environments.
ACT 3 devices are designed to meet two primary logic integration
requirements: high speed and high user I/O. ACT 3 provides the
highest-performance, general-purpose programmable solution
available, and the unprecedented design flexibility of the highest
pin-to-gate ratios available. The high performance of the ACT 3
family has been achieved through evolutionary enhancements to
Actel's proven two-module general-purpose FPGA architecture.
These enhancements include four high-speed clock distribution
networks and 10 ns clock-to-out I/O modules. The two-module
architecture consists of combinatorial and combinatorial-sequential
modules. A block diagram of the ACT 3 architecture is shown in
Figure 2.
The ACT 3 family is supported by the Action Logic™ System
(ALS), which offers automatic pin assignment, validation of
electrical and design rules, automatic placement and routing,
timing analysis, user programming, and debug and diagnostic
probe capabilities. The Action Logic System is available on SunTM,
Hp® and Apollo® workstations, and on 386/486 PC platforms.

ACT 3 Architecture

Product Family Profile

Capacity
Gate Array Equivalent Gates
PLD/LCA Equivalent Gates
TIL Equivalent Packages

Advance
Information

The ACT 3 family architecture is an evolutionary upgrade from the
ACT 2 family. After extensive research into alternate logic module
architectures, Actel found that the ACT 2 two-module design is
optimal for most applications. The small, simple structure of the
logic modules has been retained, with a single enhancement to the
sequential logic module. These numerous, general-purpose logic
modules constitute a design architecture that provides a highperformance solution for a wide range of applications, as shown in
Figure 3.
The I/O module is enhanced significantly, allowing more complex
logic functions to be implemented in the 110 module. This
significantly increases performance of key device parameters, like
clock-to-output. Clocking flexibility is also enhanced over the ACT 2
family with the inclusion of two high-speed dedicated clocks in
addition to the two routed clocks. A block diagram of the family
architecture is shown in Figure 4.
Two-Module Design

ACT 3 architecture uses the proven multiplexor-based combinatorial
module (C-Module) of ACT 2 devices, and an enhanced version of
the ACT 2 multiplexor-based combinatorial-sequential module
(S-Module). The ACT 3 S-Module combinatorial logic preceding
the register is equivalent to the combinatorial logic within the
C-module. This aJlo'M> for more complex logic functions to be
implemented in a single level of logic and makes logic synthesis more
efficient due to the regular combinatorial structure throughout the
device.

January 1992

1-111

•

User I/Os

250
ACT 3

200

150

100

50

O~--------~------~--------.--------r-------.---

6

4

2

10

8

Gate Capacity (in thousands)

Figure 1. ACT 3 Offers an Abundance of I/Os
I/O Buffers,

I/:n~~:;~
1

1

1

1

1

III

1

1

1

1

1

1

1

1

1

1

1

I~I

1

1

1

1

1

1

1

1

1

1

1

1

1

"

~

/
Horizontal Routing Tracks

Logic Modules

~

/
/

1

~

1

1

BUffers,/
~ I/O
Program

1

I

1

1

1

1

1

1

1/1

1

1

1

1

---1

L . . ._ _ _ _ _ _ _ _ _ _ _ _

and Test

Vertical Routing
Channel

Figure 2. Block Diagram of ACT 3 Architecture

1-112

1

ACT3FPGAs

Relative
Capacity
(%)

Actel's General-Purpose
Architecture
120

Architecture with
Specialized Features

100

80

60

40

20

o

•

Applications Range
(Counters, Multipliers, Decoders, etc.)

Figure 3. Actel's General-Purpose Architecture Addresses All Applications

Four Clock Sources

r-------,

r---------- -----,

I
I

I
I

-----,
I
I

t---4._--I D

Q

t---'---;---

I
I
I
I
I
1.I.

_______ .J

1...__________ _ ____ .J

C Module

S Module
Clear

Figure 4. Logic Modules Use Identical Combinatorial Logic

1-113

Interconnect Routing Using the PLiCE Antlfuse

I/O Module

Interconnections between logic modules are made using the
PLICE antifuse. The interconnections use a segmented wiring
channel similar to channeled gate arrays. The horizontal and
vertical channel segments vary in length, and are tuned to allow
automatic place and route of the most interconnect-intensive
applications. All speed-critical module-to-module connections are
accomplished with only two low-resistance antifuse elements. Most
connections are implemented in either two or three antifuse
elements. No connections require more than four antifuse
elements in a path.

The ACT 3 I/O module is a significant enhancement over the ACT:
latch-based I/O module. The ACT 3 I/O module contains inpu
and output registers and a register hold function that allow.
selective updating of the I/O module register. Thus, the regis ten
can be used for more complex logic functions in addition to simpl<
timing functions. In particular, microprocessor based systems wil
benefit from the selective update capability of the ACT 3 I/C
module. A variety of feedback options on the I/O module allov
registered outputs, registered inputs, or direct inputs to be selectee
as input to the array. Each I/O module contains a slew contro
feature, which allows output rise and fall times to be tailored to th(
particular application. The block diagram for the ACT 3 I/C
module is shown in Figure 5.

Output Buffer Enable

------,

r-

Output

I
I
I
I
I

I
I
I
I
I

D

Qt--....---"'------I

----r----ii-----.-IE

Output
Register
Enable

Input

~-~--~--~~Q

D....---__- - - <

Input
Register
Enable

~_

Clock

_ _____________________ J
I/O Module

Figure 5. I/O Module with Registered Inputs and Outputs

1-114

ACT3FPGAs

Clocking Options

Hard and Soft Macros

The ACT 3 family provides four clock distribution networks, twice
the networks offered by the ACT 2 family. In addition to two
routed clocks, ACT 3 provides two dedicated clocking sources: one
for the array and one for the I/O module. The routed clocks are
compatible with the ACT 2 family and are optimized for light to
medium loaded clocking nets. They can also be used for special
high fanout nets, such as reset or enable. The dedicated clock
networks are optimized for high fanout nets in either the array or
the I/O module. Since these clocks are dedicated, no special
circuitry is required to route the clock signals. This results in a very
controlled, high-speed clocking network for the large fanout
portion of the design. The high-speed clock-to-output capability of
the ACT 3 family is a direct result of the dedicated clock in the I/O
module.

Designing within the Actel design environment is accomplished
through a building block approach. Over 250 logic function macros
are provided in the ACT 3 design libraries. Hard macros range
from simple SSI gates such as AND, NOR, and exclusive OR to
more complex functions such as flip-flops with 4: 1 multiplexed data
inputs. Hard macros are implemented within the ACT 3
architecture by utilizing one or more C-Modules and/or
S-Modules. Over 150 of these macros are implemented within a
single logic module, although several two-module macros are
available. One- and two-module macros have a small propagation
delay variance, which allows accurate performance prediction.

Programmable I/O Pins

Each I/O pin is available as an input, output, three-state, or
bidirectional buffer. Inputs are TTL and CMOS compatible.
Output drive levels meet 12 rnA TTL and 6 rnA HCT standards.

Designing with ACT 3
Design Methodology

The simple, highly regular logic module architecture of the ACT 3
family is ideal for synthesis optimization. The ALS design
environment supports a wide variety of popular design approaches
for schematic entry and synthesis. Synthesis libraries for top-down
design also are available. Boolean entry and state machine design
are supported with the ALES™ logic optimizer tool. In addition,
ALS software provides 100 percent automatic placement and
routing at up to 95 percent module utilization.

Soft macros comprise multiple hard macros connected to form
complex functions ranging from MSI functions to 16-bit counters
and accumulators. A large number of TTL equivalent hard and soft
macros also are provided.
Design Compatibility

The design libraries for ACT 3 are fully upward compatible from
the ACT 1 and ACT 2 design libraries. ACT 1 and ACT 2 designs
can be converted to equivalent gate-count ACT 3 arrays. The
Activator®2 programmer supports the ACT 3 family; this single
programming unit also supports ACT 1 and ACT 2 device families.
Reliability

Actel builds the most reliable FPGAs in the industry, with overall
reliability ratings of less than 10 Failures-In-Time (FITs),
corresponding to a useful life of more than 40 years. Actel FPGAs
have been production-proven, with over 1 million devices shipped
and over 130 billion antifuses manufactured. Actel devices are fully
tested prior to shipment, with an outgoing defect level of only 122
ppm.

1-115

•

1-116

ACT™ 1 and ACT 2 Military
Field Programmable
Gate Arrays
ACT 1 Features

ACT 2 Features

• up to 2000 Gate Array Gates
(6000 PLD/LCA™ equivalent gates)

• up to 8000 Gate Array Gates
(20,000 PLD/LCA™ equivalent gates)

• Replaces up to 53 TTL Packages

• Replace up to 210 TTL Packages

• Replaces up to 17 2O-Pin PAL Packages
• Design Library with over 250 Macros

• Replace up to 69 20-Pin PAL Packages
• Design Library with over 250 Macros

• Single Logic Module Architecture

• Single-Module Sequential Functions

• Up to 547 Logic Modules

• Wide-Input Combinatorial Functions

• Up to 273 Flip-Flops
• Two In-Circuit Diagnostic Probe Pins Support Speed Analysis
to 50 MHz

• Up to 1232 Programmable Logic Modules
• Up to 998 Flip-Flops
• 16-Bit Counter Performance to 50 MHz (MIL Temp)

• Built-In High-Speed Clock Distribution Network

• 16-Bit Accumulator Performance to 25 MHz (MIL Temp)

• I/O Drive to 4 rnA
• Nonvolatile, User Programmable

• Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 50 MHz

• Logic Fully Tested Prior to Shipment

• Two High-Speed, Low-Skew Clock Networks

I

• I/O Drive to 6 rnA
• Nonvolatile, User Programmable
• Logic Fully Tested Prior to Shipment

Product Family Profile
ACT 1

ACT 2

Family

Device

A1280

A1240

A1020A

A1010A

Capacity
Gate Array Equivalent Gates
PLD/LCA Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages

8,000
20,000
210
69

4,000
10,000
105
34

2,000
6,000
17

1,200
3,000
34
12

1,232
624
608

684
348
336

547

295

998

565

273

147

36

36
15
400,000

22
13

22
13

Logic Modules
S-Modules
C-Modules
Flip-Flops (maximum)
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Column
PLlCE® Antifuse Elements
User I/Os (maximum)
Packages 1

Performance (MIL Temp)
16-Bit Counters
16-Bit Accumulators
CMOS Process

15
750,000

53

140

104

69

57

176 CPGA
172 CQFP

132 CPGA

84 CPGA
84 CQFP
44/68/84 JQCC

84 CPGA

39 MHz
23 MHz

50 MHz
25 MHz

39 MHz2
20 MHz2

39 MHz2
20 MHz2

1.2).lm

1.2).lm

1.2).lm

1.2).lm

Note:
1. See product plan on page 1-130 for package availability.
2. Performance is based on a -1 speed graded device at worst-case military operating conditions.
©

1992 Actel Corporation

April 1992

1-117

High Reliability, Low Risk Solution
Actel builds the most reliable field programmable gate arrays
(FPGAs) in the industry, with overall antifuse reliability ratings of
less than 10 Failures-In-Time (FITs), corresponding to a useful life
of more than 40 years. Actel FPGAs have been production-proven,
with over one million devices shipped and over 130 billion antifuses
manufactured. Actel devices are fully tested prior to shipment, with
an outgoing defect level of only 122 ppm. (Further reliability data is
available in the ''Acte1 Reliability Report.")

100% Tested Product
Device functionality is fully tested before shipment and during
device programming. Routing tracks, logic modules, and
programming, debug, and test circuits are 100% tested before
shipment. Antifuse integrity also is tested before shipment.
Programming algorithms are tested when a device is programmed
using Actel's Activator 1 or 2@ programming stations.

Benefits
No cost risk - Once you have an Action Logic™ System (ALS),
Actel's CAE software and programming package, you can produce
as many chips as you like for just the cost of the device itself, with no
NRE charges to eat up your development budget each time you
want to try out a new design.
No time risk - After entering your design, placement and routing
is automatic, and programming the device takes only about 5 to 15
minutes for an average design. You save time in the design entry
process by using tools that are familiar to you. The Action Logic
System software interfaces to popular CAE software such as Mentor
Graphics@, Valid™, OrCAD™, HP DCS, and Viewlogic@ and runs
on popular platforms such as Apollo®, HP, Sun™, and 386/486™
PC compatible machines.

No testing risk - Unprogrammed Actel parts are fully tested at
the factory. This includes the logic modules, interconnect tracks,
and I/Os. AC performance is assured by special speed path tests,
and programming circuitry is verified on test anti fuses. During the
programming process, an algorithm is run to assure that all
antifuses are correctly programmed. In addition, Acte1's
Actionprobe™ diagnostic tools allow 100% observability of all
internal nodes to check and debug your design.

ACT 1 Description
The ACT 1 family of FPGAs offers a variety of package, speed, and
application combinations. Devices are implemented in silicon gate,
1.2-micron two-level metal CMOS, and they employ Acte1's PLICE
antifuse technology. The unique architecture offers gate array
flexibility, high performance, and instant turnaround through user
programming. Device utilization is typically 95% of available logic
modules.
ACT 1 devices also provide system designers with unique on-chip
diagnostic probe capabilities, allowing convenient testing and
debugging. Additional features include an on-chip clock driver with
a hardwired distribution network. The network provides efficient
clock distribution with minimum skew.
The user-definable lIOs are capable of driving at both TTL and
CMOS drive levels. Available packages include ceramic J-leaded
chip carriers, ceramic quad flatpack, and ceramic pin grid array.
A security fuse may be programmed to disable all further
programming and to protect the design from being copied or
reverse engineered.

ACT 2 Description

No reliability risk - The PLICE™ anti fuse is a one-time
programmable, nonvolatile connection. Since Actel devices are
permanently programmed, no downloading from EPROM or
SRAM storage is required. Inadvertent erasure is impossible and
there is no need to reload the program after power disruptions.
Both the PLICE antifuse and the base process are radiation
tolerant. Fabrication using a low-power CMOS process means
cooler junction temperatures. Acte1's non-PLD architecture
delivers lower dynamic operating current. Our reliability tests show
a very low failure rate of91 FITs at 90°C junction temperature with
no degradation in AC performance. Special stress testing at wafer
test eliminates infant mortalities prior to packaging.

The ACT 2 family represents Acte1's second generation ofFPGAs.
The ACT 2 family presents a two-module architecture consisting of
C-Modules and S-Modules. These modules are optimized for both
combinatorial and sequential designs (see Figure 1). Based on
Actel's patented channeled array architecture, the ACT 2 family
provides significant enhancements to gate density and
performance while maintaining upward compatibility with the
ACT 1 design environment. The devices are implemented in
silicon gate, 1.2-}Jm, two-level metal CMOS, and employ Actel's
PLICE antifuse technology. This revolutionary architecture offers
gate array design flexibility, high performance, and fast
time-to-production through user programming.

No security risk - Reverse engineering of programmed Actel
devices from optical or electrical data is extremely difficult.
Progr~mmed antifuses cannot be identified from a photograph or
by usmg a SEM. The antifuse map cannot be deciphered either
electrically or by microprobing. Each device has a silicon signature
that identifies its origins, down to the wafer lot and fabrication
facility.

The ACT 2 family is supported by the ALS, which offers automatic
pin assignment, validation of electrical and design rules, automatic
placement and routing, timing analysis, user programming, and
~ebug and diagnostic probe capabilities. The Action Logic System
IS supported on the following platforms: 386/486 PC, Sun, HP and
Apollo workstations. It provides CAE interfaces to the following
design environments: Valid, Viewlogic, Mentor Graphics, HP DCS
and OrCAD.

1 118

ACT 1 and ACT 2 Military FPGAs

ACT 1 Architecture

Programmable I/O Pins

ACT 1 devices consist of a matrix oflogic modules arranged in rows
;eparated by wiring channels. This array is surrounded by a ring of
peripheral circuits including I/O buffers, testability circuits, and
jiagnostic probe circuits providing real-time diagnostic capability.
Between rows of logic modules are routing channels containing
;ets of segmented metal tracks with PLICE antifuses. Each channel
has 22 signal tracks. Vertical routing is permitted via 13 vertical
tracks per logic module column. The resulting network allows
nbitrary and flexible interconnections between logic modules and
[f0 modules.

Each I/O pin can be configured as an input, output, three-state, or
bidirectional buffer. Input and output levels are compatible with
standard TTL and CMOS specifications. Outputs sink or source
4 rnA at TTL levels. See Electrical Specifications for additional 110
buffer specifications.

The ACT 1 Logic Module
fhe ACT 1 logic module is an 8-input, one-output logic circuit
;hosen for the wide range of functions it implements and for its
!fficient use of interconnect routing resources (Figure 1).
fhe logic module can implement the four basic logic functions
:NAND, AND, OR, and NOR) in gates of two, three, or four
nputs. Each function may have many versions, with different
;ombinations of active-low inputs. The logic module can also
mplement a variety of D-latches, exclusivity function, AND-ORs,
md OR-ANDs. No dedicated hardwired latches or flip-flops are
'equired in the array since latches and flip-flops may be constructed
rom logic modules wherever needed in the application.

Probe Pin
ACT 1 devices have two independent diagnostic probe pins. These
pins allow the user to observe any two internal signals by entering
the appropriate net name in the diagnostic software. Signals may
be viewed on a logic analyzer using Actel's Actionprobe diagnostic
tools. The probe pins can also be used as user-defined I/Os when
debugging is finished.

ACT 2 Architecture
This section of the datasheet is meant to familiarize the user with
the architecture of ACT 2 family devices. A generic description of
the family will first be presented, followed by a detailed description
of the logic blocks, the routing structure, the antifuses, and the
special function circuits. Diagrams for the AI280 and AI240 are
provided at the end of the datasheet. The additional circuitry
required to program and test the devices will not be covered.

Array Topology
The ACT 2 family architecture is composed of five key elements or
building blocks: Logic modules, 110 modules, Routing Tracks,
Global Clock Networks, and Probe Circuits. The basic structure is
similar for all devices in the family, differing only in the number of
rows, columns, and I/Os.
Table 1. Array Sizes
Device

Rows

Columns

Logic

I/O

A1280

18

82

1232

140

A1240

14

62

684

104

The Logic and I/O modules are arranged in a two-dimensional
array (Figure 2). There are three types of modules: Logic, 110, and
Bin. Logic and I/O modules are available as user resources. Bin
modules are used during testing and are not available to users.

Figure 1. ACT 1 Logic Module

1-119

•

o
10
20
30
70
80
171 I I I I I I I I I I I I I I I I I I I I I I I I I I I I••• 1 I I I I I I I / I I / I
o
10
20
30
70
80
161 I II IslslclclslslclclslslclclslslclclslslclclslslclclslslcIclslsl ••• lslslclclslslclclslslclcll II I
•••
o
10
20
30
70
80

II IslslclclslslclclslslclclslslclclslslclclslslclclslslcIclslsl ••• lslslclclslslc/clslslclcll II I

811

o

10

20

30

70

80

71 I IIIslslclclslslclclslslclclslslclclslslclclslslclclslslcIclslsl ••• lslslclclslslclclslslclcll II I
o
10
20
30
70
80
61 I II IslslclclslslclclslslclclslslclclslslclclslslclclslslcIclslsl ••• lslslclclslslclclslslclcl I II1
o
10
20
30
70
80
51 I II IslslclclslslclclslslclclslslclclslslclclslslclclslslcIclslsl ••• lslslclclslslclclslslclcl I II I
o
10
20
30
70
80

41 I II IslslclclslslclclslslclclslslclclslslclclslslclclslslcIclslsl ••• lslslclclslslclclslslclcl I II1

o
10
20
30
70
80
31 I II Isis/clclslslclclslslclclslslclclslslclclslslclclslsicIclslsl ••• lslslclclslslclclslslclcl III I
o
10
20
30
70
80
211

II Islslclclsls/clclslslclclslslclclslslclclslslclclslslcIcls/sl ••• lslslclclslslclclslslclcll II I

o

10

20

o

10

20

30

70

80

11 I II IslslclclslslclclslslclclslslclclslslclclslslclclslslcIclslsl ••• lslslclclslslclclslslclcll III

01 I I I I I I I I I I I I I I I I I I I I I I I I I
s = Sequential Module, C = Combinatorial Module, I = I/O Module

II

30

I

I

70

I••• 1 I I I

I

II

I

I

80

I

Figure 2. Actel1280 Simplified Floor Plan

Logic Modules
Logic modules are classified into two types: combinatorial
C-modules and sequential S-modules (see Figures 3 and 4). The
C-module is an enhanced version of the Act I family logic module
optimized to implement high fan-in combinatorial macros, such as
5-input AND, 5-input OR, etc. The S-module is designed to
implement high speed flip-flop functions within a single module.
S-modules also include combinatorial logic, which allows an
additional level of logic to be implemented without additional
propagation delay. C-modules and S-modules are arranged in pairs
called module-pairs. Module-pairs are arranged in alternating pairs
(shown in Figure 2) and make up the bulk of the array. This
arrangement allows the placement software to support two-module
macros of four types (CC, CS, SC, and SS). I/O-modules are
arranged around the periphery of the array.
The combinatorial module (shown in Figure 3) implements the
following function:

Z

= !SI * (DOO * ISO + DOl * SO) + Sl * (DlO * ISO + Dll * SO)

where:

SO = AO * BO
Sl = Al + BI

1-120

000
001

Y

010

OUT

011

Sl

SO

Up to 8-input function

Figure 3. C-Module Implementation

I

III

ACT 1 and ACT 2 Military FPGAs

The sequential module implements this same function Z, followed
by a sequential block. The sequential block can be configured to
implement either a D-type flip-flop or transparent latch. It can also
be fully transparent so that S-modules can be used to implement

purely combinatorial functions. The function of the sequential
module is determined by the macro selection from the design
library of hard macros. Allowable S-module implementations are
shown in Figure 4.

000

000

ClR

001

y

010

001
OUT

ClK

y

010

011

OUT

GATE

011

so

so

Up to 7-input function plus latch

Up to 7-input function plus Ootype flip-flop with clear

000

ClR

00

001

y

01

OUT

y

010

GATE

OUT

I

011

s

Up to 4-input function plus latch with clear

Up to 8-input function (same as C-Module)

Figure 4. S-Module Implementations

I/Os
The I/O architecture consists of pad drivers located near the
bonding pads and I/O modules located in the array. Top/bottom
I/O modules are located in the top and bottom rows respectively.
Side I/O modules occupy the leftmost two columns and the
rightmost two columns of the array. The function of all I/O
modules is identical, but the top/bottom I/O modules have a
different routing interface to the array than the side I/O modules.
I/Os implement a variety of user functions determined by library
macro selection.

Special Purpose I/Os

Table 2. Special I/O Pads
SDI

Serial Data In

SDIO

Serial Data Out

BININ

Binning Circuit In

BINOUT

Binning Circuit Out

DCLK

Serial Data Clock In

PRA

Probe A Output

PRB

Probe B Output

Certain I/O pads are temporarily used for programming and
testing the device. During normal user operation, these special I/O
pads are identical to other I/O pads. The following special I/O pads
and their functions are shown in Table 2.

1-121

Two other pads, CLKA and CLKB, also differ from normal l/Os in
that they can be used to drive the global clock networks. Power,
Ground, and Programming pads are not considered I/O functions.
Their function is summarized as follows:
VCCA, VCCQ, VCCI

Power

GNDA, GNDQ, GNDI

Circuit Ground

VSV, VKS

Programming Pads

MODE

Program/Debug Control

TO TRACKS

TO PAD BUffER

EN - - - - - - - - - - - - - -.... EN

mw

(regie::: ~
U02

:

Y

j

.mw

1--.-----.... DATAOUT

~L
GOUT------~

I/O Pads
I/O pads are located on the periphery of the die and consist of the
bonding pad, the high-drive CMOS drivers, and the TIL
level-shifter inputs. Each I/O pad is associated with a specific I/O
module. Connections form the I/O pad to the I/O module are
made using the signals DATAOUT, DATAIN and EN (shown in
Figure 5).
OUTEN
(global)

y-----...--I
DATAIN

SELECT
GIN - - - - - - - - - '
INEN
(global)

EN

SIEW

Figure 6. I/O Module
-------+-~

SEL
DATAOUT

-----I

DO

D1

SDATA
DATAIN

--------------------1
Figure 5. I/O Pad Signals

I/O Modules
There are two types of I/O modules: side and top/bottom. The I/O
module schematic is shown in Figure 6. In the side I/O modules,
there are two inputs supplying the data to be output from the chip:
U01 and U02. (UO stands for user output). Two are used so that
the router can choose to take the signal from either the routing
channel above or the routing channel below the I/O module. The
top/bottom I/O modules interact with only one channel and
therefore have only one UO input.

1-122

The EN input enables the tristate output buffer. The global signals
INEN and OUTEN (Figure 5) are used to disable the inputs and
outputs during certain test modes. Latches are provided in the
input and output path. When GOUT is low, the output signal on
U01/U02 is latched. When it is high, the latch is transparent. The
latch can be used as the second stage of a rising-edge flip-flop as
described in the Applications note accompanying this data sheet.
GIN is the reverse of GOUT. When GIN is high, the input data is
latched; when it is low, the input latch becomes transparent.
The output of the module, Y, is used for data being input to the
chip. Side I/O modules have a dedicated output segment for Y
extending into the routing channels above and below it (similar to
logic modules). Side I/O modules may also connect to the array
through nondedicated Long Vertical Tracks (LVTs). Top/Bottom
I/O modules have no dedicated output segment. Signals coming
into the chip from the top or bottom must be routed using F-fuses
and LVTs (F-fuses and LVTs are explained in detail in the routing
section). As a result, I/O signals connected to I/O modules on
either the top or bottom of the array may incur a slight delay
penalty ( -InS) over signals connected to I/O modules on the sides.

ACT 1 and ACT 2 Military FPGAs

Routing Structure

Horizontal Routing

The ACT 2 architecture uses Vertical and Horizontal routing
tracks to interconnect the various Logic and I/O modules. These
routing tracks are metal interconnects that may either be of
continuous length or broken into pieces called segments. Segments
can be joined together at the ends using antifuses to increase their
lengths up to the full length of the track.

Horizontal channels are located between the rows of modules and
are composed of several routing tracks. The horizontal routing
tracks within the channel are divided into one or more segments.
The minimum horizontal segment length is the width of a
module-pair, and the maximum horizontal segment length is the
full length of the channel. Any segment that spans more than
one-third the row length is considered a long horizontal segment.
A typical channel is shown in Figure 7. Nondedicated horizontal
routing tracks are used to route signal nets. Dedicated routing
tracks are used for the global clock networks and for power and
ground tie-off tracks.

MODULE ROW
CLKO

,

TRACK_
SEGMENTS

,

0

NVCC
SIGNAL

0
0

SIGNAL
(LHT)

0
0

0
0

HF-

0

0

0
0

0

I
I
I
I
I
I
I
SIGNAL
NVSS
CLK1

MODULE ROW

Figure 7. Horizontal Routing Tracks and Segments

1-123

I

Vertical Routing
Other tracks run vertically through the modules. Vertical tracks are
of three types: input, output, and long. Vertical tracks are also
divided into one or more segments. Each segment in an input track
is dedicated to the input of a particular module. Each segment in an
output track is dedicated to the output of a particular module. Long
segments are uncommitted and can be assigned during routing.
Each output segment spans four channels (two above and two
below), except near the top and bottom of the array where edge
effects occur. LVTs contain either one or two segments. An
example of vertical routing tracks and segments is shown in Figure 8.

An antifuse is a "normally open" structure as opposed to the
normally closed fuse structure used in PR OMs or PAL®s. The use
of antifuses to implement a Programmable Logic Device results in
highly testable structures as well as efficient programming
algorithms. The structure is highly testable because there are no
pre-existing connections, therefore temporary connections can be
made using pass transistors. These temporary connections can
isolate individual antifuses to be programmed as well as isolate
individual circuit structures to be tested. This can be done both
before and after programming. For example, all metal tracks can be
tested for continuity and shorts between adjacent tracks, and the
functionality of all logic modules can be verified.

Antifuse Structures

c

:::> LVTs
MODULE ROW

C-MODULE

S-MODULE

V~.

..

CHANNEL

'III

VERTICAL INPUT
SEGMENT C

XF

C

•• FF
S-MODULE

C-MODULE

Figure 8. Vertical Routing Tracks and Segments

Antifuse Connections
Four types of antifuse connections are used in the routing structure
of the Act 2 array. (The physical structure of the antifuse is identical
in each case, only the usage differs.) The four types are:
XF

Cross connected antifuse

Most intersections of horizontal and vertical tracks have an XF that connects the
perpendicular tracks.

HF

Horizontally connected antifuse

Adjacent segments in the same horizontal track are connected end-to-end by an HF.

VF

Vertically connected antifuse

Some long vertical tracks are divided into two segments. Adjacent long segments
are connected end-to-end by a VF.

FF

"Fast-Fuse" antifuse

The FF connects a module output directly to a long vertical track.

Examples of all four antifuse connections are shown in Figures 7 and 8.

1-124

ACT 1 and ACT 2 Military FPGAs

Antlfuse Programming
The ACT 2 family uses the PLICE antifuse developed by Actel.
The PLICE element is programmed by placing a high voltage ( - 20 V)
across the element and supplying current (-5 rnA) for a short
duration ( < ImS). In the ACT 2 architecture, most antifuses are
programmed to - 500 ohms resistance, except for the F-fuses which
are programmed to -250 ohms. The programming circuits are
transparent to the user.

Clock Networks

The user configures the clock module by selecting one of two clock
macros from the macro library. The macro CLKBUF is used to
connect one of the two external clock pins to a clock network, and
the macro CLKINT is used to connect an internally generated
clock signal to a clock network. Since both clock networks are
identical, the user does not care whether CLKO or CLKI is being
used.
The clock input pads may also be used as normal I/Os, by-passing
the clock networks.

Module Interface

Two low-skew, high fan-out clock distribution networks are
provided in the Act 2 architecture (Figure 9). These networks are
referred to as CLKO and CLK1. Each network has a clock module
(CLKMOD) that selects the source of the clock signal and may be
driven as follows:

Connections to Logic and I/O modules are made through vertical
segments that connect to the module inputs and outputs. These
vertical segments lie on vertical tracks that span the entire height of
the array.

1. externally from the CLKA pad

Module Input Connections

2. externally from the CLKB pad

Vertical tracks span the vertical height of the array. The tracks
dedicated to module inputs are segmented by pass transistors in
each module row. During normal user operation, the pass
transistors are inactive (oft), which isolates the inputs of a module
from the inputs of the module directly above or below it. During
certain test modes, the pass transistors are active (on) to verify the
continuity of the metal tracks. Vertical input segments span only
one channel. Inputs to the array modules come either from the
channel above or the channel below. The logic modules are
arranged such that half of the inputs are connected to the channel
above and half of the inputs to segments in the channel below
(Figure 10).

3. internally from the CLKINA input
4. internally from the CLKINB input
The clock modules are located in the top row of I/O modules. Clock
drivers and a dedicated horizontal clock track are located in each
horizontal routing channel.

[ ~~:

CLKINB
CLKINA

I :ROM
PADS

SO

1

INTERNAL
SIGNALS

S1

CLKO 17
CLOCK

I

Module Output Connections
Module outputs have dedicated output segments. Output segments
extend vertically two channels above and two channels below,
except at the top or bottom of the array. Output segments twist, as
shown in Figure 10, so that only four vertical tracks are required.

LVT Connections

DRIVERS~

CLKO(16)

CLKO(15)

CLKO(2)

Outputs may also connect to nondedicated segments, (LVTs). Each
module pair in the array shares three LVTs that span the length of
column as shown in Figure 9. Any module in the column pair can
connect to one of the LVTs in the column using an FF connection.
The FF connection uses anti fuses connected directly to the driver
stage of the module output, by-passing the isolation transistor. FF
antifuses are programmed at a higher current level than HF, VF, or
XF antifuses to produce a lower resistance value.

Antifuse Connections
CLKO(1)

CLOCK TRACKS

In general every intersection of a vertical segment and a horizontal
segment contains an unprogrammed antifuse (XF-type). One
exception is in the case of the clock networks.

Figure 9. Clock Networks

1-125

I

I

I

I Y+2

I

I

Yf

Y+2 Y+1

I

I I

81
A1

I I

D01 DOO

80

AO

D10 D11

III

---!,Y

I

/

I

~Y-1

I

I
I
~Y-21

I

Y-2

LVTs
S-MODULES

C-MODULES

Figure 10. Logic Module Routing Interface

Clock Connections
To minimize loading on the clock networks, only a subset of inputs
has fuses on the clock tracks. Only a few of the C-module and

S-module inputs can be connected to the clock networks. To further
reduce loading on the clock network, only a subset of the horizontal
routing tracks can connect to the clock inputs of the S-Module.
Both of these are illustrated in Figure 11.

MODULE
C1

C2

CLKO

}

CLK1

}

Antifuses
Deleted

Figure 11.

1-126

CI~

Tracks

No_

Routing
Tracks

ACT 1 and ACT 2 Military FPGAs

registers surrounding the array. Data is clocked into these registers
using the DCLK pin. The registers are connected as a long series of
shift registers as shown in Figure 12. The Mode register determines
the test or programming state of the device. Many of the test modes
are used during wafer sort and final test at the factory. Other test
modes are used during programming in the Activator 2, and some
of the modes are available only after programming. The
Actionprobe function is one such function available to users.

Programming and Test Circuits
The array of logic and I/O modules is surrounded by test and
programming circuits controlled by the external pins: MODE, SDI,
and DCLK. The function of these pins is summarized below. When
MODE is low (GND), the device is in normal or user mode. When
MODE is high (VCC), the device is placed into one of several
programming or test states. The sm pin (when MODE is high) is
used to input serial data to the Mode register and various address

MODE REGISTER

r--r-t

Y1

Y1 REGISTER

Y1

Y2 < 0 >

Y2 REGISTER

Y2

"v

!oof--,------....u SOl

"v

'-

'-

X

C\I

x

I
II:
LU

II:
LU

~

aLU

MODULE ARRAY

II:

II:

X

~

"

o

X

~

"

o
V

SDO

~

aLU

V

OTHER REGISTERS

Figure 12. ACT 2 Shift Register

Actionprobe
If a device has been successfully programmed and the security fuse
has not been programmed, any internal logic or I/O module output
can be observed using the Actionprobe circuitry and the PRA
and/or PRB pins. The Actionprobe Diagnostic system provides the
software and hardware required to perform real-time debugging.
The software automatically performs the following functions.

A pattern of "Is" and "Os" is shifted into the device from the SDI
pin at each positive edge transition of DCLK. The complete
sequence contains 10 bits of counter, 21 bits of Mode Register, n
bits of zeros (filler of unused fields, where n depends on the
particular device type), R bits ofX2, C bits ofY2, R bits of Xl, C bits
ofY1, and a stop bit ("0" or "I"). After the stop bit has been shifted
in, DCLK is left high (see definitions below). Xl and Y1 represent
the (X,Y) location in the array for the Actionprobe output, PRA.

1-127

and the selected row and column is "high." The timing sequence is
shown in Figure 13. The recommended frequency is 10 MHz with
10 nS setup and hold times allowing for SDI and DCLK transitions.
The selected module output will be present at the PRA or PRB
output approximately 20 nS after the stop-bit transition.

X2 and Y2 represent the (X,Y) location in the array for the
Actionprobe output, PRB. Rand C are the row and column size as
defined in Table 1. The filler bits, counter pattern, and Mode
register pattern are shown in Table 3. Addressing for rows and
columns is active high, i.e. unselected rows and columns are "zeros"

Table 3. Bit Stream Definitions for Actlonprobe Diagnostics
Counter_Pattern
Probe_Mode
Filler (n)
Device

Mode_Register_Pattern

# of clocks

A1280

Probe A only

443

0011011111

000000110001111100000

675

A1280
A1280

Probe B only
Probe A and B

443
443

0011011111
0011011111

000000101001111100000
000000111001111100000

675
675

A1240

Probe A only

361

1111000001

000000110001111100000

541

A1240

Probe Bonly
Probe A and B

361

1111000001
1111000001

000000101001111100000
000000111001111100000

541
541

Probe A only
Probe B only

308
308
308

1101011010

000000110001111100000

458

1101011010
1101011010

000000101001111100000
000000111001111100000

458
458

A1240
A1225
A1225
A1225

Probe A and B

361

For Example: Selecting PRA for A1280 results in the following bit stream:
0011011111 000000110001111100000
(443 zerOS)j<2<0> ... X2< 17> _Y2<81 > ... Y2<0> _X1 <0> ... X1 <0> ... X1 <17> _Y1 <0> ...Y1 <81 > _0,
where "_" is used for clarity only.

I--

LOAD COUNTER

-+-

FILLER ZEROS
LOAD MODE REG

---I Ir--- x, Y ADDRESS --.j S~~P I--- PROBING --I ~6fo--

MODE~

Figure 13. Timing Waveforms

1-128

ACT 1 and ACT 2 Military FPGAs

Military Device Ordering Information
A

A1010

-

PG

1

84

B

I

Applicat;on (Temperature Range)
C = Commercial (0 to + 75°C)
M = Military (-55 to + 125°C)
B = MIL-STD-883

Package Lead Count
Package Type
CQ = Ceramic Quad Flatpack
JQ = J-Ieaded Cerquad Chip Carrier
PG = Ceramic Pin Grid Array
Speed Grade
Std = Standard Speed
-1 = Standard + 15% Speed
Die Revision
Part Number
A1010A
A1020A
A1240
A1280

-1200
-2000
-4000
-8000

Gates
Gates
Gates
Gates

I

SMD Drawing Number to Actel Part Number Cross Reference

SMD Number

Cage Number

Actel Part Number

5962-9096401 MZX

OJ4Z0

A1010A-PG84B

5962-9096501 MXX

OJ4Z0

A1020A-JQ44B

5962-9096501 MYX

OJ4Z0

A1020A-JQ68B

5962-9096501 MZX

OJ4Z0

A1020A-JQ84B

5962-9096501 MUX

OJ4Z0

A1020A-PG84B

5962-9096501 MTX

OJ4Z0

A1020A-CQ848

1-129

Product Plan
Speed Grade
Std
-1*

C

Application
M
B

E

A 1280 Device
176-pln Ceramic Pin Grid Array (PG)
172-pin Ceramic Ouad Flatpack (CO)

t/
t/

P
P

t/
t/

t/
t/

t/
t/

t/

P

t/

t/

t/

t/
t/
t/
t/
t/

t/
t/
t/
t/
t/

t/
t/
t/
t/
t/

t/
t/
t/
t/
t/

t/
t/
t/
t/
t/

t/

t/

t/

A 1240 Device
132-pin Ceramic Pin Grid Array (PG)
A 1020A Device
84-pin
84-pin
84-pin
68-pin
44-pin

Ceramic Pin Grid Array (PG)
Ceramic Ouad Flatpack (CO)
J-Ieaded Cerquad Chip Carrier (JO)
J-Ieaded Cerquad Chip Carrier (JO)
J-Ieaded Cerquad Chip Carrier (JO)

A1010A Device
84-pin Ceramic Pin Grid Array (PG)
Applications:C = Commercial
M = Military
B = MIL-STD-883C
E = Extended Flow

Availability: t/ = Available
P = Planned
- = Not Planned

* Speed Grade:

-1 = 15% faster than Standard

Device Resources
User I/Os
CPGA

CQFP

Logic
Modules

Gates

176-pln

A1280

1232

8000

140

A1240

684

4000

A1020A

547

2000

69

A1020A

295

1200

57

Device

1-130

132-pln

84-pin

172-pin

JQCC

84-pin

84-pln

68-pin

44-pin

69

69

57

34

140
104

ACT 1 and ACT 2 Military FPGAs

Pin Description
ClKA

Clock A (Input)

TIL Clock input for clock distribution networks. The Clock input
is buffered prior to clocking the logic modules. This pin can also be
used as an 1/0.

ClKB

Clock B (Input)

TTL Clock input for clock distribution networks. The Clock input
is buffered prior to clocking the logic modules. This pin can also be
used as an I/O.

OClK

Diagnostic Clock (Input)

TIL Clock input for diagnostic probe and device programming.
DCLK is active when the MODE pin is HIGH. This pin functions
as an I/O when the MODE pin is LOW.

GNO

Ground (Input)

Input LOW supply voltage.

I/O

Input/Output (Input, Output)

I/O pins function as an input, output, three-state, or bidirectional
buffer. Input and output levels are compatible with standard TIL
and CMOS specifications. Unused I/O pins are automatically
driven LOW by the ALS software.

MODE

Mode (Input)

The MODE pin controls the use of multi-function pins (DCLK,
PRA, PRB, SDI, SDO). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is LOW, the pins
function as I/0s.

NC

PRB

Probe B (Output)

The Probe B pin is used to output data from any user-defined
design node within the device. This independent diagnostic pin is
used in conjunction with the Probe A pin to allow real-time
diagnostic output of any signal path within the device. The Probe B
pin can be used as a user-defined I/O when debugging has been
completed. The pin's probe capabilities can be permanently
disabled to protect programmed design confidentiality. PRB is
active when the MODE pin is HIGH. This pin functions as an I/O
when the MODE pin is LOW.

SOl

Serial Data Input (Input)

Serial data input for diagnostic probe and device programming.
SDI is active when the MODE pin is HIGH. This pin functions as
an I/O when the MODE pin is LOW.

SOO

Serial Data Output (Output)

Serial data output for diagnostic probe. SDO is active when the
MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.

Vee

Supply Voltage (Input)

Input HIGH supply voltage.

VKS

Programming Voltage (Input)

Input supply voltage used for device programming. This pin must
be connected to GND during normal operation.

No Connection

This pin is not connected to circuitry within the device.

PRA

pin can be used as a user-defined I/O when debugging has been
completed. The pin's probe capabilities can be permanently
disabled to protect programmed design confidentiality. PRA is
active when the MODE pin is HIGH. This pin functions as an I/O
when the MODE pin is LOW.

Probe A (Output)

The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic pin is
used in conjunction with the Probe B pin to allow real-time
diagnostic output of any signal path within the device. The Probe A

Vpp

Programming Voltage (Input)

Input supply voltage used for device programming. This pin must
be connected to Vee during normal operation.

Vsv

Programming Voltage (Input)

Input supply voltage used for device programming. This pin must
be connected to Vee during normal operation.

1-131

•

Actel Military Product Flow
Step

883C-Class B
883C Method

Screen

883C-Class B
Requirement

Military
Datasheet
Requirement

1.0

Internal Visual

2010, Test Condition B

100%

100%

2.0

Temperature Cycling

1010, Test Condition C

100%

100%

3.0

Constant Acceleration

2001, Test Condition E
(min), Y1, Orientation only

100%

100%

4.0

Seal
a. Fine
b. Gross

1014
100%
100%

100%
100%

5.0

Visual Inspection

100%

100%

6.0

Pre Burn-in
Electrical Parameters

In accordance with Actel
applicable device specifications

100%

N/A

7.0

Burn-in Test

1015 Condition D
160 hours @ 125°C Min.

100%

N/A

B.O

Interim (post burn-in)
Electrical Parameters

In accordance with Actel
applicable device specifications

100%

100%
(as final test)

9.0

Percent Defective Allowable

5%

All Lots

N/A

Final Electrical Test

In accordance with Actel
applicable device specifications

a. Static Tests
(1) 25°C
(Subgroup 1, Table I, 5005)
(2) -55°C and + 125°C.
(Subgroups 2, 3, Table I, 5005)

100%

100%

b. Dynamic and Functional Tests
(1) 25°C
(Subgroup 7, Table I, 5005)
(2) -55°C and + 125°C.
(Subgroups BA and B8, Table I, 5005)

100%

100%

c. Switching Tests at 25°C
(Subgroup 9, Table I, 5005)

100%

100%

10.0

11.0

Qualification or Quality
Conformance Inspection Test
Sample Selection (Group A)

S005

All Lots

N/A

12.0

External Visual

2009

100%

Actel specification

1-132

ACT 1 and ACT 2 Military FPGAs

Actel Extended Flow 1, 2
Method

Screen

1.
2.

Wafer Lot

Acceptance3

Destructive In-Line Bond

Pull 4

Requirement

5007 with step coverage waiver

All Lots

2011, condition D

Sample

3.

Internal Visual

2010, condition A

100%

4.

Temperature Cycling

1010, condition C

100%

5.

Constant Acceleration

2001, condition E (min) Y1 orientation only

100%

6.

Visual Inspection

2009

100%

7.

Particle Impact Noise Detection

2020, condition A

100%

8.

Serial ization

9.

Pre Burn-in Electrical Parameters

In accordance with Actel applicable device specification

100%

10.

Burn-in Test

1015,240 hours @ 125°C minimum

100%

11.

Interim (Post Burn-in) Electrical Parameters

In accordance with Actel applicable device specification

100%

12.

Reverse Bias Burn-in

1015, condition A or C, 72 hours @ 150°C minimum

100%

13.

Interim (Post Burn-in) Electrical Parameters

In accordance with Actel applicable device specification

100%

14.

Percent Defective Allowable (PDA) Calculation

5%,3% functional parameters @ 25°C

15.

Final Electrical Test

In accordance with Actel applicable device specification

a.

b.

c.
16.

Static Tests
(1) 25°C
(Subgroup 1, Table 1)
(2) -55°C and 125°C
(Subgroups 2, 3, Table 1)
Dynamic or Functional Tests
(1) 25°C
(Subgroup 4 or 7, Table 1)
(2) -55°C and 125°C
(Subgroups 5 and 6, or 8 a and b, Table 1)
Switching Tests at 25°C
(Subgroup 9, Table 1)

Seal
a.
b.

100%

All Lots
100%
100%

5005
5005
100%
5005
5005
5005

100%

1014

100%

100%

Fine
Gross

17.

Radiographic

2012, two views

18.

Qualification or Quality Conformance Inspection
Test Sample Selection

5005

Per
Group A

19.

External Visual

2009

100%

Notes:
1. Actel offers the Extended Flow in order to satisfy those customers that
require additional screening beyond the requirements of
MIL-SID-883C, Class B. Actel is compliant to the requirements of
MIL-SID-883C, Paragraph 1.2.1, and MIL-M-3851O Appendix A.
Actel is offering this extended flow incorporating the majority of the
screening procedures as outlined in Method 5004 of MIL-SID-883C
Class S. The exceptions to Method 5004 are as shown in Notes 2-4
below.

2. Method 5004 requires 100% Radiation Latch-up testing to Method
1020. Actel will not be performing any radiation testing and this
requirement must be waived in its entirety.
3. Wafer lot acceptance is performed to Method 5007, however the step
coverage requirement as specified in Method 2018 must be waived.
4. Method 5004 requires a 100%, Non-Destructive Bond Pull to Method
2023. Actel substitutes a Non-Destructive Bond Pull to Method 2011,
condition D on a sample basis only.

1-133

I

Absolute Maximum Ratings

Recommended Operating Conditions

Free air temperature range

Parameter

Symbol

Limits

Units

Parameter
Temperature
Range 1

Vee

DC Supply Voltage 1, 2,

-0.5 to +7.0

Volts

VI

Input Voltage

-0.5 to Vee + 0.5

Volts

Vo

Output Voltage

-0.5 to Vee + 0.5

Volts

11K

Input Clamp Current

±20

mA

10K

Output Clamp Current

±20

mA

10K

Continuous Output Current

±25

mA

T STG

Storage Temperature

-65 to +150

°C

3

Commercial

o to

Power Supply
Tolerance

+70

±5

Military

Units

-55 to + 125

°C

±10

%Vee

Note:
1. Ambient temperature (fA) is used for commercial and industrial; case
temperature (fc) is used for military.

Stresses beyond those listed above may cause permanent damage to the
device, Exposure to absolute maximum rated conditions for extended
periods may affect device reliability. Device should not be operated
outside the Recommended Operating Conditions.
Notes:
1. V pp = Vee, except during device programming.
2. Vsv = Vee, except during device programming.
3. V KS = GEN, except during device programming.

Package Thermal Characteristics
The device junction to case thermal characteristic is ajc, and the
junction to ambient air characteristic is aja. The thermal
characteristics for aja are shown with two different air flow rates.

Maximum junction temperature is 150°C.
A sample calculation of the maximum power dissipation for a
CPGA 176-pin package at military temperature is as follows:

Max. junction temp. (0C) - Max. military temp. (0C)
aja (OC/W)

150°C - 125°C

= 1.2W

20°C/W

ala
Stili air

ala
300 ft/min~nits

Pin Count

alc

Ceramic Pin Grid Array

84
132
176

8
5
2

33
30
20

20
15
8

Ceramic Quad Flatpack

84
172

5

40

30

°cm
°cm
°cm
°cm

J-!eaded Cerquad Chip Carrier

44

8
8
8

38
35
34

30
25
24

°cm
°cm
°cm

Package Type

68
84

1-134

ACT 1 and ACT 2 Military FPGAs

ACT 1 Electrical Specifications
Military

Commercial
Parameter

Max.

Min.

= -4 mAl
(IOH = -3.2 mAl
(IOl = 4 mAl
(IOH

VOH 1
VOL l

Max.

Min.

I
I

Units

V

3.84

V

3.7
0.33

0.40

V
V

VIL

-0.3

0.8

-0.3

0.8

VIH

2.0

Vee + 0.3

2.0

Vee + 0.3

V

500

ns

500

Input Transition Time t R• tF2
CIO I/O Capaeitanee2. 3

10

10

pF

Standby Current. lee 4

10

25

mA

Leakage Current!>
(Vo

los Output Short
Circuit Currents

(Vo

= Vecl
= GND)

-10

10

-10

10

pA

20

140

20

140

mA

-10

-100

-10

-100

mA

Notes:
1. Only one output tested at a time. Vee = min.
2. Not tested. for information only.
3. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f = 1 MHz.
4. 'lYpical standby current = 3 rnA. All outputs unloaded. All inputs = Vee or GND.
5. Va. V IN = Vee or GND.
6. Only one output tested at a time. Min. at Vee = 4.5 V; Max. at Vee = 5.5 V.

I

ACT 2 Electrical Specifications
Commercial

Military

Parameter

Units

Min.
VOH l
VOll

= -6 mAl
= -4 mAl
(IOL = 6 mAl
(lOH

Max.

Min.

Max.

3.84

V

3.7

(IOH

V

0.40

0.33

VIL

-0.3

0.8

-0.3

0.8

V

VIH

2.0

Vee + 0.3

2.0

Vee + 0.3

V

500

500

ns

CIO I/O Capaeitanee2. 3

10

10

pF

Standby CUrrent. lee4

10

25

mA

10

pA

Input Transition Time t R• tF2

Leakage Current!>

-10

Notes:
1. Only one output tested at a time. Vee = min.
2. Not tested. for information only.
3. Includes worst-case 176-pin CPGA package capacitance. V OUT
4. All outputs unloaded. All inputs = Vee or GND.
5. Va. V IN = VeeorGND.

10

-10

= 0 V, f = 1 MHz.

1-135

ACT 1 Power Dissipation

ACT 2 Power Dissipation

The following formula is used to calculate total device dissipation.

P

Total Device Power (m W)
(0.80 x P x F3)

= (0.20 x N x F1) + (0.085 x M x F2) +

lactive is the current flowing due to CMOS switching.

= Average logic module switching rate in MHz

F2 = CLKBUF macro switching rate in MHz
F3

= Average I/O module switching rate in MHz

M

=

Number of Logic modules connected to the CLKBUF
macro

N

=

Total number of Logic modules used in the design
(including M)

P

=

Number of outputs loaded with 50 pF

Average switching rate of logic modules and of I/O modules is
some fraction of the device operating frequency (usually
CLKBUF). Logic modules and I/O modules switch states (from
low-to-high or from high-to-Iow) only if the input data changes
when the module is enabled. A conservative estimate for average
logic module and I/O module switching rates (variables F1 and F3,
respectively) is 10% of device clock driver frequency.
If the CLKBUF macro is not used in the design, eliminate the
second term (including F2 and M variables) from the formula.

Sample A 1020 Device Power Calculation
To illustrate the power calculation, consider a large design
operating at high frequency. This sample design utilizes 85% of
available logic modules on the AlO20-series device (.85 x 547 = 465
logic modules used). The design contains 104 flip-flops (208 logic
modules). Operating frequency of the design is 16 MHz. In this
design, the CLKBUF macro drives the clock network. Logic
modules and I/O modules are switching states at approximately
10% of the clock frequency rate (.10 x 16 MHz = 1.6 MHz). Sixteen
outputs are loaded with 50 pF.
To summarize the design described above: N = 464; M = 208;
F2 = 16; F1 = 4; F3 = 4; P = 16. Total device power can be
calculated by substituting these values for variables in the device
dissipation formula.
Total device power for this example

=

(0.20 x 465 x 1.6) + (0.085 x 208 x 16) + (0.80 x 16 x 1.6) = 452 m W

1-136

lou Vou N + IOH·(Vcc-V oH)·M

Icc is the current flowing when no inputs or outputs are changing.

Where:
F1

= [Icc + lactive] • Vee +

Where:

IOL' IOH are TTL sink/source currents.
VOL, V OH are TTL level output voltages.
N equals the number of outputs driving TTL loads to VOL.
M equals the number of outputs driving TTL loads to V OH .
An accurate determination of Nand M is problematical because
their values depend on the design and on the system I/O. The
power can be divided into two components: static and active.
Static Power

Static power dissipation is typically a small component of the
overall power. From the values provided in the Electrical
Specifications, the maximum static power (commercial) dissipation is:
10 mAx 5.25 V

= 52.5 mW

The static power dissipated by TTL loads depends on the number
of outputs that drive high or low and the DC lead current flowing.
Again, this number is typically small. For instance, a 32-bit bus
driving TTL loads will generate 42 m W ATT with all outputs
driving low or 140 mW with all outputs driving high. The actual
dissipation will average somewhere between as I/Os switch states
with time.
Active Power

The active power component in CMOS devices is frequency
dependent and depends on the user's logic and the external I/O.
Active power dissipation results from charging internal chip
capacitance such as that associated with the interconnect,
unprogrammed antifuses, module inputs, and module outputs plus
external capacitance due to PC board traces and load device inputs.
An additional component of active power dissipation is due to
totem-pole current in CMOS transistor pairs. The net effect can be
associated with an equivalent capacitance that can be combined
with frequency and voltage to represent active power dissipation.

ACT 1 and ACT 2 Military FPGAs

Equivalent Capacitance

Module Utilization = 80% of combinatorial modules

The power dissipated by a CMOS circuit can be expressed by
Equation 1.

Average Module Frequency = F/l0
Inputs

Power (}JW) = CEQ. V cc 2 • f

Average Input Frequency = F/5

(1)

Where:

= 1/3 of I/O

Outputs = 2/3 of I/Os

CEQ is the equivalent capacitance expressed in pE

Average Output Frequency = F/l0

Vee is power supply in volts.

Clock Net 1 Loading = 40% of sequential modules

f is the switching frequency in MHz.

Clock Net 1 Frequency = F

Equivalent capacitance is calculated by measuring Iactive at a
specified frequency and voltage for each circuit component of
interest. The results for ACT 2 devices are:

7.7
18.0
25.0
2.5

The results of estimating active power are displayed in Figure 14.
The graphs provide a simple guideline for estimating power. The
tables may be interpolated when your application has different
resource utilizations or frequencies.

To calculate the active power that is dissipated from the complete
design, you must solve Equation 1 for each component. In order to
do this, you must know the switching frequency of each part of the
logic. The exact equation is a piece-wise linear summation over all
components, as shown in Equation 2.
Power = [(m. 7.7 • f1) + (n. 18.0. f2)
+ (q. 2.5 • t)] • V CC2

Clock Net 2 Frequency = F/2
Estimated Power

CEQ(PF)
Modules
Input Buffers
Output Buffers
Clock Buffer Loads

Clock Net 2 Loading = 40% of sequential modules

3.0

// / /

2.0

+ (p • (25.0 + C L) . f3)
(2)

1.0

Where:
n

Number of logic modules switching at frequency fl

m

Number of input buffers switching at frequency f2

p

Number of output buffers switching at frequency f3

q

Number of clock loads on the global clock network

f1

Average logic module switching rate in MHz

f2

Average input buffer switching rate in MHz

~

V

Average output buffer switching rate in MHz

/

~

// ),/
V /

/

0.1

/

L
A1240

/

Frequency of global clock

f3

•

A/ /

/ /

/

/

/

V

./

C L = Output load capacitance
Determining Average Switching Frequency

In order to determine the switching frequency for a design, you
must have a detailed understanding of the data input values to the
circuit. The following rules will help you to determine average
switching frequency in logic circuits. These rules are meant to
represent worst-case scenarios so that they can be generally used
for predicting the upper limits of power dissipation. These rules are
as follows:

1.0

10.0

100.0

MHz
Figure 14. ACT 2 Power Estimates

1-137

Parameter Measurement
Output Buffer Delays

o

To AC test loads (shown below)

Vee

Vee

GND

GND

GND
VOH

PAD

PAD

PAD
GND

VOL
toLH

tENZL

toHL

90%

1.5V

~NLZ

~NHZ

tENZH

AC Test Loads
Load 1
(Used to measure propagation delay)

Load 2
(Used to measure rising/failing edges)

GND

Vee

•

To the output under test

)>------'l

T

•

50PF

R to Vee for tpLZ/tpZL

Rto GND for tpHZ/tpZH
To the output under test ) - - - - .

R = 1 kQ

50PF

T
Input Buffer Delays

Combinatorial
Macro Delays

Vee

s, ~ V"50%

GND

50 o/:-r-.,.
Vee

y

/V50 %

"",50%

GND
t pLH

tpHL

Y

GND
~NYH

1-138

Vee
500/.:,
tpHL

tlNYL

GND
tpLH

/"50%

ACT 1 and ACT 2 Military FPGAs

Sequential Timing Characteristics
Flip-Flops and Latches

PRE

D

Q

E

CLK

CLR
(Positive edge triggered)

-l ItHO

D1 ____~)(~______________________) ( - - - - - - - - - - - - - - -

I--

tSUD

I-

--l

t

-I

WCLKA

______~
-l I---

CLK __________~~I--~

r--

tSUENA

1. .
I

----1--11
~____~~

1-----

tWCLKI

tA

---I

•

HtHENA

E

------------------------------~

I
-J)(

)(_________

Q ____________________________

I-

PRE,CLR

tSUASYN - /

j.- t

--------~~I------------------------------~I

I-

pD

.,

I~______________
tWASYN -/

Notes:
1. D represents all data functions involving A, B, and S for multiplexed flip-flops.

1-139

Sequential Timing Characteristics (continued)
Input Buffer Latches (ACT 2 only)

ISDl

ClK

X

PAD

--l

I

G

X
tlNH

I-

I-

t lNSU

--l

tHEXT

I-

I

ClK

I-

tSUEXT

Output Buffer Latches (ACT 2 only)

:~OOOLHS~
--~)(-------------------~)(~----l

toUTSU

I-

----------------~I--------------

--l

1-140

toUTH

ACT 1 and ACT 2 Military FPGAs

capacItIve loading of the macro's inputs, as well as the
interconnect's resistance and capacitance.

Timing Characteristics
Timing characteristics for ACT arrays fall into three categories:
family dependent, device dependent, and design dependent. The
output buffer characteristics are common to all ACT 2 family
members. Internal module delays are device dependent. Internal
wiring delays between modules are design dependent. Design
dependency means actual delays are not determined until after
placement and routing of the users design is complete. Delay values
may then be determined by using the ALS Timer utility or
performing simulation with post-layout delays.
The macro propagation delays shown in the Timing Characteristics
tables include the module delay plus estimates derived from
statistical analysis for wiring delay. This statistical estimate is based
on fully utilized devices (90% module utilization).
Critical Nets and Typical Nets

Propagation delays are expressed for two types of nets: critical and
typical. Critical nets are determined by net property assignment
before placement and routing. Up to 6% of the nets in a design may
be designated as critical, while 90% of the nets in a design are
typical.
Fan-Out Dependency

Propagation delays depend on the fan-out (numberofloads) driven
by a macro. Delay time increases when fan-out increases due to the
ACT 1 Timing Derating Factor (x typical)

Long Tracks

Some nets in the design use long tracks. Long tracks are special
routing resources that span multiple rows or columns or modules,
and are used frequently in large fan-out (> 10) situations. Long
tracks employ three and sometimes four antifuse connections. This
increased capacitance and resistance results in longer net delays for
macros connected to long tracks. Typically up to 6% of the nets in a
fully utilized device require long tracks. Long tracks contribute an
additional 10 ns to 15 ns delay.

Timing Derating
Operating temperature, operating voltage, and device processing
conditions, along with device die size and speed grade, account for
variations in array timing characteristics. These variations are
summarized into a derating factor for array typical timing
specifications. The derating factors shown in the table below are
based on the recommended operating conditions for applications.
The derating curves in Figure 15 showworst-to-best case operating
voltage range and best-to-worst case operating temperature range.
The temperature derating curve is based on device junction
temperature. Actual junction temperature is determined from
Ambient Temperature, Power Dissipation, and Package Thermal
characteristics.
ACT 2 Timing Derating Factor (x typical)

Military

Commercial
Speed Grade

BestCase

Worst·
Case

BestCase

WorstCase

Standard Speed
-1 Speed Grade

0.45
0.45

1.54
1.28

0.37
0.37

1.79
1.49

Note:
"Best-case" reflects maximum operating voltage, minimum operating temperature, and best-case processing. "Worst·case" reflects minimum operating voltage, maximum operating temperature, and worst-case processing.
Best-case derating is based on sample data only and is not guaranteed.

Commercial

Military

Speed Grade

BestCase

Worst·
Case

Best·
Case

Worst·
Case

Standard Speed

0.40

1.40

0.35

1.60

Note:
"Best-case" reflects maximum operating voltage, minimum operating temperature, and best-case processing. "Worst-case" reflects minimum operating voltage, maximum operating temperature, and worst-case processing.
Best-case derating is based on sample data only and is not guaranteed.

Voltage Derating Curve

Temperature Derating Curve

1.20

1.40

1.15

1.30

~'

1.10

,g

~

1.05

......

1.00
0.95
0.90

1.20

........

'" "'~

~

.,.... 1'''''''
1.10

0.90
0.80

0.80
4.75

5.0

5.25

0.70
-60

5.5

Vee (Volts)

1'''''''

.,.... ~~

........

0.85

4.5

~

1.00

~

.,....'"

-40 -20

0

20

40

60

80

100

120

Temperature (0C)

Figure 15. Derating Curves

1-141

I

~
ACT 1 Timing Characteristics
Logic Module Timing
= 5.0 V; TA = 25°C; Process = Typical; tpD = 3.0 ns @

Vcc

FO

=0

Single Logic Module Macros
(e.g., most gates, latches, multiplexors)1
Output Net

Parameter

FO

=1

FO

=2

FO

=3

FO

=4

FO

=8

Units

t pD

Critical

5.4

5.8

6.2

8.5

Note 2

ns

tpD

Typical

6.3

6.7

7.7

8.6

10.8

ns

Dual Logic Module Macros
(e.g., adders, wide Input gates)1
Output Net

Parameter

FO

=1

FO

=2

FO

=3

FO

=4

FO

=8

Units

t pD

Critical

9.2

9.6

10.0

12.3

Note 2

ns

t pD

Typical

10.2

10.6

11.6

12.5

14.6

ns

Sequential Element Timing Characteristics
Fan-Out
Parameter

FO

=1

FO

=2

FO

=3

FO

=4

FO

=8

Units

tsu

Set Up Time, Data Latches

3.5

3.9

4.2

4.5

4.8

ns

tsu

Set Up Time, Flip-Flops

3.9

3.9

3.9

3.9

3.9

ns

tH

Hold Time

0

0

0

0

0

ns

tw

Pulse Width, Minimum 3

7.7

8.5

9.2

10.0

14.0

ns

teo

Delay, Critical Net

5.4

5.8

6.2

8.5

Note 2

ns

teo

Delay, Typical Net

6.3

6.7

7.7

8.6

10.8

ns

Notes:
1. Most flip-flops exhibit single module delays.
2. Critical nets have a maximum fan-out of six.
3. Minimum pulse width, tw, applies to CLK, PRE, and CLR inputs.

1-142

ACT 1 and ACT 2 Military FPGAs

~CT

1 Timing Characteristics (continued)

I/O Buffer Timing
Icc = 5.0 V; TA = 25°C;

Process

= Typical

iNBUF Macros
Parameter

From - To

FO

=1

=2

FO

FO = 3

FO

=4

FO

=8

Units

Pad to Y

6.9

7.6

8.9

10.7

14.3

ns

Pad to Y

5.9

6.5

7.7

8.4

12.4

ns

~LKBUF (High Fan-Out Clock Buffer) Macros

Parameter

FO

= 40

FO

= 160

FO = 320

Units

9.0

12.0

15.0

ns

9.0

12.0

15.0

ns

"Iotes:
l. A clock balancing feature is provided to minimize clock skew.

2. There is no limit to the number of loads that may be connected to the
CLKBUF macro.

..

::>UTBUF, TRIBUFF, and BIBUF Macros
~L = 50 pF
TTL

Units

3.9

4.9

ns

7.2

5.7

ns

Parameter

From - To

CMOS

t pHL

o to Pad
o to Pad

t pLH
t pHZ

E to Pad

5.2

3.4

ns

t pZH

E to Pad

6.5

4.9

ns

tpLZ

E to Pad

6.9

5.2

ns

t pZL

E to Pad

4.9

5.9

ns

~hange in Propagation Delay with Load Capacitance

Parameter

From - To

CMOS

TTL

Units

t pHL

o to Pad
o to Pad

0.03

0.046

ns/pF

t pLH

0.07

0.039

ns/pF

t pHZ

E to Pad

0.08

0.046

ns/pF

t PZH

E to Pad

0.07

0.039

ns/pF

t pLZ

E to Pad

0.07

0.039

ns/pF

tpZL

E to Pad

0.03

0.039

ns/pF

\Jotes:
l. The BIBUF macro input section exhibits the same delays as the INBUF

macro.

2. Load capacitance delay delta can be extrapolated down to 15 pF
minimum.
Example:
Delay for OurnUF driving a 100-pF TTL load:
tPHL = 4.9 + (.046 x (100-50)) = 4.9 + 2.3 = 7.2 ns
tpLH = 5.7 + (.039 x (100-50)) = 5.7 + 2.0 = 7.7 ns

1-143

~
A 1280 Timing Characteristics
Propagation Delays

01cc = 5.0 V; TA = 25°C;

Process

= Typical; Derating Required)
FO = 2
FO = 1

Parameter

Description

FO = 3

FO = 4

tpOl

Single Module

Critical

4.5

5.0

5.5

6.0

t p01

Single Module

Typical

5.7

6.2

6.7

8.2

tp02

Dual Module

Critical

7.5

8.0

8.5

9.0

tpo2

Dual Module

Typical

8.7

9.2

9.7

11.2

teo

Sequential Clk to Q

Critical

4.5

5.0

5.5

6.0

teo

Sequential Clk to Q

Typical

5.7

6.2

6.7

8.2

fQo

Latch G to Q

Critical

4.5

5.0

5.5

6.0

fQo

Latch G to Q

Typical

5.7

6.2

6.7

8.2

tpo

Asynchronous to Q

Critical

4.5

5.0

5.5

6.0

tpo

Asynchronous to Q

Typical

5.7

6.2

6.7

8.2

Output Net

FO = 8

Units
ns

11.7

ns
ns

14.7

ns
ns

11.7

ns

11.7

ns

ns

ns
11.7

ns

Sequential Timing Characteristics (Over Worst-Case Recommended Operating Conditions; No Further Derating Required)
Commercial

Military

Parameter

Description

tsUD

Flip-Flop (Latch) Data Input Setup

0.4

1.0

tSUASYN

Flip-Flop (Latch) Asynchronous Input Setup

1.0

2.0

tHD

Flip-Flop (Latch) Data Input Hold

tsuENA

Flip-Flop (Latch) Enable Setup

tHENA

Flip-Flop (Latch) Enable Hold

tWCLKA

Flip-Flop (Latch) Clock Active Pulse Width

tWASYN

Flip-Flop (Latch) Asynchronous Pulse Width

tA

Flip-Flop (Latch) Clock Input Period

tlNH

Input Buffer Latch Hold

t lNSU

Input Buffer Latch Setup

loUTH

Output Buffer Latch Hold

loUTSU

Output Buffer Latch Setup

fMAX

Flip-Flop (Latch) Clock Frequency

Notes:
1. Data applies to macros based on the sequential (S-type) module. Timing
parameters for sequential macros constructed from C-type modules can
be obtained from the ALS Timer utility.

1-144

Min.

Max.

Min.

0.0
5.0

Max.

ns
ns
0.0

7.5
0.0

7.5

Units

ns
ns

0.0

ns

9.0

ns

7.5

9.0

ns

18.0

22.0
2.0

-2.5

ns
2.5

-3.5
0.0

0.4

0.0
1.0

48.0

ns
ns
ns
ns

39.0

MHz

2. Setup and hold timing parameters for the Input Buffer Latch are
defined with respect to the PAD and the G input. External setuplhold
timing parameters must account for delay from an external PAD signal
to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.

ACT 1 and ACT 2 Military FPGAs

A1280 Timing Characteristics (continued)
I/O Buffer Timing f'/cc

= 5.0 V; TA = 25°C;

Process

= Typical; Derating Required)
FO = 1
FO = 2

=3

=4

=8

Units

Parameter

Description

t lNYH

Pad to Y High

6.7

7.2

7.7

8.2

11.7

ns

t lNYL

Pad to Y Low

6.6

7.1

7.6

8.1

11.5

ns

FO

FO

FO

tlNGH

G to Y High

6.6

7.2

7.7

8.2

11.7

ns

tlNGL

GtoYLow

6.4

6.9

7.5

8.0

11.4

ns

Global Clock Network f'/cc

= 5.0 V; TA = 25°C;

Process

= Typical; Derating Required)

Parameter

Description

FO = 128

FO =384

Units

tcKH
tcKL

Input Low to High

FO = 32
9.1

10.1

12.3

ns

Input High to Low

9.1

10.2

12.5

ns

tPWH

Minimum Pulse Width High

6.0

6.0

6.0

ns

t pWL

Minimum Pulse Width Low

6.0

6.0

6.0

ns

tcKSW

Maximum Skew

0.5

1.0

2.5

ns
ns

tsuEXT

Input Latch External Setup

0.0

0.0

0.0

~EXT

Input Latch External Hold

7.0

8.0

11.2

ns

tp

Minimum Period

15.0

18.0

20.0

ns

fMAX

Maximum Frequency

66.0

55.0

50.0

MHz

Output Buffer Timing f'/cc

= 5.0 V; TA = 25°C;

Process

•

= Typical; Derating Required)

Parameter

Description

TTL

tOLH

Data to Pad High

4.6

6.7

ns

tOHL

Data to Pad Low

6.5

4.9

ns

tENZH

Enable Pad Z to High

8.3

8.3

ns

~NZL

Enable Pad Z to Low

5.5

5.5

ns

tENHZ

Enable Pad High to Z

4.5

4.5

ns

It:NLZ

Enable Pad Low to Z

6.0

6.0

ns

taLH

G to Pad High

4.6

4.6

ns

CMOS

Units

taHL

G to Pad Low

6.5

6.5

ns

jTLH

Delta Low to High

0.06

0.11

ns/pF

jTHL

Delta High to Low

0.11

0.08

ns/pF

1-145

~
PRELIMINARY DATA

A 1240 Timing Characteristics
Propagation Delays 'Ycc = 5.0 V; TA = 25°C; Process = Typical; Derating Required)
Output Net

=1

=2

=3

FO

=4

Parameter

Description

tpD1

Single Module

Critical Net

3.9

4.3

4.8

5.3

t pD1

Single Module

Typical Net

4.9

5.3

5.7

7.0

tpD2

Dual Module

Critical Net

7.5

8.0

8.5

9.0

t pD2

Dual Module

Typical Net

7.9

8.3

8.7

10.0

teo

Sequential Clk to Q

Critical Net

3.9

4.3

4.8

5.3

teo

Sequential Clk to Q

Typical Net

4.9

5.3

5.7

7.0

~o

Latch G to Q

Critical Net

3.9

4.3

4.8

5.3

~o

Latch G to Q

Typical Net

4.9

5.3

5.7

7.0

t pD

Asynchronous to Q

Critical

3.9

4.3

4.8

5.3

t pD

Asynchronous to Q

Typical

4.9

5.3

5.7

7.0

FO

FO

FO

FO

=8

Units
ns

10.0

ns
ns

13.0

ns
ns

10.0

ns
ns

10.0

ns

10.0

ns

ns

Sequential Timing Characteristics (Over Worst-Case Recommended Operating Conditions; No Further Derating Required)
Commercial

Military

Parameter

Description

tSUD

Flip-Flop (Latch) Data Input Setup

0.4

1.0

tSUASYN

Flip-Flop (Latch) Asynchronous Input Setup

1.0

2.0

tHD

Flip-Flop (Latch) Data Input Hold

tSUENA

Flip-Flop (Latch) Enable Setup

tHENA

Flip-Flop (Latch) Enable Hold

tWCLl

< !>

+

XOR

«I> CLKorG, ,  CLR,  PRE)
Optional Inversion

ClK

Flip-Flop Clock Pin

G

Latch Gate Pin

ClR

Asynchronous Clear Pin

PRE

Asynchronous Preset Pin

Notes:
1. A space between the W. and 'B' in the equation
Y = A B means A AND B.
2. Order of operators in decreasing precedence is: NOT, AND, XOR,
and OR.
3. Signals expressed in bold have a dual module delay.

ACT 2 Macro Selections
1/0 Macros
No. of Modules

Macro Name
I/O

Description

Clock

INBUF

Input

IBDl

Input with Input Latch

BBDlHS

Bidirectional with Input Latch and Output Latch

BBHS

Bidirectional

BIBUF

Bidirectional

ClKBIBUF

Bidirectional with Input Dedicated to Clock Network

ClKBUF

Input for Dedicated Clock Network

OBDlHS

Output with Output Latch

OBHS

Output

OUTBUF

Output

TBDlHS

Three State Output with Latch

TBHS

Three State Output

TRIBUFF

Three State Output

Note:
The following are functionally identical:
OBHS and OUTBUF; TRIBUFF and TBHS; BBHS and BIBUF

1-158

ACT 1 and ACT 2 Military FPGAs

ACT 2 Macro Library
TTL Macros
No. of Modules
Macro Name
TAOO
TA02
TA04
TA07
TA08
TA10
TA11
TA20
TA21
TA27
TA32
TA40
TA42
TA51
TA54
TA55
TA86
TA138
TA139
TA150
TA151
TA153
TA154
TA157
TA160
TA161
TA164
TA169
TA174
TA175
TA190
TA191
TA194
TA195
TA269
TA273
TA280
TA377
TA68a

Description
2-input NAND
2-input NOR
Inverter
Buffer
2-input AND
3-input NAND
3-input AND
4-input NAND
4-input AND
3-input NOR
2-input OR
4-input NAND
4 to 10 decoder
AND-OR-Invert
4-wide AND-OR-Invert
2-wide 4-input AND-OR-Invert
2-input exclusive OR
3 to 8 decoder with enable and active low outputs
2 to 4 decoder with enable and active low outputs
16 to 1 multiplexor
a to 1 multiplexor with enable and active low outputs
4 to 1 multiplexor
4 to 16 decoder
2 to 1 multiplexor
4-bit decode counter with clear
4-bit binary counter with clear
a-bit serial in, parallel out shift register
4-bit up/down counter
Hex D-type flip-flop with clear
Quadruple D-type flip-flop with clear
4-bit up/down decode counter with up/down mode
4-bit up/down binary counter with up/down mode
4-bit shift register
4-bit shift register
a-bit up/down binary counter
Octal register with clear
Parity generator and checker
Octal register with active low enable
a-bit identity comparator

Logic Levels
Seq.

Comb.

2

2
10
2
5
3

1
2
2
1
2
1

2

12
4
6
5
2

2

22

3
3

1
4

3
1
6

7
7
1
8

4
4
a
4
6
4
4
4
4
4
a
a

4

1

3

12
10
14

31
30
4
1
28
9

a
9

1-159

I

ACT 2 Macro Library
Soft Macros
No. of Modules
Logic Levels

Function

Description

Macro Name

Counters

4-bit binary counter with load, clear
4-bit binary counter with load, clear, carry in, carry out
4-bit up/down counter with load, carry in, and carry out
very fast 16-bit down counter
2-bit down counter, prescaler
2-bit down counter, most significant bit
4-bit down counter, middle bits
4-bit down counter, low order bits

CNT4A
CNT4B
UDCNT4A
VCNT16C
VCNT2CP
VCNT2CU
VCNT4C
VCNT4CL

Decoders

2 to 4 decoder
2 to 4 decoder with active low outputs
3 to 8 decoder
3 to 8 decoder with active low outputs
4 to 16 decoder with active low outputs
2 to 4 decoder with enable
2 to 4 decoder with enable and active low outputs
3 to 8 decoder with enable
3 to 8 decoder with enable and active low outputs

DEC2X4
DEC2X4A
DEC3X8
DEC3X8A
DEC4X16A
DECE2X4
DECE2X4A
DECE3X8
DECE3X8A

Registers

octal latch with clear
octal latch with enable
octal latch with multiplexed data
4-bit shift register with clear
8-bit shift register with clear

oLC8A
DLE8
DLM8
SREG4A
SREG8A

Adders

8-bit adder
9-bit adder
10-bit adder
12-bit adder
16-bit adder
2-bit sum generator
very fast 16-bit adder

FADD8
FADD9
FADD10
FADD12
FADD16
SUMX1A
VADD16C

4-bit identity comparator
8-bit identity comparator
2-bit magnitude comparator with enable
4-bit magnitude comparator with enable
8-bit magnitude comparator with enable

ICMP4
ICMP8
MCMPC2
MCMPC4
MCMPC8

3
3
4

5
5
9
18

6

36

8 to 1 multiplexor
8 to 1 multiplexor with active low outputs
16 to 1 multiplexor

MX8
MX8A
MX16

2
2
2

3
3

Comparators

Multiplexors

1-160

4
4

5

Seq.

Comb.

4
4
4

8

34
5
2
4
4

7
13
31
2
3
8
7
4
4
8
8
20
4
4
11
11

1
2
1
2
2

8
8
8
4
8
3

3
3
4
5
2

3
2

44
49

56
69
97
5
97

5

ACT 1 and ACT 2 Military FPGAs

ACT 2 Macro Library
Combinable Hard Macros 1 (for OF1, OF1 B, OFC1 B, OFC10, OL1, OL1B, OLC, and OLCA)
No. of Modules
Function

Description

Macro Name

Equation(s)

AND

2-input

AND2
AND2A
AND2B
AND3B

Y
Y
Y
Y

AND-OR

A01A
A01D

Y = «!A) B) + C
Y = (!A !B) + C

AND-OR Invert

AOI1D

Y = !«!A !B) + !C)

Buffers and
Inverters

BUF
BUFA
INV
INVA

Y=A
Y = !(!A)
Y =!A
Y =!A

Clock Net
Interface

GAND2
GNOR2
GOR2

Y=AG
Y = !(A + G)
Y=A+G

Multiplexor

MX2

Y = (A IS) + (B S)

2-input

NAND2A
NAND2B

Y = !(!AB)
Y = !(!A !B)

3-input

NAND3C

Y = !(!A !B !C)

2-input

NOR2
NOR2A
NOR2B

Y = !(A + B)
Y = !(!A + B)
Y = !(!A +!8)

NOR
3-input

NOR3A

Y = !(!A + 8 + C)

OA1

Y = (A + B) C

2-input

OR2
OR2A

Y=A+B
Y = !A + B

3-input

OR3

Y=A+B+C

OR-AND

OR

Comb.

= AB
= !AB
=!A!B
= !A!B C

2:1

NAND

Seq.

I

1-161

~
ACT 2 Macro Library
Combinable Hard Macros 2 (for DF1, DF1 B, DFC1 B, DFC1 D, DL1, and DL1B)
No. of Modules
Description

Macro Name

Equatlon(s)

3-input

AND3
AND3A
AND3C

Y=ABC
Y = !A B C
Y = !A!B!C

4-input

AND4B
AND4C

Y = !A!B C D
Y = !A!B!C D

AND-OR

A01
A01B
A01C
A01E
A011
A02
A02A
A02B
A02C
A02D
A03
A03B
A03C
A04A
A05A

Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y

=
=
=
=
=
=
=
=
=
=
=
=
=
=
=

(A B) + C
(A B) + (!C)
((!A) B) + (!C)
(!A !B) + !C
A B + ((A + B) C)
((A B) + C + D)
((!A B) + C + D)
(!A !B) + C + D
(!A B) + !C + D
(!A !B) + !C + D
(!A B C) + D
(!A! B C) + D
(!A !B !C) + D
(!A B C) + (A C D)
(!A B) + (A C) + D

AND-OR Invert

AOl1A
AOl1B
AOl1C
AOl2A
AOl3A

Y
Y
Y
Y
Y

=
=
=
=
=

!((!A B) + C)
!((A B) + !C)
!((!A !B) + C)
!((!A B) + C + D)
!((!A !B !C)+(!A !D)

AX1B

Y = (!A !B)

CS2
CY2B

Y = !((A + S) B) C + ((A + S) B) D
Y = A1 B1 + (AO+ BO) A1 + (AO+ BO) B1

Function

AND

Exclusive OR

XNOR. AND-XOR

Boolean

C

GNAND2
GXOR2
MAJ3

Y = (A B) + (B C) + (A C)

MX2A
MX2C

Y = (!A !S) + (B S)
Y = (!A !S) + (!B S)

4:1

MX4

Y = (DO !SO !S1) + (D1 SO !S1)
+ (D2 !SO S1) + (D3 SO S1)

2-input

NAND2

Y = !(AB)

3-input

NAND3A
NAND3B

Y = !(!A B C)
Y = !(!A!B C)

4-input

NAND4C
NAND4D

Y = !(!A !B !C D)
Y = !(!A !B !C !D)

3-input

NOR3
NOR3B
NOR3C

Y = !(A + B + C)
Y = !(!A + !B + C)
Y = !(!A + !B + !C)

4-input

NOR4A
NOR4B

Y = !(!A + B + C + D)
Y = !(!A + !B + C + D)

AND-OR

Multiplexor

NOR

1-162

A

Y = (DO !SO !G) + (D1 !G SO)
+ (D2 G !SO) + (D3 SO G)
Y = !(AG)
Y=AAG

GMX4

Clock Net
Interlace

NAND

Seq.

Comb.

ACT 1 and ACT 2 Military FPGAs

ACT 2 Macro LIbrary
Combinable Hard Macros 2 (continued) (for DF1, DF1 B, DFC1 B, DFC1 D, DL1, and DL1B)
No. of Modules
Macro Name

Equatlon(s)

OR-AND

OA1A
OA1B
OA1C
OA2
OA2A
OA3
OA3A
OA4
OA4A
OA5

Y
Y
Y
Y
Y
Y
Y
Y
Y
Y

OR-AND Invert

OAI1
OAI2A
OAI3A

Y = !«A + B) C)
Y = !«A + B + C) !D)
Y = !«A + B) !C !D )

3-input

OR3A
OR3B

Y = !A + B + C
Y = !A + !B + C

4-input

OR4
OR4A

Y=A+B+C+D
Y = !A + B + C + D

XOR

XOR
X01
X01A

Y=A"B
Y = (A " B) + C
Y = !(A A B) + C

XNOR, AND-XOR

XNOR
XA1
XA1A

Y = !(A A B)
Y = (A A B) C
Y = !(A A B) C

Function

Description

OR

Exclusive OR

Seq.
=
=
=
=
=
=
=
=
=
=

Comb.

(!A + B) C
(A + B) (!C)
(!A + B) (!C)
(A + B) (C + D)
(!A + B) (C + D)
«A + B) C D)
«A + B) !C D)
(A + B + C) D
«A + B + !C) D)
(A+B+C)(A+D)

I

1-163

~
ACT 2 Macro LIbrary
Non-Combinable Hard Macros
No. of Modules
Description

Macro Name

Equatlon(s)

4-input

AND4
AND4A
AND4D

Y=ABCD
Y = (!ABCD)
Y = IA IB!C!D

5-input

AND5B

Y = !A!B CD E

2-input

OR2B

Y = !A + !B

3-input

OR3C

Y = !A + !B + !C

4-input

OR4B
OR4C
OR4D

Y = !A + !B + C + 0
Y = !A + !B + !C + D
Y = IA + IB + !C + !D

5-input

OR5B

Y = !A + !B + C + D + E

3-input

NAND3

Y = !(A B C)

4-input

NAND4
NAND4A
NAND4B

Y = I(A BCD)
Y = !(!A BCD)
Y = !(!A !B C D)

5-input

NAND5C

Y = !(!A!B!C D E)

4-input

NOR4
NOR4C
NOR4D

X = I(A + B + C + D)
Y = !(!A + !B + !C + D)
Y = !(!A + !B + !C + !D)

5-input

NOR5C

Y = !(!A + !B + !C + 0 + E)

XNOR, AND-XOR

AX1
AX1A
AX1C

Y = (!A B) '" C
Y = !(!A B) " C
Y = (A B) " C

AND-OR

A02E
A03A
A06
A06A
AO?
AOa
A09
A010

Y = (!A !B) + !C + !D
Y = (A B C) + 0
Y=AB+CD
Y = A B + C!D
Y=ABC+D+E
Y = (A B) + (!C !D) + E
Y = (A B) + C + 0 + E
Y = (A B + C) (0 + E)

AND-OR Invert

AOl1
AOl2B
AOl4
AOl4A

Y = !(A B +
Y = !((!A B)
Y= !((A B) +
Y = !(A B +

OR-AND

OA3B

Y = ((!A + B) !C D)

OR-AND Invert

OAI3

Y = !((A + B) CD)

MX2B

Y = (A IS) + (!BS)

Function

AND

OR

NAND

NOR

Exclusive OR

Multiplexor

1-164

2:1

Seq.

Comb.
1
2

1
2

2

2

1
2

C)
+ !C + D)
(C
!C D)

0»

1
2

ACT 1 and ACT 2 Military FPGAs

ACT 2 Macro Library

Non-Combinable Hard Macros (continued)
No. of Modules
Function

Description

Macro Name

Equatlon(s)

HA1

CO=AB
S=A" B

2

HA1A

CO=!A B
S= !(A " B)

2

HA1B

CO=!(A B)
S=!(A A B)

2

HA1C

CO=!(A B)
S=(A" B)

2

FA1A

CO=(CI!B !A) + (A!B) + (B CI A)
S = (B !A !CI) + (CO !A CI) + (CO A !CI)
+ (BACI)

2

FA1B

CO = !A(!B + B CI) + A(!B CI)
S = !A(!CI CO + CI B) + A(!CI B + CI CO)

2

FA2A

CO=(CI !B !(AO+A1)) + (!B (AO+A1))
+ (B CI (AO+A1))
S=(B l(AO+A1) lCI) + (CO l(AO+A1) CI)
+ (CO(AO+A1) !CI) + (B(AO+A1)CI)

2

Seq.

Comb.

half

Adders

full

CS1
CY2A
Boolean

MXT
MXC1

Y = !(A + S B) C + D (A + S B)
Y = A1 B1 + AO BO A1 + AO BO B1
Y=(!S1 (!SOADO) + (SOAD1»
+ (S1 (!SOB D2 + SOB D3))
Y= !(!S A + S B) C + (!S A + S B) D

2

o

DF1
DF1A
DF1B
DF1C

= (ClK. D. -. -)
ON = !(ClK. D. -. -)
o = (!ClK. D. -. -)
ON = !(!ClK. D.- .-)

with clear

DFC1
DFC1A
DFC1B
DFC1D
DFC1E
DFC1G

0= (ClK. D. ClR. -)
0= (!ClK. D. ClR. -)
o = (ClK. D. !ClR.-)
o = (!ClK. D. !ClR. -)
ON = !(ClK. D. !ClR. -)
ON=!(!ClK. D. !ClR.-)

with enable

DFE
DFE1B
DFE1C
DFE3A
DFE3B
DFE3C
DFE3D
DFEA

0= (ClK. !E 0 + ED. -.-)
O=(ClK. !E D + EO. -. -)
O=(!ClK. D!E + 0 E. -.-)
0= (ClK. D E + 0 !E. !ClR. -)
0= (!ClK. D E + 0 !E. lClR. -)
O=(ClK. D !E + 0 E. !ClR.-)
Q=(!ClK. D !E + Q E. !ClR.-)
O=(!ClK. !E 0 + ED. -.-)

D-type
Flip-Flops

I
2

1-165

ACT 2 Macro Library
Non-Combinable Hard Macros (continued)
No. of Modules
Function

Description

Macro Name

Equatlon(s)

a

with multiplexed data

DFM
DFM1B
DFM1C
DFM3
DFM3B
DFM3E
DFM4C
DFM4D
DFM6A
DFM6B
DFM7A

D-type
Flip-Flops
(continued)

DFM7B
DFMA
DFMB
DFME1A

Comb.

= (ClK, A !S + B S, -, -)
ON = !(ClK, A !S + B S, -, -)
ON = !(!ClK, A !S + B S, -, -)
0= (ClK, A !S + B S, ClR, -)
a = (!ClK, A!S + B S, !ClR,-)
0= (!ClK, A !S + B S, ClR, -)
ON = !(ClK, !A!S + !B S, -, !PRE)
ON = !(!ClK, A !S + B S, -, !PRE)
a = (ClK, (DO ISO !S1 + D1 SO !S1
+ D2 ISO S1 + D3 SO S1), !ClR, -)
a = (!ClK, (DO ISO !S1 + D1 SO !S1
+ D2 ISO S1 + D3 SO S1), !ClR, -)
a = (ClK, !ClR, (DO ISO + D1 SO) !(S10 + S11)
+ (D2 ISO + D3 SO) (S10 + S11»
a = (!ClK, !ClR, (DO ISO + D1 SO) !(S10 + S11)
+ (D2 ISO + D3 SO) (S10 + S11»
a = (!ClK, A !S + B S, -, -)
a = (ClK, A !S + B S, !ClR, -)
O=(ClK,!E A!S + !E B S + E Q, -,-)

a

with preset

DFP1
DFP1A
DFP1B
DFP1C
DFP1D
DFP1E
DFP1F
DFP1G

= (ClK, D, -, PRE)
= (!ClK, D, -, PRE)
a = (ClK, D, -, !PRE)
ON = !(ClK, D, -, PRE)
a = (!ClK, D, -, !PRE)
ON = !(ClK, D, -, !PRE)
a = (!ClK, D, -, PRE)
ON = !(!ClK, D, -, !PRE)

with clear
and preset

DFPC
DFPCA

a
a

JK Flip-Flops

JKF
JKF1B
JKF2A
JKF2B
JKF2C
JKF2D

0= (ClK, !O J + OK, -,-)
O=(!ClK,!O J + OK, -,-)
0= (ClK, !O J + OK, !ClR,-)
O=(!ClK, !O J + OK, !ClR, -)
0= (ClK, !O J + a K, ClR, -)
O=(!ClK,!O J + OK, ClR,-)

T-type Flip-Flops

TF1A
TF1B

0= (ClK, T !O + !T a, !ClR, -)
O=(!ClK, T!O + !TO, !ClR,-)

a

Data latch

Dl1
DL1A
DL1B
Dl1C
DL2A
DL2B
DL2C
DL2D

1-166

Seq.

2
2

a

= (ClK, D, ClR, PRE)
= (!ClK, D, !ClR, PRE)

2

1

2

2
2

= (G, D, -,-)

ON = !(G, D, -, -)
a = (!G, D, -, -)
ON = !(!G, D, -, -)
0= (G, D, !ClR, PRE)
ON = !(!G, D, ClR, PRE)
0= (!G, D, !ClR, PRE)
ON = !(G, D, ClR, !PRE)

2
2
2
2

ACT 1 and ACT 2 Military FPGAs

ACT 2 Macro Library
Non-Combinable Hard Macros (continued)
No. of Modules
Function

Description

Macro Name

Equatlon(s)

with clear

DLC
DLC1
DLC1A
DLC1F
DLC1G
DLCA

Q = (G, D, !CLR,-)
Q= (G, D, CLR,-)
Q = (!G, D, CLR, -)
QN = !(G, D, CLR, -)
QN = !(!G, D, CLR, -)
Q = (!G, D, !CLR, -)

with enable

DLE
DLE1D
DLE2A
DLE2B
DLE2C
DLE3A
DLE3B
DLE3C
DLEA
DLEB
DLEC

Q=(G,Q!E + DE,-,-)
QN = !(!G, !E !D + E QN, -, -)
Q=(!G, Q!E + DE, CLR,-)
Q=(!G, D!E + Q E, !CLR,-)
Q=(!G,!E D + Q E, CLR,-)
Q=(!G, ED + Q !E, -, PRE)
Q=(!G,!E D + Q E, -, PRE)
Q=(!G,!E D + Q E, -, !PRE)
Q = (G, Q E + D !E, -, -)
Q=(!G, Q!E + DE, -,-)
Q=(!G, Q E + D !E, -,-)

DLM
DLM2A

DLMA

Q = (G, A !S + B S, -, -)
Q=(!G, A!S + B S, CLR,-)
Q = (G, DO ISO !S1 + D1 SO !S1 + D2 ISO S1
+ D3 SO S1, -, -)
Q = (!G, DO ISO !S1 + D1 SO !S1 + D2 ISO S1
+ D3 SO S1, -, -)
Q = (!G, A!S + B S, -,-)

with multiplexed data
and enable

DLME1A

Q = (!G, A !S !E

with preset

DLP1
DLP1A
DLP1B
DLP1C
DLP1D
DLP1E

Q = (G, 0, -, PRE)
Q=(!G, D, -, PRE)
Q = (G, D, -, !PRE)
Q = (!G, D, -, PRE)
QN = !(G, D, -, !PRE)
QN = !(!G, D, -, !PRE)

Data latch
(continued)

with multiplexed data

DLM3
DLM3A

Seq.

+

B S !E

+

Comb.

2
1

•

E Q, -, -)

Clock Net Interface

CLKINT

clock
modules = 1

Tie-Off

VCC
GND

modules =
modules =

a
a

1-167

ACT 2 Macro Library
Hard Macro Symbols

I/O Buffers
(I/O Module Count = 1)

D

D

I/O Buffers with Latches

D

OBDLHS
G

D

Q

D

Q

TBDLHS

BBDLHS

G

G
Q

D 1-------1

Gn-------

1-168

ACT 1 and ACT 2 Military FPGAs

ACT 2 Macro Library
2-lnput Gates
(Module Count

= 1)

~
~
~
~

~

~

~NAND~

~NAND~

~
~

~
~

I
3-lnput Gates
(Module Count = 1)

1-169

~
ACT 2 Macro Library
4-lnput Gates
(Module Count

= 1)

~~

~B--r

~~

~B-x

~~

~Br

~~

~~NAN~

~~

~~

i~

~~

~~

~~

~~

~&

~~

i~

~~

~~

A~
~

~B-r

(Module Count = 2)

~~fAN~
... Indicates extra delay input

5-lnput Gates
(Module Count = 1)

~~
Buffers
(Module Count = 1)

1-170

y

8

OR58

ACT 1 and ACT 2 Military FPGAs

ACT 2 Macro Library
XOR Gates (Module Count = 1)

XOR-OR Gates (Module Count = 1)

XOR-AND Gates (Module Count = 1)

AND-XOR Gates
(Module Count = 1)

I

(Module Count = 2)

1-171

ACT 2 Macro Library
AND-OR Gates
(Module Count = 1)
A
B

C

D

A
B

A
B
c-----~_

__

A

C

B

D

C --------c

D ---------1

A
B

A

c

B
D

c --------{

A

D --------1

B

c--------~

D --------1

A
B

y

A
8

c --------{
o -------{

D ---------1

A
B

C ------/

A
B

A

c

B

D-------1

A

c

B

D-------1

c
D

1-172

ACT 1 and ACT 2 Military FPGAs

ACT 2 Macro Library
AND-OR Gates, continued
(Module Count = 1)

A

A

B

B

c - - - - Q__

c-----u'~

;~I
y

(Module Count = 2)
A
B

C
D

A
B

c:---------I
D--------1

A
B

C

E--------1

1-173

ACT 2 Macro Library

OR-AND Gates
(Module Count = 1)

1-174

ACT 1 and ACT 2 Military FPGAs

~CT

2 Macro Library

J!ultlplexors
Module Count = 1)

A

A

B

B

DO
D1
Y

D2
D3

Module Count = 2)
C

DO
D
D1

•

A

D2
B

D3

S

.atches
Module Count = 1)

----n-0

-G-

-0

----D-

-t:J

---G-

-t:J

1-175

ACT 2 Macro library
D-Latches with Clear
(Module Count

= 1)

o

a

o

a

o

CLR

PRE

PRE

o

aN

DLC1F

o

DLC1G
G

G

CLR

a

o

DLP1A

DLP1

G

G

PRE

PRE

a

DLP1B

a

o

DLP1C
G

G

o

PRE

aN

DLP1D

o

aN

DLP1E
G

G

= 2)

PRE

PRE

a

o

o

DL2A
G

aN

PRE

o

DL2C
G

CLR

PRE

a

o

DL2B
G

CLR

1-176

a

o

CLR

PRE

o

(Module Count

ON

a

G

CLR

CLR

CLR

o

DLC1A

G

G

G

a
DLC1

DLCA

DLC

aN
DL2D

G

CLR

CLR

ACT 1 and ACT 2 Military FPGAs

.CT 2 Macro Library
I-Latches with Enable
v'lodule Count = 1)

~

~

n

TI

=0

-0

±::l-

D-

PRE

PRE
D

aN

o

a

o

a

E DLE1D

E DLE2B

E DLE2C

E DLE3B

E DLE3C

G

G

G

G

G

CLR

CLR

~odule

o

a

o

a

•

Count = 2)

PRE

o

o

a

Q

E DLE2A

E DLE3A

G

G

CLR

lux Latches
~odule

Count

= 1)

n; OLM

DLME1A

DO
01
02
03
SO
S1
G

Q

DLM3

DO
01
02
03
SO
S1

Q

A
B

DLMA

DLM3A
S

G

G

Q

n

lodule Count = 2)
A

Q

B

DLM2A
S

1-177

ACT 2 Macro Library
Adders
(Module Count

= 1)
C----------------~

81

81
D----------------~

y

A1 CY2A
80
0

A------,

y

A1 CY2B
80
1

AO

AO

8
S

(Module Count = 2)

13=

A
8

8

CO

HA1

S

8
CO

CO

S

S

HA1A

CO

CI

....S

HA1C

AO
A1
8
CI

CO

....S
FA18

FA1A

co
s

HA1B

A
8

A
8
CI

A
B

A

CO
.... S

FA2A

Macros FA1A, FA1 B, and FA2A have two level delays from the inputs to the S outputs, as indicated by the ....

D-Type Flip-Flops
(Module Count = 1)

-O-~--D--G-

-0

1-178

-0

-0

-0

ACT 1 and ACT 2 Military FPGAs

ACT 2 Macro Library
D-Type Flip-Flops with Clear

= 1)

(Module Count

o

D

o

D

DFC1D

DFC1B

o
CLR

CLR

(Module Count = 2)

o
DFC1

ON
DFC1A

CLR

CLR

D

D

ON
DFC1E

D

ON
DFC1G

D

0-Type Flip-Flops with Preset
(Module Count

= 1)
PRE
D
ON
DFP1E

I

PRE

D
ON
DFP1G

(Module Count = 2)

PRE

PRE

D

0

D

DFP1

PRE
0

D

0

DFP1A

DFP1B

PRE

PRE
D
ON
DFP1F

D

0

DFP1D

PRE
D
ON
DFP1C

D-Type Flip-Flops with Preset and Clear
(Module Count = 2)

PRE
D

PRE
0

D

0

DFPC

DFPCA

CLR

CLR
1-179

ACT 2 Macro Library
D-lYpe Flip-Flops with Enable
(Module Count = 1)

£1--D--

-0
o

Q

-LJ
o

Q

:±:}---

-0
o

Q

o

Q

E DFE1C

ClK

o

Q

E DFE3A

E DFE3B

E DFE3C

E DFE3D

ClK
ClR

ClK
ClR

ClK
ClR

ClK
ClR

JK Flip-Flops
(Module Count = 1)

D-

-D

(Module Count

JKF1B

J

Q

ClK

Q

ClK
K

K

ClR

ClR

= 2)
JKF2D

JKF2C

Q

J

ClK

Q

ClK

K

K

ClR

ClR

Toggle Flip-Flops
(Module Count

= 1)
Q

T
TF1A

1-180

Q

J

ClK

K

J

JKF2B

JKF2A

J

T

Q

TF1B

ACT 1 and ACT 2 Military FPGAs

ACT 2 Macro Library
Mux Flip-Flops
(Module Count == 1)

A
8

a
DFMB

S

DFM7B

DFM7A
00
01

a

01

A
8

ON

DFM18

02

SO
ClK
ClR

SO
ClK
ClR

A
8

ON

S
E

ClK

a

II

A
8

DFM4C

S

S

ClK

ClK

a

DFME1A

03
S10
S11

DFM1C

S

A

8

02

03
S10
S11

A
8

a

00

ClK

DFM4D
S

ClK

(Module Count == 2)

A
8

a

a

A
8

DFM3
S

ClK
ClR

CLKBUF Interface Macros
(Module Count

= 1)

00
01

y

A

02
03

I> Indicates clock input for connection to the global clock networks.

1-181

Package Pin Assignments: 84-Pin CPGA
(Top View)

2

A
B

C
D

E

F
G
H

J
K
L

3

4

5

6

7

8

9

10 11

00000000000
00000000000
000
00
00.
00
00 (';
000
000
84-PIN
000
000
CPGA
000
000
00
00
000
00
00
00000000000
00000000000
• Orientation Pin (C3)

Signal

A101 O-Serles Devices

A1020-Serles Devices

PtfA

All

All

"PRe

Bl0

Bl0

MODE

Ell

Ell

SDI

Bll

Bll

DCLK

Cl0

Cl0

Vpp

K2

K2

ClK or I/O

F9

F9

GND

B7, E2, E3, K5, Fl0,Gl0

B7, E2, E3, K5,Fl0,Gl0

Vee

B5, Fl,G2,K7,E9, El0

B5, Fl,G2, K7, E9, El0

N/C (No Connection)

Bl, B2,Cl,C2, Kl,J2, Ll,Jl0, Kl0, Kll,Cll,Dl0,Dll

B2

Notes:
1. Vpp must be terminated to Vee, except during device programming.
2. MODE must be terminated to circuit ground, except during device
programming or debugging.

1-182

3. Unused 110 pins are designated as outputs by ALS and are driven low.
4. All unassigned pins are available for use as liDs.

ACT 1 and ACT 2 Military FPGAs

Package Pin Assignments: 132-Pin CPGA
(Top View)

1

2

3

4

5

6

7

8

9

10

11

12 13

AOOOOOOOOOOOOOA
BOOOOOOOOOOOOOB
cOOOOOOOOOOOOOc
00000

000

0000

000 E
EOOO
000 0 F
FOOOO
132-Pin
OOOOG
GOOOO
CPGA
HOOOO
OOOOH
JOOO
OOOJ
KOOO
000
OOOK
LOOOOOOOOOOOOOL
MOOOOOOOOOOOOOM
NOOOOOOOOOOOOON
2

3

4

5

6

7

8

9

10

11

Signal

Pin No.

PRA or 110

113

88

PR8 or 110

121

C6

•

12 13

Location

MODE

2

A1

SOl or I/O

101

812

SDO or 110

65

N12

DClKor 110

132

C3

ClKA or I/O

115

87

ClK8 or 110

119

86

GND

9,10,26,27,41,58,59,73,74,92,93,
107, 108, 125, 126

E3, F4, J2, J3, l5, M9, 19, K12, J11, E12, E11,
C9, 89, 85,C5

Vee

18,19,49,50,83,84,116,117

G3, G2, l7, K7,G10, G11,D7, C7

Vpp

82

G13

Vsv

17,85

G4, G12

VKS

81

H13

~otes:

.. Unused IIO pins are designated as outputs by ALS and are driven low.
~. All unassigned pins are available for use as IIOs.
i. MODE = GND, except during device programming or debugging.

4. V pp = Vee, except during device programining.
5. Vsv = Vee, except during device programming.
6. VgS = GND, except during device programming.

1-183

Package Pin Assignments: 176-Pin CPGA
(Top View)
1

2

3

4

5

6

7

8

9 10 11

12 13 14 15

AOOOOOOOOOOOOOOOA
80000000000000008

cOOOOOOOOOOOOOOOc
00000000000000000

EOOOO
,OOOOE
FOOOO
OOOOF
OOOOG
GOOOO
176-Pin
OOOOH
HOOOO
CPGA
OOOOJ
JOOOO
OOOOK
KOOOO
LOOOO
/OOOOL
MOOOOOOOOOOOOOOOM
NOOOOOOOOOOOOOOON
pOOOOOOOOOOOOOOOp
ROOOOOOOOOOOOOOOR
2

3

4

5

6

7

8

9 10 11

12 13 14 15

Signal

Pin No.

Location

PRA or 110

152

C9

PRS or 110

160

07

MODE

2

C3

SOl or 110

135

814

SOO or 110

87

P13

OCLK or 110

175

83

ClKA or I/O

154

A9

ClK8 or 110

158

88

GND

1,8,18,23,33,38,45,57,67,77,89,
101,106,111,121,126,133,145,156,165

04, E4, G4, H4, K4, l4, M4, M6, M8, M10, M12,
K12,J12, H12, F12, E12,012, 010, CB,06

Vee

13,24,2B,52,6B,B2, 112, 116, 140, 155, 170

F4, H3,J4, M5, NB, M11,H13,G12,011,OB, 05

Vpp

110

J14

Vsv

25,113

H2, H14

VKS

109

J13

Notes:
1. Unused 110 pins are designated as outputs by ALS and are driven low.
2. All unassigned pins are available for use as liDs.
3. MODE:: GND, except during device programming or debugging.

1-184

4. V pp :: Vee, except during device programming.
5. Vsv :: Vee, except during device programming.
6. V KS = GND, except during device programming.

ACT 1 and ACT 2 Military FPGAs

Package Pin Assignments: 84-Pin CQFP
(Top View)

g
o
z

CJ

Pin #1
Index

NC 1

is

I~

84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64

•

PRA or I/O
DCLK or I/O
61 SDI or I/O

63

/'

62
60

59
58
58

VDD
VDD

55

MODE

57

GND 7
GND 8
10

54

84·PIN
CQFP

11

53
52

12
13

51

VDD 14
VDD 15

50

49

16

48

17

47

18

46

19

45

20

44

21

,'-

CLK or I/O

I

GND
GND

43

22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
~
0
0

~

&

Notes:
1. V pp must be terminated to Vee, except during device programming.
2. MODE must be terminated to circuit ground, except during device
programming or debugging.

~

3. Unused 110 pins are designated as outputs by ALS and are driven low.
4. All unassigned pins are available for use as 1I0s.

1-185

Package Pin Assignments: 172-Pin CQFP
(Top View)
Pin #1
Index

...

172171170169168167166165164

~

~

1

6

=

/.~r~========================~~~

;~
5

137136135134133132131 130

129
128
127
126

c:::===:::n
c:::===:::n

125
124
123
122

~~3

•
•
•

•
•
•

172-PIN
CQFP

95

35
36
37

94

38

92

93

39

91

40
41
42
43

90
89
88

~====================~/~/~==~ 87

\...

"'J

V

•••
44 45 46 47 48 49 50 51 52

79 80 81 82 83 84 85 86

Signal

Pin Number

MODE
GND
Vee
Vsv
VKS
Vpp
SOD or I/O
SOl or I/O
PRA or I/O
PRS or I/O
ClKA or I/O
ClKS or I/O
DClKor I/O

1
7,17,22,32,37,55,65,75,98,103,108,118,123,141,152,161
12,23,27,50,66,80,109,113,136,151,166
24,110
106
107
85
131
148
156
150
154
171

Notes:

1. V pp must be terminated to Vee, except during device programming.
2. MODE must be terminated to circuit ground, except during device
programming or debugging.

1-186

3. Unused 110 pins are designated as outputs by ALS and are driven low.
4. All unassigned pins are available for use as liDs.

ACT 1 and ACT 2 Military FPGAs

Package Pin Assignments: 44-Pin, 68-Pin, 84-Pin JQCC

o

o

(!)

(!)

z

z

6 5 4 3 2 1 4443424140

9 8 7 6 5 4 3 2 1 686766 656463 6261

PRB or I/O

J5RA or I/O

PRB or I/O

J5RA or I/O

DClK or I/O
SDI or I/O
Vee
MODE
ClK or I/O
GND

GND

44-PIN

JOCC
Vee

DClKor I/O
SDI or I/O
Vee
MODE

GND
GND

58-PIN

JOCC

Vpp

GND

Vee

1819202122232425262728

ClK or I/O

Vpp

•

o
z

(!)

1110987654 32184838281807978777675

NC

GND
GND

84-PIN

JOCC
Vee
Vee

Notes:
1. V pp must be terminated to Vee, except during device programming.
2. MODE must be terminated to circuit ground, except during device
programming or debugging.

74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54

PRA or I/O
DClKor I/O
SDI or I/O

Vee
Vee
MODE
ClK or I/O
GND
GND

3. Unused 110 pins are designated as outputs by ALS and are driven low.
4. All unassigned pins are available for use as 1I0s.

1-187

Package Mechanical Details: 84-Pin CPGA

-..\ \.- .050" ± .010"

II

Pin #1

.
: ~)';::========~

(4 pies)

~

~

.018" ± .002"

_____L
.100" typo

-----r

~

1.100"

+ .020" Square

~

OOOOOOOOOOGf--~

00000000000
00
000
00
00
00
000
000
o 0 0 1.000 sse
000
000
000
00
00
00.
000
00
00000000000
C100000000001--L...
•

1-188

Orientation Pin

.120"
.140"

ACT 1 and ACT 2 Military FPGAs

Package Mechanical Details: 132-Pin CPGA

~l
.110"

Pin #1 ID

:~
,

- ..'-:.".'-.--------.......

~

1.360" ± .015"

0

0

0

0 0
@ 0 0 0
0 0 0 0
0 0 0
0 0
0 0 0
0 0 0
0 0 0
0 0
0 0

0

0

0

@

•

0
0
0
0
0
0
0
0
0

0

0

0 0 0

0 0
0 0
0 0
0 0

0
0 0
0 0
0

cJ 0 0 0 0 0 0
•

""u.'"

----1

tJ

__ l

- --r

.050" ± .010"
(4 Places)

0 0 0 0 OG0 0 0 0 @ 0
0 0 0 0 o 0
0
0 0 0
0 0 0
0 0 0 0
1.200 " sse
0 0 0 0
0 0 0 0
0 0 0
0
0 0 0
0 0 0 0 0 0
0 0 0 0 @ 0
0 0 0 0 o 0--

-..JI

.100"

sse

•

.120"
.140"

Orientation Pin

1-189

Package Mechanical Details: 176-Pin CPGA

Pin#11D

~l~I
.132"

-.l·018" +_. 002"
t
____L

----rsse
.100"

~

1.570" ± .015" "''''''''

--1

.050" ± .005"
(4 Places)

00000000000000
0@00000000000@0
000000000000000
000000000000000
0000
0000
0000
0000
0000
0000
0000
0000 1.400" sse
0000
0000
0000
0000
0000
0000
000000000000000
000000000000000
O@OOOOOOOOOOO@O
o 0 0 0 0 0 0 0 0 0 0 0 0 0 t4+-----'L--

1-190

-l

ACT 1 and ACT 2 Military FPGAs

Package Mechanical Details: 84-Pin CQFP

n

0.058" ± .010"

Pin #1

~

0.085/1 ± .010/1

.010" ± .002/1

:'\

//

rs

l
r

E1

E

j
.025" ± .005/1

1
H

"'-

.050/1 ± .010/1

--I~o--

0.006" ± .002"

I

~~

"

0

0.350/1 ± .025" ~

I

I
D1
D

Lead Count

0, E

01, E1

84

1.350" ± .030"

0.650" ± .010"

.1

I

.1

1-191

Package Mechanical Details: 172-Pin CQFP
4-2.300 ± 0.010

1r

0.035 ± 0.005

4-1.500 ± 0.015
-

4-1.180 ± 0.012

2-4>0.100 ± 0.002

~~==~~---r

NeTB
(alumina 90%)
ALLOV42 . /
0.105 ± 0.012

ALUMINA
(90% BLACK)

8o
+1

~

C\i

1010

8<5

00
+1

§
C\i

1
N

0.090 ± 0.010
0.1
± O.

+0.002
0006
.
-0.001

~~ 0.018 TYP

4-4>0.060 REF

Notes:
1. All exposed metalized areas and leads are

HEAT SINK

--I~+--"'I

2.
3.
4.
S.

0.067 ± 0.010 SQ.

I
BorrOMVIEW
1-192

gold plated 100 microinches (2.S J.I mm) min.
thickness over 80 to 3S0 microinches 2.0 to
8.9 J.l mm) thickness of nickel.
Seal ring area is connected to GNDA.
Die attach pad is connected to GNDA.
GNDQ (4 PLS) is connected to GNDA.
Tolerances unless otherwise specified: ± 1%
N.L.T. ±O.OOS.

ACT 1 and ACT 2 Military FPGAs

Package Mechanical Details: JQCC

.023"

.050"

min'1,,,,"",~=~=

rEJ..J~1.L1..LJ...LJ...J...L...L.U"I-""" b.I~_~Pin
_ ---j:;;".

1 Index Chamber

sse

_-=:1 _

--1 -

0.007"
0.011"

E1

.105" ± .010"

-0-

E

~m

.155"
.180"

Lead Count

O,E

01, E1

I

.650" ± .008"

44

.690" ± .005"

68

.990" ± .005"

.950" ± .008"

84

1.190" ± .005"

1.150" ± .008"

1-193

1-194

A10M20A Mask
Programmed
Gate Array

Preliminary

Features

Description

• High Gate Count: 2000 gate array gates
(6000 PLD/LCA equivalent gates)

The Actel AlOM20A Mask Programmed Gate Array (MPGA)
offers a lower cost, faster alternative to the AlO20A Field
Programmable Gate Array (FPGA). These AlOM20A MPGAs are
pin-for-pin compatible with the A1020A FPGAs. The devices are
manufactured in 1.2 micron, two-level metal CMOS and the Actel
PUCE@ antifuse is replaced by a metal connection via. Actel's
unique architecture offers gate array flexibility and high
performance.

• Pin-for-Pin Compatible with Actel's A1020A FPGA at Lower
Cost
• Easy Conversion From FPGA to Mask Programmed Gate
Array (MPGA)
• Re-routing Not Required for FPGA to MPGA Conversion

• ATG Vectors Provide 100% Test Coverage for all Detectable
Faults

Actel's MPGA provides automatic test vector generation and 100%
test coverage for all detectable faults. This procedure is automatic.
Additional features include an on-chip clock driver with a
hard-wired distribution network. The on-chip clock driver provides
efficient clock distribution with minimum skew.

• 35-70% Faster than Programmable AlO20A FPGA

The user-definable I/Os can drive TTL and CMOS levels.

• Gate Array Architecture Allows Completely Automatic Place
and Route

The Action Logic System

• Automatic Test Generation (ATG) Eliminates Test Vector
Generation

• Short Lead Times to Prototypes and Production

The MPGA is supported by Actel's Action Logic™ System, which
allows logic design to be implemented with minimum effort. The
Action Logic System (ALS) interfaces with the resident CAE
platform to provide a complete gate array design environment for the
ACT 1 MPGA It allows schematic capture, simulation, fully
automatic place and route, timing verification, and device
programming. The Action Logic System also provides timing and
simulation information for the MPGA device. The Action Logic
System is supported on the following platforms: 386/486 PC, and
Sun@, HP® and Apollo@ workstations. It provides CAE interfaces to
the following design environments: Valid™, Viewlogic®, Mentor
Graphics™, HP DCS and OrCad™.

• Low-Power CMOS Technology
• System Level Performance to 50 MHz
• Toggle Rates to 120 MHz
• I/O Drive to 8 rnA
• Nonvolatile, Permanent Programming
• Built-In Clock Distribution Network

Product Profile
Device
Capacity
Gate Array Equivalent Gates
PLD/LCA Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages

A10M20A

2,000
6,000

50
15

Logic Modules

547

Flip-Flops (maximum)

273

Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Column

25

User I/Os (maximum)

69

Packages

CMOS Process

© 1992 Actal Corporation

13

68-pin PLCC
84-pin PLCC
100-pin PQFP
1.2pm

The MPGA offers the user the ability to move into volume
production much faster than with conventional masked gate arrays.
Actel produces prototype devices directly from customer generated
design files. The user can employ the Action Logic System to
perform all schematic capture, pre-route simulation, place and
route, and post-route back-annotated simulation. Since there are
no additional routes or simulations needed at the vendor's site,
there are no extra CPU charges. This gives the user the opportunity
to fully determine the functionality of the device prior to paying any
NRE development charges.

Device Structure
The AlOM20A MPGA:s basic structure is similar to the AlO20A
FPGA Logic modules are arranged in horizontal rows separated
by horizontal interconnect tracks, with vertical interconnect tracks
running over the logic modules. The FPGA has PLICE antifuses,
located at the intersection of the horizontal and vertical tracks,
which connect its logic module inputs and outputs. During the
programming cycle, the software addresses and programs the
connections required by the circuit application. The MPGA is
designed so that all programmable antifuses are removed.

January 1992

1-195

I

Antifuses are replaced by low-impedance metal vias. Metal via
connections are made according to specific customer designs.

module column. Metal via connections are made between the
routing tracks to implement a customer's design.

The Actel Logic Module

Automatic Test Generation

The Actel Logic Module is an eight-input, one-output logic circuit
chosen for its wide range of functions and its efficient use of
interconnect routing resources. AIl of the functions available in the
ACT 1 FPGA family are available for the A10M20A device.

ATG test vectors are generated automatically to verify user design
and interconnect wiring, with 100% fault coverage. Testing is
facilitated by testability structures incorporated in the MPGA logic
module.

The logic module implements the four basic logic functions
(NAND, AND, OR, and NOR) in gates of two, three, or four
inputs. Each function has many versions, due to different
combinations of active-low inputs. The logic module also
implements a variety of D-latches, an exclusivity function,
AND-ORs and OR-AND relationships. Dedicated hard-wired
latches or flip-flops are not required, since latches and flip-flops
may be constructed from logic modules, wherever needed in the
application.

Greater details concerning the methods used to generate the ATG
test vectors can be found in the technical paper entitled ''Array
Architecture for ATG with 100% Fault Coverage," included in this
datasheet.

I/O Buffers
Each I/O pin can be configured as an input, output, three-state, or
bidirectional buffer. Input and output levels are compatible with
standard TTL and CMOS specifications.

Device Organization

Device Performance
Temperature, Voltage and Processing Effects
Worst-case delays for the AlO20A FPGA device and the A10M20A
MPGA device are calculated in the same manner as for
conventional masked gate arrays. A typical delay parameter is
multiplied by a derating factor to account for temperature, voltage,
and processing effects.
The total derating factor from typical to worst-case for the
AlOM20A MPGA is 1.54 to 1.

Logic Module Size

The MPGA consists of a matrix of logic modules arranged in rows
separated by wiring channels. The number of logic modules and
routing resources is identical for the A1020A FPGA and the
AlOM20A MPGA (14 rows by 44 columns, 547 logic modules and
69 I/O modules). The MPGA has ATG peripheral circuits for
generating test vectors. Routing channels, which contain 22
horizontal segmented metal tracks, are between the rows of logic
modules. Vertical routing is provided by 13 vertical tracks per logic

The logic module size also affects performance. A conventional
masked gate array ceIl with four transistors usually implements
only one logic level. In more complex logic modules (similar to the
complexity of a gate array macro), of both the AlO20A FPGA, and
the A10M20A MPGA, it is possible to implement multiple logic
levels within a single module. This eliminates inter-level wiring and
associated RC delays.

Ordering Information

Product Plan

Al0M20

A

-

84

PL

C

1

1

Package Type

Application

Package Lead Count

Package Type
Die Revision
Part Number

1-196

Lead Count

Application

PL

68

PL

84

c
c

100

c

PO

PL
PO
C

=

=

Plastic Leaded Chip Carrier
Plastic Quad Fiatpack
Commercial

A 1OM20A Mask Programmed Gate Array

Power Dissipation

Device Resources
User I/Os
Device
Series

The following formula is used to calculate total device dissipation.

Logic
Modules

Gates

58-Pin

84-Pln

1DO-Pin

547

2000

57

69

69

A10M20A

Total Device Power (m W) = (0.067 x N x F1)
+ (0.80 x P x F3)
Where:
F1

Absolute Maximum Ratings

F2

Free air temperature range

F3
Limits

Parameter

Symbol

Units

-0.5 to +7.0

Volts

VI

Input Voltage

-0.5 to Vee + 0.5

Volts

Vo

Output Voltage

-0.5 to Vee + 0.5

Volts

Vee

DC Supply Voltage

11K

Input Clamp Current

±20

mA

10K

Output Clamp Current

±20

mA

10K

Continuous Output Current

±25

mA

-65 to +150

°C

TSTG

Storage Temperature

Note:
Stresses beyond those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. Exposure to absolute
maximum rated conditions for extended periods may affect device
reliability. Device should not be operated outside the Recommended
Operating Conditions.

Recommended Operating Conditions
Parameter
Temperature

Commercial
Range l

Power Supply Tolerance

Note:
1. Ambient temperature (fA).

Units

o to +70
±5

%Vcc

+ (0.028 x M x F2)

=
=
=

Average logic module switching rate in MHz.
CLKBUF macro switching rate in MHz.
Average I/O module switching rate in MHz.

M

Number of logic modules connected to the CLKBUF
macro.

N

Total number of logic modules used in the design
(including M).

P

= Number of outputs loaded with 50 pR

The average switching rate of logic modules and I/O modules is
some fraction of the device operating frequency (usually
CLKBUF). Logic modules and I/O modules switch states (from
low-to-high or from high-to-Iow) only if the input data changes
when the module is enabled. A conservative estimate for average
logic module and I/O module switching rates (variables F1 and F3,
respectively) is 10% of device clock driver frequency.
If the CLKBUF macro is not used in the design, eliminate the
second term (including F2 and M variables) from the formula.

Sample A 1OM20A Power Dissipation Calculation
This sample design uses 85% of available logic modules on the
A1OM20A-series device (.85 x 547 = 465 logic modules). The
design contains 104 flip-flops (208 logic modules). The design's
operating frequency is 16 MHz. The CLKBUF macro drives the
clock network. Logic modules and I/O modules switch states at
approximately 10% of the clock frequency rate (.10 x 16 MHz = 1.6
MHz). Sixteen outputs are loaded with 50 pR
To summarize the design described above: N = 465; M = 208;
F2 = 16; F1 = 1.6; F3 = 1.6; P = 16. Total device power can be
calculated by substituting these values for variables in the device
dissipation formula.
Total device power for this example =
(0.067 x 465 x 1.6) + (0.028 x 208 x 16)

+ (0.80 x 16x 1.6) =

164mW

1-197

I

Electrical Specifications
Parameter

Min.
(loH = -8 mA)

2.4

(loH = -4 mA)

3.84

Units

Max.

v
v

(IOL = 8 mA)
(IOL = 4mA)
-0.3

0.5

v

0.33

v
v

0.8

2.0

Vee

Input Transition Time tR. tF2
CIO 110 Capacitance2, 3

V

+ 0.3

500

ns

10

pF

Standby Current. Icc4

mA

-10

Leakage Current5
los Output Short
Circuit Currents

10

}JA

(Vo = Vee)

20

140

mA

(Vo = GND)

-10

-100

mA

Notes:
1. Only one output tested at a time. Vee = min.
2. Not tested, for information only.
3. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f = 1 MHz.
4. Jypical standby current = 300}lA. All outputs unloaded. All inputs = Vee or GND.
5. Va, V IN = Vee or GND.
6. Only one output tested at a time. Min. at Vee = 4.5 V; Max. at Vee = 5.5 V.

Package Thermal Characteristics
The device junction to case thermal characteristic is ajc, and the
junction to ambient air characteristic is aja. The thermal
characteristics for aja are shown in the following table, with two
different air flow rates.

Package Type
Plastic J-Ieaded Chip Carrier

Plastic Flatpack

1-198

Pin Count

aje

aja
Stili air

68
84

13
12

44

33

100

13

55

50

45

aja
300 ft/mln.

35

Units

A10M20A Mask Programmed Gate Array

The AlOM20A MPGA is 35-70% faster than the A1020A FPGA
because the antifuse is replaced by a metal via connection. The
designer needs to be aware of these timing differences when
converting from an AI020A FPGA to the AlOM20A MPGA.
These differences can be quickly analyzed at the customer's facility
usingALS.

Timing Characteristics
Timing is design dependent; actual delay values are determined
after place and route of the design using the ALS Timer utility. The
following delay values use statistical estimates for wiring delays
based on 85% to 90% module utilization. Device utilization above
95% will result in performance degradation.

Logic Module 11mlng
= 5.0 V; TA = 25°C; Process = Typical

vec

Single Logic Module Macros

(e.g., most gates, latches, multiplexors)1
Parameter

Output Net

tpD

Typical

FO

=1

4.3

FO

=2

=3

FO

4.5

4.4

=4

FO

4.6

FO

=8

4.8

Units
ns

Dual Logic Module Macros

(e.g., adders, wide input gates)1
Parameter

Output Net

t pD

Typical

FO

=1

6.9

FO

=2

7.0

FO

=3

7.1

=4

FO

7.3

FO

=8

7.6

Units
ns

Sequential Element Timing Characteristics
Fan-Out
Parameter
FO

=1

FO

=2

FO

=3

FO

=4

FO

=8

Units

tsu

Set Up Time, Data Latches

2.7

2.8

3.0

3.3

3.8

ns

tsu

Set Up Time, Flip-Flops

2.8

2.8

2.8

2.8

2.8

ns

tH

Hold Time

0

0

0

0

0

ns

tw

Pulse Width, Minimum2

6.0

6.3

6.5

7.0

8.0

ns

teQ

Delay, Typical Net

3.7

3.8

3.9

4.0

4.2

ns

tpRE

Asynchronous Preset to Q

4.3

4.4

4.5

4.6

4.8

ns

teLR

Asynchronous Clear to Q

4.3

4.4

4.5

4.6

4.8

ns

Notes:
1. Most flip-flops exhibit single module delays.
2. Minimum pulse width, tw, applies to CLK, PRE, and CLR inputs.

1-199

I

PRELIMINARY DATA

I/O Buffer TImIng
vcc

= 5.0V;TA = 25°C; Process = Typical

INBUF Macros
Parameter
tpHL

From - To

FO

=1

=2

FO

FO

=3

Pad to Y

2.2

2.3

2.3

Pad toY

2.1

2.1

2.2

FO

=4

=8

FO

Units

2.4

2.6

ns

2.2

2.4

ns

CLKBUF (High Fan-Out Clock Buffer) Macros
Parameter

FO

tpLH

= 40

FO

= 160

FO

= 320

Units

4.1

4.1

4.1

ns

4.3

4.3

4.3

ns

Notes:
1. A clock balancing feature is provided to minimize clock skew.

2. There is no limit to the number of loads that may be connected to the

CLKBUF macro.

OUTBUF, TRIBUFF & BIBUF Macros
CL = 50 pF
Parameter

From - To

CMOS

TTL

Units

tpHL

D to Pad

7.0

8.2

ns

tpLH

D to Pad

7.9

6.1

ns
ns

tpHZ

E to Pad

9.1

9.1

tpZH

E to Pad

8.6

6.6

ns

tpLZ

E to Pad

8.9

8.9

ns

tpZL

E to Pad

8.2

9.4

ns

From - To

CMOS

TTL

Units

tpHL

D to Pad

0.05

0.05

ns/pF

tpLH

D to Pad

0.08

0.07

ns/pF

tpHZ

E to Pad

0.11

0.11

ns/pF

tpZH

E to Pad

0.09

0.05

ns/pF

t pLZ

E to Pad

0.11

0.11

ns/pF

tpZL

E to Pad

0.05

0.07

ns/pF

Change In Propagation Delay with Load Capacitance
Parameter

Notes:
1. The BIBUF macro input section exhibits the same delays as the INBUF
macro.

1-200

2. Load capacitance delay delta can be extrapolated down to 15 pF

minimum.
Example:
Delay for OUTBUF driving a 100-pF 1TL load:
tpHL = 8.2 + (0.05 x (100-50» = 10.7 ns
tPLH = 6.1 + (0.07 x (100-50» = 9.6 ns

A10M20A Mask Programmed Gate Array

Timing Derating
Operating temperature and voltage and device processing
condition account for variations in array timing characteristics.

These variations are summarized into a derating factor for the
AlOM20A MPGA typical timing specifications. Derating factors
are shown below.

Timing Derating Factor (x typical)
Commercial
Device
A10M20A

Best Case
0.50

Worst Case

1.64

Note:
Best case reflects maximum operating voltage, minimum operating temperature, and best case processing. Worst case reflects minimum operating voltage, maximum operating temperature, and worst case processing.
Best case derating is based on sample data only and is not guaranteed.

Output Buffer Delays

o

To AC test loads (shown below)

I
GND
tpHL

1-201

AC Test Loads
Load 2
(Used to measure propagation delay
only for tpLZ/tpZL. tpHz/tpZH)

Load 1
(Used to measure propagation delay)

GNO

Vee

)>----'l

T

•

•

To the output under test

SOPF

R to Vee for tpLZ/tpZL
R to
To the output under test >------1.

GNO for tpHz/tpZH

R = 1 kO

50PF

T
Module Delays

Input Buffer Delays

sfian_out=2
A

Y

B

Vee

S, ~ ......50%

50°/;:" , ___G_N;;,.O_ _ _ __
Vee

Out

/V"50%

',50%

GNO
tpLH

tpHL

Out

Vee

50%,

GNO

t pHL

GNO /~O%
t pLH

tpLH

D-Type Flip-Flop and Clock Delays
tw

tw

ClK
Fan-out = 2

0=Q-a

ClK

01

Q

ClR

PRE
(Positive edge triggered)
ClR

Note:
1. For flip-flops with multiplexed inputs, D represents all data functions involving A, B, or S.

1-202

tcLR

A10M20A Mask Programmed Gate Array

Macro Library
Overview
This selection guide describes ACT 1 macros, which are the same
for both FPGA and MPGA devices. These macros are building
blocks for designing programmable gate arrays with the Action
Logic System (ALS) and your CAE interface.

The macros are divided into four categories: I/O Macros, Hard
Macros, Soft Macros and TTL Macros.

Equation Statement Elements
Combinatorial Elements
All equations for combinatorial logic elements use the following
operators:
Operator
AND

Q

Symbol
See Note 1

NOT
OR

Sequential Elements
All equations for sequential logic elements use the following
formula:

+

XOR

= < I>

« I > ClK or G, < data equation>,  ClR,  PRE)



Optional Inversion

CLK

Flip-Flop Clock Pin

G

Latch Gate Pin

CLR

Asynchronous Clear Pin

PRE

Asynchronous Preset Pin

Notes:
1. A space between the 'N. and 'B' in the equation
Y = AB means A AND B.
2. Order of operators in decreasing precedence is: NOT, AND, XOR
and OR.
3. Signals expressed in bold have a dual module delay.

•

MPGA Macro Selections
I/O Macros
No. of Modules
Macro Name
INBUF

I/O

Description
Clock
Input

BIBUF

Bidirectional

CLKBUF

Input for Dedicated Clock Network

TRIBUF

Three State Output

OUTBUF

Output

1-203

TTL Macros
Macro Name

Description

TA138
TA139
TA151
TA153

3 to 8 decoder with enable and active low outputs
2 to 4 decoder with enable and active low outputs
8 to 1 multiplexor with enable and active low outputs
4 to 1 multiplexor
Equations:
X = (CO!B !A) + (C1 !B A) + (C2 B !A) + (C3 B A)
Y = (!EN X)
2 to 1 multiplexor
Equation:
Y = (!EN !S A) + (!EN S B)
4-bit binary counter with clear
8-bit shift register with serial in/parallel out
4-bit up/down counter
4-bit shift register
4-bit shift register
8-bit up/down binary counter
Octal register with clear
Parity generator and checker
Octel register with enable

TA157

TA161
TA164
TA169
TA194
TA195
TA269
TA273
TA280
TA377

1-204

Logic Levels

Modules
Required

2
1
3

12
4
5

2

2

3
1
6
1
1
8
1
4

22
18
25
14
11

50
18
9
16

A10M20A Mask Programmed Gate Array

Soft Macros
Logic Levels

Modules
Required

FA1
FADD8
FADD12
FADD16
FADD24
FADD32

3
4
5
5
6
7

3
37
58
79
120
160

Comparators

4-bit identity comparator
8-bit identity comparator
2-bit magnitude comparator with enable
4-bit magnitude comparator with enable
8-bit magnitude comparator with enable
16-bit magnitude comparator

ICMP4
ICMP8
MCMPC2
MCMPC4
MCMPC8
MCMP16

2
3
3
4
6
5

5
9
9
18
36
93

Counters

4-bit binary counter with load, clear
4-bit binary counter with load, clear, carry in, and carry out
4-bit up/down counter with load, carry in, and carry out

CNT4A
CNT48
UDCNT4A

4
4
6

18
15
24

Decoders

2 to 4 decoder
2 to 4 decoder with active low outputs
2 to 4 decoder with enable
2 to 4 decoder with enable and active low outputs
3 to 8 decoder
3 to 8 decoder with active low outputs
3 to 8 decoder with enable
3 to 8 decoder with enable and active low outputs
4 to 16 decoder with active low outputs

DEC2X4
DEC2X4A
DECE2X4
DECE2X4A
DEC3X8
DEC3X8A
DECE3X8
DECE3X8A
DEC4X16A

1
2
2
2

4
4
4
5
8
9
11
11
20

Multiplexors

8 to 1 multiplexor
8 to 1 multiplexor with active low output
16 to 1 multiplexor

MX8
MX8A
MX16

2
2
2

3
3
5

Multipliers

8 x 8 multiplier

SMULT8

Registers

Octal latch with clear
Octal latch with enable
Octal latch with multiplexed data
Octal with preset, clear, and enable
Octal with preset, clear, enable, and active low clock
4-bit shift register with clear
8-bit shift register with clear

DLC8A
DLE8
DLM8
REGE8A
REGE88
SREG4A
SREG8A

Function

Description

Macro Name

Adders

1-bit adder
8-bit adder
12-bit adder
16-bit adder
24-bit adder
32-bit adder

241

1
1
2
2
2
2

8
8
8
20
20
8
18

1-205

•

~
Hard Macros
Function

Macro Name

Equatlon(s)

2-lnput

AND2
AND2A
AND2B

Y = AB
Y = !AB
Y =!A!B

3-lnput

AND3
AND3A
AND3B
AND3C

Y
Y
Y
Y

=
=
=
=

ABC
!A BC
!A !BC
!A!B!C

4-lnput

AND4
AND4A
AND4B
AND4C
AND4D

Y
Y
Y
Y
Y

=
=
=
=
=

(A BCD)
(!ABCD)
!A!B C D
!A!B !CD
(!A !B !C !D)

2-lnput

OR2
OR2A
OR2B

Y=A+B
Y = !A + B
Y = !A + !B

3-lnput

OR3
OR3A
OR3B
OR3C

Y=A+B+C
Y = !A + B + C
Y = !A + !B + C
Y = !(A B C)

1
2

4-lnput

OR4
OR4A
OR4B
OR4C
OR4D

Y=A+B+C+D
Y = !A + B + C + D
Y = !A + !B + C + D
Y = !A + !B + !C + D
Y = !A + !B + !C + !D

1
2
2
2

2-lnput

NAND
NAND2A
NAND2B

Y = !(AB)
Y = !(AB)
Y = !(!A !B)

NAND3
NAND3A
NAND3B
NAND3C

Y
Y
Y
Y

=
=
=
=

!(A B C)
!(!A B C)
!(!A!B C)
!(!A!B !C)

2

3-lnput

4-lnput

NAND4
NAND4A
NAND4B
NAND4C
NAND4D

Y
Y
Y
Y
Y

=
=
=
=
=

!(ABCD)
!(!A BCD)
!(!A !B C D)
!(!A !B !C D)
!(!A !B !C !D)

2
2
2

2-lnput

NOR2
NOR2A
NOR2B

Y = !(A + B)
Y = !(!A + B)
Y = !(!A + !B)

3-lnput

NOR3
NOR3A
NOR3B
NOR3C

Y
Y
Y
Y

=
=
=
=

4-lnput

NOR4
NOR4A
NOR4B
NOR4C
NOR4D

Y
Y
Y
Y
Y

= !(A +
= !(!A +
= !(!A +
= !(!A +
= !(!A +

AND

OR

NAND

NOR

1-206

Modules
Required

Description

2
2
1
1
2

!(A + B + C)
!(!A + B + C)
!(!A + !B + C)
!(!A + !B + !C)
B + C + D)
B + C + D)
!B + C + D)
!B + !C + D)
!B + !C + !D)

2
1
2
2

A10M20A Mask Programmed Gate Array

Hard Macros (continued)
Modules
Required

Description

Macro Name

Equation(s)

XOR

XOR
X01
X01A

Y=AAB
Y = (A A B) + C
Y = !(A A B) + C

XNOR

XNOR

Y = !(A A B)

XOR-AND

XA1
XA1A

Y = (A A B) C
Y = !(A A B) C

AND-XOR

AX1
AX1A
AX1B

Y = (fA B) A C
Y = !«!A B) A C)
Y = (fA !B) A C

AND-OR

A01
A01A
A01B
A01C
A02
A02A
A03
A04A
A05A
MAJ3

Y
Y
Y
Y
Y
Y
Y
Y
Y
Y

=
=
=
=
=
=
=
=
=
=

(A B) + C
(!A B) + C
(A B) + (fC)
(!A B) + (!C)
«A B) + C + D)
((fA B) + C + D)
(fA B C) + D
(fA B C) + (A C D)
(!A B) + (A C) + D
(A B) + (B C) + (A C)

AND-OR
Invert

AOl1
AOl1A
AOl1B
AOI2A
AOl2B
AOl3A
AOl4

Y
Y
Y
Y
Y
Y
Y

=
=
=
=
=
=
=

f(A B + C)
f«fA B) + C)
!«A B) + !C)
!«!A B) + C + D)
!«!AB) + fC + D)
f«fA !B !C) + (fA fD»
!(A B + CD)

OR-AND

OA1
OA1A
OA1B
OA1C
OA2
OA2A
OA3
OA3A
OA3B
OA4A
OA5

Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y

=
=
=
=
=
=
=
=
=
=
=

(A + B) C
(fA + B) C
(A+ B) (!C)
(fA + B) (lC)
(C + D) (A + B)
«C + D) (!A + B»
«A + B) C D)
«A + B) !C D)
«!A + B) !C D)
«A + B + fC) D)
(A + B + C) (A + D)

OR-AND
Invert

OAI1
OAI2A
OAI3
OAI3A

Y
Y
Y
Y

=
=
=
=

!«A
!«A
f«A
f«A

Buffers and
Inverters

BUF
BUFA
INV
INVA

Y=A
Y = f(fA)
Y = !A
Y = fA

Function

Exclusive OR

+
+
+
+

B) & C)
B + C) !D)
B) CD)
B) !C !D)

2

2

1

1
2

1-207

•

~
Hard Macros (continued)
Function

Modules
Required

Description

Macro Name

Equatlon(s)

2:1

MX2
MX2A
MX2B
MX2C

Y = (A IS) + (B S)
Y = (!A IS) + (B S)
Y = (A IS) + (!BS)
Y= (!A IS) + (!B S)

Multiplexors

MX4

4:1

Y = (DO ISO !S1) + (01 SO !S1) + (02 ISO S1)
+ (03 SO S1)

HA1

CO =AB
S =A" B

2

HA1A

CO = !A B
S = !(A A B)

2

HA1B

CO = !(A B)
S = !(A A B)

2

HA1C

CO = !(A B)
S = (A" B)

FA1A

CO = (CI !B !A) + (A !B) + (B CI A)
S = (B !A !CI) + (CO !A CI) + (CO A !CI)
+ (BACI)

2

FA1B

CO = !A(!B + B CI) + A(!B CI)
S = !A(!CI CO + CI B) + A(!CI B + CI CO)

2

FA2A

CO = (CI !B !(AO+A1» + (!B (AO+A1» +
(B CI (AO+A1»
S = (B !(AO+A1) !CI) + (CO !(AO+A1) CI) +
(CO (AO+A1) !CI) + (B (AO+A1)CI)

2

FA3A

CO = (BO !(AO+A1)!B1)+(!(AO + A1) B1)+
«AO + A1) !B1) + «AO + A1) B1)
S = (BO !(AO + A1) !B2) + (!(AO + A1) B2) +
(BO (AO + A1) !B1)

2

MXCI

Y

MXT

Y = (!S1 !SOA ~O) + (!S1 SOA 01) +
(S1 !SOB 02) + (S1 SOB 03)

OF1
OF1A
OF1B
OF1C
OFC1
OFC1A
OFC1B
OFC1C
OFC10
OFC1E
OFC1F
OFC1G

a = (ClK. O. -. -)
aN = !(ClK. O. -. -)
a = (!ClK. O. -. -)
aN = !(!ClK. O. -. -)
a = (ClK. O. ClR.-)
a = (!ClK. O. ClR. -)
a = (ClK. O. !ClR.-)
aN = !(ClK. O. ClR. -)
a = (!ClK. O. !ClR. -)
aN = !(ClK. O. !ClR. -)
aN = !(!ClK. O. ClR. -)
aN = !(!ClK. O. !ClR. -)

Half

Adders

Full

Boolean

O-type
Flip-Flops

1-208

with clear

=

(!((!S A)

+ (S B» C) + «(!S A) + (S B» D)

2
2
2
2
2
2
2
2
2
2
2
2

A 1OM20A Mask Programmed Gate Array

Hard Macros (continued)
Function

D-type
Flip-Flops
(continued)

Modules
Required

Description

Macro Name

Equatlon(s)

with enable

DFE
DFE1B
DFE1C
DFE2D
DFE3A
DFE3B
DFE3C
DFE3D
DFE4
DFE4A
DFE4B
DFE4C
DFEA
DFEB
DFEC
DFED

Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q

(CLK. E D + IE Q. -. -)
(CLK. IE D + E Q. -. -)
(ICLK. IE D + E Q. -. -)
(ICLK. IE D + E Q. ICLR. PRE)
= (ICLK. ED + IE Q. IClR. -)
= (!ClK. ED + !E Q. !ClR. -)
= (CLK. !E D + E Q. !CLR.-)
= (!CLK. !E D + E Q. !CLR. -)
= (CLK. ED + !E Q. -. PRE)
= (!ClK. E D + !E Q. -. PRE)
= (CLK. !E D + E Q. -. PRE)
= (!ClK. !E D + E Q. -. PRE)
= (!ClK. E D + !E Q. -. -)
= (CLK. E D + !E Q. !ClR.PRE)
= (!ClK. E D + !E Q. !ClR. PRE)
= (ClK. !E D + E Q. !CLR. PRE)

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

with
multiplexed
data

DFM
DFM1B
DFM1C
DFM3
DFM3B
DFM3E
DFM3F
DFM3G
DFM4
DFM4A
DFM4B
DFM4C
DFM4D
DFM4E
DFM5A
DFM5B
DFMA
DFMB

Q = (CLK. !S A + S B. -. -)
QN = !(CLK. !S A + S B. -. -)
QN = !(!ClK. !S A + S B. -. -)
Q = (ClK. !S A + S B. ClR. -)
Q = (!ClK. !S A + S B. !CLR. -)
Q = (!ClK. !S A + S B. ClR. -)
QN = !(ClK. !S A + S B. ClR.-)
QN = !(!CLK. !S A + S B. CLR. -)
Q = (ClK. !SA + S B. -. PRE)
Q = (ClK. !S A + S B. -. !PRE)
Q = (!ClK. !S A + S B. -. !PRE)
QN = !(ClK. !S A + S B. -. !PRE)
QN = !(!ClK. !S A + S B. -. !PRE)
Q = (!CLK. !S A + S B. -. PRE)
Q = (CLK. !S A + S B. !ClR. PRE)
Q = (!ClK. !S A + S B. !CLR. PRE)
Q = (!CLK. !SA + S B. -.-)
Q = (ClK. !S A + S B. !ClR. -)

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

with multiplexed
data and enable

DFME1A

Q = (ClK. !E (!S A

with preset

DFP1
DFP1A
DFP1B
DFP1C
DFP1D
DFPIE
DFP1F
DFP1G

Q = (CLK. D. -. PRE)
Q = (!ClK. D. -. PRE)
Q = (ClK. D. -. !PRE)
QN = !(CLK. D. -. PRE)
Q = (!ClK. D. -. !PRE)
QN = !(ClK. D. -. !PRE)
QN= !(!ClK. D. -. PRE)
QN = !(ICLK. D. -. IPRE)

2
2
2
2
2
2
2
2

with clear and
preset

DFPC
DFPCA

Q = (CLK. D. !CLR. PRE)
Q = (!CLK. D. !CLR. PRE)

2
2

=
=
=
=

+

S B)

+

E Q. -. -)

2

1-209

•

~
Hard Macros (continued)
Function

Macro Name

Equatlon(s)

JKF
JKF1B
JKF2A
JKF2B
JKF2C
JKF2D
JKF3A
JKF3B
JKF3C
JKF3D
JKF4B
JKFPC

Q = (ClK, (!Q J + Q 1<)), -, -)
Q = (!ClK, (!Q J + Q 1<), -, -)
Q = (ClK, (!Q J + Q 1<), !ClR, -)
Q = (!ClK, (!Q J + Q 1<), !ClR, -)
Q = (ClK, (!Q J + Q K), ClR, -)
Q = (!ClK, (!Q J + Q 1<), ClR, -)
Q = (ClK, (!Q J + Q 1<), - !PRE)
Q = (!ClK, (!Q J + Q 1<), -, !PRE)
Q = (ClK, (!Q J + Q 1<), -, PRE)
Q = (!ClK, (!Q J + Q 1<), -, PRE)
Q = (!ClK, (!Q J + Q 1<), !ClR, PRE)
Q = (ClK, (!Q J + Q 1<), !ClR, PRE)

with clear

Dl1
Dl1A
Dl1B
Dl1C
DlC
DlC1
DlC1A
DlC1F
DlC1G
DlCA

Q = (G, D, -, -)
QN = !(G, D, -,-)
Q = (!G, D, -, -)
QN = !(!G, D, -, -)
Q = (G, D, !ClR, -)
Q = (G, D, ClR, -)
Q = (!G, D, ClR, -)
QN = !(G, D, ClR,-)
QN = !(!G, D, ClR, -)
Q = (!G, D, !ClR, -)

with enable

DlE
DlE1D
DlE2A
DlE2B
DlE2C
DlE3A
DlE3B
DlE3C
DlEA
DlEB
DlEC

Q = (G, (E D + !E Q), -, -)
QN = !(!G, (!E D + E Q), -, -)
Q = (!G, (E D + !E Q), ClR, -)
Q = (!G, (!E D + E Q), !ClR, -)
Q = (!G, (!E D + E Q), ClR, -)
Q = (!G, (E D + !E Q), -, PRE)
Q = (!G, (!E D + E Q), -, PRE)
Q = (!G, (!E D + E Q), -, !PRE)
Q = (G, (!E D + E Q), -, -)
Q = (!G, (E D + !E Q), -, -)
Q = (!G, (!E D + E Q), -, -)

with multiplexed
data

DlM
DlM2A
DlMA

Q = (G, (A !S + B S), -, -)
Q = (!G, (A !S + B S), ClR, -)
Q = (!G, (A!S + BS), -,-)

with multiplexed
data and enable

DlME1A

Q

with preset

DlP1
DlP1A
DlP1B
DlP1C
DlP1D
DlP1E

Q = (G, D, -, PRE)
Q = (!G, D, -, PRE)
Q = (G, D, -, !PRE)
Q = (!G, D, -, !PRE)
QN = !(G, D, -, !PRE)
QN = !(!G, D, -, !PRE)

with preset
and clear

DL2A
DL2B
DL2C
DL2D

Q = (G, D, !ClR, PRE)
QN = !(!G, D, ClR, !PRE)
Q = (!G, D, !ClR, PRE)
QN = !(G, D, ClR, !PRE)

Description

JK Flip-Flops

Data Latches

1-210

= (!G,

!E (A !S + B S) + E Q, -, -)

Modules
Required
2
2
2
2
2
2
2
2
2
2
2
2

A 1OM20A Mask Programmed Gate Array

Hard Macros (continued)
Function

Clock Net Interrace
Macros

Logical Tieoff
Macros

Description

Macro Name

Equation(s)

GAN02
GMX4

Y=AG
Y = (00 !SO !G) + (01 !G SO) +
(02 G !SO) + (03 SO G)
Y = !(AG)
Y = !(A + G)
Y=A+G
Y=AAG

GNAN02
GNOR2
GOR2
GXOR

Modules
Required

GNO
VCC

I

1-211

Hard Macro Library Overview
The following illustrations show all the available Hard Macros.

2-lnput Gates (Module Count

= 1)

~ ~ ~
~ ~NAND3P ~NAND~
~ ~ ~
~ ~ ~
3-lnput Gates (Module Count = 1, unless indicated otherwise)

®

Indicates 2-module macro

... Indicates extra delay input

~

~AND~

!§ AND~ !§

~NAN~

~ ~ ~
~ t)NO~
1-212

AND0-r

A 1OM20A Mask Programmed Gate Array

4-lnput Gates (Module Count

= 1, unless indicated otherwise)

®

Indicates 2-module macro

... Indicates extra delay input

~ I10~
A

I1NO~
XOR Gates
(Module Count

XOR OR Gates

= 1)

(Module Count

= 1)

I

XOR AND Gates
(Module Count

~&

c

c

~&

c

~

= 1)

c

AND XOR Gates
(Module Count

= 1)

1-213

AND OR Gates (Module Count = 1)

® Indicates 2-module macro
... Indicates extra delay input

y

A
8
y

A

c

8

D

C
D

1-214

A10M20A Mask Programmed Gate Array

OR AND Gates (Module Count = 1)

®

Indicates 2-module macro

•

Indicates extra delay input

•

1-215

Buffers (Module Count

= 1)

1/0 Buffers (I/O Module Count = 1)

D

D

Multiplexors (Module Count

= 1)

A

A

B

B

DO
D1
D2
D3

C

DO
D1

D

A

D2
D3

B

S

1-216

Y

A 1OM20A Mask Programmed Gate Array

Latches (Module Count = 1)

-O--G--D--G--

---t:J -0 -t:J -t:J

D Latches with Clear (Module Count = 1)

Q

D

OLCA
G

G

CLR

CLR

D Latches with Enable (Module Count

=

Q

D

OLC

1)

I

±:l-D-D-D-

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Mux Latches (Module Count = 1)
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A
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Macros FA1A, FA1B, and FA2A have two level delays from the inputs to the S outputs, as indicated by the'"
1-217

D-type Flip-FlOpS (Module Count

= 2)

-D---G--D--G-

--0 --0 -0 -0

D-type Flip-Flops with Clear

o

D

o

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DFC1C

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DFC1A

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DFC1E

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DFC1F

D
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DFC1G

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CLR

CLR

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0

D-type Flip-Flops with Preset

PRE
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DFP1

DFP1A

DFP1B

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D
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DFP1C

PRE

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DFP1F

PRE
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DFP1G

D

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D

PRE

PRE
0

0

DFP1D

0

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DFP1E

D

0

D-type Flip-Flops with Preset and Clear

PRE
D

1-218

PRE
0

D

0

DFPC

DFPCA

CLR

CLR

A1OM20A Mask Programmed Gate Array

D-type Flip-Flops with Enable (Module Count = 2)

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1-219

Package Pin Assignments: 84-Pin PLCC
(Top View)

oz

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1110987 654 32 184838281807978n7675
74
73
72
71

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MODE

65
64
63
62
61

84-Pln
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GND
GND

59
58
57

66
55
54

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Package Pin Assignments: 6S-Pin PLCC
(Top View)
o
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987 654 3216867666564636261

DClKor I/O
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GND
GND

Vee

MODE

68-Pln
PlCC

Vee
Vee

Notes:
1. MODE must be terminated to circuit ground.
2. All unassigned pins are available for use as liDs.

1-220

ClKor I/O

GND

A 1OM20A Mask Programmed Gate Array

Package Pin Assignments: 100-Pin PQFP
(Top View)

uuuu
zzzz

81
82
83
84
85
GND 86
GND 87
88
89
ClK OR I/O 90
91
MODE 92
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Vee 94
95
96
97
SDI or I/O 98
DClK OR I/O 99
100

8

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50
49
48
47
46
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44
43
42
41
40
39
38
37
36

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Vee

I

GND
GND

35
34
33
32
31

Notes:
1. MODE must be terminated to circuit ground.
2. All unassigned pins are available for use as 1I0s.

1-221

Package Mechanical Details
Plastic J-Leaded Chip Carrier

Pin #1 Index

D1

D

~JJl
-.J ~ .029/1

± .003/1

.175/1 ± .010/1
Lead Count

1-222

D,E

01, E1

68

.990/1 ± .005/1

.955/1 ± .005/1

84

1.190/1 ± .005/1

1.155/1 ± .005/1

A10M20A Mask Programmed Gate Array

Package Mechanical Details (continued)
Plastic Quad Flatpack
Dimensions in millimeters

100

I
2.95 ± .15

.,8,.051
80

t

t

~2.71±.OO

±10~.I~--------~ I~

2000 ±05

.1

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23.20 ± .10 - - - - - - - - - -

1-223

1-224

Array Architecture
for ATG with 100%
Fault Coverage
Abstract
This paper discusses array architecture, circuitry and methodology
for the automatic generation of test vectors. The architecture is
implemented in a mask programmed version of an anti fuse based
FPGA. The architecture allows the designer to 100% control and
observe each node in the circuit. This allows the automatic
generation oftest vectors with 100% fault coverage independent of
the design implemented in the array circuit. In addition to
architecture and circuit implementation details, this paper
discusses the ATG generation methodology and algorithms, circuit
overhead for the test features as well as test times and results.

Overview
To the ASIC user, Field Programmable Gate Arrays (FPGAs) [1)
offer many advantages over conventional mask programmable
gate arrays. A primary advantage of the FPGA is that it speeds up
the "time to market" of the new system by removing the ASIC
design from the critical path of the system design cycle. However,
once the new system goes into high volume production, the user
will often convert his FPGA design into a conventional gate array
to reduce the cost of the system. Though the conversion to a gate
array may ultimately reduce manufacturing costs, significant
engineering time is expended translating FPGA design net lists to a
gate array and, especially, developing test vectors to test the gate
array.
An ideal ASIC solution should (a) provide fast time to market, (b)
reduce high volume manufacturing costs and (c) eliminate the need
for further design engineering involvement in translating netlists
and generating test vectors. A masked programmable gate array,
which is a one-mask version of an antifuse-based FPGA has been
developed to satisfy the above requirements. The architecture of
the antifuse based FPGA shown in Figure 1 is essentially that of a
channelled gate array with rows of functional logic modules
alternating with channels of horizontal routing tracks [1). Antifuses
are programmed to connect the logic module inputs and outputs to
the routing tracks. In the mask programmable version of the
FPGA, the antifuses programmed for a given design are simply
replaced with vias connecting two metal layers, thus preserving the
original netlist. This is accomplished with the aid of software which
automatically converts a fuse design netlist into a via mask layer for
that design. All other mask layers are common between designs.
The MPGA has a much smaller die than the FPGA version
because the antifuses and, more significantly, the associated
programming circuitry have been eliminated, thus providing
substantial cost savings.
A significant advantage of the MPGA over a conventional gate
array, is that the MPG~s architecture includes built-in testability.
This architecture, which is the focus of this paper, reduces the
problem of generating test vectors for an entire design into a set of
predetermined tests of the individual logic modules. Test vectors
are generated automatically to test the user design and
interconnect wiring with 100% fault coverage. It is important to

©

1992 Actel Corporation

Technical Paper

note that while this built-in testability has been implemented in a
mask-programmable version of an FPGA, it could easily be
included in the design of FPGAs and conventional gate arrays.

Architecture and Circuitry
The MPGA architecture, which is similar to the AI020 FPGA
consists of 14 rows and 44 columns of logic modules with routing
channels between the module rows as shown in Figure 1. The user's
logic design is created by interconnecting logic module inputs and
outputs to routing tracks. Logic modules implement the required
logic functions while I/O modules connect logic modules to I/O
buffers and to package pins.
The ATG control operation works as follows. Each logic module
(Figure 2) is divided into an input section LM' and an output
section LM". Each has its own latching capability. The two sections
may be isolated from one another or connected by the operating
modes of the circuit. Since inputs and outputs of all modules are
interconnected together by routing tracks, separating LM' and
LM" of all logic modules essentially breaks the entire design up
into combinational pieces where each LM' of a logic module is
driven by LM" of other modules or its own LM". Using this feature,
complex testing situations such as feedback loops, reconvergent
connections, and sequential circuits are converted into simple
combinational circuits that can be readily tested. Any LM" can be
randomly addressed and controlled with desired logic values which
serve as the stimuli for the LM' sections. Each LM' is tested by
controlling the corresponding LM"s connected to its inputs.
Then, the LM' logic function is computed and latched into the LM'
latch. Subsequently, the latched result is transferred from LM'
latch to LM" for ''ATG observe". In this mode, any LM" can be
randomly addressed and its contents read out to the periphery
circuits [2). Periphery and control circuits provide all the necessary
timing and mode control operations needed to implement the
above functions.

Logic Module
The MPGA Logic Module with testability capability is shown in
Figure 2. The logic module has eight data inputs (SO, SI, SA, AI,
AD, BO, Bl, SB), 1 output (OUT), 5 control signals (Yi, Xi, TDI, C2,
Cl) and a sense output signal (SEN_Xi). Control signals determine
logic module operations in the various operating modes.
As explained above, the logic module is divided into two sections
LM' and LM". Signals Cl and C2 control sections LM' and LM".
When Cl = 0, mux3 is enabled and latchl is transparent. When
Cl = 1, mux3 is disabled with a three-state output and latchl is in a
latching mode. C2=0 turns Ql "ON" and makes latch2
transparent. C2= 1 turns Ql "OFF" and configures latch2 as a
latch. When Ql is "OFF", LM" is disconnected from LM'. By
controlling Cl and C2, the following operations are possible: (a)
data can be stored in latchl and/or latch2, (b) LM" can be
connected or disconnected from LM', and (c) data can be
transferred from LM' to LM".

January 1992

1-225

I

In the ATG Control phase, Xi, Yi, and TDI (fest Data Input) are
used to control LM". In this phase LM" is separated from LM' by
maintaining C2 at "1" and Cl at "0". The ATG Observe phase
works as follows. The controlled LM" outputs drive LM' of other
logic modules (or its own LM') and subsequently causes logic
computation in the driven LM'. Using Cl and C2 control signals
the computed data is first latched into LM' and then transferred to
LM". The final result is then read out via the micro-probe sensing
circuits and the SEN_Xi line. In normal logic module operation,
Cl, C2, and Xi are at "0", latchl and latch2 become transparent,
LM' is connected to LM", and LM" is isolated from the TDI input.

I/O Module
Figure 3 shows the schematic for the 110 Module. P_EN, P_OUT,
and P_IN are direct input and output interconnects to the I/O
Buffer; EN, IN are 110 Module inputs. Xi, Yi, TDI, and SEN_Xi
perform identical functions as the Logic Module. C3, which is
similar to Cl and C2, is for ATG control operation. When C3 =0,
the I/O module is normally operating where P_EN is controlled by
EN input. When C3 = 1, P_EN is controlled by TDI. Thus, the 110
Buffer can be set as an "input pin" or an "output pin" by storing the
appropriate TDI data bit into latch 1 ofI/O module in ATG testing.

Array Test Example
A "5 X 5 Logic Module Array example" with interconnect is shown
in Figure 4. For simplicity, each logic module will be denoted as
LM(Xi,Yi), and each I/O module will be denoted as I/OM(Xi,Yi).
The bottom row address will be XO and the left-most column will be
YO. All LM(Xi,Yi) and I/OM(Xi,Yi) are controlled by Cl, C2, C3,
and TDI global control signals. In a normal chip operation, Cl, C2,
C3, Xi, and Yi are "0" and the array functions are the desired user
design.
Assume LM(2,1) is to be ''ATG-tested''. Inputs LM'(2,1) are
connected to LM"(2, 1), I/OM(3,0), LM"(l,l), and LM"(1,2). When
C2 is placed in "high" state, all LM"(Xi,Yi) are disconnected from
their LM'(Xi,Yi). Also, all logic module data are preserved at the
LM" latches. By addressing and controlling LM"(2,1), LM"(l,l),
and LM"(1,2), inputs ofLM'(2,1) can be set to a specific test vector
for ATG testing. Since IOM(3,0) is one of the inputs to LM'(2,1)
also, its associated I/O buffer needs to be converted to an input pin
so that test vectors can be applied to the pin directly. This is
achieved by ATG control of IOM(3,0) with a data value "1".
After the ATG control is completed for the inputs ofLM'(2,1), Cl
is placed in "high" state to latch new data in all LM'(Xi,Yi). Then,
C2 is placed in "low" state to connect and enable data transfer from
LM' to LM". New data can be read from the corresponding
SEN_Xi linefor verification. As for LM(2,1), new data is read from
SEN_X2line and this completes the ATG testing for this particular
logic module and its input interconnects to the other modules.

1-226

Automatic Test Generation (ATG)
An example of a basic test flow is illustrated as follows. One of the
greatest difficulties in ATG is testing circuits that contain
sequential elements, feedback loops and reconvergent fan-outs.
Instead of generating ATG vectors for the complete circuit, vectors
are generated only for the logic module whose simplified ATG
model is shown in Figure 5. The only variable in this "logic module
ATG" is the connectivity of the circuit. Feedback connections used
to implement sequential circuits are broken by virtue of the split
module sections described above. Sequential testing is thus
replaced by combinational testing.
The module shown in Figure 5 has no reconvergent fan-out. The
module is composed of a few primitive gates. The small size of the
module and the fact that it is free of feedback and reconvergent
fan-outs means it is practical to exhaustively scan the complete
search space for a test solution. This implies the fact that if a fault is
detectable, the logic module ATG will always find a test vector in a
reasonable amount of time. Thus, the module is guaranteed a
100% fault coverage (single stuck-at-O, stuck-at-l fault model).
Compared to other test approaches, without any built-in testability,
feedback, reconvergent fan-outs or just circuit complexity make
ATG systems CPU or memory bound, possibly yielding poor fault
coverage. Scan design and built-in probing provide some form of
built in testability, but SUb-circuits partitioned by scan cells, may
still contain reconvergent fan-outs, and are thus difficult for ATG
testing. In general, scan based ATG systems give very good fault
coverage, but 100% fault coverage is still rarely achievable.
Unlike scan based ATG systems, the MPGA architecture provides
design independent ATG. Built-in testability shields testing details
from the designer and more importantly, simplifies the ATG
problem.

ATG Strategy
The ATG strategy is to generate a test vector which completely
tests each module based on its input net configuration. Vector sets
of each module are grouped together to form a single set of vectors
which are translated to different tester formats.
In order to generate a compact vector set, a traditional ATG
approach is used. The ATG uses simple D-algorithm for vector
generation and a fault simulator for compaction. A single fault is
picked from a list of alI possible faults. A D-algorithm is performed
to see if the fault is detectable. If an undetectable fault (redundant
fault, which has no effect on the circuit) is found, the fault will be
removed from the fault list. If the fault is detectable, the vector is
fault simulated to see if more faults can be detected. AlI detected
faults are removed from the fault list until the list is exhausted.
The fault model is based on single stuck-at-zero and stuck-at-one
faults on input pins of primitive gates. Output pin and interconnect
stuck-at faults are tested by verifying their equivalent stuck-at faults
at input pins.

Array Architecture for ATG with 100% Fault Coverage

Multiplexor Fault Modeling
The MPGA module is based on 2 input multiplexors. General gate
array fault modeling approaches usually treat the Multiplexor as a
primitive gate as shown in Figure 6 and model the multiplexor as a
combination of AND, OR gates. This is not an accurate fault
representation. In our ATG module, a more detailed representation is
shown in Figure 7. The advantage of modelling at such low level, is
that we can examine one of the multiplexor problems [6]
traditionally ignored by ATG systems. If the select line S is at fault,
we can detect its fault. But if the gate of the transistor is stuck at 0
(Figure 8), a correct result should be the value ofB. But for a faulty
device, both transistors are turned off and thus the output node is at
high impedance state. This is the same as a stuck open fault on the
output pin, a vector pair fault, which can be detected by transition.
To handle such a special case, the D-algorithm is extended to
support vector pair generation. Whenever the fault under test is the
stuck-at-O fault on the gate of the multiplexor, the D-algorithm
switches into transition vector pairs mode. The fault simulator also
extends its capability to fault simulate transition vector pairs.

Design Independent Testing
To complete the testing of the array, there are several tests which
are independent of the implemented design. The tests include (a)
DC Input Levels (VIH, V 1L), (b) DC Output Levels (VIH, V 1L, V OH ,
VOL, I oL), (c) Net Shorts test, (d) Three-state Output Leakage, and
(e) Static IDD.

Net Shorts Testing
The algorithms used for the module test ATG, and probably all
ATG algorithms, use the circuit schematic as input for vector
generation. The actual layout of the schematic in silicon is not
considered in the ATG process. Therefore, as shown in Figure 8,
test vectors generated to exercise Net A, do not consider the
potential for a short between Net A and Net B, which cross each
other in the layout. However, the built-in testability of the MPGA
allows net shorts testing to be performed.
Net shorts testing is accomplished by first latching logic Is into the
outputs of a set of modules and logic Os into the outputs of the
remaining logic modules. Then, the static current of the power
supply is measured. If the current is increased over a previously
measured baseline value, there must be a short between at least two
of the nets driven to opposite states.
The vector set for net shorts testing is surprisingly compact, with
only 10 vectors/current measurements required. A vector set is
used to test for shorts between nets driven from modules in
different rows of the array. Similarly, another vector set is used to
test for shorts between nets driven from modules in a different
column of the array. When the two vector sets are combined, they
exhaustively check for every short. (Note that the vector set for a

particularrow or column is a binary expansion ofthe row or column
number.) Furthermore, the vector set is completely design
independent and depends only on the number of columns and rows
of logic modules in the base array.

DC/Parametric Testing
The MPGXs testing architecture allows for all DC and parametric
testing to be design independent. The control and observe features
of the I/O modules provide much of this capability. For example, to
test input levels (VIH, V 1L), the I/O module is first set as an "input
pin" using the ATG control feature to three-state its associated
output. The switching levels of an input signal are applied to the
I/O module so that it can be monitored with the addressable
microprobe. This three-state mode is also used to measure leakage
current in the disabled output buffer and to measure static IDD.

Conclusion
A logic array architecture and circuit implementation for the
automatic generation of test vectors has been presented. A masked
programmed gate array, which is just one version of an antifuse
based FPGA has been developed to satisfy the above requirements.
A key feature of the architecture is the ability to control and
observe 100% of every node in the design. The test algorithms and
methodology used to achieve 100% fault coverage is presented.
Three user designs have been implemented. The designs required
an average of 4.8 vectors per module for a total of 2600 vectors per
design. Test time was well below 1 second.

Acknowledgements
The authors gratefully acknowledge contributions from Jon
Greene, Paul Jasmine, Kurt Kolkind, Sifuei Ku, Ken Joyner, Telle
Whitney and Kitty Shaw.

References
1. EI-Ayat, K. et ai, ''A CMOS Electrically Configurable Gate
Array", IEEE Journal of Solid State Circuits, Vol. 24, No.3,
June 1989.

2. EI-Ayat, K. et ai, "Testing Apparatus and Diagnostic Method
for use with Programmable Interconnect Architecture", U.S.
Patent # 4,857,774.
3. Gheewala, T., "CrossCheck: A Cell Based VLSr Testability
Solution", Proc. Design Automation Conference, 1989, pp. 706.
4. TestScan Product Description, Cadence Design Systems.
5. Roth, J.P', "Diagnosis of Automata Failures: A Calculus and a
Method", IBM Journal of Research and Development, Vol. 10,
July 1966, pp. 278-291.
6. Makar S.R. and McCluskey E.J., "On the Testing of
Multiplexors", Proc. Int. Test Conf., 1988.

1-227

I

PROGRAMMED
HORIZONTAL
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PROGRAMMED
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Figure 1. Channelled Gate Array Architecture of Antlfuse Based FPGA

1-228

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Array Architecture for ATG with 100% Fault Coverage

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1-229

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1 230

Array Architecture for ATG with 100% Fault Coverage

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1-231

I

SO
S1

SA

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Figure 5. ATG Model of Logic Module

1-232

Array Architecture for ATG with 100% Fault Coverage

s-----,
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Figure 7. Realistic Multiplexor Model

1-233

Force-to-1

L

s-----.-------,

B-----+------'
High Impedance

...------y

A-----------'

Good Machine:

Y = Value of B. Vector pair toggles B.

Bad Machine:

Y = High impedance. Vector pair has no effect on value of Y.

Figure 8. Testing a MUX for Stuck-at-O Fault with a Vector Pair

1-234

Array Architecture for ATG with 100% Fault Coverage

NET A

/

POTENTIAL SHORT

NET B

•

Figure 9. Layout of Two Independent Nets

1-235

1-236

Development Tools

Software Product Selector Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1

Action Logic System FPGA Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-3

Action Logic System on 386 PC Platform .....................................................................

2-5

Action Logic System for Mentor Graphics Design System ............. ,. . . . .. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .

2-7

Action Logic System for Valid Logic Design System ............................................................

2-9

Action Logic System for Viewlogic/Sun Design System ......................................................... 2-11
Activator 2 Programmer/Tester/Dubugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-13
Using Actionprobe Diagnostic Tools ......................................................................... 2-15
Using the Actel Debugger as a Functional Tester. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-17

Software Product
Selector Guide
ALS System Selector Table
Activator 2
Actionprobe
Activator 1
Programmer Programmer Diagnostics

Simulation

ACT2 FPGA
ACT1 FPGA
Design Software Design

Includes
VI EWDRAW®
Supports
OrCAD/SOT III

Optional
VIEWSIM®
Supports
OrCAONST®

Included

Optional

Included

Optional

Included

ALS-113

Includes
VI EWORAW
Supports
OrCAD/SOT III

Optional
VIEWSIM
Supports
OrCADNST

Included

Optional

Included

Optional

Optional

386 PC with
VIEWLOGIC/
OrCAD/SOT III

ALS-115

Includes
VI EWORAW
Supports
OrCAD/SOT III

Optional
VIEWSIM
Supports
OrCAONST

Included

Optional

Optional

Optional

Optional

386 PC with
VIEWLOGIC/
OrCAD/SOT III

ALS-210

Includes
VI EWORAW
Supports
OrCAD/SDT III

Optional
VIEWSIM
Supports
OrCADNST

Included

Included

Not
Required

Included

Included

386 PC with
VIEWLOGIC/
OrCAO/SOT III

ALS-213

Includes
VI EWORAW
Supports
OrCAO/SOT III

Optional
VIEWSIM
Supports
OrCAONST

Included

Included

Not
Required

Included

Optional

386 PC with
VIEWLOGIC/
OrCAO/SDT III

ALS-215

Includes
VI EWORAW
Supports
OrCAO/SOT III

Optional
VIEWSIM
Supports
OrCAONST

Included

Included

Optional

Optional

Optional

ALS-035
MENTOR
GRAPHICS CAE
(HPApollo®)

Supports
NETED®

Supports
QU/CKS/M®

Included

Optional

Optional

Optional

Optional

ALS-230
MENTOR
GRAPHICS CAE
(HP Apollo)

Supports
NETED

Supports
QUICKSIM

Included

Included

Not
Required

Included

Included

ALS-233
MENTOR
GRAPHICS CAE
(HPApollo)

Supports
NETED

Supports
QUICKSIM

Included

Included

Not
Required

Included

Optional

ALS-235
MENTOR
GRAPHICS CAE
(HPApollo)

Supports
NETED

Supports
QUICKSIM

Included

Included

Optional

Optional

Optional

ALS-045
VALID LOGIC
(Sun Microsystems™)

Supports
VALIDGED®

Supports
VALIDSIM®/
RAPIDSIM®

Included

Optional

Optional

Optional

Optional

ALS-240
VALID LOGIC
(Sun Microsystems)

Supports

Supports
VALIDGED
RAPIDSIM

Included
VALIDSIM/

Included

Not

Included
Required

Included

VALID LOGIC
ALS-243
(Sun Microsystems)

Supports

Supports
VALIDGED
RAPIDSIM

Included
VALIDSIM/

Included

Not

Included
Required

Optional

VALID LOGIC
ALS-245
(Sun Microsystems)

Supports

Supports
VALIDGED
RAPIDSIM

Included
VALIDSIM/

Included

Optional

Optional

Optional

VIEW LOGIC
ALS-055
(Sun Microsystems)

VI EWDRAW

VIEWSIM
(Supports)

Included
(Supports)

Optional

Optional

Optional

Optional

VIEW LOGIC
ALS-250
(Sun Microsystems)

VI EWDRAW

VIEWSIM
(Supports)

Included
(Supports)

Included

Not

Included
Required

Included

ALS-253
VIEW LOGIC
(Sun Microsystems)

VI EWDRAW

VIEWSIM
(Supports)

Included
(Supports)

Included

Not

Included
Required

Optional

ALS-255
VIEW LOGIC
(Sun Microsystems)

VIEWDRAW

VIEWSIM
(Supports)

Included
(Supports)

Included

Optional

Optional

Optional

Host
Environment

Actel System Schematic
Part Number Capture

386 PC with
VIEWLOGIC®/
OrCAD/SDT III®

ALS-110

386 PC with
VIEWLOGIC/
OrCAD/SOT III

©

1992 Actel Corporation

April 1992

II

2-1

2 2

Action Logic System
FPGA Design Environment
Overview
The Action Logic™ System (ALS) is a high-productivity
Computer Aided Engineering environment for designing with the
ACT™ series of field programmable gate array devices. A
menu-driven interface allows users to complete ACT designs, from
concept to silicon, in hours without costly Non-Recurring
Engineering costs. The system includes a software development
environment and an Activator™ programmer, tester, and
debugger. ALS is supported on most popular CAE platforms.
Designers use their PCs or workstations to capture schematics; to
simulate, verify, place and route; to perform timing analysis; to
program and to debug the chip. On-line help screens and detailed
reference manuals speed and simplify the design process.
To help you select the version of the Action Logic System that is
correct for your needs, we will first explain the various modules that
make up the software, and then show the platforms they run on.

Schematic Capture and Simulation
Users enter the design into the ACT device by drawing a schematic
using the Actel Macro Library. When schematic capture is
complete, functional simulation can be performed on the design. If
the 386 PC Viewlogic version of the ALS is purchased, then the
schematic capture system is provided by Actel. For all other
platforms, Actel provides the Macro Library for an existing
schematic capture system.

Gate Array Macro Library
The Actel Macro Library contains the logic function building
blocks necessary to create a design. The library includes macros
ranging in complexity from simple gates to complex functions.
Each macro has a graphic symbol or icon. Hard macros also
::ontain placement information, a netIist, and timing data.
Basic gates from the library are used to create soft macros, such as
~ounters, adders, and decoders. The Actel Macro Library contains
:wer 200 different macros.

Pin Editor
fhe Actel Pin Editor is an easy-to-use, menu-driven program for
lser assignment of logic 1/0s and package pins. The Editor
lUtomatically scrolls a list of all user-designated I/Os. The user
:hen chooses whether the pins should be assigned manually or
lUtomatically. To manually assign any pin to an I/O, the user simply
!nters the desired pin number next to the I/O node name. During
!ach pin assignment, the Editor ensures that each pin is a valid
Jackage pin and is not already assigned to another chip I/O.
'\utomatic I/O pin assignment is also available.

)esign Validator
[he Actel Design Validator examines an ACT design for
ldherence to design rules specific to the ACT device chosen for the

;:, 1992 Actel Corporation

Product
Brief

design. Validation verifies routability and performs design rule
checks prior to routing. The Validator produces error and
information messages and system warnings regarding electrical
rule violations such as excessive fan-out, shorted outputs, or
unconnected inputs. For example, a warning message is issued if a
net exceeds a fan-out of ten. An unconnected module input,
however, produces an error message.
The Validator also provides statistical information about
rout ability, logic module count, average fanout per net, and array
utilization. After passing through the Validator, the design is free of
electrical rule violations.

Automatic Place and Route
Fully automatic place and route software minimizes design delay by
assigning macros to optimal locations in the chip. The system uses
the design's netIist, critical net information, and I/O assignments to
automatically place and route all the logic blocks within the circuit.
No manual intervention is required, even at high device utilization.
The software provides the user with data on actual wire lengths,
capacitive loading, and wiring congestion. The route program
assigns the shortest possible net segments to connect the library
macros with minimal delay, routing 100% of the nets automatically
for 85% to 95% logic module utilization.

Timing Analysis
The timing analyzer (Timer) is an interactive tool that determines
and highlights all critical and non-critical paths within a specified
design. After the layout phase is completed, the Timer extracts
accurate net delays. These delays are back annotated to the netIist
and evaluated with the Timer or a CAE simulator. Using this
information, the designer can optimize the design to meet timing
specifications. The Timer accepts as input the design's netIist and
delay information. The user directs the type of analysis and output.
Delay reports generated by the timing analyzer using post-route
numbers provide the final AC specifications for the design.
The user also can perform timing analysis using an optional CAE
simulator supplied by vendors such as Viewlogic, Mentor or
Cadence. The Action Logic System can generate a post-route
annotation file which can be used by these simulators to provide
accurate timing information.

Device Programming and Functional Test
Programming is controlled by the Activator programming system.
The Activator 1 system only programs ACT 1 devices and is
supplied with most of the entry level packages that support the
ACT 1 family. The Activator 2 system programs both ACT 1 and
ACT 2 families of devices and is supplied with most of the design
packages that support both families.
Action Logic software generates a fuse map for the ACT device,
which is used by the Activator for programming. A series of
internal address registers that specify the programming element

April 1992

2-3

II

(PLICE™ Antifuse) to be programmed are loaded automatically.
A programming sequence is then initiated, creating a permanent
link. These steps are repeated until all interconnections are made.
The Activator also supports functional testing using an I/O test
vector file.
In addition, Actel supports third party programmers such as the
data I/O Unisite@.

In-Circuit Test and Debug
Once the device is programmed and functionally verified, it is ready
for operation in the user's system. Actionprobe™ diagnostic tools
may then be used to further evaluate circuit integrity. The
Actionprobe diagnostic tool is an adapter to the Activator
programmer which connects to the ACT device socket in the target
system. Under full control of the Actionprobe software, any two of
the internal networks can be selected to be brought out on the two
diagnostic probe pins for analysis. Timing and waveform analysis is
then accomplished using an oscilloscope or a logic analyzer.
Versions of the Actionprobe system are available for both the
Activator 1 and the Activator 2 programming systems.
Optional features are:

ALES Logic Optimizer
The Actel Logic Optimizer (ALES™ 1) allows designers to
combine schematics with PAL) equations (pALASM™ 2,
ABEL™, CUPL™). The synthesized logic can then be simulated
and integrated into a hierarchical design with emphasis on
optimizing either area or delay. ALES is available for the 386 PC
platform, and the Apollo and Sun workstations.

Synopsys Libraries
Actel supplies a technology library for the Synopsys logic synthesis
environment. It allows designers to capture Actel designs by
entering VHDUHDL format source files into Synopsys' design
compiler. The design compiler outputs an EDIF netlist, which is
read by the Actel supplied ED IF reader in the ALS design
environment. Versions of the Synopsys libraries are available for all
the design platforms except the 386 Pc.

Annual Support/Update Program
An Annual Support agreement ensures that the software you
purchase is up to date and that you get priority service when you
have problems or technical questions. It also ensures that the
software you have supports the most recently released devices and
packages. Software upgrades are typically released twice a year and
are sent to Annual Support agreement holders free of charge.
The Support/Update program also gives you access to technical
expertise via the Actel Technical Hotline. Applications engineers
are available anytime during Actel's regular working hours to
answer your questions or fix your problems. You also have access to
Actel's on-line Bulletin Board System. Services available via the
BBS are:
• Known Bug List
• Software Corrections and Updates
• User-designed Macro Library.

2-4

• Design file Uploading and Downloading for troubleshooting
purposes
• Message service for communicating with applications
engineers
• User Forum for communicating with other users of Actel
products

Design Platforms
Versions of the Action Logic System are available to run on a
variety of platforms. Because not all users will need all of the
capabilities (or want all the expense) provided by the complete
system, Actel has made several versions of the ALS available for
each platform. These versions include:
• ACT 1 software support only
• ACT 1 software support and the Activator 1 programmer
• ACT 1 software support, the Activator 1 programmer, and
the Actionprobe diagnostics
• ACT 1 and ACT 2 software support
• ACT 1 and ACT 2 software support and the Activator 2
Programmer
• ACT 1 and ACT 2 software support, the Activator 2
programmer, and the Actionprobe diagnostics
The system can be upgraded to add missing functions whenever the
customer desires.
The basic platforms supported are:
Viewlogic and orCAD on 386 PC. This system is designed to run
on an 80386 or 80486 processor based IBM-compatible PC running
DOS. Actel provides the Viewlogic Viewdraw schematic capture
package, the Actel Macro Library, and the Action Logic System
design modules. Viewsim simulation support is available from
Actel as an option. Libraries supporting the OrCAD schematic
capture system are also provided.
Mentor Graphics on HP/Apollo Workstation. This version
integrates with existing design systems utilizing Mentor Graphics'
NETED schematic capture and QuickSim simulator running on
HP/Apollo workstations. Actel provides the Actel Macro Libraries
and the Action Logic System design software designed to link
directly with the Mentor Graphics netlist format.
VALID Logic on Sun Workstation. This version integrates with
existing design systems utilizing Valid's ValidGED schematic
capture and ValidSIM and RapidSIM simulator running on Sun
Workstations. Actel provides the Actel Macro Libraries and the
Action Logic System design software. Design files can be exported
directly from Valid's netlist format.
Viewlogic on Sun Workstations. Provides ACT 1 or ACT 1 and
ACT 2 design and programming capability for an existing
Viewlogic design system running on a Sun Workstation. Actel
provides the Actel Macro Libraries and the Action Logic System
design software. Design files can be exported directly from
Viewlogic's netlist format into the Actel ALS system.
A selector guide was provided at the front of this chapter to help
you select the version of the software that best suits your needs.
Complete datasheets on each version of the software follow.

Action Logic System
for 386 PC Platform

Product
Brief

Action Logic System Software and Hardware with
Viewlogic Schematic Capture for ACT 1 and ACT 2 Designs
Development System Capabilities

Hardware Requirements

ACT 1 and ACT 2 FPGA Design, Programming and Design
Verification/Probe capability for 80386 based IBM-PCs and
compatibles.

386-Based PC-AT with:

Actel's Action Logic™ System (ALS) for the 386 PC platform is a
low-cost Field Programmable Gate Array design and
programming system for the ACT™ 1 and ACT™ 2 families. The
software included with the system consists of Viewlogic's 3150
schematic capture software and the Actel design software and ACT
1 and ACT 2 Macro Libraries for the Viewlogic environment. Also
included is the Actel Activator® Programmer and debugger, and
the Actionprobe. diagnostic tools. The ACT Macro Library
integrates with the Viewlogic schematic capture and simulator
(optional) packages to provide all of the elements for a complete
FPGA design, simulation, and programming environment. Design
files can be exported from Viewlogic directly into the ALS
environment.

• One Parallel Port

After importing the files, the ALS Design Validator verifies design
rule compliance by completing an electrical rules check and
provides statistical use information such as utilization percentage
and average fan-out. After validation, the automatic place and
route software configures the device to the engineer's design.
Through the use of the Timer, an engineer can check circuit timing
before and after the place and route. Once the design is optimized,
the Activator programmer programs the proper antifuses to
configure the FPGA. The debugger software allows the designer to
check the functionality of the FPGA by running test vectors
through the device using the Activator programmer. The
Actionprobe hardware and software provides 100% real-time
observability of internal nodes while the FPGA is in the target
system.
For users who do not need all of these capabilities, versions of the
development system are offered without all of the features of the
complete system. The hardware and software can be upgraded
later as the user's needs change.
The Action Logic System for the 386 PC platform also includes the
OrCAD/SDT and OrCADNST interface and macro libraries.
These allow the system to work with an installed copy of
OrCAD/SDT Version 3.1 or higher.

Software Requirements
MS-DOS 3.0 (or later)
Note: OreAD users need SDT III Release 3.1 or 3.2.
Viewlogic users need Viewlogic release 3.2 or 4.0.

©

1992 Actel Corporation

• 4 Megabytes RAM (8Mb recommended)
• One RS-232C Port (COMI or COM2)
• 40 Megabyte Hard Disk (40 Mb recommended)
• 1.2 or 1.44 Megabyte Floppy Drive
• VGA, EGA, or Monochrome Graphics Card
• Vacant 1/2 Card AT Bus Slot

Simulators
ALS-016: Viewlogic's 3350 Simulator. Fully integrated to
Viewlogic's schematic capture and Actel's ALS design system for
complete FPGA simulation. The ALS-016 is a menu-driven
interactive simulator that provides pre-layout and post-layout
timing simulation with delay back annotation to verify
performance after layout. Advanced interactive debugging tools
help designers quickly find and eliminate problems.
ALS-016S: Annual Support Fee, per system. Order with ALS-OI6.
ALS-017: Viewlogic's low-cost simulator. Similar in capabilities to
the ALS-016 with a maximum simulation capability of 3000 gates.
ALS-017S: Annual Support Fee, per system. Order with ALS-017.

ALES 1 Logic Optimizer
ALS-114: Actel Logic Optimizer (ALESTM 1) allows designers to
combine schematics with PAL® equations (PALASM®2, ABEL,
CUPL). The synthesized logic can be simulated and integrated into
a hierarchical design with emphasis on optimizing either area or
delay.
ALS-114S: Annual Support Fee, per system. Order with ALS-1l4.

Schematic Generator
ALS-VL-001: Viewlogic's Viewgen schematic generator. Allows
Viewdraw schematics to be created from an Actel or Viewlogic
netlist.

Activator 2 Programming Modules
ALS-280:
ALS-281:
ALS-282:
ALS-283:
ALS-284:
ALS-285:
ALS-286:

April 1992

100 OFP (ACT 1)
44PLCC
68PLCC
84PLCC
84PGA
840FP
132PGA

ALS-287: 176PGA
ALS-288: 84 PLCC (ACT 2)
ALS-289: 100 PGA (ACT 2)
ALS-290: 1oo0FP (ACT 2)
ALS-292: 1440FP
ALS-293: 1600FP
ALS-294: 1720FP

2-5

I

~

~
ALS System Selector Table
ACTEL System
Part Number

ACT 1 FPGA
Design Software

ACT 2 FPGA

ALS-110

Included

Optional

Included

Optional

Included

ALS-113

Included

Optional

Included

Optional

Optional

ALS-115

Included

Optional

Optional

Optional

Optional

ALS-210

Included

Included

Not Required

Included

Included

ALS-213

Included

Included

Not Required

Included

Optional

ALS-215

Included

Included

Optional

Optional

Optional

Design Software

Activator 1
Programmer

Activator 2
Programmer

Actlonprobe
Diagnostics

Software and Hardware upgrades are available for Actel systems. Please contact your local sales representative for details and pricing.

2-6

Action Logic System
for Mentor Graphics
Design System

Product
Brief

Action Logic System Software and Hardware for
EXisting Mentor Graphics Design System for ACT 1 and ACT 2 Designs
Development System Capabilities

Hardware Components

ACT 1 and ACT 2 FPGA Design, Programming, and Design
Verification/Probe Capability for Existing Mentor Graphics
Design System on HP/Apollo Workstation

• Activator 2 Programmer

Software Requirements

Description
The Action Logic System (ALS) is a complete ACT 1 and ACT 2
FPGS design, debugging, and programming system (for Mentor
Graphics on HP/Apollo workstations). The ALS-230 macro
library fully integrates with existing Mentor Graphics design
systems utilizing Mentor Graphics' NETED schematic capture and
QuickSim simulator. The design files can be exported from Mentor
Graphics' netlist format directly into the Actel ALS environment,
which is resident on the HP/Apollo workstation.
After importing the files, the ALS Design Validator verifies design
rule compliance by completing an electrical rules check and
provides statistical use information such as utilization percentage
and average fanout. After validation, the automatic place and route
software configures the gate array to the engineer's design.
Through the use of the Timer, an engineer can check circuit timing
for the place and route. Once the design is optimized, the Activator
2 Programmer programs the proper antifuses to configure the
FPGA. The Activator 2 can program up to 4 devices simultaneously
in approximately one-half the time of the Activator 1 Programmer.
Modular approach allows for different packages to be programmed
by switching programming modules. Lastly, the Actionprobe
diagnostics hardware and software provides 100% real time
observability of internal nodes while the FPGA is running in the
target system.
For users who do not need all of these capabilities, versions of the
development system are offered without all of the features of the
complete system. The hardware and software can be upgraded
later as the user's needs change.

Software Components
ACT 1 / ACT 2 FPGA Design System for Apollo:
• Macro Library
• Automatic Placement and Routing
• Timing Analysis

• Actionprobe Diagnostic Pod

• Mentor Graphics Idea Station Release 7.0 (for Capture and
Design) and AEGIS Release 10.3 or Greater

Hardware Requirements
• HP/Apollo series DN3000, DN4000, 400S, AND 400T

Options
ALES Logic Optimizer
ALS-134: Actel Logic Optimizer (ALES 1) for Mentor Graphics
on HP/Apollo allows designers to combine schematics with PAL
equations (PALASM2, ABEL, CUPL). The synthesized logic can
be simulated and integrated into a hierarchical design with
emphasis on optimizing either area or delay.
ALS-134S: Annual Support Fee, per system. Order with ALS-134.

Synthesis
ALS-SYN-DN: Actel's technology libraries for the Synopsys logic
synthesis environment. Allows designers to capture Actel designs
by entering VHDUHDL format source files in Synopsys' design
compiler. The design compiler outputs an EDIF format netlist
which is read by the Actel supplied EDIF reader in the Actel ALS
design environment. The remaining design validation, placement
and routing, and programming steps are completed in the ALS
environment.

Activator 2 Programming Modules
ALS-280:
ALS-281:
ALS-282:
ALS-283:
ALS-284:
ALS-285:
ALS-286:

100 OFP (ACT 1)
44PLCC
68PLCC
84PLCC
84PGA
840FQ
132PGA

ALS-287:
ALS-288:
ALS-289:
ALS-290:
ALS-292:
ALS-293:
ALS-294:

176PGA
84 PLCC (ACT 2)
100 PGA (ACT 2)
1000FP (ACT 2)
1440FP
1600FP
1720FP

• Design Verification and In-Circuit Probe Software

©

1992 Actel Corporation

April 1992

2 7

I

ALS System Selector Table
ACTEL System
Part Number

ACT 1 FPGA
Design Software

ACT 2 FPGA
Design Software

Activator 1
Programmer

Activator 2
Programmer

Actlonprobe
Diagnostics

ALS-035

Included

Optional

Optional

Optional

Optional

ALS-230

Included

Included

Not Required

Included

Included

ALS-233

Included

Included

Not Required

Included

Optional

ALS-235

Included

Included

Optional

Optional

Optional

Software and Hardware upgrades are available for Actel systems. Please contact your local sales representative for details and pricing.

2-8

Action Logic System
for Valid Logic
Design System

Product
Brief

Action Logic System Software and Hardware for
Existing Valid Logic Design System for ACT 1 and ACT 2 Designs
Development System Capabilities

Hardware Components

ACT 1 and ACT 2 FPGA Design, Programming, and Design
Verification/Probe Capability for Existing Valid Logic Design
System on Sun Workstation

• Activator 2 Programmer

Software Requirements

Description
The Action Logic System (ALS) is a complete ACT 1 and ACT 2
FPGA design, debugging, and programming system (for Valid
Logic on Sun workstations). The ALS-240 macro library fully
integrates with existing Valid Logic design systems utilizing Valid's
ValidGED schematic capture and ValidSIM/RapidSIM simulator.
The design files can be exported from Valid's netIist format directly
into the Actel ALS environment, which is resident on the Sun
workstation.
After importing the files, the ALS Design Validator verifies design
rule compliance by completing an electrical rules check and
provides statistical use information such as utilization percentage
and average fanout. After validation, the automatic place and route
software configures the gate array to the engineer's design.
Through the use of the Timer, an engineer can check circuit timing
for the place and route. Once the design is optimized, the Activator
2 Programmer programs the proper antifuses to configure the
FPGA. The Activator 2 can program up to 4 devices simultaneously
in approximately one-half the time of the Activator 1 Programmer.
Modular approach allows for different packages to be programmed
by switching programming modules. Lastly, the Actionprobe
diagnostics hardware and software provides 100% real time
observability of internal nodes while the FPGA is running in the
target system.
For users who do not need all of these capabilities, versions of the
development system are offered without all of the features of the
complete system. The hardware and software can be upgraded
later as the user's needs change.

Software Components
ACT 1 / ACT 2 FPGA Design System for Sun:
• Macro Library
• Automatic Placement and Routing
• Timing Analysis

• Actionprobe Diagnostic Pod

• Sun OS 4.0.3 or 4.1

Hardware Requirements
• Sun CAE Workstation

Options
ALES Logic Optimizer
ALS-144: Actel Logic Optimizer (ALES 1) for Valid on Sun allows
designers to combine schematics with PAL equations (PALASM2,
ABEL, CUPL). The synthesized logic can be simulated and
integrated into a hierarchical design with emphasis on optimizing
either area or delay.
ALS-144S: Annual Support Fee, per system. Order with ALS-l44.

Synthesis
ALS-SYN-S4: Actel's technology libraries for the Synopsys logic
synthesis environment. Allows designers to capture Actel designs
by entering VHDL/HDL format source files in Synopsys' design
compiler. The design compiler outputs an EDIF format netlist
which is read by the Actel supplied EDIF reader in the Actel ALS
design environment. The remaining design validation, placement
and routing, and programming steps are completed in the ALS
environment.

Activator 2 Programming Modules
ALS-280:
ALS-281:
ALS-282:
ALS-283:
ALS-284:
ALS-285:
ALS-286:

100 OFP (ACT 1)
44PLCC
68PLCC
84PLCC
84PGA
840FP
132PGA

ALS-287:
ALS-288:
ALS-289:
ALS-290:
ALS-292:
ALS-293:
ALS-294:

176PGA
84 PLCC (ACT 2)
100 PGA (ACT 2)
1000FP (ACT 2)
1440FP
1600FP
1720FP

• Design Verification and In-Circuit Probe Software

©

1992 Actel Corporation

April 1992

2-9

I

ALS System Selector Table
ACTEL System
Part Number

ACT 1 FPGA
Design SoftWare

ACT 2 FPGA
Design SoftWare

Activator 1
Programmer

Activator 2
Programmer

Actlonprobe
Diagnostics

ALS-045

Included

Optional

Optional

Optional

Optional

ALS-240

Included

Included

Not Required

Included

Included

ALS-243

Included

Included

Not Required

Included

Optional

ALS-245

Included

Included

Optional

Optional

Optional

Software and Hardware upgrades are available for ActeI systems. Please contact your local sales representative for details and pricing.

2-10

Action Logic System
for Viewlogic/Sun
Design System

Product
Brief

Action Logic System Software and Hardware for
Existing Viewlogic Design System for ACT 1 and ACT 2 Designs
Development System Capabilities

Hardware Components

ACT 1 and ACT 2 FPGA Design, Programming, and Design
Verification/Probe Capability for Existing Viewlogic Design
System on Sun Workstation

• Activator 2 Programmer
• Actionprobe Diagnostic Pod

Software Requirements

Description
The Action Logic System (ALS) is a complete ACT 1 and ACT 2
FPGA design, debugging, and programming system (for Viewlogic
on Sun workstations). The ALS-2S0 macro library fully integrates
with existing Viewlogic design systems utilizing Viewlogic's
Viewdraw schematic capture and Viewsim simulator. The design
files can be exported from Viewlogic's netlist format directly into
the Actel ALS environment, which is resident on the Sun
workstation.
After importing the files, the ALS Design Validator verifies design
rule compliance by completing an electrical rules check and
provides statistical use information such as utilization percentage
and average fanout. Mter validation, the automatic place and route
software configures the gate array to the engineer's design.
Through the use of the Timer, an engineer can check circuit timing
for the place and route. Once the design is optimized, the Activator
2 Programmer programs the proper antifuses to configure the
FPGA. The Activator 2 can program up to 4 devices simultaneously
in approximately one-half the time of the Activator 1 Programmer.
Modular approach allows for different packages to be programmed
by switching programming modules. Lastly, the Actionprobe
diagnostics hardware and software provides 100% real time
observability of internal nodes while the FPGA is running in the
target system.

• Viewlogic Workview 6000, Version 4.1
• Sun OS 4.0.3 or 4.1

Hardware Requirements
• Sun CAE Workstation

Options
ALES Logic Optimizer
ALS-144: Actel Logic Optimizer (ALES 1) for Viewlogic on Sun
allows designers to combine schematics with PAL equations
(pALASM2, ABEL, CUPL). The synthesized logic can be
simulated and integrated into a hierarchical design with emphasis
on optimizing either area or delay.
ALS-144S: Annual Support Fee, per system. Order with ALS-144.

Synthesis

For users who do not need all of these capabilities, versions of the
development system are offered without all of the features of the
complete system. The hardware and software can be upgraded
later as the user's needs change.

ALS-SYN-S4: Actel's technology libraries for the Synopsis logic
synthesis environment. Allows designers to capture Actel designs
by entering VHDUHDL format source files in Synopsys' design
compiler. The design compiler outputs an ED IF format netlist
which is read by the Actel supplied EDIF reader in the Actel ALS
design environment. The remaining design validation, placement
and routing, and programming steps are completed in the ALS
environment.

Software Components

Activator 2 Programming Modules

ACT 1 / ACT 2 FPGA Design System for Sun:

ALS-280:
ALS-281:
ALS-282:
ALS-283:
ALS-284:
ALS-285:
ALS-286:

• Macro Library
• Automatic Placement and Routing
• Timing Analysis
• Design Verification and In-Circuit Probe Software

©

1992 Actei Corporation

April 1992

100 QFP (ACT 1)
44PLCC
68PLCC
84PLCC
84PGA
84QFP
132PGA

ALS-287:
ALS-288:
ALS-289:
ALS-290:
ALS-292:
ALS-293:
ALS-294:

176PGA
84 PLCC (ACT 2)
100 PGA (ACT 2)
100QFP (ACT 2)
144QFP
160QFP
172QFP

2-11

I

ALS System Selector Table
ACTEL System
Part Number

ACT 1 FPGA
Design Software

ACT 2 FPGA
Design Software

Activator 1
Programmer

Activator 2
Programmer

Actionprobe
Diagnostics

ALS-055

Included

Optional

Optional

Optional

Optional

ALS-250

Included

Included

Not Required

Included

Included

ALS-253

Included

Included

Not Required

Included

Optional

ALS-255

Included

Included

Optional

Optional

Optional

Software and Hardware upgrades are available for Actel systems. Please contact your local sales representative for details and pricing.

2-12

Activator™ 2
Programmer/Tester/Debugger

Product
Brief

Features

The unit supports different CAE platforms using SCSI connectors.

• Supports ACT™ 1 and ACT 2 Device Families
• Interfaces to 386™ PC, Sun™ and ApoIIoTM Workstations
using a SCSI Bus

The Activator 2 may operate with four different adapter modules
inserted or with three of the sockets as slaves to the first, permitting
simultaneous programming of four identical devices. The
Activator 2 then addresses anyone of the sockets for programming.

• Runs Adapter Modules for Each Package/Family
Combination

Activator 2 Base Unit

• Up to Two Times Faster Than Activator™ 1 for ACT 1
Programming
• Supports Functional Verification with Actionprobe ™
Diagnostic Pod

The base unit contains the control board and the analog board.
The LED display on the top of the programmer shows when the
unit receives power. Four adapter ports located on the top of the
base unit accept the different adapter modules for each device type.
The adapter ports are identical, allowing interchangeability of
modules. SCSI connectors are located on the back of the unit.

• Simultaneously Programs a Single Pattern in Up To Four
Identical Devices
• Includes In-Circuit Probing of Up To Four Devices
Simultaneously

The Adapter Module

Product Description
Activator 2 is Actel's state-of-the-art desktop programmer. It
utilizes ActeI's Action Logic™ System (ALS) software and
PLICE™ antifuse technology to program custom-engineered
devices from ActeI's ACT 1 and ACT 2 device families. SCSI
connectors, shipped with the unit, provide a convenient connection
for 386 PC, Sun, and Apollo workstation support. Customized
adapter modules for each device type permit easy interchange of
programmable devices. Programming, Test, and Debug execute up
to two times faster than on the Activator 1; users can program up to
four devices at one time. The accompanying diagnostic pod and
ALS debug software support observation of all internal signals.

The adapter modules customize pin configurations for each device;
the user need only switch adapter modules to program another
device. All four ports may be used simultaneously when
programming identical devices. The adapter modules are compact
and sturdy. Any module may be used on any available port.

The Diagnostic Pod
The diagnostic pod supports ALS diagnostics and connects to the
programmer via cable. The Activator permits the user to view any
internal circuit activity through ActeI's on-chip diagnostic ports.
Up to four pods may be used simultaneously. A six-foot cord
connects the pod to the base unit and provides debugging
flexibility.

The unit is software-driven, providing flexibility of application and
a built-in barrier to obsolescence. Independently powered, the unit
provides desktop device programming, functional testing, and
in-circuit debugging.

©

1992 Actel Corporation

April 1992

2 13

I

2-14

Using Actionprobe ™
Diagnostic Tools

Applications
Note

Introduction

In-Circuit Probing

Actel's probe pin circuitry permits external monitoring of ACT™ 1
and ACT™ 2 device internal signals after device programming.
This unique diagnostic feature allows 100 percent observability of a
device. Observability reduces the time required for design
verification and test vector generation; it also facilitates system
troubleshooting. One hundred percent observability of all internal
device signals is unique to Actel field programmable gate arrays;
this feature is not available in conventional masked gate arrays or
programmable logic devices.

Changing the signal nodes is done simply by changing node names
with the Debugger software. The newly assigned signals are
connected automatically to the probe pins. Internal signals up to 10
MHz can be monitored externally. The internal signal passes
through an inverting buffer before reaching the probe pin.

Two dedicated probe pins, PRA and PRB, provide this
observability on ACT family devices. Actel's Actionprobe™
software and Actionprobe diagnostics hardware permit the
connection of any two signal nodes on the device to the probe pins.
Signal node assignments may be changed freely under software
control.

Setup
The Activator™1 and the Activator 2 programmer each have their
own Actionprobe hardware.
Actionprobe 1 hardware consists of a tower probe with a footprint
of the selected package. A socket on top of the tower probe holds
the programmed ACT device in place. The Actionprobe 1 unit,
with a programmed ACT device is then plugged directly into a
system board.
The Actionprobe hardware for the Activator 2 programmer is a
diagnostic pod that connects to the programmer via cable. The pod
is connected to dedicated test points in the target system using
several "flying lead" connections. The Activator 2 programmer
supports up to four Actionprobe diagnostic pods.
In both cases the device is verified and debugged in the target board
as it receives real-time stimuli from the system.
The Activator Programmer drives the control signals SDI, DCLK,
MODE, and GND via a flat ribbon cable. The MODE pin
determines whether the device is in debug mode. SDI receives the
serial addresses of the internal nodes from the Activator bus board.
DCLK clocks the serial address into the device. When the device is
being debugged in-circuit, SDI, DCLK, and MODE are
terminated to ground through a > 10 kO resistor. Probe pins may
be connected directly to a logic analyzer or oscilloscope.

©

1992 Actel Corporation

The "ICP" (In-Circuit Probing) command connects the probe pins
to internal nodes. The syntax is :
ICP node_1 node_2

where "node_I" (node name) is connected electrically to PRA, and
"node_2" is connected electrically to PRB.

Probe Calibration
The probe circuitry does not introduce any additional loading to
the design, so the AC characteristic of the observed internal nodes
remains unchanged. And, because probe propagation delay is
independent of layout, probe delay remains unchanged for all
points in the device.
The skew of the probe pins can be measured, then used to calibrate
for accurate measurement of propagation delay. When both probe
pins are assigned to the same point on the device, the delay
difference measured is the skew of the probe pins. This skew is
subtracted from subsequent delay measurements in the circuit. In
Figure la, for example, both PRA and PRB are connected
electrically to node NetO. The delay difference is the skew,
calculated as tSK = tpRA - tpRB. Using the Debugger software, the
slower probe (PRA) is assigned to node Net3. Figure 1b shows this
configuration. In this example, actual propagation delay is the
measured delay time between the output of GO and the output of
G3, minus the probe skew time. Actual delay is calculated as:
tpD

=

tpRA - tpRB - tSK.

Note: Due to the propagation delay difference between rising and
falling signals, both probe pin signals must be either rising or
falling when they are used to calibrate for delay
measurements.

Pin Assignment for Dedicated I/O Pins
During device verification, dedicated pins SDI, DCLK, PRA, and
PRB are assigned as special I/O pins. These pins should be
assigned as non-critical so that the design is functional without
them. After device verification, these pins can be assigned as
regular I/Os by programming the security fuses. This disables the
probe pins to prevent unauthorized device probing.

April 1992

2-15

I

G3

Figure 1a. Measuring Skew of Probe Pins

2-16

G3

PRA

PRA

PRB

PRB

Figure 1b. Calibrating for Accurate Propagation Delay
Measurement

Using the Actel Debugger
as a Functional Tester

combination of the two. Command files and test vector files are
created with an ASCII text editor, then loaded into the Debugger.
User-defined macros may be created in a command file, then
executed in the Debugger.

Introduction
Actel's Activator™ programming and diagnostics unit, together
with Actel's Debugger software, provide powerful tools to
functionally test an ACT™ device. Device debugging begins after
design configuration and device programming. Debugging is
performed with the device inserted in the Activator unit. The user
accesses Debugger software from the Action Logic™ System
(ALS) main menu.

This applications note shows Debugger commands for a sample
design. The sample design is Actel's TT269 (TTL 74269), an
eight-bit binary loadable up/down counter with count enable.
Figure 1 shows the sample design; Table 1 shows the truth table for
the part. PO through P7 are parallel load inputs; 00 through 07 are
counter outputs; CLK is the counter clock; UD is the up/down
count selector. Internal nodes (nets) should be labeled during
design capture for easy reference during debugging.

Debugger functional test allows the user to observe any internal
node of the device. The user defines the device inputs with
Debugger menu commands, with a command file, or with any

UD-I----1

Applications
Note

UO
U13

PO-I----!
P1-1----1
P2-1----1
P3-1--~

P4-1----!
P5-1----!
P6-1----!
P7-1----1

U1
U2
U3
U4
U5
U6
U7
U8

ClK-I----!

PO

UD

00

P1

01

P2

02

P3

03

P4

04

P5

TT269

05

P6

06

P7

07

ClK

TC

00
01
02
03
04
05
06
07

TC

OOUTO
OOUT1

I

OOUT2
OOUT3
OOUT4
OOUT5
OOUT6
OOUT7

TCOUT

CEP-I--~

CET-I---~

PE-I----!

PE

U12

Figure 1. 1T269

©

1992 Actel Corporation

2-17

Assigning Test Vectors

Table 1. TT269 Truth Table
Inputs

Outputs

PE

CEP

CET

UD

a
a

x
x

x
x
X

a
a

1

X

a

X

X

a
a

P[7:0]

CLK

x

a

X
X

FF
X

X

X

t
t
t
t
t
t

0[7:0]

TC

a

1

FF

a

Hold
Hold

The default input radix for all test vectors is decimal. To specify a
binary, hex, or octal radix, add a ~b, Oh, or 00 prefIx, respectively, to
the vector (e.g., OblOlO or Oh7e). Outputs are in binary format. To
interactively defIne input test vectors, use the Debugger menu.
Alternatively, use input command files to define test vectors. To
view outputs and internal nodes, print them to the PC screen
display or to an output file.

Increment
Decrement

....-_ _ _ _ _,.-_ _ _ _ _ Action Logic System _ _ _ _ _ _ _ _ _ _ _--,
~D_e_b_u~g~g~e_r_____4L INPUTl INPUT2 INPUT3 INPUT4 INPUT8 CLOCKIN

Low

H INPUT5 INPUT6 INPUT7
TABADD INPUT2 INPUT5 CLOCKIN _____
TABADD OUTPUTl OUTPUT2 OUTPUT3
~

High

STEP

Vector
Assign

Hi-Z
FAssign
Print
FPrint
Step
Setup
View

Help

L

H INPUT2

STEP

_--------=-- Revise input stimulus

STEP
PRINT --.----_
.....
_ _ _ _ _ _ __
INPUT2=0
INPUT5=l
CLOCKIN=O

Print values of signals
in tablist to pc screen

OUTPUT 3 =0

Design:
sample
Figure 2. Typical Debug Command Sequence

2-18

of signals
to obseNe

Apply stimulus;
allow time for
response

STEP

OUTPUTl=l
OUTPUT2=l
Exit

Set up list

Using the Actel Debugger as a Functional Tester

Defining User Macros

The sample macro in part A of Figure 3, c lkl0, provides 10 clock
pulses to the pin CLK and prints the value of internal vector Q to a
specified output file after each clock pulse. The outfile
command specifies the output file.

You may save time by creating user-defined macros for the
Debugger. These macros may contain a series of basic Debug
commands or may nest any combination of basic commands and
user-defined macros.

define (clkl0)

Part B of Figure 3 shows a nested macro, clkl00, that executes
the c 1 kl 0 macro 10 times, providing 100 clocks to the CLK pin.

(repeat 10 (1 CLK)

define (clkl00)

(step)

(h CLK)

(step)

(fprint Q»

(repeat 10 (clklO»

Figure 3. Sample Command Macros

Creating a Command File (TT269. cmd)
The command file (see Figure 4) applies test vectors to the TT2 6 9
counter. It redirects results to an output file, TT269. out, and
compares the output vector Q of the counter to an existing results
file, TT269 . cmp. The following notes correspond to each line in
the command file.
Lines 1 and 2: The vec tor command defines eight parallel load
input bits as vector P and counter output as vector Q.
Line 3: The tabadd command defines the internal or external
nodes to be displayed or printed when the print or fprint
command is executed.
Lines 4, 5, and 6: The infile, outfile, and compfile
commands define input and output files. The inf i Ie command
opens a file containing input test vectors. The ou t f i 1 e command
contains the output results. The compfile command contains
the data to be compared against the current device status. Use the
full path name of the file, and enclose it in question marks.

Line 7: The define commands create user-defined macros. In
this example, the clkl0 macro provides 10 clock pulses to the
CLKinput, fprint prints all nodes in the tabaddcommand toa
file defined by outfile, and fcomp compares the status of
vector Q to the file specified by compfile.
Lines 8, 9, and 10: Defines three user macros: up, down, and
load.

Loading a Command File
The loadfile command loads a defined command file into
the Debugger. Select setup I loadfile from the Debugger
menu, then enter the full path name of the command file. For
example:
/designs/TT269/TT269.cmd

Executing User-Defined Macros
To execute any previously defined macro, type the macro at the
command line while in the Debugger.

Line
1

(vector P PO PI P2 P3 P4 P5 P6 P7)

2

(vector Q QO Ql Q2 Q3 Q4 Q5 Q6 Q7)

3

(tabadd PE CEP CET UD P CLK Q TC)

4

(infile "/designs/tt269/tt269.pat")

5

(outfile "/designs/tt269/tt269.out")

6

(compfile l/designs/tt269/tt269.cmp")

7

(define (clkl0)

8

(define (up)

(repeat 10 (1 CLK) (step)(h CLK) (step) (fprint) (fcomp Q»)

(1 CEP CET) (h PE UD) (step) (clklO»

9

(define (down)

(h PE)(l CEP CET UD) (step) (clklO»

10

(define (load)

(1 PE CLK) (step) (fassign P)(h CLK) (step»
Figure 4. Debug Command File (TT269. crod)

2-19

I

Running the Sample Command File

Input Pattern File (TT269. pat)

In the following example, we will assign input test vectors from an
input pattern file named TT269. pat and will write output
results to a file named TT269. out. The command file
(TT269 . cmd) compares the counter's output vector Q to an
existing results file (TT269. cmp.)

ObOOOOOOOO
Ob10000000
Ob01000000
Ob11000000

Output Results File (TT269. out)
S
T
E
P

00005:
00007:
00009:
00011:
00013:
00015:
00017:
00019:
00021:
00023:
00028:
00030:
00032:
00034:
00036:
00038:
00040:
00042:
00044:
00046:
00051:
00053:
00055:
00057:
00059:
00061:
00063:
00065:
00067:
00069:
00074:
00076:
00078:
00080:
00082:
00084:
00086:
00088:
00090:
00092:

2 20

Output Compare File (TT269. cmp)

pee u

P C

Q T

E E E D
P T

L
K

C

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0

00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
10000000
10000000
10000000
10000000
10000000
10000000
10000000
10000000
10000000
10000000
01000000
01000000
01000000
01000000
01000000
01000000
01000000
01000000
01000000
01000000
11000000
11000000
11000000
11000000
11000000
11000000
11000000
11000000
11000000
11000000

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

10000000
01000000
11000000
00100000
10100000
01100000
11100000
00010000
10010000
01010000
00000000
11111111
01111111
10111111
00111111
11011111
01011111
10011111
00011111
11101111
11000000
00100000
10100000
01100000
11100000
00010000
10010000
01010000
11010000
00110000
01000000
10000000
00000000
11111111
01111111
10111111

0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
001~1111 0
11011111 0
01011111 0
10011111 0

Ob10000000
Ob01000000
Ob11000000
Ob00100000
Ob10100000
Ob01100000
Ob11100000
Ob00010000
Ob10010000
Ob01010000
ObOOOOOOOO
Ob11111111
Ob01111111
Ob10111111
Ob00111111
Ob11011111
Ob01011111
Ob10011111
Ob00011111
Ob11101111
Ob11000000
Ob00100000
Ob10100000
Ob01100000
Ob11100000
Ob00010000
Ob10010000
Ob01010000
Ob11010000
Ob00110000
Ob01000000
Ob10000000
ObOOOOOOOO
Ob11111111
Ob01111111
Ob10111111
Ob00111111
Ob11011111
Ob01011111
Ob10011111

Test and Reliability Reports

ACT Family Reliability Report ..............................................................................

3-1

Testing and Programming the A 1010/A1020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3-17

Acr

By Steve Chiang
and
Ken Hayes

M

Family
Reliability Report

AlOlO/AlO20 are 1200- and 2000-gate (respectively) field
programmable gate arrays (FPGAs). The programming element is
an Actel-invented PUCE ™ (Programmable Low-Impedance
Circuit Element) antifuse. An antifuse is a normally open device in
which an electrical connection is established by the application of a
programming voltage. Although the AlOlO/A 1020 are one-time
programmable devices, their unique architecture includes
complete functional testability.
Actel currently manufactures two versions of each product. The
A1010/A1020 device is processed using 2 pm design rules while the
A101ONA1020A is a 20% linear shrink which uses 1.2 pm design
rules. Both the full sized and shrink products are manufactured
using the same wafer fab lines and process flows. The technology
used is a standard double metal, twin well, CMOS process in which
three additional masking steps have been added to implement the
PUCE antifuse. A description of the main process parameters is
shown in Table 1. Because the A101O/A1020 are manufactured
with a conventional CMOS process, normal CMOS failure modes
will be observed. However, the addition of the antifuse adds
another structure which could affect the device's reliability.
Actel has completed numerous studies in order to quantify the
reliability of the antifuse. These studies lead to the conclusion that
Table 1.

the time to failure of the antifuse is substantially more than 40 years
under normal operating conditions and that the combined
contribution of all antifuses to the gate array product's hard failure
rate is less than 10 FITs (Failures-in-Time or 0.001% failures per
1000 hours).

The PLiCE Antifuse
The anti fuse is a vertical, two-terminal structure. It consists of a
polysilicon layer on top, N + doped silicon on the bottom, and an
ONO (oxide-nitride-oxide) dielectric layer in between. A Scanning
Electron Microscope (SEM) cross-section of the anti fuse is shown
in Figure 1. On the A10I0/A 1020 the size of the anti fuse is 3.2 pm 2
while it is 1.4 pm 2 on the A101ONA1020A. This small size, along
with a low programmed on-resistance, typically 500 Ohms, makes
the PUCE antifuse a very attractive alternative to EPROM,
EEPROM, or RAM for use as a programming element in a large
programmable gate array. In the unprogrammed state, the
resistance of the antifuse is in excess of 100 MOhms. The A10I0
and A1020 contain 112,000 and 186,000 anti fuses respectively.
However, typical applications utilizing 85% of the available gates
require programming only 2% to 3% of the available antifuses.

A1010/A1020 Process Description

Process Type: CMOS, double metal, dual polysilicon, dual well, EPI wafer
Dimensions

N+
P+
Cell Poly-Si
Gate POly-Si
Metal I
Metal II
Contact
Via
Thickness
Normal Gate Oxide
High Voltage Gate Oxide
Cell Poly-Si
Gate Poly-Si
Metal I
Metal II
Passivation

I

1.2 pm Process

2.0 pm Process
Width ()Jm)

Space ()Jm)

Width ()Jrn)

Space ()Jm)

4.0
4.0
2.0
1.6
4.0
4.S
1.S x 1.S
2.0 x 2.0

2.0
2.0
3.6
2.4
2.0
2.2
2.0
2.0

3.2
3.2
2.1
1.6
3.2
3.S
1.2 x 1.2
1.3 x 1.3

1.6
1.6
2.4
1.6
1.6
1.S
1.S
1.9

2.0 pm Process
25nm
40nm
450nm
450nm
900nm
1000nm
1100 nm

1.2 pm Process
25nm
40nm
450nm
450nm
900nm
1000 nm
1100 nm

Compositions
Metal I
Metal II
Passivation

©

1992 Actel Corporation

AI - Si (1 %) - Cu (0.5%)
AI - Si (1 %) - Cu (0.5%)
3000 nm Si0 2 , SOO nm SiN

April 1992

AI - Si (1 %) - Cu (0.5%)
AI - Si (1 %) - Cu (0.5%)
3000 nm Si02 , SOO nm SiN

3-1

Metal 2

Metal 1

BPSG

Polysilicon
ONO Antifuse
N+ Diffusion

Figure 1. Antifuse SEM Cross-Section

The Unprogrammed Antifuse
In order to evaluate antifuse reliability, Actel has developed
models and collected data for both unprogrammed and
programmed antifuses 1,2. We'll consider the unprogrammed
antifuse first. Since the antifuse is a dielectric sandwiched between
polysilicon and silicon, the model for its reliability, in the
unprogrammed condition, is the same as that used to evaluate
reliability ofMOS transistor gate oxides3 • The parameter we wish
to evaluate is the time to breakdown (tbd) of the dielectric. This
parameter is a function of the electric field across the dielectric as
well as temperature and has the following relationship 3.
tbd = to * exp(G/E)

(1)

where tbd is the time to breakdown in seconds, to is a constant in
seconds, E is the electric field in Mv/cm, and G is the field
acceleration factor in Mv/cm (G is temperature dependent and will
be discussed later).
By taking the log of both sides of equation 1 we have:
In (tbd )

= G * (l/E) + In(to)

(2)

From experimental data, we can plot the log of the time to
breakdown of the antifuse at various temperatures versus the

3-2

reciprocal of the electric field across it and derive G from the slope
and to from the Y intercept. Actel has done this on single antifuses,
large antifuse capacitors, test arrays of 28,000 antifuses, and actual
AlOlO/A 1020 products. These antifuse areas range from 3.2 pm 2 to
0.35 mm 2 • Figure 2 shows plots of data collected on these different
sized antifuses.
There is some discussion in the literature regarding whether time
to breakdown depends on E or liE. To verify the validity of
equation 2, we conducted the following experiment. Large 200 pm
by 200 pm (0.04 mm 2) area capacitors were packaged and then
stressed at more than eleven different voltages. Capacitors were
chosen from two different wafer runs with thicknesses ranging
from a low of B.O nm to a high of 9.5 nm. A total of 642 capacitors
were used in the experiment. The test splits and sample sizes are
summarized in Table 2. The distribution of time to breakdown of
the dielectric at each voltage is shown in Figure 3. In Figure 4, we
plot the median of the cumulative failure percentage rates (tso)
from Figure 3 versus liE. In Figure 5 the median failure percentage
is plotted versus E. By comparing the two figures, the validity of the
liE model is clearly established. A more detailed statistical
verification of the liE model for the ONO antifuse is given in
Reference 2.

ACT Family Reliability Report

Table 2.

Field Accelerated Test Data for Two Lots with Thickness Ranging from 8 nm to 9.5 nm.
(The test was done on 0.04 mm2 area capacitor.)
Lot B

Lot A
E-Field
(MV/cm)

#of
Capacitors

tso
(sec)

Voltage

M

Tox
(nm)

M

Tox
(nm)

13.5

8.3

16.2

22

4.2 e-3

14.0

8.7

12.5

8.3

15.1

22

3.7 e-2

13.0

8.7

12.0

8.3

14.4

22

1.5 e-1

12.5

11.5

8.3

13.8

22

8.6 e-1

11.0

8.4

13.1

22

4.7 eO

Voltage

E-Field
(MV/cm)

#of
Capacitors

tso
(sec)

15.9

25

9.8 e-3

14.9

25

5.0 e-2

8.7

14.3

25

2.4 e-1

12.0

8.7

13.7

25

1.3 eO

11.4

8.7

13.1

25

9.0 eO

10.5

8.4

12.5

9

5.8e1

11.2

8.7

12.5

45

8.0 e1

10.0

8.3

12.0

6

3.2e2

10.8

9.0

12.0

45

3.52e2

6
36

2.5e3

10.2

45

2.88 e3

9.7

9.0
9.0

11.3

2.5e4

10.8

45

2.07e4

9.5

8.3

11.4

9.0

8.3

10.7

8.5

8.3

10.2

15

2.3e5

9.0

8.7

10.3

32

3.35 e5

8.0

8.3

9.6

59
241
642

1.5 e6

9.0

9.3

9.7

32

2.22e6

Subtotal of tested capacitors:
Total of tested capacitors:

401

TDD8 (sec)
1.0E+10--------------------------------------------------~

1.0E+09
1.0E+08

I

Single Antifuse: 3.2um2

1.0E+07

Capacitor: O.04mm2

1.0E+06

Product: 0.3Smm2

1.0E+OS
1.0E+04
1.0E+,()3
1.0E+02

Single Antifuse

1.0E+0 1
1.0E+00
1.0E-01
1.0E-02
1.0E-03

1.0E-04k-----~----~--~~--~~--~----~~--~----~

4

S

6

789

10

11

12

100/E (cm/MV)

Figure 2. Field Accelerated Test

3-3

TDDB(sec)
1.0E+08-------------------------------------------M--V-/C-m~

1.0E+07

l::,.

1.0E+06

o

9.7
10.3

1.0E+05
1.0E+04

x

1.0E+03

o

00 0

1.0E+02

11.4
12.5

*

13.0

1.0E+01
1.0E+00

+

14.0

1.0E-01

...... ....... . .

1.0E-02

16.0

1.0E-03
1.0E-04 0 . 1

12

5

10

20 30405060 70 80

90

95

9899

99.9

Cumulative Failure (%)
Figure 3. TDDB Distribution

TDDB (sec)
1.0E+08~----------------------------------------------

+

1.0E+07

Lot A

o

Lot B

1.0E+06
1.0E+05
1.0E+04
1.0E+03
1.0E+02
1.0E+01
1.0E+00
1.0E-01
1.0E-02
1.0E-03L-----~-----L----~L-----~-----L----~----~

5

6

7

8

9

100/E (cm/MV)
Figure 4. ONO Reliability (1/E Model)

3-4

10

11

12

ACT Family Reliability Report

TDDB (sec)
1.0E+08~------------------------------------------------'

+

1.0E+07

Lot A

o

Lot B

1.0E+06
1.0E+05
1.0E+04
1.0E+03
1.0E+02
1.0E+O 1
1.0E+OO
1.0E-01
1.0E-02
1.0E-03L----L----~--~----~----~--~----~----~--~

9

8

10

11

12

13

14

15

16

17

E (MV fem)
Figure 5. ONO Reliability (E Model)

In order to quantify the temperature dependence of the time to
breakdown, we use the Arrhenius equation to determine the
semiconductor failure rate of a given process (failure mode) over
temperature:
R

= Ro * exp (EalkT)

(3)

where R is the failure rate, Ro is a constant for a particular process,
T is the absolute temperature in degrees Kelvin, k is Boltzmann's
constant (8.62 X 10-5 e V / OK) and Ea is the activation energy for the
process in electron volts. To determine the acceleration factor for a
given failure mode at temperature T z as compared with
temperature T 1 we use equation 3 to derive:
A(Th T z) = exp [(EaIk) * {(l/T l )

-

(lITz)}]

(4)

where A is the acceleration factor.
In Figure 6 we plot t50 at different temperatures and electric fields.
This plot shows that time to breakdown is dependent on
temperature as well as electric field. For a given time to breakdown
of a dielectric, the expression,
Ea = k * dln(tbd)/d(lIT)

(5)

gives us the activation energy2. The slope in Figure 6 represents the
activation energy Ea. Ea also shows a linear correlation with liE as
shown in Figure 7. The field acceleration factor, G, is also
temperature dependent, i.e.
G(T)

= G(298) * [1

+ 8/k

* {liT -

lI298}]

(6)

where G(298) is the field acceleration factor at room temperature
(25°C = 298°K) and 8 (in eV) characterizes the temperature
dependence of G.
By combining equations 1, 5, and 6, Ea can be related to G(T) by:
Ea

= G(298) * 8/E -

Eb

(7)

where 8 and Eb are treated as fitting parameters between Ea and G.
From the data shown in Figures 3, 4, 6, and 7 we can obtain values of
G(298), 8, E b, and Ea regardless of antifuse area. Typical values of
G(298), 8, E b, and Ea at 5.5V are 480MV/cm, 0.014eV, 0.43 eV,and
1 X 10- 16• By combining equations 1, 6, and 7, we obtain an overall
equation for the time to breakdown for a given temperature and E
field:
tbd = to * exp{(G(298)/E) [l+(8/k) * (lIT-lI298)] - (EJk) *
(1/T-lI298)}
(8)
By applying the values for the constants as defined above, the time
to breakdown for the antifuse dielectric can be derived for a given
temperature and electric field. In Table 3, we have used equation 8
to solve for the acceleration factors associated with powering up a
device at high voltage and/or temperature and comparing the
failure rate with more typical voltages or temperatures. We can see
the effect of temperature by comparing 125°C at 5.5 V with 55°C
at 5.5 V in which the Actel model (equation 8) gives us an
acceleration factor of 55.3, or 6.3 equivalent years for a 1000 hour

3-5

II

The second method of determining product reliability was to look
at production wafer sort results. As was mentioned earlier, all
antifuses receive a high voltage stress at wafer sort to screen out
infant mortality failures. Specifically, all antifuses receive the
equivalent of two, 10 V stresses for one second each. The first stress
is to screen out clearly defective antifuses. The second stress is to
catch weaker antifuses which could cause product programming
yield problems or infant mortality failures. Actual failure rates
observed on the AlOlO over ten runs for these two stresses (FS-1
and FS-2) demonstrate average yield loss at the second stress
screen ofless than 0.3%. By extrapolating this yield loss to a normal
5.5 V operating voltage, we thus conclude that the contribution of
the antifuse to the overall product's lifetime is less than 10 FITs.

burn-in at 125 °C. Note that this acceleration factor of 55.3 is close
to the value of 41.8 derived from the Arrhenius equation (equation
4) using an activatjon energy of 0.6 eV and the same temperatures.
We use 0.6 eV (and 0.9 eV) as a general semiconductor failure
mode activation energy when calculating failure rates from high
temperature operating life (HTOL) later in this report.
We can also see from Table 3 that a small change in voltage is a
much more effective reliability screen than is a change in
temperllture. For example, if we compare 25 °C at 5.75 V to 25 °c at
5.25 V we see that just a half volt change yields an acceleration
factor of 1092.6, or 124.7 equivalent years per 1000 hours at 5.75 V.
This strong dependence on voltage allows Actel to screen out
antifuse infant mortality failures during normal wafer sort testing
simply by performing a special test in which a higher than normal
voltage is applied across all antifuses. Because antifuse infant
mort~lity failures can be detected and effectively screened,
AlOlO/A1020 devices have as high a level of reliability as standard
CMOS processed products.

The third technique of determining the product's antifuse failure
rate is by doing an accelerated burn-in of A1010/A 1020 products.
The acceleration is accomplished by using both higher voltage
(5.75 V to 6.0 V) and high temperature (125°C to 150°C). Units are
programmed to a specific design and exercised in a manner similar
to what may occur in a real application. For a detailed description
of the test and the results, see the High Temperature Operating
Life section later in this report. Here, too, the conclusion is that the
anti fuse contributes less than 10 FITs to the product's overall
failure rate and it is thus an insignificant factor in product lifetime
of 40 years at 5.5 V and 125 0c.

In order to establish that the anti fuse contributes less than 10 FITs
(at 5.5 V, 125°C) to the overall product reliability, Actel has
calculated the product failure rates due to the antifuse using three
different techniques. In the first case, we evaluated the tbd
distribution of 125 AlOlO units in which the anti fuses received an
11 V stress. Using Ea = 0.9 eV and extrapolating to 5.5 V, we find
that the 1% antifuse failure lifetime at 5.5 V is well over 40 years
and less than 10 FITs.

TDDB (sec)

125C

85C

55C

*

0

25C

1.00E+07
1.00E+06
1.00E+05

9.7

1.00E+04

10.2

1.00E+03
1.00E+02
1.00E+01

10.8

-r--=

11.3

~

11.8

[J""

0

L
6:

6

12.3 L

1.00E+00
1.00E-01

14.3

1.00E-02
2.2

2.4

z
2.6

2.8

A:

Z

Z

3

3.2

1OOO/T (1/Kelvin)
Figure 6. Dependence of E-Field Acceleration on Temperature

3-6

3.4

3.6

ACT Family Reliability Report

Activation Energy (ev)
0.9~~--~~--~~--~~--~~--~~--~~--~~--~~

0.8
0.7
0.6
0.5~·····'·······'········'··············'············

...

0.4

0.3
0.2~·

;......... ; ...... ;......... ;..................;.......

··,······;·I~~························:········:······..

:

...... : ....... , . . .

j

0.1
O~~--~--~~--~~~--~~--~--~~--~--~--~~--~~

-0.1

r·····,······,······

,

....... , ' / " . , ...

c········.··········································,· . . . . . . • . . . . . , . .

,.......

, ....... j

-0.2
-0.3
-0.4

h/····;·········,·

_0.5L--L--~~--~--L--L--~~--~--L-~--~~--~--~~~

o

2

3

4

5

6

7

8

9

10

11

12 13 14 15 16

17

100/E (em/MV)
Figure 7. Activation Energy versus 1IE

Table 3.

to

=

Acceleration Factor vs. Operating Conditions (Unprogrammed Antifuse)

1 X 10- 16 sec., G

= 480 MY/cm, 8

= 0.014 eV, Eb

Acceleration
Factor

High

Typical

Fixed Voltage

125°C/5.5V
125°C/ 5.5 V

55°C I 5.5 V
90°C I 5.5 V

Fixed Temperature

25°C / 5.5 V
25°C/ 5.75 V
25°C / 5.75 V
25°C / 6.0 V
25°C/6.0 V

Varied Temperature and Voltage

Fixed 0.6 eV Activation Energy
Voltage - Independent

Model

I

= 0.43 eY.

TemperatureNoltage

Equivalent Years
for 1000 Hour
125°C Burn-In

55.3
6.1

6.3
0.7

25°CI 5.25 V
25°C/ 5.25 V
25°C/ 5.5 V
25°C I 5.25 V
25°CI 5.5 V

38.8
1092.6
28.2
23321
601.8

4.4
124.7
3.2
2662
68.7

125°C/ 5.5 V
125°C / 5.75 V
125°C / 5.75 V
125°C / 6.0 V
125°C/6.0V

55°C/ 5.25 V
55°C I 5.5 V
90°C I 5.5 V
55°C I 5.5 V
90°C I 5.5 V

1787.2
987.8
109.4
13865
1535.9

204.0
112.8
12.5
1583
175.3

150°CI 5.5 V
150°C I 5.5 V
125°CI 5.5 V
125°CI 5.5 V

55°C I 5.5
90°C I 5.5
55°C I 5.5
90°C I 5.5

117.6
15.2
41.8
5.4

13.4
1.7
4.8
0.6

V
V
V
V

3-7

The Programmed Antifuse

12

A Kelvin test structure as shown in Figure 8 was used to evaluate
reliability of a programmed antifuse. Here, a strip of polysilicon
crosses an N + diffusion. The antifuse is located at their
intersection. There are metal-to-poly contacts at nodes 1 and 3 as
well as metal-to-N + contacts at nodes 2 and 4. A four terminal
Kelvin structure is useful should a failure occur, because antifuse
opens can be separated from other problems (such as polysilicon or
contact opens) simply by checking for continuity on appropriate
pairs of nodes.

11

... -

Antifuse Accelerated Lifetest
250°C 5 mA Test

.- ,

10

I
::- ~
~ ~ "':-

rl

"",
~

I'

I
Q)

II

I

en

:§
c

c(

,,
I

en
en

I

~

0
c(
Q)

,

I

,

1
~

0

-- -

I

... l.l-

3

::p-.. "'.-....I - ~ p ~

I
I
J

,

-

N+

Diffusion

I-f-

0

I""
2

2448 72 96 120144168192216240264288312336360384408432456

GND

+V
po l y -

1

0

Figure 8. Antifuse Kelvin Structure

Test devices were stressed by forcing a constant 5 rnA current from
polysilicon to N + through the antifuse at 250°C, Note that this
stress is far greater than a programmed antifuse would see in a
device under normal operating conditions. Because the antifuse is
used to connect two networks together, there is usually no voltage
across it and hence no current passes through. A voltage will appear
across the antifuse only momentarily while a network switches
from low-to-high or high-to-Iow.
During the 5 rnA, 250°C stress, the voltage across the antifuse was
monitored. Figure 9 is a plot of the monitored voltage as a function
of stress time. A sudden increase in voltage indicates that an open
occurred. As can be seen from the figure, failures occurred at about
300 hours of stress. However, by probing on nodes 3 and 4 of the
Kelvin structure, we were able to measure continuity and
determine that the cause of failure was not the antifuse. The failed
units were then examined on an SEM, where the cause of failure
was revealed as metal-to-poly contact electromigration. This is a
well-known failure mode in CMOS, which has been determined to
have an activation energy of 0.9 eV. Using equation 4 we can predict
a lifetime under normal operating conditions in excess of 40 years
for this failure mode. The lifetime of the programmed antifuse is
even longer.

3-8

""

40

2

t:: 1'--

Elapsed Time (Hours)

Figure 9. Voltage Across Antifuse versus Stress Time

Ai 01 0/Ai 020/A 1280 Product Reliability
Product Reliability was evaluated on five Actel products; a 64K
PROM (PROM64), a 300-gate FPGA (1003), a 12oo-gate FPGA
(AlOlO/AlOI0A), a 2000-gate FPGA (A lO20/A 1020A), and an
8000-gate FPGA (A 1280). The PROM64 product uses the same
process and antifuse as the AlOlO/A1020. The 1003 is a test device
which is a smaller version of the AlOlO/AI020, and was used for
early characterization and qualification. As mentioned earlier, the
AlOlOA and A1020A are 20% linear die shrink versions of the
AlOlO and AlO20, respectively. The PROM64 units were packaged
in 24 pin side-brazed packages while the FPGA units were in 68 and
84 pin JLeC (ceramic J-Ieaded chip carriers), JQCC (ceramic
leaded chip carriers), and PLeC (plastic leaded chip carriers)
packages. Package characteristics for the AlOlO/AlO20 are shown
in Table 4.

High Temperature Operating Life (HTOL)
The intent of HTOL is to dynamically operate a device at high
temperature (usually 125°C or 150°C) and extrapolate the failure
rate to typical operating conditions. This test is defined by Military
Standard-883 in the Group C Quality Conformance Tests. The
Arrhenius relationship in equations 3 and 4 is used to do the
extrapolation. To use the Arrhenius equation, we need to know the
activation energy of the failure mode. Activation energies of
antifuse failure modes were discussed earlier. Table 5 gives the
Activation energies of general semiconductor failure modes.

ACT Family Reliability Report

Table 4.

A 10101A 1020 Packaging Description

PLCC
Sumitomo 6300H
Fused silicon 70% by weight
Copper
Solder, 300-800 micro inches ()Jin)
Silver Epoxy
UL-94, V-O
Gold, 1.3 mil diameter
Thermosonic

Molding Compound
Filler Material
Lead Frame Material
Lead Plating Composition
Die Attach Material
Flame Retardance
Bond Wire
Bond Attach Method
JQCC

Ceramic
Ceramic
Glass
Alloy 42 (40% Nickel, 60% Iron)
99% Aluminum, 1% Si, 1.25 mil diameter
Ultrasonic
Solder dip, 200 }lin. min.

Body Material
Lid Material
Sealant
Lead Frame Material
Bond Wire
Bond Attach Method
Lead Finish
Thermal Resistances (OC/Watt)
Package

44 PLCC

44 JQCC

68 PLCC

68 JQCC

84 PLCC

84 JQCC

15

8

13

8

12

8

52

38

45

35

44

34

Six different data patterns were programmed into the 64K PROMs
for HTOL testing: a diagonal of zeros (98% programmed); a
diagonal of ones (2% programmed); a topological checkerboard
pattern (50%); all zeros (100%); all ones (0%); and an incrementing
pattern (50%). During bum-in, all addresses are sequenced
through at a 1 MHz clock rate. The outputs are enabled and loaded
with a 100 ohm resistor to a 2 V supply. This results in an output
loading of equal to or greater than the specified limits of loh = -4
rnA and 101 = 16 rnA. In most cases, the PROMs were burned-in at
Vee = 5.5 V and at 125°C. However, voltage acceleration
experiments were also done at 7 V, 125 °C as well as 8 V, 25°C.
The PROM is useful for antifuse reliability studies for several
reasons. First of all, we can program anywhere from 0% to 100% of
the anti fuses although we program only 2-3% of the anti fuses for a
given design on the AlOlO/AlO20 device. Also, an antifuse failure
on the PROM is very noticeable, since the anti fuse is directly
addressed. A weak fuse would show an AC speed drift, and a failed
antifuse would read the wrong data.
For evaluating the 1003/A1010/AlO20/Al280, we programmed an
actual design application into most devices (some units were
burned-in unprogrammed) and performed a dynamic bum-in by
toggling the clock pins at a 1 MHz rate. The designs selected
utilized 85-97% of the available logic modules and 85-94% of the
lias. Outputs were loaded with 1.2 K ohm resistors to Vee which
results in greater than 4 rnA of sink current as each I/O toggled low.
Under these conditions, each A1010 typically draws about 100 rnA

84 PGA

84 CQFP

100 PQFP

8

8

20

35

38

65

during dynamic bum-in. Most of this current comes from the
output loading while about 5 rnA is from the device supply current.
The thermal resistance (junction to ambient) of the 68 and 84 pin
PLeC packages is about 45°C/Watt and for the JLeC packages itis
about 35°C/Watt. For a 125°C bum-in, this results in junction
temperatures of about 150°C for plastic packages and 145°C for
ceramic packages. Most bum-in was done at 5.75 V or 6.0 V (for
voltage acceleration of the anti fuse) and 125°C or 150°C.
Table 5.

CMOS Failure Mechanisms

Failure Mechanism

Activation Energy

Ionic Contamination

1.0 eV

Oxide Defects

0.3eV

Hot Carrier Trapping in Oxide
(Short Channels)

-0.06 eV

Silicon Defects

0.5eV

Aluminum-Silicon-Copper
Electromigration

0.6eV

Contact Electromigration
Electrolytic Corrosion

0.geV

0.54 eV

3-9

I

Some initial bum-in evaluation was also done on the first member
ofthe new ACT 2 family - the A 1280. This is an 8000-gate product
which is manufactured using the same processing technology as
used for the AlOlONAlO20A (1.2 pm).
As was mentioned earlier, some units are burned-in unprogrammed.

To accomplish this, we use a special bum-in circuit which allows us
to use the product's test features in order to serially shift in
commands to the chip during bum-in. All internal routing tracks
are toggled between V ss and V cc. When vertical tracks are at V cc,
horizontal tracks are held at Vss and vise versa. Thus all antifuses
which can connect vertical and horizontal tracks receive a full V cc
stress in both directions. Since vertical tracks connect to logic
module inputs and outputs, these too are toggled between Vss and
V cc. Finally, a command is sent to the chip to toggle some external
I/O pins between V ss and V cc. This special dynamic bum-in circuit
is the same that is used by Actel to screen unprogrammed product
to MIL-883C requirements. Since virtually all antifuses receive a
full Vee stress, this screen is much more effective at catching
unprogrammed antifuse infant mortality failures than is burning-in
programmed devices where only a fraction of the anti fuses are
stressed.
A summary of the HTOL data collected by Actel is shown in
Table 6. A failure is defined as any device which shows a functional
failure, exceeds datasheet DC limits, or exhibits any AC speed drift.
Among the parts tested, no speed drift, faster or slower, was
observed within the accuracy of the test set-up. Failure rates at
55°C, 70°C, and 90°C were extrapolated by using the Arrhenius
equation and general activation energies of 0.6 eV and 0.9 eY.
Poisson statistics were used to derive a calculated failure rate with a
60% confidence level. Use of Poisson statistics is valid for a failure
rate which is low and a failure mode which occurs randomly with
time. At 55°C, the calculated failure rate with a 60% confidence
level was found to be 36 FITs or 0.0036% failures per 1000 hours.
This number was derived from over 4.8 million device hours
(125°C) of data. There were six total failures. Only one occurred in
the first 80 hours of bum-in (1003 product). The others failed at
300,417,500 (x2), and 650 hours. Five of the six failures observed
were due to common CMOS failure mechanisms (gate oxide
failure, silicon defects, open via). Only one unit failed due to an
anti fuse failure. This unit was burned-in in the unprogrammed
state to stress all anti fuses. It was stressed at 6 V, 150°C. It passed at
168 hours and failed at 650 hours due to an anti fuse becoming
programmed. By passing at 168 hours, the unit received a total

3-10

stress well in excess of 100 years of operation at 5.5 V, 125°C (using
equation 8). With only one antifuse related failure in 4,830,000
device hours at 125°C, we use equation 8 to derive that this one
antifuse failure at 6 V is less than 10 FITs at 5.5 y.

Unbiased Steam Pressure Pot
This test is used to qualify products in plastic packages. Units are
placed in an autoclave (pressure pot) and exposed to a saturated
steam atmosphere at 121°C and 15 psi. Problems with bonding,
molding compounds, or wafer passivation can cause metal
corrosion to occur in this atmosphere. The existence of metal
corrosion is detected during a full electrical test of the device
following exposure to the autoclave environment.
A total of773 units from 17 wafer runs were evaluated. Read points
were taken at 96, 168, 240, and 336 hours. There were a total of five
failures (Table 7). All five failures were found to be due to bond
wires lifting off bond pads. These were due to assembly problems
which occurred only on our first lots of plastic units built. The
failures were caused by temperature and not by metal corrosion.
The assembly problems have been corrected, with no further
failures observed.

Biased Moisture Life Test (85/85)
In this test, the units are placed in a chamber at a temperature of
85°C and a relative humidity of 85%. A voltage of 5.5 V is applied
to every other device pin while other pins are grounded. 5.5 V is
applied to Vee while Vss is grounded. This test is effective at
detecting die related and plastic package related problems.
As shown in Table 8, a total of 481 units have been stressed. There

have been three failures. Two failures were due to lifted bond wires
and came from the same lot in which we saw failures in steam
pressure pot. The 1000 hour failure is nonfunctional due to an open
Metal I line.

Temperature Cycling
This test checks for package integrity by cycling units through
temperature extremes. Data was taken for cycles of 0 °C to 125°C,
-40°C to 125°C, and -65°C to 150°C. Both programmed and
unprogrammed units are placed on temperature cycle. As shown in
Table 9, of 1466 units tested to date, there have been no failures.

ACT Family Reliability Report

Table 6.

High Temperature Operating Life HTOL Test Summary
Device Hours
At 125°C

Eqiv Dev Hrs
(in millions)
At 55°C (0.6 eV)

Eqiv Dev Hrs
(In millions)
At 70°C (0.6 eV)

Product

Units

Wafer
Runs

PROM64
1003
A1010
A1010A
A1020
A1020A
A1280

295
238
703
479
334
909
80

4
3
10
11
5
13
3

618,000
360,000
1,170,000
681,000
216,000
1,710,000
80,000

1
0
3
0

71.5
3.4

5.9
19.3
11.3
3.6
28.3
1.3

3038

48

4,830,000

6

202.0

79.8

Totals

Failures

10.2

25.9
15.0
48.7
28.5

0

9.0

Overall FITs
Ambient Temp

Activation Energy (eV)

Observed

90°C

0.6

230

60% Confidence
281

70°C

0.6

75

92

55°C

0.6

30

36

90°C
70°C

0.9

0.9

80
15

98
18

55°C

0.9

4

5

High Temperature Operating Life
# Units

# Hours

# Fail

Temp (Oe)

Vce (Volts)

59
36
40
40
10
50
50
10

2000
2500
2000
2000
2000
2500
2500
2500

0
0
0
0
0
0
0
0

125
125
125
125
25
125
125
25

5.50
5.50
5.50
7.00
8.00
5.50
7.00
8.00

84JLCC
84JLCC
84 JLCC
84JLCC

25
32
159
22

2000
2000
500
1000

0
0
1
0

125
125
150
125

5.75
5.75
7.00
5.75

DG1042
DG1047
DG1073
DG1077

84JLCC
84JLCC
84JLCC
84 JLCC

3
2
10
15

1000
1000
2000
2000

0
0
0
0

125
125
125
125

5.75
5.75
5.75
5.75

JB13
JB13
JB13
JB14
JB22
JB42
JB44
JB46

84 PLCC
68 PLCC
84 JLCC
68 PLCC
68JLCC
68 PLCC
68 PLCC
68 PLCC
68 PLCC

32
126
64
100
50
100
47
40
49

2000
2000
2000
2000
2000
1000
1000
1000
1000

0
1
0
0
0
0
0
0
0

125
125
125
125
125
125
125
125
125

5.75
5.75
5.75
5.75
5.75
5.75
5.75
5.75
5.75

T124

68 PLCC

65

2000

0

125

5.75

Product

Run#

Package

64KPR
64KPR
64KPR
64KPR
64KPR
64KPR
64KPR
64KPR

DG1060
DG1064
JB13
JB13
JB13
JB14
JB14
JB14

24SB
24SB
24SB
24SB
24SB
24SB
24SB
24SB

1003
1003
1003
1003

1063
1065
1065
1067

A1010
A1010
A1010
A1010
A1010
A1010
A1010
A1010
A1010
A1010
A1010
A1010
A1010
A1010

~B14

II

3-11

~
Table 6.

High Temperature Operating Life HTOL Test Summary (continued)

High Temperature Operating Life
Product

Run#

Package

# Units

# Hours

# Fail

Temp (OC)

Vcc (Volts)

A1010A
A1010A

JG03
JG03

68 PLCC
68 PLCC

59
117

2000
1000

0
0

125
125

5.75
5.75

A1010A
A1010A
A1010A
A1010A
A1010A
A1010A
A1010A

TI24
TI29
TI31
TI32
TI33
Ti35
TI1104
TI1243
TI1263
TI1297

68
68
68
68
68
68
68

PLCC
PLCC
PLCC
PLCC
PLCC
PLCC
PLCC

74
53
26
9
19
15
107

2000
1000
2000
2000
2000
2000
1000

0
1
0
0
0
0
0

125
125
125
125
125
125
125

5.75
5.75
5.75
5.75
5.75
5.75
5.75

A1020

OG1133

84JLCC

29

2000

0

125

5.75

A1020
A1020
A1020
A1020
A1020
A1020

JB22
JB22
JB25
JB26
JE03
JB33

84 PLCC
84JLCC
84 PLCC
84 PLCC
84JQCC
84JLCC

16
32
16
32
104
105

1000
1000
1000
500
186
80

0
0
0
0
0
0

125
125
125
125
150
150

5.75
5.75
5.75
5.75
5.75
5.75

A1020A
A1020A
A1020A
A1020A
A1020A
A1020A
A1020A
A1020A
A1020A
A1020A
A1020A
A1020A
A1020A
A1020A
A1020A

JF01
JF01
JF02
JF02
JF04
JF04
JF14
JF14
JF37
JF37
JF39
JF39
JF42
JF42
JF67

84 JLCC
84 PLCC
84JLCC
84JLCC
84 PLCC
84 PLCC
84 PLCC
84 PLCC
84 PLCC
84 PLCC
84 PLCC
84 PLCC
68 PLCC
68 PLCC
84 PLCC

25
15
44
41
20
58
100
14
20
32
29
49
79
49

2000
2000
2000
2000
1000
500
417
417
300
300
300
300
1000
1000
500

0
0
0
0
0
0
0
1
1
0
0
0
0
1
0

125
125
125
125
125
125
150
150
150
150
150
150
150
150
125

5.75
5.75
5.75
5.75
5.75
5.75
6.00
6.00
6.00
6.00
6.00
6.00
6.00
6.00
5.75

A1020A

TI1130
TI1139
TI1210
T11800
TI1803

84 PLCC

223

1000

0

150

6.00

84 PLCC

34

1000

0

150

6.00

176 PGA

80

1000

0

125

5.75

A1020A
A1280

3-12

JG03
JG05
JG06

77

ACT Family Reliability Report

Table 7.

121°C, 15 psi Steam Pressure Pot (unbiased autoclave)
# Units

96 Hours

Number of Failures
240 Hours
168 Hours

336 Hours

Product

Run#

Package

A1010
A1010
A1010
A1010
A1010
A1010

JB13
JB13
JB14
JB22
JB27
JB28

84
68
68
68
68
68

PLCC
PLCC
PLCC
PLCC
PLCC
PLCC

34
71
71
50
50
42

0
1
0
0
0
1

3
0
0
0
0
0

0
0
0
0
0
0

A1010A
A1010A
A1010A

TI15
TI24
TI1104
TI1243
TI1263
TI1297

68 PLCC
68 PLCC
68 PLCC

77
129
77

0
0
0

0
0

0
0
0

A1020A

T11800
TI1859
TI2156

84 PLCC

77

0

A1020A
A1020A
A1020A

JF33
JF64
JF68

84 PLCC
84 PLCC
84 PLCC

30
30
35

0
0
0

0

0

0
0
0

0

0

Failure Analysis:
Three A 1010 JB13 failures at 168 hours due to lifted bond wires. Corrective action implemented at assembly vendor.
A 1010 JB13 failure at 96 hours same problem as above.
A 1010 JB28 failure at 96 hours due to open bond wire caused by lifted die paddle. This was the first qual lot from a new
assembly vendor and corrective action was implemented.

Table 8.

85°C/85% Humidity with DC Alternate Pin Bias of 0-5.5 V

Product

Run#

Package

# Units

A1010
A1010
A1010
A1010
A1010

JB13
JB14
JB22
JB26
JB27

68 PLCC
68 PLCC
68 PLCC
68 PLCC
68 PLCC

80
81
54
54
19

A1010A

TI1104
TI1243
TI1263
TI1297

68 PLCC

80

A1020

JF48
JF49

84 PLCC
84 PLCC

A1020A

JF33

84 PLCC

168 Hours

Number of Failures
500 Hours 1000 Hours
2
0
0
0
0

1
0
0
0
0

0

0

0

34
49

0
0

0
0

30

0

0

2000 Hours
0
0

Failure Analysis:
A1010 JB13:

Two failures at 500 hours. Open pins due to bond lifting. Corrective action implemented at assembly vendor.
One failure at 1000 hours. Horizontal track open (Metal I}.

3-13

•

Table 9.

Temperature Cycling Test

Number of Failures
100 Cycles SOO Cycles 1000 Cycles 2000 Cycles

Product

Run#

Package

# Units

A1010
A1010
A1010
A1010
A1010

DG1077
JB13
JB14
JB26
JB28

84JLCC
68 PLCC
68 PLCC
68 PLCC
68 PLCC

20
158
28
21
31

0
0
0
0
0

0
0
0
0

A1010A
A1010A
A1010A

TI15
TI24
TI1104
TI1243
TI1263
TI1297

68 PLCC
68 PLCC
68 PLCC

125
176
129

0
0
0

0
0
0

A1020

JB22

84 PLCC

17

A1020A

TI1800
TI1859
TI2156

84 PLCC

129

o
o

o

o

o

0

0

o

-40°C-12S0C Cycles
A1010A

TI1104
TI1243
TI1263
TI1297

68 PLCC

129

0

0

0

0

A1020A

TI1800
TI1859
TI2156

84 PLCC

129

0

0

0

0

-6SoC-1S0°C Cycles
A1010A

TI1104
TI1243
TI1263
TI1297

68 PLCC

129

0

0

0

0

A1020A

TI1800
TI1859
TI2156

84 PLCC

129

0

0

0

0

A1020A

JF33

84 PLCC

116

0

0

0

Other Tests
Electro Static Discharge (ESD)

All Actel products contain static electricity protection circuitry and
are tested for sensitivity to static electricity by using the human
body model as described in MIL-883C (100 pf discharged through
1.5 K ohms). Three positive and three negative pulses are
discharged into each pin tested at each voltage level characterized.
For inputs and 1I0s, these six pulses are applied with three different
grounding conditions; V ss only grounded, V cc only grounded, and
all other IJOs grounded. Thus each pin receives a total of eighteen
pulses for each test voltage. After pulsing, the units are then tested
on a VLSI tester. Leakage currents are measured at 0 V and 5.5 V.
Any pin showing more than 1,uA of leakage current is considered
to be a failure. To date, all Actel products pass ESD testing at 1000
V. For further information about specific products and packages,
please contact Actel.

3-14

Latch-Up

Latch-up is a well-known cause of failure in CMOS circuits.
Parasitic bipolar transistors are created by the P-Channel
transistors, the N-Channel transistors, the N-Well, and the
P-Substrate. These transistors are connected in a manner which
effectively creates an SCR. If a voltage on an external pin were to
forward bias to the substrate, the parasitic SCR can be latched to
the on state creating a low impedance path between Vcc and
ground. A large amount of current then flows through this path.
This current can, at best, temporarily make the device
nonfunctional and, at worst, cause permanent damage.
There are several techniques used by CMOS designers to reduce
the chance of latch-up. One of the most common techniques is the
use of guard rings to isolate P-Channel and N-Channel transistors.
The disadvantage of this method is that it requires additional
silicon die area. Another method is to use a substrate bias

ACT Family Reliability Report

generator. Creating a negative substrate bias means that an input
must go even more negative to cause latch-up. A third technique is
to use EPI wafers in order to achieve low substrate resistance,
which lowers the chance of triggering latch-up. Actel uses both
guard ring and EPI wafer techniques for the A101O/A 1020 devices.
The latch-up test method used is defined by JEDEC Standard No.
17. Each I/O pin on a tested device was forward biased in both
directions (to Vss and Vee) by forcing negative and positive
currents ranging from + -50 rnA to + -250 rnA in 50 rnA
increments. Following each stress, the device lee current was
measured. If the current exceeded the datasheet limit of 10 rnA, the
unit would be rejected. The device was also functionally tested.
Fifteen units from three different wafer lots were tested. Testing
was done at room temperature as well as at a worst case
temperature of 135°C. All device I/Os and power supplies were
tested. No failures were detected up through 250 rnA
Radiation Hardness
A programmed antifuse makes a connection between an upper
layer of polysilicon and an N + diffusion on the bottom. This
connection is very similar to a "buried contact" used in some MOS
processes. Many other programmable logic products rely on stored
charge to make their connections (i.e., RAM, EPROM, or
EEPROM). This stored charge can be susceptible to degradation
due to radiation exposure. The Actel antifuse makes a hard contact
and does not rely on stored charge. As a result, one would expect
the Actel products to have superior radiation tolerance as
compared to products which use stored charge.

Although Actel has not yet performed any radiation testing, several
customers and independent laboratories have performed tests and
shared their data. This data shows the A1010/AlO20 devices can
withstand a total radiation dose in excess of one million RADs.
Upsets/bit-day have been measured at 1 X 10-6 . Single Event Upset
(SEU) sensitivity measurements gave an asymptotic cross-section
of 3.6 X 10-6 cm 2/bit. The threshold for Linear Energy Transfer
(LET) was 22 MeV-cm 2/mg. For further information, please
contact Actel.

Summary
The data presented in this report establishes the excellent
reliability of the Actel AlOlO/AlO20. Both Actel models and actual
device testing show that the antifuse is highly reliable and that the
combined contribution of all anti fuses to the gate array product's
hard failure rate is less than 10 FITs (Failures-in-Time) or 0.001%
failures per 1000 hours.

References
1) E. Hamdy, et aI, "Dielectric Based Antifuse for Logic and
Memory ICs", IEDM paper, p. 786-789,1988.
2) S. Chiang, et aI, "Oxide-Nitride-Oxide Antifuse Reliability",
Proc. Int. ReI. Phys. Symp., 1990
3) J. Lee, I-Chen, and C.Hu, "Modeling and Characterization of
Gate Oxide Reliability", IEEE Trans. ofElec. Dev., Dec. 1988.
ACT and PLICE are trademarks of Actel Corporation.

ACT 2 Addendum
High Temperature Operating Life
# Hours

# Fail

Temp

Vcc

7
129

CHI1240
CHI1240

500
1000

0
0

125
125

5.75
5.75

132 PGA
132 PGA
132 PGA

38
55
36

CHI1240
CHI1240
CHI1240

2000
2000
2000
1000

0
0
0

5.75
5.75
5.75
5.75

Product

Run#

Package

1240
1240

TI3257
TI3257

132 PGA
144 PQFP

1240
1240
1240

TI 1045571
TI 1053933
TI 1053932

# Units

Pattern

1240

UI-01

132 PGA

JH05
JH06
JH03(K)
JH03(SB)

176 PGA
176 PGA
176 PGA
176 PGA

CHI1240
BETA12
BETA12
BETA12
BETA12

0

1280
1280
1280
1280

50
15
15
25
25

125
125
125
125

2000
2000
2000
2000

0
0
0
0

125
125
125
125

5.75
5.75
5.75
5.75

1280
1280
1280

TI1143649
TI1143650
TI1136307
UH-01
UH-02

176 PGA
176 PGA
176 PGA
176 PGA
176 PGA

44
44
42
26
26

BETA12
BETA12
BETA12
BETA12
BETA12

1000
1000
1000
1000
1000

1
0
0
0
0

125
125
125
125
125

5.75
5.75
5.75
5.75
5.75

1280

UH-05

176 PGA

40

SPEED9

1000

0

125

5.75

1280

UH-04

160 PQFP

80

SPEED12

168

0

125

5.75

1280
1280

3-15

I

~
HTOL Summary:
Total
Total
Total
Total

697
15
8.23E+05
1

Units:
Runs:
Device Hours:
Failures:

Equivalent Device Hours:
Ambient Temp,
Activation Energy

Device Hours

70C,0.6EV
55C,0.6EV
70C,0.9EV
55C,0.9EV

1.36E+07
3.44E+07
5.53E+07
2.23E+08

FITS:
60%
Confidence

Observed
74
29
18
4

70C,0.6EV
55C,0.6EV
70C,0.9EV
55C,0.9EV

162
64
40
10

Failure Analysis:
Product

Run #

Hours

Cause

1280

TI1143649

500

TRISTATE LKG PIN 28 (IN FAILURE ANALYSIS)

85°C/85% Humidity with DC Alternate Pin Bias of 0-5.5 V:
Product

Run#

Package

# Units

1240

TI3256

144 PQFP

78

168 Hours

Number of Failures
500 Hours 1000 Hours

o

2000 Hours

o

Temperature Cycle:
-65°C-150°C Cycles:
Product

Run#

Package

# Units

1225
1240

UJ-01
TI 1053932
TI 1045571
TI1053933
TI3256
UI-01
UI-02
TI1136307
TI1143650
TI1143649
UH-01
UH-02
UH-04
UH-14

100 PGA
132 PGA
132 PGA
132 PGA
144 PQFP
132 PGA
132 PGA
176 PGA
176 PGA
176 PGA
176 PGA
176 PGA
160 PQFP
160 PQFP

80
15
20
42
80
50
50
71
5
1
25
26
34
48

1240
1240
1240
1280

1280
1280
1280
1280

Number of Failures
200 Cycles 500 Cycles 1000 Cycles 2000 Cycles

o
000

o
o
o
o
o
o
o
o
o

o

o
o
o

o

o
o

Thermal Shock -65°C-150°C:
Product

Run #

Package

# Units

100 Cycles

1280
1240

UH-01,02
TI1149935

176 PGA

30
43

0

Number of Failures
200 Cycles 500 Cycles 1000 Cycles

2000 Cycles

0

121°C, 15 PSI Steam Pressure Pot (Unbiased Autoclave):
Product

Run#

Package

# Units

1240

TI10301

144 PQFP

79

3-16

96 Hours

Number of Failures
168 Hours 240 Hours

o

336 Hours

0

Testing and Programming
the A1010/A1020

Introduction
Users of masked gate arrays have long had to struggle with
:estability issues. In order to avoid board level, system level, or even
)ossible field failures, the system designer is forced to extend much
!ffort to develop test vectors for gate array designs. Even after the
rectors are developed, fault coverage for typical designs may be
)nly about 70% with 95% coverage being about the best possible.
With a 70% fault coverage, it has been shown that typical masked
~ate array designs are likely to have 2% to 5% defective devices!.
Field programmable logic devices have allowed the user to
~enerally avoid the need to develop test vectors due to t~sts
)erformed by the semiconductor vendor prior to programmmg.
nowever, most one-time programmable logic devices have not yet
lchieved the functional quality levels of other semiconductor
levices because it is not possible for the chip manufacturer to
lccess and test all internal gates. Early one-time programmable
levices had poor test coverage and users were often disappointed
:0 see functional failure rates of more than 10 percent on parts that
lad passed programming. However, on-chip test circuits and
:esting techniques have greatly improved over time and now
)ne-time programmable devices have functional defect rates in the
·ange of 0.1 to 1 percent2• Although this failure rate is low for
ndividual chips, putting 10 such chips on a single board can
:ontribute to a 5 to 10 percent board failure rate.
~eprogrammable

logic devices which use EPROM, EEPROM, or
technology have improved functional quality levels to nearly
LOO%. Since the semiconductor manufacturer can program these
:hips to any desired configuration, it is possible to test all internal
~ates. This can result in functional failure rates equivalent to most
)ther semiconductor devices.
~AM

restability of the A 1010/A 1020
\Ithough Actel's ACT ™ 1 Family arrays use a one-time
)rogrammable technology, the device's unique architecture
)ermits a degree of testability comparable to reprogrammable
levices. Special test modes allow functional testing of
Lnprogrammed devices at essentially 100% fault coverage. This
estability is independent ofthe large number of equivalent gates in
he AlOlO (1200 gates) and the A 1020 (2000 gates). In order to show
lOW this is accomplished, we will first review the architecture of the
\1010/AlO20 describe how they are programmed.

'rchitecture
"he basic building block of the AlOlO/A1020 is the Logic Module.
~ach Logic Module is programmable and capable of implementing
II two input logic functions, most three input functions, and many
ther functions up to seven inputs. For sequential circuits, latches
an be implemented with one Logic Module while flip-flops use
NO. With an architecture similar to a channeled gate array, Logic
10dules are organized in rows and columns across the chip (Fig. 1).
~djacent to each row of Logic Modules are routing channels.
lorizontal routing channels are shown in the figure but vertical

I 1992 Actel Corporation

By Ken Hayes

channels also exist (running through the Logic Modules). Routing
channels are used to configure a Logic Module and connect inputs
and outputs of Logic Modules together to implement a design.
Surrounding the array of Logic Modules and routing channels are
I/O buffers and test circuits.
Within the routing channels are programmable antifuse
(pLICE TM) elements. The anti fuse is normally open and is
programmed to form an electrical connection between routing
elements. An antifuse which connects a horizontal routing track to
a vertical track is called a cross antifuse. An example of a Logic
Module interconnection (or a net) is shown in Figure 2. Here, the
output from Module 3 is connected to a horizontal routing track by
programming a cross antifuse. Another cross antifuse is
programmed to connect an input from Module 4. In a similar
manner, the output of Module 3 is connected to the input of
Module 2. Notice that not all horizontal tracks are continuous
across the chip. Often tracks are broken into a series of smaller
tracks called "segments". Segments are useful because it is often
desirable to connect Logic Modules which are close to each other,
and using a full horizontal track would waste routing resources and
slow down circuit performance. Sometimes, however, it is
necessary to connect two segments together to form a longer
segment. This can be done by programming a special type of
antifuse referred to as a horizontal antifuse. As an example, the
output of Module 3 is also connected to the input of Module 1 by
programming two cross antifuses and one horizontal antifuse. The
AlOlO/AlO20 also have vertical antifuses used to connect two
vertical segments (not shown).
A more detailed example of the A101O/AlO20 architecture is
shown in Figure 3. Six Logic Modules (two rows, three columns) are
shown. Between the two rows are six horizontal tracks. Down each
column are five vertical tracks. Note that the actual AlOlO/A1020
typically have 25 horizontal and 13 vertical tracks. The circles at the
intersection of vertical and horizontal tracks represent cross
antifuses. There are also circles at certain points on the horizontal
tracks which are horizontal antifuses. No vertical antifuses are
shown. Notice the transistors which connect both horizontal and
vertical tracks. These are referred to as horizontal and vertical pass
transistors. By turning on selected transistors, various horizontal or
vertical tracks can be connected together even though an antifuse
has not been programmed. This ability to connect tracks in
unprogrammed devices is used extensively during antifuse
programming and is one of the key elements responsible for the
excellent testability of the AlOlO/A1020.
Configuration of Logic Modules is interesting because there are no
dedicated antifuses in the Module in order to accomplish this.
Instead, the inputs (and outputs) ofI--egic Modules extend into the
cross antifuse array. Each Logic Module has eight inputs and one
output. By programming appropriate antifuses, an input can be
connected to a dedicated horizontal ground line, a V cc line, or a
horizontal routing track. The Logic Module implements a
particular logic function by tying appropriate unused inputs to
ground or Vcc.

April 1992

317

•

~

1/0 Buffers, Program and Test Circuits

I
~
::s

2
U
ti

~

"
C

1"11

Row of
Logic Modules

E
1"11
C,
0

•
•
•
•

Routing
Channel

Ii:
~

~
::s

I

I

III

g

I
I

Figure 10. Architecture

Programmed
Horizontal Antifuse

Logic Module
Input

Output
Segment

Logic Module
Output

'"

-+-----

Input
Segment

Programmed
Cross
Antifuses

I

Rows of
Logic
Modules

L
Figure 11. Routing

3-18

A1010/1020

Vertical
Control

L,I

L,I

L,I

L,I

;::IT

~I

r-II

.JI

~~

Vertical
Track
Segment

r...
I-'
,,~

,~

Cross
Antifuse

r...

'I-"V

'-1/

" t'\

I't'\

..I

," ./

1' ....

I' ....

I' '\

1''\

,"~

~,

------=='''' ,
r...

-I' ....

~~

4~

I

i=h "

'+'

'-./

I' ~
'I-' , ~

I

i=, "

'+'

"

;:::rr

..I
1''\

,
I' ....

"

,"

'-V

1' ....

I't'\

1" ....

,

1" ....

....

"
I

....

'+'

r-.

U

," ,"

'-1/

I' ....

"t'\

'''' ,

;.l

,

r-.

1'''

, ," ," ''''
I'

I't'\

'V
I"~

rh "

I't'\

'V

I'~

I

rh

r"\

'+'

rr-.

.... ./

,./

,

1" .....

...../

'"11
,.JI

-'1
,.JI

~I

I'~

'V 'I-'

,

~I

4~

,,~

'..I , 7

' 7 , 7 ' ./ '-./
Vertical
.... 1' ....
Pass ___
.... .... ....
./
'Transistor
____
-'1
-'1

"

~

I't'\

V 'I-'

.JI

0

I-'

L,I

L,I

-'1
,.JI

" .... 1' .....
-,7
,
1" ....

''''

,
I'

I

rfLEp-

I

r~

I

r fLEp-

1''\

.... ./
,.. ....
....

11
roll

4_
4~

~~

U

0

0

Logic
Module - - -

I'~

Horizontal
Track - - Segment

~

t'\

'''' '" V
7,
1' ....

']

"

1"'\
1/

i=::; "

t'\

V

'+'

I

1''\
.... 1/

/

I"~

r...

r''''
....
"

'..I

,..I

.... 1/

I" ....

,

r

Horizontal
Control

1' ....

I'

.... 1/

r=i
1/

/
Horizontal
Pass Transistor

r"\

,..I

, ..I

1" ....

, ,

'-V~

1" ....

, ..I
I"

.... 1/

,..

....

11

.... v

Horizontal
Antifuse

Figure 12. Programmable Interconnect

Programming
An antifuse is programmed by applying a sufficiently high voltage
across it. This voltage is referred to as Vpp. In order to access an
antifuse deep inside the chip, it is necessary to create electrical
paths from Vpp and ground to the antifuse. This is done by turning
on the appropriate horizontal and vertical pass transistors (in
normal chip operation, these transistors are always off). The
transistors are turned on by applying Vpp to their gates. In Figure
4A, we see an example of programming a typical cross antifuse.
Vpp is applied to a vertical track at the top of the chip and ground is
applied to a horizontal track on the right side. The design of the
AlOlO/AlO20 actually allows applying Vpp or ground from the top,
bottom, left, or right as is appropriate to best access a particular
antifuse. Notice that Vpp is also applied to the gates of the
horizontal and vertical pass transistors on the tracks accessing the

cross antifuse. The circled cross antifuse now has Vpp applied to it
on one side and ground on the other. This voltage breaks down the
antifuse's dielectric and creates an electrical connection between
the horizontal and vertical routing tracks.
There is one other important consideration when programming an
anti fuse. Notice that the cross antifuses in the same vertical track as
the antifuse to be programmed also have Vpp applied to them on
one side. This is true until the track is broken by a vertical pass
transistor below it which is turned off. However, the potential on
the other side of the antifuses is not being driven. Should this
potential be at ground, the other cross anti fuses on the vertical
segment could be accidently programmed. The same logic applies
to other antifuses on the same horizontal track. Here, one side of
the antifuse is being driven to ground and if the other side were at
Vpp, extra antifuses could program.

3-19

GND
Vertical
Control

L,I

L,I

-II

-II

4~
Vertical
Track - - Segment

L,I
rll

4.

0

1"1-\

1"1-\

1"1-\

1"1-\

'I-'

'V

'I-'

'V

1'1-\

,.1-\

1'1-\

,.1-\

I

'V 'V 'V 'V

Cross
Antifuse

------==

1"1-\

1"1-\

1'1-\

1'1-\

'V '1-1 '1-1 '1-1

-1'1-\

'I-'
Vertical
I"r-.
Pass ~
Transistor
_____'V

1'1-\

1'1-\

,1-\

'I-'

V

1'\

1'1-\

1'\

V

'V 'V

"1

V

1

rh

1'"'\

L,I

~I

~I

~I

4.

1"1-\

1 1-\

1 1-\

I'~

1'1-\

1-\

1-\

1'1-\

rhr'i

1'1-\

~

iIt., 1-\

Antifuse to
' I-'~ ~
be Pro rammed I' 1'\
1'\
'V I-' ,

"1

11-\

I

rFi

'V ' V ' V
1'"'\
~

rh

1'"'\

,

I"

,1 1-\ ,, 1-\

'V ' V '

'V

11'\

1 1'\

, 1-\

,.1-\

11'\

,

,1-\

,.1-\

,

V '

,

,

4~

1

rfyvGND

'I-'

"11

GND

.,JI

~I

4~

rfyv-

I-'

'11

rll

1

1'1-\

'I-'
,.r-.

'+'

,

'v

, , ,

"1

~I

4~

1'\

,.r-.

1'1'\

l

Vpp

4~

4~

'V I-' , I-' ,
I'
1''' 1 ~ 1
'V ' V , V 'V

~I

4~

L,I

'V , V , V 'V

"1

~I

L,I

'+'

'+'

Vpp

Vpp

Vpp

4~

4~

logic
Module---

Horizontal
Track - - Segment

1'1"\

1'1"\

,1"\

1'1"\

'I-'

'I-'
,.1"\

'I-'

'I-'
,.1"\

1'1"\

1'1"\

I

rh

'V 'V 'V 'V

1'"'\

11"\

'+'

I-'

1 1"\

, 1'\

1'1"\

1-\

1'\

'V

I-'

"V

_/~

11'\

rh

1-\

'

1/

/

/
Horizontal
Control

Horizontal
Pass Transistor

1'"'\

'+''\

1 1'\

1"\

, 1-\
I'

'V '

,1-\

I-'
1-\

1

rfyv-

'1-1

Horizontal
Antlfuse

Figure 4A. Programmable Interconnect

The above problem is solved by first applying what is referred to as
a "precharge cycle." During the precharge cycle, all horizontal and
vertical tracks are charged to Vpp/2. As a result, there is no voltage
across the antifuses. The appropriate vertical track is then driven to
Vpp and a horizontal track to ground (Fig. 4B). At this point, other
antifuses on the vertical track have a potential of Vpp/2 across

3-20

them (Vpp on one side and Vpp/2 on the other). This Vpp/2
voltage is not sufficient to program the antifuses. Other antifuses
on the same horizontal track also have Vpp/2 across them (Vpp/2
on one side and ground on the other). Most other antifuses in the
chip still have Vpp/2 on both sides and will not program.

A1010/1020

Vertical
Control

L,I

L,I

.-JI

.-JI

4~

Vertical
Track - - Segment

.... r..

,I'--

Cross
Antifuse

.... r..

r..

------==

I' r..

L,-I
,..-II

4~

rh r..

rr-

'V

1

I'r..

I'"

r..

I-'

I-'
rr..

I'"

L,I

,-II

,..-II

,..-II

1'1"\

,
,

rf:; "

,

'II

'II

'II

.-JI

.-II

.-II

1

rh

r..

'+"

1"'1'\

,

r- 1"\
'I-' 'I-"

I'"

I'"

1"'1"\
"I-'
1"'1"\

"I-'

j=h~

/'1"\

'I-'

I

~

"

"

1"'1'\

I'"

"I-"

"

1"\

"I-"

I-"

1"\

'I-" "
j"

I

r~ Vpp/2

1

r ~ Vpp/2

1"\

1~ 1b... 11'--

JI"\

/'1"\

Vpp

4~

,/

1

'I-' ' I-' , ,/ 'I-'
r1"''''
"I-'
'I-'

"I-'
I
'V
'I-' ' I-' , I-' 'I-'
r..
r.. I' r.. I'r1'1"\ IJ ~r 1"\
'I-' , I-' , I-' , I-'
Antifuse to
' I-'~ Ii''' ,/
be
Pro!
rammed
r..
I'
rI'
I'"
r.. r r.. r
-

Vertical
Pass ____
______
Transistor

L,I

0

"\

Vpp

L,I

4~

1"'1'--

I' 1"\

Vpp

Vpp/2 Vpp

I'"

I-' 'I-'

I'r..

GND

4~

'"" '""

Vpp/2
~

Vpp/2

Vpp/2
~

Vpp/2

GND

"I-" 'I-"

I'D. 11"\

Vpp/2

'I-" " I-" " I-" 'I-"
"11
':Ii
,..-II
r11

'I-'

'II
,.JI

GND

4_
I~

4~

4~

4~

4~

Logic
Module - - -

;:1=; r..

Horizontal
Track - - Segment

I-'

I-' '"" 'I-'
I'r.. I' r.. I' r.. I'r'I-' , I-' , I-' 'I-'

I

'V

1'1"\ L b...

r

'I-' ' ""

,

1"\

r

'"

I'

/
Horizontal
Control

"I-'

1"1"\

"I-'
r'"

"

rh

1/

/

Horizontal
Pass Transistor

r..

L~

L~

~

"I-'
1''''

"I-'

I-'

'I-'

'"

(1'\

'+"",1-'

r'"
'I-'

I-'

""

I

r

~ Vpp/2
Vpp/2

Horizontal
Antifuse

Figure 4B. Programmable Interconnect

Programming Algorithm
In concept, the AlOlO/AlO20 are programmed in a manner very
similar to many other programmable logic devices as well as
memories such as EPROMs. The programming algorithm consists
of:
1. An addressing sequence to select the antifuse to be
programmed.
2. A programming sequence where Vpp is applied in pulses
until the antifuse programs.
3. A soak or "overprogram" step to assure uniform, low
antifuse resistance.
4. A verify step to make sure the antifuse was properly
programmed.
Unlike a memory where an antifuse is addressed by applying a
parallel address, the AlOlO/AlO20 are addressed in a serial manner
by using the special DCLK (Data Clock) and SDr (Serial Data In)
pins. There is a large shift register which travels around the
periphery of the chip. Bits in this shift register can be used to drive
tracks to ground, Vee, Vpp, or float. It is also possible to sense the

level on the track (high or low) and load this information into the
shift register. The shift register is about 320 bits long in the AIOlO
and 420 bits long in the A 1020 (due to the larger number of tracks).
By shifting in the correct address, any antifuse can be selected for
programming. The shift register also plays a key role in the testing
of the chip. This will be discussed later.
The programming sequence starts with the precharge pulse where
Vpp/2 is applied to the Vpp pin. This is followed by a programming
pulse where Vpp is applied to the pin. Following the program pulse,
the voltage on the Vpp pin is returned to a nominal value (about 6
volts). See Figure 5 for a typical Vpp waveform example. The
precharge/program pulse sequence is repeated until either the
selected antifuse programs or a maximum number of pulses is
exceeded (in which case the antifuse is considered nonprogrammable and the device is rejected).
Confirmation that an antifuse has programmed is determined by
monitoring the current on the Vpp pin. This current is very low
(typically < 10 ua) until an antifuse programs. Once an antifuse is
programmed, an electrical connection is made between Vpp and
ground in which case currents in the range of 3-1Sma may be

3-21

I

observed on Vpp. Once this current is observed, the antifuse is
considered programmed and enters the soak or "overprogram"
cycle. Here, extra pulses are applied to the antifuse to achieve
minimum antifuse resistance.

5.

6.

150-300 }Js

6V

·1

Figure 5. Vpp Waveform

7.

ACT Family Programming Algorithm
8.

Current Parameters

V Program
V Precharge
V Verify
t Program
t Precharge
I Threshold
I Max
# Soak
Maxpulses

21 V
12.35 V
6.0V
150 -300}Js
25}Js
~2.5mA

(to detect programmed antifuse)
15 mA (clamp current)
30-800 pulses
60,000

9.

Test Modes of the A 1010/A 1020
The unique architecture described above allows outstanding
testability of unprogrammed devices at the factory. Details of the
various test modes available are as follows:
1. The shift register circling the periphery of the chip can be

both downloaded and uploaded. This allows the use of
various test patterns to assure the shift register is fully
functional.
2. All vertical and horizontal tracks can be tested for continuity
and shorts. There are several ways to implement these tests.
One way of doing continuity testing is to precharge the
array, turn on all vertical or horizontal pass transistors on a
track, drive the track low from one side of the chip, and read
a low on the other side. Shorts can be detected by driving
every other track low after precharge and reading back on
the other side. Note that these tests also confirm that the
vertical and horizontal pass transistors will turn on.
3. It is important for programming to make sure that all tracks
can hold the precharge level. By charging a track, floating it,
and waiting a predetermined amount of time, the track can
be read back and confirmed it is still high.
4. Leakage of vertical and horizontal pass transistors can be
tested for by driving one side of a track to a voltage via the
Vpp pin and grounding the other side. All pass transistors
except the one being tested are turned on. If excess current

3-22

10.

11.

12.

is detected on the Vpp pin, the pass transistor is considered
defective.
The AlOlO/AlO20 have a dedicated clock buffer which
travels across all horizontal channels. This buffer can be
tested by driving with the clock pin and reading for the
proper levels at the sides of the array.
The A1010/AlO20 have two special pins referred to as Probe
A and Probe B (Actionprobes TM). By entering a test mode,
the shift register can be made to address the internal output
of any Logic Module. This output is then directed to one of
two dedicated vertical tracks which in turn can be observed
externally on the Probe A or B pins. This ability to observe
internal signals (even on unprogrammed parts) allows Actel
to perform a large number of functional tests. The first such
test is the Input Buffer Test. Input buffers on all I/O pins
can be tested for functionality by driving at the input pad
and reading the internal I/O output node through the probe
pins.
Test modes exist to drive all output buffers low, high, or
tristate. This allows testing of Vol, Voh, 101, loh, and leakage
on all I/Os.
One of the key tests is the ability to functionally test all
internal Logic Modules. By turning on various vertical pass
transistors and driving from the top or bottom of the chip,
any of the eight module inputs can be forced to a high or
low. The output of the module can then be read through the
Actionprobe pins. The Logic Module test allows 100% fault
coverage of each Module. In addition, the architecture
allows Modules to be tested in parallel for reduced test time.
The AlOlO/AlO20 have two dedicated columns on the chip
which are transparent to the user and used by the factory for
speed selection. These columns are referred to as the
"Binning Circuit." Modules in the columns are connected to
each other by programming antifuses. The speed of the
completed test circuit can then be tested. The Binning
Circuit allows the separation of units into different speed
categories. It also allows the speed distribution within each
category to be minimized.
There are several tests to confirm the programming circuitry
is working. The first such test is a basic junction
stress/leakage test. The program mode is enabled and Vpp
voltage plus a guardband is applied to the Vpp pin. All
vertical and horizontal tracks are driven to Vpp; thus no
voltage is applied across the antifuses. The Ipp current is
then measured. If it exceeds its normal value, the device is
rejected.
The A1010/A1020 have a test to assure all antifuses are not
programmed. This is referred to as the Antifuse Shorts Test
(or Blank Test). The array is precharged and then the
vertical tracks are driven to ground. The horizontal tracks
are then read to confirm they are still high (a programmed
or leaky anti fuse would drive a horizontal track low). The
test is repeated by driving horizontal tracks low and reading
vertical tracks.
The functionality of the programming circuitry can be
verified by programming various extra antifuses on the chip
which are transparent to the user. Some of these antifuses
were already described earlier when the Binning Circuit was
discussed. The AlOlO/A1020 also have a Silicon Signature TM.
The Silicon Signature consists of four words of data, each

A101 0/1 020
word 23 bits in length. The first word is hard wired (no
anti fuses) and contains a manufacturer ID number as wen as
a device ID number. These numbers can be read by a
programmer and the proper programming algorithm would
be automaticany selected. The other words contain antifuses
and are programmable. Actel is currently using bits in these
words to store information such as the wafer number and
run number the chip came from. Thus each AlOlO/AlO20
has traceability down to the wafer level. By programming
this information, the functionality of the programming
circuitry is also tested. Future Actel software win al10w the
user to program a design ID and checksum into the Silicon
Signature, and by later reading this back, the user can verify
the chip is correctly programmed to a given design.
13. The most important antifuse test is the stress test. When this
test is enabled, a voltage applied to the Vpp pin can be
applied across an antifuses on the chip (the other side is
grounded). The voltage applied is the precharge voltage plus
a significant guardband. After the voltage is applied, the
Antifuse Shorts Test is again used to make sure no antifuses
have programmed. The anti fuse stress test is effective at
catching antifuse defects. Since the reliability of the antifuse
is much more voltage dependent than it is temperature
dependent, this test is also an effective antifuse infant
mortality screen. See the Actel AlOlO/AlO20 Reliability
Report for details.

Burn-In of the A 1010/A 1020
As mentioned above, Actel has found that antifuse infant mortality
failures can be effectively screened out during electrical testing,
and it is thus unnecessary to do any kind of bum-in for standard
commercial production units to screen out antifuse infant mortality
failures. However, bum-in is stiII an effective screen for standard
CMOS infant mortality failure mechanisms, and it is required for
an military 883C Class B products. MIL-883C Method 1005 anows
several types of bum-in screens. These can be divided into two
categories: steady-state (static) and dynamic. Static bum-in applies
DC voltage levels to the pins of the device under test. The device
mayor may not be powered up. Dynamic bum-in applies AC
signals to device inputs. These signals are selected such that the
device receives internal and external stresses similar to what it may
see in a typical application.
Static bum-in is by far the simplest method to implement. By
choosing appropriate biasing conditions and load resistors, it is
possible to design a single bum-in circuit which could be used for
both unprogrammed and programmed devices. It would not matter
what pattern is programmed into the device. Static bum-in can be
an effective screen for some types of failure modes, particularly
those which may happen at device inputs or outputs (such as
screening for mobile ionic contamination). It is not, however, very
effective at stressing internal device circuits. Many internal nodes
may be biased at ground without receiving any voltage or current
stress. Signal lines win not toggle, and it may not be possible to
screen failure modes such as metal electromigration.
A properly designed dynamic bum-in can effectively stress inputs,
outputs, and internal circuits. However, dynamic burn-in of ASIC

2

products can be very expensive because customer specific custom
bum-in circuits and bum-in boards must be designed and built in
order to properly stress each design implemented in the ASIC. This
results in large NRE costs and long lead times to design and build
these boards. From the standpoint of bum-in, a programmed
AlOlO/A 1020 FPGA is essentiany the same as a mask-programmed
ASIC, and it would require similar custom bum-in circuits to do a
dynamic burn-in. However, Actel has been able to use the
testability features of its FPGA products to anow effective dynamic
bum-in of unprogrammed devices. This dynamic bum-in anows us
to stress circuits in a way which static bum-in would be unable to
duplicate.
During bum-in of unprogrammed units, test commands are seriany
shifted into each device using the SDI pin and clocked using the
DCLK pin. There are three test modes shifted into each device.
The first test stresses each cross antifuse with a voltage ofVpp-2V
(Vpp is norm any set at 7.5V so each antifuse gets 5.5V across it).
This voltage is applied to an vertical tracks while the horizontal
tracks are grounded. It requires 322 bits of data to enable this mode
for the AlOlO and 416 bits for the A1020. The data is shifted in at a 1
MHz cycle rate. Once enabled, the stress mode is held for 10 ms.
The second test mode is identical to the first except that the
horizontal tracks are driven to Vpp-2 V while the vertical tracks are
grounded. Note that both of these modes are similar to the antifuse
stress tests described earlier (although the stress voltage is lower
during bum-in). Not only do these tests stress the antifuses, but
they also toggle an routing tracks in the chip to Vpp-2V and
ground. An input and output tracks to the logic modules are also
toggled.
The third test drives several I/O pins on the chip to a low state.
Prior to this, they are at high impedance state and held at Vcc
through pun-up resistors. This test confirms that the bum-in is
being properly implemented by looking at these I/O pins to see if
they display the proper wave form. It also passes current through
each I/O as it toggles low.
Although the chip is unprogrammed, the above tests anow us to
apply stresses to the inputs, outputs, and internal nodes which are
similar to what a programmed device may see in normal operation.
Once bum-in is completed, post burn-in testing as specified by
MIL-883C is performed (including PDA) to assure funy compliant
devices are shipped to the customer.

Conclusion
The description of the AIOlO/AlO20 architecture and the
numerous test modes attest to the outstanding testability of these
devices. An internal logic gates can be tested without programming
antifuses other than the few for the Binning Circuit and Silicon
signature. Because the AlOlO/AlO20 are one-time programmable,
the only item that is not funy tested at the factory is the
programmability of an the individual antifuses. However, this is
done on the programmer while the units are being programmed.
Being able to test an internal gates anows Actel to achieve
functional yields that are superior to other one-time programmable
devices and equivalent to reprogram mabIe parts.

Henshaw, "User Requirements for Fault Coverage", Wescon Proceedings, 1990, P. 179
AMD PAL Device Data Book, 1988, P. 3-106

ACT, PLICE, and Actionprobe are trademarks of Actel Corporation. Silicon Signature is a trademark of SEEQ, Inc.

3-23

I

3-24

Article Reprints

Artice Reprint 3:
An Architecture for Electrically-Configured Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1

Article Reprint 4:
Dielectric-Based Antifuse for Logic and Memory ICs ........................................................

4-7

Article Reprint 9:
Oxide-Nitrate-Oxide Antifuse Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-13
Article Reprint 10:
An FPGA Family Optimized for High Densities and Reduced Routing Delay ..................................... 4-21

Article Reprint 3

AN ARCHITECTURE FOR
ELECTRICALLY CONFIGURABLE
GATE ARRAYS
by Abbas EI Garnal, Jonathan Greene, Justin Reyneri,
Eric Rogoyski, Khaled A. EI-Ayat, Arnr Mohsen

I

Reprinted from
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Vol. 24, No.3, 1989
©

1992 Actel Corporation

4-1

394

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 24, No.2, APRIL 1989

An Architecture for Electrically
Configurable Gate Arrays
ABBAS EL GAMAL, SENIOR MEMBER, IEEE, JONATHAN GREENE, JUSTIN REYNERI,
ERIC ROGOYSKI, KHALED A. EL-AYAT, AND AMR MOHSEN, SENIOR MEMBER, IEEE

Ahstract -An architecture for electrically configurable gate arrays using
a two-terminal anti-fuse element is described. The architecture is extensible, and can provide a level of integration comparable to mask-programmable gate arrays. This is accomplished by using a conventional gate array
organization with rows of logic modules separated by wiring channels.
Each channel contains segmented wiring tracks. The overhead needed to
program the anti-fuses is minimized by an addressing scheme that utilizes
the wiring segments, pass transistors between adjacent segments, shared
control lines, and serial addressing circuitry at the periphery of the array.
This circuitry can also be used to test the device prior to programming and
observe internal nodes after programming. By providing sufficient wiring
tracks segmented into carefully chosen lengths and a logic module with a
high degree of symmetry, fully automated placement and routing is facilitated.

vertical
control

vertical
track
segment

I

I

INTRODUCTION

Manuscript received August 22, 1988; revised December 2. 1988.
The authors are with Actel Corporation. Sunnyvale. CA 94086.
IEEE Log Number 8826132.

Lf.=F
L --.J

pass
transistor
logic
module

I

I

I

f---J

J
L.::::r

r-

L --.J
horizontal
track
segment

horizontal
control

Fig. 1.

horizontal

pass transistor

horizontal
fuse

Interconnect architecture.

pitch of the first- and second-level metal lines that connect
to it; it is about the same size as a via.
This paper focuses on the architecture itself, which is
fairly independent of the exact details of the particular
CMOS technology and the anti-fuse. Other papers describe
more fully the anti-fuse [4], a CMOS circuit implementing
the architecture [5], and a study comparing the architecture's logic density to that of conventional gate arrays [6].

II.

PROGRAMMABLE INTERCONNECT ARCHITECTURE

The general architecture, shown in Fig. 1, exhibits the
familiar gate array organization: rows of logic cells interspersed with routing channels. There are, of course, several
key differences.
The tracks in the channels are not simply empty areas in
which metal lines can be arranged for a specific design.
Rather, they contain predefined wiring "segments" of various lengths. Other wiring segments pass through the channels vertically. Each input and output of a logic module is
connected to a dedicated vertical segment. Other vertical
segments just pass through the modules, serving as
feedthroughs between channels. (The number and lengths
of segments in Fig. 1 are only suggestive.)

0018-9200/89/0400-0394$01.00 <01989 IEEE

4-2

--.J

L ~

vertical

M

ASK-programmable gate arrays offer the architectural flexibility and efficiency to integrate thousands of gates, but require long development time and high
nonrecurring engineering costs. On the other hand, the
convenience of field programming is available with programmable logic device (PLD) technologies, but their architectures have not allowed integration of a wide variety
of applications exceeding a few hundred gates [1], [2].
We describe a novel gate array architecture [3] which
combines the flexibility of mask-programmable arrays with
the convenience of field programmability. Its implementation is made possible by a two-terminal electrically programmable anti-fuse offering low resistance in its conducting state and small area.
The architecture supports a design style similar to conventional gate arrays, including fully automatic placement
and routing algorithms attaining 85-95-percent utilization.
This required considerable emphasis on symmetry and
routability, which we touch on below.
The anti-fuse is so called because it irreversibly changes
from high to low resistance when "blown" by applying a
programming voltage across it. The anti-fuse, or fuse for
short, has an ON-state resistance of approximately 500 Q.
The layout area of the fuse cell is generally limited by the

I
L~

L

cross
fuse

L

I.

I

L ~

Article Reprint 3

EL GAMAL

et al.:

395

ARCHITECTURE FOR ELECTRICALLY CONFIGURABLE GATE ARRAYS

Fig. 2.

I

Horizontal fuse programming.

I

I

~I:;

j"i

i"L

F2

I

I

I

jl:;

f'L
F3

F4

Fig. 4.
Fig. 3.

GND

FS

A sneak path.

Cross-fuse programming.
TABLE I

A fuse is located at each crossing of a horizontal and
vertical segment. Programming one of these "cross fuses"
provides a low-resistance bidirectional connection between
the segments. Other fuses are located between adjacent
horizontal segments within a track. When blown, these
"horizontal fuses" connect the two segments to form a
longer one. (Although not shown in the diagram, fuses
may also be provided to connect adjacent vertical segments.)
In order to program a fuse, we need to apply high
voltage across it. This is accomplished by an efficient
addressing scheme that uses the wiring segments themselves, pass transistors connecting adjacent segments, and
control logic at the periphery of the array. Fuse addresses
are shifted into the chip serially.
As shown in Fig. 1, each column of "horizontal pass
transistors" connecting horizontal tracks is controlled by a
shared "horizontal control" line running across the array.
Each row of "vertical pass transistors" is controlled by a
"vertical control" line. The peripheral circuitry can drive
the control lines and the segments at the end of each track.
Horizontal fuse programming is quite simple. In the
example of Fig. 2, we apply programming voltage Vpp
across the fuse Fl' All horizontal control lines except the
one in the column containing Fl are turned on by connecting them to V pp , and the appropriate track segments are
driven to GND and Vpp as shown. (Vertical fuses, if
present, are programmed similarly.) Cross-fuse programming uses both horizontal and vertical control lines as
shown in Fig. 3. Segments not driven to either GN D or Vpp
are left t:>recharged to Vpp /2. Thus the voltage across fuses
not being programmed is either zero or Vpp/2.
Some care is required to assure that a unique fuse is
addressed. Fig. 4 shows how previously blown fuses can
divert current along a "sneak path," in this case programming fuse Fs through previously blown fuses F3 and F4
instead of programming F2 • Fortunately, we are not interested in blowing an arbitrary pattern of fuses (this is not a
PROM!). For example, we are not concerned with programming a pattern that connects two outputs together
since this does not form a useful net. If we consider only
relevant patterns, it can be shown that programming the

4 transistor cells

modules

3 input NOR
4: I mux. non-invening
D latch with clear
D flip-flop with clear/set

full adder

10

fuses in a carefully chosen order eliminates sneak paths. In
general, fuses must be programmed starting from the center of the chip and moving outward, channel by channel.
Determining the proper order is a bin sort operation, and
can be done by software in linear time.
The pass transistors and peripheral control logic are also
used to test the chip; this is discussed in detail later.

III.

I

CHOICE OF THE LOGIC MODULE

As outlined so far, the programmable interconnection
architecture could be used with a variety of logic modules.
Which would be best? This turned out to be a very
difficult question, involving subtle trade-offs among
routability, the logical capability of the module as perceived by the user, and delays due to capacitive loading in
the routing segments.
The complexity of the module must be balanced with
the routing overhead. Mask-programmed gate arrays provide very flexible and efficient routing. They therefore use
a simple four· transistor cell. On the other hand, routing is
very expensive in both area and delay with present programmable logic arrays. These generally use a module
capable of implementing more complex functions [2]. The
architecture outlined here has a cost of routing closer to a
conventional gate array, suggesting a logic module of intermediate size. Because this is about the same complexity as
conventional gate array hard macros, the designer can use
a library like the familiar gate array cell libraries; there is
no need to map logic into a more complex module. Table I
lists several typical gate array macros and the numbers of
four-transistor cells and logic modules required to implement them.
4-3

396

IEEE JOURNAl. Of SOUD·STATE CIRCUITS, VOL. 24, NO.2, APRIl.

Prograrruned
Horiwntal Fuse
Logic Module

Al
SA

OUT

Input
Input
Segment

Output
Segment

Logic Module
Output

~~~~~~~

:::;::

Bl

Prograrruned

SB
~------------~

Sl ------------~

Fig. 5.

Rows of
Logic M~ules

Module function.

Our ~hosen module, shown in Fig. 5, has eight inputs
and a slllgie output. It is composed of three two~to-one
~ultiplexo~s, with an OR gate on the last stage's select
lllpUt. Vanous macros, such as those in the table are
imple~ented by using an appropriate subset of the i~puts
and tylllg the remaining inputs high or low. Thus the
m~dule ca~ implement all macros with two inputs, most
wIth three lllPUtS, many with four inputs, etc.
The. module's output is connected to a vertical segment
spanmng several channels. Each input is connected to a
short vertical segment spanning one channel. Four of these
span the channel above the module, four the channel
below. The use of short segments for the inputs reduces
parasitic capacitance and hence delay.
Note that each input is accessible from either the channel above or below but not both. At first, this would
appear to limit routability compared to a conventional
"doubl.e-entry" gate array cell, in which signals may enter
from eIther channel. However, there is nearly always more
than one way to implement a macro. For example, there
maybe up to four distinct ways to implement a two-input
gate: with both signals connecting to inputs in the top
channel, with both signals connecting to inputs in the
bottom channel, with one signal in the top and the other in
the bottom channel, or vice-versa.
By letting the router choose an implementation that uses
inputs accessed from convenient channels, the benefits of
full double-entry symmetry are approached or sometimes
attained. The degree of symmetry possible for a particular
macro m implemented in a given module is reflected in the
following measure S:

S{m) = log2 (N{m))
where N(m) is the number of distinct possible implementations of the macro m. Full double-entry symmetry would
correspond to a value S( m) equal to the fan-in of the
macro. To evaluate the overall symmetry of a module, we
average SCm) over the macro library, weighted by relative
macro usage U(m) and the fan-in F(m):

LU{m)S{m)
LU{m)F{m)'
4 4

1989

~~~~~~~~cross
Fig. 6.

Fuses

A routing path.

Thi~

is the effective fraction of macro inputs in a typical
deSIgn that have double-entry symmetry, and is an important criterion for choosing a module.
IV.

ROUTING

Fig. 6 illustrates the routing of a net. The vertical
segment connected to the driving module's output is connected by cross fuses to horizontal segments, which in turn
connect to the segments associated with module inputs. In
the top channel, a horizontal fuse is used to link two
segments into a longer one.
Th~ resistance of the blown fuses and the parasitic
capacItance of the segments used form an RC tree, with
th~ driver of the net as the root. Note that each input is
dnven through a maximum of three and generally two
fuses to limit the delay. (If the number of series stages in
the RC tree were allowed to increase further, the delay
through the routing would increase rapidly.) The maximum number of fuses and the segment lengths (hence
capacitances) can be altered to suit the chip dimensions
and the resistance of the fuse technology.
In rare instances, it is not possible to place the macros
so that all inputs on the net lie within the channels
spanned by the output segment of the driving module. To
handle this case, a few additional uncommitted long vertical segments are provided. The net is then routed from the
out~ut segment to a horizontal segment, then to the long
v.ertIcal segment, then to another horizontal segment, and
fmally to the necessary input segments. To keep the number of fuses in series limited to four, no horizontal fuses
are allowed in such nets. (If necessary, the architecture can
be extended to provide a special fuse connecting the output directly to a long vertical segment passing over the
driving module, thus eliminating the first horizontal segment and reducing the total number of fuses in series back
to three.)
A means must also be provided to connect internal
signals to the bonding pads of the chip. Each pad has a
dedicated bidirectional buffer, which connects to the array
through an associated I/O module. The I/O modules fit
in the outer columns and rows of the array next to the
logic modules. Each I/O module has two inputs, data and
enable, and an output. The data and enable signals are

Article Reprint 3

397

EL GAMAL et at.: ARCHITECTURE FOR ELECTRICALLY CONFIGURABLE GATE ARRAYS

sent to the output buffer of the associated bonding pad,
and the module's output comes from the input buffer of
the pad. Thus the I/O module can be configured to
provide input, output, tristate, or bidirectional capability.
To minimize clock skew due to differential routing delay, one entire track (or more if needed) in each channel is
set aside for clock distribution. These tracks are connected
directly to buffers, so that each input presents a similar
load driven through exactly one fuse.
An interesting theoretical question is whether more horizontal tracks are needed in each channel here (where the
lengths of the wiring segments must be predetermined)
than in mask-programmed routing (where the wiring is
customized for the design). Surprisingly, a high probability
of routability is obtained with only a few tracks above
channel density.
This requires a careful choice of the lengths of the
segments, based on statistics from an extensive suite of
design examples. This was done by first determining the
distribution of net lengths, i.e., the length each net would
run along each channel if the constraint of fixed segmentation were absent (as in a conventional gate array). The
distribution of physical segment lengths provided on the
chip was chosen to obey similar statistics. Then the segmentation was" tuned" manually based on actual routings
which obeyed the constraints it imposed.
To obtain good routing performance it is also necessary
to take advantage of the symmetry of the macros where
possible. For example, observe that if macro 4 in Fig. 6
permits its input to be routed from either the upper or
lower channel, there is a better chance of finding a free
horizontal segment to connect it.

V.

TESTING

To assure high programming yield, It IS necessary to
thoroughly test the chip for defects in the modules and
fuses prior to programming. With a simple addition, the
addressing circuitry used for programming suffices for this
purpose as well.
Continuity of the tracks is easily verified by turning on
all vertical and horizontal pass transistors, and using the
peripheral circuits to drive the tracks from one end and
read them back from the other. Testing for the absence of
shorts between adjacent tracks is done in a similar way by
applying a pattern of alternating ZERO'S and ONE'S.
Shorted or weak cross fuses are detected by turning on
all horizontal and vertical pass-transistor lines, grounding
all horizontal segments, and driving all vertical segments
to some stress voltage. Horizontal fuses are tested column
by column, with the same addressing method that is used
to program them.
To verify the functional operation of the modules, we
need to apply test vectors to their inputs and read their
outputs. A vector is applied simultaneously to an entire
row of modules by turning on all vertical pass transistors
except those in the row being tested. Data are applied to

Probe
___

1::

Colwnn
Enable

r
To
__ ~x~al

~

~-

,~ ...."~

~~
Module

Row Sele<:!

Column Sense

i
Fig. 7.

Probe circuit.

the inputs in the channel above the row from the periphery
at the top of the array, and to the inputs in the channel
below the row from the bottom of the array.
Since the outputs of the modules share a vertical track
with outputs of other modules above and below them,
some other means is required to read the module outputs
at the array periphery. As shown in Fig. 7, a select line is
provided along each row of modules, and a sense line
along each column. Activating the select line for the row of
modules under test gates their output values onto the sense
lines. The sense lines are loaded into a shift register at the
top of the array.
This ability to read the output of any module at the
array periphery is highly useful after programming as well.
Only a small amount of extra circuitry is required to select
one of the sense lines and make its value available at an
external pin of the chip. Thus by shifting in the appropriate address, the user can observe any internal node of his
design externally in real time. This virtual probe can be
used and its address changed even as the programmed chip
is operating in the user's system.

VI.

IMPLEMENTATION: SILICON

AND

I

SOFTWARE

The architecture has been implemented in a CMOS
device. For details, including the speed of the module in
isolation and in an application, see f5].
Computer-aided design tools have been developed to
support the architecture. Designs are entered as schematics
or net lists using a cell library.
The placement and routing algorithms are specific to the
architecture. As usual these are time consuming, taking up
to a few hours on a low-cost workstation. They achieve
lOO-percent routing completion. (Even expert users have
never been able to improve manually on the automatic
router.) The probability of successful routing can be predicted by analyzing some statistics of the design.
Because the nets are RC trees, delays are not a simple
function of capacitive load as with mask-programmed gate
4-5

398

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 24, No.2, APRIL 1939

arrays. Nevertheless, we are able to quickly calculate precise delays at each input for post-layout simulation and
timing verification.

ACKNOWLEDGMENT

The authors gratefully acknowledge the technical contributions of J. Chang, D. Gluss, R. Guo, D. How, and F.
Sohail.

REFERENCES

[IJ
[2J
[3)
[4J
[5)

Eric Rogoyski received the B.S. degree in mathematics from the State University of New York at
Stony Brook in 1972.
He was at IBM Corporation from 1974 to
1982 with his last position in EDS at East
Fishkill, NY. He held various positions in physical design from 1982 to 1984 at the company he
co-founded, California Automated Design Inc.,
and from 1984 to 1986 at Mentor Graphics
Corporation. He is currently a software consultant at Actel Corporation, Sunnyvale, CA, supporting the architectural development and physical design of Actel's
configurable technology.

Abbas EI Garnal (S'71-M'73-SM'83) received
the B.Sc. degree in electrical engineering from
Cairo University, Egypt, in 1972, and the M.Sc.
degree in statistics and the Ph.D. degree in electrical engineering both from Stanford University,
Stanford, CA, in 1977 and 1978, respectively.
From 1978 to 1980 he was an Assistant Professor of electrical engineering at the University of
Southern California, Los Angeles. Since 1980 he
has been with the Electrical Engineering Department of Stanford University where he is currently an Associate Professor. From 1984 to 1986 he was Director of the
Systems Research Laboratory, LSI Logic Corporation, Milpitas, CA. He
is a co-founder and Chief Scientist of Actel Corporation, Sunnyvale, CA.

Khaled A. EI-Ayat received the B.Sc. degree in
electrical engineering from the University of
Cairo, Egypt, in 1968, the M.Sc. degree in electrical engineering and computer science from the
University of Toronto, Canada, in 1971, and the
Ph.D. degree in electrical engineering and computer science from the University of California,
Santa Barbara, in 1977.
In May 1977 he joined Intel Corporation,
Santa Clara, CA, to work in the Microprocessor
Design Group, where he worked on the definition and development of industry standard microprocessor families such
as 8086, 80186, and 80386. As a Project Manager at Intel, he was
responsible for the design of the control structures of the 80386 Microprocessor. After leaving Intel, he cofounded Actel Corporation in Sunnyvale, CA, and was the Program Manager responsible for development of
electrically configurable gate arrays. His present research interests include
configurable logic and application-specific architectures, VLSI design,
and microprocessor architectures. He has authored many articles and
holds patents covering Actei's architecture and testability techniques.
Presently he is a Chief Engineer working on the definition of the next
generation of products.

Jonathan Greene received the Sc.B. degree in
biology from Brown University, Providence, RI,
and the Ph.D. degree in electrical engineering
from Stanford University, Stanford, CA, in 1983,
where he performed research on configurable
VLSI arrays, VLSI complexity, and information
theory.
During 1984 he was with Hewlett-Packard
Laboratories. From 1984 to 1986 he worked on
cell design automation and module compilation
at the LSI Logic Systems Research Laboratory'
in Palo Alto, CA. He is currently Manager of System Architecture at
Actei Corporation, Sunnyvale, CA.

Arnr Mohsen (S'72-M'74-SM'84) received the
Ph.D. degree in electrical engineering and applied physics from the California Institute of
Technology, Pasadena.
He is the founder, President, and Chief Executive Officer of Actel Corporation, Sunnyvale,
CA, and has more than 20 years of experience in
the semiconductor industry. Before founding Actel, he was a Senior Engineering Manager in the
technology division at Intel Corporation. He also
worked on charge-coupled device development at
Bell Laboratories and served as a consultant. He has authored more than
45 articles relating to semiconductors and is responsible for inventions
covered by 20 patents.

[6)

4-6

S. Wong, H. So, C. Hung, and J. Ou, "CMOS erasable programmable logic with z.ero standby power," in ISSCC Dig. Tech.
Papers, Feb. 1986, pp. 242-243.
H. Hsieh et al., "A second generation user programmable gate
array," in Proc. Custom Integrated Circuits Con/., May 1987, pp.
515-521.
A. El Gamal, K. El-Ayat, and A. Mohsen. "Programmable interconnect architecture," pending U.S. patent.
E. Hamdy et al., "Dielectric based anti fuse for logic and memory
ICs," in lEDM Tech. Dig. (San Francisco, CA), 1988, pp. 786-789.
K. El-Ayat et al., "A CMOS electrically configurable gate array," in
ISSCC Dig. Tech. Papers, Feb. 1988, pp. 76-77.
B. Osann and A. El Gamal, "Compare ASIC capacities with gate
array benchmarks," Electron. Des., vol. 36, no. 23, pp. 93-98, Oct.
13, 1988.

Justin Reyneri received the B.S. and M.S.E.E.
mathematics degrees from Stanford University,
Stanford, CA, in 1978, and the Ph.D. degree in
electrical engineering, also from Stanford, in
1985, having done research in cryptology and
information theory.
He is now Manager of System Development at
Actel Corporation, Sunnyvale, CA, where he has
worked since 1986. Prior to that he worked at
LSI Logic's System Research Laboratory on automated data-path layout, and at Hellman Associates on communications security systems.

~•

Article Reprint 4

DIELECTRIC BASED ANTIFUSE
FOR LOGIC AND MEMORY ICS
by Esmat Hamdy, John McCollum, Shih-ou Chen,
Steve Chiang, Shafy Eltoukhy, Jim Chang,
Ted Speers, Amr Mohsen

I

A paper presented at the
International Electron Devices Meeting, 1988
©

1992 Actel Corporation

4-7

DIELECTRIC BASED ANTIFUSE FOR LOGIC AND "E"ORY

IC ••

Es.at Haady, John "oCollua, Shih-ou Chen, Steve Chiang,
Shafy Eltoukhy, Ji. Chane, Ted Speers, Aar "ohsen

Actel Corporation, 955 East Arques Ave., Sunnyvale CA 94088

ABSTRACT
This paper
describes
a
Proeraaaable
Low
lapedanee Circuit £leaent  100M OHMS

Fig.(3) Photomicrograph of 64K PROM

Fig.(l) SEM cross-section of antifuse.

~
~

III

20 f18

CJ

i!
S
>

15 l-

CJ

j

10 I-

2

ca::

8a::
Do

I-

100

200

300

400

PROGRAMMING TIME

500

~s)

Fig.(4) Programming time of antifuse
with l8V programming voltage.

Fig.(2) Photomicrograph of 2000 gate
programmable gate array.

788-IEDM88
4-10

Article Reprint 4

Programmed Antlfuae Realatance Hlatogram

Kelvin StrucUe

70'....-,(..1

~

10

0

10

S
Dlff.

ao

.

10

..

to

~

... , 02

4

,

Qnd

~~~~--~~~~

Poly

1

0

~.v

0
L...--

tOOIOOIOOnoIOOttDOtIOOtIOO1fOOtIOO
Programmed AntlfuM RMletance (ofwIa)

Fig.(8) Antifuse Kelvin structure.

Fig.(5) Programmed antifuse resistance
histogram, programmed with 5 rnA current.
1~r-----------------------------------~

ANTIFUSE ACCELERATED LIFETEST
250C 5mA TEST
12

W

I/)
:;)

8GO

i=

!

7

10

Z

r

rt

C

&00

§

.#

I

11

LL.

I

W

:J:
l-

J

I/)
I/)

400

0

I

II:

Ii!

0

1:>

C

200

-

w

CJ
C

I~

0

>

10

24 48 72 N 120 144 168112216240 264 288 312 336 360 384 408 432 456

•

Fusing Current Ip (mA)
ELAPSED TIME (HOURS)

Fig.(6) Programmed antifuse resistance
versus programming current.
R

Fig.(9) Voltage across antifuse versus
stress tim-e, with 5 rnA stress current.

(0)

11V

10V

8V

8V

7V

10

1.000
&+OS

,...

.1000

4Oy.....

,"~
~

.M ~

...

1

~/~ ~ IIiIIIo.

r'IIII ~

-

........ ~

E

-r-

~

10.00

11

1.0,...

~

Fig.(7) Programmed antifuse resistance
versus reading current, with 100 ohms of
parasitic resistance in series.

lIE (cmlllV)

Fig.(lO) Time to breakdown versus inverse
electric field.

IEDM 88-789
4-11

4-12

Article Reprint 9

OXIDE-NITRIDE-OXIDE
ANTIFUSE RELIABILITY
by Steve Chiang, Roger Wang, Jacob Chen, Ken Hayes, John
McCollum, Esmat Hamdy of Actel Corp., Sunnyvale, CA and
Chenming Hu of the Dept. of Electrical Engineering and
Computer Science, u.c. Berkeley, Berkeley, CA

I

Reprinted from
RELIABILITY PHYSICS 1990 28TH ANNUAL
PROCEEDINGS, IEEE

©

1992 Actel Corporation

4-13

oxide-Nit ride-Oxide Antifuse Reliability
steve Chiang, Roger wang, Jacob Chen, Ken Hayes, John McCollum, Esmat Hamdy, Chenming HU*
Actel Corp.

955 E. Arques Ave. sunnyvale, CA 94086
Phone:(408)739-1010

*Department of Electrical Engineering and computer Science U.C. Berkeley, Berkeley, CA 94720

Abstract

40 year lifespan, the programming yield is
excellent, and the programmed antifuse is not
subject to any measurable electromigration.
The weakest link in the technology is not the
antifuse, but typical CMOS process limitations.

Compact, low-resistance oxide-nit ride-oxide
antifuses are studied for TDDB, program disturb, programmed anti fuse resistance stabi 1ity, and effective screen.
aNa antifuse is
superior to oxide anti fuse.
No aNa anti fuse
failures were observed in 1.8 million accelerated burn-in device-hours accumulated on
1108 product units.
This is in agreement
with the l/E field acceleration model.

Antifuse structure
The aNa anti fuse is sandwiched between N+
diffusion and N+ poly-silicon gate to form a
very dense array with density limited by
metal pitches (Fig. 2).
A thin layer of oxide is thermally grown on top of the N+ surf ace, followed by LPCVD ni tride, and the reoxidized top oxide.
The target electrical
thickness of the combined layer is equivalent
to 9nm of silicon dioxide.

Introduction
Field programmable gate arrays has been a
fast growing field only recently [1].
The
key to thei r configurabi li ty is the development of a programmabl e interconnect el ement.
This element should have small area, low post
programming
resistance,
and
be
rei iabl e.
Many known interconnect elements have been
used, including SRAMs, EPROMs, and EEPROMs.
Problems encountered
using
these
elements
are: large area, high resistance, or inefficient utilization due to circuit complexity.
The antifuse
approach,
however,
has
some
unique and attractive features.
Since it is
only a two terminal device, the area required
is small, and the simple two terminal resistor structure allows simple and efficient
routing schemes [2]. The programmed anti fuse
has very low resistance.
It was found that
oxide-nitride-oxide (aNa) antifuses have a
lower and
tighter
resistance
distribution
than that of oxide antifuses (Fig. 1). The
choice of antifuse material has further improved both the yield and the reliability
'over that of oxide antifuses.
In addition,
ONO is highly radiation resistant.
Initial
evaluation results
indicate
that
products
containing aNa antifuses can withstand 1.5
million rads [3].
The technology and performance characteristics of the aNa anti fuse has
been previously described [4].
In this paper, we wi 11 report the rei iabi 1 i ty characterization of the aNa antifuse.

TDDB of Unprogrammed Antifuaes at S.SV
For the sub 10 nm ONO thickness, time-dependent-dielectic-breakdown (TDDB) reliabili ty over 40 years is an important consideration.
The very first task in determining the
feasibility of the antifuse was to examine
its TDDB reliability.
Typical
electrical
field and temperature accelerated tests were
done in order to extrapolate the diel ectric
lifetime under normal operating conditions.
Based on the oxide study [5], it was reported
that there may be different field dependencies of 1 i fetime in high field (>6MV I cm) and
in low field «5MV/cm) regimes.
In the case
of aNa anti fuses, the S. sv operating field is
already over 6MV/cm.
The extrapolated data
from the high field regime was therefore assumed accurate.
This assumption was later
confirmed with device burn-in data.

Field Acceleration (E va liE model for ONO)
200X200 um 2 (0.04mm 2 ) area capacitors were
packaged and then stressed at different voltages.
aNa thickness ranging from 8nm to
9.5nm were studied.
The test splits and sample sizes are summarized in Table 1.
The
TDDB distribution at each vol tage condition
is shown in Fig. 3.

We wi 11 discuss three di f ferent types of
antifuse reliability.
The first is that the
unprogrammed anti fuse has to survive a 5. 5v
40 year operating condition.
The second is
that during
programming,
all
unprogrammed
antifuses are subject to a momentary stress
of half the programming voltage (vpp/2).
The
programming yield is required to match or exceed PAL yields which are in excess of 99%.
The third is that programmed antifuses should
have a very low resistance, which will not
increase in value over the life of the part.
As will
be shown below,
the unprogrammed
antifuse is reliable, well in excess of the

CH2787·0/90/0000-0186$01.00 c 1990 IEEE/IRPS

4-14

In the literature,
the oxide intrinsic
1 i fetime
has
been
observed
to
have
an
exp(l/E)
dependence,
which
is
explained
mainly with
the
Fowler-Nordheim tunneling
mechanism [6].
Oxide Log( r) curves and lifetime Lo9(t SO ) curves exhibit a linear function of
liE behavior.
On the other hand,
nitride Log(I) has been shown to follow the
Frenkel Poole behavior (,[E) [7].
Log( I)
of
aNa
is
not
a
1 inear
function
of
liE
(Fig. 4a).
Rather, it more closely follows E

186

Article Reprint 9

4b).
Also, several studies have fitted
lifetime of ONO to an E model [8,9].

(Fig.

Program Disturb and Screen

Neverthel ess a careful examination of our
data revealed that TDDB lifetime of ONO foIlows the liE model (Fig. 5) better than the E
model (Fig. 6).
This is in agreement w1th
concl usions from one study [10], but in contradiction with others which did not examine
the fit between data and the liE model [8,9].
Based on our observation, we found that the E
model can fi t the data well over 4 to 5 orders of magni tude of time span.
However, as
time span increases to 7 orders of magnitude,
the E model is clearly inadequate (F1g. 6).

Since there is no theoretical basis for ONO
to follow the liE model or the E model, we
tried a
statistical approach
to find
out
which model can best fit the data.
First,
the data is fitted to different field dependent models of exp(E n ) with n ranging from
-1.5
to 1 at
0.5
intervals.
Then
the
correlation
coefficient
1S
compared
for
different models in F'ig. 7.
The residual
comparison is shown in Fig. 8. Again, the E
model (n=l) turns out not to be a good fit
for the data.
The best fit appears to be
n = -.5 or -1.
This seems to suggest that
ONO behavior is similar to oxide (n = -1).
But,
the addition of nitride (n=0.5)
has
changed the n to between -0.5 to -1.
Which
of the two exponents, n=-0.5 or -1, should be
used
may
depend
on
the
ONO
process1ng
conditions.
The
difference
between
extrapolated
lifetime
based
on these
two
models is not nearly as
dramatic as
the
choice between E and liE.
At 5.5V,
the
di f ference
in
the
extrapol ated
lifetime
between n=
-0.5
and
-1 1S
one order
of
magnitude in time.
On the other hand, the
difference between n=l and -1 is 5 orders of
magnitude.
In the subsequent analysis, we
will use LIE model exclusively for slmpl1ci ty. The concl usion reached wi 11 not change
much i f the l/~E model were to be used.
Besides the 0.04mm2 area capacitor data, we
also did a TDDB study on single anti fuses
(3.2um 2 ) and ACT 1010 product antifuse arrays

During programming, all anti fuse electrodes
are precharged at a given voltage, Vpre.
To
program the antifuse, its poly-silicon electrode is raised to vpp while its N+ diffusion
is grounded.
The unsel ected anti fuses are
subjected to the stress of either Vpre to
ground or vpp to Vpre for an average of 100
t1mes the single ant1fuse programing time.
usual 1 y the vpre is set such that stress is
approximately Vpp/2. If defective unselected
antifuses fail
(become
programmed) due
to
this stress, they will show up as programming
fai 1 ures.
These defective anti fuses can be
screened out at wafer sort by a 1 second
stress at 10 volts (lOV/ls).
This screen is
done tWIce during sort.
The first IOv/ls
(FS-I) screens out the defective dielectric
distribution.
The
second
lOV/ls
stress
(FS-2)
simulates
the
percent
yield
loss
during programming.
In Fig. 13, it shows a
typ1cal wafer trend on the fai 1 ure rate of
both fll:St and second stress.
The 10 run
average of Fs-2 is 0.3 %.
This suggests that
the programming failure loss due to anti fuse
defects after the screen shaul d be 1 ess than
0.3%.
Unlike floating gate EPROMs and EEPROMs,
latent ONO defects can be easily screened out
with a voltage stress as described above.
This ~s one more advantage of the antifuse
structure as a programming el ement.
Once an
antifuse has passed the voltage screen at
sort, it is very reliable.
Based on either
liE or
l/~E
model,
the lOV/ls stress
is
equivalent to a stress time at S.sv well over
40 years.
We have calculated the equivalent
product failure rate at 5.5v as a function of
the I:'S-2 screen Y1eld loss.
It shows that
for an Fs-2 of 0.5%, the equivalent FITs at
S.5V 125"C is less than 50, which is consistent with the results mentioned at the end of
the previous sectIon.

Programmed Antifuae Reliability
Once the antifuse is programmed and forms a
low resistance path, the resistance should
remain low.
In the case of oxide, it is a
known fact that they are susceptible to self
healing [11]
or an increase In resistance
wi th tIme.
This is not the case for ONO as
will be shown In the followIng section.

(O.36mm 2 ).
Results
are shown
in FIg.
9.
Agaln, the data follows the liE model well
for all different area sizes.

Temperature Acceleration
The temperature effect on the O. 04mm 2 ONO
area capaci tor 1 i fet1me is shown in F1g. 10.
The activation energy as a function of the
electrical f1eld IS shown In F1g. 11.
A
field dependent activation energy has been
reported for oxide TDDB lifet1me, as well.

A four terminal Kelvin structure was used
for the reliabllity study (Fig. 14).
A constant SmA current, which 1S much larger than
the operating current, was passed through the
antlfuse at 2S0"c
(through terminals A,B)
wh1le the voltage across the antifuse was
moni tared between terminal s A and B.
A typical vol tage vs time graph is shown in Fig.
15.
A sudden ~ncrease in vol tage indicates
that an open c1rcuit has formed.
Prior to
that, there 1S no significant change in the
vol tage across the anti fuse indicating that
the resistance remained low.

For the 5.5 volt lifetime estimate, the activation
energy
IS
close
to
0.geV
(l/E
model).
Using this estimate and the product
TDDB defect distribution (Fig. 12), the 1%
failure lifetime at 5.5V 1S well
over 40
years.
The projected product ant1 fuse faILure rate (contain1ng lOOK to 200K anti fuses)
is less than 50 FITS at 125'C.

Next, electric cont~nuity measurement and
scann1ng electron microscopy (SEM) were done
on the KelVIn structure.
It was found that

187

4-15

II

the antifuse resistance still remained low
when measured from the other two unstressed
terminals C and D.
This is the case for all
samples tested under this condition.
SEM
analysis showed that the open circuit was related to the metal to poly contact electromigration failure (Fig. 16).
The activation
energy (based on 250'C and 200"C data) for
the contact electromigration is 1.leV, which
is in agreement with typical values obtained
from contact electromigration failures [12].
The extrapolated
lifetime
of contacts
in
these circuits under normal operating conditions is well in excess of 40 years.
The
real lifetime of a programmed antifuse itself
is yet to be determined.

References
[1] A. Haines, "Field-Programmable Gate Array with Non-Volatile Configuration", Microprocessors and Microsystems, Vol. 13, No.5,
pp. 305-312, June, 1989.
[2] A. El GamaL J. Greene, J. Reyneri, E.
Rogoyski, K. El-ayat, and A. Mohsen, "An Architecture for Electrically Configurable Arrays", IEEE J. Sol id-state Circuits. Vol 24,
No.2 pp. 394-398, Apr. 1989.
[3]
Preliminary data from a military system
manufacturer. Test done on total dose Gamma
Irradiation Survivability Test.
[4] E. Hamdy, J. McCollum, S. Chen, S. chiang, S. ELtoukhy, J. Chang, T. Speers, A.
Mohsen,
"
Dielectric Based Antifuses
for
Logic and Memory ICs", IEDM Tech. Digest, pp.
786-789, 1988.

High Temperature Product Burn-in Life Data
In previous sections, it was demonstrated
that the extrapolated aNa antifuse lifetime
follows the l/E model instead of the E model.
Product burn-in data supports this conclusion. ll08 units (including PROMs, ACTI010,
and ACTI020) containing an average of about
lOOK anti fuses per unit, about 5% of which
were programmed, underwent dynamic burn-in at
12S'C and 5.5V with roughly an accumulated
1.8 million device hours.
No antifuse failure has been observed while two CMOS circuit
failures have been observed and identified in
the peripheral circuitry.
This data is consistent with
the
failure
rate
projection
based on liE extrapolation, while the E model
extrapolation based on 'l'DDB test data would
have projected 90 uni t fai lures (out of 1108
units) due to aNa antifuses.

[5] K. Boyko, D. Gerlach, "Time Dependent Dielectric Breakdown of 210 A Oxides", Proc.
Int. Rei. phys. Symp.
pp. 1-8, 1989.
[6] 1. Chen, S. Holland, C. Hu, "Electric
Breakdown in Thin Gate and Tunneling Oxides",
IEEE Trans. Electron Devices, ED-32, No.2,
pp. 413-422. Feb. 1985.
[7] S. Sze, "Physics of Semiconductor devices", 2nd Edition, John Wiley and Sons,Inc.
pp 402-407,
1981.
[8] A. Nishimura, S. Murata, S. Kuroda, O.
Enomoto, H. Ki tagawa, and S. Hasegawa, "Long
Term Reliabi li ty of si02/siN/sio2 Thin Layer
Insulator Formed in 9 urn Deep Trench on High
Boron Concentrated Silicon", Proc. Int. ReI.
phys. Symp. pp. 158-162, 1989.

Conclusions
We have investigated three reliability aspects of the aNa anti fuses.
During operation, the lifetime of the aNa antifuse is
well in excess of 40 years at el evated temperatures.
It has been further demonstrated
that the E model is not adequate for lifetime
extrapolation.
Results indicate that liE is
a better choice.
The key to successful extrapolation is that data should span over
seven orders of magni tude in time.
Based on
the liE model, the extrapolated lifetime is
well over 40 years at 5. 5V.
To screen out
the programming yield loss due to breakdowns
of defective unsel ected anti fuses, a screen
was developed.
This is not a yield limiting
factor in the typical process as the yield
loss due to the screen on the average is 1%.
After the screen, the programming yield is
higher than 99%.
The reliability of programmed aNa antifuses was also studied. It
was found that the lifetime is limited by the
contact electromigration,
not
by the aNa
anti fuse.
In
addition,
the
resistance
remains low throughout the test indicating
the anti fuse resistance does not increase.
Finally, more than 1100 product units and
over 1.8 million unit hours of burn-in data
have shown no fai lure at all that can be
attributed to the ONO antifuses.
This is in
agreement with the prediction based on waferlevel tests and the liE model.

[9] Y. Ohji, T. Kusaka, 1. Yoshida, A. Hiraiwa, K. Yagi, and K. Mukai, and o. Kasahara, "Reliability of Nano-Meter Thick MultiLayer Dielectric Films on Poly-Crystalline
Silicon", Proc. Int. ReI. phys. Symp. pp. 5559, 1987.
[10] P. Hiergeist, A. Spitzer, and S. Rohl,
"Lifetime of
Thin Oxide-Nitride-Oxide Dielectrics
within
Trench
Capacitors
for
DRAM's", Trans. Electron devices, Vol. 36,
No.5, pp. 913-919, May, 1989.
[11]
D.
Walters,
J.
van
"Dielectric Breakdown in MOS
I,ll, III", Phillips J. Res.
115-192, 1985.

[12] D.S. Peck and 0.0. Trapp, "Accelerated
Testing Handbook", pp. 5-36 to 5-37, 1987.

188

4-16

der
School,
Devices, Part
Vol. 40, pp.

Article Reprint 9

Table 1 Field accelerated test data for two lots with thickness ranging from Som to 9.5nm. The
test was done on 0.04mm2 area capacitor.
Lot B

Lot A
Voltage
(V)

Tox

13.5
12.5
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0

8.3
8.3
8.3
8.3
8.4
8.4
8.3
8.3
8.3
8.3
8.3

(om)

# of cap

E-field
(MV/cm)

16.2
15.1
14.4
13.8
13.1
12.5
12.0
1l.4
10.7
10.2
9.6

22
22
22
22
22
9
6
6
36
15
59

Sub-total of tested cap.
Total of tested cap.
Table 2
Device

PROM64
1003JLCC
1010JLCC
1020JLCC
1010PLCC
1020PLCC
Total

*

t50
(sec)
4.2e-3
3.7e-2
1.5e-1
8.6e-1
4.7eO
5.8e1
3.2e2
2.5e3
2.5e4
2.3e5
1.5e6

Voltage
(V)

Tox

E-field

(om)

(MV/cm)

14.0
13.0
12.5
12.0
11.4
11.2
10.8
10.2
9.7
9.0
9.0

8.7
S.7
8.7
S.7
8.7
8.7
9.0
9.0
9.0
8.7
9.3

, of cap.
25
25
25
25
25
45
45
45
45
32
32

15.9
14.9
14.3
13.7
13.1
12.5
12.0
1l.3
10.8
10.3
9.7

t50
(sec)
9.8e-3
5.0e-2
2.4e-1
1.3eO
9.0eO
8.0e1
3.52e2
2.88e3
2.07e4
3.35e5
2.22e6

401

241
642

High temperature operating life test data (HTOL).
Device Hours
@ 125°C/5. SV*

# fuse
Fail

Equivalent
Device Hours
@ 55°C

65,536
40,000
112,000
186,000
112,000
186,000

450,000
359,400
283,000
90,000
616,000
5,300

0

°00
°a

18.8 Million
15.0
11.8
3.8
25.8
.2

°

701,536

1,804,100

a

75.5 Million

# of
units

# of fuse
per unit

275
238
144
61
358
32
1108

All PLCC, 114/144 of 1010 JLCC and 32/61 of 1020 JLCC have 5.75V.

•

Vf...ROCAL TRACKS
METAl VPOl.Y

I
LOGIC IIiO

60
.ONO

ouu

"

1

I

~OXIDE

50

"

I

I

-Y

-c~

'-i-J/
C-/

~

30

10

200

600

1000

HOO

I

Anlifuse Res/slance (ohms)

Fig.
2
showing
antifuse
selected
Vpp/2 or

Fig. 1 ONO antifuse has a tighter resistance
distribution than oxide antifuse.

J
~

v,.f
Vpj>12

ETA&. ,<>12

S~plified
product
architecture
logic modules, routing tracks, and
arrays. Vpp is applied to program a
antifuse.
Unselected antifuses have
OV stress.

189
4-17

TOOB C.eel

1.0e-08 .:.T~DD=B::(.::.:::ol:""""_ _ _ _ _ _ _ _ _ _ _ _U;ii::1
~l>l>l>l>

1.0e-07
tOE-08

AAA~OOOO

tOE-oe

o

1.0E-02
1.0e-Ol
1.0E-00
1.0E-Ol
1.0E-02

10.3

-II e~)O()(X X

X

)(XXX~OOO

0

r'r._._._.~*

* .**

~

11 ••

1.0e-04
1.0e-03

** *

,rH111111+++++ +
+++H'I'
+ ++
................ .

1.0E-02
1.0E-Ol

+

1.0E-00
1.0E-Ol

... -

1.0E-03

Lot"

1.0e-08
1.0E-oe

~t

000

+

1.0e-07

000

tOE-04
1.0E-03

0

1.0E-OB

'.7

1.0E-040!!...1-....lJ12L-...J.-l.l..0-2::!-:.O,....f..0::-:.~0.::!-:.O~.O~70:-:.~0-.-::O:--:';--;~~;;!'

Fig. 3 Cumulative percentage failure verses
time on a log-normal scale.

0

8

Cumulative Failure (%)

10

II

12

100/E (em/MV)

O.04mm2

Fig. 5 Log tso vs lIE for two lots.
area capacitor was used.

1.0E_08T
.!-D~D~B~(s~ec~)~_ _ _ _ _ _ _ _ _ _ _ _--,

+

1.0E-07

Lot A

0 Lot B

1.0E-08
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-Ol
1.0e-00
1.0E-Ol
1.0E-02
1.0e-03 L-'---'---.L.---'----'---..L--.1.1.-~18---=:17
B
w ft
n
~
«
g

E (MV/cm)

******

GRAPHICS
******
o . o~-c! .J-EPLOT
MOCEl.

Fig. 6 Log tso vs E for two lots.
has a similar E dependence.

Log tl0

Correlation Coelllclent(R aqaure)
0.90 ;:..::.==::.:...:.:.::.:..:..:.:.:..:..:...:..:.-:....:..:~...:...-----------,
0.988
0.988

*

*

*

0.984
0.982
0.98

*

0.978

*

0.978 L_.......I_ _-'-_ _-'--_--''--_--'-_ _-'-_ _
~

~

~

~

0

~

u

n(exponent of E field dependence)

Fig. 4 I-V characteristics of oxide, nitride,
and ONO.
(a) Fowler-Nordheim tunneling plot.
(b) J vs E plot.
Log (J) of ONO is not a
linear function of lIE I-V.

Fig.
7 tso was fitted to 5 different
distributions.
The fitting
correlation
coefficient (R2) is plotted against the field
exponent n in [exp(En)].
l/E(n= -1) has the
best
fit
with
the
largest
correlation
coefficient.
190

4-18

Article Reprint 9
0.5 ~A~ct~iv~a~ti~On~En~e~rg~y:..:(~e.::v)~-----------1

2~R~eS~id~u~a~ls~[J~n(~td~b~IJ_ _ _ _ _ _ _ _ _ _ _ _ _~

n'l

0.5

0 .•

-0.5
0.5

0.3

-1

-1.5

0.2

-0.5
-1

0.1

-1.5

0~--~---.L-----J-----~1~--~1~1-----:12

-29L--~10~--Jl1--~12--~~-~I.~-JI5--~18-~17

8811

Fig_ 8 Residuals at each data point are
plotted for 5 different n's.
E field
dependence has the largest residuals.
liE
and 1/~have the smallest residuals

Fig. 11. Field dependence of
energy.

activation

1.0E·03
I.OE·02

~".~

~

•

ONO

1.0E.0. ;:TI~m~I~lo~b:.r::I.::kd~o::w..:::n(:.:I.::c~)_ _ _ _ _ _ _ _ _ _- ,

1.0E+l0 ,;.T.:.DD::.B::...:.(s:.:e:..:c::...>_ _ _ _ _ _ _ _ _ _ _ _ _ _-,
40 YEARS
1.0E·09
1.0E·08
Singi. FUI.: 3.2um2
1.0E·07
Capacl1or: 0.04mm2
1.0E·08
1010 Producl: 0.35mm2
1.0E·05
1.0E·0.
1.0E·03
1.0E·02
1.0E·Ol
1.0E·00
1.0E-Ol
1.0E-02
1.0E-03
1.0E -0. L_-'--_--'-_---'~_.L__
7
8

0

100/E (cm/MV)

E-Field (MV Icm)

I.OE·OI
1.0E·OO
I·.OE-Ol

Singlo FulO

X

_'__
II

Product
12

.l...__..J

__I. _ _

10

11

e

10

20 aO<0101070 10

.0

8G

....

• •••

Cumulative failure (%)

12

100/E (cm/MV)

Fig. 9 Log tso can be fit as a linear
function of liE with the same slope for three
different structures: single fuse (3. 2um2 ) ,
area cafacitor (0. 04mm 2 ), and product array
(O.35mm ) .

Fig. 12. Cumulative percenta~e failure o~
product antifuse array (0.3Smm ) vs breakdown
time at IlV stress.
.. Fallure(Arbltary Unit)
..... F8-'
-e- F8-2

1.0E.07 ,;T.::D.::OB::....::(s:.:e:..:c::...>_ _ _ _ _ _ _ _ _ _ _ _ __

11.8

1010 Product
10 Run Average lor FS-2: 0.3'10

~)(_--.-..-;-----lL------

14.3 e~---+_---4------"
Wafer No.
2.8

2.8

3

3.2

3 .•

1000/T (lIKelvin)

Fig. 13 A typical wafer sort yield loss plot
for one lot.
After the screen, the 10 run
average yield loss is less than 0.3%. Since

Fig. 10. Field effect on tso at different
temperatures ranging from 25°C to 150°C.

the screen ia more aevere than 5.5V/40 yearl,
the product will be very reliable throughout
the operating lifetime.
191
4-19

•

C

Antifuse

Diffusion

+

D
0

A

R
Poly

Fig. 14 A four terminal Kelvin structure is
used for programmed antifuse reliability
test.
When an open failure is detected
tnrough two stressed terminals, A and B, the
antifuse resistance remains low as measured
tnrough two unstressed terminals, C and D.

W

(/)

~

~

12
11

r

2S00C. SmA Test

10

Fig.
16
SEM photograph
of
the
Kelvin
structure after showing an open circuit. The
open is identified to be at poly to metal
contact due to contact electromigration.

~

t

<
W
j:
~
0

a:
0

<

w

;...,.,.,01

Cl

<

~

0

>
24

~

72 86 120 144 168

1~2

216 240264 28S3123343603S4 408432 458

ELAPSED TIME (HOURS)

Fig. 15 Voltage across antifuse versus stress
time, with SmA current. Antifuse resistances
remains little changed prior to contact
failure.

192

4-20

Article Reprint 10

AN FPGA FAMILY OPTIMIZED
FOR HIGH DENSITIES AND
REDUCED ROUTING DELAY
by Mike Ahrens, Abbas El Gamal, Doug Galbraith,
Jonathan Greene, Sinan Kaptanoglu, K.R. Dharmarajan,
Lynn Hutchings, Sifuei Ku, Phil McGibney, John McGowan,
Amer Samie, Kitty Shaw, Norma Stiawalt, Telle Whitney,
Tom Wong, Wayne Wong, Bortay Wu
of Actel Corp., Sunnyvale, CA

I

Reprinted from
IEEE 1990 CUSTOM INTEGRATED CIRCUITS
CONFERENCE PROCEEDINGS
©

1992 Actel Corporation

4-21

Reprinted from PROCEEDINGS OF THE IEEE 1990 CUSTOM INTEGRATED
CIRCUITS CONFERENCE, Boston, Massachusetts, May 13-16, 1990

An FPGA Family Optimized for High Densities and Reduced Routing Delay
Mike Ahrens, Abbas El Gamal, Doug Galbraith, Jonathan Greene, Sinan Kaptanoglu
K.R. Dharmarajan, Lynn Hutchings, Sifuei Ku, Phil McGibney, John McGowan, Amer Samie
Kitty Shaw, Norma Stiawalt, TeUe Whitney, Tom Wong, Wayne Wong, Bortay Wu

Actel Corporation
955 E. Arques Ave.
Sunnyvale, California 94086

ABSTRACT: The Act-2 family of CMOS FieldProgrammable Gate Arrays uses an electrically programmable
"antifuse" and new architectural and circuit features to obtain
higher logic densities while increasing speed and routability.
Improvements include: two new logic modules, novel 10 and
clock driver circuitry, and more flexible and faster routing
paths. New addressing circuitry shortens programming time
and speeds complete testing for shorts, opens and stuck-at
faults. Fully automatic placement and complete routing are
retained. Special software tools used for architectural
exploration and layout generation are noted.

1. Introduction.
Previous papers described an architecture for fieldprogrammable
gate arrays (FPGAs)
[1], and its
implementation in the Act-l FPGA circuits [2]. These
demonstrate that user programmability can be obtained
without sacrificing the application flexibility of a channeled
gate array architecture.
This paper describes new architectural features, circuit
techniques and software that approximately double system
speeds, and are capable of extending the architecture to logic
densities of 8,000 gates in 1.2 micron technology and to
approximately 16,000 gates for 0.8 micron. (Note that these
gate counts are based on the capacity of an equivalent maskprogrammed gate array. Other measures would yield higher
values.) The circuits employ a one-time electrically
programmable "antifuse" offering small area and capacitance,
and low resistance once programmed [3].
As before, the architecture consists of rows of logic
modules separated by horizontal channels. This organization
is similar to that of a channeled gate array, except that
instead of an area for custom metallization the channels
contain wiring segments of various lengths which can be
connected by antifuses.
A key goal was to insure complete automatic placement
and routing with acceptable routing delays. This is facilitated
by the inherent flexibility of the channeled architecture and
the integration of large numbers of antifuses (700,000 or
more) on a single chip.

2. Logic Module
The choice of the logic module is critical to an FPGA
architecture. The module must be simple enough to pe,mit a
compact and high-speed circuit layout. Yet it must also be
flexible enough to accommodate the most frequently used
logic functions (macros) with several choices of routing. Our
approach is to evaluate many candidate modules against
macro usage statistics from actual applications. (The
philosophy is similar to that used to define the instruction set
of a RISC microprocessor. It has also recently been applied
to BiCMOS gate arrays [4].) To assist in this task, a program
has been developed that can enumerate all macros
accommodated by a given module in minutes [5].
The Act-l family uses one general-purpose module,
which implements all combinational functions of 2 inputs,
many of 3 or 4 inputs, and others ranging up to 8 inputs [1].
Any sequential macro can be configured from one or more
modules using appropriate feedback routings.
At higher logic densities, the law of averages makes
designs begin to adhere more closely to typical macro usage
statistics (see, e.g., [4]). This motivates the use of a mix of
two new modules, each of which is most efficient for a
different set of macros. The "C-module" is a modified
version of the Act-l module reoptimized to better
accommodate high-fan-in combinational macros, e.g. wider
AND gates, though with some loss in ability to accommodate
sequential functions. The S-module, on the other hand, is
optimized for configuring sequential macros. It can
accommodate a latch or flip-flop and/or many combinational
macros of one to seven inputs. Both transparent-high and
-low latches and rising- and falling-edge-triggered flip-flops
are possible.
The two-module scheme can reduce the number of
modules required for a block of logic by up to a factor of 3.
On average, logic density per module is increased by over
50%. Furthermore, because the density is increased, the
number of routed nets in a typical critical path is reduced.
This significantly improves speed. Fig. 1 shows how a
typical critical path in a state machine can be implemented to
take advantage of the wide fan-in of the C-module, and the
capabilities of the S-module. The delay paths include only
two routed nets. Performance data is summarized in Table 1.
Since the fan-in of each module is no larger than that of
a typical gate-array macro, the two-module scheme maintains

31.5.1
IEEE 1990 CUSTOM INTEGRATED CIRCUITS CONFERENCE

4-22

CH2860-5!90/0000-0166

©

1990 IEEE

Article Reprint 10

the generality of a "fine-grained" architecture. Significantly
larger and more specialized modules would risk a sharp loss
of efficiency for applications that deviate from typical usage
statistics. Using a larger module, or more types of modules,
also adds constraints to the placement and routing problem,
making automatic solution more difficult and ultimately
increasing net delay.

3. Input/Output
Of particular importance to system performance is the
delay between the time a clock signal changes at an input
pad and when data appears on an output pad, referred to as
TC/k-Q' (Memory bus interface applications are a good
example). The goal is to gain maximum speed without
sacrificing flexibility.
This is accomplished by providing a dedicated
transparent-high latch in each output path. If desired, the
dedicated latch can be combined with a transparent-low latch
configured from a logic module to form a rising edgetriggered flip-flop. (Note that the net connecting the two
latches is not in the critical path, so Tclk - Q is not increased
relative to having a dedicated flip-flop in each 10.) If flowthrough operation is desired, the output latch gate is simply
tied off to make the latch transparent.
To limit set-up time requirements, a dedicated
transparent-low latch is provided on each input path. The
polarities of the input and output latches are chosen so they
can be combined with each other, and possibly with other
internal latches or flip-flops, to form a path that is
functionally equivalent to a chain of rising-edge flip-flops.
(See Fig. 2.).
Chips with many simultaneously switching outputs
require some form of slew rate control to avoid noise
problems; several alternatives are possible. Sequencing the
operation of several parallel drivers limits the slope of the
current ramp when driving a passive load, but large di/dt can
occur in bus contention situations when the contending driver
suddenly shuts off. Feedback remedies this problem, but can
still allow large dildt in asynchronous systems where the
logic state changes before a transition is complete. Instead a
current mirror circuit was used to limit the drive current.

This results in lower dildt noise in worst case situations, a
simple way to implement programmable slew rate, and 90%
power efficiency. The output buffer meets the 4mA HCf
buss driver specification for AC, and the 6mA specification
in steady state when the current limit shuts off. ESD
protection is >2000V.
Connections between the array and the 10 pads are
made via special 10 modules interspersed with the logic
modules. The 10 module has inputs for data, slew control,
tristate, and separate gates for the input and output latches.
The gate inputs are not restricted to a dedicated clock signal,
but may each be driven from any pad or internal net.

4. Clock Distribution
Clock distribution is a problem in most large chips. In
an FPGA, where the load capacitance may be changed or
redistributed to suit each application, it is a greater challenge.
Special distribution networks are provided to deliver
high-fanout clock signals to the inputs of any logic or 10
module with minimal skew. Each network may be driven
directly from an input pad for high speed, or from userdefined internal logic. High speed and low power are
obtained by a distributed driver with 90% power efficiency.
Skew is further reduced by automatic placement
algorithms that balance the loading on each branch of the
distribution tree.
All clock inputs may also be routed in the normal way
instead, allowing many local asynchronous clock signals if
desired.

<6
5-7
8

•

<5
ad):

15-20

Table I: Performance Estimates.
(1.2 micron CMOS, typical process, 5 volts, 25 C).
A. Desired behavior:

B. Using latches and rising-edge-triggered flip-flops:

8-8-EJ-8-E]
, 10 module

' logic mod':es - - -

10

C. Using latches and faUing-edge-triggered flip-flops:

'10 module

m~ules

I

' - logic modules ,/

Legend:
RFF

Figure 1: part of a state machine implemented
in four C-modules and one S-module.

=rising-edge D flip-flop.

TIlL =

transparent-high latch.

FFF

=faIIing-edge D flip-flop.

1lL=

transparent-low latch.

Figure 2: 10 clocking--three equivalent implementations.

31.5.2
4-23

S. Routing Architecture
Each routing channel contains horizontal tracks divided
into segments of various lengths [1]. Surprisingly, the
restriction to segments of predefined length does not greatly
increase the number of tracks beyond what would be required
in the unrestricted case of mask-programmed channels [6].
In an efficient architecture it is inevitable that some
nets' routings will be slower than others. The use of a low
resistance switch, such as the antifuse, helps to narrow the
resulting delay distribution. Further improvements have been
obtained by a reduction in the maximum number of anti fuses
in the worst delay paths, as follows.
In the vertical direction, most nets are routed using a
short dedicated segment connected to the module's output
driver through an "isolation" transistor (Fig. 3). (The
transistor isolates the module circuitry from programming
voltages present on the segments). In this case, there are only
two antifuses plus the isolation device in the path from the
buffer to each input (input A in the figure).t Though this
favorable routing can be assured for speed critical nets,
generally some 5-10% of the other nets must be placed with
an input in some channel beyond the span of the dedicated

segment (input B, Fig. 3). In the past, this required use of an
uncommitted vertical segment and 4 antifuses.
Alteration of the order in which antifuses are
programmed and a robust driver circuit permit limited
programming of antifuses on the node connecting the driver
to the isolation device, without risk of device breakdown [7].
This allows direct connection of the driver to any of several
uncommitted vertical segments, as shown in Fig. 4. Since the
additional antifuse presents little more resistance than that of
the bypassed isolation device, the delay of these nets is not
much greater than those using dedicated segments. Prediction
of delays prior to placement (when it is not yet known which
nets require uncommitted segments) becomes more accurate
as well.
Segmented channels represent an unusual layout
challenge. They are as dense and large as a memory array,
yet not repetitive. (A carefully chosen but irregular mix of
segment lengths is provided for good routability.) For this
reason, a layout generation program was developed that
assembles the channels and modules automatically from the
same database used by the routing software. This permits
rapid layout of a family of arrays of various sizes by simply
rerunning the generator with the appropriate input files.

6. Placement and Routing Software
uncommitted vertical segment
horizontal segment in a ___
channel above the span
of the dedicated vertical
segment

'-........
--i~---~f---

/programmed anti-fuse
--~r-------~~-----

dedicated
vertical
_ segment
isolation
device,
Figure 3: Act-l Routing

Several new complexities are added to the placement
optimization problem. Macros must be placed in modules of
the appropriate type (C or S). Macros hooked to a clock
network should be distributed so as to balance the load on
the network's branches. There should not be excess demand
for uncommitted vertical segments within the same column.
Speed critical nets should be routed using only short
horizontal segments and dedicated vertical segments.
Nevertheless, new algorithms make it possible to satisfy
all these constraints. Nearly all designs with module
utilization under 85%, and most designs with utilization
under 95%, route without manual intervention. Table 2
summarizes results for several applications. Time for
complete placement and routing is about 45-60 minutes on a
68030-based workstation.

7. Programming and Testing
uncommitted vertical segment

/'

driver
dedicated
vertical
_ segment

The time required to program an antifuse falls
exponentially with the applied voltage.
To keep
programming time under 5-10 minutes for a chip with nearly
a million antifuses, new circuit designs were developed that
eliminate the threshold voltage drop along the path from the
chip's supply pad to the antifuse being programmed.
Changes have also been made in the addressing circuits.
The pass transistor scheme described in [1] is appropriate for
cases where there are many short segments in a track.
Two adjacent horizontal segments in the same ttack may be connected end-to-end by an antifuse to fonn a longer segment [IJ. For
good routability it is necessary to route some small percentage of
the nets in this way [6J. which adds an antifuse to the path. However. speed critical nets are routed without this additional antifuse.

isolation
device
Figure 4: Act-2 Routing

31.5.3
4 24

Article Reprint 10

However in larger chips the number of horizontal segments
per unit area decreases to the point that it is possible to
address each individual segment directly using only a small
proportion of area for the addressing circuitry [7]. The
reduction in the number of pass devices in the programming
path improves the programming current and lowers the
resistance of programmed antifuses, improving performance.
The pass transistor scheme is still used in the vertical
direction where tracks are highly segmented.
Direct addressing also reduces the time required to test
for breakdown of defective unselected antifuses during
programming. A complete test for unintended connections
between any two segments can be done after the conclusion
of programming (despite the fact that it is not possible to
uniquely address each individual antifuse once programming
commences). The number of vectors required is only
logarithmic in the number of nets. Previously, the test for
shorts required one or more vectors after each antifuse is
programmed.
Proper closure of a programmed antifuse is confirmed
by the passage of the programming current. Note that this
complete testing for shorts and opens, combined with
exhaustive testing of each logic and 10 module prior to
programming, is more thorough than even a so-called "100%
stuck-at fault coverage" test done on a conventional gate
array.
Once programming and testing are complete, no increase
in resistance of a programmed antifuse or false programming
of an unprogrammed antifuse have been observed in 1.8
million accelerated burn-in device-hours [8].
8. Other Circuit Improvements
The Act-l and Act-2 architectures allow user selection
of any internal logic signal for presentation at a "probe" pad.
This allows real-time external observation of each net as the
chip operates in a system (similar to an in-circuit emulator
for a microprocessor). Use of a sense amp circuit greatly
increases the speed of the in-circuit probe path.
Another challenge is to keep the gates of thousands of
isolation devices pumped to a high voltage during normal

operation. A rapid, high-power pump operates when the chip
turns on. It is then shut down when the desired voltage is
reached and a low-power sustainer pump takes over. The
required standby current is under 300uA.
Acknowledgements
The authors acknowledge contributions by: Rick
Wilkenson (layout); Sam Beal, Andy Haines, Dennis
McCarty, Bob Osann (applications); Gregg Bakker, Steve
Chiang, Shafy Eltoukhy, Esmat Hamdy, John McCollum,
(technology); Sanko Lan, Justin Reyneri (logic) and Jeff
Schlageter for his support. Sample designs were contributed
by Texas Instruments, Data General, many Actel customers,
and the EE 218 class at Stanford University.
References
[1] A. EI Gamal, J. Greene, J. Reyneri, E. Rogoyski, K. EIAyat, and A. Mohsen. "An Architecture for Electrically
Configurable Gate Arrays." IEEE 1. Solid-State Circuits,
Vol. 24, No.2, April, 1989, pp. 394-398.

[2] K. EI Ayat, et. al. "A CMOS Electrically Configurable
Gate Array." IEEE 1. Solid-State Circuits, Vol. 24, No.3,
June, 1989, pp. 752-762.
[3] E. Hamdy, et. al. "Dielectric Based Antifuse for Logic
and Memory ICs." IEDM Tech. Digest, San Francisco,
CA, 1988, pp. 786-789.
'
[4] A. EI Gamal, 1. Kouloheris, D. How, M. Morf.
"BiNMOS: A Basic Cell for BiCMOS Sea-of-Gates."
Proc. IEEE 1989 Custom Integrated Circuits Con£., page
8.3.l.
[5] S. Lan, J. Reyneri, 1. Greene, A. EI Gamal. "An
Automatic Function Generator for Field Programmable
Gate Arrays." In preparation.

•

[6] 1. Greene, V. Roychowdhury, S. Kaptanoglu, A. EI
Gamal. "Segmented Channel Routing." Submitted for
publication.
[7] A. EI Gamal, 1. Greene, J. Reyneri. "Programmable
Interconnect Architecture." US Patent 4,873,549.

eSlgn
99.4
98.1
97.1
97.0
94.5
92.7
87.3
86.8
86.7

4.30
4.57
3.99
4.78
3.37
4.34
3.83
5.25
4.33

93.2
92.6

4.68
4.73

[8] S. Chiang, R. Wang, 1. Chen, K. Hayes,
J. McCollum, E. Hamdy, C. Hu.
"Oxide-Nitride-Oxide
Antifuse
Reliability." In!'1 Reliability Physics
Symp., March 1990.

Table 2: Place and Route Examples.
Examples routed in possible implementations of the architecture with 1232 (a-j) and
649 (k-m) logic modules. The notation "(xN)" means the block was replicated N
times.

31.5.4
4-25

4-26

General Information

General Information

Metastability ............................................................................................

5-1

Three-Stating A1010/1020 Designs. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . .. . . . . . . .. . .. .. . . . . . .. . . . . . . . . .. . .

5-3

Socket Selector Guide ....................................................................................

5-5

Technical Support Services. .. .............................................................................

5-7

Applications
Note

Metastab iIity

Actel Metastability Characteristics
Designers often have asynchronous signals coming into
synchronous systems. Typically a flip-flop is used to synchronize the
incoming signal with the system clock.
If the asynchronous incoming signal does not meet the setup time
requirement for the flip-flop, there exists a window of time where
the incoming signal may cause the flip-flop to develop an unknown,
or metastable, logic condition. Figure 1 shows this window as two
Actual clock setup time of the flip-flop is shown as tsu; propagation
delay of the flip-flop is shown as t CQ . Resolution time (t res) between
flip-flop output and the next clocked device is the amount of time
required for the metastable condition to stabilize.

The duration of a metastable condition is probabilistic. But the
designer can calculate how often a metastable state will last longer
than a given duration. Mean time between failures (MTBF) can be
calculated from the following equation:

MTBF = _ _ _ _1"'---_ __
felk * f dat * C 1 e -C2"lres
where the constants depend on the ACTTM 1 device characteristics,
and:
MTBF = Mean time between failures (s)
felk = System clock frequency (Hz)
f dat = Incoming data rate (Hz)

e = Natural log base
tres

= Resolution time (ns)

C1 = 1O-9/Hz
C2 = 4.6052/ns
(Value of C2 derived from circuit simulations.)

--n-CLKtJ

DATA IN

DATA IN

f

Q1

I

~---------------------------

CLK-----",

"1"
Q1 ___________J

________ "0"

Figure 1. Metastable Condition

£) 1992 Actal Corporation

5-1

Sample Calculation
Using the MTBF equation for a design with a system clock
frequency of 10 MHz and a data rate of 1 MHz, various resolution
times produce the results shown in Figure 2. Linear increases in
resolution time cause exponential increases in MTBE

1011

1000 YEARS

10 10
109
108
107

~I

106
105
104
103
102
101

2

4

6

8

Figure 2. Metastable MTBF as a Function of Resolution Time

5-2

ns

Three-Stating
A1010/A1020 Designs

During board test and debug it is frequently desirable to place all
chip lias into a three-stated condition. This provides isolation
from other three-stating circuit devices connected to signals
common to the ACT™ device. The three-stated condition also
allows board test for trace integrity or insertion damage to ACT
device pins.
Three-stating a design is easy using the unique debug features of
ACT device architecture. Three special pins on the ACT device
facilitate three-stating: MODE, SDI, and DCLK.

Three-State Pin Assignments
44-pin
MOOE

PLCC/JQCC
68-pin
84-pln

34

54

66

PGA
84-pin
E11

SOl

36

56

72

B11

OCLK

37

57

73

C10

Applications
Note

Pins SDI and DCLK should remain unassigned by the user or
should be defined as input-only.
You may three-state all user-defined pins regardless of their
normal mode definition: input-only, output-only, or
three-stateable. Each pin can be temporarily three-stated for test
and debug purposes.
Figure 1 shows the sequence of three-stating. Seven data bits are
clocked into the device, using the sm pin as data input, and DCLK
as clock. The MODE pin distinguishes "test" mode from "normal."
The data sequence clocked is {OOO1Oll}. After clocking the
seventh bit, all user-defined pins enter a three-state condition until
MODE is taken low.
Actel Actionprobe™ diagnostic tools allow 100% observabiIity of
internal nodes; ACT devices may also be isolated from external
board circuitry. Together, these two features provide a powerful
debugging feature previously unavailable in custom devices.

> 1)Js

OCLK

V1H
V1L

SOl

V1H
V1L
V1H
V1L

Figure 1. Three-state Timing

Notes:
1. 0 V S V IL s 0.5 V; 3.0 V S VIA -.;:; Vee
2. Test mode configuration is a low frequency ( < 1.0 MHz) operation.
3. All setup and hold conditions (th' ts) ~ 250 ns.

©

1992 Actel Corporation

April 1992

5-3

I

5-4

Socket Selector
Guide

Actel has compiled this list of known suppliers for the convenience
of our customers. This is simply a list of suppliers that we are aware
ofrather than a list ofrecommended sockets, as we have not tested

them for reliability. For information on these sockets, contact the
manufacturers directly.

Socket Sources for Actel FPGA Packages
Production Sockets
Lead
Count
44

PLCC

68
84

Source

Through-Hole

Surface-Mount

AMP
METHODE
AMP
METHODE
AMP
METHODE

821551-3
213-44-101
821574-3
213-068-101
821573-3
213-084-101

821979-3 or 822035-3
213-044-602
822029-3 or 822073-3
213-068-602
821808-1 (high profile)
213-084-602

PGA (11x11)

85

MILL-MAX
McKENZE

510-91-085-11-041
PGA-85H-012B1-1107

PGA (11x11)

101

McKENZE

PGA-101M-012B-1-11 B5

PGA (13x13)

133

McKENZE

PGA-133H-003B-1-13GO

PGA (15x15)

176

MILL-MAX
McKENZE

510-91-176-15-061
PGA-177M-003B-1-1552

PQFP

100
144
160

YAMAICHI
AMP
AMP

N/A
822114-3/8222115-3
822114-4/822115-4

IC149-100-05-S5

Lead
Count

Source

Through-Hole

Surface-Mount

CQFP

84
132
172

WELLS
ENPLAS
ENPLAS

619-1000311-001
OTQ-132-0.635-01
OTQ-172(196)-0.635-02

PQFP

100
144
160

YAMAICHI
YAMAICHI
YAMAICHI

IC51-1004-814-2
IC51-1014-KS10418
IC51-1604-845-1

PGA

85
101
133
176

YAMAICHI
YAMAICHI
NEPENTHE
YAMAICHI

NP35-112-G4-BF85
NP89-12110-G4-BF101
NEP5-132-RS1311
NP89-22508-G4-BF177

PLCC

44
68
84

YAMAICHI
YAMAICHI
YAMAICHI

IC51-0444-400
IC51-0684-390-1
IC51-0844-40 1-1

Zero Insertion Sockets

CONTACTS:

©

1992 Actal Corporation

AMP
ENPLAS
METHODE
MIL-MAX
McKENZE
NEPENTHE
WELLS
YAMAICHI

I

(408) 725-4914
(415) 572-1683
(408) 262-3812
(516) 922-6000
(510) 651-2700
(415) 856-9332
(408) 559-8118
(408) 452-0797

April 1992

5-5

5 6

Technical
Support Services

macros, and upload design files. The current modem configuration
is 2400 baud, 8 data bits, one stop bit, no parity.

Actel Technical Support
Supporting customers is important to us. We want to offer help in as
many ways as possible to suit your particular needs. You can obtain
Actel technical assistance by Technical Hotline, Bulletin Board,
Customer Training, and our new Action Facts system.
Technical Hotline

The Technical Hotline provides information on Actel hardware
and software products. Our applications engineers are ready to
answer your calls from 7:00 a.m. to 5:30 p.m. PST, Monday to
Friday. Our priority is to always have an applications engineer
answer your calls "live." In addition to answering your calls, the
applications engineers develop other ways of assisting our
customers, such as writing application notes, user guides, and
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software.
Bulletin Board

We currently offer information access by a 24-hour bulletin board.
Customers can view information, download files such as new

Customer Training

Actel offers an introductory two-day course covering all aspects of
designing an Actel device. The class covers a discussion of the
architecture of both the ACT 1 and ACT 2 families, design
methodology, a brief look at the Viewlogic schematic capture and
simulation tools, details of the Boolean entry tool (ALES 1), and a
thorough examination of the Actel FPGA design software (ALS).
With the guidance of the instructor, students develop an example
circuit, which is programmed into an Actel device, debugged, and
verified in a system board.
Action Facts

We are proud to announce a fast new 24-hour service to our
customers - Action Facts! Current bugs, software schedules, new
package pinouts, the latest application notes, and many more
documents can be accessed instantaneously with this new system.
Simply call the toll-free number, select the document you require,
enter your fax number and extension, and the document will be
faxed to you immediately!

TECHNICAL HOTLINE

800-262-1060
(U.S. & CANADA)

408-739-1540 (FAX)

II
BULLETIN BOARD

408-739-6397

ACTEL
CUSTOMER TECHNICAL
SUPPORT

ACTION FACTS

800-262-1062

CUSTOMER TRAINING

408-739-101 0 x257

:§) 1992 Actel Corporation

April 1992

5-7

Notes:

Notes:

Notes:

Notes:

Notes:

ACTEL CORPORATION ADMINISTRATIVE OFFICES
Actel Corporation
955 E. Arques Avenue
Sunnyvale, CA 94086 ....................................... (408) 739-1010

Actel Europe Ltd. Intec 2
Wade Road, Basingstoke
Hants RG24 ONE UK .............................. +44 (0) 25629209

Actel Central Europe
Dingolfinger Strasse 2
W-8000 Miinchen80 Germany ... +49(0) 89418 00078

ACTEL CORPORATION DIRECT SALES OFFICES
UNITED STATES
955 E. Arques Avenue
Sunnyvale, CA 94086 ................................. (408) 739-1010

6525 The Corners Parkway, Suite 400
Norcross, GA 30092.
........ (404) 409-7888

3800 N. Wilke Road, Suite 300
Arlington Heights, IL 60004 ..

.... (708) 259-1501

8130 McFadden Avenue, Suite 109
Westminster, CA 92683 ...
............ (714) 373-4488

1740 Mass Avenue
Boxborough, MA 01719 .. .

2350 Lakeside Blvd., Suite 850
Richardson, TX 75082 ..

.... (214) 235-8944

OHIO
J.R. Thornberry Co. (Chagrin Falls)
J.R. Thornberry Co. (Dublin) ..

.... (216) 247-0060
.. (614) 792-5171

OREGON
U Ltd. ..

.... (503) 629-8555

PENNSYLVANIA
Omega Electronic Sales (Trevose)
J.R. Thornberry Co. (Bridgeville) .

(215) 244-4000
.... (412) 745-8441

........ (508) 635-0010

DOMESTIC REPRESENTATIVES
ALABAMA
BITS, Inc. ..
ARIZONA
Luscombe Engineering ..

.. .... (205) 881-2900

IDAHO
First Source ..

............. (602) 949-9333

IOWA
Carlson Electronic Sales Associates ....... (319) 378-1450
KANSAS
DLE Electronics ..

........ (316) 683-6400

MARYLAND
New Era Sales ..

.. .. (410) 544-4100

MASSACHUSETTS
Advanced Technical Sales, Inc. .

........ (508) 664-0888

............. (303) 649-9717

MICHIGAN
Electronic Sources, Inc...

...... (313) 227-3598

(203) 284-0838

MINNESOTA
Gibb Technology Sales ....

(612) 835-3370

CALIFORNIA
Centaur Corporation (Calabasas)
Centaur Corporation (Irvine) .. . .........
Centaur Corporation (San Diego) ..........
[2 Inc. (Roseville)
[2 Inc. (Santa Clara)
COLORADO
Thom Luke Sales, Inc. .

(208) 378-4680

CONNECTICUT
Advanced Technical Sales, Inc.

(818) 591-1655
(714) 261-2123
(619) 278-4950
(916) 784-0530
(408) 988-3400

TEXAS
OM Associates (Austin) ................................. (512) 794-9971
OM Associates (Houston)
(713) 789-4426
OM Associates (Richardson)
(214) 690-6746
UTAH
First Source ..... .

.... (801) 943-6894
... (206) 827-8555

FLORIDA
QXI, Inc. (St. Petersburg) ..
............. (813) 894-4556
QXI, Inc. (Fort Lauderdale) ........................ (305) 978-0120
QXI, Inc. (Orlando) " ..................................... (407) 872-2321
QXI, Inc. (Melbourne) ..
............. (407) 676-1491

MISSOURI
John G. Macke Co ............................................. (314) 432-2830

WASHINGTON
ULtd ...

NEW JERSEY
Nexus ..

WISCONSIN
Carlson Electronic Sales Associates ..... (414) 476-2790

GEORGIA
BITS, Inc ............................................................. (404) 564-5599
ILLINOIS
Carlson Electronic Sales Associates ....... (708) 956-8240

NEW YORK
L-MAR Associates (Marcellus) ................ (315) 673-1325
L-MAR Associates (Fairport).
........ (716) 425-9100
L-MAR Associates (Lackawanna) ......... (716) 826-1301
L-MAR Associates (Troy) .
. (518) 235-0962

INDIANA
Bailey's Electronic Sales & Technology . (317) 848-9958

NORTH CAROLINA
BITS,Inc. ...

...... (919) 676-1880

MICHIGAN
Livonia ..

..... (313) 525-1800

MINNESOTA
Eden Prairie ...

OHIO
Cleveland ..
Dayton.

.. (216) 587-3600
... (513) 236-9900

........ (612) 944-3355

PENNSYLVANIA
Pittsburgh.

.... (412) 782-2300

TEXAS
Austin.
Dallas .'
Houston ..

.... (512) 835-4000
... (214) 386-7300
... (713) 495-4700

WISCONSIN
Brookfield . ....

.... (414) 784-3480

....... (404) 623-1003

NORTH CAROLINA
Morrisville .......

.. (919) 460-1530

........ (301) 921-0660

PENNSYLVANIA
Horsham ..

.... (215) 674-4000

.... (201) 947-0151

CANADA
Clark-Hurman Associates
(Quebec) ..
... (514) 426-0453
Clark-Hurman Associates
(Ontario-Brampton) ..
... (416) 840-6066
Clark-Hurman Associates
(Ontario-Nepean) ............................................. (613) 727-5626

U.S. DISTRIBUTORS

Pioneer Standard Electronics
CALIFORNIA
Irvine ..
Woodland Hills ..

....................................... (714) 753-5090
. ......... (818) 883-4640

CONNECTICUT
Shelton .....
ILLINOIS
Addison

........... (203) 929-5600

NEW JERSEY
..................................... (708) 495-9680

........ (201) 575-3510

INDIANA
Indianapolis ..

.......... (317) 573-0880

MASSACHUSETTS
Lexington.

............. (617) 861-9200

Fairfield.
NEW YORK
Binghamton ......................................................... . (607) 722-9300
Fairport ................................................................... . (716) 381-7070
....... (516)921-8700
Woodbury ..

............. (205) 837-9300

GEORGIA
Duluth ..

Pioneer Technologies
ALABAMA
Huntsville ...
CALIFORNIA
San Jose .....

.. (408) 954-9100

FLORIDA
Altamonte Springs ........................................ (407) 834-9090

MARYLAND
Gaithersburg ....

DOMESTIC DISTRIBUTORS (CONTINUED)

Wyle Laboratories
ARIZONA

COLORADO

Phoenix ...

......................... (602) 437-2088

TEXAS
........................ (303) 457-9953

Thornton ..

MASSACHUSETTS

CALIFORNIA
Calabasas ..
Irvine ...
Rancho Cordova ....
San Diego ..
Santa Clara .

····.H ...... (818) 880-9000

. (714) 863-9953
...................... (916) 638-5282
................ (619) 565-9171
(408) 727-2500

..... (617) 272-7300

Burlington ..

Austin ..... .
Houston.
Richardson ..... .

................ (512) 345-8853
. ....... (713) 879-9953
... (214) 235-9953

UTAH

OREGON
Beaverton

• ••••H

••••••••••

(503) 643-7900

Salt Lake City .....

.H ••••

(80l) 974-9953

WASHINGTON
Redmond ....... .

••••••••••••••• : ••••••••••••• H •••••••••

• •• H

(206) 881-1150

••••

CANADIAN DISTRIBUTORS

Zentronics
ALBERTA

MANITOBA
. .... .. (403) 295-8838
...... (403) 482-3038

Calgary ..
Edmonton.

BRITISH COLUMBIA
.. (604) 273-5575

Richmond.

QUEBEC

Winnipeg.

....... (204) 694-1957

ONTARIO
Mississauga ..
Nepean

H.

Ville St. Laurent .
Ste.Foy H'

H

HHHHHHH

• •••• H ••

(514) 737-9700
(418) 654-1077

(416) 507-2600
(613) 226-8840

INTERNATIONAL REPRESENTATIVES
FRANCE
Mustronic (Paris) ..

(1) 34 65 90 4

·H.HHHH.

ITALY
ROAN sri (Milano) ..

HH ••• H.HHH •••••

H'

(2) 38 09 3259

INTERNATIONAL DISTRIBUTORS
AUSTRALIA

HONG KONG

Reptechnic (Neutral Bay, NSW)

H

H. H.H •••• H •••• HH.

(2) 953 9844

PEOPLE'S REPUBLIC OF CHINA

Twin-Star Trading Co. (Yau Tong)

(852) 346 9085

INDIA

AUSTRIA
Codico Ges.m.b.H. & Co KG (Wien)

(0222) 86 24 28

HH • • H.

(02) 720 59 83

Acal Auriema NV /SA (Zaventem)

(65) 2991605

Benchmark Systems (Singapore)
A.5.T. Ltd. (Herzelia)

Nortec Electronics A/S (Herlev)

.H

(042) 842000

••• H.

.. H'·H. 052583355

H

S.E.E. (Cairo) ..........

H.H . . . . . . . . . . . . . H ....... H ••• H . . . . . . . . . H .... H .. H.H ••••••

(2) 665 948

LAS! Elettronica S.pA (Milan)

H

'''H

FINLAND
(9) 0-692 6022

.H ........ H ••• H .. H .. HH.H .• H ..

(02) 661431

H

H

HHHHHHHH.

HHH.H •• HHH

A2M (Paris) ......
SCAIB SA (Paris)
SCAIB SA (Grenoble) .

H··H.H ....... H ..... H.·H •• H .... H.HH.HH ... H.H •.••• H

..H··H •• H ••• HHH.

(1) 39 54 91 13
(1) 46 872313
(1) 76902260

Actel Sulzer (Briigg) ...

(75) 951 8151

TAIWAN
•

H .....

(053) 330336

HHHHHH.

HH

NORWAY
Nortec Electronik A/S (Hvalstad)

HH

HHHHH

(02) 84 6210

0 32'5363 75

HHHHHHHH.H.H

(2) 7127321

UNITED KINGDOM
Gothic-Crellon Ltd. (Wokingham)
(0734) 788878
Manhattan Skyline Ltd.
(Maidenhead)
(0628) 778686
Microprocessor & Memory Distribution Ltd.
(0734) 313232
(Reading)
HH

REIN Elektronik GmbH (Nettetal)
(02153) 733-0
Microcomputers Systems Components (07249) 7580

• • • HHHH . . . . . .

HHHH ••••

NETHERLANDS
Transfer BV (Enschede) .. ..

GERMANY

(2) 553 2997

(93) 2172340
(91) 7422313

.(0)87051800

H

Aexcel Technology Corporation
(Taipei)
H'''H

•

HHHH

SWITZERLAND

HH. H.

Anam Semiconductor Design Co., Ltd.
(Seoul) .

H

SWEDEN

(45) 474 9037

KOREA

FRANCE

Semiconductores S.A. (Barcelona)
Semiconductores SA (Madrid)
Nortec Electronics AB (Solna)

Innotech Corporation
(Yokohama-Shi)..
Matsushita Electronics Corporation
(Kyoto)
.HHHHHHHHHH.

OY Fintronic AB (Helsinki)

(11) 7868144

HH.HHHH'.H.

H

JAPAN

EGYPT

ASIC Design Services (Sandton)

SPAIN

ITALY

DENMARK

........ (408) 865-0142

ESAE Associates (U.sA)

SOUTH AFRICA

ISRAEL

BELGIUM

12/92

H •• H ••••

H

HH.HHHH .. HHH.

•

HHHHHHH •• HHH

H •••• HHHHH.

•

. . . . HHHHHHHH.H



File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date                     : 2017:11:01 09:58:58-08:00
Modify Date                     : 2017:11:01 10:37:01-07:00
Metadata Date                   : 2017:11:01 10:37:01-07:00
Producer                        : Adobe Acrobat 9.0 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:93090f2d-4ba8-1e48-9ffa-cd251ec4d12e
Instance ID                     : uuid:f2111916-7a54-774e-93c7-073a2719795b
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 340