1992_Analog_Devices_Audio_Video_Reference_Manual 1992 Analog Devices Audio Video Reference Manual

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ADCs
DACs

Special Functions
OpAmps

DSP
App Notes

OP AMPS · AUDIO ADCs • VIDEO ADCs •

.... ANALOG

..... OEVICES

AUDIO DACs • VIDEO DACs • SPECIAL FUNCT ION AUD IO ·
SPECIAL FUNCTION VIDEO • DSP • APPLICATION NOTES

.... ANALOG
WOEVICES

1992

AUDIONIDEO
REFERENCE
MANUAL

General Information
Operational Amplifiers
Audio AID Converters
Video AID Converters
Audio D/A Converters
Video D/A Converters

©Analog Devices, Inc., 1992
All Rights ReselVed

Special Function Audio Products
Special Function Video Products

IlANALOG

DEVICES

Digital Signal Processing Products

II

••
II
•II
•II
a

Appendix

III
II
lEI
III

Index

II

Other Products
Application Notes
Package Information

.... ANALOG

.... DEVICES
1992

AUDIOIVIDEO REFERENCE MANUAL
© Analog Devices, Inc., 1992
All Rights Reserved

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
Analog Devices.
U.S.:

RE29,992, RE30,586, RE31,850, 3,729,660, 3,793,563, 3,803,590, 3,842,412, 3,868,583, 3,890,611, 3,906,486,
3,932,863, 3,940,760, 3,942,173, 3,942,173, 3,946,324, 3,950,603, 3,961,326, 3,978,473, 3,979,688,
4,020,486, 4,029,974, 4,034,366, 4,054,829, 4,055,773, 4,056,740, 4,068,254, 4,088,905, 4,092,639,
4,109,215, 4,118,699, 4,123,698, 4,131,884, 4,136,349, 4,138,671, 4,141,004, 4,142,117, 4,168,528,
4,213,806, 4,228,367, 4,250,445, 4,260,911, 4,268,759, 4,270,118, 4,272,656, 4,285,051, 4,286,225,
4,313,083, 4,323,795, 4,333,047, 4,338,591, 4,340,851, 4,349,811, 4,363,024, 4,374,314, 4,374,335,
4,395,647, 4,399,345, 4,400,689, 4,400,690, 4,404,529, 4,427,973, 4,439,724, 4,444,309, 4,449,067,
4,460,891, 4,471,321, 4,475,103, 4,475,169, 4,476,538, 4,481,708, 4,484,149, 4,485,372, 4,491,825,
4,511,413, 4,521,764, 4,538,115, 4,542,349, 4,543,560, 4,543,561, 4,547,766, 4,547,961, 4,556,870,
4,562,400, 4,565,000, 4,572,975, 4,583,051, 4,586,019, 4,586,155, 4,590,456, 4,596,976, 4,601,760,
4,608,541, 4,622,512, 4,626,769, 4,633,165, 4,639,683, 4,644,253, 4,646,056, 4,646,238, 4,675,561,
4,678,936, 4,683,423, 4,684,922, 4,685,200, 4,687,984, 4,694,276, 4,697,151, 4,703,283, 4,707,682,
4,717,883, 4,722,910, 4,739,281, 4,742,331, 4,751,455, 4,752,900, 4,757,274, 4,761,636, 4,769,564,
4,774,685, 4,791,318, 4,791,551, 4,800,524, 4,804,960, 4,808,908, 4,811,296, 4,814,767, 4,833,345,
4,855,585, 4,855,618, 4,855,684, 4,857,862, 4,859,944, 4,862,073, 4,864,454, 4,866,505, 4,878,770,
4,884,075, 4,885,585, 4,888,589, 4,891,533, 4,891,645, 4,899,152, 4,902,959, 4,904,921, 4,924,227,
4,928,103, 4,928,934, 4,929,909, 4,933,572, 4,940,980, 4,957,583, 4,962,325, 4,969,823, 4,970,470,
4,978,871, 4,980,634, 4,983,929, 4,985,739, 4,990,797, 4,990,803, 4,990,916, 5,008,671, 5,010,297,
5,021,120, 5,026,667, 5,027,085, 5,030,849,

3,909,908,
4,016,559,
4,092,698,
4,210,830,
4,309,693,
4,383,222,
4,454,413,
4,503,381,
4,558,242,
4,604,532,
4,677,369,
4,709,167,
4,771,011,
4,839,653,
4,879,505,
4,926,178,
4,973,978,
5,010,337,

France:

111.833,70.10561,75.27557,7608238,77 20799, 78 10462,79 24041,80 00960, 80 11312,80 11916,81 02661,
81 14845,8303140,9608238
Japan:

1,092,928,1,242,936,1,242,965,1,306,235, 1,337,318, 1,401,661, 1,412,991, 1,432,164, 1180463
West Germany:

2,014034, 25 40 451.7, 26 11 858.1
U.K.:

1,310,591, 1,310,592, 1,537,542, 1,590,136, 1,590,137, 1,599,538, 2,008,876, 2,032,659, 2,040,087, 2,050,740,
2,054,992, 2,075,295, 2,081,040, 2,087,656, 2,103,884, 2,104,288, 2,107,951, 2,115,932, 2,118,386, 2,119,139,
2,119,547, 2,126,445, 2,126,814, 2,135,545
Canada:

984,015,1,006,236,1,025,558,1,035,464, 1,054,248, 1,140,267, 1,141,034, 1,141,820, 1,142,445, 1,143,306, 1,150,414,
1,153,607, 1,157,571, 1,159,956, 1,177,127, 1,177,966, 1,184,662, 1,184,663, 1,191,715, 1,192,310, 1,192,311,
1,192,312, 1,203,628, 1,205,920, 1,212,730, 1,214,282, 1,219,679, 1,219,966, 1,223,086, 1,232,366, 1,233,913,
1,234,921
Sweden:

7603320-8

General Information
Contents
Page

President's Letter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
How to Use this Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Master Selection Guides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Product Assurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20

GENERAL INFORMATION 1-1

II

1-2 GENERAL INFORMA TION

Since its founding in 1965, Analog Devices has dedicated itself to the design, manufacture and marketing of products used in real-world signal processing applications. Our
product universe includes data converters, operational amplifiers, digital signal processors, special function devices and application specific ICs that combine these functions
on a single chip.
Analog's core strengths are its analog circuit design expertise and state-of-the-art linear
and mixed-signal semiconductor process technology, which have led to a long list of
technically innovative products. These strengths are supported by a number of manufacturing locations around the world and by a technical sales force trained and ready to
serve your needs.
The decade of the '90s offers many exciting opportunities for linear and mixed-signal
ICs for a wide range of emerging applications in computer peripherals, telecommunications equipment and consumer products, including the automotive market. Many of
these involve processing audio and/or video information, which has become an increasingly significant part of Analog's business in recent years, and which was enhanced last
year by the acquisition of Precision Monolithics.
Among other successes, our efforts to provide technically innovative and economically
practical products for audio and video signal processing applications have resulted in
Analog becoming a leading supplier of both DIA converters used in compact disc players and RAM-DACs used in VGA displays. And our monolithic SSM-2125 Dolby ProLogic Surround Sound Decoder has been recognized as the best integrated solution
available for implementing this function in consumer electronics products.
This first edition of our AudiolVideo Reference Manual is a clear sign of our commitment to continue developing and marketing high performance integrated circuits for a
wide range of audio and video signal processing applications in professional, consumer,
automotive, medical, military and industrial applications. Here you will find data sheets
containing complete specifications and applications information on 103 product families, as well as 40 application notes to assist you in your product development efforts.
The products described in this reference guide represent integrated solutions that offer
higher performance, increased reliability and lower overall cost, and as a consequence,
will help you design products that make your company more competitive in its markets. We look forward to serving your needs for these types of products for many years
to come.

5 fti

Ray Stata
Chairman of the Board
Chief Executive Officer
Analog Devices

GENERAL INFORMA TION 1-3

II

Introduction
Analog Devices designs, manufactures and sells worldwide
sophisticated electronic components and subsystems for use in
real-world signal processing. More than six hundred standard
products are produced in manufacturing facilities located
throughout the world. These facilities encompass all relevant
technologies, including several embodiments of CMOS, BiMOS,
bipolar and hybrid integrated circuits, each optimized for specific attributes-and assembled products in the form of potted
modules, printed-circuit boards and instrument packages.
State-of-the-art technologies (including surface micromachining)
have been utilized (and in many cases invented) to provide
timely, reliable, easy-to-use advanced designs at realistic prices.
Our popular IC products are available in both conventional and
surface-mount packages (SOIC, LCC, PLCC), and many of our
assembled products employ surface-mount technology to reduce
manufacturing costs and overall size. A quarter-century of successful applications experience and continuing vertical integration insure that these products are oriented to user needs. The
ongoing application of today's state-of-the-art and the invention
of tomorrow's state-of-the-art processes strengthen the leadership position of Analog Devices in standard data-acquisition and
signal-processing products and make us a strong contender in
high performance mixed-signal ASICs.
MAJOR PROGRESS
Audio electronic components are an important subset of products for equipment designers instrumenting the multimedia
interface between information in electronic form and human
communication capabilities (particularly sight, speech, hearing,
and the audible and visual arts).

The Audio Handbook, published by Precision Monolithics, Inc.
-which was acquired by and became a Division of Analog
Devices in 1990-described many of our analog IC products for
the audio equipment subset. However, we also manufacture
many analog, digital, and mixed-signal products that are useful
in the processing and display of video signals, as well as conversion products for professional and consumer audio equipment. It
appeared to make good sense in this new edition to expand the
publication's concept to include all products-including many
new ones-designed for the multimedia interface.
Important products described here that we have introduced for
this industry include:
• the AD9020/9060 families of lO-bit "flash" converters that
provide interfacing for both conventional and HDTV digital
video systems

>Dolby is a registered trademark of Dolby Laboratories, Inc.
CEG/DAC aod TrimDAC are trademarks of Analog Devices, Inc.

1-4 GENERAL INFORMA TlON

• the ADSP-2105 and ADSP-21020 flXed- and floating-point
digital signal processors for high speed implementation of
computational algorithms
• the ADV7141146/48 CEGIDAC·· family of monolithic RAMDACs, designed to eliminate "jaggies" and improve color resolution in VGA displays at low cost
• the AD712 family of low-noise-and-distortion op amps for
audio preamplification
• the AD847 op amp for video line driving and other high
speed applications
• the ADl879 dual-channel 18-bit ADC and the ADl865 dualchannel DAC for stereo applications
• the DAC-8840 and DAC-8841 TrimDACs'" for digitally controlled circuit parameter adjustment
• the SSM-20I8 voltage-controlled amplifier, for audio panning,
equalization, remote volume control, and compressor/limiter
applications-using patented Operational Voltage-ControlledElement COVCE) architecture
• the SSM-2125 Dolby* Pro-Logic Surround Sound Matrix
Decoder, a low cost chip that gives home-entertainment system manufacturers a practical way to bring the benefits of
theater-type sound to consumers
• the SSM-2142 and SSM-2141 balanced line driver and line
receiver for transporting analog signals with minimal signal
degradation
Many more could have been added to this list.

AUDIONIDEO REFERENCE MANUAL
The Audio/Video Reference Manual is one of a set of books
cataloguing Analog Devices products. It is accompanied by the
Linear Products Databook and the two-volume Data Converter

Reference Manual.
This volume provides comprehensive technical data and application notes on 103 Analog Devices product families designed for
incorporation in professional and consumer audio, video, imaging, and multimedia equipment. Included are the following:
•
•
•
•

comprehensive data sheets and package information
selection guides for fmding products rapidly
a set of 40 application notes
ordering guide, publications list, and worldwide sales
directory
• indexes:
-application notes, by topic and by part numbers
-all Analog Devices products, listed a1phanumerically by
part number and keyed to catalog location.

TECHNICAL SUPPORT
Our extensive technical literature discusses the technology and
applications of products for real-world signal processing. Besides
tutorial material and comprehensive data sheets, including a
large number in our Databooks, we offer Application Notes,
Application Guides, Technical Handbooks (at reasonable prices),
and several free serial publications; for example, Analog
Productlog provides brief information on new products being
introduced, and AnalogDialogue, our technical magazine, provides in-depth discussions of new developments in analog and
digital circuit technology as applied to data acquisition, signal
processing, control, and test. DSPatch ,. is a quarterly newsletter that brings its readers up-to-date applications information on
our DSP products and the general field of digital signal processing. We maintain a mailing list of engineers, scientists, and
technicians with a serious interest in our products. In addition
to Databook catalogs-and general short-form selection guideswe also publish several short-form catalogs on specific product
families. You will fmd typical publications described on pages
13-4 to 13-7 at the back of the book.

SALES AND SERVICE
Backing up our design and manufacturing capabilities and our
extensive array of publications, is a network of distributors, plus
sales offices and representatives throughout the United States
and most of the world, staffed by experienced sales and applications engineers. Our Worldwide Sales Directory, as of the publication date, appears on pages 13-8 and 13-9 at the back of the
book.

RELIABILITY

Improvement Process (QIP). In addition, we maintain facilities
that have been qualified under such standards as MIL-M-38SI0
(Class B and Class S) for ICs in the U.S. and MIL-STD-1772
for hybrids. Many of our products-both proprietary and
second-source-have qualified for JAN part numbers; others are
in the process. A larger number of products-including many of
the newer ones just starting the JAN qualification process-are
specifically characterized on Standard Military Drawings (SMDs).
Most of our ICs are available in versions that comply with MILSTD-883C Class B, and many also comply with Class S. We
publish a Military Products Databook for designers who specify
ICs and hybrids for military contracts. The 1990 issue consists
of two volumes with data on 343 product families; the 120
entries in the second of those volumes describe qualified products manufactured by our PMI Division. A newsletter, Analog
Brieft,ngs®, provides current information about the status of reliability at AD!.
Our PLUS program makes available standard devices (commercial and industrial grades, plastic or ceramic packaging) for any
user with demanding application environments, at a small premium. Subjected to stringent screening, similar to MIL-STD883 test methods, these devices are suffixed "/ +" and are
available from stock.

PRICES
Accurate, up-to-date prices are an important consideration in
making a choice among the many available product families.
Since prices are subject to change, current price lists and/or
quotations are available upon request from our sales offices and
distributors.

The manufacture of reliable products is a key objective at
Analog Devices. The primary focus is the companywide Quality

Analog Brieflngs is a registered trademark of Analog Devices, Inc.
DSPatch is a trademark of Analog Devices, Inc.

GENERAL INFORMATION 1-5

1

How to Use This Book
THIS IS THE ANALOG DEVICES AUDIONIDEO REFERENCE MANUAL
It contains Data Sheets, Selection Guides and Application Notes on IC products for audio and video equipment design.

It is one member of a four-volume set of reference manuals on Linear, Converter and AudioNideo products from Analog Devices,
Inc., in IC, hybrid and assembled form for measurement, control and real-world signal processing.

IF YOU KNOW THE MODEL NUMBER
Turn to the product index at the back of the book and look up the model number. You will find the location of any product
catalogued in this volume or those listed below, with the Volume-Section-Page location of any data sheet in this volume.

IF YOU DON'T KNOW THE MODEL NUMBER
Find your functional group in the list on the opposite page. Turn directly to the appropriate Section. You will find a functional Selection Guide at the beginning of the Section. The Selection Guides will help you find the products that are the closest to satisfying your need. Use them to compare all products in the category by salient criteria. A comprehensive Table of
Contents (of this volume) is provided for your convenience on pages 1-7 through 1-10.

IF YOU CAN'T FIND IT HERE. _ . ASK!
If it's not an audio/video product, it's probably in one of the two companion reference manuals, the Linear Products
Databook or the Data Converter Reference Manual. If you don't already own these volumes, you can have them FREE by getting in touch with Analog Devices or the nearest sales office, or by phoning 1-800-262-5643 (U.S.A. only) or (617) 329-4700,
Ext. 3392.
See the Worldwide Sales Directory on pages 13-8 and 13-9 at the back of this volume for our sales office phone numbers.

Contents of Other Reference Manuals
DATA CONVERTER PRODUCTS
(VOLUME I)
D/A Converters
SID Converters
Communications Products
Digital Panel Meters
Digital Signal Processing Products
Bus Interface & Serial 110 Products
Application Specific ICs
Power Supplies

1-6 GENERAL INFORMA TlON

DATA CONVERTER PRODUCTS
(VOLUME II)
AID Converters
V/F & FN Converters
SamplelTrack-Hold Amplifiers
Switches & Multiplexers
Voltage References
Data Acquisition Subsystems
Analog I/O Ports
Application Specific ICs
Power Supplies

LINEAR PRODUCTS
Operational Amplifiers
Comparators
Instrumentation Amplifiers
Isolation Amplifiers
Analog MnitiplierslDividers
Log!Antilog Amplifiers
RMS-to-DC Converters
Mass Storage Components
ATE Components
Special Function Components
Temperature Transducers
Signal Conditioning Components
& Subsystems
Digital Panel Instruments
Bus Interface & Serial
110 Products
Automotive Components
Application Specific ICs
Power Supplies
Component Test Systems

Table of Contents
Page

Operational Amplifiers - Section 2 .............................................. 2-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
AD711- Precision, Low Cost, High Speed BiFET Op Amp • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
AD712
AD713
ADS11
ADS27

- Dual Precision, Low Cost, High Speed, BiFET Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- Quad Precision, Low Cost, High Speed BiFET Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- High Performance Video Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-High Speed, Low Power Dual Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-17
2-29
2-41
2-45

ADS29 - High Speed, Low Noise Video Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
ADS40 - Wideband, Fast Settling Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
ADS41 - Wideband, Unity-Gain Stable, Fast Settling Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73
ADS42 - Wideband, High Output Current, Fast Settling Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-S1
AD843 - 34 MHz CBFET Fast Settling Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89
AD844 - 60 MHz, 2000 V/!'-s Monolithic Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-101
AD845 - Precision, 16 MHz CBFET Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-113
AD846 - 450 V/!,-s, Precision, Current Feedback Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . 2-121
AD847 - High Speed, Low Power Monolithic Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-133
AD848/AD849 - High Speed, Low Power Monolithic Op Amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-145
AD5539 - Ultrahigh Frequency Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-153
OP-27 - Low Noise, Precision Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-169
OP-37 - Low Noise, Precision High Speed Operational Amplifier (AVCL~5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1S1
OP-61- Wide-Bandwidth Precision Operational Amplifier (Av ee:lO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-193
OP-64 - High Speed, Wide-Bandwidth Operational Amplifier (AVCL ee:5) . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . 2-211
OP-I60 - High Speed, Current Feedback Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-225
OP-249 - Dual, Precision JFET High Speed Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-249
OP-260 - Dual, High Speed, Current Feedback Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-267
OP-271 - High Speed, Dual Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-287
OP-275 - Dual Bipolar/JFET, Low Distortion Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-297
OP-471 - High Speed, Low Noise Quad Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-299
SSM-2131- Ultralow Distortion, High Speed Audio Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-315
SSM-2134 - Low Noise, Audio Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-327
SSM-2139 - Dual, Low Noise, High Speed, Audio Operational Amplifier (AVCL ee:3) . . . . . . . . . . . . . . . . . . . . . . . . 2-333

Audio AID Converters - Section 3 .............................................. 3-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
AD1876 - 16-Bit 100 kSPS Sampling ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
AD187S - High Performance Stereo 16·Bit Oversampled ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
AD1879 - High Performance Stereo IS-Bit Oversampled ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
AD1S85 - Low Cost Stereo 16-Bit Oversampled ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

Video AID Converters - Section 4 .............................................. 4-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
AD773 - 100Bit 18 MSPS Monolithic AID Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
AD9020 - 10-Bit 60 MSPS AID Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
AD9048 - Monolithic 8-Bit Video AID Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
AD9060 - 10-Bit 75 MSPS AID Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
GENERAL INFORMATION 1-7

•

Page

Audio D/A Converters - Section 5 .............................................. 5-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
ADlS511ADlS61 - 16-BitllS-Bit 16 x Fs PCM Audio DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
ADlS56 - 16-Bit PCM Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . 5-13
ADlS60 - IS-Bit PCM Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
ADlS62 - Ultralow Noise, 20-Bit Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
AD1864 - Complete Dual IS-Bit Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
ADlS65 - Complete Dual IS-Bit 16 x Fs Audio DAC . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . . . 5-55
ADlS66 - Single-Supply Dual 16-Bit Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65
AD186S - Single-Supply Dual IS-Bit Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67

Video D/A Converters - Section 6 .............................................. ~l
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

~2

ADV453 - CMOS 66 MHz Monolithic 256 x 24 Color Palette RAM-DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

~3

ADV476 - CMOS Monolithic 256 x 18 Color Palette RAM-DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6~9

x 24 (18) Color Palette RAM-DACs . . . . . . . . . . . . . . . . . . . . . . . . .

~19

ADV7120 - CMOS SO MHz Triple S-Bit Video DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

~31

ADV712117122 - CMOS 80 MHz Triple 10-Bit Video DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

~37

ADV47S/471 - CMOS SO MHz Monolithic 256

ADV714117l4617l48 - CMOS Continuous Edge Graphics RAM-DACs (CEGIDAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49

Special Function Audio Products - Section 7 ................................... 7-1
Selection Guides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '7-2

AD600/602 - Dual, Low Noise, Wideband Variable Gain Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
AD7111- LOGDAC CMOS Logarithmic D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
AD7118 - LOGDAC CMOS Logarithmic D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
MAT-04 - Matched Monolithic Quad Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
PKD-Ol - Monolithic Peak Detector with Reset-and-Hold Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
SSM-2013 - Voltage-Controlled Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51
SSM-2014 - Voltage-Controlled Amplifier/OVCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-57
SSM-2015 - Low Noise, Microphone Preamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-'59
SSM-2016 - Ultralow Noise, Differential Audio Preamplifier . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . 7-65
SSM-2017 - Self-Contained Audio Preamplifier

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . 7-73

SSM-2018 - Voltage-Controlled Amplifier/OVCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-S1
SSM-2024 - Quad Current-Controlled Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-93
SSM-21l0 - True RMS-to-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-99

SSM-2120/2122 - Dynamic Range Processors/Dual VCAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-111
SSM-2125/2126 - Dolby Pro-Logic Surround Matrix Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-123
SSM-2141- High Common-Mode Rejection Differential Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-133
SSM-2142 - Balanced Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-139
SSM-2143 - -6 dB Differential Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-145
SSM-2210 - Audio Dual Matched NPN Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-147
SSM-2220 - Audio Dual Matched PNP Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-159

SSM-2402/2412 - Dual Audio Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . 7-167
SSM-2404 - Quad Audio Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-177
1-8 GENERAL INFORMATION

Page

Special Function Video Products - Section 8 ................................... 8-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
AD539 - Wideband Dual-Channel Linear Multiplier/Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
AD633 - Low Cost Analog Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
ADno - RGB to NTSCIPAL Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
AD734 - 10 MHz, 4-Quadrant Multiplier/Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
AD834 - 500 MHz Four-Quadrant Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33
AD9300 - 4x I Wideband Video Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41
DAC-8408 DAC-8800 DAC-8840 DAC-8841 -

Quad 8-Bit Multiplying CMOS D/A Converter with Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Octal 8-Bit CMOS D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-Bit Octal4-Quadrant Multiplying CMOS TrimDAC" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-Bit Octal 2-Quadrant Multiplying CMOS TrimDAC" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-49
8-63
8-77
8-87

Digital Signal Processing Products - Section 9 .................................. 9-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
ADDS-2100A-ICE - In-Circuit Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
ADDS-2101-EZ - EZ-Tools Hardware Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
ADDS-2101-ICE - In-Circuit Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
ADDS-2IXX-SW - ADSP-2100 Family Development Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
ADDS-21OXX - SW-ADSP-21000 Family Development Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
ADSP-2100/2100A - 12.5 MIPS DSP Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
ADSP-2101 - DSP Microcomputer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
ADSP-2105 - DSP Microcomputer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23
ADSP-2111 - DSP Microcomputer with Host Interface Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29
ADSP-21020 - IEEE Floating-Point DSP Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33

Other Products - Section 10 .................................................... 10-1
Analog-to-Digital Converters Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
Digital-to-Analog Converters Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
Operational Amplifiers Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16

Application Notes - Section 11 ................................................. 11-1
AN-IS - Minimization of Noise in Operational Amplifier Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
AN-102 - Very Low Noise Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
AN-lOS - Applications of the MAT-04, A Monolithic Matched Quad Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
AN-ll1 - A Balanced Summing Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27
AN-112 - A Balanced Input High Level Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
AN-I 13 - An Unbalanced, Virtual Ground Summing Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31
AN-114 - A High Performance Transformer - Coupled Microphone Preamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33
AN-115 - Balanced, Low Noise Microphone Preamplifier Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35
AN-116 - AGe Amplifier Design with Adjustable Attack and Release Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37
AN-121 - High Performance Stereo Routing Switcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39
AN-122 - A Balanced Mute Circuit for Audio Mixing Consoles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43
AN-123 - A Constant Power "Pan" Control Circuit for Microphone Audio Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45
GENERAL INFORMA TlON 1-9

II

Page
AN-124 - Three High Accuracy RIAAlIEC MC and MM Phono Preamplifiers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-47

AN-l2S - A Two-Channel Dynamic Filter Noise Reduction System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-53
AN-127 - An Unbalanced Mute Circuit for Audio Mixing Channels

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-55

AN-l28 - A Two-Channel Noise Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-57
AN-129 - A Precision Sum and Difference (Audio Matrix) Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-59
AN-130 - A Two-Band Audio Compressor/Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-61
AN-131 - A Two-Channel VCA Level (Volume) Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-63
AN-133 - A High-Performance Compandor for Wireless Audio Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-65
AN-134 - An Automatic Microphone Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-69
AN-135 - The Morgan Compressor/Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-73
AN-136 - An Ultra!ow Noise Preamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-81
AN-142 - Voltage Adjustment Applications of the DAC-8800 TrimDAC", an Octal, 8-Bit D/A Converter

. . . . . . . . . . 11-83

AN-201 - How to Test Basic Operational Amplifier Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-97
AN-202 - An I.C. Amplifier Users' Guide to Decoupling, Grounding, and Making Things Go Right for a Change . . . . . 11-101
AN-20S - Video Formats & Required Load Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-109
AN-206 - Analog Panning Circuit Provides Almost Constant Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-113
AN-207 - Interfacing Two 16-Bit ADl8S6 (ADl8S1) Audio DACs with the Philips SAA7220 Digital Filter . . . . . . . . . 11-117
AN-208 - Understanding LOGDACs" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-121
AN-209 - 8th Order Programmable Low Pass Analog Filter Using Dual 12-Bit DACs . . . . . . . . . . . . . . . . . . . . . . . 11-125
AN-211 - The Alexander Current Feedback Audio Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-133
AN-212 - Using the AD834 in DC to 500 MHz Applications RMS-to-DC Conversion,
Voltage-Controlled Amplifiers and Video Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-149
AN-213 - Low-Cost, Two-Chip Voltage-Controlled Amplifier and Video Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-159
AN-214 - Ground Rules for High-Speed Circuit Layout and Wiring Are Critical in Video-Converter Circuits,
How to Keep Interference to a Minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-165
AN-21SA - Designer's Guide to Flash-ADC Testing - Part 1, Flash ADCs Provide the Basis for
High Speed Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-169
AN-2lSB - Designers' Guide to Flash-ADC Testing - Part 2, DSP Test Techniques Keep Flash ADCs in Check . . . . . 11-177
AN-21SC - Designers' Guide to Flash-ADC Testing - Part 3, Measure Flash-ADC Performance
for Trouble-Free Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-183
AN-216 - Video VCAs and Keyers Using the AD834 and AD811 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-193
AN-217 - Audio Applications of the ADSP Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-201
AN-218 - DSP Multirate Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-205
AN-219 - Electronic Adjustment Made Easy with the TrimDAC"

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-215

Package Information - Section 12 .............................................. 12-1
Appendix- Section 13 ......................................................... 13-1
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Technical· Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Worldwide Sales Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . 13-8

Index - Section 14 ............................................................. 14-1
Application Notes by Topic ., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
Application Notes by Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
Alphanumeric Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4

1-10 GENERAL INFORMATION

Selection Guide
Operational Amplifiers
Video Amplifiers
Model

SR
~P
VI".s deg
typ
typ

%
typ

Settling
Time
nsto%
typ

AD811

2500

0.01

65--0.01

120

AD844
OPI60
OP260
AD5539
AD846
AD840
AD842
AD841
AD847
AD827
AD829
AD848
AD849
AD843
OP64
AD845

2000 0.D25 0.008
1300 0.04 0.04
1000 0.067 0.02
600
0.1
0.04
450
0.03 0.Dl
400
0.04 0.025
375
0.035 0.015
300
0.02 0.03
300
0.04
0.2
300
0.2
0.04
300
0.04 0.02
300
0.08 0.07
300
0.04 0.08
250 1).025 0.025
170
0.018 0.045
100
0.025 0.04

100--0.1
75--0.1
250--0.1
12-1
110--0.01
100--0.01
100--0.01
1l0--0.Dl
120--0.1
120--0.1
90--0.1
100--0.1
80--0.1
135--0.01
100--0.1
350--0.01

60
90
90
220
80
40
40
40
50
50
50
35
30
34
16
16

0.01

~G

BWat

Input
Bias
Current
".A max

Voltage
Noise
lOUT Supply
nVIVHz
rnA
Range
@ 10 kHz min
±Volts

Supply
Current Spice
Model
rnA
typ
Avail. Page

3

10

2

100

4.5 to 18

16.5

-I
I
I
2
-I
10
2

0.15
5
3.5
3
0.075
0.3

I
1
5
2S
1
5

2
0.5

0.25
20
8
13
0.25
5
5
5
5
7
7
5
5
0.001

2
5.5
5.5
6
2
4
9
13
15
15
2
5
3
19
8
18

20
35
35
15
20
50
100
50
20
20
20
20
20
50
50
25

4.5 to 18
4 to 15
4 to 15
4.5 to 10
5 to 18
5 to 18
5 to 18
5 to 18
4.5 to 18
4.5 to 18
4.5 to 18
4.5 to 18
4.5 to 18
4.5 to 18
5 to 18
4.75 to 18

6.5
6.5
9
14
5
10.5
13
II
5.3
10
5
5.1
5.1
12
6.2
10

Ac, Min Ac,
MHz
typ

Vos
VN mV
min max

0.75
1
1
0.25

0.001

X

X
X
X
X

X
X
X
X

X

2-41
2-101
2-225
2-267
2-153
2-121
2-65
2-81
2-73
2-133
2-45
2-53
2-145
2-145
2-89
2-211
2-113

Comments
Best Video Specifications Flatness = 0.1 dB
to 35 MHz
Constant 10 ns Rise Time for Any Pulse
Disable Mode for Low Power Applications
Dual OP160; Only Dual Transimpedance
Improved Replacement for Industry Standard
Highest DC Precision High Speed Amplifier
Fast Settling Time; Gain > 10
High Current Output; Gain > 2
Fast Settling Time and Unity Gain Stable
General Purpose, Low Power, Unity Gain
Dual AD847
Low Noise and High Speed
General Purpose, Low Power, Gain > 5
General Purpose, Low Power Preamplifier
High Performance, Replaces LH0032
Stable for Gains> 5
General Purpose. Unity Gain Stable

~
~
~
.....
~

(S
lJ

~

:::!

,.~

•

I'

;;;

Selection Guide

~~ Operational Amplifiers
.....
~

Audio Amplifiers

:0

Single Op Amps

cg
~

SR
V/p.s

GBW
MHz

Model

Voltage Noise
@lkHz
nV/Viii typ

typ

typ

AD829
AD846
AD844
OP27
OP37
OP61
SSM2134
OPI60
OP64
SSM2131
AD7ll
AD843
AD845

2
2
2
3
3
3.4
3.5
5.5
8
13
18
19
25

300
450
2000
2.8
17
40
13
1300
170
50
20
250
100

750
80
60
8
63
200
10
90
80
10
4

:::!
0
 Serial Data In

Digital Signal Processing Products
DSP Processor Key Feature Summary
Model

Instruction
Cycle
Time
ns

ADSP2100A
ADSP-2101
ADSP-210S
ADSP-2111

80
60
100
60

Internal
Off·Chip Program
Harvard Memory
Arch
RAM

Internal
Data
Memory
RAM

Internal
Program
Cache
Word

Program
Memory
Boot

Serial
Ports

16 x 24
2K x 24
lK x 24
2K x 24

lK x 16
O.SK x 16
lK x 16

2
1
2

Programmable
Timer

Low
Power
Modes

Pin
Count

Page

4
3
3
3

100
68
68
100

9-13
9-17
9-23
9-29

4

223

9-33

Ext
Interrupts

32140-Bit Floating Point
ADSP-21020

40

32 x48

~
~
~
r~

~
~

~

:::l

~
I

iO

•

Product Assurance
PRODUCT ASSURANCE OVERVIEW
Introduction
Analog Devices has long been a leader in its innovations of analog integrated circuit design, processing, and testing. Of equal
importance to innovation is its commitment to continuous
improvement of quality, reliability and excellence in service.
Achieving, and continuously striving to improve the quality and
reliability have led to Analog's success as a world-recognized,
leading supplier of analog integrated circuits.
Product Assurance Philosophy
Product Assurance's role within Analog Devices is many faceted. All of the traditional roles of Product Assurance are maintained, including Military Programs management, QAlReliability
conformance inspections, specification control, auditing, failure
analysis, corrective action, calibration systems, as well as many
other functions. In addition, Analog's Product Assurance
departments maintain an active role in servicing internal operational entities' requirements as well as our customers' needs.
This is accomplished through various programs aimed at
improving product quality, reliability and service.
Continuous Improvement and Statistical Process Control
Programs
Fundamental to our beliefs about manufacturing success is that
quality and reliability are not inspected into the process as was
the historical methodology, but instead built into the process
from the outset. In order to be successful at consistently providing excellence in all areas, it is essential that the processes be
measured, understood, and have controlled variance. Keeping
this in mind, ADI has been aggressively pursuing statistical process control.
ADI is engaged in continuous improvement as an integral portion of our cultural development. The overall intent of this process has been to create an environment in which each employee
is trained and is empowered to change and to improve the process. Essential to this environment are the absence of fear and
an active encouragement to take risks to improve.
All manufacturing and related service personnel are trained in
the concepts of problem solving and statistical process control
(SPC) techniques. SPC training is also an orientation requirement for all new employees.
Quality improvement teams are continually being formed, as
opportunities to improve and to implement change are identified. These groups have addressed many issues and have had a
dramatic effect on ADI's manufacturing and administrative processes. These teams have typically crossed departmental and
functional lines, as the effects of change or the type of problem
could not be solved without cooperation and resultant expanded
knowledge bases.

1-:20 GENERAL INFORMA TlON

PRODUCT RELIABILITY
Reliability Assurance Programs
Reliability assurance programs at Analog Devices are designed
to encompass all aspects necessary to achieve and to improve
product performance and lifetimes. We recognize that reliability
cannot be tested or screened in if the aggressive goals set by
both our customers as well as ourselves are to be met.
The major areas of focus within Analog Devices include:
Design For Manufacturability (Design for Success). Product
and process designs focus on achieving product performance and
"building-in reliability." Causes for degraded reliability performance must be well understood and controlled. Reliability
design rules, updated frequently as experience grows and the
industry matures, are essential to improving product performance.
Process Capability. A new or an established process must not
only be capable of meeting specification limits but must also
exhibit a sufficient safety margin to ensure continued performance over the product life.
Manufacturing Process Control. Of utmost importance is the
control of the manufacturing environment under which product
is fabricated, assembled, tested or stored. Temperature, humidity, particulate, ionic contamination and equipment interactions·
must be well understood and controlled.
Process Monitoring. 100% inspections or sampling points of
key parameters with appropriate controls on output are utilized
throughout the manufacturing process. These include the following as listed in order of timeliness of information feedback:
In-line or in-situ measurements utilizing SPC.
Process step specific.
Wafer ship measurements.
Wafer level testing; i.e., sort, wafer level stress testing.
Die visual quality.
Final electrical testing after assembly.
Reliability stress testing of customer-ready finished goods.
CUstomer feedback.
Program Goal
Our goal is to provide our customers with the highest level of
reliability performance obtainable. It is a Program which is, by
its nature at Analog Devices, an integral part of all new products and process introductions, as well as all changes made
within the products, processes or facilities for which it measures.
Reliability Qualification Program
Analog Devices maintains a reliability qualification program that
includes extensive use of accelerated stress testing. The program's intent is not only to meet the requirements of the military programs but also to provide products in plastic which, at
minimum, meet or exceed world-class standards of excellence.
All new processes and facilities are qualified. Any changes to
existing qualified processes are also qualified as appropriate (see
Process Change Notification section).

Reliability Monitor/Audit Program
Periodic monitoring of all fabrication and assembly locations is
performed. The monitoring program uses highly accelerated
stress testing in order to monitor our various processes. The
program is geared to fabrication process and packaging families.
Process Change Notification System
Analog Devices has a standard procedure and criteria for classifying and controlling changes to our processes, packages, materials, facilities and manufacturing techniques. This system
includes technical reviews of proposed changes, qualification
plans including all considerations of MIL-M-385 10, customer
specification, as well as AD!'s internal qualification requirements. Included in this program is a system to notify customers
of the proposed changes in a timely fashion.
Reliability Defmitions and Theory
Reliability The probability that a device or system will perform
a required function satisfactorily or without failure (within specification limits) under stated conditions for a stated period of
time. Reliability is described as a mathematical expression of
probability.
Hazard Rate The instantaneous rate of failure for units of the
population that have survived to a given time.

Table I. Early Life Failure Mechanisms (Infant Mortality)
Failure Mechanism Defect
Thin or defective
oxide (masking
and oxidation)

System electrical
noise/transients.
System power
interruptions.
Inductive loading.

Open wire bonds

Assembly defects

Ultrasonic exposure during
printed circuit
board assembly.
Excessive burn-in
temperatures.

Lifted die bonds

Assembly defects

Excessive burn-in
temperatures.

Fused die
metallization

EARLY LIFE

FAILURE
RATE

A(I)

WEAR-OUT

"CONSTANT" fAILURE RATE LIFE

System electrical
noise/transients.
System power
interruptions.
Inductive loading.

Shofts

Inadequate spacing
between adjacent
traces.

Opens

Inadequate trace
width (masking
and evaporation)

Failure Usually involves the degradation in performance to
specified parameters which are typically electrically measurable.
Semiconductor failure patterns follow that of long-life devices
and are typically described by the so-called "Bathtub Curve,"
named for its shape, as shown in Figure 1. There are three distinct regions on this curve: Early Life, Constant Failure Rate
Life, and Wear-Out.

Stress Factors

Oxide ruptures

Corrosion of wire
bonds andlor die
metallization

Seal leaks
(defective
encapsulation);
poor lead frame/plastic
adhesion at
interface

Handling damage.
Excessive solder
heat during printed
circuit board
assembly. Ionic
contamination.

L-=:l::==:...:::.==:::j:::"'_
TIME-t

Figure 1. Semiconductor Failure Rate "Bathtub Curve"
Early Life Sometimes called infant mortality, early or initial
failure time. This region may exhibit a high initial failure rate
compared to the remaining population, typically because of
defects from the manufacturing or assembly process. To a user
the failures can also exhibit themselves due to debugging or misuse. Refer to Table I. Early failure rate reduction programs are
in place throughout Analog Devices.

Constant Failure Rate Region Also called the intrinsic or accidental failure time and is considered the useful life region of the
product. This region is a mixture of any of the remaining manufacturing defects which require longer times to fail as well as the
failures from the main distribution of the product.
Wear-out Region Alternately referred to as the degradation
period. The failure rate continuously increases with time. Under
typical use conditions, silicon semiconductor devices will never
approach this region relative to system life expectancies (see
Table II).

GENERAL INFORMATION 1-21

II

Table II. Wearout Failure Mechanisms
Failure Mechanism Defect Observed

Contributing Factors

Electromigration

Voids, oPen
circuits, 'hillock
or metal
accumulation.

Grain boundary
diffusion. Grain
size and distribution.
Fiber texture.

Slow Trapping
charge injection

Electrical
degradation

Structural defects
related to the
oxidation process.
Metallic impurities.
Bond breaking
processes.

Charge
Accumulation
mobile ions

Electrical
degradation

Alkali ions-sodium,
potassium and
lithium in the oxide.
Other negative ions!
heavy metals.

Intermetallic
Growth in
AI-Au wire
bonds

Highly resistive
bonds. Open
circuit at bond.
Bond lift failures.

Kirkendahi Voiding.
Diffusion of Al into
Au.

Wire and Wire
Bond Failures
during thermal
cycling

Open/intermittent A fatigue mechanism.
circuits.
Thermal mismatch.
Short circuits.
Stress induced wire
creep. Intermetallics.
Wire Length not
optimized
Too taut-breakage
Too long -sag.

Life Distributions
Time-to-failure data is analyzed in order to predict the future
reliability of the product. Four .life distributions are typically
used in the analysis of silicon semiconductor reliability.
1. Normal Distribution Function-Describe the wear-out region
where there exists a monotonically increasing failure rate with
respect to time.

2. Lognormal Distribution Function- The. natural logarithm of
the failure time is distributed normally. Extensive use of this
,distribution occurs, as it can be used to fit many different
kinds of data.
3. Weibull Distribution Function-In this case the hazard rate
varies as a power of device age. The failure-rate curve does
not start at zero as is the case of the lognormal distribution.
4. Exponential Distribution Function - This distribution is used
when the failure rate is constant. Failures occur randomly
and are characteristic of the constant failure rate region of the
"Bathtub Curve."

1-22 GENERAL INFORMA TlON

Accelerated Life Stress Testing
It is possible to evaluate the early life reliability levels from
short-term burn-ins, customer system burn-ins, and early failure
rates in the field. It is not practical, however, to evaluate the
useful life' or wear-out failure rates from these same sources.
The amount of time necessary to obtain statistically significant
data far exceeds the useful life of most systems. Obtaining data
about the life of a semiconductor beyond the infant stage
requires a higher than normal stress level to be applied to the
device. In practice, a sample of devices of sufficient quantity to
statistically represent the population is subjected to stress levels
from various types of environmental stimuli to evaluate these
failure levels and mechanisms. This type of testing is known as
accelerated stress testing.
The time and temperature dependences of most semiconductor
failure mechanisms over the life of a product have been studied
and quantified. The established relationship between time,
temperature, and particular failUre mechanisms has been
demonstrated to be a log-nortnai function capable of being represented by the "Arrhenius" mOdel that includes the effects of
temperature and activation energy of the failure mechanisms.
It is possible, by using the model, to characterize failure modes
from accelerated stress testing, and then to predict reliability
levels at normal, nonaccelerated conditions. .As applied to accelerated life testing of semiconductors, the
Arrhenius model assumes that the degradation of a performance
parameter is linear with respect to time, with the mean time
between failures (MTBF) as a function of the temperature
stress. The temperature dependence is taken to be the exponential function that defmes the probability of occurrence, resulting
in the following formula for defming the lifetime or MTBF at a
given temperature stress level:
tl = t z exp[E.lk(11T1

-

IlT z)]

where:
MTBF at junction temperature TI
MFBF at junction temperature T z
junction temperature in OK
thermal activation energy in electron volts (eV)
Boltzman'sconstant (8.617 x 10- 5 eVfK
The activation energy in this formula is the mean E. for aU of
the failure mechanisms of the particular product line for which
the calculation is being done. These activation energies are
established by the examination of failures from stress testing.
See Table III.

Table III. Time-Dependent Failure Mechanisms in Silicon Semiconductor Devices'
Device
Association

Failure
Mechanism

Relevant
Factors

Acceleration
Factors

Acceleration
(Ea eV = Apparent Activation Energy)

Silicon Oxide
and
Silicon-Silicon
Oxide Interface

Surface Charge
Accumulation

Mobile ions
V,T

T

Ea = 1.0 - 1.5 eV
depends on ion density

Metallization

Bonds and Other
Mechanical Interfaces

Hermeticity

Dielectric Breakdown

EF,T

EF,T

Ea = 0.2 - 1.0 eV, EF, (T) = I - 4.4

Charge Injection

EF, T, Qf

EF,T

Ea = 1.3 eV (slow trapping)
Ea = -I eV (hot electron ejection)

Electromigration

T, J, A, Gradients of
T and J, Grain Size

T, J

Ea = 0.5 - 1.2 eV
J, (T) = 1-4

Corrosion
(chemical, galvanic,
electrolytic)

Contamination
H,V,T

H,V,T

Strong H effect
Ea = 0.3 - 1.1 eV (for electrolysis)
V may have thresholds

Contact Degradation

T, Metals, Impurities

Varied

Intermetallic Growth

T, Impurities,
Bond Strength

T

Fatigue

Bond Strength,
Temperature Cycling

Temperature
extremes in
cycling

Seal Leaks

Pressure Differential,
Atmosphere

Pressure

Al - Au: Ea = 1.0 - 1.05 eV

NOTE
V~voltage, T~temperature;

EF-electric field; J-current density; A-area; H-humidity; Qf-charge
ID. S. Peck, "Practical Applications of Accelerated Testing-Introduction," Reliability Physics, 13th Annual Proceedings, 1975, pp. 253-254.

Reliability Testing

Methods

Standards Conformance. Test methods to confirm the reliability of Analog Devices product are detailed below, and are determined prinIarily through conformance to the various industry
standards. These include MIL-STD, JEDEC, IEC, JIS, and
EIAJ.

High Temperature Operating Life Test (HTOL). The operating life test demonstrates the quality or reliability of devices
subjected to the specified conditions over an extended twe
period. HTOL stressing applies a static DC bias at an elevated
ambient temperature. This bias is maintained throughout the
duration of the test as well as during cool-down from elevated
temperature after stress. HTOL testing is particularly useful
because it provides a means of accelerated time-to-failure of temperature sensitive failure mechanisms.

I. MIL-STD - U.S. Military Standards:
MIL-STD-750 Test Methods for Semiconductor Devices
MIL-STD-202 Test Methods for Electronics and Electrical
Component
MIL-STD-883 Test Methods and Procedures for Microelectronics
2. JEDEC
3. JIS - Japanese Industrial Standards:
JIS-C-7022 Environmental Testing Methods and Endurance
Testing Methods for Semiconductor Integrated Circuits.
4. IEC Standard:
Publication 68 Basic Environmental Testing Procedures.
5. EIAJ Standard:
IC-121 Test Methods for Reliability of Integrated Circuits.

High Temperature Storage Life Test (HTSL). High temperature storage life testing is performed in order to demonstrate the
quality or reliability of devices subjected to elevated temperature
storage conditions without electrical bias.
Thermal Shock (TMSK). Thermal shock testing demonstrates
the qualiry or reliability of devices exposed to extreme changes
in temperature, especially to alternating extremes. The change
in temperature is quite rapid as the heat transfer is by conduction and the transfer time from one temperature extreme to
another in minimal «10 sec.). Thermal shock testing induces
mechanical stresses caused by thermal expansion and contraction. These stresses can be extreme, especially in plastic molded
devices where large differences in the thermal coefficients of
expansion between the die, leadframe and plastic material can
exist. This is especially critical for large dies where the stress
can be too severe and will induce failures that would not be

GENERAL INFORMA TION 1-23

•

expected in a real application. As a result of the permanent
changes in electrical and mechanical characteristics and/or physical damage that may result from thermal shock, any tests in
which the duration is greater than ten cycles shall be considered
destructive.
'
Temperature Cycle (TMCL). Temperature cycle testing is
performed to demonstrate the quality or reliability of devices
exposed to the extremes of high and low temperatures, and
especially to alternating extremes. TMCL testing more closely
relates to actual use conditions as the temperature change of the
device is due to convection and, therefore, is at a slower rate
than thermal shock. This slower rate of change will more closely
simulate such use conditions as the transfer to or from heated
storage in cold climates, or where ambient temperature is
relatively mild but heats up greatly as the system is operating.
This is a very good test to measure the overall die-to-package
compatibility.
Temperature and Humidity Life (THB). Temperature and
humidity life testing demonstrates the quality or reliability of
devices exposed to the combination of high temperature and
high humidity, with an applied voltage bias. Maximum bias
voltage levels are desired as this bias accelerates any electrolysis
of the device metalization as well as increasing ion mobility. At
the same time, device power dissipation is desired to be minimized as any localized heating at die level will tend to lower the
humidity level at the die surface and lessen the electrolysis
potential. In certain cases, power cycling must be used in order
to permit moisture accumulation on die surface during the
"power-off" periods.
AutoclavelPressure Pot (PTH). Autoclave testing evaluates the
quality and reliability of devices exposed to a saturated humidity
and high temperature environment under pressure. This test is
performed without bias, and therefore, once equilibrium is
reached, the die temperature and relative humidity will be the
same as the external environment. PTH conditions, although
not typical of actual operating environments, are very effective
at evaluating the moisture resistance of a device/package combination in a relatively short period of time.
Biased Pressure Pot (HAST). Biased pressure pot testing evaluates the quality and reliability of devices urider bias subjected
to a humid, high temperature environment under pressure. This
test can be considered an acceleration of the THB test due to
the elevated temperature and steam environment which is under
pressure. Biasing guidelines are the same as for THB testing,
with an additional consideration: because of the elevated temperature, certain high power devices will dissipate sufficient power
to elevate the die temperature above the glassivation temperature
of the plastic molding compound. This,could occur even though
power cycling techuiques are employed. This condition is not
desired as abnormal conditions not related to real operating conditions could e,ast, resulting in anomalous failure mechanisms.
Resistance to Solder Heat (RTSH). Resistance to solder heat
evaluates the ability of a product/package to withstand the
worst-case heat cycles that could be encountered during normal
printed circuit board assembly.

1-24 GENERAL INFORMATION

QUALITY ASSURANCE
Vendor Assurance Programs
Analog maintains an active program with its vendors to ensure
that the highest standards of quality are met. The program
focuses on many key areas including vendor qualification and
certifications, periodic vendor audits, rigorous incoming inspection of fit, form, and function, as well as tracking the vendor
performance over time.
Analog Devices has established minimum standards of performance for our vendors, who are audited for compliance to minimum standards. We then rate each vendor on the quality and
delivery of incoming material. It.is through this program that
we can assess and then purchase material based upon cost-ofownership. This contrasts to buying strictly on purchase price,
as the purchase price alone does not completely reflect the total
cost. Another benefit of our vendor quality program is that we
have the necessary information to work in partnership with our
vendors to continuously evaluate and improve the quality of
incoming product.
Incoming Quality Assurance (IQA)
Analog Devices' IQA orgauization performs deta.iled inspections
of vendor quality performance. Conformance to specification is
directly measured to ensure compliance with the specified
requirements. When a fa.ilure to meet the requirements is discovered, a corrective action from the vendor is required. Extensive follow-up is done to ensure future and continued
compliance.
Vendor Audits
Analog Devices performs periodic audits of all of its
manufacturing-related vendors. ADI performs these audits to
assess compliance to MIL-Q-9858 and MIL-I-45208. Corrective
action requests are issued with deadlines for compliance appropriate to the noncompliance. These audits are ,also used to discuss both open and closed quality, reliability, and service issues.
Through this extensive interaction, ADI has been able to continuously improve the quality and reliability of incoming materials.
QUALITY CONTROL SYSTEMS
Corrective Action
An active, internal, closed loop-corrective action system has
been utilized for many years both to commumcate deficiencies
as well as to provide traceability of corrective actions. This system has been a key element of process audits and customer
return issues. The program has been very effective in correcting
deficiencies in a timely manner.
Traceability and Recerd Retention
Traceability after shipment is maintained through actual marking of devices with lot identifiers. This information will provide
traceability through assembly and wafer fabrication for all
devices. This traceability allows for very good control of products as well as for direct correlation of products to time of process, machines, processes, and other pertinent related items.

Control of Nonconforming Material
Whenever nonconforming material is found, it is put under control for disposition. This holding of material is done at all stages
in the process from incoming inspection through all inventory
locations. Response to hold requests, whenever necessary, is
quick and complete.
Process Audits - Fab, Assembly, and Test
In addition to auditing our venders, ADI has an ongoing internal process auditing group. This group audits all of Analog's
manufacturing areas to ensure compliance to specification. In
addition, selected service areas are audited where appropriate.
Dedicated process auditors perform verifications in wafer fabrication, assembly and test. All types of critiques are used to
review compliance, and the results are reviewed with appropriate supervisors and managers. The criticality of all deficient
items is assessed and appropriate action is taken. Periodic
reports are also issued to all levels of management.
Quality Conformance Inspections (QCI)
In-process QCI is employed throughout the manufacturing process to verify compliance to specification. All QCI is performed
to specification and results are tracked and reported as appropriate. The QCI inspections include both very traditional and innovative methods to measure and to control product conformance.
These inspections provide very valuable information about the
processes they measure. Analog Devices uses these inspections
and the results obtained to enhance, where appropriate, our statistical process control program.
Average Outgoing Quality (AOQL)
At the end of manufacturing processing, just prior to moving
product into finished goods inventory, product is sampled for
electrical, visual/mechanical and hermeticity to determine compliance to the requirements. The sampling and results include
all products released to production and, therefore, include all
new products and packages. These performance levels are
tracked in very precise detail. Results of this inspection determine ADI's reported AOQ.
Added to this very extensive sampling program are quality
improvement teams to address the findings. These teams meet
on an ongoing basis to review the results, to determine root
causes and to correct the processes as appropriate.
CUSTOMER SERVICE
Regional Customer Service Centers
Responsiveness to customer problems is a key factor in maintaining a leadership position in today's semiconductor marketplace. In order to improve support to Analog Devices' customers,
five Regional Customer Service Centers have been established
worldwide. These locations are strategically located within direct
reach of our customers without having time zone logistics issues.
Two centers are established in Asia (Japan/Taiwan), two are in
the USA (Boston, MAiSanta Clara, CAl, and one is in Europe
(Ireland). These centers will provide Engineering Support to
customers in the areas of failure analysis, problem resolution
and reliability information.

The goals established for the Regional Customer Service Centers
include the following:
• Assume regional failure analysis responsibility for all ADI
monolithic products.
• Provide rapid response to customer perceived problems
through correlation, failure analysis results and failure analysis.
• Minimize the impact of a field performance problem by
immediate, on-site interaction with the customer.
• Provide to ADI a "voice of the customer" for field performance information.
• Improve customer satisfaction and become a competitive tool
for ADI.
• Maintain the technical expertise required to meet customer
and factory needs.
• Provide a single point of contact for all quality and failure
analysis issues.
Customer Returns
The customer returns processing area, as well as evaluations of
returned material, is administered by the Quality Assurance
Engineering organization. QA Engineering receives the returned
material, and also controls it until disposition. All customer
returns are reviewed, verified, and/or failure analyzed as appropriate. Formal reports of fmdings are issued and appropriate
actions are taken.
Periodic reports are issued to all levels of management and engineering. The reports provide details of any returned material as
well as trend information to highlight appropriate areas for
action.
The extensive evaluations of customer returns have, over time,
been one of the more valuable feedbacks from the customer to
ADI's internal systems. By directly working with both ADI's
engineering and the customer, Analog has been able to supply
its customers with the highest level of qUality. Consistent processing and delivery of quality product that meets the customer's expectations are direct results of close working relationships.
Failure Analysis
Analog maintains a full service analytical laboratory staffed with
professional engineers and technicians who analyze failures. The
purpose of the laboratory is to provide, through detailed analysis, timely and effective feedback to customers on the quality
and reliability of Analog's product. The analysis will involve the
identification of the failure modes and mechanisms and probable
failure causes. A complete written report is then supplied to the
customer describing in detail the exact steps taken during the
analysis and any conclusions drawn from the analysis. Where
necessary, corrective actions are initiated based on the results
and conclusions of the analysis. Thus, the results of analysis
performed are fed back into the manufacturing process to continually improve the quality and reliability of Analog's product.
A flow of how Analog handles customer failure analysis is shown
in Figure 2. Figure 3 shows a failure analysis approach diagram
and Figure 4 shows a generalized failure analysis flow diagram.

GENERAL INFORMA TlON 1-25

II

A flow of how Analog handles customer failure analysis is shown
in Figure 2. Figure 3 shows a failure analysis approach diagram
and Figure 4 shows a generalized failure analysis flow diagram.

Reports Incidence of Failure to
Sales Personnel.
Completes Failure Analysis Input
Request (FAIR) Fonn

.i1d Transfers

(CONSULTAnON)

Devices from Customer to Failure
Analysis O1rectty or Via Customer

service.

ENVIRONMENTAL

Transfers FAIR Form and devices to
Failure Analysis. Lisees With Failure

TEST
• TIC
• TIS
MONITORED
VIBRAnON ETC

Analysis and Sales/Customer.

Complete Failure Analysis on
Devices. Provide Customer WHh a
Written Report Detailing Analysis
Results. Initiate Corrective Actions
Resulting From Analysis.

Figure 2. Failure Handling Procedure

--,

r-,..._-1-_-,
I SEM/EMA I

I ANALVStS
L..
____ ....II

rA~Rl

I SURFACE I
IL..ANALYSIS
____ ..JI

Figure 3. Failure Analysis Approach Flow Diagram

Figure 4. Generalized Failure Analysis Flow

1-26 GENERAL INFORMA TION

Table IV. Failure Modes
Failure Mode

Definition

Effect on Device or Ie

I. Internal Short

Short Circuit between Metallized Leads or Across
Junction.

Short Circuit or Circuit Malfunction.

2. Internal Open

Open Circuit in the Metallization or Wire Bond

Open Circuit

3. Parametric Variation

Variation in Gain or Other Electrical Parameter

Marginal Performance, Temperature Sensitivity,
or No Effect

4. Junction Leakage

Leakage Current Across P-N Junctions.

Effects Range from None to Malfunctions.

5. Threshold Shift

Sruft in Turn-on Voltage.

Random Logic Malfunction

6. Seal Integrity

Ingress of Ambient Air, Moisture andlor Contaminants.

Effects Range from Degradation to Complete
Malfunction.

Following are defmitions used in ADI failure analysis:

Failure mode - the characteristic of a device for which the
device has been characterized a failure, i.e., deviation from a
specification or desired performance. A summary of failure
modes is given in Table IV.
Failure mechanism - a physical process which leads to failure.
The "physics of failure."
Ionic contamination - ionic species in the passivation layers can
cause permanent or temporary threshold voltage srufts of the
silicon surface below. This may cause leakage (channeling)
between device elements resulting in nonfunctionality.
Electromigration - at high current densities atoms of the conductor material are swept along due to the momentum of the
electron "wind." Trus creates a depletion of conductor material
upwind and an accumulation downwind. Electromigration can
cause open circuits or short circuits between closely spaced conductor lines.

Electrostatic discharge (ESD) and electrical overstress (EOS) these are probably two of the most frequently identified failure
mechanisms. ESD, created by the exchange of charge between
two dissimilar materials, can cause pin junction damage as well
as rupture of dielectrics. Although it generally has a short pulse
width, the voltage and current transients generated can be
extremely large. EOS is characterized by excessive voltages or
currents that tend to be sustained for a much longer period than
ESD pulses. It will cause conductor or wire bond bum-out as
well as pin junction damage.
Corrosion - package environment, package moisture content,
glassivationlpassivation integrity, presence of ionic species and
electrical bias conditions can all contribute to corrosion. Corrosion occurs when two or more electrodes are present in an electrolyte (typically moisture) along with some ionic species
(contamination).
Figure 5 shows a summary of identified failure mechanisms
from 1983 to 1990.

Intermetallics - in the microdimensions of integrated circuits,
the interactions between dissimilar metals cannot be ignored.
These intermetallics can have radically different physical, chemical and electrical properties from those of the individual elements or compounds.
Radiation - the ionizing effects of radiation can generate
electron-hole pairs. Recombination of these electron-hole pairs
can result in latch-up, shorting paths, pin junction breakdown
and excessive leakage. Robustness to these radiation effects is
particularly important for semiconductors intended for space or
military applications.
Mechanical - thermal cycling or power cycling can lead to
device failure due to the differences in the coefficients of thermal expansion of the materials used in semiconductor manufacture. Coefficients of thermal expansion can range from 2 to over
40 ppml"C. Fatigue of bond wires can occur during ultrasonic
cleaning due to a high cycle fatigue mechanism. This happens in
hermetic packages that are ultrasonically cleaned in a tank
whose resonant frequency matches those of the bond wires.

Figure 5. Identified Failure Mechanisms (1983-1990)

GENERAL INFORMA TION 1-27

II

1-28 GENERAL INFORMA TION

Operational Amplifiers
Contents
Page

Operational Amplifiers - Section 2 .............................................. 2-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
AD711 - Precision, Low Cost, High Speed BiFET Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
AD712 - Dual Precision, Low Cost, High Speed, BiFET Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
AD713 - Quad Precision, Low Cost, High Speed BiFET Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
AD811 - High Performance Video Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
AD827 - High Speed, Low Power Dual Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45
AD829 - High Speed, Low Noise Video Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
AD840 - Wideband, Fast Settling Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
AD841 - Wideband, Unity-Gain Stable, Fast Settling Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73
AD842 - Wideband, High Output Current, Fast Settling Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81
AD843 - 34 MHz CBFET Fast Settling Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89
AD844 - 60 MHz, 2000 V/"..s Monolithic Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-101
AD845 - Precision, 16 MHz CBFET Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-113
AD846 - 450 VI"..s, Precision, Current Feedback Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-121
AD847 - High Speed, Low Power Monolithic Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-133
AD848/AD849 - High Speed, Low Power Monolithic Op Amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-145

AD5539
OP-27 OP-37 OP-61 -

- Ultrahigh Frequency Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Noise, Precision Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Noise, Precision High Speed Operational Amplifier (AvcL 2:5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wide-Bandwidth Precision Operational Amplifier (Av 2:IO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-153
2-169
2-181
2-193

OP-64 - High Speed, Wide-Bandwidth Operational Amplifier (AvCL2:5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-211
OP-160 - High Speed, Current Feedback Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-225
OP-249 - Dual, Precision JFET High Speed Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-249
OP-260 - Dual, High Speed, Current Feedback Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-267
OP-271 - High Speed, Dual Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-287
OP-275 - Dual Bipolar/JFET, Low Distortion Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-297
OP-471 - High Speed, Low Noise Quad Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-299
SSM-2131 - Ultralow Distortion, High Speed Audio Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-315
SSM-2134 - Low Noise, Audio Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-327
SSM-2139 - Dual, Low Noise, High Speed, Audio Operational Amplifier (AvcL2:3) . . . . . . . . . . . . . . . . . . . . . . . . 2-333

OPERA TlONAL AMPLIFIERS 2-1

II

'"

Selection Guide

~
~

Operational Amplifiers

0

Video Amplifiers

'I"
0

:::!

~

r--

h

~
:ngj
en

Model

SR
AP
V/".s deg
typ
typ

AG
%
typ

Settling
Time
nsto%
typ

BWat
AclMin ACl Vos
MHz
VN mV
typ
min max

Input
Bias
Current
".A max

nV/vHZ rnA
@ 10 kHz min

AD811

2500

0.01

0.01

65-0.01

120

3

10

2

AD844
OP160
OP260
AD5539
AD846
AD840
AD842
AD841
AD847
AD827
AD829
AD848
AD849
AD843
OP64
AD845

2000
1300
1000
600
450
400
375
300
300
300
300
300
300
250
170
100

0.025
0.04
0.067
0.1
0.03
0.04
0.035
0.02
0.2
0.2
0.04
0.08
0.04
0.025
0.018
0.025

0.008
0.04
0.02
0.04
0.01
0.025
0.015
0.03
0.04
0.04
0.D2
0.D7
0.08
0.025
0.045
0.04

100-0.1
75-0.1
250-0.1
12-1
llO-O.OI
100-0.01
100-0.01
110-0.01
120-0.1
120-0.1
90-0.1
100-0.1
80-0.1
135-0.01
100-0.1
350-0.01

60
90
90
220
80
40
40
40
50
50
50
35
30
34
16
16

0.15
5
3.5
3
0.075
0.3
1

0.25
20
8
13
0.25
5
5
5
5
7
7
5
5
0.001
1
0.001

2
5.5
5.5
6
2
4
9
13
15
15
2
5
3
19
8
18

-I
1
1
2
-1
10
2

1
5
25
1
5
1

1
2
0.5
1
0.75
1
0.25

Voltage
Noise

Supply
Range
±Volts

Supply
Current Spice
rnA
Model
typ
Avail. Page

100

4.5 to 18

16.5

20
35
35
15
20
50
100
50
20
20
20
20
20
50
50
25

4.5 to 18
4 to 15
4 to 15
4.5 to 10
5 to 18
5 to 18
5 to 18
5 to 18
4.5 to 18
4.5 to 18
4.5 to 18
4.5 to 18
4.5 to 18
4.5 to 18
5 to 18
4.75 to 18

6.5
6.5
9
14
5
10.5
13
11
5.3
10
5
5.1
5.1
12
6.2
10

lOUT

X

X
X
X
X

X
X
X
X

X

2-41
2-101
2-225
2-267
2-153
2-121
2-65
2-81
2-73
2-133
2-45
2-53
2-145
2-145
2-89
2-211
2-113

Comments
Best Video Specifications Flatness = 0.1 dB
to 35 MHz
Constant 10 ns Rise Time for Any Pulse
Disable Mode for Low Power Applications
Dual OPI6O; Only Dual Transimpedance
Improved Replacement for Industry Standard
Highest DC Precision High Speed Amplifier
Fast Settling Time; Gain > 10
High Current Output; Gain > 2
Fast Settling Time and Unity Gain Stable
General Purpose, Low Power, Unity Gain
Dual AD847
Low Noise and High Speed
General Purpose, Low Power, Gain > 5
General Purpose, Low Power Preamplifier
High Performance, Replaces LH0032
Stable for Gains> 5
General Purpose. Unity Gain Stable

Audio Amplifiers
Single Op Amps
Model

Voltage Noise
@lkHz
nV/vHZtyp

SR
V/IJ-s
typ

AD829
AD846
AD844
OP27
OP37
OP61
SSM2134
OPI60
OP64
SSM2131
AD711
AD843
AD845

2
2
2
3
3
3.4
3.5
5.5
8
13
18
19
25

300
450
2000
2.8
17
40
13
1300
170
50
20
250
100

750
80
60
8
63
200
10
90
80
10
4

SR
V/IJ-s
typ

GBW

Model

Voltage Noise
@lkHz
nVtvHZtyp

SSM2139
OP275
OP260
OP271
OP249
AD712

3.6
5
6
7.6
17
18

11
20
1000
8.5
22
20

GBW

MHz
typ

34
16

Supply
Current
mAmax

VOUT Volts min

Page

Comments

6.8
6.5
7.5
4.67
4.67
8
6.5
8
8
6.5
2.8
13
12

500 n
500 n
500 n
600 n
600 n
500 n
600 n
500 n
200 n
= 1000 n
+ 13/-12.5, RL = 2000
±10, RL = 500 n
± 12.5, RL = 500 n

2-53
2-121
2-101
2-169
2-181
2-193
2-325
2-225
2-211
2-315
2-5
2-89
2-113

Ideal High Gain, Low Noise Input Device
Current Feedback
Low Noise, Highest Slew Rate
Low Cost, Precision
AVCL 2: 5, Low Cost
AVCL 2: 10
Improved 5532
Current Feedback
AVCL 2: 5, High Output Current
Ulttalow Distortion
Precision BiFET
Low Bias Current, Fast Settling
Low Bias Current, Faster Settling

±IO, RL =
±10, RL =
±10, RL =
±10, RL =
±10, RL =
±11, RL =
±12, RL =
±11, RL =
±10, RL =
±11.5, RL

n

Dual Op Amps
typ

Supply
Current
mAlAmpmax

VOUT
Volts
min

Page

Comments

30
8
90
5
4.7
4

3.25
2
5.25
3.25
3.5
2.8

±12, RL = 2000 n
±13, RL = 600 n
±12, RL = 1000 n
±12, RL = 2000 n
±12, RL = 2000 n
+ 13 -12.5, RL = 2000

2-331
2-297
2-267
2-287
2-249
2-17

AVCL 2: 3
Ulttalow Distortion
Current Feedback
Precision
Low Power, Low Distortion
Low Cost, Dual AD711

MHz

n

Quad Op Amps
SR

GBW

V/IJ-S

MHz

Model

Voltage Noise
@lkHz
nVtvHZtyp

typ

OP471
AD713

6.5
18

8
20

c

~
~
:::!

c

~

r-

l>

s::

;:2
5i
ii1

~
~

Co).

typ

Supply
Current
mAlAmpmax

VOUT
Volts
min

Page

Comments

6.5
4

2.75
3

±12, RL = 2000 n
+ 13/-12.5, RL = 2000

2-299
2-29

Precision
QuadAD711

n

2-4 OPERA TlONAL AMPLIFIERS

11IIIIIIII ANALOG
WDEVICES
FEATURES
Enhanced Replacement for LF411 and TL081
AC PERFORMANCE:
Settles to ±O.01% in 1",s
16V/",s min Slew Rate (AD711JI
3MHz min Unity Gain Bandwidth (AD711J1
DC PERFORMANCE:
O.25mV max Offset Voltage: (AD711CI
3",VI"C max Drift: (AD711CI
200V/mV min Open-Loop Gain (AD711KI
4",V p-p max Noise, O.1Hz to 10Hz (AD711CI
Available in Plastic Mini-DIP, Plastic SO, Hermetic
Cerdip, and Hermetic Metal Can Packages
MIL-STD-883B Parts Available
Available in Tape and Reel in Accordance with
EIA-481A Standard
Surface Mount (SOICI
Dual Version: AD712
Quad Version: AD713

PRODUCT DESCRIPTION
The AD71l is a high speed, precision monolithic operational
amplifier offering high performance at very modest prices. Its
very low offset voltage and offset voltage drift are the results of
advanced laser wafer trimming technology. These performance
benefits allow the user to easily upgrade existing designs that
use older precision BiFETs and, in many cases, bipolar op
amps.
The superior ac and dc performance of this op amp makes it
suitable for active filter applications. With a slew rate of 16V/ILS
and a settling time of IlLS to ±O.OI%, the AD71l is ideal as a
buffer for l2-bit D/A and AID Converters and as a high-speed
integrator. The settling time is unmatched by any similar IC
amplifier.
The combination of excellent noise performance and low input
current also make the AD7ll useful for photo diode preamps.
Common-mode rejection of 88dB and open loop gain of 400V/mV
ensure 12-bit performance even in high-speed uriity gain buffer
circuits.
The AD7ll is pinned out in a standard op amp configuration
and is available in seven performance grades. The AD7l iJ and
AD71lK are rated over the commercial temperature range of 0
to + 70°C. The AD7IlA, AD711B and AD711C are rated over
the industrial temperature range of - 40°C to + 85°C. The
AD71lS and AD711T are rated over the military temperature
range of - 55°C to + 125°C and are available processed to MILSTD-883B, Rev. C.

REV. A

Precision, Low Cost,
High Speed BiFET Op Amp
AD711 I
CONNECTION DIAGRAMS
Plastic Mini-DIP (N) Package
Plastic Small Outline (R)
and
Cerdip (Q) Package

TO-99
(H) Package
NC

INVERTING
INPUT

NONINVERTING
INPUT

vNOTE: PIN 4 CONNECTED TO CASE
NC = NO CONNECT

~

~-'5V

Vos TRIM

Extended reliability PLUS screeuing is available, specified over
the commercial and industrial temperature ranges. PLUS screening
includes 168-hour burn-in, as well as other environmental and
physical tests.
The AD711 is available in an 8-pin plastic mini-DIP, small
outline, cerdip, TO-99 metal can or in chip form.
PRODUCT HIGHLIGHTS
1. The AD711 offers excellent overall performance at very
competitive prices.
2. Analog Devices' advanced processing technology and with
100% testing guarantees a low input offset voltage (0.25mV
max, C grade, 2mV max, J grade). Input offset voltage is
specified in the warmed-up condition. Analog Devices' laser
wafer drift trimming process reduces input offset voltage
drifts to 3ILVrC max on the AD711C.
3. Along with precision dc performance, the AD71l offers
excellent dynamic response. It settles to ±0.01% in IlLS and
has a 100% tested minimum slew rate of 16V/ILS. Thus this
device is ideal for applications such as DAC and ADC buffers
which require a combination of superior ac and dc
performance.
4. The AD711 has a guaranteed and tested maximum voltage
noise of 4ILV p-p, 0.1 to 10Hz (AD711C).
5. Analog Devices' well-matched, ion-implanted JFETs ensure
a guaranteed input bias current (at either input) of 25pA max
(AD711C) and an input offset current of 10pA max (AD711C).
Both input bias current and input offset current are guaranteed
in the warmed-up condition.

OPERA TIONAL AMPLIFIERS 2-5

II

AD711-SPECIFICATIONS
Model

(@ +25°C and Vs

AD711JIAIS

Min
INPUT OFFSET VOLTAGE'
Initial Offset

Tn>

Max

0.3

211/1
3/2/2

Tmin toT.....

vs.Temp.
vs. Supply
VB. Supply, T min to T max:
Lolli Term Offset Stability

7
·95

76

Full Power Response
Stew Rate, Unity Gain

AD711KIIIIT
Typ
0.2

20120120
80
80

76176176
15

INPUT BIAS CURRENT'
Either Input, VeM == 0
Either Input at T_,
VCM ~0(70"C185"C1125"C)
Either Input, VCM ~ + IOV
Offset Current, VCM = 0
Offset Current at T mu.
(70"C185"C1125"C)
FREQUENCY RESPONSE
UnityGain, Small Signal

Mia

15

= ±15V dc, unless othelWise noted)

5
100

15

SO

4
200
20
I

16

Senling Time to 0.01%'

0.5
1.0
10

AD711C
Typ
0.1

86
86

2
110

20
5

100
25

SO

3.4

1.2

4
200
20
I

Unitt

0.25
0.45
3

mV
mV
fJ. VrC
dB
dB

fLVlmonth

IS

25
1.6

pA
nA

100
25

20
5

SO
10

pA
pA

0.65

nA

0.5711.6126

18

Mu

15

1.113.2151

0.57/1.6126
3.0

Mira

15

1.1/3.2/51
20
10

MOll

3.4
18

1.2

4
200
20
I

MHz
kHz
V/fJ.s

1.2

fJ.S

Total Harmonic Distortion
f~

1kHz
R L "'2k!l, Vo~ 3VRMS
INPUT IMPEDANCE
Differential
Conuuon-Mode

0.0003

0.0003

0.0003

%

3x 1012 115.5
3x 1012 115.5

3x 10 12 115.5
3x 10 12 115.5

3x 10 12 115.5
3x 1012 115.5

IlllpF
IlllpF

INPUT VOLTAGE RANGE

Differential4
Common-Mode Voltage
Over Max Operating Range'
Common-Mode Rejection Ratio

VCM= ±lOV

76

Tmin to Tmu
VCM= ± llV

76176176

TJlliDtoT_

0020
+ 14.5, - 11.5

0020
+ 14.5, -11.5
-Vs+4V

+Vs-1V

80
80
76
74

88
84
84

70
10170170

80

INPUT VOLTAGE NOISE
VoltageO.IHzto 10Hz

86
86
76
74

88
84
84

80

94
90
90

V
dB
dB
dB
dB

84

18
16
0.01

0.01

0.01

pAIYHZ

400

V/mV

22

f~IOkHz

V
+Vs-1V

2
45
22
18
16

2
45

f~

f~lkHz

-Vs+4V

2
45
22
18
16

f~IOHz

100Hz

0020

+ 14.5, -11.5
+Vs-1V

-Vs+4V

4.0

fJ.Vp-p
itV/YHZ
nV/YHZ
nVIYHZ
nV/YHZ

INPUT CURRENT NOISE
f~lkHz

OPEN LOOP GAIN"

Vo= ±lOV,RL~2kU
Vo= ± lOV,RL~2kO,
TmintoTmu

OUTPUT CHARACTERISTICS
Voltage@RL ",2k!l
Voltage@RL "'2k!l,
T min to Tmax
Short-Circuit Current
POWER SUPPLY
Rated Performance
OperatingRange
Quiescent Current

400

ISO

100

10011001100

400

200

100

100

VlmV

+13, -12.5

+ 13.9, -13.3

+13, -12.5 + 13.9, -13.3

+13, -12.5 + 13.9,-13.3

V

±12l±12l:t12

+ 13.8,-13.1
25

±Il

±12

V
mA

±IS

±IS
±4.5

TEMPERATURE RANGE
Operating, Rated Perfonnance
Conuuercial(O to + 1O"C)
Induattial ( - 4O"C to + 85"C)
Military ( -55"Cto + 125"C)
PACKAGEOPTlONS'
Plaatic(N-8)
SOIC(R-8)
CCrdip (Q-8)
TO-99 (H-08A)
Tape aod Reel
J, KaodSChipsAvailable
TRANSISTOR COUNT

2-6 OPERA TIONAL AMPLIFIERS

2.5

±18
3.4

AD71lJ
AD7llA
AD711S
AD711JN
AD711JR
AD71IAQ, AD711SQ
AD71IAH, AD71lSH
AD711JR-REEL
30

+ 13.8, - 13.1
25

±4.5
2.5

0015
±IB
3.0

AD711K
AD711B
AD71lT
AD711KN
AD711KR
AD71IBQ,AD71ITQ
AD71IBH,AD71lTH
AD7IIKR-REEL
30

+ 13.8, -13.1
25

±4.5
2.5

±IB
1.B

V
V
mA

AD71IC

AD711CQ
AD711CH

30

REV. A

AD711
NOTES
'Input offset voltage specifications are gUaranteed after 5 minutes of operation at TA = + 25°C.
2Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at T A = + 25°C.
For higher temperature, the current doubles every lOoC.
'Refer to Figure 29.
'Defmed as voltage between inputs, such that neither exceeds ± IOV from ground.
STypically exceeding - 14.1 V negative common-mode voltage on either input results in an output phase reversal.
'Open-Loop Gain is specified with Vos both nulled and unnulled.
'H = Metal Can; N = Plastic DIP; Q = Cerdip; R = SOIC. For outline information see Package Information section.
Specifications subject to change without notice.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at fmal
electrical test. Results from those tests are used to calculate outgoing quality levels.

ABSOLUTE MAXIMUM RATINGS·
Supply Voltage . . . . . .
Internal Power Dissipation2 . .
Input Voltage 3 • • • • • • • • •
Output Short Circuit Duration
Differential Input Voltage . . .
Storage Temperature Range Q, H
Storage Temperature Range N
Operating Temperature Range

±18V
500mW
. ±18V
Indefinite
+Vsand -Vs
- 65°C to + 150°C
- 65°C to + 125°C

NOTES
I Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
lThermal Characteristics
8-PinPlasticPackage:6jc = 33°CIW,6jA = lOO°CIW
8-PinCerdipPackage:6jc = 22°CIW,6jA'= 1l0"CIW
8-PinMetaICanPackage:6jc = 6S CIW,6jA = ISO"CIW
3Por supply voltages less than ± 18V, the absolute maximum input voltage is
equal to the supply voltage.

AD711J/K
0 to + 70°C
AD71lA/B/C . . . . . . . .
- 40°C to + 85°C
AD71lS/T . . . . . . . . .
- 55°C to + 125°C
Lead Temperature Range (Soldering 60 seconds) . . .. 300°C

0

METALLIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.

OFFSET
NULL
1

-IN 2

+IN 3

0.067
(1.7018)

6 OUT

5 OFFSET
NULL

L
REV. A

4

vO.065
(1.651)

v-

CONNECTED TO CASE
PIN 8 = NO CONNECT

OPERA TIONAL AMPLIFIERS 2-7

•

AD711-Typical Characteristics
20~----~-------r------~------'

20

~

t, 15~-----1-------+------1.~L-~

/

/

/

V
o

/

o

I
w

~

~

~
~ .~----~~~-+------+-----~
o

RL""ZkU
2,"C

10

~15V ~"'PPllES
10~-----1-------+~~--~----~

15

I

I
o

0~0------~----~'~0------~15~----~20

20

100

Figure 3. Output Voltage' Swing
VS. Load Resistance

•

2.7

100

r- Ave!..

•

1

2.

,

I"
-

I

f

2.25

.

f

2.

•

10

15

20

10- 1
-60

-40

20

0

Figure 4. Quiescent Current VS.
Supply Voltage

60

26

Va= ±15Y

20

2."C

'" r\...

2-8 OPERA TIONAL AMPLIFIERS

:; 4.5

,

,-\

%

~

2

::l

~ I"-

10
0

20

40

60

80

"1::

.....

"

~ r--...

~

""

-60 -40 -20

4.0

z

100

120 140

AMBIENT TEMPERATURE - "C

VS.

10M

5.0

I:i

12

10

1M

lOOk

Figure 6. Output Impedance
VS. Frequency

VS.

=!!

14

-.

10k

1k

FREQUENCY _ Hz

I

-OUTPUT'CURREN~

I.

r-~

140'

I

+" OUTPUT CURRENT

18

LI~••••"A

120

i

"'"

.1

22

COMMON MODE VOLTAGE - Volb

100

..

r- .........

24

Figure 7. Input Bias Current
Common Mode Voltage

80

0.01

0q

Figure 5. Input Bias Current
Temperature.

100

MAX J GRADE

20,. 40

TEMPERATURE -

SUPPLY VOLTAGE - :!:Volts

-10

II'"
0.1

f

1.7

o

+1

10

I•
"

10k

1k

LOAD RESISTANCE - Ohms

Figure 2. Output Voltage Swing
vs. Supply Voltage

Figure 1. Input Voltage Swing
VS. Supply Voltage

10

~Volts

SUPPLY VOLTAGE -

SUPPLY VOLTAGE - :!:Volts

/

Figure 8. Short Circuit Current
Limit VS. Temperature

r--. r---..

........

Z
:> 3.5

3.0
-60 -40 -20

20

40

60

80

~

100 120

140

TEMPERATURE _ "C

Figure 9. Unity Gain Bandwidth
VS. Temperature

REV. A

AD711
+100

--~

+80

,-

t

--- ---PHASE

""

,

CJ +40

~

\

11 •

-20

lOOk

10k

Rl ",2kl)
25"C

\

+0

1k

• 60

\

I
I
I

"r\.

= 2kU
C = 100pF
R~

100

120

\

~ +20

10

180'

\

~N

~

110

12.

140'

110

-+20'

""
1M

"

1O.

~

9.

20'

10M

IIII

80

VCM ",1V pop

~

~,

60

1\

~

40

~

1\

°

10

100

1k

15

10

10

20

10k

lOOk

20

~

R(=2kH
25'C
Vs~

2kU
Ct. = l00pF

-90

",

-120

4
2

... -~

~

~

°

lOOk

1M

"

-6

o

~,

0.'

0.7

0.6

"""" ~"
0.8

,.

20

.

10

V

~

~

1

V

15

w

r--r-.

lOOk

1.0

0.'

Figure 15. Output Swing and
Error vs. Settling Time

,

Figure 16. Total Harmonic
Distortion vs. Frequency

r\.

SETTLING TIME - j.1S

;;

10k

\

-10

10M

0.01%

\ 1\ \

-8

t---.r-.

"
/'

FREQUENCY _ Hz

0.01%

0.1%

\

>- -4

::>

I'::>

1

REV. A

1%

2.

~

1k

ERROR

"~ -2

10

0.1"10

0

Figure 14. Large Signal
Frequency Response

-130
100

/1 /
1"10

:l

::!:15V

15

I

-100

j:
-110

.,

1;

1000

Rl

.......::: V"" ~

o

\

1M

lOOk

1// /
L ilL

INPUT FREQUENCY - Hz

-70

10k

Figure 12. Power Supply
Rejection vs. Frequency

>

..........

1M

1k

SUPPLY MODULATION FREQUENCY - Hz

:\

Figure 13. Common Mode
Rejection vs. Frequency

3VRMS

100

10

FREQUENCY - Hz

-80

IIII I

o

o

....

20

.....

Vs = ± 15V SUPPLIES
WITH 1V pop SINE
WAVE 25"C

20

~

Vs""::!:1SV

:l

Q

40

2.

25"

.",

/

....
,SUPPLY

30

..

....
....

60

Figure ". Open-Loop Gain vs.
Supply Voltage

100



Max

Uaita

0.1

0.30
0.60

mV
mV

3
110

5

,.vrc

dB
dB
JA,V/month

15

25

75

20

75

20

SO

pA

1.7/4.8/77

0.5/1.3/20

1.7/4.8/77

1.3

10

100
25

5

100
25

5

l.2
75
10

nA
pA
pA

0.3/0.7/11

0.611.6126

0.1I0.l/5

0.611.6126

0.3

0.7

nA

O.l
-0.6
5
10

mV
mV

110.710.7
211.511.5
10
25

20120120
25
120

120

90

16

110.710.7
Vl.Sll.5
10

0.611.6126

lllll

Total Harmonic Distortion
f= lkHz,RL ;:=:2k!l, Vo=3Vrms

Mia

15

4/2/2

l.O

AD71ZC

Max

4
200
20
I

120

90

1.4

18
1.2

4
200
20
I

90

l.4
18
1.2

4
200
20
I

,.vrc

pA
dB
dB
MHz
kHz

Vi ....
1.2

....

O.oool

O.oool

0.0003

%

lXI0 12 115.5
lxlO 12 115.5

lx 10"115.5
3x 10"115.5

lxlO 12 115.5
lxlO 12 115.5

fillpF
fillpF

±20

V

INPUT IMPEDANCE
Differential

Common Mode
INPUT VOLTAGE RANGE
Oifferential6
CommOn-Mode Voltllg<
Over Max Operating Range'
Common-Mode Rejection Rstio
VCM.= ::tIOV
Tmin to Tmax
VCM = ::tHV
TmintoT_

±20

-Vs+4V
76

88

76fl6l76

84
84
80

70
70170170

±20

+ 14.,5, 11.5 +Vs -2V

-Vs+4V
80
80
76
74

+ 14.5, -11:5 +Vs -2V

-Vs+4V

88
84

86
86

84

76
74

80

+14.5, -11.5 +Vs -2V
94

V
dB
dB
dB
dB

90
90

84

INPUT VOLTAGE NOISE
VoltageO. 1Hz to 10Hz
f=IOHz
f=IOOHz
f=lkHz
f= 10kHz

2
45
22
-18
16

2
45
22
18
16

2
45
22
18
16

INPUT CURRENT NOISE
f= 1kHz

0.01

0.01

0.01

pAlYHz

400

V/mV
VlmV

OPEN LOOP GAIN
Vo= ±lOV,RL~2kO
TmintoTmu,RL~2kfl

OUTPUT CHARACTERISTICS
Voltage@RL "2kn
T min to T_
SbortCircuit Current
POWER SUPPLY
RstedPerlormaru:e
Operating Range
Quiescent Current,
Both Amplif....

ISO
10011001100

400

200
100

+13, -12.5
+ 13.9, - 13.3
±12, ± 12,:1::12 + 13.8,- 13.1
25

TEMPERATURE RANGE
Operating, Rated Performance
Commercial (0 to + 7O"C)
Industrial ( - 4O"C to + 85°C)
Military ( - SSOCto + 125"C)
PACKAGE OPTIONS'
SOIC(R-8)
Plastic (N-8)
Cerdip (Q-8)
TO-99 (H-08A)
Tape and Reel
A, J and S Grsde Chips Available

2-18 OPERATIONAL AMPLIFIERS

6.8

%4.5

nV/VHz

+13, -12.S + 13.9, -13.3
±12
+ 13.8,-13.1
25

5

V
V
mA

±15
%18
6.0

AD712J
AD712A
AD712S

AD712K
AD712B
AD712T

AD712JR
AD7l2JN
AD712AQ, AD712SQ
AD712AH, AD712SH
AD712JR

AD712KN
AD712BQ,AD712TQ
AD712BH,AD712TH

%4.5
5

"Vl"P
nV/YHz

nV/YHz
nV/YHz

100

± 15
%18

5

200

+13, -U.S + 13.9, - 13.3
±12
+ 13.8,-13.1
25

±15
%4.5

400

4

%18

V
V

5.6

mA

AD712C

AD712CQ
AD712CH

REV. A

AD712
NOTES
Ilnput Offset Voltage specifications are guaranteed after 5 minutes of operation at TA = + 25"C.
lBias Current specifkations are guaranteed maximum at either input after 5 minutes of operation at T A == + 25"<:. For hiJber temperature, the current doubles every 1O"C.
JMatching is defmed as the difference between paramerers of the two amplifiers.
4Refer to FiJure 21.
51lefer to FiJure 29.
'Defined as volt. between inputs, such that neither exceeds ± lOY from ground.
7Typicallyexceeding -14.1V negative common-mode voltage on either input results in an outpUt phase reversal.
-Por outline information see Package Information section.
Specifications subject to change without notice.
SpeciflClllions in boldface are tested on all production units at final electrical test. Results from dtose tests are used to calculate outgoing quality levels. AU min and max spcciflCltions
are guaranteed., although only those shown in boldface are tested on all production units.

ABSOLUTE MAXIMUM RA TINGS 1
Supply Voltage . . . . . .
. ±18V
Internal Power Dissipation 2 • •
SOOmW
Input Voltage3 • • • • • • . • •
. ±18V
Output Short Circuit Duration
Indefinite
Differential Input Voltage . . .
+Vs and -Vs
Storage Temperature Range Q, H
-65°C to + 150°C
- 65°C to + 125°C
Storage Temperature Range N
Operating Temperature Range
AD712JIK
. . . 0 to + 70°C
AD712A1BIC . . . . . . .
- 40°C to + 85°C
AD712SIT . . . . . . . .
- 55°C to + 125°C
Lead Temperature Range (Soldering 60 seconds) . . .. 300°C

NOTES
IStresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
lThermal Characteristics:
8-Pin Plastic Package: 6 jA ~ 16S'CIW.
8-PinCerdipPackage:6Jc = 220C1W,8JA = 1I0°C/W.
8-PinMetalCan Package: 6jc ~6S'CIW,6jA c-ISO'C/W.
JFor supply voltages less than ± 18V, the absolute maximum input voltage is
equal to the supply voltage.

METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and Cmm).

1

'0---------- ~~~
v+

--------->..j!

r-'"'
OUTPUT

-IN

REV. A

-IN

8

+IN

5 +IN

v-

OPERATIONAL AMPLIFIERS 2-19

•

AD112 - Typical Characteristics
20

30

20

",..

.. 25

/

/

~

*!i!,
>

/

/

o

!
,

10

:>~

...~

RL =2kU
250C

~

0

SUPPLY VOLTAGE

~

Yolts

"

0

zo

10

0

(

"

I

I

100

1k

10k

Figure 3. Output Voltage Swing
VS. Load Resistance

100

10-'

1-

::>

I-"
10

LOAD RESISTANCE - Ohms

Figure 2. Output Voltage Swing
vs. Supply Voltage

t

/

II

o

10-~

"~
..~

/

SUPPlY VOLTAGE:!: Volts

Figure 1. Input Voltage Swing
vs. Supply Voltage

lSV SUPPLIES

5

20

15

:!:

10

~
~

::>

10

11

20

I..
"

~

III
i!

~

o

~

15

10

~ 10-~

~

i.

.i3

/
10-!J

1

; 10- 10

0

~~ 10-

0.1

./

11

I,.;'
10

15

10- 12
-60

zo

40 -20

0

Figure 4. Quiescent Current vs.
Supply Voltage

MAX J GRAol

75

50

i

~

g

25

60

80

100

0.01

120 140

1k

--

Figure 5. Input Bias Current vs.
Temperature

LI~

24

"E,
t:

~

Vs "" :t15V
250C

::>

~

"5
COMMON MODE VOLTAGE - Volts

Figure 7. Input Bias Current vs.
Common Mode Voltage
2-20 OPERATIONAL AMPLIFIERS

2Z
20

.~ ,.
"t:
~
0
~

.'"

,.

10M

1M

100k

Figure 6. Output Impedance vs.
Frequency

5.0

"

........

-OUTPUT

+ OUTPUT CURRENT

"!\1\

:l!

lE 4.'

,
~

.......
CURREN~'

i

"
:!

Z

r" ~

......

~ .......

4.0

.......

r--.... j'-.....

~

......

"~

....... ~

r---.

Z
::> 3.S

14

.......

12

o
-10

10k

fREQUENCY - Hz

Z6

100

Ia

40

TEMPERATURE _ "C

SUPPLY VOLTAGE ± Votts

,

20

10

10
-60 -40 -20

0

20

40

60

80

100

120 140

AMBIENT TEMPERATURE - "C

Figure 8. Short Circuit Current
Limit vs. Temperature

3.0
-60 -40 -20

20

40

80

80

100 120

140

TEMPERATURE - "C

Figure 9. Unity Gain Bandwidth
vs. Temperature

REV. A

AD712
+100

+,oo~

--~ ~- --- ----

+so

"0

125

-, ,

"

\

";' +60
Z

;;

\

""

§'"

+40

i!i

:!i+20

GAIN

+40"

\

~

Z

Rl=2kll

~ ~

\

8~
":E ~

2S"C

110

\

+20"

~ ~ 105

~

0

'\

10

100

10k

1k

lOOk

.
~

2

o

10

20

15

1111

~,
~

"

~ .0

~

10

"

20

I!:

\

20

Rl =2kU

100

1k

10k

lOOk

1M

10

RL = 2kU
C L = l00pF

-go

1I

,

,
C -100
~

i!'

V

-110

-

-130
100

r--...'~
0.5

1.0

0.9

Figure 15. Output Swing and
Error vs. Settling Time

25

20

t,

V

15

10

V

1,....00"'o

1
100k

1

10

1k
100
FREQUENCY - Hz

10k

lOOk

,,-

.,

V

S
~

10k

t::--"'

SETTLING TIME - ",5

1'1--

FREQUENCY - Hz

"

0.8

0.7

0.'

~

V"

1k

\

\ 1\ \

-8

Figure 14. Large Signal
Frequency Response

~

a>

0.01%

-10
10M

1M

,...-.

0.01%

0.,1010

\

1000

,VRMS I

0.1%

1%

INPUT FREQUENCY' - Hz

-so

-120

1%

"- ........ r-.

Figure 13. Common Mode
Rejection vs. Frequency

1M

II I
// I

'\
lOOk

100k

1// /

ERROR

FREQUENCY - Hz

-70

10k

/

25"C
Vs= :!:15V

~

15

"c

....

1k

/ . :::;;-.....

..

"'
"

~

g

o
10

100

Figure 12. Power Supply
Rejection vs. Frequency

g

5

"

IIII I

SUPPLY MODULATION FREQUENCY _ Hz

25

.0

,

~

WAVE 25"C

10

~

25..,

I"

Vs = ± 1SV SUPPLIES

WITH lV p.p SINE

Figure 11. Open Loop Gain vs.
Supply Voltage

Vs::±15V
VcM =1V p.p

"

,SUPPLY

iil

'0

....

I"

SUPPLY VOLTAGE ± Volts

100

so

"

o

Figure 10. Open Loop Gain and
Phase Margin vs. Frequency

o

'"
~

95

FREQUENCY - Hz

r-..

.0

20

10M

1M

OJ

+LJpL

I"

100

20"

-20

~

.,.--- / '

II
~

80

Z

/
V

'" 0
Z

\

"~

LOAD

+0

C

\

PHASE
2kU l00pF

,

~

+60' ~ ";' 115

\

'\

a>

m..

\

r'\.

a>

a>

-....

100
12.

V

o

V

/

100

200

300

400

500

600

700

800

900

INPUT ERROR SIGNAL - mV

(AT SUMMING JUNCTION I

Figure 16. Total Harmonic
Distortion vs. Frequency

REV. A

Figure 17. Input Noise Voltage
Spectral Density

Figure 18. Slew Rate vs. Input
Error Signal
OPERA TIONAL AMPLIFIERS 2-21

•

AD712

J,

INPUT

i2.~;--r-t~--r-~~~-4~

;

Figure 20. T.H.D. Test Circuit
'5~-L~

__~~~__~~~__L-~

-60 -40 -20

0

20

40

60

80

100

V OUT

120 140

TEMPERATURE _ "C

2OkO

Figure 19. Slew Rate vs.
Temperature

Figure 21. Crosstalk-Test Circuit

SQUARE
WAVE

-Vs

INPUT

Figure 22a. Unity Gain Follower

Figure 22b. Unity Gain Follower
Pulse Response (Large Signal)

Figure 22c. Unity Gain Follower
Pulse Response (Small Signal)

Figure 23b. Unity Gain Inverter
Pulse Response (Large Signal)

Figure 23c. Unity Gain Inverter
Pulse Response (Small Signal)

SkU

SkU

SQUARE
WAVE

INPUT
-Vs

Figure 23a. Unity Gain Inverter

2-22 OPERA TIONAL AMPLIFIERS

REV. A

AD712
OPTIMIZING SETTLING TIME
Most bipolar high-speed DIA converters have curent outputs;
therefore, for most applications, an external op amp is required
for current-to-voltage conversion. The settling time of the converter/op amp combination depends 9n the settling time of the
DAC and output amplifier. A good approximation is:
t, Total = Vet, DAC)2 + (t, AMP)2
The settling time of an op amp DAC buffer will vary with the
noise gain of the circuit, the DAC output capacitance, and with
the amount of external compensation capacitance across the
DAC output scaling resistor.
Settling time for a bipolar DAC is typically 100 to 500ns. Previously, conventional op amps have required much longer settling
times than have typical state-of-the-art DACs; therefore, the
amplifier settling time has been the major limitation to a high-speed
voltage-output D-to-A function. The introduction of the AD7111
712 family of op amps with their Il1s (to :to.01% of final value)
settling time now permits the full high-speed capabilities of
most modem DACs to be realized.

In addition to a significant improvement in settling time, the
low offset voltage, low offset voltage drift, and high open-loop
gain of the AD71l1AD712 family assures 12-bit accuracy over
the full operating temperature range.
The excellent high-speed performance of the AD712 is shown in
the oscilloscope photos of Figure 25. Measurements were taken
using a low input capacitance amplifier connected directly to the
summing junction of the AD7l2 - both photos show the worst
case situation: a fuil-scale input transition. The DAC's 4kU
[lOknllskU=4.4kH) output impedance together with a 10k!!
feedback resistor produce an op amp noise gain of 3.25. The
current output from the DAC produces a IOV step at the op
amp output (0 to - IOV Figure 25a, - lOY to OV Figure 25b.)
Therefore, with an ideal op amp, settling to :t l/2LSB (:to.01%)
requires that 37511 V or less appears at the summing junctioq.
This means that the error between the input and output (that
voltage which appears at the AD7l2 summing junction) must be
less than 37511V. As shown in Figure 25, the total settling time
for the AD7121AD565 combination is 1.2 microseconds.

Figure 24. ± 10V Voltage Output Bipolar DAC

AD712

SUMMING
JUNCTION

AD712
SUMMING
JUNCnON

AD712

AD712

OUTPUT

OUTPUT

a. (Full-Scale Negative Transition)

b. (Full-Scale Positive Transition)

Figure 25. Settling Characteristics for AD712 with AD565A

REV. A

OPERA TIONAL AMPLIFIERS 2-23

AD712
OP AMP SETTLING TIME - A MATHEMATICAL
MODEL
The design of the AD712 gives careful attention to optimizing
individual drcuit components; in addition, a careful tradeoff
was made: the gain bandwidth product (4MHz) and slew rate
(20VI ",s) were chosen to be high enough to provide very fast
settling time but not too high to cause a significant reduction in
phase margin (and therefore stability). Thus designed, the AD712
settles to ±O.OI%, with a IOV output step, in under I'",s, while
retaining the ability to drive a 2S0pF load capacitance when
operating as a unity gain follower.
If an op amp is modeled as an ideal integrator with a unity gain
crossover frequency of Old2-rr, Equation 1 will accurately describe
the small signal behavior of the circuit of Figure 26a, consisting
of an op amp connected as an I-to-V converter at the output of
a bipolar or CMOS DAC. This equation would completely
describe the output of the system if not for the op amp's finite
slew rate and other nonlinear effects.

Equation 1.

v,.

Figure 26b. Simplified Model of the AD712 Used as an
Inverter

Vo
lIN = R(Cf +
(1)0

-R

Cx) S2 + (GN + RCf) s + I
Wo

where ~; = op amp's unity gain frequency
GN

When Ro and 10 are replaced with their Thevenin VIN and RIN
equivalents, the general purpose inverting amplifier of Figure
26b is created. Note that when using this general model, capacitance Cx is EITHER the input capacitance of the op amp if a
simple inverting op amp is being simulated OR it is the combined
capacitance of the DAC output and the op amp input if the
DAC buffer is being modeled.

= "noise" gain of drcuit (I + ~J

This equation may then be solved for

In either case, the capacitance Cx causes the system to go from
a one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp
output. Since the value of Cx can be estimated with reasonable
accuracy, Equation 2 can be used to choose a small capacitor,
Cp , to cancel the input pole and optimize amplifier response.
Figure 27 is a graphical solution of Equation 2 for the AD7l2
with R = 4kO.

Cr:

Equation 2.

Cr

=

2 - GN + 2YRCX Olo + (1- GN)
ROlo
ROlo

In these equations, capacitor Cx is the total capacitance appearing
at the inverting terminal of the op amp. When modeling a DAC
buffer application, the Norton equivalent circuit of Figure 26a
can be used directly; capacitance Cx is the total capacitance of
the output of the DAC plus the input capacitance of the op amp
(since the two are in parallel).

x

"

.
Figure 27. Value of Capacitor CF

VB.

Value of Cx

The photos of FigUres 28aand 28b show the dynamic response
of the AD712 in the settling test circuit of Figure 29.

Figure 26a. Simplified Model of the AD712 Used as a
Current-Out DAC Buffer

2-24 OPERA TIONAL AMPLIFIERS

The input of the settling time fixture is driven by a flat-top
pulse generator. The error sign'ai output from the false summing
node of Al is clamped, amplified byA2 and then clamped
again. The error signal is thus clamped twice: once to prevent
overloading amplifier A2 and then a second time to avoid overloading the oscilloscope preamp. The Tektronix oscilloscope
preamp type 7A26 was carefully chosen because it does not
overload with these input levels. Amplifier A2 needs to be a
very high-speed, FET-input op amp; it provides a gain of 10,
amplifying the error signal output of AI.

REV. A

AD712
~-f

r-l ; : r~+
I

I

I
-

Figure 2&. Settling Characteristics 0 to + 10V Step
Upper Trace: Output of AD712 Under Test (5V!Div)
Lower Trace: Amplified Error Voltage (0.01%1Div)

:

-

-

500nS

Figure 28b. Settling Characteristics 0 to -10V Step
Upper Trace: Output of AD712 Under Test (5V!Div)
Lower Trace: Amplified Error Voltage (0.01%1Div)

Figure 29. Settling Time Test Circuit

GUARDING
The low input bias current (I SpA) and low noise characteristics
of the AD712 BiFET op amp make it suitable for electrometer
applications such as photo diode preamplifiers and picoampere
current-to-voltage converters. The use of a guarding technique
such as that shown in Figure 30, in printed circuit board layout
and construction is critical to minimize leakage currents. The
guard ring is connected to a low impedance potential at the
same level as the inputs. High impedance signal lines should not
be extended for any unnecessary length on the printed circuit
board.

TO-99 (8) Package

Plastic Mini-DIP (N) Package
and
Cerdip (Q) Package

DIA CONVERTER APPLICATIONS
The AD712 is an excellent output amplifier for CMOS DACs.
It can be used to perform both 2 quadrant and 4 quadrant operation.
The output impedance of a DAC using an inverted R-2R ladder
approaches R for codes containing many Is, 3R for codes containing
a single I, and for codes containing all zero, the output impedance
is infinite.

For example, the output resistance of the AD7S4S will modulate
between Ilk!! and 33k!!. Therefore, with the DAC's internal
feedback resistance of Ilk!!, the noise gain will vary from 2 to
4/3. This changing noise gain modulates the effect of the input
offset voltage of the amplifier, resulting in nonlinear DACamplifi.:r performance.
The AD712K with guaranteed 700fLV offset voltage minimizes
this effect to achieve 12-bit performance.
Figures 31 and 32 show the AD712 and AD7S4S (l2-bit CMOS
DAC) configured for unipolar binary (2-quadrant multiplication)
or bipolar (4-quadrant multiplication) operation. Capacitor CI
provides phase compensation to reduce overshoot and ringing.

Figure 30. Board Layout for Guarding Inputs

REV. A

OPERATIONAL AMPLIFIERS 2-25

II

AD712
Figures 33a and 33b show the settling time characteristics of the
AD712 when um:d asa DAC outp~~"buffer for the AD7545.

lili iii

-

•

11"

!l-"

I

II I
-I

--

I= ·~

I-

H·

+-+

~I~

I-

•

s

:JRt!~

--

..-

r- 1111-

,1

,

i
I. illl ----y-- ;;; III
;~ 1

II

a. Full-Scale Positive
Transition

I-

·m·

II ::::!l s

1

i

5

II:~

b.. Full-Scale Negative
Transition .

Figure 33. Settling Characteristics for AD712 with AD7545
NOISE CHARACTERISTICS
The random nature of noise, particularly in the IIf region, makes
it difficult to specify in practical terms. At the same time, designers
of precision instrumentation require certain guaranteed maximum
noise levels to realize the full accuracy of their equipment.

Figure 31. Unipolar Binary Operation

The AD712C grade is specified at a maximum level of 4.01LV
p-p, in a 0.1 to 10Hz bandwidth. Each AD712C receives a
100% noise test for two 10-second intervals; devices with any
excursion in excess of 4.01LV are rejected. The screened lot is
then submitted to Quality Control for verification on an AQL
basis.
All other grades of the AD712 are sample-tested on an AQL
basis to a limit of 61LV P-P, 0.1 to 10Hz.

Figure 32. Bipolar Operation
Rl and R2 Calibrate the zero offset and gain error of the DAC.
Specific values for these resistors depend upon the grade of
AD7545 and are shown below.

DRIVING THE ANALOG INPUT OF AN AID
CONVERTER
An op amp driving the analog input of an AID converter, such
as that shown in Figure 34, must be capable of maintaining a
constant output voltage under dynamically changing load conditions. In successive-approximation converters, the input current
is compared to a series of switched trial currents. The comparison
point is diode clamped but may deviate several hundred millivolts
resulting in high frequency modulation of AID input current.
The output impedance of a feedback amplifier is made artificially
low by the loop gain. At high frequencies, where the loop gain
is low, the amplifier output impedance can approach its open
loop value. Most IC amplifiers exhibit a minimum open loop
output impedance of 250 due to current limiting resistors. A

TRIM
RESISTOR JN/AQISD

KNIBQfI1) LN/CQIUD GUi'/GCQIGUD

R1

5000

2000

R2

1500

680

1000
330

200
6.80

Table I. Recommended Trim Resistor Values vs. Grades
of the AD7545 for Voo = + 5V



,

I"- ;--...

4.0

i'-.

...... ........

,.S

r--.. r--....

12

10
-60 -40 -20

0

20

40

60

80

100

120 140

AMBIENT TEMPERATURE - "C

Figure 8. Shon Circuit Current Limit
vs. Temperature

3 .•
-60 -40 -20

20

40

60

80

100 120

140

TEMPERATURE _ "C

Figure 9. Gain Bandwidth Product vs.
Temperature

REV. A

AD713
+100"

--~ ~+BO

--- ----

~+60
Z

--4

"'-....

1M

lOOk

1M

........::: ~,....-

;:;

Rl =2kU

"

lOOk

LL L

~

0

10k

SUPPLY MODULATION fREQUENCY _ Hz

r\

~15V

r-.

10

1k

25

"

o

100

10

25"C

":Eu 40

•

l[ ]

10

Figure 1,. Open Loop Gain vs. Supply Figure 12. Power Supply Rejection vs.
Voltage
Frequency

VcM =lV pop

,

20

20

30

1111

"

"SUPP1.V

SUPPLY VOLTAGE!: VOLTS

100

"

Vs=:t 15V SUPPUES
WITH 1V p-p SINE
WAVE 25"C

o

o

.lulL

iii ..

,.0

Figure 10. Open Loop Gain and Phase
Margin vs. Frequencv

1.0

0.9

SETTLING TIME - 115

Figure 14. Large Signal Frequency
Response

Figure 15. Output Swing and Error vs.
Settling Time

,

1000

II"

-so

..,

Ii .

,--- .."

1\

"

, BO

l;?
« 9

I

1M

lOOk

10k

~

+40" 3!l:

\

"i'\.

PHASE - - - -

+0

\

r--

120

+60" ~ ~"5

\

~

+40

~

\

'\..

§"

11

100
+80"

"'

.

11.

12.

-"

3VRMS
RL = 2kU
CL = l00pF

-9.

'-

II

0 - 100

i!:

/

-110

-120

-130

--

"

~V

5
1

,/

r--""

V

V'

V-

0

~

~..-'

V

'..,.IV

1

'.0

10k

lOOk

FREQUENCY _ Hz

Figure 16. Total Harmonic Distortion
vs. Frequency

REV. A

~

0

V

1

I.

100

"

I ••

lOOk

FREQUENCY - Hz

Figure 17. Input Noise Voltage Spectral
Density

.

100

200

300

400

500

600

100

800

900

INPUT ERROR SIGNAl- mV
lAY SUMMING JUNCTIONI

Figure 18. Slew Rate vs. Input Error
Signal

OPERATIONAL AMPLIFIERS 2-33

Applying the AD713
-70

II

-80

r,.,

I g; •

9kll

+ v..

I1: .'f1

COM
ALL 4 AMPLIFIERS
ARE CONNECTED
AS SHOWN

-v.

a

1!

1'f1
IO"f1 I'f1
o

F

F

:1':l!3

F

F

V
a

AD7'3
PIN "

."

-90

~

1-100

~

-

I~:

[i] 0~
~

I~: 0 0*

3 1";1

iu

~
-120

"THE SIGNAL INPUT ('kHz SINEWAVE. 2V p·pllS APPLIED
TO ONE AMPLIFIER AT A·TIME. THE OUTPUTS OF THE OTHER
THREE AMPLIFIERS ARE THEN MEASURED FOR CROSSTALK.

."

-140

Figure 19. Crosstalk Test Circuit

Figure 21a. Unity Gain Follower

1 T03

tI

;: 0~

-130

10

, T02

V~~~

~

1['

~ -110

1 T04

~~

100

~

~

1k
10k
FREQUENCY - Hz

100k

Figure 20. Crosstalk vs. Frequency

Figure 21b. Unity Gain Follower
Large. Signal Pulse Response

Figure 21c. Unity Gain Follower
Small Signal Pulse Response

1.5pF

2kn

ru-

SQUARE
WAVE
INPUT

Figure 22a. Unity Gain Inverter

2-34 OPERATIONAL AMPLIFIERS

Figure 22b. Unity Gain Inverter
Large Signal Pulse Response

Figure 22c. Unity Gain Inverter
Small Signal Pulse Response

REV. A

AD713
MEASURING AD713 SETTLING TIME
The photos of Figures 24 and 2S show the dynamic response of
the AD713 while operating in the settling time test circuit of
Figure 23. The input of the settling time fixture is driven by a
flat-top pulse generator. The error signal output from the false
summing node of AI, the AD713 under test, is clamped, amplified by op amp A2 and then clamped again.
TO TEKTRONIX
1A26
OSCILLOSCOPE
PREAMP
INPUT SEcnON
{VIA LESS THAN
1FT 50.11
COAXIAL CABLEI

r------,

-

I

I

:

~ ,E0PF:

:'Mn~T

:

I

,

L ______ .1

The error signal is thus clamped twice: once to prevent overloading amplifier A2 and then a second time to avoid overloading the oscilloscope preamp. A Tektronix oscilloscope preamp
type 7A26 was carefully chosen because it recovers from the
approximately 0.4 volt overload quickly enough to allow accurate measurement of the AD713's l,...s settling time. Amplifier
A2 is a very high speed FET input op amp; it provides a voltage
gain of 10, amplifying the error signal output of the AD713
under test (providing an overall gain of S).

E~
~
, •....
~

:II2x
HP2835

~

1=,•
ri
~··

II,.

I~~··

II

I
. 11

Il,
-I II

----

-

1=

.. . . : . . .

.
~v

I

I~ nS

NOTE
USE CIRCUIT BOARD
WITH GROUND PLANE

Figure 25. Settling Characteristics to -10V Step. Upper
Trace: Output of AD713 Under Test (5Vldiv). Lower Trace:
Amplified Error Voltage (O.Ol%ldiv)

4.99kU
10kU
·USE VERY
SHORT CABLE

OR TERMINATION
RESISTOR

DATA
DYNAMICS

5109
OR
EQUIVALENT

I

_______ .1

Figure 23. Settling Time Test Circuit

Figure 24. Settling Characteristics 0 to + 10V Step. Upper
Trace: Output of AD713 Under Test (5V/div). Lower Trace:
Amplified Error Voltage (O.Ol%1div)

REV. A

POWER SUPPLY BYPASSING
The power supply connections to the AD713 must maintain a
low impedance to ground over a bandwidth of 4MHz or more.
This is especially important when driving a significant resistive
or capacitive load, since all current delivered to the load comes
from the power supplies. Multiple high quality bypass capacitors
are recommended for each power supply line in any critical
application. A O.I,...F ceramic and a I,...F electrolytic capacitor as
shown in Figure 26 placed as close as possible to the amplifier
(with short lead lengths to power supply common) will assure
adequate high frequency bypassing in most applications. A
minimum bypass capacitance of O.I,...F should be used for any
application.

Figure 26. Recommended Power Supply Bypassing

OPERA TIONAL AMPLIFIERS 2-35

•

AD713
A 10GB SPEEl) INSTRUMENTATION AMPLIFIER
CIRCUIT

A 10GB SPEED FOUR OP AMP CASCADED AMPLIFIER
CIRCUIT

The instrumentation amplifier circuit shown in Figure 27 can
provide a range of gains from unity up to 1000 and higher using
only a single AD713. The circuit bandwidth is 1.2MHz at a gain
of 1 and 250kHz at a gain of 10; .settling time for the entire circuit is less than 5,...s to within 0.01 % for a 10 volt step,
(G = 10). Other uses for amplifier A4 include an active data
guard and an active sense input.

Figure 29 shows how the four amplifiers of the AD713may be
connected in cascade to form a high gain, high bandwidth .
amplifier. This gain of 100 amplifier has a -3dB bandwidth
greater than 600kHz.

o:' +

CIRCUIT GAIN = 2OA

1

·1.6pF ~ 20pF

.

·ITRIM .FOR BElT SEJJUNG TIMEI

SENSE

100kn

TO BUFFERED
VOLTAGE REFERENCE
OR
REMOTE GROUND
SENSE

COM
.....

V

., :1~7~~

-Vs

Figure

27.

FOUR OP·AMP CASCADED AMPliFIER
GAIN'" 100

+Vs:

BANDWIDTH ( - 3dB) = 632kHz

I

I
OPTIONAL Vos I
ADJUSTMENT ...JI
IL ______

Figure 29. A High Speed Four Op Amp Cascaded
Amplifier Circuit
TO SPECTRUM ANALYZER ~

·VOlTRONles 5P20 TRIMMER CAPACITOR
OR EQUIVALENT
··RATIO MATCHED 1% METAL FILM RESISTORS

ERROR SIGNAL
QUTFUT

(ERROR"'1

A High Speed Instrumentation Amplifier Circuit

'kU

. NULL
ADJUST

,aon

10kn

10kU

Table I provides a performance summary for this circuit. The
photo of Figure 28 shows the pulse response of this circuit for a
gain of 10.
'kU

Gain
I

2
10

RG

Bandwidth

NC
20k!l
4.04k!l

l.2MHz
1.0MHz
0.25MHz

T Settle (0.01%)

.Q

l00pF

-V.

Table I. Performance Summary for the High Speed
Instrumentation Amplifier Circuit

Figure 28. The Pulse Response of the High Speed
Instrumentation Amplifier. Gain = 10
2-36 OPERATIONAL AMPLIFIERS

Figure 30. THO Test Circuit
HIGH SPEED OP AMP APPLICATIONS AND
TECHNIQUES
DAC Buffers (I~to-V Converters)
The wide input dynamic range of JFET amplifiers makes them
ideal for use in both waveform reconstruction and digital-audioDAC applications. The AD713, in conjunction with the AD1860
DAC, can achieve 0.0016% THD (here at a 4fs or a 176.4kHz
update rate) without requiring the use of a deglitcher. Just such
a circuit is shown in Figure 31. The 470pF feedback capacitor
used with IC2a, along with op amp IC2b and its associated components, together form a 3·pole low-pass filter. Each or all of
these: poles can be tailored for the desired attenuation and phase
characteristics required for a particular application. In this application, one half of an AD713 serves each channel in a twochannel stereo system.

REV. A

AD713
-v.
MSBTRIM
470kU

DIGITAL
,.t;GND

'OOkU

200kU

-V.

+V.

+VCC

•

~

lOUT

-V.
CLOCK
LATCH
ENABLE
DATA
INPUT

+ Vee

3kn

CONTROL
LOGIC

:t
I,,,F

COM

1=,,,F

-VEE

:1

•

ANALOG
POWER
SUPPLY

-SV

I,,,F

th


a!.

,

.,"~

II:

Z

!:;

0

....
::J

....
::J

>~

0

>

~

i!;

S

::J

0

3;

0

0

10

20

5

0

Figure 1. Input Common-Mode
Range vs. Supply Voltage

------

-

\

1,,\

----

20

o 1:=
10

iiPPT

~~

10k

100
lk
LOAD RESISTANCE - U

Figure 3. Output Voltage Swing vs.
Load Resistance

o

10

15

20

-2
-60 -40 -20

14

E

T~ ~

I

10

/.

~ I'

~

6
-60 -40 -20

?/

~

~

~v

40

C

~35

ffi

60

80

40

60

80

100

120 140

lOOk

"525

100 120 140

"e

Figure 7. Quiescent Current vs.
Temperature

2-48 OPERA TlONAL AMPLIFIERS

1M
FREQUENCY - Hz

100M

10M

Figure 6. Closed-Loop Output
Impedance vs. Frequency,
Gain = +1

52

I I
POSITIVE
CURRENT

30

~

::J

~

40

I-

20

Ir ~

i::l

~

20

-

Figure 5. Input Bias Current vs.
Temperature

....

Vs =±5V

TEMPERATURE -

'--. r-

TEMPERATURE _ °C

Figure 4. Quiescent Current vs.
Supply Voltage

C 12

/

Vs= ±sv

'"""

SUPPLY VOLTAGE ± Volts

8

15

+5VOLT, _

-5

---

~~

10

Figure 2. Output Voltage Swing vs.
Supply Voltage

12

iB

~

SUPPLY VOLTAGE ± Volts

SUPPL Y VOLTAGE ± Yolts

8

j

10

o •
0

1S

~i5Vo~T

SUPPLIES

V

w 15

~ 10

10

/

20

11
~

w

0
:IE
:IE
0

..

~I

~ 15

l!:

il

n

~ 2.

J!!
15

11c
~

30

20

20

V

/

r- ~ ~LIMIT

" ~~

NEGATiVe
CURRENT
LIMIT

~

20

"-60 -40

-20

0

20

40

60

80

AMBIENT TEMPERATURE _

~,
f---

51

150
;a

r--

Z

~

~

"-

100 120 140

"e

Figure 8. Short-Circuit Current Limit
vs. Temperature

•
•

60

40 - 20

20 40
60
TEMPERATURE _ °C

80

100

120 140

Figure 9. Gain Bandwidth vs.
Temperature

REV. 0

100

..

'-

,

-,

+80'

~ .l.vsuPPLES
~
~

+00'

~

\
\

~
~

i

+40"

\

\

\

+2r

~

~

!=

"

10M

10k
lOOk
1M
FREQUENCY - Hz

,,

VS=+l~~

ID

';'70
~

"~6S

,~

~
w

~ 60

if

~

V

so

100M

80I--->"o--1'<:--t---t---+---i

~

Vs =±5V

~60~--+-~~~--t---+--~
z

~~ 4 0 1 - - - + - - - t - " " " c - " " , , - - - + - - - i

!

~201---+---t---+--->"~~.--i

55

I
10

100

10k

lk

FREQUENCY - Hz

LOAD RESISTANCE - U

Figure 10. Open-Loop Gain and
Phase Margin vs. Frequency

10

~

II

75

~

-20
100

100 r-----r---,----r----r---,

\

lkULOAD

;!: 5V SUPPLIES" \
5OOULOAD

.

+lDO"

-

AD827

Figure 12. Power Supply Rejection
Ratio vs. Frequency

Figure 11. Open-Loop Gain vs.
Load Resistance

0r---~

10

30

r-- r----..

5

0
N=·
,5
V
VCM
:: :2:1V p-p

.

'\

>

1\

0

/

g
RL =lkU

o
::!

2

IE

0

/

o

"'"

0

20

5

t'...

"-

0

5

0
10'

"

lOOk
1M
FREQUENCY _ Hz

10M

0
100M

1%

0.1%

1%

0.1%

.........,

'\..

'\

-8

~

-10
100M

I

\ \

5- •

5

0-6

o

20

40

"\..

"-

"--

60
80
100
SETTUNG TIME - ns

120

140

160

Figure 15. Output Swing and Error
vs. Settling Time

Figure 14. Large Signal Frequency
Response

I

3V~S

I:!!

RL ""lldl

~

~ -100

i

./"

0

~

V~

i

i"II il
HAR

c

:z: -120

-130
100

111.

II

10k

100.

FREQUENCY - Hz

Figure 16. Harmonic Distortion vs.
Frequency

REV. 0

1\

40

350

\
\ '-....

~

2NDNARMONte

i§

1-"

'"

V

50

-so
-90

i-

/

V

ERROR

2

INPUT FREQUENCY _ Hz

-70

,

10M

1M

Figure 13. Common-Mode
Rejection Ratio vs. Frequency

,

1\

/

/

30

20

i

~I--r-I--r-t-~~r--+-t-~~

~

i
I

250

~ ~~~-~~-t-.+~~=+-+---+--j

10

lSO

o

10

100

f-+--I-+-f-+-+---+-J...-"J-·--j

1k

10k
lOOk
FREQUENCY - Hz

1M

Figure 17. Input Voltage Noise
Spectral Density

1--:~'""1-+--+-H~-F-+-+---i

10M

TEMPERATURE _

°c

Figure 18. Slew Rate vs.
Temperature
OPERA TIONAL AMPLIFIERS 2-49

•

AD827
I II

-40

VOUT

Ii'

VIN=OdBm

-50

'II

/1

-60

~

r:
~

I.

u

RL~~~ "- ~15V
~L=I'~

-90
-100

J/l I

-110
10k

100k

1M
FREQUENCY - Hz

10M

=

=

RL 500n FOR tV. 5V.1kn FOR ±v" = 15V
USE GROUND PLANE
PINOUT SHOWN IS FOR MINIDIP PACKAGE
100M

Figure 20. Crosstalk Test Circuit

Figure 19. Crosstalk vs. Frequency

INPUT PROTECTION PRECAUTIONS
An input resistor (resistor RIN of Figure 21a) is recommended
in circuits where the input common-mode voltage to the AD827
may exceed (on a transient basis) the positive supply voltage.
This resistor provides protection for the input transistors by limiting the maximum current that can be forced into their bases.

For high performance circuits, it is recommended that a second
resistor (Ra in Figures 21a and 22a) be used to reduce biascurrent errors by matching the impedance at each input. This
resistor reduces the error caused by offset voltages by more than
an order of maguitude.

RB
12511

.v,

Figure 21a. Follower Connection

1kU

Figure 21b. Follower Large Signal
Pulse Response

Figure 21c. Follower Small Signal
Pulse Response

Figure 22b. Inverter Large Signal
Pulse Response

Figure 22c. Inverter Small Signal
Pulse Response

1kU

.v,

rI
OPTJONAL d.
BYPASStNG T

RB
487U

Figure 22a. Inverter Connection

2-50 OPERATIONAL AMPLIFIERS

REV. 0

Applications-AD827
+Ys

A HIGH SPEED 3 OP AMP INSTRUMENTATION
AMPLIFmR CIRCUIT
The instrumentation amplifier circuit shown in Figure 24 can
provide a range of gains. The chart of Table II details
performance.

~N

.vs

TRIM FOR BEST
SETTLINGnME

•

2-BpF

TAIMFOR

OPTIMUM
BANDWIDTH

VOUT

7-15pF

Figure 23. A Video Line Driver

2kU

R,

VIDEO LINE DRIVER
The AD827 functions very well as a low cost, high speed line
driver for either terminated or unterminated cables. Figure 23
shows the AD827 driving a'doubly terminated cable in a follower configuration.
The termination resistor, Rn (when equal to the cable's characteristic impedance) minimizes reflections from the far end of the
cable. While operating from ±S V supplies, the AD827 maintains a typical slew rate of 200 V/",s, which means it can drive a
±I V, 30 MHz signal into a terminated cable.

+v..
CIRCUIT GAIN

NOTE: PINOUT SHOWN IS FOR MINIDIP PACKAGE

Figure 24. A High Bandwidth Three Op Amp Instrumentation Amplifier

Video Line Driver Performance Summary
VIN*

o dB or ±SOO mV Step
o dB or ±SOO mV Step
o dB or ±SOO mV Step
o dB or ±500 mV Step
o dB or ±500 mV Step
o dB or ±SOO mV Step

VSUPPLY
±IS
±15
±15
±5
±5
±S

Cc

-.3 dB Bw

Overshoot

20 pF
15 pF
o pF
20 pF
15 pF
OpF

23 MHz
21 MHz
J3MHz
18 MHz
16 MHz
II MHz

4%
0%
0%
2%
0%
0%

NOTE
* - 3 dB bandwidth numbers are for the 0 dBm signal input. Overshoot numbers are the perceot overshoot of the 1 Volt step input.

= ~o + 1

Small Signal
Bandwidth
@ 1 V p-p Output

Gain

Ro

I
2
10
100

Open
2k
2260
200

16.1 MHz
14.7 MHz
4.9 MHz
660 kHz

Table II. Performance Specifications for the Three Op
Amp Instrumentation Amplifier

Table I. Video Line Driver Performance Chart
A back-termination resistor (RBn also equal to the characteristic
impedance of the cable) may be placed between the AD827 output and the cable input, in order to damp any reflected signals
caused by a mismatch between RT and the cable's characteristic
impedance. This will result in a flatter frequency response,
although this requires that the op amp supply ± 2 V to the output in order to achieve a ± I V swing at resistor RT .

REV. 0

OPERA TIONAL AMPLIFIERS 2-51

AD827
bandwidth. The 1.25 rnA full-scale output current of the AD539
and the 3 kO feedback resistor set the full-scale output voltage
of each multiplier at 3.25 V p-p.

A TWO-CHIP VOLTAGE-CONTROLLEO AMPLIFIER
.
(VCA) WITH EXPONENTIAL RESPONSE
Voltage-controlled amplifiers are often used as. building blocks
in automatic gain control systems. Figure 25 shows a two-chip
VCA built using the A0827 and the AD539, a dual, currentoutput multiplier. As configured, the circuit has its two multipliers connected in series. They could also be placed in parallel
with an increase in bandwidth and a reduction in gain. The gain
of the circuit is controlled by Vx, which can range from 0 to
3 V dc. Measurements show that this circuit easily supplies 2 V
p-p into a 100 0 load while operating from ±5 V supplies. The
overall bandwidth of the circuit is approximately 7 MHz with
0.5 dB of peaking.

Current limiting in the AD827 (typically 30 mA) limits the output voltage in this application to about 3 V p-p across a 100 0
load. Driving a 50 0 reverse-terminated load divides this value
by two, liiniting the maximum signal delivered to a 50 0 load to
about 1.5 V p-p, which suffices for video signalleve1s. The dynamic range of this circuit is approximately 55 dB and is primarily limited by feedthrough at low input levels and by the maximum output voltage at high levels.
Guidelines for Grounding and Bypassing
When designing practical high frequency circuits using the
AD827, some special precautions are in order. Both short interconnection leads and a large ground plane are needed whenever
possible to provide low resistance, low inductance circuit paths.
One should remember to minimize the effects of capacitive coupling between circuits. Furthermore, IC sockets should be
avoided. Feedback resistors should be of a low enough value
that the time constant formed with stray circuit capacitances at
the amplifier summing junction will not limit circuit performance. As a rule of thumb, use feedback resistor values that are
less than 5 kO. If a larger resistor value is necessary, a small
«10 pF) feedback capacitor in parallel with the feedback resistor may be used. The use of 0.1 ILF ceramic disc capacitors is
recommended for bypassing the op amp's power supply leads~

Each half of the AD827 serves as an IN converter and converts
the output eurtent of one of the two multipliers in the AD539
into an output voltage. Each of the AD539's two multipliers
contains two internal 6 kO feedback resistors; one is connected
between the CHI output and ZI, the other between the CHI
output and WI. Likewise, in the CH2 multiplier, one of the
feedback resistors is connected between CH2 and Z2 and the
other is connected between CH2 and Z2. In Figure 25, ZI and
WI are tied together, as are Z2 and W2, providing Ii 3 kO feedback resistor for the op amp. The 2 pF capacitors connected
between the AD539's WI and CHI and W2 and CH2 pins are
in parallel with the feedback resistors and thus reduce peaking
in the VCA's frequency response. Increasing the values of C3
and C4 can further reduce the peaking at the expense of reduced
INPUT RANGE:
10MV TO 3V (55dB) ,..-_ _ _ _.,

AD539
Vx

r--l

1 CONTROL
2 HF COMP

VO.II1~F 3 CH 1
+5V

4.70

4 IN

.-AMr-!:;;-:;:::;;1 +Vs
4.70 ..... O.1~F
...f-AM,.....v~45 -Vs
O.1~F ~ 6 CH2

-5V

IN

7 INPUT
COM
8 OUTPUT
COM
·PINOUT SHOWN IS FOR MINI·DIP PACKAGE

VouTAT TERMINATION RESISTOR,

~

VX2 VIN

= av;-

V'V
VOUT AT PIN & OF AD827 = ~
4V'

Figure 25. A Wide Range Voltage-Controlled Amplifier Circuit

2-52 OPERA TIONAL AMPLIFIERS

REV. 0

1IIIIIIII ANALOG

WDEVICES

High Speed, Low Noise Video Op Amp
AD829 I

FEATURES
High Speed
120 MHz Bandwidth. Gain = -1
230 V/".s Slew Rate
90 ns Settling Time to 0.1%
Ideal for Video Applications
0.02% Differential Gain
0.040 Differential Phase
Low Noise
2 nV/YHz Input Voltage Noise
1.5 pA/YHz Input Current Noise
Excellent DC Precision
1 mV max Input Offset Voltage (Over Temp)
0.3 ".v/oe Input Offset Drift
Flexible Operation
Specified for :t:5 V to :t:15 V Operation
:t:3 V Output Swing into a 150 n Load
External Compensation for Gains 1 to 20
5 mA Supply Current
PRODUCT DESCRIPTION
The AD829 is a low noise (2 nV/y'Hz), high speed op amp with
custom compensation that provides the user with gains from ± 1
to :t:20 while maintaining a bandwidth greater than 50 MHz.
The AD829's 0.040 differential phase and 0.02% differential gain
performance at 3.58 MHz and 4.43 MHz, driving reverseterminated 50 n or 75 n cables, makes it ideally suited for professional video applications. The AD829 achieves its 230 V/!,-s
uncompensated slew rate and 750 MHz gain bandwidth product
while requiring only 5 mA of current from the power supplies.
The AD829's external compensation pin gives it exceptional versatility. For example, compensation can be selected to optimize
the bandwidth for a given load and power supply voltage. As a
gain-of-two line driver, the - 3 dB bandwidth can be increased
to 95 MHz at the expense of 1 dB of peaking. In addition, the
AD829's output can also be clamped at its external compensation pin.
The AD829 has excellent dc performance. It offers a minimum
open-loop gain of 30 V/mV into loads as low as 500 n, low input voltage noise of 2 nV/y'Hz, and a low input offset voltage
of 1 m V maximum. Common-mode rejection and power supply
rejection ratios are both 120 dB.
The AD829 is also useful in multichannel, high speed data conversion where its fast (90 ns to 0.1 %) settling time is of importance. In such applications, the AD829 serves as an input buffer
for 8-to-1O-bit AID converters and as an output IIV converter
for high speed DIA converters.

REV. 0

CONNECTION DIAGRAM
8-Pin Plastic Mini-DIP (N),
Cerdip (Q) and SOIC (R) Packages
OFFSET

OFFSET

NULL

NULL

-IN

+vs

+IN

OUTPUT

CCOMP

The AD829 provides many of the same advantages that a transimpedance amplifier offers, while operating as a traditional voltage feedback amplifier. A bandwidth greater than 50 MHz can
be maintained for a range of gains by changing the external
compensation capacitor. The AD829 and the transimpedance
amplifier are both unity gain stable and provide similar voltage
noise performance (2 nV/y'Hz). However, the current noise of
the AD829 (1.5 pNy'Hz) is less than 10% of the noise of transimpedance amps. Furthermore, the inputs of the AD829 are
symmetrical.
PRODUCT HIGHUGHTS
1. Input voltage noise of 2 nV/y'Hz, current noise of 1.5
pNy'Hz and 50 MHz bandwidth, for gains of I to 20, make
the AD829 an ideal preamp.
2. Differential phase error of 0.04 and a 0.02% differential gain
error, at the 3.58 MHz NTSC and 4.43 MHz PAL and
SECAM color subcarrier frequencies, make it an outstanding
video performer for driving reverse-terminated 50 n and
75 n cables to ± 1 V (at their terminated end).
0

3. The AD829 can drive heavy capacitive loads.
4. Performance is fully specified for operation from ± 5 V to
± 15 V supplies.
5. Available in plastic, cerdip, and small outline packages.
Chips and MIL-STD-883B parts are also available.

OPERA TlONAL AMPLIFIERS 2-53

AD829 -SPECIFICATIONS
Model

(@ TA

Conditions

INPUT OFFSET VOLTAGE

= +25°C and Vs = ±15 V dc, unless otherwise noted)
Vs

Min

AD829J
Typ

±S V, ±IS, V

0.2

±SV,±ISV

0.3

±SV,±ISV

3.3

Tmin to T"""
Offset Voltage Drift
INPUT BIAS CURRENT

T min to·Tmax
INPUT OFFSET CURRENT

±SV, ±ISV

50

±S V, ±IS V

0.5

Tmin to Tmax
Offset Current Drift
OPEN-LOOP GAIN

Vo=±2.5V
RLOAD = 500 n

30
20

Full Power Bandwidth 2

Vo=2Vp-p
RLOAD = 500 n
Vo = 20 V p-p
R LOAD = 1 kn
RLOAD = 500 n
R LOAD = I kn
Av = -19
-2.5 V to +2.5 V
10 V Step
CLOAD = 10 pF
RLOAD = I kn

Slew Rate2
Settling Time to 0.1%

Phase Margin2

0.5
0.5

0.3
7
8.2

3.3

500
500

50
0.5

7
9.5
500
500

Units
mV
mV
,.VI"C
,.A

!LA
nA
nA
nAl"C

65

30
20

65
40

V/mV
V/mV
V/mV

85

85

V/mV
V/mV
V/mV

±S V
±ISV

600
750

600
750

MHz
MHz

±SV

25

25

MHz

±ISV
±S V
±ISV

3.6
150
230

3.6
ISO
230

V/,.s
V/,.s

±SV
±IS V
±IS V

65
90

65
90

ns
ns

60

60

Degrees

0.02

0.02

%

50
20

DIFFERENTIAL GAIN ERROR'

RLOAD

= lOon
CcOMP = 30 pF

±IS V

DIFFERENTIAL PHASE ERROR'

R LOAD = loon
CcoMi = 30 pF

±IS V

COMMON-MODE REJECTION

VCM = ±2.S V
VCM = ±12 V

±SV
±IS V

POWER SUPPLY REJECTION

Vs = ±4.5 V to ± 18 V
T min to ~max

T~n to

0.1

40

RLOAD = 500 n

l•

I
I

AD829A1S
Typ
Max

±IS V

Tmin to Tmax
DYNAMIC PERFORMANCE
Gain Bandwidth Product

Min

±SV

Tmio to Tmax
RLOAD = 150 n
V6UT = ±IOV
RLOAD = 1 kn

Max

100

50
20

MHz

0.04

Degrees

100
100
96

120
120

100
100
96

120
120

dB
dB
dB

98
94

120

98
94

120

dB
dB

0.04

Tmax

100

INPUT VOLTAGE NOISE

f= I kHz

±IS V

2

2

nV/YHz

INPUT CURRENT NOISE

f= 1kHz

±IS V

I.S

1.5

pAlyHZ

±SV

+4.3
-3.8
+14.3
-13.8

+4.3
-3.8
+14.3
-13.8

V
V
V
V

3.6
3.0
1.4
13.3
12.2
32

±V
±V
±V
±V
±V
mA

13
S
1.5

13
S
I.S

kn
pF
pF

2

2

Mn

INPUT COMMON-MODE
VOLTAGE RANGE

±ISV
OUTPUT VOLTAGE SWING

RLOAD
RLOAD
RLOAD
RLOAD
RLOAD

- soon
= Ison
= son
=1 kO
= soo n

Short Circuit Current
INPUT CHARACTERISTICS
Input Resistance (Differential)
Input Capacitance (Differential)'
Input Capacitance (Common Mode)
CLOSED-LOOP OUTPUT
RESISTANCE

2-54 OPERA TIONAL AMPLIFIERS

Av = + I, f = I kHz

SV
SV
SV
IS V
ISV
SV, ±ISV

3.0

2.S
12
10

3.6
3.0
1.4
13.3
12.2
32

3.0

2.S
12
10

REV. 0

AD829
Conditions

Model

Min

Vs

POWER SUPPLY
Operating Range
Quiescent Current

AD829J
Typ

±4.5
±5 V

5

±15 V

5.3

T min to Tmalt

T min to Tmax
TRANSISTOR COUNT

Max

Min

±18
6.5
8.0
6.8
8.3

±4.5
5
5.3

46

Number of Transistors

AD829 AJS
Typ
Max
±18
6.5
8.218.7
6.8
8.5/9.0

Units
V
rnA
rnA
rnA
rnA

46

NOTES
'Full Power Bandwidth = Slew Ratel2 "VPEAK '
2Tested at Gain = + 20, CCOMP = 0 pF.
'3.58 MHz (NTSC) and 4.43 MHz (PAL & SECAM).
4Differential input capacitance consists of 1.S pF package capacitance plus 3.5 pF from the input differential pair.
Specifications subject [0 change without notice.

ABSOLUTE MAXIMUM RATINGS'
Supply Voltage . . . . . . . . . . . . . . . . .
. .. ±18V
Internal Power Dissipation2
Plastic (N) ....
. . 1.3 Watts
Small Outline (R) . . . . .
. . 0.9 Watts
Cerdip (Q) . . . . . . . . . .
. . 1.3 Watts
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±Vs
Differential Input Voltage' . . . . . . . . . . . . . . . . . . ±6 Volts
Output Short Circuit Duration . . . . . . . . . . . . . . . Indefinite
-65°C to + 150°C
Storage Temperature Range Q . . . . . .
Storage Temperature Range N, R . . . . . . . . -65°C to + l25'C
Operating Temperature Range
AD829J . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to + 70°C
AD829A . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
AD829S . . . . . . . . . . . . . . . . . . . . . . . -SSOC to + 125°C
Lead Temperature Range (Soldering 60 sec) ....... + 300°C

II

METALIZATION PHOTO
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
NULL
1

NULL
8

-IN

2

+IN
3

NOTES
IStresses above those listed under "Absolute Maximum Ratings" may cause
pennanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational section of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
2Maximum internal power dissipation is specified so that T J does not exceed
+ 175°C at an ambient temperature of + 25°C.
Thermal characteristics:
8-pin plastic package: alA = lOO'C/watt (derate at 8.7 mW/'C)
8-pin cerdip package: alA = llO'C/watt (derate at 8.7 mW/,C)
8-pin small outline package: alA = 155'C/watt (derate at 6 mW/,C).
3If the differential voltage exceeds 6 volts, external series protection resistors
should be added to limit the input current.

I"

SUBSTRATE CONNECTED
TO +Vs

ORDERING GUIDE
Model
AD829JN
AD829JR'
AD829AQ
AD829SQ
AD829SQ/883B

Temperature
Range

Package
Description

Package
Options l • 2

o to
o to

8-Pin
8-Pin
8-Pin
8-Pin
8-Pin

N-8
R-8
Q-8
Q-8
Q-8

+70°C
+70°C
-40°C to +85°C
-55°C to + 125°C
- 55°C to + 125°C

Plastic Mini-DIP
Plastic SOIC
Cerdip
Cerdip
Cerdip

NOTES
'N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOlC). For outline information
see Package Information section.
'J grade chips also available.
'Available in tape and reel packaging.

REV. 0

OPERA TIONAL AMPLIFIERS 2-55

AD829 - Typical Performance Characteristics
2O..-----,.--"'T""---r----,

2O"---~--"'T""--r---'

30

I I II

.....±15'VOL~ I
SUPPLIES

I

J

J

oL-_~

°0~----~----~1~0----~1~5----~2'0

'1I
!i:

5.5

II:
II:

~~

-

5.0

!i:w

..
...

-

!i:

M
5 4.5

100

~

:::>

U

:!i

r--.. ........

Figure 3. Output Voltage Swing vs.
Resistive Load

100

r----r---,----,---~--~

10

\---t---\--+--7''-tT--\

-3

0.1

\---t-r-\T-+---+---\

0.01

\---+:,.--\--+---+---\

Vs = ±5V, ±15V

I'--.
a.

g

a.
i!:

a

10k

lk

-4

II:
II:

!;

±SVOLT

ItUPtLli,

LOAD RESISTANCE - Ohmo

-5

w
U

o

~_~

Figure 2. Output Voltage Swing vs.
Supply Voltage

8.0

:::>

__

SUPPLY VOLTAGE - ±Vo""

Figure 1. Input Common-Mode
Range vs. Supply Voltage

I

~

10

SUPPLY VOLTAGE - ±Vo""

1

__

o

""

:.- _r-

..
c

4.0

-2

o

10

20

15

-60 -40 -20 0

SUPPLY VOLTAGE - ±von.

Figure 4. Quiescent Current vs.
Supply Voltage

VS =±15V

I'II~
~

~~

~

~

?

~~

20 40

60 80 100 120 140

~

10k

TEMPERATURE - ·C

;..-

~ IT

Vs=±5V

40

"
I

t:

35

~

~

11

30 -

II:

~

~~
iT '~

POSITIVE
CURRENT LIMIT

:::>

25

Ii!
u
Ii:0

20

:::>

..

10M

100M

65

NE~ATI~E

I
CURRENT LIMIT

~I

I

U

t:

1M

Figure 6. Closed-Loop Output Impedance vs. Frequency

Figure 5. Input Bias Current vs.
Temperature

E

lOOk

FREQUENCY - Hz

Vs=±5V

~

,

if
::E

vL!J
Av =.20
C coup =OpF

60

I

:z:

"

I'

..."~...
z

..
I

55

-

I-"

50

:z:

3
-60 -40 -20 0

20 40 60 80 100 120140

TEMPERATURE _·C

Figure 7. Quiescent Current vs.
Temperature

2-56 OPERA T10NAL AMPLIFIERS

15
-60 -40 -20 0

45
20 40 60 80 100 120 140

AMBIENT TEMPERATURE - ·C

Figure 8. Short Circuit Current
Limit vs. Temperature

-60 -40 -20

0

20 40

60 80 100 120 140

TEMPERATURE - ·C

Figure 9. -3 dB Bandwidth vs.
Temperature

REV. 0

AD829

...

120

"--"--T"""""'""T'"-""T'"-.,.-....,

100

1=:::j::::::::~I-I~

ID

~

i

40

...

+40

~

~

E1

CJ

8

~--lI ~

1---+--+--+--+.......

o

r--Js~1l5vl ~.

-

95

;;

__- k__

lk

10k

~

__

lOOk

~

1M

go

i5a.

+20

__

o

75
10

100M

rr
rr
60

.

~ 20
I

~

lOOk

10k

1M

FREQUENCY - Hz

'"

10M

I;;

100M

I

-100

11

RL =2kO

~

-

30k

lOOk

Figure 16. Total Harmonic Distortion (THO) vs. Frequency

-2

I;;
a.
I;;

-4

1%

0.1%

1%

0.1%

o

~ ~
20

I-

40

60

80

100 120 140 160

Figure 15. Output Swing & Error vs.
Settling Time

~ t------i~----t-____t_---t-----1
~

40

CCOMP=30pF

I

~

t-t--

SETTLING nME - ns

Av=-l

-30

!g -

r--

1\

-8

100

,

_\ ..1

-6
-10

ERROR AV=-19
CCOMP =OpF

,----,-----,-----r----..

-SO I---+---+~~~~--i

4

~

3 ..
I\\---t-----t---,t---t----t---l

~

2\--~+-_+-+--+--+---1

~

1\

!:;

g
~

.,

_~L-

10k

3:


-

Y'N = 2.24V RMS

=100pF

II 1

INPUT FREOUENCY - MHz

)

-go

-110
100

I

10

- 20

I---- t-- CCOMP= 30pF

In

~

I I

V,N =3VRMS
Ay =-l
CLOAO

...

Figure 12. Power Supply Rejection
Ratio (PSRR) vs. Frequency

g
V.=±15V
RL =lkn
A y =+2O

CC';"P =ripF

0

-70

- 80

t- V.=±5V

0
R L = SOOO
> 10
t- Ay= +20 I;;
a.

Figure 13. Common-Mode Rejection Ratio vs. Frequency

I--- t--

15

!:;

"\

I I

lk

10k

~

"\

=

CCOMP = OpF

20

lk

10

I..

"\

I

•

40

100

a. 25 i--

BO

I--

60

30

,~

'\
40

~

Figure 11. Open-Loop Gain vs.
Resistive Load

100

~

BO

I

LOAD RESISTANCE - 0

Figure 10. Open-Loop Gain & Phase
Margin vs. Frequency

ill

ID

rr
rr

II

FREOUENCY - Hz

120

...

85

L-~

10M

-

100

\~~
,
Vs=i5V -

80

100

I'
i--"

-i

20
0L-~

120

III

100
ID

80

~D.60

105

+100

o

__

~

____- k____-L__

500k

1M

~

105M

FREQUENCY - Hz

Figure 17. 2nd & 3rd Harmonic
Distortion vs. Frequency

2M

It---t---t---t---t---T---i

0'-_'--_'--_'--_'--_'----'
10

100

lk

10k

lOOk

1M

10M

FREQUENCY - Hz

Figure 18. Input Voltage Noise
Spectral Density

OPERA TIONAL AMPLIFIERS 2-57

AD829
400

0.03

350

I

" r--

~300

.
'"
0

> 250

I

OIFFC)AIN

I

"'....

"
0:

...

~

200

~

.o

~ 150

0:

~


....
'"

5Do
50

±1SV:~

-32

I-r-

,

\\
\

I-- V,N = -38

20dBM
RL=Ik.Q
RF=Ik.Q
GAIN=-1
c eCIIP = 4pF

-

\

\

-44

2k.Q
10

100

FREQUENCY - MHz

Figure 35. Closed-Loop Frequency Response vs. Supply
for the Inverting Amplifier Using Current Feedback
Compensation

A Low Error Video Line Driver
The buffer circuit shown in Figure 37 will drive a backterminated 75 n video line to standard video levels (1 V p-p)
with 0.1 dB gain flatness to 30 MHz with only 0.04° and 0.02%
differential phase and gain at the 4.43 MHz PAL color subcarrier frequency. This level of performance, which meets the
requirements for high definition video displays and test equipment, is achieved using only 5 rnA quiescent current.

Figure 36. Noninverting Amplifier Connection Using
Current Feedback Compensation

7511

7511
COAX
CABLE

OPTIONAL

2-7pF
FLATNESS
TRIM

Figure 37. A Video Line Driver with a Flatness over
Frequency Adjustment

REV. 0

OPERA TIONAL AMPLIFIERS 2-63

•

2-64 OPERA TIONAL AMPLIFIERS

r.ANALOG
WDEVICES
FEATURES
Wideband AC Performance
Gain Bandwidth Product: 400 MHz (Gain 2: 10)
Fast Settling: 100 ns to 0.01% for a 10 V Step
Slew Rate: 400 V/",s
Stable at Gains of 10 or Greater
Full Power Bandwidth: 6.4 MHz for 20 V p-p into a
5000 Load
Precision DC Performance
Input Offset Voltage: 0.3 mV max
Input Offset Drift: 3
typ
Input Voltage Noise: 4 nV/VHz
Open-Loop Gain: 130 VlmV into a 1 kO Load
Output Current: 50 mA min
Supply Current: 12 mA max

",vrc

APPLICATIONS
Video and Pulse Amplifiers
DAC and ADC Buffers
Line Drivers
Available in 14-Pin Plastic DIP, Hermetic Cerdip
and 20-Pin LCC Packages and in Chip Form
MIL-STD-883B Processing Available
PRODUCT DESCRIPTION
The AD840 is a member of the Analog Devices' family of wide
bandwidth operational amplifiers. This high speedlhigh precision
family includes, among others, the AD841, which is unity-gain
stable, and the AD842, which is stable at a gain of two or
greater and has 100 rnA minimum output current drive. These
devices are fabricated using Analog Devices' junction isolated
complementary bipolar (CB) process. This process permits a
combination of dc precision and wideband ac performance previously unobtainable in a monolithic op amp. In addition to its
400 MHz gain bandwidth product, the AD840 offers extremely
fast settling characteristics, typically settling to within 0.01 % of
final value in 100 ns for a 10 volt step.
The AD840 remains stable over its full operating temperature
range at closed-loop gains of 10 or greater. It also offers a low
quiescent current of 12 rnA maximum, a minimum output current drive capability of 50 rnA, a low input voltage noise of
4 nV/VHz and a low input offset voltage of 0.3 mV maximum
(AD840K).
The 400 V/fJ-S slew rate of the AD840, along with its 400 MHz
gain bandwidth, ensures excellent performance in video and
pulse amplifier applications. This amplifier is ideally suited for
use in high frequency signal conditioning circuits and wide
bandwidth active filters. The extremely rapid settling time of

REV. A

Wideband,
Fast Settling Op Amp
AD840 I
CONNECTION DIAGRAMS

•

LCC (E) Package

Plastic DIP (N) Package
and
Cerdip (Q) Package

g

::l

"

z

z

~

!i

0

3

2

u

,

Z

~

2.

!i

'9

NC 4

18 NC

-IN 5

17 +Vs

NC.

16 Ne

+IN 7

1S OUTPUT
14 NC

NC B

~

f

~ ~ ~

NC == NO CONNECT

the AD840 makes it the preferred choice for data acquisition
applications which require 12-bit accuracy. The AD840 is also
appropriate for other applications such as high speed DAC and
ADC buffer amplifiers and other wide bandwidth circuitry.
APPLICATION HIGHLIGHTS
I. The high slew rate and fast settling time of the AD840 make
it ideal for DAC and ADC buffers, line drivers and all types
of video instrumentation circuitry.
2. The AD840 is truly a precision amplifier. It offers 12-bit
accuracy to 0.01 % or better and wide bandwidth, performance previously available only in hybrids.
3. The AD840's thermally balanced layout and the high speed
of the CB process allow the AD840 to settle to 0.0 I % in
100 ns without the long "tails" that occur with other fast op
amps.
4. Laser wafer trimming reduces the input offset voltage to
0.3 mV max on the K grade, thus eliminating the need for
external offset nulling in many applications. Offset null pins
are provided for additional versatility.
5. Full differential inputs provide outstanding performance in
all standard high frequency op amp applications where circuit
gain will be 10 or greater.
6. The AD840 is an enhanced replacement for the HA2540.

OPERATIONAL AMPLIFIERS 2-65

AD840-SPECIFICATIONS

(@ +25°C and ±15 V dc, unless otherwise noted)

Model
Conditions

Min

INPUT OFFSET VOLTAGE'

AD840J
Typ
Max
0.2

0.1

3.5

S
10

3.5

5
6

0.1

0.4
0.5

0.1

0.2
0.3

5

INPUT BIAS CURRENT
Tmm-Tmax
INPUT OFFSET CURRENT
Tmm - Tmax
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance

INPUT VOLTAGE NOISE
Wideband Noise

f=lkHz
10 Hz to 10 MHz

OPEN LOOP GAIN

Vo = ±lOV
RLOAD = 1 kG

T min ..... Tmax

T min - Truax
RLOAD = 500 {}
T min - Tmax
RLOAD

T min

FREQUENCY RESPONSE
Gain Bandwidth Product
Full Power Bandwidth'
Rise Time
Overshoot'
Slew Rate'
Settling Time' -10 V Step

0.3
0.7

AD840S
Typ
Max

Units

1
2

mV
mV
fJ-VI"C

3.5

S
12

0.1

0.4
0.6

JJ.A
JJ.A
JJ.A
JJ.A

0.2

3

30
2

VCM = ±10V

Current
Output Resistance

Min

5

Differential Mode

INPUT VOLTAGE RANGE
Common Mode
Common-Mode Rejection

OUTPUT CHARACTERISTICS
Voltage

AD840K
Typ
Max

1
1.5

Tmin - Tmax
Offset Drift

Min

-

2:

±10
90
85

30
2

12
110

±10
106
90

4
10
100
50
75
SO

12
1lS

±IO
90
85

4
10

130
80

100
75
100
75

130
100

100
50
75
SO

30
2

kG
pF

12
110

V
dB
dB

4
10

nV/y'Hz
fJ-Vrms

130
80

V/mV
V/mV
V/mV
V/mV

500 {}

Tmax

VOUT = ±lOV
Open Loop
VOUT = 90 mV p-p
Av = -10
Vo = 20Vp-p
RLOAD 2: 500 {}
Av = -10
Av = -10
Av = -10
Av = -10
toO.l%
to 0.01%

±10
50

5.5

350

±10
50

V

±10
50

rnA

15

IS

15

G

400

400

400

MHz

6.4
10
20
400

MHz
ns
%
VlfJ-s

6.4
10
20
400

5.5

350

6.4
10
20
400

5.5

350

80
100

80
100

80
100

ns
ns

+ Overdrive

190
350

190
350

190
350

ns'
ns

DIFFERENTIAL GAIN

f = 4.4 MHz

0.025

0.025

0.025

%

DIFFERENTIAL PHASE

f = 4.4 MHz

0.04

0.04

0.04

Degree

OVERDRIVE RECOVERY

-Overdrive

POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current

±15
±5
10.5

T min
Power Supply Rejection Ratio

-

Tmax

Vs= ±5Vto±18V

T min

-

Tmax

TEMPERATURE RANGE
Rated Performance4
TRANSISTOR COUNT

90
80

100

0

# of Transistors

2-66 OPERA TIONAL AMPLIFIERS

±15
±lS
12
14

10.5
94
86

+75

72

±5

±15
±lS
12
14

+75

72

10.5
90
80

100

0

±5

±lS
12
16

100

-55

V
V

rnA
rnA
dB
dB

+125

°C

72

REV. A

AD840
NOTES
IInput offset voltage specifications are guaranteed after 5 minutes at TA := +2S oC.
2Full power bandwidth = slew rate!21T VPEAK '
'Refer to Figures ZZ and Z3.
""S" grade Tmin-Tmax specifications are tested with automatic test equipment at TA = -55°C and TA = +12S oC.
All min and, max specifications are guaranteed. Specifications shown in boldface are tested on all production units.
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS'
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation 2
Plastic (N) . . . . . . . . . . .
1.5 W
Cerdip (Q) . . . . . . . .
I.3W
LCC(E) . . . . . . . . . . . .
1.0 W
Input Voltage . . . . . . . . . .
. . . . . . . . . . . ±Vs
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . ± 6 V
Storage Temperature Range
Q, E . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to + 150°C
N . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to + 125°C
Junction Temperature (TJ ) • . . • • • • • • • • • . • . .
+ 175°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . + 300°C

•

Plastic DIP (N) Package
and
Cerdip (Q) Package

NOTES
IStresses above those listed under "Absolute Maximum Ratings" may cause

permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated
in the operational section of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
2Maximum internal power dissipation is specified so that Tl does not exceed
+ 175°C at an ambient t.:mperature of + 25°C.
Thermal Characteristics:
B
9lA
Derate at
Cerdip Package 30°CIW lWOCIW 8.7 mW/oC
Plastic Package 30°CIW 100°CIW 10 mWrC
LCC Package
3S oCIW ISO°CIW 6.7 mWrC

LCC (E) Package
::I

"z

,C

~

~O

1

20 19

!i

NC 4

Recommended Heat Sink:
Aavid Engineering

10

~
o

/

•

V

o
10
15
SUPPLY VOLTAGE_ ±Volts

10

20

100
lk
LOAD RESISTANCE - H

Figure 2. Output Voltage Swing
vs. Supply Voltage

0

-

10k

Figure 3. Output Voltage Swing
vs. Load Resistance

f

1/

I'

!

,

'\

8

ffi

~

15V SUPPLIES

wI 5

100

E

o

/

, 20

12

.,

5

!

~

6

5
10
15
SUPPLY VOLTAGE - :': Volts

0

§

!;

e:

t2

/.

15

>

V"
~

o
o

0

~

I

1\r'\.

6

" --

/

~ o.

o

10
15
SUPPLY VOLTAGE _ :rVolts

20

3
-60 -40

/

0
20
40
60
TEMPERATURE - "C

80

100 120 140

/
/

0

/

1

0

V

tOOk

.
0

7/
40

80

80

100 1211 140

TEMPERATURE - "c

Figure 7. Quiescent Current vs.
Temperature

2-68 QPERA TlQNAL AMPLIFIERS

1M

10M

h

~hUTP'uT CURRENT
5

~

CUR~ENT ~

0

" "'"

• / 1/

~~

-60 -40 -20 0
20
40
60
80 100
AMBIENT TEMPERATURE - gc

100M

Figure 6. Output Impedance vs.
Frequency

1\

/
20

''""

- OUTPUT

/

,/

-60 -40 -20

10k

45 0

0"0

I'

0.0 1

FREQUENCY - Hz

140

14

1/

1

Figure 5. Input Bias Current vs.
Temperature

Figure 4. Quiescent Current vs.
Supply Voltage

15

-20

/

1

f".. ........

4

/

0

120 140

Figure 8. Short-Circuit Current
Limit vs. Temperature

3'-60
•

/

-40 -20

V

/

I

/ \

~

Av = 10

20 40
60 80
TEMPERATURE - "C

100 120 140

Figure 9. Gain Bandwidth Product
vs. Temperature

REV. A

AD840
20

'00

,

+'00

t-- 1'-." -- -- --.

"

\

\

"I'-."

0

40

+60

\

\
\
+'0

\

'" "

\
+20

"" LOT

0
'00

10k

1k

tOOk

1M

~

E,
~
:Ii
:E
III

95

-20
100M

~

90

o

.

10

..

2.

15

Figure 1,. Open-Loop Gain vs.
Supply Voltage

IIII I
=

!\

,

Rt :: lkH
+ 25°C
\V s =±15V

\

1M

~

-,.

100M

-130
'00

~

~~

HARMON''i/

17

40

.'"

50

~
.......

~

I'-.....

60
70
80
SETTLING TIME - ns

90

I-

V

vI--'

3RDHARMONIC

'00

6

t-1\\HfttH--+tt+-+-I-tfjf-+++t+-H++l+++-H

~ 5~-kH++-H+~-H~~~f-+-H~}4+H

1/

V-

1k

V
,/

45 0

~

i/

i

1000

Figure 16. Harmonic Distortion vs.
Frequency

1

/

~400
~

/

-. 350

300

I

FREQUENCY - Hz

REV. A

\

5 ••

lNl

-11 0

-120

•.• ,%

I:!! 1 H-H+l--f-++It+Hl-I+++H--f-+++l--H+H

I

_9 0

-100

~

V

100

'10

Figure 15. Output Swing and
Error vs. Settling Time

I
3VRMS
Rl = lkU

~

~

./

V

...

., -so
-=

0.1%

'\

30

Figure 14. Large Signal Frequency
Response

-1 0

I

0.01%

FREQUENCY·· Hz

Figure 13. Common-Mode
Rejection vs. Frequency

Z

0.1%

•

'OM

100M

•

7

-B

'OM

100M

0

i

FREQUENCY - Hz

10M

;/

/

r-..

,

0

1M

. / ......

/

0

r-..

100k

tOOk

Figure 12. Power Supply Rejection
vs. Frequency

"1\

Vs == ±1SV

I

1\

FREQUENCY - Hz

7

'\

10k

10k

1k

,.

V CM
1V pop
~25'C

I

"

•
•,

SUPPLY VOLTAGE - ':!:.V

0

1k

it

iil.•

lklllOAD

30

"

- SUPPLY

~

.. 2

'20

"

+SUPPLV

rJ

il!60

/

.

Figure 10. Open-Loop Gain and
Phase Margin Phase vs. Frequency

20

~

(

'00

FREQUENCY - Hz

'00

•

Z B

"

10M

,

0

!Ii,

'0'

iE

",:

20

,.

+BO

\

I'\..

0

'20

"0

.;

vI"

/

V

l/

2.0

'0

'00

'0

10k

100k

1M

'OM

FREQUENCY - Hz

Figure 17. Input Voltage Noise
Spectral Density

-60 -40 -20

20
40
60
TEMPERATURE - "C

10

100

120 140

Figure 18. Slew Rate vs.
Temperature

OPERATIONAL AMPLIFIERS 2-69

AD840
R, = 4.99kll

RIN

=

HP3314A
49911
FUNCTION
GENERATOR ~""'1111\..--<~
OR
EaUIVALENT
49.9!!

Figure 19a. Inverting Amplifier
Configuration (DIP Pinout)

R,=110U

Figure 19b. Inverter Large Signal
Pulse Response

Figure 19c. Inverter Small Signal
Pulse Response
.

Figure 20b. Noninverting Large
Signal Pulse Response

Figure 20c. Noninverting Small
Signal Pulse Response

RF = 1kn

HP3314A
FUNCTION
GENERATOR ~......-'V'w--{
OR
EaUIVALENT

Figure 20a. Noninverting Amplifier
Configuration (DIP Pinout)

OFFSET NULLING
The input offset voltage of the AD840 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 21 ~n be used.

Figure 21. Offset Nulling (DIP Pinout)

2-70 OPERATIONAL AMPLIFIERS

REV. A

Applying the AD840
AD840 SETTLING TIME
Figures 22 and 24 show the settling performance of the AD840
in the test circuit shown in Figure 23.
Settling time is defined as:
The interval of time from the application of an ideal step
function input until the closed-loop amplifier output has
entered and remains within a specified error band.
This defmition encompasses the major components which comprise settling time. They include (1) propagation delay through
the amplifier; (2) slewing time to approach the fmal output
value; (3) the time of recovery from the overload associated with
slewing; and (4) linear settling to within the specified error
band.
Expressed in these terms, the measurement of settling time is
obviously a challenge and needs to be done accurately to assure
the user that the amplifier is worth consideration for the
application.

OUTPUT:
5V/DiV

Figure 24 shows the "long-term" stability of the settling characteristics of the AD840 output after a 10 V step. There is no evidence of settling tails after the initial transient recovery time.
The use of a junction isolated process, together with careful layout, avoids these problems by minimizing the effects of transistor isolation capacitance discharge and thermally induced shifts
in circuit operating points. These problems do not occur even
under high output current conditions.

II
OUTPUT:
5V/OIV

OUTPUT
ERROR:
O.02%/DiV

Figure 24. AD840 Settling Demonstrating No Settling Tails

OUTPUT
ERROR:
O.02%/OIV

Figure 22. AD840 0.01% Settling Time

TEK

7603
OSCILLOSCOPE

GROUNDING AND BYPASSING
In designing practical circuits with the AD840, the user must
remember that whenever high frequencies are involved, some
special precautions are in order. Circuits must be built with
short interconnect leads. Large ground planes should be used
whenever possible to provide a low resistance, low inductance
circuit path, as well as minimizing the effects of high frequency
coupling. Sockets should be avoided, because the increased
inter-lead capacitance can degrade bandwidth.
Feedback resistors should be of low enough value to assure that
the time constant formed with the circuit capacitances will not
limit the amplifier performance. Resistor values of less than
5 kO are recommended. If a larger resistor must be used, a
small (± 10 pF) feedback capacitor in connected parallel with the
feedback resistor, Rp , may be used to compensate for these
stray capacitances and optimize the dynamic performance of the
amplifier in the particular application.
Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. A 2.2 f1F capacitor in parallel
with a 0.1 f1F ceramic disk capacitor is recommended.

FETPROBE
TEK P6201

Figure 23. Settling Time Test Circuit

Figure 23 shows how measurement of the AD840's 0.01 % settling in 100 ns was accomplished by amplifying the error signal
from a false summing junction with a very high speed proprietary hybrid error amplifier specially designed to enable testing
of small settling errors. The device under test was driving a
420 0 load. The input to the error amp is clamped in order to
avoid possible problems associated with the overdrive recovery
of the oscilloscope input amplifier. The error amp amplifies the
error from the false summing junction by 11, and it contains a
gain vernier to fme trim the gain.

REV. A

CAPACITIVE LOAD DRIVING ABILITY
Like all wideband amplifiers, the AD840 is sensitive to capacitive loading. The AD840 is designed to drive capacitive loads of
up to 20 pF without degradation of its rated performance. Capacitive loads of greater than 20 pF will decrease the dynamic
performance of the part although instability should not occur
unless the load exceeds 100 pF. A resistor in series with the output can be used to decouple larger capacitive loads.
USING A HEAT SINK
The AD840 draws less quiescent power than most high speed
amplifiers and is specified for operation without a heat sink.
However, when driving low impedance loads the current to the
load can be 4 to 5 times the quiescent current. This will create a
noticeable temperature rise. Improved performance can be
achieved by using a small heat sink such as the Aavid Engineering #602B.
OPERA TlONAL AMPLIFIERS 2-71

AD840
HIGH SPEED DAC BUFFER CIRCUIT

OVERDRIVE RECOVERY

The AD840's 100 ns settling time to 0.01% for a 10 V step
makes it well suited as an output buffer for high speed DIA converters. Figure 25 shows the connections for producing a 0 to
+ 10.24 V output swing from the AD568 35 ns DAC. With the
AD568 in unbuffered voltage output mode, the AD840 is placed
in noninverting configuration. As a result of the 1 kll span resistor provided internally in the AD568, the noise gain of this
topology is 10. Only 5 pF is required across the feedback (span)
resistor to optimize settling.

Figure 26 shows the overdrive recovery capability of the AD840.
Typical recovery time is 190 ns from negative overdrive and
350 ns from positive overdrive.

INPUT SQUARE WAVE
SCALE 1 VIDIVISION

+15Y

OVERDRIVEN OUTPUT
SCALE: 10V/DIVISION

r

~

TIME: 200ns/DiVISION

Figure 26. Overdrive Recovery

5

i~ ·
1

I·

HP3314A
PULSE GENERATOR

OR EQUIVALENT
l~s

±lV SQUARE

WAVE INPUT

Figure 25.0 to +10.24 V DAC Output Buffer

2-72 OPERATIONAL AMPLIFIERS

Figure 27. Overdrive Recovery Test Circuit

REV. A

IIIIIIIIIII ANALOG

WDEVICES
FEATURES
AC PERFORMANCE
Unity-Gain Bandwidth: 40 MHz
Fast Settling: 110 ns to 0.01%
Slew Rate: 300 V/",s
Full Power Bandwidth: 4.7 MHz for 20 V p-p into a
500n Load

Wideband, Unity-Gain Stable,
Fast Settling Op Amp
AD841 I
CONNECTION DIAGRAMS
Plastic DIP (N) Package
and
Cerdip (Q) Package

TO-8 (H) Package

DC PERFORMANCE
Input·Offset Voltage: 1 mV max
Input Voltage Noise: 13 nV/YHz typ
Open-Loop Gain: 45V/mV into a 1 kn Load
Output Current: 50 mA min
Supply Current: 12 mA max
APPLICATIONS
High Speed Signal Conditioning
Video and Pulse Amplifiers
Data Acquisition Systems
Line Drivers
Active Filters
Available in 14-Pin Plastic DIP and Hermetic Cerdip,
12-Pin TO-8 Metal Can and 20-Pin LCC Packages and
in Chip Form
Chips and MIL-STD-883B Parts Available

Ne = NO CONNECT

NOTE: CAN TIED TO
NC = NO CONNECT

v+

LCC (E) Package

~

j

5 t;
ddl!!
, 2
NO,
17

+v,.

NC.
1& OUTPUT

PRODUCT DESCRIPTION
The AD841 is a member of the Analog Devices family of wide
bandwidth operational amplifiers. This high speedlhigh precision family includes, among others, the AD840, which is stable
at a gain of 10 or greater, and the AD842, which is stable at a
gain of two or greater and has 100 rnA minimum output current
drive. These devices are fabricated using Analog Devices' junction isolated complementary bipolar (CB) process. This process
permits a combination of de precision and wide band ac performance previously unobtainable in a monolithic op amp. In addition to its 40 MHz unity-gain bandwidth product, the AD841
offers extremely fast settling characteristics, typically settling to
within 0.01 % of final value in 110 ns for a 10 volt step.
Unlike many high frequency amplifiers, the AD841 requires no
external compensation. It remains stable over its full operating
temperature range. It also offers a low quiescent current of
12 rnA maximum, a minimum output current drive capablity of
50 rnA, a low input voltage noise of 13 nV/yHz and low input
offset voltage of I mV maximum.
The 300 ViliS slew rate of the AD841, along with its 40 MHz
gain bandwidth, ensures excellent performance in video and
pulse amplifier applications. This amplifier is well suited for use
in high frequency signal conditioning circuits and wide bandwidth active filters. The extremely rapid settling time of the

NC.

14NC

l!!

'i'

l!! l!!

l!!

Ne = NO CONNECT

AD841 makes it the preferred choice for data acquisition applications which require 12-bit accuracy. The AD841 is also appropriate for other applications such as high speed DAC and ADC
buffer amplifiers and other wide bandwidth circuitry.
APPLICATION HIGHLIGHTS
1. The high slew rate and fast settling time of the AD841 make
it ideal for DAC and ADC buffers, and all types of video
instrumentation circuitry.
2. The AD841 is a precision amplifier. It offers accuracy to
0.01% or better and wide bandwidth performance previously
available only in hybrids.
3. The AD841's thermally balanced layout and the speed of the
CB process allow the AD841 to settle to 0.01 % in 110 ns
without the long "tails" that occur with other fast op amps.
4. Laser wafer trimming reduces the input offset voltage to
1 mV max on the K grade, thus eliminating the need for
external offset nulling in many applications. Offset null pins
are provided for additional versatility.
5. The AD841 is an enhanced replacement for the HA2541.

REV. A

OPERA TIONAL AMPLIFIERS 2-73

•

AD841-SPECIFICATIONS

(@ +25°C and ±15 V dc, unless otherwise noted)
AD84IK

AD84IJ
Model

Conditions

Min

INPUT OFFSET VOLTAGE'

Typ

Max

0.8

Tmin-Tmax
Offset Drift

3.5

Input Offset Current

0.1

Tmin-Tmax

1.0

S

3.5

Typ

Max

Units

0.5

2.0
5.5

mV
mV
flVrc

S

flA

12

fl.A
fl.A
fl.A

3.3
35

0.4
0.5

0.1

200
2

VCM = :tIOV

INPUT VOLTAGE NOISE
Wideband Noise

f=lkHz
10 Hz to 10 MHz

OPEN-LOOP GAIN

Vo = :tIOV

Tmin-Tmax

RLOAD~500

n

Tmin-Tmax

Current

0.5

Min

35
5
6
0.2
0.3

3.5
0.1

0.4
0.6

Differential Mode

INPUT VOLTAGE RANGE
Common Mode
Common Mode Rejection

OUTPUT CHARACTERISTICS
Voltage

2.0
5.0

10

Tmin-Tmax

INPUT CHARACTERISTICS
Input Resistance
Input Capacitance

Max

35

INPUT BIAS CURRENT

ADS4IS

Typ

Min

RLOAD~500

:t 10
86
80

200
2
:t10
103
100

12
100
IS
47

25
12

:t10
S6
80

12
109
15
47

45

25
20

45

25
12

200
2

kn

12
100

V
dB
dB

IS
47

nV/y'Hz
flY rms

45

V/mV
V/mV

pF

n

Tmin-Tmax
VOUT = :t1O V

:t10
50

±IO
50

:t10
50

V
rnA

OUTPUT RESISTANCE

Open Loop

5

5

5

n

FREQUENCY RESPONSE
Unity Gain Bandwidth
Full Power Bandwidth'

V OUT = 90 mV p-p
Vo = 20 V p-p

40

40

40

MHz

4.7
10
10
300

MHz

RLOAD~500

Rise Time'
Overshoot3
Slew Rate'
Settling Time - 10 V Step

n

Av =-1
Av =-1
Av =-1
Av =-1
to 0.1%
to 0.01%

3.1

200

4.7
10
10
300

3.1

200

4.7
10
10
300

3.1

200

ns

%
V/flS

90
llO

90
llO

90
llO

ns

ns

OVERDRIVE RECOVERY

-Overdrive
+ Overdrive

200
700

200
700

200
700

ns
ns

DIFFERENTIAL GAIN
Differential Phase

f = 4.4 MHz
f = 4.4 MHz

0.03
0.022

0.03
0.022

0.03
0.022

%
Degree

POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
Power Supply Rejection Ratio

±15
:t5

II
Tmin-Tmax
Vs= ±5Vto±18V

Tmin-Tmax
TEMPERATURE RANGE
Rated Performance'
PACKAGE OPTIONS'
LCC (E-20A)·
Cerdip (Q-14)
Plastic (N-14)
TO-8 (H-l2)
J and S Grade Chips
Also Available

86
80

±15
:tIS
12
14

100

0

:t5

II
90
S6

+75

AD84lJQ
AD84lJN
AD84lJH

±15
:tIS
12
14

100

0

II
86
SO

+75

AD841KQ
AD841KN
AD841KH

:t5

-55

:tIS
i2
16

100

+125

V
V
mA
mA
dB
dB
°C

AD84ISE, AD841SEl883B
AD84ISQ, AD841SQ/883B
AD84ISH, AD841SHl883B

AD841JCHIP

AD841S CHIP

NOTES
1Input offset voltage specifications are guaranteed after 5 minutes at T A = + 25°C.
'Full power bandwidth = Slew Ratel2" VPEAK •
'Refer to Figure 19.
4"8" grade T min and T max specifications are tested with automatic test equipment at T A = -55°C and T A = + 125OC.
sPor outline information see Package Information section.
·Contact factory for availability.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units.
Specifications subject to change without notice.

2-74 OPERA TIONAL AMPLIFIERS

REV. A

AD841
ABSOLUTE MAXIMUM RATINGS '
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2
TO-8 (H) .
. ...... 1.4 W
Plastic (N) .
. ...... 1.5 W
. . . . . . . 1.3 W
Cerdip (Q) .
Input Voltage
. . . . . . . . ±Vs
Differential Input Voltage . . . . . . . . . . . . . . ...... ± 6 V
Storage Temperature Range
Q, H, E . . . . . . . . . . . . . . . . . . . . . . . -65°C to + 150°C
N . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C .to + 125°C
Junction Temperature . . . . . . . . . . . . . . . .
+ 175°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . + 300°C

NOTES
IStresses above those listed under UAbsolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only, and functional

operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not impl~ed. Exposure
to absolute maximum rating conditions for extended periods may affect
device reliability.
2 Maximum internal power dissipation is specified so that T J does not exceed
+ 175°C at an ambient temperature of +25OC.
Thermal Characteristics:
Cerdip Package
TO·8 Package
Plastic Package
LCC Package

alC

alA

3S'CIW
30'CIW
30'C/W
3S'CIW

\1O'CIW 38'CIW Recommended Heat Sink:
100'CIW 37'CIW Aavid Engineering "#602B
100'CIW
\SO'CIW

aSA

METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).

1"'4>------------ ~~~r -----------.j°l
.......- - - ,

BALANCE--,

+VS

0.067

11.71
OUTPUT

........._1...I...-_ _

REV. A

L

SUBSTRATE CONNECTED TO +Vs

-Vs

...J

OPERA TIONAL AMPLIFIERS 2-75

II

AD841---Typical Characteristics (at +Z5°C and Vs = ±15 V, unless otherwise noted.
20

20

0

t 2.
~

/

/
v.-/

V

V
/
o

o
o

5

10

15

20

/

/

V

/"

..~ ,
i

10

15

20

(

51\

4

/

f\.
O.

i-

V

«

V

.

~

/

130

E
I-

/

V

20

0
20
40
60
TEMPERATURE - ·C

120

~

"0

aili

100

~

Ir:

~

20

40

60

80

100 120 140

Figure 7. Quiescent Current vs.
Temperature

2-76 OPERA TIONAL AMPLIFIERS

1M

10M

100M

FREQUENCY - Hz

Figure 6. Output Impedance
VS. Frequency

~

90

~

80

60

40

V

0

CURRENT~~

20

0

20

40

.1 . . . .

~

70

TEMPERATURE _ "C

tOOk

'Ok

5

!"'- ~

/
0

r- I-"
,

~ + OUTPUT CURRENT

-OUTPUT

60

./

~

f'"

U

7
-20

100 120 140

1/

0

t:

/V
-60 -40

80

'40

I

0

40

,

Figure 5. Input Bias Current vs.
Temperature

Figure 4. Quiescent Current vs.
Supply Voltage

/

/

0.0
60

20

10
15
SUPPLY VOLTAGE - !;Volts

,

'Ok

Figure 3. Output Voltage Swing
VS. Load Resistance

.'\

3

4

100
lk
LOAD RESISTANCE - H

1/

"'- ~ r- l-

/

'0

'0

\

15

,/

o

..

4

o

/

,

6

-

lSV SUPPLIES

g~ ,0

Figure 2. Output Voltage Swing
vs. Supply Voltage

12

10

:!:

5

SUPPLY VOLTAGE - :!:Volts

Figure 1. Input Common-Mode
Range vs. Supply Voltage

j

0

I

§ •

o

SUPPLY VOLTAGE - ::!:Volts

V

60

"

80

f'.

100

120 140

V

/'

./

V

0

- 60

40

20

0

20

40

60

80

100 120 140

TEMPERATURE - "c

AMBIENT TEMPERATURE - "C

Figure 8. Short-Circuit Current
Limit vs. Temperature

/'

,/"

Figure 9. Gain Bandwidth Product
Temperature

VS.

REV. A

AD841
'0

o~

0

K--

~

~

0

~

4

~

20

'00

1
1k

'00

\
\

"

+60·

I

80

r-.. r'1+ sUPPlY

.!:,

\

\

"'" "~

Z

, .:ll'".

\

"0'

\

,

20

~

g

Rl = lkH
+25OC

'0

0

'\
20 '':-k...J...-'-U'O'f:k...J...-'-'':'OO:':-k...J...-'-':''M~L...J..J':':O'::M:-'-....LJ''::'.OOM

'OM

FREQUENCY - Hz

2

if
z

0

'"§

..

\.

:J

o
:I;

V

o

Vs = :!:15V

1\

>

-2

E

-4

:J

o

'"

0.1%

0.01%

\,

•
-B

100M

-'0 30

,/

/

V

\

i"""'" "--...........

40

50

60

........ ...........

70

80

90

100

110

SETTLING TIME - ns

Figure 15. Output Swing and
Error vs. Settling Time

Figure 14. Large Signal Frequency
Response

-70

0.1%

L
0.01%

\

FREQUENCY - Hz

Figure 13. Common-Mode
Rejection vs. Frequency

100M

./

~

\

.......-- V

V

~

r'\

15

10M

Figure 12. Power Supply Rejection
vs. Frequency

'0

25

1M

FREQUENCY - Hz

Figure 11. Open-Loop Gain vs.
Supply Voltage

~

500

I

-80

45 0

3VRMS
At = 'kill

25

!ND HARMONIC

-'00

M

0

-'20

-

-'30

'00

~

P.:;,

-

,I,

~

..

.1_

/

350

300

250

V
lk

10k

lOOk

fREQUENCY - Hz

200
-60

/

~,

V
./'
-40

/'

-20

~

0

>

15

5

/

20
40
60
TEMPERATURE - "C

20

~

//

-[::: JRD tRiOj'C

Figure 16. Harmonic Distortion vs.
Frequency

REV. A

>,

S

1\

I:!!

~ 400

-90

-11

1k

'00

30

'"~

I'

o

20

15

SUPPLY VOLTAGE - :tV

Figure 10. Open-Loop Gain and
Phase Margin vs. Frequency

II

40

Rt

90
10M

"

•

\

500JI LOAD

-20

,
+80'

""l\.

", 0

z

120

B

+100"

--

--- ---

~

,01-1-+++++ttlf-I-+++++HtH-+1*t-t+H
80

Figure 17. Slew Rate vs.
Temperature

100

120 140

~LO-L~'O~O-L~'+k-L~'O±k~U'~OO~k~~'~M~~'OM
fREQUENCY - Hz

Figure 18. Input Noise Voltage
Spectral Density

OPERA TIONAL AMPLIFIERS 2-77

AD841

HP3314A
FUNCTION
GENERATOR i-+-"iNIr-......
OR
EQUIVALENT

Figure 19a. Inverting Amplifier
Configuration (DIP Pinout)

Figure 19b. Inverter Large Signal
Pulse Response

Figure 19c. Inverter Small Signal
Pulse Response

R.
12011

HP3314A
FUNCTION
GENERATOR
OR
EQUIVALENT

1--_.JY'V'v---<

Figure 20a. Unity-Gain Buffer Amplifier
Configuration (DIP Pinout)

Figure 20b. Buffer Large Signal
Pulse Response

Figure 20c. Buffer Small Signal
Pulse Response

OFFSET NULLING

INPUT CONSIDERATIONS

The input offset voltage of the AD841 is very low for Ii high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 21 can be used.

An input resistor (R1N in Figure 20) is recommended in circuits
where the input to the AD841 will be subjected to transient or
continuous overload voltages exceeding the ±6 V maximum differentiallimit. This resistor provides protection for the input
transistors by limiting the maximum current that can be forced
into the input.
For high performance circuits it is recommended that a resistor
(RB in Figures 19 and 20) be used to reduce bias current errors
by matching the impedance at each input. The output voltage
error caused by the offset current is more than an order of magnitude less than the error present ·if the bias current error is not
removed.

Figure 21. Offset Nulling (DIP Pinout)

2-78 OPERATIONAL AMPLIFIERS

REV. A

Applying the AD841
AD841 SETTLING TIME
Figures 22 and 24 show the settling performance of the AD841
in the test circuit shown in Figure 23.
Settling time is defined as:
The interval of time from the application of an ideal step
function input until the closed-loop amplifier output has
entered and remains within a specified error band.
This definition encompasses the major components which comprise settling time. They include (I) propagation delay through
the amplifier; (2) slewing time to approach the final output
value; (3) the time of recovery from the overload associated with
slewing and (4) linear settling to within the specified error band.

associated with the overdrive recovery of the oscilloscope input
amplifier. The error amp gains the error from the false summing
junction by 10, and it contains a gain vernier to fme trim the
gain.
Figure 24 shows the "long term" stability of the settling characteristics of the AD841 output after a 10 V step. There is no evidence of settling tails after the initial transient recovery time.
The use of a junction isolated process, together with careful layout, avoids these problems by minimizing the effects of transistor isolation capacitance discharge and thermally induced shifts
in circuit operating points. These problems do not occur even
under high output current conditions.

t
I

•

-~t-t---j

OUTPUT
ERROR:
O.02%/DIV

OUTPUT
ERROR:
O.02%/DIV

OUTPUT:
5V/DIV

OUTPUT:
5V/DIV

Figure 22. AD847 0.07% Settling Time

Figure 24. AD847 Settling Demonstrating No Settling
Tails

Expressed in these terms, the measurement of settling time
is obviously a challenge and needs to be done accurately to
assure the user that the amplifier is worth consideration for the
application.

T••
7AU

T••

'60'

OSCILLOSCOPE

TE'

'1A18

GROUNDING AND BYPASSING
In designing practical circuits with the AD841, the user must
remember that whenever high frequencies are involved, some
special precautions are in order. Circuits must be built with
short interconnect leads. Large ground planes should be used
whenever possible to provide a low resistance, low inductance
circuit path, as well as minimizing the effects of high frequency
coupling. Sockets should be avoided because the increased interlead capacitance can degra.de bandwidth.
Feedback resistors should be of low enough value to assure that
the time constant formed with the circuit capacitances will not
limit the amplifier performance. Resistor values of less than
5 kn are recommended. If a larger resistor must be used, a
small « 10 pF) feedback capacitor in parallel with the feedbac.k
resistor, RF , may be used to compensate for these stray capacitances and optimize the dynamic performance of the amplifier in
the particular application.

49911

Figure 23. Settling Time Test Circuit

Measurement of the AD841's 0.01% settling in 110 ns was accomplished by amplifying the error signal from a false summing
junction with a very high speed proprietary hybrid error amplifier specially designed to enable testing of small settling errors.
The device under test was driving a 500 n load. The input to
the error amp is clamped in order to avoid possible problems

REV. A

Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. A 2.2 I1F capacitor in parallel
with a 0.1 I1F ceramic disk capacitor is recommended.
CAPACITIVE LOAD DRIVING ABILITY
Like all wideband amplifiers, the AD841 is sensitive to capacitive loading. The AD841 is designed to drive capacitive loads of
up to 20 pF without degradation of its rated performance. Capacitive loads of greater than 20 pF will decrease the dynamic
performance of the part although instability should not occur
unless the load exceeds 100 pF (for a unity-gain follower). A
resistor in series with the output can be used to decouple larger
capacitive loads.

OPERATIONAL AMPLIFIERS 2-79

2

AD841
Figure 25 shows a typical configuration for driving a large capacitive load. The 51 n output resistor effectively isolates the
high frequency feedback from the load and stabilizes the circuit.
Low frequency feedback is returned to the amplifier summing
junction via the low pass filter formed by the 51 n resistor and
the load capacitance, CL .

If termination is not used, cables appear as capacitive loads. If
this capacitive load is large, it should be decoupled from the
AD841 by a resistor in series with the output (see above:
Driving a Capacitive Load).

lkll

15pF

V OUT

V,N
INPUT

lkll

TERMINATION
RESISTOR
FOR INPUT
SIGNAL

RT = RBT = CABLE CHARACTERISTIC IMPEDANCE

Figure 26. Line Driver 'Configuration
Figure 25. Circuit for Driving a Large Capacitive Load

USING A HEAT SINK
The AD841 draws less quiescent power than most precision
high speed amplifiers and is specified for operation without a
heat sink. However, when driving low impedance loads, the current to the load can be 4 to 5 times the quiescent current. This
will create a noticeable temperature rise. Improved performance
can be achieved by using a small heat sink such as the Aavid
Engineering #602B.
TERMINATED LINE DRIVER
The AD841 functions very well as a high speed line driver of
either terminated or unterminated cables. Figure 26 shows the
AD841 driving a doubly terminated cable in a follower configuration. The AD841 maintains a typical slew rate of 300 V/fj-s,
which means it can drive a ±10 V, 4.7 MHz signal or a ±3 V,
15.9 MHz signal.
The termination resistor, R r , (when equal to the characteristic
impedance of the cable) minimizes reflections from the far end
of the cable. A back-termination resistor (ROT' also equal to the
characteristic impedance of the cable) may be placed between
the AD841 output and the cable in order to damp any stray signals caused by a mismatch between RT and the cable's characteristic impedance. This will result in a "cleaner" signal, but
since 112 the output voltage will be dropped across ROT' the op
amp must supply double the output signal required if there is
no back termination. Therefore the full power bandwidth is cut
in half.

OVERDRIVE RECOVERY
Figure 27 shows the overdrive recovery capability of the AD841.
Typical recovery time is 200 ns from negative overdrive and
700 ns from positive overdrive.

OVERDRIVEN
OUTPUT: l0V/DIV

INPUT SQUARE
WAVE: lV/DIV

Figure 27. Overdrive Recovery

HP33l4A
PULSE GENERATOR
OR EQUIVALENT
llJ.S ± lV SQUARE
WAVE INPUT

Figure 28. Overdrive Recovery Test Circuit

2-80 OPERA T10NAL AMPLIFIERS

REV. A

Wideband, High Output Current,
Fast Settling Op Amp
AD842 I

11IIIIIIII ANALOG
WDEVICES
FEATURES
AC PERFORMANCE
Gain Bandwidth Product: 80 MHz (Gain
2)
Fast Settling: 100 ns to 0.01% for a 10 V Step
Slew Rate: 375 V/fJ-s
Stable at Gains of 2 or Greater
Full Power Bandwidth: 6.0 MHz for 20 V p-p

=

CONNECTION DIAGRAMS
Plastic DIP (N) Package
and
Cerdip (Q) Package

LCC (E) Package

i i
~

DC PERFORMANCE
Input Offset Voltage: 1 mV max
Input.Offset Drift: 14 fJ-V/oC
Input Voltage Noise: 9 nV/YHz typ
Open-Loop Gain: 90 V/mV into a 500 n Load
Output Current: 100 rnA min
Quiescent Supply Current: 14 rnA max
APPLICATIONS
Line Drivers
DAC and ADC Buffers
Video and Pulse Amplifiers
Available in Plastic DIP Hermetic Metal Can,
Hermetic Cerdip and LCC Packages and in Chip Form
MIL-STD-883B Parts Available
PRODUCT DESCRIPTION
The AD842 is a member of the Analog Devices family of wide
bandwidth operational amplifiers. This family includes, among
others, the AD840 which is stable at a gain of 10 or greater and
the AD841 which is unity-gain stable. These devices are fabricated using Analog Devices' junction isolated complementary
bipolar (CB) process. This process permits a combination of dc
precision and wideband ac performance previously unobtainable
in a monolithic op amp. In addition to its 80 MHz gain bandwidth, the AD842 offers extremely fast settling characteristics,
typically settling to within 0.01 % of fmaI value in less than
100 ns for a 10 volt step.
The AD842 also offers a low quiescent current of 13 rnA, a high
output current drive capability (100 rnA minimum), a low input
voltage noise of 9 nVv'Hz and a low input offset voltage (1 mV
maximum).
The 375 V/jJ.s slew rate of the AD842, along with its 80 MHz
gain bandwidth, ensures excellent performance in video and
pulse amplifier applications. This amplifier is ideally suited for
use in high frequency signal conditioning circuits and wide
bandwidth active ftIters. The extremely rapid settling time of
the AD842 makes this amplifier the preferred choice for data
acquisition applications which require 12-bit accuracy. The
AD842 is also appropriate for other applications such as high
speed DAC and ADC buffer amplifiers and other wide bandwidth circuitry.

REV. A

~

(5

~

~

0

~

3212019

,. NC

17

+v.

•

16 Ne
15 OUTPUT

'4 Ne
9

~
NC "" NO CONNECT

10 "

:f

12

13

~ ~ ~

He "" NO CONNECT

TO-S (H)
Package
NC

-INPUT

OUTPUT

NC
TOP VIEW
NOTE: CAN TIED TO V+
Ne '" NO CONNECT

APPLICATION mGHLIGHTS
I. The high slew rate and fast settling time of the AD842 make
it ideal for DAC and ADC buffers amplifiers, lines drivers
and all types of video instrumentation circuitry.
2. The AD842 is a precision amplifier. It offers accuracy to
0.01% or better and wide bandwidth; performance previously
available only in hybrids.
3. Laser-wafer trimming reduces the input offset voltage of
I m V max, thus eliminating the need for external offset nulling in many applications.
4. Full differential inputs provide outstanding performance in
all standard high frequency op amp applications where the
circuit gain will be 2 or greater.
5. The AD842 is an enhanced replacement for the HA2542.

OPERA TIONAL AMPLIFIERS 2-81

AD842-SPECIFICATIONS(@ +25°C and ±15 V dc, unless otherwise noted)'
Moci~1

.'.

Conditions

Min

INPUT OFFSET VOLTAGE'

AD842J
Typ
Max
0.5

T_-T"""
Offset Drift

4.2

Tmin-Tmax
Input Offset Current

0.1

Tmin-Tmax

INPUT VOLTAGE RANGE
Common Mode
Common-Mode Rejection

Differential Mode

VCM = ±IOV
Tmin-Tmu:

INPUT VOLTAGE NOISE
Wideband Noise

f=lkHz
10 Hz to 10 MHz

OPEN-LOOP GAIN

Vo = ±IOV
R LoAD2500 !l
Tmin-Tmax

OUTPUT CHARACTERISTICS
Voltage
Current
FREQUENCY RESPONSE
Gain Bandwidth Product
Full Power Bandwidth2
Rise Time'
Overshoot'
Slew Rate'
Settling Time'

Differential Gain
Differential Phase

R LoAD 2500 !l
VoUT=±IOV
OPen Loop
VOUT = 90 mV
Vo=20Vp-p
RLOAD2500 !l
AVCL = -2
AVCL = -2
AVCL = -2
10V Step
to 0.1%
to 0.01%
f = 4.4 MHz
f = 4.4 MHz

POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
Power Supply Rejection Ratio

0.3

S
10
0.4
0.5

3.5
0.05

±10
90
86

115

50
25

± 10
100

4.7

300

S
12
0.4
0.6

,.A
,.A
,.A
,.A

14

0.1

±10
86
80

115

40

90

,.vrc

100
2.0

kO
pF

115

V
dB
dB

9
28

nVlv'Hz
,.Vrms

90

VlmV
V/mV

20
:1:10
100

V

rnA
5

!l

80

80

80

MHz

6
10
20
375

MHz
ns
%

80
100
0.015
0.035

ns
ns
%
Degree

6
10
20
375

13

PACKAGE OPTIONS'
Plastic (N-14)
Cerdip (Q-14)
TO-8 (H-I2A)
LCC· (E-20A)
J and S Grade Chips
Also Available

mV
mV

5

4.7

300

±5
13

90
86

+75
AD842JN
AD842JQ
AD842JH

4.7

300

±15
±lS
14
16

100

0

6
10
20
375
80
100
0.015
0.035

±15

TEMPERATURE RANGE
Rated Performance'

4.2

Units

1.5
3.5

5

80
100
0.015
0.Q35

86
80

5
6
0.2
0.3

±10
100

±5
Tmin-Tmax
Vs =±5Vto±15V
Tmin-Tmax

0.5

9
28

90

AD842S
Typ
Max

1.0
1.5

100
2.0

9
28

40
20

.',

Min

14

100
2.0
± 10
86
80

AD842K
Typ
Max

1.5
2.5

14

INPUT BIAS CURRENT

INPUT CHARACTERISTICS
Input Resistance
Input Capacitance

Min

±15
±18
14
16

lOS

0

±5
13

86
80

+75
AD842KN
AD842KQ
AD842KH

V/,.s

-55

±lS
14
19

100

V
V

rnA
rnA
dB
dB

+125

°C

AD842SQ, AD842SQ/883B
ADg42SH
AD842SE

NOTES
'Input offset voltage specifications are guaranteed after 5 minutes at TA ;" +250(;.
2FPBW Slew Rateli" VPEAK '
'Refer to Figures 22 and 23.
'''S'' grade Tmin and T_ specifications are tested with automatic test equipment at TA = -55°C and TA = +1250(;.
5Por outline information see Package Information section.
·Contact factory for availability.
AU min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Results from
those tests are used to calculate outgoing quality levels.
Specifications subject to change without notice.

2-82 OPERATIONAL AMPLIFIERS

REV. A

AD842
ABSOLUTE MAXIMUM RATINGS'
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2
Plastic (N) . . . . . . . . . . . . . . . . . . . .
1.5 W
Cerdip (Q) . . . . . . . . . . . . . . . . . . . .
I.IW
TO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . l.3W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±Vs
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . ±6 V
Storage Temperature Range
Q, H . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to + 150°C
N . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to + 125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . + 175°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . +300°C
NOTE
lStresses above those listed under "Absolute Maximum Ratings" may cause
pennanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated
in the operational section of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
2Maximum internal power dissipation is specified so that TJ does not exceed
+ l50"C at an ambient temperature of +25"C.
Thermal Characteristics:
Plastic Package
Cerdip Package
TO-S Package

SIC

aJA

eSA

30°C/W
30°C/W
30°C/W

IOO°C/W
11 O"C/W
lOO"ClW

3SoC/W
27°C/W

METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
14.-------0.,0612.681

-------.1"

1
BALANCE

~r

,
v+

BALANCE

I

-VIN

1

0.067

1'.691

OUTPUT

SUBSTRATE CONNECTED
TO+Vs

Recommended heat sink: Aavid Engineering<> #602B

REV. A

OPERA TIONAL AMPLIFIERS 2-83

•

AD842 - Typical Characteristics (at +25°C and Vs = ±15 V, unless otherwise noted.)
20

20

0

.l!

~ 1S

/

o

/
o

V
V
10

0

:v

v.. /

/

•

"

LV

I

15

20

5

/

/

I/:!: 15V SUPPLIES

/

0

II

/
o

o

o

5

10

15

10

20

100

Figure 7. Input Common-Mode
Range VS. Supply Voltage

Figure 2. Output Voltage Swing
Supply Voltage

10k

Figure 3. Output Voltage Swing
VS. Load Resistance

VS.

,.

lk

LOAD RESISTANCE - 1l

SUPPLY VOLTAGE - :!:Volts

SUPPLY VOLTAGE - '!"Volts

'00

-5

/

\

1&

V

i'-.

./

12

~

I

""- ......

I

V

10

-2
15
10
SUPPLY VOLTAGE - :!:Volts

Figure 4. Quiescent Current
Supply Voltage

20

-60

- 40 - 20

/

1

1/

o. 1

/

--

0.01
0

20

40

60

80

100 120 '40

1M

100k

10k

TEMPERATURE _ °C

10M

100M

FREQUENCY - Hz

Figure 5. Input Bias Current
Temperature

VS.

,.

Figure 6. Output Impedance
Frequency

VS.

VS.

••

300

/

17

~

,.

V

"E, 15

V

~
114

a

!! "

/

M
:3 12
o

11

=,

\

,.

/

0

1'-':

-c~~~:~; r'::

/

•

I" t'--

V

10
-60 -40 -20

20 40
60
TEMPERATURE - -c

80

100 120 140

~ i'..

Figure 7. Quiescent Current
Temperature

20

40

"-

60

80

100

120 140

AMBIENT TEMPERATURE _ °C

VS.

2-84 OPERA T10NAL AMPLIFIERS

1\

\

"i'
0

1\

70

~

100
-60 -40 -20

V

\

125

..... v

.- v

~OUTPUT CURRENT

Figure 8. Short-Circuit Current
Limit VS. Temperature

as
-60 -40 -20

0

20 40 10 80
TEMPERATURE - "C

100 120 140

Figure 9. Gain Bandwidth Product
VS. Temperature

REV. A

AD842
120

\ -- r-- -- -

100

.....

100

,

~60

soon LOAD
1

o
100

10k

1k

TOOk

/"

I

I

'"

2

I

I

N

10M

1M

~

I--

I

20

Z 80

-

I

"'-

o

/

~20

15

100

20

10

. / fo-

5

VCM = TV pop
,+25-':

/

\

0

\

r'-,

0

40

10k

lOOk

10M

1M

'"

10M

100M

FREQUENCY _ Hz

\

/'

•
100M

".V

V

,/

0.01%

-10
3D

0.01'"

\
[\.

""."""'-"

40

50

10

70

f'... 10

80

550

v

500

'l!,

r:~

1\

LD HARMON''Y ~

0

1\

/

_I-"

JRD rRM;'

- +11
10'

100.

FREQUENCY - Hz

Figure 16. Harmonic Distortion
Frequency

/

//

-130

1k

VV

450

lJ".

~

o
~ -120

110

Figure 15. Output Swing and
Error vs. Settling Time

-go

40

100

SETTUNO TIME - ns

..
3VRMS
Rl = lk~l

100M

/

\

-8

Figure 14. Large Signal Frequency
Response

-00

REV. A

.1%

fREQUENCY - Hz

Figure 13. Common-Mode
Rejection VS. Frequency

-140
100

0.1%

2

5

~

10M

0

5

60

/

2

RL = TkO
+25-':
Vs = ±15V

1\

r....,

lOOk
1M
FREQUENCY _ Hz

Figure 12. Power Supply Rejection
vs. Frequency

VS.

Vs = :!:15V

'"

10k

1k

~v

30

100

I~

o
10

Figure 11. Open-Loop Gain
Supply Voltage

IIII I

l~~

i

SUPPLY VOlTAGE-

120

V

.~

L

500.0 LOAD

o

Figure 10. Open-Loop Gain and
Phase Margin vs. Frequency

I\::su,"

-5

i:!60

90
100M

FREQUENCY - Hz

r'-

~

'l,!

\

~~40

I-----

100

\

"",-

a

120

00

"~

~80
Z

110

VS.

1\
10

10

300

100

"

10k

TOOle

1M

fREQUENCY - Hz

Figure 17. Input Voltage
Frequency

VS.

10M

...

V
/

V

-60 -40 -20

20 40
60 80 100 120 140
TEMPERATURE - ·c

Figure 18. Slew Rate
Temperature

VS.

OPERA TIONAL AMPLIFIERS 2-85

•

AD842

Figure 19a. Inverting Amplifier
Configuration (DIP Pinout)

R1

=

205n

Rf

'"

Figure 19b. Inverter Large Signal
Pulse Response

Figure 19c. Inverter Small Signal
Pulse Response

20SU

HP3314A

FUNCTION
GENERATOR
OR
EQUIVALENT

I--"'....."'Wv--{

Figure 20a. Noninverting Amplifier
Configuration (DIP Pinout)

Figure 20b. Noninverting Large Signal
Pulse Response

Figure 20c. Noni;1Verting Small
Signal Pulse Response

OFFSET NULLING
The input offset voltage of the AD842 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 21 can be used.

Figure .21. Offset Nulling
(DIP Pinout)

2-86 OPERATIONAL AMPLIFIERS

REV. A

Applying the AD842
AD842 SETTLING TIME
Figures 22 and 24 show the settling performance of the AD842
in the test circuit shown in Figure 23.

OUTPUT:
IOV/DIV

Settling time is defined as:
The interval of time from the application of an ideal step
function input until the closed-loop amplifier output has
entered and remains within a specified error band.
This definition encompasses the major components which comprise settling time. They include: (I) propagation delay through
the amplifier; (2) slewing time to approach the final output
value; (3) the time of recovery from the overload associated with
slewing; and (4) linear settling to within the specified error
band.

OUTPUT
ERROR:

O.02"I0/DIV

Figure 22. AD842 0.01% Settling Time

Expressed in these terms, the measurement of settling time
is obviously a challenge and needs to be done accurately to
assure the user that the amplifier is worth consideration for the
application.
TEK
7A13

TEK

1603
OSCILLOSCOPE
TEK

7A18

4990

0005109
FlAT·TOP

4990

1kn

PULSE GENERATOR

FET PROBE

}---+~ TEK P6201
499U

Figure 23. Settling Time Test Circuit

Figure 23 shows how measurement of the AD842's 0.01% settling in 100 ns was accomplished by amplifying the error signal
from a false summing junction with a very high-speed proprietary hybrid error amplifier specially designed to enable testing
of small settling errors. The device under test was driving a
300 n load. The input to the error amp is clamped in order to
avoid possible problems associated with the overdrive recovery
of the oscilloscope input amplifier. The error amp gains the
error from the false summing junction by 15, and it contains a
gain vernier to fine trim the gain.
Figure 24 shows the "long term" stability of the settling characteristics of the AD842 output after a 10 V step. There is no evidence of settling tails after the initial transient recovery time.
The use of a junction isolated process, together with careful layout, avoids these problems by minimizing the effects of transistor isolation capacitance discharge and thermally induced shifts
in circuit operating points. These problems do not occur even
under high output current conditions.
GROUNDING AND BYPASSING
In designing practical circuits with the AD842, the user must
remember that whenever high frequencies are involved, some

REV. A

OUTPUT:
5V/DIV

OUTPUT
ERROR:

O.01"lo/DIV

Figure 24. AD842 Settling Demonstrating No Settling
Tails

special precautions are in order. Circuits must be built with
short interconnect leads. Large ground planes should be used
whenever possible to provide a low resistance, low inductance
circuit path, as well as minimizing the effects of high frequency
coupling. Sockets should be avoided because the increased interlead capacitance can degrade bandwidth.
OPERA TIONAL AMPLIFIERS 2-87

II

AD842
Feedback resistors should be of low enough value to assure that
the time constant formed .with the. circuit capacitances will not
limit the amplifier performance. Resistor values of less than
5 kG are recommended. If a larger resistor must be used, a
small «10 pF) feedback capacitor connected in parallel with the
feedback resistor, R F , may be used to compensate for these
stray capacitances and optimize the dynamic performance of the
amplifier in the particular application.

RT

CHARACTERISTIC
IMPEDANCE

SOH OR 7Sfl CABLE

Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. A 2.2 ,...F capacitor in parallel
with a 0.1 ,...F ceramic disk capacitbr is recommended.
CAPACITIVE LOAD DRMNG ABILITY
Like all wideband amplifiers, the AD842 is sensitive to capacitive loading. The AD842 is designed to drive capacitive loads
of up to 20 pF without degradation of its rated performance.
Capacitive loads of greater than 20 pF will decrease the dynamic
performance of the part although instability should not occur
unless the load exceeds 100 pF.
USING A HEAT SINK
The AD842 draws less quiescent power than most precision
high speed amplifiers and is specified for operation without a
heat sink. However, when driving low impedance loads, the current to the load can be 10 times the quiescent current. This will
create a noticeable temperature rise. Improved performance can
be achieved by using a small heat sink such as the Aavid Engineering #602B.

R2

Figure 25. Line Driver Configuration

OVERDRIVE RECOVERY
Figure 26 shows the overdrive recovery capability of the AD842.
Typical recovery time is 80 ns from negative overdrive and
400 ns from positive overdrive.

OVERDRIVEN OUTPUT,
10VIDIVISION

TERMINATED LINE DRIVER
The AD842 is optimized for high speed line driver applications.
Figure 25 shows the AD842 driving a doubly terminated cable
in a gain-of-2 follower configuration. The AD842 maintains a
typical slew rate of 375 VII's, which means it can drive a
±IO V, 6.0 MHz signal or a ±3 V, 19.9 MHz signal.
The termination resistor, RT, (when equal to the characteristic
impedance of the cable) minimizes reflections from the far end
of the cable. A back-termination resistor (RBT> also equal to the
characteristic impedance of the cable) may be placed between
the AD842 output and the cable in order to damp any stray signals caused by a mismatch between RT and the cable's characteristic impedance. This will result in a "cleaner" signal. With
this circuit, the voltage on the line equals VIN because one half
of VOUT is dropped across R BT •

INPUT SQUARE WAVE,
1VIDIVISION

TIME: 100ns/DIVISION

Figure 26. Overdrive Recovery

The AD842 has ±100 mA minimum output current and, therefore, can drive ±5 V into a 50 G cable.

HP3314A

PULSE GENERATOR

The feedback resistors, Rl and R z, must be chosen carefully.
Large value resistors are desirable in order. to limit the amount
of current drawn from the amplifier output. But large resistors
can cause amplifier instability because the parallel resistance
R1IIRz combines with the input capacitance (typically 2-5 pF) to
create an additional pole. Also, the voltage noise of the AD842
is equivalent to a 5 kG resistor, so large resistors can significantly increase the system noise. Resistor values of 1 kG or
2 kG are recommended.

= RaT = CABLE

OUTPUT

OR EQUIVALENT

lkU
1",5,

:!:

lV SQUARE

WAVE INPUT

Figure 27. Overdrive Recovery Test Circuit

If termination is not used, cables appear as capacitive loads and
can be decoupled from the AD842 by a resistor in series with
the output.

2-88 OPERA TlONAL AMPLIFIERS

REV. A

34 MHz, CBFET
Fast Settling Op Amp
AD843 I

11IIIIIIII ANALOG
WDEVICES
FEATURES
AC PERFORMANCE
Unity Gain Bandwidth: 34 MHz
Fast Settling: 135 ns to 0.01%
Slew Rate: 250 V I ILS
Stable at Gains of 1 or Greater
Full Power Bandwidth: 3.9 MHz
DC PERFORMANCE
Input Offset Voltage: 1 mV max (AD843K/B)
Input Bias Current: 0.6 nA typ
Input Voltage Noise: 19 nV/v'Hz
Open Loop Gain: 30 V/mV into a 500.n Load
Output Current: 50 mA min
Supply Current: 13 mA max
Available in 8-Pin Plastic Mini-DIP 8. Cerdip Packages.
20-Pin LCC and 12-Pin Hermetic Metal Cans
Chips and MIL-STD-883B Parts Also Available
APPLICATIONS
High Speed Sample-and-Hold Amplifiers
High Bandwidth Active Filters
High Speed Integrators
High Frequency Signal Conditioning

CONNECTION DIAGRAMS
Plastic (N) and
Cerdip (Q) Package

16-Pin SOIC Package

Ne "" NO CONNECT

LCC (E) Package
::j

::j

NC '" NO CONNECT

"Iiiz Iii"z
"z3 ~2 "z, 2.~

TO-S (H) Package

0

TOP VIEW

,.
~

11
11
LJ

NC 4

18 NC

-IN 5

17 +Vs

NC 6

16 NC

+IN 7

15 OUTPUT

NC.

14 Ne

PRODUCT DESCRIPTION
The AD843 is a fast settling, 34 MHz, CBFET input op amp.
The AD843 combines the low (0.6 nA) input bias currents char·
acteristic of a FET input amplifier while still providing a
34 MHz bandwidth and a 13S ns settling time (to within 0.01%
of final value for a 10 volt step). The AD843 is a member of the
Analog Devices' family of wide bandwidth operational amplifiers. These devices are fabricated using Analog Devices' junction
isolated complementary bipolar (CB) process. This process permits a combination of dc precision and wideband ac perform·
ance previously unobtainable in a monolithic op amp.
The 2S0 V/fJ-s slew rate and 0.6 nA input bias current of the
AD843 ensure excellent performance in high speed sample-andhold applications and in high speed integrators. This amplifier is
also ideally suited for high bandwidth active filters and high fre·
quency signal conditioning circuits.
Unlike many high frequency amplifiers, the AD843 requires no
external compensation and it remains stable over its full operating temperature range. It is available in five performance grades:
the AD843J and AD843K are rated over the commercial tempera·
ture range of O°C to + 70°C. The AD843A and AD843B are rated
over the industrial temperature range of -40°C to +8S°C. The
AD843S is rated over the military temperature range of - SSOC
to + 12SoC and is available processed to MIL-STD-883B, Rev. C.

+IN

NOTE: CAN TIED TO V+

9

10 11

~

f

12

13

~ 12l l2l

NC = NO CONNECT

NC '" NO CONNECT

PRODUCT HIGHLIGHTS
I. The high slew rate, fast settling time and low input bias

current of the AD843 make it the ideal amplifier for 12-bit
D/A and AID buffers, for high speed sample-and-hold amplifiers and for high speed integrator circuits. The AD843
can replace many FET input hybrid amplifiers such as the
LH0032, LH4104 and OPA600.
2. Fully differential inputs provide outstanding performance in
all standard high frequency op amp applications such as signal conditioning and active filters.
3. Laser wafer trimming reduces the input offset voltage to
I mV max (AD843K and AD843B).
4. Although external offset nulling is unnecessary in many
applications, offset null pins are provided.
S. The AD843 does not require external compensation at closed
loop gains 'of 1 or greater.

The AD843 is offered in either 8-pin plastic DIP or hermetic
cerdip packages, in 16-pin SOIC, or in a 12-pin metal can.
Chips are also available.

REV. A

OPERA TlONAL AMPLIFIERS 2-89

II

AD843 -SPECIFICATIONS
Model

Conditions

(@ TA +25°C and ±15 V dc, unless otherwise noted)

Min

1.0
1.7
12

INPUT OFFSET VOLTAGE '
Tmin-T ....
Offset Drift
INPUT BIAS CURRENT

INPUT OFFSET CURRENT

AD843J/A
Typ
Max

Initial (TJ = +25'<:)
Warmed-Up 1
Tmin-T _

50
0.8

Initial (TJ - + 25°C)
Warmed-Upl
Tmin-Tmax

30
0.25

Min

2.0
4.0

2.5
601160

60
60

AD843S
Typ

1.0
2.0
35

1.0
3.0
12

40
0.6

1.0

50
0.8

23/65
20
0.2

1.0

30
0.25

0.4

9126
10'0
6

1010
6
±10

Min

0.5
1.2
12

23/64

INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
INPUT VOLTAGE RANGE
Common Mode

AD843KIB
Typ
Max

+12,
-13

±10

72
72

70
68

+12,

Units
mV
mV
fLVI'C

2.5
2600

nA

pA

nA
pA

1.0
1025

nA
nA

1010
6

0
pF

±10

+12,
-13

V

60
60

72
72

dB
dB

19
60

nVIv'Hz
fLV-rms

-13
76
76

Max
2.0
4.5

COMMON MODE REJECTION

VCM = ±IOV
Tmin-Tmax

INPUT VOLTAGE NOISE
Wideband Noise

f = 10 kHz
10 Hz to 10 MHz

OPEN LOOP GAIN

Vo = ±IOV
R LOAD ,,=5000
Tmin-Tmax

15
10

25
20

20
10

30
25

15
10

30
25

V/mV
V/mV

R LOAD ,,=500 0

±10

+1l.5,
-12.6

±10

+1l.5,
-12.6

±10

+ 1l.5,
-12.6

V

VOUT = ±IOV
Open Loop

50

OUTPUT CHARACTERISTICS
Voltage
Current
Output Resistance
FREQUENCY RESPONSE
Unity Gain Bandwidth
Full Power Bandwidth2
Rise Time
Overshoot
Slew Rate
Settling Time

Overdrive Recovery
Differential Gain
Differential Phase

VOUT = 90 mV p-p
Vo = 20 Vp-p
Rk5000
AYCL = -I
AYCL = -I
AYCL = -I
10 V Step
AyCL = -I
to 0.1%
to 0.01%
-Overdrive
+ Overdrive
f= 4.4 MHz
f = 4.4 MHz

POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
Rejection Ratio
Rejection Ratio

19
60

2.5

160

19
60

50
12

12

0

34

34

34

MHz

3.9
10
15
250

MHz
ns
%
V/fLS

ns
ns
ns
ns
%
Degree

3.9
10
15
250

2.5

160

Tmin-Tmax

TEMPERATURE RANGE
Operating, Rated Performance
Commercial (0 to + 700C)
Industrial (- 40'<: to + 85°C)
Military ( - WC to + 125'<:)'
PACKAGE OPTIONS'
Plastic (N)
Cerdip (Q)
Metal Can (H)
LCC(E)'
SOIC (R)

2-90 OPERATIONAL AMPLIFIERS

2.5

160

95

95

135

135

135

200
700
0.025
0.025

200
700
0.025
0.025

200
700
0.025
0.025

±15

±15

65
62

3.9
10
15
250

95

±4.5
Tmin-Tmax
±5 V to ±18 V

rnA

50

12

12
12.3
76
76

AD843J
AD843A

±18
13
14

±4.5

70
68

12
12.3 .
80
80

±15
±18
13
14

±4.5

65
62

12
12.5
76
76

±18
13
16

V
V
rnA

rnA
dB
dB

AD843K
AD843B
AD843S

AD843JN
AD843AQ

AD843KN
AD843BQ
AD843BH

AD843SQ, AD843SQ/883B
AD843SH
AD843SE, AD843SEl883B

AD843JR

REV. A

AD843
NOTES
ISpecifications are guaranteed after 5 minutes at T A = + 25°C.
'Full power bandwidth ~ Slew Ratel2 TrV peak.
3All "S" grade T min-T max specifications are tested with automatic test equipment at T A = -55°C and T A = + 125°C.
4For outline information see Package Information section.
SContact factory for availability.
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels.
All min and max specifications are guaranteed although only those shown in boldface are tested on all production units.

ABSOLUTE MAXIMUM RATINGS'
Supply Voltage . . . . . . . . . . . . . . . . .
. .. ± IS V
Internal Power Dissipation2
Plastic Package . . . . . .
1.50 Watts
1.35 Watts
Cerdip Package. . . . . . .
I.S0 Watts
12-Pin Header Package. .
20-Pin LCC Package . . . . . . . . . . . . . . . . . . . . 1.0 Watt
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± Vs
Output Short Circuit Duration . . . . . . . . . . . .... Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . +Vs and -Vs
Storage Temperature Range (N, R) .
-65°C to + 150°C
Storage Temperature Range (Q, H) . . . . . . . -65°C to + 125°C
Operating Temperature Range
ADS43J/K . . . . . . . . . . . . . . . . . . . . . . . . . 0 to + 70°C
ADS43NB . . . . . . . . . . . . . . . . . . . . . . -40°C to +S5°C
AD843S . . . . . . . . . . . . . . . . . . . . . . . - 55°C to + 125°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C

NOTES
IStresses above those listed under "Absolute Maximum Ratings" may cause
pennanent damage to the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
28-Pin Plastic Package: aJA = lOO°ClWatt
8-Pin Cerdip Package: 6JA ~ IlO°ClWatt
12-Pin Header Package: BJA ~ 80°ClWatt
20-Pin LCC Package: QJA ~ ISO°ClWatt

METALIZA TION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (nun).

Vs

0.067

"r

REV.A

4

OPERATIONAL AMPLIFIERS 2-91

•

AD843 - Typical Characteristics

.

20

11 '5
~

,

IIIz
:!
III

!,

V

'0

g

I

./

i

V

TA =+25OC

,0
SUPPLY VOLTAGE -

V
o

zo

15
~

'5

II '0

V

'"g

!:i

30

V

/
V

/

II

:t15VSUPPLlE8

..........

/

TA = +25"C

j

o

,.

'0

20

~

o

Figure 1. Input Voltage Range
Supply Voltage

LOAD RESISTANCE -

Figure 2. Output Voltage Swing
vs. Supply Voltage

VS.

1k

'00

'0

SUPPLY VOLTAGE-::!: Volts

Volts

17'

'Ok

n

Figure 3. Output Voltage Swing
vs. Load Resistance

'00

15

-f--

VCM=O

Iof

!,

'"E '2

,

10
10- 1

!

I

..il •
z

i
~

I" .

'0-'

'0-"11_

Iof

0.'

AVCL = +1

10-"

•

10- 12
0

'0
SUPPLY VOLTAGE -

%.

Figure 4. Quiescent Current
Supply Voltage

11
I

\

1.0

1
U

i..
Ii!

0.8

'30

0.•

l!
0.4

0.2
-15

-10

,

1120

,

t: 110

~

+20 +40 +80 +80 +100 +120 +140

'Ok

100k

1M
FREQUENCV - Hz

""

-5
10
COMMON MODE VOLTAGE - Volts

Figure -7. Input Bias Current vs.
Common Mode Voltage

2-92 OPERA TIONAL AMPLIFIERS

''\

"

~

..... ~

i '00
u

90

+OUTPUT
CURRENT

t:

K eo
~:I:

on

~
ro-...

Ie

::l

I,

-OUTPUT
CURRENT

~ .......

~

10

so

..... r-..,

I,

I'\.
.......

50
15

-so

100M

~

~

T,.. = +25"C
WI....OUT
HEATStNK

10M

Figure 6. Output Impedance vs.
Frequency

Figure 5. Input Bias Current vs.
Junction Temperature

VS.

'40

\

U

JUNCTION TEMPERATURE _·C

1.4

'.2

oJ

0.01

-80 -40 -20

20

'5
Volts

-40

-20

0

+20 +40 +60 +80 +100 +120 +140

JUNCTION TEMPERATURE -

oc

Figure 8. Short Circuit Current
Limit vs. Junction Temperature (T)

25L--L~L--L

-60 -40

-20

0

__L--L__L--L__L--L~
+20 +40 +60 +80 +100 +120 +140

TEMPERATURE -

·c

Figure 9. Gain Bandwidth Product
vs. Temperature

REV. A

Typical Characteristics -AD843
'00

..

"0

92

'00
PHASE

IITT

.0

II j I

flloo
,

GAIN

~
....
§

"
Z

\

iii

1\
RI.""5OQfl

~20

,.

-20

'00

:1i

:I!

..
v,

88

~

20

i!;

IE

.,

100M

fII,

z

0

!
~

0

:I!

z

0

:I!
:I!

8

..

Vs

::

~

Vo "" Vs - 4V

~

•

= ::t;15V

,.

~

g~

I

5

~

o

::

~

,

+0

i

~

10

~
........

100M

lOOk

1M

10M

4

V-

Figure 13. Common Mode
Rejection vs. Frequency

10M

100M

SEE FIGURE 21

0.01%

0.1%

ERROR

0
0.01%

0.1%

-2

1\
\

\
\

-6
-B

.......

-1.
100M

~

I

60

10

"'-

80

FREQUENCY - Hz

FREQUENCY - Hz

,M

lOOk

-

V

I
I

... -4

~

10M

6

>
o
:;

~

20

1M

10k

~

~

+1

.\

5

100k

1JIlJW
,. 1

'00

Figure 12. Power Supply
Rejection vs. Frequency

''''' 500n
Vs = ±lSV
TA "" +25 ac

",

15

II

~

SINE WAVE APPLIED

FREQUENCY - Hz

AvcL

20

+SUPPlY

Vs= :!;15V
WITH 1V p-p

,.

~

r-.

-IS~IY

40

•

2.

15

:!: 25

so

10k

r-.

SUPPLY VOLTAGE - ~ Volts

I

~~

,.

.

I 2.

35

TA = +25'"C

'00

.0

t

ii:

lVp-p

.

~

= SOOU

Figure 11. Open Loop Gain vs.
Supply Voltage

IIII I

YCM

Z

0
RL

'00

'"

Figure 10. Open Loop Gain and
Phase Margin vs. Frequency

'00

~

v

~

-20

'20

/'

.,

84

10M

100k
1M
'Ok
FREQUENCY - Hz

/

~ 9

"

Z

oo

.. ,
.. " .
ir

\

f'..
90

r-- ....,..,
100

110

120

130

140

SETTLING TIME - ns

Figure 14. Large Signal Frequency
Response

Figure 15. Output Swing and
Error vs. Settling Time

'0.
2B.
-OOr-t--rrHr-t-~HH--r-~~--~-rH

VOUT "" 1.5V rms

I

~

-110

1-t--rrHr-t--,"'-=r'nOOfi--'--rl~-:;;o~-rH

-120

t:t:t~~t::t:~=!=+l~--~~

-, ••

1-t--rrHl-+-~HH--t-~~--~-rH

-140

'-~...J...u..'--'--'-J...U'-'-.J...J...LI._..w

ro

~

~

~

FREQUENCY - Hz

Figure 16. Harmonic Distortion vs.
Frequency

REV. A

'OOk

w

2"

~

220

~

i-""'"

........

-~

~ 260

~>
,

fII -'D. 1-t--rrHr-t--'-LJ.J--L--'-j~--~-tI'I

AVCL -

1

200

AVCI..= +1

"~D.J....L..U,OO~...J..U,.....-'-L..U,.......J....u.a.'oow.
• ...l.J..' ....
M.J....I..W
,OM
FREQUENCY - Hz

Figure 17. Input Noise Voltage Spectral
Density

18~60

I I
-40 -20

0

+20

+40 +60 +80 +100+120 +140

TEMPERATURE - OC

Figure 18. Slew Rate vs.
Temperature

OPERA TIONAL AMPLIFIERS 2-93

AD843
95

II

9.

L

~Vs=:t:15V

VO'''''/J ~O~ !.ov

85
I

~

i!;

g
z

~

0

SO

,.
.

L'
/

INPUT

I

4UkCI

j

6.
55

V

SQUARE
WAVE

Va= ;!:5V
Vo= ±1V

:1

"

--.n
_
- U-

-+--

1/

'Il

1.

1.

100

•••

LOAD RESISTANCE - U

Figure 19. Open Loop Gain vs.
Resistive Load

Figure 20c. Inverter Small Signal
Pulse Response. CF '" 0,
CL "'10pF

Figure 20a. Inverting Amplifier
Connection

Figure 20d. Inverter Large Signal
Pulse Response. CF = 5 pF,
CL =110pF

Figure 20b. Inverter Large Signal
Pulse Response. CF ' " 0,
CL ", 10pF

Figure 20e. Inverter Small Signal
Pulse Response. CF = 5 pF,
CL = 110pF

.kfi

JU-

C,
SQUARE ....---H------,

WAVE
INPUT

••0
49.90

SCOPE PROBE
INClUDi..
'Opf~
CAPACITANCE

. Figure 21a. Unity Gain Inverter
Circuit for Driving Capacitive
Loads
2-94 OPERA TIONAL AMPLIFIERS

Figure 21b. Inverter Cap Load
Large Signal Pulse Response.
CF = 15pF, CL = 410pF

Figure 21c. Inverter Cap Load
Small Signal Pulse Response.
CF = 15pF, CL =410pF

REV. A

AD843
SQUARE

WAVE

INPUT

v,.
RL

499H

r
CL

INCLUDES lOpF
SCOPE PROBE
CAPACITANCE

Figure 22a. Unity Gain Buffer
Amplifier

Figure 22b. Buffer Large Signal
Pulse Response. CL = 10 pF

Figure 22c. Buffer Small Signal
Pulse Response. CL = 10 pF

Figure 23b. Buffer Cap Load Large
Signal Pulse Response.
CF = 33 pF, CL = 10 pF

Figure 23c. Buffer Cap Load Small
Signal Pulse Response.
CF = 33 pF, CL = 10 pF

Figure 23d. Buffer Cap Load Large
Signal Pulse Response.
CF = 33 pF, CL = 110 pF

Figure 23e. Buffer Cap Load Small
Signal Pulse Response.
CF = 33pF, CL = 110pF

200n
CF 33pF

+---1
SQUARE
WAVE
INPUT

10U

49.til

l

0.1.'
C, 10pF
l...J"..... INCLUDES
~

2.2~

Your

"'-

49tH

SCOPE PROBE

CAPACITANCE

Figure 23a. Unity Gain Buffer
Circuit for Driving Capacitive
Loads

REV. A

OPERA TIONAL AMPLIFIERS 2-95

•

AD843
DRIVING CAPACITIVE LOADS
Like most high bandwidth amplifiers, the ADS43 is sensitive to
capacitive loading. Although it will drive capacitive loads up to
20 pF without degradation of its' rated perfonnance, both an
increased capacitive load drive capability and a "cleaner" (nonringing) pulse response "can be obtained from the ADS43 by
using the circuits illustrateQ.m Figures 20 to 23. The addition of
a 5 pF feedback capacitor to the unity gain .inverter connection
(Figure 20a ) sUbStantia!l.y reduces the .circuit's overshoot, even
when it is driving a 110 pF load. This can be seen by comparing
the waveforms of Figures 20b through 20e. To drive capacitive
loads greater than 100 pF, the load should be decoupled from
the amplifier's output by a 10 0 resistor and the feedback
capacitor, CF , should be connected directly between tile amplifier's output and its inverting input (Figure 21a). When using a
IS pF feedback capacitor, this circuit can drive 400 pF with less
than 20% overshoot, as illustrated in Figures 21b and 21c.
Increasing capacitor CF to 47 pF also increases the capacitance
drive capability to 1000 pF, at the expense of a 10:1 reduction
in bandwidth compared with the sinlple unity gain inverter circuit of Figure 20a.

GROUNDING AND BYPASSING
In designing practical circuits using the ADS43, the user must
.. keep in mind that some special precautions are needed when
dealing with high frequency signals. Circuits must be wired
using short interconnect leads. Ground planes should be used
whenever possible to provide both a lowtesistance, low inductance circuit path and to mininlize the effects of high frequency
coupling. IC sockets should be avoided, since their increased
interlead capacitance can degrade the bandwidth of the device.
Power supply leads should be bypassed to ground as close as
possible to the pins of the amplifier. Again, the component leads
should be kept very short. As shown in Figure 24, a parallel
combination of a 2.2 I1F tantalum and a 0.1 I1F ceramic disc
capacitor is recommended.

Unity gain voltage followers (buffers) are more sensitive to
capacitive loads than are inverting amplifiers because there is no
attenUation of the feedback signal. The AD843 can drive 10 pF
to 20 pF when connected in the basic unity gain' buffer circuit
of Figure 22a.
The 1 kG resistor in series with the ADS43's noninverting input
serves two functions: first, together with the amplifier's input
capacitance, it forms a low pass mter which slows down the
actual signal seen by the ADS43. This helps reduce ringing on
the amplifier's output voltage. The resistor's second function is
to limit the current into the amplifier when the differential input
voltage exceeds the total supply voltage.
The ADS43 will deliver a much "cleaner" pulse response when.
connected in the somewhat more elaborate follower circuit of
Figure 23a. Note the reduced overshoot in Figure 23b and 23c
as compared to Figure 22b and 22c.
For maximum bandwidth, in most applications, input and feedback resistors used with the ADS43 should h&',e.resistance valUeS equal to or less than 1.5 kO. Even with these Jow resistance
v!i1ue~, the resultant RC time constant formed between them
and stray circuit capacitances is large enough to cause peaking in
the amplifier's response. Adding a small capacitor, CF , as shown
in Figures 20a to 23a will reduce this peaking and flatten the
overall frequency response. CF will norrnallybe less than 10 pF
in value.
.

Figure 24. Recommended Power Supply Bypassing for
the AD843 (DIP Pinout)

USING A HEAT SINK
The ADS43 consumes less quiescent power than most precision
high speed amplifiers and is specified to operate without using a
heat sink. However, when driving low inlpedance loads, the current applied to the load can be 4 to 5 times greater than the quiescent current. This will produce a noticeable temperatUre rise,
which will increase input bias currents. The use of a small heat
sink, such as the Mouser Electronics #33HSOOS is recommended.

The ADS43 can di"ive resistive loads over. the range of 500 0 to
00 with no change in dynamic respop.se. While a 499 o load was
used in the circuits of Figures 20-23, the perfonnance of these
circuits will be essentially the same even if this load is removed
or changed to some other value, such as 2 kO.
To obtain the "cleanest" possible transient response when driving heavy capacitive loads, be sure to connect bypass capacitors
directly between the power supply pins of the ADS43 and
ground as outlined in "grounding and bypassing."

Offset Null Configuration (DIP Pinout)

2-96 OPERATIONAL AMPLIFIERS

REV. A

AD843
SAMPLE-AND-HOLD AMPLIFIER CIRCUITS
A Fast Switching Sample & Hold Circuit
A sample-and-hold circuit possessing short acquisition time and
low aperture delay can be built using an AD843 and discrete
JFET switches. The circuit of Figure 25 employs five n-channel
JFETs (with turn-on times of 35 ns) and an AD843 op amp
(which can settle to 0.01 % in 135 ns). The circuit has an aperture delay time of 50 ns and an acquisition time of I jJ.S or less.
This circuit is based on a noninverting open loop architecture,
using a differential hold capacitor to reduce the effects of pedestal error. The charge that is removed from CHI by Q2 and Q3
is offset by the charge removed from CH2 by Q4 and Q5. This
circuit can tolerate low hold capacitor values (approximately
100 pF), which improve acquisition time, due to the small gateto-drain capacitance of the discrete JFETs. Although pedestal
error will vary with input signal level, making trimming more
difficult, the circuit has the advantages of high bandwidth and
short acquisition times. In addition, it will exhibit some nonlinearity because both amplifiers are operating with a common
mode input. Amplifier A2, however, contributes less than
0.025% linearity error, due to its 72 dB common mode rejection
ratio.

HOLD

~ 03

To make sure the circuit accommodates a wide ± 10 V input
range, the gates of the JFETs must be connected to a potential
near the -IS V supply. The level-shift circuitry (diode D3,
PNP transistor Q7, and NPN transistor Q6) shifts the TTLlevel SIH command to provide for an adequate pinch-off voltage
for the JFET switches over the full input voltage range.
The JFETs Q2, Q3, Q4 and Q5 across the two hold capacitors
ensure signal acquisition for all conditions of VIN and VOUT
when the circuit switches from the sample to the hold mode.
Transistor QI provides an extra stage of isolation between the
output of amplifier Al and the hold capacitor CHI.
When selecting capacitors for use in a sample-and-hold circuit,
the designer should choose those types with low dielectric
absorption and low temperature coefficients. Silvered-mica
capacitors exhibit low (0 to 100 ppm/"C) temperature coefficients
and will still work in temperatures exceeding 200°C. It is also
recommend that the user test the chosen capacitor to insure
that its value closely matches that printed on it since not all
capacitors are fully tested by their manufacturers for absolute
tolerance.

soon
01

02

~ lN~4K14r8~~_6~.~2k{~1~~~::1N_4D1~4_8~1~N~4_14_8-e______________-e____~2~.~1k~n~
SAMPLE

.......----....- -15V

Figure 25. A Fast Switching Sample-and-Hold Amplifier

REV. A

OPERA TIONAL AMPLIFIERS 2-97

II

AD843
A PING-PONG SIll AMPLIFIER
For improved throughput over the circuit of Figure 25, a "pingpong" architecture may be used. A ping-pong circuit overcomes
some of the problems associated with high speed SIH amplifiers
by allowing the use of a larger hold capacitor for a given sample
rate: this will reduce the associated feedthrough, droop and pedestal errors.

output is connected to the input of the AID converter. When .
the select command goes to logic LOW, the two output amplifiers alternate functions.

Figure 26 illustrates a simple, four-chip ping-pong sample-andhold amplifier circuit. This design increases throughput by
using one channel to acquire a new sample while another channel holds the previous sample. Instead of having to reacquire the
signal when switching from hold to sample mode, it alternately
connects the outputs from Channel I or from Channel 2 to the
AID converter. In this case, the throughput is the slew rate and
settling time of the output amplifiers, A2 and A3.
A high speed CB amplifier, AI, follows the input signal. VI, a
dual wide-band "T" switch, connects the input buffer amp to
one of the two output amplifiers while selecting the complementary amplifier to drive the AID input. For example, when
"select" is at logic high, Al drives CHI, A2 tracks the input
signal and the output of A3 is connected to the input of the AID
converter. At the same time, A3 holds an analog value and its

Since the input to the AID converter is the alternated "held"
outputs from Al and A2, the offset voltage mismatch of the two
amplifiers will show up as nonlinearity and, therefore, distortion
in the output signal. To minimize this, potentiometers can be
used to adjust the offsets of the output amplifiers until they are
equal. Alternatively, an autocalibration circuit using two D/A
converters can be employed. This can also be used to calibrateout the effects of offset voltage drift over temperature.
The switch choice, for VI, is critical in this type of design. The
DG542 utilizes "T" switching techniques on each channel for
exceptionally low crosstalk and for high isolation. The part further improves these specifications by using ground pins between
the signal pins. With an input frequency of 5 MHz, crosstalk
and isolation are - 85 dB and -75 dB, respectively. A limitation
of this switch is that it operates from a maximum - 5 V negative
supply, making bipolar operation more difficult. It is recommended that amplifiers AI, A2 and A3 operate from the same
- 5 V supply to minimize any potential latch-up problems.

+5V

U1

SELECT

~

IN1
D1

+5V

GND
S1

:!:3V

IN2
D2
GND
S2

DG542DJ

S4
GND
D4

.

+5V
OUTPUT
TO
AID
CONVERTER

S3
GND
D3

~CHANNEL'

~7
~
~HANNEL2
EQUIVALENT
SIMPLIFIED
DIAGRAM

'::'

~7

FOR AMPLIFIERS A1 TO A3,
ADD BYPASS CAPACITORS
TO EACH POWER SUPPLY PIN
AS SHOWN IN FIGURE 24

Figure 26. A Ping-Pong Sample-and-Hold Amplifier

2-98 OPERA TIONAL AMPLIFIERS

REV. A

Applying the AD843
TO TEKTRONIX
1kO

9kO

tl

r - - - -.,

7A26
II 1
OSCILLOSCOPE

20 II

T
L ____

:~::ECTION I MO

pF I
(VIA LESS THAN
....J
1FT. 500
..
COAXIAL CABLE) VERROR X 5
2500

2x
HP2835

II

0.47"'F~_VS
112 VERROR
1kO

1kO

NOTE
USE CIRCUIT BOARD
WITH GROUND PLANE

1000

r
I

-;~T::;:O-;

-

PULSE

1kO

1

I

:

GENERAT~O~ J.. V

I

DATA
DYNAMICS
5109
OR.
EQUIVALENT

,N

I
I
I
I
I

L _____ -'

2.2"F~

Figure 27. Settling Time Test Circuit

MEASURING AD843 SETTLING TIME
Figure 28 shows the dynamic response of the AD843 while
operating in the settling time test circuit of Figure 27. The
input of the settling time fixture is driven by a flat-top pulse
generator. The error signal output from AI, the AD843 under
test, is amplified by op amp A2 and then clamped by two high
speed Schottky diodes.

I:

.I .i

~

t-

~
I

: r

'50,(S

t-

~

The error signal is clamped to prevent it from greatly overloading the oscilloscope preamp. A Tektronix oscilloscope preamp
type 7A26 was chosen because it will recover from the approximately 0.4 volt overload, quickly enough to allow accurate measurement of the AD843's 13S ns settling time. Amplifier A2 is a
very high speed op amp; it provides a voltage gain of 10, providing a total gain of S from the error signal to the oscilloscope
input.
Figure 28. Settling Characteristics: + 10 V to 0 V Step.
Upper Trace: Amplified Error Voltage (0.01%IDiv)
Lower Trace: Output of AD843 Under Test (5 VIDiv)

REV. A

OPERA TIONALAMPLIFIERS 2-99

AD843 - Applications Circuit
A FAST PEAK DETECTOR CIRCUIT
The peak detector circuit of Figure 29, can accurately capture
the amplitude of input pulses as narrow as 200 ns and can hold
their value with a droop rate of less than 20 fJ.V/fJ.s. This circuit
will capture the peak value of positive polarity waveforms; to
detect negative peaks, simply reverse the polarity of the two
diodes.
The high bandwidth and 200 V/fJ.s slew rate of amplifier A2, an
AD843, allows the detector's output to "keep up" with its input
thus minimizing overshoot. The low « I nA) input current of
the AD843 ensures that the droop rate is limited only by the
reverse leakage of diode D2, which is typically <10 nA for the
type shown. The low droop rate is apparent in Figure 30. The

detector's output (top trace) loses slightly over a volt of the 8
volt peak input value (bottom trace) in 75 ms, or a rate of
approximately 16 ILVIlLS
Amplifier AI, an AD847, can drive 680 pF hold capacitor, Cp ,
fast enough to "catch-up" with the next peak in 100 ns and still
settle to the new value in 250 ns, as illustrated in Figure 31.
Reducing the value of capacitor Cp to 100 pF will maximize the
speed of this circuit at the expense of increased overshoot and
droop. Since the AD847 can drive an arbitrarily large value of
capacitance, Cp can be increased to reduce droop, at the expense
of response time.

1kO

VON

1kO

-Vs

Figure 29. A Fast Peak Detector Circuit

OV

OV

TOP TRACE: PEAK DETECTOR OUTPUT

TOP TRACE: PEAK DETECTOR OUTPUT. 8V

BOTTOM TRACE: INPUT. 8V PEAK

BOTTOM TRACE: INPUT VOLTAGE. 8V PEAK.
650n5 PULSE WIDTH

(a

125Hz

Figure 30. Peak Detector Response to 125 Hz Pulse Train

2-100 OPERATIONALAMPLIFIERS

Figure 31. Peak Capture Time

REV. A

60MHz,2000V/fJ.S
Monolithic Op Amp
AD844 I

11IIIIIIII ANALOG
WDEVICES
FEATURES
Wide Bandwidth: 60MHz at Gain of-1
33MHz at Gain of -10
Very High Output Slew Rate: Up to 2000V/IJ.s
20MHz Full Power Bandwidth, 20V pk-pk, RL =soon
Fast Settling: 100ns to 0.1% (10V Step)
Differential Gain Error: 0.03% at 4.4MHz
Differential Phase Error: 0.15° at 4.4MHz
High Output Drive: ±SOmA into son Load
Low Offset Voltage: 1S0IJ.V max (B Grade)
Low Quiescent Current: 6.SmA
APPLICATIONS
Flash ADC Input Amplifiers
High Speed Current DAC Interfaces
Video Buffers and Cable Drivers
Pulse Amplifiers

PRODUCT DESCRIPTION
The AD844 is a high speed monolithic operational amplifier fabricated using Analog Devices' junction isolated complementary
bipolar (CB) process. It combines high bandwidth and very fast
large signal response with excellent dc performance. Although
optimized for use in current to voltage applications and as an
inverting mode amplifier, it is also suitable for use in many noninverting applications.

CONNECTION DIAGRAM
8-Pin
Plastic (N),
and Cerdip (Q)
Packages

16-Pin SOIC
(R) Package

PRODUCT HIGHLIGHTS
1. The AD844 is a versatile, low cost component providing an
excellent combination of ac and dc performance. It may be
used as an alternative to the EL2020 and CLC400/1.
2. It is essentially free from slew rate limitations. Rise and fall
times are essentially independent of output level.
3. The AD844 can be operated from ±4.SV to ± 18V power
supplies and is capable of driving loads down to 500, as
well as driving very large capacitive loads using an external
network.

The AD844 can be used in place of traditional op amps, but its
current feedback architecture results in much better ac performance, high linearity and an exceptionally clean pulse response.

4. The offset voltage and input bias currents of the AD844 are
laser trimmed to minimize dc errors; Vos drift is typically
1".vrC and bias current drift is typically 9nArC.

This type of op amp provides a closed-loop bandwidth which is
determined primarily by the feedback resistor and is almost independent of the closed-loop gain. The AD844 is free from the
slew rate limitations inherent in traditional op amps and other
current-feedback op amps. Peak output rate of change can be
over 2000V/jLs for a full 20V output step. Settling time is typically lOOns to 0.1 %, and essentially independent of gain. The
AD844 can drive 500 loads to ±2.SV with low distortion and is
short circuit protected to 80mA.

5. The AD844 exhibits excellent differential gain and differential phase characteristics, making it suitable for a variety of
video applications with bandwidths up to 60MHz.
6. The AD844 combines low distortion, low noise and low drift
with wide bandwidth, making it outstanding as an input amplifier for flash AID converters.

The AD844 is available in four performance grades and three
package options. In the 16-pin SOIC (R) package, the AD844J
is specified for the commercial temperature range of 0 to + 70°C.
The AD844A and AD844B are specified for the industrial
temperature range of -40°C to +8S oC and are available in the
cerdip (Q) package. The AD844A is also available in an 8-pin
plastic mini-DIP (N). The AD844S is specified over the military
temperature range of - 55°C to + 125°C and is available in the
cerdip (Q) package. "A" and "S" grade chips and devices processed to MIL-STD-883B, REV. C are also available.

REV. A

OPERATIONALAMPLIFIERS 2-101

II

AD844-SPECIFICATIONS

(@ TA+"25OC and Vs=±15V dc, unless otherwise noted)
AD844B

AD844J/A

Model
INPUT OFFSET VOLTAGE'
Tmin-Tmax
vs. Temperature
vs. Supply
Initial
Tmin-T ....
vs. Common Mode
Initial
Tmin-T ....
INPUT BIAS CURRENT
- Input Bias Current'
Tmin-Tmax
vs. Temperature
vs. Supply
Initial
Tmin-T""",
vs. Common Mode
Initial
Tmin-T"""
+Input Bias Current'
Tmin-Tmax
vs. Temperature
vs. Supply
Initial
Tmin-T""",
vs. Common Mode
Initial
Tmin-T""",

Conditious

Min

Typ

Max

50
75
1

300
500

4
4

Min

AD844S

Typ

Max

50

ISO

Min

Typ

Max

Units

300
SOO
5

ILV
ILV
ILVI"C

is

zoo

1

5

50
125
1

ZO

4
4

10
10

4
4

20
20

ILVN
ILVN

10
10

35

10
10

20
ZO

10
10

35
35

ILVN
ILVN

200
SOO
9

4SO
1500

150
750
9

2SO
1100
15

200
1900
20

4SO
Z500
30

nA
nA
nAf'C

175
220

ZSO

175
220

ZOO
240

175
220

ZSO
300

nAN
nAN

90
llO
150
350
3

160

90
llO
100
300
3

110
ISO
ZOO
500
7

90
120
100
SOO
7

160
200
400
1300
15

nAN
nAN
nA
nA

5V-lSV

VCM =±10V

5V-lSV

VcM =±10V

400
700

nAl'C

5V-lSV
SO
100

ISO

SO
100

100
120

SO
120

ISO
ZOO

nAN
nAN

90
130

ISO

90
130

120
190

90
140

ISO
200

nAN
nAN

SO
10

65

SO
10

65

SO
10

65

{}

VcM =±IOV

INPUT CHARACTERISTICS
Input Resistance
-Input
+ InpUt
Input. Capacitance
-Input
+Input
Input Voltage Range
Common Mode

7

7

2
2

2
2
±10

±10

7

2
2

M{}
pF
pF
V

±10

INPUT VOLTAGE NOISE

f~lkHz

2

2

2

nVlYHz

INPUT CURRENT NOISE
-Input
+ Input

f~lkHz

10
12

10
12

10
12

pAlYHz
pAlYHz

3.0
1.6
4.5

MO
M{}
pF

OPEN LOOP TRANSRESISTANCE

f~lkHz

VoUT -±10V
R LoAD =5000

Tmin-Tm ",
TranscapacitaDce

Z.Z
1.3

3.0
2.0
4.5

Z.8
1.6

3.0
2.0
4.5

Z.Z

1.3

DIFFERENTIAL GAIN ERROR2

f-4.4MHz

0.03

0.03

0.03

%

DIFFERENTIAL PHASE ERROR2

f=4.4MHz

0.15

0.15

0.15

Degree

60
33

60
33

60
33

MHz
MHz

0.005

0.005

0.005

%

100
100

100
100

100
100

ns
ns

llO
100

llO
100

llO
100

ns
ns

FREQUENCY RESPONSE
SmaIl Signal Bandwidth
'Gain=-1
4Gain=-10
TOTAL HARMOMIC DISTORTION

f-l00kHz,
2V rms5

SETTLING TIME
10V Output Step.
Gain=-I, to 0.1%5
Gain=-10, to 0.1%6
2V Output Step
Gain=-I, to 0.1%5
Gain= -10, to 0.1%6

2-102 OPERATIONAL AMPLIFIERS

± 15V Supplies

±5V Supplies

REV. A

AD844
AD844J/A
Typ
Max

Model

Conditions

Min

OUTPUT SLEW RATE

Overdriven
Input

1200 2000

FULL POWER BANDWIDTH
VOUT=20V pop'
VOUT=2V pop'
OUTPUT CHARACTERISTICS
Voltage
Shon Circuit Current
T_-Tmax
Output Resistance

6.5
7.5

±IS
7.S
S.S

AD844S
Typ
Max

1200 2000

Units
V/",s

20
20

II

10

SO
60
IS
±4.S

Min

20
20

II

10

Open Loop

POWER SUPPLY
Operating Range
Quiescent Current
T_-Tmax

1200 2000

20
20

Vs=±ISV
Vs=±SV
THD=3%
RLOAO=soon

AD844B
Typ
Max

Min

MHz
MHz

II

±V

SO

SO

60

60

rnA
rnA

IS

IS

n

±4.S
6.5
7.5

10

±IS
7.S
S.S

±4.S
6.5
S.S

±IS
7.S
9.S

V
rnA
rnA

NOTES
'Rated perfonnance after a 5 minute warmup at T" =25"C.
'Input signal 285mV pop carrier (40 IRE) riding on 0 to 642mV (90 IRE) ramp. RL = lOon; RI, R2=30OO.
'Input signal OdBm, CL=10pF, RL =5000, RI=500n, R2=500n in Figure 26.
'Input signal OdBm, CL=lOpF, RL =5000, RI=500n, R2=50n in Figure 26.
'CL=IOpF, RL =5000, Rl=lkn, R2=lkn in Figure 26.
'CL=lOpF, RL =5000, Rl=50OO, R2=50n in Figure 26.
Specifications subject to change without notice. All min and max specifications are guaranteed.
Specifications shown in boldface are tested on all production units at final electrical test.

ABSOLUTE MAXIMUM RATINGS!
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ±lSV
Power Dissipation2 • • • • • • • • • • • • • • • • • • • • • • • • • 1.1 W
Output Shon Circuit Duration . . . . . . . . . . . . . . . Indefinite
Common Mode Input Voltage . . . . . . . . . . . . . . . . . . . ±Vs
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . 6V
Inverting Input Current
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SmA
Transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • lOrnA
Storage Temperature Range Q . . . . . . . . . . -65°C to + 150°C
N, R . . . . . . • . -65°C to + 125°C
Lead Temperature Range (Soldering 60sec) . . . . . . . . +300"C
NOTES
IStresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
'8-Pin Plastic Package: OJA = IOO'CIWatt
8-Pin Cerdip Package: OJA = 1I0'CIWatt
16-Pin SOIC Package: OJA = 100'CIWatt

MET~TIONPHOTOG~
Contact factory for latest dimensions.

Dimensions shown in inches and (mm).
-IN

0.076
(1.9)

l~~
I.
SUBSTRATE CONNECTED

ORDERING GUIDE!

TO +V.

Model!

Temperature
Range

Package
Option2

ADS44JR
ADS44AN
ADS44AQ
ADS44BQ
ADS44SQ
ADS44SQ/SS3B

O°C to +70°C
-40°C to +SsoC
-40°C to +SsoC
-40°C to +SsoC
- 55°C to + 125°C
- 55°C to + 125°C

R-16
N-S
Q-S
Q-S
Q-S
Q-S

NOTES
S"'A" and "S" grade chips are also available.
'N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC). For outline
information see Package Information section.

REV. A

OPERATIONALAMPLIFIERS 2-103

II

AD844-Typical Characteristics (T =+25°C and Vs=±15V unless otherwise noted)
A

-00

70

"... I--

-70

./

/

/'

/

!fI,

/

Z

i

-80

lVrms

3

~

-90

~

-100

:1:..,.110

40

o

'0

20

'5

I ,.I

-'30

, ..

~

[iRDiM~NII

~
,00k

'Ok
INPUT FREQUENCY - Hz

SUPPLY VOLTAGE - '£:V

,

~

2ND HARMONIC
-120

30

/'

C5

I

50

V

/' , / , / f..--'"

Ra.=soon

,.......

1\=50.11

-

,..f.-

..

..

..

,

,

TEMPERATURE -

oc

Figure 3. Transresistance
VS. Temperature

Figure 2. Harmonic Distortion
VS. Frequency, R 1 = R2 = 1k(}'

Figure 1. -3dB Bandwidth vs.
Supply Voltage R1 =R2=500(}'

20

rj"

('"

'0

20

/

V

/

/

f\.=500U
+Z5°C

/..c
V

,. /

/

V

/

/
Vs=±16V

~
./

):::: .
",

.,.

./

I-' ~

V
V V
Vr±5V

./

V

.'.
10

20

10
15
SUPPLY VOLTAGE -'±Volts

15

20

-110 -40 -20

0

SUPPLY VOLTAGE - :!!Volts

Figure 5. Output Voltage Swing

Figure 4. Noninverting Input VCfltage
Swing vs. Supply Voltage

+20 +40

+60 +80 +100 +120 +140

TEMPERATURE -

oc

Figure 6. Quiescent Supply Current
vs. Temperature and Supply Voltage

VB. Supply Voltage

.

'00

-JJ-

35

'0

"1, '

I

t,
G

0

i

-2
-50

I--

--

~

-V

/

I..

''\

50

TEMPERATURE -

0.'

oc

..

,

~

.7~

/

25

-r-

Vs=±5V

20

15

,..

Figure 7. Inverting Input Bias Current (lSN) and Noninverting Input
Bias Current (lsp) vs. Temperature

2-104 OPERA TIONAL AMPLIFIERS

-

30

~

+5V VOLT SUPPLIES

.............

r---.

~

0.01
'Ok

lOOk

'M

'OM

'OOm

FREQUENCY - Hz

Figure 8. Output Impedance
vs. Frequency, Gain=-1,. R1 =R2= 1k(}'

'0
-60 -40 -20

0

+20 +40 +60 +80 +100 +120+140

TEMPERATURE -

oc

. Figure 9. -3dB Bandwidth vs.
Temperature, Gain=-1,
R1=R2=1k()'

REV. A

AD844
Inverting Gain of 1 AC Characteristics
••

+v.

-.ao

R'~R2="'"

ld--,J
11\ \

4.70

~~
...... ....... ......

-210

......

'\

R1=RZ=11cQ

I

R2

-I

VOUT

I--

\

I

I-..

I

J-270

-24

Figure 10. Inverting Amplifier,
Gain of -1 (R1 =R2)

R1""IQ=1kn

-300

....

-v.

R1=R2=5000

"'

'r-...
........

..

-330
100M

1M
10M
FREQUENCY - Hz

•

"\
II
1"-.. .......

I

-II

""-I,

0

50

FREQUENCY - MHz

Figure 12. Phase vs. Frequency
Gain=-1, RL =500n, CL=OpF

Figure 11. Gain vs. Frequency for
Gain = -1, RL =500n, CL=OpF

T

I

Figure 14. Small Signal Pulse
Response, Gain=-1, R1=R2=1kn

Figure 13. Large Signal Pulse
Response, Gain=-1, R1=R2=1kn

Inverting Gain of 10 AC Characteristics

.
.

... ~

-

RL=5DOR

I..::::::

~

..:.....

,'I

~

I
~

\

-210

r'\

I-I

Figure 15. Gain of -10 Amplifier

REV. A

--,...

1M
10M
FREQUENCY - Hz

Figure 16. Gain vs. Frequency,
Gain=-10

r\.

[\, !"I.. .... =.....

,(

-300

-v.

"r\:

.....,K, "-

)

1-270
-330

~ ......

......
o

••

,
l"I'-.

FREOUENCY - MHz

'0

Figure 17. Phase vs. Frequency,
Gain=-10

OPERA TIONALAMPLIFIERS 2-105

AD844
Inverting Gain of 10 Pulse Response

T

I

Figure 18. Large Signal Pulse
Response, Gain=-10, RL =500n

Figure 19. Small Signal Pulse
Response, Gain=-10, RL =500n

Noninverting Gain of 10 AC Characteristics

.
'"},

20
",

8 ' ", ,

"

\[\

...

i-

,

i\=soou

"

V

'\ ~

240

~" r--...
II

27o

RL =50fl

0

,.

~

r-....
r-.... ....
50

FRt:aUENCY - MHz

Figure 21. Gain vs. Frequency,
Gain=+10

Figure 23. Noninverting Amplifier Large Signal
Pulse Response, Gain = + 10, RL =500n

,~

-300

100M

10M

~

\

-330
1M

FREQUENCY - Hz

2-106 OPERATIONAL AMPLIFIERS

1-,

1\

",

2

•,

-210

\\

,

"""'= ~

RL~~

Rc="" I\\,

•

Figure 20. Noninverting Gain of
+ 10 Amplifier

-'50

I

Figure 22. Phase vs. Frequency,
Gain=+10

Figure 24. Small Signal Pulse
Response, Gain = + 10, RL =500n

REV. A

AD844
UNDERSTANDING THE AD844
The AD844 can be used in ways similar to a conventional op
amp while providing performance advantages in wideband applications. However, there are important differences in the internal
structure which need to be understood in order to optimize the
performance of the AD844 op amp.
Open Loop Behavior
Figure 25 shows a current feedback amplifier reduced to essentials. Sources of fixed dc errors such as the inverting node bias
current and the offset voltage are excluded from this model and
are discussed later. The most important parameter limiting the
dc gain is the transresistance, Rt, which is ideally infinite. A
finite value of Rt is analogous to the finite open loop voltage
gain in a conventional op amp.
The current applied to the inverting input node is replicated by
the current conveyor so as to flow in resistor Rt. The voltage
developed across Rt is buffered by the unity gain voltage follower. Voltage gain is the ratio Rtf R'N' With typical values of
Rt=3MO and R IN =500, the voltage gain is about 60,000. The
open loop current gain is another measure of gain and is determined by the beta product of the transistors in the voltage follower stage (see Figure 28); it is typically 40,000.

The closed loop transresistance is simply the parallel sum of RI
and Rt. Since RI will generally be in the range 5000 to 2kO
and Rt is about 3MO the closed loop transresistance will be only
0.02% to 0.07% lower than Rl. This small error will often be
less than the resistor tolerance.
When RI is fairly large (above SkO) but still much less than Rt,
the closed loop HF response is dominated by the time constant
RICt. Under such conditions the AD844 is over-damped and
will provide only a fraction of its bandwidth potential. Because
of the absence of slew rate limitations under these conditions,
the circuit will exhibit a simple single pole response even under
large signal conditions.
In Figure 26, R3 is used to properly terminate the input if desired. R3 in parallel with R2 gives the terminated resistance. As
RI is lowered, the signal bandwidth increases, but the time constant RICt becomes comparable to higher order poles in the
closed loop response. Therefore, the closed loop response becomes complex, and the pulse response shows overshoot. When
R2 is much larger than the input resistance, R'N' at Pin 2, most
of the feedback current in Rl is delivered to this input; but as
R2 becomes comparable to R IN , less of the feedback is absorbed
at Pin 2, resulting in more heavily damped response. Consequently, for low values of R2 it is possible to lower RI without
causing instability in the closed loop response. Table I lists combinations of RI and R2 and the resulting frequency response for
the circuit of Figure 26. Figure 13 shows the very clean and fast
± 10V pulse response of the AD844.

a

Rt

Figure 25. Equivalent Schematic
The important parameters defining ac behavior are the transcapacitance, Ct, and the external feedback resistor (not shown).
The time constant formed by these components is analogous to
the dominant pole of a conventional op amp, and thus cannot be
reduced below a critical value if the closed loop system is to be
stable. In practice, Ct is held to as Iowa value as possible (typically 4.5pF) so that the feedback resistor can be maximized
while maintaining a fast response. The finite R'N also affects the
closed loop response in some applications as will be shown.
The open loop ac gain is also best understood in terms of the
transimpedance rather than as an open loop voltage gain. The
open loop pole is formed by Rt in parallel with Ct. Since Ct is
typically 4.5pF, the open loop comer frequency occurs at about
12kHz. However, this parameter is of little value in determining
the closed loop response.
Response as an Inverting AmpUfier
Figure 26 shows the connections for an inverting ampUfier.
Unlike a conventional ampUfier the transient response and the
sma11 signal bandwidth are detenhlned primarily by the value of
the external feedback resistor, RI, rather than by the ratio of
RIIR2 as is customarily the case in an op amp application. This
is a direct result of the low impedance at the inverting input. As
with conventional op amps, the closed loop gain is - RIIR2.

REV. A

R3
OPTIONAL

>-"-"'--1~VOUT

'-----t

CL

Figure 26. Inverting Amplifier

Gain

Rl

R2

-I
-I
-2
-2
-5
-5
-10
-10
-20
-100
+100

IkO
5000
2kO
IkO
5kO
5000
lkn
5000
Ikn
SkO
SkO

IkO
5000
IkO
5000
IkO
1000

1000
500
500
500
500

BW(MHz)

GBW(MHz)

35
60
IS
30
5.2
49
23
33
21
3.2
9

35
60
30
60
26
245
230
330
420
320

900

Table I.

OPERATIONALAMPLIFIERS 2-107

•

AD844
Response as an I~V Converter
The AD844 works well as the active element in an operational
current to voltage converter, used in conjunction with an external scaling resistor, RI, in Figure 27. This analysis includes the
stray capacitance, Cs , of the cUrrent source, which might be a
high speed DAC. Using a conventional op amp, this capacitance
forms a "nuisance pole" with RJ. which destabilizes the closed
loop response of the system. Most op amps are internally compensated for the fastest response at unity gain, so the pole due
to RI and Cs redU<;e8 the already narrow phase margin of the
system. For example, if RI were 2.SkO a Cs of ISpF would
place this pole at a frequency of about 4MHz, well within the
response range of even a medium speed operatioIial amplifier. In
a current feedback amp this nuisance pole is no longer determined by RI but by the input resistance, R IN . Since this is
about SOO for the AD844, the same ISpF forms a pole 212MHz
and causes little trouble. It can be shown that the response of
this system is:
KRI
VOUT = -Isig (l+sTd)(1+sTn)
where K is a factor very close to unity and represents the finite
dc gain of the amplifier, Td is the dominant pole and Tn is the
nuisance pole:
Rt
K = Rt+RI
Td = KRICt
Tn = RINCS

(assuming RIN

«

RI)

Using typical values ofRI=lkO and Rt=3MO, K is 0.9997; in
other words, the "gain error" is only 0.03%. This is much less
than the scaling error of virtually all DACs and can be
absorbed, if necesS8ty, by the trim needed in a precise system.
In the AD844, Rt is fairly stable with temperature and supply
voltages, and consequently the effect of fmite "gain" is negligible unless high value feedback resistors are used. Since that
would result in slower response times than are possible, the relatively low value of Rt in the AD844 will rarely be a significant
source of error.

>-.......- V O U T

Figure 27. Current to Voltage Converter
Circuit Description of the AD844
A simplified schematic is shown in Figure 28. The AD844 differs from a conventional op amp in that the signal inputs have
radically different impedance. The noninverting input (Pin 3)
presents the usual high impedance. The voltage on this input is
transferred to the inverting input (Pin 2) with a low offset voltage, ensured by the close matching of like polarity transistors

2-108 OPERATIONALAMPLIFIERS

Figure 28. Simplified Schematic
operating under essentially identical bias conditions. Laser trimming nulls the residual offset voltage, down to a few tens of microvolts. The inverting input is the common emitter node of a.
complementary pair of grounded base stages and behaves as a
current summing node. IQ an ideal current feedback op amp the
input resistance would be zero. In the AD844 it is about SOO.
A current applied to the inverting input is transferred to a complementary pair of unity-gain current mirrors which deliver the
same current to an internal node (Pin S) at which the full output
voltage is generated. The unity-gain complementary voltage follower then buffers this voltage and provides the load driving
power. This buffer is designed to drive low impedance loads
such as terminated cables, and can deliver ±SOmA into a SOO
load while maintaining low distortion, even when operating at
supply voltages of only ±6V. Current limiting (not shown) ensures. safe operation under short circuited conditions.

It is important to understand that the low input impedance at
the inverting input is locally generated, and does not depend on
feedback. This is very different from the "virtual ground" of a
conventional operational amplifier used in the current summing
mode which is essentially an open circuit until the loop settles.
In the AD844, transient current at the input does not cause
voltage spikes at the summing node while the amplifier is setding. Furthermore, .all of the transient current is delivered to
the slewing (TZ) node (Pin S) via a short signal path (the
grounded base stages and the wideband current mirrors).
The current available to charge the capacitance (about.4.SpF)
at TZ node, is always proportional to the input error current, and
the slew rate limitations associated with the large signal response
of op amps do not occur. For this reason, the rise and fall
times are almost independent of signal level. In practice, the
input current will eventually cause the mirrors to saturate.
When using ± lSV supplies, this occurs at about 10mA (or
±2200Vll1s). Since signal currents are rarely this large, classical
"slew rate" limitations are absent.
This inherent advantage would be lost if the voltage follower
used to buffer the output were to have slew rate limitations: The
AD844 has been designed to avoid this problem, arid as a result
the output buffer exhibits a clean large signal traIisient response,
free from anomalous effects arising from internal saturation.

REV. A

Applying the AD844
Response as a Noninverting Amplifier
Since current feedback amplifiers are asymmetrical with regard
to their two inputs, performance will differ markedly in noninverting and inverting modes. In noninverting modes, the large
signal high speed behavior of the AD844 deteriorates at low
gains because the biasing circuitry for the input system (not
shown in Figure 28) is not designed to provide high input voltage slew rates.
However, good results can be obtained with some care. The
noninverting i.nput will not tolerate a large transient input; it
must be kept below ± 1V for best results. Consequently this
mode is better suited to high gain applications (greater than
x 10). Figure 20 shows a noninverting amplifier with a gain of
10 and a bandwidth of 30MHz. The transient response is shown
in Figures 23 and 24. To increase the bandwidth at higher
gains, a capacitor can be added across R2 whose value is approximately the ratio of R1 and R2 times Ct.

4.70

4.70

Figure 29. Noninverting Amplifier Gain = 100, Optional
Offset Trim Is Shown

Noninverting Gain of 100
The AD844 provides very clean pulse response at high noninverting gains. Figure 29 shows a typical configuration providing
a gain of 100 with high input resistance. The feedback resistor is
kept as low as practicable to maximize bandwidth, and a peaking capacitor (CpK) can optionally be added to further extend
the bandwidth. Figure 30 shows the small signal response with
CPK = 3nF, RL = 5000 and supply voltages of either ± SV or
± lSV. Gain bandwidth products of up to 900MHz can be achieved

in this way.
The offset voltage of the AD844 is laser trimmed to the 5011V
level and exhibits very low drift. In practice, there is an additional offset term due to the bias current at the inverting input
(IBN) which flows in the feedback resistor (R1). This can
optionally be nulled by the trimming potentiometer shown in
Figure 29.

REV. A

46

II

V.=,~15V
40

....,

r-- r-.. ~ll
[\

34

~

I

Z

~

Vs=±SV

28

\
~\

\\
\1

22

16
lOOk

1M
FREQUENCY - Hz

10M

20M

Figure 30. AC Response for Gain = 100, Configuration
Shown in Figure 29
USING THE AD844
Board Layout
As with all high frequency circuits considerable care must be
used in the layout of the components surrounding the AD844. A
ground plane, to which the power supply decoupling capacitors
are connected by the shortest possible leads, is essential to
achieving clean pulse response. Even a continuous ground plane
will exhibit finite voltage drops between points on the plane,
and this must be kept in mind in selecting the grounding points.
Generally speaking, decoupling capacitors should be taken to a
point close to the load (or output connector) since the load currents flow in these capacitors at high frequencies. The + In and
- In circuits (for example, a termination resistor and Pin 3)
must be taken to a common point on the ground plane close to
the amplifier package.
Use low impedance capacitors (AVX SR30SC224KAA or equivalent) of 0.2211F wherever ac coupling is required. Include either
ferrite beads and/or a small series resistance (approximately
4.70) in each supply line.
Input Impedance
At low frequencies, negative feedback keeps the resistance at the
inverting input close to zero. As the frequency increases, the
impedance looking into this input will increase from near zero to
the open loop input resistance, due to bandwidth limitations,
making the input seem inductive. If it is desired to keep the
input impedance flatter, a series RC network can be inserted
across the input. The resistor is chosen so that the parallel sum
of it and R2 equals the desired termination resistance. The
capacitance is set so that the pole determined by this RC network is about half the bandwidth of the op amp. This network
is not important if the input resistor is much larger than the termination used, or if frequencies are relatively low. In some
cases, the small peaking that occurs without the network can be
of use in extending the - 3dB bandwidth.

OPERATIONALAMPLIFIERS 2-109

II

AD844
Driving Large Capacitive Loads
Capacitive drive capability is 100pF without an external network. With the addition of the network shown in Figure 31, the
capacitive drive can be extended to over 10,OOOpF, limited by
internal power dissipation. With capacitive loads, the output
speed becomes a function of the overdriven output current limit.
Since this is roughly ± 100mA, under these conditions, the maximum slew rate into a 1000pF load is ± 100V/fLS. Figure 32
shows the transient response of an inverting amplifier
(Rl=R2=lkn) using the feed forward network shown in Figure
31, driving a load of 1000pF.

>-,-_V

OUT

Cl

01. 02 IN6263 OR EQUIV. SCHOTTKY DIODE

Figure 33. Settling Time Test Fixture

Figure 31. Feed Forward Network for Large
Capacitive Loads

DC Error Calculation
Figure 34 shows a model of the dc error and noise sources for
the AD844. The inverting input bias current, IBN' flows in the
feedback resistor. IBP ' the noninverting input bias current, flows
in the resistance at Pin 3 (Rp), and the resulting voltage (plus
any offset voltage) will appear at the inverting input. The total
error, Va' at the output is:
VO=(IBP Rp+ Vas +IBN R1N)

(1+ ~~) + IBN Rl

Since IBN and IBP are unrelated both in sign and magnitude,
inserting a resistor in series with the noninverting input will not
necessarily reduce de error and may actually increase it.

Figure 32. Driving 1000pF CL with Feed Forward Network
of Figure 31

Settling Time
Settling time is measured with the circuit of Figure 33. This
circuit employs a false suinming node, clamped by the two
Schottky diodes, to create the error signal and limit the input
signal to the oscilloscope. For measuring settling time, the ratio
of R6IRS is equal to RIIR2. For unity gain, R6 = RS = lkn, and
RL = soon. For the gain of -10, RS = son, R6 = soon and RL
was not used since the summing network loads th~ output with
approximately 27Sn. Using this network in a unity-gain configuration, settling time is lOOns to 0.1% for a -SV to +SV step
with CL = 10pF.

Figure 34. Offset Voltage and Noise Model for the AD844

Noise
Noise sources can be modeled in a manner similar to the dc bias
currents, but the noise sources are Inn, Inp, Vn, and the
amplifier-induced noise at the output, VON' is:
VON =

~((Inp Rpi+Vn2) (1+ ~)2 +(Inn Rli

Overall noise can be reduced by keeping all resistor values to a
minimum. With typical numbers, Rl=R2=lk, Rp=O,
Vn=2nV/yHz, Inp=IOpNyHz, Inn=12pNVHz, VON calculates to 12nV/VHz. The current noise is dominant in this case,
as it will be in most low gain applications.

2-110 OPERATlONALAMPLlFIERS

REV. A

Applications - AD844
Video Cable Driver Using ±S Volt Supplies
The AD844 can be used to drive low impedance cables. Using
±5V supplies, a 1000 load can be driven to ±2.5V with low
distortion. Figure 35a shows an illustrative application which
provides a noninverting gain of 2, allowing the cable to be
reverse-terminated while delivering an overall gain of + I to the

load. The - 3dB bandwidth of this circuit is typically 30MHz.
Figure 35b shows a differential gain and phase test setup.
In video applications, differential-phase and differential-gain
characteristics are often important. Figure 35c shows the variation in phase as the load voltage varies. Figure 35d shows the
gain variation.

+5V

•

v,.

300n

Figure 35b. Differential Gain/Phase Test Setup

Figure 35a. The AD844 as a Cable Driver
+0.3

NOTE,

!•• =

+0.06

+0.2

i,

+0.04

~

+0.1

~

~

I~

~

1-0.02
is

-0.2
-0.3

+0.02

3

J
1-0.,
i

NOTE~ IRE = 7.,lmv

7.'JoV

~~

-0.04

o

,.

3.

54

72

-0.06

90

o

,.

3.

54
VOUT -IRE

72

.

Figure 35c. Differential Phase for the Circuit of Figure 35a

Figure 35d. Differential Gain for the Circuit of Figure 35a

High Speed DAC Buffer
The AD844 performs very well in applications requiring
current-to-volmge conversion. Figure 36 shows connections for
use with the AD568 current output DAC. In this application the
bipolar offset is used so that the full scale current is ±5.12mA,
which generates an output of ± 5.12V using the lkO application
resistor on the AD568. Figure 37 shows the full scale transient
response. Care is needed in power supply decoupJing and

grounding techniques to achieve the full 12-bit accuracy and
realize the fast settling capabilities of the system. The unmarked
capacitors in this figure are O.IIJ.F ceramic (for example, AVX
Type SR305CI04KAA), and the ferrite inductors should be
about 2.51J.H (for example, Fair-Rite Type 2743002122). The
AD568 data sheet should be consulted for more complete details
about its use.

~1-------------1---------CE~~+'w

1221--+---++_---:---+------..--a~~

-15V

DIGITAL
INPUTS

I-~~~~------------+_--~---o~~~~
GROUND

DIGITAL

~1-~~----------------------~~SU~y
·O.U,.F
POWER SUPf"LY
BVPASS CAPACfTORS

Figure 37. DAC Amplifier Full-Scale
Transient Response

Figure 36. High Speed DAC Amplifier

REV. A

OPERA TIONALAMPLIFIERS 2-111

AD844
Figure 39 shows the small signal response for a SOdB gain control range (Vx=+lOmV to +3.16V). At small values ofVx ,
capacitive feedthrough on the PC board becomes troublesome,
and very careful layout techniques are needed to minimize this
problem. A ground strip between the pins of the ADS39 will be
helpful in this regard. Figure 40 shows the response to a 2V
pulse on Vy for Vx=+IV, +2V and +3V. For these results, a
load resistor of 5000 was used and the supplies were ±9V. The
multiplier will operate from supplies between ±4.SV and
±16.SV.

20MHz Variable Gain Amplifier

The AD844 is an excellent choice as an output amplifier for the
ADS39 multiplier, in all of its connection modes. (See ADS39
data sheet for full details.) Figure 38 shows a simple multiplier
providing the output:
VxV
---zvy

Vw

=

where Vx is the "gain control" input, a positive voltage of from
o to +3.2V (max) and Vy is the "signal voltage", nominally
±2V FS but capable of operation up to ±4.2V. The peak output in this configuration is thus ±6.7V. Using all four of the
internal application resistors provided on the ADS39 in parallel
results in a feedback resistance of l.SkO, at which value the
bandwidth of the AD844 is about 22MHz, and is essentially
independent of Vx . The gain at Vx =3.l6V is +4dB.

Disconnecting Pins 9 and 16 on the ADS39 alters the denominator in the above expression to 1V, and the bandwidth will be
approximately 10MHz, with a maximum gain of IOdB. Using
only Pin 9 or Pin 16 results in a denominator of O.SV, a bandwidth of SMHz and a maximum gain of 16dB.

,-_ _ _ _ _ _ _ _ _ _ _.--<>+v,
ton

10n

TYP.+6V
(,,1SmA

INPUTS

V,
OTO +3V

V,o-I-+-+{)
:t2V FS

'nF

10n

TYP.-6V
(fl25mA
L -_ _ _ _~""'~----~-<>_V,

10n
-V x AND Vv INPUTS MAY OPTIONALLY

BE TERMINATED - TYPICALLY BY

USING A 50n OR 7SU RESISTOR
to GROUND.

Figure 38. 20MHz VGA Using the AD539
+4

,'"

V=3r SV
X

-6

vlt='(V

\

-16

Vx=ofsV

'1l

. -26

~

VIt=O(OV

........

Vx =O.032V

.......

-'6
-46

"
,

"

-56
1DOl<

1M

10M

&oM

FREQUENCY - Hz

Figure 39. VGA AC Response

2-112 OPERA TlONALAMPLIFIERS

Figure 40. VGA Transient Response with
Vx = lV, 2V, and 3V

REV. A

Precision 16 MHz
CBFET Op Amp
AD845 I

r'IIIIANALOG
WDEVICES
FEATURES
Replaces Hybrid Amplifiers in Many Applications
AC PERFORMANCE:
Settles to 0.01% in 350 ns
100 V/,..s Slew Rate
12.8 MHz min Unity-Gain Bandwidth
1.75 MHz Full-Power Bandwidth at 20 V p-p
DC PERFORMANCE:
0.25 mV max Input Offset Voltage
5 ,..VlOC max Offset Voltage Drift
0.5 nA Input Bias Current
250 VlmV min Open-Loop Gain
4 ,..V p-p max Voltage Noise, 0.1 Hz to 10 Hz
94 dB min CMRR
Available in Plastic Mini-DIP, Hermetic Cerdip and SOIC
Packages
PRODUCT DESCRIPTION
The AD845 is a fast, precise, N channel JFET input, monolithic operational amplifier. It is fabricated using Analog
Devices' complementary bipolar (CB) process. Advanced laserwafer trimming technology enables the very low input offset
voltage and offset voltage drift performance to be realized. This
precision, when coupled with a slew rate of 100 V/fLS, a stable
unity-gain bandwidth of 16 MHz, and a settling time of 350 ns
O.OI%-while driving a paralle110ad of 100 pF and 500 0represents a combination of features unmatched by any FET
input IC amplifier. The AD845 can easily be used to upgrade
many existing designs which use BiFET or FET input hybrid
amplifiers and, in some cases, those which use bipolar input op
amps.
The AD845 is ideal for use in applications such as active fIlters,
high speed integrators, photo diode preamps, sample-and-hold
amplifiers, log amplifiers, and in buffering AID and D/A converters. The 250 fLV max input offset voltage makes offset nulling unnecessary in many applications. The common-mode
rejection ratio of llO dB over a ± 10 V input voltage range represents exceptional performance for a JFET input high speed op
amp. This, together with a minimum open-loop gain of
250 VImV ensures that 12-bit performance is achieved, even in
unity-gain buffer circuits.

REV. A

CONNECTION DIAGRAM
Plastic Mini-DIP (N) Package
and Cerdip (Q) Package

16-Pin SOIC (R) Package

NULL

+INPUT

-v

NC

NC

= NO CONNECT

The AD845 conforms to the standard op amp pinout except that
offset nulling is to V+. The AD845J and AD845K grade devices are available specified to operate over the commercial 0 to
+ 70°C temperature range. AD845A and AD845B devices are
specified for operation over the -40°C to + 85°C industrial temperature range. The AD845S is specified to operate over the full
military tempemture range of -55°C to + 125°C. Both the industrial and military versions are available in 8-pin cerdip packages. The commercial version is available in an 8-pin plastic
mini-DIP and 16-pin SOIC. "1" and "S" grade chips are also
available.
PRODUCT HIGHLIGHTS
1. The high slew rate, fast settling time, and dc precision of the
AD845 make it ideal for high speed applications requiring
12-bit accuracy.
2. The performance of circuits using the LF400, OP-42, OP-44,
OP-16, OP-17, HA2520/2/5, HA2620/2/5, 3550, OPA605,
and LH0062 can be upgraded in most cases.
3. The AD845 is unity-gain stable and internally compensated.
4. The AD845 is specified while driving 100 pF/500 0 loads.

OPERATIONALAMPLIFIERS 2-113

•

AD845-SPECIFICATIONS

(@ +25°C and ±15 V dc, unless otherwise noted)

AD845J/A
Typ
Min

Model
Conditions
INPUT OFFSET VOLTAGE'
Initial Offset

0.7

Tmin-Tmu
Offset Drift
INPUT BIAS CURRENT'
Initial

0.75

VCM = OV

25

VCM = OV
Tmin-TInlIK

INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
INPUT VOLTAGE RANGE
Differential
Common Mode
Common-Mode Rejection

Max

1.5
2.5
20

0.1

2

0.5

1.5

300
3/6.5

IS

Max

Unils

0.25
0.4
5.0

0.25

1.0
2.0
10

mV
mV
.,.VI"C

I
18/38

0.75

2

nA
nA

100
1.212.6

25

500

:t20 '

+ 10.51-13

+10
94

110

+ 10.51-13

±IO
86

113

300
20

4.0

:t20
VCM = :tIOV

Typ

Min

lO"

lO"
4.0

:t10
86

AD845S

Typ

Min

45175

TuUu-Tmu.
INPUT OFFSET CURRENT
Initial

AD845K/B
Max

pA
nA

lO"
4.0

ldl

:t20
+10.5/-13
110

V
V
dB

pF

INPUT VOLTAGE NOISE

0.1 to 10 Hz
f= 10Hz
f = 100 Hz
f= I kHz
f=lOkHz
f= 100kHz

4
80
60
25
18
12

4
80
60
25
18
12

4
80
60
25
18
12

.,.V p"p
nVlv'Hz
nVlyHZ
nVlyHZ
nVlv'Hz
nV"/Hi

INPUT CURRENT NOISE

f=lkHz

0.1

0.1

0.1

pAlv'Hz

OPEN-LOOP GAIN

Vo - ±IOV
RLOAo"'2 k.o
RLOAo"'SOO

500
250

VlmV
VlmV
VlmV

n

200
100
70

n

±12.5

Tmin-Tmu:
OUTPUT CHARACfERISTICS
Voltage
Current
Output Resistance
FREQUENCY RESPONSE
Small Signal
Full Power Bandwidth'
Rise Time
Overshoot
Slew Rste
Settling Time

RLOAo"'SOO
Short Circuit
Open Loop

Unity Gain
Vo = ±IOV
R LOAO = 500

500
250

250
125
75

12.8

80

200
100
50

±12.5

±12.5
SO
5

SO
5

n

500
250

13.6

16

V
rnA

SO
5

16

13.6

n

MHz

16

1.75

1.75

1.75

20
20
100

20
20
100

20
20
100

V/.,.s

350
250

ns
ns
ns
ns

94

94,

MHz
ns
%

10 V Step
~AO = lOOpF

RLOAO =
to 0.01%
to 0.1%

soon

350
250

350
250

500

500

DIFFERENTIAL GAIN

f - 4.4 MHz

0.04

0.04

0.04

%

DIFFERENTIAL PHASE

f- 4.4 MHz

0.02

0.02

0.02

Degree

POWER SUPPLY
Rsted Performance
Operating Range
Rejection Rstio
Quiescent Current

±IS
±4.75
Vs=±Sto±ISV
to Tmu.

Tmil1

88

±IS
:t18

110
10

12

±4.75
9S

±IS
±18

113
10

±4.75

88
12

±18
110
10

12

V
V
dB
rnA

NOTES
'Input offset voltage specification. are guaranteed after 5 minute. of operation at TA = +2S"C.
2Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at T A = +.250(;.
'FPBW=slew rate/2", V peak.
'''S'' grade Tmln-Tmu are tested with automatic test equipment at TA = -5S"C and TA = +12S"C.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at fmal electrical test. Results from these tests
are used to calculate· DUtsoins quality level•.
Specifications subject to change without notice.

2-114 OPERA TIONALAMPLIFIERS

REV. A

AD845
ABSOLUTE MAXIMUM RATINGS I
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ±IS V
Internal Power Dissipation2
Plastic Mini-DIP . . . . . . . . . . . . . . . . . . . . . . 1.6 Watts
Cerdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Watts
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±Vs
Output Short-Circuit Duration . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . +Vs and -Vs
Storage Temperature Range
Q . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to + 150°C
N, R . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to + 125°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
NOTES
IStresses above those listed under "Absolute Maximum Ratings" may cause
pennanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure [0 absolute maximum rating conditions for extended periods may affect
device reliability.
'Mini-DIP package: aJA = lOO'Clwatt; cerdip package: aJA = 1l0'Clwan.

ORDERING GUIDE
Modell

Temperature
Range

Package
Option'

ADS4SJN
ADS4SKN
ADS4SJR'
ADS4SAQ
ADS4SBQ
ADS4SSQ
ADS4SSQ/SS3B

O°C to +70°C
O°C to +70°C
O°C to +70°C
-40°C to +SsoC
-40°C to +SsoC
-55°C to + 125°C
-55°C to + 125°C

N-S
N-S
R-S
Q-S
Q-S
Q-S
Q-S

NOTES
IUJ" and "S" grade chips are also available.
'N = Plastic DIP; Q = Cerdip; R = Small Outline Ie (SOlC). For oudine
information see Package Information section.
'Available in tape and reel packaging.

METALIZATION PHOTOGRAPH
Dimensions sbown in inches and (mm).
Contact factory for latest dimensions.

Ira;;;~

"l~~:=.J
+v

NUll NULL

SUBSTRATE CONNECTED TO +Vs

REV. A

OPERA TlONALAMPLlFIERS 2-115

•

AD845 - Typical Characteristics
2.r------r------T-----~~--~

2.

'5

'5

30

25

..
.'

~

j!:>

0"

!!j~

E~
zg

~~

,.

~~
~~

~~I

~

,.

+)./

Ii

V

V'

/

/

~

~,

~

20

II
:!: 15V SUPPLIES

g

'5

1/

~ ,.

RL = 2kfi

fA"" +Z5-c

0

V-VOUT

SUPPLY VOLTAGE- :!:Votts

Figure 1. Input Voltage Swing
VS. Supply Voltage

'2

:.--

I
I

--

,.

••

·~.------~-----7.,.~----~'5~--~ro

i

/

,

,.
7

~

7

i '

I..,

/
/

/

,

20

'5

f- ......

/

10- 1
-60 -40 -20

0.01

0

20

40

60' 80

TEMPERATURE -

100

120

140

7.

=---+---+----+--__1

••

750 ....

,
5.. r----+--~t_--_f--__I

r----+--''''''-'''''':I---_f-----'......;:::-I

~

'00'

10k

oc

,.M

,M

'OOM

FREQUENCY - Hz

Figure 6. Magnitude of Output
Impedance VS. Frequency

Figure 5. Input Bias Current VS.
Temperature

VS.

,... r------r------~----~----__,

25.

Figure 3. Output Voltage Swing
Resistive Load

f--

!2

;

..

,

1k

'00

Figure 4. Quiescent Current
Supply Voltage

I"

'00

VS.

,

,.

,

V
LOAD RESISTANCE - n

Figure 2. Output Voltage Swing
VS. Supply Voltage

SUPPLY VOLTAGE - ::tYotts

1

~

•,.

20

'5
5UPPLYVOlTAOE_ ::tVofts

17.0

........

........
.........

t'

50

I••

i, '..

,,-OUTPUT CURRENT

'k'k
+OUTPUT.........

CURRENT

~ ..........

5

I,. .

........

i'... ...........

...........
...........

z

~"

~

i

r-.... ........

15.5

t--..

WITH

HEAT SINK

.L-____-L____
-10

~

______

~

____

-5
COMMON·MODE VOLTAGE - Volts

Figure 7. Input Bias Current vs.
Common-Mode Voltage

2-116 OPERATIONALAMPLIFIERS

~

10

30
-80 -40 -20

~

0

20
40 80 80
TEMPERATURE _ OC

100

120 140

Figure 8. Short-Circuit Current
Limit vs. Temperature

-80 -40 -20

0

20

40

60

80

100 120

140

TEMPERATURE - "C

Figure 9. Unity-Gain Bandwidth
VS. Temperature

REV. A

AD845

,,

+'40
+120

i - - '""""-

·+100

,

Z

MARGIN~ r--

'\
GIN

+SO

9

~

,,

+BO

;;:

"I!;

""

'\

+40

'\
Vs =

:!: 15VSUPP~ES

-20
10

100

1k

10k

tOOk

FREQU~NCY -

+75

1M

+120

D

i

+60

0

10M

l,

. "5
Z

;;:

. §"
.ifill iii

+45" <;

I ,/"

Ie

+ 3D"
+15

0

+40

.

,

100M

'0

'5

SUPPLY VOLTAGE -

-20

20

10

:!: Volts

""

BO

~,
Ie

so

25

""

0.1%

o

'M

'OOk

'00'

'OM

'M

Figure 13. Common-Mode Rejection vs. Frequency

"-

I

V /1

II

1-,20

;!

l/
3AD

/,/
1k

10k

Figure 16. Harmonic Distortion
vs. Frequency

'" "

250

./

30D

350

400

-

./

100

~

i

IHARjOilC

FREQUENCY - Hz

REV. A

i

.....

t--

,

-130

'00

200

/

I '0

"

150

l,

~

I

100

110

~, '00
2ND HARMONIC

50

Figure 15. Output Swing and Error
vs. Settling Time

...

~,

~

SETTLING TIME - ns

,

Z -110

~~=~-

0.01%

!\

-'0 0

10M

Figure 14. Large Signal Frequency
Response

-'00

100M

0.01%

ERROR

INPUT FREQUENCY - Hz

FREQUENCY - Hz

//

0.1%

!\
'Ok

10M

V

40

1k

1M

II

\

=

tOOk

III

"'- l\.

RL "" 2kn
TA +25"C
Vs = ±15V

r'\

'00

10k

Figure 12. Power Supply Rejection
vs. Frequency

1,\

= +25"<:

20

1k

'0

Vs = ::t15V
VCM '" 1Vp-p
T ...

100

SUPPl V MODULATION FREQUENCY - Hz

Figure 11. Open-Loop Gain vs.
Supply Voltage

IIII

"" ~

I • "~V SU~PLY

o

•

"- ~

V'

Hz

1'\

-SUPPLY

~
tUPPlV'" ~

+60

30

'00

'" "'.~

+20

D"

'20

"

+BO

~ 110

Figure 10. Open-Loop Gain and
Phase Margin vs. Frequency

IE

../

~

RL=2kll
TA = +25"C

IE

_15 0

.........

+'00

~

Z

,
,,
,
"'" "
I

+20

+'40

+SO"

·~AS:I\

r\..

~

120

+105°

'00k

'0

'00

lk

10k

,....

FREQUENCV - Hz .

Figure 17. Input Noise Voltage
Spectral Density

I
90

'M

-&0

4020020406080

100

120

140

TEMPERATURE - "C

Figure 18. Slew Rate vs. Temperature

OPERATIONAL AMPLIFIERS 2-117

AD845

.

NULL

,

+Vs

+Vs

6 'Jour

.

-V,

Figure 19. Recommended Power
Supply Bypassing

Figure 22a. Unity-Gain Follower

Figure 20. AD845 Simplified
Schematic

Figure 21. Offset Null Configuration

Figure 22b. Unity-Gain Follower
Large Signal Pulse Response

Figure 22c. Unity-Gain Follower
Small Signal Pulse Response

Figure 23b. Unity-Gain Inverter
Large Signal Pulse Response

Figure 23c. Unity-Gain Inverter
Small Signal Pulse Response

1kH

Figure 23a. Unity-Gain Inverter

2-118 OPERATIONALAMPLIFIERS

REV. A

Applying the AD845
MEASURING AD845 SETTLING TIME
The Figure 24 shows the AD845 settling time performance.
This measurement was accomplished by driving the amplifier
in the unity-gain inverting mode with a fast pulse generator.
The input summing junction was measured using false nulling
techniques.
Settling time is defined as:
The interval of time from the application of an ideal
step function input until the closed-loop amplifier output
has entered and remains within a specified error band.
Components of settling time include:
1. Propagation time through the amplifier
2. Slewing time to approach the final output value
3. Recovery time from overload associated with the slewing
4. Linear settling to within a specified error band.
These individual components can easily be seen in Figure 24.
Settling time is extremely important in high speed applications
where the current output of a DAC must be converted to a voltage. When driving a 500 0 load in parallel with a 100 pF capacitor, the AD845 settles to 0.1% in 250 ns and to 0.01% in
310 ns.

A HIGH SPEED INSTRUMENTATION AMP
The three op amp instrumentation amplifier circuit shown in
Figure 26 can provide a range of gains from unity up to 1000
and higher. The instrumentation amplifier configuration features
high common-mode rejection, balanced differential inputs and
stable, accurately defmed gain. Low input bias currents and fast
settling are achieved with the FET input AD845.
Most monolithic instrumentation amplifiers do not have the high
frequency performance of the circuit in Figure 26. The circuit
bandwidth is 10.9 MHz at a gain of 1 and 8.8 MHz at a gain of
10; settling time for the entire circuit is 900 ns to 0.01% for a
10 V step (Gain = 10).
The capacitors employed in this circuit greatly improve the
amplifier's settling time and phase margin.
+v,
+Vs~

....---:+:...:.

12- 1SpF

V+...1..''''F

v,.

-Vs~

+15V

COMM
-15V

CIRCUIT GAIN ::: 2::: +1

Figure 26. High Performance, High Speed Instrumentation Amplifier

Figure 24. Settling Characteristics 0 to 10 V Step
Upper Trace: Output of AD845 Under Test (5 VlDiv)
Lower Trace: Error Voltage (1 mVIDiv)

'"

7A13

'"
""

OSCILLOSCOPE

,.,

3 OP-AMP IN-AMP
Gain

RG

Small Signal
Bandwidth

to 0.01%

Settling Time

1
2
10
100

Open
2k
2260
200

10.9 mHz
8.8 mHz
2.6mHz
290 kHz

500 ns
500 ns
900 ns
7.5 ILS

1A1.

Note: Resistors around the amplifiers' input pins ueed to be small enough in
value so that the RC time constant they form, with stray circuit capacitance,
does not reduce circuit bandwidth.

Table I. Performance Summary for the Three Op Amp
Instrumentation Amplifier Circuit

.¢.

100pF

Figure 25. Settling Time Test Circuit

REV. A

OPERATIONALAMPLIFIERS 2-119

II

Applying the AD845
DRIVING THE ANALOG INPUT OF AN NO
CONVERTER
An op amp driving the analog input of an AID converter, such
as that shown in Figure 29, must be capable of maintaining a
constant output voltage under dynamically changing load conditions. In successive-approximation converters, the input current
is compared to a series of switched tria1 currents. The comparison point is diode clamped but may deviate several hundred
millivolts resulting in high frequency modulation of AiD input
current. The output impedance of a feedback amplifier is made
artificially low by the loop gain. At high frequencies, where the
loop gain is low, the amplifier output impedance can approach
its open-loop value. Most
amplifiers exhibit a minimum
open-loop output impedance of 25 n due to current limiting
resistors. A few hundred microamps reflected from the change
in converter loading can introduce errors in instantaneous input
voltage. If the AiD conversion speed is not excessive and the
bandwidth of the amplifier is sufficient, the amplifier's output
will return to the nominal value before the converter makes its
comparison. However, many amplifiers have relatively narrow
bandwidth yielding slow recovery from output transients. The
AD845 is ideally suited to drive high resolution AiD converters
with 5 ...s on longer conversion times since it offers both wide
bandwidth and high open-loop gain.

Ie

Figure 27. The Pulse Response of the Three Op Amp
Instrumentation Amplifier. Gain = 1, Horizontal Scale:
0.5 mslOiv; Vertical Scale: 5 VlOiv

Figure 28a. Settling Time of the Three Op Amp Instrumentation Amplifier. Horizontal Scale:200 nslOiv; Vertical
Scale, Positive Pulse Input: 5 VIOiv; Output Settling:
1 mVIOiv

±10V

ANALOG
INPUT

Figure 29. A0845 As AOC Unity Gain Buffer

Figure 28b. Settling Time of the Three Op Amp Instru-·
mentation Amplifier. Horizontal Scale: 200 nslOiv; Vertical
Scale, Negative Pulse Input: 5 VIOiv; Output Settling:
1 mVIOiv

2-120 OPERA TIONALAMPLIFIERS

REV. A

450 V/fJ-s, Precision,
Current-Feedback Op Amp
AD846 I

~ANALOG

WDEVICES
FEATURES

CONNECTION DIAGRAM

AC PERFORMANCE
Small Signal Bandwidth: 80 MHz (Av -1)
Slew Rate: 450 V/ ..s
Full Power Bandwidth: 6.S MHz at 20 V pop,
RL =5000
Fast Settling: for 10 V Step: 110 ns to 0.01%,
SO ns to 0.1%
Differential Gain: <0.01% @ 4.4 MHz
Differential Phase: <0.028° @ 4.4 MHz
Total Harmonic Distortion (THO): 0.0005% @ 100 kHz
Open-Loop Transimpedance: 200 MO
Input Voltage Noise: 2 nV/YHz

=

DC PERFORMANCE
Input Offset Voltage: 75 ..V max (B Grade)
Input Offset Drift: 3.5 ..V/oC max (B Grade)
Quiescent Supply Current: 6.5 mA max
APPLICATIONS
High Speed DAC Buffers
Multiflash ADC Error Amplifiers
Flash ADC Buffers
Coaxial Cable Drivers
High Performance Audio Circuitry
Available in Plastic Mini-DIP, Hermetic Cerdip, and
Hermetic Metal Can Packages
MIL-STD-S83B Parts Available
PRODUCT DESCRIPTION
The AD846 is a monolithic, very high speed operational amplifier offering high performance. Although technically classed as
a current-feedback or transimpedance amplifier, it may be used
in much the same way as traditional op amps while providing
significant performance benefits. Employing Analog Devices'
junction isolated complementary bipolar (CB) process, the
AD846 achieves true "12-bit" (0.01%) precision on critical ac
and dc parameters, a level of performance unmatched by amplifiers fabricated using either the dielectrically isolated (DI) or
other bipolar processes.
The AD846 offers significant advantages over conventional high
speed .()perational amplifiers. It maintains a nearly constant
bandwidth and settling time to 0.01% over a wide range of
closed-loop gains. This makes the AD846 ideal for amplifying
the residue in multiple-pass analog-to-digital converters.

REV. A

Plastic Mini-DIP (N) Package
and
Cerdip (Q) Package
Top View

NC = NO CONNECT

Other advantages include: low input errors and high open-loop
transresistance (200 MO) into a 500 0 load, ensuring true 12-bit
dc accuracy for closed-loop gains from -I to gains greater than
-100. This combination of ac and dc performance makes the
AD846 an excellent choice for buffering precision high speed
DACs and flash ADCs.
The AD846 is available in three performance grades. The
AD846A and AD846B are rated over the industrial temperature
range of -40°C to +85°C. The AD846S is rated over the full
military temperature range of - 55°C to + 125°C and is available
processed to MIL-STD-883B, Rev C.
Extended reliability PLUS screening is available specified over
the commercial temperature range. PLUS screening includes
168 hour bum-in as well as other environmental and physical
tests. The AD846 is available in two types of 8-pin package:
plastic mini-DIP and hermetic cerdip. "A" and "S" grade chips
are also available.
PRODUCT HIGHLIGHTS
1. The AD846 achieves settling times of 110 ns to 0.01% for
gains of -I to -10, with a 450 V/floS slew rate, while consuming only 5 rnA of supply current.
2. For closed-loop gains of -I to -100, the high speed performance of the AD846 is achieved without sacrificing full
12-bit dc precision.
3. The AD846 is well suited to line driver and video buffer
applications where the properties of low distortion and high
slew rate are required.

OPERATIONALAMPLIFIERS 2-121

II

AD846-SPECIFICATIONS (@ +25°C and ±15 V dc, unless otherwise noted)
Model

Conditions

Min

INPUT OFFSET VOLTAGE'
Initial

25
50
O.S

Tmin-Tmax
vs. Temperature
vs. Supply (PSRR)
Initial

AD846A
Typ
Max

Min

200
350
5

AD846B
Typ
Max
25
50
O.S

Min

75
125
3.5

AD846S
Typ

Max

Units

25
100
I

200
350
5.5

",V
",V

5 V-IS V2

Tmin-Tmax

vs. Common Mode (CMRR)
Initial

110
110

125
120

120
116

125
120

110
94

125
116

dB
dB

110
110

125
120

120
116

125
120

110
94

125
116

dB
dB

VCM = ±IO-V

Tmin-Tmax

INPUT BIAS CURRENT'
- Input Bias Current
Initial

Tmin-Tmax
vs. Temperature
vs. Supply
Initial

",vrc

ISO
450
6

450
1200
20

100
400
6

250
750
17

150
1000
9

450
1500
20

nA
nA
nArC

9
11

15
20

9
11

10
15

9
11

15
25

nAIV
nAIV

5
5

10
IS

3
3

5
7

5
5

10
20

nAIV
nAIV

3
4
IS

15
20
SO

3
4
IS

5
7
45

3
5
15

15
20
SO

",A
",A
nArC

5
5

15
20

5
5

10
15

5
5

15
20

nAIV
nAIV

5
5

15
IS

3
3

10
10

5
5

15
20

nAIV
nAIV

5 V-ISV2

Tmin-Tmax

vs. Common Mode
Initial

VCM=±IOV

Tmin-Tmax

+ Input Bias Current
Initial

Tmin-Tmax
vs. Temperature
vs. Supply
Initial

5 V-18 V2

Tmin-Tmax

VCM = ±IO V

vs. Common Mode
Initial
Tmin-Tmax

INPUT CHARACTERISTICS
Input Resistance
-Input
+ Input
Input Capacitance
-Input
+ Input
INPUT VOLTAGE RANGE
Common Mode
INPUT VOLTAGE NOISE
Input Current Noise
-Input
+ Input
OPEN LOOP
TRANSRESISTANCE

OUTPUT CHARACTERISTICS
Voltage
Current
Output Resistance
FREQUENCY RESPONSE
Small Signal Bandwidth
(-3dB)
FuIj Power Bandwidth'
Rise Time
Overshoot
Slew Rate
Settling Time
10 V Step, Ay

=-

TOTAL HARMONIC
DISTORTION'

I

50
10

50
10

50
10

n
kn

2
2

2
2

2
2

pF
pF

±IO

±IO

±IO

V

F= I kHz

2

2

2

nV!\ Hz

1kHz
1 kHz

20
6

20
6

20
6

pAl\ Hz
pAl,Hz

200

Mn
Mn

VOUT = ±IOV
RLOAD = 500 n
Tmi~-Tmax
RLOAD = 500 n
Short Circuit
Open Loop

100
50

200

±10

150
75

200

±10

100
50
±10

V

65
16

65
16

65
16

rnA

Ay = -IRp= Ik
Av = -10 RF = S75 n
Ay = -30 RF = 875 n
VOUT = 20 V p-p
R, = 500n
Ay =-1
Ay =-1
Ay =-1

SO
31
15

SO
31
.15

SO
31
15

MHz
MHz
MHz

6.S
10
20
450

6.S
10
20
450

6.S
10
20
450

MHz
ns
%
VI",s

to 0.1%
to 0.01%

SO
110

SO
110

SO
110

ns
ns

F = 100kHz

0.0005

0.0005

0.0005

%

2-122 OPERATIONALAMPLIFIERS

n

REV. A

AD846
Min

0.01

0.01

0.01

%

DIFFERENTIAL PHASE

F - 4.4 MHz, RL -

0.028

0.028

0.028

Degree

:±: 15

:±:S

±I8
6.5

5

Tmin-Tmax

72

TRANSISTOR COUNT

Min

±5
5

Max

Units

F - 4.4 MHz, RL - 100

:±: 15

Max

AD846S
Typ

DIFFERENTIAL GAIN

n
100 n

Max

AD846B
Typ

Conditions

POWER SUPPLY
Rated Performance
Operating· Range
Quiescent Current

Min

AD846A
Typ

Model

±I8

V
V

7

mA

:±: 15

±I8
6.5

±5
5

72

72

NOTES
lInput Offset Voltage Specifications are guaranteed after 5 minuies at TA = +25°C.
'Test Conditions: +Vs = 15 V, -Vs = 5 V to 18 V and +Vs = 5 V to 18 V, -Vs = 15 V.
3Bias Current Specifications are guaranteed maximum after 5 minutes at T A = +25°C.
4FPBW = Slew Ratel2 'If VPEAK'
STotal Harmonic Distortion.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at final electrical test.
Results from those tests are used to calculate outgoing quality levels.
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS l
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ± IS V
Internal Power Dissipation 2
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . I. 5 W
Cerdip Package . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Common-Mode Input Voltage, Max Safe . . . . . . . . . IVsl -3 V
Output Short Circuit Duration . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . ± I V
Continuous Input Current
Inverting or Noninverting . . . . . . . . . . . . . . . . . . 2.0 rnA
Storage Temperature Range Q
-65°C to + 150°C
Storage Temperature Range N . . . . . . . . . . -65°C to + 125°C

ORDERING GUIDE

Modell

Temperature
Range

Package
Option2

ADS46AN
ADS46BN
ADS46AQ
ADS46BQ
ADS46SQ
ADS46SQ/SS3B

-40°C
-40°C
-40°C
-40°C
-55°C
-55°C

N-S
N-S
Q-S
Q-S
Q-S
Q-S

to +SsoC

to
to
to
to
to

+SsoC
+SsoC
+SsoC
+ 125°C
+ 125°C

NOTES
luA" and "S" grade chips are also available.
'N = Plastic DIP Package; Q = Cerdip Package. For outline information see
Package Information section.

REV. A

Operating Temperature Range
ADS46A1B . . . . . . . . . . . . . . . . . . . . . . -40°C to +SsoC
ADS46S . . . . . . . . . . . . . . . . . . . . . . . -55°C to + 125°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . +300°C
NOTES
lStresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only; the functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
2Maximum internal power dissipation is specified so that T J does not exceed
+175°C at an ambient temperature of +25"C, derate cerdip (Q) package at
8.7 mwrc and plastic (N) package at 10 mWrC.
Plastic Package: 0IA = IOO°ClWatt, 0IC =33°CIW.
Cerdip Package: 0IA = 110°ClWatt, 0IC = 30"C/W.

METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
Consult factory for latest dimensions.
+Vs
7

-INPUT

0.087

rli~=;;;;r.r.J~ii~;:~

6 OUTPUT

SUBSTRATE
CONNECTED
TO

'r,~"" ~--------""'"f"I"'--., ·:.~ro.
OPERA TlONAL AMPLIFIERS 2-123

•

AD846 - Typical Characteristics
20

~,

V
o

,
-7

20

/

o

V

I

/

~

0

,.

A

Rl =2kU
+2!i"C

~

5

~

i"

,.

10

20

SUPPLY VOLTAGE - ±Volts

..
!!;

~
J!

4

,

~

~

0

:15 VOLT SUPPLIES

>

~

I .......

::>

3.
30

/'

2•

~

~,

J

20

II

,.

~

~

-

II

r- 1-- ....

:t:

.......

20

15

!;
I!:
::>

10

II

15 VOLT SUPPLIES

RL=500n

Z5

0

>

10

0

20

"

Figure 3. Quiescent Current
vs. Supply Voltage

15 VOLT SUPPLIES

~

V
i""'"

VV

10

SUPPLY VOLTAGE - :tValts

II

:!:

i""'"~

.

~

o

Figure 2. Output Voltage Swing
vs. Supply

30

.
!.

o
20

SUPPLY VOLTAGE - :tVohs

3.

~

,.

10

Figure 1. Input Voltage Swing
vs. Supply

~

"

/

~

I!i

~

+VOUT

10

~

+2Sec

~

"'\.

'\
!\

0

II

V1

-60 -40 -20

0

+20 +40 +60 +80 +100 +120 +140

TEMPERATURE - "C

Figure 4. Quiescent Supply Current
vs. Temperature

.

I~
..

r-

/

150

100

/

~

3.1

""I

3.0

i

Vs= :l:16V

RL =500n
Yo= -V.+4V. +V.-4V

I

10

4.

15

SUPPLY VOLTAGE- :tVolts

Figure.7. Open-Loop Transimpedance vs. Supply

2-124 OPERA nONALAMPLIFIERS

20

1M

100k

100M

10M

INPUT FREQUENCY - Hz

Figure 6. Large Signal Frequency
Response

210

',!

r-- r--

i

i

;i!

50

10k

n

3.2

200

~

1k

LOAD RESISTANCE -

Figure 5. Output Voltage Swing vs.
Resistive Load

250

i,

100

10

----

Vs= ::!:15V

+25"C
2.9

2.8

2.7
-10

-.

,

190

i.

::> 170

"~

..
i

150

~

~

SlZ

130

110

10

COMMON·MODE VOLTAGE - Volts

Figure 8. Positive Input Bias Current
vs. Common-Mode Voltage

V

-10

V
-.

V

/

Vs= :!:15V

+Z5"C

10

COMMON·MODE VOLTAGE - Volts

Figure 9. Negative Input Bias Current
vs. Common-Mode Voltage

REV. A

AD846
,..

-1.5

i

e~

~ -2.0
~

~

...,

I'-..

-2.5

'" "'"

Z

5

-3.0

Iz

0-3.5

,

...
~ -4.0

i

I-

-5.0

~
~

-5.5
-60 -40 -20

0

2.S

+120

2 .•

+, ..

"Ii:z ,..
~
, ,..

.,

"-

1'\ J

--

~
a:

..S

::>
u

.,
...~

~ -0.5

;!:

I-

--

-1.0
-60 -40 -20

+20 +4D +60 +80 +100+120+140
TEMPERATURE _ ·C

.........

"-

+80

vV

V V

iI!
Ie

+ ••
+40
+2.

-20
0

""
""I"
Rf =lkU

~

;!:

!!iu -4.5

i

+140

+20 +40 +60 +80 +100+120+140

10

100

lk

TEMPERATURE - ·C

Figure 10. Positive Input Bias
Current vs. Temperature

tOOk

1M

.,

40

2.S ""'''''''''''-'''TIT''T''TT1rr'1--rI'TrTl''Tl'rr'TT'TI

R~ = toon

IIIII
RL "" lkll

Il!

--~

%

~

+8.

~

" '"

a: + ••
a:

+4.

-20
10

100

lk

10k

tOOk

1M

~

r-.

10M

1.5

i

H-HI*++HH-HHt-++HIt--II+tIt++tH

Figure 14. Input Noise Voltage
Spectral Density

..
"- r-....

'00

~

~

...
:: ...
;.

'" ""

;.

,

so

Ii:0

..

2.
-60 -40 -20

o

..... ~

I'~

+20 +40 +60 +80 +100 +120+140

Figure 16. Short Circuit Current
Limit vs. Temperature

~,

i'-.........

i

~

300

..
..

o

RISING

+20 +40 +60 +80 +100+120+140
TEMPERATURE _ "C

Figure 17. Slew Rate vs.
Temperature

SLEW RATE

/

V/

/V
//
JV

240

'80

'20

••

250
-60 -40 -20

'OM

,..-

,
..:I. ,

r---.. i'--

..

TEMPERATURE - "C

REV. A

.......

,M

V ~~

420

~
"iiia:z ,

r-.....

:z: 40

'Ok
FREQUENCY - Hz

...

[!!

~

...

,

1k

...

Figure 15. Inverting Input Noise
Current Spectral Density

.S.

a:
a:

"::>t:
~

,. ,..

FREQUENCY - Hz

,

::>

r-.

1.0,L.-'--.LJ.J,Uo.
••....L...u.,IL.-'--u..u..,!"·
••....L...u.,.....-.J-J..uI'M--'-.J..':'J.lOM

100M

Figure 13. Common-Mode Rejection
vs. Frequency

,

'\

w

FREQUENCY - Hz

e so
E

\

H-+'f++o+~H+H+-+~IH+H++~

o

"

+2.

2.0

I.,

RF =lkU

~

:IE
u

100M

Figure 12. Power Supply Rejection
vs. Frequency

+120
+100

10M

FREQUENCY _ Hz

Figure 11. Negative Input Bias
Current vs. Temperature

+140

10k

II

~

t/ V

FALUNG
SLEW RATE

~

.

,

200

300

INPUT ERROR SIGNAL - mV

...

•••

(AT SUMMING JUNCnoNI

Figure 18. Slew Rate vs. Input
Error Signal

OPERATIONAL AMPLIFIERS 2-125

A0846-Typical Characteristics, Inverting Gain of 1
+3

lkll

SOOU LOAD

I

5\1
lkU

"1-r~

lkll

I

r~

*

Rp
10011

-•
I
, i

ri

I

~III

~.

~ =

I

iIIOij

-.

(OPTIONAL)

I

I

'PLUS 2pF SCOPE
PROBE CAPACITANCE

i.

I ..

-

I'

VOUT

'II,

SOn

!

~I\

= I~

r--..
'\

-3

501 LOAD
-9

-12

i.,. -

~

~

-6

:1:15 VOLT SUPPt..IES
AF

=,
1

-'"'00'

kll.GAIN =-1

i', i 1."['

1

,M

,.M

100M 200M

INPUT FREQUENCY - Hz

Figure 19a. Inverting Amplifier,
Gain of 1

+270

ri '\

+180

Ii

"0

son

X
,

.,

11 ~
LOAD

-105
2 VOLTS
Rl =5001.
Cl =20pf

z

\

i

0

;::

~

'"

~

:15 VOlT SUPPLIES

t-

-310
lOOk

It. = 1 kn. GAIN = -1

"it, ,
1M

-135

-145
10M

100M

........

Figure 21. Phase Shift vs. Frequency

I
V

10

50

/

~

I
2ND HARMONIC

/
100k

I
t

!Ii

I

V

"

15

SUPPLY VOLTAQE :Votts

Figure 24. 3 dB Bandwidth vs.
Supply Voltage

2-126 OPERATlONALAMPLlFIERS

20

20

40

••

I
~

\

, I.

:IE

~
~
z

.
,

/

80

~

V

75

/

~

0.1

10k

lOOk

1M
FREQUENCY - Hz

10M

Figure 25. Output Impedance
vs. Frequency

100M

\ 1
\1

80
80
100
120
SETTLING TIME - ns

RL =500J!
~ 15V SUPPUES

:l!

1

-

140

180

Figure 23. Settling Time
vs. Step Size

70

10

~

0

/

:t15 VOLT SUPPLIES

I

0.1% 1\0.01%

.

.0.01

o

\l

Figure 22. Total Harmonic Distortion
vs. Frequency

e,

RL =500U
+25'1:

\ \
\".

-6

-I

100

v

I I

Rs=lkU RF =lkn.----,-

-,.

10k
FREQUENCY - Hz

0.01%

0.1%

ERROR
-2
-4

:f

/'"

GAIN OFI_l

::l

I

,.

I

~,
51

V

INPUT FREQUENCY - Hz

90

~ .....

~

Z

:i
-270

INPUT L E V y

/ I I I
1 V I I

"'~

/ . r d HARMONIC

0
:IE -125

-180

II
,m.

-115

II

"' -90

i

,.

-95

,;

~.~~, Loio

Figure 20. Normalized Output Amplitude vs. Frequency vs. Load

Figure 19b. Large Signal Pulse
Response, Gain of -1

..

/

/

-

'\

\

/

II'

-60 -40 -20

0 +20 +40 +10 +80 +100 +120+140
TEMPERATURE - "C

Figure 26. 3 dB Bandwidth
Temperature

VS.

REV. A

Typical Characteristics, Inverting Gain of 10-AD846
+3

I

90911

!II

~...nLOAD

I

~
"

-3

~O

-6

i

90.911

Rp
4711

son LOAD
:I:

~c

-12

Z

-15

~

(OPTIONAL)

15 VOLT SUPPLIES

-9

'PLUS 2pF SCOPE
PROBE CAPACITANCE

\

\

\,

•

\

-18
lOOk

1M

10M

100M

INPUT FREQUENCY - Hz

Figure 27a. Inverting Amplifier,
Gain of 10

Figure 28. Normalized Output Amplitude vs. Frequency vs. Load

Figure 27b. Large Signal Pulse
Response, Gain of 10

+270

10

+180

~

-===

+90

~

~

~

I

.iE

~-+----+-+-1+--+--4I''-+-A--l

-115

I--t-.--+-t-t+---,Y----Y--+-+-l

i

~-+--- +--l-fE-.,A'---+-+-H

SJ

L~AD

E
UI

-105

Z

~~r" e~

Ii:

;:

~

:1:15 VOLT SUPPLIES

-90

~

V

-125

J / /
GAIN OF -10

ERROR

5

-2

~

~ - 135
-270

I--+--:>"'!;>",,+-t+--+--+-+-+-l

~

-6

Rs=87.SU RF ",,815n

\ \\.

-4

~

I\:t- ("'Y~t

1M

100M

10M

-145'-_-'-_-'_-'-......._ _-'-_-'--'-'....
lk
10k
tOOk

INPUT FREQUENCV - Hz

0

f-"

/

/

:IE

rJ

,.

~

:1

"I!:

~I

/

0.1

0.01
SUPPLY VOLTAGE- ±Volts

I'
10k

tOOk

1M

10M

FREQUENCY _ Hz

VS.

28

Z

0

20

I

:!: fSV SUPPLIES

30

I;

I-

15

100

1

V

I

I

25

REV. A

Rl =500n

:!!

z

"

80

32

IL

I

Figure 32. 3 dB Bandwidth
Supply Voltage

60

120

140

160

3.

10

Rl =500U
+25"C

10

40

Figure 31. Settling Time vs.
Step Size

100

/

20

SETTLING TIME - ns

Figure 30. Harmonic Distortion
vs. Frequency

33

31

I'1\.

-10

FREOUENCY _ Hz

Figure 29. Phase vs. Frequency
vs. Load

\.~

\

-8
-360
tOOk

""'

I{~~
K~
o'
o'

I

~

-180

I
W

!.!

l~~b"'"

w

UI

I I /

Figure 33. Output Impedance
vs. Frequency

100M

/

26

.

V

/

.......

,

l\

./

22
-60 -40 -20

0

+20 +40 +60 +80 +100 +120+140
TEMPERATURE - '"C

Figure 34. 3 dB Bandwidth vs.
Temperature

OPERA T10NAL AMPLIFIERS 2-127

Applying theAD846
POWER SUPPLY CONSIDERATIONS
The power supply connections to the AD846 must maintain a
low impedance to ground over a bandwidth of 40 MHz or more.
This is es~cia1ly important when driving a significant resistive
or capacitive load, since all current delivered to the load comes
from the power supplies. Multiple high quality bypass capacitors
are recommended for each power supply line in' any critical application. A 0.1 .... F ceramic and a 2.2 .... F electrolytic capacitor
as shown in Figure 35 placed as close as possible to the amplifier (with short lead lengths to power supply common) will assure adequate high frequency bypassing, in most applications. A
minimum bypass capacitance of 0.1 .... F should be used for any
application.
'

)--
Q,

Figure 40. Op Amp Three-Terminal Model

0

e---

9

@

'"9u

A more detailed examination of the closed-loop transfer function
of the AD846 results in the following equation:

.:±
R,

AD8.6
= :olOkll

r,
i,

AD846

,

.'\.R,

r-.. I,

\

10

~

-

~

RH~~ll~ e--

S~~~~E -""
MODEL

) A~8il

I

1

Closed-Loop Gain Gis)

1M

lOOk

7lkll

'(

10M

\
,

.\
100M

3dB BANDWIDTH - Hz

Compare this to the equation for a conventional op amp:

Closed-Loop Gain Gis)

where: CCOMP is the internal compensation capacitor of the amplifier; gM is the input stage transconductance of the
amplifier.
In the case of the voltage amplifier, the closed-loop bandwidth
decreases directly with increasing values of (1 + RF/R s ), the
closed-loop gain. However, for the transimpedance amplifier,
the situation is different. At low gains, where (I + RF/Rs) RIN
is small compared to R F, the closed-loop bandwidth is controlled by the internal compensation capacitance of 7 pF and the
value of R F, and not by the closed-loop gain. At higher gains,
where (1 + RF/Rs) RIN is much larger than R F, the behavior is
that of a conventional operational amplifier in which the input
stage transconductance is equal to the inverting terminal input
impedance of the transimpedance amplifier (R IN = 50 0).

REV. A

Figure 41. Closed-Loop Voltage Gain
Various Values of RF

VS.

Bandwidth for

For the case where RF = I kO and Rs = 100 0 (closed-loop
gain of -10), the closed-loop bandwidth is approximately
28 MHz. It should also be noted that the use of a capacitor to
shunt R F, a normal practice for stabilizing conventional op
amps, will cause this amplifier to become unstable because the
closed-loop bandwidth will increase beyond the stable operating
frequency.
A similar approach can be taken to calculate the noise performance of the amplifier. A simplified noise model is shown in
Figure 42.
The equivalent mean-square output noise voltage spectral
density will equal:
V ON2 =IRF

+

INN)2

+

(I

4kT RF(~: + I)

OPERATIONALAMPLIFIERS 2-129

II

Applying the AD846
Where:
Rp is the external resistance placed in series with the
noninverting input
RF is the feedback resistor
Rs is the source resistor
INN is the noise current in the inverting input
INP is the noise current in the noninverting input
VN is the input noise voltage.

(RF = I kO, Rs = 10 0) it will be 4 MHz. At gains of 3 or
greater, a small capacitor (2 pF-5 pF) connected across the
feedback resistor will help reduce overShoot; but when operating
at noninverting gains below 3, this same capacitance will cause
instability.
+V,

Typical values for these parameters (@ I kHz) in pA/\IHz are:
INN = 20, IpN = 6, VN = 2.
Or, referring to the signal input, the equivalent mean-square
input voltage noise is:

vii

= (R F INN)2

(1 + ~:Y +
+4
(1+ ~:)

+

[VN2

(Rp INP)2+4 kT Rp]

kT Rs

Resistor Rp is required for both inverting and noninverting (follower) operation, to insure stable operation. The amplifier's
noninverting input current (flowing through Rp of 100 0) will
typically add less than 300 ....V to the AD846's input offset voltage. This can be trimmed-out using the optional network shown
in Figure 44. The following table gives recommended values
for Rp.

Supply Voltage

Gain(R~)

Recommended
Value for Rp

6 V to IS V
6 V to 15 V
6 V to 15 V
5V
5V

1-10
10-20
20-200
1-10
10-200

1000
470
00
47 n
00

Figure 43. AD846 Noninverting Amplifier Configuration
USING THE COMPENSATION PIN OF THE AD846
Additional compensation may be provided for the AD846 by
applying an external capacitance between Pin 5 and analog
ground (Figure 44). The nominal value of the AD846's internal
compensation capacitor is 7 pF. For a given value of feedback
resistance (RF), any added external capacitance reduces the amplifier's slew rate and bandwidth proportionally.

INN

Figure 44. AD846 Inverting Amplifier Showing External
Compensation Connection, Rp and Optional Vas Trim

Figure 42. Op Amp Simplified Noise Model
NONINVERTING GAIN OPERATION
'Ihe AD846 can be used as a noninverting amplifier or voltage
follower, operating at gains between 1 and 200. A minimum
value of RF eqnal to 1 kO should be employed. For low gains (1
to 2), the input signal should be applied to the AD846's noninverting input through a 1000 series resistor; this will help reduce peaking. The best transient response will occur when the
amplifier's output level is below 5 V peak to peak.
At closed-loop gains of 3 or more, the input resistor is not required unless peak signals greater than 3 V will be applied. The
amplifier's bandwidth can be determined by using the inverting
amplifier's bandwidth equation or from Figure 41. For example,
at a gain of + 10 (RF = 1 kO, Rs = 100 0) the bandwidth of
the AD846 will be approximately 33 MHz; at a gain of + 100,

2-130 OPERATIONAL AMPLIFIERS

In addition to providing for external compensation, Pin 5 may
be used to clamp the output of the amplifier, as shown in Figure 45. The output can be clamped anywhere within the output
range (approximately ± 10 V) of the amplifier. The input should
also be clamped as a precaution against damaging the amplifier's
input transistors.
R,

OUTPUT

POSmVE (DC) ClAMPING
VOLTAGE
NEGATIVE (DC) CLAMPING
TYPE HP2835
VOLTAGE
DIODES

Figure 45. AD846 Used as a Clamped Amplifier

REV. A

A0846
This compensation node may also be used as an additional output terminal as in the precision transconductance amplifier application of Figure 46.

v,.

(±10V maxi

lOUT

=-O.1mAlVOLT

Figure 46. A Precision Transconductance Amplifier
The AD846 can be used in either the inverting transconductance
mode as shown in Figure 46, or in a noninverting mode with Rs
grounded and VIN applied to the noninverting terminal. The
current output is essentially constant over a compliance range of
± 10 V at the compensation node. The output current (from Pin
5) is limited to about ± I mA due to internal saturation. Under
these circumstances the normal output pin provides a buffered
version of the compensation node output voltage. Output load
impedance of 500 n or greater will not affect the accuracy of the
transconductance conversion.

THE AD846 IN A 2 MHz, 12-BIT SUBRANGING AID
CONVERTER CIRCUIT
The combination of fast settling times at high gains and low dc
errors make the AD846 ideal for use as an error amplifier in
high speed, 12-bit subranging A-D applications. In the circuit of
Figure 47, an AD842 serves as an input amplifier. First pass
conversion is accomplished, in a straightforward manner, determining the top 7 bits. The latch then holds these top 7 bits
which are applied to a 7 bit, 12-bit accurate DAC and also to
the highest 7 bits of the adder (note that a sample-and-hold
should be used ahead of this converter to minimize errors due to
its 500 ns acquisition time). In the second pass, the input
switches S I and S2 and S3 are set to state 2. The DAC output is
then subtracted from the input signal and the resulting difference is then amplified by an AD846 gain of 32 follower. This
gain, together with a 1I64th scale offset, insures a unipolar residue which can be converted by the flash A-D. Conversion is
accomplished via switches S1, S2 and S3 in state 1. Switch S 1
connects the input signal of the AD846 residue amplifier to
ground which minimized overload recovery tinIe.

THE AD846 AS AN OPEN-LOOP LEVEL SHIFTER
The AD846 can also be used for open-loop level shifting. As
shown in Figure 48, resistor Rs is used to develop an input current which is proportional to the input voltage, VIN • This current flows from the compensation node (Pin 5) developing a
voltage across resistor Re (Re is equal in value to resistor Rs)
which, rather than being grounded, has one end tied to reference voltage V2. The voltage appearing at Pin 5 is, therefore,
voltage V IN plus voltage V2 and will directly follow changes in
V IN • By scaling resistor Re, a level shift with voltage gain can
be produced.
In addition, the normal voltage output at Pin 6 is approximately
equal to the voltage at Pin 5 thus providing a low impedance,
buffered output for the level shifter.

v"'"

(BUFFEREDI

v,.

VOUT

(UNBUFFEREDI
-Vo

Figure 48. AD846 Connected as a Level Shift Amplifier

THE AD846 AS A HIGH SPEED DAC BUFFER
The AD846 will enable the AD568 12-bit DAC to develop a
10 V output step which settles to within 0.025 percent of its
final value in about 100 ns. This AD8461AD568 combination is
shown in the circuit of Figure 49. Correct power supply decoupiing is essential: a 2.2 ...F tantalum capacitor connected in parallel with a 0.1 ... F to 0.01 ... F ceramic disc capacitor is usually
sufficient. These should be placed as close to the power supply
pins as possible. Also, a ground plane should be employed; this
ensure that there is a low inIpedance signal path to ground
which allows the fastest possible output settling. In 12-bit systems with the AD846 operating at gains of 10 or less, inadequate supply decoupling can cause the output settling to degrade
from 100 ns to as much as 300 ns, with a 10 V output step
applied.

'""

RESULT

SWITCH POSITIONS:

1 '" FIRST PASS,MSBTO liT 7
Z K 2ND PASS. lIT 7 TO LSB.
PlU5OVERlAPBrTS •• l
'R1 AND RWI:' RATIO TO 0.0''11. 011 aenER

Figure 47. Block Diagram of a 2 MHz, 12-Bit Subranging
AID Converter

REV. A

Figure 49. The AD846 Serving as a DAC Buffer

OPERA T10NAL AMPLIFIERS 2-131

•

2-132 OPERATIONALAMPLIFIERS

~ANALOG

WDEVICES

High Speed, Low Power
Monolithic Up Amp
AD847 I

FEATURES
50 MHz Unity Gain Bandwidth
4.8 mA Supply Current
300 VI fJ.s Slew Rate
65 ns Settling TIme to 0.1% for a 10 V Step
0.04% Differential Gain
0.19" Differential Phase
Drives Capacitive· Loads
DC Performance
5.5 V/mV Open-Loop Gain into a 1 kG Load
1 mV max Input Offset Voltage
Performance Specified for ±5 V and ±15 V
Operetion
Available in Plastic. Hermetic Cerdip and
Small Outline Packages; Chips and
MIL-STD-883B Processing Available
Available in Tape and Reel in Accordance with
EIA-481A Standard
Dual Version Available: AD827
APPUCATIONS
Unity Gain Buffer
Cable Drivers
8- and 10-Bit Deta Acquisition Systems
Video and RF Amplification
Signal Generators
PRODUCT DESCRIPTION
The AD847 is a high speed, low power monolithic operational
amplifier. The AD847 achieves its combination of fast ac and
good de performance by utilizing Analog Devices' junction isolated complementary bipolar (CB) process. This process enables
the AD847 to achieve its high speed while only requiring
4.8 rnA of current from the power supplies.
The AD847 is a member of Analog Devices' family of high
speed op amps. This family includes, among others, the AD848,
which is stable at a gain of five or greater, and the AD849,
which offers 725 MHz of gain bandwidth at gains of 25 or
greater. For more demanding applications, the AD840, AD841
and AD842 offer even greater precision and greater output current drive.

CONNECTION DIAGRAM

•
NC = NO CONNECT

Plastic DIP (N), Small
Outline (R) and
Cerdip (Q) Packages
APPLICATION HIGHLIGHTS
1. The high slew rate and fast settling time of the AD847 make
it ideal for all types of video instrumentation circuitry, fast
DAC and flash ADC buffers, and line drivers.
2. As a buffer, the AD847 offers a full-power bandwidth of
30 MHz (for 2 V POp with Vs = ±5 V) making it outstanding as an input buffer for flash AID converters.
3. In order to meet the needs of both video and data acquisition
applications, the AD847 is optimized and tested for ±5 V
and ± 15 V power supply operation.
4. The low power and small outline packaging of the AD847
make it very well suited for high density applications such as
multiple pole active filters.
5. The AD847 is internally compensated for unity gain operation and remains stable when driving any capacitive load.
6. Laser wafer trimming reduces the input offset voltage to less
than 1 mV maximum on all AD847 grades, thus eliminating
the need for external offset nulling in many applications.
7. The AD847 is an enhanced replacement for the LM6161
series and can function as a pin for pin replacement for many
high speed amplifiers such as the HA2544, HA25201215 and
the EL2020.

The AD847 also has good dc performance. When operating with
±5 V supplies, it offers an open loop gain of 3,500 VIV (with a
500 n load) and low input offset voltage of 1 mV maximum.
Common-mode rejection is a minimum of 80 dB. Output voltage
swing is ±3 V even into loads as low as 150 n.

REV. B

OPERATfONALAMPLIFIERS 2-133

AD847 -SPECIFICATIONS (@T = +25·C, unless otherwise noted)
A

Model

AD841AR

AD841J
Coaditioas

INPUT OFFSET VOLTAGE'

Vs
±S V

Mia

Tnt

Mas

Tnt

Mas

Uaita

0.5

1
3.5

0.5

1
4

mV
mV

TMJN to TMAJ<

Offset Drift

Mia

IS

INPUT BIAS CURRENT

6.6
7.2

3.3

6.6
10

.,.A
.,.A

±SV,±ISV

50

300
400

50

300
500

nA
nA

TMJN to TMAJ<

Offset Cumnt Drift
OPEN-LOOP GAIN

0.3
Vo - ±2.5V
RwAD = 5000
TMJNtoTMAJ<
RLOAD = 1500
VOUT = ±IOV
RLOAD = I ItO
TMJNtoTMAJ<

DYNAMIC PERFORMANCE
Unity Gain Bandwidth
Full Power Bandwidth2

Slew Rate'
Settling Time to 0.1%

to 0.01%
Phase Margin

Differential Gain
Differential Phase
COMMON-MODE REJECTION

POWER SUPPLY REJECTION
INPUT VOLTAGE NOISE
INPUT CURlU!NT NOISE
INPUT COMMON-MODE
VOLTAGE RANGE

-2.5 V to +2.5 V
10V Step, Av = -I
-2.5 V to +2.5 V
10VSrep,Av = -I
~AD= 10pF
RLOAD =,1 kO
f - 4.4 MHz
f- 4.4 MHz

2
I

3.5
1.6

3
1.5

5.5

1.6

VImV

5.5

V/mV
VImV

MHz
MHz

12.7

12.7
4.7
200

225

225

78
18

140
120
SO
0.04
0.19

50
0.04
0.19

Degree

95

dB
dB

95

±15 V

±5V

+4.3
-3.4
+14.3
-13.4

±5V
±5V
±15 V
;tIS V
±15 V

3.0
2.5
12
10

300

DS

18
18

95

75
15
72

MHz
VillA
V/",s

65
65
140
120

6S

±ISV
±IS V

MHz

35
50

4.7
200
300
65

±IS V

Shon-Circuit Cumnt

VImV
V/mV

±IS V
±SV
±IS V
±SV
±IS V
±5V
±IS V
±ISV

f - 10kHz

5000
1500
I ItO
5000

3.5

±SV

±SV
±IS V

=
=
=

3
1.5

35
50

VCM - ±2.5 V
VCM = ±12V
RJN = 100 0 (See Figure 20)
TMJN to TMAJ<
Vs - ±SVto±ISV
TMJN to TMAJ<
f - 10kHz

RLOAD
RLOAD
RLOAD
RLOAD

2
I

±ISV

±IS V
OUTPUT VOLTAGE SWING

nArc

0.3

±SV

±SV
±ISV
Vo =5Vp-p
RL = 5000,
Vo =20Vp-p,
RL = I ItO
RLOAD = lItO

",vrc

3.3

TMJNtoTMAJ<
INPUT OFFSET CURlU!NT

IS

±5 V, ±ISV

DS
DS
DS

%
Degree

95

75
86

75
72

dB

86

dB
dB

15

IS

1.5

1.5

nVlYHi
pA/y'HZ

+4.3
-3.4
+14.3
-13.4

V
V
V
V

3.6
3

±V
±V
±V
±V

3.6
3

3.0
2.5
12
10

32

32

mA

INPUT RESISTANCE

300

300

ItO

INPUT CAPACITANCE

1.5-

1.5

pF

15

IS

0

OUTPUT RESISTANCE

Open Loop

POWER SUPPLY
Operating Range
Quiescent Current

:t: 4.5
±5V

4.B

±IS V

S.3

TMJNtoTMAJ<
TMJNtoTMAJ<

:dB
U
7.3
6.3
7.6

:t:4.5
4.8
5.3

:t:18
6.0
7.3
6.3
7.6

V
mA
mA
mA
mA

NOTES
lInput Oftiet Vol. Specifications are ........teed Ifte< S minutelat TA = +2S"C.

2FuR Power Batulwidth = S.... Ratel2" VPI!Alt.
·S.... Rate is meuured em risiDg edae.

AU min and max specifications are 1IUIf8I1teed. Specifications in boIcI&ce are 100% tested at fiDaJ electrical telt.
Specifications subject to cbaDge without notice.

2-134 OPERATIONAL AMPLIFIERS

REV.B

AD847
Model

AD847AQ

CorulitiODS
INPUT OFFSET VOLTAGE I

Vs

Min

±5V

Typ

Mas

0.5

I
4

TMIN to TMAX

Offset Drift

Min

IS

INPUT BIAS CURRENT

±5 V, ±15 V

3.3

INPUT OFFSET CURRENT

±5V,±15V

50

TMIN toTMAX

Offset Current Drift
OPEN LOOP GAIN

DYNAMIC PERFORMANCE
Unity Gain Bandwidth
Bandwidth2

Slew Rate'
Settling Time to 0.1%
to 0.01%
Phase Margin
Differential Gain
DiffereDtiai Phase

Vo = 5 Vp-p
RL = 500 n,
Vo = 20 V p-p,
RL=Ik!l
RLOAD = IkO
-2.5 V to +2.5 V
10 V Step, Av = -I
-2.5 V to +2.5 V
10 V Step, Av = -I
CLOAD = 10 pF
R LOAD = I k!l
f- 4.4 MHz
f~ 4.4 MHz

COMMON·MODE REJECTION

VCM = ±2.5 V
VCM=±12V
R'N = 100 n (See Figure 20)
TMIN to TMAX

POWER SUPPLY REJECTION

Vs - ±5Vto±15V
TMIN toTMAX

Mas

Uaits

0.5

I
4

mV
mV

5
7.5

..,A
..,A

300
400

nA
nA

IS

5

3.3

300
400

50

0.3
Vo - ±2.5 V
R LOAD = 500 n
TMIN toTMAX
RLOAD = 150n
VOUT = ±IOV
RLOAD = I k!l
TMIN to T MAX

Typ

7.5

TMIN to T MAX

Full Power

AD847S

±5V

z

3.5

2
I

I
1.6

..,vrc

0.3

nArc

3.5

V/mV
VImV
V/mV

1.6

±15V
3
1.5

5.5

3
1.5

5.5

VImV
V/mV

±5V
±15 V

35
50

35
50

MHz
MHz

±5 V

12.7

12.7

MHz

±15 V
±5V
±15V
±5V
±15V
±5V
±15V
±15V

4.7
200
300
65
65
140
120

4.7
200

MHz
VI..,.
VI..,.
D.
os
DS
DS

225

80
80

80
80

95
95

75
75
72

300
65
65
140
120

50
0.04
0.19

±15V
±15V
±5V
±15V

225

Degree

50
0.04
0.19

%

95
95

dB
dB

86

dB
dB

Degree

75
86

75
72

dB

INPUT VOLTAGE NOISE

f - 10 kHz

±15V

IS

15

DVly'Hi

INPUT CURRENT NOISE

f-lOkHz

±15V

1.5

1.5

pNVHZ

±5V

+4.3
-3.4
+14.3
-13.4

+4.3
-3.4
+14.3
-13.4

V
V
V
V

3.6
3

±V
±V
±V
±V

32

32

mA

INPUT RESISTANCE

300

300

k!l

INPUT CAPACITANCE

1.5

1.5

pF

15

15

n

INPUT COMMON-MODE
VOLTAGE RANGE

±15V
OUTPUT VOLTAGE SWING

RLOAD
RLOAD
RU)AD
R LOAD

=
=
=
=

500 n
150n
I k!l
500 0

Short-Circuit Current

OUTPUT RESISTANCE

±5V
±5 V
±15V
±15V
±15V

OpeD Loop

POWER SUPPLY
Operating Range
Quiescent Current

3.6
3

10

4.8

to T MAX

±15 V
TMIN to T MAX

3.0
2.5

12

:i: 4.5
±5 V
TMIN

REV.B

3.0
2.5
12
10

5.3

:1:18
5.7
7.0
6.3
7.6

:i:4.5
4.8
5.3

:1:18
5.7
7.8
6.3
8.4

V

mA
mA
mA
mA

OPERATIONAL AMPLIFIERS 2-135

•

AD847
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage ....•..•.....•...•..••...•. ±IS V
Intemal Power Dissipation2
Plastic (N) . . . . • • . . . . . . • . . . • . . . . • . . . . 1.2 Watts
Small Outline (R) •....•.•••.•.•........ O.S Watts
Cerdip (Q) ..•.•....•.•.•..••.•...... 1.1 Watts
Input Voltage . . . . • • . . . . . . • . . . . . . . . . . . . . . . . ±Vs
Differential Input Voltage • . . . . • • . . . • . . • . . • • • • • ± 6 V
Storage Temperature Range Q .••....... -6S"C to + ISO"C
N, R ••.•.•.•••••...•.•....... -6S"C to +.12S"C
Junction Temperature ..•.....•.....••....•.• 17S"C
Lead Temperature Range (Soldering 60 sec) .....•... 300"C

CONNECTION DIAGRAM
Plastic DIP (N), Small
Outline (R) and
Cerdip (Q) Packages

NOTES
' S _ above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. 1'!rls is a stress rating only, and functional
operation of the device at tbeIc or any other conditions above those indicated
in the operational section of this specification is Dot implied. Exposure to
absolute DIIllIimum rating conditions for extended periods may affect device

reliability.
2Mini-DIP Package: 6JA

NC = NO CONNECT

= lOO"CJWatt; 6Je = 33'CIWan

Cerdip Package: OJA = UO'CIWatt; O'C = 3O'CIWatt
Small Outline Package: 6JA = lSS'CIWatt; 0JC = 33'CIWatt

METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
t-------~=----------I

7 +Vs

-INPUT

6 OUTPUT

4 -Vs

SUBSTRATEcONNECTEDTO +V.

ORDERING GUIDE

Modell
AD847JN
AD847JR
AD847AQ
AD847AR3
AD847SQ

AD847SQ/883B
AD848JIAIS
AD849]IAlS

Gain
Bandwidth
MHz
50
50
50
50
50
50
175
725

Minimum
Stable
Gain
I
I
I
I
1
1
5
25

Maximum
Offset Voltage
mV
I
I
I
I
I
1
I
1

Temperature
Range _·C

Package
Description

Package
Option2

o to
o to

Plastic
SOIC
Cerdip
SOIC
Cerdip
Cerdip

N-8
R-8
Q-8
R-8
Q-8
Q-8

+70
+70
-40 to +85
-40 to +85
-55 to + 125
-55 to + 125
See AD848 Data Sheet
See AD849 Data Sheet

NOTES
I ADS47 also available in J and S grade chips, and ADS47JR is available in tspe and reel.
'N = Plastic DIP; Q = Cerdip; R = SOIC. For outline information see Package Information section.
3Contact sales office for detailed information.

2-136 OPERATIONAL AMPLIFIERS

REV.B

AD847
Typical Characteristics (@ +25°C and Vs = ±25°C and Vs = ±15 V, unless otherwise noted)
20

20

//

-!> 1
•
",

I

r
0

~

8 •

o

,

I!i.

V-VIN

+%V

10

~

5

4~

·0

20

15

3.
2

-6

•

J

!

If

,20

I..
~

" 5.5

/
,/"""

/

5

•,.~

V

E

,

ia

15V SUPPLIES

15

">~ ,.

"

20

Figure 2. Output Voltage Swing
vs. Supply Voltage

Figure 1. Input Common-Mode
Range vs. Supply Voltage

I>

RLOAo =500n

5
10
15
SUPPLY VOLTAGE - :tVolts

SUPPLY VOLTAGE - ;tVoJb

..

•

IfVvOUT

i

5

'0

./

~ 15

Y

i

o

~

11

V

..-

±5VSUPPUES

~

I,..

100
1k
LOAD RESISTANCE _ n

-----

5

I

" 4.5

4

•

./

10

15

20

SUPPLY VOLTAGE - ::I:Volts

Figure 4. Quiescent Current
vs. Supply Voltage

Figure 3. Output Voltage Swing
vs. Load Resistance

100

/
'1,

4

.\

ia ,'\
i!;

/

"-

3

~

2
-80 -40

V s "':t:5V

"

/

r-- l -

t--

20

1/

1

~t-"

... ,..
1

-20

1/

1

40

60

80

100 120 140

TEMPERATURE - OC

Figure 5. Input Bias Current
vs. Temperature

REV.B

/

0

lOOk

1M
FREQUENCY - Hz

10M

100M

Figure 6. Output Impedance
vs. Frequency

OPERATIONAL AMPLIFIERS 2-137

AD841 ~ Typical Characteristics (@ +25"C and Vs = ::t25"C and Vs = ::t15 V, unless otherwise noted)

.
1/

Cl
E

,

V

/

!•

,..-

- :'\
1\

1

V

/

!V

/'

I

~
I\,

/

•

~

v·~r&V

"

3
-60 -40 -20

0
20 40
60 80
TEMPERATURE - "C

,.

100 120 140

-60

Figure 7. Quiescent Current VB. Temperature

-~

-20 0
20 40 60 80 100
AMBIENT TEMPERATURE - "C

Figure 8. Short-Circuit Current
Limit vs. Temperature

100

2

120 140

'-

- -

+100"

...

,

~ .J.v8ulES

1

\

11dlLOAD

::t5VSUPPLIES" ' \

..... LOAD

f-

~

\

I
I

~

~

•

•

I
4 -60 -40 -20

0

20

40

80

TEMPERATURE -

10 100 120 140

-c

-20
100

..

\

~

~

1k

10k
lOOk
1M
FREQUENCY - Hz

10M

100M

Figure 10. Open-Loop Gain and
Phase Margin VB. Frequency

Figure 9. Gain Bandwidth Product
VB. Temperature

Iv.I. Izt.v vII...··A-t/

V.-:t5V

!II

~"r----r~~~--4----i--~

VV
V

..
..,.

\

~

=
i"

i201----+----+----+-.......-t'~

I

100
,.
LOAD RESISTANCE - U

.

,

Figure 11. Open-Loop Gain VB. Load Resistance

2-138 OPERATIONAL AMPLIFIERS

~~.--~1="--~1=o.~~1±M~~~~~
FREQUENCY - HI:

Figure 12. Power Supply Rejection VB. Frequency

REV. B

AD847

.. -

,ao

30

'"

.
..

N:·16V

VCM =:tlVp-p

~

,.

,=,kG

"-

"-

'0'

0

'OOk

,M
FREQUENCY - Hz

10M

100M

'0

/

.

g

I

2

V

0.1'"

,%

0.1"-

S

0-

-,

'I,

20

40

-90

ZNDHARMONIC

I-'ao

V ...

1-"
.

./

0

'\

o

3V~
....=1kR

~

'\..

•
•
0

I

-80

\ \

!;i-

'OM

/

",

i'..

'"

60

80

iiill

%-120

~

100

120

140

110

-,oo,ao

Figure 16. Harmonic Distortion vs. Frequency

50

. .0

.. 1\

...
...

\

/'

_\

/'

'-.,

'0

,ao

".,

.... /

./

/V

,.

'Ok

,.

1M

10M

FREQUENCY _ Hz

Figure 17. Input Voltage Noise Spectral Density

REV. B

,ao.

10k

FREQUENCY - HI:

Figure 15. Output Swing and Error vs. Settling Time

o

II

1It

S£TTLiNG TIME - ns

1:2

""r--. ,-

-70

/

.~-•

,M

Figure 14. Large Signal Frequency Response

./"

I

>

0

"-

INPUT FREQUENCY-Hz

Figure 13. Common Mode Rejection vs. Frequency

2

1'\

5

0

o

r-- ~

25

'50

-eo

-40 -20

0
20 40 8D
TEMPERATURE _ '"C

eo

100 120 140

Figure 18. Slew Rate vs. Temperature

OPERATIONAL AMPLIFIERS 2-139

•

AD847
lItO

HP3314A

FUNCTION
GENERATOR

FET
PROBE

2.5MHz

TEK
7A24

OSCILLOSCOPE

Figure 19. Inverting Amplifier
Configuration

Figure 19a. Inverter Large
Signal Pulse Response

Figure 19b. Inverter Small
Signal Pulse Response
R.
1250

+15V

FET

TEK

PROBE
HP3314A

7A24

OSCILLOSCOPE

FUNCTION
GENERATOR

lkO

2.5MHz

Figure 20. Noninverting Amplifier
Configuration

Figure 20a. Noninverting
, Large Signal Pulse Response

2-140 OPERATIONAL AMPLIFIERS

Figure 20b. Noninverting
Small Signa/. Pulse Response

REV. B

AD847

•

Figure 21. Offset Nulling
OFFSET NULUNG
The input offset voltage of the AD847 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 21 can be used.
INPUT CONSIDERATIONS
An input resistor (RIN in Figure 20) is required in circuits
where the input to the AD847 will be subjected to transient or
continuous overload voltages exceedins the ±6 V maximum differentiallimit. This resistor provides protection for the input
transistors by limiting the maximum current that can be forced
into their bases.
For high performance circuits it is recommended that a resistor
(RB in Figures 19 and 20) be used to reduce bias current errors
by matching the impedance at each input. The offset voltage
error caused by the offset current is more than an order of magnitude less.
THEORY OF OPERATION
The AD847 is fabricated on Analog Devices' proprietary complementary bipolar (CB) process which enables the construction
of pnp and npn transistors with similar f,.s in the 600 MHz to
800 MHz region. The AD847 circuit (Figure 22) includes an
npn input stage followed by fast pnps in the folded cascade
intermediate gain stage. The CB pnps are also used in the current amplifying output stage. The internal compensation capacitance that makes the AD847 unity gain stable is provided by the
junction capacitances of transistors in the gain stage.
The capacitor, Cp , in the output stage mitigates the effect of
capacitive loads. At low frequencies and with low capacitive
loads, the gain from the compensation node to the output is
very close to unity. In this case Cp is bootstrapped and does not
contribute to the compensation capacitance of the pan. As the
capacitive load is increased, a pole is formed with the output
impedance of the output stage. This reduces the gain, and therefore, C p is incompletely bootstrapped. Some fraction of C p contributes to the compensation capacitance, and the unity gain
bandwidth falls. As the load capacitance is increased, the bandwidth continues to fall, and the amplifier remains stable.

REV. B

-v.
NULL 1

NULLa

Figure 22. AD847 Simplified Schematic
GROUNDING AND BYPASSING
In designing practical circuits with the AD847, the user must
remember that whenever high frequencies are involved, some
special precautions are in order. Circuits must be built with
shon interconnect leads. A large ground plane should be used
whenever possible to provide a low resistance, low inductance
circuit path, as well as minimizing the effects of high frequency
coupling. Sockets should be avoided because the increased interlead capacitance can degrade bandwidth.
Feedback resistors should be of low enough value to assure that
the time constant formed with the capacitances at the amplifier
summing junction will not limit the amplifier performance.
Resistor values of less than 5 k!l are recommended. If a 1arger
resistor must be used, a small «10 pF) feedback capacitor in
parallel with the feedback resistor, R p , may be used to compensate for the input capacitances and optimize the dynamic performance of the amplifier.
Power supply leads should be bypassed to ground as close -as
possible to the amplifier pins. 0.1 fJoFceramic disc capacitors are
recommended.

OPERATIONAL AMPLIFIERS 2-141

AD841
VIDEO LINE DRIVER

Figure 24 shows the AD847 driving 100 pF and 1000 pF loads.

The AD847 functions very well as a low cost, high speed line
driver for either terminated or unterminated cables. Figure 23
shows the AD847 driving a doubly terminated cable in a follower configuration.

me

The termination resistor, Rr, (when eqqal to
cable's characteristic impedance) minimizes reflections from the far end of the
cable. While operating from ±5 V supplies, the AD847 maintains a typical slew rate of 200 V/tJ.S, which means it can drive a
±l V, 30 MHz signal into a terminated cable.

10DpF
LOAD

,_.
LOAD

+Va
Figure 24. AD847 Driving Capacitive Loads

FLASH ADC INPUT BUFFER
The 35 MHz unity gain bandwidth of the AD847 when operated
with ± 5 V supplies makes it an excellent choice for buffering
the input of high speed flash AID converters, such as the

AD9048.
Figure 25 shows the AD847 as a unity inverter for the input to
theAD9048.

c"
SEE TABLE I

Figure 23.· Video Line Driver
Table I. Video Line Driver Performailce Chart

VIN•
odB or
odB or
odB or
o dB or
odB or
odB or
NOTE

±500 mV
±SOO mV
±SOO mV
±SOO mV
±SOO mV
±SOO mV

Step
Step
Step
Step
Step
Step

Bw

VSUPPLY

Cc

-3 dB

±IS
±IS
±IS

20pF
15 pF
OpF
20pF
IS pF
OpF

23 MHz
21 MHz
13 MHz
18 MHz
16 MHz
11 MHz

±S
±S
±S

Over-

shoot
4%
0%
0%

2%
0%
0%

*-3 dB bandwidth numbers an: for the 0 dBm signal inpUt. Overshoot numbers an: the percent overshoot of the I volt step input.

A back-termination resistor (RBT, also equal to the characteristic
intpedance of the cable) may be placed between the AD847 output and the cable input, in order to damp any reflected signais
caused by a mismatch betWeen Rr and the cable's charactmstic
intpedance. This will result in a flatter frequency reSPonse,
although this requires that the op amp supply ±2 V to the output in order to achieve a -1 V swing at resistor Rr.

2-142 OPERATIONAL AMPLIFIERS

Figure 25. Flash ADC Input Buffer

REV.B

AD847
A IfiIh Speed, Three Op-Amp In-Amp
The circllit of Figure 26 lends itself well to CCD imaging and
other video speed applications. It uses two high speed CB process op-amps: Amplif1Cl' A3, the output amplifier, is an AD847.
The input amplifier (AI and A2) is an AD827, which is a dual
version of the AD847. This circuit has the optional flexibility of
both de and ac trims for common-mode rejection, plus the ability to adjust for minimum settling time.

+15VO

COMMO

EACH
AMPLIFIER

1

I

1~
10llF
I

+Vs

IlllF I

O 1IlF
•

110llF 10.:F
-15VO

1 ..

>1

-Vs

Input
Frequency

CMRR

100 Hz
I kHz
10 kHz
100 kHz
I MHz
10 MHz

88.3
87.4
86.2
67.4
47.1
26.4

dB
dB
dB
dB
dB
dB

:~
PIN/'

O•1IlF AD827

>
2-8pF
SETTLING TIME
AC CMR ADJUST

21<0

21<0

2kQ
lkQ

CIRCUIT GAIN = 20000 + 1
RG

Bandwidth, Settling Time and Total Harmonic Distortion

Gain

Ra

(PF)

Small Signal
Bandwidth

1
2
10
100

Open

2-8
2-8
2-8
2-8

16.1 MHz
14.7 MHz
4.5 MHz
660 kHz

CAD]

2kO
2260
2000

VB.

Gain

Settling Time
to 0.1%

THD+Noise
Below Input Level
@10kHz

200 ns
200 ns
370 ns
2.5 1105

82
82
81
71

dB
dB
dB
dB

Figure 26. A High Speed In-Amp Circuit for Data Acquistion

REV.B

OPERA TlONAL AMPLIFIERS 2-143

•

AD847
IDGB SPEED DAC BUFFER
The wide bandwidth and fast settling time of the AD847 makes
it a very good output buffer for high speed current-output D/A
converters like the ADDAC-08. Figure 28 shows the ADDAC08 with the AD847 as the current to voltage converter. In this
unipolar configuration the output swing ranges from 0.00 V to
+9.96V.

pin. A -10.0 V to +9.92 V bipolar output is achievable by connecting a 10 kO resistor between the ADS87 output and the
AD847 input and replacing Rp with a 10 kO resistor.

Figure 27 shows the full scale settling time of this circuit when
the digital codes are changed from allIs to all Os. For the
+9.96 V to 0.00 V output change shown 1 LSB = 40 mV the
overall settling time of the circuit is 140 DS.

AD847

OUTPUT

The variable feedback capacitor, Cp , is used to optimize the settling time of the circuit by compensating for the additional pole
created by Rp and the stray capacitance at the inverting input

DIGITAL

INPUT

Figure 27. Settling Time for AD DAC-OB and AD847
Combination
+Vs

C.
O.2pF-5pF
+Vs

-VS

R.

4.99kfi
SETTLING TIME TEST CIRCUIT

}----4~_vv-..........- ;

TEK7613
OSCILLOSCOPE
7A13
AMPLIRER

2x
IN6263

Figure 28. High Speed DAC Buffer

2-144 OPERA TIONAL AMPLIFIERS

REV.B

11IIIIIIII

High Speed, Low Power
Monolithic Op Amps
AD848/AD849 I

ANALOG

WDEVICES
FEATURES
725MHz Gain Bandwidth - AD849
175MHz Gain Bandwidth - AD848
4.8mA Supply Current
300VIlLS Slew Rate
SOns Settling Time to 0.1 % for a 10V Step - AD849
Differential Gain: AD848 0.07%, AD849 0.08%
Differential Phase: AD848 0.08°, AD849 0.04°
Drives Capacitive Loads

=
=

=
=

CONNECTION DIAGRAM
AD848 and AD849

•

Plastic (N), Small
Outline (R) and
Cerdip (a) Packages

DC PERFORMANCE
3nVtv'Hz Input Voltage Noise - AD849
85V/mV Open Loop Gain into a 1kfl Load - AD849
1mV max Input Offset Voltage
Performance Specified for ±5V and ±15V Operation
Available in Plastic, Hermetic Cerdip and Small Outline
Packages. Chips and MIL-STO-883B Parts Available.
Tape and Reel Also Available

(AD848 with a soon load) and low input offset voltage of ImV
maximum. Common-mode rejection is a minimum of 92dB.
Output voltage swing is ±3V even into loads as low as 150n.

APPLICAnONS
cable Drivers
8- and 1G-Bit Data Acquisition Systems
Video and RF Amplification
Signal Generators

APPLICATIONS HIGHLIGHTS
1. The high slew rate and fast settling time of the AD848 and
AD849 make them ideal for video instrumentation circuitry,
low noise preamps and line drivers.

PRODUCT DESCRIPTION
The AD848 and AD849 are high speed, low power monolithic
operational amplifiers. The AD848 is internally compensated so
that it is stable for closed loop gains of 5 or greater. The AD849
is fully decompensated and is stable at gains greater than 24.
The AD848 and AD849 achieve their combination of fast ac and
good dc performance by utilizing Analog Devices' junction isolated complementary bipolar (CB) process. This process enables
these op amps to achieve their high speed while only requiring
4.8mA of current from the power supplies.
The AD848 and AD849 are members of Analog Devices' family
of high speed op amps. This family includes, among others, the
AD847 which is unity gain stable, with a gain bandwidth of
50MHz. For more demanding applications, the AD840, AD841
and AD842 offer even greater precision and greater output current drive.

NC = NO CONNECT

2. In order to meet the needs of both video and data acquisition
applications, the AD848 and AD849 are optimized and tested
for ±5V and ± 15V power supply operation.
3. Both amplifiers offer full power bandwidth greater than
20MHz (for 2V POp with ±5V supplies).
4. The AD848 and AD849 remain stable when driving any
capacitive load.
5. Laser wafer trimming reduces the input offset voltage to
ImV maximum on all grades, thus eliminating the need for
external offset nulling in many applications.
6. The AD848 is an enhanced replacement for the LM6164
series and can function as a pin-for-pin replacement for many
high speed amplifiers such as the HA2520/2/5 and EL2020 in
applications where the gain is 5 or greater.

The AD848 and AD849 have good dc performance. When operating with ±5V supplies, they offer open loop gains of BV/mV

REV. A

OPERA TlONAL AMPLIFIERS 2-145

AD848/AD849---SPECIFICATIONS
Model

Conditions

INPUT OFFSET VOLTAGE'

"'

T_ toT.,..

Offset Drift
INPUT BIAS CURRENT
T_toT....
INPUT OFFSET CURRENT

Tmin to Tmax
Offset Current Drift
OPEN LOOP GAIN

Vo=±2.SV
R LOAo =5000

DYNAMIC PERFORMANCE
Gain Bandwidth
Full Power Bandwidth2

AVCL~5

Vci=2Vp·p,
R L ",5000
Vo=20V p-p,
RL=lkO

Slew Rate
Settling Time to 0.1%

RLOAD=lkO
-2.5Vto +2.SV
lOY Step, Av = -4

Phase Margin

~oAD=IOpF

AD848A/S

Typ

Max

±5V
±15V
±SV
±15V
±5V, ±15V

0.2
0.5

1
2.3
1.5
3.0

±5V, ±ISV
±SV, ±15V

3.3

±5V,
±5V,
±5V,

50

Min

Min

7

15V
15V
15V

Typ

Max

Vaits

0.2
O.S

1
2.3
2
3.5

mV
mV
mV
mV
JLVre

6.615

!LA
!LA

7
6.6
7.2

3.3

300
400

50

7.5
300

400

0.3

0.3

nA
nA
nArc

±5V
9
7

13

9

VlmV
V/mV
V/mV

13

7/5
8

8

±15V
12

20

12
8/6

8

20

V/mV
V/mV

±5V
±15V

125
17S

12S
17S

MHz
MHz

±5V

24

24

MHz

4.7
200
300
6S
100

MHz
VljL'
V/jL'
ns
ns

±15V
±5V
±15V
±5V
±15V
±ISV

22S

RLOAo=lkO
DIFFERENTIAL GAIN

f=4.4MHz

±15V

DIFFERENTIAL PHASE

f=4.4MHz

±15V

COMMON-MODE REJECTION

VCM =±2.5V
VCM=±12V
T_toTmax

±SV
±15V

POWER SUPPLY REJECTION

= +25°C, unless otherwise noted)

AD848J

v.

Tmin to Tmax
R LOAo =1500
VoUT =±IOV
RLOAo=lkO
T_toTmax

(@TA

4.7
200
300
65
100

225

60

60

Degree.

0.07

0.07

%

0.08
92

92

lOS
lOS

88

Vs= ±4.5V to.±ISV
T_toTmax

85
80

98

0.08

Degree

92
92
88

lOS
105

dB
dB
dB

85

98

dB
dB

80

INPUT VOLTAGE NOISE

f=lOkHz

±15V

S

5

nV/yHz

INPUT CURRENT NOISE

f=IOkHz

±15V

1.5

I.S

pA/yHz

±SV

+4.3
-3.4
+14.3
-13.4

+4.3
-3.4
+14.3
-13.4

V
V
V
V

3.6
3
1.4

±V
±V
±V
±V
±V

INPUT COMMON·MODE
VOLTAGE RANGE

±ISV
OUTPUT VOLTAGE SWING

RLoAo=SOOO
RLoAo=ISOO
RLOAO=SOO
RLoAo=lkO
RLOAO=SOOO

±SV
±SV
±SV
±ISV
±ISV

3.0
2.5

3.6
3
1.4

3.0
2.5

12
10

12
10
32

32

rnA

INPUT RESISTANCE

70

70

kO

,INPUT CAPACITANCE

I.S

1.5

pF

IS

15

0

SHORT CIRCUIT CURRENT

OUTPUT RESISTANCE

±15V

Open Loop

POWER SUPPLY
Operating Rangt
Quiescent Current

:t:4.5
±5V

4.8

±ISV

5.1

Tmin to Tmax
T_toTmax

:t:18
6.0
7.4
6.8
8.0

:t:4.5
4.8
S.I

d8
6.0
7.418.3
6.8
8.019.0

V

rnA
rnA
rnA
rnA

NOTES
'Input ofUet voltqe specifications an: guaranteed after 5 minutes at T A ~ + 25'C.
ZFull

power bandwidth=s1cw ratel21f VpEAK , Refer to Figure 1.

All min and

DlU

specifications are guaranteed. Specifications in boldface are tested on all production units at fmal electrical test. All others are guaranteed but

not necessarily tested.

Specifications subject to change without notice.

2-146 OPERA T10NAL AMPLIFIERS

REV. A

AD848/AD849
Model

Conditions

INPUT OFFSET VOLTAGE'
Tmill

to Tmax

Offset Drift
INPUT BIAS CURRENT

Tmin to Tmax
INPUT OFFSET CURRENT

Tmin to Tmax
Offset Current Drift
OPEN LOOP GAIN

DYNAMIC PERFORMANCE
Gain Bandwidth
Full Power Bandwidth'

Vs

0.3
0.3

±SV, ±lsV
±SV, ±lsV

3.3

6.6
7.2

±SV, ±lsV
±SV, ±ISV
±SV, ±lsV

SO

300
400

±SV

AvcL"'2s

±SV
±lsV

Slew Rate

mV
mV
mV
mV
...vrc

3.3

6.6/5
7.5

~
~

SO

300
400

nA
nA
nArC

2

0.3

0.3
30
20/15

50

Units

0.75
0.75
1.0
1.0

SO

V/mV
V/mV
VlmV

32

±lsV
45
30

SS

VlmV
V/mV

520
725

520
725

MHz
MHz

±sv

20

20

MHz

±15V
±SV
±lsV
±SV
±lsV
±lsV

4.7
200
300
65
SO

4.7
200
300
65
SO

MHz
VI ....
VI ....
n.

DIFFERENTIAL PHASE

f=4.4MHz

±lsV

VCM=±2.sV
VcM =±12V

±sV
±lsV

Tmin

0.1
0.1

32

COMMON·MODE REJECTION

POWER SUPPLY REJECTION

1
1
1.3
1.3

20

DIFFERENTIAL GAIN

Phase Margin

AD849AJS
Typ
Max
Min

2

30

RLOAo=lkn
-2.SV to +2.sV
IOV Step, Av = - 24
CLOAO = IOpF
RLoAo=lkn
f=4.4MHz

Settling Time to 0.1%

Max

±SV
±lsV
±SV
±lsV
±SV, ±lsV

Vo=±2.5V
R LoAo =500n
T min to T max
RLoAo=lsOn
VouT=±IOV
RLOAo=lkn
Tmin to Tmax

Vo =2Vp-p,
RL=sOOn
Vo=20V p.p,
RL=lkn

AD849J
Min Typ

225

±lsV

to Tmax

V.=±4.sVto ±ISV

Tmin to Tmax

S5

45
30125

225

ns

60

60

Degrees

O.OS

O.OS

%

0.04

Degree

100
100
96

0.04
115
1lS

100
100
96

115
115

dB
dB
dB

9S
94

120

98
94

120

dB
dB

INPUT VOLTAGE NOISE

f= 10kHz

±lsV

3

3

nV/ylHz

INPUT CURRENT NOISE

f= 10kHz

±lsV

1.5

1.5

pAJylHz

±SV

+4.3
-3.4
+14.3
-13.4

+4.3
-3.4
+14.3
-13.4

V
V
V
V

3.6
3
1.4

±V
±V
±V
±V
±V

INPUT COMMON-MODE
VOLTAGE RANGE

±lsV
OUTPUT VOLTAGE SWING

R LOAo =500n
R LoAD = Ison
RLoAo=son
R LOAo =lkn
R LOAo =500n

±SV
±SV
±sv
±lsV
±lsV

3.0
2.5

3.6
3
1.4

3.0
2.5

12
10

12
10
32

32

rnA

INPUT RESISTANCE

25

25

kn

INPUT CAPACITANCE

1.5

1.5

pF

IS

IS

n

±lsV

SHORT CIRCUIT CURRENT

OUTPUT RESISTANCE

Open Loop

POWER SUPPLY
Operating Range
Quiescent Current

±4.5
±SV

4.S

±ISV

5.1

T min to Tmax
T min to Tmax

±IS
6.0
7.4
6.S
8.0

±4.5
4.S
5.1

±IS
6.0
7.418.3
6.S
8.0/9.0

V
rnA
rnA
mA
rnA

NOTES
llnpul offset voltage specifications are guaranteed after 5 minutes at TA = +25OC.
lpull power bandwidth=s1ew ratel211' VPEAK ' Refer to Figure 2.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electricaJ test. All others are guaranteed but
not necessarily tested.
Specifications subject to change without nmice.

REV. A

OPERATIONAL AMPLIFIERS 2-747

•

AD848/AD849
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage . . . • . . . . . . . . . . . . . . . . . . . . . . . . ±ISV
Internal Power Dissipation2
Plastic (N) . . . . • . . . . . . . • . . . . . . . . . . . . . . 1.1 Watts
Small Outline (R) . . . . . . . . . . . . . . . . . . . . • .0.9 Watts
Cerdip (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Watts
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±Vs
Differential Input Voltage . . . • . . . . . . . . . . . . . . . . . . +6V
Storage Temperature Range Q . . . . . . . . . . . -65°C to + 150°C
N, R . . . . . . . . . . . . . . . . . . . . . . . . . . -65OC to + 125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . • . . + 175°C
Lead Temperature Range (Soldering 60sec) . . . . . . . . . + 300°C

METALIZATION PHOTOGRAPH
Contact factory for late.st dimensions. (AD848 and AD849 are identical
except for the part number in the upper right.)
Dimensions shown in incbes and (mm).

·Suesses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
'Mini·DlP Package: alA = 11O"C Watt.
Cerdip Package: alA = IIO"C Watt.
Small Outline Package: alA = ISS"C Watt.
sussmATE CONNECTED TO +Vs

ORDERING GUIDE
Gain
Bandwidth
MHz

Min
Stable
Gain

Max
Offset Voltage
mV

ADS48JN
ADS4SJR
AD848AQ
ADS4SSQ
ADS48SQf883B

175
175
175

175
175

5
5
5
5
5

AD849JN
AD849JR
AD849AQ
AD849SQ

AD849SQ/883B

725
725
725
725
725

AD847JIAIS

50

Model

Temperature
Range - °C

Package
Option1 ,2

1
1
1
1
1

o to +70
o to +70

N·8
R·S
Q-S
Q-S
Q·8

25
25
25
25
25

1
1
0.75
0.75
0.75

oto +70
oto +70

1

1

-40 to +85
-55 to + 125
-55 to + 125

-40 to +85
-55 to + 125
-55 to + 125

N-S
R·8
Q·8
Q·8
Q-8

See ADS47 Data Sheet

NOTES
'Plastic SOIC (R) available in tape and reel. AD848 available in S grade chips. AD849 available in
J and S grade chips.
'N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC). For outline information see Package
Information section.

2-148 OPERATIONAL AMPLIFIERS

REV. A

AD848/AD849
R,
4.99kll

R,
12.5kll
+15V

HP3314A

;EUN~~W~R f--......VV'.-+-(
2.5MHz

FET

PROBE

HP3314A

TEK
7A24
OSCILLOSCOPE

Figure 1. AD848 Inverting Amplifier Configuration

Figure 1a. AD848 Large Signal
Pulse Response

Figure 1b. AD848 Small Signal
Pulse Response

;EUN~~W~R f--......VV'.-+-(
2.5MHz

FET
PROBE

TEK
7A24
OSCILLOSCOPE

Figure 2. AD849 Inverting Amplifier Configuration

Figure 2a. AD849 Large Signal
Pulse Response

Figure 2b. AD849 Small Signal
Pulse Response

OFFSET NULLING
The input voltage of the AD848 and AD849 are very low for
high speed op amps, but if additional nulling is required, the
circuit shown in Figure 3 can be used.
For high performance circuits it is recommended that a resistor
(R B in Figures I and 2) be used to reduce bias current errors by
matching the impedance at each input. The offset voltage error
caused by the input currents is decreased by more than an order
of magnitude.

Figure 3. Offset Nulling

REV. A

OPERATIONAL AMPLIFIERS 2-149

•

AD848/AD849-Typical Characteristics (@ +25°C and Vs=±15V. unless otherwise noted)
30

30

.

1".•

.

t

il

---

5

I

04.5

t"\

/

i\

V

'\

/'

\
•

•o

10

0

15

Figure 4. Quiescent Current vs.
Supply Voltage (AD848 and AD849)

15V SUl'PLIES

\

V V

"'-

'M

SUPPLY VOLTAGE - :t:Volts

V
V

...='''''

'OOM

'OM
INPUTFREQUENCV - Hz

Figure 5. Large Signal Frequency
Response (AD848 and AD849)

95

.1 I I

'00

I

v~= ±~v

V

V ....-

,I

a~

V

9
z

,;

,
70

..

,

65

'0

100

1k

LOAD f\ESISTANCE -

n

I

/V

V.==1IV

'I!

95

I'

..

I

V

•
•

.

100
1k
LOAD RESISTANCE - n

'0

'Ok

5

V

/

V

I

I

/

/
3
- 60

- 40

I\, '\.
20

40

"

&0
80
100
SEnLlNG TIME - ns

120

140

160

Figure 9. Output SWing and
Error vs. Settling Time (AD848)

V

"1\

1\
'\

~

Vs=~5V

"- "-..,

3

[\.

0

5
20

\ \

\

vs=r sv

V

0.1%

5

/V

o.

""
\ \

-,. o

Figure 8. Open Loop Gain vs.
Load Resistance (AD849)

/'

I
i

D.'".

-8

75

/

V

'"

0

/

/

I

Va= :t5V

35

/

/

•

V

90

Figure 7.. Open Loop (;ain vs.
Load Resistance (AD848)

C6
E

'Ok

Figure 6. Output Voltage Swing vs.
Load Resistance (AD848 and AD849)

Va= :t15V

I

I

100
1k
LOAD RESISTANCE _ n

'0

0

'06

90

b::: ~V

o

:tIVSUPPUES

0
20
40
60 80
TEMPERATURE - "C

100 120 140

Figure 10. Quiescent Current vs.
Temperature (AD848 and AD849)

2-150 OPERATIONAL AMPLIFIERS

H

-~

H
0
H
~
H
"
AMBIENT TEMPERATURE _

or:

~

!'-..... t--

~

Figure 11. Short Circuit Current
Limit vs. Temperature (AD848
and AD849)

~

r-

2
60

40

20

20

40

60

80

100 120 140

TEMPERATURE _·C

Figure 12. Input Bias Current vs.
Temperature (AD848 and AD849)

REV. A

AD848/AD849
'00

~'-:l--1
~ :t15VSUPPLIES~

.

~D

'2.

+100·

.-- +10"

. . . +---,

'00

'"

"VSUPPUES~

,

\

500flLOAD

\

~ r-..

+

\

80

~~UE~

~

~ so

~'\

\

lk

10k

tOOk

1M

10M

\

+

\

~

I

V s =;t;15V

~

'"f:'-\

~ •.'5r--+-+--+-+--+-+--+-1--+-+

I

•

100

100M

l!

\

2.

-2.100

lk

'011

lOOk

1M

10M

II!
0.9_':.,,".-7.
..:-_-:t2.:-.,..-:!:2.:--:..
!::--.:!:.:--:.!::."""""'.!::."""""12!::.-,J'••

100M

TEMPERATURE _ '"C

FREQUENCY_Hz

FREQUENCY _ Hr

Figure 13. Open Loop Gain and
Phase Margin vs. Frequency (AD848)

Figure 14. Open Loop Gain and
Phase Margin vs. Frequency (AD849)

-10

-90

-

L51-+-f--+-+-+-I-+-1'-+-1

\

lkOLOAD

I..

\

l~

+...

~ .,.VSUPPUES

\
\

+'00"

~"M~

.

Figure 15. Normalized Gain Bandwidth Product vs. Temperature
(AD848 and AD849)

.5.
3VRMS
Rl =lkn

1\='''''

•••
•

-95

v

35

~

,

I
2ND HARMONIC

•

-11 5

-'20'00

'OOk

Figure 16. Harmonic Distortion vs.
Frequency (AD848)

'00

. ~ "'-

'Ok

~

'M

'OOk
FREQUENCY-Hz

100M

Figure 19. Power Supply Rejection
vs. Frequency (AD848)

REV. A

'00'

'0'

Figure 17. Harmonic Distortion vs.
Frequency (AD849)

'00

,/

20
40
60
TEMPERATURE _ "C

80

100 120 140

~D849

~~

~UPPLY
80

~

'"~"-

40

,.

,./

Figure 18. Slew Rate vs. Temperature
(AD848 and AD849)

'0. ~

2.

V

k.....-

V

'50
-60 -40 -20

'20

I

/

2••

'2.

eo

'"

10M

~250

'rHjjty)
J%DHfR""(""1'

FREQUENCY - Hz

-SUPPl~

~~

•,.

,.

I·i '"

~ t'-,.

+ SUPPlY

-.UPP~

..

•,

-'2

FREQUENCY - Hz

V

~

0

1 LV

ri"M
,.
,..

~

~I

VI

.lJ..

-11 5

w300

10k

100'

1M

A~ 0-.

so

~

10M

Vs= :!:15V

VCM =;tlVp-p

'"

••
20

100M

FREQUENCY _ Hz

Figure 20. Power Supply Rejection
vs. Frequency (AD849)

,.

10k

'00'

,M

10M

'OOM

FREQUENCY - Hz

Figure 21. Common-Mode
Rejection vs. Frequency

OPERATIONAL AMPLIFIERS 2-151

•

AD848/AD849 - Applications
GROUNDING AND BYPASSING
In designing practical circuits with the AD848 or AD849, the
user must remember that whenever high frequencies are
involved, some special precautions are in order. Circuits must be
built with short interconnect leads. A large ground plane should
be used whenever possible to provide a low resistance, low inductance circuit path, as well as minimizing the effects of high
frequency coupling. Sockets should be avoided because the increased interlead capacitance can degrade bandwidth.
Feedback resistors should be of low enough value to assure that
the time constant formed with the capacitances at the amplifier
summing junction will not limit the amplifier performance. Resistor values of less than Skfl are recommended. If a larger resistor must be used, a small « IOpF) feedback capacitor in
parallel with the feedback resistor, R F , may be used to compensate for the input capacitances and optimize the dynamic performance of the amplifier.

~

~v

,;1,1

-II
II

"II

100pf
LOAD

,-j

.oi l

l~

•

" 11

1000pF
LOAD

Figure 23. AD848 Driving a Capacitive Load

Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. O.lfLF ceramic disc capacitors are
recommended.

Often termination is not used, either because signal integrity
requirements are low or because too many high frequency signals returned to ground contaminate the ground plane. Unterminated cables appear as capacitive loads. Since the AD848 and
AD849 are stable into any capacitive load, the op amp will not
oscillate if the cable is not terminated; however pulse integrity
will be degraded. Figure 23 shows the AD848 driving both
lOOpF and IOOOpF loads.

VIDEO LINE DRIVER
The AD848 functions very well as a low cost, high speed line
driver of either terminated or unterminated cables. Figure 22
shows the AD848 driving a doubly terminated cable.

LOW NOISE PRE-AMP
The input voltage noise spectral densities of the AD848 and the
AD849 are shown in Figure 24. The low wide band noise and
high gain bandwidths of these devices makes them well suited as
pre-amps for high frequency systems.

The termination resistor, RT , (when equal to the characteristic
impedance of the cable) minimizes reflections from the far end
of the cable. While operating off ±SV supplies, the AD848
maintains a typical slew rate of 200V/fLS, which means it can
drive a ±lV, 24MHz signal on the terminated cable.
A back-termination resistor eRsT> also equal to the characteristic
impedance of the cable) may be placed between the AD848 output and the cable in order to damp any reflected signals caused
by a mismatch between RT and the cable's characteristic impedance. This will result in a "cleaner" signal, although it requires
that the op amp supply ±2V to the output in order to achieve a
± 1V swing at the line.
R,

R,

25

0
0\
5

~

0
10

+Vs

'"

100

AD848

AD849
1k

10k
100k
FREQUENCY - Hz

1M

10M

Figure 24. Input Voltage Noise Spectral Density

Input voltage noise will be the dominant source of noise at the
output in most applications. Other noise sources can be minimized by keeping resistor values as small as possible.

Figure 22. Video Line Driver

2-152 OPERATIONAL AMPLIFIERS

REV. A

Ultrahigh Frequency
Operational Amplifier
AD5539 I

11IIIIIIII ANALOG
WDEVICES
FEATURES
Improved Replacement for Signetics SE/NE5539
AC PERFORMANCE
Gain Bandwidth Product: 1.4 GHz typ
Unity Gain Bandwidth: 220 MHz typ
High Slew Rate: 600 V/lJ.s typ
Full Power Response: 82 MHz typ
Open-Loop Gain: 47 dB min. 52 dB typ

CONNECTION DIAGRAM
Plastic DIP (N) Package
or Cerdip (Q) Package

NC
FREQUENCY
COMPENSATION

DC PERFORMANCE
All Guaranteed DC Specifications Are 100% Tested
For Each Device Over Its Full Temperature
Range - For All Grades and Packages
Vos: 5 mV max Over Full Temperature Range
(AD5539J)
Ie: 20 IJ.A max (AD5539J)
CMRR: 70 dB min. 85 dB typ
PSRR: 100 IJ.V/v typ
MIL-STD-883B Parts Available

PRODUCT DESCRIPTION
The AD5539 is an ultrahigh frequency operational amplifier designed specifically for use in video circuits and RF amplifiers.
Requiring no external compensation for gains greater than 5, it
may be operated at lower gains with the addition of external
compensation.
As a superior replacement for the Signetics NE/SE5539, each
AD5539 is 100% dc tested to meet all of its guaranteed dc specifications over the full temperature range of the device.

INVERTING
INPUT

NONINVERTING
INPUT

NC

v+

TOP VIEW

PRODUCT HIGHLIGHTS
1. All guaranteed dc specifications are 100% tested.
2. The AD5539 drives 50 nand 75 n loads directly.
3. Input voltage noise is less than 4 nVy'Hz.
4. Low cost RF and video speed performance.
5. ±2 volt output range into alSO n load.
6. Low cost.
7. Chips available.

The high slew rate and wide bandwidth of the AD5539 provide
low cost solutions to many otherwise complex and expensive
high frequency circuit design problems.
The AD5539 is available specified to operate over either the
commercial (AD5539JN/JQ) or military (AD5539SQ) temperature range. The commercial grade is available either in 14-pin
plastic or cerdip packages. The military version is supplied in
the cerdip package. Chip versions are also available.

REV. A

OPERATIONAL AMPLIFIERS 2-153

•

AD5539 -SPECIFICATIONS
Parameter

Min

INPUT OFFSET VOLTAGE
Illitial Offset l
Tmill to T""",
INPUT OFFSET CURRENT
Illitial Offser
T mill to T max
INPUT BIAS CURRENT
Initialz
VCM =0
Either Input
T mill to T max
FREQUENCY RESPONSE
RL = 15003
SmaIl Signal Bandwidth
Act. = 24
Gain Bandwidth Product
Act. = 26 dB
Full Power Response
Act. = 24
Act. = 7
Act. = 20
Settling Time (1 %)
Slew Rate
Large Signal Propagation Delay
Total Harmonic Distortion
RL = 00
RL = 10003
VOUT = 2 Vp-p
Act. = 7, f = 1 kHz

(@

+25"1: anil Vs

ADS539J
Typ

= :t8 V dc, unless otherwisa.noted)

Max

Min

ADS539S
Typ

Max

UI!it8

2

5
6

2

3
5

mV
mV

0.1

2
5

0.1

1
3

!LA
!LA

6

20

6

13

!LA

25

!LA

40

220

220

MHz

1400

1400

MHz

68
82
65
12
600

68
82
65
12

4

600
4

MHz
MHz
MHz
ns
V/fJ.S
ns

0.010
0.016

0.010
0.016

%
%

INPUT IMPEDANCE

100

100

kG

OUTPUT IMPEDANCE (f <10 MHz)

2

2

0

250

250

mV

2.5

2.5

V

85

dB
dB

5

5

""V

4

4

nVv'Hz

INPUT VOLTAGE RANGE
Differential'
(Max Nondestructive)
Common-Mode Voltage
(Max Nondestructive)
Common-Mode Rejection Ratio
l1VCM = 1.7 V
Rs = 100 0
Tmill to T""",
INPUT VOLTAGE NOISE
Wideband RMS Noise (RTI)
BW = 5 MHz; Rs = 500
Spot Noise
F = 1 kHz; Rs = 50 0
OPEN-LOOP GAIN
Vo = +2.3 V, -1.7 V
RL = 15003
R L =2kO
Tmill to T .... -RL = 2 kO

2-154 OPERATIONAL AMPLIFIERS

70
60

47
47
43

85

52

70
60

58
58
63

47
48
46

52

58

57
60

dB
dB
dB

REV. A

AD5539
ADSS39S

ADSS39J
Parameter
OUTPUT CHARACTERISTICS
Positive Output Swing
RL = 15003
R L =2kO
T min to Tmax with
RL = 2kO
Negative Output Swing
RL = 15003
RL = 2kO
T min to T max with
RL = 2 kO

Min

Typ

+2.3
+2.3

+2.8
+3.3

+2.3

Typ

+2.3
+2.5

+2.8
+3.3

Max

-1.7
-1.7

-2.2
-2.9

±8

V
V

14

11

100

-1.7
-2.0

V
V

-1.5

V

,dO

V
V

17
18
14
IS

rnA
rnA
rnA
rnA

1000
2000

...VN
...VN

±8
:tl0

Units

V

-1.5

PSRR
Initial
Tmin to Tmax

PACKAGE OPTIONS6
Plastic (N-14)
Cerdip (Q-14)
J and S Grade Chips Available

Min

+2.3
-2.2
-2.9

POWER SUPPLY (No Load, No Resistor to -Vs)
Rated Perfonnance
Operating Range
:t4.S
Quiescent Current
Initial 1=+
Tmin to Tmax
Initial 1=Tmin to Tmax

TEMPERATURE RANGE
Operating,
Rated Perfonnance
Commercial (0 to + 70°C)
Military (-55°C to + 125°C)

Max

±4.S

18
20
IS
17

14

1000
2000

100

11

AD5539JN, AD5539JQ
AD5539SQ
AD5539JN
AD5539JQ

AD5539SQ, AD5539SQ/883B

NOTES
'Input Offset Voltage specifications are guaranteed after 5 minutes of operation at TA = +25"C.
2Bias Current specifications are guaranteed maximum at either input after 5 minutes of operation at Tit. = + 25OC.
'Rx = 470 to -Vs.
'Externally compensated.
'Defined as voltage between inputs, such that neither exceeds +2.5 V, -5.0 V from ground.
6Por outline information see Package Information section.
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality
levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

n

REV. A

OPERATIONAL AMPLIFIERS 2-155

•

AD5539
ABSOLUTE MAXIMUM RATINGS l
Supply Voltage . . . . . .
· . . . . ±IOV
Internal Power Dissipation
· . . . 550mW
Input Voltage . . . . . . .
+2.5V, -5.0V
Differential Input Voltage .
· . . . . O.25V
-65°e to + l500 e
Storage Temperature Range Q
Storage Temperature Range N
-65°e to + l250C
Operating Temperature Range
AD5539JN
. .. 0 to + 70 e
AD5539JQ . . . . . . . .
. .. 0 to + 700 e
ADS539SQ . . . . . . . .
- 55°e to + 125°e
Lead Temperature Range (Soldering 60 seconds) . . .. 300 e

OFFSET NULL CONFIGURATION

0

VON

OR GROUND

0

NOTES
IStresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those

OUTPUT NULL RANGE

~

".

+ V. (-RR, ) TD - V. (-RR, )
NUU

NUU

OFFSET NULL CONFIGURATION

indicated in the operational section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may· affect
device reliability.

2-156 OPERA TIONAt AMPLIFIERS

REV. A

Typical Characteristics - AD5539
'.0 ,---,---,---""T"---.--......,.

3.5

J3.5~-~r---+--~-~~~-~

3.0

~

", 3.o1---t---t--,rY'--t----1

I
~

2.5

f----t-----c6~--t---_=~=.-~

~

5.0
~ .. I-

,
:

~

I

i

g

;

,
!i!ii2.0

I

..

r:

1:...-"'":l..-"""f---t---t----1

~

1.0 ~5---L---7~--~--~--.J,0·

~

o
10

SUPPLY VOLTAGE -:!: Votts

R =390J!
X

Rx =410n

Rt =100:1 _ _ _
Rl'",,15011

",35
E

,

~

/

G

/,./

~30

~ 25

~

V,.
,.

V,.'

Rt =150U

>3.0

20

R1 =15011. R.=47011--

IE

i

i

1.0

;:c

I

~

i

I

~

100
1k
LOAD RESISTANCE - Ohms

10f---:1t--+--+-

o

10k

I
7
•
SUPPLY VOLTAGE -

5

~

10

Volts

Figure 3. Maximum CommonMode Voltage vs. Supply Voltage

"

Vs == :!:8V
Rx ::: 4701!
Rt ::: 1S0U

~'

~

, 10

~

I

\

~
;;::

-5f---+--+--+-~~~

>

~

V' ,.

~/

+VCM

/

S

I

-

i---

AI =lDOS!. R,,=390n--

15r--~-,---r-_.--,--r--,

/ ,.

i

220

I

--

Rx =470U

Figure 2. Output Voltage Swing
vs. Load Resistance

Figure 1. Output Voltage Swing
vs. Supply Voltage

..

i

.I ~I

0.5

V
~
!
!i -- V-:: -- ---

I

...

~ 1.0

~I 4.0

"

vou,

+1 2 .5

:! 1.5

g

, -- 1-

~,

~

~

:;:10

-10f---+--+--+--4-r-~-~-~

"iii

if

6

"

•

I

......

I
!

3:

-15 f---+--+--+---I

9

2

./

15

7

5

-2~~3--_~2~-_~1~-70-~,-r-~-7--~

10

•

o

OUTPUT VOLTAGE - Vohs

SUPPLY VOLTAGE -:!: Volts

Figure 4. Positive Supply Current
vs. Supply Voltage

10

1

100

1k

10k

FREQUENCY - Hz

Figure 6. Low Frequency Input
Noise vs. Frequency

Figure 5. Input Voltage vs. Output
Voltage for Various Temperatures

80

I 2.lll

~

"

.

Hi~N'C

-10

.

~ -20

": -20

~

r-...
r-....r-.,

r -~

30

./

.1 =1J.l1

VOUT
2V p.p
Rx == 470n
Rl =15011
Vs == ~8V
GAIN = 26dB
(FIGURE 331

-10

u-40

i

~D

VOUT = 2V p.p
Rx = 470n
Rt = 150U

~I~:':
IFIGURE 171

~-50

IJ

HARMONIC

1-30

i
!-50
Co)

2·D

HARMONIC

-40

i--" ~r-

Z

~

:t:

roD

HARMONIC
-60

-60

1M
10M
FREQUENCY - Hz

Figure 7. Common-Mode
Rejection Ratio vs. Frequency

REV. A

100M

-70
1001<

1M

10M
FREQUENCY - Hz

180M

Figure 8. Harmonic Distortion
vs. Frequency - Low Gain

1G

-70

100k

1M

10M

100M

II

1G

FREQUENCY - Hz

Figure 9. Harmonic Distortion
vs. Frequency - High Gain

OPERATIONAL AMPLIFIERS 2-157

•

AD5539
+'0

-2.• r - - - - , - - - , . , - - . . , . - - - . - - - ,

r-'-"""""TT'""""T'""""T'""1"T'I--,--,-n..,.-..,.--.-r-n

'I
~

~

, -2.0

0~+-++~~~+H~~~+-+-+4-H
GAIN

=

~

+2

S-·~~~~-++H-+~~~~-bbH

o

fi1

RL =2kU

~

-'.S

9

GAIN = +7

Vcc=':!:8V

~-'0~~++~~~~~~-H+-+-+4~

~
~ -15 ~~++~--t-~~---l---l-H+-+-++~
I,

~

IE -'.0 I-_-I__+~L+-_-+

is

!i
~

Q

-O.• I---I~~+_--

Evaluating the lead capacitance first (ignoring R LAG and C LAG
for ,now): the feedback network, consisting of R2 and CLEAD '
has a pole frequency equal to:

so

..

\.

9 2.

~

Figure IS illustrates the use of both lead and lag compensation
to permit stable low-gain operation. The AD5539 is shown connected as an inverting amplifier with the required external components added to provide stability and improve high frequency
response. The stray capacitance between the amplifier summing
junction and ground, Cx, represents whatever capacitance is associated with the particular type of op amp package used plus
the stray wiring capacitance at the summing junction.

FA

r ... .....

50

Z

ADss39 when operating at a noise gain of 7. Under these conditions, excess phase shift causes nearly 10 dB of peaking at
ISO MHz.

PHASE _ _ _ _

,

2••

l\\1'

Usually, frequency FA is made equal to F B; that is, (RICx ) =
(R2 C LEAD ), in a manner similar to the compensation used
for an attenuator or scope probe. However, if the pole frequency, FA> will lie above the unity gain crossover frequency
(440 MHz), then the optimum location of FB will be near the

2••

-1.

280

1M

10M

100M

1G

FREQUENCY - Hz

R2

+Vs

Figure 13. Small Signal Open-Loop Gain and
Phase vs. Frequency

1nF

,:a

GENERAL PRINCIPLES OF LEAD AND LAG
COMPENSATION
The AD5539 has its first pole or breakpoint in its open-loop
frequency response at about 10 MHz (see Figure 13). At frequencies beyond 100 MHz, phase shift increases such that the
output lags the input by 1800 - well before the unity gain
crossover frequency. Therefore, severe peaking (and possible
oscillation) will result if the AD5539 is operated at noise gains
below 5, unless external compensation is employed. Figure 14
shows the uncompensated closed-loop frequency response of the

V OUT

'NOISE GAIN' =
+1.

r

~

0

~
GAIN

C

~

PHASE

-

---

~

o
z

120

~

~

o

.

\ I ,

:J -10

Figure 15. Inverting Amplifier Model Showing Both Lead
and Lag Compensation

i
~

1\

180 I

~\

2.J

\

v,.

3••

\
10M
100M
FREQUENCY - Hz

360
1G

Figure 14. AD5539 Uncompensated Response, ClosedLoop Gain = 7

REV. A

V OUT O-.....J\II/'v-.........- . . _ - -....-O

R1

-20

1M

1

-VS

1\

w

~+

Figure 16. A Model of the Feedback Network of the
Inverting Amplifier
OPERATIONAL AMPLIFIERS 2-159

•

AD5539
crossover frequency. Both of these circuit techniques add a large
amount of leading phase shift at the crossover frequency, greatly
aiding stability.

+2

+1

h

The lag network (RLAG, CLAG) increases the feedback attenuation, i.e., the am:plifier operates at a higher noise gain, above
some frequency, typically one-tenth of the crossover frequency.
As an example, to achieve a noise gain of 5 at frequencies above
44 MHz, for the circuit of Figure IS, would require a network
of:

Rl
(4RIIR2) -1

RUG

......
-1

-2

-3

(3)
-4

and ...

-"

(4)

It is worth noting that an R LAG resistor may be used alone, to
increase the noise gain above 5 at all frequencies. However, this
approach has the disadvantage of also increasing the dc offset
and low frequency noise errors by an amount equal to the increase in gain, in this case, by a factor of 5.

SOME PRACTICAL CIRCUITS
The preceding general principles may now be applied to some
actual circuits.
A General Purpose Inverter Circuit
Figure 17 is a general purpose inverter circuit operating at a
gain of -2.
For this circuit, the total capacitance at the inverting input is
approximately 3 pF; therefore, CLEAO from Equations 1 and 2
needs to be approximately 1.5 pF. As shown in Figure 17, a
small trimmer is used to optimize the frequency response of this
circuit. Without a lag compensation network, the noise gain of
the circuit is 3.0 and, as shown in Figure 18, the output amplitude remains within ±0.5 dB to 170 MHz and the -3 dB bandwidth is 200 MHz.

1M

100k

10M

1G

100M

FREQUENCY - Hz

Figure 18. Response of the (Figure 17) Inverter Circuit
without a Lag Compensation Network
A lag network (Figure 15) can be added to improve the response
of this circuit even further as shown in Figures 19 and 20. In
almost all cases, it is imperative to make capacitor C LEAO adjustable; in some cases, CLAG must also be variable. Otherwise,
component and circuit capacitance variations will dominate circuit performance.
+2

!8

,

~
I

-1

o

-2

~

,~

R LAG

+1

~

'"

1',

-3

-4

-"

CLEAD 0.1 - 2.SpF TRIMMER

11

33011
RtAG

~
~

IV'

i.--'
~

tOOk

1M

10M

lG

100M

FREQUENCY - Hz

2k

Figure 19. Response of the (Figure 17) Inverter Circuit
with an RLAG Compensation Network Employed

+BV

+2

!II

,

U

+1

3.5pF

~

son
lOR 7511)

;
~

o

33011
+lOpF

1

t\1t

-2

;!
~ -3

..j

-4

-BV

Figure 17. A General Purpose Inverter Circuit

"

lOOk

1M

10M

100M

lG

FREQUENCY - Hz

Figure 20. Response of the (Figure 17) Inverter Circuit
with an RLAG and a CLAG Compensation Network
Employed
2-160 OPERATIONAL AMPLIFIERS

REV. A

AD5539
Figures 21 and 22 show the small and large signal pulse responses of the general purpose inverter circuit of Figure 17,
with C LEAD =1.5 pF, R LAG =330 n and C LAG =3.5 pF.

R2

2k

+8V

•
-BV

Figure 21. Small Signal Pulse Response of the (Figure 17)
Inverter Circuit; Vertical Scale: 50 mV/div; Horizontal
Scale: 5 ns/div

Figure 23. A Gain of 2 Inverter Circuit with the CLEAD Capacitor Connected to Pin 12
+2.

rg

,

+10

~

"
oct

-10

o

-20

~

~

TO OUTPUT
u o
C ...

I'

~

CLEAD
PIN12

Ui -30

"',

,,

i

'" -40

-5.10Uk
Figure 22. Large Signai Response of the (Figure 17) Inverter Circuit; Vertical Scale: 200 mV/div, Horizontal
Scale: 5 ns/div
A CLEAD capacitor may be used to limit the circuit bandwidth
and to achieve a single pole response free of overshoot

(-3

dB frequency

1)

211' R2 GLEAD

If this option is selected, it is recommended that a C LEAD be
connected between Pin 12 and the summing junction, as shown
in Figure 23. Pin 12 provides a separately buffered version of
the output signal. Connecting the lead capacitor here avoids the
excess output-stage phase shift and subsequent oscillation problems (at approx. 350 MHz) which would otherwise occur when
using the circuit of Figure 17 with a CLEAD of more than about
2 pF.
Figure 24 shows the response of the circuit of Figure 23 for
each connection of C LEAD • Lag components may also be added
to this circuit to further tailor its response, but, in this case, the
results will be slightly less satisfactory than connecting C LEAD
directly to the output, as was done in Figure 17.

REV. A

I"f

1M

10M
FREQUENCY - Hz

100M

,G

Figure 24. Response of the Circuit of Figure 23 with
CLEAD = 10pF

A General Purpose Voltage Follower Circuit
Noninverting (voltage follower) circuits pose an additional complication, in that when a lag network is used, the source impedance will affect the noise gain. In addition, the slightly greater
bandwidth of the noninverting configuration makes any excess
phase shift due to the output stage more of a problem.
For example, a gain of 3 noninverting circuit with CLEAD connected normally (across the feedback resistor - Figure 25) will
require a source resistance of 200 n or greater to prevent UHF
oscillation; the extra source resistance provides some damping as
well as increasing the noise gain. The frequency response plot of
Figure 26· shows that the highest - 3 dB frequency of all the
applications circuits can be achieved using this connection, unfortunately, at the expense of a noise gain of 14.2.

OPERATIONAL AMPLIFIERS 2-161

AD5539
+2

-1

R2

I

+8V

2.

-1

-2

-3

VIN~

-4

150n

-,

lOOk

1M

10M
FREQUENCY - Hz

100M

1G

Figure 28. Response of the Gain of 3 Follower with CLEADCLAG and RLAG
-8V

Figure 25. A Gain of 3 Follower with Both Lead and Lag
Compensation
+2

R2

~

~ I-

These same principles may be applied when capacitor CLEAD is
connected to Pin 12 (Figure 29). Figure 30 shows the bandwidth
of the gain of 3 amplifier for various values of RLAG • It can be
seen from these response plots that a high noise gain is still
needed to achieve a reasonably flat response (the smaller the

2'

+SV

-,

lOOk

1M

10M
FREQUENCY - Hz

100M

1G

Figure 26. Response of the Gain of 3 Follower Circuit

Adding a lag capacitor (Figure 27) will greatly reduce the midband and low frequency noise gain of the circuit while sacrificing only a small amount of bandwidth as shown in Figure 28.

R2

2.

Figure 29. A Gain of 3 Follower Circuit with CLEAD
Compensation Connected to Pin 12

+sv
lnF

VIN~

.

I

iI

-25,OLk-l.-l.....LJ,LlM.,.--J-LL"-,O"-M--'----l...LJ1O-'-O-M-'--.....L.llJ,G

-SV

Figure 27. A Gain of 3 Follower Circuit with Both CLEAD
and RLAG Compensation
2-162 OPERATIONAL AMPLIFIERS

FREQUENCY - Hz

Figure 30. Response of the Gain of 3 Follower Circuit with
CLEAD Connected to Pin 12

REV. A

AD5539
value of R LAG , the higher the noise gain). For example, with a
220 n RLAG and a SO n source resistance, the noise gain will be
12.8, because the source resistance affects the noise gain.

0.1 - 2.5pF

TRIMMER
Uk

Figures 31 and 32 show the small and large signal responses of
the circuit of Figure 29.

+BV

+BV
OFFSET
A~. ~~~~-4-'-{
20k

7511

-sv

-BV

Figure 33. A 20 dB Gain Video Amplifier for 75 [J Systems
Figure 31. The sma/l-signal Pulse Response of the Gain
of 3 Fo/lower Circuit with RLAG and CLEAD Compensation
to Pin 12; Vertical Scale: 50 mV/div; Horizontal Scale:
5 ns/div

_5L-L-LLLL-L-LLll~~~L-L-LLU

lOOk

1M

10M

100M

1G

FREQUENCY - Kz

Figure 34. Response of the 20 dB Video Amplifier
Figure 32. The Large-Signal Pulse Response of the Gain
of 3 Fo/lower Circuit with RLAG and CLEAD Compensation
to Pin 12; Vertical Scale: 200 mV/div; Horizontal Scale:
5ns/div

In color video applications, the quality of differential gain and
differential phase response is very important. Figures 35 and 36
show a circuit and test setup to measure the ADss39's response
to a modulated ramp signal (0-90 IRE p-p ramp, 40 IRE p-p
modulation, 4.4 MHz).

A Video Amplifier Circuit with 20 dB Gain (Terminated)
.High gain applications (14 dB and up) require only a small lead
capacitance to obtain flat response. The 26 dB (20 dB terminated) video amplifier circuit of Figure 33 has the response
shown in Figure 34 using only approximately 0.5-1 pF lead
capacitance. Again, a small CLEAD can be connected, either to
the output or to Pin 12 with very little difference in response.

Figures 37 and 38 show the differential gain and phase response.

REV. A

OPERATIONAL AMPLIFIERS 2-163

AD5539
0.15

10~ IRE = 714~V

O.1-2.5pF
TRIMMER
•. 1

1kll

+8V

i

1nF

l,

0.05

I
49.9U

~~

~

Vo

~149'91l
-=

LOAD

""... V--

~

~ -0".05

i
-0.1

-0.15

•

36

18

54

72

90

RAMP AMPLITUDE - IRE

Figure 38. Differential Phase vs. Ramp Amplitude

··8V

Figure 35. Differential Gain and Phase Measurement
Circuit

RAMP

WAVEFORM

Figure 36. Differential Gain and Phase Test Setup

....
..,

TO
TEKTRONICS
7B5417A24 ~
OSCILLOSCOPE
PREAMP
'::"

430n

430n

10~ IRE = 71~mv

•.04

-

Z

~

MEASURING AD5539 SETTLING TIME
Measuring the very rapid settling times associated with AD5539
can be a real problem for the designer; proper component layout
must be used and appropriate test equipment selected. In addition, both cable dispersion (a function of cable losses) and the
quality of termination (SWR) directly affect the measurement.
The circuit of Figure 39 was used to make a "brute force"
AD5539 settling time measurement. The fixture containing the
circuit was connected directly - using a male BNC connector
(but no cable) - onto the. front of a 50 n input oscilloscope
preamp. A digital mainframe was then used to capture, average,
and expand the error signal. Most of the small-scale waveform
aberrations shown on the figure were caused by the oscilloscope
itself, especially the glitch at 15 ns. The pulse source used for
this measurement was an EH-SPG2000 pulse generator set for a
1 ns rise-time; it was coupled directly to the circuit using 18" of
microwave 50 n hard line.

0.02

~ •~
m

V

i"'v

Q

-0,02

-0.0 4
18

3.

54

n

9.

son

~

51,n

son

V OUT

~

EH SPG2000
PULSE
GENERATOR

RAMP AMPLITUDE - IRE

-BV

Figure 37. Differential Gain vs. Ramp Amplitude
Figure 39. AD5539 Settling Time Test Circuit

2-'-164 OPERATIONAL AMPLIFIERS

REV. A

AD5539
APPLICATIONS SUMMARY CHART

Gain = -I to -5
Circuit of Fig. 17

Rl

R2'

R2

2k

-

Gain = -I to -5
Circuit of Fig. 23

R2

2k

Gain = -2 to
Circuit of Fig. 27

GAIN
FLATNESS
(TRIMMED)

3 pF

-2

±0.2 dB

200 MHz

3 pF

-2

±I dB

180 MHz

3 pF

+3

±I dB

390 MHz

+3

±0.5 dB

340 MHz

±0.2 dB

80 MHz

±0.2 dB

80 MHz

2

;;; 2

7r

1
(44 x 1(j6) R LAG

=G

Rl
RI
4 R2 - 1

;;; 2

7r

(44

X

1
106) R LAG

=G

Rl
RI
10 R2 - 1

;;; 2

7r

(44

X

1
106) R LAG

= G-l

~---

G

GAIN

CLEAn

RI
RI
4 R2 - 1

~---

G

CLAG2

RLAG

3dB
BANDWIDTH

+5 3

Gain = +2 to +5'
Circuit of Fig. 29

R2

G-l

2k
~

R2
--

2k

R2

1.5 k

NA

NA

Trimmer'

1.5k

NA

NA

Trimmer'

~

G-l

Gain

< -5

NA

RI
RI
IOR2-1

3 pF

= G-I
-20

G
Gain >+5

R

G-I

+20

NOTES
G=Gain NA=Not Applicable
'Yalues given for specific results summarized here-applications can be adapted for values different than those specified.
2It is recommended that C LEAD and CLAG be trimmers covering a range that includes the computed value above.
3RsoURCE

;;:=:200

4RsoURCE

~50

n.

n.

'Use Yoltronics CPA2 0.1-2.5 pF Teflon Trimmer Capacitor (or equivalent).

The photos of Figures 40 and 41 demonstrate how the ADSS39
easily settles to 1% (l m V) in less than 12 ns; settling to 0.1%
(100 jI.V) requires less than 25 ns.

UZR 1.2

-

_--1 _1_ ::I

I

soo",ul

- -

I

+- -

~I'IS
-I -

:

1
j

t

-

I

--;:- -

t

-

-

I
--'-I~-

Figure 40. Error Signal from AD5539 Settling Time Test
Circuit - Falling Edge. Vertical Scale: 5 ns/div.; Horizontal
Scale: 500 poV/div

REV. A

--+

+-t--'--

Figure 41. Error Signal from AD5539 Settling Time Test
Circuit - Rising Edge. Vertical Scale: 5 ns/div.; Horizontal
Scale: 500 poV/div

OPERATIONAL AMPLIFIERS 2-165

•

AD5539

f

Figure 42 shows the oscilloscope response of the generator alone,
set up to simulate the ideal test circuit error signal (Figure 43).

.n..

H INDUSTRIES
SPG2000 PULSE GENERATOR OUTPUT

--r-IV

,

S4nV

-

-

DHCPD - 24.e)nS
CRS1)

o OF 1

Figure 42. The Oscilloscope Response Alone Directly
Driven by the Test Generator. Vertical Scale: 5 ns/div.:
Horizontal Scale: 500 ILV/div

Figure 43. A Simulated Ideal Test Circuit Error Signal

A 50 MHz VOLTAGE-CONTROLLED AMPLIFffiR
Figure 44 is a circuit for a 50 MHz voltage-controlled amplifier
(VeA) suitable for use in high quality video-speed applications.
This circuit uses the AD5539 as an output amplifier for the
ADS39, a high bandwidth multiplier. The outputs from the two
signal channels of the AD539 are applied to the op amp in a
subtracting configuration. This connection has two main advantages: first, it results in better rejection of the control voltage,
particularly when over-driven (Vx3.3 V). Secondly,
it provides a choice of either noninverting or inverting responses, using either input VYl or VY20 respectively. In this circuit, the output of the op amp will equal:

Hence, the gain is unity at Vx = +2 V. Since Vx can overrange to +3.3 V, the maximum gain in this configuration is
about 4.3 dB. (Note: If Pin 9 of the AD539 is grounded, rather
than connected to the output of the 5539N, the maximum gain
becomes 10 dB.)

VOUT Vx (Vy! - Vnl fi V >0
2V
or x
+9V
2.7U

The bandwidth of this circuit is over 50 MHz at full gain, and is
not substantially affected at lower gains. Of course, when Vx is
zero (or slightly negative, to override the residual input offset)
there is still a small amount of capacitive feedthrough at high
frequencies; therefore, extreme care is needed in laying out the
PC board to minimize this effect. Also, for small values of Vx ,
the combination of this feedthrough with the multiplier output
can cause a dip in the response where they are out of phase.
Figure 45 shows the ac response from the noninverting input,
with the response from the inverting input, Vy2 , essentially
identical. Test conditions: VYl = 0.5 V rms for values of Vx
from +10 mV to +3.16 V; this is with a 75 n load on the output. The feedthrough at Vx = -10 mV is also shown.

1.

VI('" +3.1B2V

~
V =+1V

-10

.,.
! -20

" l".

v x = +O.316V

~

f\ 1'-

VI('" +O.lV

1-30
II!

~

I"

VI("" +O.032V

-40
Vx "'+O.OlV

-50
VJ-O,01V
01: THOMPSON.CSF BAR·tO ORSIMILARSCHQTTKY DIODE

'¢

Z.7U

SHORT.~CONNEcnONTOGROUNDPLANE.

L'I.

-6D
1

/

~

~~
1.

~

1DO

fREQUENCY - MHz

-9V

Figure 44. A Wide Bandwidth Voltage-Controlled Amplifier

2-166 OPERATIONAL AMPLIFIERS

Figure 45. AC Response of the VCA at Different Gains
Vy = 0.5VRMS

REV. A

AD5539
The transient response of the signal channel at Vx = + 2 v,
Vy = VOUT = + or -I V is shown in Figure 46; with the VCA
driving a 75 n load. The rise and fall times are both approximately 7 ns.
A few final circuit details: in general, the control amplifier compensation capacitor for Pin 2, Ce , must have a minimum value
of 3000 pF (3 nF) to provide both circuit stability and maximum control bandwidth. However, if the maximum control
bandwidth is not needed, then it is advisable to use a larger
value of Ceo with typical values between 0.01 and 0.1 ILF. Like
many aspects of design, the value of Ce will be a tradeoff:
higher values of Cc will lower the high frequency distortion,
reduce the high frequency crosstalk and improve the signal
channel phase response. Conversely, lower values of Cc will provide a higher control channel bandwidth at the expense of degraded linearity in the output response when amplitude
modulating a carrier signal.
The control channel bandwidth will vary in inverse proportion
to the value of Ceo providing a typical bandwidth of 2 MHz
with a Ce ofO.OlILF and a Vx voltage of +1.7 volts.
Both the bandwidth and pulse response of the control channel
can be further increased by using a feedforward capacitor, Clf,
with a value between 5 and 20 percent of Ce .
should be
carefully adjusted to give the best pulse response for a particular
step input applied to the control channel. Note that since Clf is
connected between a linear control input (Pin I) and a logarith-

err

lOll

Figure 46. Transient Response of the Voltage-Controlled
Amplifier Vx = +2 Volts, Vy = ±1 Volt
mic node, the settling time of the control channel with a pulse
input will vary with different control input step levels.
Diode D I clamps the logarithmic control node at Pin 2 of the
AD539, (preventing this point from going too negative); this
diode helps decrease the circuit recovery time when the control
input goes below ground potential.
THE AD539/5539 COMBINATION AS A FAST, LOW
FEEDTHROUGH, VIDEO SWITCH
Figure 47 shows how the AD539/5539 combination can be used
to create a fast video speed switch suitable for many high fre-

0.47"F

7511 J3

+9V

~75U
OUTPUT

+9V
2.7U
Rx
470U

SIGNAL

OPTIONAL
TERMINATION

J2 \

NON.
INVERTING
INPUT

~;-"'~""'~f---t

InF

+9V ~

7511

V

lOOk

I

-JI,I\I'vo1

lOll

50k

Vos

-9V

-9V

J4 7511

n

t----.-J~r_--~~CONTROL-l
DENOTES SHORT.
DIRECT CONNECTION
TO GROUND PLANE

887U

-9V

~ INPUT

L-

+ 1V (OFF)
0 (ON)

'VALUE WILL VARY SLIGHTLY
WITH COMPONENT LAYOUT

Figure 47. An Analog Multiplier Video Switch

REV. A

OPERATIONAL AMPLIFIERS 2-167

•

AD5539
quency applications incJudfug color key switching. It features
both inverting and noninverting inputs and can provide an output of ± 1 V into a reverse-terminated 75 n load (or ±2 V into
150 n). An optional output offset adjustment is provided. The
input range of the video switch is the same as the output range:
± 1 V at either input generates ± I V (noninverting) or.:;: 1 V
(inverting) across the 75 n load. The circuit provides a gain of
about 1, when "ON," .or zero when "OFF."

The differential-gain and differential-phase characteristics of this
compatible with video applications. The incremental
switch
gain changes less than 0.05 dB over a signal window of 0 to
+ 1 V, with a phase variation of less than a.5 degree at the subcarrier frequency of 3.58 MHz. The noise level of this circuit
measured at the 75 n load is typically 200 Il.V in a 0 to 5 MHz
bandwidth or approximately· 100 nV per root hertz. The noise
spectral density is essentially flat to 40 MHz.

The differential configuration useS both, channels of the ADS39
not only to provide alternative input phases, but also to eliminate the switching pedeStal due to steP changes in the output
current as the AD539 is gated· on or off.

The waveforms shown in Figures 48 and 49 were taken across a
75 n termination; in both photos, the signal of 0 to + 1 V (in
this case, an offset sine wave at 1 MHz) was applied to the noninverting input. In Figure 48, the envelope response shows the
output being fully switched in about 50 ns. Note that the output
is ON when the control input is zero (or more negative) and
OFF for a control input of + 1 V or more. There is very little
control-signBI breakthrough.

Figure 49 shows the response to a pulse of 0 to + I V on the
signal channel. With the control input held at zero, the rise time
is under IOns. The response from the inverting input is similar.

Figure 48. The Control Response of the Video Switcher

2-168 OPERATIONAL AMPLIFIERS

are

Figure 49. The Signal Response of the Video Switcher

REV. A

Low Noise Precision
Operational Amplifier
OP-27 I

~ANALOG

WDEVICES
FEATURES
• Low Noise .................... SOnVp _p (0.1 Hz to 10Hz)

....... ..... .................... .......... 3nV/J"HZ
• Low Drift .................................. 0.2p.V/oC
• High Speed . . . . . . . . . . . . . . . . . . . . . . .. 2.SV1p's Slew Rate
............................... SMHz Gain Bandwidth
• Low Vos ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10p.V
• Excellent CMRR ............... 126dB at VCM of ± 11V
• High Open-Loop Gain. . . . . . . . . . . . . . . . . . . .. 1.S Million
• Fits 725, OP-07, OP-05, AD510, AD517, 5534A sockets
• Available in Die Form

ORDERING INFORMATION t
PACKAGE
TA =+25°C
VosMAX
(~V)

25
25

60
60
100
100
100

It

To-99

CERDIP
8-PIN

OP27AJ+
OP27EJ
OP27BJ+
OP27FJ
OP27CJ
OP27GJ

OP27P;Z+
OP27EZ
OP27BZ+
OP27FZ
OP27CZ
OP27GZ

PLASTIC
8-PIN

OPERATING
LCC
TEMPERATURE
RANGE
20-CONTACT

OP27EP
OP27BRl883
OP27FP
OP27GP
OP27Gstt

Mil
IND/COM
Mil
IND/COM
Mil
XIND
XIND

For devices processed in total compliance to Mll-STD·883, add 1883 after part
number. Consult factory for 883 data sheet.
Burn-in is available on commercial and industrial temperature range parts in
CerDIP, plastic DIP, and TO·can packages.
For availability and burn·in information on SO and PlCC packages, contact
your local sales office.

GENERAL DESCRIPTION
The OP-27 precision operational amplifier combines the low
offset and drift of the OP-07 with 'both high-speed and lownoise. Offsets down to 25p.V and drift of 0.6p.Vio C maximum
make the OP-27 ideal for precision instrumentation applications. Exceptionally low noise, en = 3.5nV/y'"HZ, at 10Hz, a
low 1/f noise corner frequency of 2.7Hz, and high gain (1.8
million), allow accurate high-gain amplification of low-level

signals. A gain-bandwidth product of 8MHz and a 2.8V/p.sec
slew rate provides excellent dynam ic accu racy in high-speed
data-acquisition systems.
A low input bias current of ±10nA is achieved by use of a
bias-current-cancellation circuit. Over the military temperature range, this circuit typically holds Ie and los to ±20nA
and 15nA respectively.
The output stage has good load driving capability. Aguaranteed swing of ± 10V into 600n and low output distortion make
the OP-27 an excellent choice for professional audio applications.
PSRR and CMRR exceed 120dB. These characteristics.
coupled with long-term drift ofO.2p.Vimonth, allow the circuit
designer to achieve performance levels previously attained
only by discrete designs.

PIN CONNECTIONS

BALfitBAL'7V+
-IN2

6 OUT

+IN 3

5 N.C.
4V- (CASE)

TO-99
(J-Sufflx)

S-PIN HERMETIC DIP
(Z-Suffix)
EPOXY MINI-DIP
(P-Suffix)
S-PINSO
(S-Suffix)
OP-27BRC/SS3
LCCPACKAGE
(RC-Sufflx)

SIMPLIFIED SCHEMATIC

OUTPUT

NON·

INVERTING

INPUT f",+I-I--+~~f-"""""",=-~
INVERTING

INPUT "'H-4.....-

t----f----...J

.......

• R1. R2 ARE PERMANENTLY ADJUSTED
AT WAFER TEST FOR MINIMUM
OFFSET VOLTAGE.

REV. A

L-_ _ _ _ _ _~-....---~~_ _ _~__.......~~~v-

OPERATIONAL AMPLIFIERS 2-169

2

OP-27
Low cost, high-volume production of OP-27 is achieved by
using an on-chip zener-zap trimming network. This reliable
and stable offset trimming scheme has proved its effectiveness over many years of production history.

Operating Temperature Range
OP-27A, OP-27B, OP-27C (J, Z, RC) ........ -55·C to + 125·C
OP-27E, OP-27F (J, Z) .•••••.......................... -25°C to +85°C
OP-27E, OP-27F (P) •..••.....................•............. O°C to +70°C
OP-27G (P, S, J, Z) ...................................... -40°C to +85°C
Lead Temperature Range (Soldering, SO sec) .............. 300°C
Junction Temperature ................................... -65°C to + 150°C

The OP-27 provides excellent performance in low-noise
high-accuracy amplification of low-level signals. Applications include stable integrators, precision summing ampli~
fiers, precision voltage-threshold detectors, comparators,
and professional audio circuits such as tape-head and
microphone preamplifiers.

PACKAGE TYPE

e lA (Note 3)

T(),99 (J)

150
148
103

8-Pin Hermetic DIP (Z)

The OP-27 isa direct replacementfor725, OP-oS, OP-07 and
OP-05 amplifiers; 741 types may be directly replaced by
removing the 741's nulling potentiometer.

8-Pin Plastic DIP (P)
20-Contact LCC (RC)

UNITS

18
16

"CJW

oelW
oelW
oelW
oelW

43
38
43

98
158

8-Pin SO(S)

e lc

NOTES:
1. For supply VDltages less than ±22.V, the absolute maximum Input voltage is
equal to the supply voltage.
2. The OP-27"s InpUls are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low noise. If diflerentiallnput voltage
exceeds ~.7V, the input current should be limited to 25mA.
3. eiA is specified for worst case mounting conditions, i.e., eiA is specified for
device in socket for TO, CerDIP, P-DIP, and LCC packages; e' A is spacified
for device soldered to printed circuit bosrd for SO package. J
4. Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.

ABSOLUTE MAXIMUM RATINGS (Note 4)
Supply Voltage ................................................................. %22V
Input Voltage (Note 1) ...................................................... %22V
Output Short-Circuit Duration ................................... Indefinite
Differential Input Voltage (Note 2) .................................. %0.7V
Differential Input Current (Note 2) ................................ %25mA
Storage Temperature Range ........................ -65·C to +150·C

ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = 25·C, unless otherwise noted.
OP-27A/E
PARAMETER

SYMBOL CONDITIONS

Input Offset Voltage

Vos

Long-Term Ves

Stability

lOS

Input Bias Current

Ie

Input Noise
Voltage Density

enp _p

(Notes 3. 5)

fo= 10Hz (Note3!

fO= 30Hz 1Note 3)
fo= 1000Hz INote3,

in

fa = 30Hz 1Notes 3, 61

fo= 10Hz (Notes 3,6,
fo= 1000Hz (Notes 3, 61

Input Resistance Differential-Mode

O.IHz to 10Hz

RIN

INote71

MAX

10
0.2

MIN

TYP

MAX

TYP

MAX

UNITS

25

20

60

30

100

~V

1.0

0.3

1.5

0.4

2.0

/lV/Mo

50

12

Input Voltage Range
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio

75

nA

±40

±12

±55

±15

±80

nA

0.08

0.18

0.08

0.18

0.09

0.25

~Vp-p

3.5
3.1
3.0

5.5
4.5
3.8

3.5
3.1
3.0

5.5
4.5
3.8

3.8
3.3
3.2

8.0
5.6
4.5

nVl..jHZ

1.7
1.0
0.4

4.0
2.3
0.6

1.7
1.0
0.4

4.0
2.3
0.6

1.7
1.0
0.4

0.6

0.94

1.3

Voltage Gain
Output Voltage
Swing

IVR

Slew Aate

=±11V

CMRR

VCM

PSRR

Vs = ±4V to ±18V

Avo

RL "2kll. VO=±10V
RL ,,60011. Vo = ± 10V

Vo
SR

pAl..jHZ

0.7

Mil

2.5

R'NCM

Large-Signal

MIN

±10

Input ReslstanceCommon-Mode

OP-27C/G

OP-27B/F

TYP

35

en

Input Noise
Current Density

(Note11

Ves/Time (Notes 2,31

Input Offset Current

Input Noise Voltage

MIN

±11.0

±12.3

±11.0

±12.3

±11.0

±12.3

V

114

126

106

123

100

120

dB

10

10
1000
800

1800
1500

1000
BOO

1800
1500

RL~2kn

±12.0

±13.8

±12.0

RL " 80011

±10.0

±11.5

±10.0

1.7

2.8

1.7

AL

~

2kn •Note 4·

2-170 OPERATIONAL AMPLIFIERS

Gil

20
700
600

1500
1500

±13.8

±11.5

±13.5

±11.5

±10.0

±11.5

2.8

1.7

2.B

~VN

VlmV

V
Vlp,s

REV. A

OP-27
ELECTRICAL CHARACTERISTICS at Vs

= ±15V, TA = 25°C, unless otherwise noted. (Continued)
OP-27A/E

PARAMETER

SYMBOL CONDITIONS

Gain Bandwidth Prod. GBW
Open-Loop Output
Resistance

Power Consumption

(Note 4)

MIN

TYP

5.0

8.0

RO

70

Pd

90

OP-27B/F
MAX

MIN

TYP

5.0

8.0

OP-27C/G
MAX

MIN

TYP

5.0

8.0

MHz

70

n

70
140

90

140

100

MAX

170

UNITS

mW

Offset Adjustment

__
~~_________________R_p_=__
10_k_n___________________±_4_.0
____________________±_4_.0____________________±_4_._0_____________
m_v_
_Range
NOTES:
1. Input offset voltage measurements arB performed - 0.5 seconds after
application of power. AlE grades guaranteed fully warmed-up.
2. Long·term input offset voltage stability refers to the average trend line of
Vas VS. Time over extended periods after the first 30 days of operation.
Excluding the initial hour of operation, changes in Vas during the first 30

days are typically 2.5"V - refer to typical performance curve.
3. Sample tested.
4. Guaranteed by design.
5. See test circuit and frequency response curve for 0.1 Hz to 10Hz tester.
6. See test circuit for current noise measurement.
7. Guaranteed by input bias current.

ELECTRICAL CHARACTERISTICS for Vs = ± 15V, -55° C ::; TA::; + 125° C, unless otherwise noted.
OP-27A
PARAMETER

SYMBOL

CONDITIONS

Input Offset Voltage

Vas

(Note 11

Average Input
Offset Drift

TeVos
TCVoSn

(Note 2)

Input Offset Current

los

Input Bias Current

Ie

Input Voltage Range

IVR

Common-Mode
Rejection Ratio

CMRR

Power Supply
Rejection Ratio

PSRR

Vs = ±4.5V to ±18V

Large-Signal
Voltage Gain

AyO

RL ,,2kU, Vo =±10V

Output Voltage
Swing

Va

MIN

(Note 31

OP-27B

TYP

MAX

30

0.2

MIN

OP-27C

TVP

MAX

MIN

TVP

MAX

UNITS

80

50

200

70

300

"V

0.6

0.3

1.3

0.4

1.8

15

50

22

85

30

135

nA

±20

±80

±28

±95

±35

±150

nA

±10.3

±11.5

±10.3

±11.5

±10.2

±11.5

V

108

122

100

119

94

116

dB

16

4

20

51

,.VN

800

1200

500

1000

300

800

VlmV

±11.5

±13.5

±11.0

±13.2

±10.5

±13.0

V

ELECTRICAL CHARACTERISTICS at VS =±15V, -25°C,; TA ,; +85°C for OP-27J and OP-27Z, DoC,; TA ,; +70°C for OP-27EP,
FP and -40°C ,; TA ,; +85°C for OP-27GP, GS, unless otherwise noted.
OP-27F

OP-27E
PARAMETER

SYMBOL

Input Offset Voltage

Vas

Average Input
Offset Drift

TCVOS
TCVOS.

Input Offset Current

los

Input Bias Current

Ie

Input Voltage Range

IVR

Common-Mode
Rejection Ratio

CONDITIONS

(Note21
(Note 31

CMRR

Power Supply
Rejection Ratio

PSRR

large-Signal
Voltage Gain

AyO

Output Voltage
Swing

Va

MIN

MAX

UNITS

40

140

55

220

"V

0.6

0.3

1.3

0.4

1.8

"VlOC

0.2

MIN

10

50

14

85

20

135

nA

±14

±80

±18

±95

±25

±150

nA

±10.5

±11.8

±to.5

±11.8

±10.5

±11.8

V

110

124

102

121

98

118

dB

15

VS =±4.5VIO ±18V

16

2

32

"VN

750

1500

700

1300

450

1000

VlmV

±11.7

±13.6

±11.4

±13.5

±11.0

±13.3

V

Input offset voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power. AlE
grades guaranteed fully warmed-up.

REV. A

TVP

50

20

NOTES:
1.

MAX

MAX

MIN

OP-27G

TYP

TYP

2. The TeVos performance is within the specifications unnulled or when
nulled with Rp = 8kU to 20kU. TCVos is 100% tested for AlE grades,
sample tested for BICIFIG grades.
3. Guaranteed by design.

OPERA TlONAL AMPLIFIERS 2-171

2

OP-27
DICE CHARACTERISTICS
1.
2.
3.
4.
6.

NULL
(-) INPUT
(+) INPUT
VOUTPUT

7. V+
8. NULL
For additional DICE ordering Information,
refer to 1990/91 Data Book, Section 2.

DIE SIZE 0.109 x 0.055 inch, 5995 sq. mils
(2.77 x 1.40mm, 3.88 sq. mm)

WAFER TEST LIMITS at Vs = ± 15V, T A = 25° C for OP-27N, OP-27G, and OP-27GR devices; T A = 125 0 C for OP-27NT and
OP-27GT devices, unless otherwise noted.
OP-27NT
PARAMETER

SYMBOL

CONDITIONS

Input Offset Voltage

Vas

(Note 11

Input Offset Current

los

Input Bias Current

IB

Input Voltage Range

IVR

Common-Mode
Rejection Ratio

CMRR

VCM = IVR

Power Supply
Rejection Ratio

PSRR

Vs = ±4V to ±18V

Large-Signal
Voltage Gain

Ava

RL ", 2kO. Vo= ±10V
RL "'6000. Vo =±10V

Output Voltage Swing

Va

R L ::=: 2kfl
R L "'6000

Power Consumption

Pd

OP-27N OP-27GT

OP-27G OP-27GR

LIMIT

LIMIT

LIMIT

LIMIT

LIMIT

UNITS

60

35

200

60

100

p.VMAX

50

35

85

50

75

nAMAX

±60

±40

±95

±55

±80

nAMAX

±10.3

±11

±10.3

±11

±11

VMIN

108

114

100

106

100

dB MIN

10

20

p.V/v MAX

V/mVMIN

10
600

1000
BOO

500

1000
BOO

700
600

±11.5

±12.0
±10.0

±11.0

±12.0
±10.0

±11.5
±10.0

VMIN

140

170

mWMAX

140

Vo=O

NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

TYPICAL ELECTRICAL CHARACTERISTICS at Vs =

± 15V, TA =

+25 0 C, unless otherwise noted.

OP-27N

OP-27G

OP-27GR

TYPICAL

TYPICAL

TYPICAL

UNITS

0.2

0.3

0.4

p.VloC

TCtos

80

130

180

pN°C

Average Input Bias
Current Drift

TCI B

100

160

200

pA/oC

tnput Noise
Voltage Density

eo

fo= 10Hz
fo= 30Hz
fo~ 1000Hz

3.5
3.1
3.0

3.5
3.1
3.0

3.B
3.3
3.2

nV/VHZ

Input Noise
Current Density

io

fo= 10Hz
fo~ 30Hz
fo~ 1000Hz

1.7
1.0
0.4

1.7
1.0
0.4

1.7
1.0
0.4

pA/VHZ

0.08

0.08

0.09

!,Vp-p

2.8

2.8

2.8

V/p.s

PARAMETER

SYMBOL

CONDITIONS

Average Input Offset
Voltage Drift

TCVos or
TCVoSn

Nulled or Un nulled
Rp ~ 8kO to 20kO

Average Input Offset
Current Drift

Input Noise Voltage

e np _p

0.1Hz to 10Hz

Slew Rate

SR

R L ", 2kll

Gain Bandwidth Protluct

GBW

MHz

NOTE:
1. Input offset voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power.

2-172 OPERA TIONAL AMPLIFIERS

REV. A

OP-27
TYPICAL PERFORMANCE CHARACTERISTICS
O.1Hz TO 10Hzp _p NOISE TESTER
FREQUENCY RESPONSE

-

'09

'00 r-1rTl"lTl11r-rrr

'00

•

90 H-t.lill'lHt-'H+

7

1 70 Hrtt-tHttt-H+

-

(5
Z 3
w

;::

~ 60 H'-H-flfHHH+

~

g

TEST TIME OF 10 SEC FURTHER

~.oL.,. .L.lwliL.L'l lw

t--

74'

TA - 25"C
Vs '" ±15V

~: ~,
~ 4 ,....
,

.0~'-H-flfHf---iH+

50

A COMPARISON OF
OP AMP VOLTAGE
NOISE SPECTRA

VOLTAGE NOISE DENSITY
VI FREQUENCY

Ilf CORNER
= 2.7Hz

2

Ilf CORNER

Ilf CORNER
2.1Hz

1£

N

O

10

100

,,

INPUT WIDEBAND VOLTAGE
NOISE vs BANDWIDTH (O.1Hz
TO FREQUENCY INDICATED)

I'f CORNER

'000

1IIIII

III

AUDIO RANGE

INSTRUMENTATION
RANGE, TO DC

TO 20kHz

10

100

'000

FREQUENCY (Hz)

FREQUENCY (Hz)

FREQUENCY (Hz)

OP AMP

~ ~OP'27

,
1

LOW NOISE
AUDIO

:::l~

11111111

IISlolLl .:_°J.WIJ.IIF.ulliUJE
IIQIWI,IUIL..:.J1C.J1...L1.u'
11111lII·I,Il..'I:_"u.I.1JUJJJ,oo
I

•

,

......

TOTAL NOISE vs SOURCE
RESISTANCE
,ooF=FATFFf1F====='=fI

VOLTAGE NOISE DENSITY
VI TEMPERATURE

i=
=.,
t-~_v-j~_=-j"r-rt+t-rtt-=_

4>-

T -25'C

5V

1--t-t-l+f+ltI-- RS = 2R,

~ 10!'!!!~~!lII~~~~~!II
~

:- AT 'OH,
AT 1kHz

0.01 '--'-J...I.UJ.II.1---1...I...J..L.I.I.I.II......I...LLllLW

lk
10k
BANDWIDTH (Hz)

'00

lOOk

100

VOLTAGE NOISE DENSITY
VI SUPPLY VOLTAGE

--

~

~

z

3

w

-50

-25

0

25

50

TEMPERATURE

76

100

125

fe)

SUPPLY CURRENT VI
SUPPLY VOLTAGE
5.0

10.0

1 4.0

AT 10Hz

t-

,'-~-~--~--~--~--~~

10k

1m

CURRENT NOISE DENSITY
VI FREQUENCY

T!.2S'C
~4

lk
SOURCE RESISTANCE

....

~
a:
a: 3.0

"

AT 1kHz

~

g2

""
~

iil 2.0

Ilf CORNER

,

o.
o

10

~

~

TOTAlSUPPlV VOLTAGE (V+ - V-I (VOLTS)

REV. A

~

,

- r- = 140Hz

'0

11111111

I

100
lk
fREQUENCY (Hz)

1.0
'Ok

S

'5

25

35

45

TOTAL SUPPLY VOLTAGE (VOLTS)

OPERA TIONAL AMPLIFIERS 2-173

OP-27
TYPICAL PERFORMANCE CHARACTERISTICS
OFFSET VOLTAGE DRIFT OF
EIGHT REPRESENTATIVE UNITS
VB TEMPERATURE.
60
40

~

r-

20

~

w

11
:;

V
V

./

V
./

....... ~ -< V"
....... ......
.".,

0

g

...

~ '-

~ -20

o

........

-60

T~Vasl
50

25

0

25

-

.:'

a'TA

:::---

-......;;

-2
OP-27B
OP·27A

~i'...

"

OP-27 ClG

50

..".. ~

fe)

/'..

I
I

"

75 100

"""

-2
-4

QP·27C

-6

125 150 175

-

50

w

W
BA"

II
THER~

SHOCK
RESPONSE

I I I
A I I I I

" t-....

10

I'-r-.

0

...

OP-278

k:u

20

40

-"

60

BO

-50

100

-26

"-

125

1

0

.'-.SLEW

'\.

I'\.

-1 0

1k
10k lOOk
FREQUENCY (Hz)

1M

10M 100M

2-174 OPERA TlONAL AMPLIFIERS

-50 -25

,....

0
25
50
75
TEMPERATURE COC)

-5

100

125

100

T~ J2~~1
Vs = ±15V

125

1M

60
100
120·_

40~Ii:

\

1

PHASE \
MARGIN

60~

-71f'

II

-

~.27A

0
25
50
75
TEMPERATURE (OCI

~Lj

-10
-75

-25

~

t\

II'-

"- I'-

25
20

10

50

QP·27B

GAIN, PHASE SHIFT vs
FREQUENCY

15

-GBW

~

-I--:

-75 -50

150

=~M

60

"-

100

100

VS,",±l5V-

"- I'-

10

0
26
50
15
TEMPERATURE tOCI

SLEW RATE, GAIN-BANDWIDTH
PRODUCT, PHASE MARGIN VB
TEMPERATURE
70

0

,,,"
,~ ~ t'--

OP-27A

OPEN-LOOP GAIN vs
FREQUENCY

130

JJ-

III

TIME (SEC)

110

I
0

IN 7rrC OIL BATH

0
~ -20

50

I i OP-27C

; - - ~ DEVICE IMMERSED

5
~

OP·27 AlE

INPUT OFFSET CURRENT
vs TEMPERATURE

IJU

20

B/F

TIME AFTER POWER ON (MINUTES)

II
30
I ,ill OP·27C
r\ \ 1\

I I I I

......
~

ap.J

f-

V

INPUT BIAS CURRENT
vs TEMPERATURE

TA = looC

V

00

o

40

I

-.... r-

TIME (MONTHS)

V~:~'5)-

111111

w 10

~
/

L

.....,

I I I II I

;-;-;-;--

L+2..J

r-- Vs -±16V

-6

OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK

25"C

-

-4

OP-Z7B

TEMPERATURI,:

TA"

WARM-UP OFFSET
VOLTAGE DRIFT

OP·27A

I--- ,.."

TRfMMING WITH"""
10k POT DOES
NOT CHANGE

-75

OP-27C
OP-27B

I

-

-40

LONG-TERM OFFSET
VOLTAGE DRIFT OF SIX
REPRESENTATIVE UNITS

1

\

"

~

180 ..
200

r\.

10M

220
100M

FREQUENCY (Hz)

REV. A

OP-27
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN-LOOP VOLTAGE GAIN
vs SUPPLY VOLTAGE
28

I

2.
5

RL = 2kn

y

2. o - T A '" 2SOC

:;-

/'

~

Ui 24

!:;
o
?
w
c

RL""SOOn

./ . / f -

zl. 5

g
~

Vs '" ±15V

14

I-

12

r-

20

POJITIJe

NEGATIVE
SWING

/1
r'l'

" 12

..::I~

.

"

::'

o

50

10
20
30
40
TOTAL SUPPLY VOLTAGE (VOLTS)

\

8

0.0

1k

SMALL-SIGNAL OVERSHOOT
vs CAPACITIVE LOAD

•

V

10

:i

r-

SWING

~

0.5

o

16

:>

,V

~1.0

18

Ill~LW

!: 16

~ /"

~

MAXIMUM OUTPUT VOLTAGE
VI LOAD RESISTANCE

MAXIMUM OUTPUT SWING
vs FREQUENCY

TA = 25°C

f--

i'10k

lOOk
1M
FREQUENCY {H:d

Vs = ±15V

I III

-2
10M

100

SMALL-SIGNAL TRANSIENT
RESPONSE

1k
LOAD RESISTANCE 1m

10k

LARGE-SIGNAL TRANSIENT
RESPONSE

100
5amV

+5V

OV

OV

-50mV

-5V

80

,;

0

40

20

o

/

/

/

o

Vs = t15V

VIN"',OOmV AV=+l

I
500

AVCl = +1, C L ~ 15pF
Vs = ±15V
TA =25"C

I

, 000
1500
2000
CAPACITIVE LOAD (pF)

A;VCL =+1
Vs =.±15V .
TA = 25°C

2500

SHORT-CIRCUIT CURRENT
vsTIME
80

140

il:

~40

il....

S
[i30

f\..

120

TA =+25°C
VS=±1SV

~

~

\

~w

i -41-----~~~~+----+----__\

ISCI+)

r\

0

20

8

ill .1---------,k:iI::9"'--+----+----__\

100

o

ili

121----1---

Vs = ±15V
VCM = ±10V

~sc~1

~

16r-----r-----,------r~~-,

111~Jl1JI

<;50

oS
....

COMMON-MODE INPUT RANGE
VI SUPPLY VOLTAGE

CMRR vs FREQUENCY

8

-8

-121-------~----+--~~~--__\
10

o

1

2

3

5

TIME FROM OUTPUT SHORTED TO GROUND (MINUTES)

80
100

-16L-____L-____
lk

10k

lOOk

~----~~~~

1M

FREQUENCY (Hz)

REV. A

OPERA TIONAL AMPLIFIERS 2-175

OP-21
TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE NOISE TEST CIRCUIT (O.1Hz-TO-10Hz)

LOW-FREQUENCY NOISE
120
80
40

-40

-80
-120

a.1Hz TO 10Hz PEAK-TO-PEAK NOISE
NOTE: ALL CAPACITOR VALUES ARE FOR
NON POLARiZeD CAPACITORS ONLY.

NOTE:
Observation time limited to 10 seconds.

OPEN-LOOP VOLTAGE GAIN VI
LOAD RES.ISTANCE
:: f-

~/ 12~1~11.+--l--+-I-J-I.mI---I--.l-U.wu

~ 2'{) I-- Vs ":t15V"t--++:I~#!--+-l-I-!-I-I~

j,
1.81--+1+I+Hl+/,-+-WW+--I-.+-WlJl.I
1-A
~ 1.6 1-+1+I+Hl.IJ1/Y+WW+--I-.+-WlJl.I

2:
~

~ 1.4 1--HI+I+IIl+-+-I-+-I+Hl+--+--I-+-I~

o

>121--H1+I~+-+-1-+-I+Hl+--+--1-+-I~

8.

~ 1.0 1--HI-+l+lJj+-+-~+I.JI+---l--l-H~
~"

!5

O.81--Hf+I+IJj+--I-~+I.JI+---l--l-H~

0.6

17-+-JL+-I++tfl,-++-+-I++lIl--I-+-+-1+llI-

PSRR VI FREQUENCY
160

I

~ 140
~ 12o~
~ 100

~
;;J
a:

o f.-

~

POSITl~

~ 60

~

il:

iil

NEGATIVE

~UPPLY

SUPPLY

40

a:
w

~

20

0.4 L.-L.W-LillLL..-L.W-llUll.......Ll..l.UllJ.
100

lk

10k

lOOk

10

LOAD RESISTANCE 1m

APPLICATIONS INFORMATION
OP-27 Series units may be inserted directly into 725, OP-06,
OP-07 and OP-05 sockets with or without removal of external
compensation or nulling components. Additionally, the OP27 may be fitted to unnulled 741-type sockets; however, if
conventional 741 nulling circuitry is in use, itshould be modified or removed to ensure correct OP-27 operation. OP-27
offset voltage maybe nulled to zero (or other desired setting)
using a potentiometer (see Offset Nulling Circuit).
The OP-27 provides stable operation with load capacitances
of up to 2000pF and ± 10V swings; larger capacitances should
be decoupled with a 500 resistor inside the feedback loop.
The OP-27 is unity-gain stable;
Thermoelectric voltages generated by dissimilar metals at
the input terminal contacts can degrade the drift performance. Best operation will be obtained when both input
contacts are maintained at the same temperature.
OFFSET VOLTAGE ADJUSTMENT
The input offset voltage of the OP-27 is trimmed at wafer
level. However, if further adjustment of Vos is necessary, a
10kO trim potentiometer may be used. TCVosis not degraded

2-176 OPERA TIONAL AMPLIFIERS

J

TA = 2rf'c-

o

100

~

~

lk
10k lOOk 1M
FREQUENCY (Hz)

10M 100M

(see Offset Nulling Circuit). Other potentiometer values from
1kO to 1MO can be used with a slight degradation (0.1 to
0.2p.VloC) of TCVos. Trimming to a value other than zero
creates a drift of approximately (Vosl300) p.Vlo C. For example, the change in TCVos will be 0.33p.V/o C if Vos is adjusted
to 100p.V. The offset-voltage adjustment range with a 10kO
potentiometer is ±4mV. If smaller adjustment range is required, the nulling sensitivity can be reduced by using a
smaller pot in conjuction with fixed resistors. For example,
the network below will have a ±280p.V adjustment range.

4.7kH

lknPOT

4.7kn

V+

NOISE MEASUREMENTS
To measure the 80nV peak-to-peak noise specification olthe
OP-27 in the 0.1 Hz to 10Hz range, the following precautions
must be observed:
(1) The device has to be warmed-up for at least five minutes.
As shown in the warm-up drift curve, the offset voltage

REV. A

OP-27
typically changes 4p.V due to increasing chip temperature
after power-up. In the 10-second measurement interval,
these temperature-induced effects can exceed tens-ofnanovolts.
(2) For similar reasons, the device has to be well-shielded

from air currents. Shielding minimizes thermocouple
effects.
(3) Sudden motion in the vicinity ofthe device can also "feedthrough" to increase the observed noise.
(4) The test time to measure 0.1 Hz-to-10Hz noise should not
exceed 10 seconds. As shown in the noise-tester frequencyresponse curve, the 0.1 Hz corner is defined by only one
zero. The test time of 10 seconds acts as an additional
zero to eliminate noise contributions from the frequency
band below 0.1 Hz.
(5) A noise-voltage-density test is recommended when
measuring noise on a large number of units. A 10Hz
noise-voltage-density measurement will correlate well
with a 0.1 Hz-to-10Hz peak-to-peak noise reading, since
both results are determined by the white noise and the
location of the 1/f corner frequency.

bias-current cancellation circuit. The OP-27 AlE has IB and
los of only ±40nA and 35nA respectively at 25° e. This is
particularly important when the input has a high sourceresistance. In addition, many audio amplifier designers
prefer to use direct coupling. The high IB' Vos, TeVos of
previous designs have made direct coupling difficult, if not
impossible, to use.
Voltage noise is inversely proportional to the square-root of
bias current, but current noise is proportional to the squareroot of bias current. The OP-27's noise advantage disappears
when high source-resistors are used. Figures 1, 2, and 3
compare OP-27 observed total noise with the noise performance of other devices in different circuit applications.
Total noise = [(Voltage nOise)2
(resistor noise)2]1/2

+ (current

noise x RS)2

+

Figure 1 shows noise-versus-source-resistance at 1000Hz.
The same plot applies to wideband noise. To use this plot, just
multiply the vertical scale by the square-root of the
bandwidth.

UNITY-GAIN BUFFER APPLICATIONS
When RIS1000 and the input is driven with a fast, large signal
pulse (>1V), the output waveform will look as shown in the
pulsed operation diagram below.

NOISE vs SOURCE RESISTANCE
(INCLUDING RESISTOR NOISE)
AT 1000Hz.
100

During the fast feedthrough-like portion of the output, the
input protection diodes effectively short the output to the
input and a current, limited only by the output short-circuit
protection, will be drawn by the signal generator. With
RI ~ 5000, the output is capable of handling the current
requirements (ILS 20mA at 10V); the amplifier will stay in its
active mode and a smooth transition will occur.

50

l....I:i

OP-08I1D8

~

toJ

1 As UNMATCHED

5634

When RI > 2kO, a pole will be created with RI and the
amplifier's input capacitance (8pF) that creates additional
phase shift and reduces phase margin. A small capacitor
(20 to 50pF) in parallel with RI will eliminate this problem.

e.g.Rs-RS1-1Ok,RS200
2RsMATCHED
•. g.RS"10k.R:sl=RS2"'5k

OP-27/37

~.l.ISTOR
NOISE ONLY
1

50

100

500 1k

itt>
"52

5k

10k

50k

RS - SOURCE RESISTANCE (n)

PULSED OPERATION
Figure 1

R,
At Rs < 1k~, the OP-27's low voltage noise is maintained.
With Rs> 1kO, total noise increases, but is dominated by the
resistor noise rather than current. or voltage noise. It is only
beyond Rs of 20kO that current noise starts to dominate. The
argument can be made that current noise is not important for
applications with low-to-moderate source resistances. The
crossover between the OP-27 and OP-07 and OP-08 noise
occurs in the 15-to-40kO region.
COMMENTS ON NOISE
The OP-27 is a very low-noise monolithic op amp. The outstanding input voltage noise characteristics ofthe OP-27 are
achieved mainly by operating the input stage at a high quiescent current. The input bias and offset currents, which would
normally increase, are held to reasonable values by the input-

REV. A

Figure 2 shows the 0.1 Hz-to-10Hz peak-to-peak noise. Here
the picture is less favorable; resistor noise is negligible, current noise becomes important because it is inversely proportional to the square-root of frequency. The crossover with the
OP-07 occurs in the 3-to-5kO range depending on whether
balanced or unbalanced source resistors are used (at 3kO the
IB' los error also can be three times the Vos spec.).

OPERATIONAL AMPLIFIERS 2-177~

2

OP-27
10Hz NOISE vs
SOURCE RESISTANCE .
(INCLUDES RESISTOR NOISE).

PEAK-TO-PEAK NOISE (0.1 to
10Hz) VB SOURCE RESISTANCE
(INCLUDES RESISTO.R NOISE).

,.

100
OP~/1OS

&liM

500

0

/,2

1111

?r.i"7
~

IIII

100

V

"

0

OP-27/37
1 RS UNMATCHED

J....

~~::I~~
500 lk

100

."
~.
5k

10k

27

,
SDk

50

RS.- SOURCE RESISTANCE In)

Figure 3

Therefore, for low-frequency applications, the OP-07 is better than the OP-27/37 when Rs> 3kO. The only exception is
when gain error is important. Figure 3 illustrates the 10Hz
noise. As expected, the results are between the previous two
figures.
For reference, typical ·source resistances of some signal
sources are listed in Table 1.

Table 1
SOURCE
I~PEDANCE

1 RS UNMATCHED

e:.g. RrR$"tOk.Rs2-G

it- I"J;

•. g.Rs=1Ok.R$t"RsrSk

DEVICE

~

1/

5

e.g.RrRs,-101c,Rs2"O
2 AS MATCHED

Figure 2

~~~7
5534

so

10
SO

~

OP-08/108

COMMENTS

Strain gauge

<.5000

Typically used in low-frequency
applications.

Magnetic
tapehead

<15000

Low la very important to reduce
self-magnetization problems when
di~t coupling is used. OP-27 la
can be neglected.

Magnetic
phonograph
cartridges

<15001l

Similar need for low la in direct
coupled applications. OP-27 will not
introduce any self-magnetization
problem.

Linear variable
differential
transformer

<15000

Used in rugged servo-feedback
applications. Bandwidth of interest is
400Hz to 5kHz.

r-

MRESISTOR

~~,sr l~i~,T
600 1k

100

2 RSMATCHEO

e.40R$=1Ok,Rs,=RS2=6k

.~.
5k

10k

SOk

RS - SOURCE RESISTANCE (n)

AUDIO APPLICATIONS
The following applications information has been abstracted
from a PMI article in the 12/20/80 issue of Electronic Design
magazine and updated.
Figure 4 is an example of a phono pre-amplifier circuit using
the OP-27 for A1; R1-R2"C1-C2·form a very accurate RIAA
network with standard component values. The popular method
to accomplish RIAA phono equalization is to employ
frequency-dependent feedback around a high-quality gain
block. Properly chosen, an RCnetwork can provide the three
necessary time constarits of 3180, 318, and 751's.1
For initial equalization accuracy and stability, precision
metal-film resistors and film capacitors of polystyrene or
polypropylene are recommended since they have low voltage
coefficients, dissipation factors, and dielectric absorption. 4
(High-K ceramic capacitors should be avoided here, though
low-K ceramics-such as NPO types, which have excellent
dissipation factors, and somewhat lower dielectric absorptioncan be considered for small values.)

C4(2)

22O,F

~~
,___ 6 l~n~
LF ROLLOFF
-=
OUT

IN

C3

OPEN-LOOP GAIN

0.47pF

OUTPUT

FREQUENCY
AT:

OP-G7

OP~27

OP47

3Hz

100dB

124dB

125dB

10Hz

100dB

120dB

125dB

30Hz

90dB

HOdB

124dB

R'

Rl
S7.6kU

lSkU

R3

For further information regarding noise calculations, see
"Minimization of Noise in Op-Amp Applications", Application
Note AN-15.

2-178 OPERATIONAL AMPLIFIERS

lOon

*)

G= 1kH%GAIN

=0.101 (1+

Figure 4

- 98.877 139.9 dBI AS SHOWN

REV. A

OP-27
The OP-27 brings a 3.2nV/VHZ voltage noise and 0.45
pAlVHZ current noise to this circuit. To minimize noise
from other sources, R3 is set to a value of 1000, which
generates a voltage noise of 1.3nVlVHZ. The noise increases the 3.2nVlVHZ of the amplifier by only 0.7dB. With
a 1 kO source, the circuit noise measures 63dB below a 1mV
reference level, unweighted, in a 20kHz noise bandwidth.
Gain (G) of the circuit at 1kHz can be calculated by the
expression:
G=0.101 (1

+ =~

)

For the values shown, the gain is just under 100 (or 40dB).
Lower gains can be accommodated by increasing R3, but
gains higher than 40dB will show more equalization errors
because of the SMHz gain-bandwidth of the OP-27.
This circuit is capable of very low distortion over its entire
range, generally below 0.01% at levels up to 7V rms. At 3V
output levels, it will produce less than 0.03% total harmonic
distortion at frequencies up to 20kHz.

The network values of the configuration yield a 50dB gain at
1kHz, and the dc gain is greater than 70dB. Thus, the worstcase output offset is just over 500mV. A single 0.471'F output
capacitor can block this level without affecting the dynamic
range.
The tape head can be coupled directly to the amplifier input,
since the worst-case bias current of SOnA with a 400mH, 100
I'in. head (such as the PRB2H7K) will not be troublesome.
One potential tape-head problem is presented by amplifier
bias-current transients which can magnetize a head. The
OP-27 and OP-37 are free of bias-current transients upon
power up or power down. However, it is always advantageous
to control the speed of power supply rise and fall, to eliminate transients.
In addition, the dc resistance of the head should be carefully
controlled, and preferably below 1kO. For this configuration, the bias-current-induced offset voltage can be greater
than the 100l'V maximum offset if the head resistance is not
sufficiently controlled.

Capacitor C3 and resistor R4 form a simple -6dB-per-octave
rumble filter, with a corner at 22Hz. As an option, the switchselected shunt capacitor C4, a non polarized electrolytic,
bypasses the low-frequency rolloff. Placing the rumble filter's high-pass action after the preamp has the desirable
result of discriminating against the RIAA-amplified lowfrequency noise components and pickup-produced lowfrequency disturbances.

A simple, but effective, fixed-gain transformerless microphone preamp (Fig. 6) amplifies differential signals from lowimpedance microphones by 50dB, and has an input impedance of 2kO. Because of the high working gain of the circuit,
an OP-37 helps to preserve bandwidth, which will be 110kHz.
As the OP-37 is a decompensated device (minimum stable
gain of 5), a dummy resistor, Rp, may be necessary, if the
microphone is to be unplugged. Otherwise the 100% feedback from the open input may cause the amplifier to oscillate.

A preamplifier for NAB tape playback is similar to an RIAA
phono preamp, though more gain is typically demanded,
along with equalization requiring a heavy low-frequency
boost. The circuit in Fig. 4 can be readily modified for tape
use, as shown by Fig. 5.

Common-mode input-noise rejection will depend upon the
match of the bridge-resistor ratios. Either close-tolerance
(0.1%) types should be used, or R4 should be trimmed for best
CMRR. All resistors should be metal-film types for best stability and low noise.

O.47,uF

TAPE
HEAD

R,

C,
Rl
313kH
R2

5kn.

loon

O.Q1J,.1F

f

Noise performance of this circuit is limited more by the input
resistors R, and R2 than by the op amp, as R, and R2 each
generate a 4nVlVHZ noise, while the op amp generates a
3.2nVlVHZ noise. The rms sum of these predominant noise
sources will be about 6nVlVHZ, equivalent to 0.91'V in a
20kHz noise bandwidth, or nearly 61dB below a 1mV input
signal. Measurements confirm this predicted performance.

Rl

T1 = 3180t-ls

R3

lkn

316kH

Cl

R6

5,uF

loon

T2 "'50,,5

Figure 5

While the tape-equalization requirement has a flat highfrequency gain above 3kHz (T2 = SOl's), the amplifier need
not be stabilized for unity gain. The decompensated OP-37
provides a greater bandwidth and slew rate. For many applications, the idealized time constants shown may require
trimming of R, and R2 to optimize frequency response for
non ideal tape-head performance and other factors. 5

REV. A

LOW IMPEDANCE
MICROPHONE INPUT ~
(Z-50T0200m
~.-L.

R3
Rl

R4
R2

R2
lkn

R7

OUTPUT

10k!1

R4

316kD

Figure 6

OPERA TlONAL AMPLIFIERS 2-179

II

OP-27
For applications demanding appreciably lower noise, a highquality microphone-transformer-coupled preamp (Fig. 7)
incorporates the internally-compensated OP-27. T1 is a
JE-115K-E 150!ll15kO transformer which provides an optimum source resistance for the OP-27 device. The circuit has
an overall gain of 40dB, the product of the transformer's
voltage setup and the op amp's voltage gain.

C2

1800pF

"'
121n

"2
1100<1

OUTPUT

eliminated in such cases, but is desirable for higher gains to
eliminate switching transients.
Capacitor C2 and resistor R2 form a 21's time constant in this
circuit, as recommended for optimum transient response by
the transformer manufacturer. With C2 in use, A1 must have
unity-gain stability. For situations where the 21's time constant is not necessary, C2 can be deleted, allowing the faster
OP-37 to be employed.
Some comment on noise is appropriate to understand the
capability of this circuit. A 1500 resistor and R1 and R2 gain
resistors connected to a noiseless amplifier will generate 220
nV of noise in a 20kHz bandwidth, or 73dB below a 1mV
reference level. Any practical amplifier can only approach
this noise level; it can never exceed it. With the OP-27 and T1
specified, the additional noise degradation will be close to
3.6dB (or -69.5 referenced to 1mV).
References

Gain may be trimmed to other levels, if desired, by adjusting
R2 or R1. Because of the low offset voltage of the OP-27,the
output offset of this circuit will be very low, 1.7mVor less; for a
40dB gain. The typical output blocking capacitor can be

1. Lipshltz. S.P., "OnRIAA Equalization Networks," JAES, Vol. 27, June 1979,
p.458-481.
2. Jung, W.G., IC Op Amp Cookbook, 2nd Ed .. HW. Sams and Company,
1980.
'
3. Jung, W.G., Audio IC Op Amp Applications, 2nd Ed., H.W. Sams and
Company, 1978.
4. Jung, W.G., and Marsh, A.M., "Picking CapaCitors," Audio, February &
March, 1980.
5. 018la, M.... F~dback-Generated Phase Nonlinearity in Audio Amplifiers,"
London AES Convention, March 1980, preprint 1976.
6. Stout, D.F., and Kaufman, M., Handbook of Operational Amplifier Circuit
Design, New York. McGraw Hill, 1976.

BURN-IN CIRCUIT

OFFSET NULLING CIRCUIT

*Tl = JENSEN JE-115K-E

JENSEN TRANSFORMERS
10735 Burbank ~vd.
N. Hollywood, CA 91601

Figure 7

>"'....----ov+
~7---'.'---_ 5)
OP-37 I

1IIIIIIII ANALOG

WDEVICES

FEATURES
• Low Noise.. .... ..... ....... 80nV pop (O.lHz to 10Hz)
...................... 3nV/yHz at 1kHz
• Low Drift .................................. O.2J1.V/oC
• High Speed ......................... 17V/J1.s Slew Rate
. . . . . . . . . . . . . . . . .. 63MHz Gain Bandwidth
• Low Input Offset Voltage ....................... l0J1.V
• Excellent CMRR ... 126dB (Common-Voltage of ±11V)
• High Open-Loop Gain . . . . . . . . . . . . . . . . . . . .. 1.8 Million
• Replaces 725, OP-05, OP-06, OP-07, AD510, AD517,
SE5534 in Gains> 5
• Available in Die Form

ORDERING INFORMATION I
PACKAGE
TA =+25°C
VosMAX
(~V)

TO-99

CERDIP
8-PIN

25
25

OP37AJ+
OP37EJ
OP378J+
OP37FJ
OP37CJ+
OP37GJ

OP37AZ+
OP37EZ
OP378Z+
OP37FZ
OP37CZ
OP37GZ

60
60
100
100
100

tt

PLASTIC
8-PIN

OPERATING
LCC
TEMPERATURE
RANGE
20-CONTACT

OP37EP
OP378RC/883
OP37FP
OP37GP
OP37GStt

MIL
IND/COM
MIL
IND/COM
MIL
XIND
XIND

The OP-37 provides the low offset and drift of the OP-07 plus
higher speed and lower noise. Offsets down to 25J1.V and drift
of 0,6J1.V/oC maximum make the OP-37 ideal for precision
instrumentation applications, Exceptionally low noise
(e n=3,SnVlyHz at 10Hz),a low 1/1 noise corner frequency of
2,7Hz,andthehighgainofl,8million,allowaccuratehigh-gain •
amplification of low-level signals.
The low input bias current of± 10nAand offset currentof7nA are
achieved by using a bias-current-cancellation circuit. Over
the military temperature range this typically holds 18 and los
to ±20nA and lSnA respectively,
The output stage has good load driving capability. A guaranteed swing of ± 10V into 600n and low output distortion make
the OP-37 an excellent choice for professional audio
applications,

PIN CONNECTIONS

VOS TRIMf2t8
VOS TR:Mv+
-IN2

60UT

+IN3

For devices processed in total compliance to MIL -STD,883, add /883 after part
number. Consult factory for 883 data sheet.
Burn·jn is available on commercial and industrial temperature range parts in
CerDIP, plastic DIP, and TO-can packages.
For availability and burn-in information on SO package, contact your local
sales office.

GENERAL DESCRIPTION
The OP-37 provides the same high performance as the OP-27,
but the design is optimized for circuits with gains greater
than five. This design change increases slew rate to 17V1J1.sec
and gain-bandwidth product to 63MHz.

5 N.C.
4

v-

(CASE)

TO-99
(J-Sufllx)

8-PIN HERMETIC DIP

(Z-Sufllx)
EPOXY MINI-DIP

(P-Sufflx)

8-PINSO
(S·Suffix)

Op·37BRC/883
LCC PACKAGE
(RC·Suffix)

SIMPLIFIED SCHEMATIC
,-------~--------~--------~--~--~~----~------~--~~--+-~V+

OUTPUT

NONINVERTING

INPUT'G+:""+--+~P--+--IE"--t:
INVERTING
INPUT ,,":...'___

+-+-______+ _______

.-+__

~-------------------~~------

REV. A

___________~~~~~~~v_

OPERA TlONAL AMPLIFIERS 2-181

PSRR and CMRR exceed 120dB. These characteristics,
coupled with long-term drift of 0.2I'Vimonth, allow the circuit
designer to achieve performance levels previously attained
only by discrete designs.

Operating Temperature Range
OP-37A, OP-37B, OP-37C (J,Z, RC) .•....•.. -55°C to + 12S·C
OP-37E, OP-37F (J, Z) ................................. -2SoC to +85·C
OP-37E, OP-37F (P) ......................................... O·C to + 70·C
OP-37G (P, S, J, Z) ......................................,-40·C to +85·C
Lead Temperature Range (Soldering, 60 sec) ............... 300·C
Junction Temperature .................................... -6SoC to + 1S0·C

Low-cost, high-volume production ofthe OP-37 is achieved by
using on-chip zener-zap trimming. This reliable and stable
offset trimming scheme has proved its effectiveness over
many years of production history.

PACKAGE TYPE

The OP-37 brings low-noise instrumentation-type performance to such diverse applications as microphone, tapehead, and RIAA phono preamplifiers, high-speed signal conditioning for data acquisition systems, and wide-bandwidth
instrumentation.

9 1A (NOTE 3)

TO·99 (J)
8-Pin Hermetic DIP (Z)
8-Pin Plastic DIP (P)
20-Contact LCC (RC, TC)
8-Pin 50(5)

a lc

UNITS

18
16
43
38
43

·C/W
·C/W
·C/W
·C/W
·C/W

150
148
103
98
158

NOTES:
1. For supply voltages less than ,,22V, the absolute maximum input voltage Is
equal to the supply voltage.
2. The OP-37's inputs are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low noise. If differential Input voltage
exceeds ,,0.7V, the input current should be limited to 2SmA.
3. alA is specified for worst case mounting conditions, i.e., aJA is specified for
device in socket for TO, CerDIP, P,DIP, and LCe packages; alA Is speCified
for device soldered to printed circuit board for SO package.
4. Absolute .maximum ratings apply to both DICE and packaged parts, unless

ABSOLUTE MAXIMUM RATINGS (Note 4)
Supply Voltage .................................................................. ±22V
Internal Voltage (Note 1) ................................................... ±22V
Output Short-Circuit Duration ..................................... Indefinite
Differential Input Voltage (Note 2) ................................... ±O. 7V
Differential Input Current (Note 2) ................................. ±25mA
Storage Temperature Range ......................... -65·C to + 150·C

otherwise noted.

ELECTRICAL CHARACTERISTICS at Vs = ±1SV, TA = 2Soc, unless otherwise noted.
PARAMETER

SYMBOL CONDITIONS

Input Offset Voltage

Vos

Long~ Term

Vas

Stability

lOS

Input Bias Current

18

Input Noise Voltage

8 np _p

Voltage Density

Input Noise
Current Density

en

in

Input Resistance Common~Mode

Input Voltage Range
Common~Mode

Rejection Ratio
Power Supply
Rejection Ratio

R'N

0.1 Hz to 10Hz

Voltage Gain

Swing
Slew Rate
Gain Bandwidth Prod.

20

60

30

100

~V

0.2

1.0

0.3

1.5

0.4

2.0

~VlMo

50

12

75

nA

±10

±40

±12

±55

±15

±80

nA

0.18

0.08

0.18

0.09

0.25

~Vp-p

5.5
4.5

5.5
4.5
3.8

3.8
. 3.3
3.2

B.O
5.6
4.5

nV/,[Hz

3.B

3.5
3.1
3.0

fa = 10Hz (Notes 3, 6)

1.7
1.0
0.4

4.0
2.3
0.6

1.7
1.0
0.4

4.0
2.3
0.6

1.7
1.0
0.4

0.6

10 = 30Hz (Notes 3,6)

(Note 7)

1.3

0.94

VCM =±11V

PSSR

Vs = ±4V to ±IBV

GBW

pA/,[Hz

0.7

Mil

2.5

CMRR

SA

UNITS

25

3.5
3.1
3.0

IVR

Vo

OP-37C/G
MIN
TYP MAX

10

R 1NCM

Avo

OP-37B/F
TYP MAX

0.08

(Notes 3,5)

RL 2: 1kU, Va = ±10V

RL = 60011, Vo = ±IV,
Vs

Output Voltage

MIN

10 = 10Hz (Note 3)
fa = 30Hz (Note 3)
'0 = 1000Hz (Note3)

RL"'2kll, Vo=±10V
Large-Signal

OP-37A/E
TYP MAX

35

fa == 1000Hz (Notes 3,6)

Input ResistanceOifferential~Mode

(Notet)

Vas/Time (Notes 2,3)

Input Offset Current

Input Noise

MIN

= ±4V, (Note 4)

AL"'2kll
RL", 60011

Gil

±11.0

±12.3

±11.0

±12.3

±11.0

±12.3

V

114

126

106

123

. 100

120

dB

10

10

20

1000
800

1800
1500

1000
BOO

1800
1500

700
400

1500
1500

250

700

250

700

200

500

±12.0

±13.8

±11.5

±12.0
±10.0

±13.8
±11.5

±11.5
±10.0

±13.5

±10.0

~VIV

V/mV

V

±11.5

RL 2:2kU (Note 4)

11

17

11

17

11

17

VlIlS

fa = 10kHz (Note 4)

45

83

45

63
40

45

63
40

MHz

10= lMHz

2-182 OPERA TlONAL AMPLIFIERS

40

REV.

A

OP-37
ELECTRICAL CHARACTERISTICS at Vs = ±15V. TA = 25°C. unless otherwise noted. (Continued)
OP-37A1E
PARAMETER

SYMBOL CONOITIONS

Open-Loop Output
Aesistance

RO

Power Consumption
Offset Adjustment

TYP

VO~O.lo~O

70
90

~

10kll

OP-37B/F

MAX

Vo~O

Rp

Range

MIN

TYP

MIN

OP-37C/G

MAX

MIN

TYP

70
140

100

±4.0

NOTES:
1. Input offset voltage measurements are performed by automated test
equipment approximately 0.5 seconds after applicatJon of power. AlE
grades guaranteed fully warmed up.
2. Long-term input offset voltage stability refers to the average trend line of
Vas VS. Time over extended periods after the first 30 days 01 operation.

UNITS

70
140

90

±4.0

MAX

11
170

±4.0

mW
mV

days are typically 2.5p.V - refer to typical performance curve.

3. Sample tested.
4.
5.
6.
7.

Excluding the initial hour of operation, changes in Vos during the first 30

Guaranteed by
See test circuit
See test circuit
Guaranteed by

design.
and frequency response curve for O.lHz to 10Hz tester,
for current noise measurement.
input bias current.

ELECTRICAL CHARACTERISTICS for Vs = ±15V. -55°C::; TA::; +125°C. unless otherwise noted.
OP-37A
PARAMETER

SYMBOL

CONOITIONS

Input Offset Voltage

Vos

tNote 1)

Average Input

TCVOS

tNote2)

Offset Drift

TCV OSn

INots31

Input Offset Current

los

Input Bias Current

Ie

Input Voltage Range

IVR

Common-Mode
Rejection Aatio
Power Supply
Rejection Ratio

CMRR

VCM == ±lOV

PSRR

Vs == ±4.SV to ± l8V

Large-:-Signal
Voltage Gain

AVO

Output Voltage
Swing

MIN

OP-37B

TYP

MAX

30
0.2

MIN

OP-37C

TYP

MAX

MIN

TYP

MAX

60

50

200

70

300

0.6

0.3

1.3

0.4

1.8

~vrc

UNITS

15

50

22

85

30

135

nA

±20

±60

±28

±95

±35

±150

nA

±10.3

±ll.S

±10.3

±ll.S

±10.2

±11.S

V

108

122

100

119

94

116

dB

16

20

51

~VIV

600

1200

500

1000

300

800

V/mV

±ll.S

±13.S

±11.0

±13.2

±10.5

±13.0

V

ELECTRICAL CHARACTERISTICS for Vs = ±15V. -25°C S TAS +85°C for OP-37EJ/FJ and OP-37EZ1FZ,O°C S TA S +70°C for
OP-37EP/FP and -40°C S TAS +85° for OP-37GPIGStGJ/GZ. unless otherwise noted.
OP-37E
PARAMETER

SYMBOL

Input Offset Voltage

Vos

Average Input

TCVos
TCVoSn

Offset Drift
Input Offset CUrrent

los

Input Bias Current

'a

Input Voltage Range

IVA

Common-Mode
Rejection Aatio
Power Supply
Rejection Ratio

Output Voltage

Swing

(Note3)

PSRR

Vs == ±4.5V to ± l8V

AVO

RL ~ 2kfi, Vo == ±lOV

Vo

MIN

(Note 2)

CMRR

Large-Signal
Voltage Gain

CONOITIONS

MAX

20
0.2

A

MIN

OP-37G

TYP

MAX

MIN

TYP

MAX

50

40

140

55

220

UNITS

0.6

0.3

1.3

0.4

1.8

~VI'C

10

50

14

85

20

135

nA

±14

±60

±18

±95

±25

±150

nA

±10.5

±11.8

±lO.S

±11.8

±10.5

±11.8

V

110

124

102

121

96

118

dB

15

16

32

750

1500

700

1300

450

1000

VlmV

±11.7

±13.6

±11.4

±13.S

±11.0

±13.3

v

NOTES:
1. Input offset voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power. AlE
grades guaranteed fully warmed up.

REV.

OP-37F

TYP

2. The TCVos performance is within the specifications unnulled or when
nulled with R p =8kO to20kO. TCVosis 100%tested for AlE grades. sample
tested for BICIFIG grades.
3. Guaranteed by design.

OPERATIONAL AMPLIFIERS 2-183

•

OP-37
DICE CHARACTERISTICS
DIE SIZE 0.098 x 0.056 Inch, 5488 sq. mils
(2.49 x 1.42 mm, 3.54 sq. mm)

WAFER TEST LIMITS

1.
2.
3.
4.
6.
7.
8.

NULL
(-) INPUT
(+) INPUT
VOUTPUT
V+
NULL

at Vs= ±15V, TA = 25°C for OP-37N, OP-37G and OP-37GR devices; TA= 125°C forOP-37NT and

OP-37GT devices. unless otherwise noted.

PARAMEl1!R

SYMBOL

CONDITIONS

Input Offset Voltage

Vos

(Note 1)

Input Offset Current

los

I nput Bias Current

Ie

Input Voltsge Range

IVR

Common-Mode
Rejection Ratio

CMRR

VcM =±l1V

Power Supply
Rejection Ratio

PSRR

TA =25°C. Vs =±4Vto±18V
TA= 125°C. Vs= ±4.5V to ±18V

Large-Signal
Voltage Gain

"w

RL2: 2kO. Vo= ±10V
RL 2:1kO.Vo =±10V

Output Voltage Swing

Vo

RL 2:2kO
RL 2:8000

Power Consumption

Pd

Vo=O

OP-37NT

OP-37N

OP~37GT

LIMIT

LIMIT

LIMIT

LIMIT

LIMIT

UNITS

60

35

200

60

100

"V MAX

OP-37G OP-37GR

50

35

85

50

75

nAMAX

±60

±4O

±95

±55

±80

nAMAX

±10.3

±11

±10.3

±11

±11

VMIN

108

114

100

106

100

dB MIN

10
16

10

10
20

10

20

800

1000
800

500

1000
800

700

±11.5

±12.0
±10.0

±11.0

±12.0
±10.0

±11.5
±10.0

VMIN

140

170

mWMAX

140

"VNMAX
VlmVMIN

NOTES:
For 25° C characteristics of OP-37NT and OP-37GT devices. see OP-37N and
OP-37G characteristics. respectively.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss. yield after peckaging is not
guaranteed for stsndard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot asembly and testing.

TYPICAL ELECTRICAL CHARACTERISTICS at Vs =

± 15V. TA = +25° C. unless otherwise noted.

OP-37NT
PARAMEl1!R

SYMBOL

CONDITIONS

Average Input Offset
Voltage Drift

TCVosor
TCVoSn

Nulled or Unnulled
Rp= 8kO to 20kO

Average Input Offset
Current Drift

OP-37N OP-37GT

OP-37G OP-37GR

TYPtCAL

TYPICAL

TYPICAL

TYPICAL

TYPICAL

UNITS

0.2

0.2

0.3

0.3

0.4

"vrc

TCl os

80

80

130

130

160

pAloC

Average Input Bias
Current Drift

TCl e

100

100

160

160

200

pAloC

Input Noise
Voltage Density

en

10= 10Hz
10= 30Hz
10= 1000Hz

3.5
3.1
3.0

3.5
3.1
3.0

3.5
3.1
3.0

3.5
3.1
3.0

3.8
3.3
3.2

nVl..[HZ

Input Noise
Current Density

in

10= 10Hz
10= 30Hz
10= 1000Hz

1.7
1.0
0.4

1.7
1.0
0.4

1.7
1.0
0.4

1.7
1.0
0.4

1.7
1.0
0.4

pAl..[HZ
"Vp.p

Input Noise Voltage

ent>-!>

O.lHz to 10Hz

0.08

0.08

0.08

0.08

0.09

Slew Rate

SR

RL2: 2kO

17

17

17

17

17

VI"s

Gain Bandwidth Product

GBW

10= 10kHz

83

83

83

83

83

MHz

NOTE:
1. Input offset voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power.

2-184 OPERATIONAL AMPLIFIERS

REV. A

OP-37
TYPICAL PERFORMANCE CHARACTERISTICS

NOISE-TESTER FREQUENCY
RESPONSE (0.1 Hz TO 10Hz)

A COMPARISON OF
OP AMP VOLTAGE
NOISE SPECTRA

VOLTAGE NOISE DENSITY
VI FREQUENCY
10
9
8

100

10Of-

90

,

1'1..

80 ~H-Irtttltt--++ttttitt

, i'
,
,

r-...

0

I.

LIMIT LOW FREQUENCY «O.lHz) GAIN.

10

l/fCORNER

111111

11111111

III

AUDIO RANGE
TO 20kHz

1

10

1

100

1000

10

FREQUENCY (Hz)

FREQUENCY (Hz)

INPUT WIDEBAND VOLTAGE
NOISE vs BANDWIDTH (0.1Hz
TO FREQUENCY INDICATED)

AMP

--

INSTRUMENTATION
RANGE, TO DC

I

1

100

~ ~",,-OP

~ ~,~37

I

TEST TIME OF 10sec MUST BE USED TO

AUDIO

111 CORNER
2.7HZ,

;; 2.7Hz

•

-

LOW NOISE!

:

I/f CORNER

50

,

ll1CQRNER

60

40

~741

TA = 25°C
Vs = ±15V

1000

100

FREQUENCY (Hz)

TOTAL NOISE vs SOURCE
RESISTANCE

VOLTAGE NOISE DENSITY
VB TEMPERATURE

100 F = 1 = F f = r ! ' f l ' F F = = = = = = R

~TA=25°C

~ ~ __

5V-rl-Htt+f-_ ~
rf-_VS
-j-=_±1t-

~4

1--II-H+l-++eI-- RS 2Rl

~

w

~10~1I

~~

3

-50

r! "

- 25

0

25

50

75

100

125

TEMPERATURE (OC)

SOURCE RESISTANCE 1m

VOLTAGE NOISE DENSITY
VI SUPPLY VOLTAGE

t"==4-+--=..j.o=

~
C;

10k

lk

100

BANOWIDTH (Hz)

-- -

~

g 21--+-+-~-+--~~-~

AT 1kHz

0.01 '---'-J....L.w.1!..1.--1....J....I..I.J..I.lll...--'--L-LJ.J.LW
100
lk
10k
lOOk

~

SUPPLY CURRENT VI
SUPPLY VOLTAGE

CURRENT NOISE DENSITY
VB FREQUENCY

5.0..----..---...,----.---.....,

10.0
25°C

<4.01---+---~---L-~__J

E

AT 10Hz

...

15

"-

AT 1kHz

~ 3.0

:>

"
~

it

~ 2.0 I-~__~--_I_--_+_---I

I--

f-1=1 ' 1i111i

0.1
10

W

~

TOTAL SUPPLY VOLTAGE (V+ - V-I (VOLTS)

REV. A

40

I/f CORNER

10

I

100
lk
FREQUENCY (Hz)

10k

as

15
25
TOTAL SUPPLY VOLTAGE (VOLTSI

45

OPERATIONAL AMPLIFIERS 2-185

OP-37
TYPICAL PERFORMANCE CHARACTERISTICS
OFFSET VOLTAGE DRIFT OF
EIGHT REPRESENTATIVE
UNITS YS TEMPERATURE
60

40

~

20

~

~

-

,/

LONG-TERM OFFSET
VOLTAGE DRIFT OF SIX
REPRESENTATIVE UNITS

OP-31C

/ ' OP-378

/ ' ,.,
,., """K '"
".

.....

i-"'"

"..

~ 2
w

OPfA

"~

OP-378

i5 ..

I-

I

g
~

...... r-

~

TRIMMING WITH"
10k POT ~OES
NOT CHANGE

T~VOSI

-60

I

......
......

0

25

50

75

30

J

~

0

-6

o

20

2S°C

15

f--

ij!3O
a:

~II
THERMAt:---L
RESPONSE

1'0 f - ~

f--

BAND

~

/1' I I I I

If I I I I I
20

40

i'

10

80

OPEN-LOOP GAIN
FREQUENCY

-50

100

-25

~'00
w

~

~
>

§
ffi

i!;

75

RL ;;. 2kn

70

65
60

I\.

80

55
30

~
;;'25

\.

40

JJ---.;

I--

OP-37C

~I\.

,~ ~ ['.. r-

OP-378

4il

--

0
25 50
75
TEMPERATURE r»CI

100

125

150

-75 -50

-25

OP-'S/B

f-.,.:

OP~7A

0

25

50

(/)M

50

.......

--

100

125

GAIN, PHASE SHIFT YI
FREQUENCY
60

VS ,.'±15V

75

TEMPERATURE fC)

80

T}' +Jc

I\.

80

50

SLEW RATE, GAIN BANDWIDTH
PRODUCT, PHASE MARGIN YI
TEMPERATURE

YS

VS:l ±16V _

r'\.

INPUT OFFSET CURRENT
YI TEMPERATURE

II I

TIME (SEC)

~ 120

TIME AFTER POWER ON (MINUTES)

OP-37C

o

60

140

V

QP-37A

IN 700C OIL BATH

o·

-20

1,\

~ DEVICE IMMERSED

0

OP-zlA/E

Vs = ±15V

"" \ \ 1\
~20
" "- r-. r--I--

SHOCK

r--

i-"""

II

2

I I I I

o

-

IIII

40

~

I-

I-

r-

50

.1
TA "

-

OP-:JBlF

VV-

INPUT BIAS CURRENT
YS TEMPERATURE

TA -70"C

V .... ,..-

/

TIME (MONTHS)

V~'±\5VI-

I I I I

~ 25

g
I-

.......,

rei

I I

j

r--..

-2

OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK

w

«~

,/"
~

-4

OP-37C

VS=±15V

OP-37C/G

6

100 125 150 175

TEMPERATURE

~

is

Tl. +25.)

r-

·6

~
w

II"

I
I

......

I

-75 -50 -25

~

o

OP-318

-40

~

~

OP-37A

r"'"

-20

10

-2

OP-'S/A

>

.--

~

h""

0

WARM-UP OFFSET
VOLTAGE DRIFT

v.I.

~

40

~,l.!."

-100

TA = +25"c

~

r-~

-120
PHASE

30

r--- .::.,w

"\

-140

MARGIN
= 71°

-160

20

---..

AV" 5

-180

10

w

I\.

20

SLEW

<20

a:

\

~

-200

15

.. 10

10

102

10"

104

105

10"

107

loB

FREQUENCY (Hz)

2-186 OPERATIONAL AMPLIFIERS

-so

40
-25

+75
+25 +50
TEMPERATURE (OCI

+100

+125

-10
lOOk

-220
1M

10M

100M

FREQUENCY 1Hz)

REV. A

OP-37
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN-LOOP VOLTAGE GAIN
vs SUPPLY VOLTAGE

I

2.

5

2B

yk"

2.o f--TA = 25°C
/'

Rl=lkH

./ . / -

5

~

24

;

20

T A '"

16

:ZSOe

14

- POsllTIJe

12

-

"

2

~

4

r--o

0.0

30

20

/.
(/

B

""

0.5

TA'" 25°C
Vs = ±15V

I III

2

104

50

40

•

NEGATIVE

12

~

~
SWING

~

"II!

~

SWING

10

~ 18

,V
10

lB

vsl.I.).~1

g

~/

0

MAXIMUM OUTPUT VOLTAGE
VB LOAD RESISTANCE

MAXIMUM OUTPUT SWING
VB FREQUENCY

105

TOTAL SUPPLY VOLTAGE (VOLIS)

100

106

SMALL-SIGNAL OVERSHOOT
vs CAPACITIVE LOAD

1k

10k

LOAD RESISTANCE (m

FREQUENCY (Hz:)

LARGE-SIGNAL TRANSIENT
RESPONSE

SMALL-SIGNAL TRANSIENT
RESPONSE

80
Vs = ±15V
VIN =2DmV
AV = +5 (1kn, 2500)

60

/

40

V

+50mV

. /~

+10V

L

20

ov

ov

-10V

-5

omV

AV = +5 (lkn. 250n)
TA = +2So C

TA =+25"C

o

o

500

1000

1500

iiii
Vs = ±16V

Vs = ±15V
AV" +5 (lkn, 250m

2000

CAPACITIVE LOAD (pF)

SHORT-CIRCUIT CURRENT
vsTIME
60

140

I":

TA = +25 0
Vs = ±1SV

r-:SC~L'

16r---r---,----r~~~

IJ!I~I±1U I

120

I\..

COMMON-MODE INPUT RANGE
vs SUPPLY VOLTAGE

CMRR VB FREQUENCY

TA = +2SOC

.....

~

V CM '" ±10V

~ 8
t\l 4 I---W'S"'''--+--+----I

100

~w

i -41--~~~~+--+----I

r\

BO

lse lt )

~

60

0

121---+--

01--.£.1---+--+----1

-B

-12r---1---f-~~~~-_i
10

i

o

TIME FROM OUTPUT SHORTED TO GROUND (MINUTES)

REV. A

-16 L..--'---,-':---~~:..:...~±20

40
1k

10k

lOOk

1M

10M

FREQUENCY 1Hz)

OPERATIONAL AMPLIFIERS 2-187

OP-37
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN-LOOP VOLTAGE GAIN
VB LOAD RESISTANCE

LOW-FREQUENCY NOISE

NOISE TEST CIRCUIT (0.1 Hz TO 10Hz)

2.4
O.1pF

120

lOOk"

;;

~

80

~

2.0

ill

40

~

1.8

(5

.'"'"

-40

!:i

t-"f-'>Nv-1

g

::~I21;.:'El~i!

-

IT~.IJ!bll

_

VS =±15V

/

~ :::

2

",n

2.2

~
8~

-60
-120

1.2
1,0

~ 0.8

i"~n

O.1Hz TO 10Hz PEAK-TO-PEAK NOISE

0••

NOTE:
Observation time limited to 10 seconds.

":" -=
NOTE: ALL CAPACITOR VALUES ARE FOR

lk

10k

lOOk

LOAD RESISTANCE In)

NON-POLARIZED CAPACITORS ONL V.

PSRR VI FREQUENCY
160

~1~
o
~ 120 -

..t5

100

~

8

TAl.

18

~,

. O-POsITI~
..

SLEW RATE
vs SUPPLY VOLTAGE

SLEW RATE VB LOAD
20

U~WJII

TA

=

125'C

AVCL ., +5

VS· :t15V

~'

i

25'~-

,.
I--

~

60

40

~

~ 20

~

0
100

lk

10k

lOOk

#~

~

;:::::;

fALL

,

NEGATIVE

~UPPLV

SUPPLY

10

15

AV'" +5
VO·2OVp-p

~

,.
~

1M

10M 100M

FREQUENCY (Hz)

15
1110

V
lk

APPLICATIONS INFORMATION
OP-37 Series units may be inserted directly into 725, OP-06,
OP-07, and OP-05 sockets with or without removal of external
compensation or nulling components, Additionally, the OP37 may be fitted to unnulled 741-type sockets; however, if
conventional 741 nulling circuitry is in use, it should be modified or removed to ensure correct OP-37 operation. OP-37
offset voltage may be nulled to zero (or other desired setting)
using a potentiometer (see offset nulling circuit).
The OP-37 provides stable operation with load capacitances
of up to 1000pF and ± 10V swings; larger capacitances should
be decoupled with a 500 resistor inside the feedback loop.
Closed-loop gain must be at least five. For closed-loop gain
between five to ten, the designer should consider both the
OP-27 and the OP-37. For gains above ten, the OP-37 has a
clear advantage over the unity-gain-stable OP-27.
Thermoelectric voltages generated by dissimilar metals at
the input terminal contacts can degrade the drift performance. Best operation will be obtained when both input
contacts are maintained at the same temperature.

2-188 OPERATIONAL AMPLIFIERS

10k

LOAD RESISTANCE

lOOk

o±3

en)

±6

±9

±12

±15

t18

±21

SUPPLY VOLTAGE (VOLTS)

OFFSET NULLING CIRCUIT

>...,...-'----ov+
>7"':6'-_-0 OUTPUT

OFFSET VOLTAGE ADJUSTMENT
The input offset voltage of the OP-37 is trimmed at wafer
level. However, if further adjustment of Vos is necessary, a
10kO trim potentiometer may be used. TCVes is not degraded
(see offset nulling circuit). Other potentiometer values from
1kO to 1MO can be used with a slight degradation (0.1 to
0.21JVlo C) of TCVes. Trimming to a value other than zero
creates a drift of approximately (Ves/300) IJVlo C. For exam-

REV. A

OP-37
pie, the change in TCVos will be 0.33,.Vlo C if Vas is adjusted
to 100,.V. The offset-voltage adjustment range with a 10kO
potentiometer is ±4mV. If smaller adjustment range is required, the nulling sensitivity can be reduced by using a
smaller pot in conjunction with fixed resistors. For example,
the network below will have a ±280,.V adjustment range.

4.7k!!

lki! POT

4.7kH

INSTRUMENTATION AMPLIFIER
A three-op-amp instrumentation amplifier provides high gain
and wide bandwidth. The input noise of the circuit below is
4.9nVly"HZ. The gain of the input stage is set at 25 and the
gain of the second stage is 40; overall gain is 1000. The
amplifier bandwidth of 800kHz is extraordinarily good for a
preCision instrumentation amplifier. Set to a gain of 1000, this
yields a gain-bandwidth product of 800M Hz. The full-power
bandwidth for a 20Vp _p output is 250kHz. Potentiometer R7
provides quadrature trimming to optimize the instrumentation amplifier's AC common-mode rejection.

BURN-IN CIRCUIT

NOISE MEASUREMENTS

(1) The device has to be warmed-up for at least five minutes.
As shown in the warm-up drift curve, the offset voltage
typically changes 4,.V due to increasing chip temperature after power-up. In the 10 second measurement interval, these temperature-induced effects can exceed tensof- nanovolts.

(3) Sudden motion in the vicinity of the device can also "feedthrough" to increase the observed noise.
(4) The testtime to measure 0.1 Hz-to-l0Hz noise should not
exceed 10 seconds. As shown in the noise-tester frequency response curve, the O.lHz corner is defined by
only one zero. The test time of 10 seconds acts as an
additional zero to eliminate noise contributions from the
frequency band below 0.1 Hz.
(5) A noise-voltage-density test is recommended when
measuring noise on a large number of units. A 10Hz
noise-voltage-density measurement will correlate well
with a 0.1 Hz-to-l0Hz peak-to-peak noise reading, since
both results are determined by the white noise and the
location of the 1If corner frequency.
OPTIMIZING LINEARITY
Best linearity will be obtained by designing for the minimum
output current required for the application. High gain and
excellent linearity can be achieved by operating the op amp
with a peak output current of less than ± 10mA.

REV. A

RS

R8
20k!! 0.1%

R6
600n 0.1%

R9
19.8kH

• TRIM R2 FOR AVCL = 1000
_TRIM R10 FOR de CMRR
-TRIM R7 FOR MINIMUM VOUT
AT VCM = 20V p_p, 10KHz

To measure the 80nV peak-to-peak noise specification ofthe
OP-37 in the 0.1 Hz to 10Hz range, the following precautions
must be observed:

(2) For similar reasons, the device has to be well-shielded
from air currents. Shielding minimizes thermocouple
effects.

soon 0.1%

140

Il~J

120

I"-

~ 100

a:
a:

ii

RIO

soon

~

~

I'

RS = lOOll.80 lkn UNBALANCED

IIIII I 1111

I'

~

10k

lOOk

TA = +25°C
60

AS = 1kil,

Vs = :t15V
VCM = 2OVp-p

AC TRIM @I 10KHz, RS = 0

40
10

100

lk

BALANCED

I'
1M

FREQUENCY (Hz)

COMMENTS ON NOISE
The OP-37 is a very low-noise monolithic op amp. The outstanding input voltage noise characteristics ofthe OP-37 are
achieved mainly by operating the input stage at a high quiescent current. The input bias and offset currents, which would
normally increase, are held to reasonable values by the inputbias-current cancellation circuit. The OP-37 AlE has 18 and
los of only ±40nA and 35nA respectively at 25°C. This is
particularly important when the input has a high sourceresistance. In addition, many audio amplifier designers

OPERATIONAL AMPLIFIERS 2-189

2

OP-37
10Hz NOISE vs
SOURCE RESISTANCE
(INCLUDES RESISTOR NOISE)

NOISE vs SOURCE RESISTANCE
(INCLUDING RESISTOR NOISE)
AT 1000Hz
100

100

50

50

~~

OP-08I108

0

~

~..,J

.,./"

OP-(JaI108

,

'/

,/

Ul-07
5534

1 RSUNMATCHED

1 RS UNMATCHED

5534

•. g.RrRs,·lOk,AS2oo(1

OP-27137...

a.g.Rs=lOk,RS'=Rs2-sk

• .. Rs-Rsl-10k,Rs2000

2 RSMATCHED

1¢>
'S2

~~SISTOR
NOISE ONLY
1
50

100

SOO

2 RSMATCHED

lk

5k

50.

10k

Figure 3

500

OP-08/108

III

100

~

IIII

V

I-'

OP-27/':f1

50

1 RS UNMATCHED

e.g.RrAS1·'Ok.Rs2000
2 RSMATCHED
•. g.Rs=lOk,RS,"'R$2=5k

~~::Ig:~
10
50 100

Figure 2

6k

10k

Therefore, for low-frequency applications, the OP-07 is better than the OP-27/37 when Rs> 3kO. The only exception is
when gain error is important. Figure 3 illustrates the 10Hz
noise. As expected, the results are between the previous two
figures.

.~.
'U

600 1k
5k 10k
RS - SOURCE RESISTANCE (n)

For reference, typical source resistances of some signal
sources are listed in Table 1.

prefer to use direct coupling. The high IB' TCVos of previous
designs have made direct coupling difficult, if not impossible,
to use.
Voltage noise is inversely proportional to the square-root of
bias current, but current noise is proportional to the squareroot of bias current. The OP-37's noise advantage disappears
when high source-resistors are used. Figures 1, 2, and 3
compare OP-37 observed total noise with the noise performance of other devices in different circuit applications.
Total noise = [(Voltage noise)2
(resistor noise2 ] 1/2

500 lk

Rs" SOURCE RESISTANCE em

Figure 2 shows the 0.1 Hz-to-10Hz peak-to-peak noise. Here
the picture is less favorable; resistor noise is negligible, current noise becomes important because it is inversely proportional to the square-root of frequency. The crossover with the
OP-07 occurs in the 3-to 5kO range depending on whether
balanced or unbalanced source resistors are used (at3kO the
IB' los error also can be three times the Vos spec.).

..3.

or,;'"

100

beyond Rs of 20kO that current noise starts to dominate. The
argument can be made that current noise is not importantfor
applications with low-to-moderate source resistances. The
crossover between the OP-37 and OP-07 and op-oa noise
occurs in the 15-to-40kO region.

PEAK-TO-PEAK NOISE (0.1 to
10Hz) vs SOURCE RESISTANCE
(INCLUDES RESISTOR NOISE)

,.

I.g.Rr1Ok,Rs1- Rsr5k

RESISTOR

1
50

RS - SOURCE RESISTANCE 1m

Figure 1

l27r~
Vii
jOllSlwtJ ~
f-

+ (current

noise

DEVICE

SOURCE
IMPEDANCE

At Rs 10)
OP-61 I

~ANALOG

WDEVICES

FEATURES
• High Gain-Bandwidth Product ...................... 200M Hz Typ
• Low Voltage Noise .......•..•.....•..•........•. 3.4nV/ v'Hi @ 1kHz
• High Speed ........................................................ 45V/!'s Typ
• Fast Settling Time (0.01 %) ........................•.•..... 330ns Typ
• High Gain ....................................................... 475V/mV Typ
• Low Offset Voltage ............................................ 1OO!,V Typ

much larger gain-bandwith product of 200M Hz. With slew rate
exceeding 45V/!'s, and settling time for 12 bits (0.01%) typically
330ns, the OP-61 has excellent dynamic accuracy.
The OP-61 is an excellent upgrade for circuits using slower op
amps such as the HA-5111, and the HA-5147. The OP-61 can
also be used as a high-speed alternative to the HA-51 01, HA5127, HA-5137, OP-27, and OP-37 amplifiers, where closedloop gains are greater than 10.

APPLICATIONS
• Low Noise Preamplifier
• Wideband Signal Conditioning
• Pulse/RF Amplifiers
• Wideband Instrumentation Amplifiers
• Active Filters
• Fast Summing Amplifiers

PIN CONNECTIONS

GENERAL DESCRIPTION
The OP-61 is a wide-bandwidth, precision operational amplifier
designed to meet the requirements of fast, precision instrumentation systems. The OP-61 's combination of DC accuracy with
high bandwidth, fast slew rate and low noise, makes it unique
among high-speed amplifiers. It is ideal for wide band systems
requiring high signal-to-noise ratio, such as fast 12-16 bit data
acquisition systems. The OP-61 maintains less than 3nV/VHz
of input referred spot voltage noise over its closed-loop bandwidth.

OP-61 ARC/883
20-CONTACT LCC
(RC-Suffix)

EPOXY MINI-DIP
(P-Suffix)
8-PIN CERDIP (Z-Suffix)
8-PIN SO (S-Suffix)

The OP-61 offers noise and gain performance similar to that of
the industry standard OP-27/37 amplifiers, but maintains a

+15V

O.1p.F

q.

V ,N

,." I

VOUT

YoUT

15p'
Io\N

900"
Av

=+10

-15V

REV. A

OPERATIONAL AMPLIFIERS 2-193

2

OP-61
ORDERING INFORMATION t

Storage Temperature Range
P, RC, S, Z Package ____________________________________ -65°C to +150°C

PACKAGE
CERDIP
8-PIN
OP6IAZ·
OP61FZ

PLASTIC

LCC

8-PIN

2O-CONTACT

OPERATING
TEMPERATURE
RANGE

OP6IARC/883·

Lead Temperature Range (Soldering, 60 sec) _______________ 300°C
Junction Temperature (Tj) ______________________________________________ 150°C
Operating Temperature Range
All A Grades ________________________________________________ -55°C to + 125°C
F & G Grades _________________________________________________ -40°C to +85°C

Mil
XIND
XIND

OP61GP
OP61GS

For devices processed in total compliance to Mll-STD-883, add 1883 after part
number_ Consult factory for 883 data sheet
Burn-in is available on commercial and industrial temperature range parts in
CerDIP, and plastic DIP packages_

alc

UNIT

8-Pln Hermetic DIP (ZI

PACKAGE TYPE

148

16

°efW

8-Pin Plastic DIP (P)

103

43

°efW

20-Contact LCC (RC)

98

38

°CfW

158

43

°CfW

alA (Note I)

8-PinSO (S)

ABSOLUTE MAXIMUM RATINGS (Note 2)
Supply Voltage _________________________________________________________________ ±18V
Differential Input Voltage _________________________________________________ ±5_0V
Input Voltage ____________________________________________________ Supply Voltage
Output Short-Circuit Duration _________________________________ Continuous

ELECTRICAL CHARACTERISTICS
PARAMETER

SYMBOL

Input Offset Voltage

Vos

Input Offset Current

los

Input Bias Current

Ie

at Vs

NOTES:
1_ ajA is specified for worst case mounting conditions, i.e., aiA is specified for
device in socket for CerDIP, P-DlP, and lCC packages; alA is specified for
device soldered to printed circuit board for SOpackage.
2. Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.

= ±15V, T A = 25°C, unless otherwise noted_

CONDITIONS

MIN

OP·61 A
TYP
MAX

OP·61F
MIN

op·61G

TYP

MAX

MIN

TYP

MAX

UNITS

750

~V

nA

100

500

150

200

1000

VCM=OV

30

150

40

200

40

200

VCM=OV

130

500

200

600

200

600

nA

3.4

3.4

-

nV/v'Hz

1.7

1.7

-

pNv'Hz

Input Noise
Voltage Density

en

fo= 1000Hz

3.4

Input Noise
Current Density

in

fo = 10kHz

1.7

Input Voltage Range

IVR

(Note I)

Common-Mode
Rejection

CMR

VCM=±I1V

Power Supply
Rejection Ratio

PSRR

Vs=±5Vto±18V

±11.0
100

±11.0
108

1.2

RL=IOkO
RL=2kQ
RL=lkO

225
200
150

475
400

94

4.0

±11.0
100

2.0

94

5.6

V
100

2.0

dB
5.6

~VN

425
350
300

175
ISO
120

425
350
300

V/mV

340

175
ISO
120

V

large-Signal
Voltage Gain

Avo

Output Voltage
Swing

Vo

RL=lkQ
RL =500Q

±12.0
±11.0

±13.2
±12.8

±12.0
±11.0

±13.2
±12.8

±12.0
±11.0

±13.2
±12.8

Slew Rate

SR

RL=lkQ
CL=50pF

40

45

35

45

35

45

VI~s

Gain Bandwidlh Prod.

GBWP

fo= IMHz

200

200

MHz

SettlingTime

ts

Av = -10, 10V Step, 0.01%

300

Isy

No load

6.1

Supply Current

200
330
7.5

6.1

330
7.5

6.1

ns
7.5

rnA

NOTES:
I. Guaranteed by CMR test

2-194 OPERATIONAL AMPLIFIERS

REV_A

OP-61
ELECTRICAL CHARACTERISTICS atV s =:l:15V, -55°C .:TA': +125°C, unless otherwise noted.
OP-61A
PARAMETER

SYMBOL

TYP

MAX

UNITS

Input Offset Voltage

Vas

200

1000

"V

Average Input
Offset Drilt

TCVos

1.0

5.0

"V/oC

CONDITIONS

MIN

Input Offset Current

los

VCM = OV

70

400

nA

Input Bias Current

18

VCM=OV

180

800

nA

Input Voltage Range

IVR

(Note 1)

Common-Mode
Rejection

CMR

V CM ="I1V

Power Supply
Rejection Ratio

PSRR

Vs =,,5Vto,,18V

Large-Signal
Voltage Gain

Ava

RL = 10ka
RL = 2kQ
RL = lkQ

175
150
120

340
260

Outpul Voltage
Swing

RL a lkQ
RL = 500a

,,11.0

.13.0

Va

.10.0

.12.7

Supply Current

ISY

No Load

,,11V

V
104

94

dB

5.6

2.0

!'-VN

400
V/mV

V
8.0

6.5

rnA

ELECTRICAL CHARACTERISTICS at Vs = :l:15V, -40°C .: T A .: +85°C.
OP-61G

OP·61F
PARAMETER

SYMBOL

Input Offset Voltage

Vas

Average Input
Offset Drilt

TCVos

CONDITIONS

MIN

TYP

MAX

TYP

MAX

UNITS

300

1250

400

1500

!'-V

3.0

7.0

3.0

7.0

"woC

MIN

Input Offset Current

los

V CM = OV

125

500

125

500

nA

Input Bias Current

18

VCM=OV

250

900

250

900

nA

Input Voltage Range

IVR

(Note I)

Common-Mode
Rejection

CMR

V CM = "l1V

PSRR

Vs = ,,5Vto.18V

Large-Signal
Voltage Gain

Ava

RL = 10kQ
RL =2kQ
RL = lkQ

150
120
100

350
300
240

150
120

Output Voltage
Swing

Va

RL = lkQ
RL = 500n

,,11.0
,,10.0

.13.0
,,12.7

Supply Current

ISY

No Load

Power Supply
Rejection Ratio

88

V

:t.11V

"IIV

88

96

4.0

6.4

10.0

8.0

dB

96

4.0

10.0

"VN

V/mV

100

350
300
240

.11.0
.10.0

,,13.0
,,12.7

V

6.4

8.0

rnA

NOTES:
1. Guaranteed by CMR test.

REV. A

OPERATIONAL AMPLIFIERS 2-195

•

OP-Sl
DICE CHARACTERISTICS

1. VOSNULL
2. -IN
3. +IN
4.
5.
6.
7.

VVosNULL
OUT
V+

DIE SIZE 0.064 x 0.068 Inch, 4,352 sq. mils
(1.63 x1.73 mm,2.81 sq.mm)

WAFER TEST LIMITS atVs=±15V, TA = 25°C.
OP-61GBC
PARAMETER

SYMBOL

Input Offset Vollage

Vos

CONDITIONS

LIMITS

UNITS

750

~VMAX

Input Offset Current

los

200

nAMAX

Input Bias Current

18

600

nAMAX

Input Voltage Range

IVR

±11.0

VMIN

Common-Mode
Rejection

CMR'

94

dBMIN

Power Supply
Rejection Ratio

PSRR

Vs=±5Vto±18V

5.6

~VIVMAX

Large-Signal
Voltage Gain

Avo

RL = tOkQ
RL=2kQ
RL=lkQ

175
150
120

VlmVMIN

Output Voltage Swing

Vo

RL=lkQ
RL= 500Q

±12.0
±11.0

VMIN

Slew Rate

SR

RL=lkQ
CL=50pF

35

Supply Current

Isv

No load

7.5

V/~s

MIN

mAMAX

NOTE:
Electrical tests are performed at wafer probe to the limits shown, Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for
standard product dice, Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

2-196 OPERATIONAL AMPLIFIERS

REV. A

OP-Sl
TYPICAL PERFORMANCE CHARACTERISTICS

OPEN·LOOP GAIN,
PHASEvsFREQUENCY

".
;i
~

z

.

3

00

~

40

I!i

~
0

.

"""

TA .2S"C
Vs _1:15V
RL.,2ka

'00

r-

(

GAIN

PHASE

DO

....

'35

·ii,~~

....

..

!

100k

1M

m
a:
~ '~"

4S

if

40

=

22.

35

_

'oou

'OM

'>< ......

if

~

~

+. I-- I--

'00

,..

i'- r-....
2S

~

so

r- ".

n

~
g

~
~z

~
3

..
!. ,.

~.~
'Is

:O:l:15V
AL .. 2kQ

I

1.:l!~I!,~

~~

111111111

3.

~

~~~I~,.I

l\

,.

,;

•,.

WIDEBAND PEAK·TO·PEAK
VOLTAGE NOISE

'Ok

100k

,.u

1M

CURRENT NOISE DENSITY
vsFREQUENCY

'00

l~ll.1,~!JI

T" _+25"C

\Is ....15Y
Rs ·1kO

Vs .:t.15V

30

•

1\

~

FREQUENCY (Hz)

~

.....

i

2S

.iii
~

I" ,.
z
~

""
~

ISO IIIIIII~

m 100

~

20

III0

~

~:!I~,rr

ao

TEMPERATURE .-«:)

FREQUENCV (H:r:)

VOLTAGE NOISE DENSITY
vs FREQUENCY

3.

~

11111

,

tk

,ao

I

,.:c
t;

iiig so

45

,.

,ao

CLOSED·LOOP GAIN
vs FREQUENCY

7.

'00

.~'5V

Vs
A L -2kO

55

i'

"-

GAIN·BANDWIDTH PRODUCT,
PHASE MARGIN
vs TEMPERATURE

"
~

,. \

,.

....

z

~

a:
a:
u

BANDWIDTH: 1kHz TO 100kHz

TA

=+25·C

"

'Is =:l:.15V

•,.

100

111
10k
FREQUENCY (Hz)

,,.

,u

100k

-,., -

Va '" :l:15V

ALana
CL. SOpF

00

/

COMMON·MODE REJECTION
VB FREQUENCY
'40

!

IJsW,1

T••

Va _:l:15V

'20

.,1;1

~

~

2S

~

TEMPERATURE rC)

REV. A

~

~ll..~~h'
'Is

z

'00

iil
a:

00

0

1I ...

15V

.....

....

.g .
"'" ••

+PSR

-PSA

~

z

0

8'"

20

20

_

...

~

30

_

POWER SUPPLY REJECTION
VB FREQUENCY

'20

;

;i

V

20

'Ok

1k

FREQUENCY (Hz)

SLEW RATE VB
TEMPERATURE
70

tOO

_

m

o

,.

10k

tOOk
FREQUENCY (Hz)

1M

,ou

,.

100

111

10k

100k

,u

FREQUENCY (Hz)

OPERATIONAL AMPLIFIERS 2-197

OP-61
TYPICAL PERFORMANCE CHARACTERISTICS

Continued

CLOSED-LOOP OUTPUT
IMPEDANCE V$ FREQUENCY

MAXIMUM OUTPUT SWING
vs FREQUENCY

'"

BOO

T~; ;~;!~

.
..

TYPICAL DISTRIBUTION OF
INPUT OFFSET VOLTAGE
700

Va =:l:15V

T.I.~!C

19QOUNITS
FROM 3 RUNS_

~

Vs =:l:15V

600
500

-

400
40

300

AvCL " 1000

AvCl " 100-

AVCL=10~

20

o
1k

10k

TYPICAL DISTRIBUTION
OF TCVOS

to-

o

1M

10M

-1.0 -0.8 -0.6 -0.4 -0.2

VCM

= DV

,

80

100

'-

150

'r---..

60

100

o

~
\

60

r--.. t-- r-

[\.

40

~

o

0.5

1.0

1,5

2.0

2.

50

o_

2.5

3.0

3.5

4.0

4.5

_

_

~

50

= rn

n

5.0

TEMPERATURE

TCVos(tLV;eCj

SUPPLY CURRENT
vs TEMPERATURE

--a

0

re)

•
_

COMMON-MODE REJECTION
vs TEMPERATURE

= :l:1SV

Vs = :l:15V
VCM = :tt1V

I--

j....--" V

"z
0

~

110

w

105

~

t-..

~I'--

0

_

0

~

60

TEMPERATURE

n

m

rn

re)

r-

.~. '.0

1.0

os

0.5

2-198 OPERA TlONAL AMPLIFIERS

.

-75

~

-

~

m

rei

Vs R:t5VTO;l;18V

0

_

r50

2.0

l"- t--

0

3_

~

2.5

a

u

_

POWER SUPPLY REJECTION
RATIO vs TEMPERATURE

115

l..- +--

1.0

3.0

NO L.OAD

iD

_

,

TEMPERATURE

120

Vs

0.8

VCM",OV

i-

.....

0.6

~S. "lsV

Vs" :t15V

200

20

0.4

100

250

d15 ullTS I

40

0.2

INPUT OFFSET CURRENT
vs TEMPERATURE

300

FROM 3 RUNS

..

0

INPUT OFFseT VOLTAGE (mY)

INPUT BIAS CURRENT
vs TEMPERATURE

v;. ,'~V

l-

140
120

tOOk

.....

10-

100

FREQUENCY (Hz)

FREQUENCY (Hz)

160

UIt1I

200

It>'
I'>

-50

-25

0
25
50
75
TEMPERATURE rei

100

125

o
-75

,.,.
-so

-25

~

V

i-"""

J....-"

25
50
75
TEMPERATURE re)

V

100

125

REV. A

OP-61
TYPICAL PERFORMANCE CHARACTERISTICS Continued

500

z

~

vs SUPPLY VOLTAGE

20

B••

V, _.t15V

!

SUPPLY CURRENT

OUTPUT VOLTAGE SWING
vs SUPPLY VOLTAGE

OPEN·LOOP GAIN

vs TEMPERATURE
600

i-

R L =10kC

r

'00

Ae • 2]

@;

RL=1kD../

S300

~

---

NO LOAD

TA _.2S-C
R l _1kO

"

r-.... ........
r- t--

pos,/

V

./

"

..............

............ ......

-50

-25

25

50

75

100

.... •

125

TEMPERATURE ("C)

OPEN·LOOP GAIN
vs SUPPLY VOLTAGE
500

..

.,.

.5

T.... +25·C
R L .. 2kn

/

i

6.0

i!l

5.5

....

.,.

.m"

/'

u

5
~

"
"ri

0

t:

Ii;

2.

ili

200

o

."

.5

"0
SUPPLY VOLTAGE (VOLTS)

.20

.. ,...

SINK

-

V, "':e-15V

[450
~

...

TAI.i~CI

lO:l:t5V_

........ r-..

,.
•

SUPPLY VOLTAGE (VOLTS)

OPEN·LOOP GAIN

SOURCE

r-.....
....

.,. ."

.5

vs LOAD RESISTANCE
500

........

~

-5...........

550

50

U

...

SHORT CIRCUIT
OUTPUT CURRENT
vs JUNCTION TEMPERATURE

eo

30

0

250

70

~

'.5

.20

II

~ ~- I-

... •

SUPPLY VOLTAGE

\Is

+2!rC

7••

!§

'00

...

a

i ~5

NEGATIVE

-,.

-75

~

r--

200

'00

"

u

"V

TA

7.'

~

@;

I

~

'00

3'.

/

300

2,.
200

~

•
~
50
~
JUNCTION TEMPERATURE rC)

~

~

'00

1k

10k

'OOk

LOAD RESISTANCE (0)

MAXIMUM OUTPUT VOLTAGE
vs LOAD RESISTANCE

,.

BURN·IN CIRCUIT

T•• ;2'.ri
VI =.t15V

"

.'BY

/

.VOM-I-VOMI

/
-'BY
o
'DO

,.

'Ok

LOAD RESISTANCE (a)

REV. A

OPERATIONAL AMPLIFIERS 2-199

OP-61
SIMPLIFIED SCHEMATIC
NULL

NULL

r-~------'--------r~~------~~------------~r-~~-------oV+

+INo----I::.

OUT

L-----------~--~------~~~--~~------~----__o

APPLICATIONS INFORMATION
The OP-61 combines high speed with a level of precision and noise
performance normally only found with slower amplifiers. Data
acquisition and instrumentation technology has progressed to
where dynamic accuracy and high resolution are both maintained
to a very high level. The OP-61 was specifically designed to meet
the stringent requirements of these systems.

to any op amp are simply another set of sensitive differentially
balanced inputs. Therefore, care must always be exercised in
laying out signal paths by not placing the trimmer, or the nulling
input lines, directly adjacent to high frequency signal lines.

+V
O.1J.1F

Signal-to-noise ratio degrades as input referred noise or bandwidth increases. The OP-61 has a very wide bandwidth, but its
input noise is only 3nV/,(RZ. This makes the total noise generated over its closed-loop bandwidth considerably less than
previously available wideband operational amplifiers.
The OP-61 provides stable operation in closed-loop gain configurations of 10 or more. Large load capacitances should be
decoupled with a resistor placed inside the feedback loop (see
Driving Large Capacitive Loads).
OFFSET VOLTAGE ADJUSTMENT
Offset voltage can be adjusted by a potentiometer of 10kn to
100kn resistance. This potentiometer should be connected between pins 1 and 5 with the wiper connected directly to the OP-61
V+ pin (see Figure 1). By connecting this line directly to the op
amp V+ terminal, common impedance paths shared by both
return currents and the null inputs will be avoided. Nulling inputs

2-200 OPERA TIONAL AMPLIFIERS

V-

~

vos

ADJUST

-v

POTENTIOMETERS RANGING FROM 10ku TO 100kU
CAN BE USED TO OBTAIN A MINIMUM OF ±2mV OF
Vos ADJUSTMENT.

FIGURE 1: Input Offset Voltage Nulling

REV. A

OP-61
O.1",F

+v

+v

~
10.000v

REF·10

•

GND

-v
At
7SkQ

DACA

A.
150kQ

'k..

• k..

+v
DACB

.
DAce

OTHER OUTPUTS
AVAILABLE FOR
OTHER FUNCTIONS

,.
DB,
7

(MSB)

DAeD

DIGITAL

CONTROL

FIGURE 2: Trimming OP-61 Voltage Offset with 0 to 10V Voltage Output, PM-7226 Quad D/A
D/A converters can also be used for offset adjustments in systems that are microprocessor controlled. Figure 2 illustrates a
PM-7226 quad, 8-bit D/A, used to null the OP-61's offset voltage. A stable fixed bias current is provided into pin 5 of the OP61, from R2 , and a REF-1 0, +1 OV precision voltage reference.
Current through R" from the D/A voltage output provides the
programmed V0 s adjustment control. Symmetric control of the
offset adjustment is effected since equal currents are sourced
into R, and R2 when the D/A is at half scale, binary input code =
10000000.
With the circuit components shown in Figure 2, the maximum
Vos adjustment range is ±500mV, referred to the input of the
OP-61. Incremental adjustment range is approximately 21lV per
bit, allowing Vos to be trimmed to ±2IlV.

REV. A

SpF

FIGURE 3: Large- and Small-Signal Response Test Circuit

OPERA TIONAL AMPLIFIERS 2-201

OP-61
TRANSIENT RESPONSE PERFORMANCE
Figures 4 and 5, respectively, show the small·signal and largesignal transient response of the OP-61 driving a 20pF load from
the circuit in Figure 3. Both waveforms are symmetric and exhibit
only minimal overshoot. The slew rate symmetry, apparent from
the large-signal response, decreases the DC offsets that occur
when processing input signals that extend outside the range of
the OP-61 's full-power bandwidth.

V,N

C LOAD

20pF

r'OOOpF

. R.

'00"
FIGURE 6: OP-61 Noninverling Gain of 10 Amplifier,
Compensated to Handle Large Capacitive Loads
FIGURE 4: Small-Signal Transient Response
thereby preserving adequate phase margin. The resulting pulse
response can be seen in Figure 7. Extra care may be required to
ensure adequate decoupling by placing a 1jlF to 1OIlF capacitor
in parallel with the existing decoupling capacitor. Adequate
decoupling ensures a low impedance path for high frequency
energy transferred from the decoupling capacitors through the
amplifier's output stage to a reactive load.

FIGURE 5: Large-Signal Transient Response

DRIVING CAPACITIVE LOADS
Direct capacitive loading will reduce the phase margin of any op
amp. A pole is created by the combination of the op amp's output
impedance and the capacitive load that induces phase lag and
reduces stability. However, high-speed amplifiers can easily drive
a capacitive load indirectly. This is shown in Figure 6. The OP-61
is driving a 1OOOpF capacitive load. R1 and C 1 serve to counteract the loss of phase margin by feedforwarding a small amount of
high frequency output signal back to the amplifier's inverting input,

2-202 OPERATIONAL AMPLIFIERS

FIGURE 7: Pulse Response of Compensated XI 0 Amplifier in
Figure 6, V,N = 100m Vp _p, VOUT;" I Vp _p , Frequency of Square
Wave =1MHz, CWAD = IOOOpF!

REV. A

OP-61
DECOUPLING AND LAYOUT GUIDELINES
The OP-61 op amp is a superb choice for a wide range of precision high-speed, low noise amplifier applications. However,
care must be exercized in both the design and layout of highspeed circuits in order for the specified performance to be realized.
Although the OP-61 has excellent power supply rejection over a
wide bandwidth, the negative supply rejection is limited at high
frequencies since the amplifier's internal integrator is biased via
the negative supply line. This operation is typical performance
for all monolithic op amps, and not unique to the OP-61. Since
the negative supply rejection will approach zero for signals
above the close-loop bandwidth, high-speed transients and
wideband power supply noise, on the negative supply line, will
result in spurious signals being directly added to the amplifier's
output. Adequate power supply decoupling prevents this problem.
Generally, a O.l!-,F tantalum decoupling capacitor, placed in
close proximity across the amplifier's actual power supply pin
and ground is recommended. This will satisfy most decoupling
requirements, especially when the circuit is built on a low impedance ground plane. When a heavy copper clad ground plane is
not used, it becomes especially important to confine the high
frequency output load currents confined to as small a high-frequency signal path as possible, as suggested in Figure 8.

+v

Power management of complex systems sometimes results in a
complex l-C network that has high frequency natural resonances that cause stability problems in circuits internal to the
system. Resistors added in series to the supply lines can lower
the Q of the undesired resonances, preventing oscillations on
the supply lines. Resistors of 3 to 10 ohms work well and serve
to ensure the stability of the OP-61 in such systems.
ADDITIONAL CAVEATS FOR HIGH·SPEEDAMPLIFIERS IN·
ClUDE:
1. Keep all leads as short as pOSSible, using direct point-to-point
wiring. Do not wire-wrap or use "plug-in" boards for prototyping circuits.

2. Op amp feedback networks should be placed in close proximo
ity to the amplifiers inputs. This reduces stray capacitance
that compromises stability margins.

3. Maintain low feedback and source resistance values. Impedance levels greater than several kilo-ohms may result in degrading the amplifier's overall bandwidth and stability.
4. The use of heavy ground planes reduces stray inductance,
and provides a better return path for ground currents.
5. Decoupling capacitors must have short leads and be placed
at the amplifier's supply pins. Use low equivalent series resistance (ESR) and low inductance chip capacitors wherever
possible.
6. Evaluation of prototype circuits should be performed with a
low input capacitance, Xi 0 compensated oscilloscope
probe. Xl uncompensated probes introduce excessive stray
capacitance which alters circuit characteristics by introducing additional phase shifts.
7. Do not directly drive either large capacitive loads or coax
cables with high-speed amplifiers (see DRIVING COAXIAL
CABLES).

8. Watch out for parasitic capacitances at the +/- inputs to wideband noninverting op amp circuits. Since these nodes are not
maintained at virtual ground as in the inverting amplifier configuration, parasitics may degrade bandwidth. Wideband
noninverting amplifiers may require the ground plane trace
removed from local proximity to the op amp's inputs.
-v

FIGURE 8: Proper power supply bypassing is required to obtain
optimum performance with the OP-61. Maintain as smalf wideband signal current path as possible. Where signal common is a
low impedance ground plane, simply decouple O. 1!-,F to ground
plane near the OP-61.

REV. A

OPERA TIONAL AMPLIFIERS 2-203

OP-61
+.5V

+15V

I

O
.•••

'k"

'M<>

."".

~

3p.

Av =-10

-15V

'M"

FIGURE 9: High-Speed Settling Time Fixture (for 0.1 and 0.01%)

SETILING TIME
Settling time is the time between when the input signal begins to
change and when the output permanently enters a prescribed
error band. Figure 9 illustrates the artificial summing node test
configuration, used to characterize the OP-61 settling time. The
OP-61 is set in a gain of -10 with a 1.0V step input.The error
bands on the output are 5mV and 0.5mV, respectively, for 0.1 %
and 0.01% accuracy.
The test circuit, built on a copper clad circuit board, has a FET
input stage which maintains extremely low loading capacitance
at the artificial sum node. Preceeding stages are complementary emitter follower stages, providing adequate drive current for
a 50Q oscilloscope input. The OP-97 establishes biasing for the
input stage, and eliminates excessive offset voltage errors.
Figure 10 illustrates the OP-61 's typical settling time of 330ns.
Moreover, problems in settling response, such as thermal tails
and long-term ringing are nonexistent. This performance of the
OP-61 makes it a suberb choice for systems demanding both
high sampling rates and high resolution.

2-204 OPERA TIONAL AMPLIFIERS

FIGURE 10: Settling Characteristics of the OP-61 to 0.01%.
No Thermal Settling Tail Appears as Part of the Settling
Response.

REV. A

OP-61
+15V

I+

rt-

7A13 PLUG·'N

7All PLUG·'N

'''''

100"
300pF
+15V

DIGITAL
lTL
INPUT

r
1.8kg

+15Vo---WV--.

220"

• NOTE: DECOUPLE CLOSE
TOGETHER ON GROUND PLANE
WITH SHORT LEAD LENGTHS

FIGURE 11: Transient Output Impedance Test Fixture

TRANSIENT OUTPUT IMPEDANCE
Settling characteristics of operational amplifiers also includes
an amplifier's ability to recover, i.e., settle, from a transient current output load condition. An example of this includes an op
amp driving the input from a SAR type AID converter. Although
the comparison point of the converter is usually diode clamped,
the input swing of plus-and-minus a diode drop still gives rise to
a significant modulation of input current. If the closed-loop output impedance is low enough and bandwidth of the amplifier is
sufficiently large, the output will settle before the converter
makes a comparison decision which will prevent linearity errors
or missing codes.
Figure 11 shows a settling measurement circuit for evaluating
recovery from an output current transient. An output disturbing
current generator provides the transient change in output load
current of 1mAo As seen in Figure 12, the OP-61 has extremely
fast recovery of 180n5, (to 0.01 %), for a 1mA load transient. The
performance makes it an ideal amplifier for data acquisition
systems.

REV. A

FIGURE 12: OP-61's Extremely Fast Recovey Time from a
1mA Load Transient to 0.01%

OPERATIONAL AMPLIFIERS 2-205

II

OP-61
DRIVING COAXIAL CABLES
The OP-61 amplifier, and a BUF-03 unity-gain buffer, make an
excellent drive circuit for 75Q or 50Q coaxial cables. To maintain optimum pulse response, and minimum reflections, op amp
circuits driving coaxial cables should be terminated at both
ends. Unterminated cables can appear as a resonant load to the
amplifier, degrading stability margins. Also, since coaxial
cables represent a significant capacitive load shunting the driving amplifier, it is not possible to drive them directly from the op
amp's output (RG-58 coax. typically has 33pF/foot of capacitance).
Figure 13 illustrates an OP-61 noninverting, gain of 10, amplifier
stage, driving a double-matched coaxial cable. Since the
double-matching of the cable results in voltage gain loss of6dB,
the composite voltage gain of the entire circuit is 5, or 14dB.

Resistors R3 and R4 serve to absorb reflections at both ends of
the cable. The OP-61 's wide bandwidth and fast symmetric slewing, results in a very clean pulse reponse, as can be seen in
Figure 15. The BUF-03 serves to increase the output current
capability to 70mA peak, and the ability to drive up to a 1 J1F
capacitive load (or a longer cable). The value of C, may need to
be slightly adjusted to provide an optimum value of phase lead,
or pulse response. This capacitor serves to correct for the current buffers phase lag, internal to the OP-61 's feedback loop.

NOISE MODEL AND DISCUSSION
The OP-61 's exceptionally low voltage noise (en 3.0nV/Hz,
high open-loop gain, and wide bandwidth makes it ideal for accurately amplifying wideband low-level signals. Figure 15a
shows the OP-61 cleanly amplifying a 5mVp-p, 1MHz sine wave,
with inverting gain of 100. Noise or limited bandwidth prevents
most amplifiers from achieving this performance.

=

+v

v,.

-v

",'0CKl
FIGURE 13: OP-61 Noninverting, Amplifier Driving Coaxial
Cable, Composite Gain = 5 from VII,po VOUT ' Adjust C 1 for
Desired Pulse Response.
'

FIGURE 14: Pulse Response from Amplifier Circuit in Figure
13, Driving 15 Ft. of RG-58 Coaxial Cable

2-206 OPERATIONAL AMPLIFIERS

-v

FIGURE 15a: Example of Low Level Amplifier in an Inverting
Configuration, Gain =Vou.,N/N =-RjRj =-100

FIGURE 15b: OP-61, Gain =-100.0, WidebandAmplifier,
V1N =5mVp •p Signal at 1MHz, V OUT =500mVp •p

REV. A

OP-61
z,

The equivalent input voltage noise, referred to the output, can
be found by adding all the noise sources in a sum-of-square
fashion:

Referred back to the amplifiers input:
en; =..§L =
IAveLl
V(en2 {N.G.)2 + in21Z12 (N.G.)2+ in2 IZ1I2 + iZS2 IZil2 + 8Zf2)
FIGURE 16: Inverting Gain Configuration Noise Model for the
OP-61

The inverting amplifier model, seen in Figure 16, can be used to
calculate the equivalent input noise, eni' eni is the voltage noise,
modeled as part of the input signal. It represents all the current
and voltage noise sources lumped into one equivalent input
voltage.
Typical values for the OP-61 nOise parameters are:
en = 3.4nV/ /HZ @ 1kHz

IAveLl
To capitalize on the low voltage performance of the OP-61 , Z, Z,
and especially Zs must be as low impedance as possible. With
low impedance values of Z, and Zs:
. Ven 2 (1 + IAveLj) 2 or e.
eOI!i!I!
m
1Avel 1
I

a

en (N.G.)
(N.G.)-1

All noise contributions are now easily modelled as a signal
equivalent noise voltage source, en; (see Figure 17).

in = 1.7pN ,/Hz @ 10kHz
(where it is assumed that in = in - = in +).
It can be defined from the model in Figure 16:
en; = total input referred spot voltage noise (all noise
contributions lumped into one equivalent voltage
noise source).
en = spot voltage noise of OP-61
in = spot current noise of OP-61
Zs = total input impedance
Z = impedance at OP-61 + input node
AyCl = closed-loop gain for inverting amplifier
N.G. = 1 + IAycll = noise gain for inverting amplifier

FIGURE 17: Equivalent Noise MOdel, Where All Noise Contributions are Lumped Into e ni

izs = spot noise current generated by ZS. If Zs = Rs' then
izs = iRS = 0.12~ nV/v'HZ.
eZf = spot voltage noise generated by Z, . If Z, = R"
then ez, = eR, = 0.129

VA;"nV/VHz.

Note: Equation is derived from Johnson noise relationship of
resistor R:
e R =-/4kTR =y'4kT.fA = 0.129.fA nV/VHz. R is in ohms.

REV. A

OP-61 SPICE MACROMODEL
Figures 18 and 19 show the node and net listfor a SPICE macromodel of the OP-61. The model is a simplified version of the
actual device and simulates important DC parameters such as
Vos' los, IB,Ayo' CMR, Vo and ISY. AC parameters such as slew
rate, gain and phase reponse and CMR change with frequency
are also simulated by the model.
The model uses typical parameters for the OP-61. The poles
and zeros in the model were determined from the actual open
and closed-loop gain and phase reponse of the OP-61. In this
way the model presents an accurate AC representation of the
actual device. The model assumes an ambient temperature of
25°C (see following pages).

OPERATIONAL AMPLIFIERS 2-207

OP-61

OP-51
OP-61 MACROMODEL AND TEST CIRCUIT

©AD11990

• subckt OP-61 1 238 99 50
• INPUT STAGE & POLE AT 300 MHz
rl
r2
r3
r4
cin
c2
il
ios
eos
ql
2

9

2
1
5
6
1
5
4
1
9
5
6

3
3
99
99
2
6
50
2
1
2
9

4
4

5Ell
5Ell
51.6
51.6
5E-12
5.141E-12
lE-3
2E-7
poly(l) 26 32 400E-6 1
qx
qx

• POLE AT 200M Hz
r23
r24
c9
cl0
911

23
23
23
23
99
~12 23

• POLE AT 200M Hz
r25
26
cll
c12
913

24
24
24
24
99
~14 24

99
50
99
50
24
50

• FIRST GAIN STAGE

• POLE AT 200MHz

r7
r8
dll
d12
91
92
e1
e2

r27
r28
c13
c14
915

·

11
11
11
12
99
11
99
12

99
50
10
11
11
50
10
50

lE6
lE6
dx
dx
5 6 2E-4
652E-4
poly(l) 99 32 -4.4 1
poly(l) 32 50 -4.4 1

• SECOND GAIN STAGE & POLE AT 2.5kHz

r9
rl0
c3
c4
93
94
v2
v3
d1
d2

·

13
13
13
13
99
13
99
15
13
15

99
50
99
50
13
50
14
50
14
13

5.1598E6
5.1598E6
12.338E-12
12.338E-12
POIY!l) 11 32 4.24E-3 9.69E-5
poly 1) 32 11 4.24E-3 9.69E-5
2.3
2.3
dx
dx

• POLE-ZERO PAIR AT 4MHz I 8MHz

rll
r12
r13
r14
c5
c6
95
~6

·

16
16
16
16
17
18
99
16

99
50
17
18
99
50
16
50

lE6
lE6
lE6
lE6
19.89E-15
19.89E-15
1332 lE-6
32 13 lE-6

• ZERO-POLE PAIR AT 85M Hz 1300MHz

r17
r18
r19
r20
13
14
97
~8

19
19
20
21
20
21
99
19

20
21
99
50
99
50
19
50

1E6
lE6
2.529E6
2.529E6
1.342E-3
1.342E-3
1632 1E-6
32 16 lE-6

• POLE AT 40MHz
r21
r22
c7
c8
99

22
22
22
22
99
~10 22

99
50
99
50
22
50

lE6
lE6
3.979E-15
3.979E-15
1932 lE-6
32 19 lE-6

lE6
lE6
.796E-15
.796E-15
2232 lE-6
3222 lE-6

99
50
99
50
23
50

25
25
25
25
99
~16 25

99
50
99
50
25
50

lE6
lE6
.796E-15
.796E-15
23321E-6
3223 lE-6

1E6
lE6
.796E-15
.796E-15
2432 lE-6
32 24 1E-6

• COMMON-MODE GAIN NETWORK WITH ZERO AT 40kHz
r29
r30
15
16
917

26
26
27
28
99
~18 26

27
28
99
50
26
50

lE6
lE6
3.979
3.979
33 32 1E-ll
32331E-11

• POLE AT 300MHz
r32
r33
c15
c16
919
920

31
31
31
31
99
31

99
50
99
50
31
50

lE6
1E6
.531E-15
.531E-15
2532 lE-6
3225 lE-6

• OUTPUT STAGE
r34
r35
r36
r37
17
921
922
923
924
v6
v7
d5
d6
d7
d8
d9
dl0

·

32
32
33
33
33
36
37
33
50
34
33
31
35
99
99
50
50

99
50
99
50
38
50
50
99
33
33
35
34
31
36
37
36
37

20.0E3
20.0E3
30
30
1.65E-7
31 33 33.3333333E-3
33 31 33.3333333E-3
99 31 33.3333333E-3
31 50 33.3333333E-3
.2
.2
dx
dx
dx
dx
dy
dy

• MODELS USED

·model ~x NPN(BF=1250)
·model x D!IS=lE-15)
'modeldy D IS=1E-15 BV=50)

FIGURE 19: OP-61 SPICE Net List
.. PSpice Is a registered trademark of MicroSim Corporation .
.... HSPICE is a tradename of Mela-Software, Inc.

REV. A

OPERA TIONAL AMPLIFIERS 2-209

•

2-210 OPERA TlONAL AMPLIFIERS

High-Speed, Wide-Bandwidth
Operational Amplifier (AvCL :> 5)
OP-64 I

11IIIIIIII ANALOG
WDEVICES
FEATURES

GENERAL DESCRIPTION

• High Slew Rate ................................................ 130VIllS Min
• Fast Settling Time (+10V, 0.1%) ....................•.. 100nsTyp
Gain-Bandwidth Product (AvCL = +5) .....•.....•.. SOMHz Typ
Low Supply Current ............................................ SmA Max
Low Noise ....................................................... SnV/-YHz Typ
Low Offset Voltage .............................................. 1mV Max
High Output Current ........................................ ±SOmA Typ
Eliminates External Buffer
Standard S-Pin Packages
Available in Die Form

The OP-64 is a high-performance monolithic operational amplifierthat combines high speed and wide bandwidth with low power
consumption. Advanced processing techniques have en-

Continued.
PIN CONNECTIONS
EPOXY MINI-DIP
(P-Suffix)
S-PIN CERDIP
(Z-Suffix)

ORDERING INFORMATION t
PACKAGE
T.=+25°C
VosMAX
(mV)
1.0
1.0
2.0
2.5
2.5

To-99
II-PIN

HERMETIC
DIP
II-PIN

PLASTIC
II-PIN

OP64AJ' OP64AZ'
OP64EJ OP64EZ
OP64FJ OP64FZ

EPOXY SO
(S-Suffix)

OPERATING
HERMETIC
LCC
TEMPERATURE
2()'CONTACT
RANGE
MIL
XIND
XIND
XIND
XIND

OP64ARC/883

OP64GP
OP64GS"

XIND = Extended Indust!ial Temperature Range, -40°C to +85°C
For devices processed in total compliance to MIL-SDT-883, add 1883 after part
number. Consult factory for 883 data sheet.
Burn-in is available on commercial and industrial temperature range parts in
CerDlP, plastic DIP, and TO·99 can packages.
tt For availability and burn-in information on SO and PLCC packages, contact

your local sales office.

20-LEAD HERMETIC LCC
(RC-Suffix)

TO-99
(J-Suffix)

SIMPLIFIED SCHEMATIC
r----.--~--------------~--~------._--------.--------.--------.---~v+

OUT

~--~--~---------1----~------4---------~----------

NULL

REV. A

__--------4---~ v-

NULL

OPERA TlONAL AMPLIFIERS 2-211

OP-64
GENERAL DESCRIPTION Continued

enabled PMI to make the OP-64 superior in cost and performance to many dielectrically-isolated and hybrid op amps.
Slew rate of the OP-64 is over 130VIllS. It is stable in gains of ~5
and has a settling time of only lOOns to 0.1% with a 10V step
input. However, unlike other high-speed op amps which have
high supply requirements, the OP-64 needs less than SmA of
supply current. This enables the OP-64 to be packaged in space
saving S-pin packages. The OP-64 can deliver ±SOmA of output
current eliminating the need for a separate buffer !!!!!plifier in
many applications. Noise of the OP-64 is only SnV"Hz, reducing system noise in wideband applications. In addition to its dynamic performance, the OP-64 adds DC precision with an input
offset voltage of under 1mV.
The OP-64 is an ideal choice for RF, video and pulse amplifier
applications and in new designs can replace the HA-5190/95 or
EL-2190/95 with improved performance and reduced power
consumption. Its high output current also suits the OP-64 for use
in AID or cable driver applications. The OP-64 includes a DiSABLE pin which, when set low, shuts the amplifier off and reduces the supply current to 0.75mA.

ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage ................................................................. :i: ISV
Input Voltage .................................................... Supply Voltage
Differential Input Voltage ................................................... 20V

DISABLE Input Voltage ................................... Supply Voltage
Output Short-Circuit Duration ........................................ 10 sec
Storage Temperature Range
(J, Z, RC) .................................................... -SS·C to + 17S·C
(P, S) ... :...................................................... -6S·C to +IS0·C
Operating Temperature Range
OP-64A (J, Z, RC) ...................................... -SS·C to +12S·C
OP-64E, F (J, Z) ........................................... -40·C to +8S·C
OP-64G (P, S) .............................................. -40·C to +8S·C
Maximum Junction Temperature
OP-64A (J ,Z, RC) ...............................•... ,..............•.. +17S·C
OP-64E, F (J, Z) ........................................................ +17S·C
OP-64G (P, S) ................................. :......................... +150·C
Lead Temperature (Soldering, 60 sec) ........................ +300·C
alC

UNITS

TO·99 (J)

PACKAGE TYPE

150

18

·CIW

8-Pin Hermelic DIP (Z)

148

16

·CIW

8-Pin Plastic DIP (P)

103

43

·CIW

98

38

·CIW

158

43

·CIW

alA (Note 2)

20-Contacl LCC (RC. TC)
8-Pln SO (5)

NOTES:
1. Absolute maximum ratings apply to both DICE and packaged perls, unless
otherwise noted.
2. alA is spacified lor worst case mounting conditions, I.e., alA is specified for
device In socket lor TO, CerDIP, P-DIP, and LCC packages; alA is specified
for device soldered to printed circuit board for SO package.

ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = +25°C, unless otherwise noted.
CONDITIONS

MIN

OP-64A1E
TYP

Offset
Voltage

vos

0.4

0.8

2

1.2

2.5

mV

Input Bias
Current

IB

0.2

0.4

2

0.8

2.5

~A

Input Offset
Current

los

0.1

0.3

2

0.6

2.5

~A

Input Voltage
Range

IVR

Common·Mode
Rejection

CMR

Power·Supply
Rejection Ratio

PSRR

Vs =±SV to ±18V

Large·Signal
Voltage Gain

Avo

RL = 2kil, Vo = ±IOV
RL = 2000, Vo = ±SV

Output Voltage
Swing

Vo

Output
Current

lOUT

Supply
Current

ISY

±11

90

MAX

±11

84

100

5

17.8

MIN

±11

94

15

84

31.6

UNtTS

V

94

15

dB

31.6

~V!V

30
12.5

45
18

20
10

35
16

20
10

35
16

V/mV

±11
±10

±12.5
±Il.7

±11
±IO

±12.5
±11.7

±11
±10

±I2.5
±Il.7

V

±80

mA

±80

No Load

MIN

OP-64G
TYP
MAX

SYMBOL

(Note II

MAX

OP-64F
TYP

PARAMETER

6.2

±80

8

6.2

8

6.2

8

mA

NOTE:
1. Guaranteed by CMR test.

2-212 OPERA TIONAL AMPLIFIERS

REV. A

OP-64
ELECTRICAL CHARACTERISTICS at Vs =±15V, T A = +25°C, unless otherwise noted.
PARAMETER

SYMBOL

CONDITIONS

ISY DiS

DISABLE =OV
Total for both supplies

DISABLE
Current

IDiS

DISABLE = OV

Slew Rate

SR

RL =2kn

Full·Power
Bandwidth

BWp

(Note 2)

Gain·Bandwidth
Product

GBWP

Av=+5

Settling Time

ts

10V Step 0.1%

Disable Supply

Current

MIN

OP-64A/E
TYP

MAX

MIN

OP-64F
TYP

MAX

MIN

OP-64G
TYP
MAX

UNITS

0.75

0.75

0.75

mA

0.5

0.5

0.5

mA

t30

t70

t30

t70

t30

170

V/~s

2

2.7

2

2.7

2

2.7

MHz

MHz

80

80

80

100

100

100

57

57

57

ns

-

Phase Margin

em

Input
Capacitance

C 1N

5

5

5

pF

Open-Loop
Output

Ro

30

30

30

n

en

fo = 10Hz
fo = 100Hz
fo = 1kHz
fo = 10kHz

30
10
8
8

30
10
8
8

30
10
8
8

in

fo = 10kHz

7.5

7.5

7.5

4

4

4

Av =+5

degrees

Resistance
Voltage

Noise
Density

Current Noise
Density
External Vcs
Trim Range

Rpo '= 20kn

Supply Voltage
Range

Vs

±5

±15

±18

±5

±15

±18

±5

±15

-

nV/VHz

-

pAlVHz

mV

±18

V

NOTES:
1. Guaranteed by CMR test.
2. Guaranteed by slew·rate test and formula BWp = SRI(2xl0V pEAK ).

REV. A

OPERA TIONAL AMPLIFIERS 2-213

II

OP-64
ELECTRICAL CHARACTERISTICS at Vs = ±15V, -40°C S TAS +85°C for OP-64E1F/G, unless otherwise noted.
PARAMETER

SYMBOL

Offset
Voltage

Vos

Input Bias
Current

la

CONDITIONS

MIN

OP-64E
TYP

MAX

MIN

OP-64F
TYP

0.5

t.5

1.0

VCM=OV

0.3

2.5

0.5

los

VCM =OV

0.2

2.5

0.5

Input Voltage
Range

IVR

(Note I)

Common·Mode
Rejection

CMR

VCM=±II

Power·Supply
Rejection Ratio

PSRR

Vs =±5Vto±18V

Large·Signal
Voltage Gain

Avo

RL =2kn, Vo=±IOV
RL =200Q, Vo =±5V

Output Voltage
Swing

Vo

RL=2kn
RL =200Q

Supply
Current

ISY

No load

Input Offset

Current

±II

86

MAX
3

3

±II

100

5

80

OP-64G
TYP
MAX

94

80

3:5

mV

1.5

3.5

~A

t.O

3.5

~A

V

94

IS

50

UNITS

1.5

±II

IS

31.6

MIN

dB

50

~VN

20
7.5

40
12

IS
5

35
10

IS
5

35
10

VlmV

±II
±IO

±12.3
±11.5

±II
±IO

±12.3
±11.5

±II
±IO

±12.3
±11.5

V

6.3

8.5

6.3

8.5

6.3

8.5

mA

NOTE:
I. Guaranteed by CMR test.

ELECTRICAL CHARACTERISTICS at VS = ±15V, -55°C S T A S + 125°C for OP-64A, unless otherwise noted.
PARAMETER

SYMBOL

Offset
Voltage

Vos

Input Bias
Current

la

Input Offset
Current

CONDITIONS

MIN

OP-64A
TYP

MAX

UNITS

0.4

2

mV

VCM=OV

0.35

2

~A

los

VCM=OV

0.3

2

~A

Input Voltage
Range

IVR

(Note I)

Common·Mode
Rejection

CMR

VCM=±II

Power-Supply
Rejection Ratio

PSRR

Vs =±5Vto±18V

large·Signal
Voltage Gain

Avo

RL =2kQ, Vo=±IOV
RL = 200Q, Vo = ±5V

Output Voltage
Swing

Vo

RL =2kQ
RL =2ooQ

Supply
Current

ISY

No load

±II

86

V

100

8

dB

31.6

~VN

20
7.5

30
10

V/mV

±II
±7.5

±12
±IO

V

6.4

8.5

mA

NOTE:
I. Guaranteed by CMR test.

2-214 OPERATIONAL AMPLIFiERS

REV. A

OP-64
DICE CHARACTERISTICS

1.
2.
3.
4.
5.
6.
7.
8.

NULL
-IN
+IN
VNULL
OUT
V+
DISABLE

II

DIE SIZE 0.086 x 0.065 inch, 5,590 sq. mils
(2.18 x 1.65 mm, 3.60 sq. mm)

WAFER TEST LIMITS at Vs

= ±15V, TA = +25°C, unless otherwise noted.

OP-64GBC
PARAMETER

SYMBOL

Offset Voltage

Vas

Input Bias Current

18

Input Offset Current

los

Input Voltage Range

IVR

(Note 1)

Common-Mode Rejection

CMR

VCM =±I1V

Power Supply
Rejection Ratio

PSRR

Vs = ±5V to ±18V

Large·Signal
Voltage Gain

Ava

RL = 2kO, Va = ±10V
RL = 200n, Va = ±5V

Output Voltage
Swing

Va

RL =2kO
RL = 2000

Slew Rate
Supply Current

SR

CONDITIONS

LIMITS

UNITS

2.5

mVMAX

VCM = OV

2.5

~AMAX

VCM = OV

2.5

~AMAX

VMIN

84

dBMIN

31.6

~VNMAX

20
10

V/mVMIN

±11
±10
120

RL =2kn
ISY

±11

No Load

8

VMIN
V/~s

MIN

rnA MAX

NOTES:
1. Guaranteed by CM R test.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for
standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

REV. A

OPERA TlONAL AMPLIFIERS 2-215

OP-64
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs TEMPERATURE
0.7
=±15V

~:;~~v

0 .•

~

i!;
~

:.-- I--

0.3

~

0.4

"

0.3

."~

......... V

~

0.4

V

-

0.5

g

i

0.4

0.5

Ys

~w

"\

~
0.2

"-

~

0.2

-50

-25

25

50

75

100

-25

25

50

SETTLING TIME
vs STEP SIZE

RL=2k~,1_

i"-- .........

-

100

2

51

1'-

..

0

~

-2

~

-10

-SO

-25

25

SO

75

100

125

\

-75

125

-SO

-25

-

1-25

50

75

r-100

125

=±15V I

Av=+S
R L =200U

65

D r::::

,

o

50

25

75

10mV

100

40
-75

125

50

20

-SO

-25

0

25

50

75

100

125

+2~~~

TA =
Vs =±15V

TA '" +2S·C
Vs =*15V
VIN '" 20mVp-p
AV = +5

.0

t-r-

CLOSED-LOOP OUTPUT
IMPEDANCEvsFREQUENCY

100

'0

~r-GBW'-

TEMPERATURE (OC)

SMALL SIGNAL OVERSHOOT
vs CAPACITIVE LOAD

OPEN-LOOP GAIN,
PHASEvsFREQUENCY

-

m

45

SETTLING TIME (ns)

100

~

140

lis
+10mV

~

TEMPERATURE (0C)

40
NEGATIVE EDGE

iD 60

'~"

"-

40

fil

~

$

f'..

1\

5-4
-8

:

100

/
IL

4

~
w

I'-.. ......

i"--

-8R

'"
~

50

~

0.1

GAIN-BANDWIDTH PRODUCT, PHASE
MARGIN vs TEMPERATURE

I

o

~

~

1\\

70

=

ill

~

0.2

TEMPERATURE (OC)

TA =+2SOC
Vs =±15V
AV =+5

Vs =±15V
Av +5V

~

-75

"

10

w

o

."~

r--

75

SLEW RATEvs
TEMPERATURE

i'- i'-

l150
~

-50

TEMPERATURE (OC)

+SR

200

0.3

;!;

r-

TEMPERATURE (OC)

250

~

I
........

=~'5V

~M=OV

o

0.1
-75

125

•

1\

~
;!;

0.1
-75

INPUT OFFSET CURRENT
vs TEMPERATURE

INPUT BIAS CURRENT
vs TEMPERATURE

e.

20

135

ill
f
~

0

~

t;

""

60

1j

0

~

~

30

z

~

~

40

i!!

20
AYCL=+100
AYCL=+10AyCt=+S-

180
10

20

0 ' - _ - - l ._ _...L.._ _.1--_--'_ _-'
10k

lOOk

1M

10M

100M

FREQUENCY (Hz)

2-216 OPERATIONAL AMPLIFIERS

o

20

40

60

CAPACITIVE LOAD (pF)

80

100

o

i
1k

10k

"
100k

i>"

~

1M

10M

FREQUENCY (Hz)

REV. A

OP-64
TYPICAL PERFORMANCE CHARACTERISTICS
CLOSED-LOOP GAIN
vs FREQUENCY
50

AvcL

CURRENT NOISE DENSITY
vs FREQUENCY

VOLTAGE NOISE DENSITY
vs FREQUENCY

..

100

~~" ~~.:,

II I I! I

40

Continued

\Is

TA _+25OC

=±15Y

Vs =±15V

=+100
11111

lv~~1 ~1~'01

~

111111

!!!

AYCL

"

~
w

0
Z

=+5

II

~

10

~

mllill

0:

"

0

-10

110~..J..J...J..J.J..lJ'':00:-.l....Jw....cJ.l.U'kl.......J..J...J..ll.llU,,,

-20
10k

"

lOOk

1M

lUM

100M

FREQUENCY (Hz)

SUPPLY CURRENT
vs TEMPERATURE

1

10

Isy DISABLE vs
TEMPERATURE
1.00

...~

~

§
o

~v

./
. /. /
V/
/..,
."
/'r'
:/'

6.4

i

6.2

~ 5.6

5.0
4 ••

-75

-50

-25

25

50

75

100

125

o

TEMPERATURE ("C)

Vs =±15V

~'2

6

~ 10

I,.
I
"

/

/

%10

.15

-75

..0

-50

-25

~

1A

125

= +25OC

~

~-I-VOMI

~

~

".

V'"

/'

40

../

0

i

iii

6

"

;; 2.5

4

100

R L =2kU

~ 2.7

§

75

50

2.8

:E 2.6

50

OPEN-LOOP GAIN
vs SUPPLY VOLTAGE

TA=+25"C

g,

25

60

2.'

l-vOM I

-

i--

TEMPERATURE lOCI

3.0

IIU
+Vou ..

o

MAXIMUM OUTPUT VOLTAGE
vs LOAD RESISTANCE
Vs =±5V

II

TA =+25OC

14

-- r-r-.. -

SUPPLY VOLTAGE (VOLTS)

MAXIMUM OUTPUT VOLTAGE
vs LOAD RESISTANCE
Vs =±15V
16

~ 0.25

..... S~PIS

.

r--.. ........ r--

~

L

5.2

+ISVDIS

~ 0.50

~'C

il:

i"-r-. ........

l

;

+25"C

5.8

DISABLE=OY

...

0.75

+125"C

6.0

m5.4

3

10'

SUPPLY CURRENT
vs SUPPLY VOLTAGE
NO LOAD

6.6

!Z
ll!

lk

FREQUENCY (Hz)

6.8

Va =±15V
NO LOAD

100

FREQUENCY (Hz)

30

V-

/

20
2.4

o

100

1.
LOAD RESISTANCE (U)

REV. A

10k

2.3
100

10

"

LOAD RESISTANCE (U)

10k

o

..

:t10

±15

toO

SUPPLY VOLTAGE (VOLTS)

OPERATIONAL AMPLIFIERS 2-217

OP-64
TYPICAL PERFORMANCE CHARACTERISTICS Continued
OPEN-LOOP GAIN

COMMON-MODE REJECTION
vs FREQUENCY

vs SUPPLY VOLTAGE
25

140

TA=+~~I

TA =+25"C
RL =21~O1!

120

20

>E

~

z

C

,.

V

V

"

I

!!.100

i'

.

o

;

60

a:

so

±10

%15

-20

±20

140

T~ ~~~:'C

"

!i100

a:

1:11

!~

I

+PS~~",

40
20

I

il:

I..

I

I

i

~i
1~~N

~ 60

i!

..,C

I

I

I
I

....

1k

10k

tOOk

0.8
0.5

G

0.4

~

D.'

~-

0.2
0.1

I
100

10M

TA =+25·C
"s="5V

0.7

I

r-.

1M

0..

!

I

100k
FREQUENCY (Hz)

INPUT BIAS CURRENT vs
COMMON-MODE VOLTAGE

Vs =±15V

o

10k

"

SUPPLY VOLTAGE (VOLTS)

POWER SUPPLY REJECTION
RATIO vs FREQUENCY
m120

I\.

I:

10

o

Vs =:t15V

;;;

~

o

1M

FREQUENCY (Hz)

10M

r\
\

\

""

-12.5 -10.0 -7.5 -5.0 -2.5

0

2.5

5.0

7.5 10.0 12.5

COMMON-MODE VOLTAGE (VOLTS)

BURN-IN CIRCUIT
10kU

+15V

.---+--0 DISABLE

10kS.l

tOU

-15V

2-218 OPERATIONAL AMPLIFIERS

REV. A

OP-64
LARGE SIGNAL RESPONSE (Vs =±15V)

LARGE AND SMALL SIGNAL RESPONSE
TEST CIRCUIT
+v

OUTPUT

, . - - - - - 0 DISABLE
INPUT

/,---,,---~---oVOUT

200U

SMALL SIGNAL RESPONSE (Vs = ±15V)

OUTPUT

INPUT

LARGE SIGNAL RESPONSE (V s = ±5V)

Av =+5

-v

obtaining optimum performance from the OP-64. Proper high
frequency layout reduces unwanted signal coupling in the circuit. When breadboarding a high frequency circuit, use direct
point-to-point wiring, keeping all lead lengths.as short as possible. Do not use wire-wrap boards or "plug-in" prototyping
boards.
During PC board layout, keep all lead lengths and traces as
short as possible to minimize inductance. The feedback and
gain-setting resistors should be as close as possible to the inverting input to reduce stray capacitance althat point..To further

OUTPUT

v+
INPUT

APPLICATIONS INFORMATION
POWER SUPPLY BYPASSING AND
LAYOUT CONSIDERATIONS
Proper power supply bypassing is critical in all high-frequency
circuit applications. For stable operation of the OP-64, the
power supplies must maintain a low impedance-to-ground over
an extremely wide bandwidth. This is most critical when driving
a low resistance or large capacitance, since the current required
to drive the load comes from the power supplies. A 1 O~F and
0.1 ~F ceramic bypass capacitor are recommended for each
supply, as shown in Figure 1, and will provide adequate highfrequency bypassing in most applications. The bypass capacitors should be placed at the supply pins of the OP-64. As with all
high frequency amplifiers, circuit layout is a critical factor in

REV. A

v-

FIGURE 1: Proper power supply bypassing is required to obtain
optimum performance with the OP-64.

reduce stray capacitance, remove the ground plane from the
area around the inputs of the OP-64. Elsewhere, the use of a
solid unbroken ground plane will insure a good high-frequency
ground.

OPERATIONAL AMPLIFIERS 2-219

•

OP-64
v.

.15V

..-----oOiiiAiilli
~--OOIlT

RPOT

=:I

20k11 TO 100kJ,l

v-

FIGURE 2: Input Offset Voltage Nulling

OFFSET VOLTAGE ADJUSTMENT
Offset voltage is adjusted with a 20kO potentiometer as shown
in Figure 2. The potentiometer should be connected between
pins 1 and 5 with its wiper connected to the V- supply. The typical trim range is ±4mV.

OP-64 DISABLE AMPLIFIER SHUTDOWN
Pin 8 of the OP-64, DISABLE, is an amplifier shutdown control
input. The OP-64 operates normally when Pin 8 is left floating.
When greater than 250llA is drawn from the DISABLE pin, the
OP-64 is disabled. The supply current drops to 1mA and the
output impedance rises to 2kO. To draw current from the DISABLE pin, an open collector output logic gate or a discrete NPN
transistor can be used as shown in Figure 3. An internal resistor

FIGURE 4: DISABLE Tum-On/Tum-Off Test Circuit
limits the DISABLE current to around 500liA if the DISABLE pin
is grounded with the OP-64 powered by ±15V supplies. These
logic interface methods have the added advantage of level shifting the TTL signal to whatever supply voltage is used to power
theOP-64.
Figure 4 shows a test circuit for measuring the turn-on and turnoff times for the OP-64. The OP-64 is in a gain of 5 with a +1V DC
input. As the input pulse to the 74LS04 rises its output falls,

v.

v.

SkU

2V
I I 0---./l1lI'--1:.
ov--.J L

v-

LOOICGATE
WITH OPEN
COLLECTORIORAIN
OIITPUT

v-

FIGURE 3: Simple circuits allow the OP-64 to be shut down.

2-220 OPERA T10NAL AMPLIFIERS

REV. A

OP-64
drawing current from the DISABLE pin and disabling the amplifier. The output voltage delay is shown in Figure 5 and takes
500llS to reach ground due to the extra current supplied to the
amplifier by the 1OIlF electrolytic bypass capacitors. The turnon time is much quicker than the turn-off time. In this situation as
the inputlo the 74LS04 falls its output rises, returning the OP-64
to normal operation. The amplifier's output turns on in 250ns.

The 750 cable termination resistor minimizes reflections from
the end of the cable. The 750 series output resistor absorbs any
reflections caused by a mismatch between the 750 termination
resistor and the characteristic cable impedance. In this circuit
the output voltage, Voup is one-half of the OP-64's output voltage due to the divider formed by the 750 terminating resistors.
The output voltage at the end of the terminated cable, Voup
spans -1 V to + 1V. The differential gain and phase for the video
amplifier is summarized in Tablel.

(8)
OUTPUT

TABLE 1: Differential Gain and Phase of Video Amplifier/Line
Driver
Differential Gain

LOGIC INPUT

Differential Phase

3.58MHz

5MHz

3.58MHz

5MHz

0.008dB
0.008dB

0.016dB
0.018dB

0.03°
0.03°

0.03°
0.03°

±15V
±12V

+15V

(b)
OUTPUT

1I1S,±1V
SQUARE WAVE

LOGIC INPUT

·INo-~----I

~---~--oVo~
501'
200U

FIGURE 5: (a) OP-64 turn-on and turn-off performance. (b)
Expanded scale showing turn-on performance of the OP-64.
-15V

OVERDRIVE RECOVERY
Figure 6 shows the overdrive recovery performance of the OP64. Typical recovery time is 270ns from negative overdrive and
80ns from positive overdrive.

FIGURE 7: Overdrive Recovery Test Circuit

+15V

VIDEO AMPLIFIERrrERMINATED LINE DRIVER
The OP-64 can be used as a video amplifier/terminated line
driver as shown in Figure 8. With its high output current capability, the OP-64 eliminates the need for an external buffer.

·'No-...----;

V OUT

lOV/DIVISION
-1SV

V'N
lV/DIVISION

FIGURE 8: Video Amplifier/Terminated Line Driver

FIGURE 6: OP-64 Overdrive Recovery

REV. A

OPERATIONAL AMPLIFIERS 2-221

•

OP-64
+5V

------1

1::..~~DANce
1M11
1SOURCE
.--MH--o--+--.I
1
R,

1

1

8IJO{1

-:-

1_____ -

1
1

R2
:100n

FIGURE 9: Fast Transimpedance Amplifier
FAST TRANSIMPEDANCE AMPLIFIER

The circuit shown in Figure 9 is a fast transimpedance amplifier
designed to handle high speed signals from a high impedance
source such as the output of a photomultiplier tube. The input
current is amplified and converted to an output voltage by the
transimpedance amplifier.
A JFET source-follower input is used to reduce the input bias
current of the amplifier to 100 pA and lower the input current
noise. Transimpedance of the amplifier is:
VOUT =
liN

(.81. + 1) A3

FIGURE 10: Output of the Fast TransimpedanceAmplifier

A2

and for the values shown equals
VOUT =(8000 + 1) 400kO = 2V/IlA
liN
2000
Figure 10 shows the output of the transimpedance amplifier
when driven from a 1MO source impedance. The input signal of
lOIlAp.p is converted into an output voltage of (1 01lA) 2V/IlA =
20Vp.p. Output slew rate is 100V/IlS. The slew rate is limited by
the combination of the capacitance of the JFET gate with the
1MO ~ource impedance. For best performance. the stray input
capacitance should be kept as small as possible. The OP-97 is
used in an integrator loop to reduce the total amplifier offset
voltage to under 251lV.

2-222 OPERATIONAL AMPLIFIERS

OP-64 SPICE MACRO·MODEL

Figure 11 shows the node and net list for a SPICE macro-model of
the OP-64. The model is a simplified verSion of the actual device and
simulates important DC parameters such as Vos' los· Ie. Avo. CMR.
V0 and ISY. AC parameters such as slew rate. gain and phase response and CMR change with frequency are also simulated by the
model.
The model uses typical paremeters for the OP·64. The poles and
zeros in the model were determined from the actual open and closedloop gain and phase response of the OP-64. In this way the model
presents an accurate AC representation of the actual device. The
model assumes an ambient temperature of 25°C (see following
pages).
.

REV. A

OP-64
99
©PM11989

R,

IN-

R,

0,

•
R,

II

D,

"os

1

R.

11

R,
IN+

G,

C,

R,

R,

CJN

los

C.

G,

C,

Ra

-+

0,

C,

R,o

G,
C,

(a)

(b)

(e)

9.

t.,
R21

0.

C,

22

R23

G"

C,

G13

Ca

R"

c"

R,.

C 12

2.

23

0,.

R..

G12

R24

c,.

G"

L,

SO
~

(d)

(I)

(e)

(h)

(0)

V.

99

G23

oa
G"

R"

CIS

R,.

R34
0,

V,
34

+-

3.
31

V,

35

-+

R30
28

Goo

R"

c"

R35

R"
G"

L,
50
(I)

(I)

(k)

FIGURE 11 a: OP-64 SPICE Macro-Model Schematic and Node List

., PSpice is a registered trademark of MicroSim Corporation.
*'" HSPICE is a tradename of Meta-Software, Inc.

REV. A

OPERA TIONAL AMPLIFIERS 2-223

OP-64

·
·
·

OP-64 MACRO-MODEL e PMll989

INPUT STAGE & POLE AT 39.8 MHz
rl
r2
r3
r4
r5
r6
cin
c2
il
ios
eos
ql
~2

2
1
5
6
4
4
1
5
4
1
9
5
6

3
3
99
99
7
8
2
6
50
2
1
2
9

7
8

j5Ell
5Ell
474.86
474.86
423.26
423.26
5E-12
4.2106E-12
lE-3
lE-7
poly(l) 26 32 4E-4 1
qx
qx

: SECOND STAGE & POLE AT 3.8 kHz
r7
r8
c3
c4
gl
g2
v2
v3
dl
d2

·

·

11
11
11
11
99
11
99
12
11
12

99
50
99
50
11
50
10
50
10
11

7.1229E6
7.1229E6
5.88E-12
5.88E-12
poly(l) 5 6 4.31E-3 2.1059E-3
poly(l) 6 5 4.31E-3 2.1059E-3
2.25
2.25
dx
dx

• POLE AT 39.8 MHz
r9
rIO
c5
c6
93
94

·
·

13
13
13
13
99
13

99
50
99
50
13
50

lE6
lE6
4E-15
4E-15
11 321E-6
32 11 lE-6

• ZERO-POLE PAIR AT 26.5 MHz /159 MHz
r13
r14
r15
r16
11
12
g5

~6

·

16
16
17
18
17
18
99
16

17
18
99
50
99
50
16
50

lE6
lE6
5E6
5E6
5.005E-3
5.005E-3
13 32 lE-6
32 13 lE-6

• ZERO-POLE PAIR AT 31.8 MHz /39.8 MHz
r17
r18
r19
r20
13
14
97

~8

·

·

·POLE AT 159 MHz

osubckt OP-64 1 238 99 50

19
19
20
21
20
21
99
19

20
21
99
50
99
50
19
50

lE6
lE6
2.5157E5
2.5157E5
1.006E-3
1.006E-3
16 321E-6
32 161E-6

r23
r24
e9
cl0
gll
g12

·
·

23
23
23
23
99
23

99
50
99
50
23
50

lE6
lE6
lE-15
lE-15
22 32 lE-6
32 22 lE-6

·POLE AT 159 MHz
r25
r26
ell
e12
g13
g14

·
·

24
24
24
24
99
24

99
50
99
50
24
50

lE6
lE6
lE-15
lE-15
23 321E-6
3223 lE-6

·COMMON-MODE GAIN NETWORK WITH ZERO AT 20kHz
r29
r30
15
16
917
918

·
·

26
26
27
28
99
26

27
28
99
50
26
50

lE6
lE6
7.9575
7.9575
3332 lE-ll
3233 lE-ll

• POLE AT 159 MHz
r32 31
r33 31
e15 31
e16 31
g19 99
g2031

·
·

99
50
99
50
31
50

lE6
lE6
lE-15
lE-15
24 321E-6
32 241E-6

• OUTPUT STAGE
r34
r35
r36
r37
17
g21
g22
g23
g24
v6
v7
d5
d6
d7
d8
d9
dl0

·

32
32
33
33
33
36
37
33
50
34
33
31
35
99
99
50
50

99
50
99
50
38
50
50
99
33
33
35
34
31
36
37
36
37

20.0E3
20.0E3
60
60
2.9E-7
31 33
33 31
99 31
31 50
1.7
1.7
dx
dx
dx
dx
dy
dy

16.6666667E-3
16.6666667E-3
16.6666667E-3
16.6666667E-3

·

• MODELS USED
omodel qx NPN(BF=2500)
omodel dx
D(IS=lE-15)
omodel dy
D(IS=lE-15 BV=50)
oends OP-64

• POLE AT 100 MHz
r21
r22
e7
c8
99
g10

22
22
22
22
99
22

99
50
99
50
22
50

lE6
lE6
1.59E-15
1.59E-15
19 321E-6
32 19 lE-6

FIGURE 11 b: OP-64 SPICE Net-List

2-224 OPERATIONAL AMPLIFIERS

REV. A

High-Speed, Current Feedback
Operational Amplifier
OP-160 I

r.ANALOG
WDEVICES
FEATURES
•
•
•
•
•
•
•

Easy To Use - Drives Large Capacitive Loads
Very High Slew Rate (Av +1) .................... 1300 V/~s Typ
Bandwidth (Av = +1) .............•........................... 90MHz Typ
Low Supply Current .....................•.................... 6.5mA Typ
Bandwidth Independent of Gain
Unity-Gain Stable
Power Shutdown Pin

=

Slew rate of the OP-160 is typically 1300V/~s and is guaranteed
to exceed 1000V/~s.ln addition, the OP-160's current feedback
design has the added advantage of nearly constant bandwidth
versus gain. In a gain of + 1 the -3dB bandwidth is 90MHz! The
OP-160 also requires only 6.5mA of supply current, a considerable power savings over other high-speed amplifiers.
Applications using the OP-160 can be implemented with the same
circuit assumptions utilized for conventional voltage feedback
op amps. With its high speed and bandwidth, the OP-160 is ideal
for a variety of applications including video amplifiers, RF amplifiers, and high-speed data acquisition systems.

APPLICATIONS
•
•
•
•
•

topology for very high slew rate and wide bandwidth performance.

High-Speed Data Acquisition
Communication Systems/RF Amplifiers
Video Gain Block
High-Speed Integrators
Driving High-Speed ADCs

The OP-160 is an easy-to-use alternative to the AD844, AD846,
EL2020 and EL2030.
For applications requiring a high-speed, wide bandwidth dual
amplifier, see the OP-260.

ORDERING INFORMATION t
TA =+2SoC
V,osMAX
(mV)
5.0
5.0
5.0

PACKAGE
CERDIP
B-PIN
OP160AZ'
OP160FZ

PLASTIC
a·PIN

LCC
20·CONTACT
OP 160ARC/883

OP160GP
OP160GSrt

OPERATING
TEMPERATURE
RANGE
MIL
XIND
XIND

• For devices processed in total compliance to MIL-STD-883, add 1883 after part
number. Consult factory for 883 data sheet.
t Burn-in is available on extended industrial temperature range parts in CerDIP
and plastic packages.
It For availability and burn-in information on SO package, contact your local sales
office.

GENERAL DESCRIPTION
The OP-160 is an easy-to-use high-speed, current feedback op
amp. Designed to handle large capacitive loads, the OP-160
resists unstable operation. The OP-160 combines PMI's highspeed complementary bipolar process with a current feedback

FAST SETTLING (0.01%)

Av

REV. B

=-1, +10V STEP INPUT

PIN CONNECTIONS

Ves NULL

-IN

N.C•

• IN

N.C.
-IN

8-PIN EPOXY MINI-DIP
(P-Suffix)

V+

N.C.

N.C.

+IN

OUT

8-PIN CERDIP
(Z-Suffix)
8-PINSO
(S-Suffix)

20-CONTACT LCC
(RC-Suffix)

DRIVES CAPACITIVE LOADS

Av = +1, C L = 1000pF

OPERA T10NAL AMPLIFIERS 2-225

II

OP-160
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage ...................•............................................. ±18V
Input Voltage ....•......•..............................••..•..•.. Supply Voltage
Differential Input Voltage ................................................... ±1V
Inverting Input Current ....................••......•••. ±7mA Continuous
...............................................•...................... ±20mA Peak
Output Short-Circuit Duration ........................................ 10 sec
Operating Temperature Range
OP-160A (Z. RC) ....•.........••..........•......••••.. -55°C to + 125°C
OP-160A.F (Z) ............................................. -4O°C to +85°C
OP-160G (p.S) .•.•••..•....................•••.•••••••.•••• -40°Cto+85°C
Storage Temperature (Z. RC) ..........•.....••.•... -65°C to + 175°C
(P. S) ........••..•......••••..............•..••......•••...•... -65°Cto+150°C
Junction Temperature (Z. RC) .....•..•••••••.•••••• -65°C to + 175°C
(P. S) ............................•............•..••.••••..•..•. -65°Cto+150°C
Lead Temperature (Soldering. 10 sec) .•..••••..............•. +300°C

8 1A (Note 2)

PACKAGE TYPE

UNITS

8 1C

8-Pin Hermetic DIP (Z)

148

16

·CIW

8-Pin Plastic DIP (P)

103

43

·CIW

98

38

·CIW

158

43

·CIW

20-Contact LCC (RC)
8-Pln SO(S)

NOTES:
1. Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2. 8'A is specified for worst case mounting conditions, l.e., a'A is specified for

dkvice in socket for CerDIP, P·DIP, and LCC packages; 8~ is specified for
device soldered to printed circuit board for SO package.

ELECTRICAL CHARACTERISTICS at Vs = ±15V. V CM = OV. RF = 820Q, TA = +25°C, unless otherwise noted.
PARAMETER

SYMBOL

Input Offset
Voltaga

VIOS

Input Bias
Current
Input Bias Current
Common-Mode

lB.
Ie-.

CONDITIONS

MIN

OP-160AlF
TYP MAX

Noninverting Input

Inverting Input

MIN

OP-160G
TYP MAX

UNITS

5

mV

2

5

0.2
6

1
20

0.4
10

1,5
30

J1A

40
30

75
75

50
40

125
125

nAN

1
20

5
50

1,5
25

10
75

nAN

VCM = ±11V
Noninverting Input

Rejection Ratio

CMRRI B•
CMRRI B_

Input Bias Current
Power Supply
Rejection Ratio

PSRRI B•
PSRRI B_

Noninverting Input

CMR

VCM = ±11V

60

65

60

65

dB

Power Supply
R;jection

PSR

Vs =±9Vto±18V

74

80

74

80

dB

Open·Loop
Transimpedance

RT

RL = SOOO
Vo = ±10V

3

4

3

4

MO

Input Voltage
Range

IVR

(Note 1)

±11

±11

V

Output Voltage
Swing

Vo

RL = SOOO

±11

±11

V

Output Current

10

Vo = ±10V

±35

Supply Current

Isv

No LO,ad

Common-Mode

Rejection

Slew Rate

Inverting Input
Vs = ±9Vto±18V
Inverting Input

6.5

Av= +1. Vo =±10V,
RL = SOOO, Test at Vo = ±5V

All Grades

Av;" +2, VO =±10V,
RL '= 5000,TestatVo = ±5V

Op·160A
Op·160F
OP'160G

SR

2-226 OPERA TIONAL AMPLIFIERS

±35

+60/-45

8

6.5

1300

rnA

+60/-45

8

rnA

1300
VII'S

1000
800

1300
1300
800

1,300

REV. B

OP-160
ELECTRICAL CHARACTERISTICS at Vs =±15V, VCM = OV, RF = 8200, TA = +25°C, unless otherwise noted. Continued
OP-160G

OP-160A/F
PARAMETER
Rise Time

-3dB Bandwidth

SYMBOL

CONDITIONS

tR

Av=+1
Av=-I

BW

-3dB Point
RL =5oon

MIN
Vo=±IOOmV
Av=-I
AV=+I
Av=+2

TYP

MAX

MIN

TYP

MAX

UNITS

4
6.4

4
6.4

ns

55
90
65

55
90
65

MHz

125
75

125
75

ns

Settling Time

t.

Av=-I,IOVStep
0.01%
0.1%

Input Capacitance

CIN

Noninverting Input

4

4

pF

Input Resistance

RIN

Noninverting Input
Inverting Input

17
60

10
60

Mn
n

Voitage Noise
Density

e"

f

= 1kHz

5.5

5.5

Current Noise
Density

f
i

= 1kHz
Noninverting Input
Inverting Input

5
20

20

0.004

0.004

%

0.04

0.04

%

0.04

0.04

2.3

2.3

Total Harmonic

Distortion

"

THD

Differential Gain

Dilferential Phase
Disable Supply

IsVDrS
Current
NOTE:
1. Guaranteed by CMR test.

REV. B

f

= IkHz,A v = +1,
Vo = 2V RMS ' RL = soon

f

=3.58MHz

Av= +1, RL = 500n

f

=3.58MHz
Av= +1, RL = soon
DISABLE =OV
No Load

-

nV/y'Hz

pAlv'Hz

-

degrees

rnA

OPERA TIONAL AMPLIFIERS 2-227

OP-160
ELECTRICAL CHARACTERISTICS at Vs

=±15V, V CM = OV,

RF =

8200, -55°C ~ TA ~ +125°C, for the OP-160A, unless other-

wise noted.

OP-160A
PARAMETER

SYMBOL

Input Offset Voltage

V,OS

Average Input Offset
Voltage Drift

TC vos

CONDITIONS

MIN

TYP

MAX

UNITS

3

8

rnV

10

J!.VI'C

la+
la_

Noninverting Input
Inverting Input

Input Bias
Current CommonMode Rejection

CMRRl a+
CMRRl a_

VCM =±10V
Noninverting Input
Inverting Input

55
45

150
150

nAN

Input Bias
Current Power
Supply Reiection Ratio

PSRRl a+
PSRRl a_

Vs =±9VtO±18V
Noninverting Input
Inverting Input

2
40

10
100

nAN

Common-Mode
Rejection

CMR

VCM =±10V

56

60

dB

Power Supply
Rejection

PSR

Vs =±9VtO±18V

70

76

dB

Open-Loop
T ransimpedance

RT

RL =5000
Vo =±10V

1.75

3

MO

Input Voltage
Range

IVR

(Note 1)

±10

V

Output Voltage
Swing

Vo

RL =5000

±10

V

Supply Current

ISY

No Load

Input Bias CUrrent

0.35
12

2
30

J!.A

6.75

9

rnA

NOTE:
t. Guaranteed by CMR test.

2-228 OPERA TIONAL AMPLIFIERS

REV. B

OP-160
ELECTRICAL CHARACTERISTICS atVs =±15V VCM = OV, RF = 8200, -40·C $

TA $

+85·C, forthe OP-160F/G, unless

otherwise noted.

OP-160F
SYMBOL

Input Offset
Voltage

VIOS

Average Input
Offset Voltage

TCV os

Input Bias
Current

IB+
IB_

Noninverting Input
Inverting Input

0.3
10

30

0.5
15

3
40

CMRRI B+
CMRRI B_

VCM =±10V
Noninverting Input
Inverting Input

45
35

150
150

55
45

250
250

nAN

PSRRI B+
PSRRI B_

Vs =±9Vto±1aV
Noninverting Input
Inverting Input

1.5
30

10
100

2.5
3.5

20
150

nAN

Common· Mode
Rejection

CMR

VCM =±10V

56

62

56

62

dB

Power Supply
Rejection

PSR

Vs = ±9V to ±1aV

70

ao

70

ao

dB

Open·Loop
Transimpedance

RT

RL = soon
Vo =±10V

1.75

3

1.75

3

Mn

Input Voltage
Range

IVR

(Note 1l

±10

±10

V

Output Voltage
Swing

Vo

RL = soon

±10

±10

V

Supply Current
Current

ISY

No Load,
Both Amplifiers

Input Bias

Current Common·
Mode Rejection Ratio
Input Bias

Current Power
Supply Rejection Ratio

CONDITIONS

MIN

OP-160G

PARAMETER

TYP

MAX

2.75

a

MIN

10

6.75

9

TYP

MAX

UNITS

2.75

mV

10

I'V/'C

6.75

9

I'AI

mA

NOTE:
1. Guaranteed by CMR test.

REV. B

OPERA T10NAL AMPLIFIERS 2-229

OP-160
DICE CHARACTERISTICS

1.
2.
3.
4.
5.
6.
7.
8.

VosNULL
-IN
+IN
VVosNULL
OUT
V+
DISABLE

DIE SIZE 0.071 x 0.099 inch, 7,029 sq. mils
(1.80 x 2.52 mm, 4.54 sq. mm)

WAFER TEST LIMITS at Vs

= ±15V, VCM = OV, RF = 8200, TA = +25°C, unless otherwise noted.
OP-160GBC

PARAMETER

SYMBOL

UMITS

UNITS

5

mVMAX

Inverting Input

1.5
30

vA MAX

Mode Rejection Ratio

CMRRI B+
CMRRI B_

V CM =±llV
Noninverting Input
Inverting Input

125
125

nAN MAX

Input Bia.
Current Power
Supply Rejection Ratio

PSRRI B+
PSRRI B_

Vs a±9Vto±18V
Nonlnverting Input
Inverting Input

10
75

nAN MAX

CMR

VCM =±ltV

60

dBMIN

PSR

V s =±9Vto±18V

74

dBMIN

RT

RL =5000
Vo =±10V

3

Mil MIN

±11

VMIN

±11

VMIN

8

mAMAX

Input Ollset Voltage

V,OS

Input Bias Current

IB+
IB_

Input Bias

Current Common·

Common-Mode

Rejection
Power Supply
Rejection
Open-Loop
Transimpedance

CONDITIONS

Noninverting Input

Input Voltage Range

IVR

Output Voltage
Swing

Vo

RL =5000

Supply Current

ISY

No Load

NOTES:
1. Guaranteed by CMR test.
Electrical tests are perlormed at waler probe to the limits shown. Due to variations in assembly methods and normal yield loss. yield alter packaging is not guaranteed for
standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembfy and testing.

2-230 OPERATIONAL AMPLIFIERS

REV.B

OP-160
TYPICAL PERFORMANCE CHARACTERISTICS

SLEWRATEvs
NONINVERTING GAIN
2500

~

:;:

~

'" \.:,

1000

w

'"

RISING

~a:

,~

..J

TA=+25'C
RF= 820Q
VO=±10V
Vs=±15V

2000

1500

w

~

:;:

......:: r--

500

RISING

r- r -

r--+-.

1500

o

5

1

8

6

9

1000

I'.

o

...... r-Ioo.

r-

-5 -ti
GAIN

PHASE SHIFT vs FREQUENCY
Av=+1

-3dB BANDWIDTH vs
SUPPLY VOLTAGE
Av=+1

iii
w
w
a: -90
w -135

....U-

-190

'"w

-225

s:

:I:

e

~g/

Q.

-315
-360

....

80

~

75

~

..,
'?

TA =+25°C
RF= 8200
VS =±15V

I

iii
w
w
a:

"

~
t;:

-135

'"'"w«

-225

s:

:I:

Q.

r-RLI=5~0

-90 r -

60

100

2

filii_

1/

1S

..-

/

iii

:!:.

z
:;;:

=+25°C

TA

-360

RF = 8200
VS=±15V
10
FREQUENCY (MHz)

100

i"( -'\

-

-5

18

10
FREOUENCY (MHz)

1

-

-10

-

RL=5OO0
2000
500

I

0
-45

iii
w
w -so _RL=5000
2000
a:
500
w -135 !:

~
~ .......

:I:

'"w~

:I:
Q.

1

10
FREQUENCY (MHz)

100

..... IiiIIIII

-180
-225

~.

-270
-315
-360

11111

-15

100

PHASE SHIFT vs FREQUENCY
A v =+5

"
e.
....

z

:;;:
-5

RL=50Dn
2000-,\
500,

-1S

6
8
10 12 14 16
±SUPPLY VOLTAGE (VOLTS)

:!:.

-315

0

-10

iii

"

TA=+25°C
RF= 8200
VS=±1SV
NORMALIZED
TO OdS

10

III

2000
500

100

GAIN vs FREQUENCY
Av=+2

TA = +25°C
RF= 8200
Vs =±15V
NORMALIZED TO OdB

10

-270

10
FREQUENCY (MHz)

1

-9 -10

GAIN vs FREQUENCY
Av =+5

15

-180

REV. B

-B

I
I

PHASE SHIFT vs FREQUENCY
Av=+2

-45

-7

"

70
65

10
FREQUENCY (MHz)

11

-4

85

<>

CD
CD

0

-3

:I:

~ -270

:I:

-2

TA'=+2J,C
RF= 8200
RL=5oon

"N

RL=~~O~ 'i

f"

-10

95
90

-45

-

-15

-1

II 1111

•

500~

r--......

GAIN

0

III
Ilt=5l~
2oo0~

FALLING

500

10

TOOdB

5

...... i'..

~

'"

TA=+25'C
RF= 82Dn
Vs =±15V
NORMALIZED

10

r- A~

FALLlNG- I--

"e.

15

2500

TA =+25°C
RF = 8200
Vo=±10V
VS=±15V
RL=5000

2000

<:.

GAIN vs FREQUENCY
Av=+1

SLEWRATEvs
INVERTING GAIN

TA=+2S'C
RF= 8200
Vs =±1SV
10
FREQUENCY (MHz)

100

OPERA TIONAL AMPLIFIERS 2-231

OP-160
TYPICAL PERFORMANCE CHARACTERISTICS Continued

GAIN vs FREQUENCY
Av = +10

PHASE SHIFT vs FREQUENCY
Av=+10

T~=I+~d~1

TA = +25°C
R,= 820n
Vs =±15V
NORMALIZED TO OdS

5

iiJ
w

UJ

a:

~



n-

7A13

PLUG~N

7A13 PLUG-IN

lk1l
300pF
+15V

The test circuit, built on a ~opper clad circuit board, has a FET
input stage which maintains extremely low loading capacitance
at the artificial sum node. Preceding stages are complementary
emitter follower stages, providing adequate drive current for a
50n oscilloscope input. The OP-97 establishes biasing for the
input stage, and eliminates excessive offset voltage errors.
TRANSIENT OUTPUT IMPEDANCE
Settling characteristics of operational amplifiers also includes an
amplifier's ability to recover, i.e., settle, from a transient current
output load condition. An example of this includes an op amp
driving the input from a SAR type AID converter. Although the
comparison pOint of the converter is usually diode clamped, the
input swing of plus-and-minus a diode drop still gives rise to a
significant modulation of input current. If the closed-loop output
impedance is low enough and bandwidth of the amplifier is sufficiently large, the output will settle before the converter makes
a comparison decision which will prevent linearity errors or
missing codes.
Figure 12 shows a settling measurement circuit for evaluating
recovery from an output current transient. An output disturbing
current generator provides the transient change in output load
current of 1mA.Asseen in Figure 13, theOP-160 has extremely
fast recovery of BOns, (to 0.01 %), for a 1mA load transient. The
performance makes it an ideal amplifier for data acquisition
systems.

VRE ,

• NOTE: DECOUPLE CLOSE

TOGETHER ON GROUND PLANE
WJTH SHORT LEAD LENGTHS

FIGURE 12: Transient Output Impedance Test Fixture

2-240 OPERA TIONAL AMPLIFIERS

FIGURE 13: OP-160's Extremely Fast Recovery Time from a
1mA Load Transient to 1mV (0.01%)

REV. B

OP-160
+15V

.1.0I'F

O.1JLF~

RPOT : Hill TO 10kn

~=

;5,.:6::"-_-0 OUT

II

c::8_ _-o PISABLE

1kn

v2V

n

ov--.J

L

FIGURE 14: Input Offset Voltage Nulling
OFFSET VOLTAGE ADJUSTMENT
Offset voltage is adjusted with a 20kn potentiometer as shown
in Figure 14. The potentiometer should be connected between
pins 1 and 5 with its wiper connected to the V+ supply. The
typical trim range is ±40mV.
DISABLE AMPLIFIER SHUTDOWN
Pin 8 of the OP-160, DISABLE, is an amplifier shutdown control
input. The OP-160 operates normally when Pin 8 is left floating.
When greater than 1OOO~A is drawn from the DISABLE pin, the
OP-160 is disabled. To draw current from the DISABLE pin, an
open collector output logic gate or a discrete NPN transistor can
be used as shown in Figure 15. An internal resistor limits the
DISABLE current to around 500~A if the DISABLE pin is
grounded with the OP-160 powered by ±15V supplies. These
logic interface methods have the added advantage of level

-15V

FIGURE 16: DISABLE Turn-On/Turn-Off Test Circuit

shifting the TTL signal to whatever supply voltage is used to
power the OP-160.
In the DISABLE mode, the OP-160 maintains 40dB of input-tooutput isolation if the input signal remains below ±1.5V. Output
resistance is very high, over 100kQ, if the output is driven by
signals of less than ±1.5V. Higher signals will be distorted.
Figure 16 shows a test circuit for measuring the turn-on and
turn-off times for the OP-160. The OP-160 is in a gain of + 1 with
a + 1V DC input. As the input pulsetothe inverter rises its output
falls, drawing current from the DISABLE pin and disabling the

v+

2V

n

ov--.J

L

l'-_-Ir.

kn
o-.,,5I/o

v-

LOGIC GATE
WITH OPEN
COLLECTORIDRAIN

OUTPUT

v-

FIGURE 15: Simple circuits allow the OP-160 to be shut down.

REV. B

OPERATIONAL AMPLIFIERS 2-241

OP-160
+15V

a)
OUTPUT

11J.S.±1V

SQUARE WAVE
VOUT

yS'----......--OV,N
LOGIC INPUT

500
1kll

b)
OUTPUT

-15V

FIGURE 18: Overdrive Recovery Test Circuit
LOGIC INPUT

FIGURE 17: (a) OP-160 tum-on and tum-off performance. (b)
Expanded scale showing tum-on performance of the OP-160.
Be aware of the high-frequency spike during tum-on.
amplifier. The output voltage delay is shown in Figure 17 and
takes 200>1-s to reach ground. The turn-on time is much quicker
than the turn-off time. In this situation as the input to the inverter
falls its output rises, returning the OP-160 to normal operation.
The amplifier's output reaches its proper output voltage in
450ns.

OVERDRIVE RECOVERY
Figure 19 shows the overdrive recovery performance of the op160. Typical recovery time is 120ns from positive and negative
overdrive.

FIGURE 19: The OP-160 recovers from both positive and
negative overdrive in 120ns.

+15V

APPLICATIONS
NONINVERTING AMPLIFIER
The OP-160 can be used as a voltage-follower or noninverting
amplifier as shown in Figure 20. A currentfeedback amplifier in this
configuration yields the same transfer function as a voltage feedbackopamp:

VOOT = 1 + R:!

Y,N

R,

Remember to use a 820Q feedback resistor in voltage-follower
applications.
In non inverting applications, stray capacitance at the inverting input of a current feedback amplifier will cause peaking which will increase as the closed-loop gain decreases. The gain setting resistor, R, ' is in parallel with this stray capacitance creating a zero in the

-15V

FIGURE 20: The OP-160 as a voltage fol/oweror noninverting
amplifier.

2-242 OPERA TIONAL AMPLIFIERS

REV. B

OP-160
closed-loop response. For large non inverting gains, R, is small,
creating a very high-frequency open-loop pole which has limited effect on the closed-loop response. As the non inverting gain is decreased, R, becomes larger and the stray zero becomes lower in
frequency, having a much greater effect on the closed-loop response.
To reduce peaking at low noninverting gains, place a series resistor, Rc ' in series with the noninverting input as shown in Figure 20.
This resistor combines with the stray capacitance atthe noninverting
inputto form a low-pass fi~erthat will reduce the peaking. The value
of Rc should be determined experimentally in the actual PCB layout. Less peaking will occur in inverting gain configurations since
the inverting input is a virtual ground which forces a constant voltage across the stray capacitance.
A common practice to stabilize voltage feedback op amps is to use
a capacitor across the feedback resistance. This creates a zero in
the voltage feedback amplifier response to offset the loss of phase
margin due to a parasitic pole. In current feedback amplifiers, this
technique will cause the amplifier to become unstable because the
closed-loop bandwidth will increase beyond the stable operating
frequency.
INVERTING AMPLIFIER
The op- t 60 is also capable of operation as an inverting amplifier
(see Figure 21). The transfer function of this circuit is identical to
that using a voltage feedback op amp:

USING CURRENT FEEDBACK OP AMPS IN INTEGRATOR
APPLICATIONS
The small-signal model of a current feedback op amp shown
earlier in Figure 3 assumes a non-varying value of feedback
impedance. A non-varying feedback impedance ensures that
the bandwidth of the amplifier does not extend beyond its 1800
phase shift point and create unwanted oscillations. In integrator
circuits, the feedback element is a capacitor whose impedance
does vary with frequency. By definition then, integrator applications using current feedback amplifiers should be unstable.
However, a simple trick, shown in Figure 22, enables highspeed, wide bandwidth current feedback op amps to be used in
integrator applications.
Resistor RF is placed between an artificial sum node and the
inverting input of the amplifier. This resistor maintains a minimum value of feedback impedance over all frequencies. At high
signal frequencies, the integrator capacitor, C 1 , is a short cirCUit;
the feedback impedance is equal to RF only and the amplifier
has maximum bandwidth. At low frequencies, C 1 adds to the
overall feedback impedance. This lowers the amplifier's bandwidth but not enough to affect the integrator's performance.

Voor = _R2
VIN

Rl

100kll

R,

C,

1kll
+15V

vFIGURE 22: An Integrator Using a Current Feedback Op Amp

-15V

FIGURE 21: The OP-160 as an inverting amplifier.

REV. B

OPERA TlONAL AMPLIFIERS 2-243

2

OP-160
Figure 23 shows the gain and phase performance of the integrator. The integrator has the desired one-pole response for signal
frequencies
fc» 1/(21tR2C l ) '" 16kHz.
A more strenuous test of integrator performance is the pulse
response. Ideally, this should be a linear ramp. The current
feedback integrator's pulse response is exhibited in Figure 24.
The response closely approximates the ideal linear ramp.

i"'-.....

2

40

.....

30

b~,~
i'I

20
10

a;z
 ' ' - - - - - - -..................'''''OVOUT

FIGURE 23: Gain and phase response of the integrator shows
a one-pole response.

i

lOl'F

,
::;=cs
,
V-

FIGURE 26: A current feedback op amp configured for noninverting gain. Parasitic capacitances affecting gain are also
shown.
FIGURE 24: Pulse response of the current feedback integrator.

f=2MHz.
ACHIEVING FLAT GAIN RESPONSE WITH CURRENT FEEDBACKOPAMPS
In high-performance systems, flat gain response is often required. Current feedback op amps provide wide bandwidth performance but even these may not fulfill the gain flatness requirements of some systems.
Current feedback op amps exhibit both gain roll-off and peaking
as shown in Figure 25. Peaking is primarily due to parasitic

capacitance; gain roll-off is determined by the amount and type
of load on the amplifier. Peaking is controlled by careful layout
and circuit design; however, its cause can provide a method of
improving gain flatness over a desired frequency range.
Consider the noninverting amplifier of Figure 26. The gain
equals:

1+

R2
R,tIZ(CcIICg)

and at low frequencies
Av = 1 + ~ = 1 + 910n = 2

R1

2-244 OPERA TlONAL AMPLIFIERS

910n

REV. B

OP-160
At higher frequencies the gain increases or peaks due to the
effect of the parasitic capacitance, Cs ' on the gain equation. Any
capacitance at the inverting input will create a zero in the amplifier's response. This fact car] be used to compensate for gain
roll-off due to loading on the amplifier.
Begin by measuring or estimating the amplifier's -6dB point
(this is the frequency at which the output signal is half its original
amplitude). This can be easily determined from a network
analyzer plot of the amplifier's frequency performance. From
this the amount of capacitance, Cc ' which will double the gain
at the -6dB frequency and restore the original gain, can be
determined.

will be increased. At higher gains, gain flatness can be significantly improved without gain peaking. Figure 28 depicts the
OP-160 with Av = +10. In this example f-6dS ~ 22 MHz so,
C = 9pF +
S

1
21t(91 Q)22MHz

+

-::-~-,..-,-,-:-:c-.,-

21t(820Q)22MHz

= 97pF
The nearest standard capacitor value is 100pF.
Gain performance is flat to 0.5dB to 30M Hz and the amplifier's
-3dB point is 38MHz. This gives the amplifier an effective gainbandwidth of 380MHz! Compensating the OP-160 does not effect the pulse response as shown in Figure 29.

From the -6dB frequency, Cc can be calculated:

Cc = Cs +

+

1
21tR1 f-6dS

26

21tR2t6dS

for non inverting configuration, where C s is the combination of
the amplifier's input capacitance and the stray capacitance at
the input.
In the example shown,
Cs = 9pF = OP-160 input capacitance (4pF) + stray capacitance
(5pF)
1
+ _ _ _ _ __
C =9pF+
s
21t(910Q)32MHz
21t(910Q)32MHz

20

«


1000

"

o
'0

'00

II
Ok

FREQUENCY (Hz)

'0'

OPERA TIONAL AMPLIFIERS 2-255

OP-249
TYPICAL PERFORMANCE CHARACTERISTICS Continued

DISTORTION vs FREQUENCY

"'"~=~###F="'i='F=H

~.oo,~§_~Tll ~!

tOO

DISTORTION vs FREQUENCY

DISTORTION vs FREQUENCY

~v.:O:- :1~05Vv.·pC

l~ __ i_L.LL~.Ul.. __ ....i_..i-_i_U.J
:"J",:
..
L.L,: iW.''---..0-'-'-h''CT+t--t'---r'-j-'-;-' RL=10kQ i
_

',,'

i"

~.ool~§.~--Ljle~~ . __--,_,_~ll!
DISTORTION vs FREQUENCY

~"::+=i=+---:-=-:::
---~

i~i~~;:~

: : -:

l"i

Av;;10 2~

DISTORTION vs FREQUENCY

~-+::: :-=----r
.1 .•

l :;~it::l

i

-:-'"~~

:~--:

: , '! :::~:~I

I Ay=+10 I

1. 2.

.
. 1ll111~J
.,.

•,,,,V

Ii
~

-l11V

i.

~

9
BANDWIDTH (O.1H2 TO 10Hz)

Va .a15V

"'::!'~,.

Va. al5V

••
1\

..

~

1\
100k

1M

FREQUENCY (Hz)

2-256 OPERA TIONAL AMPLIFIERS

10M

AvcL=+10~

,.

-20

10k

AvcL·+' .......

~

-,. "TI';;,;'
UlIll~
1k

3D

I.

'ffi'lilil"

U

tl;~~1

Vs=""5V

l.;~~'2,~

3.

50

I~~I••~-hl

1111111I1

50

Ta.l: +25°C

CLOSED-LOOP
OUTPUT IMPEDANCE
vs FREQUENCY

CLOSED-LOOP GAIN
vs FREQUENCY

LOW FREQUENCY NOISE

100II

ili':r'--·'•• 1"-

.

•,

IIIILOO f'
1k

11*

[}
~
100k

'M

'.M

FREQUENCY Ig)

REV. A

OP-249
TYPICAL PERFORMANCE CHARACTERISTICS Continued

SMALL·SIGNAL OVERSHOOT
vs LOAD CAPACITANCE

MAXIMUM OUTPUT SWING
vs FREQUENCY

,

3D

~

25

~

20

I
!;

go

..
8

AL= 1Dku

......

l

15

1k

100k

10k

o

10M

1M

//

,

b

10

'\

i!

~

I

t-....

-Ii

-20

320

280

±5

..

........

±10

±15

200

-

180

5.4

I-"

~

~

~

~

~

~

TEMPERATURE lOCI

Vos DISTRIBUTION
(J PACKAGE)

Vos DISTRIBUTION
(PPACKAGE)
180

T;.+J.C I

J.C

TAI . .

=

150

Vs ±15V
350 x OP249
(700 OP AMPS)

-

1
!z

5.6

~

1l
~

~

5.4 f--~""'""""'~+-=....-----i

5.2 1---+---+---'--+----1

5.2_

±20

-

I--

SUPPLY VOLTAGE (YOLTS)

140

=

5.0 O~--.J....--..J,0'---,:':5-----:'2O

m

SUPPLY VOLTAGE (VOLTS)

TCVOS DISTRIBUTION
(J PACKAGE)

I

Vs =±15V

Vs ±15V
415 x OP249
(830 OP AMPS)

240 f-t-+--+--+--t---1i---t -4Q°C to +85°C

--

(700 OP AMPS)

210 ......

120

240

~

V

~

!';

........... ........
o

5.S f---+---+---+-----i

"

-10

10k

SUPPLY CURRENT vs
SUPPLY VOLTAGE

V'~±15VI

I1l 5.5

-15

1k

6.0,---,---,.---....,---,

g

..........

100

LOAD RES4STANCE un

5.S

./

~
III

500

NO lOAD

/

!l

3D0

200

SUPPLY CURRENT
vs TEMPERATURE

6.0

...

RL=2kn

~

400

LOAD CAPACITANCE (pFI

TA=+~

~ 10

'"
o~-~~~~~--~~~~

100

o

OUTPUT VOLTAGE SWING
vs SUPPLY VOLTAGE

15

)
A""J'+5

FREQUENCY (Hz)

20

I

._

20

o

+'Iom= I-Voml

NEGATIVE EDGE

40

~ 30

5

~

. / _I-/' ~=+1
POSI1TIVE EDGE

AVCL=+l

%

::!

~

:Ii

14 I-Vs =:±15V

70

" 10

;

TA' ;25.d

Vs
Rl=2kU
YIN = 100mvpl'

80

A VCL=+l

15

=±1~V

pIlTA.I+i5~
Vs =±15V

MAXIMUM OUTPUT VOLTAGE
vs LOAD RESISTANCE

I"-

--

150 f-+-+--+--+--t-f-t--t--+--+---i
~ 1~f-+-~~-+--t--r-t--t--r-+-i

J11 100

is

J11

80

r-

I=-

.01-+-+-~-+-+--1-+-+-~-+--1

120

50

80

40

so

1-+-+--l_:::::l,---I-+-+--+-++-1

40

20

3D

I-+-+--+---l-..!--.....
-+-+-+--l-H

o

o

-1 k -800 -600 -400 -200

0

200 400 600 800 1k

\Ios(.V)

REV. A

r-

-1 k --800 --600 -400 -200

0

200 400 600 800 1k

VosbN)

O~~~-L-L~~~~~
o .5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
(llyrC)

OPERA T10NAL AMPLIFIERS 2-257

OP-249
TYPICAL PERFORMANCE CHARACTERISTICS Continued

OFFSET VOLTAGE
WARM-UP DRIFT

TCVOS DISTRIBUTION
(PPACKAGE)
3DO

50

~;:".as.c-

210

Vs

INPUT BIAS CURRENT
VB TEMPERATURE
10k

.:l:1~Y

V. _:l:15V
Vcu-OV

(8300PAMPS)

240

r-

40

....~

210

"-

f-

~
g
Iii

it0

i-

.
so

i-

.... ....

r- f- fo

2

4

6

8

10 12 14 16 18

a

H

o

N

V

20

10

f-

30

30

i

1k

i
"

1DO

-~

10

~

/

V

o

1

(\lvre)

2

-'IL
~ I-"""

1

4

-75

-SO

-25

nilE AFTER POWER APPLIED IMINUTES)

BIAS CURRENT VB
COMMON-MODE VOLTAGE

BIAS CURRENT
WARM-UP DRIFT

.

10'

TA _+U-C
Vsu:1SV

25

50

tOO

12S

INPUT OFFSET CURRENT
VB TEMPERATURE

.

TA =+2S·C
Va _",15V

75

rC)

TEMPERATURE

v.

;.,SVI

VCM

=ov

40
10'

i
~.
"
I"

i

..
G
..;
~

1/

10'

30

10

10'
-15

-10

-6

10

o

15

1

20

t-

/

~
!i

10'

o

o

2

4

-75

10

-so

OPEN-LOOP GAIN
VB TEMPERATURE

..

12k
VI _:l:1!5V

...."\

FlL_2kO

k

TEMPERATURE

H

~

so
rc)

TEMPERATURE

2-258 OPERA TIONAL AMPLIFIERS

100

18

r-cJ

v. :"svi

.,NK ......

~ !=::::::

--

0

k

~

V
75

&E

AL=1OkO

.......

0

21

SHORT-CIRCUIT
OUTPUT CURRENT
VB JUNCTION TEMPERATURE

10k

~

-25

TIME AFTER POWER APPUED (MINUTES)

COMMON-MODE VOLTAQE (VOLTS)

1',...

V
50

V

~

~

m

0~

_

_

0

H

so

TEMPERATURE

n

r-

_

m

rC)

REV. A

OP-249
SIMPLIFIED SCHEMATIC (1/2 OP-249)
r-----------~~--~----~---o~

-IN

~--_+--+_------~~--+_----~--_o~

BURN-IN CIRCUIT

+3Yo-----=_!

a)
5110

OP-249

+18V

+3Yo-----=_!
SIc"
-18V

b)
LT10S7

APPLICATIONS INFORMATION
The OP-249 represents a reliable JFET amplifier design, featuring an excellent combination of DC precision and high speed. A
rugged output stage provides the ability to drive a 600a load and
still maintain a clean AC response. The OP-249features a largesignal response that is more linear and symmetric than previously available JFET input amplifiers - compare the OP-249's
large-signal reponse, as illustrated in Figure 1, to other industry
standard dual JFET amplifiers.
Typically, JFET amplifier's slewing performance is simply specified as just a number of volts/f.ls. There is no discussion on the
quality, i.e., linearity, symmetry, etc. of the slewing response.

REV. A

FIGURE 1: Large-Signal Transient Response. Av =+1.
V,N=20Vp.p'ZL =2/(g11200pF. Vs=:!:15V

OPERA TIONAL AMPLIFIERS 2-259

OP-249
The OP-249 was carefully designed to provide symmetrically
matched slew characteristics in both the negative and positive
directions, even when driving a large output load.
An amplifier's slewing limitation determines the maximum frequency at which a sinusoidal output can be obtained without
significant distortion. It is, however, important to note that the
nonsymmetric slewing typical of previously available JFET amplifiers adds a higher series of harmonic energy content to the
resulting response - and an additional DC output component.
Examples of potential problems of nonsymmetric slewing behaviour could be in audio amplifier applications, where a natural, low-distortion sound quality is desired, and in servo or signal
processing systems where a net DC offset cannot be tolerated.
The linear and symmetric slewing feature of the OP-249 makes
it an ideai choice for applications that will exceed the full-powerbandwidth range of the amplifier.

VERTICAL so"V/D1V
INPUT VARIATION

HORIZONTAL 5V/DIV
OUTPUT CHANGE

FIGURE 3: Open-Loop Gain Linearity. Variation in Open-Loop
Gain Results in Errors in High Closed-Loop Gain Circuits.
RL =6000, Vs =%15V

+v

RJ Y'N
50kQl

200""

-v

FIGURE 2: Small-Signal Transient Response, Av
ZL =2kOIl100pF; No Compensation, Vs %15V

=

=+ 1,

+V

'f

501d>

Supply decoupling should be used to overcome inductance and
resistance associated with supply lines to the amplifier. A 0.11'F
and a 1OI'F capacitor should be placed between each supply pin
and ground.

OFFSET VOLTAGE ADJUSTMENT
The inherent low offset voltage of the OP-249 will make offset
adjustments unnecessary in most applications. However,
where a lower offset error is required, balancing can be performed with simple external circuitry, as illustrated in Figures 4
and 5.

2-260 OPERA T10NAL AMPLIFIERS

=.V (~)
,

FIGURE 4: Offset Adjust for Inverting Amplifier Configuration

As with most JFET-input amplifiers, the output of the OP-249
may undergo phase inversion if either input exceeds the specified input voltage range. Phase inversion will not damage the
amplifier, nor will it cause an internal latch-up condition.

OPEN-LOOP GAIN LINEARITY
The OP-249 has both an extremely high open-loop gain of
1 kV/mV minimum and constant gain linearity. This feature ofthe
OP-249 enhances its DC precision, and provides superb accuracy in high closed-loop gain applications. Figure 3 illustrates
the typical open-loop gain linearity - high gain accuracy is assured, even when driving a 6000 load.

Vos ADJUST RANGE

R,
2001<11

-v

Y'N
FIGURE 5: Offset Adjust for Noninverting Amplifier
Configuration
In Figure 4, the offset adjustment is made by supplying a small
voltage at the noninverting input of the amplifier. Resistors Rl
and R2 attenuates the pot voltage, providing a %2.5mV (with V s
%15V) adjustment range, referred to the input. Figure 5 illustrates offset adjust for the noninverting amplifier configuration,
also providing a %2.5mV adjustment range. As indicated in the
equations in Figure 5, if R4 is not much greater than R2, there will
be a resulting closed-loop gain error that must be accounted for.

=

REV. A

OP-249
Settling time is the time between when the input signal begins to
change and when the output permanently enters a prescribed
error band. The error bands on the output are 5mV and 0.5mV,
respectively, for 0.1 % and .0.01 % accuracy.

Unity-gain stability, a low offset voltage of 300I-lV typical, and a
fast settling time of S70ns to 0.01 %, makes the OP-249 an ideal
amplifier for fast digital-to-analog converters.
For CMOS DAC applications, the low offset voltage of the OP249 results in excellent linearity performance. CMOS DACs, such
as the PM-7545, will typically have a code-dependent output
resistance variation between 11 kO and 33kO. The change in
output resistance, in conjunction with the 11 kO feedback resistor,
will result in a noise gain change. This causes variations in the
offset error, increasing linearity errors. The OP-249 features low
offset voltage error, minimizing this effect and maintaining 12bit linearity performance over the full scale range olthe converter.

Figure 6 illustrates the OP-249's typical settling time of S70ns.
Moreover, problems in settling response, such as thermal tails
and long-term ringing are nonexistent.

DAC OUTPUT AMPLIFIER

Since the DAC's output capacitance appears at the operational
amplifiers inputs, it is essential that the amplifier is adequately
compensated. Compensation will increase the phase margin, and
ensure an optimal overall settling response. The required lead
compensation is achieved with capacitor C in Figure 7.

FIGURE 6: Settling Characteristics of the OP-249 to 0.01%.

a) UNIPOLAR OPERATION
75U

REFERENCE

OR VIN CHI,"""",IV'-'''l

DATA INPUT

b) BIPOLAR OPERATION

REFERENCE

OR YlNo- I I

\

RF=2.5kn
RL=5000
Ys=:t15V

\.%

••

FREQUENCY (11Hz)

Vs·:t15V

0.1%

I-TA=25"C

T..,=25OC

NORMAUZED TO DdB

\
I

~

~ IIfz::

I

••

'00

..

-

100

-

.%

-.5

J

V
160

FREQUENCY (MHz)

190

220

250

280

310

340

SETTUNG TIME (ns)

PHASE vs FREQUENCY
Av=-10

II Iii
Lilli

••

\

\
.%\
\

,'

"F=~-

RL=5OOn

Vs=:t1SY

T,,=2fiOC

••

.00

..

FREQUENCY (MHz)

2-272 OPERA TIONAL AMPLIFIERS

-

100

II
130

160

••

'00

1.

Va =:t15V
~TA.25-C

RL= 5.1kn

5011<1,

NORMALIZED TO OdB

,

\

I
RLa2Mfr.
.~

..

10.1%

lson(

-

II
190 220 250 280
seTTUNG nilE (ns'

..........;;~

...

I

.%/

Y

"

111111

\0.1%

I

-8

\

FREQUENCY (MHz)

RF =2.5kO

1\

J

-3.5

:iJ'

GAIN vs FREQUENCY
Av=+1

.5

"L= son"!'Ii

TA=25"C

.... •

SETTLING TIME
vs OUTPUT STEP
Av=-10

.......... ...... ~L~J.iJ,1

RF= 2.5kn
Vs·:t15V

II

0.1"'-

I
1/
130

"L=.=~ ~~

..

\

I

-6

••

.... •

SETTLING TIME vs OUTPUT STEP
Av=-1

-6

......

:tIO

SUPPLY VOLTAGE (VOLTS)

\

-3'5

....

..

-

:t5

~~

"L" .~~ ~~
son-"

-.35

...
-'s

••

.00

GAil (ABSOLUTE)

-45

~

;I

!

'00

200

'"

/

200

i'

/

AL-SOOO

f4

/

~L=soon

"

Ii;

",.

AV= +10
TAlI2rC
Your =MAX SWING

BOO

Vs =:t1SY

.

GAIN vs FREQUENCY
Av=-1

SLEWRATEvs
SUPPLY VOLTAGE

SLEW RATE vs GAIN

310

340

-.5

•

••

.00

FREQUENCY (MHz)

REV.C

OP-260
TYPICAL ELECTRICAL CHARACTERISTICS Continued
SMALL-SIGNAL
-3dB BANDWIDTH
vs SUPPLY VOLTAGE

Av

.... -~~=.j""
50

=25"C

~

I

/

b

20

,.

/

~30

!

15

./

!,35

25

15

,.

I

1-_t--+-t-+l+H RL = son

Ii:

f---+-+-HttHt---+-++t+Mti

-80

-180

1

100

PHASE SHIFT vs FREQUENCY

GAIN vs FREQUENCY

PHASE SHIFT vs FREQUENCY

Av=+2

Av=+5

Av=+5

15

,.

T" = 2S-C

~

-225

,.

11111'""

-15

100

l:/

FREQUENCY (MHz)

.......... ~t--

,-90
iii

"L=l00n J

~~

FREQUENCY (MHz)

Ys=:t:15V

-180

j"':::
-5

-1.

1.

•

t=~lL
2OOn-~

TA=25"C

:t2:t:4 :t6 :t8 :t10 :t12 :t14 :t;16 :t18 :1;20
SUPPLY VOLTAGE (VOLTS)

~F"~.~

Ii:

NORMALIZED TO Gel

VS=:t1SV -+-+++++I--t-+-t-+-t+lfII

-360

-135

II

Vs =±15Y
f-TA=2&'C

soon

~ -225 1--+-+-I-+++IIl+--+-+-+-f+-h1II
~ ~.I--+-+-~++~--+--++++~

/

RF =2.51I:U

5~4V.4-1~rHl

~ -135

RF= 2.5kn

•o

I

Av= +2

Av= +1
~

RL =50U
_ TA

~

GAIN vs FREQUENCY

PHASE SHIFT vs FREQUENCY

=+1

~F~i.JJ

Rp=2.5tl:D
Vs =:t15Y
f- TA =25-C
NORMALIZED TO OdB

~

:'1:\

-315

Ii:
:;:

'"

1-270
..

-5

............: 1""'1"-

-1.

"L=l"""·=:

1

100

1.

son J

-180

:: -225

i-270

'r\

-15

....,

"L= 5.1""---<::

~ -135

"L=5.1"",

iD

~

-315

lsonl

~~II

-360

,.

100

FREQUENCY (MHz)

FREQUENCY (MHz)

PHASE SHIFT vs FREQUENCY

Av= +10

Av= +10

Vs =:t15V

GAIN vs FREQUENCY

,.

~F'=J..l.i

I I I I

Av= +50
"F='~5.ri

~

Itit

-135

Ii:

-180

:

-225

e.

;;:

..~

-90

r:::s ~
RL= S.lka

~~

=

TA_H-C

~~

-

NORMAUZED TO OdB

~

iD

rs

~
Z

'i

-5

'"

RLI: 5.1kO

-15 -

FREQUENCY (MHz)

REV.C

,.
FREQUENCY (MHz)

-20
100

f-

5OO---OV

OUT

(b)

(a)

FIGURE 7: Simplified noise models for the OP-260 in noninverting (a) and inverting (b) gain.
where:
EN =
en =
inn =
in;
=
Rs
AVCL =

=

total input referred noise
amplifier voltage noise
noninverting input current noise
inverting input current noise
source resistance
closed loop gain = 1 + R/Rl

For the inverting amplifier, the equivalent input voltage noise,
referred to the input, is:
en2 (1 + IAVLCI)2+ (R2 in;)2
IAvLCI
(l AVLCIl 2
assuming Rs « R1· AvCL = closed loop gain = -R 2/R 1 ·
En =

Typical values @ 1 kHz for the noise parameters of the OP-260
are:
en = 5.0nV/VHZ
inn
3.0pAlYHZ
in;
20.0pAlYHZ
SHORT CIRCUIT PERFORMANCE
To avoid sacrificing bandwidth and slew rate performance the
OP-260's output is not short circuit protected. Do not short the
amplifier's output to ground or to the supplies. Also, the buffer
output current should not exceed a value of ±20mA peak or
±7mA continuous.
POWER SUPPLY BYPASSING AND LAYOUT
CONSIDERATIONS
Proper power supply bypassing is critical in all high-frequency
circuit applications. For stable operation of the OP-260, the
power supplies must maintain a low impedance-to-ground over
an extremely wide bandwidth. This is most critical when driving
a low resistance or large capacitance, since the current required
to drive the load comes from the power supplies. A 10llF and

REV.C

O.1IlF bypass capacitor are recommended for each supply, as
shown in Figure 8, and will provide adequate high-frequency
bypassing in most applications. The bypass capacitors should
be placed at the supply pins of the OP-260. As with all high frequency amplifiers, circuit layout is a critical factor in obtaining
optimum performance from the OP-260. Proper high frequency
layout reduces unwanted signal coupling in the circuit. When
breadboarding a high frequency circuit, use direct point-to-point
wiring, keeping all lead lengths as short as possible. Do not use
wire-wrap boards or "plug-in" prototyping boards.
During PC board layout, keep all lead lengths and traces as
short as possible to minimize inductance. The feedback and
gain-setting resistors should be as close as possible to the inverting input to reduce stray capacitance at that point. To further reduce stray capacitance, remove the ground plane from
the area around the inputs olthe OP-260. Elsewhere, the use of
a solid unbroken ground plane will insure a good high-frequency
ground.

v.

v-

FIGURE 8: Proper power supplying bypassing is required to
obtain optimum performance with the OP-260.

OPERA TlONALAMPLIFIERS 2-279

OP-260
APPLICATIONS
NONINVERTING AMPLIFIER
The OP-260 can be used as a voltage-follower or non inverting
amplifier as shown in Figure 9. A current feedback amplifier in this
configuration yields the same transfer function as a voltage feedbackopamp:

Vour =1 +A2.
VIN

R1

Remember to use a 2.51<0 feedback resistor in voltage-follower
application.
In non inverting applications, stray capacitance at the inverting input of a current feedback amplifier will cause peaking which will increase as the closed-loop gain decreases. The gain setting resis.15V

tor, R, ' is in parallel with this stray capaqitance creating a zero in the
closed-loop response. For large noninverting gains, R, is small,
creating a very high frequency open-loop pole which has limited effeet on the closed-loop response. As the noninverting gain is decreased, R, becomes larger and the stray zero becomes lower in
frequency, having a much greatereffectontheclosed-loopresponse.
To reduce peaking at low noninverting gains, place a series resistor, Re, in series with the noninverting input as shown in Figure 9.
This resistor combines with the stray capacitance atthe noninverting
inputto form a low-pass filter that will reduce the peaking. The value
of Re should be determined experimentally in the actual PCB layout. Less peaking will occur in inverting gain configurations since
the inverting input is a virtual ground which forces a constant voltage across the stray capacitance.
A common practice to stabilize voltage feedback op amps is to use
a capacitor across the feedback resistance. This creates a zero in
the voltage feedback amplifier response to offset the loss of phase
margin due to a parasitic pole. In current feedback amplifiers, this
technique will cause the amplifier to become unstable because the
closed-loop bandwidth will increase beyond the stable operating
frequency. For the same reason, current feedback amplifiers will
not be stable in integrator applications.
INVERTING AMPLIFIER
The OP-260 is also capable of operation as an inverting amplifier
(see Figure 10). The transfer function of this circuit is identical to
that using a voltage feedback op amp:

• SEE TEXT

Vour __ A2
VIN -

~.

An optional offset voltage trim is shown in Figure 11.
VOUT
. 1 .R:z
YIN
R,
-15V

FIGURE 9: The OP-260 as a voltage follower or noninverting
amplifier.

AUTOMATIC GAIN CONTROL AMPLIFIER
One of the shortcomings of using voltage feedback op amps in an
Automatic-Gain-Controlamplifieristhatitsbandwidthdropsoffrapidly
as gain increases,limiting the useful bandwidth. However, for currentieedbackamplifiers, bandwidth is relatively independent of gain,

.15V

V.. o--wV-_~

-15V

FIGURE 10: The OP-260 as an inverting amplifier.

2-280 OPERATIONALAMPLIFIERS

-'5V
FIGURE 11: Optional offset voltage trim circuit for the OP-260.

REV.C

OP-260

lOOkz
3

MIL
XND
XND
XND
XND

For devices processed in total compliance to MIL-STD-883. add 1883 after part
number. Consult factory for 883 data sheet.
Burn~in is available on commercial and industrial temperature range parts in
CerDIP. plastic DIP. and TO-can packages.
It For availability and burn-in information on SO and PLCC packages, contact
your local sales office.

N.C.
17

GENERAL DESCRIPTION

OUTB

N.C.

t

The OP-271 is a unity-gain stable monolithic dual op amp featur·
ing excellent speed, 8.5V/IlS typical, and fast settling time, 21ls
typical to O. 01 %. The OP-271 hasa gain-bandwidth of 5MHz with
a high phase margin of 62°.

+INA
N.C.

LCC
(RC-Suffix)

+IN B
-INB

16-PINSOL
(S-Suffix)

EPOXY MINI-DIP
(P-Suffix)
8-PIN HERMETIC DIP
(Z-Suffix)

SIMPLIFIED SCHEMATIC (One of the two amplifiers is shown.)
r-~------~------.-----~--~--------------------------.---~----~--ov+

OUT

-INo--.....t-..,.....

L-----------------~--~--------~--------~~--~--4-~--~-o~

REV. B

OPERA TIONAL AMPLIFIERS 2-287

OP-271
The OP~271 offers outstanding DC and AC matching between
channels. This is especially valuable for applications such as
multiple gain blocks, high-speed instrumentation and amplifiers, buffers and active filters.

Lead Temperature (Soldering, 60 sec) ........................ +300°C
Junction Temperature (Tj ) .............................. -65°C to + 150C
Operating Temperature Range
OP-271 A ................................................... -55°C to + 125°C
OP-271 E, OP-271 F, OP-271G ................... -40°C to +85°C

The OP-271 conforms to the industry standard 8-pin dual op
amp pinout. It is pin compatible with the TL072, TL082,
LF412, and 1458/1558 dual op amps and can be used to
significantly improve systems using these devices.

PACKAGE TYPE

For applications requiring lower voltage noise, see the OP270. For a quad version of the OP-271, see the OP-471.

PARAMETER
Input Offset
Voltage

SYMBOL

CONDITIONS

'CIW

8-Pin Plastic DIP (P)

96

37

'CIW

20-Contact LCC (RC)

88

33

'CIW

8-PinSO(S)

92

27

'CIW

=±15V. TA =+25°C. unless otherwise noted.
MIN

OP-271A/E
TYP
MAX
75

Vas

Input Offset
Current

los

VCM =OV

Input Bias
Current

I.

VCM=OV

4

Inpul Noise
Voltage
Density

en

fa = 1kHz

7.6

Large-Signal
Voltage
Gain

Ayo

Input Voltage
Range

IVR

Output Voltage
Swing
Common·Mode
Rejection
Power Supply
Rejection
Ratio
Slew Rate

SR

Phase Margin

om

Ay=+1

62

Supply Current
(All Amplifiers)

ISY

No Load

4.5

Gain Bandwidth
Product

GBW

Channel
Separalion

UNITS

12

NOTES:
1. Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2. The OP-271 's inputs are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low noise performance. If differential
voltage exceeds ±1.0V, the input current should be limited to ±2SmA.
3. a' A is specified for worst case mounting conditions, i.e., a' A is specified for
d~vice in socket for CerDIP, P-DIP, and LCC packages; alA is specified for
device soldered to printed circuit board for SOL package. I

ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage ................................................................. ±18V
Differential Input Voltage (Note 2) ................................... ±1.0V
Differential Input Current (Note 2) ................................. ±25mA
Input Voltage .................................................... Supply Voltage
Output Short-Circuit Duration ................................ Continuous
Storage Temperature Range ........................ -65°C to + 150°C
ELECTRICAL CHARACTERISTICS at Vs

ale

134

alA (Note 3)

8-Pin Hermetic DIP (2)

MIN

OP-271F
TYP
MAX

MIN

OP-271G
TYP
MAX

UNITS

200

150

300

200

400

"'v

10

4

15

7

20

nA

20

6

40

12

60

nA

7.6

-

nVI Hz

7.6

Vo =,,10V
400
300

650
500

300
200

500
300

250
175

400

(Note 1)

,,12

,,12.5

,,12

,,12.5

,.12

,.12.5

V

Va

RL ~2kO

,,12

,,13

,,12

,,13

,.12

,.13

v

CMR

VCM =,.12V

106

120

100

115

90

105

dB

PSRR

V s =,.4.5VtO,.18V

CS

RL = 10kll
RL = 2kO

0.6
5.5

3.2

8.5

1.8
5.5

4.5

5
Va = 20V•••
= 10Hz (Note 2)

'a

125

175

8.5

5.5

62
6.5

125

2.4

5.6

V/mV

250

7.0

8.5
deg

62
6.5

",VN

4.5

6.5

mA

5

5

MHz

175

175

dB

Input CapaCitance C'N

3

3

3

pF

In6~~::~i~~~.~~de R'N

0.4

0.4

0.4

Mil

20

20

20

GO

2

2

2

"'s

Input Resistance
Common· Mode
Settling Time

R 1NCM

ts

Ay = +I,10V Step
to 0.01%

NOTES:
1. Guaranteed by CMR test.
2. Guaranteed but not 100% tested.

2-288 OPERA TIONAL AMPLIFIERS

REV. B

OP-271
ELECTRICAL CHARACTERISTICS at Vs = ±15V, -55·C:5 TA :5125·C for OP-271A, unless otherwise noted.
OP-271A
CONDITIONS

MIN

PARAMETER

SYMBOL

TYP

MAX

Input Offset Voltage

Vos

115

400

TCVos

0.4

Average Input
Offset Voltage Drift

UNITS
pV
pVloC

Input Offset Current

los

VCM = OV

1.5

30

nA

Input Bias Current

18

VCM = OV

7

60

nA

Large-Signal
Voltage Gain

Avo

Vo= ±10V
RL = 10kn
RL = 2kn

300
200

600
500

VlmV

Input Voltage Range

IVR

(Note 1)

±12

±12.5

V

Output Voltage Swing

Vo

RL ", 2kn

±12

±13

V

Common-Mode
Rejection

CMR

VCM =±12V

100

120

dB

Power Supply
Rejection Ratio

PSRR

Vs = ±4.5V to ±18V

1.0

5.6

pV/v

Supply Current
(All Amplifiers)

ISY

No Load

5.3

7.5

rnA

NOTE:
1. Guaranteed by CMR test.

ELECTRICAL CHARACTERISTICS at Vs

=

±15V, -40·C" T A" +85·C, unless otherwise noted.
OP·271F

OP·271AJE

PARAMETER

SYMBOL

InputOffsel
Voltage
Average Input
Offsel Voltage
Drift
Input Offset
Current

los

VCM = OV

CONDITIONS

MIN

TYP

MAX

Vos

100

330

TCVos

0.4

2

Input Bias

OP·271G

TYP

MAX

215

MIN

TYP

MAX

UNITS

560

300

700

JlV

4

2.0

5

JlVrC

30

5

40

15

50

nA

60

10

70

15

80

nA

18

V CM = OV

Large-Signal
Voltage
Gain

Avo

Vo =,,10V
RL = 10kD
RL = 2kD

300
200

600
500

200
100

500
400

150
90

400
300

V/mV

Input Voltage
Range

IVR

(Note 1)

,,12

,,12.5

,,12

,,12.5

,,12

,,12.5

V

Output Vollage
Swing

Vo

RL ~2kD

,,12

,,13

,,12

,,13

,,12

,,13

V

Common·Mode
Rejection

CMR

VCM = ,,12V

100

120

94

115

90

100

dB

PSRR

Vs =:4.5Vto,,18V

0.7

5.6

51.8

10

2.0

15

JlV/V

ISY

No Load

5.2

7.2

5.2

7.2

5.2

7.2

rnA

Current

Power Supply
Rejection

6

MIN

Ratio

Supply Current
(All Amplifiers)

NOTE:
1. Guaranteed by CMR test.

REV. B

OPERA TIONALAMPLIFIERS 2-289

II

OP-271
DICE CHARACTERISTICS

1.
2.
3.
4.

OUT A
-INA
+INA

V5. +IN B
6. -IN B
7.0UTB

8. V+

DIE SIZE 0.094 X 0.092 inch, 8,648 sq. mils
(2.39 X 2.34 mm, 5.60 sq. mm)

For additional DICE ordering information,
refer to PMl's Data Book, Section 2.

WAFER TEST LIMITS at Vs = ±15V, TA = 25°C, unless otherwise noted.
OP-271GBC
PARAMETER

SYMBOL

Input Offset Voltage

Vas

CONDITIONS

LIMIT

UNITS

300

~VMAX

Input Offset Current

los

VCM = OV

15

nAMAX

Input Bias Current

18

VCM = OV

40

nAMAX

Ava

Vo= ±IOV
RL = 10k!!
RL = 2k!!

300
200

VlmV MIN

VMIN

Large-Signal
Voltage Gain
Input Voltage Range

IVR

(Note I)

±12

Output Voltage Swing

Va

RL

±12

VMIN

Common-Mode Rejection

CMR

VCM= ±12V

100

dBMIN

Power Supply
Rejection Ratio

PSRR

Vs = ±4.5V to ±18V

5.6

Supply Current
(All Amplifiers)

ISY

No Load

6.5

::::

2kCl

~VIV

MAX

mAMAX

NOTES:
I. Guaranteed by CMR test.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

2-290 OPERA TIONALAMPLIFIERS

REV. B

OP-271
TYPICAL PERFORMANCE CHARACTERISTICS

.,

VOLTAGE NOISE DENSITY
vs FREQUENCY
100

Iit:;

T,,-25°C
Ys +1SV

~

40

~ 30

t
~

"

~
~

'"

w

'~"

TOTAL HARMONIC DISTORTION
vs FREQUENCY
D.1

,.0

.0
AT 10Hz

0
z

~

j!

AT 1kHz

0

Ay11

>-

,

±,

0

FREQUENCY (Hz)

±20

±15

±10

CURRENT NOISE DENSITY
vs FREQUENCY

100

INPUT OFFSET VOLTAGE
vs TEMPERATURE

TA:: 25°C
YS - ±15V

WARM-UP OFFSET
VOLTAGE DRIFT
10
TA=~·C

Vs" ±15V

~'"
0

~

>

>w

~
>-

..
::I

1/t CORNER - 40Hz

.3 B
w

BD
BD

I I I II
100

1k

'0

-'0-75

10.

./

40

!!

I IIIII I II

Vs"" ±15V

;;-

100

~
w

10k

1k

FREQUENCY (Hz)

120

10

I

D.DD1
10

SUPPLY VOLTAGE (VOLTS)

10

0.1

Ay-10

":c

w
'" 10

,.

II

D.D1

,.,."Z

>

100

I

Q
u

0

10

Ay= 100

Iii

~

1

Yo=10Vp-p
RL -2kO

z
0
;::

~ 15
w
on

g •

Va - :!::15V

!

z

1/f CORNER - 40Hz

r ... -25°C

TA ""25°C

>
>iii

20

10

VOLTAGE NOISE DENSITY
vs SUPPLY VOLTAGE

"",

~

'"

g

7

6

>-

/

/
-SO

V

!/

~

5

o

4

~

3

~

!!

I

~

I

u

-25

FREQUENCY (Hz)

25

50

75

100

o

125

/

o

TEMPERATURE (Oe)

INPUT BIAS CURRENT
vs TEMPERATURE

TIME (MINUTES)

INPUT BIAS CURRENT vs
COMMON-MODE VOLTAGE

INPUT OFFSET CURRENT
vs TEMPERATURE

10
TA = 25°C
Vs == ±15V

Va"'" ±15V
VCM""OY

./

/

V

l/

...-

-75

i,.

2

So

/

_6

1
>-

I--.

z

,.ill

::I
U

i

U

on

-1

~

>- -.

!;

!

-

~

,

::I

o

~

-3

4

3

-4

-50

-25

25

50

T~MPERATURE

REV.B

3

,.

V
-.

C

(Oel

75

100

125

-,-75

-SO

-25

0

25

50

TEMPERATURE (a e)

75

100

125

•

/

V

~ I-"'"

-12.5 -10 -7.5 -5 -2.5

0

2.5

5

7.5

10 12.5

COMMON-MODE VOLTAGE (VOLTS)

OPERATIONALAMPLIFIERS 2-291

OP-271
TYPICAL PERFORMANCE CHARACTERISTICS Continued

TOTAL SUPPLY CURRENT
YS SUPPLY VOLTAGE

CMR ys FREQUENCY
130

III

120
110
100

Vs= ±15V

c

! 61---+---+---+------1

.ffi

90

!..

~
~

80

..

70

U

51---+-----,'"""_::.-

~...

60
50

30

VSI71I~1SV

10
1

100

10

1k

10k

100k

3~--~--~--~--~
±s
±10
±1S
o
±20

1M

FREQUENCY (Hz)

,,

100

l!.

"""
"I'-"I'"I'-"

80

~ 60
40

".

I'\. -PSR

+PSR

l!.

80

0

~

60

0

40

~

"

20

o

1

10

100

1k

10k

""

m100
z
C

100k

1M

o

1

10

OPEN-LOOP GAIN, PHASE SHIFT
YS FREQUENCY

"

15

l!.

z
~

~AIN

10

........

:!;

9

..:!;

z
C

""

100

1k

.."
..9

"
10k

~

""

100k

""

1M

5

Z

0

-5

--

""-

~i'

o

PHASE MARGIN
=620

"

140

t

~

.

160 ~

.......

l:

180 ~

1' ....

>'

~

60

1

4

5

6

7 8 910

FREQUENCY (MHz)

2-292 OPERA TIONAL AMPLIFIERS

_

1500

100k

1M

10M

f::Y.~ ±15~

70

~

GSW-

e.z

z

C;

~

ill
500

o

-10

10k

GAIN-BANDWIDTH PRODUCT,
PHASE MARGIN YS TEMPERATURE

C
~ 1000

~

.....
l-

FREQUENCY (Hz)

TA "" 25°C
RL"" 10kn

~

.....
20

1.

OPEN-LOOP GAIN
SUPPLY VOLTAGE

120 _

.....

-20 I -

10M 100M

YS

100

.Jo't'

40

0

Q

2000

~PHASE

125

Vs =±15V

l!.

FREQUENCY (Hz)

TA""25°C
Vs "" ±15V

100

T. =

iI

FREQUENCY (Hz)

25

75

60

20

10M 100M

50

TA := 2S<>C
VS"" ±15V

-.

120

I\.. I\..

25

80

TA - 25°C

I\.. I\..

-25

CLOSED-LOOP GAIN
YS FREQUENCY

140

120

-50

TEMPERATURE (DC)

OPEN-LOOP GAIN
YS FREQUENCY

PSR YS FREQUENCY

~

3
-75

SUPPLY VOLTAGE (VOLTS)

140

20

V

~

..-

TA = 25°C

20

iii

V

~ 41----F---+---+---j

40

..

TOTAL SUPPLY CURRENT
YS TEMPERATURE

~
o

±5

±1D

----

.

.".-

±1S

SUPPLY VOLTAGE (VOLTS)

±20

;

60

~

50

40
-75 -50 -25

-Om

25

50

75

100

0
125 150

TEMPERATURE ( 3kO, a pole created by AI and the amplifier's input
capacitance (3pF) creates additional phase shift and reduces
phase margin. A small capacitor in parallel with AI helps
eliminate this problem.
COMPUTER SIMULATIONS
Many electronic design and analysis programs include models
forop amps which calculate AC performance from the location
of poles and zeros. As an aid to designers utilizing such a
program, major poles and zeros of the OP-271 are listed below.
Their location will vary slightly between production lots.
Typically, they will be within ±15% of the frequency listed. Use
of this data will enable the designer to evaluate gross circuit
performance quickly, but should not supplant rigorous characterization of a breadboarded circuit.

FIGURE 1: Driving Large Capacitive Loads
v+

POLES

ZEROS

15 Hz
1.2 MHz
2 x 32 MHz
8x40 MHz

2.5 MHz
4x23 MHz

C2

+--C-3-.!.j~o8

O.1rr ":'"
":"

.,

A2

C4

~-c-.-.-I,o~

0.18
":'"

v-

PLACE SUPPLY DECOUPLING
CAPACITORS AT OP-271

UNITY-GAIN BUFFER APPLICATIONS
When AI:::; 1000 and the input is driven with a fast, large-signal
pulse (>1 V), the output waveform will look as shown in Figure 2.

During thefastfeedthrough-like portion oftheoutput, the input
protection diodes effectively short the output to the input. and a
current, limited only by the output short-circuit protection, will
be drawn by the signal generator. With AI;:O: 5000, the output is
capable of handling the current requirements (IL :::; 20mA at
10V); the amplifier will stay in its active mode and a smooth
transition wi II occu r.

APPLICATIONS
LOW PHASE ERROR AMPLIFIER
The simple amplifier depicted in Figure 3 utilizes a monolithic
dual operational amplifier and a few resistors to substantially
reduce phase error compared to conventional amplifier designs.
At a given gain, the frequency range for a specified phase
accuracy is over a decade greater than for a standard single op
amp amplifier.

The low phase error amplifier performs second-order frequency
compensation through the response of op amp A2 in the
feedback loop of A1. Both op amps must be extremely well
matched in frequency response. At low frequencies, the A 1
feedback loop forces V2/(K1 + 1) VIN. The A2 feedback loop
forces Vo/(K1 + 1) V2/(K1 + 1) yielding an overall transfer
function of VOIVIN = K1 + 1. The DC gain is determined by the
resistor divider at the output, Vo, and is not directly affected by
the resistor divider around A2. Notethat, like a conventional
single op amp amplifier, the DC gain is set by resistor ratios
only. Minimum gain for the low phase error amplifier is 10.

=

=

FIGURE 3: Low Phase Error Amplifier
R2

R2=R1

~~----------~~~

.2
Ki

r------'l
I

I

I
~-l----..JV2

FIGURE 2: Pulsed Operation

.,

V'N

0----11--1

L-------o
ASSUME: Ai AND A2 ARE MATCHED.

Yo=(K1

Vo

+ 1) YIN

Ao(S)""~

2-294 OPERA TIONALAMPLIFIERS

REV. B

OP-271
FIGURE 4: Phase Error Comparison

~~;';:N~~OAN~
"
DESIGN

_-.

:ilc

~ -3

~w

::

~

~

-1

DUAL 12-BIT VOLTAGE OUTPUT DAC
The dual voltage output DAC shown in Figure 5 will settle to
12-bit accuracy from zero to full scale in 21's typically. The
CMOS DAC-8222 utilizes a 12-bit, double-buffered input structure allowing faster digital throughput and minimizing digital
feedthrough.

CASCADED
(TWO STAGES)

I

=f""'"
W~~I ERR~R

-4 -

V

Lol

FAST CURRENT PUMP
Maximum output current of the fast current pump shown in
Figure 6 is ±11mA. Voltage compliance exceeds ±10V with
±15V supplies. The current pump has an output resistance of
over 3MO and maintains 12-bit linearity over its entire output
range.

,

1\

AMPLIFIER

'"

.. -5
-6

1\

-7
0.001

1\

FIGURE 6: Fast Current Pump

I
0.01
I
0.1
0.005
0.05
FREQUENCY RATIO (1/,u)(w/wT)

I

0.5

1.0
R3

Figure 4 compares the phase error performance of the low
phase error amplifier with a conventional single op amp
amplifier and a cascaded two-stage amplifier. The low phase
error amplifier shows a much lower phase error, particularly for
frequencies where W/f:!wT<0.1. For example, phase error of
-0.10 occurs at 0.002 wlf:!wrforthesingleopamp amplifier, but
at 0.11 wlf:!wr for the low phase error amplifier.

Y,N

For more detailed information on the low phase error amplifier,
see Application Note AN-107.
lOUT =

~=

,!:'n =

10mAIV

-15Y

FIGURE 5: Dual 12-Bit Voltage Output DAC
+15V
10~F

+~

+5V

~
+10Y
REFERENCE
VOLTAGE

I
I

__ 1 __ -,
tI
VOD

RFBA

O.1~F

~

OAC·B••• EW

+--'-"'~

>-+"-4------oVoU,...

'---F-..,...--..,...--<> -15V

>--1f'-......-----oVourB
DAC {
CONTROL

REV. B

oJ!1llAl:A/DAC •
19

o-.!!!J=
~

--I-- ..J
DOND

OPERA nONAL AMPLIFIERS 2-295

2-296 OPERA TlONAL AMPLIFIERS

Dual Bipolar/JFET, Low Distortion
Operational Amplifier
OP-275* I

1IIIIIIII ANALOG

WDEVICES

PIN CONNECTIONS

FEATURES
"Sounds Good"
Low Noise: 5 nV/VHZ
Low Distortion: 0.0006%
High Slew Rate: 20 V/fJ.S
Wide Bandwidth: 8 MHz
Low Supply Current: 2 mA/Amplifier
Low Offset Voltage: 1 mV
Low Offset Current: 2 nA
Unity Gain Stable

8-Lead Narrow Body SOIC
(S SuffIx)

•

8-Lead Epoxy DIP
(P Suffix)

APPLICATIONS
High Performance Audio
Active Filters
Fast Amplifiers
Integrators

GENERAL DESCRIPTION
The OP-Z75 is the fIrst amplifier to feature the Butler Amplifie
front-end. This new front-end design combines the accuracy and
low noise perfonnance of bipolar transistors with the speed and
sound quality of JFETs. This yields better THD and noise performance than previous audio amplifiers, at much lower supply
currents.
Bias and offset currents are also greatly reduced over bipolar
designs.
The OP-Z75 is specified over the extended industrial and military temperature ranges. OP-Z75s are available in plastic and
ceramic DIP plus SOIC 8-pin surface mount packages.
ORDERING GUIDE
Model

Temperature
Range

OP275AZ1883
OP275ARCl883
OP27SGP
OP27SGS
OP27SGBC

- 55°C to
- 55°C to
-40°C to
-40°C to
+Z5°C

+ lZ5°C
+ lZ5°C
+85OC
+85°C

upply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Input Voltage2 • • • • • • • • • • • • • • • • • • • • • • • • • • • ± 18 V
Differential Input Voltage2 • • • • • • • • • • • • • • • • • • • • • 36 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Limited
Storage Temperature Range
Y, Z, RC Package . . . . . . . . . . . . . . . . -6SoC to + 175°C
P, S Package . . . . . . . . . . . . . . . . . . . . -6SoC to + ISO°C
Operating Temperature Range
OP-27SA . . . . . . . . . . . . . . . . . . . . . . -55°C to + 125°C
OP-27SG . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Junction Temperature Range
Y, Z, RC Package . . . . . . . . . . . . . . . . -65°C to + ISOOC
P, SPackage . . . . . . . . . . . . . . . . . . . . -65°C to +ISO°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C
3

Package Option

Package Type

a)A

14-Pin Cerdip
ZO-Contact LCC
8-Pin Plastic DIP
8-Pin SOIC
DICE

8-Pin Cerdip (Z)
8-Pin Plastic DIP (P)
8-Pin SOIC (S)
ZO-Contact LCC (RC)

148
103
158
NA

a)C

16
43
43
NA

Units
0c/w
0c/w
0c/w
0c/w

NOTES
I

Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise nored.

·Patent pending.

'Par supply voltages less than ± 18 V, the absolute maximum input voltage is
equal to the supply voltage.
39JA is specified for the worst case conditions, i.e., 8JA is specified for device in

socket for cerdip, P·DIP, and Lee packages;
soldered in circuit board for sOle package.

alA

is specified for device

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

REV. 0

OPERA T10NALAMPLIFIERS 2-297

OP~275 - SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ Ys =±15.0 Y, TA =
Parameter

Symbol

INPUT CHARACTERISTICS
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection
Large Signal Voltage Gain
Offset Voltage Drift

Vos
IB
los
VCM
CMR
Avo
t..Vos/t..T

OUTPUT CHARACTERISTICS
Output Voltage Swing

Vo

Open Loop Output Resistance

RoUT

POWER SUPPLY
Power Supply Rejection Ratio
Supply Current!Amplifier
Supply Voltage Range

PSRR
ISY
Vs

DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Total Harmonic Distortion

SR
BWp
ts
GBP
THD

Phase Margin
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Voltage Noise Density
Current Noise Density
Current Noise Density
Overshoot Factor

WAFER TEST LIMITS

+25OC unless otherwise specified.)
Min

Conditions

Typ

Max

Units

+11

mV
nA
nA
V
dB
V/mV
jJ.vrc

I
150
2

VCM = 0 V
VCM = 0 V
-II
S6

VCM = ±II V
RL = 600n

200
5

RL = 10kn
RL = 6OOn, Vs = ±ISV

-13

13
±17

SO
2
±IS

±4.5
20

S
0.002
0.0006
62

@20kHz
@lkHz

00
en P-P
en
en

f= 30Hz, Vs = ±ISV, V,N = lOVrms
f= I kHz, Vs = ±ISV, V,N = 10 V rms
f=30Hz
f=lkHz
VIN = 100 mY, AVD = I,
RL = 600 n, CL = 100 pF

i"
i"

S
5

10

V
V
n
dB
mA
V
V/jJ.s
kHz
jJ.S
MHz
%
%
degrees
jJ.Vp-p
nWVHz
nV/y'Hz
pAlVHz
pAly'Hz

%

(@ Ys=±15.0 Y, TA = +25OC unless otherwise specified.)

Parameter

Symbol

Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range'
Common-Mode Rejection
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Range
Supply. Current!Amplifier

Vos
IB
los

VCM = 0 V
VCM = 0 V

CMRR
PSRR
Avo
Vo
Isy

VCM = ± 11 V
V = ±9 V to ± IS V
RL = 10 kn
RL = 10kn
Vo = OV, RL = x

Conditions

Limit

Units
mVmax
nAmax
nAmax
V min
dB min
jJ.VN
VlmVmin
V min
mAmax

NOTES
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for
standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
'Guaranteed by CMR test.
Specifications subject to change without notice.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2-298 OPERA TlONALAMPLlFIERS

REV.

a

High Speed Low Noise Quad
Operational Amplifier
OP-471 I

r.ANALOG
WDEVICES
FEATURES
•
•
•
•
•
•
•
•
•
•

Excellent Speed . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8V1/J.s Typ
Low Noise ................... 11nVl.j"iiZ @ 1kHz Max
Unity-Gain Stable
High Gain-Bandwidth ...................... 6.5MHz Typ
Low Input Offset Voltage ................... O.BmV Max
Low Offset Voltage Drift ................... 4/J.V/oC Max
High Gain ............................... 500VlmV Min
Outstanding CMR ......................... 105 dB Min
Industry Standard Quad Pinouts
Available in Die Form

ORDERING INFORMATION t
PACKAGE
TA =+25"<:
VosMAX
CERDIP
(IN)
PLASTIC
800
800
800
1500
1800
1800

LCC'

OP471EY
OP471FY
OP471GP
OP471 Gstt

PIN CONNECTIONS

OPERATING
TEMPERATURE
RANGE

OP471ATC/883
OP471ARC/883

OP471Ar

The OP-471 has an input offset voltage under O.amV and an
input offset voltage drift below 4/J.V/oC, guaranteed over the
full military temperature range. Open loop gain of the OP-471
is over 500,000 into a 10k!! load insuring outstanding gain
accuracy and linearity. The input bias current is under 2SnA

MIL
MIL
INO
INO
XINO
XINO

14-PIN HERMETIC DIP
(V-Suffix)
14-PIN PLASTIC DIP
(P-Suffix)

N.C.

For devices processed in total compliance to MIL-STD-883, add 1883 after part
number. Consult factory for 883 data sheet.
Burn-in is available on commercial and industrial temperature range parts in
CerDIP, plastic DIP, and TO-can packages.
It For availability and burn-in information on SO and PLCC packages, contact
your local sales office.

+IN D

N.C.

N.C.

y-

N.C.

:
"T

The OP-471 is a monolithic quad op amp featuring low noise,
11nv/y'HZ Max @ 1kHz, excellent speed, 8V//J.s typical, a
gain-bandwidth of 6.5MHz, and unity-gain stability.

+IN D
y-

(""" r.::1;',"'. "',,:":'2°":":3'-:;)
GENERAL DESCRIPTION

16-PIN SOL
(S-Suffix)

+INC

+IN8

+INC

r::;"\r.~r.;1t«1r.;;;Jr.;1r.;;;J '7

N.C.

~-Q ~ ~

6

Z

6 ,.

20-LEADLCC
(RC-Suffix)

28-LEADLCC
(TC-Suffix)

SIMPLIFIED SCHEMATIC (One of four amplifiers is shown.)
r-~------~----~----~r-~~----------------------~~~~----~-Ov+

OUT

-IN 0 -.....-1'-.....

L-----------------~--+_--------~--------__~--+_--~_+--~_ov-

REV. B

OPERA TlONAL AMPLIFIERS 2-299

OP-471
Lead Temperature Range (Soldering, 60 sec) .............. 300°C
Junction Temperature (T1 ............................ -65°C to + 150°C
Operating Temperature Range
OP-471 A .................................................... -55°C to + 125°C
OP-471 E, OP-471 F ..................................... -25°C to +85°C
OP-471 G ...................................................... -40°Cto +85°C

limiting errors due to signal source resistance. The OP-471 's
CMR of over 105dB and PSRR of under 5.6"VIV significantly
reduce errors caused by ground noise and power supply
fluctuations.
The OP-471 offers excellent amplifier matching which is
important for applications such as multiple gain blocks, lownoise instrumentation amplifiers, quad buffers and low-noise
active filters.

8 JA (Note 2)

PACKAGE TYPE

UNITS

8 JC

·CIW
94
10
14-Pin Hermetic DIP (V)
·CIW
33
14-Pin Plastic DIP (P)
76
·CIW
30
20-Contact LCC (RC)
78
28
·CIW
28-Contact LCC (TC)
70
IS-Pin SOL (S)
88
23
OCIW
NOTES:
I. Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2. 8. is specified for worst case mounting conditions. i.e.• 8' A is specified for
d~~ice in socket for CerDIP. P-DIP. and LCC packages;
is specified for
device soldered to printed circuit board for SOL package.
3. The OP-471's inputs are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low noise performance. If differential
voltage exceeds ±I .OV. the input current should be limited to ±25mA.

The OP-471 conforms to the industry standard 14-pin DIP
pinout. It is pin compatible with the OP-11, LM148/149,
HA4741, RM4156, MC33074, TL084 and TL074 quad op amps
and can be used to upgrade systems using these devices.
For applications requiring even lower voltage noise the OP470, with a voltage density of 5nV/.,j'Hz Max @ 1kHz, is
recommended.

8: A

ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage ................................................................. ±18V
Differential Input Voltage (Note 3) .................................. ±1.0V
Differential Input Current (Note 3) ............................... ±25mW
Input Voltage .................................................... Supply Voltage
Output Short-Circuit Duration ................................ Continuous
Storage Temperature Range
p, RC, TC, Y -Package ............................... -65°C to + 150°C

ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = 25°C, unless otherwise noted.
SYMBOL

Input Offset Voltage

vas

Input Offset Current

los

VCM = OV

Input Bias Current

18

VCM = OV

Input Noise Voltage

e np _p

O.IHz to 10Hz
(Note 1)

en

10 = 10Hz
10= 100Hz
10= 1kHz
(Note 2)

In

10= 10Hz
10 = 100Hz
10 = 1kHz

Ava

Vo= ±10V
RL = 10kll
RL = 2kll

500
350

700
550

Input Noise

Voltage Density

Input Noise
Current Density

Large-Signal
Voltage Gain

CONDITIONS

OP-471A/E
MIN
TYP MAX

PARAMETER

MIN

OP-471F
TYP MAX

MIN
;-

0.25

0.8

0.5

1.5

4

10

7

25

15

OP-471G
TYP MAX
1.8

mV

20

12

30

nA

50

25

60

nA
nVp _p

250

500

250

500

250

500

9

16
12
11

9
6.5

16
12
11

6.5

16
12
11

6.5

1.7
0.7
0.4

1.7
0.7
0.4
300
175

UNITS

1.0

nV/.,[HZ

1.7
0.7
0.4

pA/.,[HZ

V/mV

500
275

300
175

500
275

Input Voltage Range

IVR

(Note 3)

±11

±12

±11

±12

±11

±12

Output Voltage Swing

Va

RL22kll

±12

±13

±12

±13

±12

±13

V

VCM = ±l1V

105

120

95

115

95

115

dB

Common-Mode Rejection CMR
Power Supply
Rejection Ratio

Slew Rate

PSRR
SR

2-300 OPERATIONAL AMPLIFIERS

5.6

5.6

Vs = ±4.5V to ±18V
6.5

8

6.5

8

17.8

5.6
6.5

V

17.8

!'VIV
V/!'s

REV. B

OP-471
ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = 25°C, unless otherwise noted. (Continued)
OP-4nF

OP-4nA/E
PARAMETER

SYMBOL

CONDITIONS

Supply Current
(All Amplifiers)

ISY

No Load

MIN

TYP

MAX

9.2

11

6.5

11

TYP

MAX

UNITS

9.2

11

mA

dB

2.6

2.6

pF

1.1

1.1

1.1

M!!

11

11

11

G!!

4.5
7.5

4.5
7.5

4.5
7.5

~s

Va ~ 20Vp"p
fa ~ 10Hz (Note 1)

Input Capacitance

C'N

2.6

Input Resistance
Differential-Mode

R'N
R 1NCM

Common-Mode

9.2

MIN

MHz

CS

125

MAX

6.5

Av~

Channel Separation

+10

OP-4nG

TYP

150

Gain-Bandwidth Product GBW

Input Resistance

MIN

150

6.5
125

150

125

Av~+1

Settling Time

to 0.1%
to 0.01%

ts

NOTES:
1. Guaranteed but not 100% tested.
2. Sample tested.
3. Guaranteed by CMR test.

ELECTRICAL CHARACTERISTICS at Vs = ±15V, -55°C::; TA::; 125°C for OP-471 A, unless otherwise noted.
OP-4nA
PARAMETER

SYMBOL

Input Offset Voltage

Vas

Average Input

Offset Voltage Drift

CONDITIONS

MIN

TYP

MAX

0.4

1.2

mV

4

~V;oC

TCVos

UNITS

Input Offset Current

los

VCM~

OV

6

20

nA

Input Bias Current

I.

VCM~

OV

16

50

nA

Vo~

Large-Signal
Voltage Gain

Ava

±10V
RL ~ 10k!!
RL ~ 2k!!

375
250

500
350

V/mV

Input Voltage Range

IVR

(Note 1)

±11

±12

V

Output Voltage Swing

Va

R L 202k!!

±12

±13

V

CMR

VCM~

100

115

dB

PSRR

Vs ~ ±4.5V to ±18V

5.6

10

~VIV

ISY

No Load

9.3

11

mA

Common-Mode
Rejection

Power Supply
Rejection Ratio

Supply Current
(All Amplifiers)

±11V

NOTE:
1. Guaranteed by CMR test.

REV.B

OPERATIONAL AMPLIFIERS 2-301

•

OP-471
ELECTRICAL CHARACTERISTICS at Vs = ±15V, -25°C ~ TA ~ +85°C for OP-471 ElF, -40°C ~ T A ~ +85°C for OP-471 G, unless
otherwise noted.

OP-471E
PARAMETER

SYMBOL

Input Offset Voltage

Vas

Average Input

Offset Voltage Drift

CONDITIONS

OP-4nF

TYP

MAX

0.3

1.1

MIN

OP-4nG

TYP

MAX

0.6

2.0

MIN

TYP

MAX

1.2

2.5

4

TCVos

Input Offset Current

los

VCM

~

OV

Input Bias Current

18

VCM

~

OV

mV
MVI'C

20
13

UNITS

25

50

40

20

50

nA

70

40

75

nA

Vo~±10V

Large-Signal
Voltage Gain

MIN

Ava

RL
RL

~
~

10k!!
2k!!

400

375
250

600
400

200
125

200

200
125

200

400

V/mV

Input Voltage Range

IVR

(Note 1)

±11

±12

±11

±12

±11

±12

V

Output Voltage Swing

Va

RL2: 2k!!

±12

±13

±12

±13

±12

±13

V

CMR

VCM = ±11V

100

115

90

110

90

110

dB

PSRR

Vs

ISY

No Load

Common-Mode
Rejection
Power Supply

Rejection Ratio
Supply Current

(All Amplifiers)

= ±4.5V to ±18V

3.2

10

18

31.6

18

31.6

MV/V

9.3

11

9.3

11

9.3

11

mA

NOTE:
1. Guaranteed by CMR test.

2-302 OPERA TlONAL AMPLIFIERS

REV. B

OP-471
DICE CHARACTERISTICS

1.
2.
3.
4.
5.

OUT A
-INA
+INA

v+
+IN B

6. -IN B
7. OUT B
8.0UTC
9. -INC
10. +IN C
11. V12. +IN D
13. -IN D
14. OUT D

DIE SIZE 0.163 X 0.106 Inch, 17,278 sq. mils
(4.14 X 2.69 mm, 11.14 sq. mm)

WAFER TEST LIMITS at Vs = ±15V, TA = 25°C, unless otherwise noted.
OP-471GBC
PARAMETER

SYMBOL

Input Offset Voltage

Vos

CONDITIONS

LIMIT

UNITS

1.5

mVMAX

Input Offset Current

los

VCM = OV

20

nAMAX

Input Bias Current

18

VCM = OV

50

nAMAX

Avo

Vo = ±10V
RL = 10k!!
RL = 2k!!

300
175

V/mVMIN

VMIN

Large-Signal
Voltage Gai n
Input Voltage Range

IVR

Note 1

±11

Output Voltage Swing

Vo

RL2: 2k!!

:±.12

VMIN

Common-Mode Rejection

CMR

VCM=:!.-11V

95

dB MIN

Power Supply
Rejection Ratio

PSRR

Vs = ±4.5V to ±18V

17.8

MVIV MAX

Slew Rate

SR

6.5

VIMS MIN

Supply Current
(All Amplifiers)

ISY

11

mAMAX

No Load

NOTES:
1. Guaranteed by CMR test.
Electrical tests are performed at wafer probe to the limits shown. Due to vanations In assembly methods and normal yield loss, Yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

REV.B

OPERA TIONAL AMPLIFIERS 2-303

OP-471
TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE NOISE DENSITY
vs FREQUENCY

VOLTAGE NOISE DENSITY
vs SUPPLY VOLTAGE

100
TA - 25°C
Vs - +15V

~

20

0
z

10

.

>

AT 10Hz

40
30

!w

O.1Hz TO 10Hz NOISE

10r-----~-----r-----r-----,

I

Ii •r - - - t - - - + - - - t - - - I
~w

~~

6z 6~----+-----~----~-----4

w

"a~

w

"g~

AT 1kHz

!ll

a
z

w

"~

r - 11t CO~~I~R - 5Hz

>

g

II IIIII I I

JIIIIII

1

TIME (SEC)

T.=25°C

I

10

1

2L-____
100

o

1k

____

~

____

±10

~

____

Ys=±1SV

~

±15

±20

SUPPLY VOLTAGE (VOLTS)

CURRENT NOISE DENSITY
vs FREQUENCY

WARM-UP OFFSET
VOLTAGE DRIFT

INPUT OFFSET VOLTAGE
vs TEMPERATURE
20

400

10.0
TA
Vs

25~C

VS =±lSY

+15V

>

Ii
i

;: 300

"a~

'I'

w

1.0

a
z
....

~

±5

FREQUENCY (Hz)

!!l

10

4~----+-----~----~-----4

./

>

~

,

illa:
a:
u

::J

I

10

a
!;

!

it' c'lR1iEtIIW

H'

III

0.1

200

V

w

~ 14

!:l

g 12

V

....

10k

1k

FREQUENCY (Hz)

~

~

-75

z

:!:

-50

-25

./

~ 10

:::a

100

o

TA = 25°C
Vs = ±15V

>
..5 16

.
•

4

U

1111111

100

~

,

1.

,.,

25

50

75

100

125

/

I

o
o

2
TIME (MINUTeS)

INPUT BIAS CURRENT vs
COMMON-MODE VOLTAGE

INPUT OFFSET CURRENT
vs TEMPERATURE

20

10
Vs = ±15V
VCM

15

'\

ffi
a:
a:

a

10

1\....... r--...

iii

!;
5

o_

_

TA = 25°C
Vs = ±15V

=ov

'\

:Il

!

I

TEMPERATURE (DC)

INPUT BIAS CURRENT
vs TEMPERATURE

~

I'

_

~

~

~

~

m

TEMPERATURE (OC)

~

~7~5---~50---~25~~0--~2~5--5~0--~~--~'0-0~'25
TEMPERATURE (DC)

-

--

10.0
-12.5

",

,/

1/

",

-5.0
-7.5

~

5.0
-2.5

2.5

10.0
7.5

12.5

COMMON-MODE VOLTAGE (VOLTS)

2-304 OPERA TIONALAMPLIFIERS

REV. B

OP-471
TYPICAL PERFORMANCE CHARACTERISTICS

130

I+~I~ 2S

120

Vs

10

D
C

YS=±15V

= ±15V

110

;(

.§. 8

100

I-

90

::ia:

01

80

"

60

""
il:
"

a:

!!.
a: 70

,.

TOTAL SUPPLY CURRENT
vs TEMPERATURE

TOTAL SUPPLY CURRENT
vs SUPPLY VOLTAGE

CMR vs FREQUENCY

~

.

50

6

~

~

40

0

I-

30
20
10
10

100

1k

10k

1M

lOOk

±5

0

FREQUENCY (Hz)

±10

140

80

TA = 2S D C

.
a.

"- "-

120

80
40

20

1

10

100

z

a

10k

lOOk

1M

10M

80

9

..

0

40

"a.
0

~

Ys= ±15Y
60

.....

""\

!!.

-PSR

1k

r---

m 100

""
" "-" "" "-"

+PSR

80

o

TA = 2SD C

=±15V

Vs

100

01

100M

10

100

80

a

"a.

10

~ ........

0

9

zw
a.
0

-5

-

Vs=±15V

;;;;;

40

'\

i -

'-'\.

10k

lOOk

-

20

~

9

" "1M

10M

"
-20
1k

100M

10k

lOOk

1M

10M

FREQUENCY (Hz)

GAIN-BANDWIDTH
PRODUCT, PHASE MARGIN
vs TEMPERATURE

TA = 2S"C

Vs - ±15V

RL = 10kfl

100

r=±15V

GBW

¥

PHASE

--""" J:t

"N"-",

120

140

MARGIN
=57" ,_

180

r"'r-. i'
10

FREQUENCY (MHz)

~

:il

~

c;

~

z

~

o

Ii:

~

_

1500

~

o

!.

10

6 I-

""c

a

o

z

1000

./ ~

500

o

o

II:

..

~ 60

,/

4 :I:

~

it

V

200
220

1

:>

160 w

-10

REV.B

TIn
TA "" 2S"C

200 0

TA = 2SD C

r--

1k

-

0

OPEN-LOOP GAIN
vs SUPPLY VOLTAGE

25

15

"

"a.

-

CLOSED-LOOP GAIN
vs FREQUENCY

FREQUENCY (Hz)

OPEN-LOOP GAIN, PHASE
SHIFT vs FREQUENCY

01
!!.
z

~
z
a

20

FREQUENCY (Hz)

20

TEMPERATURE (DC)

OPEN-LOOP GAIN
vs FREQUENCY

140

!!.
a:

±20

±15

SUPPLY VOLTAGE (VOLTS)

PSR vs FREQUENCY
120

_ ___~~0__-L
~ __..
L-~
~__~
~~
m

_

2L-~

2
1

I;
ic
z

-t/>
50

2

"
40

±5

c
'l'
z

a

±10

±15

SUPPLY VOLTAGE (VOLTS)

±20

0

-75 -50 -25

0

25

50

75

100

125 150

TEMPERATURE (DC)

OPERA TIONAL AMPLIFIERS 2-305

OP-471
TYPICAL PERFORMANCE CHARACTERISTICS

•• ...

-

C;; 24

~

!:l

TA ""

16

=

12

~

~

~

14

1111111\

\

...::.
~

,.

..

9

!

6

o

:0

6
~
II!

8

~

360

I II

II

I-

PJSWE
SWING

Io?'
NEGATIVE
SWING

10

II!

180

...:0i!!
...:0a.

10k

lOOk

o

0
100

10M

1M

•
10k

=1

lOOk

1M

10M

100M

TOTAL HARMONIC
DISTORTION vs FREQUENCY

170

TA "" 25°C

160
8.5

~

150

-SR .....
KR

g

8.0

w
7.5

~

~ 7.0

6.0
-75

1k

Ay

111111111
111111111

FREQUENCY (Hz)

CHANNEL SEPARATION
vs FREQUENCY

SLEW RATE
TEMPERATURE

9.0

6.5

100

10k

"

LOAD RESISTANCE (n)

FREQUENCY (HZ)

VB

120

0

60

t--

1k

a:

.40

c-

o

!c

S
w

"ilz

;J
4

T~I!"~~OC
Vs ... ±15V

300

16

g -

~

:!l

TA'.5·C
V,'±15V

iii'

20

~

19

THO"" 1%

o

2:.

.0

25~CI

Va"" ±15Y

l-

CLOSED-LOOP
OUTPUT IMPEDANCE
VB FREQUENCY

MAXIMUM OUTPUT
VOLTAGE vs
LOAD RESISTANCE

MAXIMUM OUTPUT SWING
vs FREQUENCY

I
I

!l

-50

=-

~

~

~

f

-25

~

a:
0

In

120

"0Z

110

."...
a:

.

90

"

70

TA"" 25°C

60

Vs =±15V
Yo == 20Yp _p TO 100kHz

Z

:z:

:z: 80

25

50

75

100

125

50
10

I

0.1

is

~ 100
w

z

Vo -10Vp•p
RL == 2kO

0

;:

140

~ 130

fia:

Vs"" ±15V

Z

0.01
Ay -10

j!

100

TEMPERATURE (DC)

1k

10k

.....,..

...0
lOOk

1M

10M

TA = 25°C
Vs'" ±15V
Ay =+1

2-306 OPERATIONAL AMPLIFIERS

100

Av- 1

Ilflll
1k

10k

FREQUENCY (Hz)

FREQUENCY (H:r:)

LARGE-SIGNAL
TRANSIENT RESPONSE

I

-I--

0.001
10

SMALL-SIGNAL
TRANSIENT RESPONSE

T:'=.2S0C
Vs "" ±15,V

Ay=:-'

REV.S

OP-471
CHANNEL SEPARATION TEST CIRCUIT

TOTAL NOISE AND SOURCE RESISTANCE
The total noise of an op amp can be calulated by:

SkU

+ (in RS)2 + (et)2

En = V(e n)2
where:

En = total input referred noise

>-~--o V1 20Vp•p

en = op amp voltage noise
in = op amp current noise
et = source resistance thermal noise

SOkn

Rs = source resistance
>----<>---0

The total noise is referred to the input and at the output would
be amplified by the circuit gain.

V,

CHANNEL SEPARATION"" 20 IOg(

V2/~~OO)

Figure 1 shows the relationship between total noise at 1kHz
and source resistance. For Rs < 1kll the total noise is domi-

FIGURE 1: Total Noise vs Source Resistance (Including
Resistor Noise) at 1kHz

BURN-IN CIRCUIT

~
•

+1V
-18V

~
_

-w

10

+

C

~3_

8

"::"

7

5 +

0

-w

12

+

w

ozct.I

10

OP-4OO

OP-471

~

i!

1!

14

100

1k

"::"

10k

10Ol<

Rs - SOURCE RESISTANCE (il)

FIGURE 2: Total Noise vs Source Resistance (Including
Resistor Noise) at 10Hz

APPLICATIONS INFORMATION
100

VOLTAGE AND CURRENT NOISE
The OP-471 is a very low-noise quad op amp, exhibiting a
typical voltage noise of only 6.5nv/J"HZ @ 1kHz. The low
noise characteristic of the OP-471 is in part achieved by
operating the input transistors at high collector currents
since the voltage noise is inversely proportional to the square
root of the collector current. Current noise, however, is
directly proportional to the square root of the collector
current. As a result, the outstanding voltage noise performance of the OP-471 is gained atthe expense of current noise
performance which is typical for low noise amplifiers.
To obtain the best noise performance in a circuit it is vital to
understand the relationship between voltage noise (en), current noise (in), and resistor noise (et).

REV.B

..,oj

Ii'>
~

.,w

!£

OP-11

OP-471

i!0

OP-470

~

"

OP-400

10

0z

...

j.

~
100

RESISTOR
NOISE ~rLY

1k

10k

lOOk

Rs - SOURCE RESISTANCE (n)

OPERA TIONALAMPLIFIERS 2-307

II

OP-471
nated by the voltage noise of the OP-471. As Rs rises above
1kn, total noise increases and is dominated by resistor noise
rather than by voltage or current noise of the OP-471. When
Rs exceeds 20kn, current noise of the OP-471 becomes the
major contributor to total noise.
Figure 2 also shows the relationship between total noise and
source resistance, but at 10Hz. Total noise increases more
quickly than shown in Figure 1 because current noise is
inversely proportional to the square root of frequency. In
Figure 2, current noise of the OP-471 dominates the total
noise when Rs > Skn.
From Figures 1 and 2 it can be seen that to reduce total noise,
source resistance must be kept to a minimum. In applications
with a high source resistance, the OP-400, with lower current
noise than the OP-471, will provide lower total noise.
Figure 3 shows peak-to-peak noise versus source resistance
over the 0.1 Hz to 10Hz range. Once again, at low values of Rs,
FIGURE 3: Peak-To-Peak Noise (0.1Hz To 10Hz) vs Source
Resistance (Includes Resistor Noise)
1000

OP·11

the voltage noise of the OP-471 is the major contributor to
peak-to-peak noise. Current noise becomes the major contributor as Rs increases. The crossover point between the OP471 and the OP-400 for peak-to-peak noise is at Rs = 17kn.
The OP-470 is a lower noise version of the OP-471, with a
typical noise voltage density of 3.2nV/y"HZ @ 1kHz. The
OP-470 offers lower offset voltage and higher gain than the
OP-471, but isa slower speed device, with a slew rate of 2V/Ils
compared to a slew rate of 8V/Ils for the OP-471.
For reference, typical source resistances of some signal
sources are listed in Table I.

TABLE I
DEVICE

SOURCE
IMPEDANCE
<50011

Typically used in low-frequency
applications.

Magnetic
1apehead

<150011

Low 16 very important to reduce
self-magnetization problems when
direct coupling is used. OP-471 I B
can be neglected.

Magnetic
phonograph
cartridges

<150011

Similar need for low 18 in direct
coupled applications. OP-471 will not
introduce any self-magnetization
problem.

Linear variable
differential
transformer

< 150011

Used in rugged servo-feedback
applications. Bandwidth of interest is
400Hz \0 5kHz.

OP-4DO

.~
00

~

OP-471

i5

.."z
00

~

OpL7l

100

,/

For further information regarding noise calculations, see
"Minimization of Noise in Op-Amp Applications", Application Note AN-1S.

6
~

~

~
10
100

COMMENTS

Strain gauge

RESISTOR
NOISE ONLY

11111111
1k
Rs -

10k

SOURCE RESISTANCE (ll)

lOOk

NOISE MEASUREMENTS PEAK-TO-PEAK VOLTAGE NOISE
The circuit of Figure 4 is a test setup for measuring peak-topeak voltage noise. To measure the SOOnV peak-to-peak

FIGURE 4: Peak-To-Peak Voltage Noise Test Circuit (0.1Hz To 10Hz)

.3

C4

4.99kD

..Lcs
J1~F

O.032pF

2-308 OPERA TlONAL AMPLIFIERS

GAIN = 50,000
Vs =±15V

REV.S

OP-471
noise specification of the OP-471 in the 0.1 Hz to 10Hz range,
the following precautions must be observed:
1. The device has to be warmed-up for at least five minutes.
As shown in the warm-up drift curve, the offset voltage
typically changes 131'V dueto increasing chip temperature
after power-up. In the 10-second measurement interval,
these temperature-induced effects can exceed tensof-nanovolts.
2. For similar reasons, the device has to be well-shielded
from air currents. Shielding also minimizes thermocouple
effects.
3. Sudden motion in the vicinity of the device can also "feedthrough" to increase the observed noise.
FIGURE 5: 0.1 Hz To 10Hz Peak-To-Peak Voltage Noise
Test Circuit Frequency Response

4. The test time to measure 0.1 Hz-to-l0Hz noise should not
exceed 10 seconds. As shown in the noise-tester frequency-response curve of Figure 5, the 0.1 Hz corner is
defined by only one pole. The test time of 10 seconds acts
as an additional pole to eliminate noise contribution from
the frequency band below O.lHz.
5. A noise-voltage-density test is recommended when measuring noise on a large number of units. A 10Hz noisevoltage-density measurement will correlate well with a
0.1 Hz-to-l0Hz peak-to-peak noise reading, since both
results are determined by the white noise and the location •
of the llf corner frequency.
6. Power should be supplied to the test circuit by well
bypassed low-noise supplies, e.g. batteries. These will
minimize output noise introduced through the amplifier
supply pins.
NOISE MEASUREMENT - NOISE VOLTAGE DENSITY
The circuit of Figure 6 shows a quick and reliable method of
measuring the noise voltage density of quad op amps. Each
individual amplifier is series-connected and is in unity-gain,
save the final amplifier which is in a noninverting gain of 101.
Since the ac noise voltages of each amplifier are uncorrelated, they add in rms fashion to yield:

100

~
0",

0

iii' •
:!!.

z

~

eOUT = 101

40

The OP-471 is a monolithic device with four identical amplifiers. The noise voltage density of each individual amplifier will
match, giving:

20

o '0.01

(J e nA2 + e nB2 + e nc 2 + e n o2 )

eOUT= 101 ( Q ) = 101 (2e n)
0.1

10

100

FREQUENCV (Hz)

FIGURE 6: Noise Voltage Density Test Circuit

.,
100n

.2
10kO

e OUT (nVl\! Hz) IE 101(2e n)
Vs "" ±15V

REV. B

OPERA TIONALAMPLIFIERS 2-309

OP-471
FIGURE7: Current Noise Density Test Circuit

"3

_" OUT TO

~-r-" SPECTRUM ANALYZER

8.0",n

".

GAIN

200n

NOISE MEASUREMENT - CURRENT NOISE DENSITY
The test circuit shown in Figure 7 can be used to measure
current noise density. The formula relating the voltage output
to current noise density is:

= 10,000

Vs =±15V

FIGURE 8: Driving Large Capacitive Loads
V+

C2

C3

(~)2 _(40nv/VHzf

~08

O.1~
":"

Rs
where:
G = gain of 10000
Rs = 100kO source resistance
CAPACITIVE LOAD DRIVING AND POWER
SUPPLY CONSIDERATIONS
The OP-471 is unity-gain stable and is capable of driving
large capacitive loads without oscillating. Nonetheless, good
supply bypassing is highly recommended. Proper supply
bypassing reduces problems caused by supply line noise and
improves the capacitive load driving capability olthe OP-471.
In the standard feedback amplifier, the op amp's output resistance combines with the load capacitance to form a lowpass filter that adds phase shift in the feedback network and
reduces stability. A simple circuit to eliminate this effect is
shown in Figure 8. The added components, C1 and R3,
decouple the amplifier from the load capacitance and provide
additional stability. The values of C1 and R3 shown in Figure
8 are for load capacitances of up to 1000pF when used with
the OP-471.

VON

-=

R2

Cl

.,

.3

50n
C4

~-C-.--,~o~

~18
"':'"

"SEE TEXT

V-

PLACE SUPPLY DECOUPLING
CAPACITORS AT 01'-471

FIGURE 9: Pulsed Operation

",

In applications where the OP-471's inverting or noninverting
inputs are driven by a low source impedance (under 100!l) or
connected to ground, if V+ is applied before V-, orwhen V- is
disconnected, excessive parasitic currents will flow. Most

2-310 OPERAnONALAMPUFIERS

REV.S

OP-471
applications use dual tracking supplies and with the device
supply pins properly bypassed, power-up will not present a
problem. A source resistance of at least 100n in series with all
inputs (Figure 8) will limit the parasitic currents to a safe level
if V- is disconnected. It should be noted that any source
resistance, even 100n, adds noise to the circuit. Where noise
is required to be kept at a minimum, a germanium or Schottky
diode can be used to clamp the V- pin and eliminate the
parasitic current flow instead of using series limiting resistors.
For most applications, only one diode clamp is required per
board or system.
UNITY-GAIN BUFFER APPLICATIONS
When Rt :> 1000 and the input is driven with a fast, largesignal pulse (>1 V), the output waveform will look as shown in
Figure 9.

HIGH OUTPUT AMPLIFIER
The amplifier shown in Figure 13 is capable of driving 20V p _p
into a floating 400n load. Design of the amplifier is based on a
bridge configuration. A 1 amplifies the input signal and drives
the load with the help of A2. Amplifier A3 is a unity-gain
inverter which drives the load with help from A4. Gain of the
high output amplifier with the component values shown is 10,
but can easily be changed by varying R1 or R2.

rF_IG_U
__
R_E_1_0_:_L_O_W_N_0_i_s_e_A_m_p_l_if_ie_r__________________

--,~

+15V

V,N

0--+-----'-1

R3

200n

During the fast feedthrough-like portion of the output, the
input protection diodes effectively short the output to the
input, and a current, limited only by the output short-circuit
protection, will be drawn by the Signal generator. With Rt 2
5000, the output is capable of handling the current requirements (IL:> 20mA at 10V); the amplifier will stay in its active
mode and a smooth transition will occur.

R6
20011

When Rt > 3kO, a pole created by Rt and the amplifier's input
capacitance (2.6pF) creates additional phase shift and reduces
phase margin. A small capacitor (20 to 50pF) in parallel with
Rt helps eliminate this problem.

R9

200n

APPLICATIONS
LOW NOISE AMPLIFIER
A simple method of reducing amplifier noise by paralleling
amplifiers is shown in Figure 10. Amplifier noise, depicted in
Figure 11, is around 5nV/J'HZ @ 1kHz (R.T.I.). Gain for each
paralleled amplifier and the entire circuit is 100. The 200n
resistors limit circulating currents and provide an effective
output resistance of 50n. The amplifier is stable with a 10nF
capacitive load and can supply up to 30mA of output drive.
HIGH-SPEED DIFFERENTIAL LINE DRIVER
The circuit of Figure 12 is a unique line driver widely used in
professional audio applications. With ± 18V supplies the line
driver can deliver a differential signal of 30V p _p into a 1.5kll
load. The output of the differential line driver looks exactly
like a transformer. Either output can be shorted to ground
without changing the circuit gain of 5, so the amplifier can
easily be set for inverting, noninverting, or differential operation. The line driver can drive unbalanced loads, like a true
transformer.

REV. 8

R12

200n

Skn

FIGURE 11: Noise Density of Low Noise Amplifier, G = 100

OPERATIONALAMPLIFIERS

2~311

2-312 OPERATIONAL AMPLIFIERS

REV.B

OP-471
QUAD PROGRAMMABLE GAIN AMPLIFIER
The combination of the quad OP-471 and the DAC-8408, a
quad 8-bit CMOS DAC, creates a space-saving quad programmable gain amplifier. The digital code present at the
DAC, which is easily set by a microprocessor, determines the
ratio between the fixed DAC feedback resistor and the impedance the DAC ladder presents to the op amp feedback loop.
Gain of each amplifier is:

where n equals the decimal equivalent of the 8-bit digital
code present at the DAC. If the digital code present at the
DAC consists of all zeros, the feedback loop will be open
causing the op amp output to saturate. The 20Mll resistors
placed in parallel with the DAC feedback loop eliminates this
problem with a very small reduction in gain accuracy.

VOUT
256
v;;=--n-

FIGURE 14: Quad Programmable Gain Amplifier

+15V

>----;--I\"I'----'

FIGURE 4: Inverting Adder

FIGURE 2: Large-Signal Transient Response, ZL "" 2knl/75pF

.,

...,
.... "-ri'"""'
..., ',11~

As with most JFET -input amplifiers, the output of the SSM-2131
may undergo phase inversion if either input exceeds the specified input voltage range. Phase inversion will not damage the
amplifier, nor will it cause an internal latch-up.
Supply decoupling should be used to overcome inductance and
resistance associated with supply lines to the amplifier.

••

+1" Rs

For most applications, a 0.1!iF to 0.01!iF capacitor should be
placed between each supply pin and ground.

OFFSET VOLTAGE ADJUSTMENT
Offset voltage is adjusted with a 1Okn to 1OOkO potentiometer
as shown in Figure 3. The potentiometer should be connected
between pins 1 and 5 with its wiper connected to the V- supply.

FIGURE 5: Noninverting Adder

Alternately, Vos may be nulled by attaching the potentiometer
wiper through a 1MO resistor to the positive supply rail.

2-320 OPERA TlONAL AMPLIFIERS

REV. A

SSM-2131
CURRENT FEEDBACK

In a current feedback amplifier, a unity or low gain input buffer
drives a low impedance network. Any differential current that flows
in the collectors of the buffer (SSM-2131) outputtransistors is fed,
via the two complementary Wilson current mirrors A and B, to a
high impedance gain node where the high output voltage is
generated.

AUDIO POWER AMPLIFIER
The SSM-2131 can be used as the input buffer in a current feedback audio power amplifier as shown in Figure 6. This design is
capable of very good performance as shown in Figures 7, a and
9. At 1kHz and 50 watts output into an aQ load, the amplifier
generates just 0.002% THD, and is flat to 1 MHz. The slew rate
for the overall amplifier is more than adequate at 300VIllS and is
responsible for the very low dynamic intermodulation distortion
(DIM-1 00) that was measured at just 0.0017% at 50 watts output
into ohms. The total amplifier idling current for all tests was
approximately 300mA; the V+/V++ and V-/V- power supplies
were both ±40V; and the gain was set to 24.0.

This voltage is then buffered by a double emitter follower driver
stage and fed to the complementary power MOSFET output stage.
No RC compensation network to ground or output inductor is
required at the output of this amplifier to make it stable. As the
100kHz square wave response shows, there's no evidence of any
instability in the circuit. Capacitive load compensation can be
provided by the components marked TBO on the amplifier
schematic. These were not used in the test, however.

a

r

V+o--~---------------------~~_-_--_-_~_~_--_-_------------------.-------~--,

v+

2pF

POLY100V

20kU

I WILSON CURRENT
MIRROR A

ALL RESISTORS 1% MF 1i4 W
UNLESS OTHERWISE NOTED

33DIlF

100V
f MOSFET BIAS ADJUST

1N965B

r

MPSU10

(ON HEATSINK)

100U

IRF
240

1DOll
INPUT

1

OUTPUT

IXTMI
-=-

17P20

• MOUNTED ON
OUTPUT HEATSINK

WILSON CURRENT
I MIRRORB
100U

100.1.1 r
I

~o---~------------------------~-~-~-~-~-~-~-~~_~_~I----------------~------~

I

2"F

POLY

l00V

+

330"F
1'00V
V-

FIGURE 6: Audio Power Amplifier Schematic

REV. A

OPERA TfONAL AMPLIFIERS 2-321

2

SSM-2131

.,'_~
l

~.'.'_I§
O.OO~L..J....I.l.J,L1..k---'-L.....1...J....JL..LJ.1J.'.k-----:'2"
FREQUENCY (Hz)

FIGURE 7: THD vs. Frequency (at SOW into SQ).

35
30

t-

25

""

20

i

!

15

1.

...
-1.
-15

10

100

lk

10k

lOOk

1M

FREQUENCY (Hz)

FIGURE 8: Frequency Response

10M

One problem that is commonly encountered with current feedback amplifiers is that the mismatch between the two current
mirrors A and B forces a small bias current to appear at the input
buffer's output terminal. This bias current (usually in the range of
1-1 OOIlA) is multiplied by the feedback resistor of 750n and generates an output offset that could be tens of millivolts in magnitude. Matched transistors could be used in the current mirrors,
but these do not completely eliminate the output offset problem.
An inexpensive solution is to use a low power precision DC op
amp, such as the OP-97, to control the amplifier's DC characteristics, thus overriding the DC offset due to mismatch in the currentfeedback loop. The OP-97 acts as a current output DC-servo
amplifier that injects a compensating current into the emitters of
the low voltage regulator transistors (that power the SSM-2131)
to correct for current mirror mismatch. Since the OP-97 is set for
an overall input-to-output gain of24.0 as well, the DC output offset
is equal to the OP-97's Vos x 24.0, which is roughly 1 millivolt.
Thus, any offset trimming can be completely eliminated. Together,
the SSM-2131 and OP-97 provide a level of performance that
exceeds most of the requirements for audio power amplifers. The
driver circuit can handle several pairs of power MOSFETs in the
output stage if required. This topology can be used in circuits that
must deliver several hundreds of watts to a load by using higher
voltage transistors in the driver stage. Operation with rail voltages
in excess of ±1 OOV is possible. If more gain is desired, the SSM2131 input buffer can have its gain increased from the nominal
value of 1.5 used in this example to as much as 10 before its
bandVliidth drops below that of the current feedback section.
DRIVING A HIGH·SPEED ADC
The SSM-2131's open-loop output resistance is approximately
son. When feedback is applied around the amplifier, output resistance decreases in proportion to closed-loop gain divided by
open-loop gain (AvCL/AvOL)' Output impedance increases as
open-loop gain rolls-off with frequency. High-speed analog-todigital converters require low source impedances at high frequency. Output impedance at 1MHz is typically 5n for an SSM2131 operating at unity-gain. If lower output impedances are required, an output buffer may be placed at the output olthe SSM2131.

FIGURE 9: 100kHz Square Wave into SQ.

2-322 OPERATIONALAMPLIFIERS

REV. A

SSM-2131
HIGH-CURRENT OUTPUT BUFFER
The circuit in Figure 10 shows a high-current output stage forthe
SSM-2131 capable of driving a 750 load with low distortion.
Output current is limited by R1 and R2. For good tracking between the output transistors 01' 02' and this biasing diodes D,
and D2 , thermal contact must be maintained between the transistor and its associated diode. If good thermal contact is not
maintained, R1 and R2 must be increased to 5-60 in order to
prevent thermal runaway. Using 50 resistors, the circuit easily
drives a 750 load (Figure 11). Output resistance is decreased
and heavier loads may be driven by decreasing R, and R2 •
Base current and biasing for 01 and 02 are provided by two
current sources, the SSM-2131 and the JFET. The 2kO potentiometer in the JFET current source should be trimmed for optimum transient performance. The case of the SSM-221 0 should
be connected to V-, and decoupled to ground with a O.II1F capacitor. Compensation for the SSM-2131 's input capacitance is
provided by C c ' The circuit may be operated at any gain, in the
usual op amp configurations.

FIGURE 11: Output Buffer Large-Signal Response
operating at any gain including unity. Typically, an SSM-2131
will drive more than 250pF at any temperature. Supply decoupiing does affect capacitive load driving ability. Extra care should
be given to ensure good decoupling when driving capacitive
loads; between 111F and 1OI1F should be placed on each supply
rail.
Large capacitive loads may be driven utilizing the circuit shown
in Figure 12. R, and C 1 introduce a small amount of feedforward
compensation around the amplifier to counteract the phase lag
induced by the ouput impedance and load capacitance. At DC
and low frequencies, R, is contained within the feedback loop.
At higher frequencies, feedforward compensation becomes increasingly dominant, and R, 's effect on output impedance will
become more noticeable .

.....- - _......-CVOUT

v+
10f,lF

~
~

O.1J.1F
V,N

R,
VOUT

,0<>
D.1f.1F

,.51«>
AVCL = 1 + RF/Ro
R, AND", ARE ,-60,
SEE TEXT

BpF

v-

10nF

2k!l

RG

DRIVING CAPACITIVE LOADS
Best performance will always be achieved by minimizing input
and load capacitances around any high-speed amplifier. However, the SSM-2131 is guaranteed capable of driving a 100pF
capacitive load over its full operating temperature range while

C,

211pF

FIGURE 10: High-Current Output Buffer

REV. A

~
~

10J.lF

RF

2k!l

2k!l

FIGURE 12: Compensation for Large Capacitive Loads

OPERA TIONAL AMPLIFIERS 2-323

SSM-2131
When driving very large capacitances, slew rate will be limited
by the short-circuit current limit. Although the unloaded slew rate
is insensitive to variations in temperature, the output current limit
has a negative temperature coefficient, and is asymmetrical with
regards to sourcing.and sinking current. Therefore, slew rate into
excessive capacities will decrease with increasing temperature,
.
and will lose symmetry.

the SSM-2131. Amplifier bandwidth is reduced by the same gain
factor applied to offset voltage, however the SSM-2131 's 10MHz
gain-bandwic;:lth product results in no reduction of the CMOS
converter's multiplying bandwidth.
Individual DAC data sheets should be consulted for more complete descriptions of the converters and their circuit applications.

CAC OUTPUT AMPLIFIER
The SSM-2131 is an excellent choice for a DAC output amplifier, since its high speed and fast settling-time allow quick transitions between codes, even for full-scale changes in output level.
The DAC output capacitance appears at the operational amplifier inputs, and must be compensated to ensure optimal settling
speed. Compensation is achieved with capacitor C in Figure 13.
C must be adjusted to accountforthe DAC's output capacitance,
the op amp's input capacitance, and any stray capacitance at
the inputs. With a bipolar DAC, an additional shunt resistor may
be used to optimize response. This technique is described in
PMI's application AN-24.
FIGURE 14: DAC Output Amplifier Response (PM-7545 DAC)

c
20pF

NOTE: RF IS INTERNAL TO MOST CMOS DACS

FIGURE 13: DAC Output Amplifier Circuit
Highest speed is achieved using bipolar DACs such as PMI's
DAC-08, DAC-l 0 or DAC-312. The output capacitances of these
converters are up to an order of magnitude lower than their CMOS
counterparts, resulting in substantially faster settling-times. The
high output impedance of bipolar DACs allows the output amplifier
to operate in a true current-to-voltage mode, with a noise gain of
unity, thereby retaining the amplifier's full bandwidth. Offset
voltage has minimal effect on linearity with bipolar converters.
CMOS digital-to-analog converters have higher output capacitances and lower output resistances than bipolar DACs. This results in slower settling-times, higher sensitivity to offset voltages
and a reduction in the output amplifier's bandwidth. These tradeoffs must be balanced against the CMOS DAC's advantages in
terms of interfacing capability, power dissipation, accuracy levels and cost. Using the internal feedback resistor which is present on most CMOS converters, the gain applied to offset voltage
varies between 4/3 and 2, depending upon output code. Contributions to linearity error will be as much as 2/3 Vos' In a 10-volt
12-bit system, this may add up to an additional 1/5LSB DNL with

2-324 OPERA TIONAL AMPLIFIERS

COMPUTER SIMULATIONS
The following pages show the SPICE macro-model for the SSM2131 high-speed audio operational amplifier. This model was
tested with, and is compatible with PSpice* and HSPICE**. The
schematic and net-list are included here so that the model can
easily be used. This model can accommodate multiple frequency
poles and multiple zeroes, which is an advanced concept that
results in more accurate AC and transient responses necessary
for simulating the behavior of today's high-speed op amps. For
example, 8 poles and 2 zeroes are required to sufficiently simulate the SSM-2131, which this advanced model can easily accommodate.
Throughoutthe SSM-2131 macro-model, RC networks produce
the multiple poles and zeroes which simulate the SSM-2131 's
AC behavior. Each stage contains a pole or a pole-zero pair. The
stages are separated from each other by voltage-controlled current sources so that the poles and zero locations do not interact.
The only nonlinear elements in the entire model are two p-channel JFETs which comprise the input stage. Limiting the model to
almost entirely linear circuit elements significantly reduces
simulation time and simplifies model development.

"PSpice is a registered trademark of MicroSim Corporation.
"HSPICE is a tradmark of Meta-Software. Inc.

REV. A

SSM-2131
:;;SM-2131 MACRO-MODEL

©PM11989

: subckt SSM-2131 1 232 99 50
: INPUT STAGE & POLE AT 15.9 MHz
rl
r2
r3
r4
cjn
c2
jl
jos
eos
·1

l2

1
2
5

3
3
50
50

6
1
5

2
6

99

4

1

2

7
5

1
2
7

6

4
4

5Ell
5Ell
707.36
707.36
5E-12
7.08E-12
lE-3
4E-12
poly(1) 20 26 1 E-3 1
jx

IX

: POLE AT 53 MHz
r17
,18
cll
c12
g9
pl0

18
18
18
18
99
18

99
50
99
50
18
50

lE6
lE6
3E-15
3E-15
17261E-6
26171E-6

• POLE AT 53 MHz
r19
,20
c13
c14
gll
p12

19
19
19
19
99
19

99
50
99
50
19
50

lE6
lE6
3E-15
3E-15
18261E-6
26181E-6

: SECOND STAGE & POLE AT 45 Hz

:COMMON-MODE GAIN NETWORK WITH ZERO AT 100 kHZ

,5

9

,S

9

c3
c4
gl
g2
v2
v3
dl
d2

9
9
99

,21
,22
11
12
g13
p14

9
99
10
9
10

99
50
99
50
9
50
8
50
8

9

17S.84E6
17S.84E6
20E-12
20E-12
poly(l) 5 6 3.96E-3 1.4137E-3
poly(l) 6 5 3.96E-3 1.4137E-3
2.5
3.1
dx
dx

: POLE-ZERO PAIR AT 1.80 MHz/2.20 MHz

,7

11
r8 11
r9 11
rl0 11
c5 12
c6 13
g3 99
p4 11

99
50
12
13

99
50
11
50

lE6
lE6
4.5ES
4.5E6
16.1E-15
16.1E-15
9 2S lE-6
26 9 lE-S

: POLE-ZERO PAIR AT 1.80 MHz/2.20 MHz
,11
r12
r13
r14
c7
c8
g5
p6

14
14
14
14
15
16
99
14

99
50
15
16
99
50
14
50

lE6
lE6
4.5ES
4.5E6
lS.lE-15
16.1E-15
11 26 lE-6
2611 lE-6

: POLE AT 53 MHz
r15
r16
c9
cl0
g7
p8

REV. A

17
17
17
17
99
17

99
50
99
50
17
50

lES
lE6
3E-15
3E-15
1426 lE-S
26 14 lE-6

20
20
21
23
99
20

21
23
99
50
20
50

lE6
lE6
1.5915
1.5915
3 26 lE-ll
26 3 lE-ll

:POLE AT 79.6 MHz
,24
r25
c15
c16
g15
p16

25
25
25
25
99
25

99
50
99
50
25
50

lE6
lE6
2E-15
2E-15
1926 lE-6
26 19 lE-6

:OUTPUT STAGE
r26
r27
,28
,29
13
g17
g18
g19
g20
vS
v7
d5
d6
d7
d8
d9
dl0

2S
2S
27
27
27
30
31
27
50
28
27
25
29

99
99
50
50

99
50
99
50
32
50
50
99
27
27
29
28
25
30
31
30
31

111.1E3
111.1E3
90
90
2.5E-7
252711.1111E-3
272511.1111E·3
992511.1111E-3
2550 11.1111E-3
0.7
0.7
dx
dx
dx
dx
dy
dy

• MODELS USED
-model jx PJF(BETA=999.3E-S VTO=-2.000 IS=4E-ll)
-model dx
D(IS=lE-15)
-model dy D(IS=l E-15 BV=50)
-ends SSM-2131

OPERA TlONALAMPLIFIERS 2-325

•

2-326 OPERA TIONALAMPLIFIERS

REV. A

low Noise Audio
Operational Amplifier
SSM-2134 I

1IIIIIIII ANALOG

WDEVICES
FEATURES

GENERAL DESCRIPTION

• Very Low Input Noise Voltage ......••..•...... 3.5nV/.../Hz Typ
• Wide Small-Signal Bandwidth ......................... 1OM Hz Typ
• High Current Drive Capability
(10V RMS into 600n@V s =±18V)
• High Slew Rate •................................................. 13V/IlS Typ
• Wide Power Bandwidth ................................... 200kHz Typ
• High Open-Loop Gain ................................... 200VImV Typ
• Extended Industrial
Temperature Range ................................... -40°C to +85°C
• Direct Replacement for Industry Standard 5534AN

The SSM-2134 is a high performance low noise operational
amplifier which offers exceptionally low voltage noise of 3.5nVI
v'RZ. outstanding output drive capability. and very high smallsignal and power bandwidth. This makes the SSM-2134 an ideal
choice for use in high quality and professional audio equipment.
instrumentation. and control circuits.

The SSM-2134 is offered in an a-pin plastic DIP and its performance and characteristics are guaranteed over the extended industrial temperature range of -40°C to +85°C.

APPLICATIONS
•
•
•
•
•
•
•

The SSM-2134 is internally compensated for Av ~ 3. However.
the frequency response can be optimized with an external
compensation capacitor to enable the SSM-2134 to operate at
unity-gain or drive large capacitive loads.

High Quality Audio Amplifiers
Telephone Channel Amplifiers
Active Filter Designs
Microphone Preamplifiers
Audio Line Drivers
Low-Level Signal Detection
Servo Control Systems

PIN CONNECTIONS
BALANCE

S-PIN
EPOXY DIP
(P-Suffix)

SIMPLIFIED SCHEMATIC
BALANCE/COMP

BALANCE

COMP

r---~~~--------------~--~~------~r---------.-------~------~~v+

(+) INPUT

O-=---_......r----1---+---....,

(-) INPUT

0----*-............,[.

OUTPUT

SUBSTRATE

REV. A

OPERA TIONALAMPLIFIERS 2-327

I

SSM-2134
ORDERING INFORMATION t
OPERATING
TEMPERATURE
RANGE

PACKAGE
SSM2134P

8-Pin Plastic

-40°C to +85°C

Power Dissipation ........................................................ 300mW
Derate Above +24°C ............................................. 2.5mWrC
Short-Circuit Duration (Note 3) .................................. Indefinite
Operating Temperature Range ....................... -40°C to +85°C
Storage Temperature .................................... -60°C to + 150°C
NOTES:
1. The SSM-2134's inputs are protected by diodes. Current limiting resistors are

not used in order to achieve low noise. If differential input voltage exceeds ±O.6V,

ABSOLUTE MAXIMUM RATINGS
Supply Voltage .................. ,.. ,.. ,..... ,..... ,.. ,........... " ......... ,., ±22V
Differential Input Voltage (Note 1) .................................. ±O.5V
Input Voltage (Note 2) ...................................................... ±22V

the input current should be limited to lOrnA.
2. For supply voltages less than ±22V, the absolute maximum input voltage is
equal to the supply voltage.
3. Output maybe shorted to ground at Vs =±15V, TA = +25°C. Temperature andl
or supply voltages must be limited to ensuredissipation rating is not exceeded.

ELECTRICAL CHARACTERISTICS at Vs ; ±15V and T A ; +25°C, unless otherwise noted.
SSM·2134P
PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX
2

Input Offset Voltage

Vas

-40°C ~ T A ~ +85°C

0.3
0.4

Input Offset Current

los

-40'C ~ T A ~ +85°C

25

Input Bias Current

IB

-40'C ~ T A ~ +85'C

Large-Signal Voltage Gain

Ava

Supply Current

15

ISY

200

15

150

±12
±15

±13

No Load

(Note 1)

R'N

(Note 2)

Input Voltage Range

IVR

Common-Mode Rejection

CMR

mV

nA

nA

V/mV

4.5

V s =±15V, RL ~600n

Ise

Differential-Mode

2000

25

Output Short-Circuit Current
Input Resistance-

1500

500

RL ~600n, V o =±10V
-40°C ~ T A ~ +85°C

Va

300
400

350

RL ~600n, V o =±10V

Output Voltage Swing

3

UNITS

Vs = ±18V, RL ~ 600n

V cM =±12V

6.5

rnA
V

±16
65

rnA

30

100

kn

±12

±13

V

70

114

dB
~V!V

Power Supply Rejection Ratio

PSRR

Rise Time

t,

RL ~ 600n, C c = 22pF

20

ns

Overshoot

OS

C L = 100pF

20

%

Cc = 0, fa = 10kHz
C c = 22pF, fa = 10kHz

6
2.2

V/mV
MHz

ACGain
Unity-Gain Bandwidth

100

GBW

Cc = 22pF, C L = 100 P F

10

Slew Rate

SR

Cc=O
C c = 22pF

13

Full Power Bandwidth

BWp

Input Noise Voltage Density

e,

fo= 30Hz
fa = 1kHz

5.5

7.0

3.5

4.5

Input Noise Current Density

i

,

fa = 30Hz
fo= 1kHz

2.5
0.6

pAl-/Hz

0.7

dB

0.025

%

Va =±10V, C c = 22pF

95
200

Cc=O

Broadband Noise Figure

FN

Rs = 5kn, f = 10Hz to 20kHz

Total Harmonic Distortion

THD

Y'N = 3V RMS ' Av = +1000, RL = 2kn

NOTES:
1. Output may be shorted to ground at V s = ±15V, T A = +25'C. Temperature andl
or supply voltages must be limited to ensure dissipation rating is not exceeded.
2. Guaranteed by design.

2-328 OPERA TIONAL AMPLIFIERS

V/~s

6

kHz

nV/VHz

Specifications subject to change, Consult latest data sheet.

REV. A

SSM-2134
TYPICAL PERFORMANCE CHARACTERISTICS Continued

,·.omnmm

VOLTAGE NOISE DENSITY
vs FREQUENCY

CURRENT NOISE DENSITY
vs FREQUENCY

BROADBAND INPUT
NOISE VOLTAGE

~~4=P+Pm==+++P~~:r~~

TA= +25°C
VS=±15V

'02

1---H-t+I-l*---l-+1+1+Ht-~: ~ ::;

8

"

TA,=+25"C

,.

>
a

VS=±15V

w

"i!!
~

I
i ,.,.,

,.

,.

'~,~-U~~,._~~~,L.~~~~

••, L..-...J....Ju...LWIL_.L..I..L.L.I..LW...---'....LJu..&.JJII
100
1k
'Ok

FREQUENCY (Hz)

.

'.Hz.......

,0'

. /~
V

i8 ,.

. / "/

...

~ ,.,.,
,

. ,. ,.

,

Rs(Q)

CLOSED·LOOP GAIN
vs FREQUENCY

t,t,=.25OC

..zsoc

Vs=±1SV

'0'

i

'03

'20
TAS

~

,02

OPEN·LOOP GAIN
vs FREQUENCY

TOTAL INPUT NOISE DENSITY

,

...

,

FREQUENCY (Hz)

,.

.

"~

.. ,.

,

'\ '\..

10

100

1k

10k

100k

Ce=L. ~ V Ce.J,.,.,I
V('I Ce=·7pF
K'(

~,L.03~~~-'~"~~'''~-~'.~'-~''''
FREQUENCY (Hz)

..
..

,.
'20

Ii
~

f~= ....c
Vs=±15Y

r--

"

..

3 ..

PSR vs FREQUENCY

T.=ob·e
Vs st15Y

"

I

7D

•PO)
~

....

so

1M

10M

100M

•,.

,.

....!•

,

I"

40

20

~~

100k

100M

40

\\\
1Dk

1aM

CMR vs FREQUENCY

T.=+25°C
VS=(15V -

1k

1M

FREQUENCY (Hz)

'40

fREQUENCY (Hz)

REV. A

'\ ~

Ce=22pF

OUTPUT VOLTAGE SWING
vs FREQUENCY

,.
100

~=DPF

~

-4D

3D

•

""""

~

SOURCE RESISTANCE

'02

..

RL_1DIXl
CL_3OpF

i!!

V'THERMAL NOISE OF

~

Ii
~
z
C

T&=+25°C
Vs=±15Y

Vs=±1SV

.. = f::::;:: .......

3D
1k

10k

1C1C1k

FREQUENCY (Hz)

1M

'OM

1k

10k

lOOk

'M

FREQUENCY (Hz)

OPERA TlONAL AMPLIFIERS 2-329

SSM-2134
TYPICAL PERFORMANCE CHARACTERISTICS Continued

SLEW RATE vs

,.

COMPENSATION CAPACITOR

'2

r\

~
I........

2.

r---.

40

I'- t..

a.

I''00

Cc(pF)

TOTAL HARMONIC DISTORTION vs FREQUENCY

TOTAL HARMONIC DISTORTION vs FREQUENCY

."lIr:=-!·~PI~~~II~~~~Y"~~3~·~~""~.
'TA=+H-C_::
;"AL-2IUl
":

-,1,-

!:~:~:~il~i--'-~·~,+:~;!~;i~~~~·~,n:i~'~·~

•••1• . . ... ' .

TOTAL HARMONIC DISTORTION vs FREQUENCY

2-330 OPERA TIONALAMPLIFIERS

:; ..,

':iiij

*.

TOTAL HARMONIC DISTORTION vs FREQUENCY

REV. A

SSM-2134
TYPICAL PERFORMANCE CHARACTERISTICS Continued

INPUT COMMON-MODE
VOLTAGE vs SUPPLY VOLTAGE

OUTPUT VOLTAGE SWING
vs LOAD RESISTANCE

SUPPLY CURRENT

vs SUPPLY VOLTAGE

30

16

TA=+25°C

NEGATIVE

TA

Vs=±15V

14

POSITIVE

~

1

~

20

w

II

"~

~

g

~

10

;!;

~

TA=+2$°C

VS=I±1s~1

o

2

100

100k

lk
10k
LOAD RESISTANCE (0)

b

o

A-1-

V

posmVE-

'/

±lO

o

±30

±20

120

~

0.8

..........

~

0.3

"

Iii

~

I

""

I"

i'o..

g
0.2

0.1

±4

~

m

'-...I - , /

110
0.8

0.4

±6 ±8 ±lO ±12 ±14 H6 ±18 ±20
SUPPLY VOLTAGE (VOLTS)

CMR vs TEMPERATURE

Vs= ±15V

OA

a

±2

130

1.0
Vs=I±15V

:>

o

INPUT BIAS CURRENT
vs TEMPERATURE

O.S

L-- f.-

.- I-...... .-

SUPPLY VOLTAGE (VOLTS)

INPUT OFFSET VOLTAGE
vs TEMPERATURE

=+25°C

r---..~

i

iD

100

"'
"

90

-

Vs= ±15V

~

:0

......... i--

90

0.2
70

o
-55

-25

25

50

75

100

125

o

-25

-55

25

so

75

TEMPERATURE 1°C)

TEMPERATURE (OC)

PSR vs TEMPERATURE

SUPPLY CURRENT
vs TEMPERATURE

100

.0
-5S

125

-25

7.

so

2S

100

12S

TEMPERATURE rC)

SHORT-CIRCUIT CURRENT
vs TEMPERATURE
100

Vs='±15V

Vs='±15V

.,/

..-

""

.-...- ~

.-

- --

Vs= ±15V

80

i

i
0

25

50

75

TEMPERATURE (OC)

REV. A

i'o..

"

40

o

2

-25

'- ..........

60

~

0

-55

.........

100

125

-55

-25

25

50

75

TEMPERATURE «C)

100

125

-55

-25

25

50

f......

75

100

125

150

TEMPERATURE eel

OPERA T10NAL AMPLIFIERS 2-331

II

SSM-2134
APPLICATIONS INFORMATION
PREAMPLIFIER-RIAA/NAB COMPENSATION
+15V

O.22pF

INPUT~

>----.---0 OIITPUT

lRSI...
100kU

1MU:

NAB

1.1MU

16kn

O.003F

"SELECT TO PROVIDE SPECtFIED TRANSDUCER LOADING

OUTPUT NOISE O.8mVRMS (WITH INPUT SHORTED)

70

60

70

BODEPL~

60

I--'-~

50

50

i

40

~

30

'\.

"

..

{-ACTUAL
_RESPONSE _

.

~

30

"

~-

.. J.

.1.

::".~r:rUAL RESPONse -

BODE PLOT

"

'~

20

'0

'0'

~

iD

,-~

,

'0
102

103

1()4

FREQUENCY (Hz)

'0'

BODE PLOT OF RIAA EQUALIZATION AND THE
RESPONSE REALIZED IN AN ACTUAL CIRCUIT
USING THE SSM·2134

'0'

102

103

t()4

FREQUENCV (Hz)

'"

'05

BODE PLOT OF NAB EQUALIZATION AND THE
RESPONSE REALIZED IN THE ACTUAL CIRCUIT
USING THE SSM-2134

TEST CIRCUIT
FREQUENCY COMPENSATION
AND OFFSET VOLTAGE
ADJUSTMENT CIRCUIT

CLOSED-LOOP FREQUENCY RESPONSE
v.

J'OOpF

600n

v-

2-332 OPERA TlONAL AMPLIFIERS

REV. A

Dual, Low Noise, High-Speed
Audio Operational Amplifier (AvCL> 3)
SSM-2139 I

r.ANALOG
WDEVICES

FEATURES
• Ultra-Low Voltage Noise .................................. 3.2nV/.,I'Hi
• High Slew Rate ......................................................... 11 VI~s
• Excellent Gain Bandwidth Product ........................ 30MHz
• Low Supply Current (Both Amplifiers) •.••••..•..•.••.••.•.. 4mA
• Low Offset Voltage ................................................... 500~V
• High Gain ............................................................ 1,700V/mV
• Compensated for Minimum Gain of 3
• LowCost
• Industry Standard 8-Pln Plastic Dual Pinout
APPLICATIONS
• Microphone Preamplifiers
• Audio Line Drivers
• Active Filters
• Phono and Tape Head Preamplifiers
• Equalizers
ORDERING INFORMATION
PACKAGE
PLASnc
16-PIN

GENERAL DESCRIPTION
The SSM-2139 is a low noise, high-speed dual audio operational
amplifier which has been internally compensated for gains equal
to, or greater than three.
•
This monolithic bipolar op amp offers exceptional voltage noise
performance of 3.2nV/v'Hz (typical) with a guaranteed specification of only 5nV/v'HZ MAX@ 1kHz.
The high slew rate of 11 V/~s and the gain-bandwidth product of
30MHz is achieved without compromising the power consumption of the device. The SSM-2139 draws only 4mA of supply current for both amplifiers.
Continued

PIN CONNECTIONS

B-PlN

SOL

OPERATING
TEMPERATURE
RANGE

SSM2139P

SSM2139S

XINO'

• XINO = -40°C to +85°C
For availability on SOL package, contact your local sales office.

8-PIN
PLASTIC MINI-DIP
(P-Suffix)
16-PIN SOL
(S-Suffix)

SIMPLIFIED SCHEMATIC (One of two amplifiers is shown.)
r-.-------.-----~----_.--_.------------------------_.--~--~~~O~

OUT

-INo--~--+

~----------------~--~--------~--------~~--~--+-~--~-O~

REV. A

OPERATIONAL AMPLIFIERS 2-333

SSM-2139
These characteristics make the SSM-2139 an idea!.cho.iCe for
use in high quality professional audio equipment, instrumentation, and control circuit applications.
.
The low offset voltage Vos of 50011 V MAX (2011V typical) and offs~
voltage drift of only 2.511 V1°C MAX assures system accuracy and
eliminates the need for external Vos adjustments.
The SSM-2139's outstanding open-loop gain of 1,700,000 and
its exceptional gain linearity eliminate incorrectable system
nonlinearities and provides superior performance in high closedloop gain applications, such as preamplifiers.
The SSM-2139 is offered in an 8-pin plastic DIP and Small Outline (SO) package and its performance and characteristics are
guaranteed over the extended industrial temperature range of40°C to +85°C.

Input Voltage ......................•............................. Supply Voltage
Short-Circuit Duration ................................ Continuous
Storage Temperature Range .......................... -65°C to + 150C
Lead Temperature Range (Soldering, 60 sec) ............... 300°C
Junction Temperature (T) ............................. -65°C to +150°C
Operating Temperature Range
SSM-2139 (P, S) ............................................ -40°C to +85°C
O~put

PACKAGE TYPE

alA (Note t)

UNITS

a lc

8-Pin Plastic DIP (P)

96

37

°CIW

16-Pin SOL (5)

92

27

°elW

NOTES:
1. alA is specified for worst case mounting conditions, i.e., a.Ais specified fordevice
in socket for P-DIP package; a iA is specified for devihe soldered to printed
circuit board for SOL package.
2. The SSM-2139 inputs are protected by back-to-back diodes. Current limiting

resistors are not used in order to achieve low noise performance. If differential

ABSOLUTE MAXIMUM RATINGS

voltage exceeds ±1.0V, the input current should be limited to ±25mA.

Supply Voltage .................................................................. ±18V
Differential Input Voltage (Note 2) .................................. ±1.0V
Differential Input Current (Note 2) ................................. ±25mA

ELECTRICAL CHARACTERISTICS at V5 =±15V, T A =25°C, unless otherwise noted.
SSM-2139
PARAMETER

SYMBOL

CONDITIONS

Input Noise Voltage

9 np"p

O.IHzto 10Hz
(Note 1)

Input Noise
Voltage Density

en

Input Noise
Current Density

in

TYP

MAX

UNITS

80

200

nVp-p

fo = 10Hz
fo= 100Hz
fo= 1kHz
(Note 2)

3.6
3.2
3.2

6.5
5.5
5.0

fo = 10Hz
fO = 100Hz
fO= 1kHz

1.1
0.7
0.6
11

V/~s

30

MHz

130

kHz

Slew Rate

SR

Gain Bandwidth Product

GBW

fo= 100kHz

Full Power Bandwidth

BWp

Vo =27Vp_p
RL = 21<0 (Note 3)

Supply Current
(All Amplifiers)

ISY

No load

Total Harmonic Distortion

THO

RL =2kQ
VO =3V RMS ' fo= 1kHz

Input Offset Vo~age

Vos

Input Offset Current

los

Vc",=OV

Input Bias Current

18

Vc",=OV
Vo =±10V
RL= 10kQ

Avo

Output Voltage Swing

Vo
Vo +
V o-

RL ~2kQ
RL ~600Q

CMR

VCM =±12V

2-334 OPERATIONAL AMPLIFIERS

4

RL =2kQ
RL =600Q

5

nV/v'Hz

pAiv'Hz

6.5

0.002
20

Large-Signal
Voltage Gain

Common-Mode Rejection

MIN

mA

%
500

~V

50

nA

80

nA

1000
500

1700
900
900

V/mV

±12

±13.5
+13
-10

V

115

dB

RL~600Q

94

REV. A

SSM-2139
ELECTRICAL CHARACTERISTICS at Vs =±15V. TA =25°C. unless otherwise noted. Continued
SSM-2139
PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

Power Supply
Rejection Ratio

PSRR

Vs = ±4.5V to ±18V

105

120

dB

Input Voltage Range

IVR

±12.0

±12.5

V

20
40

rnA

(Note 4)

UNITS

Output Short·Circuit
Current

Isc

Input Resistance
Common·Mode

A1NCM

20

GO

Input Resistance
D'fferential·Mode

R'N

004

MO

Input Capacitance

C'N

3

pF

175

dB

Channel Separation

Sink

MAX

CS

Source

Va = 20V p_p
fo= 10Hz (Note 1)

125

NOTES:
1. Guaranteed but not 100% tested.
2. Sample tested.
3. BWp = SR/2n VPEAK .
4. Guaranteed by CMR test.

ELECTRICAL CHARACTERISTICS at Vs =±15V. -40°C S T AS 85°C. unless otherwise noted.
SSM-2139
PARAMETER

SYMBOL

CONDITIONS

Supply Current
(All Amplifiers)

ISY

No Load

Output Vonage Swing

Va

Large·Signal
Voltage Gain

Ava

MIN

TYP

MAX

UNITS

4.4

7.2

rnA

RL~2ka

±12

±13

V

Va = ±10V
RL = 10ka
RL =2kO

500
250

1400
700

VlmV

Input Offset Voltage

Vas

45

700

~V

Average Input
Offset Voltage Drift

TCVos

004

2.5

~V/'C

Input Offset Current

los

VCM=OV

1.5

60

nA

6

90

nA

Input Bias Current

I.

VCM=OV

Common·Mode
Rejection

CMR

VCM =±12V

Power Supply
Rejection Ratio

PSRR

Input Voltage Range

IVR

94

115

dB

Vs =±4.5to±18V

100

115

dB

(Note 1)

±12

±12.5

V

NOTES:
1. Guaranteed by CMR test.

REV. A

OPERA TIONAL AMPLIFIERS 2-335

II

SSM-2139
TYPICAL PERFORMANCE CHARACTERISTICS

VOLTAGE NOISE DENSITY
vs FREQUENCY

VOLTAGE NOISE DENSITY
vs SUPPLY VOLTAGE

O.lHz TO 10Hz NOISE

10

••

s;-

TA= +25OC

TA=+25"C
Ys =±15V

"

~

,~

o

"f
:.

4

w

~

r--....
,. po

z~

Hz

"~

AT 10kHz

g

3

..

w

AT 1kHz

0
z

:lI

~
g

10
TIME (SEC)

TA
1

10

1

,.

100

1

.

0

FREOUENCY (Hz)

"0

INPUT OFFSET VOLTAGE
vs TEMPERATURE

105E~1I
=
±15V

/V

ys=l t1SV
40

§l~"".g.~1
~I=

/

1--Hf+tHttt-H" 1ft CORNER =200Hz

100

lk

10k

....

-75

--50

-25

25

75

50

2
-75

100

V

-50

-25

25
~
TEMPERATURE re)

75

100

125

TOTAL SUPPLY CURRENT
vs SUPPLY VOLTAGE

T.I=.~C

!±15

Ys =±15V

V

.........
........

~

i-"""

I/~

INPUT BIAS CURRENT vs
COMMON-MODE VOLTAGE

VcM=OV

~

V

TEMPERATURE (OC)

INPUT OFFSET CURRENT
vs TEMPERATURE

o_

,/

I

FREQUENCY (Hz)

\Is

=±15V

VCM=OV

/

.. /

-10

10

Vs

/

~
i

0.1 '--'-J..J..J..LUl'::--'-J..J..J..LUl'--'-J..J..J.J.llJJ

INPUT BIAS CURRENT
vs TEMPERATURE

~

TA= +25"C

g

±20

"5

SUPPLY VOLTAGE (VOLTS)

CURRENT NOISE DENSITY
vs FREQUENCY
Vs

=+25OC

Vs =±15V

"'"

~

r~

n

-

~

m

TEMPERATURE COC)

2-336 OPERA TIONAL AMPLIFIERS

",.

,.

f

-

i
i

51--~---+--~--~

B

......,

~

~

2
-12.5 -10 -7.5 -5 -2.5

0

2.5

5

7.5

COMMON·MODE VOLTAGE (VOLTS)

10 12.5

3

2'---'---'---'--~

o

±5

±10

±15

±2D

SUPPLY VOLTAGE (VOLTS)

REV. A

SSM-2139
TYPICAL PERFORMANCE CHARACTERISTICS Continued

TOTAL SUPPLY CURRENT
vs TEMPERATURE

OPEN-LOOP GAIN
vsFREQENCY

.

I ••

TA=+2SOC

VS=±15V

".

--

. /V

..

""

60

'\..

""

""

~

~

~

~

~

~

•

m

1

10

100

1k

OPEN-LOOP GAIN
vs SUPPLY VOLTAGE

20

r-...

'\..

~

~
0

2.

3000

1000

V

••

/

±15

V~=±I'~

..

,

TA
Vs

13

----

.'"

t:

•. 1

'1.

~

..
0

10M

100M

15

=
=±15V

I.

THO= 1%

13

TA +2SOC
Vs

=

TA +25·C
Vs =+15V

POSITIVE

SWING

~
g

12

JY

!>

11

~

SWING

10

~EGATIVE

~ A,
Vo

6"

+25 0
±15V

,.

5
100.

1M

100

10M

H_

!:VRIIS =

Ii

10.

LOAD RESISTANCE (U)

FREQUENCY (Hz)

~
~

I--

1M

MAXIMUM OUTPUT VOLTAGE
vs LOAD RESISTANCE

TOTAL HARMONIC DISTORTION
vs FREQUENCY

SLEW RATE
vs TEMPERATURE

".. . /

100k

!

•,.

±2•

-8A

10k

FREQUENCY (Hz)

12

SUPPLY VOLTAGE (VOLTS)

"

....

10M 100M

/
±10

±5

""

1M

16

//

....

I.

1\

2'

~

"

,

28

....
~

lOOk

MAXIMUM OUTPUT SWING
vs FREQUENCY

5000

~

10k

"-

FREQUENCY (Hz)

TEMPERATURE ("C)

II

"-

40

2.

•_

TA~'~~
Vs=±15V

Vs =±15V

,
"
~ ••
"~
~ ••
g
••
iD

~ i--

CLOSED-LOOP GAIN
vs FREQUENCY

TOTAL HARMONIC DISTORTION
vs OUTPUT VOLTAGE

r--

•.5

r--r-,-....,-,.-r--r-,-....,

==

••1

f--+-+---+-+-f--+-+---+

-

-

AV= +100

.... 1--+-+--+-+-1--+-+--1

!: ::= --I--1-+-f--+--l

0.01

0.01

f-'O"-=r20"""'"ZT--i----1r-+-f--t--l

a:

l!...
i!
I;!

0.001

7

-75

-50

-25

0

25

50

75

TEMPERATURE ("C)

REV. A

100

125

150

1.

0.001
100

"

FREQUENCY (Hz)

10k 20k

I.....-'-_-'--1_..L..._'--'-_-'--I
1
OUTPUT VOlTAGE

Nt.. )

OPERA TIONAL AMPLIFIERS 2-337

SSM-2139
",
"11

-OUT

50n

",

",

2ka

",2ka

IN

",

",

10kn

2k"

",.
1ka

10kn

""

10kn

",

""

lkn

",

""

2ka

son

+OUT

",
tOkQ

FIGURE 1: High-Speed Differential Line Driver

APPLICATIONS INFORMATION
+15V

VIN o-~------'-I

200a

200a

200.0

HIGH·SPEED DIFFERENTIAL LINE DRIVER
The circuit of Figure 1 is a unique approach to a line driver circuit
widely used in professional audio applications. With ±18V supplies, the line driver can deliver a differential signal of 30Vp-p
into a 1.5kn load. The output of the differential line driver looks
exactly like a transformer. Either output can be shorted to ground
without changing the circuit gain of 5, so the amplifier can easily
be set for inverting, noninverting, or differential operation. The
line driver can drive unbalanced loads, like a true transformer.
LOW NOISE AMPLIFIER
A simple method of reducing amplifier noise is by paralleling
amplifiers as shown in Figure 2. Amplifier noise, depicted in Figure
3, is around 2nV/y'HZ@ 1kHz (R.T.I.). Gain for each paralleled
amplifier and the entire circuit is 1000. The 200n resistors limit
circulating currents and provide an effective output resistance
of50n.

SOkn

200a

SOka

FIGURE 2: Low Noise Amplifier

FIGURE 3: Noise Density of Low Noise Amplifier, G = tOOO

2-338 OPERA TlONAL AMPLIFIERS

REV. A

SSM-2139
VOLTAGE AND CURRENT NOISE
The SSM-2139 is a low noise, high-speed dual op amp, exhibiting a typical voltage noise of only 3.2nVfVHz@ 1kHz. The exceptionally low noise characteristics of the SSM-2139 is in part
achieved by operating the input transistors at high collector currents since the voltage noise is inversely proportional to the
square root of the collector current. Current noise, however, is
directly proportional to the square root of the collector current.
As a result, the outstanding voltage noise performance of the
SSM-2139 is gained at the expense of current noise performance, which is normal for low noise amplifiers.
To obtain the best noise performance in a circuit, it is vital to
understand the relationship between voltage noise (en)' current
noise (in)' and resistor noise (et ).

100

~

-

SSM~

./
1

En = "\j'(e n)2 + (in RS)2 = (et )2

..H1
RESISTOR

~~'~~ ~~LY
1k

lDO

TOTAL NOISE AND SOURCE RESISTANCE
The total noise of an op amp can be calculated by:

V

10k

lOOk

Rs - SOURCE RESISTANCE (U)

FIGURE 4: Total Noise vs. Source Resistance (Including
Resistor Noise) at 1kHz

where:
En = total input referred noise
en = op amp voltage noise

lDO

in = op amp current noise
et = source resistance thermal noise

i/

Rs = source resistance
The total noise is referred to the input and at the output would be
amplified by the circuit gain.
Figure 4 shows the relationship between total noise at 1kHz and
source resistance. For Rs < 1kQ, the total noise is dominated by
the voltage noise ofthe SSM-2139. As Rs rises above 1kQ, total
noise increases and is dominated by resistor noise rather than
by voltage or current noise of the SSM-2139. When Rs exceeds
20kQ, current noise of the SSM-2139 becomes the major contributor to total noise.
Figure 5 also shows the relationship between total noise and
source resistance, but at 10Hz. Total noise increases more
quickly than shown in Figure 4 because current noise is inversely
proportional to the square root of frequency. In Figure 5, current
noise ofthe SSM-2139 dominates the total noise when Rs > 5kQ.

V
~SSM-2139

...I'r

V
100

RESISTOR
NOIS~~~lY
1k

10k

lOOk

Rs - SOURCE RESISTANCE (U)

FIGURE 5: Total Noise vs. Source Resistance (Including
Resistor Noise) at 10Hz

From Figures 4 and 5, it can be seen that to reduce total noise,
source resistance must be kept to a minimum.

REV. A

OPERA TIONAL AMPLIFIERS 2-339

•

SSM-2139
Figure 6 shows peak-to-peak noise versus source resistance over
the 0.1 Hz to 10Hz range. Once again, at low values of Rs ' the
voltage noise of the SSM-2139 is the major contributor to peakto-peak noise with current noise the major contributor as Rs increases.

TABLE 1

Strain Gauge

<5000

Typically us!>d in low·frequency
applications.

For reference, typical source resistances of some signal sources
are listed in Table 1.

Magnetic
Tapehead,
Microphone

<1500n

Low I. very important to reduce
self·magnetization problems when
direct coupling is used. SSM·2139 I.
can be neglected.

Magnetic
Phonograph
Cartridge

<15000

Similar need for low I. in direct
coupled applications. SSM-2139 will not

For further information regarding noise calculations, see "Minimization of Noise in Op Amp Applications," Application Note AN-

15.

DEVICE

SOURCE
IMPEDANCE

COMMENTS

introduce any self-magnetization

problem.
Linear Variable

<15000

Used in rugged servo·feedback
applications. Bandwidth of interest is
400Hz to 5kHz.

Differential
Transformer

1000

NOISE MEASUREMENTSPEAK-TO-PEAK VOLTAGE NOISE
The circuit of Figure 7 is a test setup for measuring peak-to-peak
voltage noise. To measure the 200nV peak-to-peak noise
specification of the SSM-2139 in the 0.1 Hz to 10Hz range, the
following precautions must be observed:

/
SSM-2139

V

V
RESISTOR

'0

NOIS~~~LY
1k

'DO

10k

As - SOURCE RESISTANCE (J:!)

1. The device has to be warmed-up for at least five minutes. As
shown in the warm-up drift curve, the offset voltage typically
changes 211V due to increasing chip temperature after powerup. In the 1O-second measurement interval, these temperature-induced effects can exceed tens-of-nanovolts.

...

,

FIGURE 6: Peak-to-Peak Noise (0.1 Hz to 10Hz) vs. Source
Resistance (Includes Resistor Noise)

.,

2. For similar reasons, the device has to be well-shielded from
air currents. Shielding also minimizes thermocouple effects.

·3

.,

51>

.,

50

.,

c,

600kU

9090

2000

O.032p.F

=

":"

GAIN 50,000
Vs =±15Y

FIGURE 7: Peak-to-Peak Voltage Noise Test Circuit (0. 1Hz to 10Hz)

2-340 OPERA TlONAL AMPLIFIERS

REV. A

SSM-2139
3. Sudden motion in the vicinity of the device can also "feedthrough" to increase the observed noise.
4. The test time to measure 0.1 Hz to 1OHz noise should not exceed 10 seconds. As shown in the noise-tester frequencyresponse curve of Figure 8, the 0.1 Hz corner is defined by
only one pole. The test time of 10 seconds acts as a additional pole to eliminate noise contribution from the frequency
band below 0.1 Hz.

II

5. A noise-voltage-density test is recommended when measuring noise on a large number of units. A 10Hz noise-voltagedensity measurement will correlate well with a 0.1 Hz-to-1 OHz
peak-to-peak noise reading, since both results are determined
by the white noise and the location of the 1If corner frequency.
6. Power should be supplied to the test circuit by well bypassed
low-noise supplies, e.g. batteries. These will minimize output
noise introduced via the amplifier supply pins.

0.1

10

100

FREQUENCV (Hz)

FIGURES: O.1Hz to 10Hz Peak-to-Peak Voltage Noise Test
Circuit Frequency Response

CHANNEL SEPARATION TEST CIRCUIT
Sk"

> - - 4 - 0 V1 20Vp-p

5""
500<1

>---0 v,
CHANNEL SEPARATION = 20 tog (

REV. A

V2/~~ )

OPERA TIONAL AMPLIFIERS 2-341

2-342 OPERA TlONAL AMPLIFIERS

Audio AID Converters
Contents
Page

Audio AID Converters - Section 3 .............................................. 3-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
AD1876 - 16-Bit 100 kSPS Sampling ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
AD1878 - High Performance Stereo 16-Bit Oversampled ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
ADl879 - High Performance Stereo 18-Bit Oversampled ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
AD1885 - Low Cost Stereo 16-Bit Oversampled ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

AUDIO AID CONVERTERS 3--1

•

1>
...,
~

Selection Guide

~ Audio Analog-to-Digital Converters
~

Model

Res
Bits

Converter
Type

ADl876
ADl879
ADl878
ADl885

16
18
16
16

Sampling

(')

a
<:

hi:J::J
n:I
Vl

ka
ka
ka

'-0.05 dB Input, A-Weighted Filter

Channels

SNR
OdB-dB typ

THD+N
%typ

Input
Architecture

Input Range
Volts

Supplies
Volts

Power
mWtyp

Pins

Page

Single
Dual
Dual
Dual

No Spec
103
98
85

90'

Single-ended
Differential
Differential
Differential

±3V
±3V
±3 V
±3V

±5, ±12
±5
±5
±5

235
llOO
llOO
500

16
28
28
28

3-3
3-17
3-15
3-19

98
98
85

11IIIIIIII

l6-Bit 100 kSPS
Sampling ADC
AD1876 I

ANALOG

WDEVICES
FEATURES
Autocalibrating
0.002% THO
90 dB S/(N+DI
1 MHz Full Power Bandwidth
On-Chip Sample & Hold Function
2x Oversampling for Audio Applications
16-Pin DIP Package
Serial Twos Complement Output Format
Low Input Capacitance-typ 50 pF
AGND Sense for Improved Noise Immunity

FUNCTIONAL BLOCK DIAGRAM

AGNDSENSE 9
VREF

II

AGND

lEVEL TRANSLATORS

BUSY
DOUT ClK

PRODUCTION DESCRIPTION
The AD1876 is a 16-bit serial output sampling A/D converter
which uses a switched capacitor/charge redistribution architecture to achieve a 100 kSPS conversion rate (10 fLS total
conversion time). Overall performance is optimized by
digitally correcting internal nonlinearities through on-chip
autocalibration.

CAL
ClK

MICROCODED
CONTROllER

DOUT

AD1876

The circuitry of the ADI876 is partitioned onto two monolithic
chips, a digital control chip fabricated with Analog Devices'
DSP CMOS process and an analog ADC chip fabricated with
the BiMOS II process. Both chips are contained in a single
package.
The serial output interface requires an external clock and sample
command signal. The output data rate may be as high as 2.08
MHz, and is controlled by the external clock. The twos complement format of the output data is MSB first and is directly compatible with the NPC SMS805 digital decimation filter used in
consumer audio products. The ADI876 is also compatible with
a variety of DSP processors.
The AD1876 is packaged in a space saving 16-pin plastic DIP
and operates from + 5 V and ± 12 V supplies; typical power consumption is 235 mW. The digital supply (V DO) is isolated from
the linear supplies (VEE and Vee) for reduced digital crosstalk.
Separate analog and digital grounds are also provided.

REV. A

AUDIO AID CONVERTERS 3-3

AD1876-SPECIFICATIONS

(lmin tOlma••

Vee

= +12V ± 5%. VEE = -12V ± 5%. Voo = +5 V± 10%)1

Parameter

Min

TEMPERATURE RANGE

0

TOTAL HARMONIC DISTORTION (THDl'
-0.05 dB Input

AD1876J
Typ

Max

Units

70

·C

-88

1.0

dB
%
dB
%
dB
%

92

dB

92
90
73
70
34
31

dB
dB
dB
dB
dB
dB

-95
0.002
-78
0.01

-20 dB Input

0.004

-40

-60 dB Input
D-RANGE, -60 dB, A-WEIGHTED
SIGNAL-TO-NOISE AND DISTORTION (S/(N+D)) RATIO'
-0.05 dB Input, A-Weighted
-0.05 dB Input, 48 kHz Bandwidth
-20 dB Input, A-Weighted
- 20 dB Input, 48 kHz Bandwidth
-60 dB Input, A-Weighted
-60 dB Input, 48 kHz Bandwidth

83

PEAK SPURIOUS OR PEAK HARMONIC COMPONENT

-99

INTERMODULATION DISTORTION (IMD)4
2nd Order Products
3rd Order Products

-102
-98

FULL POWER BANDWIDTH

-89

dB
dB

1

VOLTAGE REFERENCE INPUT RANGEs (VREF)

3

MHz

5

ANALOG INPU'r
Input Range (VIN)
Input Impedance
Input Capacitance During Sample
Aperture Delay
Aperture Jitter

*
50*
6
100

POWER SUPPLIES
Operating Current
Icc
lEE
Inn
Power Consumption

9
9
3
235

dB

10.0

V

±VREF

V
pF
ns
ps

12

rnA

12

rnA
rnA

12
350

mW

NOTES
IVREF = 5.00 V; conversion rate = 96 kSPS; fIN = 1.06 kHz; VIN = -0.05 dB unless otherwise indicated. All measurements referred to a 0 dB
(10 Vpp) input signal. Values are post calibration.
'Includes first 19 harmonics.
'Minimum value of S/(N+D) corresponds to 5.0 V reference; typical values of S/(N+D) correspond to 10.0 V reference.
4f. = 1008 Hz; fb = 1055 Hz. See Definition of Specifications section and Figure 14.
'See Applications section for recommended voltage reference circuit and Figure 11 for performance with other reference voltage values.
·See Applications section for recommended input buffer circuit.
*For explanation of input characteristics, see "Analog Input" section.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test at worst case temperature. Results from those tests are used to calculate outgoing
quality levels. All min and max specifications are goaranteed. although only those shown in boldface are tested.

ORDERING GUIDE

Model

Temperature
Range

THD
dB

Package
Description

Package
Option*

ADl876JN

O·C to +70·C

-95

Plastic l6-Pin DIP

N-16

*N = Narrow Plastic DIP. For outline information see Package Information section.

3-4 AUDIO AID CONVERTERS

REV. A

AD1876
DIGITAL SPECIFICATIONS (1

min

= +12 V ±

5%, VEE

Test Conditions

Parameter
LOGIC INPUTS
VIH
High Level Input Voltage
Low Level Input Voltage
VIL
High Level Input Current
IIH
Low Level Input Current
IlL
Input Capacitance
CIN
LOGIC OUTPUTS
High Level Output Voltage
VOH
VOL

to 1m••, Vee

Low Level Output Voltage

= -12 V ±

5%, VDD

Min

= +5 V ±

10%)

Typ

2.4
-0.3
VIH = Voo
VIL = 0 V

-10
-10

IOH = 0.1 rnA
IOH = 0.5 rnA
IOL = 1.6 rnA

Voo-I V
2.4

Max

Units

0.8
+10
+10
10

V
V
J.1A
J.1A
pF

0.4

V
V
V

Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test at worst case temperature. Results from those tests are used to calculate outgoing
quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.

ABSOLUTE MAXIMUM RATINGS·
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . + 300°C, 10 sec
Vcc to VEE . . . . . . . . . . . . . . . . . . . . . -0.3 V to +26.4 V
Storage Temperature . . . . . . . . . . . . . . . . -60°C to + 100°C
Voo to DGND . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V
Vcc to AGND . . . . . . . . . . . . . . . . . . . . -0.3 V to +18 V
·Stresses greater than those listed under "Absolute Maximum Ratings" may
VEE to AGND . . . . . . . . . . . . . . . . . . . . -18 V to +0.3 V
cause permanent damage to the device. This is a stress rating only and
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
functional operation of the device at these or any other conditions above those
Digital Inputs to DGND . . . . . . . . . . . . . . . . . 0 V to 5.5 V
indicated in the operarional section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
Analog Inputs, VREF to AGND . . . . . . . . . (Vcc + 0.3 V) to
affect device reliability.
(VEE -0.3 V)
ESD SENSITIVITY _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
The ADI876 features input protection circuitry consisting of large "distributed" diodes and
polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and
fast, low energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the
AD1876 has been classified as a Category I Device.
Proper ESD precautions are strongly recommended to avoid functional damage or perfonnance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test
equipment, and discharge without detection. Unused devices must be stored in conductive foam
or shunts, and the foam discharged to the destination socket before devices are removed. For
further information on ESD precaution, refer to Analog Devices' ESD Prevention Manual.

TIMING SPECIFICATIONS

1
(Tmin

to 1m"., Vee

= +12 V ±

5%, VEE

Parameter

Symbol

Min

Sampling Rate2
Sampling Period2
Acquisition Time (Included in t s )
Calibration Time
CLK Period
CAL to BUSY Delay
CLK to BUSY Delay
CLK to DOVT Hold Time
CLKHIGH
CLKLOW
DouTCLKLOW
SAMPLE LOW to 1st CLK Delay
CAL HIGH Time
CLK to DOUT CLK
SAMPLE LOW

fs = lIts
ts = lIfs
tA
lcr
Ie
leALB
tCB
tco
tCH
leL
tOCL
tsc
tCALH
leDH
tSL

I

= -12 V ± 5%, VDD = +5 V ±
Typ

10

10%, VREF
Max

Units

100
1000

kSPS
I'-s
I'-S
Ie
ns
ns
ns
ns
ns
ns
ns
ns
Ie
ns
ns

2
5000
480
0
50

120

175

80

200

200

275

10

160
50
30
50
4
150
50

= 5.00 V)

NOTES
'See Figure 1 and Figure 2 and the Conversion Control and Autocalibration sections for detailed explanations of the above timing.
2Depends upon external clock frequency; includes acquisition time and conversion time. The minimum sampling rate/maximum sampling period is specified to
account for droop of the internal sample/hold. Operation at slower rates than specified may degrade performance.

REV. A

AUDIO AID CONVERTERS 3-5

•

AD1876
CAL

-.J

II

~~'~~---tC-A-l-B----------- tCT

BUSY

~

\I

I~ ~tl~ ~I

L

tCH tCl

j--tCB

CLK

Figure 1. AD1876 Calibration Timing

r-____

SAMPLE

~~I·~----------ts-(-~-~-)----~~r------------------------.,·I

1~.2-tA--1~......I=-"';;';;''''I--''-'"''~I~
~.'I.~:I~!l~~"-I-----j:t--. .-:. :. tA- I~!
Jt~tCB~CH.1 ~C~

BUSY

~ ~f---t-CB---------

ClK

PREVIOUS LSB

LSB

DOUTClK
Figure 2. Recommended AD1876 Conversion Timing

Definition of Specifications
NYQUIST FREQUENCY
An implication of the Nyquist sampling theorem, the "Nyquist
Frequency" of a converter is that input frequency which is onehalf the sampling frequency of the converter.

BANDWIDTH
The full power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.

TOTAL HARMONIC DISTORTION
Total harmonic distortion (THO) is measured as the ratio of the
rms sum of the first nineteen harmonic components to the rms
value of a I kHz full-scale sine wave input signal and is expressed in percent (%) or decibels (dB). For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.

INTERMODULATION DISTORTION (IMD)
With inputs consisting of sine waves at two frequencies, f. and
fb' any device with nonlinearities will create distortion products,
of order (m+n), at sum and difference frequencies of mf. ± nfb'
where m, n = 0, I, 2, 3 .... Intermodulation terms are those
for which m or n is not equal to zero. For example, the second
order terms are (f. + fb) and (f. - fb), and the third order
terms are (2f. + fb), (2f. - fb), (f. + 2fb) and (f. - 2fb ). The
IMD products are expressed as the decibel ratio of the rms sum
of the measured input signals to the rms sum of the distortion
terms. The two signals applied to the converter are of equal amplitude, and the peak value of their sum is -0.05 dB from full
scale. The IMO products are normalized to a 0 dB input signal.

SIGNAL-TO-NOISE PLUS DISTORTION RATIO
Signal-to-noise plus distortion (SIN + 0) is defined to be the ratio of the rms value of the measured input signal to the rms sum
of all other spectral components below the Nyquist frequency,
including harmonics but excluding dc.
D·RANGE DISTORTION
O-range distortion is the ratio of the distortion plus noise to the
signal at a signal amplitude of -60 dB. In this case, an A·
weight filter is used. The value specified for O-range perfor·
mance is the ratio measured plus 60 dB.

APERTURE DELAY
Aperture delay is the time required after SAMPLE. is taken
LOW for the internal sample-hold of the ADl876 to open, thus
holding the value of VJN.
APERTURE JITTER
Aperature jitter is the variation in the aperture delay from
sample to sample.

3-6 AUDIO AID CONVERTERS

REV; A

AD1876
PIN DESCRIPTION

Pin
No.

Name

Type

Description

SAMPLE

DI

VIN Acquisition Control Pin. During conversion, SAMPLE controls the state of the internal
Sample-Hold Amplifier and initiates conversion (see "Conversion Control" paragraph).
During calibration, SAMPLE is active HIGH, forcing DOUT (Pin 3) LOW. If SAMPLE is
LOW during calibration, DOUT will output diagnostic information (See "Autocalibration"
paragraph. )

2

CLK

DI

Master Clock Input. The ADI876 requires 17 clock pulses to execute a conversion. CLK is
also used to derive DOUT CLK (Pin 14). During calibration, 5000 clock pulses are applied.

3

DouT
DGND

DO

Serial Output Data, Twos Complement format.

4

P

Digital Ground.

5

Vee

P

6

NIC

7

NIC

8

AGND

PIAl

Analog Ground.

9

II

+ 12 V Analog Supply Voltage.
No Connection.
No Connection.

AGND SENSE

AI

Analog Ground Sense.

10

VIN

AI

Analog Input Voltage, referred the AGND SENSE.

11

VREF

AI

External Voltage Reference Input, referred to AGND.

12

VEE

P

-12 V Analog Supply Voltage.

13

Voo

P

+5 V Logic Supply Voltage.

14

DouTCLK

DO

The rising edge of DOUT CLK may be used to latch DouT (Pin 3). DOUT CLK is derived
fromCLK.

IS

BUSY

DO

Status Line for Converter. Active HIGH, indicating a conversion or calibration in progress.

16

CAL

DI

Calibration Control Pin (asynchronous).

Type:

AI = Analog Input.
DI = Digital Input.
DO = Digital Output.
P =- Power.

SAMPLE

CAL
BUSY

ClK
DOUT
DGND

DOUT elK
AD1876
TOP VIEW

VREF
AGNO

VOO

(Not to Scale)
VCC

VEE

NIC

VREF

NIC

VIN

BUSY
OOUTClK
CAL

DOUT

AGNDSENSE

AGND

ClK

Package Pinout

AD1876

Functional Block Diagram

REV. A

AUDIO AID CONVERTERS 3-7

AD1876
FUNCTIONAL DESCRIPTION
The AD1876 is a 16-bit analog-to-digital converter including a
sample/hold input circuit, successive approximation register,
ground sensing circuitry, serial output port and a microcon;
troller based autocalibration circuit. These functions are segmented onto two monolithic chips, an analog signal processor
and a digital controller. Both chips are contained within the
AD1876 package.
The ADl876 employs a successive-approximation technique to
determine the value of the analog input voltage. However, instead of the traditional laser-trimmed resistor-ladder approach,
the ADl876 uses a capacitor-array, charge-redistribution technique. An array of binary-weighted capacitors subdivides the
input value to perform the actual analog to digital conversion.
This capacitor array also serves a samplelhold function without
the need for additional external circuitry.
The autocalibration circuit within the AD1876 employs a microcontroller and calibration DAC to measure and compensate capacitor mismatch errors. As each error is determined, its value
is stored in on-chip memory (RAM). Subsequent conversions
use these RAM values to improve conversion accuracy. The autocalibration routine may be invoked at any time. Autocalibration insures high performance while eliminating the need for any
user adjustments, and is described in detail below.
The microcontroller controls all of the various functions within
the AD1876. These include the actual successive approximation
routine, the autocalibration routine, the sample/hold operation,
and the serial data transmission.
AUTOCALIBRATION
The ADI876 achieves rated performance without the need for
user trims or adjustments. This is accomplished through the use
of on-chip autocalibration.
In the autocalibration sequence, sample/hold offset is nulled by
internally connecting the input circuit to the ground sense circuit. The resulting offset voltage is measured and stored in
RAM for later use. Next, the capacitor representing the most
significant bit (MSB) is charged to the reference voltage. This
charge is then inverted and shared between the MSB capacitor
and one of equal size composed of all the least significant bits.
The difference in the summation of the charges in each of the
equally sized capacitors represents the amount of capacitor mismatch. A calibration D/A converter (DAC) adds an appropriate
value of error correction voltage to cancel the mismatch. This
correction factor is also stored in RAM. This process is repeated
for each of the capacitors representing the remaining bits. The
accumulated values in RAM are then used during subsequent
conversions to adjust conversion results.
As shown in Figure I, when CAL is taken HIGH the ADI876
internal circuitry is reset, the BUSY pin is driven HIGH and
the part prepares for calibration. This is a 'hard' reset and will
interrupt any conversion or calibration currently in progress. In
order to guarantee that all internal undefined states are cleared,
the CAL pin should be held HIGH for at least 4 CLK cycles.
Actual calibration begins when the CAL pin is taken LOW and
completes in less than 5000 clock cycles or about 2.5 msec with
a continuous 500 nsec clock.
During calibration the SAMPLE pin adopts an alternative function. If it is held LOW, DOUT provides diagnostic test information (not intended to be used by the customer). If SAMPLE is
held HIGH, DOUT will be forced LOW. In either case, DOUT
3-8 AUDIO AID CONVERTERS

CLK will continue pulsing. Since the SAMPLE pin has no control over the actual calibration process, normal conversion timing may also be used for calibration. In this case, however, the
DOUT pin will output test information during those periods that
SAMPLE is LOW. BUSY going LOW will always indicate the
end of calibration.
A calibration sequence should be followed by one "dummy"
conversion to clear the internal circuitry of the AD1876 in order
to guarantee subsequent conversion accuracy.
In most applications, it is sufficient to calibrate the AD1876
only upon power-up, in which case care should be taken that
the power supplies and voltage reference have stabilized first.

CONVERSION CONTROL
The AD1876 is controlled by two signals: SAMPLE and CLK,
as shown in Figure 2. It is assumed that the part has been calibrated and the digital I/O pins have the levels shown at the start
of the timing diagram.
A conversion consists of an input acquisition followed by 17
clock pulses which are required to run the 16-bit internal successive approximation routine. The analog input is acquired by
taking the SAMPLE line HIGH for a minimum acquisition time
of t A. The actual sample taken is the voltage present on VIN at
the instant the SAMPLE pin is brought LOW. Care should be
taken to ensure that this negative edge is well defined and jitter
free to reduce the uncertainty (noise) in ac signal acquisition.
On that edge the ADI876 commits itself to the initiated conversion-the input at VIN is disconnected from the internal capacitor array and the SAMPLE input will be ignored until the
conversion is completed (i.e., BUSY goes LOW). After a delay
of at least tse (SAMPLE to eLK setup) the 17 eLK cycles are
applied. BUSY is asserted after the first positive edge on CLK
and reset after the 17th. Both the DOUT and the DOUT CLK
outputs are generated in response to the rising edges of valid
CLK pulses. As indicated in the timing diagram, the 2s complement output data is presented MSB first. This data may be captured with the rising edge of DOUT CLK or the falling edge of
CLK provided leH ;,: leDH. The ADI876 will ignore CLK after
BUSY has gone LOW and not change DOUT or DOUT CLK
until a new sample is acquired. SAMPLE will no longer be ignored after BUSY goes LOW, and so an acquisition may be initiated even during the HIGH time of the 17th CLK pulse for
maximum throughput rate while enabling full settling of the
sample/hold circuitry. Note that if SAMPLE is already HIGH
when BUSY goes LOW, then an acquisition is immediately initiated and tA starts from that time.
During signal acquisition and conversion, care should be taken
with the logic inputs to avoid digital feedthrough noise. It is not
recommended that CLK be running during VIN sampling. If a
continuous CLK is used, then the user must avoid eLK edges
at the instant of disconnecting VIN' i.e., the falling edge of
SAMPLE (see the tse specifications). The LOW level time of
CLK (teLl should be at least lOOns to avoid the negative edge
transition disrurbing the internal comparator's settling (whose
decision is latched on the positive edge of each valid CLK). For
the same reason, it is also not recommended that the SAMPLE
pin change state during conversion (i.e., until after BUSY returns LOW).
Internal de error terms such as comparator voltage offset are
sampled, stored on internal capacitors and used to correct for
their corresponding errors when needed. Because these voltages

REV. A

AD1876
are stored on capacitors, they are subject to leakage decay and
so require refreshing. For this reason the part is required to be
run continuously-i.e., there is a minimum ts specification. If
the part has been idle for too long (i.e., ts has expired) then a
dummy conversion cycle is required to refresh these correction
voltages.
BUSY is HIGH during a conversion and goes LOW when the
conversion is completed. The twos complement output data is
presented MSB first, with MSB data valid on the rising edge of
the second DOUT CLK pulse. Subsequent data is valid on rising
edges of subsequent DOUT CLK pulses. Table I illustrates the
ADI876 output coding.
V IN

Output Code

-Full Scale
- Full Scale + I LSB
Midscale - I LSB
Midscale
Midscale + I LSB
Full Scale - I LSB
Full Scale

100... 00
100... 01
111. .. 11
000 ... 00
000 .... 01
OIl. .. 10
OIl. .. 11

Table I. Serial Output Coding Format (Twos Complement)
A simple method for generating the required signals for the
ADI876 is to connect one or more ADI876s to an NPC SM5805
digital filter. This device supplies all signals required to operate
the ADI876 at a 96 kHz sample rate, which is 2 x Fs for audio
applications. This is more fully discussed in the applications sec·
tion of this data sheet, accompanied by Figures 9 and 10.

APPLICATIONS
POWER SUPPLIES AND DECOUPLING
The ADI876 has three power supply input pins. VEE and Vee
provide the supply voltages to operate the analog portions of
the ADI876 including the ADC and SHA. Vnn provides the
supply voltage which operates the digital portions of the
AD 1876 including the serial output port and the autocalibration
controller.
Decoupling capacitors should be used on all power supply pins.
These capacitors should be placed as close as possible to the

package pins as well as the ground connections. The logic supply (V DO) should be decoupled to digitill common (DGND)
with a 0.1 iJoF ceramic capacitor, and the analog supplies (VEE
and Vee) should be decoupled to analog common (AGND) with
4.7 iJoF and 0.1 iJoF tantalum capacitors in parallel, represented
by CI. An effort should be made to minimize the trace length
between the capacitor leads and the respective converter power
supply and common pins. The recommended decoupling scheme
is illustrated in Figure 3.
As with most high performance linear circuits, changes in the
power supplies can produce undesired changes in the performance of the circuit. Analog Devices recommends that well
regulated power supplies with less than I % ripple be incorporated into the design of any system using these devices.
BOARD LAYOUT
Designing with high resolution data converters requires careful
attention to board layout. Trace impedance is a significant issue.
A 1.22 mA current through a 0.5 n trace will develop a voltage
drop of 0.6 mY, which is 4 LSBs at the 16 bit level for a 10 V
full-scale span. In addition to ground drops, inductive and capacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital signals. Finally, power supplies need to be decoupled in order to
filter ac noise.
Analog and digital signals should not share a common return
path. Each signal should have an appropriate analog or digital
return routed close to it. Using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise.
Wide PC tracks, large gauge wire, and ground planes are highly
recommended to provide low impedance signal paths. Separate
analog and digital ground planes are also desirable, with a single
interconnection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them, if at all, only at right angles. A solid analog
ground plane around the AD 1876 will isolate large switching
ground currents. For these reasons, the use of wire wrap circuit
construction is not recommended; careful printed circuit construction is preferred.
GROUNDING
The ADI876 has three grounding pins, designated ANALOG
GROUND (AGND), DIGITAL GROUND (DGND) and ANALOG GROUND SENSE (AGND SENSE). The analog ground
pin is the "high quality" ground reference point for the device.
The analog ground pin should be connected to the analog common point in the system.
AGND SENSE is intended to be connected to the input signal
ground reference point. This allows for slight differences in level
between the analog ground point in the system and the input
signal ground point. However, no more than 100 mV is recommended between the analog ground pin and the analog ground
sense pin for specified performance.

SYSTEM
DIGITAL
COMMON

SYSTEM
ANALOG
COMMON

Cl

12V -12V

The digital ground pin is the reference point for all of the digital
signals that operate the AD1876. This pin should be connected
to the digital common point in the system. As illustrated in
Figure 3, the analog and digital grounds should be connected
together at one point in the system.

Figure 3. Grounding and Decoupling the AD1876

REV. A

AUDIO AID CONVERTERS 3-9

•

AD1876
VOLTAGE REFERENCE
The AD 1876 requires the use of an external voltage reference.
The input voltage range is determined by the value of the reference voltage; in general, a reference voltage of n volts produces
an input range of ±n volts. Signal-to-noise performance is increased proportionately with input signal range. The AD1876 is
specified with as. 0 V reference and an analog input of ± 5 V.
In the presence of a fixed amount of system noise, increasing
the LSB size (which results from increasing the reference voltage) will increase the effective S/(N + D) performance for input
values below the point where input distortion occurs. Figure 11
illustrates S/(N + D) as a function of input amplitude and reference voltage.
During a conversion, the switched capacitor array of the
ADI876 presents a dynamically changing current load at the
voltage reference as the successive-approximation algorithm cycles through various choices of capacitor weighting. The output
impedance of the reference circuitry must be low so that the
output voltage will remain sufficiently constant as the current
drive changes. In most applications, this requires that the output of the voltage reference be buffered by an amplifier with
low impedance at relatively high frequencies. A (10 fJ.F or
larger) capacitor connected between VREF and AGND will reduce the demands on the reference by decreasing the magnitude
of high frequency components.
The following two sections represent typical design approaches.
VOLTAGE REFERENCE-AUDIO APPLICATIONS
Audio applications require optimal ac performance over a relatively narrow temperature range, with low cost being important.
Figure 4 shows one such approach towards attaining these goals.
A voltage reference, consisting of a Zener diode, capacitor, resistor and op amp with typical component values, is shown. This
simple circuit has the advantage of low cost, but the reference
voltage value is sensitive to changes in the + 12 V supply. Additionally, changes in the Zener value due to temperature variations will also be reflected in the reference voltage. RaPTION
may be required for other component selections if the Zener
requires more current than the op amp can supply.

range, the AD586L grade exhibits less than a 2.25 mV output
change from its initial value at + 25°C. A noise-reduction capacitor, eN' reduces the broadband noise of the AD586 output,
thereby optimizing the overall performance of-the AD1876.
+12V

1

Figure 5.
For higher performance needs, the AD588 reference provides
improved drift, low noise, and excellent initial accuracy. The
AD588 uses a proprietary ion-implanted buried Zener diode in
conjunction with laser-trimmed thin-film resistors for low offset
and gain. The AD588 output is accurate to 0.65 mV from its
value at + 25°C over the ooe to + 70°C range. The circuit shown
in Figure 6 includes a noise-reduction network on Pins 4, 6 and
7. The I fJ.F capacitors form low pass filters with the internal
resistance of the ADS 88 and external 3.9 kfl resistor. This reduces the wide-band (to I MHz) noise of the AD588, providing
optimum performance of the AD1876.

R OPTION

Figure 6.

Figure 4. Low Cost Voltage Reference Circuit
VOLTAGE REFERENCE-PRECISION MEASUREMENT
APPLICATIONS
In applications other than audio, parameters such as low drift
over temperature and static accuracy are important. Figure 5
shows a voltage reference circuit featuring the 5 V AD586. The
AD586 is a low cost reference which utilizes a buried Zener architecture to provide low noise and drift. Over the ooe to +70°C

3-10 AUDIO AID CONVERTERS

ANALOG INPUT
As previously discussed, the analog input voltage range for the
AD1876 is ±VREF • For purposes of ground drop and commonmode rejection, the VIN and VREF inputs each have their own
ground. VREF is referred to the local analog system ground
(AGND), and VIN is referred to the analog ground sense pin
(AGND SENSE) which allows a remote ground sense for the
input signal. If AGND SENSE is not used, it should be connected to the AGND pin at the package. The AGND SENSE
pin is intended to be tied to potentials within 100 mV of AGND
to maintain specified performance.
The AD1876 analog inputs (V IN , VREF and AGND SENSE)
exhibit dynamic characteristics. When a conversion cycle begins,
each analog input is connected to an internal, discharged 50 pF
capacitor which then charges to the voltage present at the corresponding pin. The capacitor is disconnected when SAMPLE is

REV. A

AD1876
taken LOW and the stored charge is used in the subsequent

. AID conversion. In order to limit the demands placed on the
external source by this high initial charging current, an internal
buffer amplifier is employed between the input and this capacitance for a few hundred nanoseconds. During this time the
input pin exhibits typically 20 kO input resistance, 10 pF input capacitance and ±40 !LA bias current. Next, the input is
switched directly to the now precharged capacitor and allowed
to fully settle, after which SAMPLE is taken LOW. During this
time the input sees only a 50 pF capacitor. Once the sample is
taken, the input is internally floated so that the external input
source sees a very high input resistance and a parasitic input
capacitance of typically only 2 pF. As a result, the only dominant input characteristic which must be considered is the high
current steps which occur when the internal buffers are switched
in and out.
In most cases, it is desirable to use external op amps to drive
the AD1876. For ac applications where low cost and low distortion are desired, the AD711 may be used as shown in Figure 7.
Another option is the 5532/5534 series. Care should always be
taken with op amp selection-many available op amps do not
meet the necessary low distortion requirements with even moderate loading conditions.

The test procedure consists of the following steps. First, the
device is calibrated by its on-board controller. Next, the'device
under test digitizes the input waveform. This conversion is performed at a 96 kSPS rate and transmits the resulting serial data
to the tester. The tester performs an FFT on the test data and
determines the actual performance of the device.
AC PERFORMANCE
Using the aforementioned test methodology, ac performance
of the ADI876 is measured. AC parameters, which include
S/(N + D), THD, etc., reflect the AD1876's effect on the spectral content of the analog input signal. Figures II through 15
provide information on the AD 1876's ac performance under a
variety of conditions.
As a general rule, averaging the results from several conversions
reduces the effects of noise and, therefore, improves such parameters as S/(N+D) and THD. ADI876 performance is optimized by operating the device at its maximum sample rate of
100 kSPS and digitally filtering the resulting bit stream to the
desired signal bandwidth. This succeeds in distributing noise
over a wider frequency range, thus reducing the noise density in
the frequency band of interest. This subject is discussed in the
following section.
OVERSAMPLING AND NOISE FILTERING
The Nyquist rate for a converter is defined as one-half its sampling rate. This is established by the Nyquist theorem, which
requires that a signal be sampled at a rate corresponding to at
least twice its widest bandwidth of interest in order to preserve
the information content. Oversampling is a conversion technique
in which the sampling frequency is an integral (2 or more) multiple of twice the frequency bandwidth of interest. In auclio applications, the ADl876 can operate at a 2x oversampling rate.
In quantized systems, the information content of the analog input is represented in the frequency spectrum from dc to the
Nyquist rate of the converter. Within this same spectrum are
higher frequency aliased noise components. Antialias, or lowpass, filters are used at the input to the ADC to remove the portion of these noise components attributed to high frequency
analog input noise. However, wideband noise contributed by the
ADI876 will not be reduced by the antiaIias filter. The ADI876
contributed noise is evenly distributed from dc to the Nyquist
rate, and this fact can be used to minimize its overall effect.

Figure 7.

TESTING THE ADl876
Analog Devices employs a high performance mixed signal VLSI
tester to verify the electrical performance of every AD1876. The
test system consists of two main sections, an input signal generator and a digital data and control section.
The stimulus section is responsible for providing a high purity,
noise-free, band limited tone to the input of the device. This
input frequency is 1.06 kHz. The test tone is passed through a
bandpass filter to remove distortion products and then buffered
by a high performance op amp. An external 5.000 V reference
voltage is also supplied by this section.
The control section of the test equipment provides an external
clock and the control signals for calibration, conversion and data
transmission. This section of the tester also contains the processing unit that calculates the actual performance of the device under test.

REV. A

The ADl876 contributed noise effects can be reduced by oversampling-sampling at a rate higher than defined by the
Nyquist theorem. This spreads the noise energy over a clistribution of frequencies wider than the frequency band of interest,
and by judicious selection of a digital filter, noise frequencies
outside the bandwidth of interest may be eliminated. The process of quantization inherently produces noise, known as quantization noise. The magnitude of this noise is a function of the
resolution of the converter, and manifests itself as a limit to the
theoretical signal-to-noise ratio achievable. This limit is described by S/(N+D) = (6.02 n + 1.76 + 10 log Fs/2 Fa) dB,
where n is the resolution of the converter in bits, Fs is the sampling frequency, and Fa is the signal bandwidth of interest. For
auclio bandwidth applications, the ADl876 is capable of operating at a 2 x oversample rate (96 kSPS), which typically produces
an improvement in S/(N + D) of 3 dB compared with operating
at the Nyquist conversion rate of 48 kSPS. Oversampling has
another advantage as well; the demands on the antialias filter are

AUDIO AID CONVERTERS 3--11

II

AD1876
lessened. In summary, system performance is optimized by run·
ning the ADI876 at or near its maximum sampling rate of 100
kHz and digitally filtering the resulting spectrum to eliminate
undesired frequencies.
DSP INTERFACE
Figure 8 illustrates the use of the Analog Devices ADSp-2101
digital signal processor with the ADl876. The ADSP-2101 FO
(flag out) pin of serial port I (SPORT 1) is connected to the
SAMPLE line and is used to control acquisition of data. The
ADSp-2101 timer is used to provide precise timing of the FO
pin.

SAMPLE

FO

SERIAL
PORT"

elK

{~

DOUT

DRO
RFSO
DTO
TFSO

SIGNAL PROCESSING

An audio spectrum analyzer can be produced by combining an
ADl876 and an ADSp-2101 signal processing microcomputer.
This system can analyze signals from dc to 50 kHz depending
on the sample rate. This is ideal for applications such as audio
analysis, but could also be applied to vibration analysis as well.
AUDIO DELAY LINE
A high performance, l6-bit stereo delay line can be constructed
from two ADI876 audio ADCs, a signal processing microcom·
puter and two ADl856 audio DACs. Depending on the length
of the internal buffer which produces the delay, a variable delay
is possible. Other applications are also possible with only a
change in software. For example, a reverb or echo effect could
be generated as well.

AD1876

ADSP-2101

can be programmed to generate an interrupt after the last data
bit is received. To maximize the conversion rate, SAMPLE
should be brought HIGH immediately after the last data bit is
received.

BUSY

Figure 8. ADSP-2101 Interface

The SCLK pin of the ADSP-2101 SPORTO provides the CLK
input for the AD1876. The clock should be programmed to be
approximately 2 MHz to comply with AD1876 specifications.
To minimize digital feedthrough, the clock should be disabled
(by setting Bit 14 in SPORTO control register to 0) during data
acquisition. Since .the clock floats when disabled, a pulldown
resistor of 12 k-15 k!l should be connected to SCLK to ensure
it will be LOW at the falling edge of SAMPLE. To maximize
the conversion rate, the serial clock should be eriabled immedi·
ately after SAMPLE is brought LOW (hold mode).
The ADI876 BUSY signal is connected to RFO to notify
SPORTO when a new data word is coming. SPORTO should be
configured in normal, external, noninverting framing mode and

ADl876 AND SM5805 DIGITAL FILTER @ 2 Fs
A simple method for generating the required signals for the
AD1876 is to connect one or more ADl876s to an NPC SM5805
digital filter. This device supplies all signals required to operate
the ADl876 at a 96 kHz sample rate, which is 2 x Fs for audio
applications.
To minimize group delay distortion, the input to the ADI876 is
filtered only by a low order analog filter. The ADl876 samples
the output of the filter at 2 Fs (96 kHz). To prevent aliasing,
the SM5805 filters the data with a sharp, linear phase filter roll·
ing off at 0.5 Fs. The resulting data is decimated to a sample
rate of 48 kSPS.
Interfacing the two chips is straight forward, as shown in Figure
9. The start signal for the ADl876 (for 96 kSPS operation) is
provided by the S/H pin of the SM5805, and CLK is derived
from the BCC pin. Figure 10 illustrates the corresponding tim·
ing diagram.

LEFT
CHANNEL

INPUT

DECIMATED

DATA. LEFT
DECIMATED

DATA. RIGHT
RIGHT
CHANNEL
INPUT
TO +5V

Figure 9. AD 1876 and SM5805 Digital Filter

I"

o~p~-'~----

~

In. (f. = 48kHz)

1

______________________________~r----1~__________________________________~
.

1

SBC
OUTPUT

DINR-;.......;.MS:;S;,."..v-::3"\r.4~.~::"'.v-::7v:8v:.:v.~;:V,::-,v.;I.~13:v.,";'.V,::'v:-::LS::;S-----VMS::;'Sr:'~3~";'4V-::5v::m~·;:V8-::V":"8v.;'.~I:"\1r.,::.V':;3v.;"~15:V-LS=B:---r---Figure 10. SM5805 Timing Diagram
3-12 AUDIO AID CONVERTERS

REV. A

Typical Dynamic Perfonnance -AD1876
90
......

80
70

lDao -

...
I

r---

,

C

~40

......

)~

iJj'
30

10

~V

,0

...... ~

VREF = 10V

50

20

~

~~
L

~

~ r\
~

...
ID

90

~~II~~ui

80

I II

70

~50

\·V REF =7V

40

V

30
20

-lIO -70
-60 -60 -40
-30 -20 -10
0
INPUT AMPLITUDE, REFERRED TO FULL-SCALE - dB

-60dB INPUT

I J1

o

100

lk

10k

lOOk

1M

Figure 12. SI(N+D) vs. Input Frequency and Amplitude

OdB

OdB
ID

-30dB

ID

-30dB

'"

-6OdB

'Y

-7OdB

g

-&OdB

::I

....
Q.

-9OdB

!::

r

INPUT FREQUENCY - Hz

Figure 11. SI(N+D) VS. VREF vs. Input Amplitude

Q

iY

S60
+

VREF = 5V

o

'Y

i\

12~~!~pJT

r

!:i

-70dB
-90dB

~

:E -11OdB
C

-llOdB
C -l3OdB

-l3OdB
-l50dB

-15OdB
0
FREQUENCY - Hz

FREQUENCY - Hz

Figure 13. 4096 Point FFT at 96 kSPS, f,N = 1.06 kHz

Figure 14. IMD Plot for f'N = 1008 Hz (f.), 1055 Hz (fb ) at
96kSPS

+5V

90

~7

80

.12V

70
-12V

ID

'Y

60

C

•

Z 50

iJj'

40
30
20

o

100

lk

10k

lOOk

1M

RIPPLE FREQUENCY - Hz

Figure 15. Power Supply Rejection (f,N = 1.06 kHz,
fSAMPLE = 96 kSPS, VRIPPLE = 0.3 V p-p)

REV. A

AUDIO AID CONVERTERS 3-13

II

3-14 AUDIO AID CONVERTERS

r.ANALOG
WDEVICES
FEATURES
Dual Channel
98 dB Signal-to-Noise Ratio
98 dB THD+N
0.0004 dB Passband Ripple
115 dB Stopband Attenuation
64x Oversampling
Unear Phase

High Performance Stereo
16-Bit Oversampled ADC
AD1878 I
FUNCTlONAL BLOCK DIAGRAM
WCK

DATA
CLOCK

51

APPLICATIONS
DAT and DCC Tape Players
Direct-to-Disc Recorders
Digital Audio Editors
Digital Mixing Consoles

RESET

DGND

DVDD

PRODUCT DESCRIPTION
The AD1878 is a two-channel, 16-bit oversampled digital audio
ADC. Each channel incorporates a high performance one-bit
noise shaping modulator and a digital decimating filter. An onboard voltage reference is also included. ADC output data is
transmitted from a flexible serial data port. The circuitry of the
AD1878 is segmented between two monolithic chips.

AVSs1
AVDD2

AV OD1
NC

The .voltage reference and one-bit modulators are fabricated
BiCMOS chip. The reference circuitry provides a reft
age that is stable over temperature and time. Us·
master clock, the one'bit modulators 0
sampling ratio. This oversampling ratio
ters to be simple resistor-capacitor combi
ns
linear phase throughout the passband. The mod
order and employ differential switched capacitor fil
to provide the required noise shaping characteristics and extremely
low distortion.
The digital decimating filters and serial port are fabricated using
a CMOS process. Using a proprietary technique, these singlestage digital filters provide a narrow transition band, deep stopband attenuation and low passband ripple.
The output port provides a single, serial bit stream which can
operate in several MASTER or SLAVE modes. It is controlled
by a clock and mode select pins. The format of the data is twos
complement, MSB first. The output signals are TTL and 5 volt
CMOS compatible. Output words may be transmitted in a rightjustified, I2 S or user-defmed format.

VINL-

VINL+
REFL

The AD1878 operates with ±5 volt power supplies. Separate
digital and analog power supplies and ground connections are
provided for reduced digital crosstalk. The AD1878 is guaranteed to operate over a temperature range of - 25°C to +70°C
and is packaged in a 28-pin plastic DIP.

PRODUCT HIGHLIGHTS
1. 64 x F s sampling rate.

2. From 2.5 kHz to 50 kHz output word rates.
3. Passband ripple is less than 0.001 dB.
4. Stopband attenuation is 115 dB.
5. Excellent low level signal performance is achieved.
6. No sample-and-hold circuits are required.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

REV. 0

AUDIO AID CONVERTERS ~15

•

AD1878 -SPECIFICATIONS

@ ± 5 volt Supplies. TA

= +25°C. Clock = lU88 MHz

PBrameter

Target

Units

RESOLUTION

18

Bits

OVERSAMPLING RATIO

64

DYNAMIC RANGE, 0 kHz to 20 kHz, No A-Weight Filter
Stereo Model
Mono Model

98
101

dB
dB

98

dB
dB
dB

SIGNAL TO (NOISE + DISTORTION)
o dB, 1 kHz
-20 dB, 1 kHz
-60 dB, 1 kHz

85
45

ANALOG INPUTS
Input Range
Input Impedance

V.
kG

REFERENCE OUTPUT
Output Voltage
Output Impedance

V

DC ACCURACY
Gain Matching
Gain Error
Gain Drift
Midscale Error
Midscale Drift

dB

%
ppml"C
LSBs
ppml"C

0
't

PHASE DEVIATION (Interchannel)

Degrees

CROSSTALK
20 kHz, EIAJ Method

dB

DIGITAL FILTER CHARACTERISTICS
Passband Ripple
Stopband Attenuation
12.288 MHz Master Clock'
Passband Edge
Stopband Edge
11.2896 MHz ClockS
Passband Edge
Stopband Edge
DIGITAL INPUTS AND OUTPUTS
V'H

,L

V
IIH @: V1H

=5V

I'L @: V'L = 0 V
VOH @: IOH = 4 mA
VOL @: IOL = 4 mA
NOMINAL MASTER CLOCK FREQUENCY
POWER SUPPLIES
Voltage, +VL and +Vs
Voltage, -VL and -Vs
Current, +IL and +Is
Current, - IL and - Is

0.001

115
21.7

dB
dB

26.2

kHz
kHz

20
24.1

kHz
kHz

2.0
0.8
10
10

4.5

0.5
12.288

MHz

5

V
V
mA
mA

-5
TBD
TBD

POWER DISSIPATION
Operation
Power Down APD = "I"

900

400

mW
mW

POWER SUPPLY REJECTION RATIO

67

dB

TEMPERATURE RANGE
Specification
Operation
Storage

25
-25 to +70

·C
·C
"C

NOTES
'Stereo Mode uses output of each channel independently.
2Mono Mode sums output words to derive higher Dynamic Range.

'l6-bit LSBs.

-60 to +100
4Master Clock Frequenty for 48 kHz sample rate.
'Master Clock Frequenty for 44.1 kHz sample rate.
Specifications subject to change without notice.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

. 3-16 AUDIO IVD CONVERTERS

REV. 0

11IIIIIIII ANALOG
WDEVICES
FEATURES
Dual Channel
103 dB Signal-to:Noise Ratio
98dBTHD+N
0.0004 dB Passband Ripple
115 dB Stopband Attenuation
64x Oversampling
Linear Phase

High Performance Stereo
l8-Bit Oversampled ADC
AD1879 I
FUNCTIONAL BLOCK DIAGRAM
WCK
DATA
CLOCK
SI

APPUCATIONS
Pro Audio Digital Tape Recorders
Direct-to-Disc Recorders
Digital Audio Editors
Digital Mixing Consoles

RESET
DGND

DYOD

PRODUCT DESCRIPTION
The AD1879 is a two-channel, l8-bit oversampled digital audio
ADC. Each channel incorporates a high performance one-bit
noise shaping modulator and a digital decimating fllter. An onboard voltage reference is also included. ADC output data is
transmitted from a flexible serial data port. The circuitry of the
AD1879 is segmented between two monolithic chips.
The voltage reference and one-bit modulators are fabricpted
BiCMOS chip. The reference circuitry provides a refer
age that is stable over temperature and time. Us·
master clock, the one-bit modulators 0
sampling ratio. This oversampling ratio
fllters to be simple resistor-capacitor co
linear phase throughout the passband. The m
to proorder and employ differential switched capacitor fll
vide the required noise shaping characteristics and extremely
low distortion.
The digital decimating fllters and seria1 port are fabricated using
a CMOS process. Using a proprietary technique, these singlestage digital fllters provide a narrow transition band, deep stopband attenuation and low passband ripple.
The output port provides a single, serial bit stream which can
operate in several MASTER or SLAVE modes. It is controlled
by clock and mode select pins. The format of the data is twos
complement, MSB fIrst. The output signals are TTL and 5 volt
CMOS compatible. Output words may be transmitted in a rightjustifIed, 12S or user-defmed format.

AVssl
AVoo2

AV DD1
NC
VINL-

VlNL+

REFL

PRODUCT HIGHLIGHTS
1. 64 x F s sampling rate.
2. Passband ripple

i~

less than 0.001 dB.

3. Stopband attenuation is 115 dB.
4. Excellent low level signal performance is achieved.
S. No sample-and-hold circuits are required.
6. Fully differential analog inputs.
7. Extremely flexible serial data output port.

The AD1879 operates with ±5 volt power supplies. Separate
digital and analog power supplies and ground connections are
provided for reduced digital crosstalk. The AD1879 is guaranteed to operate over a temperature range of -25°C to +70°C
and is packaged in a 28-pin plastic DIP.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
REV. 0

AUDIO AID CONVERTERS ~ 17

•

AD1879 -SPECIFICATIONS

@ ±5 VSupplies, T,

= 25°C, Clock = 12.288 MHz

Parameter

Target

Vilits

RESOLUTION

18

Bits

OVERSAMPLING RATIO

64

DYNAMIC RANGE, 0 kHz to 20 kHz, No A-Weight Filter
Stereo Mode'
Mono Mode'

106

dB
dB,

SIGNAL TO (NOISE + DISTORTION)
odB, 1 kHz
-20 dB, 1 kHz
-60 dB, 1 kHz

98
85
45

dB
dB
dB

103

ANALOG INPUTS
Input Range
Input Impedance

v

REFERENCE OUTPUT
Output Voltage
Output Impedance

V

kO

DC ACCURACY
Gain Matching
Gain Error
Gain Drift
Midscale Error
Midscale Drift

dB
%
ppmI"C
LSBs
ppmI"C

PHASE DEVIATION (Interchannel)

Degrees

CROSSTALK
20 kHz, EIAJ Method

dB

DIGITAL FILTER CHARACTERISTICS
Passband Ripple
Stopband Attenuation
12.288 MHz Master Clock'
Passband Edge
Stopband Edge
11.2896 MHz Clock'
Passband Edge
Stopband Edge

lI5

dB
dB

21.7
26.2

kHz
kHz

20
24.1

kHz
kHz

0.001

DIGITAL INPUTS AND OUTPUTS
V IH
V IL
I'H@VIH = 5 V
IIL@VIL = OV
VOH @ IOH = 4mA
VOL@IOL=4mA

2.0
0.8
10
10
4.5
0.5

NOMINAL MASTER CLOCK FREQUENCY

12.288

MHz

5
-5

V

V

IlA
IlA
V
V

POWER SUPPLIES
Voltage, +VL and +Vs
Voltage, -VL and -Vs
Current, + IL and + Is
Current, -IL and -Is

TBD
TBD

V
V
mA
mA

POWER DISSIPATION
Operation
Power Down APD = "1"

900
400

mW
mW

POWER SUPPLY REJECTION RATIO

67

dB

TEMPERATURE RANGE
Specification
25
"C
Operation
- 25 to + 70
"C
Srorage~________________________________________~_________-_60
__t_o_+_1_00________________- L_________o_C____

NOTES
IStereo mode uses output of each channel independently.
2Mono mode sums output words to derive higher dynamic range.
'l6-bit LSBs.

'Master Clock Frequency for 48 kHz sample rate.
SMaster Clock Frequency for 44.1 kHz' sample rate.
Specifications subject to change without notice.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

3-18 AUDIO AID CONVERTERS

REV. 0

Low-Cost Stereo
16-Bit Oversampled ADC
AD1885 I

r.ANALOG
WDEVICES
FEATURES
Dual Channel
85 dB Signal-to-Noise Ratio
85 dB THD+N
±0.01 dB Passband Ripple
80 dB Stopband Attenuation
64 Times Oversampling
Linear Phase

FUNCTIONAL BLOCK DIAGRAM
WCK
SERIAL OUTPUT INTERFACE

DATA
CLOCK

81
RESET

APPLICATIONS
RDAT Machines
High Performance Sampling Kevboards
Multimedia Workstations

DGND
DVDD

PRODUCT DESCRIPTION

AVDD2

The AD1885 is a two-channel, 16-bit oversam
ADC. Each channel incorporates a high perfo
e on
noise-shaping modulator and a digital decimating filte .
board voltage reference is also included. ADC output dat is
transmitted from a flexible serial data port. The circuitry of the
AD1885 is segmented between two monolithic chips.
The reference circuitry provides a reference voltage that is stable
over temperature and time. Using an external master clock, the
one-bit modulator operates at 64 x Fs oversampling rate. This
oversampling rate permits the antialias filters to be simple
resistor-capacitor combinations and results in linear phase
throughout the passband. The third-order modulators employ
differential switched capacitor filters to provide the required
noise-shaping characteristics and extremely low distortion.
The digital decimating filters and serial port are fabricated using
a CMOS process. Using a proprietary technique, these singlestage digital filters provide a narrow transition band, deep stopband attentuation and low passband ripple.
The output port provides right and left channel.data in a single,
serial bit stream controlled by user-supplied BCK, LRCK and
WCK signals. The twos complement, MSB first data can be
transmitted in a right-justified, left-justified or user-defined
format.

AVDDl

NC = NO CONNECT

The AD 1885 operates with ± 5 V power supplies. Separate digital and analog ground connections are provided for reduced digital crosstalk. The AD 1885 is guaranteed to operate over a
temperature range of -25·C to +70·C. The AD1885 is packaged in a 28-pin plastic SOIC.

PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
8.

64 x F s sampling rate.
44.1, 48 and 32 kHz output word rates.
Passband ripple is less than ±0.01 dB.
Stopband attenuation is 80 dB.
Excellent low-level performance.
No sample-and-hold circuits are required.
Analog inputs are fully differential.
Serial data output port.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

REV. 0

AUDIO AID CONVERTERS 3-19

II

AD1885 - SPECIFICATIONS

(@ ±5 VSupplies, TA

= +25°C, Clock = 18 x 432 MHz (= 384 x48 kHz»
Target

Parameter
RESOLUTION

16
64

Unit
Bits

OVERSAMPLING RATIO
DYNAMIC RANGE, 0 to 20 kHz, NO A-WEIGHT FILTER
Stereo Model

85

dB

THD+N (SIGNAL TO (NOISE + DISTORTION))
o dB, 1 kHz
-20 dB, 1 kHz
-60 dB, 1 kHz

85
TBD
TBD

dB
dB
dB

ANALOG INPUTS
Input Range
Input Impedance

±3
30

kO

REFERENCE OUTPUT
Output Voltage
Output Impedance

V

DC ACCURACY
Gain Matching
Gain Error
Gain Drift
Midscale Error
Midscale Drift
PHASE DEVIATION (INTERCHANNEL)

dB
%
ppmf'C
LSBs2
ppmf'C
Degrees

CROSSTALK
20 kHz, EIAJ Method
DIGITAL FILTER CHARACTERISTICS
Passband Ripple
Stopband Attenuation
18.432 MHz Master Clock3 (= 384 x 48 kHz)
Passband Edge
Stopband Edge
16.9344 MHz Master Clock4 (= 384 x 44.1 kHz)
Passband Edge
Stopband Edge

dB

DIGITAL INPUT AND OUTPUTS
V,H

±0.01
80

dB
dB

21.6
26.4

kHz
kHz

19.8
24.3

kHz
kHz

2.0
0.8
10
10
4.5

V,L

IIH @VIH = 5 V
I'L@V'L = 0 V
VOH @ IOH = 4 rnA
VOL @ IOL = 4 rnA
MASTER CLOCK FREQUENCY
POWER SUPPLIES
Voltage, AVDDI and AVDD2
Voltage, AVSSI and AVSS2
Current, + IL and Is
Current, - IL and - Is
POWER DISSIPATION
Operation
Power Down APD = "1"

0.5
18.432

MHz

5

V
V
rnA
rnA

-5
TBD
TBD

500
50

mW
mW
dB

+25
-25 to +70
-60 to +100

·C
·C
·C

375

POWER SUPPLY REJECTION RATIO (IN BAND)
TEMPERATURE RANGE
Specification
Operation
Storage
NOTES
lStereo mode uses output of each channel.
'16-bit LSBs.

v

'Master Clock Frequency for 48 kHz sample rate.
Master Clock Frequency for 44.1 kHz sample rate.
Specifications subject to change without notice.

4

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future- manufacture unless otherwise agreed to in writing.

3--20 AUDIO AID CONVERTERS

REV. 0

Video AID Converters
Contents
Page

Video AID Converters - Section 4 .............................................. 4-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
AD773 - lO-Bit 18 MSPS Monolithic AID Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
AD9020 - 10-Bit 60 MSPS AID Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
AD9048 - Monolithic 8-Bit Video AID Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
AD9060 - lO-Bit 7S MSPS AID Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39

a

VIDEO AID CONVERTERS 4-1

t Selection Guide
s
~ Video Analog-to-Digital Converters

0

~

8:c:
~

~

Model

Res
Bits

Sample
Rate
(MSPS)

Input
Bandwidth
MHz, -3 dB

Power
Dissipation
W

AD9048

8

35

15

0.55

AD773
AD9020

10
10

18
60

100
175

1.3
2.8

AD9060

10

75

175

2.8

i;:!

ill

Page
4-31
4-31
4-31
4-31
4-3
4-19
4-19
4-39
4-39

Comments

On-Board Track and Hold, Evaluation PCB
Evaluation PCB
Evaluation PCB

11IIIIIIII

ANALOG

WDEVICES
FEATURES
Monolithic 10-Bit 18 MSPS AID Converter
Low Power Dissipation: 1.2 W
Signal-to-Noise Plus Distortion Ratio
f'N
1 MHz: 55 dB
f'N = 8 MHz: 52 dB
Guaranteed No Missing Codes
On-Chip Track-and-Hold Amplifier
100 MHz Full Power Bandwidth
High Impedance Reference Input
Out of Range Output
Twos Complement and Binary Output Data
Available in Commercial and Military Temperature
Ranges

10-Bit 18 MSPS
Monolithic AID Converter
AD773 I
FUNCTIONAL BLOCK DIAGRAM

=

a
OTR MSB BIT 1 BIT 10
(MSB) (l.SB)

PRODUCT DESCRIPTION
The AD773 is a monolithic lO-bit, 18 MSPS analog-to-digital
converter incorporating an on-board, high performance trackand-hold amplifier (THA). The AD773 converts video bandwidth signals without the use of an external THA. The AD773
implements a multistage differential pipelined architecture with
output error correction logic. The AD773 offers accurate performance and guarantees no missing codes over the full operating
temperature range.
Output data is presented in binary and twos complement format. An out of range (OTR) signal indicates the analog input
voltage is beyond the specified input range. OTR can be
decoded with the MSB/MSB pins to signal an underflow or
overflow condition. The high impedance reference input allows
multiple AD773s to be driven in parallel from a single reference.
The combined dc precision and dynamic performance of the
AD773 is useful in a variety of applications. Typical applications
include: video enhancement, HDTV, ghost cancellation, ultrasound imaging, radar and high speed data acquisition.

PRODUCT HIGHLIGHTS
I. On-board THA
The high impedance differential input THA eliminates the
need for external buffering or sample and hold amplifiers.
The THA offers the choice of differential or single-ended
inputs. Input current is typically 5 fJ.A.
2. High Impedance Reference Input
The high impedance reference input (200 kO) allows direct
connection with standard + 2.5 V references, such as the
AD680, ADS80 and REF43.
3. Output Data Flexibility
Output data is available in bipolar offset and bipolar twos
complement binary format.
4. Out of Range (OTR)
The OTR output bit indicates when the input signal is beyond the AD773's input range.

The AD773 was designed using Analog Devices' ABCMOS-l
process which utilizes high speed bipolar and 2-micron CMOS
transistors on a single chip. High speed, precision analog circuits are now combined with high density logic circuits. Laser
trimmed thin film resistors are used to optimize accuracy and
temperature stability.
The AD773 is packaged in a 28-pin ceramic DIP and is available in commercial (O°C to + 70°C) and military (-55°C to
+ 125°C) grades.

REV. 0

VIDEO AID CONVERTERS 4-3

AD773 - SPECIFICATIONS
AVDD = +5 V ± 5%, AVss = -5 V ± 5%, DVDD = +5 V ±5%,
DC SPECIFIC".'JIONS DRVDDto=TMAl(+5with
V ± 5%, V = +2.500 V unless otherwise indicated)
(TMIN

REF

AD773)

Parameter

Min

RESOLUTION

10

DC ACCURACY (+ 25°C)
Integral Nonlinearity
TMINto TMAX
Differential Linearity Error
TMIN to T MAX
Offset
Gain Error
No Missing Codes

LOGIC INPUT
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = DVoo)
Low Level Input Current (VIN = 0 V)
Input Capacitance
LOGIC OUTPUTS
High Level Output Voltage (loH = 0.5 rnA)
Low Level Output Voltage (IoL = 1.6 rnA)
POWER SUPPLIES
Operating Voltages
AVoo
AVss
DVoo,DRV oo
Operating Current
IAVoo
IAVss
IDVoo
IDRVoo 1

AD773K
Max

Min

Max

1
5

±2

±0.75
±1
0.5
3.5
0.5
2.0
GUARANTEED
1
5

20
10

200
2.5

50

+3.5

20
10

-10
-10

+1.0
+10
+10

-10
-10

10

10

+2.4

+2.4

+5.25
-4.75
+5.25

Vp-p
j.LA
pF

V
V
j.LA
j.LA
pF

+0.4

V
V

+5.25
-4.75
+5.25

Volts
Volts
Volts

85
-140
15
10

100
-185
20
15

rnA
rnA
rnA
rnA

+0.4

+4.75
-5.25
+4.75

LSB
LSB
LSB
LSB
%FSR
%FSR

k!l
Volts

200
2.5

+3.5
+1.0
+10
+10

Units
Bits

±0.75

±1
0.5
0.5

50

Typ

10

±1

ANALOG INPUT
Input Range
Input Current
Input Capacitance
REFERENCE INPUT
Reference Input Resistance
Reference Input

Typ

+4.75
-5.25
+4.75

85
-140
15
10

100
-185
20
15

POWER CONSUMPTION2

1.2

1.5

1.2

1.5

W

POWER SUPPLY REJECTION

6

16

6

16

mVN

+70

°C

TEMPERATURE RANGE
Specified (J/K)

0

+70

0

NOTES
IC L = 15 pF typical.
'100% production t..ted.
Specifications subject to change without nOlice. See Definition of Specifications for additional information.

4-4 VIDEO AID CONVERTERS

REV. 0

AD773
to TMAl( with AVDD = +5 V ± 5%, AVss = -5 V ± 5%, DVDD = +5 V ± 5%, DRVDD = +5 V
AC SPEC IFI CAT10NS(TMIN
± 5%, V = +2.500 V unless otherwise indicated, fSAMPLE = 18 MSPS, fiN amplitude = -0.3 dB)
REF

AD773)
Parameter
DYNAMIC PERFORMANCE I
Signal-to-Noise plus Distortion
(SIN+D) Ratio
fiN = I MHz
fIN = 8.1 MHz
fIN = 9 MHz
Effective Number of Bits (ENOB)
fIN = I MHz
fIN = 8.1 MHz
fIN = 9 MHz
Total Harmonic Distortion (THD)
fIN = I MHz
fIN = 8.1 MHz
fIN = 9 MHz
Spurious Free Dynamic Range2
Full Power Bandwidth
Interrnodulation Distortion (IMD)3
Second Order Products
Third Order Products
Differential Phase
Differential Gain
Transient Response
Overvoltage Recovery Time

Min

Typ

52
45

56
53
53

AD773K

Max

Min

Typ

54
47

56
53
53

dB
dB
dB

9.0
8.5
8.5

Bits
Bits
Bits

9.0
8.5
8.5

-64
-55
-56
-67
100

-57

-64
-55
-56
-67
100

-46

-69
-63
0.2
0.8
25
25

-69
-63
0.2
0.8
25
25

Max

-59
-48

Units

dB
dB
dB
dB
MHz
dB
dB
Degree

%
ns
ns

NOTES
IFor typical dynamic performance curves at fSAMPLE = 16.2 MSPS and 18 MSPS, see Figures 2 through 13.
'fiN = I MHz.
'fa = 1.0 MHz, fb = 1.05 MHz.
Specifications subject to change without notice.

(for all grades TMIN to TMAl( with AVDD = +5 V ± 5%, A~ss ~ .-5 V ± 5%, DVDD = +5 V ± 5%,
TIMING SPECIFICATIONS
II
DRVDD = +5 V ± 5%, VREF = +2.500 V unless otherwise mdlcated, fSAMPLE = 18 MSPS)
Symbol
Conversion Rate
Clock Period
Clock High
Clock Low
Output Delay
Aperture Delay
Aperture Jitter
Pipeline Delay (Latency)

Typ

Min

Max

Units

18

MSPS
ns
ns
ns
ns
ns
ps
Clock Cycles

55
27
27

teLK

teH
teL
toD

20
7
9

32
4

N
N+1

VIN

CLOCK

ItCH

BIT 1-10
MSB.OrR

==x

::;j

I

tCL

X

X

X

~tOD

X

DATA
N

~
N+1

Figure 1. AD773 Timing Diagram

REV. 0

VIDEO AID CONVERTERS 4-5

II

AD773
CAUTION _________________________________________________
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted.

WARNING!

d

~~EDEVICE

ABSOLUTE MAXIMUM RATINGS*
Parameter

With Respect to

Min

Max

Units

AVoo
AVss
DVoo , DRVoo
AGND
AV oo , AVss
CLK
REFIN
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)

AGND
AGND
DGND,DRGND
DGND,DRGND
DVoo , DRVoo
DVoo , DRVoo
REFGND, AGND

-0.5
-6.5
-0.5
-1.0
-6.5
-6.5
-0.5

+6.5
+0.5
+6.5
+1.0
+0.5
+0.5
+6.5
+150
+150

V
V
V
V
V
V
V
°C
°C

-65

+300 °C

*Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect device reliability.

PIN CONFIGURATION
AGND
V INB
V 1NA

AVss

AD773
TOP VIEW
(Not to Scale)

DV OD
eLK

DRV OD
DAGND
OTA

ORDERING GUIDE

MSB

Model

Temperature
Range

Description

Package
Option*

AD773JD
AD773KD

O°C to +70°C
O°C to +70°C

28-Pin Ceramic DIP
28-Pin Ceramic DIP

D-28
D-28

*D

= Ceramic

BIT 1 (MSB)
BIT 2
BIT3

BIT 0

DIP. For outline information see Package Information section.

PIN DESCRIPTION
Symbol

Pin No.

Type

Name and Function

AGND
AVoo
AVss
BIT I (MSB)
BIT 2-BIT 9
BIT 10 (LSB)
CLK

5,28
4
3,25
18
17-10
9
23

P
P
P
DO
DO
DO
DI

DVoo
DRVoo
DGND
DRGND
MSB
OTR

24
7,22
8,21
19
20

P
P
P
P
DO
DO

I
2
26
27

AI
AI
AI
AI

Analog Ground.
+ 5 V Analog Supply.
-5 V Analog Supply.
Most Significant Bit.
Data Bit 2 through Data Bit 9.
Least Significant Bit.
Clock Input. The AD773 will initiate a conversion on the falling edge of the clock input. See the
Timing Diagram for details.
+5 V Digital Supply.
+ 5 V Digital Supply for the output drivers.
Digital Ground.
Digital Ground for the output drivers.
Inverted Most Significant Bit. Provides twos complement output data format.
Out of Range is Active HIGH on the leading edge of Code 0 or the trailing edge of Code 1023.
See Output Data Format Table II.
REF GND is connected to the ground of the external reference.
REF IN is the external 2.5 V reference input, taken with respect to REF GND.
( + ) Analog input signal to the differential input THA.
( - ) Analog input signal to the differential input THA.

REFGND
REF IN
V1NA
VINB

6

Type: AI = Analog Input; DI = Digital Input; DO = Digital Output; P = Power.

4-6 VIDEO AID CONVERTERS

REV. 0

Definitions of Specifications - AD773
INTEGRAL NONLINEARITY (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from "zero" through "full scale." The point
used as "zero" occurs 112 LSB before the first code transition.
"Full scale" is defined as a level I 112 LSB beyond the last code
transition. The deviation is measured from the center of each
particular code to the true straight line.
DIFFERENTIAL LINEARITY ERROR (DNL, NO
MISSING CODES)
An ideal ADC exhibits code transitions that are exactly I LSB
apart. DNL is the deviation from this ideal value.
OFFSET
The first transition should occur at a level 112 LSB above
"zero." Offset is defined as the deviation of the actual first code
transition from that point.
GAIN ERROR
The last code transition should occur for an analog value I 112
LSB below the nominal full scale. The gain error is the deviation of the actual level at the last transition from the ideal level.
POWER SUPPLY REJECTION
One of the effects of power supply variation on the performance
of the device will be a change in gain error. The specification
shows the maximum gain error deviation as the supplies are varied from their nominal values to their specified limits.
SIGNAL-TO-NOISE PLUS DISTORTION (SIN+D)
RATIO
SIN + D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components including
harmonics but excluding dc. The value for SIN+D is expressed
in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
ENOB is calculated from the following expression:
SIN+D = 6.02N + 1.76, where N is equal to the effective
number of bits.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com·
ponents to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
SPURIOUS FREE DYNAMIC RANGE
The peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. This
value is expressed in decibels relative to the rms value of a fullscale input signal.

REV. 0

INTERMODULATION DISTORTION (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m+n), at sum and difference frequencies of mfa±nfb,
where m, n = 0, 1,2,3 .... Intermodulation terms are those
for which m or n is not equal to zero. For example, the second
order terms are (fa+fb) and (fa-fb) and the third order terms
are (2fa+fb), (2fa-fb), (fa+2fb) and (fa-2fb). The IMD products are expressed as the decibel ratio of the rms sum of the
measured input signals to the rms sum of the distortion terms.
The two signals are of equal amplitude and the peak value of
their sums is -0.5 dB from full scale. The IMD products are
normalized to a 0 dB input signal.
DIFFERENTIAL GAIN
The percentage difference between the output amplitudes of a
small high frequency sine wave at two stated levels of a low frequency signal on which it is superimposed.
DIFFERENTIAL PHASE
The difference in the output phase of a small high frequency
sine wave at two stated levels of a low frequency signal on which
it is superimposed.
TRANSIENT RESPONSE
The time required for the AD773 to achieve its rated accuracy
after a full-scale step function is applied to its input.
OVERVOLTAGE RECOVERY TIME
The time required for the ADC to recover to full accuracy after
an analog input signal 150% of full scale is reduced to 50% of
the full-scale value.
APERTURE DELAY
The difference between the switch delay and the analog delay of
the THA. This effective delay represents the point in time, relative to the rising edge of the CLOCK input, that the analog input is sampled.
APERTURE JITTER
The variations in aperture delay for successive samples.
PIPELINE DELAY (LATENCY)
The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every clock cycle.
FULL POWER BANDWIDTH
The input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 dB for a full-scale input.

VIDEO AID CONVERTERS 4-7

a

AD773 - Dynamic Characteristics
o

60

F~N~~JEN~A~

-~r-50

...III

~~

-6dB

40

-20

~

I

~ 30

"

I\.

-o.3IIB

~

IL

--

THD

20

10

o

lOOk

1M

-100

100M

10M

lOOk

10-'"
2i

D

.,.

~

rii, i

1M

Nl

10M

rrrr
3RD

100M

FREQUENCY - Hz

FREQUENCY - Hz

Figure 2. SIN+D vs. Input Frequency, (eLK = 18 MSPS

Figure 5. Harmonic Distortion vs. Input Frequency,
feLK = 18 MSPS: Small Signal

o

Or-~r-~--~---r--'---~--~-'

-10r--ir---r---r-~r-~--~--~--~

-2O~-H---+--~--+-~~-+---r~

-20

...III

1/

...III -40
I

II:

~-60

~

.,.,... ~

V

I

I!I

~

~O~~~--~--r-~r-~--~--~--~

-40~~~--~--r-~r-~--~--~--~

~==

2

a:

...J

••
••
••
••
••
••
••
••
••
••
••
••
••••
••
• ••••••
••••

••
•
•••
••
••
••
•

•

Figure 29. Solder Side PCB Layout

REV. 0

VIDEO AID CONVERTERS 4-15

II

AD 773

•

c-

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4-16 VIDEO AID CONVERTERS

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Figure 31. Power Layer PCB Layout

REV. 0

AD773

a
Figure 32. Silkscreen Layer PCB Layout

REV. 0

VIDEO AID CONVERTERS 4-17

4-18 VIDEO AID CONVERTERS

10-Bit, 60 MSPS
AID Converter
AD9020 I

1IIIIIIII ANALOG

WDEVICES
FEATURES
Monolithic 10·Bit/60 MSPS Converter
TTL Outputs
Bipolar (:1.75 VI Analog Input
56 dB SNR @ 2.3 MHz Input
Low (45 pFllnput Capacitance
MIL·STD·883 Compliant Versions Available

FUNCTIONAL BLOCK DIAGRAM
. . . LSBS

INVPT INVI!AT

ANALOG IN

~:~----,

AD9020

APPLICATIONS
Digital Oscilloscopes
Medical Imaging
Professional Video
Radar Warning/Guidance Systems
Infrarad Systems

51 OVERFLOW

0. (M9a)

GENERAL DESCRIPTION
The AD9020 AID converter is a lO·bit monolithic converter capable of word rates of 60 MSPS and above. Innovative architec·
ture using 512 input comparators instead of the traditional 1024
required by other flash converters reduces input capacitance and
improves linearity.

Do
II,

Encode and outputs are TTL"compatible, making the AD9020 an
ideal candidate for use in low power systems. An overflow bit is
provided to indicate analog input signals greater than + VSENSE'
Voltage sense lines are provided to insure accurate driving of the
± VREF voltages applied to the units. Quarter-point taps on the
resistor ladder help optimize the integral linearity of the unit.
Either 68·pin ceramic leaded (gull wing) packages or ceramic
LCCs are available and are specifically designed for low thermal
impedances. Two performance grades for temperatures of both 0
to +70°C and -55°C to + 125°C ranges are offered to allow the
user to select the linearity best suited for each application. Dy·
namic performance is fully characterized and production tested
at + 25°C. MIL·STD·883 units are available.

-v,..
-,,",

The AD9020 AID Converter is available in versions compliant
with MIL·STD·883. Refer to the Analog Devices Military Products Databook or current AD9020/883B data sheet for detailed
specifications.

REV. A

VIDEO AID CONVERTERS 4-19

a

AD9020 -SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS·

3/4aEP' 1I2REP ' 1I4REP Current ..•...•• ,'... ' .... ±10 mA
Digital Output Current ... ,. . . . . . . . . . . . . . . . . . • 20 mA
Operating Temperature
AD9020JElKElJZlKZ . . . . . . . . . . . . . . . . . . 0 to +70"C
Storage Temperature . . . . . . . . . . . . . . . • -65"C to + 150"C
Maximum Junction Temperature2. • • • • • • • • • • • • • • + 175"C
Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . +300"C

+Vs . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . +6 V
-Vs . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . -6V
ANALOG IN . . . . . . . . . . . . . . . . . . . . . . . -2 V to +2 V
+VREP' -VREP' 3/4aEP' 1I2REP' 1I4REP . . . . . -2 V to +2 V
+VREP to -VREP . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
DIGITAL INPUTS . . . . . . . . . . . . . . . . . . -0.5 V to +Vs

ELECTRICAL CHARACTERISTICS (ds = ±5 v; ±V
Parameter (Conditions)

Temp

Test
Level

RESOLUTION
DC ACCURACy3
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
ANALOG INPUT
Input Bias Current·
Input Resistance
Input Capacitance·
Analog Bandwidth
REFERENCE INPUT
Reference Ladder Resistance
Ladder Tempco
Reference Ladder Offset
Top of Ladder
Bottom of Ladder
Offset Drift Coefficient
SWITCHING PERFORMANCE
Conversion Rate
Aperture Delay (tA )
Aperture Uncertainty (Jitter)
Output Delay (ton)'
Output Time Skew'
DYNAMIC PERFORMANCE
Transient Response
Overvoltage Recovery Time
Effective Number of Bits (ENOB)
fIN = 2.3 MHz
fIN = 10.3 MHz
fIN = 15.3 MHz
Signal-to-Noise Ratio'
fIN =2.3 MHz
fIN = 10.3 MHz
fIN = 15.3 MHz
Signal-to-Noise Ratio'
(Without Harmonics)
fIN = 2.3 MHz
fIN = 10.3 MHz
fIN = 15.3 MHz

4-20 VIDEO AID CONVERTERS

SEIISE

Min

= ±1.75 v; ENCODE = 40 MSPS unless otherwise notedj3
AD9020jElJZ
Typ
Max

10

Min

AD9020KFJKZ
Typ
Max

10

+25·C
Full
+ 25·C
Full
Full

I
VI
I
VI
VI

1.0

+25·C
Full
+25·C
+25·C
+25·C

I
VI
I
V
V

0.4

+25·C
Full
Full

I
VI
V

+25·C
Full
+25·C
Full
Full

I
VI
I
VI
V

+ 25°C
+25·C
+25·C
+ 25·C
+25·C

I
V
V
I
I

+25·C
+25·C

V
V

+25·C
+ 25·C
+ 25·C

I
IV
IV

8.6
8.0
7.5

9.0
8.4
8.0

+25·C
+25"C
+ 25·C

I
I
I

54
50
47

+25·C
+ 25·C
+25"C

I
I
I

54
51
48

l.25

1.25
1.5
2.0
2.5

Units
Bits

0.75
1.0

1.0
1.25
1.5
2.0

LSB
LSB
LSB
LSB

1.0
2.0

mA

Guaranteed

2.0

7.0
45
175

22
14

37

1.0
2.0

56
66

0.4
2.0

7.0
45
175

22
14

37

45
45

90
90
90
90

45

nt"C
90
90
90
90

50

I
5
10
3

MSPS
ns
PS. rms
ns
ns

60

60

I
5
10
3

13
5

6

n
n
mV
mV
mV
mV
V-VPC

45

50

6

56
66

0.1

0.1

mA
k!l
pF
MHz

13
5

10
10

ns
ns

8.6
8.0
7.5

9.0
8.4
8.0

Bits
Bits
Bits

56
53
50

54
50
47

56
53
50

dB
dB
dB

56
54
52

54
51
48

56
54
52

dB
dB
dB

10
10

REV. A

AD9020
Parameter (Conditions)
DYNAMIC PERFORMANCE
(CONTINUED)
Harmonic Distortion
fIN = 2.3 MHz
fIN = 10.3 MHz
fiN = 15.3 MHz
Two-Tone Intermodulation
Distortion Rejection7
Differential Phase
Differential Gain
ENCODE INPUT
Logic "1" Voltage
Logic "0" Voltage
Logic "1" Current
Logic "0" Current
Input Capacitance
Pulse Width (High)
Pulse Width (Low)
DIGITAL OUTPUTS
Logic "1" Voltage (loH = 2 rnA)
Logic "0" Voltage (loL = 10 rnA)
POWER SUPPLY
+ Vs Supply Current

Temp

Test
Level

Min

+25 DC
+ 25 DC
+25 DC

I
I
I

61
55
49

+ 25 DC
+25 DC
+25 DC

V
V
V

Full
Full
Full
Full

+ 25DC
+ 25 DC
+25 DC

VI
VI
VI
VI
V
I
I

Full
Full

VI
VI

+25"C

440

Full

I
VI
I
VI
I
VI

Full

VI

6

Full
- Vs Supply Current

+ 25DC
Full

Power Dissipation
Power Supply Rejection
Ratio (PSRR)8

+25"C

AD9020JElJZ
Typ
Max

67
59
53

AD9020KEIKZ
Min

Typ

61
55
49

67
59
53

dBc
dBc
dBc

70
0.5

dBc

I

%

70
0.5
1
2.0

Max

Degree

2.0
0.8
20
800

0.8
20
800

5

5

6
6

2.4

140
2.8

10

IIoA

V
V

0.4
530
542
170
177
3.3
3.4

V
V
/loA
pF
ns
ns

6
6

2.4

Units

440
140
2.8
6

rnA
rnA
rnA
rnA

530
542
170
177
3.3
3.4

W
W

10

rnVN

NOTES
I Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
'Typical thermal impedanct. (part soldered onto board): 6S·pin leaded ceramic chip carrier: 0JC = IOC/W; OJA = 170c/w (no air flow); OJA = ISoc/w
(air flow = 500 LFM). 68·pin ceramic LCC: 0JC = 2.6OC/W; 0JA = ISoc/w (no air flow); 0JA = 13"C1W (air flow = 500 LFM).
'3/4REF , 1I2REF , and 1I4REF reference ladder taps are driven from de sources at +0.875 V, 0 V, and -0.875 V, respectively. Accuracy of the overflow compara·
tor is not tested and not included in linearity specifications.
'Measured with ANALOG IN = +VSENSE.
'Output delay measured as worst·case time from 50% point of the rising edge of ENCODE to 50% point of the slowest rising or falling edge of Do-D•. Output
skew measured as worst-case difference in output delay among Do-D9'
6RMS signal to rms noise with analog input signal I dB below full scale at specified frequency.
'Intermodulation measured with analog input frequencies of 2.3 MHz and 3.0 MHz at 7 dB below full scale.
8Measured as the ratio of the worst-case change in transition voltage of a single comparator for a 5% change in +Vs or -Vs'
Specifications subject to change without notice.

REV. A

VIDEO AID CONVERTERS 4-21

a

AD9020
EXPLANATION OF TEST LEVELS
Test Level
I
II

-

III IV V VI -

100% production tested.
100% production tested at + 2SOC, and sample tested at
specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization
testing.
Parameter is a typical value only.
All devices are 100% production tested at +2SOC. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature extremes for commercial/industrial devices.

ORDERING GUIDE
Device
AD9020JZ
AD9020]E
AD9020KZ
AD9020KE
AD9020SZl883
AD9020SEl883
AD9020TZl883
AD9020TEl883
AD90201PCB

Temperature
Range

o to +70·C
o to +70OC
o to +70·C
o to +70·C
-S5OC to + 125·C
-55OC to + 125·C
- 550C to + 125·C
- 550C to + 125·C
o to +70·C

Description
68-Pin Leaded Ceramic
68-Pin Ceramic LCC
68-Pin Leaded Ceramic
68-Pin Ceramic LCC
68-Pin Leaded Ceramic
68-Pin Ceramic LCC
68-Pin Leaded Ceramic
68-Pin Ceramic LCC
Evaluation Board

Package
Option*
Z-68
E-68A
Z-68
E-68A
Z-68
E-68A
Z-68
E-68A

*E = Ceramic Leadless Chip Carrier; Z = Ceramic Leaded Chip Carrier.
For outline information see Package Information section.

DIE LAYOUT AND MECHANICAL INFORMATION
Die Dimensions . . . . . . . . . . . . . 206 x 140 x IS (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 4 x 4 mils
Metalization . • . . . • . . . . . . . . . . . . . . . . . . • . . . . . Gold
Backing . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . • . . . . . . . . . . . . • • . . . . • -Vs
Passivation . . . . . . . . . . . . . . . • . . . . . • . . . . . . . Nitride

+5.0V

.v.
D,
D,

n,

+Vs
GROUND

D.
D,(MSB)
OVERFLOW

.V.

•

-Ys
.Ys
ENCODE
GROUND
+VAEF

.v.....

GROUND

•

+Vs
-VRIF

-v...u
LSBolNVERT

STATIC: AD1 =-2V; AD2 • +lIAV
DYNAMIC: AD1 =t2V TRIANGLE WAVE
AD2 =TTL PULSE TRAIN

AD9020 Burn-In Circuit

4-22 VIDEO AID CONVERTERS

REV. A

AD9020

NC

NC
LSBslNVERT

+VSENSE

NC

+VREF

GND
ENCODE
+Vs
-'lis
GND
+Vs
(LSB)0,

-VSENSE
-VREF

AD9020
TOP VIEW

(Not to scale)

D,
D,
D,
D.

+vs
-VS
GND
+Vs
OVERFLOW
D,(MSB)

D,
D,
D.
D,

NC
+Vs

•

+Vs
NC

NC

AD9020 Pin Designations
AD9020 PIN DESCRIPTIONS
Pin No.

Name

Function

1I2REF

Midpoint of internal reference ladder.

2, 16, 28, 29, 35,
41, 42, 54, 64

- VS

Negative supply voltage; nominally -5.0 V ±5%.

3, 6, 15, 18, 25, 30,
33, 34, 37, 40, 45,
52, 55, 65, 68

+ VS

Positive supply voltage; nominally +5 V ±5%.

4,5, 13, 17,27,31,32
36, 38, 39, 43, 53, 66, 67

GROUND

All ground pins should be connected together and to lowimpedance ground plane.

7

3/~EF

Three-quarter point of internal reference ladder.

8,9

ANALOG IN

Analog input; nominally between ±1.75 V.

11

+VSENSE

Voltage sense line to most positive point on internal resistor
ladder. Normally +1.75 V.

12

+VREF

Voltage force connection for top of internal reference ladder.
Normally driven to provide + 1. 75 V at + VSENSE'

14

ENCODE

TTL-compatible convert command used to begin digitizing
process.

19-23,46-50

Do-D.

TTL-compatible digital output data.

51

OVERFLOW

TTL-compatible output indicating ANALOG IN >
+VSENSE'
Voltage force connection for bottom of internal reference
ladder. Normally driven to provide -1.75 V at -VSENSE'
Voltage sense line to most negative point on internal resistor
ladder. Normally -1.75 V.

56
57

-VSENSE

59

LSBs INVERT

NormaIiy grounded. When connected to + Vs, lower order
bits (00 -0 8 ) are inverted.

61

MSB INVERT

Normally grounded. When connected to + Vs' most
significant bit (MSB; D.) is inverted.

63

REV. A

One-quarter point of internal reference ladder.

VIDEO AID CONVERTERS 4-23

AD9020
THEORY OF OPERATION
Refer to the AD9020 block diagram. As shown, the AD9020
uses a modified "flash", or parallel, AID architecture. The analog input range is determined by an external voltage reference
(+VREF and -VREF), nominally ±1.75 V. An internal resistor
ladder divides this reference into 512 steps, each representing
two quantization levels. Taps along the resistor ladder (lI~F'
1I2REF and 3/~EF) are provided to optimize linearity. Rated
performance is achieved by driving these points at 114, 112 and
3/4, respectively, of the voltage reference range.
The AID conversion for the nine most significant bits (MSBs) is
performed by 512 comparators. The value of the least significant
bit (LSB) is determined by a unique interpolation scheme
between adjacent comparators. The decoding logic processes the
comparator outputs and provides a IO-bit code to the output
stage of the convener.
Flash architecture has an advantage over other AID architectures
because conversion occurs in one step. This means the performance of the converter is limited primarily by the speed and
matching of the individual comparators. In the AD9020, an
innovative interpolation scheme takes advantage of flash architecture but minimizes the input capacitance, power and device
count usually associated with that method of conversion.
These advantages occur because of using only half the normal
number of input comparator celli> to accomplish the conversion.
In addition, a proprietary decoding !>Cheme minimizes error
codes. Input control pins allow the user to select from among
Binary, Inverted Binary, Twos Complement and Inverted Twos
Complement coding (See AD9020 Truth Table).

APPLICATIONS
Many of the specifications ui>ed to describe analog/digital converters have evolved from system performance requirements in
these apppcations. Different systems emphasize particular specifications~ depending on how the part is ui>ed. The following
applications highlight some of the specifications and features
that make the AD9020 attractive in these systems.
Wideband Receivers
Radar and communication receivers (baseband and direct IF
digitization), ultrasound medical imaging, signal intelligence and
spectral analysis all place stringent ac performance requirements
on analog-to-digital converters (ADCs). Frequency domain characterization of the AD9020 provides signal-ta-noise ratio (SNR)
and harmonic distortion data to simplify selection of the ADC.
Receiver sensitivity is limited by the Signal-ta-Noise Ratio
(SNR) of the system. The SNR for an ADC is measured in the
frequency domain and calculated with a Fast Fourier Transform
(FFT). The SNR equals the ratio of the fundamental component of the signal (rms amplitude) to the rms value of the
"noise." The noise is the sum of all other spectral components,
including harmonic distortion, but excluding dc.
Good receiver design minimizes the level of spurious signals in
the system. Spurious signals developed in the ADC are the
result of imperfections in the device transfer function (nonlinearities, delay mismatch, varying input impedance, etc.). In
the ADC, these spurious signals appear as Harmonic Distortion.
Harmonic Distortion is also measured with an FFT and is specified as the ratio of the fundamental component of the signal
(rms amplitude) to the rms value of the worst case harmonic
(usually the 2nd or 3rd).

Two-Tone Intermodulation Distortion (IMD) is a frequently cited
specification in receiver design. In narrow-band receivers, thirdorder IMD products result in spurious signals in the pass band
of the receiver. Like mixers and amplifiers, the ADC is characterized with two, equal-amplitude, pure input frequencies. The
IMD equals the ratio of the power of either of the two input
signals to the power of the strongest third-order IMD signal.
Unlike mixers and amplifiers, the IMD does not always behave
as it does in linear devices (reduced input levels do not result in
predictable reductions in IMD).

4-24 VIDEO AID CONVERTERS

REV. A

AD9020 I
~erformance graphs provide typical harmonic and SNR data for
the AD9020 for increasing analog input frequencies. In choosing
an AID converter, always look at the dynamic range for the analog input frequency of interest. The AD9020 specifications provide guaranteed tninimum limits at three analog test frequencies.

Aperture Delay is the delay between the rising edge of the
ENCODE command and the instant at which the analog input
is sampled. Many systems require simultaneous sampling of
more than one analog input signal with multiple ADCs. In these
situations, titning is critical and the absolute value of the aperture delay is not as critical as the matching between devices.

Aperture Uncertainty, or jitter, is the sample-ta-sample variation
in aperture delay. This is especially important when sampling
high slew rate signals in wide bandwidth systems. Aperture
uncertainty is one of the factors which degrades dynamic performance as the analog input frequency is increased.
Digitizing Oscilloscopes
Oscilloscopes provide amplitude information about an obsel"lJed
waveform with respect to time. Digitizing oscilloscopes must
accurately sample this signal, without distorting the information
to be displayed.
One figure of merit for the ADC in these applications is Effective Number of Bits (ENOBs). ENOB is calculated with a sine
wave curve fit and equals:
ENOB = N - LOGz [Error (measured)/Error (ideal)]
N is the resolution (number of bits) of the ADC. The measured
error is the actual rms error calculated from the converter outputs with a pure sine wave input.
The Analog Bandwidth of the converter is the analog input frequency at which the spectral power of the fundamental signal is
reduced 3 dB from its low frequency value. The analog bandwidth is a good indicator of a converter's slewing capabilities.
The Maximum Conversion Rate is defmed as the encode rate at
which the SNR for the lowest analog signal test frequency tested
drops by no more than 3 dB below the guaranteed limit.

I
+FS~
I

I

-FS-

!

I

i

I

I

I

ENCODE~
Imaging Application Using AD9020
The actual resolution of the converter is limited by the thermal
and quantization noise of the ADC. The low frequency test for
SNR or ENOB is a good measure of the noise of the AD9020.
At this frequency, the static errors in the ADC detertnine the
useful dynamic range of the ADC.
Although the signal being sampled does not have a significant
slew rate, this does not imply dynamic performance is not
important. The Transient Response and Overvoltage Recovery
Time specifications insure that the ADC can track full-scale
changes in the analog input sufficiently fast to capture a valid
sample.

Transient Response is the time required for the AD9020 to
achieve full accuracy when a step function is applied. Overvoltage Recovery Time is the time required for the AD9020 to
recover to full accuracy after an analog input signal 150% of full
scale is reduced to the full-scale range of the converter.
Professional Video
Digital Signal Processing (DSP) is now common in television
production. Modern studios rely on digitized video to create
state-of-the-art special effects. Video instrumentation also
requires high resolution ADCs for studio quality measurement
and frame storage.
The AD9020 provides sufficient resolution for these demanding
applications. Conversion speed, dynamic performance and analog bandwidth are suitable for digitizing both composite and
RGB video sources.

Imaging
Visible and infrared imaging systems both require similar characteristics from ADCs. The signal input (from a CCD camera,
or multiplexer) is a time division multiplexed signal consisting of
a series of pulses whose amplitude varies in direct proportion to
the intensity of the radiation detected at the sensor. These varying levels are then digitized by applying encode commands at
the correct times, as shown below.
.

REV. A

VIDEO AID CONVERTERS 4-25

a

AD9020
USING THE AD9020
Voltage References
The AD9020.requires that .the user provide two voltage references: +VREF and -VREP • These two voltages are applied
across an internal resistor ladder (nominally 37 n) and set the
analog input voltage range of the converter. The voltage references should be driven from a stable, low impedance source. In
addition to these two references, three evenly spaced taps on the
resistor ladder (l/~EP' 1/2REF' 3/~p) are available. Providing
a reference to these quarter points on the resistor ladder will
improve the integral linearity of the converter and improve ac
perfOrtnance. (AC and dc specifications are tested while driving
the quarter points at the indicated levels.) The figure below is
not intended to show the transfer function of the ADC, but
illustrates how the linearity of the device is affected by reference
voltages applied to the ladder.

The select resistors (Rs) shown in the schematic (each pair can
be a potentiometer) are chosen to adjust the quarter-point voltage references, but are not necessary if RI-R4 match within
0.05%.

An alternative approach for defining the quarter-point references
of the resistor ladder is to evaluate the integral linearity error of
an individual device, and adjust the voltage at the quarter-points
to minimize this error. This may improve the low frequency ac
perfOrtnance of the converter.
Perfortnance of the AD9020 has been optimized with an analog
input voltage of ± I. 75 V (as measured at ± V SENS~. If the analog input range is reduced below these values, relatively larger
differential nonlinearity errors may result because of comparator
mismatches. As shown in the figure below, perfOrtnance of the
converter is a function of ± VSENSE.

...
III

1100000000

I_---+-----+-~'----'w:..-----l

8
~

~

56

I

zi" 50
!!?

w

w

1~1_---1__.~-~~--__l---~

10.0

62

1111111111 , - - - - , - - - - - , - - - - - . . , . . - - - . . . . , . .

~Z

V ....

/

/

--

9.0 iii'

~

~

!!:!.
8.0

....
C

w

III

7.0

44

0100000000

f---/----;;;;/F---

:Ii

::;)

Z

w

z

i

I&.

0

II:

*

o

Ii

6.0

38

~w
I&.
I&.

W

~&-----~------~----~~----~
-VSENSE
1/4REF
112REF
3/4REF
+VBENSE

Effect of Reference Taps on Linearity
Resistance between the reference connections and the taps of the
first and last comparators causes offset errors. These errors,
called "top and bottom of the ladder offsets," can be nulled by
using the voltage sense lines, + VSENSE and - VSENSE, to adjust
the reference voltages. Current through the sense lines should be
limited to less than 100 !lAo Excessive current drawn through
the voltage sense lines will affect the accuracy of the sense line
voltage.
The next page shows a reference circuit which nulls out the offset errors using two op amps and provides appropriate voltage
references to the quarter-point taps. Feedback from the sense
lines causes the op amps to compensate for the offset errors.
The two transistors limit the amount of current drawn directly
from the op amps; resistors at the base connections stabilize
their operation. The 10 kn resistors (RI-R4) between the voltage sense lines form an external resistor ladder; the quarter
point voltages are taken off this external ladder and buffered by
an op amp. The actual values of resistors RI-R4 are not critical,
but they should match well and be large enough (2:10 kn) to
limit the amount of current drawn from the voltage sense lines.

4-26 VIDEO AID CONVERTERS

32
0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

5.0
2.0

±VSENSE - Volts

AD9020 SNR and ENOB vs. Reference Voltage
Applying a voltage greater than 4 V across the internal resistor
ladder will cause current densities to exceed rated values, and
may cause pertnanent damage to the AD9020. The design of
the reference circuit should limit the voltage available to the
references.
Analog Input Signal.
The signal applied to ANALOG IN drives the inputs of 512
parallel comparator cells (see Equivalent Analog Input figure).
This connection typically has an input resistance of 7 kn, and
input capacitance of 45 pF. The input capacitanCe is nearly constant over the analog input voltage range, as shown in the graph
which illustrates that characteristic.
The analog input signal should be driven from a low distortion,
low noise amplifier. A good choice is the AD9617, a wide bandwidth, monolithic operational amplifier with excellent ac and dc
performance. The input capacitance should be isolated by a
small series resistor (24 n for the AD9617) to improve the ac
performance of the amplifier (see AD90201PCB Evaluation
Board Block Diagram).

REV. A

AD9020
ANALOG INPUT

,
I

~-

"'

101cU

I

I

AD9020 Equivalent Analog Input

+V.

20klJ

"'"
L...._...._

....... DIGITAL BITS

AND OVERFLOW·

-5V

AD9020 Reference Circuit
AD9020 Equivalent Digital Outputs

+S.OV

AD9020 Equivalent Encode Circuit

REV. A

VIDEO AID CONVERTERS 4-27

AD9020
N
ANALOG - - - -..
___
....

INPUT

1,t.
I~

ENCODE

N+1

~------.....---~

1_

-

_ _ _....

I

~ too

r-

I
I

Xl"-_______
DATA FOR N

DATA _ _ _- J .
OUTPUT

X

....I

_

DATA FOR N + 1

t. - Aperture Delay
too - Output Delay
AD9020 Timing Diagram

Timing
In the AD9020, the rising edge of the ENCODE signal triggers
the AID conversion by latching the comparators. (See the
AD9020 Timing Diagram.)
The ENCODE is TTUCMOS compatible and should be driven
from a low jitter (phase noise) source. Jitter on the ENCODE
signal will raise the noise floor of the converter. Fast, clean
edges will reduce the jitter in the signal and allow optimum ac
performance. Locking the system clock to a crystal oscillator
also helps reduce jitter. The AD9020 is designed to operate with
a 50% duty cycle; small (10%) variations in duty cycle should
not degrade performance.
Data Format
The fonnat of the output data (00- 0 9 ) is controlled by the
MSB INVERT and LSBs INVERT pins. These inputs are dc
control inputs, and should be connected to GROUND or + Vs.
The A09020 Truth Table gives information to choose from
among Binaty, Inverted Binary, Twos Complement and Inverted Twos Complement coding.
The OVERFLOW output is an indication that the analog input
signal has exceeded the voltage at + VSENSE. The accuracy of
the overflow transition voltage and output delay are not tested
or included in the data sheet Iitnits. Performance of the overflow
indicator is dependent on circuit layout and slew rate of the encode signal. The operation of this function does not affect the
other data bits (00-09 ). It is not recommended for applications
requiring a critical measure of the analog input voltage.

Analog signal paths should be kept as short as possible and be
properly terminated to avoid reflections. The analog input voltage and the voltage references should be kept away from digital
signal paths; this reduces the amount of digital switching noise
that is capacitively coupled into the analog section of the circuit.
Digital signal paths should also be kept short, and run lengths
should be matched to avoid propagation delay mismatch.
In high speed circuits, layout of the ground circuit is a critical
factor. A single, low impedance ground plane, on the component side of the board, will reduce noise on the circuit ground.
Power supplies should be capacitively coupled to the ground
plane to reduce noise in the circuit. Multilayer boards allow designers to layout signal traces without interrupting the ground
plane and provide low impedance power planes.
It is especially important to maintain the continuity of the
ground plane under and around the A09020. In systems with
dedicated digital and analog grounds, all grounds of the A09020
should be connected to the analog ground plane.
The power supplies (+ VS and - Vs) of the A09020 should
be isolated from the supplies used for external devices; this
further reduces the amount of noise coupled into the AlO converter. Sockets limit the dynamic performance and should be
used only for prototypes or evaluation-PCK Elastomerics
Part # CCS-68-55 is recommended for the LCC package.
(Tel. 215-672-0787)
An evaluation board is available to aid designers and provide a
suggested layout.

Layout and Power Supplies
Proper layout of high speed circuits is always critical but is
particularly important when both analog and digital signals are
involved.

4-28 VIDEO AID CONVERTERS

REV. A

AD9020

--

!II,50

....:::::

~~
~

i<

144

I:

8.0 (

II

8.0

~ ,/+25'C

i

7.0

~

-55"C & +125'C/\

~
\~

6.0

ii

fi

~
4.0 ..

4 6 810
20
40 60 100
INPUT FREQUENCY - MHz

1

26

200

4
6 8 10
20
40
CONVERSION RATE - MSPS

60

r-

,+I25'CL ~...

,

V /...

.....V

60

/.
......
1

~

1/ /~
....

v "..'
.. ..

r-....

+25'C

.,'

'

,

44

60

100

Range

1024
1023
1022

512
5Il
510

02
01
00

.......

V

r--.. I"- .......

l/
1

-1.2~.6

0
+0.6
+1.2
ANALOG INPUT (Ao. ) - Volts

+1.8

Input Capacitance/Resistance vs. Input Voltage

Offset Binary

0= -1.15 V
FS = +1.15 V

--

CAPACITANCE

~

-1.8

AD9020 Harmonics vs. Input Frequency

Step

RESISTANCE

II'

..

4
6 8 10
20
40
INPUT FREQUENCY - MHz

a

70

k1'

40

70

100

V

35

85

60

AD9020 SNR and ENOB vs. Conversion Rate

AD9020 SNR and ENOB vs. Input Frequency
30

1\

ANALOG INPUT = 2.3MHz

~
5.0

1\

26

20

10.0

10.0

ENcol,ERA~=I~

True
MSBINV = "0"
LSBs INV = "0"

Inverted

Twos Complement

MSB INV = "I"
LSBs INV = "1"

True
MSBINV = "I"
LSBs INV = "0"

MSBINV = "0"
LSBs INV = "1"

Inverted

>+ 1.7500
+ 1.7466
+ 1.7432

(l) III III III I

III III I III
1l1l1l1ll0

(I )0000000000
0000000000
0000000001

(1)01l1l1ll1l
01l1ll1l1l
OIl Il III 10

(I) 1000000000
1000000000
1000000001

+0.0034
0.000
.,.0.0034

1000000000
OIl III III I
01 III III 10

OllllIllIl
1000000000
1000000001

0000000000
1l1l1l1l1l
III III 1110

1ll1l1ll1l
0000000000
0000000001

-1.7432
-1.7466
<-1.7466

0000000010
0000000001
OOOOOOOOOO

1l1l1l1l01
1l1l1ll1l0
llllllllll

1000000010
1000000001
1000000000

OIl III 1101
OIl III 1110
01l1l1l1l1

The ovcrflow bit is always 0 except where noted in parentheses ( ). MSB INVERT and LSBs INVERT are considered de controls.

AD9020 Truth Table

REV,A

VIDEO AID CONVERTERS

~29

AD9020
AD90201PCB EVALUATION BOARD·
The AD9020IPCB· Evaluation Board is available from the factory
and is shown here in blgck diagram form. The board includes a
reference circuit that allows the user to adjust both references
and the quarter-point voltages. The AD9617 is included as the
drive amplifier, and the user can configure the gain from -I to

-IS.

On-board reconstruction of the digital data is provided through
the AD9713, a 12-bit monolithic DAC. The analog and reconstructed waveforms can be summed on the board to allow the
user to observe the linearity of the AD9020 and the effects of
the quarter-point voltages. The digital data and an adjustable
Data Ready signa1 are available through a 37-pin edge connector.
DAC
OUT

-5V

+5V

AD97130AC
D

D
ANALOG
INPUT

A09020

TO ERROR
WAVEFORM
CIRCUIT

OUT

+YR1F

.VSENSE
314 f1EF
REFERENCE
CIRCUIT

D.

0,
D.

0,

0,
(USB) D.
OVERFLOW

ENCODE

D
D
Q
D
D
TTL
D LATCHES
D

OUTPUT

1-------,(1

D
D
D
D

CO,::trOR
DATA
READY

i-----t<>t----ot

AD9020/PCB Evaluation Board Block Diagram

4-30 VIDEO AID CONVERTERS

REV. A

IIIIIIIIIIII ANALOG

WDEVICES
FEATURES

Monolithic 8-Bit
Video AID Converter
AD9048 I
FUNCTIONAL BLOCK DIAGRAM

35MSPS Encode Rate
16pF Input Capacitance
550mW Power Dissipation
Industry-Standard Pinouts
MIL-8TO-883 Compliant Versions Available
APPLICATIONS
Professional Video Systems
Special Effects Generators
Electro-Optics
Digital Radio
Electronic Warfare (ECM. ECCM. ESMI

•

GENERAL DESCRIPTION
The AD9048 is an 8-bit, 35MSPS flash converter, made on a
high speed bipolar process, which is an alternate source for the
TDCl048 unit but offers enhancements over its predecessor.
Lower power dissipation makes the AD9048 attractive for a
variety of system designs.

Because of its wide bandwidth, it is an ideal choice for real-time
conversion of video signals. Input bandwidth is flat with no
missing codes.
Clocked latching comparators, encoding logic and output buffer
registers operating at minimum rates of 35MSPS preclude a
need for a sample-and-hold (S/H) or track-and-hold (T/H) in
most system designs using the AD9048. All digital control inputs
and outputs are TTL compatible.
Devices operating over two ambient temperature ranges and
with two grades of linearity are available. Linearities of either
O.5LSB or O.75LSB can be ordered for a commercial range of 0
to + 70·C, or extended case temperatures of - 55"C to + l25·C.
Commercial versions are packaged in 28-pin DIPs; extended
temperature versions are available in ceramic DIP and ceramic
LCC packages. Both commercial units and MIL-STD-883 units
are standard products.
The AD9048 AID converter is available in versions compliant
with MIL-STD-883. Refer to the Analog Devices Military Products
Darabook or current AD9048/883B data sheet for detailed
specifications.

REV. A

VIDEO AID CONVERTERS 4-31

AD9048 ~ SPECIFICATIONS

!tJpicaJ willi nominal suppUes un. othIIWisa noIIId)

ABSOLUTE MAXIMUM RATINGS!
Vccto PGND ..
-O.5V de to +7.0V de
AGND toDGND . . . . . . . . . . . -O.5V de to +O.5V de
VEE to AGND • • . . . . . . . . . . . + O.5V de to -7.0V de
VIN, VRT or Vim to AGND . . . . . . . . . . . +O.5V to VEE
VRT to VRii . . . '• . . • . • . . • . . -2.2V de to +2.2V de
CONY, NMINV or NLINV to DGND. -O.SVdeto +5.5Vde
Applied Output Voltage to DGND. - O.5V de to + 5.5V de2
Applied Output Current, Extemally Forced
. . . . . . . . . . . . . . . . . . . -l.0rnA to + 6.0rnA 3, 4

Output Short-Circuit Duration . . . . . •
Operating Temperature Range (Ambient)
AD9048JNIKNIlJIKJIJQ/KQ . . . . .
AD9048SElSQrrEffQ . . • . . • . . •
Maximum Junction Temperature (Plastic)
Maximum Junction Temperature (Hermetic)
Lead Temperature (Soldering, 10sec)
Storage Temperature Range . . . . . . • . .

o to +70"C
- 55"C to + 125"C
+ 150"C6
. . . . . + 175"C6
. . . . . +300·C
- 65"C to +150"C

ELECTRICAL CHARACTERISTICS !Vee = +5.OV; V = -5.2Y; Differential RefII1IIIC8 Yofta&e=2.OV, IIIIess oIherwise _
EE

AD9048JNIJJIIQ
~(CoadiIioa)

Temp

Test
LeYeI

RESOLUTION
DC ACCURACY
DiffereDtiaI NcmJineority

+25"C
Full
Full

+25"C

+2S"C
Full
+25"C
Full
Full

I
VI
I
VI
V

Full

V

+25"C
Full
+ 25"C
Full
+25"C
+25"C

I
VI
I
VI
III
III

Full
Full
Full
Full
Full
+25"C

V
V
V
VI
V
VI
V

DYNAMIC PERFORMANCE"
Conversion Rate lZ , 14
Apenure Delay
Apenure Uncertainty (Jitter)
Output Delay (tro)" 12
Output Hold Time (toH)"
Transient Responsc"
OvervoItaseRecovery Time'7
RiseTime
FaUTime
OutputTimeSkew"'

+25"C
+ 25"C
+25"C
+25"C
+25"C
+25"C
+25"C
+25"C
+25"C
+ 25"C

I
III
III
I
I
I
V
I
I
I

NMINV and NUNV INPUTS" 12
+ 0.4V Input Current
+2.4VIDputCurrent
+5.5VlnputCurrent

Full
Full
Full

VI
VI
VI

CONVERT INPUT
J..osic: "I" Voltase
LoPe "0" Voltase
J..osic:"I"Cutrent(V,= +2.4V),,12
J..osic: "I" Current (V, = + 5.5V)'·12
Lope 110" CUJ'I'CIltl. 12
Input Clpocitaoce
Convert Puloe Width (LOW)
Convert Pulsc Width (HIGH)

Full
Full
FuU
Full
FuU
+25"C
+25"C
+25"C

VI
VI
VI
VI
VI
III
I
I

Full

No MissiDgCodes
INITIAL OFFSET JlRR.OR
Top of Reference Ladder
BottomofRefemx:e Ladder
Offset Drift CoeftiC:ient
ANALOG INPUT
Input Voltase Ranae
Input Bias Current" I,'
Input Rcsiswx:c
Input Clpacitaoce
Full Power Bandwidth'·
REFI!RENCEINPUT
PoIitiveRefemx:e Voltase"
Neptive Refereuce Voltase"
Differmtial Reference Voltase
Reference Ladder Resistaoce
LadderTemperatuteCoeflicient
Reference LadderCurrent 12
Reference InputllaDdwiclth

Typ

Ala

8
I
VI
I
VI
VI

Intep1ll NcmJineority

Mia

Full

4-32 VIDEO AID CONVERTERS

0.6

0.75
1.0
0.75
1.0

0.4

V"*
Bits

0.3

-2.1;
+0.1
36
60
100

-2.1;
+0.1
60
36
100

-2.1;
+0.1
60
36
100

-2.1;
+0.1
36
60
100

V
p.A
p.A

4

200
40

300

20
10

90

38
2.4
25
13
8
6
8

20
10

0.0
-2.0
2.0
125

50

40

35
5
50
15
5
20

90

9
14
7

125
40

38
2.4
25
9
8

5
50
IS

6
8

4.5

50

16
15

90

5
20
9
14
7

38
2.4
25
9
8
6
8
4.5

200
10
10

0.8
IS
15
500
6

4

20
10

16
15

125

SO

90

0.22
23
10

40

35
5
50
15
5
20
9
14
7

38
2.4
25
9
8
6
8
4.5

200
10
10

0.8
15
15
SOO
6

20

0.8
15
15
500
6

4
18
10

pF
MHz
V
V
V

125
40

n

nrc
mA

MHz
MHz
5
SO
IS

DB
pi

DB '
DB

9
14
7

ns
as
as
as
as

200
10
10

p.A
p.A
,..A

0.8
IS
15
500
6

V
V
p.A
p.A
p.A
pF

20

2.0

4
18
10

kG
kG

300

0.0
-2.0
2,.0

2.0

4
18
10

5

200
40

300

0.22
23
10
35

2.0

2.0

12
12
8
8

0.0
-2.0
2.0

0.22
23
10

200
10
10

4

4

200
40

300

16
15

5

12
12
8
8

-

LSB
LSB
LSB
LSB

20

4.5

18
10

Ala

0.5
0.75
0.4
0.5
0.75
GUARANTEED

0.75
1.0
0.6
0.75
1.0
GUARANTEED
0.4

12
12
8
8

Typ

8

20

0.22
23
10

5

0.5
0.75
0.5
0.75

AD9048TEITQ
Mia

20

16
15

5

0.0
-2.0
2.0

35

Ala

8
0.3

12
12
8
8

Typ

20

4

50

Mia

mV
mV
mV
mV
,..Vr'C

5

10

Ala

GUARANTEED

GUARANTEED

200
40

Tn>

8
0.4

AD9048SEISQ

AD9048KNIKJIKQ
Mia

DB

as

REV. A

AD9048
AD9048JN/JJ/JQ
l'uometot(CoIlditioa.)
ACUNEARITY
In-Bond HIrmoaic:s
de to Z.438MHz"
de to 9.35MHz'O
Sipal-to-Noioo Ratio (SNR)19
1.248MHzlnputFrequ.ncy21
2.438MHz Input Frequmcy'l
1.248MHz Input Frequ.ncy"
2.438MHz Input Freq\lOllCy"
SipaI-to-Noioo Ratio(SNR)20
1.248MHz Input Frequmcy'l
9.35MHzlnputFrequency"
Noioo Power Ratio (NPRr'
DifIotentiai ~.
DifIotentiai Gain"
DlGITALOUTPUTS
LotPc "I" VolllF"
l.oIic "0" VolllF" I.
Short Cin:uit Cunent'

POWER SUPPLY
PooitivcSupplyCurront( + 5.5V)
(VEE ~ - 5.5V)
Neptivc Supply Cu,mll ( - 5.5V)
Nominal Power DiIoipation
Rof_ Ladder Dissipation

To.t
Lnol

MiD

Tn>

+25'C
+25'C

I

47

+25'C
+25'C
+25'C
+25'C

I

+25'C
+25'C
+25'C
+25'C
+25'C

Ala

MiD

Tn>

50
48

49

43.5
43
52.5
52

44
44
53
53

I
V
III
III
III

43.5

44
40.5
39

Fun
Fun
Fun

VI
VI
VI

2.4

+25'C
Fun
+25'C
Fun
+25'C
+25'C

I
VI
I
VI
V
V

Tomp

V

I
I
I

36.5

Max

90

AD9048TEfJ'Q

Ala

u.

MiD

Tn>

50
48

49

55
48

dBc
dBc

44
44
53
53

45
44
54
53

46
46

55
55

43.5
43
52.5
52

dB
dB
dB
dB

45

46

43.5

46

36.5

44
40.5
39

45

40.5
39

36.5

40.5
39

MiD

Tn>

55
48

47

45
44
54
53

46
46

36.5

I

I

2

2

Max

55
55

1
2

1
2

dB
dB
dB
Dqxoo
'II.

0.5

0.5

0.5

0.5

V
V

30

30

30

30

mit.

34

46

90

48
110
120

mit.
mit.
mit.
mit.

2.4

34

AD9048SElSQ

AD9048KNIKJIKQ

2.4

46
48

34

46

110
120

90

48
110
120

550
45

SSO
45

2.4

34

46

90

48
110
120

S50
45

mW
mW

S50
45

NOTES:

I ~ ntinp .... limitins values, to be opplied iDdividuaUy, ODd beyond wbicb the ..rvia:ability of the device may be impoi.!od. FUDCtioDol operatioo UDder
conditioos is DOl lIOCOIIIrily implied. Ezpooure to absolute maaimum ratins conditioos for extended periods of tim. may affect device rdiabiJity.
'Applied
mUll be cuneat-limitecl to specif!ecl .......
'Forciq
mill! be limited '0 specif!ecl .......
'Cunen, is specif!ecl as _ri....boo flowirqj into the device.
'Outpul HiP; ODe pill to pouad; one sec:oad duratioD.
'Typic:aI rhermol impecl.mces (00 air flow) .... as fo1lows:
Conmic:DIP: '1' ~49'CIW;'lc~ 1S"CIW
LCC: ," ~69'CIW;6,c ~21"CIW
Plutic:DIP:',. ~51'C1W;'lc ~ 16"CIW
PLCC: '1' ~ 59;'lc~ 19
To c:ak:ulate iunction temperature (T,)' .... power diaipation (PD) ODd rhermol impedance:
T,~PD(6,.)+T'M'IEHT~PD('lcl~ +TCAS'
'MasweclwitbV,H ~ OVODdCONVERTlow(_plinsmode).
'Vee ~ +5.5V
'V•• ~ -5.5V
1"DourminecI bY bea, frequmoy testins for 00 miainec:odes.
"VaT ~ Vu UDderaJlcircwuEaDCCI.
IlVn = -".9V
"OutpUll terminated witb 40pF ODd lion puB-up miston.
l'Vee ~ +4.5V
l'Intervai from 50% point ofleadinseclse CONVERT puIso 'oc.,.",. in outpUt clara.
I·POl'IuD ICaIc ItepiDput, a..bit KCUnC)' anaiDc:d in specifaed. time.
17Recovcn to 8-bit ICCUraCY in specifted rime after - 3V inpu' ovcrvol.....
''ourput time skew iadudea hiah·ro-Iow UId Iow-ro.hiab rransitions as well as bit-to-bit time skew differences.
19Maswec1.t20MHz.DCOderate ..itb ....... inpu'lclBbelowfUUIIC4le.
lOMaswecI.,35MHzeDCOderate witb ....... inpu'lcIB belowfuU acaIo.

vol_
vol_

IIDY

of these

llRMSIipaI tol1DlDOiIe.
zzPeak, IipaI to I1DI noiJe.

"DC to 8MHz aoiao _width ..i,b 1.248MHz slot; four sipra losdiDs; ZOMHz oocode.
"CIookfrequency ~ 4 x NTSC ~ 14.32MHz. MaswecI witb4l).lREmocIuIa,ec1 ramp.
SpecilicatioDS ...bjoct tocbaD&e withou' notice.

EXPLANATION OF TEST LEVELS
- 100% production tested.
- 100% production tested at + 25"C and
sample tested at specified temperatures.
Test Level III - Sample tested only.
Test Level IV - Parameter is guaranteed by design and
characterization testing.
Test Levell
Test Level II

REV. A

Test Level V - Parameter is a typical value only.
Test Level VI - All devices are 100% production tested at
25"C. 100% production tested at temperature
extremes for military temperature devices;
sample tested at temperature extremes for
commercial/industrial devices.

VIDEO AID CONVERTERS 4-33

AD9048
ORDERING GUIDE
Model

Linearity

Temperature

Package
Option l

AD9048JN
AD9048KN
AD9048JJ
AD9048KJ
AD9048JQ
AD9048KQ
AD9048SE2
AD9048TE2
AD9048SQ2
AD9048TQ2

0.75LSB
0.5LSB
0.75LSB
0.5LSB
0.75LSB
O.sLSB
0.75LSB
o.sLSB
0.75LSB
0.5LSB

Oto +70oe
Oto +70oe
Oto +70"e
Oto +70oe
Oto +70oe
Oto +70oe
- 55°e to + 125°e
- 55°e to + 125°e
- 55°e to + 125°e
- 55°e to + 125°e

N-28
N-28
J-28
J-28
Q-28
Q-28
E-28A
E-28A
Q-28
Q-28

NOTES
'E = LeadlessCeramicChipCarrier;J = J-LeadedCeramic; N = Plastic DIP; Q = Cerdip.
For outline information see Package Information section.
'For specifications, refer to Analog Devices Military Products Databook.

MECHANICAL INFORMATION

127x 140x4 (±2) mils

Die Dimensions
Pad Dimensions
Metalization . .
Backing . . . .
Substrate Potential
Passivation
Die Attach
Bond Wire

Ii

a

•

II
3

a

•

DGNO •

Vee •
V.. 7
V. . .
VEE'

!
Ci
1

Iii

II

rl

C

28 27 21

..

~ ~
:I

.; .; 0

•

z «

25 "GND
.. Ne

Vee

NC

23 V.

V~

AD8048
TOP VIEW

VEE

•• He

VEE

NC

INot toSufe)

., He

VEE

NC

Vee

NC

20 He

,. AGND

DGND11

N"'V

I.

DO

~
Z

4-34 VIDEO AID CONVERTERS

J-Leaded Ceramic:

>

Vcc l0

NC=NOCONNECT

. VEE
. Nitride
Gold Eutectic
I mil Gold; Gold Ball Bonding

PIN CONFIGURATIONS
LCe

DIP

DO

4x4mils
. Gold
None

13 14 "

l!I 8

Ii

.

,. 17 11

!I
!

8

NC -NOCONNECT

c

c; 0

Iii

~

~

I
REV. A

AD9048
FUNCTIONAL DESCRIPTION
Pin
Name

Pin
Name

Description
Eight digital outputs. 01 (MSB) is the most
significant bit of the digital output word;
D8 (LSB) is the least significant bit.

AGND

One of two analog ground returns. Both grounds
should be connected together and to low impedance
ground plane near the AD9048.

DGND

One of two digital ground returns. Both grounds
should be connected together and to low impedance
ground plane near the AD9048.

Most positive reference voltage for internal
reference ladder.

Positive supply terminals; nominally

Negative supply terminals; nominally -S.2V.

CONVERT

Input for conversion signal; sampl,. of analog
input signal taken on rising edge of this pulse.

-5.2V

Analog input signal pin.

NMINV

"Not Most Significant Bit Invert." In normal
operation, this pin floats high; logic LOW at
NMINV inverts most significant bit of digital
output word [01 (MSB)].

NLINV

"Not Least Significant Bit Invert." In normal
operation, thi, pin floats high; logic LOW at
NLINV inverts the seven least significant bits of
the digital output word.

+5.0V

~~~

1r

0.'

v""

VEE

AD2

V 1N

+ S.OV.

Vee

,oon

Most negative reference voltage for internal
u,ference ladder.
Midpoint tap on internal reference ladder.

VEE

AD,

Description

RB

01-D8

(MSBID'

v..

D2

CONVERT

D4

D3

5,00

AD9048
-2.0V

D5

lie

De

r- RT

(LSII De

D7

DIGITAL
GROUND

1
20%

ANALOG
GROUND

~

'k

LOAD
RESISTORS

I
OPTION #1ISTATlCI: A
YNAMIC :

n n U n U nU n U n U n U n U r _- vVII.-..

AD2 .J U

--I5~'1-AD9048 Burn·ln Diagram

REV. A

VIDEO AID CONVERTERS 4-35

4

AD9048
THEORY OF OPERATION
Refer to the block diagram of the AD9048. The AD9048 comprises
three functional sections: a comparator array, encoding logic,
and output latches.
Within the array, the analog input signal to be digitized is compared
with 255 reference voltages. The outputs of all comparators
whose references are below the input signa1level will be high;
and outputs whose references are above that level will be low.

System timing which provides details on delays through the
AD9048, as well as the relationships of various timing events, is
shown in Figure 2, AD9048 Timing Diagram.
Dynamic performance of the AD9048, i.e., typical signa1-ta-noise
ratio, is illustrated in Figures 3 and 4.
nov

"'

The n-of-255 code which results from this comparison is applied
to the encoding logic where it is converted into binary coding.
When it is inverted with dc signals applied to the NLINV and/or
NMINV pins, it becomes twos complement.

CONV.....

After encoding, the. signa1 is applied to the output latch circuits
where it is held constant between updates controlled by the
application of CONVERT pulses.
The AD9048 uses strobed latching comparators in which comparator outputs are either high or low, as dictated by the analog
input level. Data appearing at the output pins have a pipeline
delay of one encode cycle.

r.~

Input signa1levels between the references applied to RT (Pin 18)
and RB (Pin 26) will appear at the output as binary numbers
between 0 and 255, inclusive. Signals outside that range will
show up as either full-scale positive or full-scale negative outputs.
No damage will occur to the AD9048
long as the input is
within the voltage range of VEE to +O.5V.

I
I

RI2

as

-5.ZV

The significantly reduced input capacitance of the AD9048
lowers the drive requirements of the input buffer/amplifier and
also induces much smaller phase shift in the analog input signal.

...

RI2

ANALOG
INPUT
I
I

Applications which depend on controlled phase shift at the
converter input can benefit from using the AD9048 because of
its inherently lower phase shift.

-S.2V

-1.2V

The CONVERT, analog input and digital output circuits are
shown in Figure 1, AD9048 Input/Output Circuits.

t-Ro

COMPARATOR

CELLS

Figure 1. InputiOutputCircuits

N+l
ANALOG

INPUT

CONVERT

OUTPUT
DATA

-rwI-toH

---.J-M

-I

N-l

N

N+l

1- ....
Figure 2. AD9048 Timing Diagram

4-36 VIDEO AID CONVERTERS

REV. A

AD9048
Ceramic 0.I ....F decoupling capacitors should be placed as close
as possible to the supply pins of the AD9048. For decoupling
low frequency signals, use IO ....F tantalum capacitors, also connected as close as practical to voltage supply pins.

50

.

" 1\

.
..

100kHz

Within the AD904R. reference currents may vary because of
coupling betwee'l the clock and input signals. Because of this, it
is important that the ends of the reference ladder, RT (Pin 18)
and RB (Pin 28), be connected to low impedances (as measured
from ground) .

1Mttz

10Mtb:

ANALOG INPUTFREOUENCY -1dB BELOWFUU SCALE

If the AD9048 is being used in a circuit in which the reference
is not varied, a bypass capacitor to ground is strongly recommended. In applications which use varying references, they
must ,be driven from a low impedance source.
0.1

Figure 3. AD9048 Dynamic Performance (20MHz Encode
Rate)

II

50

.
~.
..
!...
..
'Ii

~

::l

1\
01 (MSB)

Ii

100kHz

1MHz

10MHz

ANALOG INPUT mEQUENCY _ 1dB BELOW FULL SCALE

TTL

CONVERT ( . , : f . - - - - - - - - - j CONVERT
SIGNAL

DOILSB)

Figure 4. AD9048 Dynamic Performance (35MHz Encode
Rate)

LAYOUT SUGGESTIONS
Designs which use the AD9048 or any other high-speed device
must follow some basic layout rules to insure optimum
performance.

Figure 5. AD9048 Typical Connections

The first requirement is to have a large, low impedance ground
plane under and around the converter. If the system uses separate
analog and digital grounds, both should be connected solidly
together and to the ground plane as close to the AD9048 as
practical, to avoid ground loop currents.

REV. A

VIDEO AID CONVERTERS 4-37

AD9048
AD9048 Truth Table
Biliary
Step

000
001

···

True

R....

-2.oooVFS
7.843ImVStep

-2.0480VFS
8.000mVSlep

NMINV= I
NLINV = I

O.OOOOV
-0.0078V

O.OOOOV
-0.0080V

00000000
00000001

···

··
·

127
128
129

-O.996IV
-1.0039V
-1.0118V

-1.0160V
-1.0240V
-1.0320V

254
255

-1.992IV
-2.0000V

-2.0320V
-2.0400V

··
·

··
·

4-38 VIDEO AID CONVERTERS

··

·

··
·

Offset Twos
Complement
Inverted

Inverted

True

0
0

0
I

I
0

11111111
11111110

10000000
10000001

01111111
01111110

··
·

·

··

··

·

01111111
10000000
10000001

10000000
01111111
01111110

11111111
00000000
00000801

00000000
11111111
11111110

11111110
11111111

00000001
00000000

01111110
01111111

10000001
10000000

··
·

··
·

··
·

···

REV. A

lO-Bit, 75 MSPS
AID Converter
AD9060 I

11IIIIIIII ANALOG
L.III DEVICES
FEATURES
Monolithic 10-Bit/75 MSPS Converter
EClOutputs
Bipolar (±1.75 VI Analog Input
57 dB SNR @ 2.3 MHz Input
Low (45 pFllnput Capacitance
Mll-STD-883 Compliant Versions Available

FUNCTIONAL BLOCK DIAGRAM
IIIS.LHS
INVElilTIN'II!IIT

APPLICATIONS
Digital Oscilloscopes
Medical Imaging
Professional Video
Radar Warning/Guidance Systems
Infrared Systems

II
.

~(IIIS8J

D,

GENERAL DESCRIPTION
The AD9060 AID converter is a lO-bit monolithic converter capable of word rates of 75 MSPS and above. Innovative architecture using 512 input comparators instead of the traditional 1024
required by other flash converters reduces input capacitance and
improves linearity.
Inputs and outputs are ECL-compatible, which makes the
AD9060 the recommended choice for systems with conversion
rates > 30 MSPS, to minimize system noise. An overflow bit is
provided to indicate analog input signals greater than + VSENSE'

D.

D,

D,

'

1'DoIL88)

....

Voltage sense lines are provided to insure accurate driving of the
± VREF voltages applied to the units. Quarter-point taps on the
resistor ladder help optimize the integral linearity of the unit.
Either 68-pin ceramic leaded (gull wing) packages or ceramic
LCCs are available and are specifically designed for low thermal
impedances. Two performance grades for temperatures of both 0
to +70"C and - 55°C to + 1250C ranges are offered to allow the
user to select the linearity best suited for each application. Dynamic performance is fully characterized and production tested
at + 25°C. MIL-STD-883 units are available.

QROUt4D

The AD9060 AID converter is available in versions compliant
with MIL-STD-883. Refer to the Analog Devices Military
Products Darabook or current AD9060/883B data sheet for detailed specifications.

REV. A

VIDEO AID CONVERTERS 4-39

AD9060-SPECIFICATIONS
3/~, 1/2REP ' I/~p Current . . . . • . . . . . . . . . • :t 10 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature
AD9060JElKElJZIKZ . . . . . . . . . . . . . . . . . . 0 to + 7O"C
Storage Temperature . . . . . . . . . . . . . . . . -65"C to + 150°C
Maximum Junction Tempera~ . . . . . . . . . . . . . . +175"C
Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . + 300"C

ABSOLUTE MAXIMUM RATINGS'
+Vs . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
-.Vs • . . . . . • . • . . . . • . • . . . • . . • . . . . . . . . . . . -6 V
ANALOG IN ....................... -2 V to +2 V
+VIlEP' -VIlEP' 3/~EP' 1I21lEP' lI~p ..... -2 V to +2 V
+VIlEP to -VllEp • • • • • • • • • • • • • • • • • • • • • • • • • • 4.0 V
ENCODE, ENCODE . . . . . . . . . . . . . . . . . . . 0 V to -VS

Parameter (Conditions)

Temp

Test
Level

Integral Nonlinearity
No Missing Codes
ANALOG INPUT
Input Bias Current'
Input Resistance
Input Capacitance'
Analog Bandwidth
REFERENCE INPUT
Reference Ladder Resistance
Ladder Tempco
Reference Ladder Offset
Top of Ladder
Bottom of Ladder
Offset Drift Coefficient
SWITCHING PERFORMANCE
Conversion Rate
Aperture Delay (tA )
Aperture Uncertainty (Jitter)
Output Delay (toD)S
Output Rise Time
Output Fall Time
Output Time SkewS
DYNAMIC PERFORMANCE
Transient Response
Overvoltage Recovery Time
Effective Number of Bits (ENOB)
fIN = 2.3 MHz
fIN = 10.3 MHz
fIN = 29.3 MHz
Signal-to-Noise Ratio·
fIN = 2.3 MHz
fIN = 10.3 MHz
fIN = 29.3 MHz

4-40 VIDEO AlO CONVERTERS

Typ

Max

10

RESOLUTION
DC ACCURACy3
Differential Nonlinearity

AD9060JElJZ
Min

Min

AD9060KEIKZ
Typ
Max

10

+ 25°C
Full
+25"C
Full
Full

I
VI
I
VI
VI

1.0

+25"C
Full
+25"C
+25"C
+25°C

I
VI
I
V
V

0.4

+25"C
Full
Full

I
VI
V

+25°C
Full
+25"C
Full
Full

I
VI
I
VI
V

+25°C
+25°C
+25°C
+ 25°C
+25°C
+2S"C
+2SoC

I
V
V
I
I
I
I

+2S"C
+25°C

V
V

+2S"C
+2SoC
+2SoC

I
IV
IV

8.7
8.0
7.0

9.1
8.6
7.4

+2SoC
+ 25°C
+ 25°C

I
I
I

54
51

56
54
47

1.25

1.25
1.5
2.0
2.5

Units
Bits

0.75
1.0

1.0
1.25
I.S
2.0

LSB
LSB
LSB
LSB

1.0
2.0

mA
mA
ill
pF
MHz

56
66

n
n

Guaranteed

2.0

7.0
45
175

22
14

37

1.0
2.0

56
66

0.4
2.0

7.0
45
175

22
14

37

0.1
45
45

90
90
90
90

45

75

90
90
90
90

1
5
4
1
1
I.S

MSPS
ns
ps, rms
ns
ns
ns
ns

75
1
5
4
1
1
I.S

9
3
3
3

2

10

9
3
3
3

10
10

ns
ns

8.7
8.0
7.0

9.1
8.6
7.4

Bits
Bits
Bits

54
51

S6
54
47

dB
dB
dB

10

44

50

mV
mV
mV
mY
",VI"C

45

50

2

nt"C

0.1

44

REV. A

AD9060
AD9060KElKZ
Typ
Max

Temp

Test
Level

Min

+25"C
+25"C
+ 25"C

I
I
I

54
51
46

56
55
48

54
51
46

58
55
48

dB
dB
dB

+ 25"C
+25"C
+25"C

I
I
I

61
55
47

65
58
50

61
55
47

65
58
50

dBc
dBc
dBc

+25'C
+25'C
+25'C

V
V
V

70
0.5
I

dBc
Degree
%

ENCODE INPUT
Logic "I" Voltage
Logic "0" Voltage
Logic "1" Current
Logic "0" Current
Input Capacitance
Pulse Width (High)
Pulse Width (Low)

Full
Full
Full
Full
+25'C
+25'C
+25'C

VI
VI
VI
VI
V
I
I

DIGITAL OUTPUTS
Logic "I" Voltage
Logic "0" Voltage

Full
Full

VI
VI

+25'C
Full
+25'C
Full
+25'C
Full

VI
VI
VI
VI
VI
VI

420

Full

VI

6

Parameter (Conditions)
DYNAMIC PERFORMANCE
(CONTINUED)
Signal-to-Noise Ratio6
(Without Hannonics)
fIN = 2.3 MHz
fIN = 10.3 MHz
fIN = 29.3 MHz
Hannonic Distortion
fIN = 2.3 MHz
fIN = 10.3 MHz
fIN = 29.3 MHz
Two-Tone Intennodulation
Distortion Rejection7
Differential Phase
Differential Gain

POWER SUPPLY
+ Vs Supply Current
- Vs Supply Current
Power Dissipation
Power Supply Rejection
Ratio (PSRR)'

AD9060JElJZ
Typ
Max

Min

70
0.5
I

-1.1

-1.1
150
150
5

-1.5
300
300

6
6

150
150
5

-1.5
300
300

6
6

-1.1

-1.1
-1.5

150
2.8

500
500
180
190
3.3
3.5
10

-1.5
420
150
2.8

6

Units

V
V
fLA
fLA
pF
ns
ns
V
V

rnA

500
500
180
190
3.3
3.5

W
W

10

rnVN

rnA

rnA
rnA

NOTES
lAbsolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability afthe circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
'Typical thermal impedances (part soldered onto board): 68-pin leaded ceramic chip carrier: 6lC = I'CIW; 6lA = 17'CIW (no air f10W);6 IA = 15'CIW
(air flow = 5()() LFM). 68'pin ceramic LCC: 6lC = 2.6'CIW; 6lA = 15'CIW (no air flow); 6JA = l3'CIW (air flow = 500 LFM).
33J4REF , 1I2REF , and 1/4REF reference ladder taps are driven from de sources at +0.875 V, 0 V, and -0.875 V, respectively. Outputs terminated through 100 n
to -2.0 V; CL < 4 pF. Accuracy of the overflow comparator is not tested and not included in linearity specifications.
'Measured with ANALOG IN = +V'ENSE'
'Output delay measured as worst·case time from 50% point of the rising edge of ENCODE to 50% point of the slowest rising or falling edge of Do-D •. Output
skew measured as worst-case difference in output delay among Do-D9'
6RMS signal to rms noise with analog input signal I dB below full scale at specified frequency.
'Intermodulation measured with analog input frequencies of 2.3 MHz and 3.0 MHz at 7 dB below full scale.
8 Measured as the ratio of the worst-case change in transition voltage of a single comparator for a 5% change in + Vs or - Vs'
Specifications subject to change without notice.

REV. A

VIDEO AID CONVERTERS +-41

II

AD9060
EXPLANATION OF TEST LEVELS
Test Level
I
II

- 100% production tested.
- 100% production tested at + 25°C, and sample tested at
specified temperatures.
III - Sample tested only.
IV - Parameter is guaranteed by design and characterization
testing.
V - Parameter is a typical value only.
VI - All devices are 100% production tested at + 25°C.
100% production tested at temperature extremes for
extended temperature devices; sample tested at temperature extremes for commercial/industrial devices.

GROUND
D.

0,
0,
0,
D,(LSB)
GROUND
GROUND

.v.

ENCODE

EtiCliiiE
+VREF

GROUND
0,
0,

0.
0,
0, (MSB)
OVERFLOW
GROUND
GROUND

-v.

-v...

-v..lSBslNVERT

·v"EJil8£

ORDERING GUIDE

Device
AD9060JZ
AD9060JE
AD9060KZ
AD9060KE
AD9060SZ2
AD9060SE2
AD906OTZ 2
AD9060TE2
AD9060IPCB

Temperature
Range

Package
Option'

o to +700<:
o to +70OC
o to +70°C
o to +70°C

Z-68
E-68A
Z-68
E-68A
Z-68
E-68A
Z-68
E-68A
Evaluation Board

- 5SOC to +l2SoC
- SSOC to +l2SoC
-55°C to + 125°C
- SSOC to + 125°C
oto +1ooc

DIE LAYOUT AND MECHANICAL INFORMATION
Die Dimensions . . . . . . . . . . . . . 206 x 140 x IS (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 4 x 4 mils
Metalization .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . - Vs
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride

NOTES
IE = Ceramic Leadless Chip Carrier; Z = Ceramic Leaded Chip Carrier.
For outline information see Package Information section.
'For specifications, refer to Analog Devices Military Products Databook.

4-42 VIDEO AID CONVERTERS

REV. A

AD9060

NC

NC
LSBslNVERT
NC

+VSENSE

+VREF

ENCODE
ENCODE

-VSENSE
-VREF

+V.

NC

-Vs

AD9060
TOP VIEW
(Not to scale)

GND
GND
(LSB) Do

0,
0,
0,
D.

-v.
GND
GND

OVERFLOW

D,(MSB)

0,
0,
D.
0,

NC
GND

•

GND

NC

NC

AD9060 Pin Designations

AD9060 PIN DESCRIPTIONS
Pin No.

Name

Midpoint of internal reference ladder.

2, 16, 28, 29, 35,
41,42, 54,64

Negative supply voltage; nominally -5.2 V ±5%.

3,6, 15, 30, 33, 34,
37,40,65,68

Positive supply voltage; nominally +5 V ±5%.

4,5, 17, 18,25,27,
31, 32, 36, 38, 39, 43,
45, 52, 53, 66, 67

GROUND

All ground pins should be connected together and to lowimpedance ground plane.

7

3/4REF

Three-quarter point of internal reference ladder.

8,9

ANALOG IN

Analog input; nominaJly between ±1.75 V.

+VSENSE

Voltage sense line to most positive point on internal resistor
ladder. Normally + 1.75 V.

11

12

Voltage force connection for top of internal reference ladder.
Normally driven to provide + 1. 75 V at + VSENSE'

13

ENCODE

Differential ECL convert signal which starts digitizing process.

14

ENCODE

ECL-compatible convert command used to begin digitizing
process.

19-23, 46-50

Do-D.

ECL-compatible digital output data.

51

OVERFLOW

56

-VREF

57

-VSENSE

ECL-compatible output indicating ANALOG IN >
+VSENSE'
Voltage force connection for bottom of internal reference
ladder. Normally driven to provide -1.75 Vat -VSENSE'
Voltage sense line to most negative point on internal resistor
ladder. NoimaIly -1.75 V.

59

LSBs INVERT

Normally grounded. When connected to + V5' lower order
bits (00-08 ) are inverted. Not ECL-compatible.

61

MSBINVERT

Normally grounded. When connected to + V5' most
significant bit (MSB; D.) is inverted. Not ECL-compatible.

63

REV. A

FUDction

1

One-quarter point of internal reference ladder.
VIDEO AID CONVERTERS 4-43

AD9060
MIL-STD-883 Compliance Information
The AD9060 devices are classified within Microcircuits Group
57, Technology Group D (bipolar AID converters) and are constructed in accordance with MIL-STD-883. The AD9060 is
electrostatic sensitive and falls within electrostatic sensitivity
classification Class I. Percent Defective Allowance (PDA) is
computed based on Subgroup 1 of the specified Group A test
list. Quality Assurance (QA) screening is in accordance with
Alternate Method A of Method 5005.
The following apply: Burn-In per 1015; Life Test per 1005;
Electrical Testing per 5004. (Note: Group A electrical testing
assumes TA = Tc = TJ') MIL-STD-883-compliant devices are
marked with "c" to indicate compliance.

+S.ov

AD2
AD3
+2Vo-----('
-2Vo-----{:

STATIC: ADl =-2V; AD 2= ECl HIGH'-...:.....t~::::"T'"_ _ _ _ _ _- - '
AD3 =ECl lOW
T"
DYNAMIC: ADl ±2V TRIANGLE WAVE
ADZ,AD3 =ECl PULSE TRAIN
-S.2V

=

AD9060 Burn-In Connections

THEORY OF OPERATION
Refer to the AD9060 block diagram. As shown, the AD9060
uses a modified "flash," or parallel, ND architecture. The analog input range is determined by an external voltage reference
(+VREF and -VREF), nominally ± 1.75 V. An internal resistor
ladder divides this reference into 512 steps, each representing
rwo quantization levels. Taps along the resistor ladder (1I4REF'
112REF and 3/4REF) are provided to optimize linearity. Rated
performance is achieved by driving these points at 114, 112 and
3/4, respectively, of the voltage reference range.
The ND conversion for the nine most significant bits (MSBs) is
performed by 512 comparators. The value of the least significant
bit (LSB) is determined by a unique interpolation scheme
berween adjacent comparators. The decoding logic processes the
comparator outputs and provides a 10-bit code to the output
stage of the converter.
Flash architecture has an advantage over other ND architectures
because con version occurs in one step. This means the performance of the converter is limited primarily by the speed and
matching of the individual comparators. In the AD9060, an
innovative interpolation scheme takes advantage of flash architecture but minimizes the input capacitance, power and device
count usually associated with that method of conversion.
These advantages occur because of using only half the normal
number of input comparator cells to accomplish the conversion.
In addition, a proprietary decoding scheme minimizes error
codes. Input control pins allow the user to select from among
Binary, Inverted Binary, Twos Complement and Inverted Twos
Complement coding (See AD9060 Truth Table).

4-44 VIDEO AID CONVERTERS

APPLICATIONS
Many of the specifications used to describe analog/digital converters have evolved from system performance requirements in
these applications. Different systems emphasize particular specifications, depending on how the part is used. The following
applications highlight some of the specifications and features
that make the AD9060 attractive in these systems.
Wide band Receivers
Radar and communication receivers (baseband and direct IF
digitization), ultrasound medical imaging, signal intelligence and
spectral analysis all place stringent ac performance requirements
on analog-to-digital converters (ADCs). Frequency domain characterization of the AD9060 provides signal-to-noise ratio (SNR)
and harmonic distortion data to simplify selection of the ADC.
Receiver sensitivity is limited by the Signal-to-Noise Ratio
(SNR) of the system. The SNR for an ADC is measured in the
frequency domain and calculated with a Fast Fourier Transform
(FFT). The SNR equals the ratio of the fundamental component of the signal (rms amplitude) to the rms value of the
"noise." The noise is the sum of all other spectral components,
including harmonic distortion, but excluding dc.
Good receiver design minimizes the level of spurious signals in
the system. Spurious signals developed in the ADC are the
result of imperfections in the device transfer function (nonlinearities, delay mismatch, varying input impedance, etc.). In
the ADC, these spurious signals appear as Hannonic Distortion.
Harmonic Distortion is also measured with an FFT and is specified as the ratio of the fundamental component of the signal
(rms amplitude) to the rms value of the worst case harmonic
(usually the 2nd or 3rd).

REV. A

AD9060
Two-Tone Inrermodulation Distortion (IMD) is a frequently cited
specification in receiver design. In narrow-band receivers, thirdorder IMD products result in spurious signals in the pass band
of the receiver. Like mixers and amplifiers, the ADC is characterized with two, equal-amplitude, pure input frequencies. The
IMD equals the ratio of the power of either of the two input
signals to the power of the strongest third-order IMD signal.
Unlike mixers and amplifiers, the IMD does not always behave
as it does in linear devices (reduced input levels do not result in
predictable reductions in IMD).
Performance graphs provide typical harmonic and SNR data for
the AD9060 for increasing analog input frequencies. In choosing
an AID converter, always look at the dynamic range for the analog input frequency of interest. The AD9060 specifications provide guaranteed minimum limits at three analog test frequencies.

Aperture Delay is the delay between the rising edge of the
ENCODE command and the instant at which the analog input
is sampled. Many systems require simultaneous sampling of
more than one analog input signal with multiple ADCs. In these
situations, timing is critical and the absolute value of the aperture delay is not as critical as the matching between devices.
Aperture Uncertainty, or jitter, is the sample-to-sample variation
in aperture delay. This is especially important when sampling
high slew rate signals in wide bandwidth systems. Aperture
uncertainty is one of the factors which degrades dynamic performance as the analog input frequency is increased.
Digitizing Oscilloscopes
Oscilloscopes provide amplitude information about an observed
waveform with respect to time. Digitizing oscilloscopes must
accurately sample this signal, without distorting the information
to be displayed.
One figure of merit for the ADC in these applications is Effective Number of Bits (ENOBs). ENOB is calculated with a sine
wave curve fit and equals:
ENOB

=N-

LOG2 [Error (measured)/Error (ideal)]

N is the resolution (number of bits) of the ADC. The measured
error is the actual rms error calculated from the converter outputs with a pure sine wave input.
The Analog Bandwidth of the converter is the analog input frequency at which the spectral power of the fundamental signal is
reduced 3 dB from its low frequency value. The analog bandwidth is a good indicator of a converter's slewing capabilities.
The Maximum Conversion Rate is defined as the encode rate at
which the SNR for the lowest analog signal test frequency tested
drops by no more than 3 dB below the guaranteed limit.

REV. A

Imaging
Visible and infrared imaging systems both require similar characteristics from ADCs. The signal input (from a CCD camera,
or multiplexer) is a time division multiplexed signal consisting of
a series of pulses whose amplitude varies in direct proportion to
the intensity of the radiation detected at the sensor. These varying levels are then digitized by applying encode commands at
the correct times, as shown below.

+FS

-FS -

-~

------1
!
,

!!
I

I

~

!
,

ENCODE~
Imaging Application Using AD9060

The actual resolution of the converter is limited by the thermal
and quantization noise of the ADC. The low frequency test for
SNR or ENOB is a good measure of the noise of the AD9060.
At this frequency, the static errors in the ADC determine the
useful dynamic range of the ADC.
Although the signal being sampled does not have a significant
slew rate, this does not imply dynamic performance is not
important. The Transient Response and Overvoltage Recovery
Time specifications insure that the ADC can track full-scale
changes in the analog input sufficiently fast to capture a valid
sample.

Transient Response is the time required for the AD9060 to
achieve full accuracy when a step function is applied. Overvoltage Recovery Time is the time required for the AD9060 to
recover to full accuracy after an analog input signal 150% of full
scale is reduced to the full-scale range of the converter.
Professional Video
Digital Signal Processing (DSP) is now common in television
production. Modern studios rely on digitized video to create
state-of-the-art special effects. Video instrumentation also
requires high resolution ADCs for studio quality measurement
and frame storage.
The AD9060 provides sufficient resolution for these demanding
applications. Conversion speed, dynamic performance and analog bandwidth are suitable for digitizing both composite and
RGB video sources.

VIDEO AID CONVERTERS 4-45

•

AD9060
USING THE AD9060
Voltage References
The AD9060 requires that the user provide two voltage references: +VREP and -VREP.These two voltages are applied
across an internal resistor ladder (nominally 37 0) and set the
analog input voltage range of the convener. The voltage references should be driven from a stable, low impedance source. In
addition to these two references, three evenly spaced taps on the
resistor ladder (1I4REP ' 1/2REP ' 3/4REP ) are available. Providing
a reference to these quarter points on the resistor ladder will
improve the integral linearity of the converter and improve ac
performance. (AC and dc specifications are tested while driving
the quarter points at the indicated levels.) The figure below is
not intended to show the transfer characteristic of the ADC, but
illustrates how the linearity of the device is affected by reference
voltages applied to the ladder.
1111111111

The select resistors (Rs) shown in the schematic (each pair can
be a potentiometer) are chosen to adjust the quarter-point voltage references, but are not necessary if RI-R4 match within
0.05%.
10.0

62

56
III

'D

V V

I

i<
z
Ie 50
w

8z
g
.:.

.

~

--

e--

ii!

~

38

r----,----,----r--~

~

OA

0.6

0.8

1.0

1.2

tYSENSE -

1.4

1.6

1.8

~

2.0

von.

1100000000 1----+---+--""7"-"~~-_t

AD9060 SNR and ENOB vs. Reference Voltage

0100000000

i--+--:;tf'----

ooooooooooL-----~----~------~----~
-VSENSE
1/41U!F
112REF
3141&"
+V8eNBE

Effect of Reference Taps on Linearity
Resistance between the reference connections and the taps of the
first and last comparators causes offset errors. These errors,
called "top and bottom of the ladder offsets," can be nulled by
using the voltage sense lines, + V SENSE and - VSENSE' to adjust
the reference voltages. Current through the sense lines should be
limited to less than 100 ILA. Excessive current drawn through
the voltage sense lines will affect the accuracy of the sense line
voltage.
The next page shows a reference circuit which nulls out the offset errors using two op amps and provides appropriate voltage
references to the quarter-point taps. Feedback from the sense
lines causes the op amps to compensate for the offset errors.
The two transistors limit the amount of current drawn directly
from the op amps; resistors at the base connections stabilize
their operation. The 10 kG resistors (RI-R4) between the voltage sense lines form an external resistor ladder; the quarter
point voltages are taken off this external ladder and buffered by
an op amp. The actual values of resistors RI-R4 are not critical,
but they should match well and be large enough (2:10 kG) to
limit the amount of current drawn from the voltage sense lines.

4-46 VIDEO AID CONVERTERS

An alternative approach for defming the quarter-point references
of the resistor ladder is to evaluate the integral linearity error of
an individual device, and adjust the voltage at the quarter-points
to minimize this error. This may improve the low frequency ac
performance of the converter.
Performance of the AD9060 has been optimized with an analog
input voltage of ± 1.75 V (as measured at ± VSENSE)' If the analog input range is reduced below these values, relatively larger
differential nonlinearity errors may result because of comparator
mismatches. As shown in the figure below, performance of the
converter is a function of ± VSENSE'
Applying a voltage greater than 4 V across the internal resistor
ladder will cause current densities to exceed rated values, and
may cause permanent damage to the AD9060. The design of
the reference circuit should limit the voltage available to the
references.
Analog Input Signal
The signal applied to ANALOG IN drives the inputs of 512
parallel comparator cells (see Equivalent Analog Input figure).
This connection typically has an input resistance of 7 kG, and
input capacitance of 45 pF. The input capacitance is nearly constant over the analog input voltage range, as shown in the graph
which illustrates that characteristic.
The analog input signal should be driven from a low distortion,
low noise amplifier. A good choice is the AD9617, a wide bandwidth, monolithic operational amplifier with excellent ac and dc
performance. The input capacitance should be isolated by a
small series resistor (24 G for the AD9617) to improve the ac
performance of the amplifier (see AD9060/PCB Evaluation
Board Block Diagram).

REV. A

AD9060
ANALOG INPUT

.,

10kU

.2

.2

-Yu..,

AD9060 Equivalent Analog Input

20JHJ

GROUND~
201tll

~
I

I

DIGITAL BITS
AND OVERFLOW

AD9060 Equivalent Digital Outputs
AD9060 Reference Circuit

GROUND

AD9060 Encode and Encode
Equivalent Circuits

REV. A

VIDEO AID CONVERTERS 4-47

AD9060
ANALOG _ _-.N,-INPUT

-1~I'

ENCciiiE ----,;,'r - - -.....
N

ENCODE

\.. ______ .1 '--_ _-.J

-tloo r-

-4r-------~Xr-----

DATA
OUTPUT - - - "

DATA FOR N

DATA FOR N + 1

I. - Aperture Delay
tOD - OUlput Delay

AD9060 Timing Diagram

Timing
In the AD9060, the rising edge of the ENCODE signal triggers
the AJD conversion by latching the comparators. (See the
AD9060 Timing Diagram.) These ENCODE and ENCODE
signals are ECL compatible and should be driven differentially.
Jitter on the ENCODE signal will raise the noise floor of the
converter. Differential signals, with fast clean edges, will reduce
the jitter in the signal, and allow optimum ac performance. In
applications with a fixed, high frequency encode rate, converter
performance is also improved (jitter reduced) by using a crystal
oscillator as the system clock.
The AD9060 units are designed to operate with a 50% duty cycle encode signal; adjustment of the duty cycle may improve the
dynamic performance of individual devices. Since the ENCODE
and ENCODE signals are differential, the logic levels are not
critical. Users should remember, however, that reduced logic
levels will reduce the slew rate of the edges, and effectively increase the jitter of the signal. ECL terminations for the ENCODE and ENCODE signals should be as close as possible to
the AD9060 package to avoid reflections.
In systems where only single-ended signals are available, the use
of a high speed comparator (such as the AD96685) is recommended to convert to differential signals. An alternative is to
connect + 1.3 V (ECL midpoint) to ENCODE and drive the
ENCODE connection single ended. In such applications, clean,
fast edges are necessary to minimize jitter in the signal.
Output data of the AD9060, Do-D9 and OVERFLOW, are also
ECL compatible, and should be terminated through 100 n to
-2 V (or an equivalent load).
Data Format
The format of the output data (Do-D9) is controlled by the
MSB INVERT and LSBs INVERT pins. These inputs are dc
control inputs, and should be connected to GROUND or + Vs.
The AD9060 Truth Table gives information to choose from
among Binary, Inverted Binary, Twos Complement and Inverted Twos Complement coding.
The OVERFLOW output is an indication that the analog input
signal has exceeded the voltage at + VSENSE' The accuracy of
the overflow transition voltage and output delay are not tested

4-48 VIDEO AID CONVERTERS

or included in the data sheet limits. Performance of the overflow
indicator is dependent on circuit layout and slew rate of the encode signal. The operation of this function does not affect the
other data bits (Do-D9). It is not recommended for applications
requiring a critical measure of analog input voltage.
Layout and Power Supplies
Proper layout of high speed circuits is always critical but is particularly important when both analog and digital signals are
involved.
Analog signal paths should be kept as short as possible and be
properly terminated to avoid reflections. The analog input voltage and the voltage references should be kept away from digital
signal paths; this reduces the amount of digital switching noise
that is capacitively coupled into the analog section of the circuit.
Digital signal paths should also be kept short, and run lengths
should be matched to avoid propagation delay mismatch. Terminations for ECL signals should be as close as possible to the receiving gate.
In high speed circuits, layout of the ground circuit is a critical
factor. A single, low impedance ground plane, on the component side of the board, will reduce noise on the circuit ground.
Power supplies should be capacitively coupled to the ground
plane to reduce noise in the circuit. Multilayer boards allow designers to layout signal traces without interrupting the ground
plane and provide low impedance power planes.
It is especially important to maintain the continuity of the
ground plane under and around the AD9060. In systems with
dedicated digital and analog grounds, all grounds of the AD9060
should be connected to the analog ground plane.
The power supplies ( + Vs and - V,) of the AD9060 should
be isolated from the supplies used for external devices; this
further reduces the amount of noise coupled into the AID converter. Sockets limit the dynamic performance and should be
used only for prototypes or evaluation - PCK Elastomerics
Part No. CCS-68-55 is recommended for the LCC package.
(Tel. 215-672-0787)
An evaluation board is available to aid designers and provide a
suggested layout.

REV. A

AD9060
62

-

56

!l!I

-::::

5.

0.0

9.•

~

(44

!:

~

-55"C '+125"'<: / \

I

~

l

6 810

20

40

ul

60

4.0

60 100

65

v.........

+2r

7' .~::'+'--+-+-+----1--4-+-+-1

M'~~~--4L-~6-8~'.~-2O~--~~~60~~'OO

200

INPUT FREQUENCY - MHz

AD9060 SNR and ENOB vs. Input Frequency

AD9060 Harmonics vs. Input Frequency

,•..

62

-

..•

ANALOG INPUT = 2.3MHz

'\

~
z

8.• !!!

'1;,48

~

ID

~

IU

ID

::>

z

~

20

60

80

>

\I;

!i

$

'00

....... ........

02
01
00

True

= "0"
= "0"

0=-1.75V
FS
+1.75 V

MSBINV
LSBs INV

. IJ

!;

20\1;

,
-1.2

-0.6

0

.1.2

.0.6

+1.8

>+1.7500
+1.7466
+ 1.7432

(1) 1111111111

Twos Complement

Inverted

True

= "I"
= "0"

Inverted

MSBINV = "I"
LSBs INV = "I"

MSBINV
LSBs INV

1111111111
1111 III 110

(1 )0000000000
0000000000
0000000001

(1)0 111111111
0111111111
0111111110

(1)1000000000
1000000000
1000000001

+0.0034
0.000
-0.0034

1000000000
0111111111
0111111110

0111111111
1000000000
1000000001

OOOOOOOOOO
1111111111
1111lI1110

1ll111ll11
0000000000
0000000001

-1.7432
-1.7466
<-1.7466

0000000010
0000000001

111111lI01
1111 III 110
1111111111

1000000010
1000000001
1000000000

01l11lI101
0111111110
0111111111

=

512
511
510

/

Input Capacitance/Resistance vs. Input Voltage

Offset Binary

1024
1023
1022

..

3Oi!i

........ ........

ANALOG INPUT 1Au. ) - Yolts

AD9060 SNR and ENOB vs. Conversion Rate

Range

I

~~
V ~

t"-

CONVERSION RATE - USPS

Step

50~

CAPACITANCE

45

-1.8

60

1-

47

!;

IU

4 .•

_. .

RESISTANCE

5 r§46

6.• :II

26

r-

,.

I
IU

.

5.•

7

I

9.•

7 .• IL
0

20,.

'/./;

Z

INPUT FREQUENCY - MHz

56

1/

+'HOC

-55"C

so

6.• _

1\
4

--,- t-

4.

IL

7.0 0

\1\

,

I

8.• ~

/+25"C

26

20

,

ENCO~E RA~ =160~lpS

OOOOOOOOOO

MSBINV = "0"
LSBs INV "I"

=

The overflow bit is always 0 except where noted in psrenthes.. ( ). MSD INVERT and LSD. INVERT are considered de controls.

AD9060 Truth Table

REV. A

VIDEO AID CONVERTERS 4-49

•

AD9060
DAC
OUT

-SV

+SV

AD97120AC
-Vs

+Vs

GND

MSS INVERT
LSBslNVERT

A09060
OUT

TO ERROR
WAVEFORM
CIRCUIT

~EFERENCE

CIRCUIT

SV

(LSB)D.

D

D,
D,
D,

D

D.

D,
D,
D,

D

:r--o+
D
D
D
D
D

0

OUTPUT
DATA

1------,1'1 CONNECTOR

ECL
LATCHES
DATA
READY

D

D,

D

3f4 Uf

(MSB)D,

1/2A£F

OVERFLOW

D
D

CLK

1-----,

1/4REF

-V.....

-V"EF

ENCODE~----fo+---~--~--'
DIFFERENTIAL
ECLCLOCK

TIllING
CIRCUIT

ENCODE~----+O+---~

AD9060lPCB Evaluation Board Block Diagram

AD9060IPCB EVALUATION BOARD
The AD9060IPCB Evaluation Board is avaiiable from the factory
and is shown here in block diagram form. The board includes a
reference circuit that allows 'the user to adjust both references
and the quarter-point voltages. The AD%17 is included as the
drive amplifier, and the user can configure the gain from -1
to -IS.

4-50

VIDEO AID CONVERTERS

On-board reconstruction of the digital data is provided through
the AD9712, a l2-bit monolithic DAC. The analog and reconstructed waveforms can be summed on the board to allow the
user to observe the linearity of the AD9060 and the effects of
the quarter-point voltages. The digital data and an adjustable
Data Ready signal are available via a 37-pin edge connector.

REV. A

Audio OJA Converters
Contents
Page

Audio D/A Converters - Section 5 .............................................. 5-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
ADlS511ADlS61 - 16-BitlIS-Bit 16 x Fs PCM Audio DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
ADlS56 - 16-Bit PCM Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
ADlS60 - IS-Bit PCM Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
ADlS62 - Ultralow Noise, 20-Bit Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
ADlS64 - Complete Dual IS-Bit Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
ADlS65 - Complete Dual IS-Bir 16 x Fs Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55
ADlS66 - Single-Supply Dual 16-Bit Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65
ADlS6S - Single-Supply Dual IS-Bit Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67

II

AUDIO DIA CONVERTERS 5-1

~
~

§
0

Selection Guide
Audio Digital-to-Analog Converters

~
l:>

8
~
~

::l:j

nt
51

Model
ADl851
ADl856
ADl860
ADl861
ADl862
ADl864
ADl865
AD1866
ADl868

Res
Bits

16
16
18
18
20
18
18
16
18

Channels
Single
Single
Single
Single
Single
Dual
Dual
Dual
Dual

SNR

TIID+N

OdB-dBtyp

%typ

110
No Spec
No Spec
110
119
108
110
95
97.5

0.003
0.002
0.002
0.003
0.0012
0.0017
0.0017
0.005
0.004

Supplies
Volts
±5
±5
±5
±5
±5
±5
±5
5
5

to ±12
to ±12
to ±12
to ±12

Power

mWtyp

Pins

Page

100
110
110
100
288
225
225
45
50

16
16
16
16
16
24/28
24/28
16
16

5-3
5-13
5-21
5-3
5-33
543
5-55
5-65
5-67

11IIIIIIII ANALOG
WDEVICES
FEATURES
110 dB SNR
Fast Settling Permits 16x Oversampling
:!:3 V Output
Optional Trim Allows Super-Linear Performance
:!:5 V Operation
16-Pin Plastic DIP and SOIC Packages
Pin-Compatible with AD1856 & AD1860 Audio DACs
2s Complement. Serial Input

16-Bit/18-Bit, 16 x Fs
PCM Audio DACs
AD1851/AD1861 I
FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS
High-End Compact Disc Players
Digital Audio Amplifiers
DAT Recorders and Players
Synthesizers and Keyboards

PRODUCT DESCRIPTION
The ADI8511ADI861 is a monolithic PCM audio DAC. The
ADI851 is a 16-bit device, while the ADI861 is an 18-bit
device. Each device provides a voltage output amplifier, DAG,
serial-to-parallel register and voltage reference. The digital
portion of the ADI8511ADI861 is fabricated with CMOS logic
elements that are provided by Analog Devices' 2 11m ABCMOS
process. The analog portion of the ADI8511ADI861 is fabricated with bipolar and MOS devices as well as thin-film
resistors.
This combination of circuit elements, as well as careful design
and layout techniques, results in high performance audio playback. Laser-trimming of the linearity error affords low total harmonic distortion. An optional linearity trim pin is provided to
allow residual differential linearity error at midscale to be eliminated. This feature is particularly valuable for low distortion
reproductions of low amplitude signals. Output glitch is also
small, contributing to the overall high level of performance. The
output amplifier achieves fast settling and high slew rates, providing a full ±3 V signal at load currents up to 8 rnA. When
used in current output mode, the ADI8511ADI861 provides a
± I rnA output signal. The output amplifier is short circuit protected and can withstand indefinite shorts to ground.
The serial input interface consists of the clock, data and latch
enable pins. The serial 2s complement 'data word is clocked into
the DAC, MSB ftrst, by the external clock. The latch enable
signal transfers the input word from the internal serial input
register to the parallel DAC input register. The ADI851 input
clock can support a 12.5 MHz data rate, while the ADI861 input clock can support a 13.5 MHz data rate. This serial input
port is compatible with second generation digital filter chips
used in consumer audio products. These filters operate at oversampling rates of 2x, 4X, 8x and 16x sampling frequencies.

The ADI8511ADI861 operates with ±5 V power supplies, making it suitable for home use markets. The digital supply, VL,
can be separated from the analog supplies, Vs and - Vs, for reduced digital crosstalk. Separate analog and digital ground pins
are also provided. Power dissipation is 100 mW typical.
The AD18511AD1861 is available in either a 16-pin plastic DIP
or a 16-pin plastic SOIC package. Both packages incorporate the
industry standard pinout found on the AD1856 and ADI860
PCM audio DACs. As a result, the AD18511AD1861 is a dropin replacement for designs where ±5 V supplies have been used
with the AD1856/ADI860. Operation is guaranteed over the
temperature range of - 25·C to + 70·C and over the voltage supply range of ±4.75 V to ±s.25 V.
PRODUCT HIGHLIGHTS
1. ADI8s1 16-bit resolution provides 96 dB dynamic range.
AD1861 18-bit resolution provides 108 dB dynamic range.
2. No external components are required.
3. Operates with ±s V supplies.
4. Space saving 16-pin SOIC and plastic DIP packages.
5. 100 mW power dissipation.
6. High input clock data rates and 1.5 I1S settling time permits
2x, 4x, 8x and 16x oversampling.
7. ±3 V or ±I mA output capability.
8. THD + Noise and SNR are 100% tested.
9. Pin-compatible with ADI856 & ADl860 PCM audio DACs.

The critical specifications of THD+ N and signal-to-noise ratio
are 100% tested for all devices.

REV. A

AUDIO DIA CONVERTERS ~3

II

AD1851/AD1861-SPECIFICATIONS (T

A@

Min
DIGITAL INPUTS
VIH
VIL
IIH' VIH = VL
IlL> V1L = 0.4

+25°C and ±5 V supplies. unless otherwise noted)

Typ

2.0

Max

Units

+VL
0.8

V
V
I1A
I1A

1.0
-10

ACCURACY
Gain Error
Midscale Output Voltage

±I
±1O

%
mV

DRiFf WC to + 70°C)
Total Drift
Bipolar Zero Drift

±25
±4

ppm of FSRI"C
ppm of FSRf'C

1.5
1.0
9

I1S
I1S
V/l1s

350
350

ns
ns

SETTLING TIME (To ±0.0015% of FSR)
Voltage Output
6 V Step
I LSB Step
Slew Rate
Current Output
I rnA Step 10 fl to 100 fl Load
I kfl Load
OUTPUT
Voltage Output Configuration
Bipolar Range
Output Current
Output Impedance
Short Circuit Duration
Current Output Configuration
Bipolar Range (± 30%)
Output Impedance (±30%)
POWER SUPPLY
Voltage
+VL and +Vs
-Vs

:t2.88
±8

±3.12

±3.0
0.1
Indefmite to Common

fl

±1.0
1.7

4.75
-5.25

TEMPERATURE RANGE
Specification
Operation
Storage

0
-25

WARMUP TIME

I

-60

V
rnA

+25

rnA

kfl

5.25
-4.75

V
V

+70
+70
+100

°C
°C
°C
min

Spectficattons subJect to change without notice.

NC =NO CONNECT

AD1851 Functional Block Diagram

5-4 AUDIO DIA CONVERTERS

NC =NO CONNECT

AD1861 Functional Block Diagram

REV. A

AD1851/AD1861
AD1851
Min

Typ

Max

Units

16

Bits

0.003
0.004

0.004
0.008

%
%

0.009
0.009

0.016
0.040

%
%

0.9
0.9

1.6
4.0

%
%

RESOLUTION
TOTAL HARMONIC DISTORTION + NOISE
odB, 990.5 Hz
AD185IN-J, R-J
ADt85IN, R
-20 dB, 990.5 Hz
ADI85IN-J, R-J
ADt85IN, R
-60 dB, 990.5 Hz
AD185IN-J, R-J
ADt85IN, R
D-RANGE* (With A-Weight Filter)
-60 dB, 990.5 Hz AD185IN, R
AD185IN-J, R-J

88
96

SIGNAL-TO-NOISE RATIO

107

MAXIMUM CLOCK INPUT FREQUENCY

12.5

dB
dB
110

dB
MHz

ACCURACY
Differential Linearity Error

±O.OOI

% ofFSR

MONOTONICITY

14

Bits

POWER SUPPLY
Current
+1
-I
Power Dissipation

10.0
-10.0
100

13.0
-15.0

Typ

Max

Units

18

Bits

0.003
0.004

0.004
0.008

%
%

0.009
0.009

0.016
0.040

%
%

0.9
0.9

1.6
4.0

%
%

rnA
rnA

mW

AD1861
Min
RESOLUTION
TOTAL HARMONIC DISTORTION + NOISE
o dB, 990.5 Hz
AD1861N-J, R-J
AD186IN, R
-20 dB, 990.5 Hz
AD1861N-J, R-J
AD186IN, R
-60 dB, 990.5 Hz
AD186IN-J, R-J
AD186IN, R
D-RANGE* (With A-Weight Filter)
-60 dB, 990.5 Hz AD186IN, R
ADI86IN-J, R-J

88
96

SIGNAL-TO-NOISE RATIO

107

MAXIMUM CLOCK INPUT FREQUENCY

13.5

dB
dB
110

dB
MHz

ACCURACY
Differential Linearity Error

±0.001

% ofFSR

MONOTONICITY

15

Bits

POWER SUPPLY
Current
+1
-I
Power Dissipation

10.0
-10.0
100

13.0
-15.0

rnA
rnA

mW

'Tested in accordance with EIAJ Test Standard CP-307.
Specifications subject to change without notice.

REV. A

AUDIO DIA CONVERTERS 5-5

•

AD1851/AD1861
PIN ASSIGNMENTS

ABSOLUTE MAXIMUM RATINGS·
VL to DGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.50 V
Vs to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.50 V
-Vs to AGND . . . . . . . . . . . . . . . . . . . . . -6.50 V to 0 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . -0.3 V to VL
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Short Circuit . . . . . . . . . . . . . . . Indefmite Short to Ground
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . + 300°C, 10 sec
Storage Temperature . . . . . . . . . . . . . . . . . -60°C to + 100°C
"Stresses greater than those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a Slress rating only and
fum;tional operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affcct device reliability.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

. ANALOG NEGATIVE POWER SUPPLY
LOGIC GROUND
LOGIC POSITIVE POWER SUPPLY
NO CONNECTION
CLOCK INPUT
LATCH ENABLE INPUT
SERIAL DATA INPUT
NO INTERNAL CONNECTION"
V OUT
VOLTAGE OUTPUT
FEEDBACK RESISTOR
R.
SJ
SUMMING JUNCTION
ANALOG GROUND
AGND
CURRENT OUTPUT
lOUT
MSBADJ MSB ADJUSTMENT TERMINAL
TRIM
MSB TRIMMING POTENTIOMETER TERMINAL
ANALOG POSITIVE POWER SUPPLY
Vs
-Vs
DGND
VL
NC
CLK
LE
DATA
NC

·PIN 8 HAS NO INTERNAL CONNECTION; -V, FROM AD1856 OR AD1860
SOCKET CAN BE SAFELY APPLIED.

CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted.

c:J

WARNING!

~~EDEVICE

ORDERING GUIDE
Model

Resolution

THD+N

Package
Option·

ADl851N
ADI851N-J
ADl851R
ADl85IR-J
ADI861N
ADl86IN-J
AD1861R
ADl861R-J

16 Bits
16 Bits
16 Bits
16 Bits
18 Bits
18 Bits
18 Bits
18 Bits

0.008%
0.004%
0.008%
0.004%
0.008%
0.004%
0.008%
0.004%

N-16
N-16
R-I6A
R-I6A
N-16
N-16
R-16A
R-l6A

"N = Plastic DIP Package; R = Small Outline (SOIC) Package.
For outline information see Package Information section.

Typical Performance
10
175

-

150

-IOdB

125

~I

100

2

,,/

75

.01

50

~B

--

25

...

OdB
.001

10

.2

14

CLOCK FREQUENCY - MHz

Power Dissipation vs. Clock Frequency

~6

AUDIO DIA CONVERTERS

-30 -20 -10

0

10

20 30 40 50
TEMPERATURE _ °C

80

70

80 80

THD vs. Temperature

REV. A

AD1851/AD1861
TOTAL HARMONIC DISTORTION
Total harmonic distortion plus noise (THD+ N) is defined as
the ratio of the square root of the sum of the squares of the values of the first 19 harmonics and noise to the value of the fundamental input frequency. It is usually expressed in percent
(%).

THD+ N is a measure of the magnitude and distribution of linearity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depending on the amplitude of the output signal. Therefore, to be most
useful, THD+N should be specified for both large (0 dB) and
small signal amplitudes (-20 dB and -60 dB).
The THD+ N figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. This specification, therefore, provides a
direct method to classify and choose an audio DAC for a desired
level of performance.
SETTLING TIME
Settling time is the time required for the output of the DAC to
reach and remain within a specified error band about its final
value, measured from the digital input transition. It is a primary
measure of dynamic performance.
MIDSCALE ERROR
Midscale error, or bipolar zero error, is the deviation of the actual analog output from the ideal output (0 V) when the 2s complement input code representing half scale is loaded in the input
register.
D-RANGE DISTORTION
D-range distortion is equal to the value of the total harmonic
distortion + noise (THD+N) plus 60 dB when a signal level of
-60 dB below full scale is reproduced. D-range is tested with a
1 kHz input sine wave. This is measured with a standard Aweight filter as specified by EIAJ Standard CP-307.
SIGNAL-TO-NOISE RATIO
The signal-to-noise ratio (SNR) is defined as the ratio of the amplitude of the output when a full-scale output is present to the
amplitude of the output with no signal present. This is measured with a standard A-weight filter as specified by EIAJ
.
.
Standard CP-307.

REV. A

SERIAL-TO-PARALLEL
CONVERSION

Figure 1. AD18511AD1861 Functional Block Diagram

FUNCTIONAL DESCRIPTION
The AD18SlIAD1861 is a complete monolithic PCM audio
DAC. No additional external components are required for operation. As shown in Figure I above, each chip contains a voltage
reference, an output amplifier, a DAC, an input latch and a parallel input register.
The voltage reference consists of a bandgap circuit and buffer
amplifier. This combination of elements produces a reference
voltage that is unaffected by changes in temperature and age.
The DAC output voltage, which is derived from the reference
voltage, is also unaffected by these environmental changes.
The output amplifier uses both MOS and bipolar devices to produce low offset, high slew rate and optimum settling time.
When combined with the on-chip feedback resistor, the output
op amp converts the output current of the AD18SlIAD1861 to a
voltage output.
The DAC uses a combination of segmented decoder and R-2R
architecture to achieve consistent linearity and differential
linearity. The resistors which form the ladder structure are fabricated with silicon chromium thin film. Laser-trimming of
these resistors further reduces linearity error, resulting in low
output distortion.
The input register and serial-to-parallel converter are fabricated with CMOS logic gates. These gates allow the achievement
of fast switching speeds and low power consumption. This
contributes to the overall low power dissipation of the
ADl8SlIADl861.

AUDIO DIA CONVERTERS 5-7

5

AD1851/AD1861
Analog Circuit Considerations
GROUNDING RECOMMENDATIONS
The ADI8511ADI861has .two ground pins, designated Analog
and Digital gtound. The analog gtound pin is the "high quality" ground reference point for the device. The analog gtound
pin should be connected to the analog common point in the
system. The output load should also be connected to. that same
point.

However, three separate voltage supplies are not necessary for
good circuit performance. For example, Figure 3 illustrates a
system where only a single positive lind a single negative supply
are available.
In this example, the positive logic and positive analog supplies
must both be connected to + 5 V, while the negative analog supply will be connected to -5 V. Performance would benefit from
a measure of isolation between the supplies introduced by using
simple low pass ftIters in the individual power supply leads.

The digital ground pin returns ground {;urrent from the digital
logic portions of the ADI8511ADI861 circuitry. This pin should
be connected to the digital common point in the system.
As illustrated in Figure 2, the analog and digital grounds should
be connected together at one point in the system.
+5V

+5V

Figure 3. Alternate Recommended Schematic

-5V

Figure 2. Recommended Circuit Schematic

POWER SUPPLIES AND DECOUPLING
The AD1851/AD1861 has three power supply input pins. The
± V s supplies provide the supply voltliges to operate the linear
portions of the DAC including the voltage reference, output amplifier and control amplifier. The ± Vs supplies are designed to
operate at ± 5 V.
The + VL supply operates the digital portions of the chip including the input shift register and the input latching circuitry. The
+VL supply is designed to operate at +5 V.
Decoupling capacitors should be used on all power supply pins.
Furthermore, good engineering practice suggests that these capacitors be placed as close as possible to the package pins as
well as to the common points. The logic supply, +Vu should
be decoupled to digital common, while the analog supplies,
± Vs, should be decoupled to analog common.
The use of three separate power supplies will reduce feedthrough from the digital portion of the system to the linear portion of the system, thus contributing to improved performance.

As with most linear circuits, changes in the power supplies will
affecf the output of the DAC. Analog Devices recommends that
well regulated power supplies with less than 1% ripple be incorporated into the design of any system using the AD 18511
AD1861.

OPTIONAL MSB ADJUSTMENT
Use of an optional adjustment circuit allows residual differential
linearity error around midscale to be eliminated. This error is
especially important when low amplitUde signals are being reproduced. In those cases, as the signal amplitude decreases, the
ratio of the midscale differential linearity error to the signal amplitude increases, thereby increasing THD.
Therefore, for best performance at low output levels, the optional MSB adjust circuitry shown in Figure 4 may be used to
improve performance. The adjustment should be made with a
small signal input (---'20 dB or -60 dB).

T~
~

MSB
ADJUST

Figure 4. Optional THD Adjust Circuit

~8

AUDIO DIA CONVERTERS

REV. A

AD1851/AD1861
AD1851 DIGITAL CIRCUIT CONSIDERATIONS
AD1851 Input Data

AD1861 DIGITAL CIRCUIT CONSIDERATIONS
AD1861 Input Data

Data is transmitted to the AD 1851 in a bit stream composed of
16-bit words with a serial, MSB first format. Three signals must
be present to achieve proper operation. They are the Data,
Clock and Latch Enable (LE) signals. Input data bits are
clocked into the input register on the rising edge of the Clock
signal. The LSB is clocked in on the 16th clock pulse. When all
data bits are loaded, a low-going Latch Enable pulse updates the
DAC input. Figure 5 illustrates the general signal requirements
for data transfer to the AD 1851.

Data is transmitted to the AD1861 in a bit stream composed of
18-bit words with a serial, MSB first format. Three signals must
be present to achieve proper operation. They are the Data,
Clock and Latch Enable (LE) signals. Input data bits are
clocked into the input register on the rising edge of the Clock
signal. The LSB is clocked in on the 18th clock pulse. When all
data bits are loaded, a low-going Latch Enable pulse updates the
DAC input. Figure 7 illustrates the general signal requirements
for data transfer to the AD 1861.

CLOCK
DATA

CLOCK

~'UU'LJ'LJ'LJ'LJ'LJ'.

/\

LATCH~r
Figure 5. Signal Requirements for AD1851
Figure 6 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished properly. The input pins of the AD1851 are both TTL and 5 V
CMOS compatible. The input requirements illustrated in Figures 5 and 6 are compatible with data outputs provided by popular DSP filter chips used in digital audio playback systems.
The AD1851 input clock can run at a 12.5 MHz rate. This
clock rate will allow data transfer rates for 2 x, 4 x or 8 x or
16x oversampling reconstructions.

DATA

LATCH~r
Figure 7. Signal Requirements for AD1861
Figure 8 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished properly. The input pins of the AD1861 are both TTL and 5 V
CMOS compatible. The input requirements illustrated in Figures 7 and 8 are compatible with data outputs provided by popular DSP filter chips used in digital audio playback systems.
The AD1861 input clock can run at a 13.5 MHz rate. This
clock rate will allow data transfer rates for 2 x, 4x or 8 x or
16x oversampling reconstructions.

.7'"

.EXT
BITS CLOCkED
' -_ _ _ _...::::====~~===TOSHIFTREGIBTER

Figure 6. Timing Relationships of AD1851 Input Signals

REV. A

Figure 8. Timing Relationships of AD1861 Input Signals

AUDIO DIA CONVERTERS 5-9

•

AD1851/AD1861
APPLICATIONS
Figures 9 through 12 show connection diagrams for the AD1851
and ADl861 and the Yamaha YM3434 and the NPC
SM5813AP/APT digital ftIter chips.

ClK

Mf-O{) lATCH
DlO Q~HI--O DATA

AD1851

SCOO--+.....

YM3434

WCO
DRO

0---1--+--0 DATA
'-11--0 lATCH
ClK

AD1851

Figure 9. AD1851 with Yamaha YM3434 Digital Filter

+5V

ClK
lATCH
Xl

ST

DlO

DATA

AD1861

SCO

YM3434

wco
DRO

":"

DATA
LATCH
ClK

AD1861

Figure 10. AD1861 with Yamaha YM3434 Digital Filter

5-10 AUDIO DIA CONVERTERS

REV. A

AD1851/AD1861
ClK
~~-oLATCH

DOL
BCKO

o----tHI--Q DATA

AD1851

o--f....

SM5813AP/APT
WCKO
DOR

o----tHI--Q
L-j~-O

DATA
LATCH
ClK

+5V

AD1851

Figure 11. AD1851 with NPC SM5813APIAPT Digital Filter

•

ClK

r-Ir--o lATCH
DOL ()O--lH~-O DATA
BCKO

AD1861

0--+...

SM5813AP/APT
WCKO
DCR

o--IH--O DATA
~+--()

LATCH
ClK

AD1861

Figure 12. AD1861 with NPC SM5813APIAPT Digital Filter

REV. A

AUDIO DIA CONVERTERS 5-11

~12

AUDIO DIA CONVERTERS

16-Bit
PCM Audio DAC
AD1856 I

~ANALOG

WDEVICES

BLOCK DIAGRAM

FEATURES
0.0025% THD
Fast Settling Permits 2x, 4x or 8x Oversampling
:!:3V Output
Optional Trim Allows Superlinear Performance
:!:5V to :!:12V Operation
16-Pin Plastic DIP or SOIC Package
Serial Input
APPLICATIONS
Compact Disc Players
Digital Audio Amplifiers
DAT Recorders and Players
Synthesizers and Keyboards

PRODUCT DESCRIPTION
The AD1856 is a monolithic 16-bit PCM Audio DAC. Each device provides a voltage output amplifier, 16-bit DAC, 16-bit
serial-to-parallel input register and voltage reference. The digital
portion of the ADl856 is fabricated with CMOS logic elements
that are provided by Analog Devices' BiMOS. II process. The
analog portion of the AD1S56 is fabricated with bipolar and
MOS devices as well as thin film resistors.

The ADl856 can operate with ±5V to ± 12V power supplies
making it suitable for both the portable and home-use markets.
The digital supplies, VLand - V'-' can be separated from the
analog supplies, Vsand - Vs, for reduced digital crosstalk. Separate analog and digital ground pins are also provided.

This combination of circuit elements, as well as careful design
and layout techniques, results in high performance audio playback. Laser trimming of the linearity error affords extremely
low total harmonic distortion. An optional linearity trim pin is
provided to allow residual differential linearity error at midscale
to be eliminated. This feature is particularly valuable for low
distortion reconstructions of low amplitude signals. Output
glitch is also small contributing to the overall high level of performance. The output amplifier achieves fast settling and high
slew rates, providing a full ± 3V signal at load currents up to
SmA. The output amplifier is short circuit protected and can
withstand indefinite shorts to ground.

The AD1856 is packaged in a 16-pin plastic DIP or SOlC package and incorporates the industry-standard pinout. Operation is
guaranteed over the temperature range of - 25°C to + 70°C and
over the voltage supply range of ±4.75 to ± 13.2V.

The serial input interface consists of the clock, data and latch
enable pins. The serial 2s complement data word is clocked into
the DAC, MSB first, by the external data clock. The latch enable signal transfers the input word from the internal serial input register to the parallel DAC input register. The input clock
can support a lOMHz clock rate. This serial input port is compatible with popular digital filter chips used in consumer audio
products. These filters operate at oversampling rates of 2x, 4x
and 8 x sampling frequency.

REV. A

Power dissipation is llOmW typical with ±5V supplies and is a
typical 300mW when ± 12V supplies are used.

PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.

Total harmonic distortion is 100% tested.
MSB trim feature allows superlinear operation.
The AD1856 operates with ±5V to ± 12V supplies.
Serial interface is compatible with digital filter chips.
1.5fJ.s settling time permits 2x, 4x and 8x oversampling.
No external components are required.
96dB dynamic range.
±3V or ± ImA output capability.
16-bit resolution.
2s complement serial input words.
Low cost.
16-pin plastic DIP or SOlC package.

AUDIO DIA CONVERTERS 5-13

5

AD1856 -SPECIFICATIONS (typical at T, = +25"C and ±5V supplies unless otherwise noted)
Min

Typ

RESOLUTION
DIGITAL INPUTS

VIH
V1L
I,H,V1H=VL
IluVIL = 0.4

Clock Input Frequency

2.4
0

Max

Units

16

Bits

VL
0.8
1.0
-10

V
V
",A

10

,...A
MHz

ACCURACY
Gain Error
Bipolar Zero Error
Differential Linearity Error
Noise (rms, 20Hz to 20kHz) @ Bipolar Zero

±2.0
±30
±O.OOI
6

TOTAL HARMONIC DISTORTION
0dB, 99O.5Hz
ADl856N-K, R·K
ADl856N-J, R-J
ADl856N, R
-20dB,990.5Hz
ADl856N-K, R-K
ADl856N-J, R-J
ADl856N, R
ADl856N-K, R-K
-6OdB, 99O.5Hz
ADl856N-J, R-J
ADl856N, R

0.002
0.002
0.002
0.018
0.018
0.018
1.8
1.8
1.8

MONOTONICITY

IS

Bits

DRIFT (0 to + 70OC)
Total Drift
Bipolar Zero Drift

±25
±4

ppmofFSRrC
ppm ofFSRrC

SETTLING TIME (to ±0.006% of FSR)
Voltage Output
6V Step
ILSB Step
Slew Rate
Current Output
IrnA Step 100 to 1000 Load
IkO Load

1.5
1.0
9
350
350

",s
",s
VI",s
ns
ns

WARM-UP TIME
OUTPUT
Voltage Output Configuration
Bipolar Range
Output Current
Output Impedance
Short Circuit Duration
Current Output Configuration
Bipolar Range (±30%)
Output Impedance (±30%)
POWER SUPPLY
Voltage, +VL and +Vs
Voltage, -VL and -Vs
Current, +1, VL and Vs = +5V, 10MHz Clock
Current, -I, -VL and -Vs = -5V, IOMHz Clock
Current, +1, VLand Vs = +12V, 10MHzClock
Current, ~I, -VL and -Vs = -12V, 10MHz Clock

0.0025
0.004
0.008
0.020
0.040
11.040
2.0
4.0
4.0

I

±3

V
rnA
0

0.1
Indefinite to Common
1.0
1.7
4.75
-13.2

5
-5

10
-12
12
-15
110

rnA
kO
13.2
-4.75
15
-IS

V
V
rnA
rnA
rnA
mA

ISO

mW
mW

+70
+70
+100

°C
OC
°C

135
0
-25

-60

%
%
%
%
%
%
%
%
%

min

±8

POWER DISSIPATION
Vs and VL = ±5V, 10MHz Clock
VsandV L = ±12V, 10MHzClock
TEMPERATURE RANGE
Specification
Operation
Storage

%
mV
% ofpSR
",V

Specifications subject to change without notice.
Specifications sbown in boldface are tested on all production units at final test.

5-14 AUDIO DIA CONVERTERS

REV. A

AD1856
ABSOLUTE MAXIMUM RATINGS·
VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 13.2V
Vs to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 13.2V
-VL to DGND . . . . . . . . . . . . . . . . . . . . . . . -13.2 to OV
-Vs to AGND . . . . . . . . . . . . . . . . . . . . . . . - 13.2 to OV
Digital Inputs to DGND . . . . . . . . . . . . . . . . . -0.3 to VI.
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . ±O.3V
Short Circuit Protection . . . . . . . . Indefinite Short to Ground

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . + 300°C, 10sec
Storage Temperature . . . . . . . . . . . . . . . . -60°C to + 100°C
*Stresses greater than those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and fune·
tional uperation of the device at these or any other conditions above those
indicated in (he operational section of this specification is not implied. Exposure [0 absolute maximum rating conditions for extended periods may
affect device reliability.

PIN DESIGNATIONS

CONNECTION DIAGRAM

v.
TRIM
MSB ADJ
lOUT

AGND
SJ
R,

Pin
I
2
3
4
5
6
7

8
9
10
II
12
13
14
15
16

Function

Description

-Vs
DGND
VI.
NC
CLK
LE
DATA
-VL
VOUT
RF
SJ
AGND

Analog Negative Power Supply
Digital Ground
Logic Positive Power Supply
No Connection
Data Clock Input
Latch .Enable Input
Serial Data Input
Logic Negative Power Supply
Voltage Output
Feedback Resistor
Summing Junction
Analog Ground
Current Output
MSB Adjustment Terminal
MSB Trimming Potentiometer Terminal
Analog Positive Power Supply

lOUT

MSBADJ
TRIM
Vs

CAUTION ________________________~----~----~~----~~
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted.

WARNING!

cJ

~~EDEVICE

Definition of Specifications
TOTAL HARMONIC DISTORTION
Total Harmonic Distortion (THD) is defined as the ratio of the
square root of the sum of the squares of the values of the harmonics to the value of the fundamental input frequency. It is
expressed in percent (0/0) or decibels (dB).
THD is a measure of the magnitude and distribution of linearity
error and differential linearity error. The distribution of these
errors may be different, depending on the amplitude of the output signal. Therefore, to be most useful, THD should be specified for both large and small signal amplitudes.
SETTUNG TIME
Settling Time is the time required for the output to reach and
remain within a specified error band about its final value, measured from the digital input transition. It is the primary measure
of dynamic performance.
DYNAMIC RANGE
Dynamic Range is the specification that indicates the ratio of the
smallest signal the converter can resolve to the largest signal it is
able to produce. As a ratio, it is usually expressed in decibels

REV. A

(dB). The theoretical dynamic range of an n-bit converter is approximately (6xn) dB. In the case of the 16-bit AD1856, that is
%dB. The actual dynamic range of a convener is less than the
theoretical value due to limitations imposed by noise and quantization and other errors.
BIPOLAR ZERO ERROR
Bipolar Zero Error is the deviation in the actual analog output
from the ideal output (OV) when the 2scomplement input code
representing half scale (all Os) is loaded in the input register.
DIFFERENTIAL UNEARITY ERROR
Differential Linearity Error is the measure of the variation in
analog value, normalized to full scale, associated with a 1LSB
change in the digital input. Monotonic behavior requires that
the differential linearity error not exceed lLSB in the negative
direction.
MONOTONICITY
A DIA converter is monotonic if the output either increases or
remains constant as the digital input increases.

AUDIO DIA CONVERTERS 5-15

•

AD1856
FUNCTIONAL DESCRIPTION
The AD1856 is a complete, monolithic l6-bit PCM audio DAC.
No additional external components are required for operation.
As shown in the block diagram, each chip contains a voltage
reference, an output amplifier, a 16-bit DAC, a 16-bit input
latch and a 16-bit serial-to-parallel input register.
The voltage reference consists of a bandgap circuit and buffer
amplifier. This circuitry produces an output voltage that is
stable over time and temperature changes.
The 16-bit D/A converter uses a combination of segmented decoder and R-2R architectures to achieve consistent linearity and
differential linearity. The resistors which form the ladder structure are fabricated with silicon-chromium thin film. Laser trimming of these resistors further reduces linearity error
resulting in low output distortion.

The ± VL supplies are also designed to operate from ± 5V to
± 12V subject only to the limitation that - VL may not be more
negative than -Vs.
Decoupling capacitors should be used on all power supply pins.
Furthermore, good engineering practice suggests that these capacitors be placed as close as possible to the package pins as
well as the common points. The logic supplies, ± VL> should be
decoupled to digital common; and the analog supplies, ± Vs,
should be decoupled to analog common.
The use of four separate power supplies will reduce feedthrough
from the digital portion of the system to the linear portions of
the system, thus contributing to good performance. However,
+5V

The output amplifier uses both MOS and bipolar devices to
produce low offset, high slew-rate and optimum settling time.
When combined with the on-board feedback resistor, the output
op amp can convert the output current of the ADl856 to a voltage output.

ANALOG CIRCUIT CONSIDERATIONS
GROUNDING RECOMMENDATIONS
The AD1856 has two ground pins, designated ANALOG and
DIGITAL ground. The analog ground pin is the "high quality"
ground reference point for the device. The analog ground pin
should be connected to the analog common point in the system.
The output load should also be connected to that same point.
The digital ground pin returns ground current from the digital
logic portions of the ADl856 circuitry. This pin should be connected to the digital common point in the system.
As illustrated in Figure 1, the analog and digital grounds should
be connected together at one point in the system.
+5V

+5V

Figure 2. Alternate Recommended Schematic

four separate voltage supplies are not necessary for good circuit
performance. For example, Figure 2 illustrates a system where
only a single positive and a single negative supply are available.
Given that these two supplies are within the range of ± 5V to
± 12V, they may be used to power the AD 1856. In this case, the
positive logic and positive analog supplies may both be connected to the single positive supply. The negative logic and
negative analog supplies may both be connected to the single
negative supply. Performance would benefit from a measure of
isolation between the supplies introduced by using simple lowpass filters in the individual power supply leads.
A; with most linear circuits, changes in the power supplies will
affect the output of the DAC. Analog Devices recommends that
well regulated power supplies with less than 1% ripple be incorporated into the design of any system using these devices.

ANALOG
COMMON
-5V

-5V

Figure 1. Recommended Circuit Schematic

POWER SUPPLIES AND DECOUPLING
The ADl856 has four power supply input pins. ±Vs provide
the supply voltages to operate the linear portions of the DAC
including the voltage reference, output amplifier and control
amplifier. The ± Vs supplies are designed to operate from ± 5V
to ±12V.
The ± VL supplies operate the digital portions of the chip including the input shift register and the input latching circuitry.

5-16 AUDIO DIA CONVERTERS

TOTAL HARMONIC DISTORTION
The THD figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. The THD specification, therefore, provides a direct method to classify and choose an audio DAC for a
desired level of performance.
Analog Devices tests and grades all ADl856s on the basis of
THD performance. A block diagram of the test setup is shown
in Figure 3. In this test setup, a digital data stream, representing a Odb, - 20dB or -60dB sine wave is sent to the device under test. The frequency of this waveform is 990.5Hz. Input data
is sent to the ADl856 at a 4xFs rate (176.4kHz). The ADl856
under test produces an analog output signal with the on-board
op amp.

REV. A

AD1856

I--

4)(Fs

DATA
RATE
'I-BIT
DIGITAL
WAVEFORM
GENERATOR

,, , ,

0

L

,

0

,

0

,

0

4096PT.

.. ANIrvZER

o
,, ,
0

.--. ,

,,

o ,

o

0

1

23 CYCLES--l

f\./\.. .l\/\

AD1856
DATA
LATCH
VOUT
CLOCK

0

0
0
1

,,

%3V

l

99O.5Hz
NOTCH

u
:1--1

-~~

LOW PASS

10

Figure 3. Block Diagram of Distortion Test Circuit

The automatic test equipment digitizes 4096 samples of the output test waveform, incorporating 23 complete cycles of the sine
wave. A 4096 point FFf is performed on the results of the test.
Based on the first 9 harmonics of the fundamental 990.5Hz output wave, the total harmonic distortion of the device is calculated. Neither a deglitcher nor an MSB trim is used during the
THO test.
The circuit design, layout and manufacturing techniques employed in the production of the A01856 result in excellent
THO performance. Figure 4 shows the typical unadjusted THO
performance of the A01856 for various amphtudes of a 1kHz
output signal. As can be seen, the A01856 offers excellent performance, even at amplitudes as low as -60dB. Figure 5 illustrates the typical THO vs. frequency performance.

II

0.1

#'
I

I
i
~

0.5

O.U

1-2OdBI

0.01

O.ODS

~

O.OU

V

IFULL SCALEI

Jill

0.00 1
100

'000

10000

FREQUENCY - Hz

13.0

Figure 5. Typical THO vs. Frequency
#'
I

1.0

Ii

0.1

I

r.....

""'

I
~

OPTIONAL MSB ADJUSTMENT
Use of an optional adjustment circuit allows residual differential
linearity errors around midscale to be eliminated. These errors
are especially important when low amplitude signals are being
reproduced. In those cases, as the signal amplitude decreases,
the ratio of the midscale differential linearity error to the signal
amplitude increases and THO increases.

I'.
,. BITS........

f'...

0.0'

"'-...
0.001

-10

-so

-40

-30

-20

-10

VOUT - dB

NOTE
OdB:z:FULl SCALE

Therefore, for best performance at low output levels, the optional MSB adjust circuitry shown in Figure 6 may be used.
This circuit allows the differential linearity error at midscale to
be zeroed out. However, no adjustments are required to meet
data sheet specifications.

nuM~~~~~r---,~~~~~--~~~,_~.a~--~G)_v.
Figure 4. Typical Unadjusted THO vs. Amplitude

Msa ADJ

80n5

>30ns

Timing
Figure 7 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished properly. The input pins of the ADI860 are both TTL and SV
CMOS compatible, independent of the power supplies used.
The input requirements illustrated in Figures 6 and 7 are compatible with the data outputs provided by popular DSP filter
chips used in digital audio playback systems. The ADI860 input
clock can run at a 12.SMHz rate. This clock rate will allow data
transfer rates for 2x, 4x or 8x oversampling reconstruction.
The application section of this datasheet contains additional
guides for using the ADI860 with various DSP filter chips available from Sony, NPC and Yamaha.

---~
>30"5

CLK

>15"s

>60n5

>40n5

>4O"s
LATCH ENABLE (LEI

>40"5

INTERNAL DAC INPUT REGISTER
UPDATED WITH 18 MOST RECENT BITS

)
~

DATA

\_~~=~~~

BITS CLOCKED
TO SHIFT REGISTER

Figure 7. Timing Relationships of Input Signals

5-28 AUDIO DIA CONVERTERS

REV. A

AD1860
APPLICATIONS OF THE ADl860 PCM AUDIO DAC
The ADl860 is a versatile digital-to-analog converter designed
for applications in consumer digital audio equipment. Portable,
car and home compact disc player, digital audio amplifier and
DAT schemes can all use the ADI860. Various circuit architectures are popular in these systems. They include stereo playback
sections featuring one DAC per system, one DAC per audio

DATA
CLOCK

NONINVERTING
SHA
(OPTIONAL)
OUT

LATCH AD1860

SAMPLE
LEFT

channel (left/right) or multiple DACs per channel. Furthermore,
these architectures use different output reconstruction rates to
accomplish these functions including reproduction at the sample
rate Fs (Ix), at twice the sample rate (2xFs ), at four times
the sample rate (4xFs ) and even at eight times the sample rate
(8xFs )' Fs is 44. 1kHz for CD and 48kHz for DATapplications.

_-===::==~~~

LEFT
OUTPUT

___---1

RIGHT
OUTPUT

S~~ri~~---------------------~~---~~~-----~
Figure 8. AD1860 in a One DAC per System Architecture
One DAC per System
Figure 8 shows a circuit using one ADl860 per system to reproduce both channels of a typical first generation stereo digital
audio system. The input data is fed to the ADl860 in a format
which alternates between left channel data and right channel
data. The output of the ADl860 is switched between the left
channel and right channel output samplelhold amplifiers
(SHAs). The SHAs demultiplex and deglitch the output of the
AD1860. The timing diagram for the control signals for this circuit are shown in Figure 9.
However, when only two SHAs are used, the actual system performance is limited by the phase delay introduced by the demultiplexed format. This undesirable phase delay is caused by the
fact that the data words presented to the inputs of the DAC represent samples taken at precisely the same point in time. But

CLOCK

DATA

l----- LEFT WORD ----*'---- AtGHT WORO-------!

LATCHl~~r
g~ t'l"5~'
~ 1.5~s
m;n

m;n

~~~ ~------+I--------SA~~

L-J

when reconstructed and demultiplexed by a single DAC, these
same outputs occur at slightly diff~rent times.
By incorporating a noninverting SHA into the circuit, the phase
delay can be eliminated. In Figure 8, the optional SHA ensures
that the left channel output appears at the same time as the
right channel output. This minor change to the circuit eliminates the artificially induced phase delay by restoring simultaneous outputs.
Following the outputs of the SHAs are low pass filters. These
filters are required in any sampled data system to remove unwanted aliased components introduced by the sample and reconstruction operations.
One DAC per Channel
A second approach used to eliminate phase delay between left
and right channels employs one DAC per channel. In this architecture, the input data bitstream for each channel is transmitted
and then latched into the input register of each DAC. This "second generation" approach is illustrated in Figure 10. A standard
implementation of a low pass filter is shown at the output of
each DAC. An optional sampleihold amplifier could be connected between the DACs and the LPFs to deglitch th.: outputs.
This is not required, however, to achieve the specified performance.
Two DACs per Channel
Another architecture uses two DACs per channel. In this
scheme each DAC reproduces one half of the output waveform.
The advantage obtained with this structure is that midscale differentiallinearity error no longer affects the zero crossing points
of the waveforms. Its effects are shifted to the points where the
output waveform crosses 112 ± 114 full scale. The result is that
THD performance for low amplitude signals is greatly improved.

Figure 9. Control Signals for One DAC Circuit

REV. A

AUDIO DIA CONVERTERS 5-29

•

AD1860
CLOCK AD1860
LATCH
DATA AGND

DIGITAL
FILTER'
CHIP

DATA AGND
OUTo--JV""'...""'....~.,..,.....-I
LATCH
CLOCK AD1860

L
LOW PASS FILTER SECTION

OUTPUT SECTION
WITH MUTE CONTROL

Figure 10. One DAC per Channel Architecture with LPF

DIGITAL FILTERING AND OVERSAMPLING
Oversampling is a term which refers to playback techniques in
which the reconstruction frequency used is an integral (2 or
more) multiple of the original quantized data rate. For example,
in compact disc stereo digital audio playback units, the original
quantized data sample rate is 44. 1kHz. Popular oversampling
rates are 2x or 4xFs , yielding reconstruction rates of 88.2 and
176.4kHz, respectively.

68kHz. A 4xrate (176.4kHz) has unwanted components extending down to approximately 156kHz. The filter response needed
to remove these frequency components can now be less steep.
This means that a lower order filter may be used resulting in
less distortion at lower cost. Linear filters with 3 or 5 poles, as
shown in Figure 10, are adequate to do the job and are quite
common in digital audio products employing oversampling
techniques.

Oversampling is used to ease the performance constraints of the
low pass filters which follow the reconstruction DAC. In any
signal reconstructed from sampled data, unwanted frequency
components are introduced in the output spectrum; these components are centered at the reconstruction frequency. When a
44. 1kHz reconstruction frequency is used, the actual frequency
band of interest is 20Hz to 20kHz, and the band of unwanted
"image" frequency components extends from 44. 1kHz to
approximately 24kHz. These unwanted components must be
removed with a low-pass filter of very high order. First generation digital audio systems often used low-pass filters of 9, II and
even 13 poles. Linear implementations of these filters are expensive, difficult to manufacture and can produce distortion due to
varying group delay characteristics.

Oversampling techniques require the serial input data. stream to
run at the same integral multiple of the original data rate. So,
while the constraints on the output low-pass filter are eased, the
constraints on the serial digital input port and the settling time
of the output stage are not.

When a 2 x reconstruction frequency (88:2kHz) is used, the lowest frequency components now extend down to approximately

5-30 AUDIO DIA CONVERTERS

The actual oversampling operation takes place in the digital filter chip (DSP) which is located "upstream" from the DAC. The
digital filter accepts data from the media and adds the additional
reconstruction points according to the algorithm and coefficients
stored in the filter chip. Since the digital filters actually interpolate these additional reconstruction points, they have earned the
name "interpolation filters".
The AD 1860 is compatible with popular digital filter chips
used in digital audio products such as the Sony CXD1088, the
Yamaha YM3434 and the NPC SM5813.

REV. A

AD1860
DAC. The digital filter chip provides 18-bit data words to the
DACs at 4xFs ' Very high performance can be achieved.

Figure II illustrates the combihation of a second generation
digital filter chip, the Sony CXD1088, and the ADI860 audio

16.9344MHz

~

+5V

l---oCLOCK
LATCH
OUT
DATA AD1860

LEFT
OUTPUT

r--""--~

BCK ORES

Voo

03 0--+---1--1

D20-~--~----~-4

CXD1088Q

D10--+--4

DATA
LATCH
OUT
l--~ CLOCK AD1860

RIGHT
OUTPUT

,

,

OUTPUT
SECTION
24

24
BCK
LRCK ____

-I--------------------~

I

L ____ .J

L ____ .J
OPTIONAL
SHA SECTION

____________________

~-----

LRo~r~L~1~~~R~1~-Ir-~L2;-lL~R~2~~~L~3~1-~R~3--r-~L~4~L-~R~4__r_----1

J

L _ _ _ _ _~

LRo~r----------~~------------1-------------~R~1~-----=::~~r-----01
02
03

----.L__

LSB

MSB

~

____

~----------L_

APTL ________________

~------L_

LSB
MSB
________S_--------IL____

____________________

APTR __________________________

~

~

________

_________F------L________

Figure 11. 4xFs with the CXD1088Q

REV. A

AUDIO DIA CONVERTERS 5-31

II

AD1860
and right channel.output pins on the YM3434. This implementation does not require any external components to achieve the
full108dB dynamic range afforded by the 18-bit ADI860 audio
DAC. As before, optional samplelh'oICl signals are provided.

Figure 12 illustrates the combination of a Yamaha YM3434 digital filter chip and two ADI860 audio DACs. This combiIlation
of components results in 8 x F s oversampling reconstruction
rates. This rate allows the use of lower order output low pass
filters than would be required with lower oversampling rates,
without sacrificing performance. In this high performance CD
player application, the DAC input data is simultaneously transmitted to the input registers of the DACs through dedicated left

Figure 13 shows the schematic for 8xFs when two AD1860s are
used with an NPC SMS813AP/APT digital filter chip. As can be
seen, this application is very similar to the one shown in Figure
12. See Figure 10 for an example of a typical LPF.

CLOCK
LEFT
OUTPUT

LATCH
DLO r---11--