1992_Analog_Devices_Audio_Video_Reference_Manual 1992 Analog Devices Audio Video Reference Manual

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REFERENCE

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ADCs
DACs

Special Functions
OpAmps

DSP
App Notes

OP AMPS · AUDIO ADCs • VIDEO ADCs •

.... ANALOG

..... OEVICES

AUDIO DACs • VIDEO DACs • SPECIAL FUNCT ION AUD IO ·
SPECIAL FUNCTION VIDEO • DSP • APPLICATION NOTES

.... ANALOG
WOEVICES

1992

AUDIONIDEO
REFERENCE
MANUAL

General Information
Operational Amplifiers
Audio AID Converters
Video AID Converters
Audio D/A Converters
Video D/A Converters

©Analog Devices, Inc., 1992
All Rights ReselVed

Special Function Audio Products
Special Function Video Products

IlANALOG

DEVICES

Digital Signal Processing Products

II

••
II
•II
•II
a

Appendix

III
II
lEI
III

Index

II

Other Products
Application Notes
Package Information

.... ANALOG

.... DEVICES
1992

AUDIOIVIDEO REFERENCE MANUAL
© Analog Devices, Inc., 1992
All Rights Reserved

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
Analog Devices.
U.S.:

RE29,992, RE30,586, RE31,850, 3,729,660, 3,793,563, 3,803,590, 3,842,412, 3,868,583, 3,890,611, 3,906,486,
3,932,863, 3,940,760, 3,942,173, 3,942,173, 3,946,324, 3,950,603, 3,961,326, 3,978,473, 3,979,688,
4,020,486, 4,029,974, 4,034,366, 4,054,829, 4,055,773, 4,056,740, 4,068,254, 4,088,905, 4,092,639,
4,109,215, 4,118,699, 4,123,698, 4,131,884, 4,136,349, 4,138,671, 4,141,004, 4,142,117, 4,168,528,
4,213,806, 4,228,367, 4,250,445, 4,260,911, 4,268,759, 4,270,118, 4,272,656, 4,285,051, 4,286,225,
4,313,083, 4,323,795, 4,333,047, 4,338,591, 4,340,851, 4,349,811, 4,363,024, 4,374,314, 4,374,335,
4,395,647, 4,399,345, 4,400,689, 4,400,690, 4,404,529, 4,427,973, 4,439,724, 4,444,309, 4,449,067,
4,460,891, 4,471,321, 4,475,103, 4,475,169, 4,476,538, 4,481,708, 4,484,149, 4,485,372, 4,491,825,
4,511,413, 4,521,764, 4,538,115, 4,542,349, 4,543,560, 4,543,561, 4,547,766, 4,547,961, 4,556,870,
4,562,400, 4,565,000, 4,572,975, 4,583,051, 4,586,019, 4,586,155, 4,590,456, 4,596,976, 4,601,760,
4,608,541, 4,622,512, 4,626,769, 4,633,165, 4,639,683, 4,644,253, 4,646,056, 4,646,238, 4,675,561,
4,678,936, 4,683,423, 4,684,922, 4,685,200, 4,687,984, 4,694,276, 4,697,151, 4,703,283, 4,707,682,
4,717,883, 4,722,910, 4,739,281, 4,742,331, 4,751,455, 4,752,900, 4,757,274, 4,761,636, 4,769,564,
4,774,685, 4,791,318, 4,791,551, 4,800,524, 4,804,960, 4,808,908, 4,811,296, 4,814,767, 4,833,345,
4,855,585, 4,855,618, 4,855,684, 4,857,862, 4,859,944, 4,862,073, 4,864,454, 4,866,505, 4,878,770,
4,884,075, 4,885,585, 4,888,589, 4,891,533, 4,891,645, 4,899,152, 4,902,959, 4,904,921, 4,924,227,
4,928,103, 4,928,934, 4,929,909, 4,933,572, 4,940,980, 4,957,583, 4,962,325, 4,969,823, 4,970,470,
4,978,871, 4,980,634, 4,983,929, 4,985,739, 4,990,797, 4,990,803, 4,990,916, 5,008,671, 5,010,297,
5,021,120, 5,026,667, 5,027,085, 5,030,849,

3,909,908,
4,016,559,
4,092,698,
4,210,830,
4,309,693,
4,383,222,
4,454,413,
4,503,381,
4,558,242,
4,604,532,
4,677,369,
4,709,167,
4,771,011,
4,839,653,
4,879,505,
4,926,178,
4,973,978,
5,010,337,

France:

111.833,70.10561,75.27557,7608238,77 20799, 78 10462,79 24041,80 00960, 80 11312,80 11916,81 02661,
81 14845,8303140,9608238
Japan:

1,092,928,1,242,936,1,242,965,1,306,235, 1,337,318, 1,401,661, 1,412,991, 1,432,164, 1180463
West Germany:

2,014034, 25 40 451.7, 26 11 858.1
U.K.:

1,310,591, 1,310,592, 1,537,542, 1,590,136, 1,590,137, 1,599,538, 2,008,876, 2,032,659, 2,040,087, 2,050,740,
2,054,992, 2,075,295, 2,081,040, 2,087,656, 2,103,884, 2,104,288, 2,107,951, 2,115,932, 2,118,386, 2,119,139,
2,119,547, 2,126,445, 2,126,814, 2,135,545
Canada:

984,015,1,006,236,1,025,558,1,035,464, 1,054,248, 1,140,267, 1,141,034, 1,141,820, 1,142,445, 1,143,306, 1,150,414,
1,153,607, 1,157,571, 1,159,956, 1,177,127, 1,177,966, 1,184,662, 1,184,663, 1,191,715, 1,192,310, 1,192,311,
1,192,312, 1,203,628, 1,205,920, 1,212,730, 1,214,282, 1,219,679, 1,219,966, 1,223,086, 1,232,366, 1,233,913,
1,234,921
Sweden:

7603320-8

General Information
Contents
Page

President's Letter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
How to Use this Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Master Selection Guides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Product Assurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20

GENERAL INFORMATION 1-1

II

1-2 GENERAL INFORMA TION

Since its founding in 1965, Analog Devices has dedicated itself to the design, manufacture and marketing of products used in real-world signal processing applications. Our
product universe includes data converters, operational amplifiers, digital signal processors, special function devices and application specific ICs that combine these functions
on a single chip.
Analog's core strengths are its analog circuit design expertise and state-of-the-art linear
and mixed-signal semiconductor process technology, which have led to a long list of
technically innovative products. These strengths are supported by a number of manufacturing locations around the world and by a technical sales force trained and ready to
serve your needs.
The decade of the '90s offers many exciting opportunities for linear and mixed-signal
ICs for a wide range of emerging applications in computer peripherals, telecommunications equipment and consumer products, including the automotive market. Many of
these involve processing audio and/or video information, which has become an increasingly significant part of Analog's business in recent years, and which was enhanced last
year by the acquisition of Precision Monolithics.
Among other successes, our efforts to provide technically innovative and economically
practical products for audio and video signal processing applications have resulted in
Analog becoming a leading supplier of both DIA converters used in compact disc players and RAM-DACs used in VGA displays. And our monolithic SSM-2125 Dolby ProLogic Surround Sound Decoder has been recognized as the best integrated solution
available for implementing this function in consumer electronics products.
This first edition of our AudiolVideo Reference Manual is a clear sign of our commitment to continue developing and marketing high performance integrated circuits for a
wide range of audio and video signal processing applications in professional, consumer,
automotive, medical, military and industrial applications. Here you will find data sheets
containing complete specifications and applications information on 103 product families, as well as 40 application notes to assist you in your product development efforts.
The products described in this reference guide represent integrated solutions that offer
higher performance, increased reliability and lower overall cost, and as a consequence,
will help you design products that make your company more competitive in its markets. We look forward to serving your needs for these types of products for many years
to come.

5 fti

Ray Stata
Chairman of the Board
Chief Executive Officer
Analog Devices

GENERAL INFORMA TION 1-3

II

Introduction
Analog Devices designs, manufactures and sells worldwide
sophisticated electronic components and subsystems for use in
real-world signal processing. More than six hundred standard
products are produced in manufacturing facilities located
throughout the world. These facilities encompass all relevant
technologies, including several embodiments of CMOS, BiMOS,
bipolar and hybrid integrated circuits, each optimized for specific attributes-and assembled products in the form of potted
modules, printed-circuit boards and instrument packages.
State-of-the-art technologies (including surface micromachining)
have been utilized (and in many cases invented) to provide
timely, reliable, easy-to-use advanced designs at realistic prices.
Our popular IC products are available in both conventional and
surface-mount packages (SOIC, LCC, PLCC), and many of our
assembled products employ surface-mount technology to reduce
manufacturing costs and overall size. A quarter-century of successful applications experience and continuing vertical integration insure that these products are oriented to user needs. The
ongoing application of today's state-of-the-art and the invention
of tomorrow's state-of-the-art processes strengthen the leadership position of Analog Devices in standard data-acquisition and
signal-processing products and make us a strong contender in
high performance mixed-signal ASICs.
MAJOR PROGRESS
Audio electronic components are an important subset of products for equipment designers instrumenting the multimedia
interface between information in electronic form and human
communication capabilities (particularly sight, speech, hearing,
and the audible and visual arts).

The Audio Handbook, published by Precision Monolithics, Inc.
-which was acquired by and became a Division of Analog
Devices in 1990-described many of our analog IC products for
the audio equipment subset. However, we also manufacture
many analog, digital, and mixed-signal products that are useful
in the processing and display of video signals, as well as conversion products for professional and consumer audio equipment. It
appeared to make good sense in this new edition to expand the
publication's concept to include all products-including many
new ones-designed for the multimedia interface.
Important products described here that we have introduced for
this industry include:
• the AD9020/9060 families of lO-bit "flash" converters that
provide interfacing for both conventional and HDTV digital
video systems

>Dolby is a registered trademark of Dolby Laboratories, Inc.
CEG/DAC aod TrimDAC are trademarks of Analog Devices, Inc.

1-4 GENERAL INFORMA TlON

• the ADSP-2105 and ADSP-21020 flXed- and floating-point
digital signal processors for high speed implementation of
computational algorithms
• the ADV7141146/48 CEGIDAC·· family of monolithic RAMDACs, designed to eliminate "jaggies" and improve color resolution in VGA displays at low cost
• the AD712 family of low-noise-and-distortion op amps for
audio preamplification
• the AD847 op amp for video line driving and other high
speed applications
• the ADl879 dual-channel 18-bit ADC and the ADl865 dualchannel DAC for stereo applications
• the DAC-8840 and DAC-8841 TrimDACs'" for digitally controlled circuit parameter adjustment
• the SSM-20I8 voltage-controlled amplifier, for audio panning,
equalization, remote volume control, and compressor/limiter
applications-using patented Operational Voltage-ControlledElement COVCE) architecture
• the SSM-2125 Dolby* Pro-Logic Surround Sound Matrix
Decoder, a low cost chip that gives home-entertainment system manufacturers a practical way to bring the benefits of
theater-type sound to consumers
• the SSM-2142 and SSM-2141 balanced line driver and line
receiver for transporting analog signals with minimal signal
degradation
Many more could have been added to this list.

AUDIONIDEO REFERENCE MANUAL
The Audio/Video Reference Manual is one of a set of books
cataloguing Analog Devices products. It is accompanied by the
Linear Products Databook and the two-volume Data Converter

Reference Manual.
This volume provides comprehensive technical data and application notes on 103 Analog Devices product families designed for
incorporation in professional and consumer audio, video, imaging, and multimedia equipment. Included are the following:
•
•
•
•

comprehensive data sheets and package information
selection guides for fmding products rapidly
a set of 40 application notes
ordering guide, publications list, and worldwide sales
directory
• indexes:
-application notes, by topic and by part numbers
-all Analog Devices products, listed a1phanumerically by
part number and keyed to catalog location.

TECHNICAL SUPPORT
Our extensive technical literature discusses the technology and
applications of products for real-world signal processing. Besides
tutorial material and comprehensive data sheets, including a
large number in our Databooks, we offer Application Notes,
Application Guides, Technical Handbooks (at reasonable prices),
and several free serial publications; for example, Analog
Productlog provides brief information on new products being
introduced, and AnalogDialogue, our technical magazine, provides in-depth discussions of new developments in analog and
digital circuit technology as applied to data acquisition, signal
processing, control, and test. DSPatch ,. is a quarterly newsletter that brings its readers up-to-date applications information on
our DSP products and the general field of digital signal processing. We maintain a mailing list of engineers, scientists, and
technicians with a serious interest in our products. In addition
to Databook catalogs-and general short-form selection guideswe also publish several short-form catalogs on specific product
families. You will fmd typical publications described on pages
13-4 to 13-7 at the back of the book.

SALES AND SERVICE
Backing up our design and manufacturing capabilities and our
extensive array of publications, is a network of distributors, plus
sales offices and representatives throughout the United States
and most of the world, staffed by experienced sales and applications engineers. Our Worldwide Sales Directory, as of the publication date, appears on pages 13-8 and 13-9 at the back of the
book.

RELIABILITY

Improvement Process (QIP). In addition, we maintain facilities
that have been qualified under such standards as MIL-M-38SI0
(Class B and Class S) for ICs in the U.S. and MIL-STD-1772
for hybrids. Many of our products-both proprietary and
second-source-have qualified for JAN part numbers; others are
in the process. A larger number of products-including many of
the newer ones just starting the JAN qualification process-are
specifically characterized on Standard Military Drawings (SMDs).
Most of our ICs are available in versions that comply with MILSTD-883C Class B, and many also comply with Class S. We
publish a Military Products Databook for designers who specify
ICs and hybrids for military contracts. The 1990 issue consists
of two volumes with data on 343 product families; the 120
entries in the second of those volumes describe qualified products manufactured by our PMI Division. A newsletter, Analog
Brieft,ngs®, provides current information about the status of reliability at AD!.
Our PLUS program makes available standard devices (commercial and industrial grades, plastic or ceramic packaging) for any
user with demanding application environments, at a small premium. Subjected to stringent screening, similar to MIL-STD883 test methods, these devices are suffixed "/ +" and are
available from stock.

PRICES
Accurate, up-to-date prices are an important consideration in
making a choice among the many available product families.
Since prices are subject to change, current price lists and/or
quotations are available upon request from our sales offices and
distributors.

The manufacture of reliable products is a key objective at
Analog Devices. The primary focus is the companywide Quality

Analog Brieflngs is a registered trademark of Analog Devices, Inc.
DSPatch is a trademark of Analog Devices, Inc.

GENERAL INFORMATION 1-5

1

How to Use This Book
THIS IS THE ANALOG DEVICES AUDIONIDEO REFERENCE MANUAL
It contains Data Sheets, Selection Guides and Application Notes on IC products for audio and video equipment design.

It is one member of a four-volume set of reference manuals on Linear, Converter and AudioNideo products from Analog Devices,
Inc., in IC, hybrid and assembled form for measurement, control and real-world signal processing.

IF YOU KNOW THE MODEL NUMBER
Turn to the product index at the back of the book and look up the model number. You will find the location of any product
catalogued in this volume or those listed below, with the Volume-Section-Page location of any data sheet in this volume.

IF YOU DON'T KNOW THE MODEL NUMBER
Find your functional group in the list on the opposite page. Turn directly to the appropriate Section. You will find a functional Selection Guide at the beginning of the Section. The Selection Guides will help you find the products that are the closest to satisfying your need. Use them to compare all products in the category by salient criteria. A comprehensive Table of
Contents (of this volume) is provided for your convenience on pages 1-7 through 1-10.

IF YOU CAN'T FIND IT HERE. _ . ASK!
If it's not an audio/video product, it's probably in one of the two companion reference manuals, the Linear Products
Databook or the Data Converter Reference Manual. If you don't already own these volumes, you can have them FREE by getting in touch with Analog Devices or the nearest sales office, or by phoning 1-800-262-5643 (U.S.A. only) or (617) 329-4700,
Ext. 3392.
See the Worldwide Sales Directory on pages 13-8 and 13-9 at the back of this volume for our sales office phone numbers.

Contents of Other Reference Manuals
DATA CONVERTER PRODUCTS
(VOLUME I)
D/A Converters
SID Converters
Communications Products
Digital Panel Meters
Digital Signal Processing Products
Bus Interface & Serial 110 Products
Application Specific ICs
Power Supplies

1-6 GENERAL INFORMA TlON

DATA CONVERTER PRODUCTS
(VOLUME II)
AID Converters
V/F & FN Converters
SamplelTrack-Hold Amplifiers
Switches & Multiplexers
Voltage References
Data Acquisition Subsystems
Analog I/O Ports
Application Specific ICs
Power Supplies

LINEAR PRODUCTS
Operational Amplifiers
Comparators
Instrumentation Amplifiers
Isolation Amplifiers
Analog MnitiplierslDividers
Log!Antilog Amplifiers
RMS-to-DC Converters
Mass Storage Components
ATE Components
Special Function Components
Temperature Transducers
Signal Conditioning Components
& Subsystems
Digital Panel Instruments
Bus Interface & Serial
110 Products
Automotive Components
Application Specific ICs
Power Supplies
Component Test Systems

Table of Contents
Page

Operational Amplifiers - Section 2 .............................................. 2-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
AD711- Precision, Low Cost, High Speed BiFET Op Amp • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
AD712
AD713
ADS11
ADS27

- Dual Precision, Low Cost, High Speed, BiFET Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- Quad Precision, Low Cost, High Speed BiFET Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- High Performance Video Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-High Speed, Low Power Dual Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-17
2-29
2-41
2-45

ADS29 - High Speed, Low Noise Video Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
ADS40 - Wideband, Fast Settling Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
ADS41 - Wideband, Unity-Gain Stable, Fast Settling Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73
ADS42 - Wideband, High Output Current, Fast Settling Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-S1
AD843 - 34 MHz CBFET Fast Settling Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89
AD844 - 60 MHz, 2000 V/!'-s Monolithic Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-101
AD845 - Precision, 16 MHz CBFET Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-113
AD846 - 450 V/!,-s, Precision, Current Feedback Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . 2-121
AD847 - High Speed, Low Power Monolithic Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-133
AD848/AD849 - High Speed, Low Power Monolithic Op Amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-145
AD5539 - Ultrahigh Frequency Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-153
OP-27 - Low Noise, Precision Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-169
OP-37 - Low Noise, Precision High Speed Operational Amplifier (AVCL~5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1S1
OP-61- Wide-Bandwidth Precision Operational Amplifier (Av ee:lO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-193
OP-64 - High Speed, Wide-Bandwidth Operational Amplifier (AVCL ee:5) . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . 2-211
OP-I60 - High Speed, Current Feedback Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-225
OP-249 - Dual, Precision JFET High Speed Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-249
OP-260 - Dual, High Speed, Current Feedback Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-267
OP-271 - High Speed, Dual Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-287
OP-275 - Dual Bipolar/JFET, Low Distortion Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-297
OP-471 - High Speed, Low Noise Quad Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-299
SSM-2131- Ultralow Distortion, High Speed Audio Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-315
SSM-2134 - Low Noise, Audio Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-327
SSM-2139 - Dual, Low Noise, High Speed, Audio Operational Amplifier (AVCL ee:3) . . . . . . . . . . . . . . . . . . . . . . . . 2-333

Audio AID Converters - Section 3 .............................................. 3-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
AD1876 - 16-Bit 100 kSPS Sampling ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
AD187S - High Performance Stereo 16·Bit Oversampled ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
AD1879 - High Performance Stereo IS-Bit Oversampled ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
AD1S85 - Low Cost Stereo 16-Bit Oversampled ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

Video AID Converters - Section 4 .............................................. 4-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
AD773 - 100Bit 18 MSPS Monolithic AID Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
AD9020 - 10-Bit 60 MSPS AID Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
AD9048 - Monolithic 8-Bit Video AID Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
AD9060 - 10-Bit 75 MSPS AID Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
GENERAL INFORMATION 1-7

•

Page

Audio D/A Converters - Section 5 .............................................. 5-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
ADlS511ADlS61 - 16-BitllS-Bit 16 x Fs PCM Audio DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
ADlS56 - 16-Bit PCM Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . 5-13
ADlS60 - IS-Bit PCM Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
ADlS62 - Ultralow Noise, 20-Bit Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
AD1864 - Complete Dual IS-Bit Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
ADlS65 - Complete Dual IS-Bit 16 x Fs Audio DAC . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . . . 5-55
ADlS66 - Single-Supply Dual 16-Bit Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65
AD186S - Single-Supply Dual IS-Bit Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67

Video D/A Converters - Section 6 .............................................. ~l
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

~2

ADV453 - CMOS 66 MHz Monolithic 256 x 24 Color Palette RAM-DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

~3

ADV476 - CMOS Monolithic 256 x 18 Color Palette RAM-DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6~9

x 24 (18) Color Palette RAM-DACs . . . . . . . . . . . . . . . . . . . . . . . . .

~19

ADV7120 - CMOS SO MHz Triple S-Bit Video DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

~31

ADV712117122 - CMOS 80 MHz Triple 10-Bit Video DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

~37

ADV47S/471 - CMOS SO MHz Monolithic 256

ADV714117l4617l48 - CMOS Continuous Edge Graphics RAM-DACs (CEGIDAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49

Special Function Audio Products - Section 7 ................................... 7-1
Selection Guides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '7-2

AD600/602 - Dual, Low Noise, Wideband Variable Gain Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
AD7111- LOGDAC CMOS Logarithmic D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
AD7118 - LOGDAC CMOS Logarithmic D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
MAT-04 - Matched Monolithic Quad Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
PKD-Ol - Monolithic Peak Detector with Reset-and-Hold Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
SSM-2013 - Voltage-Controlled Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51
SSM-2014 - Voltage-Controlled Amplifier/OVCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-57
SSM-2015 - Low Noise, Microphone Preamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-'59
SSM-2016 - Ultralow Noise, Differential Audio Preamplifier . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . 7-65
SSM-2017 - Self-Contained Audio Preamplifier

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . 7-73

SSM-2018 - Voltage-Controlled Amplifier/OVCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-S1
SSM-2024 - Quad Current-Controlled Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-93
SSM-21l0 - True RMS-to-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-99

SSM-2120/2122 - Dynamic Range Processors/Dual VCAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-111
SSM-2125/2126 - Dolby Pro-Logic Surround Matrix Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-123
SSM-2141- High Common-Mode Rejection Differential Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-133
SSM-2142 - Balanced Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-139
SSM-2143 - -6 dB Differential Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-145
SSM-2210 - Audio Dual Matched NPN Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-147
SSM-2220 - Audio Dual Matched PNP Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-159

SSM-2402/2412 - Dual Audio Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . 7-167
SSM-2404 - Quad Audio Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-177
1-8 GENERAL INFORMATION

Page

Special Function Video Products - Section 8 ................................... 8-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
AD539 - Wideband Dual-Channel Linear Multiplier/Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
AD633 - Low Cost Analog Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
ADno - RGB to NTSCIPAL Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
AD734 - 10 MHz, 4-Quadrant Multiplier/Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
AD834 - 500 MHz Four-Quadrant Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33
AD9300 - 4x I Wideband Video Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41
DAC-8408 DAC-8800 DAC-8840 DAC-8841 -

Quad 8-Bit Multiplying CMOS D/A Converter with Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Octal 8-Bit CMOS D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-Bit Octal4-Quadrant Multiplying CMOS TrimDAC" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-Bit Octal 2-Quadrant Multiplying CMOS TrimDAC" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-49
8-63
8-77
8-87

Digital Signal Processing Products - Section 9 .................................. 9-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
ADDS-2100A-ICE - In-Circuit Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
ADDS-2101-EZ - EZ-Tools Hardware Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
ADDS-2101-ICE - In-Circuit Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
ADDS-2IXX-SW - ADSP-2100 Family Development Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
ADDS-21OXX - SW-ADSP-21000 Family Development Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
ADSP-2100/2100A - 12.5 MIPS DSP Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
ADSP-2101 - DSP Microcomputer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
ADSP-2105 - DSP Microcomputer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23
ADSP-2111 - DSP Microcomputer with Host Interface Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29
ADSP-21020 - IEEE Floating-Point DSP Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33

Other Products - Section 10 .................................................... 10-1
Analog-to-Digital Converters Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
Digital-to-Analog Converters Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
Operational Amplifiers Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16

Application Notes - Section 11 ................................................. 11-1
AN-IS - Minimization of Noise in Operational Amplifier Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
AN-102 - Very Low Noise Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
AN-lOS - Applications of the MAT-04, A Monolithic Matched Quad Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
AN-ll1 - A Balanced Summing Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27
AN-112 - A Balanced Input High Level Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
AN-I 13 - An Unbalanced, Virtual Ground Summing Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31
AN-114 - A High Performance Transformer - Coupled Microphone Preamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33
AN-115 - Balanced, Low Noise Microphone Preamplifier Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35
AN-116 - AGe Amplifier Design with Adjustable Attack and Release Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37
AN-121 - High Performance Stereo Routing Switcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39
AN-122 - A Balanced Mute Circuit for Audio Mixing Consoles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43
AN-123 - A Constant Power "Pan" Control Circuit for Microphone Audio Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45
GENERAL INFORMA TlON 1-9

II

Page
AN-124 - Three High Accuracy RIAAlIEC MC and MM Phono Preamplifiers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-47

AN-l2S - A Two-Channel Dynamic Filter Noise Reduction System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-53
AN-127 - An Unbalanced Mute Circuit for Audio Mixing Channels

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-55

AN-l28 - A Two-Channel Noise Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-57
AN-129 - A Precision Sum and Difference (Audio Matrix) Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-59
AN-130 - A Two-Band Audio Compressor/Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-61
AN-131 - A Two-Channel VCA Level (Volume) Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-63
AN-133 - A High-Performance Compandor for Wireless Audio Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-65
AN-134 - An Automatic Microphone Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-69
AN-135 - The Morgan Compressor/Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-73
AN-136 - An Ultra!ow Noise Preamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-81
AN-142 - Voltage Adjustment Applications of the DAC-8800 TrimDAC", an Octal, 8-Bit D/A Converter

. . . . . . . . . . 11-83

AN-201 - How to Test Basic Operational Amplifier Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-97
AN-202 - An I.C. Amplifier Users' Guide to Decoupling, Grounding, and Making Things Go Right for a Change . . . . . 11-101
AN-20S - Video Formats & Required Load Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-109
AN-206 - Analog Panning Circuit Provides Almost Constant Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-113
AN-207 - Interfacing Two 16-Bit ADl8S6 (ADl8S1) Audio DACs with the Philips SAA7220 Digital Filter . . . . . . . . . 11-117
AN-208 - Understanding LOGDACs" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-121
AN-209 - 8th Order Programmable Low Pass Analog Filter Using Dual 12-Bit DACs . . . . . . . . . . . . . . . . . . . . . . . 11-125
AN-211 - The Alexander Current Feedback Audio Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-133
AN-212 - Using the AD834 in DC to 500 MHz Applications RMS-to-DC Conversion,
Voltage-Controlled Amplifiers and Video Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-149
AN-213 - Low-Cost, Two-Chip Voltage-Controlled Amplifier and Video Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-159
AN-214 - Ground Rules for High-Speed Circuit Layout and Wiring Are Critical in Video-Converter Circuits,
How to Keep Interference to a Minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-165
AN-21SA - Designer's Guide to Flash-ADC Testing - Part 1, Flash ADCs Provide the Basis for
High Speed Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-169
AN-2lSB - Designers' Guide to Flash-ADC Testing - Part 2, DSP Test Techniques Keep Flash ADCs in Check . . . . . 11-177
AN-21SC - Designers' Guide to Flash-ADC Testing - Part 3, Measure Flash-ADC Performance
for Trouble-Free Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-183
AN-216 - Video VCAs and Keyers Using the AD834 and AD811 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-193
AN-217 - Audio Applications of the ADSP Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-201
AN-218 - DSP Multirate Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-205
AN-219 - Electronic Adjustment Made Easy with the TrimDAC"

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-215

Package Information - Section 12 .............................................. 12-1
Appendix- Section 13 ......................................................... 13-1
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Technical· Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Worldwide Sales Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . 13-8

Index - Section 14 ............................................................. 14-1
Application Notes by Topic ., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
Application Notes by Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
Alphanumeric Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4

1-10 GENERAL INFORMATION

Selection Guide
Operational Amplifiers
Video Amplifiers
Model

SR
~P
VI".s deg
typ
typ

%
typ

Settling
Time
nsto%
typ

AD811

2500

0.01

65--0.01

120

AD844
OPI60
OP260
AD5539
AD846
AD840
AD842
AD841
AD847
AD827
AD829
AD848
AD849
AD843
OP64
AD845

2000 0.D25 0.008
1300 0.04 0.04
1000 0.067 0.02
600
0.1
0.04
450
0.03 0.Dl
400
0.04 0.025
375
0.035 0.015
300
0.02 0.03
300
0.04
0.2
300
0.2
0.04
300
0.04 0.02
300
0.08 0.07
300
0.04 0.08
250 1).025 0.025
170
0.018 0.045
100
0.025 0.04

100--0.1
75--0.1
250--0.1
12-1
110--0.01
100--0.01
100--0.01
1l0--0.Dl
120--0.1
120--0.1
90--0.1
100--0.1
80--0.1
135--0.01
100--0.1
350--0.01

60
90
90
220
80
40
40
40
50
50
50
35
30
34
16
16

0.01

~G

BWat

Input
Bias
Current
".A max

Voltage
Noise
lOUT Supply
nVIVHz
rnA
Range
@ 10 kHz min
±Volts

Supply
Current Spice
Model
rnA
typ
Avail. Page

3

10

2

100

4.5 to 18

16.5

-I
I
I
2
-I
10
2

0.15
5
3.5
3
0.075
0.3

I
1
5
2S
1
5

2
0.5

0.25
20
8
13
0.25
5
5
5
5
7
7
5
5
0.001

2
5.5
5.5
6
2
4
9
13
15
15
2
5
3
19
8
18

20
35
35
15
20
50
100
50
20
20
20
20
20
50
50
25

4.5 to 18
4 to 15
4 to 15
4.5 to 10
5 to 18
5 to 18
5 to 18
5 to 18
4.5 to 18
4.5 to 18
4.5 to 18
4.5 to 18
4.5 to 18
4.5 to 18
5 to 18
4.75 to 18

6.5
6.5
9
14
5
10.5
13
II
5.3
10
5
5.1
5.1
12
6.2
10

Ac, Min Ac,
MHz
typ

Vos
VN mV
min max

0.75
1
1
0.25

0.001

X

X
X
X
X

X
X
X
X

X

2-41
2-101
2-225
2-267
2-153
2-121
2-65
2-81
2-73
2-133
2-45
2-53
2-145
2-145
2-89
2-211
2-113

Comments
Best Video Specifications Flatness = 0.1 dB
to 35 MHz
Constant 10 ns Rise Time for Any Pulse
Disable Mode for Low Power Applications
Dual OP160; Only Dual Transimpedance
Improved Replacement for Industry Standard
Highest DC Precision High Speed Amplifier
Fast Settling Time; Gain > 10
High Current Output; Gain > 2
Fast Settling Time and Unity Gain Stable
General Purpose, Low Power, Unity Gain
Dual AD847
Low Noise and High Speed
General Purpose, Low Power, Gain > 5
General Purpose, Low Power Preamplifier
High Performance, Replaces LH0032
Stable for Gains> 5
General Purpose. Unity Gain Stable

~
~
~
.....
~

(S
lJ

~

:::!

,.~

•

I'

;;;

Selection Guide

~~ Operational Amplifiers
.....
~

Audio Amplifiers

:0

Single Op Amps

cg
~

SR
V/p.s

GBW
MHz

Model

Voltage Noise
@lkHz
nV/Viii typ

typ

typ

AD829
AD846
AD844
OP27
OP37
OP61
SSM2134
OPI60
OP64
SSM2131
AD7ll
AD843
AD845

2
2
2
3
3
3.4
3.5
5.5
8
13
18
19
25

300
450
2000
2.8
17
40
13
1300
170
50
20
250
100

750
80
60
8
63
200
10
90
80
10
4

:::!
0
 Serial Data In

Digital Signal Processing Products
DSP Processor Key Feature Summary
Model

Instruction
Cycle
Time
ns

ADSP2100A
ADSP-2101
ADSP-210S
ADSP-2111

80
60
100
60

Internal
Off·Chip Program
Harvard Memory
Arch
RAM

Internal
Data
Memory
RAM

Internal
Program
Cache
Word

Program
Memory
Boot

Serial
Ports

16 x 24
2K x 24
lK x 24
2K x 24

lK x 16
O.SK x 16
lK x 16

2
1
2

Programmable
Timer

Low
Power
Modes

Pin
Count

Page

4
3
3
3

100
68
68
100

9-13
9-17
9-23
9-29

4

223

9-33

Ext
Interrupts

32140-Bit Floating Point
ADSP-21020

40

32 x48

~
~
~
r~

~
~

~

:::l

~
I

iO

•

Product Assurance
PRODUCT ASSURANCE OVERVIEW
Introduction
Analog Devices has long been a leader in its innovations of analog integrated circuit design, processing, and testing. Of equal
importance to innovation is its commitment to continuous
improvement of quality, reliability and excellence in service.
Achieving, and continuously striving to improve the quality and
reliability have led to Analog's success as a world-recognized,
leading supplier of analog integrated circuits.
Product Assurance Philosophy
Product Assurance's role within Analog Devices is many faceted. All of the traditional roles of Product Assurance are maintained, including Military Programs management, QAlReliability
conformance inspections, specification control, auditing, failure
analysis, corrective action, calibration systems, as well as many
other functions. In addition, Analog's Product Assurance
departments maintain an active role in servicing internal operational entities' requirements as well as our customers' needs.
This is accomplished through various programs aimed at
improving product quality, reliability and service.
Continuous Improvement and Statistical Process Control
Programs
Fundamental to our beliefs about manufacturing success is that
quality and reliability are not inspected into the process as was
the historical methodology, but instead built into the process
from the outset. In order to be successful at consistently providing excellence in all areas, it is essential that the processes be
measured, understood, and have controlled variance. Keeping
this in mind, ADI has been aggressively pursuing statistical process control.
ADI is engaged in continuous improvement as an integral portion of our cultural development. The overall intent of this process has been to create an environment in which each employee
is trained and is empowered to change and to improve the process. Essential to this environment are the absence of fear and
an active encouragement to take risks to improve.
All manufacturing and related service personnel are trained in
the concepts of problem solving and statistical process control
(SPC) techniques. SPC training is also an orientation requirement for all new employees.
Quality improvement teams are continually being formed, as
opportunities to improve and to implement change are identified. These groups have addressed many issues and have had a
dramatic effect on ADI's manufacturing and administrative processes. These teams have typically crossed departmental and
functional lines, as the effects of change or the type of problem
could not be solved without cooperation and resultant expanded
knowledge bases.

1-:20 GENERAL INFORMA TlON

PRODUCT RELIABILITY
Reliability Assurance Programs
Reliability assurance programs at Analog Devices are designed
to encompass all aspects necessary to achieve and to improve
product performance and lifetimes. We recognize that reliability
cannot be tested or screened in if the aggressive goals set by
both our customers as well as ourselves are to be met.
The major areas of focus within Analog Devices include:
Design For Manufacturability (Design for Success). Product
and process designs focus on achieving product performance and
"building-in reliability." Causes for degraded reliability performance must be well understood and controlled. Reliability
design rules, updated frequently as experience grows and the
industry matures, are essential to improving product performance.
Process Capability. A new or an established process must not
only be capable of meeting specification limits but must also
exhibit a sufficient safety margin to ensure continued performance over the product life.
Manufacturing Process Control. Of utmost importance is the
control of the manufacturing environment under which product
is fabricated, assembled, tested or stored. Temperature, humidity, particulate, ionic contamination and equipment interactions·
must be well understood and controlled.
Process Monitoring. 100% inspections or sampling points of
key parameters with appropriate controls on output are utilized
throughout the manufacturing process. These include the following as listed in order of timeliness of information feedback:
In-line or in-situ measurements utilizing SPC.
Process step specific.
Wafer ship measurements.
Wafer level testing; i.e., sort, wafer level stress testing.
Die visual quality.
Final electrical testing after assembly.
Reliability stress testing of customer-ready finished goods.
CUstomer feedback.
Program Goal
Our goal is to provide our customers with the highest level of
reliability performance obtainable. It is a Program which is, by
its nature at Analog Devices, an integral part of all new products and process introductions, as well as all changes made
within the products, processes or facilities for which it measures.
Reliability Qualification Program
Analog Devices maintains a reliability qualification program that
includes extensive use of accelerated stress testing. The program's intent is not only to meet the requirements of the military programs but also to provide products in plastic which, at
minimum, meet or exceed world-class standards of excellence.
All new processes and facilities are qualified. Any changes to
existing qualified processes are also qualified as appropriate (see
Process Change Notification section).

Reliability Monitor/Audit Program
Periodic monitoring of all fabrication and assembly locations is
performed. The monitoring program uses highly accelerated
stress testing in order to monitor our various processes. The
program is geared to fabrication process and packaging families.
Process Change Notification System
Analog Devices has a standard procedure and criteria for classifying and controlling changes to our processes, packages, materials, facilities and manufacturing techniques. This system
includes technical reviews of proposed changes, qualification
plans including all considerations of MIL-M-385 10, customer
specification, as well as AD!'s internal qualification requirements. Included in this program is a system to notify customers
of the proposed changes in a timely fashion.
Reliability Defmitions and Theory
Reliability The probability that a device or system will perform
a required function satisfactorily or without failure (within specification limits) under stated conditions for a stated period of
time. Reliability is described as a mathematical expression of
probability.
Hazard Rate The instantaneous rate of failure for units of the
population that have survived to a given time.

Table I. Early Life Failure Mechanisms (Infant Mortality)
Failure Mechanism Defect
Thin or defective
oxide (masking
and oxidation)

System electrical
noise/transients.
System power
interruptions.
Inductive loading.

Open wire bonds

Assembly defects

Ultrasonic exposure during
printed circuit
board assembly.
Excessive burn-in
temperatures.

Lifted die bonds

Assembly defects

Excessive burn-in
temperatures.

Fused die
metallization

EARLY LIFE

FAILURE
RATE

A(I)

WEAR-OUT

"CONSTANT" fAILURE RATE LIFE

System electrical
noise/transients.
System power
interruptions.
Inductive loading.

Shofts

Inadequate spacing
between adjacent
traces.

Opens

Inadequate trace
width (masking
and evaporation)

Failure Usually involves the degradation in performance to
specified parameters which are typically electrically measurable.
Semiconductor failure patterns follow that of long-life devices
and are typically described by the so-called "Bathtub Curve,"
named for its shape, as shown in Figure 1. There are three distinct regions on this curve: Early Life, Constant Failure Rate
Life, and Wear-Out.

Stress Factors

Oxide ruptures

Corrosion of wire
bonds andlor die
metallization

Seal leaks
(defective
encapsulation);
poor lead frame/plastic
adhesion at
interface

Handling damage.
Excessive solder
heat during printed
circuit board
assembly. Ionic
contamination.

L-=:l::==:...:::.==:::j:::"'_
TIME-t

Figure 1. Semiconductor Failure Rate "Bathtub Curve"
Early Life Sometimes called infant mortality, early or initial
failure time. This region may exhibit a high initial failure rate
compared to the remaining population, typically because of
defects from the manufacturing or assembly process. To a user
the failures can also exhibit themselves due to debugging or misuse. Refer to Table I. Early failure rate reduction programs are
in place throughout Analog Devices.

Constant Failure Rate Region Also called the intrinsic or accidental failure time and is considered the useful life region of the
product. This region is a mixture of any of the remaining manufacturing defects which require longer times to fail as well as the
failures from the main distribution of the product.
Wear-out Region Alternately referred to as the degradation
period. The failure rate continuously increases with time. Under
typical use conditions, silicon semiconductor devices will never
approach this region relative to system life expectancies (see
Table II).

GENERAL INFORMATION 1-21

II

Table II. Wearout Failure Mechanisms
Failure Mechanism Defect Observed

Contributing Factors

Electromigration

Voids, oPen
circuits, 'hillock
or metal
accumulation.

Grain boundary
diffusion. Grain
size and distribution.
Fiber texture.

Slow Trapping
charge injection

Electrical
degradation

Structural defects
related to the
oxidation process.
Metallic impurities.
Bond breaking
processes.

Charge
Accumulation
mobile ions

Electrical
degradation

Alkali ions-sodium,
potassium and
lithium in the oxide.
Other negative ions!
heavy metals.

Intermetallic
Growth in
AI-Au wire
bonds

Highly resistive
bonds. Open
circuit at bond.
Bond lift failures.

Kirkendahi Voiding.
Diffusion of Al into
Au.

Wire and Wire
Bond Failures
during thermal
cycling

Open/intermittent A fatigue mechanism.
circuits.
Thermal mismatch.
Short circuits.
Stress induced wire
creep. Intermetallics.
Wire Length not
optimized
Too taut-breakage
Too long -sag.

Life Distributions
Time-to-failure data is analyzed in order to predict the future
reliability of the product. Four .life distributions are typically
used in the analysis of silicon semiconductor reliability.
1. Normal Distribution Function-Describe the wear-out region
where there exists a monotonically increasing failure rate with
respect to time.

2. Lognormal Distribution Function- The. natural logarithm of
the failure time is distributed normally. Extensive use of this
,distribution occurs, as it can be used to fit many different
kinds of data.
3. Weibull Distribution Function-In this case the hazard rate
varies as a power of device age. The failure-rate curve does
not start at zero as is the case of the lognormal distribution.
4. Exponential Distribution Function - This distribution is used
when the failure rate is constant. Failures occur randomly
and are characteristic of the constant failure rate region of the
"Bathtub Curve."

1-22 GENERAL INFORMA TlON

Accelerated Life Stress Testing
It is possible to evaluate the early life reliability levels from
short-term burn-ins, customer system burn-ins, and early failure
rates in the field. It is not practical, however, to evaluate the
useful life' or wear-out failure rates from these same sources.
The amount of time necessary to obtain statistically significant
data far exceeds the useful life of most systems. Obtaining data
about the life of a semiconductor beyond the infant stage
requires a higher than normal stress level to be applied to the
device. In practice, a sample of devices of sufficient quantity to
statistically represent the population is subjected to stress levels
from various types of environmental stimuli to evaluate these
failure levels and mechanisms. This type of testing is known as
accelerated stress testing.
The time and temperature dependences of most semiconductor
failure mechanisms over the life of a product have been studied
and quantified. The established relationship between time,
temperature, and particular failUre mechanisms has been
demonstrated to be a log-nortnai function capable of being represented by the "Arrhenius" mOdel that includes the effects of
temperature and activation energy of the failure mechanisms.
It is possible, by using the model, to characterize failure modes
from accelerated stress testing, and then to predict reliability
levels at normal, nonaccelerated conditions. .As applied to accelerated life testing of semiconductors, the
Arrhenius model assumes that the degradation of a performance
parameter is linear with respect to time, with the mean time
between failures (MTBF) as a function of the temperature
stress. The temperature dependence is taken to be the exponential function that defmes the probability of occurrence, resulting
in the following formula for defming the lifetime or MTBF at a
given temperature stress level:
tl = t z exp[E.lk(11T1

-

IlT z)]

where:
MTBF at junction temperature TI
MFBF at junction temperature T z
junction temperature in OK
thermal activation energy in electron volts (eV)
Boltzman'sconstant (8.617 x 10- 5 eVfK
The activation energy in this formula is the mean E. for aU of
the failure mechanisms of the particular product line for which
the calculation is being done. These activation energies are
established by the examination of failures from stress testing.
See Table III.

Table III. Time-Dependent Failure Mechanisms in Silicon Semiconductor Devices'
Device
Association

Failure
Mechanism

Relevant
Factors

Acceleration
Factors

Acceleration
(Ea eV = Apparent Activation Energy)

Silicon Oxide
and
Silicon-Silicon
Oxide Interface

Surface Charge
Accumulation

Mobile ions
V,T

T

Ea = 1.0 - 1.5 eV
depends on ion density

Metallization

Bonds and Other
Mechanical Interfaces

Hermeticity

Dielectric Breakdown

EF,T

EF,T

Ea = 0.2 - 1.0 eV, EF, (T) = I - 4.4

Charge Injection

EF, T, Qf

EF,T

Ea = 1.3 eV (slow trapping)
Ea = -I eV (hot electron ejection)

Electromigration

T, J, A, Gradients of
T and J, Grain Size

T, J

Ea = 0.5 - 1.2 eV
J, (T) = 1-4

Corrosion
(chemical, galvanic,
electrolytic)

Contamination
H,V,T

H,V,T

Strong H effect
Ea = 0.3 - 1.1 eV (for electrolysis)
V may have thresholds

Contact Degradation

T, Metals, Impurities

Varied

Intermetallic Growth

T, Impurities,
Bond Strength

T

Fatigue

Bond Strength,
Temperature Cycling

Temperature
extremes in
cycling

Seal Leaks

Pressure Differential,
Atmosphere

Pressure

Al - Au: Ea = 1.0 - 1.05 eV

NOTE
V~voltage, T~temperature;

EF-electric field; J-current density; A-area; H-humidity; Qf-charge
ID. S. Peck, "Practical Applications of Accelerated Testing-Introduction," Reliability Physics, 13th Annual Proceedings, 1975, pp. 253-254.

Reliability Testing

Methods

Standards Conformance. Test methods to confirm the reliability of Analog Devices product are detailed below, and are determined prinIarily through conformance to the various industry
standards. These include MIL-STD, JEDEC, IEC, JIS, and
EIAJ.

High Temperature Operating Life Test (HTOL). The operating life test demonstrates the quality or reliability of devices
subjected to the specified conditions over an extended twe
period. HTOL stressing applies a static DC bias at an elevated
ambient temperature. This bias is maintained throughout the
duration of the test as well as during cool-down from elevated
temperature after stress. HTOL testing is particularly useful
because it provides a means of accelerated time-to-failure of temperature sensitive failure mechanisms.

I. MIL-STD - U.S. Military Standards:
MIL-STD-750 Test Methods for Semiconductor Devices
MIL-STD-202 Test Methods for Electronics and Electrical
Component
MIL-STD-883 Test Methods and Procedures for Microelectronics
2. JEDEC
3. JIS - Japanese Industrial Standards:
JIS-C-7022 Environmental Testing Methods and Endurance
Testing Methods for Semiconductor Integrated Circuits.
4. IEC Standard:
Publication 68 Basic Environmental Testing Procedures.
5. EIAJ Standard:
IC-121 Test Methods for Reliability of Integrated Circuits.

High Temperature Storage Life Test (HTSL). High temperature storage life testing is performed in order to demonstrate the
quality or reliability of devices subjected to elevated temperature
storage conditions without electrical bias.
Thermal Shock (TMSK). Thermal shock testing demonstrates
the qualiry or reliability of devices exposed to extreme changes
in temperature, especially to alternating extremes. The change
in temperature is quite rapid as the heat transfer is by conduction and the transfer time from one temperature extreme to
another in minimal «10 sec.). Thermal shock testing induces
mechanical stresses caused by thermal expansion and contraction. These stresses can be extreme, especially in plastic molded
devices where large differences in the thermal coefficients of
expansion between the die, leadframe and plastic material can
exist. This is especially critical for large dies where the stress
can be too severe and will induce failures that would not be

GENERAL INFORMA TION 1-23

•

expected in a real application. As a result of the permanent
changes in electrical and mechanical characteristics and/or physical damage that may result from thermal shock, any tests in
which the duration is greater than ten cycles shall be considered
destructive.
'
Temperature Cycle (TMCL). Temperature cycle testing is
performed to demonstrate the quality or reliability of devices
exposed to the extremes of high and low temperatures, and
especially to alternating extremes. TMCL testing more closely
relates to actual use conditions as the temperature change of the
device is due to convection and, therefore, is at a slower rate
than thermal shock. This slower rate of change will more closely
simulate such use conditions as the transfer to or from heated
storage in cold climates, or where ambient temperature is
relatively mild but heats up greatly as the system is operating.
This is a very good test to measure the overall die-to-package
compatibility.
Temperature and Humidity Life (THB). Temperature and
humidity life testing demonstrates the quality or reliability of
devices exposed to the combination of high temperature and
high humidity, with an applied voltage bias. Maximum bias
voltage levels are desired as this bias accelerates any electrolysis
of the device metalization as well as increasing ion mobility. At
the same time, device power dissipation is desired to be minimized as any localized heating at die level will tend to lower the
humidity level at the die surface and lessen the electrolysis
potential. In certain cases, power cycling must be used in order
to permit moisture accumulation on die surface during the
"power-off" periods.
AutoclavelPressure Pot (PTH). Autoclave testing evaluates the
quality and reliability of devices exposed to a saturated humidity
and high temperature environment under pressure. This test is
performed without bias, and therefore, once equilibrium is
reached, the die temperature and relative humidity will be the
same as the external environment. PTH conditions, although
not typical of actual operating environments, are very effective
at evaluating the moisture resistance of a device/package combination in a relatively short period of time.
Biased Pressure Pot (HAST). Biased pressure pot testing evaluates the quality and reliability of devices urider bias subjected
to a humid, high temperature environment under pressure. This
test can be considered an acceleration of the THB test due to
the elevated temperature and steam environment which is under
pressure. Biasing guidelines are the same as for THB testing,
with an additional consideration: because of the elevated temperature, certain high power devices will dissipate sufficient power
to elevate the die temperature above the glassivation temperature
of the plastic molding compound. This,could occur even though
power cycling techuiques are employed. This condition is not
desired as abnormal conditions not related to real operating conditions could e,ast, resulting in anomalous failure mechanisms.
Resistance to Solder Heat (RTSH). Resistance to solder heat
evaluates the ability of a product/package to withstand the
worst-case heat cycles that could be encountered during normal
printed circuit board assembly.

1-24 GENERAL INFORMATION

QUALITY ASSURANCE
Vendor Assurance Programs
Analog maintains an active program with its vendors to ensure
that the highest standards of quality are met. The program
focuses on many key areas including vendor qualification and
certifications, periodic vendor audits, rigorous incoming inspection of fit, form, and function, as well as tracking the vendor
performance over time.
Analog Devices has established minimum standards of performance for our vendors, who are audited for compliance to minimum standards. We then rate each vendor on the quality and
delivery of incoming material. It.is through this program that
we can assess and then purchase material based upon cost-ofownership. This contrasts to buying strictly on purchase price,
as the purchase price alone does not completely reflect the total
cost. Another benefit of our vendor quality program is that we
have the necessary information to work in partnership with our
vendors to continuously evaluate and improve the quality of
incoming product.
Incoming Quality Assurance (IQA)
Analog Devices' IQA orgauization performs deta.iled inspections
of vendor quality performance. Conformance to specification is
directly measured to ensure compliance with the specified
requirements. When a fa.ilure to meet the requirements is discovered, a corrective action from the vendor is required. Extensive follow-up is done to ensure future and continued
compliance.
Vendor Audits
Analog Devices performs periodic audits of all of its
manufacturing-related vendors. ADI performs these audits to
assess compliance to MIL-Q-9858 and MIL-I-45208. Corrective
action requests are issued with deadlines for compliance appropriate to the noncompliance. These audits are ,also used to discuss both open and closed quality, reliability, and service issues.
Through this extensive interaction, ADI has been able to continuously improve the quality and reliability of incoming materials.
QUALITY CONTROL SYSTEMS
Corrective Action
An active, internal, closed loop-corrective action system has
been utilized for many years both to commumcate deficiencies
as well as to provide traceability of corrective actions. This system has been a key element of process audits and customer
return issues. The program has been very effective in correcting
deficiencies in a timely manner.
Traceability and Recerd Retention
Traceability after shipment is maintained through actual marking of devices with lot identifiers. This information will provide
traceability through assembly and wafer fabrication for all
devices. This traceability allows for very good control of products as well as for direct correlation of products to time of process, machines, processes, and other pertinent related items.

Control of Nonconforming Material
Whenever nonconforming material is found, it is put under control for disposition. This holding of material is done at all stages
in the process from incoming inspection through all inventory
locations. Response to hold requests, whenever necessary, is
quick and complete.
Process Audits - Fab, Assembly, and Test
In addition to auditing our venders, ADI has an ongoing internal process auditing group. This group audits all of Analog's
manufacturing areas to ensure compliance to specification. In
addition, selected service areas are audited where appropriate.
Dedicated process auditors perform verifications in wafer fabrication, assembly and test. All types of critiques are used to
review compliance, and the results are reviewed with appropriate supervisors and managers. The criticality of all deficient
items is assessed and appropriate action is taken. Periodic
reports are also issued to all levels of management.
Quality Conformance Inspections (QCI)
In-process QCI is employed throughout the manufacturing process to verify compliance to specification. All QCI is performed
to specification and results are tracked and reported as appropriate. The QCI inspections include both very traditional and innovative methods to measure and to control product conformance.
These inspections provide very valuable information about the
processes they measure. Analog Devices uses these inspections
and the results obtained to enhance, where appropriate, our statistical process control program.
Average Outgoing Quality (AOQL)
At the end of manufacturing processing, just prior to moving
product into finished goods inventory, product is sampled for
electrical, visual/mechanical and hermeticity to determine compliance to the requirements. The sampling and results include
all products released to production and, therefore, include all
new products and packages. These performance levels are
tracked in very precise detail. Results of this inspection determine ADI's reported AOQ.
Added to this very extensive sampling program are quality
improvement teams to address the findings. These teams meet
on an ongoing basis to review the results, to determine root
causes and to correct the processes as appropriate.
CUSTOMER SERVICE
Regional Customer Service Centers
Responsiveness to customer problems is a key factor in maintaining a leadership position in today's semiconductor marketplace. In order to improve support to Analog Devices' customers,
five Regional Customer Service Centers have been established
worldwide. These locations are strategically located within direct
reach of our customers without having time zone logistics issues.
Two centers are established in Asia (Japan/Taiwan), two are in
the USA (Boston, MAiSanta Clara, CAl, and one is in Europe
(Ireland). These centers will provide Engineering Support to
customers in the areas of failure analysis, problem resolution
and reliability information.

The goals established for the Regional Customer Service Centers
include the following:
• Assume regional failure analysis responsibility for all ADI
monolithic products.
• Provide rapid response to customer perceived problems
through correlation, failure analysis results and failure analysis.
• Minimize the impact of a field performance problem by
immediate, on-site interaction with the customer.
• Provide to ADI a "voice of the customer" for field performance information.
• Improve customer satisfaction and become a competitive tool
for ADI.
• Maintain the technical expertise required to meet customer
and factory needs.
• Provide a single point of contact for all quality and failure
analysis issues.
Customer Returns
The customer returns processing area, as well as evaluations of
returned material, is administered by the Quality Assurance
Engineering organization. QA Engineering receives the returned
material, and also controls it until disposition. All customer
returns are reviewed, verified, and/or failure analyzed as appropriate. Formal reports of fmdings are issued and appropriate
actions are taken.
Periodic reports are issued to all levels of management and engineering. The reports provide details of any returned material as
well as trend information to highlight appropriate areas for
action.
The extensive evaluations of customer returns have, over time,
been one of the more valuable feedbacks from the customer to
ADI's internal systems. By directly working with both ADI's
engineering and the customer, Analog has been able to supply
its customers with the highest level of qUality. Consistent processing and delivery of quality product that meets the customer's expectations are direct results of close working relationships.
Failure Analysis
Analog maintains a full service analytical laboratory staffed with
professional engineers and technicians who analyze failures. The
purpose of the laboratory is to provide, through detailed analysis, timely and effective feedback to customers on the quality
and reliability of Analog's product. The analysis will involve the
identification of the failure modes and mechanisms and probable
failure causes. A complete written report is then supplied to the
customer describing in detail the exact steps taken during the
analysis and any conclusions drawn from the analysis. Where
necessary, corrective actions are initiated based on the results
and conclusions of the analysis. Thus, the results of analysis
performed are fed back into the manufacturing process to continually improve the quality and reliability of Analog's product.
A flow of how Analog handles customer failure analysis is shown
in Figure 2. Figure 3 shows a failure analysis approach diagram
and Figure 4 shows a generalized failure analysis flow diagram.

GENERAL INFORMA TlON 1-25

II

A flow of how Analog handles customer failure analysis is shown
in Figure 2. Figure 3 shows a failure analysis approach diagram
and Figure 4 shows a generalized failure analysis flow diagram.

Reports Incidence of Failure to
Sales Personnel.
Completes Failure Analysis Input
Request (FAIR) Fonn

.i1d Transfers

(CONSULTAnON)

Devices from Customer to Failure
Analysis O1rectty or Via Customer

service.

ENVIRONMENTAL

Transfers FAIR Form and devices to
Failure Analysis. Lisees With Failure

TEST
• TIC
• TIS
MONITORED
VIBRAnON ETC

Analysis and Sales/Customer.

Complete Failure Analysis on
Devices. Provide Customer WHh a
Written Report Detailing Analysis
Results. Initiate Corrective Actions
Resulting From Analysis.

Figure 2. Failure Handling Procedure

--,

r-,..._-1-_-,
I SEM/EMA I

I ANALVStS
L..
____ ....II

rA~Rl

I SURFACE I
IL..ANALYSIS
____ ..JI

Figure 3. Failure Analysis Approach Flow Diagram

Figure 4. Generalized Failure Analysis Flow

1-26 GENERAL INFORMA TION

Table IV. Failure Modes
Failure Mode

Definition

Effect on Device or Ie

I. Internal Short

Short Circuit between Metallized Leads or Across
Junction.

Short Circuit or Circuit Malfunction.

2. Internal Open

Open Circuit in the Metallization or Wire Bond

Open Circuit

3. Parametric Variation

Variation in Gain or Other Electrical Parameter

Marginal Performance, Temperature Sensitivity,
or No Effect

4. Junction Leakage

Leakage Current Across P-N Junctions.

Effects Range from None to Malfunctions.

5. Threshold Shift

Sruft in Turn-on Voltage.

Random Logic Malfunction

6. Seal Integrity

Ingress of Ambient Air, Moisture andlor Contaminants.

Effects Range from Degradation to Complete
Malfunction.

Following are defmitions used in ADI failure analysis:

Failure mode - the characteristic of a device for which the
device has been characterized a failure, i.e., deviation from a
specification or desired performance. A summary of failure
modes is given in Table IV.
Failure mechanism - a physical process which leads to failure.
The "physics of failure."
Ionic contamination - ionic species in the passivation layers can
cause permanent or temporary threshold voltage srufts of the
silicon surface below. This may cause leakage (channeling)
between device elements resulting in nonfunctionality.
Electromigration - at high current densities atoms of the conductor material are swept along due to the momentum of the
electron "wind." Trus creates a depletion of conductor material
upwind and an accumulation downwind. Electromigration can
cause open circuits or short circuits between closely spaced conductor lines.

Electrostatic discharge (ESD) and electrical overstress (EOS) these are probably two of the most frequently identified failure
mechanisms. ESD, created by the exchange of charge between
two dissimilar materials, can cause pin junction damage as well
as rupture of dielectrics. Although it generally has a short pulse
width, the voltage and current transients generated can be
extremely large. EOS is characterized by excessive voltages or
currents that tend to be sustained for a much longer period than
ESD pulses. It will cause conductor or wire bond bum-out as
well as pin junction damage.
Corrosion - package environment, package moisture content,
glassivationlpassivation integrity, presence of ionic species and
electrical bias conditions can all contribute to corrosion. Corrosion occurs when two or more electrodes are present in an electrolyte (typically moisture) along with some ionic species
(contamination).
Figure 5 shows a summary of identified failure mechanisms
from 1983 to 1990.

Intermetallics - in the microdimensions of integrated circuits,
the interactions between dissimilar metals cannot be ignored.
These intermetallics can have radically different physical, chemical and electrical properties from those of the individual elements or compounds.
Radiation - the ionizing effects of radiation can generate
electron-hole pairs. Recombination of these electron-hole pairs
can result in latch-up, shorting paths, pin junction breakdown
and excessive leakage. Robustness to these radiation effects is
particularly important for semiconductors intended for space or
military applications.
Mechanical - thermal cycling or power cycling can lead to
device failure due to the differences in the coefficients of thermal expansion of the materials used in semiconductor manufacture. Coefficients of thermal expansion can range from 2 to over
40 ppml"C. Fatigue of bond wires can occur during ultrasonic
cleaning due to a high cycle fatigue mechanism. This happens in
hermetic packages that are ultrasonically cleaned in a tank
whose resonant frequency matches those of the bond wires.

Figure 5. Identified Failure Mechanisms (1983-1990)

GENERAL INFORMA TION 1-27

II

1-28 GENERAL INFORMA TION

Operational Amplifiers
Contents
Page

Operational Amplifiers - Section 2 .............................................. 2-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
AD711 - Precision, Low Cost, High Speed BiFET Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
AD712 - Dual Precision, Low Cost, High Speed, BiFET Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
AD713 - Quad Precision, Low Cost, High Speed BiFET Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
AD811 - High Performance Video Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
AD827 - High Speed, Low Power Dual Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45
AD829 - High Speed, Low Noise Video Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
AD840 - Wideband, Fast Settling Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
AD841 - Wideband, Unity-Gain Stable, Fast Settling Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73
AD842 - Wideband, High Output Current, Fast Settling Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81
AD843 - 34 MHz CBFET Fast Settling Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89
AD844 - 60 MHz, 2000 V/"..s Monolithic Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-101
AD845 - Precision, 16 MHz CBFET Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-113
AD846 - 450 VI"..s, Precision, Current Feedback Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-121
AD847 - High Speed, Low Power Monolithic Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-133
AD848/AD849 - High Speed, Low Power Monolithic Op Amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-145

AD5539
OP-27 OP-37 OP-61 -

- Ultrahigh Frequency Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Noise, Precision Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Noise, Precision High Speed Operational Amplifier (AvcL 2:5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wide-Bandwidth Precision Operational Amplifier (Av 2:IO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-153
2-169
2-181
2-193

OP-64 - High Speed, Wide-Bandwidth Operational Amplifier (AvCL2:5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-211
OP-160 - High Speed, Current Feedback Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-225
OP-249 - Dual, Precision JFET High Speed Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-249
OP-260 - Dual, High Speed, Current Feedback Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-267
OP-271 - High Speed, Dual Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-287
OP-275 - Dual Bipolar/JFET, Low Distortion Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-297
OP-471 - High Speed, Low Noise Quad Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-299
SSM-2131 - Ultralow Distortion, High Speed Audio Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-315
SSM-2134 - Low Noise, Audio Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-327
SSM-2139 - Dual, Low Noise, High Speed, Audio Operational Amplifier (AvcL2:3) . . . . . . . . . . . . . . . . . . . . . . . . 2-333

OPERA TlONAL AMPLIFIERS 2-1

II

'"

Selection Guide

~
~

Operational Amplifiers

0

Video Amplifiers

'I"
0

:::!

~

r--

h

~
:ngj
en

Model

SR
AP
V/".s deg
typ
typ

AG
%
typ

Settling
Time
nsto%
typ

BWat
AclMin ACl Vos
MHz
VN mV
typ
min max

Input
Bias
Current
".A max

nV/vHZ rnA
@ 10 kHz min

AD811

2500

0.01

0.01

65-0.01

120

3

10

2

AD844
OP160
OP260
AD5539
AD846
AD840
AD842
AD841
AD847
AD827
AD829
AD848
AD849
AD843
OP64
AD845

2000
1300
1000
600
450
400
375
300
300
300
300
300
300
250
170
100

0.025
0.04
0.067
0.1
0.03
0.04
0.035
0.02
0.2
0.2
0.04
0.08
0.04
0.025
0.018
0.025

0.008
0.04
0.02
0.04
0.01
0.025
0.015
0.03
0.04
0.04
0.D2
0.D7
0.08
0.025
0.045
0.04

100-0.1
75-0.1
250-0.1
12-1
llO-O.OI
100-0.01
100-0.01
110-0.01
120-0.1
120-0.1
90-0.1
100-0.1
80-0.1
135-0.01
100-0.1
350-0.01

60
90
90
220
80
40
40
40
50
50
50
35
30
34
16
16

0.15
5
3.5
3
0.075
0.3
1

0.25
20
8
13
0.25
5
5
5
5
7
7
5
5
0.001
1
0.001

2
5.5
5.5
6
2
4
9
13
15
15
2
5
3
19
8
18

-I
1
1
2
-1
10
2

1
5
25
1
5
1

1
2
0.5
1
0.75
1
0.25

Voltage
Noise

Supply
Range
±Volts

Supply
Current Spice
rnA
Model
typ
Avail. Page

100

4.5 to 18

16.5

20
35
35
15
20
50
100
50
20
20
20
20
20
50
50
25

4.5 to 18
4 to 15
4 to 15
4.5 to 10
5 to 18
5 to 18
5 to 18
5 to 18
4.5 to 18
4.5 to 18
4.5 to 18
4.5 to 18
4.5 to 18
4.5 to 18
5 to 18
4.75 to 18

6.5
6.5
9
14
5
10.5
13
11
5.3
10
5
5.1
5.1
12
6.2
10

lOUT

X

X
X
X
X

X
X
X
X

X

2-41
2-101
2-225
2-267
2-153
2-121
2-65
2-81
2-73
2-133
2-45
2-53
2-145
2-145
2-89
2-211
2-113

Comments
Best Video Specifications Flatness = 0.1 dB
to 35 MHz
Constant 10 ns Rise Time for Any Pulse
Disable Mode for Low Power Applications
Dual OPI6O; Only Dual Transimpedance
Improved Replacement for Industry Standard
Highest DC Precision High Speed Amplifier
Fast Settling Time; Gain > 10
High Current Output; Gain > 2
Fast Settling Time and Unity Gain Stable
General Purpose, Low Power, Unity Gain
Dual AD847
Low Noise and High Speed
General Purpose, Low Power, Gain > 5
General Purpose, Low Power Preamplifier
High Performance, Replaces LH0032
Stable for Gains> 5
General Purpose. Unity Gain Stable

Audio Amplifiers
Single Op Amps
Model

Voltage Noise
@lkHz
nV/vHZtyp

SR
V/IJ-s
typ

AD829
AD846
AD844
OP27
OP37
OP61
SSM2134
OPI60
OP64
SSM2131
AD711
AD843
AD845

2
2
2
3
3
3.4
3.5
5.5
8
13
18
19
25

300
450
2000
2.8
17
40
13
1300
170
50
20
250
100

750
80
60
8
63
200
10
90
80
10
4

SR
V/IJ-s
typ

GBW

Model

Voltage Noise
@lkHz
nVtvHZtyp

SSM2139
OP275
OP260
OP271
OP249
AD712

3.6
5
6
7.6
17
18

11
20
1000
8.5
22
20

GBW

MHz
typ

34
16

Supply
Current
mAmax

VOUT Volts min

Page

Comments

6.8
6.5
7.5
4.67
4.67
8
6.5
8
8
6.5
2.8
13
12

500 n
500 n
500 n
600 n
600 n
500 n
600 n
500 n
200 n
= 1000 n
+ 13/-12.5, RL = 2000
±10, RL = 500 n
± 12.5, RL = 500 n

2-53
2-121
2-101
2-169
2-181
2-193
2-325
2-225
2-211
2-315
2-5
2-89
2-113

Ideal High Gain, Low Noise Input Device
Current Feedback
Low Noise, Highest Slew Rate
Low Cost, Precision
AVCL 2: 5, Low Cost
AVCL 2: 10
Improved 5532
Current Feedback
AVCL 2: 5, High Output Current
Ulttalow Distortion
Precision BiFET
Low Bias Current, Fast Settling
Low Bias Current, Faster Settling

±IO, RL =
±10, RL =
±10, RL =
±10, RL =
±10, RL =
±11, RL =
±12, RL =
±11, RL =
±10, RL =
±11.5, RL

n

Dual Op Amps
typ

Supply
Current
mAlAmpmax

VOUT
Volts
min

Page

Comments

30
8
90
5
4.7
4

3.25
2
5.25
3.25
3.5
2.8

±12, RL = 2000 n
±13, RL = 600 n
±12, RL = 1000 n
±12, RL = 2000 n
±12, RL = 2000 n
+ 13 -12.5, RL = 2000

2-331
2-297
2-267
2-287
2-249
2-17

AVCL 2: 3
Ulttalow Distortion
Current Feedback
Precision
Low Power, Low Distortion
Low Cost, Dual AD711

MHz

n

Quad Op Amps
SR

GBW

V/IJ-S

MHz

Model

Voltage Noise
@lkHz
nVtvHZtyp

typ

OP471
AD713

6.5
18

8
20

c

~
~
:::!

c

~

r-

l>

s::

;:2
5i
ii1

~
~

Co).

typ

Supply
Current
mAlAmpmax

VOUT
Volts
min

Page

Comments

6.5
4

2.75
3

±12, RL = 2000 n
+ 13/-12.5, RL = 2000

2-299
2-29

Precision
QuadAD711

n

2-4 OPERA TlONAL AMPLIFIERS

11IIIIIIII ANALOG
WDEVICES
FEATURES
Enhanced Replacement for LF411 and TL081
AC PERFORMANCE:
Settles to ±O.01% in 1",s
16V/",s min Slew Rate (AD711JI
3MHz min Unity Gain Bandwidth (AD711J1
DC PERFORMANCE:
O.25mV max Offset Voltage: (AD711CI
3",VI"C max Drift: (AD711CI
200V/mV min Open-Loop Gain (AD711KI
4",V p-p max Noise, O.1Hz to 10Hz (AD711CI
Available in Plastic Mini-DIP, Plastic SO, Hermetic
Cerdip, and Hermetic Metal Can Packages
MIL-STD-883B Parts Available
Available in Tape and Reel in Accordance with
EIA-481A Standard
Surface Mount (SOICI
Dual Version: AD712
Quad Version: AD713

PRODUCT DESCRIPTION
The AD71l is a high speed, precision monolithic operational
amplifier offering high performance at very modest prices. Its
very low offset voltage and offset voltage drift are the results of
advanced laser wafer trimming technology. These performance
benefits allow the user to easily upgrade existing designs that
use older precision BiFETs and, in many cases, bipolar op
amps.
The superior ac and dc performance of this op amp makes it
suitable for active filter applications. With a slew rate of 16V/ILS
and a settling time of IlLS to ±O.OI%, the AD71l is ideal as a
buffer for l2-bit D/A and AID Converters and as a high-speed
integrator. The settling time is unmatched by any similar IC
amplifier.
The combination of excellent noise performance and low input
current also make the AD7ll useful for photo diode preamps.
Common-mode rejection of 88dB and open loop gain of 400V/mV
ensure 12-bit performance even in high-speed uriity gain buffer
circuits.
The AD7ll is pinned out in a standard op amp configuration
and is available in seven performance grades. The AD7l iJ and
AD71lK are rated over the commercial temperature range of 0
to + 70°C. The AD7IlA, AD711B and AD711C are rated over
the industrial temperature range of - 40°C to + 85°C. The
AD71lS and AD711T are rated over the military temperature
range of - 55°C to + 125°C and are available processed to MILSTD-883B, Rev. C.

REV. A

Precision, Low Cost,
High Speed BiFET Op Amp
AD711 I
CONNECTION DIAGRAMS
Plastic Mini-DIP (N) Package
Plastic Small Outline (R)
and
Cerdip (Q) Package

TO-99
(H) Package
NC

INVERTING
INPUT

NONINVERTING
INPUT

vNOTE: PIN 4 CONNECTED TO CASE
NC = NO CONNECT

~

~-'5V

Vos TRIM

Extended reliability PLUS screeuing is available, specified over
the commercial and industrial temperature ranges. PLUS screening
includes 168-hour burn-in, as well as other environmental and
physical tests.
The AD711 is available in an 8-pin plastic mini-DIP, small
outline, cerdip, TO-99 metal can or in chip form.
PRODUCT HIGHLIGHTS
1. The AD711 offers excellent overall performance at very
competitive prices.
2. Analog Devices' advanced processing technology and with
100% testing guarantees a low input offset voltage (0.25mV
max, C grade, 2mV max, J grade). Input offset voltage is
specified in the warmed-up condition. Analog Devices' laser
wafer drift trimming process reduces input offset voltage
drifts to 3ILVrC max on the AD711C.
3. Along with precision dc performance, the AD71l offers
excellent dynamic response. It settles to ±0.01% in IlLS and
has a 100% tested minimum slew rate of 16V/ILS. Thus this
device is ideal for applications such as DAC and ADC buffers
which require a combination of superior ac and dc
performance.
4. The AD711 has a guaranteed and tested maximum voltage
noise of 4ILV p-p, 0.1 to 10Hz (AD711C).
5. Analog Devices' well-matched, ion-implanted JFETs ensure
a guaranteed input bias current (at either input) of 25pA max
(AD711C) and an input offset current of 10pA max (AD711C).
Both input bias current and input offset current are guaranteed
in the warmed-up condition.

OPERA TIONAL AMPLIFIERS 2-5

II

AD711-SPECIFICATIONS
Model

(@ +25°C and Vs

AD711JIAIS

Min
INPUT OFFSET VOLTAGE'
Initial Offset

Tn>

Max

0.3

211/1
3/2/2

Tmin toT.....

vs.Temp.
vs. Supply
VB. Supply, T min to T max:
Lolli Term Offset Stability

7
·95

76

Full Power Response
Stew Rate, Unity Gain

AD711KIIIIT
Typ
0.2

20120120
80
80

76176176
15

INPUT BIAS CURRENT'
Either Input, VeM == 0
Either Input at T_,
VCM ~0(70"C185"C1125"C)
Either Input, VCM ~ + IOV
Offset Current, VCM = 0
Offset Current at T mu.
(70"C185"C1125"C)
FREQUENCY RESPONSE
UnityGain, Small Signal

Mia

15

= ±15V dc, unless othelWise noted)

5
100

15

SO

4
200
20
I

16

Senling Time to 0.01%'

0.5
1.0
10

AD711C
Typ
0.1

86
86

2
110

20
5

100
25

SO

3.4

1.2

4
200
20
I

Unitt

0.25
0.45
3

mV
mV
fJ. VrC
dB
dB

fLVlmonth

IS

25
1.6

pA
nA

100
25

20
5

SO
10

pA
pA

0.65

nA

0.5711.6126

18

Mu

15

1.113.2151

0.57/1.6126
3.0

Mira

15

1.1/3.2/51
20
10

MOll

3.4
18

1.2

4
200
20
I

MHz
kHz
V/fJ.s

1.2

fJ.S

Total Harmonic Distortion
f~

1kHz
R L "'2k!l, Vo~ 3VRMS
INPUT IMPEDANCE
Differential
Conuuon-Mode

0.0003

0.0003

0.0003

%

3x 1012 115.5
3x 1012 115.5

3x 10 12 115.5
3x 10 12 115.5

3x 10 12 115.5
3x 1012 115.5

IlllpF
IlllpF

INPUT VOLTAGE RANGE

Differential4
Common-Mode Voltage
Over Max Operating Range'
Common-Mode Rejection Ratio

VCM= ±lOV

76

Tmin to Tmu
VCM= ± llV

76176176

TJlliDtoT_

0020
+ 14.5, - 11.5

0020
+ 14.5, -11.5
-Vs+4V

+Vs-1V

80
80
76
74

88
84
84

70
10170170

80

INPUT VOLTAGE NOISE
VoltageO.IHzto 10Hz

86
86
76
74

88
84
84

80

94
90
90

V
dB
dB
dB
dB

84

18
16
0.01

0.01

0.01

pAIYHZ

400

V/mV

22

f~IOkHz

V
+Vs-1V

2
45
22
18
16

2
45

f~

f~lkHz

-Vs+4V

2
45
22
18
16

f~IOHz

100Hz

0020

+ 14.5, -11.5
+Vs-1V

-Vs+4V

4.0

fJ.Vp-p
itV/YHZ
nV/YHZ
nVIYHZ
nV/YHZ

INPUT CURRENT NOISE
f~lkHz

OPEN LOOP GAIN"

Vo= ±lOV,RL~2kU
Vo= ± lOV,RL~2kO,
TmintoTmu

OUTPUT CHARACTERISTICS
Voltage@RL ",2k!l
Voltage@RL "'2k!l,
T min to Tmax
Short-Circuit Current
POWER SUPPLY
Rated Performance
OperatingRange
Quiescent Current

400

ISO

100

10011001100

400

200

100

100

VlmV

+13, -12.5

+ 13.9, -13.3

+13, -12.5 + 13.9, -13.3

+13, -12.5 + 13.9,-13.3

V

±12l±12l:t12

+ 13.8,-13.1
25

±Il

±12

V
mA

±IS

±IS
±4.5

TEMPERATURE RANGE
Operating, Rated Perfonnance
Conuuercial(O to + 1O"C)
Induattial ( - 4O"C to + 85"C)
Military ( -55"Cto + 125"C)
PACKAGEOPTlONS'
Plaatic(N-8)
SOIC(R-8)
CCrdip (Q-8)
TO-99 (H-08A)
Tape aod Reel
J, KaodSChipsAvailable
TRANSISTOR COUNT

2-6 OPERA TIONAL AMPLIFIERS

2.5

±18
3.4

AD71lJ
AD7llA
AD711S
AD711JN
AD711JR
AD71IAQ, AD711SQ
AD71IAH, AD71lSH
AD711JR-REEL
30

+ 13.8, - 13.1
25

±4.5
2.5

0015
±IB
3.0

AD711K
AD711B
AD71lT
AD711KN
AD711KR
AD71IBQ,AD71ITQ
AD71IBH,AD71lTH
AD7IIKR-REEL
30

+ 13.8, -13.1
25

±4.5
2.5

±IB
1.B

V
V
mA

AD71IC

AD711CQ
AD711CH

30

REV. A

AD711
NOTES
'Input offset voltage specifications are gUaranteed after 5 minutes of operation at TA = + 25°C.
2Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at T A = + 25°C.
For higher temperature, the current doubles every lOoC.
'Refer to Figure 29.
'Defmed as voltage between inputs, such that neither exceeds ± IOV from ground.
STypically exceeding - 14.1 V negative common-mode voltage on either input results in an output phase reversal.
'Open-Loop Gain is specified with Vos both nulled and unnulled.
'H = Metal Can; N = Plastic DIP; Q = Cerdip; R = SOIC. For outline information see Package Information section.
Specifications subject to change without notice.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at fmal
electrical test. Results from those tests are used to calculate outgoing quality levels.

ABSOLUTE MAXIMUM RATINGS·
Supply Voltage . . . . . .
Internal Power Dissipation2 . .
Input Voltage 3 • • • • • • • • •
Output Short Circuit Duration
Differential Input Voltage . . .
Storage Temperature Range Q, H
Storage Temperature Range N
Operating Temperature Range

±18V
500mW
. ±18V
Indefinite
+Vsand -Vs
- 65°C to + 150°C
- 65°C to + 125°C

NOTES
I Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
lThermal Characteristics
8-PinPlasticPackage:6jc = 33°CIW,6jA = lOO°CIW
8-PinCerdipPackage:6jc = 22°CIW,6jA'= 1l0"CIW
8-PinMetaICanPackage:6jc = 6S CIW,6jA = ISO"CIW
3Por supply voltages less than ± 18V, the absolute maximum input voltage is
equal to the supply voltage.

AD711J/K
0 to + 70°C
AD71lA/B/C . . . . . . . .
- 40°C to + 85°C
AD71lS/T . . . . . . . . .
- 55°C to + 125°C
Lead Temperature Range (Soldering 60 seconds) . . .. 300°C

0

METALLIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.

OFFSET
NULL
1

-IN 2

+IN 3

0.067
(1.7018)

6 OUT

5 OFFSET
NULL

L
REV. A

4

vO.065
(1.651)

v-

CONNECTED TO CASE
PIN 8 = NO CONNECT

OPERA TIONAL AMPLIFIERS 2-7

•

AD711-Typical Characteristics
20~----~-------r------~------'

20

~

t, 15~-----1-------+------1.~L-~

/

/

/

V
o

/

o

I
w

~

~

~
~ .~----~~~-+------+-----~
o

RL""ZkU
2,"C

10

~15V ~"'PPllES
10~-----1-------+~~--~----~

15

I

I
o

0~0------~----~'~0------~15~----~20

20

100

Figure 3. Output Voltage' Swing
VS. Load Resistance

•

2.7

100

r- Ave!..

•

1

2.

,

I"
-

I

f

2.25

.

f

2.

•

10

15

20

10- 1
-60

-40

20

0

Figure 4. Quiescent Current VS.
Supply Voltage

60

26

Va= ±15Y

20

2."C

'" r\...

2-8 OPERA TIONAL AMPLIFIERS

:; 4.5

,

,-\

%

~

2

::l

~ I"-

10
0

20

40

60

80

"1::

.....

"

~ r--...

~

""

-60 -40 -20

4.0

z

100

120 140

AMBIENT TEMPERATURE - "C

VS.

10M

5.0

I:i

12

10

1M

lOOk

Figure 6. Output Impedance
VS. Frequency

VS.

=!!

14

-.

10k

1k

FREQUENCY _ Hz

I

-OUTPUT'CURREN~

I.

r-~

140'

I

+" OUTPUT CURRENT

18

LI~••••"A

120

i

"'"

.1

22

COMMON MODE VOLTAGE - Volb

100

..

r- .........

24

Figure 7. Input Bias Current
Common Mode Voltage

80

0.01

0q

Figure 5. Input Bias Current
Temperature.

100

MAX J GRADE

20,. 40

TEMPERATURE -

SUPPLY VOLTAGE - :!:Volts

-10

II'"
0.1

f

1.7

o

+1

10

I•
"

10k

1k

LOAD RESISTANCE - Ohms

Figure 2. Output Voltage Swing
vs. Supply Voltage

Figure 1. Input Voltage Swing
VS. Supply Voltage

10

~Volts

SUPPLY VOLTAGE -

SUPPLY VOLTAGE - :!:Volts

/

Figure 8. Short Circuit Current
Limit VS. Temperature

r--. r---..

........

Z
:> 3.5

3.0
-60 -40 -20

20

40

60

80

~

100 120

140

TEMPERATURE _ "C

Figure 9. Unity Gain Bandwidth
VS. Temperature

REV. A

AD711
+100

--~

+80

,-

t

--- ---PHASE

""

,

CJ +40

~

\

11 •

-20

lOOk

10k

Rl ",2kl)
25"C

\

+0

1k

• 60

\

I
I
I

"r\.

= 2kU
C = 100pF
R~

100

120

\

~ +20

10

180'

\

~N

~

110

12.

140'

110

-+20'

""
1M

"

1O.

~

9.

20'

10M

IIII

80

VCM ",1V pop

~

~,

60

1\

~

40

~

1\

°

10

100

1k

15

10

10

20

10k

lOOk

20

~

R(=2kH
25'C
Vs~

2kU
Ct. = l00pF

-90

",

-120

4
2

... -~

~

~

°

lOOk

1M

"

-6

o

~,

0.'

0.7

0.6

"""" ~"
0.8

,.

20

.

10

V

~

~

1

V

15

w

r--r-.

lOOk

1.0

0.'

Figure 15. Output Swing and
Error vs. Settling Time

,

Figure 16. Total Harmonic
Distortion vs. Frequency

r\.

SETTLING TIME - j.1S

;;

10k

\

-10

10M

0.01%

\ 1\ \

-8

t---.r-.

"
/'

FREQUENCY _ Hz

0.01%

0.1%

\

>- -4

::>

I'::>

1

REV. A

1%

2.

~

1k

ERROR

"~ -2

10

0.1"10

0

Figure 14. Large Signal
Frequency Response

-130
100

/1 /
1"10

:l

::!:15V

15

I

-100

j:
-110

.,

1;

1000

Rl

.......::: V"" ~

o

\

1M

lOOk

1// /
L ilL

INPUT FREQUENCY - Hz

-70

10k

Figure 12. Power Supply
Rejection vs. Frequency

>

..........

1M

1k

SUPPLY MODULATION FREQUENCY - Hz

:\

Figure 13. Common Mode
Rejection vs. Frequency

3VRMS

100

10

FREQUENCY - Hz

-80

IIII I

o

o

....

20

.....

Vs = ± 15V SUPPLIES
WITH 1V pop SINE
WAVE 25"C

20

~

Vs""::!:1SV

:l

Q

40

2.

25"

.",

/

....
,SUPPLY

30

..

....
....

60

Figure ". Open-Loop Gain vs.
Supply Voltage

100



Max

Uaita

0.1

0.30
0.60

mV
mV

3
110

5

,.vrc

dB
dB
JA,V/month

15

25

75

20

75

20

SO

pA

1.7/4.8/77

0.5/1.3/20

1.7/4.8/77

1.3

10

100
25

5

100
25

5

l.2
75
10

nA
pA
pA

0.3/0.7/11

0.611.6126

0.1I0.l/5

0.611.6126

0.3

0.7

nA

O.l
-0.6
5
10

mV
mV

110.710.7
211.511.5
10
25

20120120
25
120

120

90

16

110.710.7
Vl.Sll.5
10

0.611.6126

lllll

Total Harmonic Distortion
f= lkHz,RL ;:=:2k!l, Vo=3Vrms

Mia

15

4/2/2

l.O

AD71ZC

Max

4
200
20
I

120

90

1.4

18
1.2

4
200
20
I

90

l.4
18
1.2

4
200
20
I

,.vrc

pA
dB
dB
MHz
kHz

Vi ....
1.2

....

O.oool

O.oool

0.0003

%

lXI0 12 115.5
lxlO 12 115.5

lx 10"115.5
3x 10"115.5

lxlO 12 115.5
lxlO 12 115.5

fillpF
fillpF

±20

V

INPUT IMPEDANCE
Differential

Common Mode
INPUT VOLTAGE RANGE
Oifferential6
CommOn-Mode Voltllg<
Over Max Operating Range'
Common-Mode Rejection Rstio
VCM.= ::tIOV
Tmin to Tmax
VCM = ::tHV
TmintoT_

±20

-Vs+4V
76

88

76fl6l76

84
84
80

70
70170170

±20

+ 14.,5, 11.5 +Vs -2V

-Vs+4V
80
80
76
74

+ 14.5, -11:5 +Vs -2V

-Vs+4V

88
84

86
86

84

76
74

80

+14.5, -11.5 +Vs -2V
94

V
dB
dB
dB
dB

90
90

84

INPUT VOLTAGE NOISE
VoltageO. 1Hz to 10Hz
f=IOHz
f=IOOHz
f=lkHz
f= 10kHz

2
45
22
-18
16

2
45
22
18
16

2
45
22
18
16

INPUT CURRENT NOISE
f= 1kHz

0.01

0.01

0.01

pAlYHz

400

V/mV
VlmV

OPEN LOOP GAIN
Vo= ±lOV,RL~2kO
TmintoTmu,RL~2kfl

OUTPUT CHARACTERISTICS
Voltage@RL "2kn
T min to T_
SbortCircuit Current
POWER SUPPLY
RstedPerlormaru:e
Operating Range
Quiescent Current,
Both Amplif....

ISO
10011001100

400

200
100

+13, -12.5
+ 13.9, - 13.3
±12, ± 12,:1::12 + 13.8,- 13.1
25

TEMPERATURE RANGE
Operating, Rated Performance
Commercial (0 to + 7O"C)
Industrial ( - 4O"C to + 85°C)
Military ( - SSOCto + 125"C)
PACKAGE OPTIONS'
SOIC(R-8)
Plastic (N-8)
Cerdip (Q-8)
TO-99 (H-08A)
Tape and Reel
A, J and S Grsde Chips Available

2-18 OPERATIONAL AMPLIFIERS

6.8

%4.5

nV/VHz

+13, -12.S + 13.9, -13.3
±12
+ 13.8,-13.1
25

5

V
V
mA

±15
%18
6.0

AD712J
AD712A
AD712S

AD712K
AD712B
AD712T

AD712JR
AD7l2JN
AD712AQ, AD712SQ
AD712AH, AD712SH
AD712JR

AD712KN
AD712BQ,AD712TQ
AD712BH,AD712TH

%4.5
5

"Vl"P
nV/YHz

nV/YHz
nV/YHz

100

± 15
%18

5

200

+13, -U.S + 13.9, - 13.3
±12
+ 13.8,-13.1
25

±15
%4.5

400

4

%18

V
V

5.6

mA

AD712C

AD712CQ
AD712CH

REV. A

AD712
NOTES
Ilnput Offset Voltage specifications are guaranteed after 5 minutes of operation at TA = + 25"C.
lBias Current specifkations are guaranteed maximum at either input after 5 minutes of operation at T A == + 25"<:. For hiJber temperature, the current doubles every 1O"C.
JMatching is defmed as the difference between paramerers of the two amplifiers.
4Refer to FiJure 21.
51lefer to FiJure 29.
'Defined as volt. between inputs, such that neither exceeds ± lOY from ground.
7Typicallyexceeding -14.1V negative common-mode voltage on either input results in an outpUt phase reversal.
-Por outline information see Package Information section.
Specifications subject to change without notice.
SpeciflClllions in boldface are tested on all production units at final electrical test. Results from dtose tests are used to calculate outgoing quality levels. AU min and max spcciflCltions
are guaranteed., although only those shown in boldface are tested on all production units.

ABSOLUTE MAXIMUM RA TINGS 1
Supply Voltage . . . . . .
. ±18V
Internal Power Dissipation 2 • •
SOOmW
Input Voltage3 • • • • • • . • •
. ±18V
Output Short Circuit Duration
Indefinite
Differential Input Voltage . . .
+Vs and -Vs
Storage Temperature Range Q, H
-65°C to + 150°C
- 65°C to + 125°C
Storage Temperature Range N
Operating Temperature Range
AD712JIK
. . . 0 to + 70°C
AD712A1BIC . . . . . . .
- 40°C to + 85°C
AD712SIT . . . . . . . .
- 55°C to + 125°C
Lead Temperature Range (Soldering 60 seconds) . . .. 300°C

NOTES
IStresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
lThermal Characteristics:
8-Pin Plastic Package: 6 jA ~ 16S'CIW.
8-PinCerdipPackage:6Jc = 220C1W,8JA = 1I0°C/W.
8-PinMetalCan Package: 6jc ~6S'CIW,6jA c-ISO'C/W.
JFor supply voltages less than ± 18V, the absolute maximum input voltage is
equal to the supply voltage.

METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and Cmm).

1

'0---------- ~~~
v+

--------->..j!

r-'"'
OUTPUT

-IN

REV. A

-IN

8

+IN

5 +IN

v-

OPERATIONAL AMPLIFIERS 2-19

•

AD112 - Typical Characteristics
20

30

20

",..

.. 25

/

/

~

*!i!,
>

/

/

o

!
,

10

:>~

...~

RL =2kU
250C

~

0

SUPPLY VOLTAGE

~

Yolts

"

0

zo

10

0

(

"

I

I

100

1k

10k

Figure 3. Output Voltage Swing
VS. Load Resistance

100

10-'

1-

::>

I-"
10

LOAD RESISTANCE - Ohms

Figure 2. Output Voltage Swing
vs. Supply Voltage

t

/

II

o

10-~

"~
..~

/

SUPPlY VOLTAGE:!: Volts

Figure 1. Input Voltage Swing
vs. Supply Voltage

lSV SUPPLIES

5

20

15

:!:

10

~
~

::>

10

11

20

I..
"

~

III
i!

~

o

~

15

10

~ 10-~

~

i.

.i3

/
10-!J

1

; 10- 10

0

~~ 10-

0.1

./

11

I,.;'
10

15

10- 12
-60

zo

40 -20

0

Figure 4. Quiescent Current vs.
Supply Voltage

MAX J GRAol

75

50

i

~

g

25

60

80

100

0.01

120 140

1k

--

Figure 5. Input Bias Current vs.
Temperature

LI~

24

"E,
t:

~

Vs "" :t15V
250C

::>

~

"5
COMMON MODE VOLTAGE - Volts

Figure 7. Input Bias Current vs.
Common Mode Voltage
2-20 OPERATIONAL AMPLIFIERS

2Z
20

.~ ,.
"t:
~
0
~

.'"

,.

10M

1M

100k

Figure 6. Output Impedance vs.
Frequency

5.0

"

........

-OUTPUT

+ OUTPUT CURRENT

"!\1\

:l!

lE 4.'

,
~

.......
CURREN~'

i

"
:!

Z

r" ~

......

~ .......

4.0

.......

r--.... j'-.....

~

......

"~

....... ~

r---.

Z
::> 3.S

14

.......

12

o
-10

10k

fREQUENCY - Hz

Z6

100

Ia

40

TEMPERATURE _ "C

SUPPLY VOLTAGE ± Votts

,

20

10

10
-60 -40 -20

0

20

40

60

80

100

120 140

AMBIENT TEMPERATURE - "C

Figure 8. Short Circuit Current
Limit vs. Temperature

3.0
-60 -40 -20

20

40

80

80

100 120

140

TEMPERATURE - "C

Figure 9. Unity Gain Bandwidth
vs. Temperature

REV. A

AD712
+100

+,oo~

--~ ~- --- ----

+so

"0

125

-, ,

"

\

";' +60
Z

;;

\

""

§'"

+40

i!i

:!i+20

GAIN

+40"

\

~

Z

Rl=2kll

~ ~

\

8~
":E ~

2S"C

110

\

+20"

~ ~ 105

~

0

'\

10

100

10k

1k

lOOk

.
~

2

o

10

20

15

1111

~,
~

"

~ .0

~

10

"

20

I!:

\

20

Rl =2kU

100

1k

10k

lOOk

1M

10

RL = 2kU
C L = l00pF

-go

1I

,

,
C -100
~

i!'

V

-110

-

-130
100

r--...'~
0.5

1.0

0.9

Figure 15. Output Swing and
Error vs. Settling Time

25

20

t,

V

15

10

V

1,....00"'o

1
100k

1

10

1k
100
FREQUENCY - Hz

10k

lOOk

,,-

.,

V

S
~

10k

t::--"'

SETTLING TIME - ",5

1'1--

FREQUENCY - Hz

"

0.8

0.7

0.'

~

V"

1k

\

\ 1\ \

-8

Figure 14. Large Signal
Frequency Response

~

a>

0.01%

-10
10M

1M

,...-.

0.01%

0.,1010

\

1000

,VRMS I

0.1%

1%

INPUT FREQUENCY' - Hz

-so

-120

1%

"- ........ r-.

Figure 13. Common Mode
Rejection vs. Frequency

1M

II I
// I

'\
lOOk

100k

1// /

ERROR

FREQUENCY - Hz

-70

10k

/

25"C
Vs= :!:15V

~

15

"c

....

1k

/ . :::;;-.....

..

"'
"

~

g

o
10

100

Figure 12. Power Supply
Rejection vs. Frequency

g

5

"

IIII I

SUPPLY MODULATION FREQUENCY _ Hz

25

.0

,

~

WAVE 25"C

10

~

25..,

I"

Vs = ± 1SV SUPPLIES

WITH lV p.p SINE

Figure 11. Open Loop Gain vs.
Supply Voltage

Vs::±15V
VcM =1V p.p

"

,SUPPLY

iil

'0

....

I"

SUPPLY VOLTAGE ± Volts

100

so

"

o

Figure 10. Open Loop Gain and
Phase Margin vs. Frequency

o

'"
~

95

FREQUENCY - Hz

r-..

.0

20

10M

1M

OJ

+LJpL

I"

100

20"

-20

~

.,.--- / '

II
~

80

Z

/
V

'" 0
Z

\

"~

LOAD

+0

C

\

PHASE
2kU l00pF

,

~

+60' ~ ";' 115

\

'\

a>

m..

\

r'\.

a>

a>

-....

100
12.

V

o

V

/

100

200

300

400

500

600

700

800

900

INPUT ERROR SIGNAL - mV

(AT SUMMING JUNCTION I

Figure 16. Total Harmonic
Distortion vs. Frequency

REV. A

Figure 17. Input Noise Voltage
Spectral Density

Figure 18. Slew Rate vs. Input
Error Signal
OPERA TIONAL AMPLIFIERS 2-21

•

AD712

J,

INPUT

i2.~;--r-t~--r-~~~-4~

;

Figure 20. T.H.D. Test Circuit
'5~-L~

__~~~__~~~__L-~

-60 -40 -20

0

20

40

60

80

100

V OUT

120 140

TEMPERATURE _ "C

2OkO

Figure 19. Slew Rate vs.
Temperature

Figure 21. Crosstalk-Test Circuit

SQUARE
WAVE

-Vs

INPUT

Figure 22a. Unity Gain Follower

Figure 22b. Unity Gain Follower
Pulse Response (Large Signal)

Figure 22c. Unity Gain Follower
Pulse Response (Small Signal)

Figure 23b. Unity Gain Inverter
Pulse Response (Large Signal)

Figure 23c. Unity Gain Inverter
Pulse Response (Small Signal)

SkU

SkU

SQUARE
WAVE

INPUT
-Vs

Figure 23a. Unity Gain Inverter

2-22 OPERA TIONAL AMPLIFIERS

REV. A

AD712
OPTIMIZING SETTLING TIME
Most bipolar high-speed DIA converters have curent outputs;
therefore, for most applications, an external op amp is required
for current-to-voltage conversion. The settling time of the converter/op amp combination depends 9n the settling time of the
DAC and output amplifier. A good approximation is:
t, Total = Vet, DAC)2 + (t, AMP)2
The settling time of an op amp DAC buffer will vary with the
noise gain of the circuit, the DAC output capacitance, and with
the amount of external compensation capacitance across the
DAC output scaling resistor.
Settling time for a bipolar DAC is typically 100 to 500ns. Previously, conventional op amps have required much longer settling
times than have typical state-of-the-art DACs; therefore, the
amplifier settling time has been the major limitation to a high-speed
voltage-output D-to-A function. The introduction of the AD7111
712 family of op amps with their Il1s (to :to.01% of final value)
settling time now permits the full high-speed capabilities of
most modem DACs to be realized.

In addition to a significant improvement in settling time, the
low offset voltage, low offset voltage drift, and high open-loop
gain of the AD71l1AD712 family assures 12-bit accuracy over
the full operating temperature range.
The excellent high-speed performance of the AD712 is shown in
the oscilloscope photos of Figure 25. Measurements were taken
using a low input capacitance amplifier connected directly to the
summing junction of the AD7l2 - both photos show the worst
case situation: a fuil-scale input transition. The DAC's 4kU
[lOknllskU=4.4kH) output impedance together with a 10k!!
feedback resistor produce an op amp noise gain of 3.25. The
current output from the DAC produces a IOV step at the op
amp output (0 to - IOV Figure 25a, - lOY to OV Figure 25b.)
Therefore, with an ideal op amp, settling to :t l/2LSB (:to.01%)
requires that 37511 V or less appears at the summing junctioq.
This means that the error between the input and output (that
voltage which appears at the AD7l2 summing junction) must be
less than 37511V. As shown in Figure 25, the total settling time
for the AD7121AD565 combination is 1.2 microseconds.

Figure 24. ± 10V Voltage Output Bipolar DAC

AD712

SUMMING
JUNCTION

AD712
SUMMING
JUNCnON

AD712

AD712

OUTPUT

OUTPUT

a. (Full-Scale Negative Transition)

b. (Full-Scale Positive Transition)

Figure 25. Settling Characteristics for AD712 with AD565A

REV. A

OPERA TIONAL AMPLIFIERS 2-23

AD712
OP AMP SETTLING TIME - A MATHEMATICAL
MODEL
The design of the AD712 gives careful attention to optimizing
individual drcuit components; in addition, a careful tradeoff
was made: the gain bandwidth product (4MHz) and slew rate
(20VI ",s) were chosen to be high enough to provide very fast
settling time but not too high to cause a significant reduction in
phase margin (and therefore stability). Thus designed, the AD712
settles to ±O.OI%, with a IOV output step, in under I'",s, while
retaining the ability to drive a 2S0pF load capacitance when
operating as a unity gain follower.
If an op amp is modeled as an ideal integrator with a unity gain
crossover frequency of Old2-rr, Equation 1 will accurately describe
the small signal behavior of the circuit of Figure 26a, consisting
of an op amp connected as an I-to-V converter at the output of
a bipolar or CMOS DAC. This equation would completely
describe the output of the system if not for the op amp's finite
slew rate and other nonlinear effects.

Equation 1.

v,.

Figure 26b. Simplified Model of the AD712 Used as an
Inverter

Vo
lIN = R(Cf +
(1)0

-R

Cx) S2 + (GN + RCf) s + I
Wo

where ~; = op amp's unity gain frequency
GN

When Ro and 10 are replaced with their Thevenin VIN and RIN
equivalents, the general purpose inverting amplifier of Figure
26b is created. Note that when using this general model, capacitance Cx is EITHER the input capacitance of the op amp if a
simple inverting op amp is being simulated OR it is the combined
capacitance of the DAC output and the op amp input if the
DAC buffer is being modeled.

= "noise" gain of drcuit (I + ~J

This equation may then be solved for

In either case, the capacitance Cx causes the system to go from
a one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp
output. Since the value of Cx can be estimated with reasonable
accuracy, Equation 2 can be used to choose a small capacitor,
Cp , to cancel the input pole and optimize amplifier response.
Figure 27 is a graphical solution of Equation 2 for the AD7l2
with R = 4kO.

Cr:

Equation 2.

Cr

=

2 - GN + 2YRCX Olo + (1- GN)
ROlo
ROlo

In these equations, capacitor Cx is the total capacitance appearing
at the inverting terminal of the op amp. When modeling a DAC
buffer application, the Norton equivalent circuit of Figure 26a
can be used directly; capacitance Cx is the total capacitance of
the output of the DAC plus the input capacitance of the op amp
(since the two are in parallel).

x

"

.
Figure 27. Value of Capacitor CF

VB.

Value of Cx

The photos of FigUres 28aand 28b show the dynamic response
of the AD712 in the settling test circuit of Figure 29.

Figure 26a. Simplified Model of the AD712 Used as a
Current-Out DAC Buffer

2-24 OPERA TIONAL AMPLIFIERS

The input of the settling time fixture is driven by a flat-top
pulse generator. The error sign'ai output from the false summing
node of Al is clamped, amplified byA2 and then clamped
again. The error signal is thus clamped twice: once to prevent
overloading amplifier A2 and then a second time to avoid overloading the oscilloscope preamp. The Tektronix oscilloscope
preamp type 7A26 was carefully chosen because it does not
overload with these input levels. Amplifier A2 needs to be a
very high-speed, FET-input op amp; it provides a gain of 10,
amplifying the error signal output of AI.

REV. A

AD712
~-f

r-l ; : r~+
I

I

I
-

Figure 2&. Settling Characteristics 0 to + 10V Step
Upper Trace: Output of AD712 Under Test (5V!Div)
Lower Trace: Amplified Error Voltage (0.01%1Div)

:

-

-

500nS

Figure 28b. Settling Characteristics 0 to -10V Step
Upper Trace: Output of AD712 Under Test (5V!Div)
Lower Trace: Amplified Error Voltage (0.01%1Div)

Figure 29. Settling Time Test Circuit

GUARDING
The low input bias current (I SpA) and low noise characteristics
of the AD712 BiFET op amp make it suitable for electrometer
applications such as photo diode preamplifiers and picoampere
current-to-voltage converters. The use of a guarding technique
such as that shown in Figure 30, in printed circuit board layout
and construction is critical to minimize leakage currents. The
guard ring is connected to a low impedance potential at the
same level as the inputs. High impedance signal lines should not
be extended for any unnecessary length on the printed circuit
board.

TO-99 (8) Package

Plastic Mini-DIP (N) Package
and
Cerdip (Q) Package

DIA CONVERTER APPLICATIONS
The AD712 is an excellent output amplifier for CMOS DACs.
It can be used to perform both 2 quadrant and 4 quadrant operation.
The output impedance of a DAC using an inverted R-2R ladder
approaches R for codes containing many Is, 3R for codes containing
a single I, and for codes containing all zero, the output impedance
is infinite.

For example, the output resistance of the AD7S4S will modulate
between Ilk!! and 33k!!. Therefore, with the DAC's internal
feedback resistance of Ilk!!, the noise gain will vary from 2 to
4/3. This changing noise gain modulates the effect of the input
offset voltage of the amplifier, resulting in nonlinear DACamplifi.:r performance.
The AD712K with guaranteed 700fLV offset voltage minimizes
this effect to achieve 12-bit performance.
Figures 31 and 32 show the AD712 and AD7S4S (l2-bit CMOS
DAC) configured for unipolar binary (2-quadrant multiplication)
or bipolar (4-quadrant multiplication) operation. Capacitor CI
provides phase compensation to reduce overshoot and ringing.

Figure 30. Board Layout for Guarding Inputs

REV. A

OPERATIONAL AMPLIFIERS 2-25

II

AD712
Figures 33a and 33b show the settling time characteristics of the
AD712 when um:d asa DAC outp~~"buffer for the AD7545.

lili iii

-

•

11"

!l-"

I

II I
-I

--

I= ·~

I-

H·

+-+

~I~

I-

•

s

:JRt!~

--

..-

r- 1111-

,1

,

i
I. illl ----y-- ;;; III
;~ 1

II

a. Full-Scale Positive
Transition

I-

·m·

II ::::!l s

1

i

5

II:~

b.. Full-Scale Negative
Transition .

Figure 33. Settling Characteristics for AD712 with AD7545
NOISE CHARACTERISTICS
The random nature of noise, particularly in the IIf region, makes
it difficult to specify in practical terms. At the same time, designers
of precision instrumentation require certain guaranteed maximum
noise levels to realize the full accuracy of their equipment.

Figure 31. Unipolar Binary Operation

The AD712C grade is specified at a maximum level of 4.01LV
p-p, in a 0.1 to 10Hz bandwidth. Each AD712C receives a
100% noise test for two 10-second intervals; devices with any
excursion in excess of 4.01LV are rejected. The screened lot is
then submitted to Quality Control for verification on an AQL
basis.
All other grades of the AD712 are sample-tested on an AQL
basis to a limit of 61LV P-P, 0.1 to 10Hz.

Figure 32. Bipolar Operation
Rl and R2 Calibrate the zero offset and gain error of the DAC.
Specific values for these resistors depend upon the grade of
AD7545 and are shown below.

DRIVING THE ANALOG INPUT OF AN AID
CONVERTER
An op amp driving the analog input of an AID converter, such
as that shown in Figure 34, must be capable of maintaining a
constant output voltage under dynamically changing load conditions. In successive-approximation converters, the input current
is compared to a series of switched trial currents. The comparison
point is diode clamped but may deviate several hundred millivolts
resulting in high frequency modulation of AID input current.
The output impedance of a feedback amplifier is made artificially
low by the loop gain. At high frequencies, where the loop gain
is low, the amplifier output impedance can approach its open
loop value. Most IC amplifiers exhibit a minimum open loop
output impedance of 250 due to current limiting resistors. A

TRIM
RESISTOR JN/AQISD

KNIBQfI1) LN/CQIUD GUi'/GCQIGUD

R1

5000

2000

R2

1500

680

1000
330

200
6.80

Table I. Recommended Trim Resistor Values vs. Grades
of the AD7545 for Voo = + 5V



,

I"- ;--...

4.0

i'-.

...... ........

,.S

r--.. r--....

12

10
-60 -40 -20

0

20

40

60

80

100

120 140

AMBIENT TEMPERATURE - "C

Figure 8. Shon Circuit Current Limit
vs. Temperature

3 .•
-60 -40 -20

20

40

60

80

100 120

140

TEMPERATURE _ "C

Figure 9. Gain Bandwidth Product vs.
Temperature

REV. A

AD713
+100"

--~ ~+BO

--- ----

~+60
Z

--4

"'-....

1M

lOOk

1M

........::: ~,....-

;:;

Rl =2kU

"

lOOk

LL L

~

0

10k

SUPPLY MODULATION fREQUENCY _ Hz

r\

~15V

r-.

10

1k

25

"

o

100

10

25"C

":Eu 40

•

l[ ]

10

Figure 1,. Open Loop Gain vs. Supply Figure 12. Power Supply Rejection vs.
Voltage
Frequency

VcM =lV pop

,

20

20

30

1111

"

"SUPP1.V

SUPPLY VOLTAGE!: VOLTS

100

"

Vs=:t 15V SUPPUES
WITH 1V p-p SINE
WAVE 25"C

o

o

.lulL

iii ..

,.0

Figure 10. Open Loop Gain and Phase
Margin vs. Frequencv

1.0

0.9

SETTLING TIME - 115

Figure 14. Large Signal Frequency
Response

Figure 15. Output Swing and Error vs.
Settling Time

,

1000

II"

-so

..,

Ii .

,--- .."

1\

"

, BO

l;?
« 9

I

1M

lOOk

10k

~

+40" 3!l:

\

"i'\.

PHASE - - - -

+0

\

r--

120

+60" ~ ~"5

\

~

+40

~

\

'\..

§"

11

100
+80"

"'

.

11.

12.

-"

3VRMS
RL = 2kU
CL = l00pF

-9.

'-

II

0 - 100

i!:

/

-110

-120

-130

--

"

~V

5
1

,/

r--""

V

V'

V-

0

~

~..-'

V

'..,.IV

1

'.0

10k

lOOk

FREQUENCY _ Hz

Figure 16. Total Harmonic Distortion
vs. Frequency

REV. A

~

0

V

1

I.

100

"

I ••

lOOk

FREQUENCY - Hz

Figure 17. Input Noise Voltage Spectral
Density

.

100

200

300

400

500

600

100

800

900

INPUT ERROR SIGNAl- mV
lAY SUMMING JUNCTIONI

Figure 18. Slew Rate vs. Input Error
Signal

OPERATIONAL AMPLIFIERS 2-33

Applying the AD713
-70

II

-80

r,.,

I g; •

9kll

+ v..

I1: .'f1

COM
ALL 4 AMPLIFIERS
ARE CONNECTED
AS SHOWN

-v.

a

1!

1'f1
IO"f1 I'f1
o

F

F

:1':l!3

F

F

V
a

AD7'3
PIN "

."

-90

~

1-100

~

-

I~:

[i] 0~
~

I~: 0 0*

3 1";1

iu

~
-120

"THE SIGNAL INPUT ('kHz SINEWAVE. 2V p·pllS APPLIED
TO ONE AMPLIFIER AT A·TIME. THE OUTPUTS OF THE OTHER
THREE AMPLIFIERS ARE THEN MEASURED FOR CROSSTALK.

."

-140

Figure 19. Crosstalk Test Circuit

Figure 21a. Unity Gain Follower

1 T03

tI

;: 0~

-130

10

, T02

V~~~

~

1['

~ -110

1 T04

~~

100

~

~

1k
10k
FREQUENCY - Hz

100k

Figure 20. Crosstalk vs. Frequency

Figure 21b. Unity Gain Follower
Large. Signal Pulse Response

Figure 21c. Unity Gain Follower
Small Signal Pulse Response

1.5pF

2kn

ru-

SQUARE
WAVE
INPUT

Figure 22a. Unity Gain Inverter

2-34 OPERATIONAL AMPLIFIERS

Figure 22b. Unity Gain Inverter
Large Signal Pulse Response

Figure 22c. Unity Gain Inverter
Small Signal Pulse Response

REV. A

AD713
MEASURING AD713 SETTLING TIME
The photos of Figures 24 and 2S show the dynamic response of
the AD713 while operating in the settling time test circuit of
Figure 23. The input of the settling time fixture is driven by a
flat-top pulse generator. The error signal output from the false
summing node of AI, the AD713 under test, is clamped, amplified by op amp A2 and then clamped again.
TO TEKTRONIX
1A26
OSCILLOSCOPE
PREAMP
INPUT SEcnON
{VIA LESS THAN
1FT 50.11
COAXIAL CABLEI

r------,

-

I

I

:

~ ,E0PF:

:'Mn~T

:

I

,

L ______ .1

The error signal is thus clamped twice: once to prevent overloading amplifier A2 and then a second time to avoid overloading the oscilloscope preamp. A Tektronix oscilloscope preamp
type 7A26 was carefully chosen because it recovers from the
approximately 0.4 volt overload quickly enough to allow accurate measurement of the AD713's l,...s settling time. Amplifier
A2 is a very high speed FET input op amp; it provides a voltage
gain of 10, amplifying the error signal output of the AD713
under test (providing an overall gain of S).

E~
~
, •....
~

:II2x
HP2835

~

1=,•
ri
~··

II,.

I~~··

II

I
. 11

Il,
-I II

----

-

1=

.. . . : . . .

.
~v

I

I~ nS

NOTE
USE CIRCUIT BOARD
WITH GROUND PLANE

Figure 25. Settling Characteristics to -10V Step. Upper
Trace: Output of AD713 Under Test (5Vldiv). Lower Trace:
Amplified Error Voltage (O.Ol%ldiv)

4.99kU
10kU
·USE VERY
SHORT CABLE

OR TERMINATION
RESISTOR

DATA
DYNAMICS

5109
OR
EQUIVALENT

I

_______ .1

Figure 23. Settling Time Test Circuit

Figure 24. Settling Characteristics 0 to + 10V Step. Upper
Trace: Output of AD713 Under Test (5V/div). Lower Trace:
Amplified Error Voltage (O.Ol%1div)

REV. A

POWER SUPPLY BYPASSING
The power supply connections to the AD713 must maintain a
low impedance to ground over a bandwidth of 4MHz or more.
This is especially important when driving a significant resistive
or capacitive load, since all current delivered to the load comes
from the power supplies. Multiple high quality bypass capacitors
are recommended for each power supply line in any critical
application. A O.I,...F ceramic and a I,...F electrolytic capacitor as
shown in Figure 26 placed as close as possible to the amplifier
(with short lead lengths to power supply common) will assure
adequate high frequency bypassing in most applications. A
minimum bypass capacitance of O.I,...F should be used for any
application.

Figure 26. Recommended Power Supply Bypassing

OPERA TIONAL AMPLIFIERS 2-35

•

AD713
A 10GB SPEEl) INSTRUMENTATION AMPLIFIER
CIRCUIT

A 10GB SPEED FOUR OP AMP CASCADED AMPLIFIER
CIRCUIT

The instrumentation amplifier circuit shown in Figure 27 can
provide a range of gains from unity up to 1000 and higher using
only a single AD713. The circuit bandwidth is 1.2MHz at a gain
of 1 and 250kHz at a gain of 10; .settling time for the entire circuit is less than 5,...s to within 0.01 % for a 10 volt step,
(G = 10). Other uses for amplifier A4 include an active data
guard and an active sense input.

Figure 29 shows how the four amplifiers of the AD713may be
connected in cascade to form a high gain, high bandwidth .
amplifier. This gain of 100 amplifier has a -3dB bandwidth
greater than 600kHz.

o:' +

CIRCUIT GAIN = 2OA

1

·1.6pF ~ 20pF

.

·ITRIM .FOR BElT SEJJUNG TIMEI

SENSE

100kn

TO BUFFERED
VOLTAGE REFERENCE
OR
REMOTE GROUND
SENSE

COM
.....

V

., :1~7~~

-Vs

Figure

27.

FOUR OP·AMP CASCADED AMPliFIER
GAIN'" 100

+Vs:

BANDWIDTH ( - 3dB) = 632kHz

I

I
OPTIONAL Vos I
ADJUSTMENT ...JI
IL ______

Figure 29. A High Speed Four Op Amp Cascaded
Amplifier Circuit
TO SPECTRUM ANALYZER ~

·VOlTRONles 5P20 TRIMMER CAPACITOR
OR EQUIVALENT
··RATIO MATCHED 1% METAL FILM RESISTORS

ERROR SIGNAL
QUTFUT

(ERROR"'1

A High Speed Instrumentation Amplifier Circuit

'kU

. NULL
ADJUST

,aon

10kn

10kU

Table I provides a performance summary for this circuit. The
photo of Figure 28 shows the pulse response of this circuit for a
gain of 10.
'kU

Gain
I

2
10

RG

Bandwidth

NC
20k!l
4.04k!l

l.2MHz
1.0MHz
0.25MHz

T Settle (0.01%)

.Q

l00pF

-V.

Table I. Performance Summary for the High Speed
Instrumentation Amplifier Circuit

Figure 28. The Pulse Response of the High Speed
Instrumentation Amplifier. Gain = 10
2-36 OPERATIONAL AMPLIFIERS

Figure 30. THO Test Circuit
HIGH SPEED OP AMP APPLICATIONS AND
TECHNIQUES
DAC Buffers (I~to-V Converters)
The wide input dynamic range of JFET amplifiers makes them
ideal for use in both waveform reconstruction and digital-audioDAC applications. The AD713, in conjunction with the AD1860
DAC, can achieve 0.0016% THD (here at a 4fs or a 176.4kHz
update rate) without requiring the use of a deglitcher. Just such
a circuit is shown in Figure 31. The 470pF feedback capacitor
used with IC2a, along with op amp IC2b and its associated components, together form a 3·pole low-pass filter. Each or all of
these: poles can be tailored for the desired attenuation and phase
characteristics required for a particular application. In this application, one half of an AD713 serves each channel in a twochannel stereo system.

REV. A

AD713
-v.
MSBTRIM
470kU

DIGITAL
,.t;GND

'OOkU

200kU

-V.

+V.

+VCC

•

~

lOUT

-V.
CLOCK
LATCH
ENABLE
DATA
INPUT

+ Vee

3kn

CONTROL
LOGIC

:t
I,,,F

COM

1=,,,F

-VEE

:1

•

ANALOG
POWER
SUPPLY

-SV

I,,,F

th


a!.

,

.,"~

II:

Z

!:;

0

....
::J

....
::J

>~

0

>

~

i!;

S

::J

0

3;

0

0

10

20

5

0

Figure 1. Input Common-Mode
Range vs. Supply Voltage

------

-

\

1,,\

----

20

o 1:=
10

iiPPT

~~

10k

100
lk
LOAD RESISTANCE - U

Figure 3. Output Voltage Swing vs.
Load Resistance

o

10

15

20

-2
-60 -40 -20

14

E

T~ ~

I

10

/.

~ I'

~

6
-60 -40 -20

?/

~

~

~v

40

C

~35

ffi

60

80

40

60

80

100

120 140

lOOk

"525

100 120 140

"e

Figure 7. Quiescent Current vs.
Temperature

2-48 OPERA TlONAL AMPLIFIERS

1M
FREQUENCY - Hz

100M

10M

Figure 6. Closed-Loop Output
Impedance vs. Frequency,
Gain = +1

52

I I
POSITIVE
CURRENT

30

~

::J

~

40

I-

20

Ir ~

i::l

~

20

-

Figure 5. Input Bias Current vs.
Temperature

....

Vs =±5V

TEMPERATURE -

'--. r-

TEMPERATURE _ °C

Figure 4. Quiescent Current vs.
Supply Voltage

C 12

/

Vs= ±sv

'"""

SUPPLY VOLTAGE ± Volts

8

15

+5VOLT, _

-5

---

~~

10

Figure 2. Output Voltage Swing vs.
Supply Voltage

12

iB

~

SUPPLY VOLTAGE ± Volts

SUPPL Y VOLTAGE ± Yolts

8

j

10

o •
0

1S

~i5Vo~T

SUPPLIES

V

w 15

~ 10

10

/

20

11
~

w

0
:IE
:IE
0

..

~I

~ 15

l!:

il

n

~ 2.

J!!
15

11c
~

30

20

20

V

/

r- ~ ~LIMIT

" ~~

NEGATiVe
CURRENT
LIMIT

~

20

"-60 -40

-20

0

20

40

60

80

AMBIENT TEMPERATURE _

~,
f---

51

150
;a

r--

Z

~

~

"-

100 120 140

"e

Figure 8. Short-Circuit Current Limit
vs. Temperature

•
•

60

40 - 20

20 40
60
TEMPERATURE _ °C

80

100

120 140

Figure 9. Gain Bandwidth vs.
Temperature

REV. 0

100

..

'-

,

-,

+80'

~ .l.vsuPPLES
~
~

+00'

~

\
\

~
~

i

+40"

\

\

\

+2r

~

~

!=

"

10M

10k
lOOk
1M
FREQUENCY - Hz

,,

VS=+l~~

ID

';'70
~

"~6S

,~

~
w

~ 60

if

~

V

so

100M

80I--->"o--1'<:--t---t---+---i

~

Vs =±5V

~60~--+-~~~--t---+--~
z

~~ 4 0 1 - - - + - - - t - " " " c - " " , , - - - + - - - i

!

~201---+---t---+--->"~~.--i

55

I
10

100

10k

lk

FREQUENCY - Hz

LOAD RESISTANCE - U

Figure 10. Open-Loop Gain and
Phase Margin vs. Frequency

10

~

II

75

~

-20
100

100 r-----r---,----r----r---,

\

lkULOAD

;!: 5V SUPPLIES" \
5OOULOAD

.

+lDO"

-

AD827

Figure 12. Power Supply Rejection
Ratio vs. Frequency

Figure 11. Open-Loop Gain vs.
Load Resistance

0r---~

10

30

r-- r----..

5

0
N=·
,5
V
VCM
:: :2:1V p-p

.

'\

>

1\

0

/

g
RL =lkU

o
::!

2

IE

0

/

o

"'"

0

20

5

t'...

"-

0

5

0
10'

"

lOOk
1M
FREQUENCY _ Hz

10M

0
100M

1%

0.1%

1%

0.1%

.........,

'\..

'\

-8

~

-10
100M

I

\ \

5- •

5

0-6

o

20

40

"\..

"-

"--

60
80
100
SETTUNG TIME - ns

120

140

160

Figure 15. Output Swing and Error
vs. Settling Time

Figure 14. Large Signal Frequency
Response

I

3V~S

I:!!

RL ""lldl

~

~ -100

i

./"

0

~

V~

i

i"II il
HAR

c

:z: -120

-130
100

111.

II

10k

100.

FREQUENCY - Hz

Figure 16. Harmonic Distortion vs.
Frequency

REV. 0

1\

40

350

\
\ '-....

~

2NDNARMONte

i§

1-"

'"

V

50

-so
-90

i-

/

V

ERROR

2

INPUT FREQUENCY _ Hz

-70

,

10M

1M

Figure 13. Common-Mode
Rejection Ratio vs. Frequency

,

1\

/

/

30

20

i

~I--r-I--r-t-~~r--+-t-~~

~

i
I

250

~ ~~~-~~-t-.+~~=+-+---+--j

10

lSO

o

10

100

f-+--I-+-f-+-+---+-J...-"J-·--j

1k

10k
lOOk
FREQUENCY - Hz

1M

Figure 17. Input Voltage Noise
Spectral Density

1--:~'""1-+--+-H~-F-+-+---i

10M

TEMPERATURE _

°c

Figure 18. Slew Rate vs.
Temperature
OPERA TIONAL AMPLIFIERS 2-49

•

AD827
I II

-40

VOUT

Ii'

VIN=OdBm

-50

'II

/1

-60

~

r:
~

I.

u

RL~~~ "- ~15V
~L=I'~

-90
-100

J/l I

-110
10k

100k

1M
FREQUENCY - Hz

10M

=

=

RL 500n FOR tV. 5V.1kn FOR ±v" = 15V
USE GROUND PLANE
PINOUT SHOWN IS FOR MINIDIP PACKAGE
100M

Figure 20. Crosstalk Test Circuit

Figure 19. Crosstalk vs. Frequency

INPUT PROTECTION PRECAUTIONS
An input resistor (resistor RIN of Figure 21a) is recommended
in circuits where the input common-mode voltage to the AD827
may exceed (on a transient basis) the positive supply voltage.
This resistor provides protection for the input transistors by limiting the maximum current that can be forced into their bases.

For high performance circuits, it is recommended that a second
resistor (Ra in Figures 21a and 22a) be used to reduce biascurrent errors by matching the impedance at each input. This
resistor reduces the error caused by offset voltages by more than
an order of maguitude.

RB
12511

.v,

Figure 21a. Follower Connection

1kU

Figure 21b. Follower Large Signal
Pulse Response

Figure 21c. Follower Small Signal
Pulse Response

Figure 22b. Inverter Large Signal
Pulse Response

Figure 22c. Inverter Small Signal
Pulse Response

1kU

.v,

rI
OPTJONAL d.
BYPASStNG T

RB
487U

Figure 22a. Inverter Connection

2-50 OPERATIONAL AMPLIFIERS

REV. 0

Applications-AD827
+Ys

A HIGH SPEED 3 OP AMP INSTRUMENTATION
AMPLIFmR CIRCUIT
The instrumentation amplifier circuit shown in Figure 24 can
provide a range of gains. The chart of Table II details
performance.

~N

.vs

TRIM FOR BEST
SETTLINGnME

•

2-BpF

TAIMFOR

OPTIMUM
BANDWIDTH

VOUT

7-15pF

Figure 23. A Video Line Driver

2kU

R,

VIDEO LINE DRIVER
The AD827 functions very well as a low cost, high speed line
driver for either terminated or unterminated cables. Figure 23
shows the AD827 driving a'doubly terminated cable in a follower configuration.
The termination resistor, Rn (when equal to the cable's characteristic impedance) minimizes reflections from the far end of the
cable. While operating from ±S V supplies, the AD827 maintains a typical slew rate of 200 V/",s, which means it can drive a
±I V, 30 MHz signal into a terminated cable.

+v..
CIRCUIT GAIN

NOTE: PINOUT SHOWN IS FOR MINIDIP PACKAGE

Figure 24. A High Bandwidth Three Op Amp Instrumentation Amplifier

Video Line Driver Performance Summary
VIN*

o dB or ±SOO mV Step
o dB or ±SOO mV Step
o dB or ±SOO mV Step
o dB or ±500 mV Step
o dB or ±500 mV Step
o dB or ±SOO mV Step

VSUPPLY
±IS
±15
±15
±5
±5
±S

Cc

-.3 dB Bw

Overshoot

20 pF
15 pF
o pF
20 pF
15 pF
OpF

23 MHz
21 MHz
J3MHz
18 MHz
16 MHz
II MHz

4%
0%
0%
2%
0%
0%

NOTE
* - 3 dB bandwidth numbers are for the 0 dBm signal input. Overshoot numbers are the perceot overshoot of the 1 Volt step input.

= ~o + 1

Small Signal
Bandwidth
@ 1 V p-p Output

Gain

Ro

I
2
10
100

Open
2k
2260
200

16.1 MHz
14.7 MHz
4.9 MHz
660 kHz

Table II. Performance Specifications for the Three Op
Amp Instrumentation Amplifier

Table I. Video Line Driver Performance Chart
A back-termination resistor (RBn also equal to the characteristic
impedance of the cable) may be placed between the AD827 output and the cable input, in order to damp any reflected signals
caused by a mismatch between RT and the cable's characteristic
impedance. This will result in a flatter frequency response,
although this requires that the op amp supply ± 2 V to the output in order to achieve a ± I V swing at resistor RT .

REV. 0

OPERA TIONAL AMPLIFIERS 2-51

AD827
bandwidth. The 1.25 rnA full-scale output current of the AD539
and the 3 kO feedback resistor set the full-scale output voltage
of each multiplier at 3.25 V p-p.

A TWO-CHIP VOLTAGE-CONTROLLEO AMPLIFIER
.
(VCA) WITH EXPONENTIAL RESPONSE
Voltage-controlled amplifiers are often used as. building blocks
in automatic gain control systems. Figure 25 shows a two-chip
VCA built using the A0827 and the AD539, a dual, currentoutput multiplier. As configured, the circuit has its two multipliers connected in series. They could also be placed in parallel
with an increase in bandwidth and a reduction in gain. The gain
of the circuit is controlled by Vx, which can range from 0 to
3 V dc. Measurements show that this circuit easily supplies 2 V
p-p into a 100 0 load while operating from ±5 V supplies. The
overall bandwidth of the circuit is approximately 7 MHz with
0.5 dB of peaking.

Current limiting in the AD827 (typically 30 mA) limits the output voltage in this application to about 3 V p-p across a 100 0
load. Driving a 50 0 reverse-terminated load divides this value
by two, liiniting the maximum signal delivered to a 50 0 load to
about 1.5 V p-p, which suffices for video signalleve1s. The dynamic range of this circuit is approximately 55 dB and is primarily limited by feedthrough at low input levels and by the maximum output voltage at high levels.
Guidelines for Grounding and Bypassing
When designing practical high frequency circuits using the
AD827, some special precautions are in order. Both short interconnection leads and a large ground plane are needed whenever
possible to provide low resistance, low inductance circuit paths.
One should remember to minimize the effects of capacitive coupling between circuits. Furthermore, IC sockets should be
avoided. Feedback resistors should be of a low enough value
that the time constant formed with stray circuit capacitances at
the amplifier summing junction will not limit circuit performance. As a rule of thumb, use feedback resistor values that are
less than 5 kO. If a larger resistor value is necessary, a small
«10 pF) feedback capacitor in parallel with the feedback resistor may be used. The use of 0.1 ILF ceramic disc capacitors is
recommended for bypassing the op amp's power supply leads~

Each half of the AD827 serves as an IN converter and converts
the output eurtent of one of the two multipliers in the AD539
into an output voltage. Each of the AD539's two multipliers
contains two internal 6 kO feedback resistors; one is connected
between the CHI output and ZI, the other between the CHI
output and WI. Likewise, in the CH2 multiplier, one of the
feedback resistors is connected between CH2 and Z2 and the
other is connected between CH2 and Z2. In Figure 25, ZI and
WI are tied together, as are Z2 and W2, providing Ii 3 kO feedback resistor for the op amp. The 2 pF capacitors connected
between the AD539's WI and CHI and W2 and CH2 pins are
in parallel with the feedback resistors and thus reduce peaking
in the VCA's frequency response. Increasing the values of C3
and C4 can further reduce the peaking at the expense of reduced
INPUT RANGE:
10MV TO 3V (55dB) ,..-_ _ _ _.,

AD539
Vx

r--l

1 CONTROL
2 HF COMP

VO.II1~F 3 CH 1
+5V

4.70

4 IN

.-AMr-!:;;-:;:::;;1 +Vs
4.70 ..... O.1~F
...f-AM,.....v~45 -Vs
O.1~F ~ 6 CH2

-5V

IN

7 INPUT
COM
8 OUTPUT
COM
·PINOUT SHOWN IS FOR MINI·DIP PACKAGE

VouTAT TERMINATION RESISTOR,

~

VX2 VIN

= av;-

V'V
VOUT AT PIN & OF AD827 = ~
4V'

Figure 25. A Wide Range Voltage-Controlled Amplifier Circuit

2-52 OPERA TIONAL AMPLIFIERS

REV. 0

1IIIIIIII ANALOG

WDEVICES

High Speed, Low Noise Video Op Amp
AD829 I

FEATURES
High Speed
120 MHz Bandwidth. Gain = -1
230 V/".s Slew Rate
90 ns Settling Time to 0.1%
Ideal for Video Applications
0.02% Differential Gain
0.040 Differential Phase
Low Noise
2 nV/YHz Input Voltage Noise
1.5 pA/YHz Input Current Noise
Excellent DC Precision
1 mV max Input Offset Voltage (Over Temp)
0.3 ".v/oe Input Offset Drift
Flexible Operation
Specified for :t:5 V to :t:15 V Operation
:t:3 V Output Swing into a 150 n Load
External Compensation for Gains 1 to 20
5 mA Supply Current
PRODUCT DESCRIPTION
The AD829 is a low noise (2 nV/y'Hz), high speed op amp with
custom compensation that provides the user with gains from ± 1
to :t:20 while maintaining a bandwidth greater than 50 MHz.
The AD829's 0.040 differential phase and 0.02% differential gain
performance at 3.58 MHz and 4.43 MHz, driving reverseterminated 50 n or 75 n cables, makes it ideally suited for professional video applications. The AD829 achieves its 230 V/!,-s
uncompensated slew rate and 750 MHz gain bandwidth product
while requiring only 5 mA of current from the power supplies.
The AD829's external compensation pin gives it exceptional versatility. For example, compensation can be selected to optimize
the bandwidth for a given load and power supply voltage. As a
gain-of-two line driver, the - 3 dB bandwidth can be increased
to 95 MHz at the expense of 1 dB of peaking. In addition, the
AD829's output can also be clamped at its external compensation pin.
The AD829 has excellent dc performance. It offers a minimum
open-loop gain of 30 V/mV into loads as low as 500 n, low input voltage noise of 2 nV/y'Hz, and a low input offset voltage
of 1 m V maximum. Common-mode rejection and power supply
rejection ratios are both 120 dB.
The AD829 is also useful in multichannel, high speed data conversion where its fast (90 ns to 0.1 %) settling time is of importance. In such applications, the AD829 serves as an input buffer
for 8-to-1O-bit AID converters and as an output IIV converter
for high speed DIA converters.

REV. 0

CONNECTION DIAGRAM
8-Pin Plastic Mini-DIP (N),
Cerdip (Q) and SOIC (R) Packages
OFFSET

OFFSET

NULL

NULL

-IN

+vs

+IN

OUTPUT

CCOMP

The AD829 provides many of the same advantages that a transimpedance amplifier offers, while operating as a traditional voltage feedback amplifier. A bandwidth greater than 50 MHz can
be maintained for a range of gains by changing the external
compensation capacitor. The AD829 and the transimpedance
amplifier are both unity gain stable and provide similar voltage
noise performance (2 nV/y'Hz). However, the current noise of
the AD829 (1.5 pNy'Hz) is less than 10% of the noise of transimpedance amps. Furthermore, the inputs of the AD829 are
symmetrical.
PRODUCT HIGHUGHTS
1. Input voltage noise of 2 nV/y'Hz, current noise of 1.5
pNy'Hz and 50 MHz bandwidth, for gains of I to 20, make
the AD829 an ideal preamp.
2. Differential phase error of 0.04 and a 0.02% differential gain
error, at the 3.58 MHz NTSC and 4.43 MHz PAL and
SECAM color subcarrier frequencies, make it an outstanding
video performer for driving reverse-terminated 50 n and
75 n cables to ± 1 V (at their terminated end).
0

3. The AD829 can drive heavy capacitive loads.
4. Performance is fully specified for operation from ± 5 V to
± 15 V supplies.
5. Available in plastic, cerdip, and small outline packages.
Chips and MIL-STD-883B parts are also available.

OPERA TlONAL AMPLIFIERS 2-53

AD829 -SPECIFICATIONS
Model

(@ TA

Conditions

INPUT OFFSET VOLTAGE

= +25°C and Vs = ±15 V dc, unless otherwise noted)
Vs

Min

AD829J
Typ

±S V, ±IS, V

0.2

±SV,±ISV

0.3

±SV,±ISV

3.3

Tmin to T"""
Offset Voltage Drift
INPUT BIAS CURRENT

T min to·Tmax
INPUT OFFSET CURRENT

±SV, ±ISV

50

±S V, ±IS V

0.5

Tmin to Tmax
Offset Current Drift
OPEN-LOOP GAIN

Vo=±2.5V
RLOAD = 500 n

30
20

Full Power Bandwidth 2

Vo=2Vp-p
RLOAD = 500 n
Vo = 20 V p-p
R LOAD = 1 kn
RLOAD = 500 n
R LOAD = I kn
Av = -19
-2.5 V to +2.5 V
10 V Step
CLOAD = 10 pF
RLOAD = I kn

Slew Rate2
Settling Time to 0.1%

Phase Margin2

0.5
0.5

0.3
7
8.2

3.3

500
500

50
0.5

7
9.5
500
500

Units
mV
mV
,.VI"C
,.A

!LA
nA
nA
nAl"C

65

30
20

65
40

V/mV
V/mV
V/mV

85

85

V/mV
V/mV
V/mV

±S V
±ISV

600
750

600
750

MHz
MHz

±SV

25

25

MHz

±ISV
±S V
±ISV

3.6
150
230

3.6
ISO
230

V/,.s
V/,.s

±SV
±IS V
±IS V

65
90

65
90

ns
ns

60

60

Degrees

0.02

0.02

%

50
20

DIFFERENTIAL GAIN ERROR'

RLOAD

= lOon
CcOMP = 30 pF

±IS V

DIFFERENTIAL PHASE ERROR'

R LOAD = loon
CcoMi = 30 pF

±IS V

COMMON-MODE REJECTION

VCM = ±2.S V
VCM = ±12 V

±SV
±IS V

POWER SUPPLY REJECTION

Vs = ±4.5 V to ± 18 V
T min to ~max

T~n to

0.1

40

RLOAD = 500 n

l•

I
I

AD829A1S
Typ
Max

±IS V

Tmin to Tmax
DYNAMIC PERFORMANCE
Gain Bandwidth Product

Min

±SV

Tmio to Tmax
RLOAD = 150 n
V6UT = ±IOV
RLOAD = 1 kn

Max

100

50
20

MHz

0.04

Degrees

100
100
96

120
120

100
100
96

120
120

dB
dB
dB

98
94

120

98
94

120

dB
dB

0.04

Tmax

100

INPUT VOLTAGE NOISE

f= I kHz

±IS V

2

2

nV/YHz

INPUT CURRENT NOISE

f= 1kHz

±IS V

I.S

1.5

pAlyHZ

±SV

+4.3
-3.8
+14.3
-13.8

+4.3
-3.8
+14.3
-13.8

V
V
V
V

3.6
3.0
1.4
13.3
12.2
32

±V
±V
±V
±V
±V
mA

13
S
1.5

13
S
I.S

kn
pF
pF

2

2

Mn

INPUT COMMON-MODE
VOLTAGE RANGE

±ISV
OUTPUT VOLTAGE SWING

RLOAD
RLOAD
RLOAD
RLOAD
RLOAD

- soon
= Ison
= son
=1 kO
= soo n

Short Circuit Current
INPUT CHARACTERISTICS
Input Resistance (Differential)
Input Capacitance (Differential)'
Input Capacitance (Common Mode)
CLOSED-LOOP OUTPUT
RESISTANCE

2-54 OPERA TIONAL AMPLIFIERS

Av = + I, f = I kHz

SV
SV
SV
IS V
ISV
SV, ±ISV

3.0

2.S
12
10

3.6
3.0
1.4
13.3
12.2
32

3.0

2.S
12
10

REV. 0

AD829
Conditions

Model

Min

Vs

POWER SUPPLY
Operating Range
Quiescent Current

AD829J
Typ

±4.5
±5 V

5

±15 V

5.3

T min to Tmalt

T min to Tmax
TRANSISTOR COUNT

Max

Min

±18
6.5
8.0
6.8
8.3

±4.5
5
5.3

46

Number of Transistors

AD829 AJS
Typ
Max
±18
6.5
8.218.7
6.8
8.5/9.0

Units
V
rnA
rnA
rnA
rnA

46

NOTES
'Full Power Bandwidth = Slew Ratel2 "VPEAK '
2Tested at Gain = + 20, CCOMP = 0 pF.
'3.58 MHz (NTSC) and 4.43 MHz (PAL & SECAM).
4Differential input capacitance consists of 1.S pF package capacitance plus 3.5 pF from the input differential pair.
Specifications subject [0 change without notice.

ABSOLUTE MAXIMUM RATINGS'
Supply Voltage . . . . . . . . . . . . . . . . .
. .. ±18V
Internal Power Dissipation2
Plastic (N) ....
. . 1.3 Watts
Small Outline (R) . . . . .
. . 0.9 Watts
Cerdip (Q) . . . . . . . . . .
. . 1.3 Watts
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±Vs
Differential Input Voltage' . . . . . . . . . . . . . . . . . . ±6 Volts
Output Short Circuit Duration . . . . . . . . . . . . . . . Indefinite
-65°C to + 150°C
Storage Temperature Range Q . . . . . .
Storage Temperature Range N, R . . . . . . . . -65°C to + l25'C
Operating Temperature Range
AD829J . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to + 70°C
AD829A . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
AD829S . . . . . . . . . . . . . . . . . . . . . . . -SSOC to + 125°C
Lead Temperature Range (Soldering 60 sec) ....... + 300°C

II

METALIZATION PHOTO
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
NULL
1

NULL
8

-IN

2

+IN
3

NOTES
IStresses above those listed under "Absolute Maximum Ratings" may cause
pennanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational section of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
2Maximum internal power dissipation is specified so that T J does not exceed
+ 175°C at an ambient temperature of + 25°C.
Thermal characteristics:
8-pin plastic package: alA = lOO'C/watt (derate at 8.7 mW/'C)
8-pin cerdip package: alA = llO'C/watt (derate at 8.7 mW/,C)
8-pin small outline package: alA = 155'C/watt (derate at 6 mW/,C).
3If the differential voltage exceeds 6 volts, external series protection resistors
should be added to limit the input current.

I"

SUBSTRATE CONNECTED
TO +Vs

ORDERING GUIDE
Model
AD829JN
AD829JR'
AD829AQ
AD829SQ
AD829SQ/883B

Temperature
Range

Package
Description

Package
Options l • 2

o to
o to

8-Pin
8-Pin
8-Pin
8-Pin
8-Pin

N-8
R-8
Q-8
Q-8
Q-8

+70°C
+70°C
-40°C to +85°C
-55°C to + 125°C
- 55°C to + 125°C

Plastic Mini-DIP
Plastic SOIC
Cerdip
Cerdip
Cerdip

NOTES
'N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOlC). For outline information
see Package Information section.
'J grade chips also available.
'Available in tape and reel packaging.

REV. 0

OPERA TIONAL AMPLIFIERS 2-55

AD829 - Typical Performance Characteristics
2O..-----,.--"'T""---r----,

2O"---~--"'T""--r---'

30

I I II

.....±15'VOL~ I
SUPPLIES

I

J

J

oL-_~

°0~----~----~1~0----~1~5----~2'0

'1I
!i:

5.5

II:
II:

~~

-

5.0

!i:w

..
...

-

!i:

M
5 4.5

100

~

:::>

U

:!i

r--.. ........

Figure 3. Output Voltage Swing vs.
Resistive Load

100

r----r---,----,---~--~

10

\---t---\--+--7''-tT--\

-3

0.1

\---t-r-\T-+---+---\

0.01

\---+:,.--\--+---+---\

Vs = ±5V, ±15V

I'--.
a.

g

a.
i!:

a

10k

lk

-4

II:
II:

!;

±SVOLT

ItUPtLli,

LOAD RESISTANCE - Ohmo

-5

w
U

o

~_~

Figure 2. Output Voltage Swing vs.
Supply Voltage

8.0

:::>

__

SUPPLY VOLTAGE - ±Vo""

Figure 1. Input Common-Mode
Range vs. Supply Voltage

I

~

10

SUPPLY VOLTAGE - ±Vo""

1

__

o

""

:.- _r-

..
c

4.0

-2

o

10

20

15

-60 -40 -20 0

SUPPLY VOLTAGE - ±von.

Figure 4. Quiescent Current vs.
Supply Voltage

VS =±15V

I'II~
~

~~

~

~

?

~~

20 40

60 80 100 120 140

~

10k

TEMPERATURE - ·C

;..-

~ IT

Vs=±5V

40

"
I

t:

35

~

~

11

30 -

II:

~

~~
iT '~

POSITIVE
CURRENT LIMIT

:::>

25

Ii!
u
Ii:0

20

:::>

..

10M

100M

65

NE~ATI~E

I
CURRENT LIMIT

~I

I

U

t:

1M

Figure 6. Closed-Loop Output Impedance vs. Frequency

Figure 5. Input Bias Current vs.
Temperature

E

lOOk

FREQUENCY - Hz

Vs=±5V

~

,

if
::E

vL!J
Av =.20
C coup =OpF

60

I

:z:

"

I'

..."~...
z

..
I

55

-

I-"

50

:z:

3
-60 -40 -20 0

20 40 60 80 100 120140

TEMPERATURE _·C

Figure 7. Quiescent Current vs.
Temperature

2-56 OPERA T10NAL AMPLIFIERS

15
-60 -40 -20 0

45
20 40 60 80 100 120 140

AMBIENT TEMPERATURE - ·C

Figure 8. Short Circuit Current
Limit vs. Temperature

-60 -40 -20

0

20 40

60 80 100 120 140

TEMPERATURE - ·C

Figure 9. -3 dB Bandwidth vs.
Temperature

REV. 0

AD829

...

120

"--"--T"""""'""T'"-""T'"-.,.-....,

100

1=:::j::::::::~I-I~

ID

~

i

40

...

+40

~

~

E1

CJ

8

~--lI ~

1---+--+--+--+.......

o

r--Js~1l5vl ~.

-

95

;;

__- k__

lk

10k

~

__

lOOk

~

1M

go

i5a.

+20

__

o

75
10

100M

rr
rr
60

.

~ 20
I

~

lOOk

10k

1M

FREQUENCY - Hz

'"

10M

I;;

100M

I

-100

11

RL =2kO

~

-

30k

lOOk

Figure 16. Total Harmonic Distortion (THO) vs. Frequency

-2

I;;
a.
I;;

-4

1%

0.1%

1%

0.1%

o

~ ~
20

I-

40

60

80

100 120 140 160

Figure 15. Output Swing & Error vs.
Settling Time

~ t------i~----t-____t_---t-----1
~

40

CCOMP=30pF

I

~

t-t--

SETTLING nME - ns

Av=-l

-30

!g -

r--

1\

-8

100

,

_\ ..1

-6
-10

ERROR AV=-19
CCOMP =OpF

,----,-----,-----r----..

-SO I---+---+~~~~--i

4

~

3 ..
I\\---t-----t---,t---t----t---l

~

2\--~+-_+-+--+--+---1

~

1\

!:;

g
~

.,

_~L-

10k

3:


-

Y'N = 2.24V RMS

=100pF

II 1

INPUT FREOUENCY - MHz

)

-go

-110
100

I

10

- 20

I---- t-- CCOMP= 30pF

In

~

I I

V,N =3VRMS
Ay =-l
CLOAO

...

Figure 12. Power Supply Rejection
Ratio (PSRR) vs. Frequency

g
V.=±15V
RL =lkn
A y =+2O

CC';"P =ripF

0

-70

- 80

t- V.=±5V

0
R L = SOOO
> 10
t- Ay= +20 I;;
a.

Figure 13. Common-Mode Rejection Ratio vs. Frequency

I--- t--

15

!:;

"\

I I

lk

10k

~

"\

=

CCOMP = OpF

20

lk

10

I..

"\

I

•

40

100

a. 25 i--

BO

I--

60

30

,~

'\
40

~

Figure 11. Open-Loop Gain vs.
Resistive Load

100

~

BO

I

LOAD RESISTANCE - 0

Figure 10. Open-Loop Gain & Phase
Margin vs. Frequency

ill

ID

rr
rr

II

FREOUENCY - Hz

120

...

85

L-~

10M

-

100

\~~
,
Vs=i5V -

80

100

I'
i--"

-i

20
0L-~

120

III

100
ID

80

~D.60

105

+100

o

__

~

____- k____-L__

500k

1M

~

105M

FREQUENCY - Hz

Figure 17. 2nd & 3rd Harmonic
Distortion vs. Frequency

2M

It---t---t---t---t---T---i

0'-_'--_'--_'--_'--_'----'
10

100

lk

10k

lOOk

1M

10M

FREQUENCY - Hz

Figure 18. Input Voltage Noise
Spectral Density

OPERA TIONAL AMPLIFIERS 2-57

AD829
400

0.03

350

I

" r--

~300

.
'"
0

> 250

I

OIFFC)AIN

I

"'....

"
0:

...

~

200

~

.o

~ 150

0:

~


....
'"

5Do
50

±1SV:~

-32

I-r-

,

\\
\

I-- V,N = -38

20dBM
RL=Ik.Q
RF=Ik.Q
GAIN=-1
c eCIIP = 4pF

-

\

\

-44

2k.Q
10

100

FREQUENCY - MHz

Figure 35. Closed-Loop Frequency Response vs. Supply
for the Inverting Amplifier Using Current Feedback
Compensation

A Low Error Video Line Driver
The buffer circuit shown in Figure 37 will drive a backterminated 75 n video line to standard video levels (1 V p-p)
with 0.1 dB gain flatness to 30 MHz with only 0.04° and 0.02%
differential phase and gain at the 4.43 MHz PAL color subcarrier frequency. This level of performance, which meets the
requirements for high definition video displays and test equipment, is achieved using only 5 rnA quiescent current.

Figure 36. Noninverting Amplifier Connection Using
Current Feedback Compensation

7511

7511
COAX
CABLE

OPTIONAL

2-7pF
FLATNESS
TRIM

Figure 37. A Video Line Driver with a Flatness over
Frequency Adjustment

REV. 0

OPERA TIONAL AMPLIFIERS 2-63

•

2-64 OPERA TIONAL AMPLIFIERS

r.ANALOG
WDEVICES
FEATURES
Wideband AC Performance
Gain Bandwidth Product: 400 MHz (Gain 2: 10)
Fast Settling: 100 ns to 0.01% for a 10 V Step
Slew Rate: 400 V/",s
Stable at Gains of 10 or Greater
Full Power Bandwidth: 6.4 MHz for 20 V p-p into a
5000 Load
Precision DC Performance
Input Offset Voltage: 0.3 mV max
Input Offset Drift: 3
typ
Input Voltage Noise: 4 nV/VHz
Open-Loop Gain: 130 VlmV into a 1 kO Load
Output Current: 50 mA min
Supply Current: 12 mA max

",vrc

APPLICATIONS
Video and Pulse Amplifiers
DAC and ADC Buffers
Line Drivers
Available in 14-Pin Plastic DIP, Hermetic Cerdip
and 20-Pin LCC Packages and in Chip Form
MIL-STD-883B Processing Available
PRODUCT DESCRIPTION
The AD840 is a member of the Analog Devices' family of wide
bandwidth operational amplifiers. This high speedlhigh precision
family includes, among others, the AD841, which is unity-gain
stable, and the AD842, which is stable at a gain of two or
greater and has 100 rnA minimum output current drive. These
devices are fabricated using Analog Devices' junction isolated
complementary bipolar (CB) process. This process permits a
combination of dc precision and wideband ac performance previously unobtainable in a monolithic op amp. In addition to its
400 MHz gain bandwidth product, the AD840 offers extremely
fast settling characteristics, typically settling to within 0.01 % of
final value in 100 ns for a 10 volt step.
The AD840 remains stable over its full operating temperature
range at closed-loop gains of 10 or greater. It also offers a low
quiescent current of 12 rnA maximum, a minimum output current drive capability of 50 rnA, a low input voltage noise of
4 nV/VHz and a low input offset voltage of 0.3 mV maximum
(AD840K).
The 400 V/fJ-S slew rate of the AD840, along with its 400 MHz
gain bandwidth, ensures excellent performance in video and
pulse amplifier applications. This amplifier is ideally suited for
use in high frequency signal conditioning circuits and wide
bandwidth active filters. The extremely rapid settling time of

REV. A

Wideband,
Fast Settling Op Amp
AD840 I
CONNECTION DIAGRAMS

•

LCC (E) Package

Plastic DIP (N) Package
and
Cerdip (Q) Package

g

::l

"

z

z

~

!i

0

3

2

u

,

Z

~

2.

!i

'9

NC 4

18 NC

-IN 5

17 +Vs

NC.

16 Ne

+IN 7

1S OUTPUT
14 NC

NC B

~

f

~ ~ ~

NC == NO CONNECT

the AD840 makes it the preferred choice for data acquisition
applications which require 12-bit accuracy. The AD840 is also
appropriate for other applications such as high speed DAC and
ADC buffer amplifiers and other wide bandwidth circuitry.
APPLICATION HIGHLIGHTS
I. The high slew rate and fast settling time of the AD840 make
it ideal for DAC and ADC buffers, line drivers and all types
of video instrumentation circuitry.
2. The AD840 is truly a precision amplifier. It offers 12-bit
accuracy to 0.01 % or better and wide bandwidth, performance previously available only in hybrids.
3. The AD840's thermally balanced layout and the high speed
of the CB process allow the AD840 to settle to 0.0 I % in
100 ns without the long "tails" that occur with other fast op
amps.
4. Laser wafer trimming reduces the input offset voltage to
0.3 mV max on the K grade, thus eliminating the need for
external offset nulling in many applications. Offset null pins
are provided for additional versatility.
5. Full differential inputs provide outstanding performance in
all standard high frequency op amp applications where circuit
gain will be 10 or greater.
6. The AD840 is an enhanced replacement for the HA2540.

OPERATIONAL AMPLIFIERS 2-65

AD840-SPECIFICATIONS

(@ +25°C and ±15 V dc, unless otherwise noted)

Model
Conditions

Min

INPUT OFFSET VOLTAGE'

AD840J
Typ
Max
0.2

0.1

3.5

S
10

3.5

5
6

0.1

0.4
0.5

0.1

0.2
0.3

5

INPUT BIAS CURRENT
Tmm-Tmax
INPUT OFFSET CURRENT
Tmm - Tmax
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance

INPUT VOLTAGE NOISE
Wideband Noise

f=lkHz
10 Hz to 10 MHz

OPEN LOOP GAIN

Vo = ±lOV
RLOAD = 1 kG

T min ..... Tmax

T min - Truax
RLOAD = 500 {}
T min - Tmax
RLOAD

T min

FREQUENCY RESPONSE
Gain Bandwidth Product
Full Power Bandwidth'
Rise Time
Overshoot'
Slew Rate'
Settling Time' -10 V Step

0.3
0.7

AD840S
Typ
Max

Units

1
2

mV
mV
fJ-VI"C

3.5

S
12

0.1

0.4
0.6

JJ.A
JJ.A
JJ.A
JJ.A

0.2

3

30
2

VCM = ±10V

Current
Output Resistance

Min

5

Differential Mode

INPUT VOLTAGE RANGE
Common Mode
Common-Mode Rejection

OUTPUT CHARACTERISTICS
Voltage

AD840K
Typ
Max

1
1.5

Tmin - Tmax
Offset Drift

Min

-

2:

±10
90
85

30
2

12
110

±10
106
90

4
10
100
50
75
SO

12
1lS

±IO
90
85

4
10

130
80

100
75
100
75

130
100

100
50
75
SO

30
2

kG
pF

12
110

V
dB
dB

4
10

nV/y'Hz
fJ-Vrms

130
80

V/mV
V/mV
V/mV
V/mV

500 {}

Tmax

VOUT = ±lOV
Open Loop
VOUT = 90 mV p-p
Av = -10
Vo = 20Vp-p
RLOAD 2: 500 {}
Av = -10
Av = -10
Av = -10
Av = -10
toO.l%
to 0.01%

±10
50

5.5

350

±10
50

V

±10
50

rnA

15

IS

15

G

400

400

400

MHz

6.4
10
20
400

MHz
ns
%
VlfJ-s

6.4
10
20
400

5.5

350

6.4
10
20
400

5.5

350

80
100

80
100

80
100

ns
ns

+ Overdrive

190
350

190
350

190
350

ns'
ns

DIFFERENTIAL GAIN

f = 4.4 MHz

0.025

0.025

0.025

%

DIFFERENTIAL PHASE

f = 4.4 MHz

0.04

0.04

0.04

Degree

OVERDRIVE RECOVERY

-Overdrive

POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current

±15
±5
10.5

T min
Power Supply Rejection Ratio

-

Tmax

Vs= ±5Vto±18V

T min

-

Tmax

TEMPERATURE RANGE
Rated Performance4
TRANSISTOR COUNT

90
80

100

0

# of Transistors

2-66 OPERA TIONAL AMPLIFIERS

±15
±lS
12
14

10.5
94
86

+75

72

±5

±15
±lS
12
14

+75

72

10.5
90
80

100

0

±5

±lS
12
16

100

-55

V
V

rnA
rnA
dB
dB

+125

°C

72

REV. A

AD840
NOTES
IInput offset voltage specifications are guaranteed after 5 minutes at TA := +2S oC.
2Full power bandwidth = slew rate!21T VPEAK '
'Refer to Figures ZZ and Z3.
""S" grade Tmin-Tmax specifications are tested with automatic test equipment at TA = -55°C and TA = +12S oC.
All min and, max specifications are guaranteed. Specifications shown in boldface are tested on all production units.
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS'
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation 2
Plastic (N) . . . . . . . . . . .
1.5 W
Cerdip (Q) . . . . . . . .
I.3W
LCC(E) . . . . . . . . . . . .
1.0 W
Input Voltage . . . . . . . . . .
. . . . . . . . . . . ±Vs
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . ± 6 V
Storage Temperature Range
Q, E . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to + 150°C
N . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to + 125°C
Junction Temperature (TJ ) • . . • • • • • • • • • . • . .
+ 175°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . + 300°C

•

Plastic DIP (N) Package
and
Cerdip (Q) Package

NOTES
IStresses above those listed under "Absolute Maximum Ratings" may cause

permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated
in the operational section of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
2Maximum internal power dissipation is specified so that Tl does not exceed
+ 175°C at an ambient t.:mperature of + 25°C.
Thermal Characteristics:
B
9lA
Derate at
Cerdip Package 30°CIW lWOCIW 8.7 mW/oC
Plastic Package 30°CIW 100°CIW 10 mWrC
LCC Package
3S oCIW ISO°CIW 6.7 mWrC

LCC (E) Package
::I

"z

,C

~

~O

1

20 19

!i

NC 4

Recommended Heat Sink:
Aavid Engineering

10

~
o

/

•

V

o
10
15
SUPPLY VOLTAGE_ ±Volts

10

20

100
lk
LOAD RESISTANCE - H

Figure 2. Output Voltage Swing
vs. Supply Voltage

0

-

10k

Figure 3. Output Voltage Swing
vs. Load Resistance

f

1/

I'

!

,

'\

8

ffi

~

15V SUPPLIES

wI 5

100

E

o

/

, 20

12

.,

5

!

~

6

5
10
15
SUPPLY VOLTAGE - :': Volts

0

§

!;

e:

t2

/.

15

>

V"
~

o
o

0

~

I

1\r'\.

6

" --

/

~ o.

o

10
15
SUPPLY VOLTAGE _ :rVolts

20

3
-60 -40

/

0
20
40
60
TEMPERATURE - "C

80

100 120 140

/
/

0

/

1

0

V

tOOk

.
0

7/
40

80

80

100 1211 140

TEMPERATURE - "c

Figure 7. Quiescent Current vs.
Temperature

2-68 QPERA TlQNAL AMPLIFIERS

1M

10M

h

~hUTP'uT CURRENT
5

~

CUR~ENT ~

0

" "'"

• / 1/

~~

-60 -40 -20 0
20
40
60
80 100
AMBIENT TEMPERATURE - gc

100M

Figure 6. Output Impedance vs.
Frequency

1\

/
20

''""

- OUTPUT

/

,/

-60 -40 -20

10k

45 0

0"0

I'

0.0 1

FREQUENCY - Hz

140

14

1/

1

Figure 5. Input Bias Current vs.
Temperature

Figure 4. Quiescent Current vs.
Supply Voltage

15

-20

/

1

f".. ........

4

/

0

120 140

Figure 8. Short-Circuit Current
Limit vs. Temperature

3'-60
•

/

-40 -20

V

/

I

/ \

~

Av = 10

20 40
60 80
TEMPERATURE - "C

100 120 140

Figure 9. Gain Bandwidth Product
vs. Temperature

REV. A

AD840
20

'00

,

+'00

t-- 1'-." -- -- --.

"

\

\

"I'-."

0

40

+60

\

\
\
+'0

\

'" "

\
+20

"" LOT

0
'00

10k

1k

tOOk

1M

~

E,
~
:Ii
:E
III

95

-20
100M

~

90

o

.

10

..

2.

15

Figure 1,. Open-Loop Gain vs.
Supply Voltage

IIII I
=

!\

,

Rt :: lkH
+ 25°C
\V s =±15V

\

1M

~

-,.

100M

-130
'00

~

~~

HARMON''i/

17

40

.'"

50

~
.......

~

I'-.....

60
70
80
SETTLING TIME - ns

90

I-

V

vI--'

3RDHARMONIC

'00

6

t-1\\HfttH--+tt+-+-I-tfjf-+++t+-H++l+++-H

~ 5~-kH++-H+~-H~~~f-+-H~}4+H

1/

V-

1k

V
,/

45 0

~

i/

i

1000

Figure 16. Harmonic Distortion vs.
Frequency

1

/

~400
~

/

-. 350

300

I

FREQUENCY - Hz

REV. A

\

5 ••

lNl

-11 0

-120

•.• ,%

I:!! 1 H-H+l--f-++It+Hl-I+++H--f-+++l--H+H

I

_9 0

-100

~

V

100

'10

Figure 15. Output Swing and
Error vs. Settling Time

I
3VRMS
Rl = lkU

~

~

./

V

...

., -so
-=

0.1%

'\

30

Figure 14. Large Signal Frequency
Response

-1 0

I

0.01%

FREQUENCY·· Hz

Figure 13. Common-Mode
Rejection vs. Frequency

Z

0.1%

•

'OM

100M

•

7

-B

'OM

100M

0

i

FREQUENCY - Hz

10M

;/

/

r-..

,

0

1M

. / ......

/

0

r-..

100k

tOOk

Figure 12. Power Supply Rejection
vs. Frequency

"1\

Vs == ±1SV

I

1\

FREQUENCY - Hz

7

'\

10k

10k

1k

,.

V CM
1V pop
~25'C

I

"

•
•,

SUPPLY VOLTAGE - ':!:.V

0

1k

it

iil.•

lklllOAD

30

"

- SUPPLY

~

.. 2

'20

"

+SUPPLV

rJ

il!60

/

.

Figure 10. Open-Loop Gain and
Phase Margin Phase vs. Frequency

20

~

(

'00

FREQUENCY - Hz

'00

•

Z B

"

10M

,

0

!Ii,

'0'

iE

",:

20

,.

+BO

\

I'\..

0

'20

"0

.;

vI"

/

V

l/

2.0

'0

'00

'0

10k

100k

1M

'OM

FREQUENCY - Hz

Figure 17. Input Voltage Noise
Spectral Density

-60 -40 -20

20
40
60
TEMPERATURE - "C

10

100

120 140

Figure 18. Slew Rate vs.
Temperature

OPERATIONAL AMPLIFIERS 2-69

AD840
R, = 4.99kll

RIN

=

HP3314A
49911
FUNCTION
GENERATOR ~""'1111\..--<~
OR
EaUIVALENT
49.9!!

Figure 19a. Inverting Amplifier
Configuration (DIP Pinout)

R,=110U

Figure 19b. Inverter Large Signal
Pulse Response

Figure 19c. Inverter Small Signal
Pulse Response
.

Figure 20b. Noninverting Large
Signal Pulse Response

Figure 20c. Noninverting Small
Signal Pulse Response

RF = 1kn

HP3314A
FUNCTION
GENERATOR ~......-'V'w--{
OR
EaUIVALENT

Figure 20a. Noninverting Amplifier
Configuration (DIP Pinout)

OFFSET NULLING
The input offset voltage of the AD840 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 21 ~n be used.

Figure 21. Offset Nulling (DIP Pinout)

2-70 OPERATIONAL AMPLIFIERS

REV. A

Applying the AD840
AD840 SETTLING TIME
Figures 22 and 24 show the settling performance of the AD840
in the test circuit shown in Figure 23.
Settling time is defined as:
The interval of time from the application of an ideal step
function input until the closed-loop amplifier output has
entered and remains within a specified error band.
This defmition encompasses the major components which comprise settling time. They include (1) propagation delay through
the amplifier; (2) slewing time to approach the fmal output
value; (3) the time of recovery from the overload associated with
slewing; and (4) linear settling to within the specified error
band.
Expressed in these terms, the measurement of settling time is
obviously a challenge and needs to be done accurately to assure
the user that the amplifier is worth consideration for the
application.

OUTPUT:
5V/DiV

Figure 24 shows the "long-term" stability of the settling characteristics of the AD840 output after a 10 V step. There is no evidence of settling tails after the initial transient recovery time.
The use of a junction isolated process, together with careful layout, avoids these problems by minimizing the effects of transistor isolation capacitance discharge and thermally induced shifts
in circuit operating points. These problems do not occur even
under high output current conditions.

II
OUTPUT:
5V/OIV

OUTPUT
ERROR:
O.02%/DiV

Figure 24. AD840 Settling Demonstrating No Settling Tails

OUTPUT
ERROR:
O.02%/OIV

Figure 22. AD840 0.01% Settling Time

TEK

7603
OSCILLOSCOPE

GROUNDING AND BYPASSING
In designing practical circuits with the AD840, the user must
remember that whenever high frequencies are involved, some
special precautions are in order. Circuits must be built with
short interconnect leads. Large ground planes should be used
whenever possible to provide a low resistance, low inductance
circuit path, as well as minimizing the effects of high frequency
coupling. Sockets should be avoided, because the increased
inter-lead capacitance can degrade bandwidth.
Feedback resistors should be of low enough value to assure that
the time constant formed with the circuit capacitances will not
limit the amplifier performance. Resistor values of less than
5 kO are recommended. If a larger resistor must be used, a
small (± 10 pF) feedback capacitor in connected parallel with the
feedback resistor, Rp , may be used to compensate for these
stray capacitances and optimize the dynamic performance of the
amplifier in the particular application.
Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. A 2.2 f1F capacitor in parallel
with a 0.1 f1F ceramic disk capacitor is recommended.

FETPROBE
TEK P6201

Figure 23. Settling Time Test Circuit

Figure 23 shows how measurement of the AD840's 0.01 % settling in 100 ns was accomplished by amplifying the error signal
from a false summing junction with a very high speed proprietary hybrid error amplifier specially designed to enable testing
of small settling errors. The device under test was driving a
420 0 load. The input to the error amp is clamped in order to
avoid possible problems associated with the overdrive recovery
of the oscilloscope input amplifier. The error amp amplifies the
error from the false summing junction by 11, and it contains a
gain vernier to fme trim the gain.

REV. A

CAPACITIVE LOAD DRIVING ABILITY
Like all wideband amplifiers, the AD840 is sensitive to capacitive loading. The AD840 is designed to drive capacitive loads of
up to 20 pF without degradation of its rated performance. Capacitive loads of greater than 20 pF will decrease the dynamic
performance of the part although instability should not occur
unless the load exceeds 100 pF. A resistor in series with the output can be used to decouple larger capacitive loads.
USING A HEAT SINK
The AD840 draws less quiescent power than most high speed
amplifiers and is specified for operation without a heat sink.
However, when driving low impedance loads the current to the
load can be 4 to 5 times the quiescent current. This will create a
noticeable temperature rise. Improved performance can be
achieved by using a small heat sink such as the Aavid Engineering #602B.
OPERA TlONAL AMPLIFIERS 2-71

AD840
HIGH SPEED DAC BUFFER CIRCUIT

OVERDRIVE RECOVERY

The AD840's 100 ns settling time to 0.01% for a 10 V step
makes it well suited as an output buffer for high speed DIA converters. Figure 25 shows the connections for producing a 0 to
+ 10.24 V output swing from the AD568 35 ns DAC. With the
AD568 in unbuffered voltage output mode, the AD840 is placed
in noninverting configuration. As a result of the 1 kll span resistor provided internally in the AD568, the noise gain of this
topology is 10. Only 5 pF is required across the feedback (span)
resistor to optimize settling.

Figure 26 shows the overdrive recovery capability of the AD840.
Typical recovery time is 190 ns from negative overdrive and
350 ns from positive overdrive.

INPUT SQUARE WAVE
SCALE 1 VIDIVISION

+15Y

OVERDRIVEN OUTPUT
SCALE: 10V/DIVISION

r

~

TIME: 200ns/DiVISION

Figure 26. Overdrive Recovery

5

i~ ·
1

I·

HP3314A
PULSE GENERATOR

OR EQUIVALENT
l~s

±lV SQUARE

WAVE INPUT

Figure 25.0 to +10.24 V DAC Output Buffer

2-72 OPERATIONAL AMPLIFIERS

Figure 27. Overdrive Recovery Test Circuit

REV. A

IIIIIIIIIII ANALOG

WDEVICES
FEATURES
AC PERFORMANCE
Unity-Gain Bandwidth: 40 MHz
Fast Settling: 110 ns to 0.01%
Slew Rate: 300 V/",s
Full Power Bandwidth: 4.7 MHz for 20 V p-p into a
500n Load

Wideband, Unity-Gain Stable,
Fast Settling Op Amp
AD841 I
CONNECTION DIAGRAMS
Plastic DIP (N) Package
and
Cerdip (Q) Package

TO-8 (H) Package

DC PERFORMANCE
Input·Offset Voltage: 1 mV max
Input Voltage Noise: 13 nV/YHz typ
Open-Loop Gain: 45V/mV into a 1 kn Load
Output Current: 50 mA min
Supply Current: 12 mA max
APPLICATIONS
High Speed Signal Conditioning
Video and Pulse Amplifiers
Data Acquisition Systems
Line Drivers
Active Filters
Available in 14-Pin Plastic DIP and Hermetic Cerdip,
12-Pin TO-8 Metal Can and 20-Pin LCC Packages and
in Chip Form
Chips and MIL-STD-883B Parts Available

Ne = NO CONNECT

NOTE: CAN TIED TO
NC = NO CONNECT

v+

LCC (E) Package

~

j

5 t;
ddl!!
, 2
NO,
17

+v,.

NC.
1& OUTPUT

PRODUCT DESCRIPTION
The AD841 is a member of the Analog Devices family of wide
bandwidth operational amplifiers. This high speedlhigh precision family includes, among others, the AD840, which is stable
at a gain of 10 or greater, and the AD842, which is stable at a
gain of two or greater and has 100 rnA minimum output current
drive. These devices are fabricated using Analog Devices' junction isolated complementary bipolar (CB) process. This process
permits a combination of de precision and wide band ac performance previously unobtainable in a monolithic op amp. In addition to its 40 MHz unity-gain bandwidth product, the AD841
offers extremely fast settling characteristics, typically settling to
within 0.01 % of final value in 110 ns for a 10 volt step.
Unlike many high frequency amplifiers, the AD841 requires no
external compensation. It remains stable over its full operating
temperature range. It also offers a low quiescent current of
12 rnA maximum, a minimum output current drive capablity of
50 rnA, a low input voltage noise of 13 nV/yHz and low input
offset voltage of I mV maximum.
The 300 ViliS slew rate of the AD841, along with its 40 MHz
gain bandwidth, ensures excellent performance in video and
pulse amplifier applications. This amplifier is well suited for use
in high frequency signal conditioning circuits and wide bandwidth active filters. The extremely rapid settling time of the

NC.

14NC

l!!

'i'

l!! l!!

l!!

Ne = NO CONNECT

AD841 makes it the preferred choice for data acquisition applications which require 12-bit accuracy. The AD841 is also appropriate for other applications such as high speed DAC and ADC
buffer amplifiers and other wide bandwidth circuitry.
APPLICATION HIGHLIGHTS
1. The high slew rate and fast settling time of the AD841 make
it ideal for DAC and ADC buffers, and all types of video
instrumentation circuitry.
2. The AD841 is a precision amplifier. It offers accuracy to
0.01% or better and wide bandwidth performance previously
available only in hybrids.
3. The AD841's thermally balanced layout and the speed of the
CB process allow the AD841 to settle to 0.01 % in 110 ns
without the long "tails" that occur with other fast op amps.
4. Laser wafer trimming reduces the input offset voltage to
1 mV max on the K grade, thus eliminating the need for
external offset nulling in many applications. Offset null pins
are provided for additional versatility.
5. The AD841 is an enhanced replacement for the HA2541.

REV. A

OPERA TIONAL AMPLIFIERS 2-73

•

AD841-SPECIFICATIONS

(@ +25°C and ±15 V dc, unless otherwise noted)
AD84IK

AD84IJ
Model

Conditions

Min

INPUT OFFSET VOLTAGE'

Typ

Max

0.8

Tmin-Tmax
Offset Drift

3.5

Input Offset Current

0.1

Tmin-Tmax

1.0

S

3.5

Typ

Max

Units

0.5

2.0
5.5

mV
mV
flVrc

S

flA

12

fl.A
fl.A
fl.A

3.3
35

0.4
0.5

0.1

200
2

VCM = :tIOV

INPUT VOLTAGE NOISE
Wideband Noise

f=lkHz
10 Hz to 10 MHz

OPEN-LOOP GAIN

Vo = :tIOV

Tmin-Tmax

RLOAD~500

n

Tmin-Tmax

Current

0.5

Min

35
5
6
0.2
0.3

3.5
0.1

0.4
0.6

Differential Mode

INPUT VOLTAGE RANGE
Common Mode
Common Mode Rejection

OUTPUT CHARACTERISTICS
Voltage

2.0
5.0

10

Tmin-Tmax

INPUT CHARACTERISTICS
Input Resistance
Input Capacitance

Max

35

INPUT BIAS CURRENT

ADS4IS

Typ

Min

RLOAD~500

:t 10
86
80

200
2
:t10
103
100

12
100
IS
47

25
12

:t10
S6
80

12
109
15
47

45

25
20

45

25
12

200
2

kn

12
100

V
dB
dB

IS
47

nV/y'Hz
flY rms

45

V/mV
V/mV

pF

n

Tmin-Tmax
VOUT = :t1O V

:t10
50

±IO
50

:t10
50

V
rnA

OUTPUT RESISTANCE

Open Loop

5

5

5

n

FREQUENCY RESPONSE
Unity Gain Bandwidth
Full Power Bandwidth'

V OUT = 90 mV p-p
Vo = 20 V p-p

40

40

40

MHz

4.7
10
10
300

MHz

RLOAD~500

Rise Time'
Overshoot3
Slew Rate'
Settling Time - 10 V Step

n

Av =-1
Av =-1
Av =-1
Av =-1
to 0.1%
to 0.01%

3.1

200

4.7
10
10
300

3.1

200

4.7
10
10
300

3.1

200

ns

%
V/flS

90
llO

90
llO

90
llO

ns

ns

OVERDRIVE RECOVERY

-Overdrive
+ Overdrive

200
700

200
700

200
700

ns
ns

DIFFERENTIAL GAIN
Differential Phase

f = 4.4 MHz
f = 4.4 MHz

0.03
0.022

0.03
0.022

0.03
0.022

%
Degree

POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
Power Supply Rejection Ratio

±15
:t5

II
Tmin-Tmax
Vs= ±5Vto±18V

Tmin-Tmax
TEMPERATURE RANGE
Rated Performance'
PACKAGE OPTIONS'
LCC (E-20A)·
Cerdip (Q-14)
Plastic (N-14)
TO-8 (H-l2)
J and S Grade Chips
Also Available

86
80

±15
:tIS
12
14

100

0

:t5

II
90
S6

+75

AD84lJQ
AD84lJN
AD84lJH

±15
:tIS
12
14

100

0

II
86
SO

+75

AD841KQ
AD841KN
AD841KH

:t5

-55

:tIS
i2
16

100

+125

V
V
mA
mA
dB
dB
°C

AD84ISE, AD841SEl883B
AD84ISQ, AD841SQ/883B
AD84ISH, AD841SHl883B

AD841JCHIP

AD841S CHIP

NOTES
1Input offset voltage specifications are guaranteed after 5 minutes at T A = + 25°C.
'Full power bandwidth = Slew Ratel2" VPEAK •
'Refer to Figure 19.
4"8" grade T min and T max specifications are tested with automatic test equipment at T A = -55°C and T A = + 125OC.
sPor outline information see Package Information section.
·Contact factory for availability.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units.
Specifications subject to change without notice.

2-74 OPERA TIONAL AMPLIFIERS

REV. A

AD841
ABSOLUTE MAXIMUM RATINGS '
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2
TO-8 (H) .
. ...... 1.4 W
Plastic (N) .
. ...... 1.5 W
. . . . . . . 1.3 W
Cerdip (Q) .
Input Voltage
. . . . . . . . ±Vs
Differential Input Voltage . . . . . . . . . . . . . . ...... ± 6 V
Storage Temperature Range
Q, H, E . . . . . . . . . . . . . . . . . . . . . . . -65°C to + 150°C
N . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C .to + 125°C
Junction Temperature . . . . . . . . . . . . . . . .
+ 175°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . + 300°C

NOTES
IStresses above those listed under UAbsolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only, and functional

operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not impl~ed. Exposure
to absolute maximum rating conditions for extended periods may affect
device reliability.
2 Maximum internal power dissipation is specified so that T J does not exceed
+ 175°C at an ambient temperature of +25OC.
Thermal Characteristics:
Cerdip Package
TO·8 Package
Plastic Package
LCC Package

alC

alA

3S'CIW
30'CIW
30'C/W
3S'CIW

\1O'CIW 38'CIW Recommended Heat Sink:
100'CIW 37'CIW Aavid Engineering "#602B
100'CIW
\SO'CIW

aSA

METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).

1"'4>------------ ~~~r -----------.j°l
.......- - - ,

BALANCE--,

+VS

0.067

11.71
OUTPUT

........._1...I...-_ _

REV. A

L

SUBSTRATE CONNECTED TO +Vs

-Vs

...J

OPERA TIONAL AMPLIFIERS 2-75

II

AD841---Typical Characteristics (at +Z5°C and Vs = ±15 V, unless otherwise noted.
20

20

0

t 2.
~

/

/
v.-/

V

V
/
o

o
o

5

10

15

20

/

/

V

/"

..~ ,
i

10

15

20

(

51\

4

/

f\.
O.

i-

V

«

V

.

~

/

130

E
I-

/

V

20

0
20
40
60
TEMPERATURE - ·C

120

~

"0

aili

100

~

Ir:

~

20

40

60

80

100 120 140

Figure 7. Quiescent Current vs.
Temperature

2-76 OPERA TIONAL AMPLIFIERS

1M

10M

100M

FREQUENCY - Hz

Figure 6. Output Impedance
VS. Frequency

~

90

~

80

60

40

V

0

CURRENT~~

20

0

20

40

.1 . . . .

~

70

TEMPERATURE _ "C

tOOk

'Ok

5

!"'- ~

/
0

r- I-"
,

~ + OUTPUT CURRENT

-OUTPUT

60

./

~

f'"

U

7
-20

100 120 140

1/

0

t:

/V
-60 -40

80

'40

I

0

40

,

Figure 5. Input Bias Current vs.
Temperature

Figure 4. Quiescent Current vs.
Supply Voltage

/

/

0.0
60

20

10
15
SUPPLY VOLTAGE - !;Volts

,

'Ok

Figure 3. Output Voltage Swing
VS. Load Resistance

.'\

3

4

100
lk
LOAD RESISTANCE - H

1/

"'- ~ r- l-

/

'0

'0

\

15

,/

o

..

4

o

/

,

6

-

lSV SUPPLIES

g~ ,0

Figure 2. Output Voltage Swing
vs. Supply Voltage

12

10

:!:

5

SUPPLY VOLTAGE - :!:Volts

Figure 1. Input Common-Mode
Range vs. Supply Voltage

j

0

I

§ •

o

SUPPLY VOLTAGE - ::!:Volts

V

60

"

80

f'.

100

120 140

V

/'

./

V

0

- 60

40

20

0

20

40

60

80

100 120 140

TEMPERATURE - "c

AMBIENT TEMPERATURE - "C

Figure 8. Short-Circuit Current
Limit vs. Temperature

/'

,/"

Figure 9. Gain Bandwidth Product
Temperature

VS.

REV. A

AD841
'0

o~

0

K--

~

~

0

~

4

~

20

'00

1
1k

'00

\
\

"

+60·

I

80

r-.. r'1+ sUPPlY

.!:,

\

\

"'" "~

Z

, .:ll'".

\

"0'

\

,

20

~

g

Rl = lkH
+25OC

'0

0

'\
20 '':-k...J...-'-U'O'f:k...J...-'-'':'OO:':-k...J...-'-':''M~L...J..J':':O'::M:-'-....LJ''::'.OOM

'OM

FREQUENCY - Hz

2

if
z

0

'"§

..

\.

:J

o
:I;

V

o

Vs = :!:15V

1\

>

-2

E

-4

:J

o

'"

0.1%

0.01%

\,

•
-B

100M

-'0 30

,/

/

V

\

i"""'" "--...........

40

50

60

........ ...........

70

80

90

100

110

SETTLING TIME - ns

Figure 15. Output Swing and
Error vs. Settling Time

Figure 14. Large Signal Frequency
Response

-70

0.1%

L
0.01%

\

FREQUENCY - Hz

Figure 13. Common-Mode
Rejection vs. Frequency

100M

./

~

\

.......-- V

V

~

r'\

15

10M

Figure 12. Power Supply Rejection
vs. Frequency

'0

25

1M

FREQUENCY - Hz

Figure 11. Open-Loop Gain vs.
Supply Voltage

~

500

I

-80

45 0

3VRMS
At = 'kill

25

!ND HARMONIC

-'00

M

0

-'20

-

-'30

'00

~

P.:;,

-

,I,

~

..

.1_

/

350

300

250

V
lk

10k

lOOk

fREQUENCY - Hz

200
-60

/

~,

V
./'
-40

/'

-20

~

0

>

15

5

/

20
40
60
TEMPERATURE - "C

20

~

//

-[::: JRD tRiOj'C

Figure 16. Harmonic Distortion vs.
Frequency

REV. A

>,

S

1\

I:!!

~ 400

-90

-11

1k

'00

30

'"~

I'

o

20

15

SUPPLY VOLTAGE - :tV

Figure 10. Open-Loop Gain and
Phase Margin vs. Frequency

II

40

Rt

90
10M

"

•

\

500JI LOAD

-20

,
+80'

""l\.

", 0

z

120

B

+100"

--

--- ---

~

,01-1-+++++ttlf-I-+++++HtH-+1*t-t+H
80

Figure 17. Slew Rate vs.
Temperature

100

120 140

~LO-L~'O~O-L~'+k-L~'O±k~U'~OO~k~~'~M~~'OM
fREQUENCY - Hz

Figure 18. Input Noise Voltage
Spectral Density

OPERA TIONAL AMPLIFIERS 2-77

AD841

HP3314A
FUNCTION
GENERATOR i-+-"iNIr-......
OR
EQUIVALENT

Figure 19a. Inverting Amplifier
Configuration (DIP Pinout)

Figure 19b. Inverter Large Signal
Pulse Response

Figure 19c. Inverter Small Signal
Pulse Response

R.
12011

HP3314A
FUNCTION
GENERATOR
OR
EQUIVALENT

1--_.JY'V'v---<

Figure 20a. Unity-Gain Buffer Amplifier
Configuration (DIP Pinout)

Figure 20b. Buffer Large Signal
Pulse Response

Figure 20c. Buffer Small Signal
Pulse Response

OFFSET NULLING

INPUT CONSIDERATIONS

The input offset voltage of the AD841 is very low for Ii high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 21 can be used.

An input resistor (R1N in Figure 20) is recommended in circuits
where the input to the AD841 will be subjected to transient or
continuous overload voltages exceeding the ±6 V maximum differentiallimit. This resistor provides protection for the input
transistors by limiting the maximum current that can be forced
into the input.
For high performance circuits it is recommended that a resistor
(RB in Figures 19 and 20) be used to reduce bias current errors
by matching the impedance at each input. The output voltage
error caused by the offset current is more than an order of magnitude less than the error present ·if the bias current error is not
removed.

Figure 21. Offset Nulling (DIP Pinout)

2-78 OPERATIONAL AMPLIFIERS

REV. A

Applying the AD841
AD841 SETTLING TIME
Figures 22 and 24 show the settling performance of the AD841
in the test circuit shown in Figure 23.
Settling time is defined as:
The interval of time from the application of an ideal step
function input until the closed-loop amplifier output has
entered and remains within a specified error band.
This definition encompasses the major components which comprise settling time. They include (I) propagation delay through
the amplifier; (2) slewing time to approach the final output
value; (3) the time of recovery from the overload associated with
slewing and (4) linear settling to within the specified error band.

associated with the overdrive recovery of the oscilloscope input
amplifier. The error amp gains the error from the false summing
junction by 10, and it contains a gain vernier to fme trim the
gain.
Figure 24 shows the "long term" stability of the settling characteristics of the AD841 output after a 10 V step. There is no evidence of settling tails after the initial transient recovery time.
The use of a junction isolated process, together with careful layout, avoids these problems by minimizing the effects of transistor isolation capacitance discharge and thermally induced shifts
in circuit operating points. These problems do not occur even
under high output current conditions.

t
I

•

-~t-t---j

OUTPUT
ERROR:
O.02%/DIV

OUTPUT
ERROR:
O.02%/DIV

OUTPUT:
5V/DIV

OUTPUT:
5V/DIV

Figure 22. AD847 0.07% Settling Time

Figure 24. AD847 Settling Demonstrating No Settling
Tails

Expressed in these terms, the measurement of settling time
is obviously a challenge and needs to be done accurately to
assure the user that the amplifier is worth consideration for the
application.

T••
7AU

T••

'60'

OSCILLOSCOPE

TE'

'1A18

GROUNDING AND BYPASSING
In designing practical circuits with the AD841, the user must
remember that whenever high frequencies are involved, some
special precautions are in order. Circuits must be built with
short interconnect leads. Large ground planes should be used
whenever possible to provide a low resistance, low inductance
circuit path, as well as minimizing the effects of high frequency
coupling. Sockets should be avoided because the increased interlead capacitance can degra.de bandwidth.
Feedback resistors should be of low enough value to assure that
the time constant formed with the circuit capacitances will not
limit the amplifier performance. Resistor values of less than
5 kn are recommended. If a larger resistor must be used, a
small « 10 pF) feedback capacitor in parallel with the feedbac.k
resistor, RF , may be used to compensate for these stray capacitances and optimize the dynamic performance of the amplifier in
the particular application.

49911

Figure 23. Settling Time Test Circuit

Measurement of the AD841's 0.01% settling in 110 ns was accomplished by amplifying the error signal from a false summing
junction with a very high speed proprietary hybrid error amplifier specially designed to enable testing of small settling errors.
The device under test was driving a 500 n load. The input to
the error amp is clamped in order to avoid possible problems

REV. A

Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. A 2.2 I1F capacitor in parallel
with a 0.1 I1F ceramic disk capacitor is recommended.
CAPACITIVE LOAD DRIVING ABILITY
Like all wideband amplifiers, the AD841 is sensitive to capacitive loading. The AD841 is designed to drive capacitive loads of
up to 20 pF without degradation of its rated performance. Capacitive loads of greater than 20 pF will decrease the dynamic
performance of the part although instability should not occur
unless the load exceeds 100 pF (for a unity-gain follower). A
resistor in series with the output can be used to decouple larger
capacitive loads.

OPERATIONAL AMPLIFIERS 2-79

2

AD841
Figure 25 shows a typical configuration for driving a large capacitive load. The 51 n output resistor effectively isolates the
high frequency feedback from the load and stabilizes the circuit.
Low frequency feedback is returned to the amplifier summing
junction via the low pass filter formed by the 51 n resistor and
the load capacitance, CL .

If termination is not used, cables appear as capacitive loads. If
this capacitive load is large, it should be decoupled from the
AD841 by a resistor in series with the output (see above:
Driving a Capacitive Load).

lkll

15pF

V OUT

V,N
INPUT

lkll

TERMINATION
RESISTOR
FOR INPUT
SIGNAL

RT = RBT = CABLE CHARACTERISTIC IMPEDANCE

Figure 26. Line Driver 'Configuration
Figure 25. Circuit for Driving a Large Capacitive Load

USING A HEAT SINK
The AD841 draws less quiescent power than most precision
high speed amplifiers and is specified for operation without a
heat sink. However, when driving low impedance loads, the current to the load can be 4 to 5 times the quiescent current. This
will create a noticeable temperature rise. Improved performance
can be achieved by using a small heat sink such as the Aavid
Engineering #602B.
TERMINATED LINE DRIVER
The AD841 functions very well as a high speed line driver of
either terminated or unterminated cables. Figure 26 shows the
AD841 driving a doubly terminated cable in a follower configuration. The AD841 maintains a typical slew rate of 300 V/fj-s,
which means it can drive a ±10 V, 4.7 MHz signal or a ±3 V,
15.9 MHz signal.
The termination resistor, R r , (when equal to the characteristic
impedance of the cable) minimizes reflections from the far end
of the cable. A back-termination resistor (ROT' also equal to the
characteristic impedance of the cable) may be placed between
the AD841 output and the cable in order to damp any stray signals caused by a mismatch between RT and the cable's characteristic impedance. This will result in a "cleaner" signal, but
since 112 the output voltage will be dropped across ROT' the op
amp must supply double the output signal required if there is
no back termination. Therefore the full power bandwidth is cut
in half.

OVERDRIVE RECOVERY
Figure 27 shows the overdrive recovery capability of the AD841.
Typical recovery time is 200 ns from negative overdrive and
700 ns from positive overdrive.

OVERDRIVEN
OUTPUT: l0V/DIV

INPUT SQUARE
WAVE: lV/DIV

Figure 27. Overdrive Recovery

HP33l4A
PULSE GENERATOR
OR EQUIVALENT
llJ.S ± lV SQUARE
WAVE INPUT

Figure 28. Overdrive Recovery Test Circuit

2-80 OPERA T10NAL AMPLIFIERS

REV. A

Wideband, High Output Current,
Fast Settling Op Amp
AD842 I

11IIIIIIII ANALOG
WDEVICES
FEATURES
AC PERFORMANCE
Gain Bandwidth Product: 80 MHz (Gain
2)
Fast Settling: 100 ns to 0.01% for a 10 V Step
Slew Rate: 375 V/fJ-s
Stable at Gains of 2 or Greater
Full Power Bandwidth: 6.0 MHz for 20 V p-p

=

CONNECTION DIAGRAMS
Plastic DIP (N) Package
and
Cerdip (Q) Package

LCC (E) Package

i i
~

DC PERFORMANCE
Input Offset Voltage: 1 mV max
Input.Offset Drift: 14 fJ-V/oC
Input Voltage Noise: 9 nV/YHz typ
Open-Loop Gain: 90 V/mV into a 500 n Load
Output Current: 100 rnA min
Quiescent Supply Current: 14 rnA max
APPLICATIONS
Line Drivers
DAC and ADC Buffers
Video and Pulse Amplifiers
Available in Plastic DIP Hermetic Metal Can,
Hermetic Cerdip and LCC Packages and in Chip Form
MIL-STD-883B Parts Available
PRODUCT DESCRIPTION
The AD842 is a member of the Analog Devices family of wide
bandwidth operational amplifiers. This family includes, among
others, the AD840 which is stable at a gain of 10 or greater and
the AD841 which is unity-gain stable. These devices are fabricated using Analog Devices' junction isolated complementary
bipolar (CB) process. This process permits a combination of dc
precision and wideband ac performance previously unobtainable
in a monolithic op amp. In addition to its 80 MHz gain bandwidth, the AD842 offers extremely fast settling characteristics,
typically settling to within 0.01 % of fmaI value in less than
100 ns for a 10 volt step.
The AD842 also offers a low quiescent current of 13 rnA, a high
output current drive capability (100 rnA minimum), a low input
voltage noise of 9 nVv'Hz and a low input offset voltage (1 mV
maximum).
The 375 V/jJ.s slew rate of the AD842, along with its 80 MHz
gain bandwidth, ensures excellent performance in video and
pulse amplifier applications. This amplifier is ideally suited for
use in high frequency signal conditioning circuits and wide
bandwidth active ftIters. The extremely rapid settling time of
the AD842 makes this amplifier the preferred choice for data
acquisition applications which require 12-bit accuracy. The
AD842 is also appropriate for other applications such as high
speed DAC and ADC buffer amplifiers and other wide bandwidth circuitry.

REV. A

~

(5

~

~

0

~

3212019

,. NC

17

+v.

•

16 Ne
15 OUTPUT

'4 Ne
9

~
NC "" NO CONNECT

10 "

:f

12

13

~ ~ ~

He "" NO CONNECT

TO-S (H)
Package
NC

-INPUT

OUTPUT

NC
TOP VIEW
NOTE: CAN TIED TO V+
Ne '" NO CONNECT

APPLICATION mGHLIGHTS
I. The high slew rate and fast settling time of the AD842 make
it ideal for DAC and ADC buffers amplifiers, lines drivers
and all types of video instrumentation circuitry.
2. The AD842 is a precision amplifier. It offers accuracy to
0.01% or better and wide bandwidth; performance previously
available only in hybrids.
3. Laser-wafer trimming reduces the input offset voltage of
I m V max, thus eliminating the need for external offset nulling in many applications.
4. Full differential inputs provide outstanding performance in
all standard high frequency op amp applications where the
circuit gain will be 2 or greater.
5. The AD842 is an enhanced replacement for the HA2542.

OPERA TIONAL AMPLIFIERS 2-81

AD842-SPECIFICATIONS(@ +25°C and ±15 V dc, unless otherwise noted)'
Moci~1

.'.

Conditions

Min

INPUT OFFSET VOLTAGE'

AD842J
Typ
Max
0.5

T_-T"""
Offset Drift

4.2

Tmin-Tmax
Input Offset Current

0.1

Tmin-Tmax

INPUT VOLTAGE RANGE
Common Mode
Common-Mode Rejection

Differential Mode

VCM = ±IOV
Tmin-Tmu:

INPUT VOLTAGE NOISE
Wideband Noise

f=lkHz
10 Hz to 10 MHz

OPEN-LOOP GAIN

Vo = ±IOV
R LoAD2500 !l
Tmin-Tmax

OUTPUT CHARACTERISTICS
Voltage
Current
FREQUENCY RESPONSE
Gain Bandwidth Product
Full Power Bandwidth2
Rise Time'
Overshoot'
Slew Rate'
Settling Time'

Differential Gain
Differential Phase

R LoAD 2500 !l
VoUT=±IOV
OPen Loop
VOUT = 90 mV
Vo=20Vp-p
RLOAD2500 !l
AVCL = -2
AVCL = -2
AVCL = -2
10V Step
to 0.1%
to 0.01%
f = 4.4 MHz
f = 4.4 MHz

POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
Power Supply Rejection Ratio

0.3

S
10
0.4
0.5

3.5
0.05

±10
90
86

115

50
25

± 10
100

4.7

300

S
12
0.4
0.6

,.A
,.A
,.A
,.A

14

0.1

±10
86
80

115

40

90

,.vrc

100
2.0

kO
pF

115

V
dB
dB

9
28

nVlv'Hz
,.Vrms

90

VlmV
V/mV

20
:1:10
100

V

rnA
5

!l

80

80

80

MHz

6
10
20
375

MHz
ns
%

80
100
0.015
0.035

ns
ns
%
Degree

6
10
20
375

13

PACKAGE OPTIONS'
Plastic (N-14)
Cerdip (Q-14)
TO-8 (H-I2A)
LCC· (E-20A)
J and S Grade Chips
Also Available

mV
mV

5

4.7

300

±5
13

90
86

+75
AD842JN
AD842JQ
AD842JH

4.7

300

±15
±lS
14
16

100

0

6
10
20
375
80
100
0.015
0.035

±15

TEMPERATURE RANGE
Rated Performance'

4.2

Units

1.5
3.5

5

80
100
0.015
0.Q35

86
80

5
6
0.2
0.3

±10
100

±5
Tmin-Tmax
Vs =±5Vto±15V
Tmin-Tmax

0.5

9
28

90

AD842S
Typ
Max

1.0
1.5

100
2.0

9
28

40
20

.',

Min

14

100
2.0
± 10
86
80

AD842K
Typ
Max

1.5
2.5

14

INPUT BIAS CURRENT

INPUT CHARACTERISTICS
Input Resistance
Input Capacitance

Min

±15
±18
14
16

lOS

0

±5
13

86
80

+75
AD842KN
AD842KQ
AD842KH

V/,.s

-55

±lS
14
19

100

V
V

rnA
rnA
dB
dB

+125

°C

AD842SQ, AD842SQ/883B
ADg42SH
AD842SE

NOTES
'Input offset voltage specifications are guaranteed after 5 minutes at TA ;" +250(;.
2FPBW Slew Rateli" VPEAK '
'Refer to Figures 22 and 23.
'''S'' grade Tmin and T_ specifications are tested with automatic test equipment at TA = -55°C and TA = +1250(;.
5Por outline information see Package Information section.
·Contact factory for availability.
AU min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Results from
those tests are used to calculate outgoing quality levels.
Specifications subject to change without notice.

2-82 OPERATIONAL AMPLIFIERS

REV. A

AD842
ABSOLUTE MAXIMUM RATINGS'
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2
Plastic (N) . . . . . . . . . . . . . . . . . . . .
1.5 W
Cerdip (Q) . . . . . . . . . . . . . . . . . . . .
I.IW
TO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . l.3W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±Vs
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . ±6 V
Storage Temperature Range
Q, H . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to + 150°C
N . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to + 125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . + 175°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . +300°C
NOTE
lStresses above those listed under "Absolute Maximum Ratings" may cause
pennanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated
in the operational section of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
2Maximum internal power dissipation is specified so that TJ does not exceed
+ l50"C at an ambient temperature of +25"C.
Thermal Characteristics:
Plastic Package
Cerdip Package
TO-S Package

SIC

aJA

eSA

30°C/W
30°C/W
30°C/W

IOO°C/W
11 O"C/W
lOO"ClW

3SoC/W
27°C/W

METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
14.-------0.,0612.681

-------.1"

1
BALANCE

~r

,
v+

BALANCE

I

-VIN

1

0.067

1'.691

OUTPUT

SUBSTRATE CONNECTED
TO+Vs

Recommended heat sink: Aavid Engineering<> #602B

REV. A

OPERA TIONAL AMPLIFIERS 2-83

•

AD842 - Typical Characteristics (at +25°C and Vs = ±15 V, unless otherwise noted.)
20

20

0

.l!

~ 1S

/

o

/
o

V
V
10

0

:v

v.. /

/

•

"

LV

I

15

20

5

/

/

I/:!: 15V SUPPLIES

/

0

II

/
o

o

o

5

10

15

10

20

100

Figure 7. Input Common-Mode
Range VS. Supply Voltage

Figure 2. Output Voltage Swing
Supply Voltage

10k

Figure 3. Output Voltage Swing
VS. Load Resistance

VS.

,.

lk

LOAD RESISTANCE - 1l

SUPPLY VOLTAGE - :!:Volts

SUPPLY VOLTAGE - '!"Volts

'00

-5

/

\

1&

V

i'-.

./

12

~

I

""- ......

I

V

10

-2
15
10
SUPPLY VOLTAGE - :!:Volts

Figure 4. Quiescent Current
Supply Voltage

20

-60

- 40 - 20

/

1

1/

o. 1

/

--

0.01
0

20

40

60

80

100 120 '40

1M

100k

10k

TEMPERATURE _ °C

10M

100M

FREQUENCY - Hz

Figure 5. Input Bias Current
Temperature

VS.

,.

Figure 6. Output Impedance
Frequency

VS.

VS.

••

300

/

17

~

,.

V

"E, 15

V

~
114

a

!! "

/

M
:3 12
o

11

=,

\

,.

/

0

1'-':

-c~~~:~; r'::

/

•

I" t'--

V

10
-60 -40 -20

20 40
60
TEMPERATURE - -c

80

100 120 140

~ i'..

Figure 7. Quiescent Current
Temperature

20

40

"-

60

80

100

120 140

AMBIENT TEMPERATURE _ °C

VS.

2-84 OPERA T10NAL AMPLIFIERS

1\

\

"i'
0

1\

70

~

100
-60 -40 -20

V

\

125

..... v

.- v

~OUTPUT CURRENT

Figure 8. Short-Circuit Current
Limit VS. Temperature

as
-60 -40 -20

0

20 40 10 80
TEMPERATURE - "C

100 120 140

Figure 9. Gain Bandwidth Product
VS. Temperature

REV. A

AD842
120

\ -- r-- -- -

100

.....

100

,

~60

soon LOAD
1

o
100

10k

1k

TOOk

/"

I

I

'"

2

I

I

N

10M

1M

~

I--

I

20

Z 80

-

I

"'-

o

/

~20

15

100

20

10

. / fo-

5

VCM = TV pop
,+25-':

/

\

0

\

r'-,

0

40

10k

lOOk

10M

1M

'"

10M

100M

FREQUENCY _ Hz

\

/'

•
100M

".V

V

,/

0.01%

-10
3D

0.01'"

\
[\.

""."""'-"

40

50

10

70

f'... 10

80

550

v

500

'l!,

r:~

1\

LD HARMON''Y ~

0

1\

/

_I-"

JRD rRM;'

- +11
10'

100.

FREQUENCY - Hz

Figure 16. Harmonic Distortion
Frequency

/

//

-130

1k

VV

450

lJ".

~

o
~ -120

110

Figure 15. Output Swing and
Error vs. Settling Time

-go

40

100

SETTUNO TIME - ns

..
3VRMS
Rl = lk~l

100M

/

\

-8

Figure 14. Large Signal Frequency
Response

-00

REV. A

.1%

fREQUENCY - Hz

Figure 13. Common-Mode
Rejection VS. Frequency

-140
100

0.1%

2

5

~

10M

0

5

60

/

2

RL = TkO
+25-':
Vs = ±15V

1\

r....,

lOOk
1M
FREQUENCY _ Hz

Figure 12. Power Supply Rejection
vs. Frequency

VS.

Vs = :!:15V

'"

10k

1k

~v

30

100

I~

o
10

Figure 11. Open-Loop Gain
Supply Voltage

IIII I

l~~

i

SUPPLY VOlTAGE-

120

V

.~

L

500.0 LOAD

o

Figure 10. Open-Loop Gain and
Phase Margin vs. Frequency

I\::su,"

-5

i:!60

90
100M

FREQUENCY - Hz

r'-

~

'l,!

\

~~40

I-----

100

\

"",-

a

120

00

"~

~80
Z

110

VS.

1\
10

10

300

100

"

10k

TOOle

1M

fREQUENCY - Hz

Figure 17. Input Voltage
Frequency

VS.

10M

...

V
/

V

-60 -40 -20

20 40
60 80 100 120 140
TEMPERATURE - ·c

Figure 18. Slew Rate
Temperature

VS.

OPERA TIONAL AMPLIFIERS 2-85

•

AD842

Figure 19a. Inverting Amplifier
Configuration (DIP Pinout)

R1

=

205n

Rf

'"

Figure 19b. Inverter Large Signal
Pulse Response

Figure 19c. Inverter Small Signal
Pulse Response

20SU

HP3314A

FUNCTION
GENERATOR
OR
EQUIVALENT

I--"'....."'Wv--{

Figure 20a. Noninverting Amplifier
Configuration (DIP Pinout)

Figure 20b. Noninverting Large Signal
Pulse Response

Figure 20c. Noni;1Verting Small
Signal Pulse Response

OFFSET NULLING
The input offset voltage of the AD842 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 21 can be used.

Figure .21. Offset Nulling
(DIP Pinout)

2-86 OPERATIONAL AMPLIFIERS

REV. A

Applying the AD842
AD842 SETTLING TIME
Figures 22 and 24 show the settling performance of the AD842
in the test circuit shown in Figure 23.

OUTPUT:
IOV/DIV

Settling time is defined as:
The interval of time from the application of an ideal step
function input until the closed-loop amplifier output has
entered and remains within a specified error band.
This definition encompasses the major components which comprise settling time. They include: (I) propagation delay through
the amplifier; (2) slewing time to approach the final output
value; (3) the time of recovery from the overload associated with
slewing; and (4) linear settling to within the specified error
band.

OUTPUT
ERROR:

O.02"I0/DIV

Figure 22. AD842 0.01% Settling Time

Expressed in these terms, the measurement of settling time
is obviously a challenge and needs to be done accurately to
assure the user that the amplifier is worth consideration for the
application.
TEK
7A13

TEK

1603
OSCILLOSCOPE
TEK

7A18

4990

0005109
FlAT·TOP

4990

1kn

PULSE GENERATOR

FET PROBE

}---+~ TEK P6201
499U

Figure 23. Settling Time Test Circuit

Figure 23 shows how measurement of the AD842's 0.01% settling in 100 ns was accomplished by amplifying the error signal
from a false summing junction with a very high-speed proprietary hybrid error amplifier specially designed to enable testing
of small settling errors. The device under test was driving a
300 n load. The input to the error amp is clamped in order to
avoid possible problems associated with the overdrive recovery
of the oscilloscope input amplifier. The error amp gains the
error from the false summing junction by 15, and it contains a
gain vernier to fine trim the gain.
Figure 24 shows the "long term" stability of the settling characteristics of the AD842 output after a 10 V step. There is no evidence of settling tails after the initial transient recovery time.
The use of a junction isolated process, together with careful layout, avoids these problems by minimizing the effects of transistor isolation capacitance discharge and thermally induced shifts
in circuit operating points. These problems do not occur even
under high output current conditions.
GROUNDING AND BYPASSING
In designing practical circuits with the AD842, the user must
remember that whenever high frequencies are involved, some

REV. A

OUTPUT:
5V/DIV

OUTPUT
ERROR:

O.01"lo/DIV

Figure 24. AD842 Settling Demonstrating No Settling
Tails

special precautions are in order. Circuits must be built with
short interconnect leads. Large ground planes should be used
whenever possible to provide a low resistance, low inductance
circuit path, as well as minimizing the effects of high frequency
coupling. Sockets should be avoided because the increased interlead capacitance can degrade bandwidth.
OPERA TIONAL AMPLIFIERS 2-87

II

AD842
Feedback resistors should be of low enough value to assure that
the time constant formed .with the. circuit capacitances will not
limit the amplifier performance. Resistor values of less than
5 kG are recommended. If a larger resistor must be used, a
small «10 pF) feedback capacitor connected in parallel with the
feedback resistor, R F , may be used to compensate for these
stray capacitances and optimize the dynamic performance of the
amplifier in the particular application.

RT

CHARACTERISTIC
IMPEDANCE

SOH OR 7Sfl CABLE

Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. A 2.2 ,...F capacitor in parallel
with a 0.1 ,...F ceramic disk capacitbr is recommended.
CAPACITIVE LOAD DRMNG ABILITY
Like all wideband amplifiers, the AD842 is sensitive to capacitive loading. The AD842 is designed to drive capacitive loads
of up to 20 pF without degradation of its rated performance.
Capacitive loads of greater than 20 pF will decrease the dynamic
performance of the part although instability should not occur
unless the load exceeds 100 pF.
USING A HEAT SINK
The AD842 draws less quiescent power than most precision
high speed amplifiers and is specified for operation without a
heat sink. However, when driving low impedance loads, the current to the load can be 10 times the quiescent current. This will
create a noticeable temperature rise. Improved performance can
be achieved by using a small heat sink such as the Aavid Engineering #602B.

R2

Figure 25. Line Driver Configuration

OVERDRIVE RECOVERY
Figure 26 shows the overdrive recovery capability of the AD842.
Typical recovery time is 80 ns from negative overdrive and
400 ns from positive overdrive.

OVERDRIVEN OUTPUT,
10VIDIVISION

TERMINATED LINE DRIVER
The AD842 is optimized for high speed line driver applications.
Figure 25 shows the AD842 driving a doubly terminated cable
in a gain-of-2 follower configuration. The AD842 maintains a
typical slew rate of 375 VII's, which means it can drive a
±IO V, 6.0 MHz signal or a ±3 V, 19.9 MHz signal.
The termination resistor, RT, (when equal to the characteristic
impedance of the cable) minimizes reflections from the far end
of the cable. A back-termination resistor (RBT> also equal to the
characteristic impedance of the cable) may be placed between
the AD842 output and the cable in order to damp any stray signals caused by a mismatch between RT and the cable's characteristic impedance. This will result in a "cleaner" signal. With
this circuit, the voltage on the line equals VIN because one half
of VOUT is dropped across R BT •

INPUT SQUARE WAVE,
1VIDIVISION

TIME: 100ns/DIVISION

Figure 26. Overdrive Recovery

The AD842 has ±100 mA minimum output current and, therefore, can drive ±5 V into a 50 G cable.

HP3314A

PULSE GENERATOR

The feedback resistors, Rl and R z, must be chosen carefully.
Large value resistors are desirable in order. to limit the amount
of current drawn from the amplifier output. But large resistors
can cause amplifier instability because the parallel resistance
R1IIRz combines with the input capacitance (typically 2-5 pF) to
create an additional pole. Also, the voltage noise of the AD842
is equivalent to a 5 kG resistor, so large resistors can significantly increase the system noise. Resistor values of 1 kG or
2 kG are recommended.

= RaT = CABLE

OUTPUT

OR EQUIVALENT

lkU
1",5,

:!:

lV SQUARE

WAVE INPUT

Figure 27. Overdrive Recovery Test Circuit

If termination is not used, cables appear as capacitive loads and
can be decoupled from the AD842 by a resistor in series with
the output.

2-88 OPERA TlONAL AMPLIFIERS

REV. A

34 MHz, CBFET
Fast Settling Op Amp
AD843 I

11IIIIIIII ANALOG
WDEVICES
FEATURES
AC PERFORMANCE
Unity Gain Bandwidth: 34 MHz
Fast Settling: 135 ns to 0.01%
Slew Rate: 250 V I ILS
Stable at Gains of 1 or Greater
Full Power Bandwidth: 3.9 MHz
DC PERFORMANCE
Input Offset Voltage: 1 mV max (AD843K/B)
Input Bias Current: 0.6 nA typ
Input Voltage Noise: 19 nV/v'Hz
Open Loop Gain: 30 V/mV into a 500.n Load
Output Current: 50 mA min
Supply Current: 13 mA max
Available in 8-Pin Plastic Mini-DIP 8. Cerdip Packages.
20-Pin LCC and 12-Pin Hermetic Metal Cans
Chips and MIL-STD-883B Parts Also Available
APPLICATIONS
High Speed Sample-and-Hold Amplifiers
High Bandwidth Active Filters
High Speed Integrators
High Frequency Signal Conditioning

CONNECTION DIAGRAMS
Plastic (N) and
Cerdip (Q) Package

16-Pin SOIC Package

Ne "" NO CONNECT

LCC (E) Package
::j

::j

NC '" NO CONNECT

"Iiiz Iii"z
"z3 ~2 "z, 2.~

TO-S (H) Package

0

TOP VIEW

,.
~

11
11
LJ

NC 4

18 NC

-IN 5

17 +Vs

NC 6

16 NC

+IN 7

15 OUTPUT

NC.

14 Ne

PRODUCT DESCRIPTION
The AD843 is a fast settling, 34 MHz, CBFET input op amp.
The AD843 combines the low (0.6 nA) input bias currents char·
acteristic of a FET input amplifier while still providing a
34 MHz bandwidth and a 13S ns settling time (to within 0.01%
of final value for a 10 volt step). The AD843 is a member of the
Analog Devices' family of wide bandwidth operational amplifiers. These devices are fabricated using Analog Devices' junction
isolated complementary bipolar (CB) process. This process permits a combination of dc precision and wideband ac perform·
ance previously unobtainable in a monolithic op amp.
The 2S0 V/fJ-s slew rate and 0.6 nA input bias current of the
AD843 ensure excellent performance in high speed sample-andhold applications and in high speed integrators. This amplifier is
also ideally suited for high bandwidth active filters and high fre·
quency signal conditioning circuits.
Unlike many high frequency amplifiers, the AD843 requires no
external compensation and it remains stable over its full operating temperature range. It is available in five performance grades:
the AD843J and AD843K are rated over the commercial tempera·
ture range of O°C to + 70°C. The AD843A and AD843B are rated
over the industrial temperature range of -40°C to +8S°C. The
AD843S is rated over the military temperature range of - SSOC
to + 12SoC and is available processed to MIL-STD-883B, Rev. C.

+IN

NOTE: CAN TIED TO V+

9

10 11

~

f

12

13

~ 12l l2l

NC = NO CONNECT

NC '" NO CONNECT

PRODUCT HIGHLIGHTS
I. The high slew rate, fast settling time and low input bias

current of the AD843 make it the ideal amplifier for 12-bit
D/A and AID buffers, for high speed sample-and-hold amplifiers and for high speed integrator circuits. The AD843
can replace many FET input hybrid amplifiers such as the
LH0032, LH4104 and OPA600.
2. Fully differential inputs provide outstanding performance in
all standard high frequency op amp applications such as signal conditioning and active filters.
3. Laser wafer trimming reduces the input offset voltage to
I mV max (AD843K and AD843B).
4. Although external offset nulling is unnecessary in many
applications, offset null pins are provided.
S. The AD843 does not require external compensation at closed
loop gains 'of 1 or greater.

The AD843 is offered in either 8-pin plastic DIP or hermetic
cerdip packages, in 16-pin SOIC, or in a 12-pin metal can.
Chips are also available.

REV. A

OPERA TlONAL AMPLIFIERS 2-89

II

AD843 -SPECIFICATIONS
Model

Conditions

(@ TA +25°C and ±15 V dc, unless otherwise noted)

Min

1.0
1.7
12

INPUT OFFSET VOLTAGE '
Tmin-T ....
Offset Drift
INPUT BIAS CURRENT

INPUT OFFSET CURRENT

AD843J/A
Typ
Max

Initial (TJ = +25'<:)
Warmed-Up 1
Tmin-T _

50
0.8

Initial (TJ - + 25°C)
Warmed-Upl
Tmin-Tmax

30
0.25

Min

2.0
4.0

2.5
601160

60
60

AD843S
Typ

1.0
2.0
35

1.0
3.0
12

40
0.6

1.0

50
0.8

23/65
20
0.2

1.0

30
0.25

0.4

9126
10'0
6

1010
6
±10

Min

0.5
1.2
12

23/64

INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
INPUT VOLTAGE RANGE
Common Mode

AD843KIB
Typ
Max

+12,
-13

±10

72
72

70
68

+12,

Units
mV
mV
fLVI'C

2.5
2600

nA

pA

nA
pA

1.0
1025

nA
nA

1010
6

0
pF

±10

+12,
-13

V

60
60

72
72

dB
dB

19
60

nVIv'Hz
fLV-rms

-13
76
76

Max
2.0
4.5

COMMON MODE REJECTION

VCM = ±IOV
Tmin-Tmax

INPUT VOLTAGE NOISE
Wideband Noise

f = 10 kHz
10 Hz to 10 MHz

OPEN LOOP GAIN

Vo = ±IOV
R LOAD ,,=5000
Tmin-Tmax

15
10

25
20

20
10

30
25

15
10

30
25

V/mV
V/mV

R LOAD ,,=500 0

±10

+1l.5,
-12.6

±10

+1l.5,
-12.6

±10

+ 1l.5,
-12.6

V

VOUT = ±IOV
Open Loop

50

OUTPUT CHARACTERISTICS
Voltage
Current
Output Resistance
FREQUENCY RESPONSE
Unity Gain Bandwidth
Full Power Bandwidth2
Rise Time
Overshoot
Slew Rate
Settling Time

Overdrive Recovery
Differential Gain
Differential Phase

VOUT = 90 mV p-p
Vo = 20 Vp-p
Rk5000
AYCL = -I
AYCL = -I
AYCL = -I
10 V Step
AyCL = -I
to 0.1%
to 0.01%
-Overdrive
+ Overdrive
f= 4.4 MHz
f = 4.4 MHz

POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
Rejection Ratio
Rejection Ratio

19
60

2.5

160

19
60

50
12

12

0

34

34

34

MHz

3.9
10
15
250

MHz
ns
%
V/fLS

ns
ns
ns
ns
%
Degree

3.9
10
15
250

2.5

160

Tmin-Tmax

TEMPERATURE RANGE
Operating, Rated Performance
Commercial (0 to + 700C)
Industrial (- 40'<: to + 85°C)
Military ( - WC to + 125'<:)'
PACKAGE OPTIONS'
Plastic (N)
Cerdip (Q)
Metal Can (H)
LCC(E)'
SOIC (R)

2-90 OPERATIONAL AMPLIFIERS

2.5

160

95

95

135

135

135

200
700
0.025
0.025

200
700
0.025
0.025

200
700
0.025
0.025

±15

±15

65
62

3.9
10
15
250

95

±4.5
Tmin-Tmax
±5 V to ±18 V

rnA

50

12

12
12.3
76
76

AD843J
AD843A

±18
13
14

±4.5

70
68

12
12.3 .
80
80

±15
±18
13
14

±4.5

65
62

12
12.5
76
76

±18
13
16

V
V
rnA

rnA
dB
dB

AD843K
AD843B
AD843S

AD843JN
AD843AQ

AD843KN
AD843BQ
AD843BH

AD843SQ, AD843SQ/883B
AD843SH
AD843SE, AD843SEl883B

AD843JR

REV. A

AD843
NOTES
ISpecifications are guaranteed after 5 minutes at T A = + 25°C.
'Full power bandwidth ~ Slew Ratel2 TrV peak.
3All "S" grade T min-T max specifications are tested with automatic test equipment at T A = -55°C and T A = + 125°C.
4For outline information see Package Information section.
SContact factory for availability.
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels.
All min and max specifications are guaranteed although only those shown in boldface are tested on all production units.

ABSOLUTE MAXIMUM RATINGS'
Supply Voltage . . . . . . . . . . . . . . . . .
. .. ± IS V
Internal Power Dissipation2
Plastic Package . . . . . .
1.50 Watts
1.35 Watts
Cerdip Package. . . . . . .
I.S0 Watts
12-Pin Header Package. .
20-Pin LCC Package . . . . . . . . . . . . . . . . . . . . 1.0 Watt
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± Vs
Output Short Circuit Duration . . . . . . . . . . . .... Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . +Vs and -Vs
Storage Temperature Range (N, R) .
-65°C to + 150°C
Storage Temperature Range (Q, H) . . . . . . . -65°C to + 125°C
Operating Temperature Range
ADS43J/K . . . . . . . . . . . . . . . . . . . . . . . . . 0 to + 70°C
ADS43NB . . . . . . . . . . . . . . . . . . . . . . -40°C to +S5°C
AD843S . . . . . . . . . . . . . . . . . . . . . . . - 55°C to + 125°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C

NOTES
IStresses above those listed under "Absolute Maximum Ratings" may cause
pennanent damage to the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
28-Pin Plastic Package: aJA = lOO°ClWatt
8-Pin Cerdip Package: 6JA ~ IlO°ClWatt
12-Pin Header Package: BJA ~ 80°ClWatt
20-Pin LCC Package: QJA ~ ISO°ClWatt

METALIZA TION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (nun).

Vs

0.067

"r

REV.A

4

OPERATIONAL AMPLIFIERS 2-91

•

AD843 - Typical Characteristics

.

20

11 '5
~

,

IIIz
:!
III

!,

V

'0

g

I

./

i

V

TA =+25OC

,0
SUPPLY VOLTAGE -

V
o

zo

15
~

'5

II '0

V

'"g

!:i

30

V

/
V

/

II

:t15VSUPPLlE8

..........

/

TA = +25"C

j

o

,.

'0

20

~

o

Figure 1. Input Voltage Range
Supply Voltage

LOAD RESISTANCE -

Figure 2. Output Voltage Swing
vs. Supply Voltage

VS.

1k

'00

'0

SUPPLY VOLTAGE-::!: Volts

Volts

17'

'Ok

n

Figure 3. Output Voltage Swing
vs. Load Resistance

'00

15

-f--

VCM=O

Iof

!,

'"E '2

,

10
10- 1

!

I

..il •
z

i
~

I" .

'0-'

'0-"11_

Iof

0.'

AVCL = +1

10-"

•

10- 12
0

'0
SUPPLY VOLTAGE -

%.

Figure 4. Quiescent Current
Supply Voltage

11
I

\

1.0

1
U

i..
Ii!

0.8

'30

0.•

l!
0.4

0.2
-15

-10

,

1120

,

t: 110

~

+20 +40 +80 +80 +100 +120 +140

'Ok

100k

1M
FREQUENCV - Hz

""

-5
10
COMMON MODE VOLTAGE - Volts

Figure -7. Input Bias Current vs.
Common Mode Voltage

2-92 OPERA TIONAL AMPLIFIERS

''\

"

~

..... ~

i '00
u

90

+OUTPUT
CURRENT

t:

K eo
~:I:

on

~
ro-...

Ie

::l

I,

-OUTPUT
CURRENT

~ .......

~

10

so

..... r-..,

I,

I'\.
.......

50
15

-so

100M

~

~

T,.. = +25"C
WI....OUT
HEATStNK

10M

Figure 6. Output Impedance vs.
Frequency

Figure 5. Input Bias Current vs.
Junction Temperature

VS.

'40

\

U

JUNCTION TEMPERATURE _·C

1.4

'.2

oJ

0.01

-80 -40 -20

20

'5
Volts

-40

-20

0

+20 +40 +60 +80 +100 +120 +140

JUNCTION TEMPERATURE -

oc

Figure 8. Short Circuit Current
Limit vs. Junction Temperature (T)

25L--L~L--L

-60 -40

-20

0

__L--L__L--L__L--L~
+20 +40 +60 +80 +100 +120 +140

TEMPERATURE -

·c

Figure 9. Gain Bandwidth Product
vs. Temperature

REV. A

Typical Characteristics -AD843
'00

..

"0

92

'00
PHASE

IITT

.0

II j I

flloo
,

GAIN

~
....
§

"
Z

\

iii

1\
RI.""5OQfl

~20

,.

-20

'00

:1i

:I!

..
v,

88

~

20

i!;

IE

.,

100M

fII,

z

0

!
~

0

:I!

z

0

:I!
:I!

8

..

Vs

::

~

Vo "" Vs - 4V

~

•

= ::t;15V

,.

~

g~

I

5

~

o

::

~

,

+0

i

~

10

~
........

100M

lOOk

1M

10M

4

V-

Figure 13. Common Mode
Rejection vs. Frequency

10M

100M

SEE FIGURE 21

0.01%

0.1%

ERROR

0
0.01%

0.1%

-2

1\
\

\
\

-6
-B

.......

-1.
100M

~

I

60

10

"'-

80

FREQUENCY - Hz

FREQUENCY - Hz

,M

lOOk

-

V

I
I

... -4

~

10M

6

>
o
:;

~

20

1M

10k

~

~

+1

.\

5

100k

1JIlJW
,. 1

'00

Figure 12. Power Supply
Rejection vs. Frequency

''''' 500n
Vs = ±lSV
TA "" +25 ac

",

15

II

~

SINE WAVE APPLIED

FREQUENCY - Hz

AvcL

20

+SUPPlY

Vs= :!;15V
WITH 1V p-p

,.

~

r-.

-IS~IY

40

•

2.

15

:!: 25

so

10k

r-.

SUPPLY VOLTAGE - ~ Volts

I

~~

,.

.

I 2.

35

TA = +25'"C

'00

.0

t

ii:

lVp-p

.

~

= SOOU

Figure 11. Open Loop Gain vs.
Supply Voltage

IIII I

YCM

Z

0
RL

'00

'"

Figure 10. Open Loop Gain and
Phase Margin vs. Frequency

'00

~

v

~

-20

'20

/'

.,

84

10M

100k
1M
'Ok
FREQUENCY - Hz

/

~ 9

"

Z

oo

.. ,
.. " .
ir

\

f'..
90

r-- ....,..,
100

110

120

130

140

SETTLING TIME - ns

Figure 14. Large Signal Frequency
Response

Figure 15. Output Swing and
Error vs. Settling Time

'0.
2B.
-OOr-t--rrHr-t-~HH--r-~~--~-rH

VOUT "" 1.5V rms

I

~

-110

1-t--rrHr-t--,"'-=r'nOOfi--'--rl~-:;;o~-rH

-120

t:t:t~~t::t:~=!=+l~--~~

-, ••

1-t--rrHl-+-~HH--t-~~--~-rH

-140

'-~...J...u..'--'--'-J...U'-'-.J...J...LI._..w

ro

~

~

~

FREQUENCY - Hz

Figure 16. Harmonic Distortion vs.
Frequency

REV. A

'OOk

w

2"

~

220

~

i-""'"

........

-~

~ 260

~>
,

fII -'D. 1-t--rrHr-t--'-LJ.J--L--'-j~--~-tI'I

AVCL -

1

200

AVCI..= +1

"~D.J....L..U,OO~...J..U,.....-'-L..U,.......J....u.a.'oow.
• ...l.J..' ....
M.J....I..W
,OM
FREQUENCY - Hz

Figure 17. Input Noise Voltage Spectral
Density

18~60

I I
-40 -20

0

+20

+40 +60 +80 +100+120 +140

TEMPERATURE - OC

Figure 18. Slew Rate vs.
Temperature

OPERA TIONAL AMPLIFIERS 2-93

AD843
95

II

9.

L

~Vs=:t:15V

VO'''''/J ~O~ !.ov

85
I

~

i!;

g
z

~

0

SO

,.
.

L'
/

INPUT

I

4UkCI

j

6.
55

V

SQUARE
WAVE

Va= ;!:5V
Vo= ±1V

:1

"

--.n
_
- U-

-+--

1/

'Il

1.

1.

100

•••

LOAD RESISTANCE - U

Figure 19. Open Loop Gain vs.
Resistive Load

Figure 20c. Inverter Small Signal
Pulse Response. CF '" 0,
CL "'10pF

Figure 20a. Inverting Amplifier
Connection

Figure 20d. Inverter Large Signal
Pulse Response. CF = 5 pF,
CL =110pF

Figure 20b. Inverter Large Signal
Pulse Response. CF ' " 0,
CL ", 10pF

Figure 20e. Inverter Small Signal
Pulse Response. CF = 5 pF,
CL = 110pF

.kfi

JU-

C,
SQUARE ....---H------,

WAVE
INPUT

••0
49.90

SCOPE PROBE
INClUDi..
'Opf~
CAPACITANCE

. Figure 21a. Unity Gain Inverter
Circuit for Driving Capacitive
Loads
2-94 OPERA TIONAL AMPLIFIERS

Figure 21b. Inverter Cap Load
Large Signal Pulse Response.
CF = 15pF, CL = 410pF

Figure 21c. Inverter Cap Load
Small Signal Pulse Response.
CF = 15pF, CL =410pF

REV. A

AD843
SQUARE

WAVE

INPUT

v,.
RL

499H

r
CL

INCLUDES lOpF
SCOPE PROBE
CAPACITANCE

Figure 22a. Unity Gain Buffer
Amplifier

Figure 22b. Buffer Large Signal
Pulse Response. CL = 10 pF

Figure 22c. Buffer Small Signal
Pulse Response. CL = 10 pF

Figure 23b. Buffer Cap Load Large
Signal Pulse Response.
CF = 33 pF, CL = 10 pF

Figure 23c. Buffer Cap Load Small
Signal Pulse Response.
CF = 33 pF, CL = 10 pF

Figure 23d. Buffer Cap Load Large
Signal Pulse Response.
CF = 33 pF, CL = 110 pF

Figure 23e. Buffer Cap Load Small
Signal Pulse Response.
CF = 33pF, CL = 110pF

200n
CF 33pF

+---1
SQUARE
WAVE
INPUT

10U

49.til

l

0.1.'
C, 10pF
l...J"..... INCLUDES
~

2.2~

Your

"'-

49tH

SCOPE PROBE

CAPACITANCE

Figure 23a. Unity Gain Buffer
Circuit for Driving Capacitive
Loads

REV. A

OPERA TIONAL AMPLIFIERS 2-95

•

AD843
DRIVING CAPACITIVE LOADS
Like most high bandwidth amplifiers, the ADS43 is sensitive to
capacitive loading. Although it will drive capacitive loads up to
20 pF without degradation of its' rated perfonnance, both an
increased capacitive load drive capability and a "cleaner" (nonringing) pulse response "can be obtained from the ADS43 by
using the circuits illustrateQ.m Figures 20 to 23. The addition of
a 5 pF feedback capacitor to the unity gain .inverter connection
(Figure 20a ) sUbStantia!l.y reduces the .circuit's overshoot, even
when it is driving a 110 pF load. This can be seen by comparing
the waveforms of Figures 20b through 20e. To drive capacitive
loads greater than 100 pF, the load should be decoupled from
the amplifier's output by a 10 0 resistor and the feedback
capacitor, CF , should be connected directly between tile amplifier's output and its inverting input (Figure 21a). When using a
IS pF feedback capacitor, this circuit can drive 400 pF with less
than 20% overshoot, as illustrated in Figures 21b and 21c.
Increasing capacitor CF to 47 pF also increases the capacitance
drive capability to 1000 pF, at the expense of a 10:1 reduction
in bandwidth compared with the sinlple unity gain inverter circuit of Figure 20a.

GROUNDING AND BYPASSING
In designing practical circuits using the ADS43, the user must
.. keep in mind that some special precautions are needed when
dealing with high frequency signals. Circuits must be wired
using short interconnect leads. Ground planes should be used
whenever possible to provide both a lowtesistance, low inductance circuit path and to mininlize the effects of high frequency
coupling. IC sockets should be avoided, since their increased
interlead capacitance can degrade the bandwidth of the device.
Power supply leads should be bypassed to ground as close as
possible to the pins of the amplifier. Again, the component leads
should be kept very short. As shown in Figure 24, a parallel
combination of a 2.2 I1F tantalum and a 0.1 I1F ceramic disc
capacitor is recommended.

Unity gain voltage followers (buffers) are more sensitive to
capacitive loads than are inverting amplifiers because there is no
attenUation of the feedback signal. The AD843 can drive 10 pF
to 20 pF when connected in the basic unity gain' buffer circuit
of Figure 22a.
The 1 kG resistor in series with the ADS43's noninverting input
serves two functions: first, together with the amplifier's input
capacitance, it forms a low pass mter which slows down the
actual signal seen by the ADS43. This helps reduce ringing on
the amplifier's output voltage. The resistor's second function is
to limit the current into the amplifier when the differential input
voltage exceeds the total supply voltage.
The ADS43 will deliver a much "cleaner" pulse response when.
connected in the somewhat more elaborate follower circuit of
Figure 23a. Note the reduced overshoot in Figure 23b and 23c
as compared to Figure 22b and 22c.
For maximum bandwidth, in most applications, input and feedback resistors used with the ADS43 should h&',e.resistance valUeS equal to or less than 1.5 kO. Even with these Jow resistance
v!i1ue~, the resultant RC time constant formed between them
and stray circuit capacitances is large enough to cause peaking in
the amplifier's response. Adding a small capacitor, CF , as shown
in Figures 20a to 23a will reduce this peaking and flatten the
overall frequency response. CF will norrnallybe less than 10 pF
in value.
.

Figure 24. Recommended Power Supply Bypassing for
the AD843 (DIP Pinout)

USING A HEAT SINK
The ADS43 consumes less quiescent power than most precision
high speed amplifiers and is specified to operate without using a
heat sink. However, when driving low inlpedance loads, the current applied to the load can be 4 to 5 times greater than the quiescent current. This will produce a noticeable temperatUre rise,
which will increase input bias currents. The use of a small heat
sink, such as the Mouser Electronics #33HSOOS is recommended.

The ADS43 can di"ive resistive loads over. the range of 500 0 to
00 with no change in dynamic respop.se. While a 499 o load was
used in the circuits of Figures 20-23, the perfonnance of these
circuits will be essentially the same even if this load is removed
or changed to some other value, such as 2 kO.
To obtain the "cleanest" possible transient response when driving heavy capacitive loads, be sure to connect bypass capacitors
directly between the power supply pins of the ADS43 and
ground as outlined in "grounding and bypassing."

Offset Null Configuration (DIP Pinout)

2-96 OPERATIONAL AMPLIFIERS

REV. A

AD843
SAMPLE-AND-HOLD AMPLIFIER CIRCUITS
A Fast Switching Sample & Hold Circuit
A sample-and-hold circuit possessing short acquisition time and
low aperture delay can be built using an AD843 and discrete
JFET switches. The circuit of Figure 25 employs five n-channel
JFETs (with turn-on times of 35 ns) and an AD843 op amp
(which can settle to 0.01 % in 135 ns). The circuit has an aperture delay time of 50 ns and an acquisition time of I jJ.S or less.
This circuit is based on a noninverting open loop architecture,
using a differential hold capacitor to reduce the effects of pedestal error. The charge that is removed from CHI by Q2 and Q3
is offset by the charge removed from CH2 by Q4 and Q5. This
circuit can tolerate low hold capacitor values (approximately
100 pF), which improve acquisition time, due to the small gateto-drain capacitance of the discrete JFETs. Although pedestal
error will vary with input signal level, making trimming more
difficult, the circuit has the advantages of high bandwidth and
short acquisition times. In addition, it will exhibit some nonlinearity because both amplifiers are operating with a common
mode input. Amplifier A2, however, contributes less than
0.025% linearity error, due to its 72 dB common mode rejection
ratio.

HOLD

~ 03

To make sure the circuit accommodates a wide ± 10 V input
range, the gates of the JFETs must be connected to a potential
near the -IS V supply. The level-shift circuitry (diode D3,
PNP transistor Q7, and NPN transistor Q6) shifts the TTLlevel SIH command to provide for an adequate pinch-off voltage
for the JFET switches over the full input voltage range.
The JFETs Q2, Q3, Q4 and Q5 across the two hold capacitors
ensure signal acquisition for all conditions of VIN and VOUT
when the circuit switches from the sample to the hold mode.
Transistor QI provides an extra stage of isolation between the
output of amplifier Al and the hold capacitor CHI.
When selecting capacitors for use in a sample-and-hold circuit,
the designer should choose those types with low dielectric
absorption and low temperature coefficients. Silvered-mica
capacitors exhibit low (0 to 100 ppm/"C) temperature coefficients
and will still work in temperatures exceeding 200°C. It is also
recommend that the user test the chosen capacitor to insure
that its value closely matches that printed on it since not all
capacitors are fully tested by their manufacturers for absolute
tolerance.

soon
01

02

~ lN~4K14r8~~_6~.~2k{~1~~~::1N_4D1~4_8~1~N~4_14_8-e______________-e____~2~.~1k~n~
SAMPLE

.......----....- -15V

Figure 25. A Fast Switching Sample-and-Hold Amplifier

REV. A

OPERA TIONAL AMPLIFIERS 2-97

II

AD843
A PING-PONG SIll AMPLIFIER
For improved throughput over the circuit of Figure 25, a "pingpong" architecture may be used. A ping-pong circuit overcomes
some of the problems associated with high speed SIH amplifiers
by allowing the use of a larger hold capacitor for a given sample
rate: this will reduce the associated feedthrough, droop and pedestal errors.

output is connected to the input of the AID converter. When .
the select command goes to logic LOW, the two output amplifiers alternate functions.

Figure 26 illustrates a simple, four-chip ping-pong sample-andhold amplifier circuit. This design increases throughput by
using one channel to acquire a new sample while another channel holds the previous sample. Instead of having to reacquire the
signal when switching from hold to sample mode, it alternately
connects the outputs from Channel I or from Channel 2 to the
AID converter. In this case, the throughput is the slew rate and
settling time of the output amplifiers, A2 and A3.
A high speed CB amplifier, AI, follows the input signal. VI, a
dual wide-band "T" switch, connects the input buffer amp to
one of the two output amplifiers while selecting the complementary amplifier to drive the AID input. For example, when
"select" is at logic high, Al drives CHI, A2 tracks the input
signal and the output of A3 is connected to the input of the AID
converter. At the same time, A3 holds an analog value and its

Since the input to the AID converter is the alternated "held"
outputs from Al and A2, the offset voltage mismatch of the two
amplifiers will show up as nonlinearity and, therefore, distortion
in the output signal. To minimize this, potentiometers can be
used to adjust the offsets of the output amplifiers until they are
equal. Alternatively, an autocalibration circuit using two D/A
converters can be employed. This can also be used to calibrateout the effects of offset voltage drift over temperature.
The switch choice, for VI, is critical in this type of design. The
DG542 utilizes "T" switching techniques on each channel for
exceptionally low crosstalk and for high isolation. The part further improves these specifications by using ground pins between
the signal pins. With an input frequency of 5 MHz, crosstalk
and isolation are - 85 dB and -75 dB, respectively. A limitation
of this switch is that it operates from a maximum - 5 V negative
supply, making bipolar operation more difficult. It is recommended that amplifiers AI, A2 and A3 operate from the same
- 5 V supply to minimize any potential latch-up problems.

+5V

U1

SELECT

~

IN1
D1

+5V

GND
S1

:!:3V

IN2
D2
GND
S2

DG542DJ

S4
GND
D4

.

+5V
OUTPUT
TO
AID
CONVERTER

S3
GND
D3

~CHANNEL'

~7
~
~HANNEL2
EQUIVALENT
SIMPLIFIED
DIAGRAM

'::'

~7

FOR AMPLIFIERS A1 TO A3,
ADD BYPASS CAPACITORS
TO EACH POWER SUPPLY PIN
AS SHOWN IN FIGURE 24

Figure 26. A Ping-Pong Sample-and-Hold Amplifier

2-98 OPERA TIONAL AMPLIFIERS

REV. A

Applying the AD843
TO TEKTRONIX
1kO

9kO

tl

r - - - -.,

7A26
II 1
OSCILLOSCOPE

20 II

T
L ____

:~::ECTION I MO

pF I
(VIA LESS THAN
....J
1FT. 500
..
COAXIAL CABLE) VERROR X 5
2500

2x
HP2835

II

0.47"'F~_VS
112 VERROR
1kO

1kO

NOTE
USE CIRCUIT BOARD
WITH GROUND PLANE

1000

r
I

-;~T::;:O-;

-

PULSE

1kO

1

I

:

GENERAT~O~ J.. V

I

DATA
DYNAMICS
5109
OR.
EQUIVALENT

,N

I
I
I
I
I

L _____ -'

2.2"F~

Figure 27. Settling Time Test Circuit

MEASURING AD843 SETTLING TIME
Figure 28 shows the dynamic response of the AD843 while
operating in the settling time test circuit of Figure 27. The
input of the settling time fixture is driven by a flat-top pulse
generator. The error signal output from AI, the AD843 under
test, is amplified by op amp A2 and then clamped by two high
speed Schottky diodes.

I:

.I .i

~

t-

~
I

: r

'50,(S

t-

~

The error signal is clamped to prevent it from greatly overloading the oscilloscope preamp. A Tektronix oscilloscope preamp
type 7A26 was chosen because it will recover from the approximately 0.4 volt overload, quickly enough to allow accurate measurement of the AD843's 13S ns settling time. Amplifier A2 is a
very high speed op amp; it provides a voltage gain of 10, providing a total gain of S from the error signal to the oscilloscope
input.
Figure 28. Settling Characteristics: + 10 V to 0 V Step.
Upper Trace: Amplified Error Voltage (0.01%IDiv)
Lower Trace: Output of AD843 Under Test (5 VIDiv)

REV. A

OPERA TIONALAMPLIFIERS 2-99

AD843 - Applications Circuit
A FAST PEAK DETECTOR CIRCUIT
The peak detector circuit of Figure 29, can accurately capture
the amplitude of input pulses as narrow as 200 ns and can hold
their value with a droop rate of less than 20 fJ.V/fJ.s. This circuit
will capture the peak value of positive polarity waveforms; to
detect negative peaks, simply reverse the polarity of the two
diodes.
The high bandwidth and 200 V/fJ.s slew rate of amplifier A2, an
AD843, allows the detector's output to "keep up" with its input
thus minimizing overshoot. The low « I nA) input current of
the AD843 ensures that the droop rate is limited only by the
reverse leakage of diode D2, which is typically <10 nA for the
type shown. The low droop rate is apparent in Figure 30. The

detector's output (top trace) loses slightly over a volt of the 8
volt peak input value (bottom trace) in 75 ms, or a rate of
approximately 16 ILVIlLS
Amplifier AI, an AD847, can drive 680 pF hold capacitor, Cp ,
fast enough to "catch-up" with the next peak in 100 ns and still
settle to the new value in 250 ns, as illustrated in Figure 31.
Reducing the value of capacitor Cp to 100 pF will maximize the
speed of this circuit at the expense of increased overshoot and
droop. Since the AD847 can drive an arbitrarily large value of
capacitance, Cp can be increased to reduce droop, at the expense
of response time.

1kO

VON

1kO

-Vs

Figure 29. A Fast Peak Detector Circuit

OV

OV

TOP TRACE: PEAK DETECTOR OUTPUT

TOP TRACE: PEAK DETECTOR OUTPUT. 8V

BOTTOM TRACE: INPUT. 8V PEAK

BOTTOM TRACE: INPUT VOLTAGE. 8V PEAK.
650n5 PULSE WIDTH

(a

125Hz

Figure 30. Peak Detector Response to 125 Hz Pulse Train

2-100 OPERATIONALAMPLIFIERS

Figure 31. Peak Capture Time

REV. A

60MHz,2000V/fJ.S
Monolithic Op Amp
AD844 I

11IIIIIIII ANALOG
WDEVICES
FEATURES
Wide Bandwidth: 60MHz at Gain of-1
33MHz at Gain of -10
Very High Output Slew Rate: Up to 2000V/IJ.s
20MHz Full Power Bandwidth, 20V pk-pk, RL =soon
Fast Settling: 100ns to 0.1% (10V Step)
Differential Gain Error: 0.03% at 4.4MHz
Differential Phase Error: 0.15° at 4.4MHz
High Output Drive: ±SOmA into son Load
Low Offset Voltage: 1S0IJ.V max (B Grade)
Low Quiescent Current: 6.SmA
APPLICATIONS
Flash ADC Input Amplifiers
High Speed Current DAC Interfaces
Video Buffers and Cable Drivers
Pulse Amplifiers

PRODUCT DESCRIPTION
The AD844 is a high speed monolithic operational amplifier fabricated using Analog Devices' junction isolated complementary
bipolar (CB) process. It combines high bandwidth and very fast
large signal response with excellent dc performance. Although
optimized for use in current to voltage applications and as an
inverting mode amplifier, it is also suitable for use in many noninverting applications.

CONNECTION DIAGRAM
8-Pin
Plastic (N),
and Cerdip (Q)
Packages

16-Pin SOIC
(R) Package

PRODUCT HIGHLIGHTS
1. The AD844 is a versatile, low cost component providing an
excellent combination of ac and dc performance. It may be
used as an alternative to the EL2020 and CLC400/1.
2. It is essentially free from slew rate limitations. Rise and fall
times are essentially independent of output level.
3. The AD844 can be operated from ±4.SV to ± 18V power
supplies and is capable of driving loads down to 500, as
well as driving very large capacitive loads using an external
network.

The AD844 can be used in place of traditional op amps, but its
current feedback architecture results in much better ac performance, high linearity and an exceptionally clean pulse response.

4. The offset voltage and input bias currents of the AD844 are
laser trimmed to minimize dc errors; Vos drift is typically
1".vrC and bias current drift is typically 9nArC.

This type of op amp provides a closed-loop bandwidth which is
determined primarily by the feedback resistor and is almost independent of the closed-loop gain. The AD844 is free from the
slew rate limitations inherent in traditional op amps and other
current-feedback op amps. Peak output rate of change can be
over 2000V/jLs for a full 20V output step. Settling time is typically lOOns to 0.1 %, and essentially independent of gain. The
AD844 can drive 500 loads to ±2.SV with low distortion and is
short circuit protected to 80mA.

5. The AD844 exhibits excellent differential gain and differential phase characteristics, making it suitable for a variety of
video applications with bandwidths up to 60MHz.
6. The AD844 combines low distortion, low noise and low drift
with wide bandwidth, making it outstanding as an input amplifier for flash AID converters.

The AD844 is available in four performance grades and three
package options. In the 16-pin SOIC (R) package, the AD844J
is specified for the commercial temperature range of 0 to + 70°C.
The AD844A and AD844B are specified for the industrial
temperature range of -40°C to +8S oC and are available in the
cerdip (Q) package. The AD844A is also available in an 8-pin
plastic mini-DIP (N). The AD844S is specified over the military
temperature range of - 55°C to + 125°C and is available in the
cerdip (Q) package. "A" and "S" grade chips and devices processed to MIL-STD-883B, REV. C are also available.

REV. A

OPERATIONALAMPLIFIERS 2-101

II

AD844-SPECIFICATIONS

(@ TA+"25OC and Vs=±15V dc, unless otherwise noted)
AD844B

AD844J/A

Model
INPUT OFFSET VOLTAGE'
Tmin-Tmax
vs. Temperature
vs. Supply
Initial
Tmin-T ....
vs. Common Mode
Initial
Tmin-T ....
INPUT BIAS CURRENT
- Input Bias Current'
Tmin-Tmax
vs. Temperature
vs. Supply
Initial
Tmin-T""",
vs. Common Mode
Initial
Tmin-T"""
+Input Bias Current'
Tmin-Tmax
vs. Temperature
vs. Supply
Initial
Tmin-T""",
vs. Common Mode
Initial
Tmin-T""",

Conditious

Min

Typ

Max

50
75
1

300
500

4
4

Min

AD844S

Typ

Max

50

ISO

Min

Typ

Max

Units

300
SOO
5

ILV
ILV
ILVI"C

is

zoo

1

5

50
125
1

ZO

4
4

10
10

4
4

20
20

ILVN
ILVN

10
10

35

10
10

20
ZO

10
10

35
35

ILVN
ILVN

200
SOO
9

4SO
1500

150
750
9

2SO
1100
15

200
1900
20

4SO
Z500
30

nA
nA
nAf'C

175
220

ZSO

175
220

ZOO
240

175
220

ZSO
300

nAN
nAN

90
llO
150
350
3

160

90
llO
100
300
3

110
ISO
ZOO
500
7

90
120
100
SOO
7

160
200
400
1300
15

nAN
nAN
nA
nA

5V-lSV

VCM =±10V

5V-lSV

VcM =±10V

400
700

nAl'C

5V-lSV
SO
100

ISO

SO
100

100
120

SO
120

ISO
ZOO

nAN
nAN

90
130

ISO

90
130

120
190

90
140

ISO
200

nAN
nAN

SO
10

65

SO
10

65

SO
10

65

{}

VcM =±IOV

INPUT CHARACTERISTICS
Input Resistance
-Input
+ InpUt
Input. Capacitance
-Input
+Input
Input Voltage Range
Common Mode

7

7

2
2

2
2
±10

±10

7

2
2

M{}
pF
pF
V

±10

INPUT VOLTAGE NOISE

f~lkHz

2

2

2

nVlYHz

INPUT CURRENT NOISE
-Input
+ Input

f~lkHz

10
12

10
12

10
12

pAlYHz
pAlYHz

3.0
1.6
4.5

MO
M{}
pF

OPEN LOOP TRANSRESISTANCE

f~lkHz

VoUT -±10V
R LoAD =5000

Tmin-Tm ",
TranscapacitaDce

Z.Z
1.3

3.0
2.0
4.5

Z.8
1.6

3.0
2.0
4.5

Z.Z

1.3

DIFFERENTIAL GAIN ERROR2

f-4.4MHz

0.03

0.03

0.03

%

DIFFERENTIAL PHASE ERROR2

f=4.4MHz

0.15

0.15

0.15

Degree

60
33

60
33

60
33

MHz
MHz

0.005

0.005

0.005

%

100
100

100
100

100
100

ns
ns

llO
100

llO
100

llO
100

ns
ns

FREQUENCY RESPONSE
SmaIl Signal Bandwidth
'Gain=-1
4Gain=-10
TOTAL HARMOMIC DISTORTION

f-l00kHz,
2V rms5

SETTLING TIME
10V Output Step.
Gain=-I, to 0.1%5
Gain=-10, to 0.1%6
2V Output Step
Gain=-I, to 0.1%5
Gain= -10, to 0.1%6

2-102 OPERATIONAL AMPLIFIERS

± 15V Supplies

±5V Supplies

REV. A

AD844
AD844J/A
Typ
Max

Model

Conditions

Min

OUTPUT SLEW RATE

Overdriven
Input

1200 2000

FULL POWER BANDWIDTH
VOUT=20V pop'
VOUT=2V pop'
OUTPUT CHARACTERISTICS
Voltage
Shon Circuit Current
T_-Tmax
Output Resistance

6.5
7.5

±IS
7.S
S.S

AD844S
Typ
Max

1200 2000

Units
V/",s

20
20

II

10

SO
60
IS
±4.S

Min

20
20

II

10

Open Loop

POWER SUPPLY
Operating Range
Quiescent Current
T_-Tmax

1200 2000

20
20

Vs=±ISV
Vs=±SV
THD=3%
RLOAO=soon

AD844B
Typ
Max

Min

MHz
MHz

II

±V

SO

SO

60

60

rnA
rnA

IS

IS

n

±4.S
6.5
7.5

10

±IS
7.S
S.S

±4.S
6.5
S.S

±IS
7.S
9.S

V
rnA
rnA

NOTES
'Rated perfonnance after a 5 minute warmup at T" =25"C.
'Input signal 285mV pop carrier (40 IRE) riding on 0 to 642mV (90 IRE) ramp. RL = lOon; RI, R2=30OO.
'Input signal OdBm, CL=10pF, RL =5000, RI=500n, R2=500n in Figure 26.
'Input signal OdBm, CL=lOpF, RL =5000, RI=500n, R2=50n in Figure 26.
'CL=IOpF, RL =5000, Rl=lkn, R2=lkn in Figure 26.
'CL=lOpF, RL =5000, Rl=50OO, R2=50n in Figure 26.
Specifications subject to change without notice. All min and max specifications are guaranteed.
Specifications shown in boldface are tested on all production units at final electrical test.

ABSOLUTE MAXIMUM RATINGS!
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ±lSV
Power Dissipation2 • • • • • • • • • • • • • • • • • • • • • • • • • 1.1 W
Output Shon Circuit Duration . . . . . . . . . . . . . . . Indefinite
Common Mode Input Voltage . . . . . . . . . . . . . . . . . . . ±Vs
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . 6V
Inverting Input Current
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SmA
Transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • lOrnA
Storage Temperature Range Q . . . . . . . . . . -65°C to + 150°C
N, R . . . . . . • . -65°C to + 125°C
Lead Temperature Range (Soldering 60sec) . . . . . . . . +300"C
NOTES
IStresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
'8-Pin Plastic Package: OJA = IOO'CIWatt
8-Pin Cerdip Package: OJA = 1I0'CIWatt
16-Pin SOIC Package: OJA = 100'CIWatt

MET~TIONPHOTOG~
Contact factory for latest dimensions.

Dimensions shown in inches and (mm).
-IN

0.076
(1.9)

l~~
I.
SUBSTRATE CONNECTED

ORDERING GUIDE!

TO +V.

Model!

Temperature
Range

Package
Option2

ADS44JR
ADS44AN
ADS44AQ
ADS44BQ
ADS44SQ
ADS44SQ/SS3B

O°C to +70°C
-40°C to +SsoC
-40°C to +SsoC
-40°C to +SsoC
- 55°C to + 125°C
- 55°C to + 125°C

R-16
N-S
Q-S
Q-S
Q-S
Q-S

NOTES
S"'A" and "S" grade chips are also available.
'N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC). For outline
information see Package Information section.

REV. A

OPERATIONALAMPLIFIERS 2-103

II

AD844-Typical Characteristics (T =+25°C and Vs=±15V unless otherwise noted)
A

-00

70

"... I--

-70

./

/

/'

/

!fI,

/

Z

i

-80

lVrms

3

~

-90

~

-100

:1:..,.110

40

o

'0

20

'5

I ,.I

-'30

, ..

~

[iRDiM~NII

~
,00k

'Ok
INPUT FREQUENCY - Hz

SUPPLY VOLTAGE - '£:V

,

~

2ND HARMONIC
-120

30

/'

C5

I

50

V

/' , / , / f..--'"

Ra.=soon

,.......

1\=50.11

-

,..f.-

..

..

..

,

,

TEMPERATURE -

oc

Figure 3. Transresistance
VS. Temperature

Figure 2. Harmonic Distortion
VS. Frequency, R 1 = R2 = 1k(}'

Figure 1. -3dB Bandwidth vs.
Supply Voltage R1 =R2=500(}'

20

rj"

('"

'0

20

/

V

/

/

f\.=500U
+Z5°C

/..c
V

,. /

/

V

/

/
Vs=±16V

~
./

):::: .
",

.,.

./

I-' ~

V
V V
Vr±5V

./

V

.'.
10

20

10
15
SUPPLY VOLTAGE -'±Volts

15

20

-110 -40 -20

0

SUPPLY VOLTAGE - :!!Volts

Figure 5. Output Voltage Swing

Figure 4. Noninverting Input VCfltage
Swing vs. Supply Voltage

+20 +40

+60 +80 +100 +120 +140

TEMPERATURE -

oc

Figure 6. Quiescent Supply Current
vs. Temperature and Supply Voltage

VB. Supply Voltage

.

'00

-JJ-

35

'0

"1, '

I

t,
G

0

i

-2
-50

I--

--

~

-V

/

I..

''\

50

TEMPERATURE -

0.'

oc

..

,

~

.7~

/

25

-r-

Vs=±5V

20

15

,..

Figure 7. Inverting Input Bias Current (lSN) and Noninverting Input
Bias Current (lsp) vs. Temperature

2-104 OPERA TIONAL AMPLIFIERS

-

30

~

+5V VOLT SUPPLIES

.............

r---.

~

0.01
'Ok

lOOk

'M

'OM

'OOm

FREQUENCY - Hz

Figure 8. Output Impedance
vs. Frequency, Gain=-1,. R1 =R2= 1k(}'

'0
-60 -40 -20

0

+20 +40 +60 +80 +100 +120+140

TEMPERATURE -

oc

. Figure 9. -3dB Bandwidth vs.
Temperature, Gain=-1,
R1=R2=1k()'

REV. A

AD844
Inverting Gain of 1 AC Characteristics
••

+v.

-.ao

R'~R2="'"

ld--,J
11\ \

4.70

~~
...... ....... ......

-210

......

'\

R1=RZ=11cQ

I

R2

-I

VOUT

I--

\

I

I-..

I

J-270

-24

Figure 10. Inverting Amplifier,
Gain of -1 (R1 =R2)

R1""IQ=1kn

-300

....

-v.

R1=R2=5000

"'

'r-...
........

..

-330
100M

1M
10M
FREQUENCY - Hz

•

"\
II
1"-.. .......

I

-II

""-I,

0

50

FREQUENCY - MHz

Figure 12. Phase vs. Frequency
Gain=-1, RL =500n, CL=OpF

Figure 11. Gain vs. Frequency for
Gain = -1, RL =500n, CL=OpF

T

I

Figure 14. Small Signal Pulse
Response, Gain=-1, R1=R2=1kn

Figure 13. Large Signal Pulse
Response, Gain=-1, R1=R2=1kn

Inverting Gain of 10 AC Characteristics

.
.

... ~

-

RL=5DOR

I..::::::

~

..:.....

,'I

~

I
~

\

-210

r'\

I-I

Figure 15. Gain of -10 Amplifier

REV. A

--,...

1M
10M
FREQUENCY - Hz

Figure 16. Gain vs. Frequency,
Gain=-10

r\.

[\, !"I.. .... =.....

,(

-300

-v.

"r\:

.....,K, "-

)

1-270
-330

~ ......

......
o

••

,
l"I'-.

FREOUENCY - MHz

'0

Figure 17. Phase vs. Frequency,
Gain=-10

OPERA TIONALAMPLIFIERS 2-105

AD844
Inverting Gain of 10 Pulse Response

T

I

Figure 18. Large Signal Pulse
Response, Gain=-10, RL =500n

Figure 19. Small Signal Pulse
Response, Gain=-10, RL =500n

Noninverting Gain of 10 AC Characteristics

.
'"},

20
",

8 ' ", ,

"

\[\

...

i-

,

i\=soou

"

V

'\ ~

240

~" r--...
II

27o

RL =50fl

0

,.

~

r-....
r-.... ....
50

FRt:aUENCY - MHz

Figure 21. Gain vs. Frequency,
Gain=+10

Figure 23. Noninverting Amplifier Large Signal
Pulse Response, Gain = + 10, RL =500n

,~

-300

100M

10M

~

\

-330
1M

FREQUENCY - Hz

2-106 OPERATIONAL AMPLIFIERS

1-,

1\

",

2

•,

-210

\\

,

"""'= ~

RL~~

Rc="" I\\,

•

Figure 20. Noninverting Gain of
+ 10 Amplifier

-'50

I

Figure 22. Phase vs. Frequency,
Gain=+10

Figure 24. Small Signal Pulse
Response, Gain = + 10, RL =500n

REV. A

AD844
UNDERSTANDING THE AD844
The AD844 can be used in ways similar to a conventional op
amp while providing performance advantages in wideband applications. However, there are important differences in the internal
structure which need to be understood in order to optimize the
performance of the AD844 op amp.
Open Loop Behavior
Figure 25 shows a current feedback amplifier reduced to essentials. Sources of fixed dc errors such as the inverting node bias
current and the offset voltage are excluded from this model and
are discussed later. The most important parameter limiting the
dc gain is the transresistance, Rt, which is ideally infinite. A
finite value of Rt is analogous to the finite open loop voltage
gain in a conventional op amp.
The current applied to the inverting input node is replicated by
the current conveyor so as to flow in resistor Rt. The voltage
developed across Rt is buffered by the unity gain voltage follower. Voltage gain is the ratio Rtf R'N' With typical values of
Rt=3MO and R IN =500, the voltage gain is about 60,000. The
open loop current gain is another measure of gain and is determined by the beta product of the transistors in the voltage follower stage (see Figure 28); it is typically 40,000.

The closed loop transresistance is simply the parallel sum of RI
and Rt. Since RI will generally be in the range 5000 to 2kO
and Rt is about 3MO the closed loop transresistance will be only
0.02% to 0.07% lower than Rl. This small error will often be
less than the resistor tolerance.
When RI is fairly large (above SkO) but still much less than Rt,
the closed loop HF response is dominated by the time constant
RICt. Under such conditions the AD844 is over-damped and
will provide only a fraction of its bandwidth potential. Because
of the absence of slew rate limitations under these conditions,
the circuit will exhibit a simple single pole response even under
large signal conditions.
In Figure 26, R3 is used to properly terminate the input if desired. R3 in parallel with R2 gives the terminated resistance. As
RI is lowered, the signal bandwidth increases, but the time constant RICt becomes comparable to higher order poles in the
closed loop response. Therefore, the closed loop response becomes complex, and the pulse response shows overshoot. When
R2 is much larger than the input resistance, R'N' at Pin 2, most
of the feedback current in Rl is delivered to this input; but as
R2 becomes comparable to R IN , less of the feedback is absorbed
at Pin 2, resulting in more heavily damped response. Consequently, for low values of R2 it is possible to lower RI without
causing instability in the closed loop response. Table I lists combinations of RI and R2 and the resulting frequency response for
the circuit of Figure 26. Figure 13 shows the very clean and fast
± 10V pulse response of the AD844.

a

Rt

Figure 25. Equivalent Schematic
The important parameters defining ac behavior are the transcapacitance, Ct, and the external feedback resistor (not shown).
The time constant formed by these components is analogous to
the dominant pole of a conventional op amp, and thus cannot be
reduced below a critical value if the closed loop system is to be
stable. In practice, Ct is held to as Iowa value as possible (typically 4.5pF) so that the feedback resistor can be maximized
while maintaining a fast response. The finite R'N also affects the
closed loop response in some applications as will be shown.
The open loop ac gain is also best understood in terms of the
transimpedance rather than as an open loop voltage gain. The
open loop pole is formed by Rt in parallel with Ct. Since Ct is
typically 4.5pF, the open loop comer frequency occurs at about
12kHz. However, this parameter is of little value in determining
the closed loop response.
Response as an Inverting AmpUfier
Figure 26 shows the connections for an inverting ampUfier.
Unlike a conventional ampUfier the transient response and the
sma11 signal bandwidth are detenhlned primarily by the value of
the external feedback resistor, RI, rather than by the ratio of
RIIR2 as is customarily the case in an op amp application. This
is a direct result of the low impedance at the inverting input. As
with conventional op amps, the closed loop gain is - RIIR2.

REV. A

R3
OPTIONAL

>-"-"'--1~VOUT

'-----t

CL

Figure 26. Inverting Amplifier

Gain

Rl

R2

-I
-I
-2
-2
-5
-5
-10
-10
-20
-100
+100

IkO
5000
2kO
IkO
5kO
5000
lkn
5000
Ikn
SkO
SkO

IkO
5000
IkO
5000
IkO
1000

1000
500
500
500
500

BW(MHz)

GBW(MHz)

35
60
IS
30
5.2
49
23
33
21
3.2
9

35
60
30
60
26
245
230
330
420
320

900

Table I.

OPERATIONALAMPLIFIERS 2-107

•

AD844
Response as an I~V Converter
The AD844 works well as the active element in an operational
current to voltage converter, used in conjunction with an external scaling resistor, RI, in Figure 27. This analysis includes the
stray capacitance, Cs , of the cUrrent source, which might be a
high speed DAC. Using a conventional op amp, this capacitance
forms a "nuisance pole" with RJ. which destabilizes the closed
loop response of the system. Most op amps are internally compensated for the fastest response at unity gain, so the pole due
to RI and Cs redU<;e8 the already narrow phase margin of the
system. For example, if RI were 2.SkO a Cs of ISpF would
place this pole at a frequency of about 4MHz, well within the
response range of even a medium speed operatioIial amplifier. In
a current feedback amp this nuisance pole is no longer determined by RI but by the input resistance, R IN . Since this is
about SOO for the AD844, the same ISpF forms a pole 212MHz
and causes little trouble. It can be shown that the response of
this system is:
KRI
VOUT = -Isig (l+sTd)(1+sTn)
where K is a factor very close to unity and represents the finite
dc gain of the amplifier, Td is the dominant pole and Tn is the
nuisance pole:
Rt
K = Rt+RI
Td = KRICt
Tn = RINCS

(assuming RIN

«

RI)

Using typical values ofRI=lkO and Rt=3MO, K is 0.9997; in
other words, the "gain error" is only 0.03%. This is much less
than the scaling error of virtually all DACs and can be
absorbed, if necesS8ty, by the trim needed in a precise system.
In the AD844, Rt is fairly stable with temperature and supply
voltages, and consequently the effect of fmite "gain" is negligible unless high value feedback resistors are used. Since that
would result in slower response times than are possible, the relatively low value of Rt in the AD844 will rarely be a significant
source of error.

>-.......- V O U T

Figure 27. Current to Voltage Converter
Circuit Description of the AD844
A simplified schematic is shown in Figure 28. The AD844 differs from a conventional op amp in that the signal inputs have
radically different impedance. The noninverting input (Pin 3)
presents the usual high impedance. The voltage on this input is
transferred to the inverting input (Pin 2) with a low offset voltage, ensured by the close matching of like polarity transistors

2-108 OPERATIONALAMPLIFIERS

Figure 28. Simplified Schematic
operating under essentially identical bias conditions. Laser trimming nulls the residual offset voltage, down to a few tens of microvolts. The inverting input is the common emitter node of a.
complementary pair of grounded base stages and behaves as a
current summing node. IQ an ideal current feedback op amp the
input resistance would be zero. In the AD844 it is about SOO.
A current applied to the inverting input is transferred to a complementary pair of unity-gain current mirrors which deliver the
same current to an internal node (Pin S) at which the full output
voltage is generated. The unity-gain complementary voltage follower then buffers this voltage and provides the load driving
power. This buffer is designed to drive low impedance loads
such as terminated cables, and can deliver ±SOmA into a SOO
load while maintaining low distortion, even when operating at
supply voltages of only ±6V. Current limiting (not shown) ensures. safe operation under short circuited conditions.

It is important to understand that the low input impedance at
the inverting input is locally generated, and does not depend on
feedback. This is very different from the "virtual ground" of a
conventional operational amplifier used in the current summing
mode which is essentially an open circuit until the loop settles.
In the AD844, transient current at the input does not cause
voltage spikes at the summing node while the amplifier is setding. Furthermore, .all of the transient current is delivered to
the slewing (TZ) node (Pin S) via a short signal path (the
grounded base stages and the wideband current mirrors).
The current available to charge the capacitance (about.4.SpF)
at TZ node, is always proportional to the input error current, and
the slew rate limitations associated with the large signal response
of op amps do not occur. For this reason, the rise and fall
times are almost independent of signal level. In practice, the
input current will eventually cause the mirrors to saturate.
When using ± lSV supplies, this occurs at about 10mA (or
±2200Vll1s). Since signal currents are rarely this large, classical
"slew rate" limitations are absent.
This inherent advantage would be lost if the voltage follower
used to buffer the output were to have slew rate limitations: The
AD844 has been designed to avoid this problem, arid as a result
the output buffer exhibits a clean large signal traIisient response,
free from anomalous effects arising from internal saturation.

REV. A

Applying the AD844
Response as a Noninverting Amplifier
Since current feedback amplifiers are asymmetrical with regard
to their two inputs, performance will differ markedly in noninverting and inverting modes. In noninverting modes, the large
signal high speed behavior of the AD844 deteriorates at low
gains because the biasing circuitry for the input system (not
shown in Figure 28) is not designed to provide high input voltage slew rates.
However, good results can be obtained with some care. The
noninverting i.nput will not tolerate a large transient input; it
must be kept below ± 1V for best results. Consequently this
mode is better suited to high gain applications (greater than
x 10). Figure 20 shows a noninverting amplifier with a gain of
10 and a bandwidth of 30MHz. The transient response is shown
in Figures 23 and 24. To increase the bandwidth at higher
gains, a capacitor can be added across R2 whose value is approximately the ratio of R1 and R2 times Ct.

4.70

4.70

Figure 29. Noninverting Amplifier Gain = 100, Optional
Offset Trim Is Shown

Noninverting Gain of 100
The AD844 provides very clean pulse response at high noninverting gains. Figure 29 shows a typical configuration providing
a gain of 100 with high input resistance. The feedback resistor is
kept as low as practicable to maximize bandwidth, and a peaking capacitor (CpK) can optionally be added to further extend
the bandwidth. Figure 30 shows the small signal response with
CPK = 3nF, RL = 5000 and supply voltages of either ± SV or
± lSV. Gain bandwidth products of up to 900MHz can be achieved

in this way.
The offset voltage of the AD844 is laser trimmed to the 5011V
level and exhibits very low drift. In practice, there is an additional offset term due to the bias current at the inverting input
(IBN) which flows in the feedback resistor (R1). This can
optionally be nulled by the trimming potentiometer shown in
Figure 29.

REV. A

46

II

V.=,~15V
40

....,

r-- r-.. ~ll
[\

34

~

I

Z

~

Vs=±SV

28

\
~\

\\
\1

22

16
lOOk

1M
FREQUENCY - Hz

10M

20M

Figure 30. AC Response for Gain = 100, Configuration
Shown in Figure 29
USING THE AD844
Board Layout
As with all high frequency circuits considerable care must be
used in the layout of the components surrounding the AD844. A
ground plane, to which the power supply decoupling capacitors
are connected by the shortest possible leads, is essential to
achieving clean pulse response. Even a continuous ground plane
will exhibit finite voltage drops between points on the plane,
and this must be kept in mind in selecting the grounding points.
Generally speaking, decoupling capacitors should be taken to a
point close to the load (or output connector) since the load currents flow in these capacitors at high frequencies. The + In and
- In circuits (for example, a termination resistor and Pin 3)
must be taken to a common point on the ground plane close to
the amplifier package.
Use low impedance capacitors (AVX SR30SC224KAA or equivalent) of 0.2211F wherever ac coupling is required. Include either
ferrite beads and/or a small series resistance (approximately
4.70) in each supply line.
Input Impedance
At low frequencies, negative feedback keeps the resistance at the
inverting input close to zero. As the frequency increases, the
impedance looking into this input will increase from near zero to
the open loop input resistance, due to bandwidth limitations,
making the input seem inductive. If it is desired to keep the
input impedance flatter, a series RC network can be inserted
across the input. The resistor is chosen so that the parallel sum
of it and R2 equals the desired termination resistance. The
capacitance is set so that the pole determined by this RC network is about half the bandwidth of the op amp. This network
is not important if the input resistor is much larger than the termination used, or if frequencies are relatively low. In some
cases, the small peaking that occurs without the network can be
of use in extending the - 3dB bandwidth.

OPERATIONALAMPLIFIERS 2-109

II

AD844
Driving Large Capacitive Loads
Capacitive drive capability is 100pF without an external network. With the addition of the network shown in Figure 31, the
capacitive drive can be extended to over 10,OOOpF, limited by
internal power dissipation. With capacitive loads, the output
speed becomes a function of the overdriven output current limit.
Since this is roughly ± 100mA, under these conditions, the maximum slew rate into a 1000pF load is ± 100V/fLS. Figure 32
shows the transient response of an inverting amplifier
(Rl=R2=lkn) using the feed forward network shown in Figure
31, driving a load of 1000pF.

>-,-_V

OUT

Cl

01. 02 IN6263 OR EQUIV. SCHOTTKY DIODE

Figure 33. Settling Time Test Fixture

Figure 31. Feed Forward Network for Large
Capacitive Loads

DC Error Calculation
Figure 34 shows a model of the dc error and noise sources for
the AD844. The inverting input bias current, IBN' flows in the
feedback resistor. IBP ' the noninverting input bias current, flows
in the resistance at Pin 3 (Rp), and the resulting voltage (plus
any offset voltage) will appear at the inverting input. The total
error, Va' at the output is:
VO=(IBP Rp+ Vas +IBN R1N)

(1+ ~~) + IBN Rl

Since IBN and IBP are unrelated both in sign and magnitude,
inserting a resistor in series with the noninverting input will not
necessarily reduce de error and may actually increase it.

Figure 32. Driving 1000pF CL with Feed Forward Network
of Figure 31

Settling Time
Settling time is measured with the circuit of Figure 33. This
circuit employs a false suinming node, clamped by the two
Schottky diodes, to create the error signal and limit the input
signal to the oscilloscope. For measuring settling time, the ratio
of R6IRS is equal to RIIR2. For unity gain, R6 = RS = lkn, and
RL = soon. For the gain of -10, RS = son, R6 = soon and RL
was not used since the summing network loads th~ output with
approximately 27Sn. Using this network in a unity-gain configuration, settling time is lOOns to 0.1% for a -SV to +SV step
with CL = 10pF.

Figure 34. Offset Voltage and Noise Model for the AD844

Noise
Noise sources can be modeled in a manner similar to the dc bias
currents, but the noise sources are Inn, Inp, Vn, and the
amplifier-induced noise at the output, VON' is:
VON =

~((Inp Rpi+Vn2) (1+ ~)2 +(Inn Rli

Overall noise can be reduced by keeping all resistor values to a
minimum. With typical numbers, Rl=R2=lk, Rp=O,
Vn=2nV/yHz, Inp=IOpNyHz, Inn=12pNVHz, VON calculates to 12nV/VHz. The current noise is dominant in this case,
as it will be in most low gain applications.

2-110 OPERATlONALAMPLlFIERS

REV. A

Applications - AD844
Video Cable Driver Using ±S Volt Supplies
The AD844 can be used to drive low impedance cables. Using
±5V supplies, a 1000 load can be driven to ±2.5V with low
distortion. Figure 35a shows an illustrative application which
provides a noninverting gain of 2, allowing the cable to be
reverse-terminated while delivering an overall gain of + I to the

load. The - 3dB bandwidth of this circuit is typically 30MHz.
Figure 35b shows a differential gain and phase test setup.
In video applications, differential-phase and differential-gain
characteristics are often important. Figure 35c shows the variation in phase as the load voltage varies. Figure 35d shows the
gain variation.

+5V

•

v,.

300n

Figure 35b. Differential Gain/Phase Test Setup

Figure 35a. The AD844 as a Cable Driver
+0.3

NOTE,

!•• =

+0.06

+0.2

i,

+0.04

~

+0.1

~

~

I~

~

1-0.02
is

-0.2
-0.3

+0.02

3

J
1-0.,
i

NOTE~ IRE = 7.,lmv

7.'JoV

~~

-0.04

o

,.

3.

54

72

-0.06

90

o

,.

3.

54
VOUT -IRE

72

.

Figure 35c. Differential Phase for the Circuit of Figure 35a

Figure 35d. Differential Gain for the Circuit of Figure 35a

High Speed DAC Buffer
The AD844 performs very well in applications requiring
current-to-volmge conversion. Figure 36 shows connections for
use with the AD568 current output DAC. In this application the
bipolar offset is used so that the full scale current is ±5.12mA,
which generates an output of ± 5.12V using the lkO application
resistor on the AD568. Figure 37 shows the full scale transient
response. Care is needed in power supply decoupJing and

grounding techniques to achieve the full 12-bit accuracy and
realize the fast settling capabilities of the system. The unmarked
capacitors in this figure are O.IIJ.F ceramic (for example, AVX
Type SR305CI04KAA), and the ferrite inductors should be
about 2.51J.H (for example, Fair-Rite Type 2743002122). The
AD568 data sheet should be consulted for more complete details
about its use.

~1-------------1---------CE~~+'w

1221--+---++_---:---+------..--a~~

-15V

DIGITAL
INPUTS

I-~~~~------------+_--~---o~~~~
GROUND

DIGITAL

~1-~~----------------------~~SU~y
·O.U,.F
POWER SUPf"LY
BVPASS CAPACfTORS

Figure 37. DAC Amplifier Full-Scale
Transient Response

Figure 36. High Speed DAC Amplifier

REV. A

OPERA TIONALAMPLIFIERS 2-111

AD844
Figure 39 shows the small signal response for a SOdB gain control range (Vx=+lOmV to +3.16V). At small values ofVx ,
capacitive feedthrough on the PC board becomes troublesome,
and very careful layout techniques are needed to minimize this
problem. A ground strip between the pins of the ADS39 will be
helpful in this regard. Figure 40 shows the response to a 2V
pulse on Vy for Vx=+IV, +2V and +3V. For these results, a
load resistor of 5000 was used and the supplies were ±9V. The
multiplier will operate from supplies between ±4.SV and
±16.SV.

20MHz Variable Gain Amplifier

The AD844 is an excellent choice as an output amplifier for the
ADS39 multiplier, in all of its connection modes. (See ADS39
data sheet for full details.) Figure 38 shows a simple multiplier
providing the output:
VxV
---zvy

Vw

=

where Vx is the "gain control" input, a positive voltage of from
o to +3.2V (max) and Vy is the "signal voltage", nominally
±2V FS but capable of operation up to ±4.2V. The peak output in this configuration is thus ±6.7V. Using all four of the
internal application resistors provided on the ADS39 in parallel
results in a feedback resistance of l.SkO, at which value the
bandwidth of the AD844 is about 22MHz, and is essentially
independent of Vx . The gain at Vx =3.l6V is +4dB.

Disconnecting Pins 9 and 16 on the ADS39 alters the denominator in the above expression to 1V, and the bandwidth will be
approximately 10MHz, with a maximum gain of IOdB. Using
only Pin 9 or Pin 16 results in a denominator of O.SV, a bandwidth of SMHz and a maximum gain of 16dB.

,-_ _ _ _ _ _ _ _ _ _ _.--<>+v,
ton

10n

TYP.+6V
(,,1SmA

INPUTS

V,
OTO +3V

V,o-I-+-+{)
:t2V FS

'nF

10n

TYP.-6V
(fl25mA
L -_ _ _ _~""'~----~-<>_V,

10n
-V x AND Vv INPUTS MAY OPTIONALLY

BE TERMINATED - TYPICALLY BY

USING A 50n OR 7SU RESISTOR
to GROUND.

Figure 38. 20MHz VGA Using the AD539
+4

,'"

V=3r SV
X

-6

vlt='(V

\

-16

Vx=ofsV

'1l

. -26

~

VIt=O(OV

........

Vx =O.032V

.......

-'6
-46

"
,

"

-56
1DOl<

1M

10M

&oM

FREQUENCY - Hz

Figure 39. VGA AC Response

2-112 OPERA TlONALAMPLIFIERS

Figure 40. VGA Transient Response with
Vx = lV, 2V, and 3V

REV. A

Precision 16 MHz
CBFET Op Amp
AD845 I

r'IIIIANALOG
WDEVICES
FEATURES
Replaces Hybrid Amplifiers in Many Applications
AC PERFORMANCE:
Settles to 0.01% in 350 ns
100 V/,..s Slew Rate
12.8 MHz min Unity-Gain Bandwidth
1.75 MHz Full-Power Bandwidth at 20 V p-p
DC PERFORMANCE:
0.25 mV max Input Offset Voltage
5 ,..VlOC max Offset Voltage Drift
0.5 nA Input Bias Current
250 VlmV min Open-Loop Gain
4 ,..V p-p max Voltage Noise, 0.1 Hz to 10 Hz
94 dB min CMRR
Available in Plastic Mini-DIP, Hermetic Cerdip and SOIC
Packages
PRODUCT DESCRIPTION
The AD845 is a fast, precise, N channel JFET input, monolithic operational amplifier. It is fabricated using Analog
Devices' complementary bipolar (CB) process. Advanced laserwafer trimming technology enables the very low input offset
voltage and offset voltage drift performance to be realized. This
precision, when coupled with a slew rate of 100 V/fLS, a stable
unity-gain bandwidth of 16 MHz, and a settling time of 350 ns
O.OI%-while driving a paralle110ad of 100 pF and 500 0represents a combination of features unmatched by any FET
input IC amplifier. The AD845 can easily be used to upgrade
many existing designs which use BiFET or FET input hybrid
amplifiers and, in some cases, those which use bipolar input op
amps.
The AD845 is ideal for use in applications such as active fIlters,
high speed integrators, photo diode preamps, sample-and-hold
amplifiers, log amplifiers, and in buffering AID and D/A converters. The 250 fLV max input offset voltage makes offset nulling unnecessary in many applications. The common-mode
rejection ratio of llO dB over a ± 10 V input voltage range represents exceptional performance for a JFET input high speed op
amp. This, together with a minimum open-loop gain of
250 VImV ensures that 12-bit performance is achieved, even in
unity-gain buffer circuits.

REV. A

CONNECTION DIAGRAM
Plastic Mini-DIP (N) Package
and Cerdip (Q) Package

16-Pin SOIC (R) Package

NULL

+INPUT

-v

NC

NC

= NO CONNECT

The AD845 conforms to the standard op amp pinout except that
offset nulling is to V+. The AD845J and AD845K grade devices are available specified to operate over the commercial 0 to
+ 70°C temperature range. AD845A and AD845B devices are
specified for operation over the -40°C to + 85°C industrial temperature range. The AD845S is specified to operate over the full
military tempemture range of -55°C to + 125°C. Both the industrial and military versions are available in 8-pin cerdip packages. The commercial version is available in an 8-pin plastic
mini-DIP and 16-pin SOIC. "1" and "S" grade chips are also
available.
PRODUCT HIGHLIGHTS
1. The high slew rate, fast settling time, and dc precision of the
AD845 make it ideal for high speed applications requiring
12-bit accuracy.
2. The performance of circuits using the LF400, OP-42, OP-44,
OP-16, OP-17, HA2520/2/5, HA2620/2/5, 3550, OPA605,
and LH0062 can be upgraded in most cases.
3. The AD845 is unity-gain stable and internally compensated.
4. The AD845 is specified while driving 100 pF/500 0 loads.

OPERATIONALAMPLIFIERS 2-113

•

AD845-SPECIFICATIONS

(@ +25°C and ±15 V dc, unless otherwise noted)

AD845J/A
Typ
Min

Model
Conditions
INPUT OFFSET VOLTAGE'
Initial Offset

0.7

Tmin-Tmu
Offset Drift
INPUT BIAS CURRENT'
Initial

0.75

VCM = OV

25

VCM = OV
Tmin-TInlIK

INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
INPUT VOLTAGE RANGE
Differential
Common Mode
Common-Mode Rejection

Max

1.5
2.5
20

0.1

2

0.5

1.5

300
3/6.5

IS

Max

Unils

0.25
0.4
5.0

0.25

1.0
2.0
10

mV
mV
.,.VI"C

I
18/38

0.75

2

nA
nA

100
1.212.6

25

500

:t20 '

+ 10.51-13

+10
94

110

+ 10.51-13

±IO
86

113

300
20

4.0

:t20
VCM = :tIOV

Typ

Min

lO"

lO"
4.0

:t10
86

AD845S

Typ

Min

45175

TuUu-Tmu.
INPUT OFFSET CURRENT
Initial

AD845K/B
Max

pA
nA

lO"
4.0

ldl

:t20
+10.5/-13
110

V
V
dB

pF

INPUT VOLTAGE NOISE

0.1 to 10 Hz
f= 10Hz
f = 100 Hz
f= I kHz
f=lOkHz
f= 100kHz

4
80
60
25
18
12

4
80
60
25
18
12

4
80
60
25
18
12

.,.V p"p
nVlv'Hz
nVlyHZ
nVlyHZ
nVlv'Hz
nV"/Hi

INPUT CURRENT NOISE

f=lkHz

0.1

0.1

0.1

pAlv'Hz

OPEN-LOOP GAIN

Vo - ±IOV
RLOAo"'2 k.o
RLOAo"'SOO

500
250

VlmV
VlmV
VlmV

n

200
100
70

n

±12.5

Tmin-Tmu:
OUTPUT CHARACfERISTICS
Voltage
Current
Output Resistance
FREQUENCY RESPONSE
Small Signal
Full Power Bandwidth'
Rise Time
Overshoot
Slew Rste
Settling Time

RLOAo"'SOO
Short Circuit
Open Loop

Unity Gain
Vo = ±IOV
R LOAO = 500

500
250

250
125
75

12.8

80

200
100
50

±12.5

±12.5
SO
5

SO
5

n

500
250

13.6

16

V
rnA

SO
5

16

13.6

n

MHz

16

1.75

1.75

1.75

20
20
100

20
20
100

20
20
100

V/.,.s

350
250

ns
ns
ns
ns

94

94,

MHz
ns
%

10 V Step
~AO = lOOpF

RLOAO =
to 0.01%
to 0.1%

soon

350
250

350
250

500

500

DIFFERENTIAL GAIN

f - 4.4 MHz

0.04

0.04

0.04

%

DIFFERENTIAL PHASE

f- 4.4 MHz

0.02

0.02

0.02

Degree

POWER SUPPLY
Rsted Performance
Operating Range
Rejection Rstio
Quiescent Current

±IS
±4.75
Vs=±Sto±ISV
to Tmu.

Tmil1

88

±IS
:t18

110
10

12

±4.75
9S

±IS
±18

113
10

±4.75

88
12

±18
110
10

12

V
V
dB
rnA

NOTES
'Input offset voltage specification. are guaranteed after 5 minute. of operation at TA = +2S"C.
2Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at T A = +.250(;.
'FPBW=slew rate/2", V peak.
'''S'' grade Tmln-Tmu are tested with automatic test equipment at TA = -5S"C and TA = +12S"C.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at fmal electrical test. Results from these tests
are used to calculate· DUtsoins quality level•.
Specifications subject to change without notice.

2-114 OPERA TIONALAMPLIFIERS

REV. A

AD845
ABSOLUTE MAXIMUM RATINGS I
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ±IS V
Internal Power Dissipation2
Plastic Mini-DIP . . . . . . . . . . . . . . . . . . . . . . 1.6 Watts
Cerdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Watts
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±Vs
Output Short-Circuit Duration . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . +Vs and -Vs
Storage Temperature Range
Q . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to + 150°C
N, R . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to + 125°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
NOTES
IStresses above those listed under "Absolute Maximum Ratings" may cause
pennanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure [0 absolute maximum rating conditions for extended periods may affect
device reliability.
'Mini-DIP package: aJA = lOO'Clwatt; cerdip package: aJA = 1l0'Clwan.

ORDERING GUIDE
Modell

Temperature
Range

Package
Option'

ADS4SJN
ADS4SKN
ADS4SJR'
ADS4SAQ
ADS4SBQ
ADS4SSQ
ADS4SSQ/SS3B

O°C to +70°C
O°C to +70°C
O°C to +70°C
-40°C to +SsoC
-40°C to +SsoC
-55°C to + 125°C
-55°C to + 125°C

N-S
N-S
R-S
Q-S
Q-S
Q-S
Q-S

NOTES
IUJ" and "S" grade chips are also available.
'N = Plastic DIP; Q = Cerdip; R = Small Outline Ie (SOlC). For oudine
information see Package Information section.
'Available in tape and reel packaging.

METALIZATION PHOTOGRAPH
Dimensions sbown in inches and (mm).
Contact factory for latest dimensions.

Ira;;;~

"l~~:=.J
+v

NUll NULL

SUBSTRATE CONNECTED TO +Vs

REV. A

OPERA TlONALAMPLlFIERS 2-115

•

AD845 - Typical Characteristics
2.r------r------T-----~~--~

2.

'5

'5

30

25

..
.'

~

j!:>

0"

!!j~

E~
zg

~~

,.

~~
~~

~~I

~

,.

+)./

Ii

V

V'

/

/

~

~,

~

20

II
:!: 15V SUPPLIES

g

'5

1/

~ ,.

RL = 2kfi

fA"" +Z5-c

0

V-VOUT

SUPPLY VOLTAGE- :!:Votts

Figure 1. Input Voltage Swing
VS. Supply Voltage

'2

:.--

I
I

--

,.

••

·~.------~-----7.,.~----~'5~--~ro

i

/

,

,.
7

~

7

i '

I..,

/
/

/

,

20

'5

f- ......

/

10- 1
-60 -40 -20

0.01

0

20

40

60' 80

TEMPERATURE -

100

120

140

7.

=---+---+----+--__1

••

750 ....

,
5.. r----+--~t_--_f--__I

r----+--''''''-'''''':I---_f-----'......;:::-I

~

'00'

10k

oc

,.M

,M

'OOM

FREQUENCY - Hz

Figure 6. Magnitude of Output
Impedance VS. Frequency

Figure 5. Input Bias Current VS.
Temperature

VS.

,... r------r------~----~----__,

25.

Figure 3. Output Voltage Swing
Resistive Load

f--

!2

;

..

,

1k

'00

Figure 4. Quiescent Current
Supply Voltage

I"

'00

VS.

,

,.

,

V
LOAD RESISTANCE - n

Figure 2. Output Voltage Swing
VS. Supply Voltage

SUPPLY VOLTAGE - ::tYotts

1

~

•,.

20

'5
5UPPLYVOlTAOE_ ::tVofts

17.0

........

........
.........

t'

50

I••

i, '..

,,-OUTPUT CURRENT

'k'k
+OUTPUT.........

CURRENT

~ ..........

5

I,. .

........

i'... ...........

...........
...........

z

~"

~

i

r-.... ........

15.5

t--..

WITH

HEAT SINK

.L-____-L____
-10

~

______

~

____

-5
COMMON·MODE VOLTAGE - Volts

Figure 7. Input Bias Current vs.
Common-Mode Voltage

2-116 OPERATIONALAMPLIFIERS

~

10

30
-80 -40 -20

~

0

20
40 80 80
TEMPERATURE _ OC

100

120 140

Figure 8. Short-Circuit Current
Limit vs. Temperature

-80 -40 -20

0

20

40

60

80

100 120

140

TEMPERATURE - "C

Figure 9. Unity-Gain Bandwidth
VS. Temperature

REV. A

AD845

,,

+'40
+120

i - - '""""-

·+100

,

Z

MARGIN~ r--

'\
GIN

+SO

9

~

,,

+BO

;;:

"I!;

""

'\

+40

'\
Vs =

:!: 15VSUPP~ES

-20
10

100

1k

10k

tOOk

FREQU~NCY -

+75

1M

+120

D

i

+60

0

10M

l,

. "5
Z

;;:

. §"
.ifill iii

+45" <;

I ,/"

Ie

+ 3D"
+15

0

+40

.

,

100M

'0

'5

SUPPLY VOLTAGE -

-20

20

10

:!: Volts

""

BO

~,
Ie

so

25

""

0.1%

o

'M

'OOk

'00'

'OM

'M

Figure 13. Common-Mode Rejection vs. Frequency

"-

I

V /1

II

1-,20

;!

l/
3AD

/,/
1k

10k

Figure 16. Harmonic Distortion
vs. Frequency

'" "

250

./

30D

350

400

-

./

100

~

i

IHARjOilC

FREQUENCY - Hz

REV. A

i

.....

t--

,

-130

'00

200

/

I '0

"

150

l,

~

I

100

110

~, '00
2ND HARMONIC

50

Figure 15. Output Swing and Error
vs. Settling Time

...

~,

~

SETTLING TIME - ns

,

Z -110

~~=~-

0.01%

!\

-'0 0

10M

Figure 14. Large Signal Frequency
Response

-'00

100M

0.01%

ERROR

INPUT FREQUENCY - Hz

FREQUENCY - Hz

//

0.1%

!\
'Ok

10M

V

40

1k

1M

II

\

=

tOOk

III

"'- l\.

RL "" 2kn
TA +25"C
Vs = ±15V

r'\

'00

10k

Figure 12. Power Supply Rejection
vs. Frequency

1,\

= +25"<:

20

1k

'0

Vs = ::t15V
VCM '" 1Vp-p
T ...

100

SUPPl V MODULATION FREQUENCY - Hz

Figure 11. Open-Loop Gain vs.
Supply Voltage

IIII

"" ~

I • "~V SU~PLY

o

•

"- ~

V'

Hz

1'\

-SUPPLY

~
tUPPlV'" ~

+60

30

'00

'" "'.~

+20

D"

'20

"

+BO

~ 110

Figure 10. Open-Loop Gain and
Phase Margin vs. Frequency

IE

../

~

RL=2kll
TA = +25"C

IE

_15 0

.........

+'00

~

Z

,
,,
,
"'" "
I

+20

+'40

+SO"

·~AS:I\

r\..

~

120

+105°

'00k

'0

'00

lk

10k

,....

FREQUENCV - Hz .

Figure 17. Input Noise Voltage
Spectral Density

I
90

'M

-&0

4020020406080

100

120

140

TEMPERATURE - "C

Figure 18. Slew Rate vs. Temperature

OPERATIONAL AMPLIFIERS 2-117

AD845

.

NULL

,

+Vs

+Vs

6 'Jour

.

-V,

Figure 19. Recommended Power
Supply Bypassing

Figure 22a. Unity-Gain Follower

Figure 20. AD845 Simplified
Schematic

Figure 21. Offset Null Configuration

Figure 22b. Unity-Gain Follower
Large Signal Pulse Response

Figure 22c. Unity-Gain Follower
Small Signal Pulse Response

Figure 23b. Unity-Gain Inverter
Large Signal Pulse Response

Figure 23c. Unity-Gain Inverter
Small Signal Pulse Response

1kH

Figure 23a. Unity-Gain Inverter

2-118 OPERATIONALAMPLIFIERS

REV. A

Applying the AD845
MEASURING AD845 SETTLING TIME
The Figure 24 shows the AD845 settling time performance.
This measurement was accomplished by driving the amplifier
in the unity-gain inverting mode with a fast pulse generator.
The input summing junction was measured using false nulling
techniques.
Settling time is defined as:
The interval of time from the application of an ideal
step function input until the closed-loop amplifier output
has entered and remains within a specified error band.
Components of settling time include:
1. Propagation time through the amplifier
2. Slewing time to approach the final output value
3. Recovery time from overload associated with the slewing
4. Linear settling to within a specified error band.
These individual components can easily be seen in Figure 24.
Settling time is extremely important in high speed applications
where the current output of a DAC must be converted to a voltage. When driving a 500 0 load in parallel with a 100 pF capacitor, the AD845 settles to 0.1% in 250 ns and to 0.01% in
310 ns.

A HIGH SPEED INSTRUMENTATION AMP
The three op amp instrumentation amplifier circuit shown in
Figure 26 can provide a range of gains from unity up to 1000
and higher. The instrumentation amplifier configuration features
high common-mode rejection, balanced differential inputs and
stable, accurately defmed gain. Low input bias currents and fast
settling are achieved with the FET input AD845.
Most monolithic instrumentation amplifiers do not have the high
frequency performance of the circuit in Figure 26. The circuit
bandwidth is 10.9 MHz at a gain of 1 and 8.8 MHz at a gain of
10; settling time for the entire circuit is 900 ns to 0.01% for a
10 V step (Gain = 10).
The capacitors employed in this circuit greatly improve the
amplifier's settling time and phase margin.
+v,
+Vs~

....---:+:...:.

12- 1SpF

V+...1..''''F

v,.

-Vs~

+15V

COMM
-15V

CIRCUIT GAIN ::: 2::: +1

Figure 26. High Performance, High Speed Instrumentation Amplifier

Figure 24. Settling Characteristics 0 to 10 V Step
Upper Trace: Output of AD845 Under Test (5 VlDiv)
Lower Trace: Error Voltage (1 mVIDiv)

'"

7A13

'"
""

OSCILLOSCOPE

,.,

3 OP-AMP IN-AMP
Gain

RG

Small Signal
Bandwidth

to 0.01%

Settling Time

1
2
10
100

Open
2k
2260
200

10.9 mHz
8.8 mHz
2.6mHz
290 kHz

500 ns
500 ns
900 ns
7.5 ILS

1A1.

Note: Resistors around the amplifiers' input pins ueed to be small enough in
value so that the RC time constant they form, with stray circuit capacitance,
does not reduce circuit bandwidth.

Table I. Performance Summary for the Three Op Amp
Instrumentation Amplifier Circuit

.¢.

100pF

Figure 25. Settling Time Test Circuit

REV. A

OPERATIONALAMPLIFIERS 2-119

II

Applying the AD845
DRIVING THE ANALOG INPUT OF AN NO
CONVERTER
An op amp driving the analog input of an AID converter, such
as that shown in Figure 29, must be capable of maintaining a
constant output voltage under dynamically changing load conditions. In successive-approximation converters, the input current
is compared to a series of switched tria1 currents. The comparison point is diode clamped but may deviate several hundred
millivolts resulting in high frequency modulation of AiD input
current. The output impedance of a feedback amplifier is made
artificially low by the loop gain. At high frequencies, where the
loop gain is low, the amplifier output impedance can approach
its open-loop value. Most
amplifiers exhibit a minimum
open-loop output impedance of 25 n due to current limiting
resistors. A few hundred microamps reflected from the change
in converter loading can introduce errors in instantaneous input
voltage. If the AiD conversion speed is not excessive and the
bandwidth of the amplifier is sufficient, the amplifier's output
will return to the nominal value before the converter makes its
comparison. However, many amplifiers have relatively narrow
bandwidth yielding slow recovery from output transients. The
AD845 is ideally suited to drive high resolution AiD converters
with 5 ...s on longer conversion times since it offers both wide
bandwidth and high open-loop gain.

Ie

Figure 27. The Pulse Response of the Three Op Amp
Instrumentation Amplifier. Gain = 1, Horizontal Scale:
0.5 mslOiv; Vertical Scale: 5 VlOiv

Figure 28a. Settling Time of the Three Op Amp Instrumentation Amplifier. Horizontal Scale:200 nslOiv; Vertical
Scale, Positive Pulse Input: 5 VIOiv; Output Settling:
1 mVIOiv

±10V

ANALOG
INPUT

Figure 29. A0845 As AOC Unity Gain Buffer

Figure 28b. Settling Time of the Three Op Amp Instru-·
mentation Amplifier. Horizontal Scale: 200 nslOiv; Vertical
Scale, Negative Pulse Input: 5 VIOiv; Output Settling:
1 mVIOiv

2-120 OPERA TIONALAMPLIFIERS

REV. A

450 V/fJ-s, Precision,
Current-Feedback Op Amp
AD846 I

~ANALOG

WDEVICES
FEATURES

CONNECTION DIAGRAM

AC PERFORMANCE
Small Signal Bandwidth: 80 MHz (Av -1)
Slew Rate: 450 V/ ..s
Full Power Bandwidth: 6.S MHz at 20 V pop,
RL =5000
Fast Settling: for 10 V Step: 110 ns to 0.01%,
SO ns to 0.1%
Differential Gain: <0.01% @ 4.4 MHz
Differential Phase: <0.028° @ 4.4 MHz
Total Harmonic Distortion (THO): 0.0005% @ 100 kHz
Open-Loop Transimpedance: 200 MO
Input Voltage Noise: 2 nV/YHz

=

DC PERFORMANCE
Input Offset Voltage: 75 ..V max (B Grade)
Input Offset Drift: 3.5 ..V/oC max (B Grade)
Quiescent Supply Current: 6.5 mA max
APPLICATIONS
High Speed DAC Buffers
Multiflash ADC Error Amplifiers
Flash ADC Buffers
Coaxial Cable Drivers
High Performance Audio Circuitry
Available in Plastic Mini-DIP, Hermetic Cerdip, and
Hermetic Metal Can Packages
MIL-STD-S83B Parts Available
PRODUCT DESCRIPTION
The AD846 is a monolithic, very high speed operational amplifier offering high performance. Although technically classed as
a current-feedback or transimpedance amplifier, it may be used
in much the same way as traditional op amps while providing
significant performance benefits. Employing Analog Devices'
junction isolated complementary bipolar (CB) process, the
AD846 achieves true "12-bit" (0.01%) precision on critical ac
and dc parameters, a level of performance unmatched by amplifiers fabricated using either the dielectrically isolated (DI) or
other bipolar processes.
The AD846 offers significant advantages over conventional high
speed .()perational amplifiers. It maintains a nearly constant
bandwidth and settling time to 0.01% over a wide range of
closed-loop gains. This makes the AD846 ideal for amplifying
the residue in multiple-pass analog-to-digital converters.

REV. A

Plastic Mini-DIP (N) Package
and
Cerdip (Q) Package
Top View

NC = NO CONNECT

Other advantages include: low input errors and high open-loop
transresistance (200 MO) into a 500 0 load, ensuring true 12-bit
dc accuracy for closed-loop gains from -I to gains greater than
-100. This combination of ac and dc performance makes the
AD846 an excellent choice for buffering precision high speed
DACs and flash ADCs.
The AD846 is available in three performance grades. The
AD846A and AD846B are rated over the industrial temperature
range of -40°C to +85°C. The AD846S is rated over the full
military temperature range of - 55°C to + 125°C and is available
processed to MIL-STD-883B, Rev C.
Extended reliability PLUS screening is available specified over
the commercial temperature range. PLUS screening includes
168 hour bum-in as well as other environmental and physical
tests. The AD846 is available in two types of 8-pin package:
plastic mini-DIP and hermetic cerdip. "A" and "S" grade chips
are also available.
PRODUCT HIGHLIGHTS
1. The AD846 achieves settling times of 110 ns to 0.01% for
gains of -I to -10, with a 450 V/floS slew rate, while consuming only 5 rnA of supply current.
2. For closed-loop gains of -I to -100, the high speed performance of the AD846 is achieved without sacrificing full
12-bit dc precision.
3. The AD846 is well suited to line driver and video buffer
applications where the properties of low distortion and high
slew rate are required.

OPERATIONALAMPLIFIERS 2-121

II

AD846-SPECIFICATIONS (@ +25°C and ±15 V dc, unless otherwise noted)
Model

Conditions

Min

INPUT OFFSET VOLTAGE'
Initial

25
50
O.S

Tmin-Tmax
vs. Temperature
vs. Supply (PSRR)
Initial

AD846A
Typ
Max

Min

200
350
5

AD846B
Typ
Max
25
50
O.S

Min

75
125
3.5

AD846S
Typ

Max

Units

25
100
I

200
350
5.5

",V
",V

5 V-IS V2

Tmin-Tmax

vs. Common Mode (CMRR)
Initial

110
110

125
120

120
116

125
120

110
94

125
116

dB
dB

110
110

125
120

120
116

125
120

110
94

125
116

dB
dB

VCM = ±IO-V

Tmin-Tmax

INPUT BIAS CURRENT'
- Input Bias Current
Initial

Tmin-Tmax
vs. Temperature
vs. Supply
Initial

",vrc

ISO
450
6

450
1200
20

100
400
6

250
750
17

150
1000
9

450
1500
20

nA
nA
nArC

9
11

15
20

9
11

10
15

9
11

15
25

nAIV
nAIV

5
5

10
IS

3
3

5
7

5
5

10
20

nAIV
nAIV

3
4
IS

15
20
SO

3
4
IS

5
7
45

3
5
15

15
20
SO

",A
",A
nArC

5
5

15
20

5
5

10
15

5
5

15
20

nAIV
nAIV

5
5

15
IS

3
3

10
10

5
5

15
20

nAIV
nAIV

5 V-ISV2

Tmin-Tmax

vs. Common Mode
Initial

VCM=±IOV

Tmin-Tmax

+ Input Bias Current
Initial

Tmin-Tmax
vs. Temperature
vs. Supply
Initial

5 V-18 V2

Tmin-Tmax

VCM = ±IO V

vs. Common Mode
Initial
Tmin-Tmax

INPUT CHARACTERISTICS
Input Resistance
-Input
+ Input
Input Capacitance
-Input
+ Input
INPUT VOLTAGE RANGE
Common Mode
INPUT VOLTAGE NOISE
Input Current Noise
-Input
+ Input
OPEN LOOP
TRANSRESISTANCE

OUTPUT CHARACTERISTICS
Voltage
Current
Output Resistance
FREQUENCY RESPONSE
Small Signal Bandwidth
(-3dB)
FuIj Power Bandwidth'
Rise Time
Overshoot
Slew Rate
Settling Time
10 V Step, Ay

=-

TOTAL HARMONIC
DISTORTION'

I

50
10

50
10

50
10

n
kn

2
2

2
2

2
2

pF
pF

±IO

±IO

±IO

V

F= I kHz

2

2

2

nV!\ Hz

1kHz
1 kHz

20
6

20
6

20
6

pAl\ Hz
pAl,Hz

200

Mn
Mn

VOUT = ±IOV
RLOAD = 500 n
Tmi~-Tmax
RLOAD = 500 n
Short Circuit
Open Loop

100
50

200

±10

150
75

200

±10

100
50
±10

V

65
16

65
16

65
16

rnA

Ay = -IRp= Ik
Av = -10 RF = S75 n
Ay = -30 RF = 875 n
VOUT = 20 V p-p
R, = 500n
Ay =-1
Ay =-1
Ay =-1

SO
31
15

SO
31
.15

SO
31
15

MHz
MHz
MHz

6.S
10
20
450

6.S
10
20
450

6.S
10
20
450

MHz
ns
%
VI",s

to 0.1%
to 0.01%

SO
110

SO
110

SO
110

ns
ns

F = 100kHz

0.0005

0.0005

0.0005

%

2-122 OPERATIONALAMPLIFIERS

n

REV. A

AD846
Min

0.01

0.01

0.01

%

DIFFERENTIAL PHASE

F - 4.4 MHz, RL -

0.028

0.028

0.028

Degree

:±: 15

:±:S

±I8
6.5

5

Tmin-Tmax

72

TRANSISTOR COUNT

Min

±5
5

Max

Units

F - 4.4 MHz, RL - 100

:±: 15

Max

AD846S
Typ

DIFFERENTIAL GAIN

n
100 n

Max

AD846B
Typ

Conditions

POWER SUPPLY
Rated Performance
Operating· Range
Quiescent Current

Min

AD846A
Typ

Model

±I8

V
V

7

mA

:±: 15

±I8
6.5

±5
5

72

72

NOTES
lInput Offset Voltage Specifications are guaranteed after 5 minuies at TA = +25°C.
'Test Conditions: +Vs = 15 V, -Vs = 5 V to 18 V and +Vs = 5 V to 18 V, -Vs = 15 V.
3Bias Current Specifications are guaranteed maximum after 5 minutes at T A = +25°C.
4FPBW = Slew Ratel2 'If VPEAK'
STotal Harmonic Distortion.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at final electrical test.
Results from those tests are used to calculate outgoing quality levels.
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS l
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ± IS V
Internal Power Dissipation 2
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . I. 5 W
Cerdip Package . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Common-Mode Input Voltage, Max Safe . . . . . . . . . IVsl -3 V
Output Short Circuit Duration . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . ± I V
Continuous Input Current
Inverting or Noninverting . . . . . . . . . . . . . . . . . . 2.0 rnA
Storage Temperature Range Q
-65°C to + 150°C
Storage Temperature Range N . . . . . . . . . . -65°C to + 125°C

ORDERING GUIDE

Modell

Temperature
Range

Package
Option2

ADS46AN
ADS46BN
ADS46AQ
ADS46BQ
ADS46SQ
ADS46SQ/SS3B

-40°C
-40°C
-40°C
-40°C
-55°C
-55°C

N-S
N-S
Q-S
Q-S
Q-S
Q-S

to +SsoC

to
to
to
to
to

+SsoC
+SsoC
+SsoC
+ 125°C
+ 125°C

NOTES
luA" and "S" grade chips are also available.
'N = Plastic DIP Package; Q = Cerdip Package. For outline information see
Package Information section.

REV. A

Operating Temperature Range
ADS46A1B . . . . . . . . . . . . . . . . . . . . . . -40°C to +SsoC
ADS46S . . . . . . . . . . . . . . . . . . . . . . . -55°C to + 125°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . +300°C
NOTES
lStresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only; the functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
2Maximum internal power dissipation is specified so that T J does not exceed
+175°C at an ambient temperature of +25"C, derate cerdip (Q) package at
8.7 mwrc and plastic (N) package at 10 mWrC.
Plastic Package: 0IA = IOO°ClWatt, 0IC =33°CIW.
Cerdip Package: 0IA = 110°ClWatt, 0IC = 30"C/W.

METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
Consult factory for latest dimensions.
+Vs
7

-INPUT

0.087

rli~=;;;;r.r.J~ii~;:~

6 OUTPUT

SUBSTRATE
CONNECTED
TO

'r,~"" ~--------""'"f"I"'--., ·:.~ro.
OPERA TlONAL AMPLIFIERS 2-123

•

AD846 - Typical Characteristics
20

~,

V
o

,
-7

20

/

o

V

I

/

~

0

,.

A

Rl =2kU
+2!i"C

~

5

~

i"

,.

10

20

SUPPLY VOLTAGE - ±Volts

..
!!;

~
J!

4

,

~

~

0

:15 VOLT SUPPLIES

>

~

I .......

::>

3.
30

/'

2•

~

~,

J

20

II

,.

~

~

-

II

r- 1-- ....

:t:

.......

20

15

!;
I!:
::>

10

II

15 VOLT SUPPLIES

RL=500n

Z5

0

>

10

0

20

"

Figure 3. Quiescent Current
vs. Supply Voltage

15 VOLT SUPPLIES

~

V
i""'"

VV

10

SUPPLY VOLTAGE - :tValts

II

:!:

i""'"~

.

~

o

Figure 2. Output Voltage Swing
vs. Supply

30

.
!.

o
20

SUPPLY VOLTAGE - :tVohs

3.

~

,.

10

Figure 1. Input Voltage Swing
vs. Supply

~

"

/

~

I!i

~

+VOUT

10

~

+2Sec

~

"'\.

'\
!\

0

II

V1

-60 -40 -20

0

+20 +40 +60 +80 +100 +120 +140

TEMPERATURE - "C

Figure 4. Quiescent Supply Current
vs. Temperature

.

I~
..

r-

/

150

100

/

~

3.1

""I

3.0

i

Vs= :l:16V

RL =500n
Yo= -V.+4V. +V.-4V

I

10

4.

15

SUPPLY VOLTAGE- :tVolts

Figure.7. Open-Loop Transimpedance vs. Supply

2-124 OPERA nONALAMPLIFIERS

20

1M

100k

100M

10M

INPUT FREQUENCY - Hz

Figure 6. Large Signal Frequency
Response

210

',!

r-- r--

i

i

;i!

50

10k

n

3.2

200

~

1k

LOAD RESISTANCE -

Figure 5. Output Voltage Swing vs.
Resistive Load

250

i,

100

10

----

Vs= ::!:15V

+25"C
2.9

2.8

2.7
-10

-.

,

190

i.

::> 170

"~

..
i

150

~

~

SlZ

130

110

10

COMMON·MODE VOLTAGE - Volts

Figure 8. Positive Input Bias Current
vs. Common-Mode Voltage

V

-10

V
-.

V

/

Vs= :!:15V

+Z5"C

10

COMMON·MODE VOLTAGE - Volts

Figure 9. Negative Input Bias Current
vs. Common-Mode Voltage

REV. A

AD846
,..

-1.5

i

e~

~ -2.0
~

~

...,

I'-..

-2.5

'" "'"

Z

5

-3.0

Iz

0-3.5

,

...
~ -4.0

i

I-

-5.0

~
~

-5.5
-60 -40 -20

0

2.S

+120

2 .•

+, ..

"Ii:z ,..
~
, ,..

.,

"-

1'\ J

--

~
a:

..S

::>
u

.,
...~

~ -0.5

;!:

I-

--

-1.0
-60 -40 -20

+20 +4D +60 +80 +100+120+140
TEMPERATURE _ ·C

.........

"-

+80

vV

V V

iI!
Ie

+ ••
+40
+2.

-20
0

""
""I"
Rf =lkU

~

;!:

!!iu -4.5

i

+140

+20 +40 +60 +80 +100+120+140

10

100

lk

TEMPERATURE - ·C

Figure 10. Positive Input Bias
Current vs. Temperature

tOOk

1M

.,

40

2.S ""'''''''''''-'''TIT''T''TT1rr'1--rI'TrTl''Tl'rr'TT'TI

R~ = toon

IIIII
RL "" lkll

Il!

--~

%

~

+8.

~

" '"

a: + ••
a:

+4.

-20
10

100

lk

10k

tOOk

1M

~

r-.

10M

1.5

i

H-HI*++HH-HHt-++HIt--II+tIt++tH

Figure 14. Input Noise Voltage
Spectral Density

..
"- r-....

'00

~

~

...
:: ...
;.

'" ""

;.

,

so

Ii:0

..

2.
-60 -40 -20

o

..... ~

I'~

+20 +40 +60 +80 +100 +120+140

Figure 16. Short Circuit Current
Limit vs. Temperature

~,

i'-.........

i

~

300

..
..

o

RISING

+20 +40 +60 +80 +100+120+140
TEMPERATURE _ "C

Figure 17. Slew Rate vs.
Temperature

SLEW RATE

/

V/

/V
//
JV

240

'80

'20

••

250
-60 -40 -20

'OM

,..-

,
..:I. ,

r---.. i'--

..

TEMPERATURE - "C

REV. A

.......

,M

V ~~

420

~
"iiia:z ,

r-.....

:z: 40

'Ok
FREQUENCY - Hz

...

[!!

~

...

,

1k

...

Figure 15. Inverting Input Noise
Current Spectral Density

.S.

a:
a:

"::>t:
~

,. ,..

FREQUENCY - Hz

,

::>

r-.

1.0,L.-'--.LJ.J,Uo.
••....L...u.,IL.-'--u..u..,!"·
••....L...u.,.....-.J-J..uI'M--'-.J..':'J.lOM

100M

Figure 13. Common-Mode Rejection
vs. Frequency

,

'\

w

FREQUENCY - Hz

e so
E

\

H-+'f++o+~H+H+-+~IH+H++~

o

"

+2.

2.0

I.,

RF =lkU

~

:IE
u

100M

Figure 12. Power Supply Rejection
vs. Frequency

+120
+100

10M

FREQUENCY _ Hz

Figure 11. Negative Input Bias
Current vs. Temperature

+140

10k

II

~

t/ V

FALUNG
SLEW RATE

~

.

,

200

300

INPUT ERROR SIGNAL - mV

...

•••

(AT SUMMING JUNCnoNI

Figure 18. Slew Rate vs. Input
Error Signal

OPERATIONAL AMPLIFIERS 2-125

A0846-Typical Characteristics, Inverting Gain of 1
+3

lkll

SOOU LOAD

I

5\1
lkU

"1-r~

lkll

I

r~

*

Rp
10011

-•
I
, i

ri

I

~III

~.

~ =

I

iIIOij

-.

(OPTIONAL)

I

I

'PLUS 2pF SCOPE
PROBE CAPACITANCE

i.

I ..

-

I'

VOUT

'II,

SOn

!

~I\

= I~

r--..
'\

-3

501 LOAD
-9

-12

i.,. -

~

~

-6

:1:15 VOLT SUPPt..IES
AF

=,
1

-'"'00'

kll.GAIN =-1

i', i 1."['

1

,M

,.M

100M 200M

INPUT FREQUENCY - Hz

Figure 19a. Inverting Amplifier,
Gain of 1

+270

ri '\

+180

Ii

"0

son

X
,

.,

11 ~
LOAD

-105
2 VOLTS
Rl =5001.
Cl =20pf

z

\

i

0

;::

~

'"

~

:15 VOlT SUPPLIES

t-

-310
lOOk

It. = 1 kn. GAIN = -1

"it, ,
1M

-135

-145
10M

100M

........

Figure 21. Phase Shift vs. Frequency

I
V

10

50

/

~

I
2ND HARMONIC

/
100k

I
t

!Ii

I

V

"

15

SUPPLY VOLTAQE :Votts

Figure 24. 3 dB Bandwidth vs.
Supply Voltage

2-126 OPERATlONALAMPLlFIERS

20

20

40

••

I
~

\

, I.

:IE

~
~
z

.
,

/

80

~

V

75

/

~

0.1

10k

lOOk

1M
FREQUENCY - Hz

10M

Figure 25. Output Impedance
vs. Frequency

100M

\ 1
\1

80
80
100
120
SETTLING TIME - ns

RL =500J!
~ 15V SUPPUES

:l!

1

-

140

180

Figure 23. Settling Time
vs. Step Size

70

10

~

0

/

:t15 VOLT SUPPLIES

I

0.1% 1\0.01%

.

.0.01

o

\l

Figure 22. Total Harmonic Distortion
vs. Frequency

e,

RL =500U
+25'1:

\ \
\".

-6

-I

100

v

I I

Rs=lkU RF =lkn.----,-

-,.

10k
FREQUENCY - Hz

0.01%

0.1%

ERROR
-2
-4

:f

/'"

GAIN OFI_l

::l

I

,.

I

~,
51

V

INPUT FREQUENCY - Hz

90

~ .....

~

Z

:i
-270

INPUT L E V y

/ I I I
1 V I I

"'~

/ . r d HARMONIC

0
:IE -125

-180

II
,m.

-115

II

"' -90

i

,.

-95

,;

~.~~, Loio

Figure 20. Normalized Output Amplitude vs. Frequency vs. Load

Figure 19b. Large Signal Pulse
Response, Gain of -1

..

/

/

-

'\

\

/

II'

-60 -40 -20

0 +20 +40 +10 +80 +100 +120+140
TEMPERATURE - "C

Figure 26. 3 dB Bandwidth
Temperature

VS.

REV. A

Typical Characteristics, Inverting Gain of 10-AD846
+3

I

90911

!II

~...nLOAD

I

~
"

-3

~O

-6

i

90.911

Rp
4711

son LOAD
:I:

~c

-12

Z

-15

~

(OPTIONAL)

15 VOLT SUPPLIES

-9

'PLUS 2pF SCOPE
PROBE CAPACITANCE

\

\

\,

•

\

-18
lOOk

1M

10M

100M

INPUT FREQUENCY - Hz

Figure 27a. Inverting Amplifier,
Gain of 10

Figure 28. Normalized Output Amplitude vs. Frequency vs. Load

Figure 27b. Large Signal Pulse
Response, Gain of 10

+270

10

+180

~

-===

+90

~

~

~

I

.iE

~-+----+-+-1+--+--4I''-+-A--l

-115

I--t-.--+-t-t+---,Y----Y--+-+-l

i

~-+--- +--l-fE-.,A'---+-+-H

SJ

L~AD

E
UI

-105

Z

~~r" e~

Ii:

;:

~

:1:15 VOLT SUPPLIES

-90

~

V

-125

J / /
GAIN OF -10

ERROR

5

-2

~

~ - 135
-270

I--+--:>"'!;>",,+-t+--+--+-+-+-l

~

-6

Rs=87.SU RF ",,815n

\ \\.

-4

~

I\:t- ("'Y~t

1M

100M

10M

-145'-_-'-_-'_-'-......._ _-'-_-'--'-'....
lk
10k
tOOk

INPUT FREQUENCV - Hz

0

f-"

/

/

:IE

rJ

,.

~

:1

"I!:

~I

/

0.1

0.01
SUPPLY VOLTAGE- ±Volts

I'
10k

tOOk

1M

10M

FREQUENCY _ Hz

VS.

28

Z

0

20

I

:!: fSV SUPPLIES

30

I;

I-

15

100

1

V

I

I

25

REV. A

Rl =500n

:!!

z

"

80

32

IL

I

Figure 32. 3 dB Bandwidth
Supply Voltage

60

120

140

160

3.

10

Rl =500U
+25"C

10

40

Figure 31. Settling Time vs.
Step Size

100

/

20

SETTLING TIME - ns

Figure 30. Harmonic Distortion
vs. Frequency

33

31

I'1\.

-10

FREOUENCY _ Hz

Figure 29. Phase vs. Frequency
vs. Load

\.~

\

-8
-360
tOOk

""'

I{~~
K~
o'
o'

I

~

-180

I
W

!.!

l~~b"'"

w

UI

I I /

Figure 33. Output Impedance
vs. Frequency

100M

/

26

.

V

/

.......

,

l\

./

22
-60 -40 -20

0

+20 +40 +60 +80 +100 +120+140
TEMPERATURE - '"C

Figure 34. 3 dB Bandwidth vs.
Temperature

OPERA T10NAL AMPLIFIERS 2-127

Applying theAD846
POWER SUPPLY CONSIDERATIONS
The power supply connections to the AD846 must maintain a
low impedance to ground over a bandwidth of 40 MHz or more.
This is es~cia1ly important when driving a significant resistive
or capacitive load, since all current delivered to the load comes
from the power supplies. Multiple high quality bypass capacitors
are recommended for each power supply line in' any critical application. A 0.1 .... F ceramic and a 2.2 .... F electrolytic capacitor
as shown in Figure 35 placed as close as possible to the amplifier (with short lead lengths to power supply common) will assure adequate high frequency bypassing, in most applications. A
minimum bypass capacitance of 0.1 .... F should be used for any
application.
'

)--
Q,

Figure 40. Op Amp Three-Terminal Model

0

e---

9

@

'"9u

A more detailed examination of the closed-loop transfer function
of the AD846 results in the following equation:

.:±
R,

AD8.6
= :olOkll

r,
i,

AD846

,

.'\.R,

r-.. I,

\

10

~

-

~

RH~~ll~ e--

S~~~~E -""
MODEL

) A~8il

I

1

Closed-Loop Gain Gis)

1M

lOOk

7lkll

'(

10M

\
,

.\
100M

3dB BANDWIDTH - Hz

Compare this to the equation for a conventional op amp:

Closed-Loop Gain Gis)

where: CCOMP is the internal compensation capacitor of the amplifier; gM is the input stage transconductance of the
amplifier.
In the case of the voltage amplifier, the closed-loop bandwidth
decreases directly with increasing values of (1 + RF/R s ), the
closed-loop gain. However, for the transimpedance amplifier,
the situation is different. At low gains, where (I + RF/Rs) RIN
is small compared to R F, the closed-loop bandwidth is controlled by the internal compensation capacitance of 7 pF and the
value of R F, and not by the closed-loop gain. At higher gains,
where (1 + RF/Rs) RIN is much larger than R F, the behavior is
that of a conventional operational amplifier in which the input
stage transconductance is equal to the inverting terminal input
impedance of the transimpedance amplifier (R IN = 50 0).

REV. A

Figure 41. Closed-Loop Voltage Gain
Various Values of RF

VS.

Bandwidth for

For the case where RF = I kO and Rs = 100 0 (closed-loop
gain of -10), the closed-loop bandwidth is approximately
28 MHz. It should also be noted that the use of a capacitor to
shunt R F, a normal practice for stabilizing conventional op
amps, will cause this amplifier to become unstable because the
closed-loop bandwidth will increase beyond the stable operating
frequency.
A similar approach can be taken to calculate the noise performance of the amplifier. A simplified noise model is shown in
Figure 42.
The equivalent mean-square output noise voltage spectral
density will equal:
V ON2 =IRF

+

INN)2

+

(I

4kT RF(~: + I)

OPERATIONALAMPLIFIERS 2-129

II

Applying the AD846
Where:
Rp is the external resistance placed in series with the
noninverting input
RF is the feedback resistor
Rs is the source resistor
INN is the noise current in the inverting input
INP is the noise current in the noninverting input
VN is the input noise voltage.

(RF = I kO, Rs = 10 0) it will be 4 MHz. At gains of 3 or
greater, a small capacitor (2 pF-5 pF) connected across the
feedback resistor will help reduce overShoot; but when operating
at noninverting gains below 3, this same capacitance will cause
instability.
+V,

Typical values for these parameters (@ I kHz) in pA/\IHz are:
INN = 20, IpN = 6, VN = 2.
Or, referring to the signal input, the equivalent mean-square
input voltage noise is:

vii

= (R F INN)2

(1 + ~:Y +
+4
(1+ ~:)

+

[VN2

(Rp INP)2+4 kT Rp]

kT Rs

Resistor Rp is required for both inverting and noninverting (follower) operation, to insure stable operation. The amplifier's
noninverting input current (flowing through Rp of 100 0) will
typically add less than 300 ....V to the AD846's input offset voltage. This can be trimmed-out using the optional network shown
in Figure 44. The following table gives recommended values
for Rp.

Supply Voltage

Gain(R~)

Recommended
Value for Rp

6 V to IS V
6 V to 15 V
6 V to 15 V
5V
5V

1-10
10-20
20-200
1-10
10-200

1000
470
00
47 n
00

Figure 43. AD846 Noninverting Amplifier Configuration
USING THE COMPENSATION PIN OF THE AD846
Additional compensation may be provided for the AD846 by
applying an external capacitance between Pin 5 and analog
ground (Figure 44). The nominal value of the AD846's internal
compensation capacitor is 7 pF. For a given value of feedback
resistance (RF), any added external capacitance reduces the amplifier's slew rate and bandwidth proportionally.

INN

Figure 44. AD846 Inverting Amplifier Showing External
Compensation Connection, Rp and Optional Vas Trim

Figure 42. Op Amp Simplified Noise Model
NONINVERTING GAIN OPERATION
'Ihe AD846 can be used as a noninverting amplifier or voltage
follower, operating at gains between 1 and 200. A minimum
value of RF eqnal to 1 kO should be employed. For low gains (1
to 2), the input signal should be applied to the AD846's noninverting input through a 1000 series resistor; this will help reduce peaking. The best transient response will occur when the
amplifier's output level is below 5 V peak to peak.
At closed-loop gains of 3 or more, the input resistor is not required unless peak signals greater than 3 V will be applied. The
amplifier's bandwidth can be determined by using the inverting
amplifier's bandwidth equation or from Figure 41. For example,
at a gain of + 10 (RF = 1 kO, Rs = 100 0) the bandwidth of
the AD846 will be approximately 33 MHz; at a gain of + 100,

2-130 OPERATIONAL AMPLIFIERS

In addition to providing for external compensation, Pin 5 may
be used to clamp the output of the amplifier, as shown in Figure 45. The output can be clamped anywhere within the output
range (approximately ± 10 V) of the amplifier. The input should
also be clamped as a precaution against damaging the amplifier's
input transistors.
R,

OUTPUT

POSmVE (DC) ClAMPING
VOLTAGE
NEGATIVE (DC) CLAMPING
TYPE HP2835
VOLTAGE
DIODES

Figure 45. AD846 Used as a Clamped Amplifier

REV. A

A0846
This compensation node may also be used as an additional output terminal as in the precision transconductance amplifier application of Figure 46.

v,.

(±10V maxi

lOUT

=-O.1mAlVOLT

Figure 46. A Precision Transconductance Amplifier
The AD846 can be used in either the inverting transconductance
mode as shown in Figure 46, or in a noninverting mode with Rs
grounded and VIN applied to the noninverting terminal. The
current output is essentially constant over a compliance range of
± 10 V at the compensation node. The output current (from Pin
5) is limited to about ± I mA due to internal saturation. Under
these circumstances the normal output pin provides a buffered
version of the compensation node output voltage. Output load
impedance of 500 n or greater will not affect the accuracy of the
transconductance conversion.

THE AD846 IN A 2 MHz, 12-BIT SUBRANGING AID
CONVERTER CIRCUIT
The combination of fast settling times at high gains and low dc
errors make the AD846 ideal for use as an error amplifier in
high speed, 12-bit subranging A-D applications. In the circuit of
Figure 47, an AD842 serves as an input amplifier. First pass
conversion is accomplished, in a straightforward manner, determining the top 7 bits. The latch then holds these top 7 bits
which are applied to a 7 bit, 12-bit accurate DAC and also to
the highest 7 bits of the adder (note that a sample-and-hold
should be used ahead of this converter to minimize errors due to
its 500 ns acquisition time). In the second pass, the input
switches S I and S2 and S3 are set to state 2. The DAC output is
then subtracted from the input signal and the resulting difference is then amplified by an AD846 gain of 32 follower. This
gain, together with a 1I64th scale offset, insures a unipolar residue which can be converted by the flash A-D. Conversion is
accomplished via switches S1, S2 and S3 in state 1. Switch S 1
connects the input signal of the AD846 residue amplifier to
ground which minimized overload recovery tinIe.

THE AD846 AS AN OPEN-LOOP LEVEL SHIFTER
The AD846 can also be used for open-loop level shifting. As
shown in Figure 48, resistor Rs is used to develop an input current which is proportional to the input voltage, VIN • This current flows from the compensation node (Pin 5) developing a
voltage across resistor Re (Re is equal in value to resistor Rs)
which, rather than being grounded, has one end tied to reference voltage V2. The voltage appearing at Pin 5 is, therefore,
voltage V IN plus voltage V2 and will directly follow changes in
V IN • By scaling resistor Re, a level shift with voltage gain can
be produced.
In addition, the normal voltage output at Pin 6 is approximately
equal to the voltage at Pin 5 thus providing a low impedance,
buffered output for the level shifter.

v"'"

(BUFFEREDI

v,.

VOUT

(UNBUFFEREDI
-Vo

Figure 48. AD846 Connected as a Level Shift Amplifier

THE AD846 AS A HIGH SPEED DAC BUFFER
The AD846 will enable the AD568 12-bit DAC to develop a
10 V output step which settles to within 0.025 percent of its
final value in about 100 ns. This AD8461AD568 combination is
shown in the circuit of Figure 49. Correct power supply decoupiing is essential: a 2.2 ...F tantalum capacitor connected in parallel with a 0.1 ... F to 0.01 ... F ceramic disc capacitor is usually
sufficient. These should be placed as close to the power supply
pins as possible. Also, a ground plane should be employed; this
ensure that there is a low inIpedance signal path to ground
which allows the fastest possible output settling. In 12-bit systems with the AD846 operating at gains of 10 or less, inadequate supply decoupling can cause the output settling to degrade
from 100 ns to as much as 300 ns, with a 10 V output step
applied.

'""

RESULT

SWITCH POSITIONS:

1 '" FIRST PASS,MSBTO liT 7
Z K 2ND PASS. lIT 7 TO LSB.
PlU5OVERlAPBrTS •• l
'R1 AND RWI:' RATIO TO 0.0''11. 011 aenER

Figure 47. Block Diagram of a 2 MHz, 12-Bit Subranging
AID Converter

REV. A

Figure 49. The AD846 Serving as a DAC Buffer

OPERA T10NAL AMPLIFIERS 2-131

•

2-132 OPERATIONALAMPLIFIERS

~ANALOG

WDEVICES

High Speed, Low Power
Monolithic Up Amp
AD847 I

FEATURES
50 MHz Unity Gain Bandwidth
4.8 mA Supply Current
300 VI fJ.s Slew Rate
65 ns Settling TIme to 0.1% for a 10 V Step
0.04% Differential Gain
0.19" Differential Phase
Drives Capacitive· Loads
DC Performance
5.5 V/mV Open-Loop Gain into a 1 kG Load
1 mV max Input Offset Voltage
Performance Specified for ±5 V and ±15 V
Operetion
Available in Plastic. Hermetic Cerdip and
Small Outline Packages; Chips and
MIL-STD-883B Processing Available
Available in Tape and Reel in Accordance with
EIA-481A Standard
Dual Version Available: AD827
APPUCATIONS
Unity Gain Buffer
Cable Drivers
8- and 10-Bit Deta Acquisition Systems
Video and RF Amplification
Signal Generators
PRODUCT DESCRIPTION
The AD847 is a high speed, low power monolithic operational
amplifier. The AD847 achieves its combination of fast ac and
good de performance by utilizing Analog Devices' junction isolated complementary bipolar (CB) process. This process enables
the AD847 to achieve its high speed while only requiring
4.8 rnA of current from the power supplies.
The AD847 is a member of Analog Devices' family of high
speed op amps. This family includes, among others, the AD848,
which is stable at a gain of five or greater, and the AD849,
which offers 725 MHz of gain bandwidth at gains of 25 or
greater. For more demanding applications, the AD840, AD841
and AD842 offer even greater precision and greater output current drive.

CONNECTION DIAGRAM

•
NC = NO CONNECT

Plastic DIP (N), Small
Outline (R) and
Cerdip (Q) Packages
APPLICATION HIGHLIGHTS
1. The high slew rate and fast settling time of the AD847 make
it ideal for all types of video instrumentation circuitry, fast
DAC and flash ADC buffers, and line drivers.
2. As a buffer, the AD847 offers a full-power bandwidth of
30 MHz (for 2 V POp with Vs = ±5 V) making it outstanding as an input buffer for flash AID converters.
3. In order to meet the needs of both video and data acquisition
applications, the AD847 is optimized and tested for ±5 V
and ± 15 V power supply operation.
4. The low power and small outline packaging of the AD847
make it very well suited for high density applications such as
multiple pole active filters.
5. The AD847 is internally compensated for unity gain operation and remains stable when driving any capacitive load.
6. Laser wafer trimming reduces the input offset voltage to less
than 1 mV maximum on all AD847 grades, thus eliminating
the need for external offset nulling in many applications.
7. The AD847 is an enhanced replacement for the LM6161
series and can function as a pin for pin replacement for many
high speed amplifiers such as the HA2544, HA25201215 and
the EL2020.

The AD847 also has good dc performance. When operating with
±5 V supplies, it offers an open loop gain of 3,500 VIV (with a
500 n load) and low input offset voltage of 1 mV maximum.
Common-mode rejection is a minimum of 80 dB. Output voltage
swing is ±3 V even into loads as low as 150 n.

REV. B

OPERATfONALAMPLIFIERS 2-133

AD847 -SPECIFICATIONS (@T = +25·C, unless otherwise noted)
A

Model

AD841AR

AD841J
Coaditioas

INPUT OFFSET VOLTAGE'

Vs
±S V

Mia

Tnt

Mas

Tnt

Mas

Uaita

0.5

1
3.5

0.5

1
4

mV
mV

TMJN to TMAJ<

Offset Drift

Mia

IS

INPUT BIAS CURRENT

6.6
7.2

3.3

6.6
10

.,.A
.,.A

±SV,±ISV

50

300
400

50

300
500

nA
nA

TMJN to TMAJ<

Offset Cumnt Drift
OPEN-LOOP GAIN

0.3
Vo - ±2.5V
RwAD = 5000
TMJNtoTMAJ<
RLOAD = 1500
VOUT = ±IOV
RLOAD = I ItO
TMJNtoTMAJ<

DYNAMIC PERFORMANCE
Unity Gain Bandwidth
Full Power Bandwidth2

Slew Rate'
Settling Time to 0.1%

to 0.01%
Phase Margin

Differential Gain
Differential Phase
COMMON-MODE REJECTION

POWER SUPPLY REJECTION
INPUT VOLTAGE NOISE
INPUT CURlU!NT NOISE
INPUT COMMON-MODE
VOLTAGE RANGE

-2.5 V to +2.5 V
10V Step, Av = -I
-2.5 V to +2.5 V
10VSrep,Av = -I
~AD= 10pF
RLOAD =,1 kO
f - 4.4 MHz
f- 4.4 MHz

2
I

3.5
1.6

3
1.5

5.5

1.6

VImV

5.5

V/mV
VImV

MHz
MHz

12.7

12.7
4.7
200

225

225

78
18

140
120
SO
0.04
0.19

50
0.04
0.19

Degree

95

dB
dB

95

±15 V

±5V

+4.3
-3.4
+14.3
-13.4

±5V
±5V
±15 V
;tIS V
±15 V

3.0
2.5
12
10

300

DS

18
18

95

75
15
72

MHz
VillA
V/",s

65
65
140
120

6S

±ISV
±IS V

MHz

35
50

4.7
200
300
65

±IS V

Shon-Circuit Cumnt

VImV
V/mV

±IS V
±SV
±IS V
±SV
±IS V
±5V
±IS V
±ISV

f - 10kHz

5000
1500
I ItO
5000

3.5

±SV

±SV
±IS V

=
=
=

3
1.5

35
50

VCM - ±2.5 V
VCM = ±12V
RJN = 100 0 (See Figure 20)
TMJN to TMAJ<
Vs - ±SVto±ISV
TMJN to TMAJ<
f - 10kHz

RLOAD
RLOAD
RLOAD
RLOAD

2
I

±ISV

±IS V
OUTPUT VOLTAGE SWING

nArc

0.3

±SV

±SV
±ISV
Vo =5Vp-p
RL = 5000,
Vo =20Vp-p,
RL = I ItO
RLOAD = lItO

",vrc

3.3

TMJNtoTMAJ<
INPUT OFFSET CURlU!NT

IS

±5 V, ±ISV

DS
DS
DS

%
Degree

95

75
86

75
72

dB

86

dB
dB

15

IS

1.5

1.5

nVlYHi
pA/y'HZ

+4.3
-3.4
+14.3
-13.4

V
V
V
V

3.6
3

±V
±V
±V
±V

3.6
3

3.0
2.5
12
10

32

32

mA

INPUT RESISTANCE

300

300

ItO

INPUT CAPACITANCE

1.5-

1.5

pF

15

IS

0

OUTPUT RESISTANCE

Open Loop

POWER SUPPLY
Operating Range
Quiescent Current

:t: 4.5
±5V

4.B

±IS V

S.3

TMJNtoTMAJ<
TMJNtoTMAJ<

:dB
U
7.3
6.3
7.6

:t:4.5
4.8
5.3

:t:18
6.0
7.3
6.3
7.6

V
mA
mA
mA
mA

NOTES
lInput Oftiet Vol. Specifications are ........teed Ifte< S minutelat TA = +2S"C.

2FuR Power Batulwidth = S.... Ratel2" VPI!Alt.
·S.... Rate is meuured em risiDg edae.

AU min and max specifications are 1IUIf8I1teed. Specifications in boIcI&ce are 100% tested at fiDaJ electrical telt.
Specifications subject to cbaDge without notice.

2-134 OPERATIONAL AMPLIFIERS

REV.B

AD847
Model

AD847AQ

CorulitiODS
INPUT OFFSET VOLTAGE I

Vs

Min

±5V

Typ

Mas

0.5

I
4

TMIN to TMAX

Offset Drift

Min

IS

INPUT BIAS CURRENT

±5 V, ±15 V

3.3

INPUT OFFSET CURRENT

±5V,±15V

50

TMIN toTMAX

Offset Current Drift
OPEN LOOP GAIN

DYNAMIC PERFORMANCE
Unity Gain Bandwidth
Bandwidth2

Slew Rate'
Settling Time to 0.1%
to 0.01%
Phase Margin
Differential Gain
DiffereDtiai Phase

Vo = 5 Vp-p
RL = 500 n,
Vo = 20 V p-p,
RL=Ik!l
RLOAD = IkO
-2.5 V to +2.5 V
10 V Step, Av = -I
-2.5 V to +2.5 V
10 V Step, Av = -I
CLOAD = 10 pF
R LOAD = I k!l
f- 4.4 MHz
f~ 4.4 MHz

COMMON·MODE REJECTION

VCM = ±2.5 V
VCM=±12V
R'N = 100 n (See Figure 20)
TMIN to TMAX

POWER SUPPLY REJECTION

Vs - ±5Vto±15V
TMIN toTMAX

Mas

Uaits

0.5

I
4

mV
mV

5
7.5

..,A
..,A

300
400

nA
nA

IS

5

3.3

300
400

50

0.3
Vo - ±2.5 V
R LOAD = 500 n
TMIN toTMAX
RLOAD = 150n
VOUT = ±IOV
RLOAD = I k!l
TMIN to T MAX

Typ

7.5

TMIN to T MAX

Full Power

AD847S

±5V

z

3.5

2
I

I
1.6

..,vrc

0.3

nArc

3.5

V/mV
VImV
V/mV

1.6

±15V
3
1.5

5.5

3
1.5

5.5

VImV
V/mV

±5V
±15 V

35
50

35
50

MHz
MHz

±5 V

12.7

12.7

MHz

±15 V
±5V
±15V
±5V
±15V
±5V
±15V
±15V

4.7
200
300
65
65
140
120

4.7
200

MHz
VI..,.
VI..,.
D.
os
DS
DS

225

80
80

80
80

95
95

75
75
72

300
65
65
140
120

50
0.04
0.19

±15V
±15V
±5V
±15V

225

Degree

50
0.04
0.19

%

95
95

dB
dB

86

dB
dB

Degree

75
86

75
72

dB

INPUT VOLTAGE NOISE

f - 10 kHz

±15V

IS

15

DVly'Hi

INPUT CURRENT NOISE

f-lOkHz

±15V

1.5

1.5

pNVHZ

±5V

+4.3
-3.4
+14.3
-13.4

+4.3
-3.4
+14.3
-13.4

V
V
V
V

3.6
3

±V
±V
±V
±V

32

32

mA

INPUT RESISTANCE

300

300

k!l

INPUT CAPACITANCE

1.5

1.5

pF

15

15

n

INPUT COMMON-MODE
VOLTAGE RANGE

±15V
OUTPUT VOLTAGE SWING

RLOAD
RLOAD
RU)AD
R LOAD

=
=
=
=

500 n
150n
I k!l
500 0

Short-Circuit Current

OUTPUT RESISTANCE

±5V
±5 V
±15V
±15V
±15V

OpeD Loop

POWER SUPPLY
Operating Range
Quiescent Current

3.6
3

10

4.8

to T MAX

±15 V
TMIN to T MAX

3.0
2.5

12

:i: 4.5
±5 V
TMIN

REV.B

3.0
2.5
12
10

5.3

:1:18
5.7
7.0
6.3
7.6

:i:4.5
4.8
5.3

:1:18
5.7
7.8
6.3
8.4

V

mA
mA
mA
mA

OPERATIONAL AMPLIFIERS 2-135

•

AD847
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage ....•..•.....•...•..••...•. ±IS V
Intemal Power Dissipation2
Plastic (N) . . . . • • . . . . . . • . . . • . . . . • . . . . 1.2 Watts
Small Outline (R) •....•.•••.•.•........ O.S Watts
Cerdip (Q) ..•.•....•.•.•..••.•...... 1.1 Watts
Input Voltage . . . . • • . . . . . . • . . . . . . . . . . . . . . . . ±Vs
Differential Input Voltage • . . . . • • . . . • . . • . . • • • • • ± 6 V
Storage Temperature Range Q .••....... -6S"C to + ISO"C
N, R ••.•.•.•••••...•.•....... -6S"C to +.12S"C
Junction Temperature ..•.....•.....••....•.• 17S"C
Lead Temperature Range (Soldering 60 sec) .....•... 300"C

CONNECTION DIAGRAM
Plastic DIP (N), Small
Outline (R) and
Cerdip (Q) Packages

NOTES
' S _ above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. 1'!rls is a stress rating only, and functional
operation of the device at tbeIc or any other conditions above those indicated
in the operational section of this specification is Dot implied. Exposure to
absolute DIIllIimum rating conditions for extended periods may affect device

reliability.
2Mini-DIP Package: 6JA

NC = NO CONNECT

= lOO"CJWatt; 6Je = 33'CIWan

Cerdip Package: OJA = UO'CIWatt; O'C = 3O'CIWatt
Small Outline Package: 6JA = lSS'CIWatt; 0JC = 33'CIWatt

METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
t-------~=----------I

7 +Vs

-INPUT

6 OUTPUT

4 -Vs

SUBSTRATEcONNECTEDTO +V.

ORDERING GUIDE

Modell
AD847JN
AD847JR
AD847AQ
AD847AR3
AD847SQ

AD847SQ/883B
AD848JIAIS
AD849]IAlS

Gain
Bandwidth
MHz
50
50
50
50
50
50
175
725

Minimum
Stable
Gain
I
I
I
I
1
1
5
25

Maximum
Offset Voltage
mV
I
I
I
I
I
1
I
1

Temperature
Range _·C

Package
Description

Package
Option2

o to
o to

Plastic
SOIC
Cerdip
SOIC
Cerdip
Cerdip

N-8
R-8
Q-8
R-8
Q-8
Q-8

+70
+70
-40 to +85
-40 to +85
-55 to + 125
-55 to + 125
See AD848 Data Sheet
See AD849 Data Sheet

NOTES
I ADS47 also available in J and S grade chips, and ADS47JR is available in tspe and reel.
'N = Plastic DIP; Q = Cerdip; R = SOIC. For outline information see Package Information section.
3Contact sales office for detailed information.

2-136 OPERATIONAL AMPLIFIERS

REV.B

AD847
Typical Characteristics (@ +25°C and Vs = ±25°C and Vs = ±15 V, unless otherwise noted)
20

20

//

-!> 1
•
",

I

r
0

~

8 •

o

,

I!i.

V-VIN

+%V

10

~

5

4~

·0

20

15

3.
2

-6

•

J

!

If

,20

I..
~

" 5.5

/
,/"""

/

5

•,.~

V

E

,

ia

15V SUPPLIES

15

">~ ,.

"

20

Figure 2. Output Voltage Swing
vs. Supply Voltage

Figure 1. Input Common-Mode
Range vs. Supply Voltage

I>

RLOAo =500n

5
10
15
SUPPLY VOLTAGE - :tVolts

SUPPLY VOLTAGE - ;tVoJb

..

•

IfVvOUT

i

5

'0

./

~ 15

Y

i

o

~

11

V

..-

±5VSUPPUES

~

I,..

100
1k
LOAD RESISTANCE _ n

-----

5

I

" 4.5

4

•

./

10

15

20

SUPPLY VOLTAGE - ::I:Volts

Figure 4. Quiescent Current
vs. Supply Voltage

Figure 3. Output Voltage Swing
vs. Load Resistance

100

/
'1,

4

.\

ia ,'\
i!;

/

"-

3

~

2
-80 -40

V s "':t:5V

"

/

r-- l -

t--

20

1/

1

~t-"

... ,..
1

-20

1/

1

40

60

80

100 120 140

TEMPERATURE - OC

Figure 5. Input Bias Current
vs. Temperature

REV.B

/

0

lOOk

1M
FREQUENCY - Hz

10M

100M

Figure 6. Output Impedance
vs. Frequency

OPERATIONAL AMPLIFIERS 2-137

AD841 ~ Typical Characteristics (@ +25"C and Vs = ::t25"C and Vs = ::t15 V, unless otherwise noted)

.
1/

Cl
E

,

V

/

!•

,..-

- :'\
1\

1

V

/

!V

/'

I

~
I\,

/

•

~

v·~r&V

"

3
-60 -40 -20

0
20 40
60 80
TEMPERATURE - "C

,.

100 120 140

-60

Figure 7. Quiescent Current VB. Temperature

-~

-20 0
20 40 60 80 100
AMBIENT TEMPERATURE - "C

Figure 8. Short-Circuit Current
Limit vs. Temperature

100

2

120 140

'-

- -

+100"

...

,

~ .J.v8ulES

1

\

11dlLOAD

::t5VSUPPLIES" ' \

..... LOAD

f-

~

\

I
I

~

~

•

•

I
4 -60 -40 -20

0

20

40

80

TEMPERATURE -

10 100 120 140

-c

-20
100

..

\

~

~

1k

10k
lOOk
1M
FREQUENCY - Hz

10M

100M

Figure 10. Open-Loop Gain and
Phase Margin VB. Frequency

Figure 9. Gain Bandwidth Product
VB. Temperature

Iv.I. Izt.v vII...··A-t/

V.-:t5V

!II

~"r----r~~~--4----i--~

VV
V

..
..,.

\

~

=
i"

i201----+----+----+-.......-t'~

I

100
,.
LOAD RESISTANCE - U

.

,

Figure 11. Open-Loop Gain VB. Load Resistance

2-138 OPERATIONAL AMPLIFIERS

~~.--~1="--~1=o.~~1±M~~~~~
FREQUENCY - HI:

Figure 12. Power Supply Rejection VB. Frequency

REV. B

AD847

.. -

,ao

30

'"

.
..

N:·16V

VCM =:tlVp-p

~

,.

,=,kG

"-

"-

'0'

0

'OOk

,M
FREQUENCY - Hz

10M

100M

'0

/

.

g

I

2

V

0.1'"

,%

0.1"-

S

0-

-,

'I,

20

40

-90

ZNDHARMONIC

I-'ao

V ...

1-"
.

./

0

'\

o

3V~
....=1kR

~

'\..

•
•
0

I

-80

\ \

!;i-

'OM

/

",

i'..

'"

60

80

iiill

%-120

~

100

120

140

110

-,oo,ao

Figure 16. Harmonic Distortion vs. Frequency

50

. .0

.. 1\

...
...

\

/'

_\

/'

'-.,

'0

,ao

".,

.... /

./

/V

,.

'Ok

,.

1M

10M

FREQUENCY _ Hz

Figure 17. Input Voltage Noise Spectral Density

REV. B

,ao.

10k

FREQUENCY - HI:

Figure 15. Output Swing and Error vs. Settling Time

o

II

1It

S£TTLiNG TIME - ns

1:2

""r--. ,-

-70

/

.~-•

,M

Figure 14. Large Signal Frequency Response

./"

I

>

0

"-

INPUT FREQUENCY-Hz

Figure 13. Common Mode Rejection vs. Frequency

2

1'\

5

0

o

r-- ~

25

'50

-eo

-40 -20

0
20 40 8D
TEMPERATURE _ '"C

eo

100 120 140

Figure 18. Slew Rate vs. Temperature

OPERATIONAL AMPLIFIERS 2-139

•

AD847
lItO

HP3314A

FUNCTION
GENERATOR

FET
PROBE

2.5MHz

TEK
7A24

OSCILLOSCOPE

Figure 19. Inverting Amplifier
Configuration

Figure 19a. Inverter Large
Signal Pulse Response

Figure 19b. Inverter Small
Signal Pulse Response
R.
1250

+15V

FET

TEK

PROBE
HP3314A

7A24

OSCILLOSCOPE

FUNCTION
GENERATOR

lkO

2.5MHz

Figure 20. Noninverting Amplifier
Configuration

Figure 20a. Noninverting
, Large Signal Pulse Response

2-140 OPERATIONAL AMPLIFIERS

Figure 20b. Noninverting
Small Signa/. Pulse Response

REV. B

AD847

•

Figure 21. Offset Nulling
OFFSET NULUNG
The input offset voltage of the AD847 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 21 can be used.
INPUT CONSIDERATIONS
An input resistor (RIN in Figure 20) is required in circuits
where the input to the AD847 will be subjected to transient or
continuous overload voltages exceedins the ±6 V maximum differentiallimit. This resistor provides protection for the input
transistors by limiting the maximum current that can be forced
into their bases.
For high performance circuits it is recommended that a resistor
(RB in Figures 19 and 20) be used to reduce bias current errors
by matching the impedance at each input. The offset voltage
error caused by the offset current is more than an order of magnitude less.
THEORY OF OPERATION
The AD847 is fabricated on Analog Devices' proprietary complementary bipolar (CB) process which enables the construction
of pnp and npn transistors with similar f,.s in the 600 MHz to
800 MHz region. The AD847 circuit (Figure 22) includes an
npn input stage followed by fast pnps in the folded cascade
intermediate gain stage. The CB pnps are also used in the current amplifying output stage. The internal compensation capacitance that makes the AD847 unity gain stable is provided by the
junction capacitances of transistors in the gain stage.
The capacitor, Cp , in the output stage mitigates the effect of
capacitive loads. At low frequencies and with low capacitive
loads, the gain from the compensation node to the output is
very close to unity. In this case Cp is bootstrapped and does not
contribute to the compensation capacitance of the pan. As the
capacitive load is increased, a pole is formed with the output
impedance of the output stage. This reduces the gain, and therefore, C p is incompletely bootstrapped. Some fraction of C p contributes to the compensation capacitance, and the unity gain
bandwidth falls. As the load capacitance is increased, the bandwidth continues to fall, and the amplifier remains stable.

REV. B

-v.
NULL 1

NULLa

Figure 22. AD847 Simplified Schematic
GROUNDING AND BYPASSING
In designing practical circuits with the AD847, the user must
remember that whenever high frequencies are involved, some
special precautions are in order. Circuits must be built with
shon interconnect leads. A large ground plane should be used
whenever possible to provide a low resistance, low inductance
circuit path, as well as minimizing the effects of high frequency
coupling. Sockets should be avoided because the increased interlead capacitance can degrade bandwidth.
Feedback resistors should be of low enough value to assure that
the time constant formed with the capacitances at the amplifier
summing junction will not limit the amplifier performance.
Resistor values of less than 5 k!l are recommended. If a 1arger
resistor must be used, a small «10 pF) feedback capacitor in
parallel with the feedback resistor, R p , may be used to compensate for the input capacitances and optimize the dynamic performance of the amplifier.
Power supply leads should be bypassed to ground as close -as
possible to the amplifier pins. 0.1 fJoFceramic disc capacitors are
recommended.

OPERATIONAL AMPLIFIERS 2-141

AD841
VIDEO LINE DRIVER

Figure 24 shows the AD847 driving 100 pF and 1000 pF loads.

The AD847 functions very well as a low cost, high speed line
driver for either terminated or unterminated cables. Figure 23
shows the AD847 driving a doubly terminated cable in a follower configuration.

me

The termination resistor, Rr, (when eqqal to
cable's characteristic impedance) minimizes reflections from the far end of the
cable. While operating from ±5 V supplies, the AD847 maintains a typical slew rate of 200 V/tJ.S, which means it can drive a
±l V, 30 MHz signal into a terminated cable.

10DpF
LOAD

,_.
LOAD

+Va
Figure 24. AD847 Driving Capacitive Loads

FLASH ADC INPUT BUFFER
The 35 MHz unity gain bandwidth of the AD847 when operated
with ± 5 V supplies makes it an excellent choice for buffering
the input of high speed flash AID converters, such as the

AD9048.
Figure 25 shows the AD847 as a unity inverter for the input to
theAD9048.

c"
SEE TABLE I

Figure 23.· Video Line Driver
Table I. Video Line Driver Performailce Chart

VIN•
odB or
odB or
odB or
o dB or
odB or
odB or
NOTE

±500 mV
±SOO mV
±SOO mV
±SOO mV
±SOO mV
±SOO mV

Step
Step
Step
Step
Step
Step

Bw

VSUPPLY

Cc

-3 dB

±IS
±IS
±IS

20pF
15 pF
OpF
20pF
IS pF
OpF

23 MHz
21 MHz
13 MHz
18 MHz
16 MHz
11 MHz

±S
±S
±S

Over-

shoot
4%
0%
0%

2%
0%
0%

*-3 dB bandwidth numbers an: for the 0 dBm signal inpUt. Overshoot numbers an: the percent overshoot of the I volt step input.

A back-termination resistor (RBT, also equal to the characteristic
intpedance of the cable) may be placed between the AD847 output and the cable input, in order to damp any reflected signais
caused by a mismatch betWeen Rr and the cable's charactmstic
intpedance. This will result in a flatter frequency reSPonse,
although this requires that the op amp supply ±2 V to the output in order to achieve a -1 V swing at resistor Rr.

2-142 OPERATIONAL AMPLIFIERS

Figure 25. Flash ADC Input Buffer

REV.B

AD847
A IfiIh Speed, Three Op-Amp In-Amp
The circllit of Figure 26 lends itself well to CCD imaging and
other video speed applications. It uses two high speed CB process op-amps: Amplif1Cl' A3, the output amplifier, is an AD847.
The input amplifier (AI and A2) is an AD827, which is a dual
version of the AD847. This circuit has the optional flexibility of
both de and ac trims for common-mode rejection, plus the ability to adjust for minimum settling time.

+15VO

COMMO

EACH
AMPLIFIER

1

I

1~
10llF
I

+Vs

IlllF I

O 1IlF
•

110llF 10.:F
-15VO

1 ..

>1

-Vs

Input
Frequency

CMRR

100 Hz
I kHz
10 kHz
100 kHz
I MHz
10 MHz

88.3
87.4
86.2
67.4
47.1
26.4

dB
dB
dB
dB
dB
dB

:~
PIN/'

O•1IlF AD827

>
2-8pF
SETTLING TIME
AC CMR ADJUST

21<0

21<0

2kQ
lkQ

CIRCUIT GAIN = 20000 + 1
RG

Bandwidth, Settling Time and Total Harmonic Distortion

Gain

Ra

(PF)

Small Signal
Bandwidth

1
2
10
100

Open

2-8
2-8
2-8
2-8

16.1 MHz
14.7 MHz
4.5 MHz
660 kHz

CAD]

2kO
2260
2000

VB.

Gain

Settling Time
to 0.1%

THD+Noise
Below Input Level
@10kHz

200 ns
200 ns
370 ns
2.5 1105

82
82
81
71

dB
dB
dB
dB

Figure 26. A High Speed In-Amp Circuit for Data Acquistion

REV.B

OPERA TlONAL AMPLIFIERS 2-143

•

AD847
IDGB SPEED DAC BUFFER
The wide bandwidth and fast settling time of the AD847 makes
it a very good output buffer for high speed current-output D/A
converters like the ADDAC-08. Figure 28 shows the ADDAC08 with the AD847 as the current to voltage converter. In this
unipolar configuration the output swing ranges from 0.00 V to
+9.96V.

pin. A -10.0 V to +9.92 V bipolar output is achievable by connecting a 10 kO resistor between the ADS87 output and the
AD847 input and replacing Rp with a 10 kO resistor.

Figure 27 shows the full scale settling time of this circuit when
the digital codes are changed from allIs to all Os. For the
+9.96 V to 0.00 V output change shown 1 LSB = 40 mV the
overall settling time of the circuit is 140 DS.

AD847

OUTPUT

The variable feedback capacitor, Cp , is used to optimize the settling time of the circuit by compensating for the additional pole
created by Rp and the stray capacitance at the inverting input

DIGITAL

INPUT

Figure 27. Settling Time for AD DAC-OB and AD847
Combination
+Vs

C.
O.2pF-5pF
+Vs

-VS

R.

4.99kfi
SETTLING TIME TEST CIRCUIT

}----4~_vv-..........- ;

TEK7613
OSCILLOSCOPE
7A13
AMPLIRER

2x
IN6263

Figure 28. High Speed DAC Buffer

2-144 OPERA TIONAL AMPLIFIERS

REV.B

11IIIIIIII

High Speed, Low Power
Monolithic Op Amps
AD848/AD849 I

ANALOG

WDEVICES
FEATURES
725MHz Gain Bandwidth - AD849
175MHz Gain Bandwidth - AD848
4.8mA Supply Current
300VIlLS Slew Rate
SOns Settling Time to 0.1 % for a 10V Step - AD849
Differential Gain: AD848 0.07%, AD849 0.08%
Differential Phase: AD848 0.08°, AD849 0.04°
Drives Capacitive Loads

=
=

=
=

CONNECTION DIAGRAM
AD848 and AD849

•

Plastic (N), Small
Outline (R) and
Cerdip (a) Packages

DC PERFORMANCE
3nVtv'Hz Input Voltage Noise - AD849
85V/mV Open Loop Gain into a 1kfl Load - AD849
1mV max Input Offset Voltage
Performance Specified for ±5V and ±15V Operation
Available in Plastic, Hermetic Cerdip and Small Outline
Packages. Chips and MIL-STO-883B Parts Available.
Tape and Reel Also Available

(AD848 with a soon load) and low input offset voltage of ImV
maximum. Common-mode rejection is a minimum of 92dB.
Output voltage swing is ±3V even into loads as low as 150n.

APPLICAnONS
cable Drivers
8- and 1G-Bit Data Acquisition Systems
Video and RF Amplification
Signal Generators

APPLICATIONS HIGHLIGHTS
1. The high slew rate and fast settling time of the AD848 and
AD849 make them ideal for video instrumentation circuitry,
low noise preamps and line drivers.

PRODUCT DESCRIPTION
The AD848 and AD849 are high speed, low power monolithic
operational amplifiers. The AD848 is internally compensated so
that it is stable for closed loop gains of 5 or greater. The AD849
is fully decompensated and is stable at gains greater than 24.
The AD848 and AD849 achieve their combination of fast ac and
good dc performance by utilizing Analog Devices' junction isolated complementary bipolar (CB) process. This process enables
these op amps to achieve their high speed while only requiring
4.8mA of current from the power supplies.
The AD848 and AD849 are members of Analog Devices' family
of high speed op amps. This family includes, among others, the
AD847 which is unity gain stable, with a gain bandwidth of
50MHz. For more demanding applications, the AD840, AD841
and AD842 offer even greater precision and greater output current drive.

NC = NO CONNECT

2. In order to meet the needs of both video and data acquisition
applications, the AD848 and AD849 are optimized and tested
for ±5V and ± 15V power supply operation.
3. Both amplifiers offer full power bandwidth greater than
20MHz (for 2V POp with ±5V supplies).
4. The AD848 and AD849 remain stable when driving any
capacitive load.
5. Laser wafer trimming reduces the input offset voltage to
ImV maximum on all grades, thus eliminating the need for
external offset nulling in many applications.
6. The AD848 is an enhanced replacement for the LM6164
series and can function as a pin-for-pin replacement for many
high speed amplifiers such as the HA2520/2/5 and EL2020 in
applications where the gain is 5 or greater.

The AD848 and AD849 have good dc performance. When operating with ±5V supplies, they offer open loop gains of BV/mV

REV. A

OPERA TlONAL AMPLIFIERS 2-145

AD848/AD849---SPECIFICATIONS
Model

Conditions

INPUT OFFSET VOLTAGE'

"'

T_ toT.,..

Offset Drift
INPUT BIAS CURRENT
T_toT....
INPUT OFFSET CURRENT

Tmin to Tmax
Offset Current Drift
OPEN LOOP GAIN

Vo=±2.SV
R LOAo =5000

DYNAMIC PERFORMANCE
Gain Bandwidth
Full Power Bandwidth2

AVCL~5

Vci=2Vp·p,
R L ",5000
Vo=20V p-p,
RL=lkO

Slew Rate
Settling Time to 0.1%

RLOAD=lkO
-2.5Vto +2.SV
lOY Step, Av = -4

Phase Margin

~oAD=IOpF

AD848A/S

Typ

Max

±5V
±15V
±SV
±15V
±5V, ±15V

0.2
0.5

1
2.3
1.5
3.0

±5V, ±ISV
±SV, ±15V

3.3

±5V,
±5V,
±5V,

50

Min

Min

7

15V
15V
15V

Typ

Max

Vaits

0.2
O.S

1
2.3
2
3.5

mV
mV
mV
mV
JLVre

6.615

!LA
!LA

7
6.6
7.2

3.3

300
400

50

7.5
300

400

0.3

0.3

nA
nA
nArc

±5V
9
7

13

9

VlmV
V/mV
V/mV

13

7/5
8

8

±15V
12

20

12
8/6

8

20

V/mV
V/mV

±5V
±15V

125
17S

12S
17S

MHz
MHz

±5V

24

24

MHz

4.7
200
300
6S
100

MHz
VljL'
V/jL'
ns
ns

±15V
±5V
±15V
±5V
±15V
±ISV

22S

RLOAo=lkO
DIFFERENTIAL GAIN

f=4.4MHz

±15V

DIFFERENTIAL PHASE

f=4.4MHz

±15V

COMMON-MODE REJECTION

VCM =±2.5V
VCM=±12V
T_toTmax

±SV
±15V

POWER SUPPLY REJECTION

= +25°C, unless otherwise noted)

AD848J

v.

Tmin to Tmax
R LOAo =1500
VoUT =±IOV
RLOAo=lkO
T_toTmax

(@TA

4.7
200
300
65
100

225

60

60

Degree.

0.07

0.07

%

0.08
92

92

lOS
lOS

88

Vs= ±4.5V to.±ISV
T_toTmax

85
80

98

0.08

Degree

92
92
88

lOS
105

dB
dB
dB

85

98

dB
dB

80

INPUT VOLTAGE NOISE

f=lOkHz

±15V

S

5

nV/yHz

INPUT CURRENT NOISE

f=IOkHz

±15V

1.5

I.S

pA/yHz

±SV

+4.3
-3.4
+14.3
-13.4

+4.3
-3.4
+14.3
-13.4

V
V
V
V

3.6
3
1.4

±V
±V
±V
±V
±V

INPUT COMMON·MODE
VOLTAGE RANGE

±ISV
OUTPUT VOLTAGE SWING

RLoAo=SOOO
RLoAo=ISOO
RLOAO=SOO
RLoAo=lkO
RLOAO=SOOO

±SV
±SV
±SV
±ISV
±ISV

3.0
2.5

3.6
3
1.4

3.0
2.5

12
10

12
10
32

32

rnA

INPUT RESISTANCE

70

70

kO

,INPUT CAPACITANCE

I.S

1.5

pF

IS

15

0

SHORT CIRCUIT CURRENT

OUTPUT RESISTANCE

±15V

Open Loop

POWER SUPPLY
Operating Rangt
Quiescent Current

:t:4.5
±5V

4.8

±ISV

5.1

Tmin to Tmax
T_toTmax

:t:18
6.0
7.4
6.8
8.0

:t:4.5
4.8
S.I

d8
6.0
7.418.3
6.8
8.019.0

V

rnA
rnA
rnA
rnA

NOTES
'Input ofUet voltqe specifications an: guaranteed after 5 minutes at T A ~ + 25'C.
ZFull

power bandwidth=s1cw ratel21f VpEAK , Refer to Figure 1.

All min and

DlU

specifications are guaranteed. Specifications in boldface are tested on all production units at fmal electrical test. All others are guaranteed but

not necessarily tested.

Specifications subject to change without notice.

2-146 OPERA T10NAL AMPLIFIERS

REV. A

AD848/AD849
Model

Conditions

INPUT OFFSET VOLTAGE'
Tmill

to Tmax

Offset Drift
INPUT BIAS CURRENT

Tmin to Tmax
INPUT OFFSET CURRENT

Tmin to Tmax
Offset Current Drift
OPEN LOOP GAIN

DYNAMIC PERFORMANCE
Gain Bandwidth
Full Power Bandwidth'

Vs

0.3
0.3

±SV, ±lsV
±SV, ±lsV

3.3

6.6
7.2

±SV, ±lsV
±SV, ±ISV
±SV, ±lsV

SO

300
400

±SV

AvcL"'2s

±SV
±lsV

Slew Rate

mV
mV
mV
mV
...vrc

3.3

6.6/5
7.5

~
~

SO

300
400

nA
nA
nArC

2

0.3

0.3
30
20/15

50

Units

0.75
0.75
1.0
1.0

SO

V/mV
V/mV
VlmV

32

±lsV
45
30

SS

VlmV
V/mV

520
725

520
725

MHz
MHz

±sv

20

20

MHz

±15V
±SV
±lsV
±SV
±lsV
±lsV

4.7
200
300
65
SO

4.7
200
300
65
SO

MHz
VI ....
VI ....
n.

DIFFERENTIAL PHASE

f=4.4MHz

±lsV

VCM=±2.sV
VcM =±12V

±sV
±lsV

Tmin

0.1
0.1

32

COMMON·MODE REJECTION

POWER SUPPLY REJECTION

1
1
1.3
1.3

20

DIFFERENTIAL GAIN

Phase Margin

AD849AJS
Typ
Max
Min

2

30

RLOAo=lkn
-2.SV to +2.sV
IOV Step, Av = - 24
CLOAO = IOpF
RLoAo=lkn
f=4.4MHz

Settling Time to 0.1%

Max

±SV
±lsV
±SV
±lsV
±SV, ±lsV

Vo=±2.5V
R LoAo =500n
T min to T max
RLoAo=lsOn
VouT=±IOV
RLOAo=lkn
Tmin to Tmax

Vo =2Vp-p,
RL=sOOn
Vo=20V p.p,
RL=lkn

AD849J
Min Typ

225

±lsV

to Tmax

V.=±4.sVto ±ISV

Tmin to Tmax

S5

45
30125

225

ns

60

60

Degrees

O.OS

O.OS

%

0.04

Degree

100
100
96

0.04
115
1lS

100
100
96

115
115

dB
dB
dB

9S
94

120

98
94

120

dB
dB

INPUT VOLTAGE NOISE

f= 10kHz

±lsV

3

3

nV/ylHz

INPUT CURRENT NOISE

f= 10kHz

±lsV

1.5

1.5

pAJylHz

±SV

+4.3
-3.4
+14.3
-13.4

+4.3
-3.4
+14.3
-13.4

V
V
V
V

3.6
3
1.4

±V
±V
±V
±V
±V

INPUT COMMON-MODE
VOLTAGE RANGE

±lsV
OUTPUT VOLTAGE SWING

R LOAo =500n
R LoAD = Ison
RLoAo=son
R LOAo =lkn
R LOAo =500n

±SV
±SV
±sv
±lsV
±lsV

3.0
2.5

3.6
3
1.4

3.0
2.5

12
10

12
10
32

32

rnA

INPUT RESISTANCE

25

25

kn

INPUT CAPACITANCE

1.5

1.5

pF

IS

IS

n

±lsV

SHORT CIRCUIT CURRENT

OUTPUT RESISTANCE

Open Loop

POWER SUPPLY
Operating Range
Quiescent Current

±4.5
±SV

4.S

±ISV

5.1

T min to Tmax
T min to Tmax

±IS
6.0
7.4
6.S
8.0

±4.5
4.S
5.1

±IS
6.0
7.418.3
6.S
8.0/9.0

V
rnA
rnA
mA
rnA

NOTES
llnpul offset voltage specifications are guaranteed after 5 minutes at TA = +25OC.
lpull power bandwidth=s1ew ratel211' VPEAK ' Refer to Figure 2.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electricaJ test. All others are guaranteed but
not necessarily tested.
Specifications subject to change without nmice.

REV. A

OPERATIONAL AMPLIFIERS 2-747

•

AD848/AD849
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage . . . • . . . . . . . . . . . . . . . . . . . . . . . . ±ISV
Internal Power Dissipation2
Plastic (N) . . . . • . . . . . . . • . . . . . . . . . . . . . . 1.1 Watts
Small Outline (R) . . . . . . . . . . . . . . . . . . . . • .0.9 Watts
Cerdip (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Watts
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±Vs
Differential Input Voltage . . . • . . . . . . . . . . . . . . . . . . +6V
Storage Temperature Range Q . . . . . . . . . . . -65°C to + 150°C
N, R . . . . . . . . . . . . . . . . . . . . . . . . . . -65OC to + 125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . • . . + 175°C
Lead Temperature Range (Soldering 60sec) . . . . . . . . . + 300°C

METALIZATION PHOTOGRAPH
Contact factory for late.st dimensions. (AD848 and AD849 are identical
except for the part number in the upper right.)
Dimensions shown in incbes and (mm).

·Suesses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
'Mini·DlP Package: alA = 11O"C Watt.
Cerdip Package: alA = IIO"C Watt.
Small Outline Package: alA = ISS"C Watt.
sussmATE CONNECTED TO +Vs

ORDERING GUIDE
Gain
Bandwidth
MHz

Min
Stable
Gain

Max
Offset Voltage
mV

ADS48JN
ADS4SJR
AD848AQ
ADS4SSQ
ADS48SQf883B

175
175
175

175
175

5
5
5
5
5

AD849JN
AD849JR
AD849AQ
AD849SQ

AD849SQ/883B

725
725
725
725
725

AD847JIAIS

50

Model

Temperature
Range - °C

Package
Option1 ,2

1
1
1
1
1

o to +70
o to +70

N·8
R·S
Q-S
Q-S
Q·8

25
25
25
25
25

1
1
0.75
0.75
0.75

oto +70
oto +70

1

1

-40 to +85
-55 to + 125
-55 to + 125

-40 to +85
-55 to + 125
-55 to + 125

N-S
R·8
Q·8
Q·8
Q-8

See ADS47 Data Sheet

NOTES
'Plastic SOIC (R) available in tape and reel. AD848 available in S grade chips. AD849 available in
J and S grade chips.
'N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC). For outline information see Package
Information section.

2-148 OPERATIONAL AMPLIFIERS

REV. A

AD848/AD849
R,
4.99kll

R,
12.5kll
+15V

HP3314A

;EUN~~W~R f--......VV'.-+-(
2.5MHz

FET

PROBE

HP3314A

TEK
7A24
OSCILLOSCOPE

Figure 1. AD848 Inverting Amplifier Configuration

Figure 1a. AD848 Large Signal
Pulse Response

Figure 1b. AD848 Small Signal
Pulse Response

;EUN~~W~R f--......VV'.-+-(
2.5MHz

FET
PROBE

TEK
7A24
OSCILLOSCOPE

Figure 2. AD849 Inverting Amplifier Configuration

Figure 2a. AD849 Large Signal
Pulse Response

Figure 2b. AD849 Small Signal
Pulse Response

OFFSET NULLING
The input voltage of the AD848 and AD849 are very low for
high speed op amps, but if additional nulling is required, the
circuit shown in Figure 3 can be used.
For high performance circuits it is recommended that a resistor
(R B in Figures I and 2) be used to reduce bias current errors by
matching the impedance at each input. The offset voltage error
caused by the input currents is decreased by more than an order
of magnitude.

Figure 3. Offset Nulling

REV. A

OPERATIONAL AMPLIFIERS 2-149

•

AD848/AD849-Typical Characteristics (@ +25°C and Vs=±15V. unless otherwise noted)
30

30

.

1".•

.

t

il

---

5

I

04.5

t"\

/

i\

V

'\

/'

\
•

•o

10

0

15

Figure 4. Quiescent Current vs.
Supply Voltage (AD848 and AD849)

15V SUl'PLIES

\

V V

"'-

'M

SUPPLY VOLTAGE - :t:Volts

V
V

...='''''

'OOM

'OM
INPUTFREQUENCV - Hz

Figure 5. Large Signal Frequency
Response (AD848 and AD849)

95

.1 I I

'00

I

v~= ±~v

V

V ....-

,I

a~

V

9
z

,;

,
70

..

,

65

'0

100

1k

LOAD f\ESISTANCE -

n

I

/V

V.==1IV

'I!

95

I'

..

I

V

•
•

.

100
1k
LOAD RESISTANCE - n

'0

'Ok

5

V

/

V

I

I

/

/
3
- 60

- 40

I\, '\.
20

40

"

&0
80
100
SEnLlNG TIME - ns

120

140

160

Figure 9. Output SWing and
Error vs. Settling Time (AD848)

V

"1\

1\
'\

~

Vs=~5V

"- "-..,

3

[\.

0

5
20

\ \

\

vs=r sv

V

0.1%

5

/V

o.

""
\ \

-,. o

Figure 8. Open Loop Gain vs.
Load Resistance (AD849)

/'

I
i

D.'".

-8

75

/

V

'"

0

/

/

I

Va= :t5V

35

/

/

•

V

90

Figure 7.. Open Loop (;ain vs.
Load Resistance (AD848)

C6
E

'Ok

Figure 6. Output Voltage Swing vs.
Load Resistance (AD848 and AD849)

Va= :t15V

I

I

100
1k
LOAD RESISTANCE _ n

'0

0

'06

90

b::: ~V

o

:tIVSUPPUES

0
20
40
60 80
TEMPERATURE - "C

100 120 140

Figure 10. Quiescent Current vs.
Temperature (AD848 and AD849)

2-150 OPERATIONAL AMPLIFIERS

H

-~

H
0
H
~
H
"
AMBIENT TEMPERATURE _

or:

~

!'-..... t--

~

Figure 11. Short Circuit Current
Limit vs. Temperature (AD848
and AD849)

~

r-

2
60

40

20

20

40

60

80

100 120 140

TEMPERATURE _·C

Figure 12. Input Bias Current vs.
Temperature (AD848 and AD849)

REV. A

AD848/AD849
'00

~'-:l--1
~ :t15VSUPPLIES~

.

~D

'2.

+100·

.-- +10"

. . . +---,

'00

'"

"VSUPPUES~

,

\

500flLOAD

\

~ r-..

+

\

80

~~UE~

~

~ so

~'\

\

lk

10k

tOOk

1M

10M

\

+

\

~

I

V s =;t;15V

~

'"f:'-\

~ •.'5r--+-+--+-+--+-+--+-1--+-+

I

•

100

100M

l!

\

2.

-2.100

lk

'011

lOOk

1M

10M

II!
0.9_':.,,".-7.
..:-_-:t2.:-.,..-:!:2.:--:..
!::--.:!:.:--:.!::."""""'.!::."""""12!::.-,J'••

100M

TEMPERATURE _ '"C

FREQUENCY_Hz

FREQUENCY _ Hr

Figure 13. Open Loop Gain and
Phase Margin vs. Frequency (AD848)

Figure 14. Open Loop Gain and
Phase Margin vs. Frequency (AD849)

-10

-90

-

L51-+-f--+-+-+-I-+-1'-+-1

\

lkOLOAD

I..

\

l~

+...

~ .,.VSUPPUES

\
\

+'00"

~"M~

.

Figure 15. Normalized Gain Bandwidth Product vs. Temperature
(AD848 and AD849)

.5.
3VRMS
Rl =lkn

1\='''''

•••
•

-95

v

35

~

,

I
2ND HARMONIC

•

-11 5

-'20'00

'OOk

Figure 16. Harmonic Distortion vs.
Frequency (AD848)

'00

. ~ "'-

'Ok

~

'M

'OOk
FREQUENCY-Hz

100M

Figure 19. Power Supply Rejection
vs. Frequency (AD848)

REV. A

'00'

'0'

Figure 17. Harmonic Distortion vs.
Frequency (AD849)

'00

,/

20
40
60
TEMPERATURE _ "C

80

100 120 140

~D849

~~

~UPPLY
80

~

'"~"-

40

,.

,./

Figure 18. Slew Rate vs. Temperature
(AD848 and AD849)

'0. ~

2.

V

k.....-

V

'50
-60 -40 -20

'20

I

/

2••

'2.

eo

'"

10M

~250

'rHjjty)
J%DHfR""(""1'

FREQUENCY - Hz

-SUPPl~

~~

•,.

,.

I·i '"

~ t'-,.

+ SUPPlY

-.UPP~

..

•,

-'2

FREQUENCY - Hz

V

~

0

1 LV

ri"M
,.
,..

~

~I

VI

.lJ..

-11 5

w300

10k

100'

1M

A~ 0-.

so

~

10M

Vs= :!:15V

VCM =;tlVp-p

'"

••
20

100M

FREQUENCY _ Hz

Figure 20. Power Supply Rejection
vs. Frequency (AD849)

,.

10k

'00'

,M

10M

'OOM

FREQUENCY - Hz

Figure 21. Common-Mode
Rejection vs. Frequency

OPERATIONAL AMPLIFIERS 2-151

•

AD848/AD849 - Applications
GROUNDING AND BYPASSING
In designing practical circuits with the AD848 or AD849, the
user must remember that whenever high frequencies are
involved, some special precautions are in order. Circuits must be
built with short interconnect leads. A large ground plane should
be used whenever possible to provide a low resistance, low inductance circuit path, as well as minimizing the effects of high
frequency coupling. Sockets should be avoided because the increased interlead capacitance can degrade bandwidth.
Feedback resistors should be of low enough value to assure that
the time constant formed with the capacitances at the amplifier
summing junction will not limit the amplifier performance. Resistor values of less than Skfl are recommended. If a larger resistor must be used, a small « IOpF) feedback capacitor in
parallel with the feedback resistor, R F , may be used to compensate for the input capacitances and optimize the dynamic performance of the amplifier.

~

~v

,;1,1

-II
II

"II

100pf
LOAD

,-j

.oi l

l~

•

" 11

1000pF
LOAD

Figure 23. AD848 Driving a Capacitive Load

Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. O.lfLF ceramic disc capacitors are
recommended.

Often termination is not used, either because signal integrity
requirements are low or because too many high frequency signals returned to ground contaminate the ground plane. Unterminated cables appear as capacitive loads. Since the AD848 and
AD849 are stable into any capacitive load, the op amp will not
oscillate if the cable is not terminated; however pulse integrity
will be degraded. Figure 23 shows the AD848 driving both
lOOpF and IOOOpF loads.

VIDEO LINE DRIVER
The AD848 functions very well as a low cost, high speed line
driver of either terminated or unterminated cables. Figure 22
shows the AD848 driving a doubly terminated cable.

LOW NOISE PRE-AMP
The input voltage noise spectral densities of the AD848 and the
AD849 are shown in Figure 24. The low wide band noise and
high gain bandwidths of these devices makes them well suited as
pre-amps for high frequency systems.

The termination resistor, RT , (when equal to the characteristic
impedance of the cable) minimizes reflections from the far end
of the cable. While operating off ±SV supplies, the AD848
maintains a typical slew rate of 200V/fLS, which means it can
drive a ±lV, 24MHz signal on the terminated cable.
A back-termination resistor eRsT> also equal to the characteristic
impedance of the cable) may be placed between the AD848 output and the cable in order to damp any reflected signals caused
by a mismatch between RT and the cable's characteristic impedance. This will result in a "cleaner" signal, although it requires
that the op amp supply ±2V to the output in order to achieve a
± 1V swing at the line.
R,

R,

25

0
0\
5

~

0
10

+Vs

'"

100

AD848

AD849
1k

10k
100k
FREQUENCY - Hz

1M

10M

Figure 24. Input Voltage Noise Spectral Density

Input voltage noise will be the dominant source of noise at the
output in most applications. Other noise sources can be minimized by keeping resistor values as small as possible.

Figure 22. Video Line Driver

2-152 OPERATIONAL AMPLIFIERS

REV. A

Ultrahigh Frequency
Operational Amplifier
AD5539 I

11IIIIIIII ANALOG
WDEVICES
FEATURES
Improved Replacement for Signetics SE/NE5539
AC PERFORMANCE
Gain Bandwidth Product: 1.4 GHz typ
Unity Gain Bandwidth: 220 MHz typ
High Slew Rate: 600 V/lJ.s typ
Full Power Response: 82 MHz typ
Open-Loop Gain: 47 dB min. 52 dB typ

CONNECTION DIAGRAM
Plastic DIP (N) Package
or Cerdip (Q) Package

NC
FREQUENCY
COMPENSATION

DC PERFORMANCE
All Guaranteed DC Specifications Are 100% Tested
For Each Device Over Its Full Temperature
Range - For All Grades and Packages
Vos: 5 mV max Over Full Temperature Range
(AD5539J)
Ie: 20 IJ.A max (AD5539J)
CMRR: 70 dB min. 85 dB typ
PSRR: 100 IJ.V/v typ
MIL-STD-883B Parts Available

PRODUCT DESCRIPTION
The AD5539 is an ultrahigh frequency operational amplifier designed specifically for use in video circuits and RF amplifiers.
Requiring no external compensation for gains greater than 5, it
may be operated at lower gains with the addition of external
compensation.
As a superior replacement for the Signetics NE/SE5539, each
AD5539 is 100% dc tested to meet all of its guaranteed dc specifications over the full temperature range of the device.

INVERTING
INPUT

NONINVERTING
INPUT

NC

v+

TOP VIEW

PRODUCT HIGHLIGHTS
1. All guaranteed dc specifications are 100% tested.
2. The AD5539 drives 50 nand 75 n loads directly.
3. Input voltage noise is less than 4 nVy'Hz.
4. Low cost RF and video speed performance.
5. ±2 volt output range into alSO n load.
6. Low cost.
7. Chips available.

The high slew rate and wide bandwidth of the AD5539 provide
low cost solutions to many otherwise complex and expensive
high frequency circuit design problems.
The AD5539 is available specified to operate over either the
commercial (AD5539JN/JQ) or military (AD5539SQ) temperature range. The commercial grade is available either in 14-pin
plastic or cerdip packages. The military version is supplied in
the cerdip package. Chip versions are also available.

REV. A

OPERATIONAL AMPLIFIERS 2-153

•

AD5539 -SPECIFICATIONS
Parameter

Min

INPUT OFFSET VOLTAGE
Illitial Offset l
Tmill to T""",
INPUT OFFSET CURRENT
Illitial Offser
T mill to T max
INPUT BIAS CURRENT
Initialz
VCM =0
Either Input
T mill to T max
FREQUENCY RESPONSE
RL = 15003
SmaIl Signal Bandwidth
Act. = 24
Gain Bandwidth Product
Act. = 26 dB
Full Power Response
Act. = 24
Act. = 7
Act. = 20
Settling Time (1 %)
Slew Rate
Large Signal Propagation Delay
Total Harmonic Distortion
RL = 00
RL = 10003
VOUT = 2 Vp-p
Act. = 7, f = 1 kHz

(@

+25"1: anil Vs

ADS539J
Typ

= :t8 V dc, unless otherwisa.noted)

Max

Min

ADS539S
Typ

Max

UI!it8

2

5
6

2

3
5

mV
mV

0.1

2
5

0.1

1
3

!LA
!LA

6

20

6

13

!LA

25

!LA

40

220

220

MHz

1400

1400

MHz

68
82
65
12
600

68
82
65
12

4

600
4

MHz
MHz
MHz
ns
V/fJ.S
ns

0.010
0.016

0.010
0.016

%
%

INPUT IMPEDANCE

100

100

kG

OUTPUT IMPEDANCE (f <10 MHz)

2

2

0

250

250

mV

2.5

2.5

V

85

dB
dB

5

5

""V

4

4

nVv'Hz

INPUT VOLTAGE RANGE
Differential'
(Max Nondestructive)
Common-Mode Voltage
(Max Nondestructive)
Common-Mode Rejection Ratio
l1VCM = 1.7 V
Rs = 100 0
Tmill to T""",
INPUT VOLTAGE NOISE
Wideband RMS Noise (RTI)
BW = 5 MHz; Rs = 500
Spot Noise
F = 1 kHz; Rs = 50 0
OPEN-LOOP GAIN
Vo = +2.3 V, -1.7 V
RL = 15003
R L =2kO
Tmill to T .... -RL = 2 kO

2-154 OPERATIONAL AMPLIFIERS

70
60

47
47
43

85

52

70
60

58
58
63

47
48
46

52

58

57
60

dB
dB
dB

REV. A

AD5539
ADSS39S

ADSS39J
Parameter
OUTPUT CHARACTERISTICS
Positive Output Swing
RL = 15003
R L =2kO
T min to Tmax with
RL = 2kO
Negative Output Swing
RL = 15003
RL = 2kO
T min to T max with
RL = 2 kO

Min

Typ

+2.3
+2.3

+2.8
+3.3

+2.3

Typ

+2.3
+2.5

+2.8
+3.3

Max

-1.7
-1.7

-2.2
-2.9

±8

V
V

14

11

100

-1.7
-2.0

V
V

-1.5

V

,dO

V
V

17
18
14
IS

rnA
rnA
rnA
rnA

1000
2000

...VN
...VN

±8
:tl0

Units

V

-1.5

PSRR
Initial
Tmin to Tmax

PACKAGE OPTIONS6
Plastic (N-14)
Cerdip (Q-14)
J and S Grade Chips Available

Min

+2.3
-2.2
-2.9

POWER SUPPLY (No Load, No Resistor to -Vs)
Rated Perfonnance
Operating Range
:t4.S
Quiescent Current
Initial 1=+
Tmin to Tmax
Initial 1=Tmin to Tmax

TEMPERATURE RANGE
Operating,
Rated Perfonnance
Commercial (0 to + 70°C)
Military (-55°C to + 125°C)

Max

±4.S

18
20
IS
17

14

1000
2000

100

11

AD5539JN, AD5539JQ
AD5539SQ
AD5539JN
AD5539JQ

AD5539SQ, AD5539SQ/883B

NOTES
'Input Offset Voltage specifications are guaranteed after 5 minutes of operation at TA = +25"C.
2Bias Current specifications are guaranteed maximum at either input after 5 minutes of operation at Tit. = + 25OC.
'Rx = 470 to -Vs.
'Externally compensated.
'Defined as voltage between inputs, such that neither exceeds +2.5 V, -5.0 V from ground.
6Por outline information see Package Information section.
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality
levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

n

REV. A

OPERATIONAL AMPLIFIERS 2-155

•

AD5539
ABSOLUTE MAXIMUM RATINGS l
Supply Voltage . . . . . .
· . . . . ±IOV
Internal Power Dissipation
· . . . 550mW
Input Voltage . . . . . . .
+2.5V, -5.0V
Differential Input Voltage .
· . . . . O.25V
-65°e to + l500 e
Storage Temperature Range Q
Storage Temperature Range N
-65°e to + l250C
Operating Temperature Range
AD5539JN
. .. 0 to + 70 e
AD5539JQ . . . . . . . .
. .. 0 to + 700 e
ADS539SQ . . . . . . . .
- 55°e to + 125°e
Lead Temperature Range (Soldering 60 seconds) . . .. 300 e

OFFSET NULL CONFIGURATION

0

VON

OR GROUND

0

NOTES
IStresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those

OUTPUT NULL RANGE

~

".

+ V. (-RR, ) TD - V. (-RR, )
NUU

NUU

OFFSET NULL CONFIGURATION

indicated in the operational section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may· affect
device reliability.

2-156 OPERA TIONAt AMPLIFIERS

REV. A

Typical Characteristics - AD5539
'.0 ,---,---,---""T"---.--......,.

3.5

J3.5~-~r---+--~-~~~-~

3.0

~

", 3.o1---t---t--,rY'--t----1

I
~

2.5

f----t-----c6~--t---_=~=.-~

~

5.0
~ .. I-

,
:

~

I

i

g

;

,
!i!ii2.0

I

..

r:

1:...-"'":l..-"""f---t---t----1

~

1.0 ~5---L---7~--~--~--.J,0·

~

o
10

SUPPLY VOLTAGE -:!: Votts

R =390J!
X

Rx =410n

Rt =100:1 _ _ _
Rl'",,15011

",35
E

,

~

/

G

/,./

~30

~ 25

~

V,.
,.

V,.'

Rt =150U

>3.0

20

R1 =15011. R.=47011--

IE

i

i

1.0

;:c

I

~

i

I

~

100
1k
LOAD RESISTANCE - Ohms

10f---:1t--+--+-

o

10k

I
7
•
SUPPLY VOLTAGE -

5

~

10

Volts

Figure 3. Maximum CommonMode Voltage vs. Supply Voltage

"

Vs == :!:8V
Rx ::: 4701!
Rt ::: 1S0U

~'

~

, 10

~

I

\

~
;;::

-5f---+--+--+-~~~

>

~

V' ,.

~/

+VCM

/

S

I

-

i---

AI =lDOS!. R,,=390n--

15r--~-,---r-_.--,--r--,

/ ,.

i

220

I

--

Rx =470U

Figure 2. Output Voltage Swing
vs. Load Resistance

Figure 1. Output Voltage Swing
vs. Supply Voltage

..

i

.I ~I

0.5

V
~
!
!i -- V-:: -- ---

I

...

~ 1.0

~I 4.0

"

vou,

+1 2 .5

:! 1.5

g

, -- 1-

~,

~

~

:;:10

-10f---+--+--+--4-r-~-~-~

"iii

if

6

"

•

I

......

I
!

3:

-15 f---+--+--+---I

9

2

./

15

7

5

-2~~3--_~2~-_~1~-70-~,-r-~-7--~

10

•

o

OUTPUT VOLTAGE - Vohs

SUPPLY VOLTAGE -:!: Volts

Figure 4. Positive Supply Current
vs. Supply Voltage

10

1

100

1k

10k

FREQUENCY - Hz

Figure 6. Low Frequency Input
Noise vs. Frequency

Figure 5. Input Voltage vs. Output
Voltage for Various Temperatures

80

I 2.lll

~

"

.

Hi~N'C

-10

.

~ -20

": -20

~

r-...
r-....r-.,

r -~

30

./

.1 =1J.l1

VOUT
2V p.p
Rx == 470n
Rl =15011
Vs == ~8V
GAIN = 26dB
(FIGURE 331

-10

u-40

i

~D

VOUT = 2V p.p
Rx = 470n
Rt = 150U

~I~:':
IFIGURE 171

~-50

IJ

HARMONIC

1-30

i
!-50
Co)

2·D

HARMONIC

-40

i--" ~r-

Z

~

:t:

roD

HARMONIC
-60

-60

1M
10M
FREQUENCY - Hz

Figure 7. Common-Mode
Rejection Ratio vs. Frequency

REV. A

100M

-70
1001<

1M

10M
FREQUENCY - Hz

180M

Figure 8. Harmonic Distortion
vs. Frequency - Low Gain

1G

-70

100k

1M

10M

100M

II

1G

FREQUENCY - Hz

Figure 9. Harmonic Distortion
vs. Frequency - High Gain

OPERATIONAL AMPLIFIERS 2-157

•

AD5539
+'0

-2.• r - - - - , - - - , . , - - . . , . - - - . - - - ,

r-'-"""""TT'""""T'""""T'""1"T'I--,--,-n..,.-..,.--.-r-n

'I
~

~

, -2.0

0~+-++~~~+H~~~+-+-+4-H
GAIN

=

~

+2

S-·~~~~-++H-+~~~~-bbH

o

fi1

RL =2kU

~

-'.S

9

GAIN = +7

Vcc=':!:8V

~-'0~~++~~~~~~-H+-+-+4~

~
~ -15 ~~++~--t-~~---l---l-H+-+-++~
I,

~

IE -'.0 I-_-I__+~L+-_-+

is

!i
~

Q

-O.• I---I~~+_--

Evaluating the lead capacitance first (ignoring R LAG and C LAG
for ,now): the feedback network, consisting of R2 and CLEAD '
has a pole frequency equal to:

so

..

\.

9 2.

~

Figure IS illustrates the use of both lead and lag compensation
to permit stable low-gain operation. The AD5539 is shown connected as an inverting amplifier with the required external components added to provide stability and improve high frequency
response. The stray capacitance between the amplifier summing
junction and ground, Cx, represents whatever capacitance is associated with the particular type of op amp package used plus
the stray wiring capacitance at the summing junction.

FA

r ... .....

50

Z

ADss39 when operating at a noise gain of 7. Under these conditions, excess phase shift causes nearly 10 dB of peaking at
ISO MHz.

PHASE _ _ _ _

,

2••

l\\1'

Usually, frequency FA is made equal to F B; that is, (RICx ) =
(R2 C LEAD ), in a manner similar to the compensation used
for an attenuator or scope probe. However, if the pole frequency, FA> will lie above the unity gain crossover frequency
(440 MHz), then the optimum location of FB will be near the

2••

-1.

280

1M

10M

100M

1G

FREQUENCY - Hz

R2

+Vs

Figure 13. Small Signal Open-Loop Gain and
Phase vs. Frequency

1nF

,:a

GENERAL PRINCIPLES OF LEAD AND LAG
COMPENSATION
The AD5539 has its first pole or breakpoint in its open-loop
frequency response at about 10 MHz (see Figure 13). At frequencies beyond 100 MHz, phase shift increases such that the
output lags the input by 1800 - well before the unity gain
crossover frequency. Therefore, severe peaking (and possible
oscillation) will result if the AD5539 is operated at noise gains
below 5, unless external compensation is employed. Figure 14
shows the uncompensated closed-loop frequency response of the

V OUT

'NOISE GAIN' =
+1.

r

~

0

~
GAIN

C

~

PHASE

-

---

~

o
z

120

~

~

o

.

\ I ,

:J -10

Figure 15. Inverting Amplifier Model Showing Both Lead
and Lag Compensation

i
~

1\

180 I

~\

2.J

\

v,.

3••

\
10M
100M
FREQUENCY - Hz

360
1G

Figure 14. AD5539 Uncompensated Response, ClosedLoop Gain = 7

REV. A

V OUT O-.....J\II/'v-.........- . . _ - -....-O

R1

-20

1M

1

-VS

1\

w

~+

Figure 16. A Model of the Feedback Network of the
Inverting Amplifier
OPERATIONAL AMPLIFIERS 2-159

•

AD5539
crossover frequency. Both of these circuit techniques add a large
amount of leading phase shift at the crossover frequency, greatly
aiding stability.

+2

+1

h

The lag network (RLAG, CLAG) increases the feedback attenuation, i.e., the am:plifier operates at a higher noise gain, above
some frequency, typically one-tenth of the crossover frequency.
As an example, to achieve a noise gain of 5 at frequencies above
44 MHz, for the circuit of Figure IS, would require a network
of:

Rl
(4RIIR2) -1

RUG

......
-1

-2

-3

(3)
-4

and ...

-"

(4)

It is worth noting that an R LAG resistor may be used alone, to
increase the noise gain above 5 at all frequencies. However, this
approach has the disadvantage of also increasing the dc offset
and low frequency noise errors by an amount equal to the increase in gain, in this case, by a factor of 5.

SOME PRACTICAL CIRCUITS
The preceding general principles may now be applied to some
actual circuits.
A General Purpose Inverter Circuit
Figure 17 is a general purpose inverter circuit operating at a
gain of -2.
For this circuit, the total capacitance at the inverting input is
approximately 3 pF; therefore, CLEAO from Equations 1 and 2
needs to be approximately 1.5 pF. As shown in Figure 17, a
small trimmer is used to optimize the frequency response of this
circuit. Without a lag compensation network, the noise gain of
the circuit is 3.0 and, as shown in Figure 18, the output amplitude remains within ±0.5 dB to 170 MHz and the -3 dB bandwidth is 200 MHz.

1M

100k

10M

1G

100M

FREQUENCY - Hz

Figure 18. Response of the (Figure 17) Inverter Circuit
without a Lag Compensation Network
A lag network (Figure 15) can be added to improve the response
of this circuit even further as shown in Figures 19 and 20. In
almost all cases, it is imperative to make capacitor C LEAO adjustable; in some cases, CLAG must also be variable. Otherwise,
component and circuit capacitance variations will dominate circuit performance.
+2

!8

,

~
I

-1

o

-2

~

,~

R LAG

+1

~

'"

1',

-3

-4

-"

CLEAD 0.1 - 2.SpF TRIMMER

11

33011
RtAG

~
~

IV'

i.--'
~

tOOk

1M

10M

lG

100M

FREQUENCY - Hz

2k

Figure 19. Response of the (Figure 17) Inverter Circuit
with an RLAG Compensation Network Employed

+BV

+2

!II

,

U

+1

3.5pF

~

son
lOR 7511)

;
~

o

33011
+lOpF

1

t\1t

-2

;!
~ -3

..j

-4

-BV

Figure 17. A General Purpose Inverter Circuit

"

lOOk

1M

10M

100M

lG

FREQUENCY - Hz

Figure 20. Response of the (Figure 17) Inverter Circuit
with an RLAG and a CLAG Compensation Network
Employed
2-160 OPERATIONAL AMPLIFIERS

REV. A

AD5539
Figures 21 and 22 show the small and large signal pulse responses of the general purpose inverter circuit of Figure 17,
with C LEAD =1.5 pF, R LAG =330 n and C LAG =3.5 pF.

R2

2k

+8V

•
-BV

Figure 21. Small Signal Pulse Response of the (Figure 17)
Inverter Circuit; Vertical Scale: 50 mV/div; Horizontal
Scale: 5 ns/div

Figure 23. A Gain of 2 Inverter Circuit with the CLEAD Capacitor Connected to Pin 12
+2.

rg

,

+10

~

"
oct

-10

o

-20

~

~

TO OUTPUT
u o
C ...

I'

~

CLEAD
PIN12

Ui -30

"',

,,

i

'" -40

-5.10Uk
Figure 22. Large Signai Response of the (Figure 17) Inverter Circuit; Vertical Scale: 200 mV/div, Horizontal
Scale: 5 ns/div
A CLEAD capacitor may be used to limit the circuit bandwidth
and to achieve a single pole response free of overshoot

(-3

dB frequency

1)

211' R2 GLEAD

If this option is selected, it is recommended that a C LEAD be
connected between Pin 12 and the summing junction, as shown
in Figure 23. Pin 12 provides a separately buffered version of
the output signal. Connecting the lead capacitor here avoids the
excess output-stage phase shift and subsequent oscillation problems (at approx. 350 MHz) which would otherwise occur when
using the circuit of Figure 17 with a CLEAD of more than about
2 pF.
Figure 24 shows the response of the circuit of Figure 23 for
each connection of C LEAD • Lag components may also be added
to this circuit to further tailor its response, but, in this case, the
results will be slightly less satisfactory than connecting C LEAD
directly to the output, as was done in Figure 17.

REV. A

I"f

1M

10M
FREQUENCY - Hz

100M

,G

Figure 24. Response of the Circuit of Figure 23 with
CLEAD = 10pF

A General Purpose Voltage Follower Circuit
Noninverting (voltage follower) circuits pose an additional complication, in that when a lag network is used, the source impedance will affect the noise gain. In addition, the slightly greater
bandwidth of the noninverting configuration makes any excess
phase shift due to the output stage more of a problem.
For example, a gain of 3 noninverting circuit with CLEAD connected normally (across the feedback resistor - Figure 25) will
require a source resistance of 200 n or greater to prevent UHF
oscillation; the extra source resistance provides some damping as
well as increasing the noise gain. The frequency response plot of
Figure 26· shows that the highest - 3 dB frequency of all the
applications circuits can be achieved using this connection, unfortunately, at the expense of a noise gain of 14.2.

OPERATIONAL AMPLIFIERS 2-161

AD5539
+2

-1

R2

I

+8V

2.

-1

-2

-3

VIN~

-4

150n

-,

lOOk

1M

10M
FREQUENCY - Hz

100M

1G

Figure 28. Response of the Gain of 3 Follower with CLEADCLAG and RLAG
-8V

Figure 25. A Gain of 3 Follower with Both Lead and Lag
Compensation
+2

R2

~

~ I-

These same principles may be applied when capacitor CLEAD is
connected to Pin 12 (Figure 29). Figure 30 shows the bandwidth
of the gain of 3 amplifier for various values of RLAG • It can be
seen from these response plots that a high noise gain is still
needed to achieve a reasonably flat response (the smaller the

2'

+SV

-,

lOOk

1M

10M
FREQUENCY - Hz

100M

1G

Figure 26. Response of the Gain of 3 Follower Circuit

Adding a lag capacitor (Figure 27) will greatly reduce the midband and low frequency noise gain of the circuit while sacrificing only a small amount of bandwidth as shown in Figure 28.

R2

2.

Figure 29. A Gain of 3 Follower Circuit with CLEAD
Compensation Connected to Pin 12

+sv
lnF

VIN~

.

I

iI

-25,OLk-l.-l.....LJ,LlM.,.--J-LL"-,O"-M--'----l...LJ1O-'-O-M-'--.....L.llJ,G

-SV

Figure 27. A Gain of 3 Follower Circuit with Both CLEAD
and RLAG Compensation
2-162 OPERATIONAL AMPLIFIERS

FREQUENCY - Hz

Figure 30. Response of the Gain of 3 Follower Circuit with
CLEAD Connected to Pin 12

REV. A

AD5539
value of R LAG , the higher the noise gain). For example, with a
220 n RLAG and a SO n source resistance, the noise gain will be
12.8, because the source resistance affects the noise gain.

0.1 - 2.5pF

TRIMMER
Uk

Figures 31 and 32 show the small and large signal responses of
the circuit of Figure 29.

+BV

+BV
OFFSET
A~. ~~~~-4-'-{
20k

7511

-sv

-BV

Figure 33. A 20 dB Gain Video Amplifier for 75 [J Systems
Figure 31. The sma/l-signal Pulse Response of the Gain
of 3 Fo/lower Circuit with RLAG and CLEAD Compensation
to Pin 12; Vertical Scale: 50 mV/div; Horizontal Scale:
5 ns/div

_5L-L-LLLL-L-LLll~~~L-L-LLU

lOOk

1M

10M

100M

1G

FREQUENCY - Kz

Figure 34. Response of the 20 dB Video Amplifier
Figure 32. The Large-Signal Pulse Response of the Gain
of 3 Fo/lower Circuit with RLAG and CLEAD Compensation
to Pin 12; Vertical Scale: 200 mV/div; Horizontal Scale:
5ns/div

In color video applications, the quality of differential gain and
differential phase response is very important. Figures 35 and 36
show a circuit and test setup to measure the ADss39's response
to a modulated ramp signal (0-90 IRE p-p ramp, 40 IRE p-p
modulation, 4.4 MHz).

A Video Amplifier Circuit with 20 dB Gain (Terminated)
.High gain applications (14 dB and up) require only a small lead
capacitance to obtain flat response. The 26 dB (20 dB terminated) video amplifier circuit of Figure 33 has the response
shown in Figure 34 using only approximately 0.5-1 pF lead
capacitance. Again, a small CLEAD can be connected, either to
the output or to Pin 12 with very little difference in response.

Figures 37 and 38 show the differential gain and phase response.

REV. A

OPERATIONAL AMPLIFIERS 2-163

AD5539
0.15

10~ IRE = 714~V

O.1-2.5pF
TRIMMER
•. 1

1kll

+8V

i

1nF

l,

0.05

I
49.9U

~~

~

Vo

~149'91l
-=

LOAD

""... V--

~

~ -0".05

i
-0.1

-0.15

•

36

18

54

72

90

RAMP AMPLITUDE - IRE

Figure 38. Differential Phase vs. Ramp Amplitude

··8V

Figure 35. Differential Gain and Phase Measurement
Circuit

RAMP

WAVEFORM

Figure 36. Differential Gain and Phase Test Setup

....
..,

TO
TEKTRONICS
7B5417A24 ~
OSCILLOSCOPE
PREAMP
'::"

430n

430n

10~ IRE = 71~mv

•.04

-

Z

~

MEASURING AD5539 SETTLING TIME
Measuring the very rapid settling times associated with AD5539
can be a real problem for the designer; proper component layout
must be used and appropriate test equipment selected. In addition, both cable dispersion (a function of cable losses) and the
quality of termination (SWR) directly affect the measurement.
The circuit of Figure 39 was used to make a "brute force"
AD5539 settling time measurement. The fixture containing the
circuit was connected directly - using a male BNC connector
(but no cable) - onto the. front of a 50 n input oscilloscope
preamp. A digital mainframe was then used to capture, average,
and expand the error signal. Most of the small-scale waveform
aberrations shown on the figure were caused by the oscilloscope
itself, especially the glitch at 15 ns. The pulse source used for
this measurement was an EH-SPG2000 pulse generator set for a
1 ns rise-time; it was coupled directly to the circuit using 18" of
microwave 50 n hard line.

0.02

~ •~
m

V

i"'v

Q

-0,02

-0.0 4
18

3.

54

n

9.

son

~

51,n

son

V OUT

~

EH SPG2000
PULSE
GENERATOR

RAMP AMPLITUDE - IRE

-BV

Figure 37. Differential Gain vs. Ramp Amplitude
Figure 39. AD5539 Settling Time Test Circuit

2-'-164 OPERATIONAL AMPLIFIERS

REV. A

AD5539
APPLICATIONS SUMMARY CHART

Gain = -I to -5
Circuit of Fig. 17

Rl

R2'

R2

2k

-

Gain = -I to -5
Circuit of Fig. 23

R2

2k

Gain = -2 to
Circuit of Fig. 27

GAIN
FLATNESS
(TRIMMED)

3 pF

-2

±0.2 dB

200 MHz

3 pF

-2

±I dB

180 MHz

3 pF

+3

±I dB

390 MHz

+3

±0.5 dB

340 MHz

±0.2 dB

80 MHz

±0.2 dB

80 MHz

2

;;; 2

7r

1
(44 x 1(j6) R LAG

=G

Rl
RI
4 R2 - 1

;;; 2

7r

(44

X

1
106) R LAG

=G

Rl
RI
10 R2 - 1

;;; 2

7r

(44

X

1
106) R LAG

= G-l

~---

G

GAIN

CLEAn

RI
RI
4 R2 - 1

~---

G

CLAG2

RLAG

3dB
BANDWIDTH

+5 3

Gain = +2 to +5'
Circuit of Fig. 29

R2

G-l

2k
~

R2
--

2k

R2

1.5 k

NA

NA

Trimmer'

1.5k

NA

NA

Trimmer'

~

G-l

Gain

< -5

NA

RI
RI
IOR2-1

3 pF

= G-I
-20

G
Gain >+5

R

G-I

+20

NOTES
G=Gain NA=Not Applicable
'Yalues given for specific results summarized here-applications can be adapted for values different than those specified.
2It is recommended that C LEAD and CLAG be trimmers covering a range that includes the computed value above.
3RsoURCE

;;:=:200

4RsoURCE

~50

n.

n.

'Use Yoltronics CPA2 0.1-2.5 pF Teflon Trimmer Capacitor (or equivalent).

The photos of Figures 40 and 41 demonstrate how the ADSS39
easily settles to 1% (l m V) in less than 12 ns; settling to 0.1%
(100 jI.V) requires less than 25 ns.

UZR 1.2

-

_--1 _1_ ::I

I

soo",ul

- -

I

+- -

~I'IS
-I -

:

1
j

t

-

I

--;:- -

t

-

-

I
--'-I~-

Figure 40. Error Signal from AD5539 Settling Time Test
Circuit - Falling Edge. Vertical Scale: 5 ns/div.; Horizontal
Scale: 500 poV/div

REV. A

--+

+-t--'--

Figure 41. Error Signal from AD5539 Settling Time Test
Circuit - Rising Edge. Vertical Scale: 5 ns/div.; Horizontal
Scale: 500 poV/div

OPERATIONAL AMPLIFIERS 2-165

•

AD5539

f

Figure 42 shows the oscilloscope response of the generator alone,
set up to simulate the ideal test circuit error signal (Figure 43).

.n..

H INDUSTRIES
SPG2000 PULSE GENERATOR OUTPUT

--r-IV

,

S4nV

-

-

DHCPD - 24.e)nS
CRS1)

o OF 1

Figure 42. The Oscilloscope Response Alone Directly
Driven by the Test Generator. Vertical Scale: 5 ns/div.:
Horizontal Scale: 500 ILV/div

Figure 43. A Simulated Ideal Test Circuit Error Signal

A 50 MHz VOLTAGE-CONTROLLED AMPLIFffiR
Figure 44 is a circuit for a 50 MHz voltage-controlled amplifier
(VeA) suitable for use in high quality video-speed applications.
This circuit uses the AD5539 as an output amplifier for the
ADS39, a high bandwidth multiplier. The outputs from the two
signal channels of the AD539 are applied to the op amp in a
subtracting configuration. This connection has two main advantages: first, it results in better rejection of the control voltage,
particularly when over-driven (Vx3.3 V). Secondly,
it provides a choice of either noninverting or inverting responses, using either input VYl or VY20 respectively. In this circuit, the output of the op amp will equal:

Hence, the gain is unity at Vx = +2 V. Since Vx can overrange to +3.3 V, the maximum gain in this configuration is
about 4.3 dB. (Note: If Pin 9 of the AD539 is grounded, rather
than connected to the output of the 5539N, the maximum gain
becomes 10 dB.)

VOUT Vx (Vy! - Vnl fi V >0
2V
or x
+9V
2.7U

The bandwidth of this circuit is over 50 MHz at full gain, and is
not substantially affected at lower gains. Of course, when Vx is
zero (or slightly negative, to override the residual input offset)
there is still a small amount of capacitive feedthrough at high
frequencies; therefore, extreme care is needed in laying out the
PC board to minimize this effect. Also, for small values of Vx ,
the combination of this feedthrough with the multiplier output
can cause a dip in the response where they are out of phase.
Figure 45 shows the ac response from the noninverting input,
with the response from the inverting input, Vy2 , essentially
identical. Test conditions: VYl = 0.5 V rms for values of Vx
from +10 mV to +3.16 V; this is with a 75 n load on the output. The feedthrough at Vx = -10 mV is also shown.

1.

VI('" +3.1B2V

~
V =+1V

-10

.,.
! -20

" l".

v x = +O.316V

~

f\ 1'-

VI('" +O.lV

1-30
II!

~

I"

VI("" +O.032V

-40
Vx "'+O.OlV

-50
VJ-O,01V
01: THOMPSON.CSF BAR·tO ORSIMILARSCHQTTKY DIODE

'¢

Z.7U

SHORT.~CONNEcnONTOGROUNDPLANE.

L'I.

-6D
1

/

~

~~
1.

~

1DO

fREQUENCY - MHz

-9V

Figure 44. A Wide Bandwidth Voltage-Controlled Amplifier

2-166 OPERATIONAL AMPLIFIERS

Figure 45. AC Response of the VCA at Different Gains
Vy = 0.5VRMS

REV. A

AD5539
The transient response of the signal channel at Vx = + 2 v,
Vy = VOUT = + or -I V is shown in Figure 46; with the VCA
driving a 75 n load. The rise and fall times are both approximately 7 ns.
A few final circuit details: in general, the control amplifier compensation capacitor for Pin 2, Ce , must have a minimum value
of 3000 pF (3 nF) to provide both circuit stability and maximum control bandwidth. However, if the maximum control
bandwidth is not needed, then it is advisable to use a larger
value of Ceo with typical values between 0.01 and 0.1 ILF. Like
many aspects of design, the value of Ce will be a tradeoff:
higher values of Cc will lower the high frequency distortion,
reduce the high frequency crosstalk and improve the signal
channel phase response. Conversely, lower values of Cc will provide a higher control channel bandwidth at the expense of degraded linearity in the output response when amplitude
modulating a carrier signal.
The control channel bandwidth will vary in inverse proportion
to the value of Ceo providing a typical bandwidth of 2 MHz
with a Ce ofO.OlILF and a Vx voltage of +1.7 volts.
Both the bandwidth and pulse response of the control channel
can be further increased by using a feedforward capacitor, Clf,
with a value between 5 and 20 percent of Ce .
should be
carefully adjusted to give the best pulse response for a particular
step input applied to the control channel. Note that since Clf is
connected between a linear control input (Pin I) and a logarith-

err

lOll

Figure 46. Transient Response of the Voltage-Controlled
Amplifier Vx = +2 Volts, Vy = ±1 Volt
mic node, the settling time of the control channel with a pulse
input will vary with different control input step levels.
Diode D I clamps the logarithmic control node at Pin 2 of the
AD539, (preventing this point from going too negative); this
diode helps decrease the circuit recovery time when the control
input goes below ground potential.
THE AD539/5539 COMBINATION AS A FAST, LOW
FEEDTHROUGH, VIDEO SWITCH
Figure 47 shows how the AD539/5539 combination can be used
to create a fast video speed switch suitable for many high fre-

0.47"F

7511 J3

+9V

~75U
OUTPUT

+9V
2.7U
Rx
470U

SIGNAL

OPTIONAL
TERMINATION

J2 \

NON.
INVERTING
INPUT

~;-"'~""'~f---t

InF

+9V ~

7511

V

lOOk

I

-JI,I\I'vo1

lOll

50k

Vos

-9V

-9V

J4 7511

n

t----.-J~r_--~~CONTROL-l
DENOTES SHORT.
DIRECT CONNECTION
TO GROUND PLANE

887U

-9V

~ INPUT

L-

+ 1V (OFF)
0 (ON)

'VALUE WILL VARY SLIGHTLY
WITH COMPONENT LAYOUT

Figure 47. An Analog Multiplier Video Switch

REV. A

OPERATIONAL AMPLIFIERS 2-167

•

AD5539
quency applications incJudfug color key switching. It features
both inverting and noninverting inputs and can provide an output of ± 1 V into a reverse-terminated 75 n load (or ±2 V into
150 n). An optional output offset adjustment is provided. The
input range of the video switch is the same as the output range:
± 1 V at either input generates ± I V (noninverting) or.:;: 1 V
(inverting) across the 75 n load. The circuit provides a gain of
about 1, when "ON," .or zero when "OFF."

The differential-gain and differential-phase characteristics of this
compatible with video applications. The incremental
switch
gain changes less than 0.05 dB over a signal window of 0 to
+ 1 V, with a phase variation of less than a.5 degree at the subcarrier frequency of 3.58 MHz. The noise level of this circuit
measured at the 75 n load is typically 200 Il.V in a 0 to 5 MHz
bandwidth or approximately· 100 nV per root hertz. The noise
spectral density is essentially flat to 40 MHz.

The differential configuration useS both, channels of the ADS39
not only to provide alternative input phases, but also to eliminate the switching pedeStal due to steP changes in the output
current as the AD539 is gated· on or off.

The waveforms shown in Figures 48 and 49 were taken across a
75 n termination; in both photos, the signal of 0 to + 1 V (in
this case, an offset sine wave at 1 MHz) was applied to the noninverting input. In Figure 48, the envelope response shows the
output being fully switched in about 50 ns. Note that the output
is ON when the control input is zero (or more negative) and
OFF for a control input of + 1 V or more. There is very little
control-signBI breakthrough.

Figure 49 shows the response to a pulse of 0 to + I V on the
signal channel. With the control input held at zero, the rise time
is under IOns. The response from the inverting input is similar.

Figure 48. The Control Response of the Video Switcher

2-168 OPERATIONAL AMPLIFIERS

are

Figure 49. The Signal Response of the Video Switcher

REV. A

Low Noise Precision
Operational Amplifier
OP-27 I

~ANALOG

WDEVICES
FEATURES
• Low Noise .................... SOnVp _p (0.1 Hz to 10Hz)

....... ..... .................... .......... 3nV/J"HZ
• Low Drift .................................. 0.2p.V/oC
• High Speed . . . . . . . . . . . . . . . . . . . . . . .. 2.SV1p's Slew Rate
............................... SMHz Gain Bandwidth
• Low Vos ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10p.V
• Excellent CMRR ............... 126dB at VCM of ± 11V
• High Open-Loop Gain. . . . . . . . . . . . . . . . . . . .. 1.S Million
• Fits 725, OP-07, OP-05, AD510, AD517, 5534A sockets
• Available in Die Form

ORDERING INFORMATION t
PACKAGE
TA =+25°C
VosMAX
(~V)

25
25

60
60
100
100
100

It

To-99

CERDIP
8-PIN

OP27AJ+
OP27EJ
OP27BJ+
OP27FJ
OP27CJ
OP27GJ

OP27P;Z+
OP27EZ
OP27BZ+
OP27FZ
OP27CZ
OP27GZ

PLASTIC
8-PIN

OPERATING
LCC
TEMPERATURE
RANGE
20-CONTACT

OP27EP
OP27BRl883
OP27FP
OP27GP
OP27Gstt

Mil
IND/COM
Mil
IND/COM
Mil
XIND
XIND

For devices processed in total compliance to Mll-STD·883, add 1883 after part
number. Consult factory for 883 data sheet.
Burn-in is available on commercial and industrial temperature range parts in
CerDIP, plastic DIP, and TO·can packages.
For availability and burn·in information on SO and PlCC packages, contact
your local sales office.

GENERAL DESCRIPTION
The OP-27 precision operational amplifier combines the low
offset and drift of the OP-07 with 'both high-speed and lownoise. Offsets down to 25p.V and drift of 0.6p.Vio C maximum
make the OP-27 ideal for precision instrumentation applications. Exceptionally low noise, en = 3.5nV/y'"HZ, at 10Hz, a
low 1/f noise corner frequency of 2.7Hz, and high gain (1.8
million), allow accurate high-gain amplification of low-level

signals. A gain-bandwidth product of 8MHz and a 2.8V/p.sec
slew rate provides excellent dynam ic accu racy in high-speed
data-acquisition systems.
A low input bias current of ±10nA is achieved by use of a
bias-current-cancellation circuit. Over the military temperature range, this circuit typically holds Ie and los to ±20nA
and 15nA respectively.
The output stage has good load driving capability. Aguaranteed swing of ± 10V into 600n and low output distortion make
the OP-27 an excellent choice for professional audio applications.
PSRR and CMRR exceed 120dB. These characteristics.
coupled with long-term drift ofO.2p.Vimonth, allow the circuit
designer to achieve performance levels previously attained
only by discrete designs.

PIN CONNECTIONS

BALfitBAL'7V+
-IN2

6 OUT

+IN 3

5 N.C.
4V- (CASE)

TO-99
(J-Sufflx)

S-PIN HERMETIC DIP
(Z-Suffix)
EPOXY MINI-DIP
(P-Suffix)
S-PINSO
(S-Suffix)
OP-27BRC/SS3
LCCPACKAGE
(RC-Sufflx)

SIMPLIFIED SCHEMATIC

OUTPUT

NON·

INVERTING

INPUT f",+I-I--+~~f-"""""",=-~
INVERTING

INPUT "'H-4.....-

t----f----...J

.......

• R1. R2 ARE PERMANENTLY ADJUSTED
AT WAFER TEST FOR MINIMUM
OFFSET VOLTAGE.

REV. A

L-_ _ _ _ _ _~-....---~~_ _ _~__.......~~~v-

OPERATIONAL AMPLIFIERS 2-169

2

OP-27
Low cost, high-volume production of OP-27 is achieved by
using an on-chip zener-zap trimming network. This reliable
and stable offset trimming scheme has proved its effectiveness over many years of production history.

Operating Temperature Range
OP-27A, OP-27B, OP-27C (J, Z, RC) ........ -55·C to + 125·C
OP-27E, OP-27F (J, Z) .•••••.......................... -25°C to +85°C
OP-27E, OP-27F (P) •..••.....................•............. O°C to +70°C
OP-27G (P, S, J, Z) ...................................... -40°C to +85°C
Lead Temperature Range (Soldering, SO sec) .............. 300°C
Junction Temperature ................................... -65°C to + 150°C

The OP-27 provides excellent performance in low-noise
high-accuracy amplification of low-level signals. Applications include stable integrators, precision summing ampli~
fiers, precision voltage-threshold detectors, comparators,
and professional audio circuits such as tape-head and
microphone preamplifiers.

PACKAGE TYPE

e lA (Note 3)

T(),99 (J)

150
148
103

8-Pin Hermetic DIP (Z)

The OP-27 isa direct replacementfor725, OP-oS, OP-07 and
OP-05 amplifiers; 741 types may be directly replaced by
removing the 741's nulling potentiometer.

8-Pin Plastic DIP (P)
20-Contact LCC (RC)

UNITS

18
16

"CJW

oelW
oelW
oelW
oelW

43
38
43

98
158

8-Pin SO(S)

e lc

NOTES:
1. For supply VDltages less than ±22.V, the absolute maximum Input voltage is
equal to the supply voltage.
2. The OP-27"s InpUls are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low noise. If diflerentiallnput voltage
exceeds ~.7V, the input current should be limited to 25mA.
3. eiA is specified for worst case mounting conditions, i.e., eiA is specified for
device in socket for TO, CerDIP, P-DIP, and LCC packages; e' A is spacified
for device soldered to printed circuit bosrd for SO package. J
4. Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.

ABSOLUTE MAXIMUM RATINGS (Note 4)
Supply Voltage ................................................................. %22V
Input Voltage (Note 1) ...................................................... %22V
Output Short-Circuit Duration ................................... Indefinite
Differential Input Voltage (Note 2) .................................. %0.7V
Differential Input Current (Note 2) ................................ %25mA
Storage Temperature Range ........................ -65·C to +150·C

ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = 25·C, unless otherwise noted.
OP-27A/E
PARAMETER

SYMBOL CONDITIONS

Input Offset Voltage

Vos

Long-Term Ves

Stability

lOS

Input Bias Current

Ie

Input Noise
Voltage Density

enp _p

(Notes 3. 5)

fo= 10Hz (Note3!

fO= 30Hz 1Note 3)
fo= 1000Hz INote3,

in

fa = 30Hz 1Notes 3, 61

fo= 10Hz (Notes 3,6,
fo= 1000Hz (Notes 3, 61

Input Resistance Differential-Mode

O.IHz to 10Hz

RIN

INote71

MAX

10
0.2

MIN

TYP

MAX

TYP

MAX

UNITS

25

20

60

30

100

~V

1.0

0.3

1.5

0.4

2.0

/lV/Mo

50

12

Input Voltage Range
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio

75

nA

±40

±12

±55

±15

±80

nA

0.08

0.18

0.08

0.18

0.09

0.25

~Vp-p

3.5
3.1
3.0

5.5
4.5
3.8

3.5
3.1
3.0

5.5
4.5
3.8

3.8
3.3
3.2

8.0
5.6
4.5

nVl..jHZ

1.7
1.0
0.4

4.0
2.3
0.6

1.7
1.0
0.4

4.0
2.3
0.6

1.7
1.0
0.4

0.6

0.94

1.3

Voltage Gain
Output Voltage
Swing

IVR

Slew Aate

=±11V

CMRR

VCM

PSRR

Vs = ±4V to ±18V

Avo

RL "2kll. VO=±10V
RL ,,60011. Vo = ± 10V

Vo
SR

pAl..jHZ

0.7

Mil

2.5

R'NCM

Large-Signal

MIN

±10

Input ReslstanceCommon-Mode

OP-27C/G

OP-27B/F

TYP

35

en

Input Noise
Current Density

(Note11

Ves/Time (Notes 2,31

Input Offset Current

Input Noise Voltage

MIN

±11.0

±12.3

±11.0

±12.3

±11.0

±12.3

V

114

126

106

123

100

120

dB

10

10
1000
800

1800
1500

1000
BOO

1800
1500

RL~2kn

±12.0

±13.8

±12.0

RL " 80011

±10.0

±11.5

±10.0

1.7

2.8

1.7

AL

~

2kn •Note 4·

2-170 OPERATIONAL AMPLIFIERS

Gil

20
700
600

1500
1500

±13.8

±11.5

±13.5

±11.5

±10.0

±11.5

2.8

1.7

2.B

~VN

VlmV

V
Vlp,s

REV. A

OP-27
ELECTRICAL CHARACTERISTICS at Vs

= ±15V, TA = 25°C, unless otherwise noted. (Continued)
OP-27A/E

PARAMETER

SYMBOL CONDITIONS

Gain Bandwidth Prod. GBW
Open-Loop Output
Resistance

Power Consumption

(Note 4)

MIN

TYP

5.0

8.0

RO

70

Pd

90

OP-27B/F
MAX

MIN

TYP

5.0

8.0

OP-27C/G
MAX

MIN

TYP

5.0

8.0

MHz

70

n

70
140

90

140

100

MAX

170

UNITS

mW

Offset Adjustment

__
~~_________________R_p_=__
10_k_n___________________±_4_.0
____________________±_4_.0____________________±_4_._0_____________
m_v_
_Range
NOTES:
1. Input offset voltage measurements arB performed - 0.5 seconds after
application of power. AlE grades guaranteed fully warmed-up.
2. Long·term input offset voltage stability refers to the average trend line of
Vas VS. Time over extended periods after the first 30 days of operation.
Excluding the initial hour of operation, changes in Vas during the first 30

days are typically 2.5"V - refer to typical performance curve.
3. Sample tested.
4. Guaranteed by design.
5. See test circuit and frequency response curve for 0.1 Hz to 10Hz tester.
6. See test circuit for current noise measurement.
7. Guaranteed by input bias current.

ELECTRICAL CHARACTERISTICS for Vs = ± 15V, -55° C ::; TA::; + 125° C, unless otherwise noted.
OP-27A
PARAMETER

SYMBOL

CONDITIONS

Input Offset Voltage

Vas

(Note 11

Average Input
Offset Drift

TeVos
TCVoSn

(Note 2)

Input Offset Current

los

Input Bias Current

Ie

Input Voltage Range

IVR

Common-Mode
Rejection Ratio

CMRR

Power Supply
Rejection Ratio

PSRR

Vs = ±4.5V to ±18V

Large-Signal
Voltage Gain

AyO

RL ,,2kU, Vo =±10V

Output Voltage
Swing

Va

MIN

(Note 31

OP-27B

TYP

MAX

30

0.2

MIN

OP-27C

TVP

MAX

MIN

TVP

MAX

UNITS

80

50

200

70

300

"V

0.6

0.3

1.3

0.4

1.8

15

50

22

85

30

135

nA

±20

±80

±28

±95

±35

±150

nA

±10.3

±11.5

±10.3

±11.5

±10.2

±11.5

V

108

122

100

119

94

116

dB

16

4

20

51

,.VN

800

1200

500

1000

300

800

VlmV

±11.5

±13.5

±11.0

±13.2

±10.5

±13.0

V

ELECTRICAL CHARACTERISTICS at VS =±15V, -25°C,; TA ,; +85°C for OP-27J and OP-27Z, DoC,; TA ,; +70°C for OP-27EP,
FP and -40°C ,; TA ,; +85°C for OP-27GP, GS, unless otherwise noted.
OP-27F

OP-27E
PARAMETER

SYMBOL

Input Offset Voltage

Vas

Average Input
Offset Drift

TCVOS
TCVOS.

Input Offset Current

los

Input Bias Current

Ie

Input Voltage Range

IVR

Common-Mode
Rejection Ratio

CONDITIONS

(Note21
(Note 31

CMRR

Power Supply
Rejection Ratio

PSRR

large-Signal
Voltage Gain

AyO

Output Voltage
Swing

Va

MIN

MAX

UNITS

40

140

55

220

"V

0.6

0.3

1.3

0.4

1.8

"VlOC

0.2

MIN

10

50

14

85

20

135

nA

±14

±80

±18

±95

±25

±150

nA

±10.5

±11.8

±to.5

±11.8

±10.5

±11.8

V

110

124

102

121

98

118

dB

15

VS =±4.5VIO ±18V

16

2

32

"VN

750

1500

700

1300

450

1000

VlmV

±11.7

±13.6

±11.4

±13.5

±11.0

±13.3

V

Input offset voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power. AlE
grades guaranteed fully warmed-up.

REV. A

TVP

50

20

NOTES:
1.

MAX

MAX

MIN

OP-27G

TYP

TYP

2. The TeVos performance is within the specifications unnulled or when
nulled with Rp = 8kU to 20kU. TCVos is 100% tested for AlE grades,
sample tested for BICIFIG grades.
3. Guaranteed by design.

OPERA TlONAL AMPLIFIERS 2-171

2

OP-27
DICE CHARACTERISTICS
1.
2.
3.
4.
6.

NULL
(-) INPUT
(+) INPUT
VOUTPUT

7. V+
8. NULL
For additional DICE ordering Information,
refer to 1990/91 Data Book, Section 2.

DIE SIZE 0.109 x 0.055 inch, 5995 sq. mils
(2.77 x 1.40mm, 3.88 sq. mm)

WAFER TEST LIMITS at Vs = ± 15V, T A = 25° C for OP-27N, OP-27G, and OP-27GR devices; T A = 125 0 C for OP-27NT and
OP-27GT devices, unless otherwise noted.
OP-27NT
PARAMETER

SYMBOL

CONDITIONS

Input Offset Voltage

Vas

(Note 11

Input Offset Current

los

Input Bias Current

IB

Input Voltage Range

IVR

Common-Mode
Rejection Ratio

CMRR

VCM = IVR

Power Supply
Rejection Ratio

PSRR

Vs = ±4V to ±18V

Large-Signal
Voltage Gain

Ava

RL ", 2kO. Vo= ±10V
RL "'6000. Vo =±10V

Output Voltage Swing

Va

R L ::=: 2kfl
R L "'6000

Power Consumption

Pd

OP-27N OP-27GT

OP-27G OP-27GR

LIMIT

LIMIT

LIMIT

LIMIT

LIMIT

UNITS

60

35

200

60

100

p.VMAX

50

35

85

50

75

nAMAX

±60

±40

±95

±55

±80

nAMAX

±10.3

±11

±10.3

±11

±11

VMIN

108

114

100

106

100

dB MIN

10

20

p.V/v MAX

V/mVMIN

10
600

1000
BOO

500

1000
BOO

700
600

±11.5

±12.0
±10.0

±11.0

±12.0
±10.0

±11.5
±10.0

VMIN

140

170

mWMAX

140

Vo=O

NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

TYPICAL ELECTRICAL CHARACTERISTICS at Vs =

± 15V, TA =

+25 0 C, unless otherwise noted.

OP-27N

OP-27G

OP-27GR

TYPICAL

TYPICAL

TYPICAL

UNITS

0.2

0.3

0.4

p.VloC

TCtos

80

130

180

pN°C

Average Input Bias
Current Drift

TCI B

100

160

200

pA/oC

tnput Noise
Voltage Density

eo

fo= 10Hz
fo= 30Hz
fo~ 1000Hz

3.5
3.1
3.0

3.5
3.1
3.0

3.B
3.3
3.2

nV/VHZ

Input Noise
Current Density

io

fo= 10Hz
fo~ 30Hz
fo~ 1000Hz

1.7
1.0
0.4

1.7
1.0
0.4

1.7
1.0
0.4

pA/VHZ

0.08

0.08

0.09

!,Vp-p

2.8

2.8

2.8

V/p.s

PARAMETER

SYMBOL

CONDITIONS

Average Input Offset
Voltage Drift

TCVos or
TCVoSn

Nulled or Un nulled
Rp ~ 8kO to 20kO

Average Input Offset
Current Drift

Input Noise Voltage

e np _p

0.1Hz to 10Hz

Slew Rate

SR

R L ", 2kll

Gain Bandwidth Protluct

GBW

MHz

NOTE:
1. Input offset voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power.

2-172 OPERA TIONAL AMPLIFIERS

REV. A

OP-27
TYPICAL PERFORMANCE CHARACTERISTICS
O.1Hz TO 10Hzp _p NOISE TESTER
FREQUENCY RESPONSE

-

'09

'00 r-1rTl"lTl11r-rrr

'00

•

90 H-t.lill'lHt-'H+

7

1 70 Hrtt-tHttt-H+

-

(5
Z 3
w

;::

~ 60 H'-H-flfHHH+

~

g

TEST TIME OF 10 SEC FURTHER

~.oL.,. .L.lwliL.L'l lw

t--

74'

TA - 25"C
Vs '" ±15V

~: ~,
~ 4 ,....
,

.0~'-H-flfHf---iH+

50

A COMPARISON OF
OP AMP VOLTAGE
NOISE SPECTRA

VOLTAGE NOISE DENSITY
VI FREQUENCY

Ilf CORNER
= 2.7Hz

2

Ilf CORNER

Ilf CORNER
2.1Hz

1£

N

O

10

100

,,

INPUT WIDEBAND VOLTAGE
NOISE vs BANDWIDTH (O.1Hz
TO FREQUENCY INDICATED)

I'f CORNER

'000

1IIIII

III

AUDIO RANGE

INSTRUMENTATION
RANGE, TO DC

TO 20kHz

10

100

'000

FREQUENCY (Hz)

FREQUENCY (Hz)

FREQUENCY (Hz)

OP AMP

~ ~OP'27

,
1

LOW NOISE
AUDIO

:::l~

11111111

IISlolLl .:_°J.WIJ.IIF.ulliUJE
IIQIWI,IUIL..:.J1C.J1...L1.u'
11111lII·I,Il..'I:_"u.I.1JUJJJ,oo
I

•

,

......

TOTAL NOISE vs SOURCE
RESISTANCE
,ooF=FATFFf1F====='=fI

VOLTAGE NOISE DENSITY
VI TEMPERATURE

i=
=.,
t-~_v-j~_=-j"r-rt+t-rtt-=_

4>-

T -25'C

5V

1--t-t-l+f+ltI-- RS = 2R,

~ 10!'!!!~~!lII~~~~~!II
~

:- AT 'OH,
AT 1kHz

0.01 '--'-J...I.UJ.II.1---1...I...J..L.I.I.I.II......I...LLllLW

lk
10k
BANDWIDTH (Hz)

'00

lOOk

100

VOLTAGE NOISE DENSITY
VI SUPPLY VOLTAGE

--

~

~

z

3

w

-50

-25

0

25

50

TEMPERATURE

76

100

125

fe)

SUPPLY CURRENT VI
SUPPLY VOLTAGE
5.0

10.0

1 4.0

AT 10Hz

t-

,'-~-~--~--~--~--~~

10k

1m

CURRENT NOISE DENSITY
VI FREQUENCY

T!.2S'C
~4

lk
SOURCE RESISTANCE

....

~
a:
a: 3.0

"

AT 1kHz

~

g2

""
~

iil 2.0

Ilf CORNER

,

o.
o

10

~

~

TOTAlSUPPlV VOLTAGE (V+ - V-I (VOLTS)

REV. A

~

,

- r- = 140Hz

'0

11111111

I

100
lk
fREQUENCY (Hz)

1.0
'Ok

S

'5

25

35

45

TOTAL SUPPLY VOLTAGE (VOLTS)

OPERA TIONAL AMPLIFIERS 2-173

OP-27
TYPICAL PERFORMANCE CHARACTERISTICS
OFFSET VOLTAGE DRIFT OF
EIGHT REPRESENTATIVE UNITS
VB TEMPERATURE.
60
40

~

r-

20

~

w

11
:;

V
V

./

V
./

....... ~ -< V"
....... ......
.".,

0

g

...

~ '-

~ -20

o

........

-60

T~Vasl
50

25

0

25

-

.:'

a'TA

:::---

-......;;

-2
OP-27B
OP·27A

~i'...

"

OP-27 ClG

50

..".. ~

fe)

/'..

I
I

"

75 100

"""

-2
-4

QP·27C

-6

125 150 175

-

50

w

W
BA"

II
THER~

SHOCK
RESPONSE

I I I
A I I I I

" t-....

10

I'-r-.

0

...

OP-278

k:u

20

40

-"

60

BO

-50

100

-26

"-

125

1

0

.'-.SLEW

'\.

I'\.

-1 0

1k
10k lOOk
FREQUENCY (Hz)

1M

10M 100M

2-174 OPERA TlONAL AMPLIFIERS

-50 -25

,....

0
25
50
75
TEMPERATURE COC)

-5

100

125

100

T~ J2~~1
Vs = ±15V

125

1M

60
100
120·_

40~Ii:

\

1

PHASE \
MARGIN

60~

-71f'

II

-

~.27A

0
25
50
75
TEMPERATURE (OCI

~Lj

-10
-75

-25

~

t\

II'-

"- I'-

25
20

10

50

QP·27B

GAIN, PHASE SHIFT vs
FREQUENCY

15

-GBW

~

-I--:

-75 -50

150

=~M

60

"-

100

100

VS,",±l5V-

"- I'-

10

0
26
50
15
TEMPERATURE tOCI

SLEW RATE, GAIN-BANDWIDTH
PRODUCT, PHASE MARGIN VB
TEMPERATURE
70

0

,,,"
,~ ~ t'--

OP-27A

OPEN-LOOP GAIN vs
FREQUENCY

130

JJ-

III

TIME (SEC)

110

I
0

IN 7rrC OIL BATH

0
~ -20

50

I i OP-27C

; - - ~ DEVICE IMMERSED

5
~

OP·27 AlE

INPUT OFFSET CURRENT
vs TEMPERATURE

IJU

20

B/F

TIME AFTER POWER ON (MINUTES)

II
30
I ,ill OP·27C
r\ \ 1\

I I I I

......
~

ap.J

f-

V

INPUT BIAS CURRENT
vs TEMPERATURE

TA = looC

V

00

o

40

I

-.... r-

TIME (MONTHS)

V~:~'5)-

111111

w 10

~
/

L

.....,

I I I II I

;-;-;-;--

L+2..J

r-- Vs -±16V

-6

OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK

25"C

-

-4

OP-Z7B

TEMPERATURI,:

TA"

WARM-UP OFFSET
VOLTAGE DRIFT

OP·27A

I--- ,.."

TRfMMING WITH"""
10k POT DOES
NOT CHANGE

-75

OP-27C
OP-27B

I

-

-40

LONG-TERM OFFSET
VOLTAGE DRIFT OF SIX
REPRESENTATIVE UNITS

1

\

"

~

180 ..
200

r\.

10M

220
100M

FREQUENCY (Hz)

REV. A

OP-27
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN-LOOP VOLTAGE GAIN
vs SUPPLY VOLTAGE
28

I

2.
5

RL = 2kn

y

2. o - T A '" 2SOC

:;-

/'

~

Ui 24

!:;
o
?
w
c

RL""SOOn

./ . / f -

zl. 5

g
~

Vs '" ±15V

14

I-

12

r-

20

POJITIJe

NEGATIVE
SWING

/1
r'l'

" 12

..::I~

.

"

::'

o

50

10
20
30
40
TOTAL SUPPLY VOLTAGE (VOLTS)

\

8

0.0

1k

SMALL-SIGNAL OVERSHOOT
vs CAPACITIVE LOAD

•

V

10

:i

r-

SWING

~

0.5

o

16

:>

,V

~1.0

18

Ill~LW

!: 16

~ /"

~

MAXIMUM OUTPUT VOLTAGE
VI LOAD RESISTANCE

MAXIMUM OUTPUT SWING
vs FREQUENCY

TA = 25°C

f--

i'10k

lOOk
1M
FREQUENCY {H:d

Vs = ±15V

I III

-2
10M

100

SMALL-SIGNAL TRANSIENT
RESPONSE

1k
LOAD RESISTANCE 1m

10k

LARGE-SIGNAL TRANSIENT
RESPONSE

100
5amV

+5V

OV

OV

-50mV

-5V

80

,;

0

40

20

o

/

/

/

o

Vs = t15V

VIN"',OOmV AV=+l

I
500

AVCl = +1, C L ~ 15pF
Vs = ±15V
TA =25"C

I

, 000
1500
2000
CAPACITIVE LOAD (pF)

A;VCL =+1
Vs =.±15V .
TA = 25°C

2500

SHORT-CIRCUIT CURRENT
vsTIME
80

140

il:

~40

il....

S
[i30

f\..

120

TA =+25°C
VS=±1SV

~

~

\

~w

i -41-----~~~~+----+----__\

ISCI+)

r\

0

20

8

ill .1---------,k:iI::9"'--+----+----__\

100

o

ili

121----1---

Vs = ±15V
VCM = ±10V

~sc~1

~

16r-----r-----,------r~~-,

111~Jl1JI

<;50

oS
....

COMMON-MODE INPUT RANGE
VI SUPPLY VOLTAGE

CMRR vs FREQUENCY

8

-8

-121-------~----+--~~~--__\
10

o

1

2

3

5

TIME FROM OUTPUT SHORTED TO GROUND (MINUTES)

80
100

-16L-____L-____
lk

10k

lOOk

~----~~~~

1M

FREQUENCY (Hz)

REV. A

OPERA TIONAL AMPLIFIERS 2-175

OP-21
TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE NOISE TEST CIRCUIT (O.1Hz-TO-10Hz)

LOW-FREQUENCY NOISE
120
80
40

-40

-80
-120

a.1Hz TO 10Hz PEAK-TO-PEAK NOISE
NOTE: ALL CAPACITOR VALUES ARE FOR
NON POLARiZeD CAPACITORS ONLY.

NOTE:
Observation time limited to 10 seconds.

OPEN-LOOP VOLTAGE GAIN VI
LOAD RES.ISTANCE
:: f-

~/ 12~1~11.+--l--+-I-J-I.mI---I--.l-U.wu

~ 2'{) I-- Vs ":t15V"t--++:I~#!--+-l-I-!-I-I~

j,
1.81--+1+I+Hl+/,-+-WW+--I-.+-WlJl.I
1-A
~ 1.6 1-+1+I+Hl.IJ1/Y+WW+--I-.+-WlJl.I

2:
~

~ 1.4 1--HI+I+IIl+-+-I-+-I+Hl+--+--I-+-I~

o

>121--H1+I~+-+-1-+-I+Hl+--+--1-+-I~

8.

~ 1.0 1--HI-+l+lJj+-+-~+I.JI+---l--l-H~
~"

!5

O.81--Hf+I+IJj+--I-~+I.JI+---l--l-H~

0.6

17-+-JL+-I++tfl,-++-+-I++lIl--I-+-+-1+llI-

PSRR VI FREQUENCY
160

I

~ 140
~ 12o~
~ 100

~
;;J
a:

o f.-

~

POSITl~

~ 60

~

il:

iil

NEGATIVE

~UPPLY

SUPPLY

40

a:
w

~

20

0.4 L.-L.W-LillLL..-L.W-llUll.......Ll..l.UllJ.
100

lk

10k

lOOk

10

LOAD RESISTANCE 1m

APPLICATIONS INFORMATION
OP-27 Series units may be inserted directly into 725, OP-06,
OP-07 and OP-05 sockets with or without removal of external
compensation or nulling components. Additionally, the OP27 may be fitted to unnulled 741-type sockets; however, if
conventional 741 nulling circuitry is in use, itshould be modified or removed to ensure correct OP-27 operation. OP-27
offset voltage maybe nulled to zero (or other desired setting)
using a potentiometer (see Offset Nulling Circuit).
The OP-27 provides stable operation with load capacitances
of up to 2000pF and ± 10V swings; larger capacitances should
be decoupled with a 500 resistor inside the feedback loop.
The OP-27 is unity-gain stable;
Thermoelectric voltages generated by dissimilar metals at
the input terminal contacts can degrade the drift performance. Best operation will be obtained when both input
contacts are maintained at the same temperature.
OFFSET VOLTAGE ADJUSTMENT
The input offset voltage of the OP-27 is trimmed at wafer
level. However, if further adjustment of Vos is necessary, a
10kO trim potentiometer may be used. TCVosis not degraded

2-176 OPERA TIONAL AMPLIFIERS

J

TA = 2rf'c-

o

100

~

~

lk
10k lOOk 1M
FREQUENCY (Hz)

10M 100M

(see Offset Nulling Circuit). Other potentiometer values from
1kO to 1MO can be used with a slight degradation (0.1 to
0.2p.VloC) of TCVos. Trimming to a value other than zero
creates a drift of approximately (Vosl300) p.Vlo C. For example, the change in TCVos will be 0.33p.V/o C if Vos is adjusted
to 100p.V. The offset-voltage adjustment range with a 10kO
potentiometer is ±4mV. If smaller adjustment range is required, the nulling sensitivity can be reduced by using a
smaller pot in conjuction with fixed resistors. For example,
the network below will have a ±280p.V adjustment range.

4.7kH

lknPOT

4.7kn

V+

NOISE MEASUREMENTS
To measure the 80nV peak-to-peak noise specification olthe
OP-27 in the 0.1 Hz to 10Hz range, the following precautions
must be observed:
(1) The device has to be warmed-up for at least five minutes.
As shown in the warm-up drift curve, the offset voltage

REV. A

OP-27
typically changes 4p.V due to increasing chip temperature
after power-up. In the 10-second measurement interval,
these temperature-induced effects can exceed tens-ofnanovolts.
(2) For similar reasons, the device has to be well-shielded

from air currents. Shielding minimizes thermocouple
effects.
(3) Sudden motion in the vicinity ofthe device can also "feedthrough" to increase the observed noise.
(4) The test time to measure 0.1 Hz-to-10Hz noise should not
exceed 10 seconds. As shown in the noise-tester frequencyresponse curve, the 0.1 Hz corner is defined by only one
zero. The test time of 10 seconds acts as an additional
zero to eliminate noise contributions from the frequency
band below 0.1 Hz.
(5) A noise-voltage-density test is recommended when
measuring noise on a large number of units. A 10Hz
noise-voltage-density measurement will correlate well
with a 0.1 Hz-to-10Hz peak-to-peak noise reading, since
both results are determined by the white noise and the
location of the 1/f corner frequency.

bias-current cancellation circuit. The OP-27 AlE has IB and
los of only ±40nA and 35nA respectively at 25° e. This is
particularly important when the input has a high sourceresistance. In addition, many audio amplifier designers
prefer to use direct coupling. The high IB' Vos, TeVos of
previous designs have made direct coupling difficult, if not
impossible, to use.
Voltage noise is inversely proportional to the square-root of
bias current, but current noise is proportional to the squareroot of bias current. The OP-27's noise advantage disappears
when high source-resistors are used. Figures 1, 2, and 3
compare OP-27 observed total noise with the noise performance of other devices in different circuit applications.
Total noise = [(Voltage nOise)2
(resistor noise)2]1/2

+ (current

noise x RS)2

+

Figure 1 shows noise-versus-source-resistance at 1000Hz.
The same plot applies to wideband noise. To use this plot, just
multiply the vertical scale by the square-root of the
bandwidth.

UNITY-GAIN BUFFER APPLICATIONS
When RIS1000 and the input is driven with a fast, large signal
pulse (>1V), the output waveform will look as shown in the
pulsed operation diagram below.

NOISE vs SOURCE RESISTANCE
(INCLUDING RESISTOR NOISE)
AT 1000Hz.
100

During the fast feedthrough-like portion of the output, the
input protection diodes effectively short the output to the
input and a current, limited only by the output short-circuit
protection, will be drawn by the signal generator. With
RI ~ 5000, the output is capable of handling the current
requirements (ILS 20mA at 10V); the amplifier will stay in its
active mode and a smooth transition will occur.

50

l....I:i

OP-08I1D8

~

toJ

1 As UNMATCHED

5634

When RI > 2kO, a pole will be created with RI and the
amplifier's input capacitance (8pF) that creates additional
phase shift and reduces phase margin. A small capacitor
(20 to 50pF) in parallel with RI will eliminate this problem.

e.g.Rs-RS1-1Ok,RS200
2RsMATCHED
•. g.RS"10k.R:sl=RS2"'5k

OP-27/37

~.l.ISTOR
NOISE ONLY
1

50

100

500 1k

itt>
"52

5k

10k

50k

RS - SOURCE RESISTANCE (n)

PULSED OPERATION
Figure 1

R,
At Rs < 1k~, the OP-27's low voltage noise is maintained.
With Rs> 1kO, total noise increases, but is dominated by the
resistor noise rather than current. or voltage noise. It is only
beyond Rs of 20kO that current noise starts to dominate. The
argument can be made that current noise is not important for
applications with low-to-moderate source resistances. The
crossover between the OP-27 and OP-07 and OP-08 noise
occurs in the 15-to-40kO region.
COMMENTS ON NOISE
The OP-27 is a very low-noise monolithic op amp. The outstanding input voltage noise characteristics ofthe OP-27 are
achieved mainly by operating the input stage at a high quiescent current. The input bias and offset currents, which would
normally increase, are held to reasonable values by the input-

REV. A

Figure 2 shows the 0.1 Hz-to-10Hz peak-to-peak noise. Here
the picture is less favorable; resistor noise is negligible, current noise becomes important because it is inversely proportional to the square-root of frequency. The crossover with the
OP-07 occurs in the 3-to-5kO range depending on whether
balanced or unbalanced source resistors are used (at 3kO the
IB' los error also can be three times the Vos spec.).

OPERATIONAL AMPLIFIERS 2-177~

2

OP-27
10Hz NOISE vs
SOURCE RESISTANCE .
(INCLUDES RESISTOR NOISE).

PEAK-TO-PEAK NOISE (0.1 to
10Hz) VB SOURCE RESISTANCE
(INCLUDES RESISTO.R NOISE).

,.

100
OP~/1OS

&liM

500

0

/,2

1111

?r.i"7
~

IIII

100

V

"

0

OP-27/37
1 RS UNMATCHED

J....

~~::I~~
500 lk

100

."
~.
5k

10k

27

,
SDk

50

RS.- SOURCE RESISTANCE In)

Figure 3

Therefore, for low-frequency applications, the OP-07 is better than the OP-27/37 when Rs> 3kO. The only exception is
when gain error is important. Figure 3 illustrates the 10Hz
noise. As expected, the results are between the previous two
figures.
For reference, typical ·source resistances of some signal
sources are listed in Table 1.

Table 1
SOURCE
I~PEDANCE

1 RS UNMATCHED

e:.g. RrR$"tOk.Rs2-G

it- I"J;

•. g.Rs=1Ok.R$t"RsrSk

DEVICE

~

1/

5

e.g.RrRs,-101c,Rs2"O
2 AS MATCHED

Figure 2

~~~7
5534

so

10
SO

~

OP-08/108

COMMENTS

Strain gauge

<.5000

Typically used in low-frequency
applications.

Magnetic
tapehead

<15000

Low la very important to reduce
self-magnetization problems when
di~t coupling is used. OP-27 la
can be neglected.

Magnetic
phonograph
cartridges

<15001l

Similar need for low la in direct
coupled applications. OP-27 will not
introduce any self-magnetization
problem.

Linear variable
differential
transformer

<15000

Used in rugged servo-feedback
applications. Bandwidth of interest is
400Hz to 5kHz.

r-

MRESISTOR

~~,sr l~i~,T
600 1k

100

2 RSMATCHEO

e.40R$=1Ok,Rs,=RS2=6k

.~.
5k

10k

SOk

RS - SOURCE RESISTANCE (n)

AUDIO APPLICATIONS
The following applications information has been abstracted
from a PMI article in the 12/20/80 issue of Electronic Design
magazine and updated.
Figure 4 is an example of a phono pre-amplifier circuit using
the OP-27 for A1; R1-R2"C1-C2·form a very accurate RIAA
network with standard component values. The popular method
to accomplish RIAA phono equalization is to employ
frequency-dependent feedback around a high-quality gain
block. Properly chosen, an RCnetwork can provide the three
necessary time constarits of 3180, 318, and 751's.1
For initial equalization accuracy and stability, precision
metal-film resistors and film capacitors of polystyrene or
polypropylene are recommended since they have low voltage
coefficients, dissipation factors, and dielectric absorption. 4
(High-K ceramic capacitors should be avoided here, though
low-K ceramics-such as NPO types, which have excellent
dissipation factors, and somewhat lower dielectric absorptioncan be considered for small values.)

C4(2)

22O,F

~~
,___ 6 l~n~
LF ROLLOFF
-=
OUT

IN

C3

OPEN-LOOP GAIN

0.47pF

OUTPUT

FREQUENCY
AT:

OP-G7

OP~27

OP47

3Hz

100dB

124dB

125dB

10Hz

100dB

120dB

125dB

30Hz

90dB

HOdB

124dB

R'

Rl
S7.6kU

lSkU

R3

For further information regarding noise calculations, see
"Minimization of Noise in Op-Amp Applications", Application
Note AN-15.

2-178 OPERATIONAL AMPLIFIERS

lOon

*)

G= 1kH%GAIN

=0.101 (1+

Figure 4

- 98.877 139.9 dBI AS SHOWN

REV. A

OP-27
The OP-27 brings a 3.2nV/VHZ voltage noise and 0.45
pAlVHZ current noise to this circuit. To minimize noise
from other sources, R3 is set to a value of 1000, which
generates a voltage noise of 1.3nVlVHZ. The noise increases the 3.2nVlVHZ of the amplifier by only 0.7dB. With
a 1 kO source, the circuit noise measures 63dB below a 1mV
reference level, unweighted, in a 20kHz noise bandwidth.
Gain (G) of the circuit at 1kHz can be calculated by the
expression:
G=0.101 (1

+ =~

)

For the values shown, the gain is just under 100 (or 40dB).
Lower gains can be accommodated by increasing R3, but
gains higher than 40dB will show more equalization errors
because of the SMHz gain-bandwidth of the OP-27.
This circuit is capable of very low distortion over its entire
range, generally below 0.01% at levels up to 7V rms. At 3V
output levels, it will produce less than 0.03% total harmonic
distortion at frequencies up to 20kHz.

The network values of the configuration yield a 50dB gain at
1kHz, and the dc gain is greater than 70dB. Thus, the worstcase output offset is just over 500mV. A single 0.471'F output
capacitor can block this level without affecting the dynamic
range.
The tape head can be coupled directly to the amplifier input,
since the worst-case bias current of SOnA with a 400mH, 100
I'in. head (such as the PRB2H7K) will not be troublesome.
One potential tape-head problem is presented by amplifier
bias-current transients which can magnetize a head. The
OP-27 and OP-37 are free of bias-current transients upon
power up or power down. However, it is always advantageous
to control the speed of power supply rise and fall, to eliminate transients.
In addition, the dc resistance of the head should be carefully
controlled, and preferably below 1kO. For this configuration, the bias-current-induced offset voltage can be greater
than the 100l'V maximum offset if the head resistance is not
sufficiently controlled.

Capacitor C3 and resistor R4 form a simple -6dB-per-octave
rumble filter, with a corner at 22Hz. As an option, the switchselected shunt capacitor C4, a non polarized electrolytic,
bypasses the low-frequency rolloff. Placing the rumble filter's high-pass action after the preamp has the desirable
result of discriminating against the RIAA-amplified lowfrequency noise components and pickup-produced lowfrequency disturbances.

A simple, but effective, fixed-gain transformerless microphone preamp (Fig. 6) amplifies differential signals from lowimpedance microphones by 50dB, and has an input impedance of 2kO. Because of the high working gain of the circuit,
an OP-37 helps to preserve bandwidth, which will be 110kHz.
As the OP-37 is a decompensated device (minimum stable
gain of 5), a dummy resistor, Rp, may be necessary, if the
microphone is to be unplugged. Otherwise the 100% feedback from the open input may cause the amplifier to oscillate.

A preamplifier for NAB tape playback is similar to an RIAA
phono preamp, though more gain is typically demanded,
along with equalization requiring a heavy low-frequency
boost. The circuit in Fig. 4 can be readily modified for tape
use, as shown by Fig. 5.

Common-mode input-noise rejection will depend upon the
match of the bridge-resistor ratios. Either close-tolerance
(0.1%) types should be used, or R4 should be trimmed for best
CMRR. All resistors should be metal-film types for best stability and low noise.

O.47,uF

TAPE
HEAD

R,

C,
Rl
313kH
R2

5kn.

loon

O.Q1J,.1F

f

Noise performance of this circuit is limited more by the input
resistors R, and R2 than by the op amp, as R, and R2 each
generate a 4nVlVHZ noise, while the op amp generates a
3.2nVlVHZ noise. The rms sum of these predominant noise
sources will be about 6nVlVHZ, equivalent to 0.91'V in a
20kHz noise bandwidth, or nearly 61dB below a 1mV input
signal. Measurements confirm this predicted performance.

Rl

T1 = 3180t-ls

R3

lkn

316kH

Cl

R6

5,uF

loon

T2 "'50,,5

Figure 5

While the tape-equalization requirement has a flat highfrequency gain above 3kHz (T2 = SOl's), the amplifier need
not be stabilized for unity gain. The decompensated OP-37
provides a greater bandwidth and slew rate. For many applications, the idealized time constants shown may require
trimming of R, and R2 to optimize frequency response for
non ideal tape-head performance and other factors. 5

REV. A

LOW IMPEDANCE
MICROPHONE INPUT ~
(Z-50T0200m
~.-L.

R3
Rl

R4
R2

R2
lkn

R7

OUTPUT

10k!1

R4

316kD

Figure 6

OPERA TlONAL AMPLIFIERS 2-179

II

OP-27
For applications demanding appreciably lower noise, a highquality microphone-transformer-coupled preamp (Fig. 7)
incorporates the internally-compensated OP-27. T1 is a
JE-115K-E 150!ll15kO transformer which provides an optimum source resistance for the OP-27 device. The circuit has
an overall gain of 40dB, the product of the transformer's
voltage setup and the op amp's voltage gain.

C2

1800pF

"'
121n

"2
1100<1

OUTPUT

eliminated in such cases, but is desirable for higher gains to
eliminate switching transients.
Capacitor C2 and resistor R2 form a 21's time constant in this
circuit, as recommended for optimum transient response by
the transformer manufacturer. With C2 in use, A1 must have
unity-gain stability. For situations where the 21's time constant is not necessary, C2 can be deleted, allowing the faster
OP-37 to be employed.
Some comment on noise is appropriate to understand the
capability of this circuit. A 1500 resistor and R1 and R2 gain
resistors connected to a noiseless amplifier will generate 220
nV of noise in a 20kHz bandwidth, or 73dB below a 1mV
reference level. Any practical amplifier can only approach
this noise level; it can never exceed it. With the OP-27 and T1
specified, the additional noise degradation will be close to
3.6dB (or -69.5 referenced to 1mV).
References

Gain may be trimmed to other levels, if desired, by adjusting
R2 or R1. Because of the low offset voltage of the OP-27,the
output offset of this circuit will be very low, 1.7mVor less; for a
40dB gain. The typical output blocking capacitor can be

1. Lipshltz. S.P., "OnRIAA Equalization Networks," JAES, Vol. 27, June 1979,
p.458-481.
2. Jung, W.G., IC Op Amp Cookbook, 2nd Ed .. HW. Sams and Company,
1980.
'
3. Jung, W.G., Audio IC Op Amp Applications, 2nd Ed., H.W. Sams and
Company, 1978.
4. Jung, W.G., and Marsh, A.M., "Picking CapaCitors," Audio, February &
March, 1980.
5. 018la, M.... F~dback-Generated Phase Nonlinearity in Audio Amplifiers,"
London AES Convention, March 1980, preprint 1976.
6. Stout, D.F., and Kaufman, M., Handbook of Operational Amplifier Circuit
Design, New York. McGraw Hill, 1976.

BURN-IN CIRCUIT

OFFSET NULLING CIRCUIT

*Tl = JENSEN JE-115K-E

JENSEN TRANSFORMERS
10735 Burbank ~vd.
N. Hollywood, CA 91601

Figure 7

>"'....----ov+
~7---'.'---_ 5)
OP-37 I

1IIIIIIII ANALOG

WDEVICES

FEATURES
• Low Noise.. .... ..... ....... 80nV pop (O.lHz to 10Hz)
...................... 3nV/yHz at 1kHz
• Low Drift .................................. O.2J1.V/oC
• High Speed ......................... 17V/J1.s Slew Rate
. . . . . . . . . . . . . . . . .. 63MHz Gain Bandwidth
• Low Input Offset Voltage ....................... l0J1.V
• Excellent CMRR ... 126dB (Common-Voltage of ±11V)
• High Open-Loop Gain . . . . . . . . . . . . . . . . . . . .. 1.8 Million
• Replaces 725, OP-05, OP-06, OP-07, AD510, AD517,
SE5534 in Gains> 5
• Available in Die Form

ORDERING INFORMATION I
PACKAGE
TA =+25°C
VosMAX
(~V)

TO-99

CERDIP
8-PIN

25
25

OP37AJ+
OP37EJ
OP378J+
OP37FJ
OP37CJ+
OP37GJ

OP37AZ+
OP37EZ
OP378Z+
OP37FZ
OP37CZ
OP37GZ

60
60
100
100
100

tt

PLASTIC
8-PIN

OPERATING
LCC
TEMPERATURE
RANGE
20-CONTACT

OP37EP
OP378RC/883
OP37FP
OP37GP
OP37GStt

MIL
IND/COM
MIL
IND/COM
MIL
XIND
XIND

The OP-37 provides the low offset and drift of the OP-07 plus
higher speed and lower noise. Offsets down to 25J1.V and drift
of 0,6J1.V/oC maximum make the OP-37 ideal for precision
instrumentation applications, Exceptionally low noise
(e n=3,SnVlyHz at 10Hz),a low 1/1 noise corner frequency of
2,7Hz,andthehighgainofl,8million,allowaccuratehigh-gain •
amplification of low-level signals.
The low input bias current of± 10nAand offset currentof7nA are
achieved by using a bias-current-cancellation circuit. Over
the military temperature range this typically holds 18 and los
to ±20nA and lSnA respectively,
The output stage has good load driving capability. A guaranteed swing of ± 10V into 600n and low output distortion make
the OP-37 an excellent choice for professional audio
applications,

PIN CONNECTIONS

VOS TRIMf2t8
VOS TR:Mv+
-IN2

60UT

+IN3

For devices processed in total compliance to MIL -STD,883, add /883 after part
number. Consult factory for 883 data sheet.
Burn·jn is available on commercial and industrial temperature range parts in
CerDIP, plastic DIP, and TO-can packages.
For availability and burn-in information on SO package, contact your local
sales office.

GENERAL DESCRIPTION
The OP-37 provides the same high performance as the OP-27,
but the design is optimized for circuits with gains greater
than five. This design change increases slew rate to 17V1J1.sec
and gain-bandwidth product to 63MHz.

5 N.C.
4

v-

(CASE)

TO-99
(J-Sufllx)

8-PIN HERMETIC DIP

(Z-Sufllx)
EPOXY MINI-DIP

(P-Sufflx)

8-PINSO
(S·Suffix)

Op·37BRC/883
LCC PACKAGE
(RC·Suffix)

SIMPLIFIED SCHEMATIC
,-------~--------~--------~--~--~~----~------~--~~--+-~V+

OUTPUT

NONINVERTING

INPUT'G+:""+--+~P--+--IE"--t:
INVERTING
INPUT ,,":...'___

+-+-______+ _______

.-+__

~-------------------~~------

REV. A

___________~~~~~~~v_

OPERA TlONAL AMPLIFIERS 2-181

PSRR and CMRR exceed 120dB. These characteristics,
coupled with long-term drift of 0.2I'Vimonth, allow the circuit
designer to achieve performance levels previously attained
only by discrete designs.

Operating Temperature Range
OP-37A, OP-37B, OP-37C (J,Z, RC) .•....•.. -55°C to + 12S·C
OP-37E, OP-37F (J, Z) ................................. -2SoC to +85·C
OP-37E, OP-37F (P) ......................................... O·C to + 70·C
OP-37G (P, S, J, Z) ......................................,-40·C to +85·C
Lead Temperature Range (Soldering, 60 sec) ............... 300·C
Junction Temperature .................................... -6SoC to + 1S0·C

Low-cost, high-volume production ofthe OP-37 is achieved by
using on-chip zener-zap trimming. This reliable and stable
offset trimming scheme has proved its effectiveness over
many years of production history.

PACKAGE TYPE

The OP-37 brings low-noise instrumentation-type performance to such diverse applications as microphone, tapehead, and RIAA phono preamplifiers, high-speed signal conditioning for data acquisition systems, and wide-bandwidth
instrumentation.

9 1A (NOTE 3)

TO·99 (J)
8-Pin Hermetic DIP (Z)
8-Pin Plastic DIP (P)
20-Contact LCC (RC, TC)
8-Pin 50(5)

a lc

UNITS

18
16
43
38
43

·C/W
·C/W
·C/W
·C/W
·C/W

150
148
103
98
158

NOTES:
1. For supply voltages less than ,,22V, the absolute maximum input voltage Is
equal to the supply voltage.
2. The OP-37's inputs are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low noise. If differential Input voltage
exceeds ,,0.7V, the input current should be limited to 2SmA.
3. alA is specified for worst case mounting conditions, i.e., aJA is specified for
device in socket for TO, CerDIP, P,DIP, and LCe packages; alA Is speCified
for device soldered to printed circuit board for SO package.
4. Absolute .maximum ratings apply to both DICE and packaged parts, unless

ABSOLUTE MAXIMUM RATINGS (Note 4)
Supply Voltage .................................................................. ±22V
Internal Voltage (Note 1) ................................................... ±22V
Output Short-Circuit Duration ..................................... Indefinite
Differential Input Voltage (Note 2) ................................... ±O. 7V
Differential Input Current (Note 2) ................................. ±25mA
Storage Temperature Range ......................... -65·C to + 150·C

otherwise noted.

ELECTRICAL CHARACTERISTICS at Vs = ±1SV, TA = 2Soc, unless otherwise noted.
PARAMETER

SYMBOL CONDITIONS

Input Offset Voltage

Vos

Long~ Term

Vas

Stability

lOS

Input Bias Current

18

Input Noise Voltage

8 np _p

Voltage Density

Input Noise
Current Density

en

in

Input Resistance Common~Mode

Input Voltage Range
Common~Mode

Rejection Ratio
Power Supply
Rejection Ratio

R'N

0.1 Hz to 10Hz

Voltage Gain

Swing
Slew Rate
Gain Bandwidth Prod.

20

60

30

100

~V

0.2

1.0

0.3

1.5

0.4

2.0

~VlMo

50

12

75

nA

±10

±40

±12

±55

±15

±80

nA

0.18

0.08

0.18

0.09

0.25

~Vp-p

5.5
4.5

5.5
4.5
3.8

3.8
. 3.3
3.2

B.O
5.6
4.5

nV/,[Hz

3.B

3.5
3.1
3.0

fa = 10Hz (Notes 3, 6)

1.7
1.0
0.4

4.0
2.3
0.6

1.7
1.0
0.4

4.0
2.3
0.6

1.7
1.0
0.4

0.6

10 = 30Hz (Notes 3,6)

(Note 7)

1.3

0.94

VCM =±11V

PSSR

Vs = ±4V to ±IBV

GBW

pA/,[Hz

0.7

Mil

2.5

CMRR

SA

UNITS

25

3.5
3.1
3.0

IVR

Vo

OP-37C/G
MIN
TYP MAX

10

R 1NCM

Avo

OP-37B/F
TYP MAX

0.08

(Notes 3,5)

RL 2: 1kU, Va = ±10V

RL = 60011, Vo = ±IV,
Vs

Output Voltage

MIN

10 = 10Hz (Note 3)
fa = 30Hz (Note 3)
'0 = 1000Hz (Note3)

RL"'2kll, Vo=±10V
Large-Signal

OP-37A/E
TYP MAX

35

fa == 1000Hz (Notes 3,6)

Input ResistanceOifferential~Mode

(Notet)

Vas/Time (Notes 2,3)

Input Offset Current

Input Noise

MIN

= ±4V, (Note 4)

AL"'2kll
RL", 60011

Gil

±11.0

±12.3

±11.0

±12.3

±11.0

±12.3

V

114

126

106

123

. 100

120

dB

10

10

20

1000
800

1800
1500

1000
BOO

1800
1500

700
400

1500
1500

250

700

250

700

200

500

±12.0

±13.8

±11.5

±12.0
±10.0

±13.8
±11.5

±11.5
±10.0

±13.5

±10.0

~VIV

V/mV

V

±11.5

RL 2:2kU (Note 4)

11

17

11

17

11

17

VlIlS

fa = 10kHz (Note 4)

45

83

45

63
40

45

63
40

MHz

10= lMHz

2-182 OPERA TlONAL AMPLIFIERS

40

REV.

A

OP-37
ELECTRICAL CHARACTERISTICS at Vs = ±15V. TA = 25°C. unless otherwise noted. (Continued)
OP-37A1E
PARAMETER

SYMBOL CONOITIONS

Open-Loop Output
Aesistance

RO

Power Consumption
Offset Adjustment

TYP

VO~O.lo~O

70
90

~

10kll

OP-37B/F

MAX

Vo~O

Rp

Range

MIN

TYP

MIN

OP-37C/G

MAX

MIN

TYP

70
140

100

±4.0

NOTES:
1. Input offset voltage measurements are performed by automated test
equipment approximately 0.5 seconds after applicatJon of power. AlE
grades guaranteed fully warmed up.
2. Long-term input offset voltage stability refers to the average trend line of
Vas VS. Time over extended periods after the first 30 days 01 operation.

UNITS

70
140

90

±4.0

MAX

11
170

±4.0

mW
mV

days are typically 2.5p.V - refer to typical performance curve.

3. Sample tested.
4.
5.
6.
7.

Excluding the initial hour of operation, changes in Vos during the first 30

Guaranteed by
See test circuit
See test circuit
Guaranteed by

design.
and frequency response curve for O.lHz to 10Hz tester,
for current noise measurement.
input bias current.

ELECTRICAL CHARACTERISTICS for Vs = ±15V. -55°C::; TA::; +125°C. unless otherwise noted.
OP-37A
PARAMETER

SYMBOL

CONOITIONS

Input Offset Voltage

Vos

tNote 1)

Average Input

TCVOS

tNote2)

Offset Drift

TCV OSn

INots31

Input Offset Current

los

Input Bias Current

Ie

Input Voltage Range

IVR

Common-Mode
Rejection Aatio
Power Supply
Rejection Ratio

CMRR

VCM == ±lOV

PSRR

Vs == ±4.SV to ± l8V

Large-:-Signal
Voltage Gain

AVO

Output Voltage
Swing

MIN

OP-37B

TYP

MAX

30
0.2

MIN

OP-37C

TYP

MAX

MIN

TYP

MAX

60

50

200

70

300

0.6

0.3

1.3

0.4

1.8

~vrc

UNITS

15

50

22

85

30

135

nA

±20

±60

±28

±95

±35

±150

nA

±10.3

±ll.S

±10.3

±ll.S

±10.2

±11.S

V

108

122

100

119

94

116

dB

16

20

51

~VIV

600

1200

500

1000

300

800

V/mV

±ll.S

±13.S

±11.0

±13.2

±10.5

±13.0

V

ELECTRICAL CHARACTERISTICS for Vs = ±15V. -25°C S TAS +85°C for OP-37EJ/FJ and OP-37EZ1FZ,O°C S TA S +70°C for
OP-37EP/FP and -40°C S TAS +85° for OP-37GPIGStGJ/GZ. unless otherwise noted.
OP-37E
PARAMETER

SYMBOL

Input Offset Voltage

Vos

Average Input

TCVos
TCVoSn

Offset Drift
Input Offset CUrrent

los

Input Bias Current

'a

Input Voltage Range

IVA

Common-Mode
Rejection Aatio
Power Supply
Rejection Ratio

Output Voltage

Swing

(Note3)

PSRR

Vs == ±4.5V to ± l8V

AVO

RL ~ 2kfi, Vo == ±lOV

Vo

MIN

(Note 2)

CMRR

Large-Signal
Voltage Gain

CONOITIONS

MAX

20
0.2

A

MIN

OP-37G

TYP

MAX

MIN

TYP

MAX

50

40

140

55

220

UNITS

0.6

0.3

1.3

0.4

1.8

~VI'C

10

50

14

85

20

135

nA

±14

±60

±18

±95

±25

±150

nA

±10.5

±11.8

±lO.S

±11.8

±10.5

±11.8

V

110

124

102

121

96

118

dB

15

16

32

750

1500

700

1300

450

1000

VlmV

±11.7

±13.6

±11.4

±13.S

±11.0

±13.3

v

NOTES:
1. Input offset voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power. AlE
grades guaranteed fully warmed up.

REV.

OP-37F

TYP

2. The TCVos performance is within the specifications unnulled or when
nulled with R p =8kO to20kO. TCVosis 100%tested for AlE grades. sample
tested for BICIFIG grades.
3. Guaranteed by design.

OPERATIONAL AMPLIFIERS 2-183

•

OP-37
DICE CHARACTERISTICS
DIE SIZE 0.098 x 0.056 Inch, 5488 sq. mils
(2.49 x 1.42 mm, 3.54 sq. mm)

WAFER TEST LIMITS

1.
2.
3.
4.
6.
7.
8.

NULL
(-) INPUT
(+) INPUT
VOUTPUT
V+
NULL

at Vs= ±15V, TA = 25°C for OP-37N, OP-37G and OP-37GR devices; TA= 125°C forOP-37NT and

OP-37GT devices. unless otherwise noted.

PARAMEl1!R

SYMBOL

CONDITIONS

Input Offset Voltage

Vos

(Note 1)

Input Offset Current

los

I nput Bias Current

Ie

Input Voltsge Range

IVR

Common-Mode
Rejection Ratio

CMRR

VcM =±l1V

Power Supply
Rejection Ratio

PSRR

TA =25°C. Vs =±4Vto±18V
TA= 125°C. Vs= ±4.5V to ±18V

Large-Signal
Voltage Gain

"w

RL2: 2kO. Vo= ±10V
RL 2:1kO.Vo =±10V

Output Voltage Swing

Vo

RL 2:2kO
RL 2:8000

Power Consumption

Pd

Vo=O

OP-37NT

OP-37N

OP~37GT

LIMIT

LIMIT

LIMIT

LIMIT

LIMIT

UNITS

60

35

200

60

100

"V MAX

OP-37G OP-37GR

50

35

85

50

75

nAMAX

±60

±4O

±95

±55

±80

nAMAX

±10.3

±11

±10.3

±11

±11

VMIN

108

114

100

106

100

dB MIN

10
16

10

10
20

10

20

800

1000
800

500

1000
800

700

±11.5

±12.0
±10.0

±11.0

±12.0
±10.0

±11.5
±10.0

VMIN

140

170

mWMAX

140

"VNMAX
VlmVMIN

NOTES:
For 25° C characteristics of OP-37NT and OP-37GT devices. see OP-37N and
OP-37G characteristics. respectively.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss. yield after peckaging is not
guaranteed for stsndard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot asembly and testing.

TYPICAL ELECTRICAL CHARACTERISTICS at Vs =

± 15V. TA = +25° C. unless otherwise noted.

OP-37NT
PARAMEl1!R

SYMBOL

CONDITIONS

Average Input Offset
Voltage Drift

TCVosor
TCVoSn

Nulled or Unnulled
Rp= 8kO to 20kO

Average Input Offset
Current Drift

OP-37N OP-37GT

OP-37G OP-37GR

TYPtCAL

TYPICAL

TYPICAL

TYPICAL

TYPICAL

UNITS

0.2

0.2

0.3

0.3

0.4

"vrc

TCl os

80

80

130

130

160

pAloC

Average Input Bias
Current Drift

TCl e

100

100

160

160

200

pAloC

Input Noise
Voltage Density

en

10= 10Hz
10= 30Hz
10= 1000Hz

3.5
3.1
3.0

3.5
3.1
3.0

3.5
3.1
3.0

3.5
3.1
3.0

3.8
3.3
3.2

nVl..[HZ

Input Noise
Current Density

in

10= 10Hz
10= 30Hz
10= 1000Hz

1.7
1.0
0.4

1.7
1.0
0.4

1.7
1.0
0.4

1.7
1.0
0.4

1.7
1.0
0.4

pAl..[HZ
"Vp.p

Input Noise Voltage

ent>-!>

O.lHz to 10Hz

0.08

0.08

0.08

0.08

0.09

Slew Rate

SR

RL2: 2kO

17

17

17

17

17

VI"s

Gain Bandwidth Product

GBW

10= 10kHz

83

83

83

83

83

MHz

NOTE:
1. Input offset voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power.

2-184 OPERATIONAL AMPLIFIERS

REV. A

OP-37
TYPICAL PERFORMANCE CHARACTERISTICS

NOISE-TESTER FREQUENCY
RESPONSE (0.1 Hz TO 10Hz)

A COMPARISON OF
OP AMP VOLTAGE
NOISE SPECTRA

VOLTAGE NOISE DENSITY
VI FREQUENCY
10
9
8

100

10Of-

90

,

1'1..

80 ~H-Irtttltt--++ttttitt

, i'
,
,

r-...

0

I.

LIMIT LOW FREQUENCY «O.lHz) GAIN.

10

l/fCORNER

111111

11111111

III

AUDIO RANGE
TO 20kHz

1

10

1

100

1000

10

FREQUENCY (Hz)

FREQUENCY (Hz)

INPUT WIDEBAND VOLTAGE
NOISE vs BANDWIDTH (0.1Hz
TO FREQUENCY INDICATED)

AMP

--

INSTRUMENTATION
RANGE, TO DC

I

1

100

~ ~",,-OP

~ ~,~37

I

TEST TIME OF 10sec MUST BE USED TO

AUDIO

111 CORNER
2.7HZ,

;; 2.7Hz

•

-

LOW NOISE!

:

I/f CORNER

50

,

ll1CQRNER

60

40

~741

TA = 25°C
Vs = ±15V

1000

100

FREQUENCY (Hz)

TOTAL NOISE vs SOURCE
RESISTANCE

VOLTAGE NOISE DENSITY
VB TEMPERATURE

100 F = 1 = F f = r ! ' f l ' F F = = = = = = R

~TA=25°C

~ ~ __

5V-rl-Htt+f-_ ~
rf-_VS
-j-=_±1t-

~4

1--II-H+l-++eI-- RS 2Rl

~

w

~10~1I

~~

3

-50

r! "

- 25

0

25

50

75

100

125

TEMPERATURE (OC)

SOURCE RESISTANCE 1m

VOLTAGE NOISE DENSITY
VI SUPPLY VOLTAGE

t"==4-+--=..j.o=

~
C;

10k

lk

100

BANOWIDTH (Hz)

-- -

~

g 21--+-+-~-+--~~-~

AT 1kHz

0.01 '---'-J....L.w.1!..1.--1....J....I..I.J..I.lll...--'--L-LJ.J.LW
100
lk
10k
lOOk

~

SUPPLY CURRENT VI
SUPPLY VOLTAGE

CURRENT NOISE DENSITY
VB FREQUENCY

5.0..----..---...,----.---.....,

10.0
25°C

<4.01---+---~---L-~__J

E

AT 10Hz

...

15

"-

AT 1kHz

~ 3.0

:>

"
~

it

~ 2.0 I-~__~--_I_--_+_---I

I--

f-1=1 ' 1i111i

0.1
10

W

~

TOTAL SUPPLY VOLTAGE (V+ - V-I (VOLTS)

REV. A

40

I/f CORNER

10

I

100
lk
FREQUENCY (Hz)

10k

as

15
25
TOTAL SUPPLY VOLTAGE (VOLTSI

45

OPERATIONAL AMPLIFIERS 2-185

OP-37
TYPICAL PERFORMANCE CHARACTERISTICS
OFFSET VOLTAGE DRIFT OF
EIGHT REPRESENTATIVE
UNITS YS TEMPERATURE
60

40

~

20

~

~

-

,/

LONG-TERM OFFSET
VOLTAGE DRIFT OF SIX
REPRESENTATIVE UNITS

OP-31C

/ ' OP-378

/ ' ,.,
,., """K '"
".

.....

i-"'"

"..

~ 2
w

OPfA

"~

OP-378

i5 ..

I-

I

g
~

...... r-

~

TRIMMING WITH"
10k POT ~OES
NOT CHANGE

T~VOSI

-60

I

......
......

0

25

50

75

30

J

~

0

-6

o

20

2S°C

15

f--

ij!3O
a:

~II
THERMAt:---L
RESPONSE

1'0 f - ~

f--

BAND

~

/1' I I I I

If I I I I I
20

40

i'

10

80

OPEN-LOOP GAIN
FREQUENCY

-50

100

-25

~'00
w

~

~
>

§
ffi

i!;

75

RL ;;. 2kn

70

65
60

I\.

80

55
30

~
;;'25

\.

40

JJ---.;

I--

OP-37C

~I\.

,~ ~ ['.. r-

OP-378

4il

--

0
25 50
75
TEMPERATURE r»CI

100

125

150

-75 -50

-25

OP-'S/B

f-.,.:

OP~7A

0

25

50

(/)M

50

.......

--

100

125

GAIN, PHASE SHIFT YI
FREQUENCY
60

VS ,.'±15V

75

TEMPERATURE fC)

80

T}' +Jc

I\.

80

50

SLEW RATE, GAIN BANDWIDTH
PRODUCT, PHASE MARGIN YI
TEMPERATURE

YS

VS:l ±16V _

r'\.

INPUT OFFSET CURRENT
YI TEMPERATURE

II I

TIME (SEC)

~ 120

TIME AFTER POWER ON (MINUTES)

OP-37C

o

60

140

V

QP-37A

IN 700C OIL BATH

o·

-20

1,\

~ DEVICE IMMERSED

0

OP-zlA/E

Vs = ±15V

"" \ \ 1\
~20
" "- r-. r--I--

SHOCK

r--

i-"""

II

2

I I I I

o

-

IIII

40

~

I-

I-

r-

50

.1
TA "

-

OP-:JBlF

VV-

INPUT BIAS CURRENT
YS TEMPERATURE

TA -70"C

V .... ,..-

/

TIME (MONTHS)

V~'±\5VI-

I I I I

~ 25

g
I-

.......,

rei

I I

j

r--..

-2

OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK

w

«~

,/"
~

-4

OP-37C

VS=±15V

OP-37C/G

6

100 125 150 175

TEMPERATURE

~

is

Tl. +25.)

r-

·6

~
w

II"

I
I

......

I

-75 -50 -25

~

o

OP-318

-40

~

~

OP-37A

r"'"

-20

10

-2

OP-'S/A

>

.--

~

h""

0

WARM-UP OFFSET
VOLTAGE DRIFT

v.I.

~

40

~,l.!."

-100

TA = +25"c

~

r-~

-120
PHASE

30

r--- .::.,w

"\

-140

MARGIN
= 71°

-160

20

---..

AV" 5

-180

10

w

I\.

20

SLEW

<20

a:

\

~

-200

15

.. 10

10

102

10"

104

105

10"

107

loB

FREQUENCY (Hz)

2-186 OPERATIONAL AMPLIFIERS

-so

40
-25

+75
+25 +50
TEMPERATURE (OCI

+100

+125

-10
lOOk

-220
1M

10M

100M

FREQUENCY 1Hz)

REV. A

OP-37
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN-LOOP VOLTAGE GAIN
vs SUPPLY VOLTAGE

I

2.

5

2B

yk"

2.o f--TA = 25°C
/'

Rl=lkH

./ . / -

5

~

24

;

20

T A '"

16

:ZSOe

14

- POsllTIJe

12

-

"

2

~

4

r--o

0.0

30

20

/.
(/

B

""

0.5

TA'" 25°C
Vs = ±15V

I III

2

104

50

40

•

NEGATIVE

12

~

~
SWING

~

"II!

~

SWING

10

~ 18

,V
10

lB

vsl.I.).~1

g

~/

0

MAXIMUM OUTPUT VOLTAGE
VB LOAD RESISTANCE

MAXIMUM OUTPUT SWING
VB FREQUENCY

105

TOTAL SUPPLY VOLTAGE (VOLIS)

100

106

SMALL-SIGNAL OVERSHOOT
vs CAPACITIVE LOAD

1k

10k

LOAD RESISTANCE (m

FREQUENCY (Hz:)

LARGE-SIGNAL TRANSIENT
RESPONSE

SMALL-SIGNAL TRANSIENT
RESPONSE

80
Vs = ±15V
VIN =2DmV
AV = +5 (1kn, 2500)

60

/

40

V

+50mV

. /~

+10V

L

20

ov

ov

-10V

-5

omV

AV = +5 (lkn. 250n)
TA = +2So C

TA =+25"C

o

o

500

1000

1500

iiii
Vs = ±16V

Vs = ±15V
AV" +5 (lkn, 250m

2000

CAPACITIVE LOAD (pF)

SHORT-CIRCUIT CURRENT
vsTIME
60

140

I":

TA = +25 0
Vs = ±1SV

r-:SC~L'

16r---r---,----r~~~

IJ!I~I±1U I

120

I\..

COMMON-MODE INPUT RANGE
vs SUPPLY VOLTAGE

CMRR VB FREQUENCY

TA = +2SOC

.....

~

V CM '" ±10V

~ 8
t\l 4 I---W'S"'''--+--+----I

100

~w

i -41--~~~~+--+----I

r\

BO

lse lt )

~

60

0

121---+--

01--.£.1---+--+----1

-B

-12r---1---f-~~~~-_i
10

i

o

TIME FROM OUTPUT SHORTED TO GROUND (MINUTES)

REV. A

-16 L..--'---,-':---~~:..:...~±20

40
1k

10k

lOOk

1M

10M

FREQUENCY 1Hz)

OPERATIONAL AMPLIFIERS 2-187

OP-37
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN-LOOP VOLTAGE GAIN
VB LOAD RESISTANCE

LOW-FREQUENCY NOISE

NOISE TEST CIRCUIT (0.1 Hz TO 10Hz)

2.4
O.1pF

120

lOOk"

;;

~

80

~

2.0

ill

40

~

1.8

(5

.'"'"

-40

!:i

t-"f-'>Nv-1

g

::~I21;.:'El~i!

-

IT~.IJ!bll

_

VS =±15V

/

~ :::

2

",n

2.2

~
8~

-60
-120

1.2
1,0

~ 0.8

i"~n

O.1Hz TO 10Hz PEAK-TO-PEAK NOISE

0••

NOTE:
Observation time limited to 10 seconds.

":" -=
NOTE: ALL CAPACITOR VALUES ARE FOR

lk

10k

lOOk

LOAD RESISTANCE In)

NON-POLARIZED CAPACITORS ONL V.

PSRR VI FREQUENCY
160

~1~
o
~ 120 -

..t5

100

~

8

TAl.

18

~,

. O-POsITI~
..

SLEW RATE
vs SUPPLY VOLTAGE

SLEW RATE VB LOAD
20

U~WJII

TA

=

125'C

AVCL ., +5

VS· :t15V

~'

i

25'~-

,.
I--

~

60

40

~

~ 20

~

0
100

lk

10k

lOOk

#~

~

;:::::;

fALL

,

NEGATIVE

~UPPLV

SUPPLY

10

15

AV'" +5
VO·2OVp-p

~

,.
~

1M

10M 100M

FREQUENCY (Hz)

15
1110

V
lk

APPLICATIONS INFORMATION
OP-37 Series units may be inserted directly into 725, OP-06,
OP-07, and OP-05 sockets with or without removal of external
compensation or nulling components, Additionally, the OP37 may be fitted to unnulled 741-type sockets; however, if
conventional 741 nulling circuitry is in use, it should be modified or removed to ensure correct OP-37 operation. OP-37
offset voltage may be nulled to zero (or other desired setting)
using a potentiometer (see offset nulling circuit).
The OP-37 provides stable operation with load capacitances
of up to 1000pF and ± 10V swings; larger capacitances should
be decoupled with a 500 resistor inside the feedback loop.
Closed-loop gain must be at least five. For closed-loop gain
between five to ten, the designer should consider both the
OP-27 and the OP-37. For gains above ten, the OP-37 has a
clear advantage over the unity-gain-stable OP-27.
Thermoelectric voltages generated by dissimilar metals at
the input terminal contacts can degrade the drift performance. Best operation will be obtained when both input
contacts are maintained at the same temperature.

2-188 OPERATIONAL AMPLIFIERS

10k

LOAD RESISTANCE

lOOk

o±3

en)

±6

±9

±12

±15

t18

±21

SUPPLY VOLTAGE (VOLTS)

OFFSET NULLING CIRCUIT

>...,...-'----ov+
>7"':6'-_-0 OUTPUT

OFFSET VOLTAGE ADJUSTMENT
The input offset voltage of the OP-37 is trimmed at wafer
level. However, if further adjustment of Vos is necessary, a
10kO trim potentiometer may be used. TCVes is not degraded
(see offset nulling circuit). Other potentiometer values from
1kO to 1MO can be used with a slight degradation (0.1 to
0.21JVlo C) of TCVes. Trimming to a value other than zero
creates a drift of approximately (Ves/300) IJVlo C. For exam-

REV. A

OP-37
pie, the change in TCVos will be 0.33,.Vlo C if Vas is adjusted
to 100,.V. The offset-voltage adjustment range with a 10kO
potentiometer is ±4mV. If smaller adjustment range is required, the nulling sensitivity can be reduced by using a
smaller pot in conjunction with fixed resistors. For example,
the network below will have a ±280,.V adjustment range.

4.7k!!

lki! POT

4.7kH

INSTRUMENTATION AMPLIFIER
A three-op-amp instrumentation amplifier provides high gain
and wide bandwidth. The input noise of the circuit below is
4.9nVly"HZ. The gain of the input stage is set at 25 and the
gain of the second stage is 40; overall gain is 1000. The
amplifier bandwidth of 800kHz is extraordinarily good for a
preCision instrumentation amplifier. Set to a gain of 1000, this
yields a gain-bandwidth product of 800M Hz. The full-power
bandwidth for a 20Vp _p output is 250kHz. Potentiometer R7
provides quadrature trimming to optimize the instrumentation amplifier's AC common-mode rejection.

BURN-IN CIRCUIT

NOISE MEASUREMENTS

(1) The device has to be warmed-up for at least five minutes.
As shown in the warm-up drift curve, the offset voltage
typically changes 4,.V due to increasing chip temperature after power-up. In the 10 second measurement interval, these temperature-induced effects can exceed tensof- nanovolts.

(3) Sudden motion in the vicinity of the device can also "feedthrough" to increase the observed noise.
(4) The testtime to measure 0.1 Hz-to-l0Hz noise should not
exceed 10 seconds. As shown in the noise-tester frequency response curve, the O.lHz corner is defined by
only one zero. The test time of 10 seconds acts as an
additional zero to eliminate noise contributions from the
frequency band below 0.1 Hz.
(5) A noise-voltage-density test is recommended when
measuring noise on a large number of units. A 10Hz
noise-voltage-density measurement will correlate well
with a 0.1 Hz-to-l0Hz peak-to-peak noise reading, since
both results are determined by the white noise and the
location of the 1If corner frequency.
OPTIMIZING LINEARITY
Best linearity will be obtained by designing for the minimum
output current required for the application. High gain and
excellent linearity can be achieved by operating the op amp
with a peak output current of less than ± 10mA.

REV. A

RS

R8
20k!! 0.1%

R6
600n 0.1%

R9
19.8kH

• TRIM R2 FOR AVCL = 1000
_TRIM R10 FOR de CMRR
-TRIM R7 FOR MINIMUM VOUT
AT VCM = 20V p_p, 10KHz

To measure the 80nV peak-to-peak noise specification ofthe
OP-37 in the 0.1 Hz to 10Hz range, the following precautions
must be observed:

(2) For similar reasons, the device has to be well-shielded
from air currents. Shielding minimizes thermocouple
effects.

soon 0.1%

140

Il~J

120

I"-

~ 100

a:
a:

ii

RIO

soon

~

~

I'

RS = lOOll.80 lkn UNBALANCED

IIIII I 1111

I'

~

10k

lOOk

TA = +25°C
60

AS = 1kil,

Vs = :t15V
VCM = 2OVp-p

AC TRIM @I 10KHz, RS = 0

40
10

100

lk

BALANCED

I'
1M

FREQUENCY (Hz)

COMMENTS ON NOISE
The OP-37 is a very low-noise monolithic op amp. The outstanding input voltage noise characteristics ofthe OP-37 are
achieved mainly by operating the input stage at a high quiescent current. The input bias and offset currents, which would
normally increase, are held to reasonable values by the inputbias-current cancellation circuit. The OP-37 AlE has 18 and
los of only ±40nA and 35nA respectively at 25°C. This is
particularly important when the input has a high sourceresistance. In addition, many audio amplifier designers

OPERATIONAL AMPLIFIERS 2-189

2

OP-37
10Hz NOISE vs
SOURCE RESISTANCE
(INCLUDES RESISTOR NOISE)

NOISE vs SOURCE RESISTANCE
(INCLUDING RESISTOR NOISE)
AT 1000Hz
100

100

50

50

~~

OP-08I108

0

~

~..,J

.,./"

OP-(JaI108

,

'/

,/

Ul-07
5534

1 RSUNMATCHED

1 RS UNMATCHED

5534

•. g.RrRs,·lOk,AS2oo(1

OP-27137...

a.g.Rs=lOk,RS'=Rs2-sk

• .. Rs-Rsl-10k,Rs2000

2 RSMATCHED

1¢>
'S2

~~SISTOR
NOISE ONLY
1
50

100

SOO

2 RSMATCHED

lk

5k

50.

10k

Figure 3

500

OP-08/108

III

100

~

IIII

V

I-'

OP-27/':f1

50

1 RS UNMATCHED

e.g.RrAS1·'Ok.Rs2000
2 RSMATCHED
•. g.Rs=lOk,RS,"'R$2=5k

~~::Ig:~
10
50 100

Figure 2

6k

10k

Therefore, for low-frequency applications, the OP-07 is better than the OP-27/37 when Rs> 3kO. The only exception is
when gain error is important. Figure 3 illustrates the 10Hz
noise. As expected, the results are between the previous two
figures.

.~.
'U

600 1k
5k 10k
RS - SOURCE RESISTANCE (n)

For reference, typical source resistances of some signal
sources are listed in Table 1.

prefer to use direct coupling. The high IB' TCVos of previous
designs have made direct coupling difficult, if not impossible,
to use.
Voltage noise is inversely proportional to the square-root of
bias current, but current noise is proportional to the squareroot of bias current. The OP-37's noise advantage disappears
when high source-resistors are used. Figures 1, 2, and 3
compare OP-37 observed total noise with the noise performance of other devices in different circuit applications.
Total noise = [(Voltage noise)2
(resistor noise2 ] 1/2

500 lk

Rs" SOURCE RESISTANCE em

Figure 2 shows the 0.1 Hz-to-10Hz peak-to-peak noise. Here
the picture is less favorable; resistor noise is negligible, current noise becomes important because it is inversely proportional to the square-root of frequency. The crossover with the
OP-07 occurs in the 3-to 5kO range depending on whether
balanced or unbalanced source resistors are used (at3kO the
IB' los error also can be three times the Vos spec.).

..3.

or,;'"

100

beyond Rs of 20kO that current noise starts to dominate. The
argument can be made that current noise is not importantfor
applications with low-to-moderate source resistances. The
crossover between the OP-37 and OP-07 and op-oa noise
occurs in the 15-to-40kO region.

PEAK-TO-PEAK NOISE (0.1 to
10Hz) vs SOURCE RESISTANCE
(INCLUDES RESISTOR NOISE)

,.

I.g.Rr1Ok,Rs1- Rsr5k

RESISTOR

1
50

RS - SOURCE RESISTANCE 1m

Figure 1

l27r~
Vii
jOllSlwtJ ~
f-

+ (current

noise

DEVICE

SOURCE
IMPEDANCE

At Rs 10)
OP-61 I

~ANALOG

WDEVICES

FEATURES
• High Gain-Bandwidth Product ...................... 200M Hz Typ
• Low Voltage Noise .......•..•.....•..•........•. 3.4nV/ v'Hi @ 1kHz
• High Speed ........................................................ 45V/!'s Typ
• Fast Settling Time (0.01 %) ........................•.•..... 330ns Typ
• High Gain ....................................................... 475V/mV Typ
• Low Offset Voltage ............................................ 1OO!,V Typ

much larger gain-bandwith product of 200M Hz. With slew rate
exceeding 45V/!'s, and settling time for 12 bits (0.01%) typically
330ns, the OP-61 has excellent dynamic accuracy.
The OP-61 is an excellent upgrade for circuits using slower op
amps such as the HA-5111, and the HA-5147. The OP-61 can
also be used as a high-speed alternative to the HA-51 01, HA5127, HA-5137, OP-27, and OP-37 amplifiers, where closedloop gains are greater than 10.

APPLICATIONS
• Low Noise Preamplifier
• Wideband Signal Conditioning
• Pulse/RF Amplifiers
• Wideband Instrumentation Amplifiers
• Active Filters
• Fast Summing Amplifiers

PIN CONNECTIONS

GENERAL DESCRIPTION
The OP-61 is a wide-bandwidth, precision operational amplifier
designed to meet the requirements of fast, precision instrumentation systems. The OP-61 's combination of DC accuracy with
high bandwidth, fast slew rate and low noise, makes it unique
among high-speed amplifiers. It is ideal for wide band systems
requiring high signal-to-noise ratio, such as fast 12-16 bit data
acquisition systems. The OP-61 maintains less than 3nV/VHz
of input referred spot voltage noise over its closed-loop bandwidth.

OP-61 ARC/883
20-CONTACT LCC
(RC-Suffix)

EPOXY MINI-DIP
(P-Suffix)
8-PIN CERDIP (Z-Suffix)
8-PIN SO (S-Suffix)

The OP-61 offers noise and gain performance similar to that of
the industry standard OP-27/37 amplifiers, but maintains a

+15V

O.1p.F

q.

V ,N

,." I

VOUT

YoUT

15p'
Io\N

900"
Av

=+10

-15V

REV. A

OPERATIONAL AMPLIFIERS 2-193

2

OP-61
ORDERING INFORMATION t

Storage Temperature Range
P, RC, S, Z Package ____________________________________ -65°C to +150°C

PACKAGE
CERDIP
8-PIN
OP6IAZ·
OP61FZ

PLASTIC

LCC

8-PIN

2O-CONTACT

OPERATING
TEMPERATURE
RANGE

OP6IARC/883·

Lead Temperature Range (Soldering, 60 sec) _______________ 300°C
Junction Temperature (Tj) ______________________________________________ 150°C
Operating Temperature Range
All A Grades ________________________________________________ -55°C to + 125°C
F & G Grades _________________________________________________ -40°C to +85°C

Mil
XIND
XIND

OP61GP
OP61GS

For devices processed in total compliance to Mll-STD-883, add 1883 after part
number_ Consult factory for 883 data sheet
Burn-in is available on commercial and industrial temperature range parts in
CerDIP, and plastic DIP packages_

alc

UNIT

8-Pln Hermetic DIP (ZI

PACKAGE TYPE

148

16

°efW

8-Pin Plastic DIP (P)

103

43

°efW

20-Contact LCC (RC)

98

38

°CfW

158

43

°CfW

alA (Note I)

8-PinSO (S)

ABSOLUTE MAXIMUM RATINGS (Note 2)
Supply Voltage _________________________________________________________________ ±18V
Differential Input Voltage _________________________________________________ ±5_0V
Input Voltage ____________________________________________________ Supply Voltage
Output Short-Circuit Duration _________________________________ Continuous

ELECTRICAL CHARACTERISTICS
PARAMETER

SYMBOL

Input Offset Voltage

Vos

Input Offset Current

los

Input Bias Current

Ie

at Vs

NOTES:
1_ ajA is specified for worst case mounting conditions, i.e., aiA is specified for
device in socket for CerDIP, P-DlP, and lCC packages; alA is specified for
device soldered to printed circuit board for SOpackage.
2. Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.

= ±15V, T A = 25°C, unless otherwise noted_

CONDITIONS

MIN

OP·61 A
TYP
MAX

OP·61F
MIN

op·61G

TYP

MAX

MIN

TYP

MAX

UNITS

750

~V

nA

100

500

150

200

1000

VCM=OV

30

150

40

200

40

200

VCM=OV

130

500

200

600

200

600

nA

3.4

3.4

-

nV/v'Hz

1.7

1.7

-

pNv'Hz

Input Noise
Voltage Density

en

fo= 1000Hz

3.4

Input Noise
Current Density

in

fo = 10kHz

1.7

Input Voltage Range

IVR

(Note I)

Common-Mode
Rejection

CMR

VCM=±I1V

Power Supply
Rejection Ratio

PSRR

Vs=±5Vto±18V

±11.0
100

±11.0
108

1.2

RL=IOkO
RL=2kQ
RL=lkO

225
200
150

475
400

94

4.0

±11.0
100

2.0

94

5.6

V
100

2.0

dB
5.6

~VN

425
350
300

175
ISO
120

425
350
300

V/mV

340

175
ISO
120

V

large-Signal
Voltage Gain

Avo

Output Voltage
Swing

Vo

RL=lkQ
RL =500Q

±12.0
±11.0

±13.2
±12.8

±12.0
±11.0

±13.2
±12.8

±12.0
±11.0

±13.2
±12.8

Slew Rate

SR

RL=lkQ
CL=50pF

40

45

35

45

35

45

VI~s

Gain Bandwidlh Prod.

GBWP

fo= IMHz

200

200

MHz

SettlingTime

ts

Av = -10, 10V Step, 0.01%

300

Isy

No load

6.1

Supply Current

200
330
7.5

6.1

330
7.5

6.1

ns
7.5

rnA

NOTES:
I. Guaranteed by CMR test

2-194 OPERATIONAL AMPLIFIERS

REV_A

OP-61
ELECTRICAL CHARACTERISTICS atV s =:l:15V, -55°C .:TA': +125°C, unless otherwise noted.
OP-61A
PARAMETER

SYMBOL

TYP

MAX

UNITS

Input Offset Voltage

Vas

200

1000

"V

Average Input
Offset Drilt

TCVos

1.0

5.0

"V/oC

CONDITIONS

MIN

Input Offset Current

los

VCM = OV

70

400

nA

Input Bias Current

18

VCM=OV

180

800

nA

Input Voltage Range

IVR

(Note 1)

Common-Mode
Rejection

CMR

V CM ="I1V

Power Supply
Rejection Ratio

PSRR

Vs =,,5Vto,,18V

Large-Signal
Voltage Gain

Ava

RL = 10ka
RL = 2kQ
RL = lkQ

175
150
120

340
260

Outpul Voltage
Swing

RL a lkQ
RL = 500a

,,11.0

.13.0

Va

.10.0

.12.7

Supply Current

ISY

No Load

,,11V

V
104

94

dB

5.6

2.0

!'-VN

400
V/mV

V
8.0

6.5

rnA

ELECTRICAL CHARACTERISTICS at Vs = :l:15V, -40°C .: T A .: +85°C.
OP-61G

OP·61F
PARAMETER

SYMBOL

Input Offset Voltage

Vas

Average Input
Offset Drilt

TCVos

CONDITIONS

MIN

TYP

MAX

TYP

MAX

UNITS

300

1250

400

1500

!'-V

3.0

7.0

3.0

7.0

"woC

MIN

Input Offset Current

los

V CM = OV

125

500

125

500

nA

Input Bias Current

18

VCM=OV

250

900

250

900

nA

Input Voltage Range

IVR

(Note I)

Common-Mode
Rejection

CMR

V CM = "l1V

PSRR

Vs = ,,5Vto.18V

Large-Signal
Voltage Gain

Ava

RL = 10kQ
RL =2kQ
RL = lkQ

150
120
100

350
300
240

150
120

Output Voltage
Swing

Va

RL = lkQ
RL = 500n

,,11.0
,,10.0

.13.0
,,12.7

Supply Current

ISY

No Load

Power Supply
Rejection Ratio

88

V

:t.11V

"IIV

88

96

4.0

6.4

10.0

8.0

dB

96

4.0

10.0

"VN

V/mV

100

350
300
240

.11.0
.10.0

,,13.0
,,12.7

V

6.4

8.0

rnA

NOTES:
1. Guaranteed by CMR test.

REV. A

OPERATIONAL AMPLIFIERS 2-195

•

OP-Sl
DICE CHARACTERISTICS

1. VOSNULL
2. -IN
3. +IN
4.
5.
6.
7.

VVosNULL
OUT
V+

DIE SIZE 0.064 x 0.068 Inch, 4,352 sq. mils
(1.63 x1.73 mm,2.81 sq.mm)

WAFER TEST LIMITS atVs=±15V, TA = 25°C.
OP-61GBC
PARAMETER

SYMBOL

Input Offset Vollage

Vos

CONDITIONS

LIMITS

UNITS

750

~VMAX

Input Offset Current

los

200

nAMAX

Input Bias Current

18

600

nAMAX

Input Voltage Range

IVR

±11.0

VMIN

Common-Mode
Rejection

CMR'

94

dBMIN

Power Supply
Rejection Ratio

PSRR

Vs=±5Vto±18V

5.6

~VIVMAX

Large-Signal
Voltage Gain

Avo

RL = tOkQ
RL=2kQ
RL=lkQ

175
150
120

VlmVMIN

Output Voltage Swing

Vo

RL=lkQ
RL= 500Q

±12.0
±11.0

VMIN

Slew Rate

SR

RL=lkQ
CL=50pF

35

Supply Current

Isv

No load

7.5

V/~s

MIN

mAMAX

NOTE:
Electrical tests are performed at wafer probe to the limits shown, Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for
standard product dice, Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

2-196 OPERATIONAL AMPLIFIERS

REV. A

OP-Sl
TYPICAL PERFORMANCE CHARACTERISTICS

OPEN·LOOP GAIN,
PHASEvsFREQUENCY

".
;i
~

z

.

3

00

~

40

I!i

~
0

.

"""

TA .2S"C
Vs _1:15V
RL.,2ka

'00

r-

(

GAIN

PHASE

DO

....

'35

·ii,~~

....

..

!

100k

1M

m
a:
~ '~"

4S

if

40

=

22.

35

_

'oou

'OM

'>< ......

if

~

~

+. I-- I--

'00

,..

i'- r-....
2S

~

so

r- ".

n

~
g

~
~z

~
3

..
!. ,.

~.~
'Is

:O:l:15V
AL .. 2kQ

I

1.:l!~I!,~

~~

111111111

3.

~

~~~I~,.I

l\

,.

,;

•,.

WIDEBAND PEAK·TO·PEAK
VOLTAGE NOISE

'Ok

100k

,.u

1M

CURRENT NOISE DENSITY
vsFREQUENCY

'00

l~ll.1,~!JI

T" _+25"C

\Is ....15Y
Rs ·1kO

Vs .:t.15V

30

•

1\

~

FREQUENCY (Hz)

~

.....

i

2S

.iii
~

I" ,.
z
~

""
~

ISO IIIIIII~

m 100

~

20

III0

~

~:!I~,rr

ao

TEMPERATURE .-«:)

FREQUENCV (H:r:)

VOLTAGE NOISE DENSITY
vs FREQUENCY

3.

~

11111

,

tk

,ao

I

,.:c
t;

iiig so

45

,.

,ao

CLOSED·LOOP GAIN
vs FREQUENCY

7.

'00

.~'5V

Vs
A L -2kO

55

i'

"-

GAIN·BANDWIDTH PRODUCT,
PHASE MARGIN
vs TEMPERATURE

"
~

,. \

,.

....

z

~

a:
a:
u

BANDWIDTH: 1kHz TO 100kHz

TA

=+25·C

"

'Is =:l:.15V

•,.

100

111
10k
FREQUENCY (Hz)

,,.

,u

100k

-,., -

Va '" :l:15V

ALana
CL. SOpF

00

/

COMMON·MODE REJECTION
VB FREQUENCY
'40

!

IJsW,1

T••

Va _:l:15V

'20

.,1;1

~

~

2S

~

TEMPERATURE rC)

REV. A

~

~ll..~~h'
'Is

z

'00

iil
a:

00

0

1I ...

15V

.....

....

.g .
"'" ••

+PSR

-PSA

~

z

0

8'"

20

20

_

...

~

30

_

POWER SUPPLY REJECTION
VB FREQUENCY

'20

;

;i

V

20

'Ok

1k

FREQUENCY (Hz)

SLEW RATE VB
TEMPERATURE
70

tOO

_

m

o

,.

10k

tOOk
FREQUENCY (Hz)

1M

,ou

,.

100

111

10k

100k

,u

FREQUENCY (Hz)

OPERATIONAL AMPLIFIERS 2-197

OP-61
TYPICAL PERFORMANCE CHARACTERISTICS

Continued

CLOSED-LOOP OUTPUT
IMPEDANCE V$ FREQUENCY

MAXIMUM OUTPUT SWING
vs FREQUENCY

'"

BOO

T~; ;~;!~

.
..

TYPICAL DISTRIBUTION OF
INPUT OFFSET VOLTAGE
700

Va =:l:15V

T.I.~!C

19QOUNITS
FROM 3 RUNS_

~

Vs =:l:15V

600
500

-

400
40

300

AvCL " 1000

AvCl " 100-

AVCL=10~

20

o
1k

10k

TYPICAL DISTRIBUTION
OF TCVOS

to-

o

1M

10M

-1.0 -0.8 -0.6 -0.4 -0.2

VCM

= DV

,

80

100

'-

150

'r---..

60

100

o

~
\

60

r--.. t-- r-

[\.

40

~

o

0.5

1.0

1,5

2.0

2.

50

o_

2.5

3.0

3.5

4.0

4.5

_

_

~

50

= rn

n

5.0

TEMPERATURE

TCVos(tLV;eCj

SUPPLY CURRENT
vs TEMPERATURE

--a

0

re)

•
_

COMMON-MODE REJECTION
vs TEMPERATURE

= :l:1SV

Vs = :l:15V
VCM = :tt1V

I--

j....--" V

"z
0

~

110

w

105

~

t-..

~I'--

0

_

0

~

60

TEMPERATURE

n

m

rn

re)

r-

.~. '.0

1.0

os

0.5

2-198 OPERA TlONAL AMPLIFIERS

.

-75

~

-

~

m

rei

Vs R:t5VTO;l;18V

0

_

r50

2.0

l"- t--

0

3_

~

2.5

a

u

_

POWER SUPPLY REJECTION
RATIO vs TEMPERATURE

115

l..- +--

1.0

3.0

NO L.OAD

iD

_

,

TEMPERATURE

120

Vs

0.8

VCM",OV

i-

.....

0.6

~S. "lsV

Vs" :t15V

200

20

0.4

100

250

d15 ullTS I

40

0.2

INPUT OFFSET CURRENT
vs TEMPERATURE

300

FROM 3 RUNS

..

0

INPUT OFFseT VOLTAGE (mY)

INPUT BIAS CURRENT
vs TEMPERATURE

v;. ,'~V

l-

140
120

tOOk

.....

10-

100

FREQUENCY (Hz)

FREQUENCY (Hz)

160

UIt1I

200

It>'
I'>

-50

-25

0
25
50
75
TEMPERATURE rei

100

125

o
-75

,.,.
-so

-25

~

V

i-"""

J....-"

25
50
75
TEMPERATURE re)

V

100

125

REV. A

OP-61
TYPICAL PERFORMANCE CHARACTERISTICS Continued

500

z

~

vs SUPPLY VOLTAGE

20

B••

V, _.t15V

!

SUPPLY CURRENT

OUTPUT VOLTAGE SWING
vs SUPPLY VOLTAGE

OPEN·LOOP GAIN

vs TEMPERATURE
600

i-

R L =10kC

r

'00

Ae • 2]

@;

RL=1kD../

S300

~

---

NO LOAD

TA _.2S-C
R l _1kO

"

r-.... ........
r- t--

pos,/

V

./

"

..............

............ ......

-50

-25

25

50

75

100

.... •

125

TEMPERATURE ("C)

OPEN·LOOP GAIN
vs SUPPLY VOLTAGE
500

..

.,.

.5

T.... +25·C
R L .. 2kn

/

i

6.0

i!l

5.5

....

.,.

.m"

/'

u

5
~

"
"ri

0

t:

Ii;

2.

ili

200

o

."

.5

"0
SUPPLY VOLTAGE (VOLTS)

.20

.. ,...

SINK

-

V, "':e-15V

[450
~

...

TAI.i~CI

lO:l:t5V_

........ r-..

,.
•

SUPPLY VOLTAGE (VOLTS)

OPEN·LOOP GAIN

SOURCE

r-.....
....

.,. ."

.5

vs LOAD RESISTANCE
500

........

~

-5...........

550

50

U

...

SHORT CIRCUIT
OUTPUT CURRENT
vs JUNCTION TEMPERATURE

eo

30

0

250

70

~

'.5

.20

II

~ ~- I-

... •

SUPPLY VOLTAGE

\Is

+2!rC

7••

!§

'00

...

a

i ~5

NEGATIVE

-,.

-75

~

r--

200

'00

"

u

"V

TA

7.'

~

@;

I

~

'00

3'.

/

300

2,.
200

~

•
~
50
~
JUNCTION TEMPERATURE rC)

~

~

'00

1k

10k

'OOk

LOAD RESISTANCE (0)

MAXIMUM OUTPUT VOLTAGE
vs LOAD RESISTANCE

,.

BURN·IN CIRCUIT

T•• ;2'.ri
VI =.t15V

"

.'BY

/

.VOM-I-VOMI

/
-'BY
o
'DO

,.

'Ok

LOAD RESISTANCE (a)

REV. A

OPERATIONAL AMPLIFIERS 2-199

OP-61
SIMPLIFIED SCHEMATIC
NULL

NULL

r-~------'--------r~~------~~------------~r-~~-------oV+

+INo----I::.

OUT

L-----------~--~------~~~--~~------~----__o

APPLICATIONS INFORMATION
The OP-61 combines high speed with a level of precision and noise
performance normally only found with slower amplifiers. Data
acquisition and instrumentation technology has progressed to
where dynamic accuracy and high resolution are both maintained
to a very high level. The OP-61 was specifically designed to meet
the stringent requirements of these systems.

to any op amp are simply another set of sensitive differentially
balanced inputs. Therefore, care must always be exercised in
laying out signal paths by not placing the trimmer, or the nulling
input lines, directly adjacent to high frequency signal lines.

+V
O.1J.1F

Signal-to-noise ratio degrades as input referred noise or bandwidth increases. The OP-61 has a very wide bandwidth, but its
input noise is only 3nV/,(RZ. This makes the total noise generated over its closed-loop bandwidth considerably less than
previously available wideband operational amplifiers.
The OP-61 provides stable operation in closed-loop gain configurations of 10 or more. Large load capacitances should be
decoupled with a resistor placed inside the feedback loop (see
Driving Large Capacitive Loads).
OFFSET VOLTAGE ADJUSTMENT
Offset voltage can be adjusted by a potentiometer of 10kn to
100kn resistance. This potentiometer should be connected between pins 1 and 5 with the wiper connected directly to the OP-61
V+ pin (see Figure 1). By connecting this line directly to the op
amp V+ terminal, common impedance paths shared by both
return currents and the null inputs will be avoided. Nulling inputs

2-200 OPERA TIONAL AMPLIFIERS

V-

~

vos

ADJUST

-v

POTENTIOMETERS RANGING FROM 10ku TO 100kU
CAN BE USED TO OBTAIN A MINIMUM OF ±2mV OF
Vos ADJUSTMENT.

FIGURE 1: Input Offset Voltage Nulling

REV. A

OP-61
O.1",F

+v

+v

~
10.000v

REF·10

•

GND

-v
At
7SkQ

DACA

A.
150kQ

'k..

• k..

+v
DACB

.
DAce

OTHER OUTPUTS
AVAILABLE FOR
OTHER FUNCTIONS

,.
DB,
7

(MSB)

DAeD

DIGITAL

CONTROL

FIGURE 2: Trimming OP-61 Voltage Offset with 0 to 10V Voltage Output, PM-7226 Quad D/A
D/A converters can also be used for offset adjustments in systems that are microprocessor controlled. Figure 2 illustrates a
PM-7226 quad, 8-bit D/A, used to null the OP-61's offset voltage. A stable fixed bias current is provided into pin 5 of the OP61, from R2 , and a REF-1 0, +1 OV precision voltage reference.
Current through R" from the D/A voltage output provides the
programmed V0 s adjustment control. Symmetric control of the
offset adjustment is effected since equal currents are sourced
into R, and R2 when the D/A is at half scale, binary input code =
10000000.
With the circuit components shown in Figure 2, the maximum
Vos adjustment range is ±500mV, referred to the input of the
OP-61. Incremental adjustment range is approximately 21lV per
bit, allowing Vos to be trimmed to ±2IlV.

REV. A

SpF

FIGURE 3: Large- and Small-Signal Response Test Circuit

OPERA TIONAL AMPLIFIERS 2-201

OP-61
TRANSIENT RESPONSE PERFORMANCE
Figures 4 and 5, respectively, show the small·signal and largesignal transient response of the OP-61 driving a 20pF load from
the circuit in Figure 3. Both waveforms are symmetric and exhibit
only minimal overshoot. The slew rate symmetry, apparent from
the large-signal response, decreases the DC offsets that occur
when processing input signals that extend outside the range of
the OP-61 's full-power bandwidth.

V,N

C LOAD

20pF

r'OOOpF

. R.

'00"
FIGURE 6: OP-61 Noninverling Gain of 10 Amplifier,
Compensated to Handle Large Capacitive Loads
FIGURE 4: Small-Signal Transient Response
thereby preserving adequate phase margin. The resulting pulse
response can be seen in Figure 7. Extra care may be required to
ensure adequate decoupling by placing a 1jlF to 1OIlF capacitor
in parallel with the existing decoupling capacitor. Adequate
decoupling ensures a low impedance path for high frequency
energy transferred from the decoupling capacitors through the
amplifier's output stage to a reactive load.

FIGURE 5: Large-Signal Transient Response

DRIVING CAPACITIVE LOADS
Direct capacitive loading will reduce the phase margin of any op
amp. A pole is created by the combination of the op amp's output
impedance and the capacitive load that induces phase lag and
reduces stability. However, high-speed amplifiers can easily drive
a capacitive load indirectly. This is shown in Figure 6. The OP-61
is driving a 1OOOpF capacitive load. R1 and C 1 serve to counteract the loss of phase margin by feedforwarding a small amount of
high frequency output signal back to the amplifier's inverting input,

2-202 OPERATIONAL AMPLIFIERS

FIGURE 7: Pulse Response of Compensated XI 0 Amplifier in
Figure 6, V,N = 100m Vp _p, VOUT;" I Vp _p , Frequency of Square
Wave =1MHz, CWAD = IOOOpF!

REV. A

OP-61
DECOUPLING AND LAYOUT GUIDELINES
The OP-61 op amp is a superb choice for a wide range of precision high-speed, low noise amplifier applications. However,
care must be exercized in both the design and layout of highspeed circuits in order for the specified performance to be realized.
Although the OP-61 has excellent power supply rejection over a
wide bandwidth, the negative supply rejection is limited at high
frequencies since the amplifier's internal integrator is biased via
the negative supply line. This operation is typical performance
for all monolithic op amps, and not unique to the OP-61. Since
the negative supply rejection will approach zero for signals
above the close-loop bandwidth, high-speed transients and
wideband power supply noise, on the negative supply line, will
result in spurious signals being directly added to the amplifier's
output. Adequate power supply decoupling prevents this problem.
Generally, a O.l!-,F tantalum decoupling capacitor, placed in
close proximity across the amplifier's actual power supply pin
and ground is recommended. This will satisfy most decoupling
requirements, especially when the circuit is built on a low impedance ground plane. When a heavy copper clad ground plane is
not used, it becomes especially important to confine the high
frequency output load currents confined to as small a high-frequency signal path as possible, as suggested in Figure 8.

+v

Power management of complex systems sometimes results in a
complex l-C network that has high frequency natural resonances that cause stability problems in circuits internal to the
system. Resistors added in series to the supply lines can lower
the Q of the undesired resonances, preventing oscillations on
the supply lines. Resistors of 3 to 10 ohms work well and serve
to ensure the stability of the OP-61 in such systems.
ADDITIONAL CAVEATS FOR HIGH·SPEEDAMPLIFIERS IN·
ClUDE:
1. Keep all leads as short as pOSSible, using direct point-to-point
wiring. Do not wire-wrap or use "plug-in" boards for prototyping circuits.

2. Op amp feedback networks should be placed in close proximo
ity to the amplifiers inputs. This reduces stray capacitance
that compromises stability margins.

3. Maintain low feedback and source resistance values. Impedance levels greater than several kilo-ohms may result in degrading the amplifier's overall bandwidth and stability.
4. The use of heavy ground planes reduces stray inductance,
and provides a better return path for ground currents.
5. Decoupling capacitors must have short leads and be placed
at the amplifier's supply pins. Use low equivalent series resistance (ESR) and low inductance chip capacitors wherever
possible.
6. Evaluation of prototype circuits should be performed with a
low input capacitance, Xi 0 compensated oscilloscope
probe. Xl uncompensated probes introduce excessive stray
capacitance which alters circuit characteristics by introducing additional phase shifts.
7. Do not directly drive either large capacitive loads or coax
cables with high-speed amplifiers (see DRIVING COAXIAL
CABLES).

8. Watch out for parasitic capacitances at the +/- inputs to wideband noninverting op amp circuits. Since these nodes are not
maintained at virtual ground as in the inverting amplifier configuration, parasitics may degrade bandwidth. Wideband
noninverting amplifiers may require the ground plane trace
removed from local proximity to the op amp's inputs.
-v

FIGURE 8: Proper power supply bypassing is required to obtain
optimum performance with the OP-61. Maintain as smalf wideband signal current path as possible. Where signal common is a
low impedance ground plane, simply decouple O. 1!-,F to ground
plane near the OP-61.

REV. A

OPERA TIONAL AMPLIFIERS 2-203

OP-61
+.5V

+15V

I

O
.•••

'k"

'M<>

."".

~

3p.

Av =-10

-15V

'M"

FIGURE 9: High-Speed Settling Time Fixture (for 0.1 and 0.01%)

SETILING TIME
Settling time is the time between when the input signal begins to
change and when the output permanently enters a prescribed
error band. Figure 9 illustrates the artificial summing node test
configuration, used to characterize the OP-61 settling time. The
OP-61 is set in a gain of -10 with a 1.0V step input.The error
bands on the output are 5mV and 0.5mV, respectively, for 0.1 %
and 0.01% accuracy.
The test circuit, built on a copper clad circuit board, has a FET
input stage which maintains extremely low loading capacitance
at the artificial sum node. Preceeding stages are complementary emitter follower stages, providing adequate drive current for
a 50Q oscilloscope input. The OP-97 establishes biasing for the
input stage, and eliminates excessive offset voltage errors.
Figure 10 illustrates the OP-61 's typical settling time of 330ns.
Moreover, problems in settling response, such as thermal tails
and long-term ringing are nonexistent. This performance of the
OP-61 makes it a suberb choice for systems demanding both
high sampling rates and high resolution.

2-204 OPERA TIONAL AMPLIFIERS

FIGURE 10: Settling Characteristics of the OP-61 to 0.01%.
No Thermal Settling Tail Appears as Part of the Settling
Response.

REV. A

OP-61
+15V

I+

rt-

7A13 PLUG·'N

7All PLUG·'N

'''''

100"
300pF
+15V

DIGITAL
lTL
INPUT

r
1.8kg

+15Vo---WV--.

220"

• NOTE: DECOUPLE CLOSE
TOGETHER ON GROUND PLANE
WITH SHORT LEAD LENGTHS

FIGURE 11: Transient Output Impedance Test Fixture

TRANSIENT OUTPUT IMPEDANCE
Settling characteristics of operational amplifiers also includes
an amplifier's ability to recover, i.e., settle, from a transient current output load condition. An example of this includes an op
amp driving the input from a SAR type AID converter. Although
the comparison point of the converter is usually diode clamped,
the input swing of plus-and-minus a diode drop still gives rise to
a significant modulation of input current. If the closed-loop output impedance is low enough and bandwidth of the amplifier is
sufficiently large, the output will settle before the converter
makes a comparison decision which will prevent linearity errors
or missing codes.
Figure 11 shows a settling measurement circuit for evaluating
recovery from an output current transient. An output disturbing
current generator provides the transient change in output load
current of 1mAo As seen in Figure 12, the OP-61 has extremely
fast recovery of 180n5, (to 0.01 %), for a 1mA load transient. The
performance makes it an ideal amplifier for data acquisition
systems.

REV. A

FIGURE 12: OP-61's Extremely Fast Recovey Time from a
1mA Load Transient to 0.01%

OPERATIONAL AMPLIFIERS 2-205

II

OP-61
DRIVING COAXIAL CABLES
The OP-61 amplifier, and a BUF-03 unity-gain buffer, make an
excellent drive circuit for 75Q or 50Q coaxial cables. To maintain optimum pulse response, and minimum reflections, op amp
circuits driving coaxial cables should be terminated at both
ends. Unterminated cables can appear as a resonant load to the
amplifier, degrading stability margins. Also, since coaxial
cables represent a significant capacitive load shunting the driving amplifier, it is not possible to drive them directly from the op
amp's output (RG-58 coax. typically has 33pF/foot of capacitance).
Figure 13 illustrates an OP-61 noninverting, gain of 10, amplifier
stage, driving a double-matched coaxial cable. Since the
double-matching of the cable results in voltage gain loss of6dB,
the composite voltage gain of the entire circuit is 5, or 14dB.

Resistors R3 and R4 serve to absorb reflections at both ends of
the cable. The OP-61 's wide bandwidth and fast symmetric slewing, results in a very clean pulse reponse, as can be seen in
Figure 15. The BUF-03 serves to increase the output current
capability to 70mA peak, and the ability to drive up to a 1 J1F
capacitive load (or a longer cable). The value of C, may need to
be slightly adjusted to provide an optimum value of phase lead,
or pulse response. This capacitor serves to correct for the current buffers phase lag, internal to the OP-61 's feedback loop.

NOISE MODEL AND DISCUSSION
The OP-61 's exceptionally low voltage noise (en 3.0nV/Hz,
high open-loop gain, and wide bandwidth makes it ideal for accurately amplifying wideband low-level signals. Figure 15a
shows the OP-61 cleanly amplifying a 5mVp-p, 1MHz sine wave,
with inverting gain of 100. Noise or limited bandwidth prevents
most amplifiers from achieving this performance.

=

+v

v,.

-v

",'0CKl
FIGURE 13: OP-61 Noninverting, Amplifier Driving Coaxial
Cable, Composite Gain = 5 from VII,po VOUT ' Adjust C 1 for
Desired Pulse Response.
'

FIGURE 14: Pulse Response from Amplifier Circuit in Figure
13, Driving 15 Ft. of RG-58 Coaxial Cable

2-206 OPERATIONAL AMPLIFIERS

-v

FIGURE 15a: Example of Low Level Amplifier in an Inverting
Configuration, Gain =Vou.,N/N =-RjRj =-100

FIGURE 15b: OP-61, Gain =-100.0, WidebandAmplifier,
V1N =5mVp •p Signal at 1MHz, V OUT =500mVp •p

REV. A

OP-61
z,

The equivalent input voltage noise, referred to the output, can
be found by adding all the noise sources in a sum-of-square
fashion:

Referred back to the amplifiers input:
en; =..§L =
IAveLl
V(en2 {N.G.)2 + in21Z12 (N.G.)2+ in2 IZ1I2 + iZS2 IZil2 + 8Zf2)
FIGURE 16: Inverting Gain Configuration Noise Model for the
OP-61

The inverting amplifier model, seen in Figure 16, can be used to
calculate the equivalent input noise, eni' eni is the voltage noise,
modeled as part of the input signal. It represents all the current
and voltage noise sources lumped into one equivalent input
voltage.
Typical values for the OP-61 nOise parameters are:
en = 3.4nV/ /HZ @ 1kHz

IAveLl
To capitalize on the low voltage performance of the OP-61 , Z, Z,
and especially Zs must be as low impedance as possible. With
low impedance values of Z, and Zs:
. Ven 2 (1 + IAveLj) 2 or e.
eOI!i!I!
m
1Avel 1
I

a

en (N.G.)
(N.G.)-1

All noise contributions are now easily modelled as a signal
equivalent noise voltage source, en; (see Figure 17).

in = 1.7pN ,/Hz @ 10kHz
(where it is assumed that in = in - = in +).
It can be defined from the model in Figure 16:
en; = total input referred spot voltage noise (all noise
contributions lumped into one equivalent voltage
noise source).
en = spot voltage noise of OP-61
in = spot current noise of OP-61
Zs = total input impedance
Z = impedance at OP-61 + input node
AyCl = closed-loop gain for inverting amplifier
N.G. = 1 + IAycll = noise gain for inverting amplifier

FIGURE 17: Equivalent Noise MOdel, Where All Noise Contributions are Lumped Into e ni

izs = spot noise current generated by ZS. If Zs = Rs' then
izs = iRS = 0.12~ nV/v'HZ.
eZf = spot voltage noise generated by Z, . If Z, = R"
then ez, = eR, = 0.129

VA;"nV/VHz.

Note: Equation is derived from Johnson noise relationship of
resistor R:
e R =-/4kTR =y'4kT.fA = 0.129.fA nV/VHz. R is in ohms.

REV. A

OP-61 SPICE MACROMODEL
Figures 18 and 19 show the node and net listfor a SPICE macromodel of the OP-61. The model is a simplified version of the
actual device and simulates important DC parameters such as
Vos' los, IB,Ayo' CMR, Vo and ISY. AC parameters such as slew
rate, gain and phase reponse and CMR change with frequency
are also simulated by the model.
The model uses typical parameters for the OP-61. The poles
and zeros in the model were determined from the actual open
and closed-loop gain and phase reponse of the OP-61. In this
way the model presents an accurate AC representation of the
actual device. The model assumes an ambient temperature of
25°C (see following pages).

OPERATIONAL AMPLIFIERS 2-207

OP-61

OP-51
OP-61 MACROMODEL AND TEST CIRCUIT

©AD11990

• subckt OP-61 1 238 99 50
• INPUT STAGE & POLE AT 300 MHz
rl
r2
r3
r4
cin
c2
il
ios
eos
ql
2

9

2
1
5
6
1
5
4
1
9
5
6

3
3
99
99
2
6
50
2
1
2
9

4
4

5Ell
5Ell
51.6
51.6
5E-12
5.141E-12
lE-3
2E-7
poly(l) 26 32 400E-6 1
qx
qx

• POLE AT 200M Hz
r23
r24
c9
cl0
911

23
23
23
23
99
~12 23

• POLE AT 200M Hz
r25
26
cll
c12
913

24
24
24
24
99
~14 24

99
50
99
50
24
50

• FIRST GAIN STAGE

• POLE AT 200MHz

r7
r8
dll
d12
91
92
e1
e2

r27
r28
c13
c14
915

·

11
11
11
12
99
11
99
12

99
50
10
11
11
50
10
50

lE6
lE6
dx
dx
5 6 2E-4
652E-4
poly(l) 99 32 -4.4 1
poly(l) 32 50 -4.4 1

• SECOND GAIN STAGE & POLE AT 2.5kHz

r9
rl0
c3
c4
93
94
v2
v3
d1
d2

·

13
13
13
13
99
13
99
15
13
15

99
50
99
50
13
50
14
50
14
13

5.1598E6
5.1598E6
12.338E-12
12.338E-12
POIY!l) 11 32 4.24E-3 9.69E-5
poly 1) 32 11 4.24E-3 9.69E-5
2.3
2.3
dx
dx

• POLE-ZERO PAIR AT 4MHz I 8MHz

rll
r12
r13
r14
c5
c6
95
~6

·

16
16
16
16
17
18
99
16

99
50
17
18
99
50
16
50

lE6
lE6
lE6
lE6
19.89E-15
19.89E-15
1332 lE-6
32 13 lE-6

• ZERO-POLE PAIR AT 85M Hz 1300MHz

r17
r18
r19
r20
13
14
97
~8

19
19
20
21
20
21
99
19

20
21
99
50
99
50
19
50

1E6
lE6
2.529E6
2.529E6
1.342E-3
1.342E-3
1632 1E-6
32 16 lE-6

• POLE AT 40MHz
r21
r22
c7
c8
99

22
22
22
22
99
~10 22

99
50
99
50
22
50

lE6
lE6
3.979E-15
3.979E-15
1932 lE-6
32 19 lE-6

lE6
lE6
.796E-15
.796E-15
2232 lE-6
3222 lE-6

99
50
99
50
23
50

25
25
25
25
99
~16 25

99
50
99
50
25
50

lE6
lE6
.796E-15
.796E-15
23321E-6
3223 lE-6

1E6
lE6
.796E-15
.796E-15
2432 lE-6
32 24 1E-6

• COMMON-MODE GAIN NETWORK WITH ZERO AT 40kHz
r29
r30
15
16
917

26
26
27
28
99
~18 26

27
28
99
50
26
50

lE6
lE6
3.979
3.979
33 32 1E-ll
32331E-11

• POLE AT 300MHz
r32
r33
c15
c16
919
920

31
31
31
31
99
31

99
50
99
50
31
50

lE6
1E6
.531E-15
.531E-15
2532 lE-6
3225 lE-6

• OUTPUT STAGE
r34
r35
r36
r37
17
921
922
923
924
v6
v7
d5
d6
d7
d8
d9
dl0

·

32
32
33
33
33
36
37
33
50
34
33
31
35
99
99
50
50

99
50
99
50
38
50
50
99
33
33
35
34
31
36
37
36
37

20.0E3
20.0E3
30
30
1.65E-7
31 33 33.3333333E-3
33 31 33.3333333E-3
99 31 33.3333333E-3
31 50 33.3333333E-3
.2
.2
dx
dx
dx
dx
dy
dy

• MODELS USED

·model ~x NPN(BF=1250)
·model x D!IS=lE-15)
'modeldy D IS=1E-15 BV=50)

FIGURE 19: OP-61 SPICE Net List
.. PSpice Is a registered trademark of MicroSim Corporation .
.... HSPICE is a tradename of Mela-Software, Inc.

REV. A

OPERA TIONAL AMPLIFIERS 2-209

•

2-210 OPERA TlONAL AMPLIFIERS

High-Speed, Wide-Bandwidth
Operational Amplifier (AvCL :> 5)
OP-64 I

11IIIIIIII ANALOG
WDEVICES
FEATURES

GENERAL DESCRIPTION

• High Slew Rate ................................................ 130VIllS Min
• Fast Settling Time (+10V, 0.1%) ....................•.. 100nsTyp
Gain-Bandwidth Product (AvCL = +5) .....•.....•.. SOMHz Typ
Low Supply Current ............................................ SmA Max
Low Noise ....................................................... SnV/-YHz Typ
Low Offset Voltage .............................................. 1mV Max
High Output Current ........................................ ±SOmA Typ
Eliminates External Buffer
Standard S-Pin Packages
Available in Die Form

The OP-64 is a high-performance monolithic operational amplifierthat combines high speed and wide bandwidth with low power
consumption. Advanced processing techniques have en-

Continued.
PIN CONNECTIONS
EPOXY MINI-DIP
(P-Suffix)
S-PIN CERDIP
(Z-Suffix)

ORDERING INFORMATION t
PACKAGE
T.=+25°C
VosMAX
(mV)
1.0
1.0
2.0
2.5
2.5

To-99
II-PIN

HERMETIC
DIP
II-PIN

PLASTIC
II-PIN

OP64AJ' OP64AZ'
OP64EJ OP64EZ
OP64FJ OP64FZ

EPOXY SO
(S-Suffix)

OPERATING
HERMETIC
LCC
TEMPERATURE
2()'CONTACT
RANGE
MIL
XIND
XIND
XIND
XIND

OP64ARC/883

OP64GP
OP64GS"

XIND = Extended Indust!ial Temperature Range, -40°C to +85°C
For devices processed in total compliance to MIL-SDT-883, add 1883 after part
number. Consult factory for 883 data sheet.
Burn-in is available on commercial and industrial temperature range parts in
CerDlP, plastic DIP, and TO·99 can packages.
tt For availability and burn-in information on SO and PLCC packages, contact

your local sales office.

20-LEAD HERMETIC LCC
(RC-Suffix)

TO-99
(J-Suffix)

SIMPLIFIED SCHEMATIC
r----.--~--------------~--~------._--------.--------.--------.---~v+

OUT

~--~--~---------1----~------4---------~----------

NULL

REV. A

__--------4---~ v-

NULL

OPERA TlONAL AMPLIFIERS 2-211

OP-64
GENERAL DESCRIPTION Continued

enabled PMI to make the OP-64 superior in cost and performance to many dielectrically-isolated and hybrid op amps.
Slew rate of the OP-64 is over 130VIllS. It is stable in gains of ~5
and has a settling time of only lOOns to 0.1% with a 10V step
input. However, unlike other high-speed op amps which have
high supply requirements, the OP-64 needs less than SmA of
supply current. This enables the OP-64 to be packaged in space
saving S-pin packages. The OP-64 can deliver ±SOmA of output
current eliminating the need for a separate buffer !!!!!plifier in
many applications. Noise of the OP-64 is only SnV"Hz, reducing system noise in wideband applications. In addition to its dynamic performance, the OP-64 adds DC precision with an input
offset voltage of under 1mV.
The OP-64 is an ideal choice for RF, video and pulse amplifier
applications and in new designs can replace the HA-5190/95 or
EL-2190/95 with improved performance and reduced power
consumption. Its high output current also suits the OP-64 for use
in AID or cable driver applications. The OP-64 includes a DiSABLE pin which, when set low, shuts the amplifier off and reduces the supply current to 0.75mA.

ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage ................................................................. :i: ISV
Input Voltage .................................................... Supply Voltage
Differential Input Voltage ................................................... 20V

DISABLE Input Voltage ................................... Supply Voltage
Output Short-Circuit Duration ........................................ 10 sec
Storage Temperature Range
(J, Z, RC) .................................................... -SS·C to + 17S·C
(P, S) ... :...................................................... -6S·C to +IS0·C
Operating Temperature Range
OP-64A (J, Z, RC) ...................................... -SS·C to +12S·C
OP-64E, F (J, Z) ........................................... -40·C to +8S·C
OP-64G (P, S) .............................................. -40·C to +8S·C
Maximum Junction Temperature
OP-64A (J ,Z, RC) ...............................•... ,..............•.. +17S·C
OP-64E, F (J, Z) ........................................................ +17S·C
OP-64G (P, S) ................................. :......................... +150·C
Lead Temperature (Soldering, 60 sec) ........................ +300·C
alC

UNITS

TO·99 (J)

PACKAGE TYPE

150

18

·CIW

8-Pin Hermelic DIP (Z)

148

16

·CIW

8-Pin Plastic DIP (P)

103

43

·CIW

98

38

·CIW

158

43

·CIW

alA (Note 2)

20-Contacl LCC (RC. TC)
8-Pln SO (5)

NOTES:
1. Absolute maximum ratings apply to both DICE and packaged perls, unless
otherwise noted.
2. alA is spacified lor worst case mounting conditions, I.e., alA is specified for
device In socket lor TO, CerDIP, P-DIP, and LCC packages; alA is specified
for device soldered to printed circuit board for SO package.

ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = +25°C, unless otherwise noted.
CONDITIONS

MIN

OP-64A1E
TYP

Offset
Voltage

vos

0.4

0.8

2

1.2

2.5

mV

Input Bias
Current

IB

0.2

0.4

2

0.8

2.5

~A

Input Offset
Current

los

0.1

0.3

2

0.6

2.5

~A

Input Voltage
Range

IVR

Common·Mode
Rejection

CMR

Power·Supply
Rejection Ratio

PSRR

Vs =±SV to ±18V

Large·Signal
Voltage Gain

Avo

RL = 2kil, Vo = ±IOV
RL = 2000, Vo = ±SV

Output Voltage
Swing

Vo

Output
Current

lOUT

Supply
Current

ISY

±11

90

MAX

±11

84

100

5

17.8

MIN

±11

94

15

84

31.6

UNtTS

V

94

15

dB

31.6

~V!V

30
12.5

45
18

20
10

35
16

20
10

35
16

V/mV

±11
±10

±12.5
±Il.7

±11
±IO

±12.5
±11.7

±11
±10

±I2.5
±Il.7

V

±80

mA

±80

No Load

MIN

OP-64G
TYP
MAX

SYMBOL

(Note II

MAX

OP-64F
TYP

PARAMETER

6.2

±80

8

6.2

8

6.2

8

mA

NOTE:
1. Guaranteed by CMR test.

2-212 OPERA TIONAL AMPLIFIERS

REV. A

OP-64
ELECTRICAL CHARACTERISTICS at Vs =±15V, T A = +25°C, unless otherwise noted.
PARAMETER

SYMBOL

CONDITIONS

ISY DiS

DISABLE =OV
Total for both supplies

DISABLE
Current

IDiS

DISABLE = OV

Slew Rate

SR

RL =2kn

Full·Power
Bandwidth

BWp

(Note 2)

Gain·Bandwidth
Product

GBWP

Av=+5

Settling Time

ts

10V Step 0.1%

Disable Supply

Current

MIN

OP-64A/E
TYP

MAX

MIN

OP-64F
TYP

MAX

MIN

OP-64G
TYP
MAX

UNITS

0.75

0.75

0.75

mA

0.5

0.5

0.5

mA

t30

t70

t30

t70

t30

170

V/~s

2

2.7

2

2.7

2

2.7

MHz

MHz

80

80

80

100

100

100

57

57

57

ns

-

Phase Margin

em

Input
Capacitance

C 1N

5

5

5

pF

Open-Loop
Output

Ro

30

30

30

n

en

fo = 10Hz
fo = 100Hz
fo = 1kHz
fo = 10kHz

30
10
8
8

30
10
8
8

30
10
8
8

in

fo = 10kHz

7.5

7.5

7.5

4

4

4

Av =+5

degrees

Resistance
Voltage

Noise
Density

Current Noise
Density
External Vcs
Trim Range

Rpo '= 20kn

Supply Voltage
Range

Vs

±5

±15

±18

±5

±15

±18

±5

±15

-

nV/VHz

-

pAlVHz

mV

±18

V

NOTES:
1. Guaranteed by CMR test.
2. Guaranteed by slew·rate test and formula BWp = SRI(2xl0V pEAK ).

REV. A

OPERA TIONAL AMPLIFIERS 2-213

II

OP-64
ELECTRICAL CHARACTERISTICS at Vs = ±15V, -40°C S TAS +85°C for OP-64E1F/G, unless otherwise noted.
PARAMETER

SYMBOL

Offset
Voltage

Vos

Input Bias
Current

la

CONDITIONS

MIN

OP-64E
TYP

MAX

MIN

OP-64F
TYP

0.5

t.5

1.0

VCM=OV

0.3

2.5

0.5

los

VCM =OV

0.2

2.5

0.5

Input Voltage
Range

IVR

(Note I)

Common·Mode
Rejection

CMR

VCM=±II

Power·Supply
Rejection Ratio

PSRR

Vs =±5Vto±18V

Large·Signal
Voltage Gain

Avo

RL =2kn, Vo=±IOV
RL =200Q, Vo =±5V

Output Voltage
Swing

Vo

RL=2kn
RL =200Q

Supply
Current

ISY

No load

Input Offset

Current

±II

86

MAX
3

3

±II

100

5

80

OP-64G
TYP
MAX

94

80

3:5

mV

1.5

3.5

~A

t.O

3.5

~A

V

94

IS

50

UNITS

1.5

±II

IS

31.6

MIN

dB

50

~VN

20
7.5

40
12

IS
5

35
10

IS
5

35
10

VlmV

±II
±IO

±12.3
±11.5

±II
±IO

±12.3
±11.5

±II
±IO

±12.3
±11.5

V

6.3

8.5

6.3

8.5

6.3

8.5

mA

NOTE:
I. Guaranteed by CMR test.

ELECTRICAL CHARACTERISTICS at VS = ±15V, -55°C S T A S + 125°C for OP-64A, unless otherwise noted.
PARAMETER

SYMBOL

Offset
Voltage

Vos

Input Bias
Current

la

Input Offset
Current

CONDITIONS

MIN

OP-64A
TYP

MAX

UNITS

0.4

2

mV

VCM=OV

0.35

2

~A

los

VCM=OV

0.3

2

~A

Input Voltage
Range

IVR

(Note I)

Common·Mode
Rejection

CMR

VCM=±II

Power-Supply
Rejection Ratio

PSRR

Vs =±5Vto±18V

large·Signal
Voltage Gain

Avo

RL =2kQ, Vo=±IOV
RL = 200Q, Vo = ±5V

Output Voltage
Swing

Vo

RL =2kQ
RL =2ooQ

Supply
Current

ISY

No load

±II

86

V

100

8

dB

31.6

~VN

20
7.5

30
10

V/mV

±II
±7.5

±12
±IO

V

6.4

8.5

mA

NOTE:
I. Guaranteed by CMR test.

2-214 OPERATIONAL AMPLIFiERS

REV. A

OP-64
DICE CHARACTERISTICS

1.
2.
3.
4.
5.
6.
7.
8.

NULL
-IN
+IN
VNULL
OUT
V+
DISABLE

II

DIE SIZE 0.086 x 0.065 inch, 5,590 sq. mils
(2.18 x 1.65 mm, 3.60 sq. mm)

WAFER TEST LIMITS at Vs

= ±15V, TA = +25°C, unless otherwise noted.

OP-64GBC
PARAMETER

SYMBOL

Offset Voltage

Vas

Input Bias Current

18

Input Offset Current

los

Input Voltage Range

IVR

(Note 1)

Common-Mode Rejection

CMR

VCM =±I1V

Power Supply
Rejection Ratio

PSRR

Vs = ±5V to ±18V

Large·Signal
Voltage Gain

Ava

RL = 2kO, Va = ±10V
RL = 200n, Va = ±5V

Output Voltage
Swing

Va

RL =2kO
RL = 2000

Slew Rate
Supply Current

SR

CONDITIONS

LIMITS

UNITS

2.5

mVMAX

VCM = OV

2.5

~AMAX

VCM = OV

2.5

~AMAX

VMIN

84

dBMIN

31.6

~VNMAX

20
10

V/mVMIN

±11
±10
120

RL =2kn
ISY

±11

No Load

8

VMIN
V/~s

MIN

rnA MAX

NOTES:
1. Guaranteed by CM R test.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for
standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

REV. A

OPERA TlONAL AMPLIFIERS 2-215

OP-64
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs TEMPERATURE
0.7
=±15V

~:;~~v

0 .•

~

i!;
~

:.-- I--

0.3

~

0.4

"

0.3

."~

......... V

~

0.4

V

-

0.5

g

i

0.4

0.5

Ys

~w

"\

~
0.2

"-

~

0.2

-50

-25

25

50

75

100

-25

25

50

SETTLING TIME
vs STEP SIZE

RL=2k~,1_

i"-- .........

-

100

2

51

1'-

..

0

~

-2

~

-10

-SO

-25

25

SO

75

100

125

\

-75

125

-SO

-25

-

1-25

50

75

r-100

125

=±15V I

Av=+S
R L =200U

65

D r::::

,

o

50

25

75

10mV

100

40
-75

125

50

20

-SO

-25

0

25

50

75

100

125

+2~~~

TA =
Vs =±15V

TA '" +2S·C
Vs =*15V
VIN '" 20mVp-p
AV = +5

.0

t-r-

CLOSED-LOOP OUTPUT
IMPEDANCEvsFREQUENCY

100

'0

~r-GBW'-

TEMPERATURE (OC)

SMALL SIGNAL OVERSHOOT
vs CAPACITIVE LOAD

OPEN-LOOP GAIN,
PHASEvsFREQUENCY

-

m

45

SETTLING TIME (ns)

100

~

140

lis
+10mV

~

TEMPERATURE (0C)

40
NEGATIVE EDGE

iD 60

'~"

"-

40

fil

~

$

f'..

1\

5-4
-8

:

100

/
IL

4

~
w

I'-.. ......

i"--

-8R

'"
~

50

~

0.1

GAIN-BANDWIDTH PRODUCT, PHASE
MARGIN vs TEMPERATURE

I

o

~

~

1\\

70

=

ill

~

0.2

TEMPERATURE (OC)

TA =+2SOC
Vs =±15V
AV =+5

Vs =±15V
Av +5V

~

-75

"

10

w

o

."~

r--

75

SLEW RATEvs
TEMPERATURE

i'- i'-

l150
~

-50

TEMPERATURE (OC)

+SR

200

0.3

;!;

r-

TEMPERATURE (OC)

250

~

I
........

=~'5V

~M=OV

o

0.1
-75

125

•

1\

~
;!;

0.1
-75

INPUT OFFSET CURRENT
vs TEMPERATURE

INPUT BIAS CURRENT
vs TEMPERATURE

e.

20

135

ill
f
~

0

~

t;

""

60

1j

0

~

~

30

z

~

~

40

i!!

20
AYCL=+100
AYCL=+10AyCt=+S-

180
10

20

0 ' - _ - - l ._ _...L.._ _.1--_--'_ _-'
10k

lOOk

1M

10M

100M

FREQUENCY (Hz)

2-216 OPERATIONAL AMPLIFIERS

o

20

40

60

CAPACITIVE LOAD (pF)

80

100

o

i
1k

10k

"
100k

i>"

~

1M

10M

FREQUENCY (Hz)

REV. A

OP-64
TYPICAL PERFORMANCE CHARACTERISTICS
CLOSED-LOOP GAIN
vs FREQUENCY
50

AvcL

CURRENT NOISE DENSITY
vs FREQUENCY

VOLTAGE NOISE DENSITY
vs FREQUENCY

..

100

~~" ~~.:,

II I I! I

40

Continued

\Is

TA _+25OC

=±15Y

Vs =±15V

=+100
11111

lv~~1 ~1~'01

~

111111

!!!

AYCL

"

~
w

0
Z

=+5

II

~

10

~

mllill

0:

"

0

-10

110~..J..J...J..J.J..lJ'':00:-.l....Jw....cJ.l.U'kl.......J..J...J..ll.llU,,,

-20
10k

"

lOOk

1M

lUM

100M

FREQUENCY (Hz)

SUPPLY CURRENT
vs TEMPERATURE

1

10

Isy DISABLE vs
TEMPERATURE
1.00

...~

~

§
o

~v

./
. /. /
V/
/..,
."
/'r'
:/'

6.4

i

6.2

~ 5.6

5.0
4 ••

-75

-50

-25

25

50

75

100

125

o

TEMPERATURE ("C)

Vs =±15V

~'2

6

~ 10

I,.
I
"

/

/

%10

.15

-75

..0

-50

-25

~

1A

125

= +25OC

~

~-I-VOMI

~

~

".

V'"

/'

40

../

0

i

iii

6

"

;; 2.5

4

100

R L =2kU

~ 2.7

§

75

50

2.8

:E 2.6

50

OPEN-LOOP GAIN
vs SUPPLY VOLTAGE

TA=+25"C

g,

25

60

2.'

l-vOM I

-

i--

TEMPERATURE lOCI

3.0

IIU
+Vou ..

o

MAXIMUM OUTPUT VOLTAGE
vs LOAD RESISTANCE
Vs =±5V

II

TA =+25OC

14

-- r-r-.. -

SUPPLY VOLTAGE (VOLTS)

MAXIMUM OUTPUT VOLTAGE
vs LOAD RESISTANCE
Vs =±15V
16

~ 0.25

..... S~PIS

.

r--.. ........ r--

~

L

5.2

+ISVDIS

~ 0.50

~'C

il:

i"-r-. ........

l

;

+25"C

5.8

DISABLE=OY

...

0.75

+125"C

6.0

m5.4

3

10'

SUPPLY CURRENT
vs SUPPLY VOLTAGE
NO LOAD

6.6

!Z
ll!

lk

FREQUENCY (Hz)

6.8

Va =±15V
NO LOAD

100

FREQUENCY (Hz)

30

V-

/

20
2.4

o

100

1.
LOAD RESISTANCE (U)

REV. A

10k

2.3
100

10

"

LOAD RESISTANCE (U)

10k

o

..

:t10

±15

toO

SUPPLY VOLTAGE (VOLTS)

OPERATIONAL AMPLIFIERS 2-217

OP-64
TYPICAL PERFORMANCE CHARACTERISTICS Continued
OPEN-LOOP GAIN

COMMON-MODE REJECTION
vs FREQUENCY

vs SUPPLY VOLTAGE
25

140

TA=+~~I

TA =+25"C
RL =21~O1!

120

20

>E

~

z

C

,.

V

V

"

I

!!.100

i'

.

o

;

60

a:

so

±10

%15

-20

±20

140

T~ ~~~:'C

"

!i100

a:

1:11

!~

I

+PS~~",

40
20

I

il:

I..

I

I

i

~i
1~~N

~ 60

i!

..,C

I

I

I
I

....

1k

10k

tOOk

0.8
0.5

G

0.4

~

D.'

~-

0.2
0.1

I
100

10M

TA =+25·C
"s="5V

0.7

I

r-.

1M

0..

!

I

100k
FREQUENCY (Hz)

INPUT BIAS CURRENT vs
COMMON-MODE VOLTAGE

Vs =±15V

o

10k

"

SUPPLY VOLTAGE (VOLTS)

POWER SUPPLY REJECTION
RATIO vs FREQUENCY
m120

I\.

I:

10

o

Vs =:t15V

;;;

~

o

1M

FREQUENCY (Hz)

10M

r\
\

\

""

-12.5 -10.0 -7.5 -5.0 -2.5

0

2.5

5.0

7.5 10.0 12.5

COMMON-MODE VOLTAGE (VOLTS)

BURN-IN CIRCUIT
10kU

+15V

.---+--0 DISABLE

10kS.l

tOU

-15V

2-218 OPERATIONAL AMPLIFIERS

REV. A

OP-64
LARGE SIGNAL RESPONSE (Vs =±15V)

LARGE AND SMALL SIGNAL RESPONSE
TEST CIRCUIT
+v

OUTPUT

, . - - - - - 0 DISABLE
INPUT

/,---,,---~---oVOUT

200U

SMALL SIGNAL RESPONSE (Vs = ±15V)

OUTPUT

INPUT

LARGE SIGNAL RESPONSE (V s = ±5V)

Av =+5

-v

obtaining optimum performance from the OP-64. Proper high
frequency layout reduces unwanted signal coupling in the circuit. When breadboarding a high frequency circuit, use direct
point-to-point wiring, keeping all lead lengths.as short as possible. Do not use wire-wrap boards or "plug-in" prototyping
boards.
During PC board layout, keep all lead lengths and traces as
short as possible to minimize inductance. The feedback and
gain-setting resistors should be as close as possible to the inverting input to reduce stray capacitance althat point..To further

OUTPUT

v+
INPUT

APPLICATIONS INFORMATION
POWER SUPPLY BYPASSING AND
LAYOUT CONSIDERATIONS
Proper power supply bypassing is critical in all high-frequency
circuit applications. For stable operation of the OP-64, the
power supplies must maintain a low impedance-to-ground over
an extremely wide bandwidth. This is most critical when driving
a low resistance or large capacitance, since the current required
to drive the load comes from the power supplies. A 1 O~F and
0.1 ~F ceramic bypass capacitor are recommended for each
supply, as shown in Figure 1, and will provide adequate highfrequency bypassing in most applications. The bypass capacitors should be placed at the supply pins of the OP-64. As with all
high frequency amplifiers, circuit layout is a critical factor in

REV. A

v-

FIGURE 1: Proper power supply bypassing is required to obtain
optimum performance with the OP-64.

reduce stray capacitance, remove the ground plane from the
area around the inputs of the OP-64. Elsewhere, the use of a
solid unbroken ground plane will insure a good high-frequency
ground.

OPERATIONAL AMPLIFIERS 2-219

•

OP-64
v.

.15V

..-----oOiiiAiilli
~--OOIlT

RPOT

=:I

20k11 TO 100kJ,l

v-

FIGURE 2: Input Offset Voltage Nulling

OFFSET VOLTAGE ADJUSTMENT
Offset voltage is adjusted with a 20kO potentiometer as shown
in Figure 2. The potentiometer should be connected between
pins 1 and 5 with its wiper connected to the V- supply. The typical trim range is ±4mV.

OP-64 DISABLE AMPLIFIER SHUTDOWN
Pin 8 of the OP-64, DISABLE, is an amplifier shutdown control
input. The OP-64 operates normally when Pin 8 is left floating.
When greater than 250llA is drawn from the DISABLE pin, the
OP-64 is disabled. The supply current drops to 1mA and the
output impedance rises to 2kO. To draw current from the DISABLE pin, an open collector output logic gate or a discrete NPN
transistor can be used as shown in Figure 3. An internal resistor

FIGURE 4: DISABLE Tum-On/Tum-Off Test Circuit
limits the DISABLE current to around 500liA if the DISABLE pin
is grounded with the OP-64 powered by ±15V supplies. These
logic interface methods have the added advantage of level shifting the TTL signal to whatever supply voltage is used to power
theOP-64.
Figure 4 shows a test circuit for measuring the turn-on and turnoff times for the OP-64. The OP-64 is in a gain of 5 with a +1V DC
input. As the input pulse to the 74LS04 rises its output falls,

v.

v.

SkU

2V
I I 0---./l1lI'--1:.
ov--.J L

v-

LOOICGATE
WITH OPEN
COLLECTORIORAIN
OIITPUT

v-

FIGURE 3: Simple circuits allow the OP-64 to be shut down.

2-220 OPERA T10NAL AMPLIFIERS

REV. A

OP-64
drawing current from the DISABLE pin and disabling the amplifier. The output voltage delay is shown in Figure 5 and takes
500llS to reach ground due to the extra current supplied to the
amplifier by the 1OIlF electrolytic bypass capacitors. The turnon time is much quicker than the turn-off time. In this situation as
the inputlo the 74LS04 falls its output rises, returning the OP-64
to normal operation. The amplifier's output turns on in 250ns.

The 750 cable termination resistor minimizes reflections from
the end of the cable. The 750 series output resistor absorbs any
reflections caused by a mismatch between the 750 termination
resistor and the characteristic cable impedance. In this circuit
the output voltage, Voup is one-half of the OP-64's output voltage due to the divider formed by the 750 terminating resistors.
The output voltage at the end of the terminated cable, Voup
spans -1 V to + 1V. The differential gain and phase for the video
amplifier is summarized in Tablel.

(8)
OUTPUT

TABLE 1: Differential Gain and Phase of Video Amplifier/Line
Driver
Differential Gain

LOGIC INPUT

Differential Phase

3.58MHz

5MHz

3.58MHz

5MHz

0.008dB
0.008dB

0.016dB
0.018dB

0.03°
0.03°

0.03°
0.03°

±15V
±12V

+15V

(b)
OUTPUT

1I1S,±1V
SQUARE WAVE

LOGIC INPUT

·INo-~----I

~---~--oVo~
501'
200U

FIGURE 5: (a) OP-64 turn-on and turn-off performance. (b)
Expanded scale showing turn-on performance of the OP-64.
-15V

OVERDRIVE RECOVERY
Figure 6 shows the overdrive recovery performance of the OP64. Typical recovery time is 270ns from negative overdrive and
80ns from positive overdrive.

FIGURE 7: Overdrive Recovery Test Circuit

+15V

VIDEO AMPLIFIERrrERMINATED LINE DRIVER
The OP-64 can be used as a video amplifier/terminated line
driver as shown in Figure 8. With its high output current capability, the OP-64 eliminates the need for an external buffer.

·'No-...----;

V OUT

lOV/DIVISION
-1SV

V'N
lV/DIVISION

FIGURE 8: Video Amplifier/Terminated Line Driver

FIGURE 6: OP-64 Overdrive Recovery

REV. A

OPERATIONAL AMPLIFIERS 2-221

•

OP-64
+5V

------1

1::..~~DANce
1M11
1SOURCE
.--MH--o--+--.I
1
R,

1

1

8IJO{1

-:-

1_____ -

1
1

R2
:100n

FIGURE 9: Fast Transimpedance Amplifier
FAST TRANSIMPEDANCE AMPLIFIER

The circuit shown in Figure 9 is a fast transimpedance amplifier
designed to handle high speed signals from a high impedance
source such as the output of a photomultiplier tube. The input
current is amplified and converted to an output voltage by the
transimpedance amplifier.
A JFET source-follower input is used to reduce the input bias
current of the amplifier to 100 pA and lower the input current
noise. Transimpedance of the amplifier is:
VOUT =
liN

(.81. + 1) A3

FIGURE 10: Output of the Fast TransimpedanceAmplifier

A2

and for the values shown equals
VOUT =(8000 + 1) 400kO = 2V/IlA
liN
2000
Figure 10 shows the output of the transimpedance amplifier
when driven from a 1MO source impedance. The input signal of
lOIlAp.p is converted into an output voltage of (1 01lA) 2V/IlA =
20Vp.p. Output slew rate is 100V/IlS. The slew rate is limited by
the combination of the capacitance of the JFET gate with the
1MO ~ource impedance. For best performance. the stray input
capacitance should be kept as small as possible. The OP-97 is
used in an integrator loop to reduce the total amplifier offset
voltage to under 251lV.

2-222 OPERATIONAL AMPLIFIERS

OP-64 SPICE MACRO·MODEL

Figure 11 shows the node and net list for a SPICE macro-model of
the OP-64. The model is a simplified verSion of the actual device and
simulates important DC parameters such as Vos' los· Ie. Avo. CMR.
V0 and ISY. AC parameters such as slew rate. gain and phase response and CMR change with frequency are also simulated by the
model.
The model uses typical paremeters for the OP·64. The poles and
zeros in the model were determined from the actual open and closedloop gain and phase response of the OP-64. In this way the model
presents an accurate AC representation of the actual device. The
model assumes an ambient temperature of 25°C (see following
pages).
.

REV. A

OP-64
99
©PM11989

R,

IN-

R,

0,

•
R,

II

D,

"os

1

R.

11

R,
IN+

G,

C,

R,

R,

CJN

los

C.

G,

C,

Ra

-+

0,

C,

R,o

G,
C,

(a)

(b)

(e)

9.

t.,
R21

0.

C,

22

R23

G"

C,

G13

Ca

R"

c"

R,.

C 12

2.

23

0,.

R..

G12

R24

c,.

G"

L,

SO
~

(d)

(I)

(e)

(h)

(0)

V.

99

G23

oa
G"

R"

CIS

R,.

R34
0,

V,
34

+-

3.
31

V,

35

-+

R30
28

Goo

R"

c"

R35

R"
G"

L,
50
(I)

(I)

(k)

FIGURE 11 a: OP-64 SPICE Macro-Model Schematic and Node List

., PSpice is a registered trademark of MicroSim Corporation.
*'" HSPICE is a tradename of Meta-Software, Inc.

REV. A

OPERA TIONAL AMPLIFIERS 2-223

OP-64

·
·
·

OP-64 MACRO-MODEL e PMll989

INPUT STAGE & POLE AT 39.8 MHz
rl
r2
r3
r4
r5
r6
cin
c2
il
ios
eos
ql
~2

2
1
5
6
4
4
1
5
4
1
9
5
6

3
3
99
99
7
8
2
6
50
2
1
2
9

7
8

j5Ell
5Ell
474.86
474.86
423.26
423.26
5E-12
4.2106E-12
lE-3
lE-7
poly(l) 26 32 4E-4 1
qx
qx

: SECOND STAGE & POLE AT 3.8 kHz
r7
r8
c3
c4
gl
g2
v2
v3
dl
d2

·

·

11
11
11
11
99
11
99
12
11
12

99
50
99
50
11
50
10
50
10
11

7.1229E6
7.1229E6
5.88E-12
5.88E-12
poly(l) 5 6 4.31E-3 2.1059E-3
poly(l) 6 5 4.31E-3 2.1059E-3
2.25
2.25
dx
dx

• POLE AT 39.8 MHz
r9
rIO
c5
c6
93
94

·
·

13
13
13
13
99
13

99
50
99
50
13
50

lE6
lE6
4E-15
4E-15
11 321E-6
32 11 lE-6

• ZERO-POLE PAIR AT 26.5 MHz /159 MHz
r13
r14
r15
r16
11
12
g5

~6

·

16
16
17
18
17
18
99
16

17
18
99
50
99
50
16
50

lE6
lE6
5E6
5E6
5.005E-3
5.005E-3
13 32 lE-6
32 13 lE-6

• ZERO-POLE PAIR AT 31.8 MHz /39.8 MHz
r17
r18
r19
r20
13
14
97

~8

·

·

·POLE AT 159 MHz

osubckt OP-64 1 238 99 50

19
19
20
21
20
21
99
19

20
21
99
50
99
50
19
50

lE6
lE6
2.5157E5
2.5157E5
1.006E-3
1.006E-3
16 321E-6
32 161E-6

r23
r24
e9
cl0
gll
g12

·
·

23
23
23
23
99
23

99
50
99
50
23
50

lE6
lE6
lE-15
lE-15
22 32 lE-6
32 22 lE-6

·POLE AT 159 MHz
r25
r26
ell
e12
g13
g14

·
·

24
24
24
24
99
24

99
50
99
50
24
50

lE6
lE6
lE-15
lE-15
23 321E-6
3223 lE-6

·COMMON-MODE GAIN NETWORK WITH ZERO AT 20kHz
r29
r30
15
16
917
918

·
·

26
26
27
28
99
26

27
28
99
50
26
50

lE6
lE6
7.9575
7.9575
3332 lE-ll
3233 lE-ll

• POLE AT 159 MHz
r32 31
r33 31
e15 31
e16 31
g19 99
g2031

·
·

99
50
99
50
31
50

lE6
lE6
lE-15
lE-15
24 321E-6
32 241E-6

• OUTPUT STAGE
r34
r35
r36
r37
17
g21
g22
g23
g24
v6
v7
d5
d6
d7
d8
d9
dl0

·

32
32
33
33
33
36
37
33
50
34
33
31
35
99
99
50
50

99
50
99
50
38
50
50
99
33
33
35
34
31
36
37
36
37

20.0E3
20.0E3
60
60
2.9E-7
31 33
33 31
99 31
31 50
1.7
1.7
dx
dx
dx
dx
dy
dy

16.6666667E-3
16.6666667E-3
16.6666667E-3
16.6666667E-3

·

• MODELS USED
omodel qx NPN(BF=2500)
omodel dx
D(IS=lE-15)
omodel dy
D(IS=lE-15 BV=50)
oends OP-64

• POLE AT 100 MHz
r21
r22
e7
c8
99
g10

22
22
22
22
99
22

99
50
99
50
22
50

lE6
lE6
1.59E-15
1.59E-15
19 321E-6
32 19 lE-6

FIGURE 11 b: OP-64 SPICE Net-List

2-224 OPERATIONAL AMPLIFIERS

REV. A

High-Speed, Current Feedback
Operational Amplifier
OP-160 I

r.ANALOG
WDEVICES
FEATURES
•
•
•
•
•
•
•

Easy To Use - Drives Large Capacitive Loads
Very High Slew Rate (Av +1) .................... 1300 V/~s Typ
Bandwidth (Av = +1) .............•........................... 90MHz Typ
Low Supply Current .....................•.................... 6.5mA Typ
Bandwidth Independent of Gain
Unity-Gain Stable
Power Shutdown Pin

=

Slew rate of the OP-160 is typically 1300V/~s and is guaranteed
to exceed 1000V/~s.ln addition, the OP-160's current feedback
design has the added advantage of nearly constant bandwidth
versus gain. In a gain of + 1 the -3dB bandwidth is 90MHz! The
OP-160 also requires only 6.5mA of supply current, a considerable power savings over other high-speed amplifiers.
Applications using the OP-160 can be implemented with the same
circuit assumptions utilized for conventional voltage feedback
op amps. With its high speed and bandwidth, the OP-160 is ideal
for a variety of applications including video amplifiers, RF amplifiers, and high-speed data acquisition systems.

APPLICATIONS
•
•
•
•
•

topology for very high slew rate and wide bandwidth performance.

High-Speed Data Acquisition
Communication Systems/RF Amplifiers
Video Gain Block
High-Speed Integrators
Driving High-Speed ADCs

The OP-160 is an easy-to-use alternative to the AD844, AD846,
EL2020 and EL2030.
For applications requiring a high-speed, wide bandwidth dual
amplifier, see the OP-260.

ORDERING INFORMATION t
TA =+2SoC
V,osMAX
(mV)
5.0
5.0
5.0

PACKAGE
CERDIP
B-PIN
OP160AZ'
OP160FZ

PLASTIC
a·PIN

LCC
20·CONTACT
OP 160ARC/883

OP160GP
OP160GSrt

OPERATING
TEMPERATURE
RANGE
MIL
XIND
XIND

• For devices processed in total compliance to MIL-STD-883, add 1883 after part
number. Consult factory for 883 data sheet.
t Burn-in is available on extended industrial temperature range parts in CerDIP
and plastic packages.
It For availability and burn-in information on SO package, contact your local sales
office.

GENERAL DESCRIPTION
The OP-160 is an easy-to-use high-speed, current feedback op
amp. Designed to handle large capacitive loads, the OP-160
resists unstable operation. The OP-160 combines PMI's highspeed complementary bipolar process with a current feedback

FAST SETTLING (0.01%)

Av

REV. B

=-1, +10V STEP INPUT

PIN CONNECTIONS

Ves NULL

-IN

N.C•

• IN

N.C.
-IN

8-PIN EPOXY MINI-DIP
(P-Suffix)

V+

N.C.

N.C.

+IN

OUT

8-PIN CERDIP
(Z-Suffix)
8-PINSO
(S-Suffix)

20-CONTACT LCC
(RC-Suffix)

DRIVES CAPACITIVE LOADS

Av = +1, C L = 1000pF

OPERA T10NAL AMPLIFIERS 2-225

II

OP-160
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage ...................•............................................. ±18V
Input Voltage ....•......•..............................••..•..•.. Supply Voltage
Differential Input Voltage ................................................... ±1V
Inverting Input Current ....................••......•••. ±7mA Continuous
...............................................•...................... ±20mA Peak
Output Short-Circuit Duration ........................................ 10 sec
Operating Temperature Range
OP-160A (Z. RC) ....•.........••..........•......••••.. -55°C to + 125°C
OP-160A.F (Z) ............................................. -4O°C to +85°C
OP-160G (p.S) .•.•••..•....................•••.•••••••.•••• -40°Cto+85°C
Storage Temperature (Z. RC) ..........•.....••.•... -65°C to + 175°C
(P. S) ........••..•......••••..............•..••......•••...•... -65°Cto+150°C
Junction Temperature (Z. RC) .....•..•••••••.•••••• -65°C to + 175°C
(P. S) ............................•............•..••.••••..•..•. -65°Cto+150°C
Lead Temperature (Soldering. 10 sec) .•..••••..............•. +300°C

8 1A (Note 2)

PACKAGE TYPE

UNITS

8 1C

8-Pin Hermetic DIP (Z)

148

16

·CIW

8-Pin Plastic DIP (P)

103

43

·CIW

98

38

·CIW

158

43

·CIW

20-Contact LCC (RC)
8-Pln SO(S)

NOTES:
1. Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2. 8'A is specified for worst case mounting conditions, l.e., a'A is specified for

dkvice in socket for CerDIP, P·DIP, and LCC packages; 8~ is specified for
device soldered to printed circuit board for SO package.

ELECTRICAL CHARACTERISTICS at Vs = ±15V. V CM = OV. RF = 820Q, TA = +25°C, unless otherwise noted.
PARAMETER

SYMBOL

Input Offset
Voltaga

VIOS

Input Bias
Current
Input Bias Current
Common-Mode

lB.
Ie-.

CONDITIONS

MIN

OP-160AlF
TYP MAX

Noninverting Input

Inverting Input

MIN

OP-160G
TYP MAX

UNITS

5

mV

2

5

0.2
6

1
20

0.4
10

1,5
30

J1A

40
30

75
75

50
40

125
125

nAN

1
20

5
50

1,5
25

10
75

nAN

VCM = ±11V
Noninverting Input

Rejection Ratio

CMRRI B•
CMRRI B_

Input Bias Current
Power Supply
Rejection Ratio

PSRRI B•
PSRRI B_

Noninverting Input

CMR

VCM = ±11V

60

65

60

65

dB

Power Supply
R;jection

PSR

Vs =±9Vto±18V

74

80

74

80

dB

Open·Loop
Transimpedance

RT

RL = SOOO
Vo = ±10V

3

4

3

4

MO

Input Voltage
Range

IVR

(Note 1)

±11

±11

V

Output Voltage
Swing

Vo

RL = SOOO

±11

±11

V

Output Current

10

Vo = ±10V

±35

Supply Current

Isv

No LO,ad

Common-Mode

Rejection

Slew Rate

Inverting Input
Vs = ±9Vto±18V
Inverting Input

6.5

Av= +1. Vo =±10V,
RL = SOOO, Test at Vo = ±5V

All Grades

Av;" +2, VO =±10V,
RL '= 5000,TestatVo = ±5V

Op·160A
Op·160F
OP'160G

SR

2-226 OPERA TIONAL AMPLIFIERS

±35

+60/-45

8

6.5

1300

rnA

+60/-45

8

rnA

1300
VII'S

1000
800

1300
1300
800

1,300

REV. B

OP-160
ELECTRICAL CHARACTERISTICS at Vs =±15V, VCM = OV, RF = 8200, TA = +25°C, unless otherwise noted. Continued
OP-160G

OP-160A/F
PARAMETER
Rise Time

-3dB Bandwidth

SYMBOL

CONDITIONS

tR

Av=+1
Av=-I

BW

-3dB Point
RL =5oon

MIN
Vo=±IOOmV
Av=-I
AV=+I
Av=+2

TYP

MAX

MIN

TYP

MAX

UNITS

4
6.4

4
6.4

ns

55
90
65

55
90
65

MHz

125
75

125
75

ns

Settling Time

t.

Av=-I,IOVStep
0.01%
0.1%

Input Capacitance

CIN

Noninverting Input

4

4

pF

Input Resistance

RIN

Noninverting Input
Inverting Input

17
60

10
60

Mn
n

Voitage Noise
Density

e"

f

= 1kHz

5.5

5.5

Current Noise
Density

f
i

= 1kHz
Noninverting Input
Inverting Input

5
20

20

0.004

0.004

%

0.04

0.04

%

0.04

0.04

2.3

2.3

Total Harmonic

Distortion

"

THD

Differential Gain

Dilferential Phase
Disable Supply

IsVDrS
Current
NOTE:
1. Guaranteed by CMR test.

REV. B

f

= IkHz,A v = +1,
Vo = 2V RMS ' RL = soon

f

=3.58MHz

Av= +1, RL = 500n

f

=3.58MHz
Av= +1, RL = soon
DISABLE =OV
No Load

-

nV/y'Hz

pAlv'Hz

-

degrees

rnA

OPERA TIONAL AMPLIFIERS 2-227

OP-160
ELECTRICAL CHARACTERISTICS at Vs

=±15V, V CM = OV,

RF =

8200, -55°C ~ TA ~ +125°C, for the OP-160A, unless other-

wise noted.

OP-160A
PARAMETER

SYMBOL

Input Offset Voltage

V,OS

Average Input Offset
Voltage Drift

TC vos

CONDITIONS

MIN

TYP

MAX

UNITS

3

8

rnV

10

J!.VI'C

la+
la_

Noninverting Input
Inverting Input

Input Bias
Current CommonMode Rejection

CMRRl a+
CMRRl a_

VCM =±10V
Noninverting Input
Inverting Input

55
45

150
150

nAN

Input Bias
Current Power
Supply Reiection Ratio

PSRRl a+
PSRRl a_

Vs =±9VtO±18V
Noninverting Input
Inverting Input

2
40

10
100

nAN

Common-Mode
Rejection

CMR

VCM =±10V

56

60

dB

Power Supply
Rejection

PSR

Vs =±9VtO±18V

70

76

dB

Open-Loop
T ransimpedance

RT

RL =5000
Vo =±10V

1.75

3

MO

Input Voltage
Range

IVR

(Note 1)

±10

V

Output Voltage
Swing

Vo

RL =5000

±10

V

Supply Current

ISY

No Load

Input Bias CUrrent

0.35
12

2
30

J!.A

6.75

9

rnA

NOTE:
t. Guaranteed by CMR test.

2-228 OPERA TIONAL AMPLIFIERS

REV. B

OP-160
ELECTRICAL CHARACTERISTICS atVs =±15V VCM = OV, RF = 8200, -40·C $

TA $

+85·C, forthe OP-160F/G, unless

otherwise noted.

OP-160F
SYMBOL

Input Offset
Voltage

VIOS

Average Input
Offset Voltage

TCV os

Input Bias
Current

IB+
IB_

Noninverting Input
Inverting Input

0.3
10

30

0.5
15

3
40

CMRRI B+
CMRRI B_

VCM =±10V
Noninverting Input
Inverting Input

45
35

150
150

55
45

250
250

nAN

PSRRI B+
PSRRI B_

Vs =±9Vto±1aV
Noninverting Input
Inverting Input

1.5
30

10
100

2.5
3.5

20
150

nAN

Common· Mode
Rejection

CMR

VCM =±10V

56

62

56

62

dB

Power Supply
Rejection

PSR

Vs = ±9V to ±1aV

70

ao

70

ao

dB

Open·Loop
Transimpedance

RT

RL = soon
Vo =±10V

1.75

3

1.75

3

Mn

Input Voltage
Range

IVR

(Note 1l

±10

±10

V

Output Voltage
Swing

Vo

RL = soon

±10

±10

V

Supply Current
Current

ISY

No Load,
Both Amplifiers

Input Bias

Current Common·
Mode Rejection Ratio
Input Bias

Current Power
Supply Rejection Ratio

CONDITIONS

MIN

OP-160G

PARAMETER

TYP

MAX

2.75

a

MIN

10

6.75

9

TYP

MAX

UNITS

2.75

mV

10

I'V/'C

6.75

9

I'AI

mA

NOTE:
1. Guaranteed by CMR test.

REV. B

OPERA T10NAL AMPLIFIERS 2-229

OP-160
DICE CHARACTERISTICS

1.
2.
3.
4.
5.
6.
7.
8.

VosNULL
-IN
+IN
VVosNULL
OUT
V+
DISABLE

DIE SIZE 0.071 x 0.099 inch, 7,029 sq. mils
(1.80 x 2.52 mm, 4.54 sq. mm)

WAFER TEST LIMITS at Vs

= ±15V, VCM = OV, RF = 8200, TA = +25°C, unless otherwise noted.
OP-160GBC

PARAMETER

SYMBOL

UMITS

UNITS

5

mVMAX

Inverting Input

1.5
30

vA MAX

Mode Rejection Ratio

CMRRI B+
CMRRI B_

V CM =±llV
Noninverting Input
Inverting Input

125
125

nAN MAX

Input Bia.
Current Power
Supply Rejection Ratio

PSRRI B+
PSRRI B_

Vs a±9Vto±18V
Nonlnverting Input
Inverting Input

10
75

nAN MAX

CMR

VCM =±ltV

60

dBMIN

PSR

V s =±9Vto±18V

74

dBMIN

RT

RL =5000
Vo =±10V

3

Mil MIN

±11

VMIN

±11

VMIN

8

mAMAX

Input Ollset Voltage

V,OS

Input Bias Current

IB+
IB_

Input Bias

Current Common·

Common-Mode

Rejection
Power Supply
Rejection
Open-Loop
Transimpedance

CONDITIONS

Noninverting Input

Input Voltage Range

IVR

Output Voltage
Swing

Vo

RL =5000

Supply Current

ISY

No Load

NOTES:
1. Guaranteed by CMR test.
Electrical tests are perlormed at waler probe to the limits shown. Due to variations in assembly methods and normal yield loss. yield alter packaging is not guaranteed for
standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembfy and testing.

2-230 OPERATIONAL AMPLIFIERS

REV.B

OP-160
TYPICAL PERFORMANCE CHARACTERISTICS

SLEWRATEvs
NONINVERTING GAIN
2500

~

:;:

~

'" \.:,

1000

w

'"

RISING

~a:

,~

..J

TA=+25'C
RF= 820Q
VO=±10V
Vs=±15V

2000

1500

w

~

:;:

......:: r--

500

RISING

r- r -

r--+-.

1500

o

5

1

8

6

9

1000

I'.

o

...... r-Ioo.

r-

-5 -ti
GAIN

PHASE SHIFT vs FREQUENCY
Av=+1

-3dB BANDWIDTH vs
SUPPLY VOLTAGE
Av=+1

iii
w
w
a: -90
w -135

....U-

-190

'"w

-225

s:

:I:

e

~g/

Q.

-315
-360

....

80

~

75

~

..,
'?

TA =+25°C
RF= 8200
VS =±15V

I

iii
w
w
a:

"

~
t;:

-135

'"'"w«

-225

s:

:I:

Q.

r-RLI=5~0

-90 r -

60

100

2

filii_

1/

1S

..-

/

iii

:!:.

z
:;;:

=+25°C

TA

-360

RF = 8200
VS=±15V
10
FREQUENCY (MHz)

100

i"( -'\

-

-5

18

10
FREOUENCY (MHz)

1

-

-10

-

RL=5OO0
2000
500

I

0
-45

iii
w
w -so _RL=5000
2000
a:
500
w -135 !:

~
~ .......

:I:

'"w~

:I:
Q.

1

10
FREQUENCY (MHz)

100

..... IiiIIIII

-180
-225

~.

-270
-315
-360

11111

-15

100

PHASE SHIFT vs FREQUENCY
A v =+5

"
e.
....

z

:;;:
-5

RL=50Dn
2000-,\
500,

-1S

6
8
10 12 14 16
±SUPPLY VOLTAGE (VOLTS)

:!:.

-315

0

-10

iii

"

TA=+25°C
RF= 8200
VS=±1SV
NORMALIZED
TO OdS

10

III

2000
500

100

GAIN vs FREQUENCY
Av=+2

TA = +25°C
RF= 8200
Vs =±15V
NORMALIZED TO OdB

10

-270

10
FREQUENCY (MHz)

1

-9 -10

GAIN vs FREQUENCY
Av =+5

15

-180

REV. B

-B

I
I

PHASE SHIFT vs FREQUENCY
Av=+2

-45

-7

"

70
65

10
FREQUENCY (MHz)

11

-4

85

<>

CD
CD

0

-3

:I:

~ -270

:I:

-2

TA'=+2J,C
RF= 8200
RL=5oon

"N

RL=~~O~ 'i

f"

-10

95
90

-45

-

-15

-1

II 1111

•

500~

r--......

GAIN

0

III
Ilt=5l~
2oo0~

FALLING

500

10

TOOdB

5

...... i'..

~

'"

TA=+25'C
RF= 82Dn
Vs =±15V
NORMALIZED

10

r- A~

FALLlNG- I--

"e.

15

2500

TA =+25°C
RF = 8200
Vo=±10V
VS=±15V
RL=5000

2000

<:.

GAIN vs FREQUENCY
Av=+1

SLEWRATEvs
INVERTING GAIN

TA=+2S'C
RF= 8200
Vs =±1SV
10
FREQUENCY (MHz)

100

OPERA TIONAL AMPLIFIERS 2-231

OP-160
TYPICAL PERFORMANCE CHARACTERISTICS Continued

GAIN vs FREQUENCY
Av = +10

PHASE SHIFT vs FREQUENCY
Av=+10

T~=I+~d~1

TA = +25°C
R,= 820n
Vs =±15V
NORMALIZED TO OdS

5

iiJ
w

UJ

a:

~



n-

7A13

PLUG~N

7A13 PLUG-IN

lk1l
300pF
+15V

The test circuit, built on a ~opper clad circuit board, has a FET
input stage which maintains extremely low loading capacitance
at the artificial sum node. Preceding stages are complementary
emitter follower stages, providing adequate drive current for a
50n oscilloscope input. The OP-97 establishes biasing for the
input stage, and eliminates excessive offset voltage errors.
TRANSIENT OUTPUT IMPEDANCE
Settling characteristics of operational amplifiers also includes an
amplifier's ability to recover, i.e., settle, from a transient current
output load condition. An example of this includes an op amp
driving the input from a SAR type AID converter. Although the
comparison pOint of the converter is usually diode clamped, the
input swing of plus-and-minus a diode drop still gives rise to a
significant modulation of input current. If the closed-loop output
impedance is low enough and bandwidth of the amplifier is sufficiently large, the output will settle before the converter makes
a comparison decision which will prevent linearity errors or
missing codes.
Figure 12 shows a settling measurement circuit for evaluating
recovery from an output current transient. An output disturbing
current generator provides the transient change in output load
current of 1mA.Asseen in Figure 13, theOP-160 has extremely
fast recovery of BOns, (to 0.01 %), for a 1mA load transient. The
performance makes it an ideal amplifier for data acquisition
systems.

VRE ,

• NOTE: DECOUPLE CLOSE

TOGETHER ON GROUND PLANE
WJTH SHORT LEAD LENGTHS

FIGURE 12: Transient Output Impedance Test Fixture

2-240 OPERA TIONAL AMPLIFIERS

FIGURE 13: OP-160's Extremely Fast Recovery Time from a
1mA Load Transient to 1mV (0.01%)

REV. B

OP-160
+15V

.1.0I'F

O.1JLF~

RPOT : Hill TO 10kn

~=

;5,.:6::"-_-0 OUT

II

c::8_ _-o PISABLE

1kn

v2V

n

ov--.J

L

FIGURE 14: Input Offset Voltage Nulling
OFFSET VOLTAGE ADJUSTMENT
Offset voltage is adjusted with a 20kn potentiometer as shown
in Figure 14. The potentiometer should be connected between
pins 1 and 5 with its wiper connected to the V+ supply. The
typical trim range is ±40mV.
DISABLE AMPLIFIER SHUTDOWN
Pin 8 of the OP-160, DISABLE, is an amplifier shutdown control
input. The OP-160 operates normally when Pin 8 is left floating.
When greater than 1OOO~A is drawn from the DISABLE pin, the
OP-160 is disabled. To draw current from the DISABLE pin, an
open collector output logic gate or a discrete NPN transistor can
be used as shown in Figure 15. An internal resistor limits the
DISABLE current to around 500~A if the DISABLE pin is
grounded with the OP-160 powered by ±15V supplies. These
logic interface methods have the added advantage of level

-15V

FIGURE 16: DISABLE Turn-On/Turn-Off Test Circuit

shifting the TTL signal to whatever supply voltage is used to
power the OP-160.
In the DISABLE mode, the OP-160 maintains 40dB of input-tooutput isolation if the input signal remains below ±1.5V. Output
resistance is very high, over 100kQ, if the output is driven by
signals of less than ±1.5V. Higher signals will be distorted.
Figure 16 shows a test circuit for measuring the turn-on and
turn-off times for the OP-160. The OP-160 is in a gain of + 1 with
a + 1V DC input. As the input pulsetothe inverter rises its output
falls, drawing current from the DISABLE pin and disabling the

v+

2V

n

ov--.J

L

l'-_-Ir.

kn
o-.,,5I/o

v-

LOGIC GATE
WITH OPEN
COLLECTORIDRAIN

OUTPUT

v-

FIGURE 15: Simple circuits allow the OP-160 to be shut down.

REV. B

OPERATIONAL AMPLIFIERS 2-241

OP-160
+15V

a)
OUTPUT

11J.S.±1V

SQUARE WAVE
VOUT

yS'----......--OV,N
LOGIC INPUT

500
1kll

b)
OUTPUT

-15V

FIGURE 18: Overdrive Recovery Test Circuit
LOGIC INPUT

FIGURE 17: (a) OP-160 tum-on and tum-off performance. (b)
Expanded scale showing tum-on performance of the OP-160.
Be aware of the high-frequency spike during tum-on.
amplifier. The output voltage delay is shown in Figure 17 and
takes 200>1-s to reach ground. The turn-on time is much quicker
than the turn-off time. In this situation as the input to the inverter
falls its output rises, returning the OP-160 to normal operation.
The amplifier's output reaches its proper output voltage in
450ns.

OVERDRIVE RECOVERY
Figure 19 shows the overdrive recovery performance of the op160. Typical recovery time is 120ns from positive and negative
overdrive.

FIGURE 19: The OP-160 recovers from both positive and
negative overdrive in 120ns.

+15V

APPLICATIONS
NONINVERTING AMPLIFIER
The OP-160 can be used as a voltage-follower or noninverting
amplifier as shown in Figure 20. A currentfeedback amplifier in this
configuration yields the same transfer function as a voltage feedbackopamp:

VOOT = 1 + R:!

Y,N

R,

Remember to use a 820Q feedback resistor in voltage-follower
applications.
In non inverting applications, stray capacitance at the inverting input of a current feedback amplifier will cause peaking which will increase as the closed-loop gain decreases. The gain setting resistor, R, ' is in parallel with this stray capacitance creating a zero in the

-15V

FIGURE 20: The OP-160 as a voltage fol/oweror noninverting
amplifier.

2-242 OPERA TIONAL AMPLIFIERS

REV. B

OP-160
closed-loop response. For large non inverting gains, R, is small,
creating a very high-frequency open-loop pole which has limited effect on the closed-loop response. As the non inverting gain is decreased, R, becomes larger and the stray zero becomes lower in
frequency, having a much greater effect on the closed-loop response.
To reduce peaking at low noninverting gains, place a series resistor, Rc ' in series with the noninverting input as shown in Figure 20.
This resistor combines with the stray capacitance atthe noninverting
inputto form a low-pass fi~erthat will reduce the peaking. The value
of Rc should be determined experimentally in the actual PCB layout. Less peaking will occur in inverting gain configurations since
the inverting input is a virtual ground which forces a constant voltage across the stray capacitance.
A common practice to stabilize voltage feedback op amps is to use
a capacitor across the feedback resistance. This creates a zero in
the voltage feedback amplifier response to offset the loss of phase
margin due to a parasitic pole. In current feedback amplifiers, this
technique will cause the amplifier to become unstable because the
closed-loop bandwidth will increase beyond the stable operating
frequency.
INVERTING AMPLIFIER
The op- t 60 is also capable of operation as an inverting amplifier
(see Figure 21). The transfer function of this circuit is identical to
that using a voltage feedback op amp:

USING CURRENT FEEDBACK OP AMPS IN INTEGRATOR
APPLICATIONS
The small-signal model of a current feedback op amp shown
earlier in Figure 3 assumes a non-varying value of feedback
impedance. A non-varying feedback impedance ensures that
the bandwidth of the amplifier does not extend beyond its 1800
phase shift point and create unwanted oscillations. In integrator
circuits, the feedback element is a capacitor whose impedance
does vary with frequency. By definition then, integrator applications using current feedback amplifiers should be unstable.
However, a simple trick, shown in Figure 22, enables highspeed, wide bandwidth current feedback op amps to be used in
integrator applications.
Resistor RF is placed between an artificial sum node and the
inverting input of the amplifier. This resistor maintains a minimum value of feedback impedance over all frequencies. At high
signal frequencies, the integrator capacitor, C 1 , is a short cirCUit;
the feedback impedance is equal to RF only and the amplifier
has maximum bandwidth. At low frequencies, C 1 adds to the
overall feedback impedance. This lowers the amplifier's bandwidth but not enough to affect the integrator's performance.

Voor = _R2
VIN

Rl

100kll

R,

C,

1kll
+15V

vFIGURE 22: An Integrator Using a Current Feedback Op Amp

-15V

FIGURE 21: The OP-160 as an inverting amplifier.

REV. B

OPERA TlONAL AMPLIFIERS 2-243

2

OP-160
Figure 23 shows the gain and phase performance of the integrator. The integrator has the desired one-pole response for signal
frequencies
fc» 1/(21tR2C l ) '" 16kHz.
A more strenuous test of integrator performance is the pulse
response. Ideally, this should be a linear ramp. The current
feedback integrator's pulse response is exhibited in Figure 24.
The response closely approximates the ideal linear ramp.

i"'-.....

2

40

.....

30

b~,~
i'I

20
10

a;z
 ' ' - - - - - - -..................'''''OVOUT

FIGURE 23: Gain and phase response of the integrator shows
a one-pole response.

i

lOl'F

,
::;=cs
,
V-

FIGURE 26: A current feedback op amp configured for noninverting gain. Parasitic capacitances affecting gain are also
shown.
FIGURE 24: Pulse response of the current feedback integrator.

f=2MHz.
ACHIEVING FLAT GAIN RESPONSE WITH CURRENT FEEDBACKOPAMPS
In high-performance systems, flat gain response is often required. Current feedback op amps provide wide bandwidth performance but even these may not fulfill the gain flatness requirements of some systems.
Current feedback op amps exhibit both gain roll-off and peaking
as shown in Figure 25. Peaking is primarily due to parasitic

capacitance; gain roll-off is determined by the amount and type
of load on the amplifier. Peaking is controlled by careful layout
and circuit design; however, its cause can provide a method of
improving gain flatness over a desired frequency range.
Consider the noninverting amplifier of Figure 26. The gain
equals:

1+

R2
R,tIZ(CcIICg)

and at low frequencies
Av = 1 + ~ = 1 + 910n = 2

R1

2-244 OPERA TlONAL AMPLIFIERS

910n

REV. B

OP-160
At higher frequencies the gain increases or peaks due to the
effect of the parasitic capacitance, Cs ' on the gain equation. Any
capacitance at the inverting input will create a zero in the amplifier's response. This fact car] be used to compensate for gain
roll-off due to loading on the amplifier.
Begin by measuring or estimating the amplifier's -6dB point
(this is the frequency at which the output signal is half its original
amplitude). This can be easily determined from a network
analyzer plot of the amplifier's frequency performance. From
this the amount of capacitance, Cc ' which will double the gain
at the -6dB frequency and restore the original gain, can be
determined.

will be increased. At higher gains, gain flatness can be significantly improved without gain peaking. Figure 28 depicts the
OP-160 with Av = +10. In this example f-6dS ~ 22 MHz so,
C = 9pF +
S

1
21t(91 Q)22MHz

+

-::-~-,..-,-,-:-:c-.,-

21t(820Q)22MHz

= 97pF
The nearest standard capacitor value is 100pF.
Gain performance is flat to 0.5dB to 30M Hz and the amplifier's
-3dB point is 38MHz. This gives the amplifier an effective gainbandwidth of 380MHz! Compensating the OP-160 does not effect the pulse response as shown in Figure 29.

From the -6dB frequency, Cc can be calculated:

Cc = Cs +

+

1
21tR1 f-6dS

26

21tR2t6dS

for non inverting configuration, where C s is the combination of
the amplifier's input capacitance and the stray capacitance at
the input.
In the example shown,
Cs = 9pF = OP-160 input capacitance (4pF) + stray capacitance
(5pF)
1
+ _ _ _ _ __
C =9pF+
s
21t(910Q)32MHz
21t(910Q)32MHz

20

«


1000

"

o
'0

'00

II
Ok

FREQUENCY (Hz)

'0'

OPERA TIONAL AMPLIFIERS 2-255

OP-249
TYPICAL PERFORMANCE CHARACTERISTICS Continued

DISTORTION vs FREQUENCY

"'"~=~###F="'i='F=H

~.oo,~§_~Tll ~!

tOO

DISTORTION vs FREQUENCY

DISTORTION vs FREQUENCY

~v.:O:- :1~05Vv.·pC

l~ __ i_L.LL~.Ul.. __ ....i_..i-_i_U.J
:"J",:
..
L.L,: iW.''---..0-'-'-h''CT+t--t'---r'-j-'-;-' RL=10kQ i
_

',,'

i"

~.ool~§.~--Ljle~~ . __--,_,_~ll!
DISTORTION vs FREQUENCY

~"::+=i=+---:-=-:::
---~

i~i~~;:~

: : -:

l"i

Av;;10 2~

DISTORTION vs FREQUENCY

~-+::: :-=----r
.1 .•

l :;~it::l

i

-:-'"~~

:~--:

: , '! :::~:~I

I Ay=+10 I

1. 2.

.
. 1ll111~J
.,.

•,,,,V

Ii
~

-l11V

i.

~

9
BANDWIDTH (O.1H2 TO 10Hz)

Va .a15V

"'::!'~,.

Va. al5V

••
1\

..

~

1\
100k

1M

FREQUENCY (Hz)

2-256 OPERA TIONAL AMPLIFIERS

10M

AvcL=+10~

,.

-20

10k

AvcL·+' .......

~

-,. "TI';;,;'
UlIll~
1k

3D

I.

'ffi'lilil"

U

tl;~~1

Vs=""5V

l.;~~'2,~

3.

50

I~~I••~-hl

1111111I1

50

Ta.l: +25°C

CLOSED-LOOP
OUTPUT IMPEDANCE
vs FREQUENCY

CLOSED-LOOP GAIN
vs FREQUENCY

LOW FREQUENCY NOISE

100II

ili':r'--·'•• 1"-

.

•,

IIIILOO f'
1k

11*

[}
~
100k

'M

'.M

FREQUENCY Ig)

REV. A

OP-249
TYPICAL PERFORMANCE CHARACTERISTICS Continued

SMALL·SIGNAL OVERSHOOT
vs LOAD CAPACITANCE

MAXIMUM OUTPUT SWING
vs FREQUENCY

,

3D

~

25

~

20

I
!;

go

..
8

AL= 1Dku

......

l

15

1k

100k

10k

o

10M

1M

//

,

b

10

'\

i!

~

I

t-....

-Ii

-20

320

280

±5

..

........

±10

±15

200

-

180

5.4

I-"

~

~

~

~

~

~

TEMPERATURE lOCI

Vos DISTRIBUTION
(J PACKAGE)

Vos DISTRIBUTION
(PPACKAGE)
180

T;.+J.C I

J.C

TAI . .

=

150

Vs ±15V
350 x OP249
(700 OP AMPS)

-

1
!z

5.6

~

1l
~

~

5.4 f--~""'""""'~+-=....-----i

5.2 1---+---+---'--+----1

5.2_

±20

-

I--

SUPPLY VOLTAGE (YOLTS)

140

=

5.0 O~--.J....--..J,0'---,:':5-----:'2O

m

SUPPLY VOLTAGE (VOLTS)

TCVOS DISTRIBUTION
(J PACKAGE)

I

Vs =±15V

Vs ±15V
415 x OP249
(830 OP AMPS)

240 f-t-+--+--+--t---1i---t -4Q°C to +85°C

--

(700 OP AMPS)

210 ......

120

240

~

V

~

!';

........... ........
o

5.S f---+---+---+-----i

"

-10

10k

SUPPLY CURRENT vs
SUPPLY VOLTAGE

V'~±15VI

I1l 5.5

-15

1k

6.0,---,---,.---....,---,

g

..........

100

LOAD RES4STANCE un

5.S

./

~
III

500

NO lOAD

/

!l

3D0

200

SUPPLY CURRENT
vs TEMPERATURE

6.0

...

RL=2kn

~

400

LOAD CAPACITANCE (pFI

TA=+~

~ 10

'"
o~-~~~~~--~~~~

100

o

OUTPUT VOLTAGE SWING
vs SUPPLY VOLTAGE

15

)
A""J'+5

FREQUENCY (Hz)

20

I

._

20

o

+'Iom= I-Voml

NEGATIVE EDGE

40

~ 30

5

~

. / _I-/' ~=+1
POSI1TIVE EDGE

AVCL=+l

%

::!

~

:Ii

14 I-Vs =:±15V

70

" 10

;

TA' ;25.d

Vs
Rl=2kU
YIN = 100mvpl'

80

A VCL=+l

15

=±1~V

pIlTA.I+i5~
Vs =±15V

MAXIMUM OUTPUT VOLTAGE
vs LOAD RESISTANCE

I"-

--

150 f-+-+--+--+--t-f-t--t--+--+---i
~ 1~f-+-~~-+--t--r-t--t--r-+-i

J11 100

is

J11

80

r-

I=-

.01-+-+-~-+-+--1-+-+-~-+--1

120

50

80

40

so

1-+-+--l_:::::l,---I-+-+--+-++-1

40

20

3D

I-+-+--+---l-..!--.....
-+-+-+--l-H

o

o

-1 k -800 -600 -400 -200

0

200 400 600 800 1k

\Ios(.V)

REV. A

r-

-1 k --800 --600 -400 -200

0

200 400 600 800 1k

VosbN)

O~~~-L-L~~~~~
o .5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
(llyrC)

OPERA T10NAL AMPLIFIERS 2-257

OP-249
TYPICAL PERFORMANCE CHARACTERISTICS Continued

OFFSET VOLTAGE
WARM-UP DRIFT

TCVOS DISTRIBUTION
(PPACKAGE)
3DO

50

~;:".as.c-

210

Vs

INPUT BIAS CURRENT
VB TEMPERATURE
10k

.:l:1~Y

V. _:l:15V
Vcu-OV

(8300PAMPS)

240

r-

40

....~

210

"-

f-

~
g
Iii

it0

i-

.
so

i-

.... ....

r- f- fo

2

4

6

8

10 12 14 16 18

a

H

o

N

V

20

10

f-

30

30

i

1k

i
"

1DO

-~

10

~

/

V

o

1

(\lvre)

2

-'IL
~ I-"""

1

4

-75

-SO

-25

nilE AFTER POWER APPLIED IMINUTES)

BIAS CURRENT VB
COMMON-MODE VOLTAGE

BIAS CURRENT
WARM-UP DRIFT

.

10'

TA _+U-C
Vsu:1SV

25

50

tOO

12S

INPUT OFFSET CURRENT
VB TEMPERATURE

.

TA =+2S·C
Va _",15V

75

rC)

TEMPERATURE

v.

;.,SVI

VCM

=ov

40
10'

i
~.
"
I"

i

..
G
..;
~

1/

10'

30

10

10'
-15

-10

-6

10

o

15

1

20

t-

/

~
!i

10'

o

o

2

4

-75

10

-so

OPEN-LOOP GAIN
VB TEMPERATURE

..

12k
VI _:l:1!5V

...."\

FlL_2kO

k

TEMPERATURE

H

~

so
rc)

TEMPERATURE

2-258 OPERA TIONAL AMPLIFIERS

100

18

r-cJ

v. :"svi

.,NK ......

~ !=::::::

--

0

k

~

V
75

&E

AL=1OkO

.......

0

21

SHORT-CIRCUIT
OUTPUT CURRENT
VB JUNCTION TEMPERATURE

10k

~

-25

TIME AFTER POWER APPUED (MINUTES)

COMMON-MODE VOLTAQE (VOLTS)

1',...

V
50

V

~

~

m

0~

_

_

0

H

so

TEMPERATURE

n

r-

_

m

rC)

REV. A

OP-249
SIMPLIFIED SCHEMATIC (1/2 OP-249)
r-----------~~--~----~---o~

-IN

~--_+--+_------~~--+_----~--_o~

BURN-IN CIRCUIT

+3Yo-----=_!

a)
5110

OP-249

+18V

+3Yo-----=_!
SIc"
-18V

b)
LT10S7

APPLICATIONS INFORMATION
The OP-249 represents a reliable JFET amplifier design, featuring an excellent combination of DC precision and high speed. A
rugged output stage provides the ability to drive a 600a load and
still maintain a clean AC response. The OP-249features a largesignal response that is more linear and symmetric than previously available JFET input amplifiers - compare the OP-249's
large-signal reponse, as illustrated in Figure 1, to other industry
standard dual JFET amplifiers.
Typically, JFET amplifier's slewing performance is simply specified as just a number of volts/f.ls. There is no discussion on the
quality, i.e., linearity, symmetry, etc. of the slewing response.

REV. A

FIGURE 1: Large-Signal Transient Response. Av =+1.
V,N=20Vp.p'ZL =2/(g11200pF. Vs=:!:15V

OPERA TIONAL AMPLIFIERS 2-259

OP-249
The OP-249 was carefully designed to provide symmetrically
matched slew characteristics in both the negative and positive
directions, even when driving a large output load.
An amplifier's slewing limitation determines the maximum frequency at which a sinusoidal output can be obtained without
significant distortion. It is, however, important to note that the
nonsymmetric slewing typical of previously available JFET amplifiers adds a higher series of harmonic energy content to the
resulting response - and an additional DC output component.
Examples of potential problems of nonsymmetric slewing behaviour could be in audio amplifier applications, where a natural, low-distortion sound quality is desired, and in servo or signal
processing systems where a net DC offset cannot be tolerated.
The linear and symmetric slewing feature of the OP-249 makes
it an ideai choice for applications that will exceed the full-powerbandwidth range of the amplifier.

VERTICAL so"V/D1V
INPUT VARIATION

HORIZONTAL 5V/DIV
OUTPUT CHANGE

FIGURE 3: Open-Loop Gain Linearity. Variation in Open-Loop
Gain Results in Errors in High Closed-Loop Gain Circuits.
RL =6000, Vs =%15V

+v

RJ Y'N
50kQl

200""

-v

FIGURE 2: Small-Signal Transient Response, Av
ZL =2kOIl100pF; No Compensation, Vs %15V

=

=+ 1,

+V

'f

501d>

Supply decoupling should be used to overcome inductance and
resistance associated with supply lines to the amplifier. A 0.11'F
and a 1OI'F capacitor should be placed between each supply pin
and ground.

OFFSET VOLTAGE ADJUSTMENT
The inherent low offset voltage of the OP-249 will make offset
adjustments unnecessary in most applications. However,
where a lower offset error is required, balancing can be performed with simple external circuitry, as illustrated in Figures 4
and 5.

2-260 OPERA T10NAL AMPLIFIERS

=.V (~)
,

FIGURE 4: Offset Adjust for Inverting Amplifier Configuration

As with most JFET-input amplifiers, the output of the OP-249
may undergo phase inversion if either input exceeds the specified input voltage range. Phase inversion will not damage the
amplifier, nor will it cause an internal latch-up condition.

OPEN-LOOP GAIN LINEARITY
The OP-249 has both an extremely high open-loop gain of
1 kV/mV minimum and constant gain linearity. This feature ofthe
OP-249 enhances its DC precision, and provides superb accuracy in high closed-loop gain applications. Figure 3 illustrates
the typical open-loop gain linearity - high gain accuracy is assured, even when driving a 6000 load.

Vos ADJUST RANGE

R,
2001<11

-v

Y'N
FIGURE 5: Offset Adjust for Noninverting Amplifier
Configuration
In Figure 4, the offset adjustment is made by supplying a small
voltage at the noninverting input of the amplifier. Resistors Rl
and R2 attenuates the pot voltage, providing a %2.5mV (with V s
%15V) adjustment range, referred to the input. Figure 5 illustrates offset adjust for the noninverting amplifier configuration,
also providing a %2.5mV adjustment range. As indicated in the
equations in Figure 5, if R4 is not much greater than R2, there will
be a resulting closed-loop gain error that must be accounted for.

=

REV. A

OP-249
Settling time is the time between when the input signal begins to
change and when the output permanently enters a prescribed
error band. The error bands on the output are 5mV and 0.5mV,
respectively, for 0.1 % and .0.01 % accuracy.

Unity-gain stability, a low offset voltage of 300I-lV typical, and a
fast settling time of S70ns to 0.01 %, makes the OP-249 an ideal
amplifier for fast digital-to-analog converters.
For CMOS DAC applications, the low offset voltage of the OP249 results in excellent linearity performance. CMOS DACs, such
as the PM-7545, will typically have a code-dependent output
resistance variation between 11 kO and 33kO. The change in
output resistance, in conjunction with the 11 kO feedback resistor,
will result in a noise gain change. This causes variations in the
offset error, increasing linearity errors. The OP-249 features low
offset voltage error, minimizing this effect and maintaining 12bit linearity performance over the full scale range olthe converter.

Figure 6 illustrates the OP-249's typical settling time of S70ns.
Moreover, problems in settling response, such as thermal tails
and long-term ringing are nonexistent.

DAC OUTPUT AMPLIFIER

Since the DAC's output capacitance appears at the operational
amplifiers inputs, it is essential that the amplifier is adequately
compensated. Compensation will increase the phase margin, and
ensure an optimal overall settling response. The required lead
compensation is achieved with capacitor C in Figure 7.

FIGURE 6: Settling Characteristics of the OP-249 to 0.01%.

a) UNIPOLAR OPERATION
75U

REFERENCE

OR VIN CHI,"""",IV'-'''l

DATA INPUT

b) BIPOLAR OPERATION

REFERENCE

OR YlNo- I I

\

RF=2.5kn
RL=5000
Ys=:t15V

\.%

••

FREQUENCY (11Hz)

Vs·:t15V

0.1%

I-TA=25"C

T..,=25OC

NORMAUZED TO DdB

\
I

~

~ IIfz::

I

••

'00

..

-

100

-

.%

-.5

J

V
160

FREQUENCY (MHz)

190

220

250

280

310

340

SETTUNG TIME (ns)

PHASE vs FREQUENCY
Av=-10

II Iii
Lilli

••

\

\
.%\
\

,'

"F=~-

RL=5OOn

Vs=:t1SY

T,,=2fiOC

••

.00

..

FREQUENCY (MHz)

2-272 OPERA TIONAL AMPLIFIERS

-

100

II
130

160

••

'00

1.

Va =:t15V
~TA.25-C

RL= 5.1kn

5011<1,

NORMALIZED TO OdB

,

\

I
RLa2Mfr.
.~

..

10.1%

lson(

-

II
190 220 250 280
seTTUNG nilE (ns'

..........;;~

...

I

.%/

Y

"

111111

\0.1%

I

-8

\

FREQUENCY (MHz)

RF =2.5kO

1\

J

-3.5

:iJ'

GAIN vs FREQUENCY
Av=+1

.5

"L= son"!'Ii

TA=25"C

.... •

SETTLING TIME
vs OUTPUT STEP
Av=-10

.......... ...... ~L~J.iJ,1

RF= 2.5kn
Vs·:t15V

II

0.1"'-

I
1/
130

"L=.=~ ~~

..

\

I

-6

••

.... •

SETTLING TIME vs OUTPUT STEP
Av=-1

-6

......

:tIO

SUPPLY VOLTAGE (VOLTS)

\

-3'5

....

..

-

:t5

~~

"L" .~~ ~~
son-"

-.35

...
-'s

••

.00

GAil (ABSOLUTE)

-45

~

;I

!

'00

200

'"

/

200

i'

/

AL-SOOO

f4

/

~L=soon

"

Ii;

",.

AV= +10
TAlI2rC
Your =MAX SWING

BOO

Vs =:t1SY

.

GAIN vs FREQUENCY
Av=-1

SLEWRATEvs
SUPPLY VOLTAGE

SLEW RATE vs GAIN

310

340

-.5

•

••

.00

FREQUENCY (MHz)

REV.C

OP-260
TYPICAL ELECTRICAL CHARACTERISTICS Continued
SMALL-SIGNAL
-3dB BANDWIDTH
vs SUPPLY VOLTAGE

Av

.... -~~=.j""
50

=25"C

~

I

/

b

20

,.

/

~30

!

15

./

!,35

25

15

,.

I

1-_t--+-t-+l+H RL = son

Ii:

f---+-+-HttHt---+-++t+Mti

-80

-180

1

100

PHASE SHIFT vs FREQUENCY

GAIN vs FREQUENCY

PHASE SHIFT vs FREQUENCY

Av=+2

Av=+5

Av=+5

15

,.

T" = 2S-C

~

-225

,.

11111'""

-15

100

l:/

FREQUENCY (MHz)

.......... ~t--

,-90
iii

"L=l00n J

~~

FREQUENCY (MHz)

Ys=:t:15V

-180

j"':::
-5

-1.

1.

•

t=~lL
2OOn-~

TA=25"C

:t2:t:4 :t6 :t8 :t10 :t12 :t14 :t;16 :t18 :1;20
SUPPLY VOLTAGE (VOLTS)

~F"~.~

Ii:

NORMALIZED TO Gel

VS=:t1SV -+-+++++I--t-+-t-+-t+lfII

-360

-135

II

Vs =±15Y
f-TA=2&'C

soon

~ -225 1--+-+-I-+++IIl+--+-+-+-f+-h1II
~ ~.I--+-+-~++~--+--++++~

/

RF =2.51I:U

5~4V.4-1~rHl

~ -135

RF= 2.5kn

•o

I

Av= +2

Av= +1
~

RL =50U
_ TA

~

GAIN vs FREQUENCY

PHASE SHIFT vs FREQUENCY

=+1

~F~i.JJ

Rp=2.5tl:D
Vs =:t15Y
f- TA =25-C
NORMALIZED TO OdB

~

:'1:\

-315

Ii:
:;:

'"

1-270
..

-5

............: 1""'1"-

-1.

"L=l"""·=:

1

100

1.

son J

-180

:: -225

i-270

'r\

-15

....,

"L= 5.1""---<::

~ -135

"L=5.1"",

iD

~

-315

lsonl

~~II

-360

,.

100

FREQUENCY (MHz)

FREQUENCY (MHz)

PHASE SHIFT vs FREQUENCY

Av= +10

Av= +10

Vs =:t15V

GAIN vs FREQUENCY

,.

~F'=J..l.i

I I I I

Av= +50
"F='~5.ri

~

Itit

-135

Ii:

-180

:

-225

e.

;;:

..~

-90

r:::s ~
RL= S.lka

~~

=

TA_H-C

~~

-

NORMAUZED TO OdB

~

iD

rs

~
Z

'i

-5

'"

RLI: 5.1kO

-15 -

FREQUENCY (MHz)

REV.C

,.
FREQUENCY (MHz)

-20
100

f-

5OO---OV

OUT

(b)

(a)

FIGURE 7: Simplified noise models for the OP-260 in noninverting (a) and inverting (b) gain.
where:
EN =
en =
inn =
in;
=
Rs
AVCL =

=

total input referred noise
amplifier voltage noise
noninverting input current noise
inverting input current noise
source resistance
closed loop gain = 1 + R/Rl

For the inverting amplifier, the equivalent input voltage noise,
referred to the input, is:
en2 (1 + IAVLCI)2+ (R2 in;)2
IAvLCI
(l AVLCIl 2
assuming Rs « R1· AvCL = closed loop gain = -R 2/R 1 ·
En =

Typical values @ 1 kHz for the noise parameters of the OP-260
are:
en = 5.0nV/VHZ
inn
3.0pAlYHZ
in;
20.0pAlYHZ
SHORT CIRCUIT PERFORMANCE
To avoid sacrificing bandwidth and slew rate performance the
OP-260's output is not short circuit protected. Do not short the
amplifier's output to ground or to the supplies. Also, the buffer
output current should not exceed a value of ±20mA peak or
±7mA continuous.
POWER SUPPLY BYPASSING AND LAYOUT
CONSIDERATIONS
Proper power supply bypassing is critical in all high-frequency
circuit applications. For stable operation of the OP-260, the
power supplies must maintain a low impedance-to-ground over
an extremely wide bandwidth. This is most critical when driving
a low resistance or large capacitance, since the current required
to drive the load comes from the power supplies. A 10llF and

REV.C

O.1IlF bypass capacitor are recommended for each supply, as
shown in Figure 8, and will provide adequate high-frequency
bypassing in most applications. The bypass capacitors should
be placed at the supply pins of the OP-260. As with all high frequency amplifiers, circuit layout is a critical factor in obtaining
optimum performance from the OP-260. Proper high frequency
layout reduces unwanted signal coupling in the circuit. When
breadboarding a high frequency circuit, use direct point-to-point
wiring, keeping all lead lengths as short as possible. Do not use
wire-wrap boards or "plug-in" prototyping boards.
During PC board layout, keep all lead lengths and traces as
short as possible to minimize inductance. The feedback and
gain-setting resistors should be as close as possible to the inverting input to reduce stray capacitance at that point. To further reduce stray capacitance, remove the ground plane from
the area around the inputs olthe OP-260. Elsewhere, the use of
a solid unbroken ground plane will insure a good high-frequency
ground.

v.

v-

FIGURE 8: Proper power supplying bypassing is required to
obtain optimum performance with the OP-260.

OPERA TlONALAMPLIFIERS 2-279

OP-260
APPLICATIONS
NONINVERTING AMPLIFIER
The OP-260 can be used as a voltage-follower or non inverting
amplifier as shown in Figure 9. A current feedback amplifier in this
configuration yields the same transfer function as a voltage feedbackopamp:

Vour =1 +A2.
VIN

R1

Remember to use a 2.51<0 feedback resistor in voltage-follower
application.
In non inverting applications, stray capacitance at the inverting input of a current feedback amplifier will cause peaking which will increase as the closed-loop gain decreases. The gain setting resis.15V

tor, R, ' is in parallel with this stray capaqitance creating a zero in the
closed-loop response. For large noninverting gains, R, is small,
creating a very high frequency open-loop pole which has limited effeet on the closed-loop response. As the noninverting gain is decreased, R, becomes larger and the stray zero becomes lower in
frequency, having a much greatereffectontheclosed-loopresponse.
To reduce peaking at low noninverting gains, place a series resistor, Re, in series with the noninverting input as shown in Figure 9.
This resistor combines with the stray capacitance atthe noninverting
inputto form a low-pass filter that will reduce the peaking. The value
of Re should be determined experimentally in the actual PCB layout. Less peaking will occur in inverting gain configurations since
the inverting input is a virtual ground which forces a constant voltage across the stray capacitance.
A common practice to stabilize voltage feedback op amps is to use
a capacitor across the feedback resistance. This creates a zero in
the voltage feedback amplifier response to offset the loss of phase
margin due to a parasitic pole. In current feedback amplifiers, this
technique will cause the amplifier to become unstable because the
closed-loop bandwidth will increase beyond the stable operating
frequency. For the same reason, current feedback amplifiers will
not be stable in integrator applications.
INVERTING AMPLIFIER
The OP-260 is also capable of operation as an inverting amplifier
(see Figure 10). The transfer function of this circuit is identical to
that using a voltage feedback op amp:

• SEE TEXT

Vour __ A2
VIN -

~.

An optional offset voltage trim is shown in Figure 11.
VOUT
. 1 .R:z
YIN
R,
-15V

FIGURE 9: The OP-260 as a voltage follower or noninverting
amplifier.

AUTOMATIC GAIN CONTROL AMPLIFIER
One of the shortcomings of using voltage feedback op amps in an
Automatic-Gain-Controlamplifieristhatitsbandwidthdropsoffrapidly
as gain increases,limiting the useful bandwidth. However, for currentieedbackamplifiers, bandwidth is relatively independent of gain,

.15V

V.. o--wV-_~

-15V

FIGURE 10: The OP-260 as an inverting amplifier.

2-280 OPERATIONALAMPLIFIERS

-'5V
FIGURE 11: Optional offset voltage trim circuit for the OP-260.

REV.C

OP-260

lOOkz
3

MIL
XND
XND
XND
XND

For devices processed in total compliance to MIL-STD-883. add 1883 after part
number. Consult factory for 883 data sheet.
Burn~in is available on commercial and industrial temperature range parts in
CerDIP. plastic DIP. and TO-can packages.
It For availability and burn-in information on SO and PLCC packages, contact
your local sales office.

N.C.
17

GENERAL DESCRIPTION

OUTB

N.C.

t

The OP-271 is a unity-gain stable monolithic dual op amp featur·
ing excellent speed, 8.5V/IlS typical, and fast settling time, 21ls
typical to O. 01 %. The OP-271 hasa gain-bandwidth of 5MHz with
a high phase margin of 62°.

+INA
N.C.

LCC
(RC-Suffix)

+IN B
-INB

16-PINSOL
(S-Suffix)

EPOXY MINI-DIP
(P-Suffix)
8-PIN HERMETIC DIP
(Z-Suffix)

SIMPLIFIED SCHEMATIC (One of the two amplifiers is shown.)
r-~------~------.-----~--~--------------------------.---~----~--ov+

OUT

-INo--.....t-..,.....

L-----------------~--~--------~--------~~--~--4-~--~-o~

REV. B

OPERA TIONAL AMPLIFIERS 2-287

OP-271
The OP~271 offers outstanding DC and AC matching between
channels. This is especially valuable for applications such as
multiple gain blocks, high-speed instrumentation and amplifiers, buffers and active filters.

Lead Temperature (Soldering, 60 sec) ........................ +300°C
Junction Temperature (Tj ) .............................. -65°C to + 150C
Operating Temperature Range
OP-271 A ................................................... -55°C to + 125°C
OP-271 E, OP-271 F, OP-271G ................... -40°C to +85°C

The OP-271 conforms to the industry standard 8-pin dual op
amp pinout. It is pin compatible with the TL072, TL082,
LF412, and 1458/1558 dual op amps and can be used to
significantly improve systems using these devices.

PACKAGE TYPE

For applications requiring lower voltage noise, see the OP270. For a quad version of the OP-271, see the OP-471.

PARAMETER
Input Offset
Voltage

SYMBOL

CONDITIONS

'CIW

8-Pin Plastic DIP (P)

96

37

'CIW

20-Contact LCC (RC)

88

33

'CIW

8-PinSO(S)

92

27

'CIW

=±15V. TA =+25°C. unless otherwise noted.
MIN

OP-271A/E
TYP
MAX
75

Vas

Input Offset
Current

los

VCM =OV

Input Bias
Current

I.

VCM=OV

4

Inpul Noise
Voltage
Density

en

fa = 1kHz

7.6

Large-Signal
Voltage
Gain

Ayo

Input Voltage
Range

IVR

Output Voltage
Swing
Common·Mode
Rejection
Power Supply
Rejection
Ratio
Slew Rate

SR

Phase Margin

om

Ay=+1

62

Supply Current
(All Amplifiers)

ISY

No Load

4.5

Gain Bandwidth
Product

GBW

Channel
Separalion

UNITS

12

NOTES:
1. Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2. The OP-271 's inputs are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low noise performance. If differential
voltage exceeds ±1.0V, the input current should be limited to ±2SmA.
3. a' A is specified for worst case mounting conditions, i.e., a' A is specified for
d~vice in socket for CerDIP, P-DIP, and LCC packages; alA is specified for
device soldered to printed circuit board for SOL package. I

ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage ................................................................. ±18V
Differential Input Voltage (Note 2) ................................... ±1.0V
Differential Input Current (Note 2) ................................. ±25mA
Input Voltage .................................................... Supply Voltage
Output Short-Circuit Duration ................................ Continuous
Storage Temperature Range ........................ -65°C to + 150°C
ELECTRICAL CHARACTERISTICS at Vs

ale

134

alA (Note 3)

8-Pin Hermetic DIP (2)

MIN

OP-271F
TYP
MAX

MIN

OP-271G
TYP
MAX

UNITS

200

150

300

200

400

"'v

10

4

15

7

20

nA

20

6

40

12

60

nA

7.6

-

nVI Hz

7.6

Vo =,,10V
400
300

650
500

300
200

500
300

250
175

400

(Note 1)

,,12

,,12.5

,,12

,,12.5

,.12

,.12.5

V

Va

RL ~2kO

,,12

,,13

,,12

,,13

,.12

,.13

v

CMR

VCM =,.12V

106

120

100

115

90

105

dB

PSRR

V s =,.4.5VtO,.18V

CS

RL = 10kll
RL = 2kO

0.6
5.5

3.2

8.5

1.8
5.5

4.5

5
Va = 20V•••
= 10Hz (Note 2)

'a

125

175

8.5

5.5

62
6.5

125

2.4

5.6

V/mV

250

7.0

8.5
deg

62
6.5

",VN

4.5

6.5

mA

5

5

MHz

175

175

dB

Input CapaCitance C'N

3

3

3

pF

In6~~::~i~~~.~~de R'N

0.4

0.4

0.4

Mil

20

20

20

GO

2

2

2

"'s

Input Resistance
Common· Mode
Settling Time

R 1NCM

ts

Ay = +I,10V Step
to 0.01%

NOTES:
1. Guaranteed by CMR test.
2. Guaranteed but not 100% tested.

2-288 OPERA TIONAL AMPLIFIERS

REV. B

OP-271
ELECTRICAL CHARACTERISTICS at Vs = ±15V, -55·C:5 TA :5125·C for OP-271A, unless otherwise noted.
OP-271A
CONDITIONS

MIN

PARAMETER

SYMBOL

TYP

MAX

Input Offset Voltage

Vos

115

400

TCVos

0.4

Average Input
Offset Voltage Drift

UNITS
pV
pVloC

Input Offset Current

los

VCM = OV

1.5

30

nA

Input Bias Current

18

VCM = OV

7

60

nA

Large-Signal
Voltage Gain

Avo

Vo= ±10V
RL = 10kn
RL = 2kn

300
200

600
500

VlmV

Input Voltage Range

IVR

(Note 1)

±12

±12.5

V

Output Voltage Swing

Vo

RL ", 2kn

±12

±13

V

Common-Mode
Rejection

CMR

VCM =±12V

100

120

dB

Power Supply
Rejection Ratio

PSRR

Vs = ±4.5V to ±18V

1.0

5.6

pV/v

Supply Current
(All Amplifiers)

ISY

No Load

5.3

7.5

rnA

NOTE:
1. Guaranteed by CMR test.

ELECTRICAL CHARACTERISTICS at Vs

=

±15V, -40·C" T A" +85·C, unless otherwise noted.
OP·271F

OP·271AJE

PARAMETER

SYMBOL

InputOffsel
Voltage
Average Input
Offsel Voltage
Drift
Input Offset
Current

los

VCM = OV

CONDITIONS

MIN

TYP

MAX

Vos

100

330

TCVos

0.4

2

Input Bias

OP·271G

TYP

MAX

215

MIN

TYP

MAX

UNITS

560

300

700

JlV

4

2.0

5

JlVrC

30

5

40

15

50

nA

60

10

70

15

80

nA

18

V CM = OV

Large-Signal
Voltage
Gain

Avo

Vo =,,10V
RL = 10kD
RL = 2kD

300
200

600
500

200
100

500
400

150
90

400
300

V/mV

Input Voltage
Range

IVR

(Note 1)

,,12

,,12.5

,,12

,,12.5

,,12

,,12.5

V

Output Vollage
Swing

Vo

RL ~2kD

,,12

,,13

,,12

,,13

,,12

,,13

V

Common·Mode
Rejection

CMR

VCM = ,,12V

100

120

94

115

90

100

dB

PSRR

Vs =:4.5Vto,,18V

0.7

5.6

51.8

10

2.0

15

JlV/V

ISY

No Load

5.2

7.2

5.2

7.2

5.2

7.2

rnA

Current

Power Supply
Rejection

6

MIN

Ratio

Supply Current
(All Amplifiers)

NOTE:
1. Guaranteed by CMR test.

REV. B

OPERA TIONALAMPLIFIERS 2-289

II

OP-271
DICE CHARACTERISTICS

1.
2.
3.
4.

OUT A
-INA
+INA

V5. +IN B
6. -IN B
7.0UTB

8. V+

DIE SIZE 0.094 X 0.092 inch, 8,648 sq. mils
(2.39 X 2.34 mm, 5.60 sq. mm)

For additional DICE ordering information,
refer to PMl's Data Book, Section 2.

WAFER TEST LIMITS at Vs = ±15V, TA = 25°C, unless otherwise noted.
OP-271GBC
PARAMETER

SYMBOL

Input Offset Voltage

Vas

CONDITIONS

LIMIT

UNITS

300

~VMAX

Input Offset Current

los

VCM = OV

15

nAMAX

Input Bias Current

18

VCM = OV

40

nAMAX

Ava

Vo= ±IOV
RL = 10k!!
RL = 2k!!

300
200

VlmV MIN

VMIN

Large-Signal
Voltage Gain
Input Voltage Range

IVR

(Note I)

±12

Output Voltage Swing

Va

RL

±12

VMIN

Common-Mode Rejection

CMR

VCM= ±12V

100

dBMIN

Power Supply
Rejection Ratio

PSRR

Vs = ±4.5V to ±18V

5.6

Supply Current
(All Amplifiers)

ISY

No Load

6.5

::::

2kCl

~VIV

MAX

mAMAX

NOTES:
I. Guaranteed by CMR test.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

2-290 OPERA TIONALAMPLIFIERS

REV. B

OP-271
TYPICAL PERFORMANCE CHARACTERISTICS

.,

VOLTAGE NOISE DENSITY
vs FREQUENCY
100

Iit:;

T,,-25°C
Ys +1SV

~

40

~ 30

t
~

"

~
~

'"

w

'~"

TOTAL HARMONIC DISTORTION
vs FREQUENCY
D.1

,.0

.0
AT 10Hz

0
z

~

j!

AT 1kHz

0

Ay11

>-

,

±,

0

FREQUENCY (Hz)

±20

±15

±10

CURRENT NOISE DENSITY
vs FREQUENCY

100

INPUT OFFSET VOLTAGE
vs TEMPERATURE

TA:: 25°C
YS - ±15V

WARM-UP OFFSET
VOLTAGE DRIFT
10
TA=~·C

Vs" ±15V

~'"
0

~

>

>w

~
>-

..
::I

1/t CORNER - 40Hz

.3 B
w

BD
BD

I I I II
100

1k

'0

-'0-75

10.

./

40

!!

I IIIII I II

Vs"" ±15V

;;-

100

~
w

10k

1k

FREQUENCY (Hz)

120

10

I

D.DD1
10

SUPPLY VOLTAGE (VOLTS)

10

0.1

Ay-10

":c

w
'" 10

,.

II

D.D1

,.,."Z

>

100

I

Q
u

0

10

Ay= 100

Iii

~

1

Yo=10Vp-p
RL -2kO

z
0
;::

~ 15
w
on

g •

Va - :!::15V

!

z

1/f CORNER - 40Hz

r ... -25°C

TA ""25°C

>
>iii

20

10

VOLTAGE NOISE DENSITY
vs SUPPLY VOLTAGE

"",

~

'"

g

7

6

>-

/

/
-SO

V

!/

~

5

o

4

~

3

~

!!

I

~

I

u

-25

FREQUENCY (Hz)

25

50

75

100

o

125

/

o

TEMPERATURE (Oe)

INPUT BIAS CURRENT
vs TEMPERATURE

TIME (MINUTES)

INPUT BIAS CURRENT vs
COMMON-MODE VOLTAGE

INPUT OFFSET CURRENT
vs TEMPERATURE

10
TA = 25°C
Vs == ±15V

Va"'" ±15V
VCM""OY

./

/

V

l/

...-

-75

i,.

2

So

/

_6

1
>-

I--.

z

,.ill

::I
U

i

U

on

-1

~

>- -.

!;

!

-

~

,

::I

o

~

-3

4

3

-4

-50

-25

25

50

T~MPERATURE

REV.B

3

,.

V
-.

C

(Oel

75

100

125

-,-75

-SO

-25

0

25

50

TEMPERATURE (a e)

75

100

125

•

/

V

~ I-"'"

-12.5 -10 -7.5 -5 -2.5

0

2.5

5

7.5

10 12.5

COMMON-MODE VOLTAGE (VOLTS)

OPERATIONALAMPLIFIERS 2-291

OP-271
TYPICAL PERFORMANCE CHARACTERISTICS Continued

TOTAL SUPPLY CURRENT
YS SUPPLY VOLTAGE

CMR ys FREQUENCY
130

III

120
110
100

Vs= ±15V

c

! 61---+---+---+------1

.ffi

90

!..

~
~

80

..

70

U

51---+-----,'"""_::.-

~...

60
50

30

VSI71I~1SV

10
1

100

10

1k

10k

100k

3~--~--~--~--~
±s
±10
±1S
o
±20

1M

FREQUENCY (Hz)

,,

100

l!.

"""
"I'-"I'"I'-"

80

~ 60
40

".

I'\. -PSR

+PSR

l!.

80

0

~

60

0

40

~

"

20

o

1

10

100

1k

10k

""

m100
z
C

100k

1M

o

1

10

OPEN-LOOP GAIN, PHASE SHIFT
YS FREQUENCY

"

15

l!.

z
~

~AIN

10

........

:!;

9

..:!;

z
C

""

100

1k

.."
..9

"
10k

~

""

100k

""

1M

5

Z

0

-5

--

""-

~i'

o

PHASE MARGIN
=620

"

140

t

~

.

160 ~

.......

l:

180 ~

1' ....

>'

~

60

1

4

5

6

7 8 910

FREQUENCY (MHz)

2-292 OPERA TIONAL AMPLIFIERS

_

1500

100k

1M

10M

f::Y.~ ±15~

70

~

GSW-

e.z

z

C;

~

ill
500

o

-10

10k

GAIN-BANDWIDTH PRODUCT,
PHASE MARGIN YS TEMPERATURE

C
~ 1000

~

.....
l-

FREQUENCY (Hz)

TA "" 25°C
RL"" 10kn

~

.....
20

1.

OPEN-LOOP GAIN
SUPPLY VOLTAGE

120 _

.....

-20 I -

10M 100M

YS

100

.Jo't'

40

0

Q

2000

~PHASE

125

Vs =±15V

l!.

FREQUENCY (Hz)

TA""25°C
Vs "" ±15V

100

T. =

iI

FREQUENCY (Hz)

25

75

60

20

10M 100M

50

TA := 2S<>C
VS"" ±15V

-.

120

I\.. I\..

25

80

TA - 25°C

I\.. I\..

-25

CLOSED-LOOP GAIN
YS FREQUENCY

140

120

-50

TEMPERATURE (DC)

OPEN-LOOP GAIN
YS FREQUENCY

PSR YS FREQUENCY

~

3
-75

SUPPLY VOLTAGE (VOLTS)

140

20

V

~

..-

TA = 25°C

20

iii

V

~ 41----F---+---+---j

40

..

TOTAL SUPPLY CURRENT
YS TEMPERATURE

~
o

±5

±1D

----

.

.".-

±1S

SUPPLY VOLTAGE (VOLTS)

±20

;

60

~

50

40
-75 -50 -25

-Om

25

50

75

100

0
125 150

TEMPERATURE ( 3kO, a pole created by AI and the amplifier's input
capacitance (3pF) creates additional phase shift and reduces
phase margin. A small capacitor in parallel with AI helps
eliminate this problem.
COMPUTER SIMULATIONS
Many electronic design and analysis programs include models
forop amps which calculate AC performance from the location
of poles and zeros. As an aid to designers utilizing such a
program, major poles and zeros of the OP-271 are listed below.
Their location will vary slightly between production lots.
Typically, they will be within ±15% of the frequency listed. Use
of this data will enable the designer to evaluate gross circuit
performance quickly, but should not supplant rigorous characterization of a breadboarded circuit.

FIGURE 1: Driving Large Capacitive Loads
v+

POLES

ZEROS

15 Hz
1.2 MHz
2 x 32 MHz
8x40 MHz

2.5 MHz
4x23 MHz

C2

+--C-3-.!.j~o8

O.1rr ":'"
":"

.,

A2

C4

~-c-.-.-I,o~

0.18
":'"

v-

PLACE SUPPLY DECOUPLING
CAPACITORS AT OP-271

UNITY-GAIN BUFFER APPLICATIONS
When AI:::; 1000 and the input is driven with a fast, large-signal
pulse (>1 V), the output waveform will look as shown in Figure 2.

During thefastfeedthrough-like portion oftheoutput, the input
protection diodes effectively short the output to the input. and a
current, limited only by the output short-circuit protection, will
be drawn by the signal generator. With AI;:O: 5000, the output is
capable of handling the current requirements (IL :::; 20mA at
10V); the amplifier will stay in its active mode and a smooth
transition wi II occu r.

APPLICATIONS
LOW PHASE ERROR AMPLIFIER
The simple amplifier depicted in Figure 3 utilizes a monolithic
dual operational amplifier and a few resistors to substantially
reduce phase error compared to conventional amplifier designs.
At a given gain, the frequency range for a specified phase
accuracy is over a decade greater than for a standard single op
amp amplifier.

The low phase error amplifier performs second-order frequency
compensation through the response of op amp A2 in the
feedback loop of A1. Both op amps must be extremely well
matched in frequency response. At low frequencies, the A 1
feedback loop forces V2/(K1 + 1) VIN. The A2 feedback loop
forces Vo/(K1 + 1) V2/(K1 + 1) yielding an overall transfer
function of VOIVIN = K1 + 1. The DC gain is determined by the
resistor divider at the output, Vo, and is not directly affected by
the resistor divider around A2. Notethat, like a conventional
single op amp amplifier, the DC gain is set by resistor ratios
only. Minimum gain for the low phase error amplifier is 10.

=

=

FIGURE 3: Low Phase Error Amplifier
R2

R2=R1

~~----------~~~

.2
Ki

r------'l
I

I

I
~-l----..JV2

FIGURE 2: Pulsed Operation

.,

V'N

0----11--1

L-------o
ASSUME: Ai AND A2 ARE MATCHED.

Yo=(K1

Vo

+ 1) YIN

Ao(S)""~

2-294 OPERA TIONALAMPLIFIERS

REV. B

OP-271
FIGURE 4: Phase Error Comparison

~~;';:N~~OAN~
"
DESIGN

_-.

:ilc

~ -3

~w

::

~

~

-1

DUAL 12-BIT VOLTAGE OUTPUT DAC
The dual voltage output DAC shown in Figure 5 will settle to
12-bit accuracy from zero to full scale in 21's typically. The
CMOS DAC-8222 utilizes a 12-bit, double-buffered input structure allowing faster digital throughput and minimizing digital
feedthrough.

CASCADED
(TWO STAGES)

I

=f""'"
W~~I ERR~R

-4 -

V

Lol

FAST CURRENT PUMP
Maximum output current of the fast current pump shown in
Figure 6 is ±11mA. Voltage compliance exceeds ±10V with
±15V supplies. The current pump has an output resistance of
over 3MO and maintains 12-bit linearity over its entire output
range.

,

1\

AMPLIFIER

'"

.. -5
-6

1\

-7
0.001

1\

FIGURE 6: Fast Current Pump

I
0.01
I
0.1
0.005
0.05
FREQUENCY RATIO (1/,u)(w/wT)

I

0.5

1.0
R3

Figure 4 compares the phase error performance of the low
phase error amplifier with a conventional single op amp
amplifier and a cascaded two-stage amplifier. The low phase
error amplifier shows a much lower phase error, particularly for
frequencies where W/f:!wT<0.1. For example, phase error of
-0.10 occurs at 0.002 wlf:!wrforthesingleopamp amplifier, but
at 0.11 wlf:!wr for the low phase error amplifier.

Y,N

For more detailed information on the low phase error amplifier,
see Application Note AN-107.
lOUT =

~=

,!:'n =

10mAIV

-15Y

FIGURE 5: Dual 12-Bit Voltage Output DAC
+15V
10~F

+~

+5V

~
+10Y
REFERENCE
VOLTAGE

I
I

__ 1 __ -,
tI
VOD

RFBA

O.1~F

~

OAC·B••• EW

+--'-"'~

>-+"-4------oVoU,...

'---F-..,...--..,...--<> -15V

>--1f'-......-----oVourB
DAC {
CONTROL

REV. B

oJ!1llAl:A/DAC •
19

o-.!!!J=
~

--I-- ..J
DOND

OPERA nONAL AMPLIFIERS 2-295

2-296 OPERA TlONAL AMPLIFIERS

Dual Bipolar/JFET, Low Distortion
Operational Amplifier
OP-275* I

1IIIIIIII ANALOG

WDEVICES

PIN CONNECTIONS

FEATURES
"Sounds Good"
Low Noise: 5 nV/VHZ
Low Distortion: 0.0006%
High Slew Rate: 20 V/fJ.S
Wide Bandwidth: 8 MHz
Low Supply Current: 2 mA/Amplifier
Low Offset Voltage: 1 mV
Low Offset Current: 2 nA
Unity Gain Stable

8-Lead Narrow Body SOIC
(S SuffIx)

•

8-Lead Epoxy DIP
(P Suffix)

APPLICATIONS
High Performance Audio
Active Filters
Fast Amplifiers
Integrators

GENERAL DESCRIPTION
The OP-Z75 is the fIrst amplifier to feature the Butler Amplifie
front-end. This new front-end design combines the accuracy and
low noise perfonnance of bipolar transistors with the speed and
sound quality of JFETs. This yields better THD and noise performance than previous audio amplifiers, at much lower supply
currents.
Bias and offset currents are also greatly reduced over bipolar
designs.
The OP-Z75 is specified over the extended industrial and military temperature ranges. OP-Z75s are available in plastic and
ceramic DIP plus SOIC 8-pin surface mount packages.
ORDERING GUIDE
Model

Temperature
Range

OP275AZ1883
OP275ARCl883
OP27SGP
OP27SGS
OP27SGBC

- 55°C to
- 55°C to
-40°C to
-40°C to
+Z5°C

+ lZ5°C
+ lZ5°C
+85OC
+85°C

upply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Input Voltage2 • • • • • • • • • • • • • • • • • • • • • • • • • • • ± 18 V
Differential Input Voltage2 • • • • • • • • • • • • • • • • • • • • • 36 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Limited
Storage Temperature Range
Y, Z, RC Package . . . . . . . . . . . . . . . . -6SoC to + 175°C
P, S Package . . . . . . . . . . . . . . . . . . . . -6SoC to + ISO°C
Operating Temperature Range
OP-27SA . . . . . . . . . . . . . . . . . . . . . . -55°C to + 125°C
OP-27SG . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Junction Temperature Range
Y, Z, RC Package . . . . . . . . . . . . . . . . -65°C to + ISOOC
P, SPackage . . . . . . . . . . . . . . . . . . . . -65°C to +ISO°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C
3

Package Option

Package Type

a)A

14-Pin Cerdip
ZO-Contact LCC
8-Pin Plastic DIP
8-Pin SOIC
DICE

8-Pin Cerdip (Z)
8-Pin Plastic DIP (P)
8-Pin SOIC (S)
ZO-Contact LCC (RC)

148
103
158
NA

a)C

16
43
43
NA

Units
0c/w
0c/w
0c/w
0c/w

NOTES
I

Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise nored.

·Patent pending.

'Par supply voltages less than ± 18 V, the absolute maximum input voltage is
equal to the supply voltage.
39JA is specified for the worst case conditions, i.e., 8JA is specified for device in

socket for cerdip, P·DIP, and Lee packages;
soldered in circuit board for sOle package.

alA

is specified for device

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

REV. 0

OPERA T10NALAMPLIFIERS 2-297

OP~275 - SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ Ys =±15.0 Y, TA =
Parameter

Symbol

INPUT CHARACTERISTICS
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection
Large Signal Voltage Gain
Offset Voltage Drift

Vos
IB
los
VCM
CMR
Avo
t..Vos/t..T

OUTPUT CHARACTERISTICS
Output Voltage Swing

Vo

Open Loop Output Resistance

RoUT

POWER SUPPLY
Power Supply Rejection Ratio
Supply Current!Amplifier
Supply Voltage Range

PSRR
ISY
Vs

DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Total Harmonic Distortion

SR
BWp
ts
GBP
THD

Phase Margin
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Voltage Noise Density
Current Noise Density
Current Noise Density
Overshoot Factor

WAFER TEST LIMITS

+25OC unless otherwise specified.)
Min

Conditions

Typ

Max

Units

+11

mV
nA
nA
V
dB
V/mV
jJ.vrc

I
150
2

VCM = 0 V
VCM = 0 V
-II
S6

VCM = ±II V
RL = 600n

200
5

RL = 10kn
RL = 6OOn, Vs = ±ISV

-13

13
±17

SO
2
±IS

±4.5
20

S
0.002
0.0006
62

@20kHz
@lkHz

00
en P-P
en
en

f= 30Hz, Vs = ±ISV, V,N = lOVrms
f= I kHz, Vs = ±ISV, V,N = 10 V rms
f=30Hz
f=lkHz
VIN = 100 mY, AVD = I,
RL = 600 n, CL = 100 pF

i"
i"

S
5

10

V
V
n
dB
mA
V
V/jJ.s
kHz
jJ.S
MHz
%
%
degrees
jJ.Vp-p
nWVHz
nV/y'Hz
pAlVHz
pAly'Hz

%

(@ Ys=±15.0 Y, TA = +25OC unless otherwise specified.)

Parameter

Symbol

Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range'
Common-Mode Rejection
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Range
Supply. Current!Amplifier

Vos
IB
los

VCM = 0 V
VCM = 0 V

CMRR
PSRR
Avo
Vo
Isy

VCM = ± 11 V
V = ±9 V to ± IS V
RL = 10 kn
RL = 10kn
Vo = OV, RL = x

Conditions

Limit

Units
mVmax
nAmax
nAmax
V min
dB min
jJ.VN
VlmVmin
V min
mAmax

NOTES
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for
standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
'Guaranteed by CMR test.
Specifications subject to change without notice.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2-298 OPERA TlONALAMPLlFIERS

REV.

a

High Speed Low Noise Quad
Operational Amplifier
OP-471 I

r.ANALOG
WDEVICES
FEATURES
•
•
•
•
•
•
•
•
•
•

Excellent Speed . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8V1/J.s Typ
Low Noise ................... 11nVl.j"iiZ @ 1kHz Max
Unity-Gain Stable
High Gain-Bandwidth ...................... 6.5MHz Typ
Low Input Offset Voltage ................... O.BmV Max
Low Offset Voltage Drift ................... 4/J.V/oC Max
High Gain ............................... 500VlmV Min
Outstanding CMR ......................... 105 dB Min
Industry Standard Quad Pinouts
Available in Die Form

ORDERING INFORMATION t
PACKAGE
TA =+25"<:
VosMAX
CERDIP
(IN)
PLASTIC
800
800
800
1500
1800
1800

LCC'

OP471EY
OP471FY
OP471GP
OP471 Gstt

PIN CONNECTIONS

OPERATING
TEMPERATURE
RANGE

OP471ATC/883
OP471ARC/883

OP471Ar

The OP-471 has an input offset voltage under O.amV and an
input offset voltage drift below 4/J.V/oC, guaranteed over the
full military temperature range. Open loop gain of the OP-471
is over 500,000 into a 10k!! load insuring outstanding gain
accuracy and linearity. The input bias current is under 2SnA

MIL
MIL
INO
INO
XINO
XINO

14-PIN HERMETIC DIP
(V-Suffix)
14-PIN PLASTIC DIP
(P-Suffix)

N.C.

For devices processed in total compliance to MIL-STD-883, add 1883 after part
number. Consult factory for 883 data sheet.
Burn-in is available on commercial and industrial temperature range parts in
CerDIP, plastic DIP, and TO-can packages.
It For availability and burn-in information on SO and PLCC packages, contact
your local sales office.

+IN D

N.C.

N.C.

y-

N.C.

:
"T

The OP-471 is a monolithic quad op amp featuring low noise,
11nv/y'HZ Max @ 1kHz, excellent speed, 8V//J.s typical, a
gain-bandwidth of 6.5MHz, and unity-gain stability.

+IN D
y-

(""" r.::1;',"'. "',,:":'2°":":3'-:;)
GENERAL DESCRIPTION

16-PIN SOL
(S-Suffix)

+INC

+IN8

+INC

r::;"\r.~r.;1t«1r.;;;Jr.;1r.;;;J '7

N.C.

~-Q ~ ~

6

Z

6 ,.

20-LEADLCC
(RC-Suffix)

28-LEADLCC
(TC-Suffix)

SIMPLIFIED SCHEMATIC (One of four amplifiers is shown.)
r-~------~----~----~r-~~----------------------~~~~----~-Ov+

OUT

-IN 0 -.....-1'-.....

L-----------------~--+_--------~--------__~--+_--~_+--~_ov-

REV. B

OPERA TlONAL AMPLIFIERS 2-299

OP-471
Lead Temperature Range (Soldering, 60 sec) .............. 300°C
Junction Temperature (T1 ............................ -65°C to + 150°C
Operating Temperature Range
OP-471 A .................................................... -55°C to + 125°C
OP-471 E, OP-471 F ..................................... -25°C to +85°C
OP-471 G ...................................................... -40°Cto +85°C

limiting errors due to signal source resistance. The OP-471 's
CMR of over 105dB and PSRR of under 5.6"VIV significantly
reduce errors caused by ground noise and power supply
fluctuations.
The OP-471 offers excellent amplifier matching which is
important for applications such as multiple gain blocks, lownoise instrumentation amplifiers, quad buffers and low-noise
active filters.

8 JA (Note 2)

PACKAGE TYPE

UNITS

8 JC

·CIW
94
10
14-Pin Hermetic DIP (V)
·CIW
33
14-Pin Plastic DIP (P)
76
·CIW
30
20-Contact LCC (RC)
78
28
·CIW
28-Contact LCC (TC)
70
IS-Pin SOL (S)
88
23
OCIW
NOTES:
I. Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2. 8. is specified for worst case mounting conditions. i.e.• 8' A is specified for
d~~ice in socket for CerDIP. P-DIP. and LCC packages;
is specified for
device soldered to printed circuit board for SOL package.
3. The OP-471's inputs are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low noise performance. If differential
voltage exceeds ±I .OV. the input current should be limited to ±25mA.

The OP-471 conforms to the industry standard 14-pin DIP
pinout. It is pin compatible with the OP-11, LM148/149,
HA4741, RM4156, MC33074, TL084 and TL074 quad op amps
and can be used to upgrade systems using these devices.
For applications requiring even lower voltage noise the OP470, with a voltage density of 5nV/.,j'Hz Max @ 1kHz, is
recommended.

8: A

ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage ................................................................. ±18V
Differential Input Voltage (Note 3) .................................. ±1.0V
Differential Input Current (Note 3) ............................... ±25mW
Input Voltage .................................................... Supply Voltage
Output Short-Circuit Duration ................................ Continuous
Storage Temperature Range
p, RC, TC, Y -Package ............................... -65°C to + 150°C

ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = 25°C, unless otherwise noted.
SYMBOL

Input Offset Voltage

vas

Input Offset Current

los

VCM = OV

Input Bias Current

18

VCM = OV

Input Noise Voltage

e np _p

O.IHz to 10Hz
(Note 1)

en

10 = 10Hz
10= 100Hz
10= 1kHz
(Note 2)

In

10= 10Hz
10 = 100Hz
10 = 1kHz

Ava

Vo= ±10V
RL = 10kll
RL = 2kll

500
350

700
550

Input Noise

Voltage Density

Input Noise
Current Density

Large-Signal
Voltage Gain

CONDITIONS

OP-471A/E
MIN
TYP MAX

PARAMETER

MIN

OP-471F
TYP MAX

MIN
;-

0.25

0.8

0.5

1.5

4

10

7

25

15

OP-471G
TYP MAX
1.8

mV

20

12

30

nA

50

25

60

nA
nVp _p

250

500

250

500

250

500

9

16
12
11

9
6.5

16
12
11

6.5

16
12
11

6.5

1.7
0.7
0.4

1.7
0.7
0.4
300
175

UNITS

1.0

nV/.,[HZ

1.7
0.7
0.4

pA/.,[HZ

V/mV

500
275

300
175

500
275

Input Voltage Range

IVR

(Note 3)

±11

±12

±11

±12

±11

±12

Output Voltage Swing

Va

RL22kll

±12

±13

±12

±13

±12

±13

V

VCM = ±l1V

105

120

95

115

95

115

dB

Common-Mode Rejection CMR
Power Supply
Rejection Ratio

Slew Rate

PSRR
SR

2-300 OPERATIONAL AMPLIFIERS

5.6

5.6

Vs = ±4.5V to ±18V
6.5

8

6.5

8

17.8

5.6
6.5

V

17.8

!'VIV
V/!'s

REV. B

OP-471
ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = 25°C, unless otherwise noted. (Continued)
OP-4nF

OP-4nA/E
PARAMETER

SYMBOL

CONDITIONS

Supply Current
(All Amplifiers)

ISY

No Load

MIN

TYP

MAX

9.2

11

6.5

11

TYP

MAX

UNITS

9.2

11

mA

dB

2.6

2.6

pF

1.1

1.1

1.1

M!!

11

11

11

G!!

4.5
7.5

4.5
7.5

4.5
7.5

~s

Va ~ 20Vp"p
fa ~ 10Hz (Note 1)

Input Capacitance

C'N

2.6

Input Resistance
Differential-Mode

R'N
R 1NCM

Common-Mode

9.2

MIN

MHz

CS

125

MAX

6.5

Av~

Channel Separation

+10

OP-4nG

TYP

150

Gain-Bandwidth Product GBW

Input Resistance

MIN

150

6.5
125

150

125

Av~+1

Settling Time

to 0.1%
to 0.01%

ts

NOTES:
1. Guaranteed but not 100% tested.
2. Sample tested.
3. Guaranteed by CMR test.

ELECTRICAL CHARACTERISTICS at Vs = ±15V, -55°C::; TA::; 125°C for OP-471 A, unless otherwise noted.
OP-4nA
PARAMETER

SYMBOL

Input Offset Voltage

Vas

Average Input

Offset Voltage Drift

CONDITIONS

MIN

TYP

MAX

0.4

1.2

mV

4

~V;oC

TCVos

UNITS

Input Offset Current

los

VCM~

OV

6

20

nA

Input Bias Current

I.

VCM~

OV

16

50

nA

Vo~

Large-Signal
Voltage Gain

Ava

±10V
RL ~ 10k!!
RL ~ 2k!!

375
250

500
350

V/mV

Input Voltage Range

IVR

(Note 1)

±11

±12

V

Output Voltage Swing

Va

R L 202k!!

±12

±13

V

CMR

VCM~

100

115

dB

PSRR

Vs ~ ±4.5V to ±18V

5.6

10

~VIV

ISY

No Load

9.3

11

mA

Common-Mode
Rejection

Power Supply
Rejection Ratio

Supply Current
(All Amplifiers)

±11V

NOTE:
1. Guaranteed by CMR test.

REV.B

OPERATIONAL AMPLIFIERS 2-301

•

OP-471
ELECTRICAL CHARACTERISTICS at Vs = ±15V, -25°C ~ TA ~ +85°C for OP-471 ElF, -40°C ~ T A ~ +85°C for OP-471 G, unless
otherwise noted.

OP-471E
PARAMETER

SYMBOL

Input Offset Voltage

Vas

Average Input

Offset Voltage Drift

CONDITIONS

OP-4nF

TYP

MAX

0.3

1.1

MIN

OP-4nG

TYP

MAX

0.6

2.0

MIN

TYP

MAX

1.2

2.5

4

TCVos

Input Offset Current

los

VCM

~

OV

Input Bias Current

18

VCM

~

OV

mV
MVI'C

20
13

UNITS

25

50

40

20

50

nA

70

40

75

nA

Vo~±10V

Large-Signal
Voltage Gain

MIN

Ava

RL
RL

~
~

10k!!
2k!!

400

375
250

600
400

200
125

200

200
125

200

400

V/mV

Input Voltage Range

IVR

(Note 1)

±11

±12

±11

±12

±11

±12

V

Output Voltage Swing

Va

RL2: 2k!!

±12

±13

±12

±13

±12

±13

V

CMR

VCM = ±11V

100

115

90

110

90

110

dB

PSRR

Vs

ISY

No Load

Common-Mode
Rejection
Power Supply

Rejection Ratio
Supply Current

(All Amplifiers)

= ±4.5V to ±18V

3.2

10

18

31.6

18

31.6

MV/V

9.3

11

9.3

11

9.3

11

mA

NOTE:
1. Guaranteed by CMR test.

2-302 OPERA TlONAL AMPLIFIERS

REV. B

OP-471
DICE CHARACTERISTICS

1.
2.
3.
4.
5.

OUT A
-INA
+INA

v+
+IN B

6. -IN B
7. OUT B
8.0UTC
9. -INC
10. +IN C
11. V12. +IN D
13. -IN D
14. OUT D

DIE SIZE 0.163 X 0.106 Inch, 17,278 sq. mils
(4.14 X 2.69 mm, 11.14 sq. mm)

WAFER TEST LIMITS at Vs = ±15V, TA = 25°C, unless otherwise noted.
OP-471GBC
PARAMETER

SYMBOL

Input Offset Voltage

Vos

CONDITIONS

LIMIT

UNITS

1.5

mVMAX

Input Offset Current

los

VCM = OV

20

nAMAX

Input Bias Current

18

VCM = OV

50

nAMAX

Avo

Vo = ±10V
RL = 10k!!
RL = 2k!!

300
175

V/mVMIN

VMIN

Large-Signal
Voltage Gai n
Input Voltage Range

IVR

Note 1

±11

Output Voltage Swing

Vo

RL2: 2k!!

:±.12

VMIN

Common-Mode Rejection

CMR

VCM=:!.-11V

95

dB MIN

Power Supply
Rejection Ratio

PSRR

Vs = ±4.5V to ±18V

17.8

MVIV MAX

Slew Rate

SR

6.5

VIMS MIN

Supply Current
(All Amplifiers)

ISY

11

mAMAX

No Load

NOTES:
1. Guaranteed by CMR test.
Electrical tests are performed at wafer probe to the limits shown. Due to vanations In assembly methods and normal yield loss, Yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

REV.B

OPERA TIONAL AMPLIFIERS 2-303

OP-471
TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE NOISE DENSITY
vs FREQUENCY

VOLTAGE NOISE DENSITY
vs SUPPLY VOLTAGE

100
TA - 25°C
Vs - +15V

~

20

0
z

10

.

>

AT 10Hz

40
30

!w

O.1Hz TO 10Hz NOISE

10r-----~-----r-----r-----,

I

Ii •r - - - t - - - + - - - t - - - I
~w

~~

6z 6~----+-----~----~-----4

w

"a~

w

"g~

AT 1kHz

!ll

a
z

w

"~

r - 11t CO~~I~R - 5Hz

>

g

II IIIII I I

JIIIIII

1

TIME (SEC)

T.=25°C

I

10

1

2L-____
100

o

1k

____

~

____

±10

~

____

Ys=±1SV

~

±15

±20

SUPPLY VOLTAGE (VOLTS)

CURRENT NOISE DENSITY
vs FREQUENCY

WARM-UP OFFSET
VOLTAGE DRIFT

INPUT OFFSET VOLTAGE
vs TEMPERATURE
20

400

10.0
TA
Vs

25~C

VS =±lSY

+15V

>

Ii
i

;: 300

"a~

'I'

w

1.0

a
z
....

~

±5

FREQUENCY (Hz)

!!l

10

4~----+-----~----~-----4

./

>

~

,

illa:
a:
u

::J

I

10

a
!;

!

it' c'lR1iEtIIW

H'

III

0.1

200

V

w

~ 14

!:l

g 12

V

....

10k

1k

FREQUENCY (Hz)

~

~

-75

z

:!:

-50

-25

./

~ 10

:::a

100

o

TA = 25°C
Vs = ±15V

>
..5 16

.
•

4

U

1111111

100

~

,

1.

,.,

25

50

75

100

125

/

I

o
o

2
TIME (MINUTeS)

INPUT BIAS CURRENT vs
COMMON-MODE VOLTAGE

INPUT OFFSET CURRENT
vs TEMPERATURE

20

10
Vs = ±15V
VCM

15

'\

ffi
a:
a:

a

10

1\....... r--...

iii

!;
5

o_

_

TA = 25°C
Vs = ±15V

=ov

'\

:Il

!

I

TEMPERATURE (DC)

INPUT BIAS CURRENT
vs TEMPERATURE

~

I'

_

~

~

~

~

m

TEMPERATURE (OC)

~

~7~5---~50---~25~~0--~2~5--5~0--~~--~'0-0~'25
TEMPERATURE (DC)

-

--

10.0
-12.5

",

,/

1/

",

-5.0
-7.5

~

5.0
-2.5

2.5

10.0
7.5

12.5

COMMON-MODE VOLTAGE (VOLTS)

2-304 OPERA TIONALAMPLIFIERS

REV. B

OP-471
TYPICAL PERFORMANCE CHARACTERISTICS

130

I+~I~ 2S

120

Vs

10

D
C

YS=±15V

= ±15V

110

;(

.§. 8

100

I-

90

::ia:

01

80

"

60

""
il:
"

a:

!!.
a: 70

,.

TOTAL SUPPLY CURRENT
vs TEMPERATURE

TOTAL SUPPLY CURRENT
vs SUPPLY VOLTAGE

CMR vs FREQUENCY

~

.

50

6

~

~

40

0

I-

30
20
10
10

100

1k

10k

1M

lOOk

±5

0

FREQUENCY (Hz)

±10

140

80

TA = 2S D C

.
a.

"- "-

120

80
40

20

1

10

100

z

a

10k

lOOk

1M

10M

80

9

..

0

40

"a.
0

~

Ys= ±15Y
60

.....

""\

!!.

-PSR

1k

r---

m 100

""
" "-" "" "-"

+PSR

80

o

TA = 2SD C

=±15V

Vs

100

01

100M

10

100

80

a

"a.

10

~ ........

0

9

zw
a.
0

-5

-

Vs=±15V

;;;;;

40

'\

i -

'-'\.

10k

lOOk

-

20

~

9

" "1M

10M

"
-20
1k

100M

10k

lOOk

1M

10M

FREQUENCY (Hz)

GAIN-BANDWIDTH
PRODUCT, PHASE MARGIN
vs TEMPERATURE

TA = 2S"C

Vs - ±15V

RL = 10kfl

100

r=±15V

GBW

¥

PHASE

--""" J:t

"N"-",

120

140

MARGIN
=57" ,_

180

r"'r-. i'
10

FREQUENCY (MHz)

~

:il

~

c;

~

z

~

o

Ii:

~

_

1500

~

o

!.

10

6 I-

""c

a

o

z

1000

./ ~

500

o

o

II:

..

~ 60

,/

4 :I:

~

it

V

200
220

1

:>

160 w

-10

REV.B

TIn
TA "" 2S"C

200 0

TA = 2SD C

r--

1k

-

0

OPEN-LOOP GAIN
vs SUPPLY VOLTAGE

25

15

"

"a.

-

CLOSED-LOOP GAIN
vs FREQUENCY

FREQUENCY (Hz)

OPEN-LOOP GAIN, PHASE
SHIFT vs FREQUENCY

01
!!.
z

~
z
a

20

FREQUENCY (Hz)

20

TEMPERATURE (DC)

OPEN-LOOP GAIN
vs FREQUENCY

140

!!.
a:

±20

±15

SUPPLY VOLTAGE (VOLTS)

PSR vs FREQUENCY
120

_ ___~~0__-L
~ __..
L-~
~__~
~~
m

_

2L-~

2
1

I;
ic
z

-t/>
50

2

"
40

±5

c
'l'
z

a

±10

±15

SUPPLY VOLTAGE (VOLTS)

±20

0

-75 -50 -25

0

25

50

75

100

125 150

TEMPERATURE (DC)

OPERA TIONAL AMPLIFIERS 2-305

OP-471
TYPICAL PERFORMANCE CHARACTERISTICS

•• ...

-

C;; 24

~

!:l

TA ""

16

=

12

~

~

~

14

1111111\

\

...::.
~

,.

..

9

!

6

o

:0

6
~
II!

8

~

360

I II

II

I-

PJSWE
SWING

Io?'
NEGATIVE
SWING

10

II!

180

...:0i!!
...:0a.

10k

lOOk

o

0
100

10M

1M

•
10k

=1

lOOk

1M

10M

100M

TOTAL HARMONIC
DISTORTION vs FREQUENCY

170

TA "" 25°C

160
8.5

~

150

-SR .....
KR

g

8.0

w
7.5

~

~ 7.0

6.0
-75

1k

Ay

111111111
111111111

FREQUENCY (Hz)

CHANNEL SEPARATION
vs FREQUENCY

SLEW RATE
TEMPERATURE

9.0

6.5

100

10k

"

LOAD RESISTANCE (n)

FREQUENCY (HZ)

VB

120

0

60

t--

1k

a:

.40

c-

o

!c

S
w

"ilz

;J
4

T~I!"~~OC
Vs ... ±15V

300

16

g -

~

:!l

TA'.5·C
V,'±15V

iii'

20

~

19

THO"" 1%

o

2:.

.0

25~CI

Va"" ±15Y

l-

CLOSED-LOOP
OUTPUT IMPEDANCE
VB FREQUENCY

MAXIMUM OUTPUT
VOLTAGE vs
LOAD RESISTANCE

MAXIMUM OUTPUT SWING
vs FREQUENCY

I
I

!l

-50

=-

~

~

~

f

-25

~

a:
0

In

120

"0Z

110

."...
a:

.

90

"

70

TA"" 25°C

60

Vs =±15V
Yo == 20Yp _p TO 100kHz

Z

:z:

:z: 80

25

50

75

100

125

50
10

I

0.1

is

~ 100
w

z

Vo -10Vp•p
RL == 2kO

0

;:

140

~ 130

fia:

Vs"" ±15V

Z

0.01
Ay -10

j!

100

TEMPERATURE (DC)

1k

10k

.....,..

...0
lOOk

1M

10M

TA = 25°C
Vs'" ±15V
Ay =+1

2-306 OPERATIONAL AMPLIFIERS

100

Av- 1

Ilflll
1k

10k

FREQUENCY (Hz)

FREQUENCY (H:r:)

LARGE-SIGNAL
TRANSIENT RESPONSE

I

-I--

0.001
10

SMALL-SIGNAL
TRANSIENT RESPONSE

T:'=.2S0C
Vs "" ±15,V

Ay=:-'

REV.S

OP-471
CHANNEL SEPARATION TEST CIRCUIT

TOTAL NOISE AND SOURCE RESISTANCE
The total noise of an op amp can be calulated by:

SkU

+ (in RS)2 + (et)2

En = V(e n)2
where:

En = total input referred noise

>-~--o V1 20Vp•p

en = op amp voltage noise
in = op amp current noise
et = source resistance thermal noise

SOkn

Rs = source resistance
>----<>---0

The total noise is referred to the input and at the output would
be amplified by the circuit gain.

V,

CHANNEL SEPARATION"" 20 IOg(

V2/~~OO)

Figure 1 shows the relationship between total noise at 1kHz
and source resistance. For Rs < 1kll the total noise is domi-

FIGURE 1: Total Noise vs Source Resistance (Including
Resistor Noise) at 1kHz

BURN-IN CIRCUIT

~
•

+1V
-18V

~
_

-w

10

+

C

~3_

8

"::"

7

5 +

0

-w

12

+

w

ozct.I

10

OP-4OO

OP-471

~

i!

1!

14

100

1k

"::"

10k

10Ol<

Rs - SOURCE RESISTANCE (il)

FIGURE 2: Total Noise vs Source Resistance (Including
Resistor Noise) at 10Hz

APPLICATIONS INFORMATION
100

VOLTAGE AND CURRENT NOISE
The OP-471 is a very low-noise quad op amp, exhibiting a
typical voltage noise of only 6.5nv/J"HZ @ 1kHz. The low
noise characteristic of the OP-471 is in part achieved by
operating the input transistors at high collector currents
since the voltage noise is inversely proportional to the square
root of the collector current. Current noise, however, is
directly proportional to the square root of the collector
current. As a result, the outstanding voltage noise performance of the OP-471 is gained atthe expense of current noise
performance which is typical for low noise amplifiers.
To obtain the best noise performance in a circuit it is vital to
understand the relationship between voltage noise (en), current noise (in), and resistor noise (et).

REV.B

..,oj

Ii'>
~

.,w

!£

OP-11

OP-471

i!0

OP-470

~

"

OP-400

10

0z

...

j.

~
100

RESISTOR
NOISE ~rLY

1k

10k

lOOk

Rs - SOURCE RESISTANCE (n)

OPERA TIONALAMPLIFIERS 2-307

II

OP-471
nated by the voltage noise of the OP-471. As Rs rises above
1kn, total noise increases and is dominated by resistor noise
rather than by voltage or current noise of the OP-471. When
Rs exceeds 20kn, current noise of the OP-471 becomes the
major contributor to total noise.
Figure 2 also shows the relationship between total noise and
source resistance, but at 10Hz. Total noise increases more
quickly than shown in Figure 1 because current noise is
inversely proportional to the square root of frequency. In
Figure 2, current noise of the OP-471 dominates the total
noise when Rs > Skn.
From Figures 1 and 2 it can be seen that to reduce total noise,
source resistance must be kept to a minimum. In applications
with a high source resistance, the OP-400, with lower current
noise than the OP-471, will provide lower total noise.
Figure 3 shows peak-to-peak noise versus source resistance
over the 0.1 Hz to 10Hz range. Once again, at low values of Rs,
FIGURE 3: Peak-To-Peak Noise (0.1Hz To 10Hz) vs Source
Resistance (Includes Resistor Noise)
1000

OP·11

the voltage noise of the OP-471 is the major contributor to
peak-to-peak noise. Current noise becomes the major contributor as Rs increases. The crossover point between the OP471 and the OP-400 for peak-to-peak noise is at Rs = 17kn.
The OP-470 is a lower noise version of the OP-471, with a
typical noise voltage density of 3.2nV/y"HZ @ 1kHz. The
OP-470 offers lower offset voltage and higher gain than the
OP-471, but isa slower speed device, with a slew rate of 2V/Ils
compared to a slew rate of 8V/Ils for the OP-471.
For reference, typical source resistances of some signal
sources are listed in Table I.

TABLE I
DEVICE

SOURCE
IMPEDANCE
<50011

Typically used in low-frequency
applications.

Magnetic
1apehead

<150011

Low 16 very important to reduce
self-magnetization problems when
direct coupling is used. OP-471 I B
can be neglected.

Magnetic
phonograph
cartridges

<150011

Similar need for low 18 in direct
coupled applications. OP-471 will not
introduce any self-magnetization
problem.

Linear variable
differential
transformer

< 150011

Used in rugged servo-feedback
applications. Bandwidth of interest is
400Hz \0 5kHz.

OP-4DO

.~
00

~

OP-471

i5

.."z
00

~

OpL7l

100

,/

For further information regarding noise calculations, see
"Minimization of Noise in Op-Amp Applications", Application Note AN-1S.

6
~

~

~
10
100

COMMENTS

Strain gauge

RESISTOR
NOISE ONLY

11111111
1k
Rs -

10k

SOURCE RESISTANCE (ll)

lOOk

NOISE MEASUREMENTS PEAK-TO-PEAK VOLTAGE NOISE
The circuit of Figure 4 is a test setup for measuring peak-topeak voltage noise. To measure the SOOnV peak-to-peak

FIGURE 4: Peak-To-Peak Voltage Noise Test Circuit (0.1Hz To 10Hz)

.3

C4

4.99kD

..Lcs
J1~F

O.032pF

2-308 OPERA TlONAL AMPLIFIERS

GAIN = 50,000
Vs =±15V

REV.S

OP-471
noise specification of the OP-471 in the 0.1 Hz to 10Hz range,
the following precautions must be observed:
1. The device has to be warmed-up for at least five minutes.
As shown in the warm-up drift curve, the offset voltage
typically changes 131'V dueto increasing chip temperature
after power-up. In the 10-second measurement interval,
these temperature-induced effects can exceed tensof-nanovolts.
2. For similar reasons, the device has to be well-shielded
from air currents. Shielding also minimizes thermocouple
effects.
3. Sudden motion in the vicinity of the device can also "feedthrough" to increase the observed noise.
FIGURE 5: 0.1 Hz To 10Hz Peak-To-Peak Voltage Noise
Test Circuit Frequency Response

4. The test time to measure 0.1 Hz-to-l0Hz noise should not
exceed 10 seconds. As shown in the noise-tester frequency-response curve of Figure 5, the 0.1 Hz corner is
defined by only one pole. The test time of 10 seconds acts
as an additional pole to eliminate noise contribution from
the frequency band below O.lHz.
5. A noise-voltage-density test is recommended when measuring noise on a large number of units. A 10Hz noisevoltage-density measurement will correlate well with a
0.1 Hz-to-l0Hz peak-to-peak noise reading, since both
results are determined by the white noise and the location •
of the llf corner frequency.
6. Power should be supplied to the test circuit by well
bypassed low-noise supplies, e.g. batteries. These will
minimize output noise introduced through the amplifier
supply pins.
NOISE MEASUREMENT - NOISE VOLTAGE DENSITY
The circuit of Figure 6 shows a quick and reliable method of
measuring the noise voltage density of quad op amps. Each
individual amplifier is series-connected and is in unity-gain,
save the final amplifier which is in a noninverting gain of 101.
Since the ac noise voltages of each amplifier are uncorrelated, they add in rms fashion to yield:

100

~
0",

0

iii' •
:!!.

z

~

eOUT = 101

40

The OP-471 is a monolithic device with four identical amplifiers. The noise voltage density of each individual amplifier will
match, giving:

20

o '0.01

(J e nA2 + e nB2 + e nc 2 + e n o2 )

eOUT= 101 ( Q ) = 101 (2e n)
0.1

10

100

FREQUENCV (Hz)

FIGURE 6: Noise Voltage Density Test Circuit

.,
100n

.2
10kO

e OUT (nVl\! Hz) IE 101(2e n)
Vs "" ±15V

REV. B

OPERA TIONALAMPLIFIERS 2-309

OP-471
FIGURE7: Current Noise Density Test Circuit

"3

_" OUT TO

~-r-" SPECTRUM ANALYZER

8.0",n

".

GAIN

200n

NOISE MEASUREMENT - CURRENT NOISE DENSITY
The test circuit shown in Figure 7 can be used to measure
current noise density. The formula relating the voltage output
to current noise density is:

= 10,000

Vs =±15V

FIGURE 8: Driving Large Capacitive Loads
V+

C2

C3

(~)2 _(40nv/VHzf

~08

O.1~
":"

Rs
where:
G = gain of 10000
Rs = 100kO source resistance
CAPACITIVE LOAD DRIVING AND POWER
SUPPLY CONSIDERATIONS
The OP-471 is unity-gain stable and is capable of driving
large capacitive loads without oscillating. Nonetheless, good
supply bypassing is highly recommended. Proper supply
bypassing reduces problems caused by supply line noise and
improves the capacitive load driving capability olthe OP-471.
In the standard feedback amplifier, the op amp's output resistance combines with the load capacitance to form a lowpass filter that adds phase shift in the feedback network and
reduces stability. A simple circuit to eliminate this effect is
shown in Figure 8. The added components, C1 and R3,
decouple the amplifier from the load capacitance and provide
additional stability. The values of C1 and R3 shown in Figure
8 are for load capacitances of up to 1000pF when used with
the OP-471.

VON

-=

R2

Cl

.,

.3

50n
C4

~-C-.--,~o~

~18
"':'"

"SEE TEXT

V-

PLACE SUPPLY DECOUPLING
CAPACITORS AT 01'-471

FIGURE 9: Pulsed Operation

",

In applications where the OP-471's inverting or noninverting
inputs are driven by a low source impedance (under 100!l) or
connected to ground, if V+ is applied before V-, orwhen V- is
disconnected, excessive parasitic currents will flow. Most

2-310 OPERAnONALAMPUFIERS

REV.S

OP-471
applications use dual tracking supplies and with the device
supply pins properly bypassed, power-up will not present a
problem. A source resistance of at least 100n in series with all
inputs (Figure 8) will limit the parasitic currents to a safe level
if V- is disconnected. It should be noted that any source
resistance, even 100n, adds noise to the circuit. Where noise
is required to be kept at a minimum, a germanium or Schottky
diode can be used to clamp the V- pin and eliminate the
parasitic current flow instead of using series limiting resistors.
For most applications, only one diode clamp is required per
board or system.
UNITY-GAIN BUFFER APPLICATIONS
When Rt :> 1000 and the input is driven with a fast, largesignal pulse (>1 V), the output waveform will look as shown in
Figure 9.

HIGH OUTPUT AMPLIFIER
The amplifier shown in Figure 13 is capable of driving 20V p _p
into a floating 400n load. Design of the amplifier is based on a
bridge configuration. A 1 amplifies the input signal and drives
the load with the help of A2. Amplifier A3 is a unity-gain
inverter which drives the load with help from A4. Gain of the
high output amplifier with the component values shown is 10,
but can easily be changed by varying R1 or R2.

rF_IG_U
__
R_E_1_0_:_L_O_W_N_0_i_s_e_A_m_p_l_if_ie_r__________________

--,~

+15V

V,N

0--+-----'-1

R3

200n

During the fast feedthrough-like portion of the output, the
input protection diodes effectively short the output to the
input, and a current, limited only by the output short-circuit
protection, will be drawn by the Signal generator. With Rt 2
5000, the output is capable of handling the current requirements (IL:> 20mA at 10V); the amplifier will stay in its active
mode and a smooth transition will occur.

R6
20011

When Rt > 3kO, a pole created by Rt and the amplifier's input
capacitance (2.6pF) creates additional phase shift and reduces
phase margin. A small capacitor (20 to 50pF) in parallel with
Rt helps eliminate this problem.

R9

200n

APPLICATIONS
LOW NOISE AMPLIFIER
A simple method of reducing amplifier noise by paralleling
amplifiers is shown in Figure 10. Amplifier noise, depicted in
Figure 11, is around 5nV/J'HZ @ 1kHz (R.T.I.). Gain for each
paralleled amplifier and the entire circuit is 100. The 200n
resistors limit circulating currents and provide an effective
output resistance of 50n. The amplifier is stable with a 10nF
capacitive load and can supply up to 30mA of output drive.
HIGH-SPEED DIFFERENTIAL LINE DRIVER
The circuit of Figure 12 is a unique line driver widely used in
professional audio applications. With ± 18V supplies the line
driver can deliver a differential signal of 30V p _p into a 1.5kll
load. The output of the differential line driver looks exactly
like a transformer. Either output can be shorted to ground
without changing the circuit gain of 5, so the amplifier can
easily be set for inverting, noninverting, or differential operation. The line driver can drive unbalanced loads, like a true
transformer.

REV. 8

R12

200n

Skn

FIGURE 11: Noise Density of Low Noise Amplifier, G = 100

OPERATIONALAMPLIFIERS

2~311

2-312 OPERATIONAL AMPLIFIERS

REV.B

OP-471
QUAD PROGRAMMABLE GAIN AMPLIFIER
The combination of the quad OP-471 and the DAC-8408, a
quad 8-bit CMOS DAC, creates a space-saving quad programmable gain amplifier. The digital code present at the
DAC, which is easily set by a microprocessor, determines the
ratio between the fixed DAC feedback resistor and the impedance the DAC ladder presents to the op amp feedback loop.
Gain of each amplifier is:

where n equals the decimal equivalent of the 8-bit digital
code present at the DAC. If the digital code present at the
DAC consists of all zeros, the feedback loop will be open
causing the op amp output to saturate. The 20Mll resistors
placed in parallel with the DAC feedback loop eliminates this
problem with a very small reduction in gain accuracy.

VOUT
256
v;;=--n-

FIGURE 14: Quad Programmable Gain Amplifier

+15V

>----;--I\"I'----'

FIGURE 4: Inverting Adder

FIGURE 2: Large-Signal Transient Response, ZL "" 2knl/75pF

.,

...,
.... "-ri'"""'
..., ',11~

As with most JFET -input amplifiers, the output of the SSM-2131
may undergo phase inversion if either input exceeds the specified input voltage range. Phase inversion will not damage the
amplifier, nor will it cause an internal latch-up.
Supply decoupling should be used to overcome inductance and
resistance associated with supply lines to the amplifier.

••

+1" Rs

For most applications, a 0.1!iF to 0.01!iF capacitor should be
placed between each supply pin and ground.

OFFSET VOLTAGE ADJUSTMENT
Offset voltage is adjusted with a 1Okn to 1OOkO potentiometer
as shown in Figure 3. The potentiometer should be connected
between pins 1 and 5 with its wiper connected to the V- supply.

FIGURE 5: Noninverting Adder

Alternately, Vos may be nulled by attaching the potentiometer
wiper through a 1MO resistor to the positive supply rail.

2-320 OPERA TlONAL AMPLIFIERS

REV. A

SSM-2131
CURRENT FEEDBACK

In a current feedback amplifier, a unity or low gain input buffer
drives a low impedance network. Any differential current that flows
in the collectors of the buffer (SSM-2131) outputtransistors is fed,
via the two complementary Wilson current mirrors A and B, to a
high impedance gain node where the high output voltage is
generated.

AUDIO POWER AMPLIFIER
The SSM-2131 can be used as the input buffer in a current feedback audio power amplifier as shown in Figure 6. This design is
capable of very good performance as shown in Figures 7, a and
9. At 1kHz and 50 watts output into an aQ load, the amplifier
generates just 0.002% THD, and is flat to 1 MHz. The slew rate
for the overall amplifier is more than adequate at 300VIllS and is
responsible for the very low dynamic intermodulation distortion
(DIM-1 00) that was measured at just 0.0017% at 50 watts output
into ohms. The total amplifier idling current for all tests was
approximately 300mA; the V+/V++ and V-/V- power supplies
were both ±40V; and the gain was set to 24.0.

This voltage is then buffered by a double emitter follower driver
stage and fed to the complementary power MOSFET output stage.
No RC compensation network to ground or output inductor is
required at the output of this amplifier to make it stable. As the
100kHz square wave response shows, there's no evidence of any
instability in the circuit. Capacitive load compensation can be
provided by the components marked TBO on the amplifier
schematic. These were not used in the test, however.

a

r

V+o--~---------------------~~_-_--_-_~_~_--_-_------------------.-------~--,

v+

2pF

POLY100V

20kU

I WILSON CURRENT
MIRROR A

ALL RESISTORS 1% MF 1i4 W
UNLESS OTHERWISE NOTED

33DIlF

100V
f MOSFET BIAS ADJUST

1N965B

r

MPSU10

(ON HEATSINK)

100U

IRF
240

1DOll
INPUT

1

OUTPUT

IXTMI
-=-

17P20

• MOUNTED ON
OUTPUT HEATSINK

WILSON CURRENT
I MIRRORB
100U

100.1.1 r
I

~o---~------------------------~-~-~-~-~-~-~-~~_~_~I----------------~------~

I

2"F

POLY

l00V

+

330"F
1'00V
V-

FIGURE 6: Audio Power Amplifier Schematic

REV. A

OPERA TfONAL AMPLIFIERS 2-321

2

SSM-2131

.,'_~
l

~.'.'_I§
O.OO~L..J....I.l.J,L1..k---'-L.....1...J....JL..LJ.1J.'.k-----:'2"
FREQUENCY (Hz)

FIGURE 7: THD vs. Frequency (at SOW into SQ).

35
30

t-

25

""

20

i

!

15

1.

...
-1.
-15

10

100

lk

10k

lOOk

1M

FREQUENCY (Hz)

FIGURE 8: Frequency Response

10M

One problem that is commonly encountered with current feedback amplifiers is that the mismatch between the two current
mirrors A and B forces a small bias current to appear at the input
buffer's output terminal. This bias current (usually in the range of
1-1 OOIlA) is multiplied by the feedback resistor of 750n and generates an output offset that could be tens of millivolts in magnitude. Matched transistors could be used in the current mirrors,
but these do not completely eliminate the output offset problem.
An inexpensive solution is to use a low power precision DC op
amp, such as the OP-97, to control the amplifier's DC characteristics, thus overriding the DC offset due to mismatch in the currentfeedback loop. The OP-97 acts as a current output DC-servo
amplifier that injects a compensating current into the emitters of
the low voltage regulator transistors (that power the SSM-2131)
to correct for current mirror mismatch. Since the OP-97 is set for
an overall input-to-output gain of24.0 as well, the DC output offset
is equal to the OP-97's Vos x 24.0, which is roughly 1 millivolt.
Thus, any offset trimming can be completely eliminated. Together,
the SSM-2131 and OP-97 provide a level of performance that
exceeds most of the requirements for audio power amplifers. The
driver circuit can handle several pairs of power MOSFETs in the
output stage if required. This topology can be used in circuits that
must deliver several hundreds of watts to a load by using higher
voltage transistors in the driver stage. Operation with rail voltages
in excess of ±1 OOV is possible. If more gain is desired, the SSM2131 input buffer can have its gain increased from the nominal
value of 1.5 used in this example to as much as 10 before its
bandVliidth drops below that of the current feedback section.
DRIVING A HIGH·SPEED ADC
The SSM-2131's open-loop output resistance is approximately
son. When feedback is applied around the amplifier, output resistance decreases in proportion to closed-loop gain divided by
open-loop gain (AvCL/AvOL)' Output impedance increases as
open-loop gain rolls-off with frequency. High-speed analog-todigital converters require low source impedances at high frequency. Output impedance at 1MHz is typically 5n for an SSM2131 operating at unity-gain. If lower output impedances are required, an output buffer may be placed at the output olthe SSM2131.

FIGURE 9: 100kHz Square Wave into SQ.

2-322 OPERATIONALAMPLIFIERS

REV. A

SSM-2131
HIGH-CURRENT OUTPUT BUFFER
The circuit in Figure 10 shows a high-current output stage forthe
SSM-2131 capable of driving a 750 load with low distortion.
Output current is limited by R1 and R2. For good tracking between the output transistors 01' 02' and this biasing diodes D,
and D2 , thermal contact must be maintained between the transistor and its associated diode. If good thermal contact is not
maintained, R1 and R2 must be increased to 5-60 in order to
prevent thermal runaway. Using 50 resistors, the circuit easily
drives a 750 load (Figure 11). Output resistance is decreased
and heavier loads may be driven by decreasing R, and R2 •
Base current and biasing for 01 and 02 are provided by two
current sources, the SSM-2131 and the JFET. The 2kO potentiometer in the JFET current source should be trimmed for optimum transient performance. The case of the SSM-221 0 should
be connected to V-, and decoupled to ground with a O.II1F capacitor. Compensation for the SSM-2131 's input capacitance is
provided by C c ' The circuit may be operated at any gain, in the
usual op amp configurations.

FIGURE 11: Output Buffer Large-Signal Response
operating at any gain including unity. Typically, an SSM-2131
will drive more than 250pF at any temperature. Supply decoupiing does affect capacitive load driving ability. Extra care should
be given to ensure good decoupling when driving capacitive
loads; between 111F and 1OI1F should be placed on each supply
rail.
Large capacitive loads may be driven utilizing the circuit shown
in Figure 12. R, and C 1 introduce a small amount of feedforward
compensation around the amplifier to counteract the phase lag
induced by the ouput impedance and load capacitance. At DC
and low frequencies, R, is contained within the feedback loop.
At higher frequencies, feedforward compensation becomes increasingly dominant, and R, 's effect on output impedance will
become more noticeable .

.....- - _......-CVOUT

v+
10f,lF

~
~

O.1J.1F
V,N

R,
VOUT

,0<>
D.1f.1F

,.51«>
AVCL = 1 + RF/Ro
R, AND", ARE ,-60,
SEE TEXT

BpF

v-

10nF

2k!l

RG

DRIVING CAPACITIVE LOADS
Best performance will always be achieved by minimizing input
and load capacitances around any high-speed amplifier. However, the SSM-2131 is guaranteed capable of driving a 100pF
capacitive load over its full operating temperature range while

C,

211pF

FIGURE 10: High-Current Output Buffer

REV. A

~
~

10J.lF

RF

2k!l

2k!l

FIGURE 12: Compensation for Large Capacitive Loads

OPERA TIONAL AMPLIFIERS 2-323

SSM-2131
When driving very large capacitances, slew rate will be limited
by the short-circuit current limit. Although the unloaded slew rate
is insensitive to variations in temperature, the output current limit
has a negative temperature coefficient, and is asymmetrical with
regards to sourcing.and sinking current. Therefore, slew rate into
excessive capacities will decrease with increasing temperature,
.
and will lose symmetry.

the SSM-2131. Amplifier bandwidth is reduced by the same gain
factor applied to offset voltage, however the SSM-2131 's 10MHz
gain-bandwic;:lth product results in no reduction of the CMOS
converter's multiplying bandwidth.
Individual DAC data sheets should be consulted for more complete descriptions of the converters and their circuit applications.

CAC OUTPUT AMPLIFIER
The SSM-2131 is an excellent choice for a DAC output amplifier, since its high speed and fast settling-time allow quick transitions between codes, even for full-scale changes in output level.
The DAC output capacitance appears at the operational amplifier inputs, and must be compensated to ensure optimal settling
speed. Compensation is achieved with capacitor C in Figure 13.
C must be adjusted to accountforthe DAC's output capacitance,
the op amp's input capacitance, and any stray capacitance at
the inputs. With a bipolar DAC, an additional shunt resistor may
be used to optimize response. This technique is described in
PMI's application AN-24.
FIGURE 14: DAC Output Amplifier Response (PM-7545 DAC)

c
20pF

NOTE: RF IS INTERNAL TO MOST CMOS DACS

FIGURE 13: DAC Output Amplifier Circuit
Highest speed is achieved using bipolar DACs such as PMI's
DAC-08, DAC-l 0 or DAC-312. The output capacitances of these
converters are up to an order of magnitude lower than their CMOS
counterparts, resulting in substantially faster settling-times. The
high output impedance of bipolar DACs allows the output amplifier
to operate in a true current-to-voltage mode, with a noise gain of
unity, thereby retaining the amplifier's full bandwidth. Offset
voltage has minimal effect on linearity with bipolar converters.
CMOS digital-to-analog converters have higher output capacitances and lower output resistances than bipolar DACs. This results in slower settling-times, higher sensitivity to offset voltages
and a reduction in the output amplifier's bandwidth. These tradeoffs must be balanced against the CMOS DAC's advantages in
terms of interfacing capability, power dissipation, accuracy levels and cost. Using the internal feedback resistor which is present on most CMOS converters, the gain applied to offset voltage
varies between 4/3 and 2, depending upon output code. Contributions to linearity error will be as much as 2/3 Vos' In a 10-volt
12-bit system, this may add up to an additional 1/5LSB DNL with

2-324 OPERA TIONAL AMPLIFIERS

COMPUTER SIMULATIONS
The following pages show the SPICE macro-model for the SSM2131 high-speed audio operational amplifier. This model was
tested with, and is compatible with PSpice* and HSPICE**. The
schematic and net-list are included here so that the model can
easily be used. This model can accommodate multiple frequency
poles and multiple zeroes, which is an advanced concept that
results in more accurate AC and transient responses necessary
for simulating the behavior of today's high-speed op amps. For
example, 8 poles and 2 zeroes are required to sufficiently simulate the SSM-2131, which this advanced model can easily accommodate.
Throughoutthe SSM-2131 macro-model, RC networks produce
the multiple poles and zeroes which simulate the SSM-2131 's
AC behavior. Each stage contains a pole or a pole-zero pair. The
stages are separated from each other by voltage-controlled current sources so that the poles and zero locations do not interact.
The only nonlinear elements in the entire model are two p-channel JFETs which comprise the input stage. Limiting the model to
almost entirely linear circuit elements significantly reduces
simulation time and simplifies model development.

"PSpice is a registered trademark of MicroSim Corporation.
"HSPICE is a tradmark of Meta-Software. Inc.

REV. A

SSM-2131
:;;SM-2131 MACRO-MODEL

©PM11989

: subckt SSM-2131 1 232 99 50
: INPUT STAGE & POLE AT 15.9 MHz
rl
r2
r3
r4
cjn
c2
jl
jos
eos
·1

l2

1
2
5

3
3
50
50

6
1
5

2
6

99

4

1

2

7
5

1
2
7

6

4
4

5Ell
5Ell
707.36
707.36
5E-12
7.08E-12
lE-3
4E-12
poly(1) 20 26 1 E-3 1
jx

IX

: POLE AT 53 MHz
r17
,18
cll
c12
g9
pl0

18
18
18
18
99
18

99
50
99
50
18
50

lE6
lE6
3E-15
3E-15
17261E-6
26171E-6

• POLE AT 53 MHz
r19
,20
c13
c14
gll
p12

19
19
19
19
99
19

99
50
99
50
19
50

lE6
lE6
3E-15
3E-15
18261E-6
26181E-6

: SECOND STAGE & POLE AT 45 Hz

:COMMON-MODE GAIN NETWORK WITH ZERO AT 100 kHZ

,5

9

,S

9

c3
c4
gl
g2
v2
v3
dl
d2

9
9
99

,21
,22
11
12
g13
p14

9
99
10
9
10

99
50
99
50
9
50
8
50
8

9

17S.84E6
17S.84E6
20E-12
20E-12
poly(l) 5 6 3.96E-3 1.4137E-3
poly(l) 6 5 3.96E-3 1.4137E-3
2.5
3.1
dx
dx

: POLE-ZERO PAIR AT 1.80 MHz/2.20 MHz

,7

11
r8 11
r9 11
rl0 11
c5 12
c6 13
g3 99
p4 11

99
50
12
13

99
50
11
50

lE6
lE6
4.5ES
4.5E6
16.1E-15
16.1E-15
9 2S lE-6
26 9 lE-S

: POLE-ZERO PAIR AT 1.80 MHz/2.20 MHz
,11
r12
r13
r14
c7
c8
g5
p6

14
14
14
14
15
16
99
14

99
50
15
16
99
50
14
50

lE6
lE6
4.5ES
4.5E6
lS.lE-15
16.1E-15
11 26 lE-6
2611 lE-6

: POLE AT 53 MHz
r15
r16
c9
cl0
g7
p8

REV. A

17
17
17
17
99
17

99
50
99
50
17
50

lES
lE6
3E-15
3E-15
1426 lE-S
26 14 lE-6

20
20
21
23
99
20

21
23
99
50
20
50

lE6
lE6
1.5915
1.5915
3 26 lE-ll
26 3 lE-ll

:POLE AT 79.6 MHz
,24
r25
c15
c16
g15
p16

25
25
25
25
99
25

99
50
99
50
25
50

lE6
lE6
2E-15
2E-15
1926 lE-6
26 19 lE-6

:OUTPUT STAGE
r26
r27
,28
,29
13
g17
g18
g19
g20
vS
v7
d5
d6
d7
d8
d9
dl0

2S
2S
27
27
27
30
31
27
50
28
27
25
29

99
99
50
50

99
50
99
50
32
50
50
99
27
27
29
28
25
30
31
30
31

111.1E3
111.1E3
90
90
2.5E-7
252711.1111E-3
272511.1111E·3
992511.1111E-3
2550 11.1111E-3
0.7
0.7
dx
dx
dx
dx
dy
dy

• MODELS USED
-model jx PJF(BETA=999.3E-S VTO=-2.000 IS=4E-ll)
-model dx
D(IS=lE-15)
-model dy D(IS=l E-15 BV=50)
-ends SSM-2131

OPERA TlONALAMPLIFIERS 2-325

•

2-326 OPERA TIONALAMPLIFIERS

REV. A

low Noise Audio
Operational Amplifier
SSM-2134 I

1IIIIIIII ANALOG

WDEVICES
FEATURES

GENERAL DESCRIPTION

• Very Low Input Noise Voltage ......••..•...... 3.5nV/.../Hz Typ
• Wide Small-Signal Bandwidth ......................... 1OM Hz Typ
• High Current Drive Capability
(10V RMS into 600n@V s =±18V)
• High Slew Rate •................................................. 13V/IlS Typ
• Wide Power Bandwidth ................................... 200kHz Typ
• High Open-Loop Gain ................................... 200VImV Typ
• Extended Industrial
Temperature Range ................................... -40°C to +85°C
• Direct Replacement for Industry Standard 5534AN

The SSM-2134 is a high performance low noise operational
amplifier which offers exceptionally low voltage noise of 3.5nVI
v'RZ. outstanding output drive capability. and very high smallsignal and power bandwidth. This makes the SSM-2134 an ideal
choice for use in high quality and professional audio equipment.
instrumentation. and control circuits.

The SSM-2134 is offered in an a-pin plastic DIP and its performance and characteristics are guaranteed over the extended industrial temperature range of -40°C to +85°C.

APPLICATIONS
•
•
•
•
•
•
•

The SSM-2134 is internally compensated for Av ~ 3. However.
the frequency response can be optimized with an external
compensation capacitor to enable the SSM-2134 to operate at
unity-gain or drive large capacitive loads.

High Quality Audio Amplifiers
Telephone Channel Amplifiers
Active Filter Designs
Microphone Preamplifiers
Audio Line Drivers
Low-Level Signal Detection
Servo Control Systems

PIN CONNECTIONS
BALANCE

S-PIN
EPOXY DIP
(P-Suffix)

SIMPLIFIED SCHEMATIC
BALANCE/COMP

BALANCE

COMP

r---~~~--------------~--~~------~r---------.-------~------~~v+

(+) INPUT

O-=---_......r----1---+---....,

(-) INPUT

0----*-............,[.

OUTPUT

SUBSTRATE

REV. A

OPERA TIONALAMPLIFIERS 2-327

I

SSM-2134
ORDERING INFORMATION t
OPERATING
TEMPERATURE
RANGE

PACKAGE
SSM2134P

8-Pin Plastic

-40°C to +85°C

Power Dissipation ........................................................ 300mW
Derate Above +24°C ............................................. 2.5mWrC
Short-Circuit Duration (Note 3) .................................. Indefinite
Operating Temperature Range ....................... -40°C to +85°C
Storage Temperature .................................... -60°C to + 150°C
NOTES:
1. The SSM-2134's inputs are protected by diodes. Current limiting resistors are

not used in order to achieve low noise. If differential input voltage exceeds ±O.6V,

ABSOLUTE MAXIMUM RATINGS
Supply Voltage .................. ,.. ,.. ,..... ,..... ,.. ,........... " ......... ,., ±22V
Differential Input Voltage (Note 1) .................................. ±O.5V
Input Voltage (Note 2) ...................................................... ±22V

the input current should be limited to lOrnA.
2. For supply voltages less than ±22V, the absolute maximum input voltage is
equal to the supply voltage.
3. Output maybe shorted to ground at Vs =±15V, TA = +25°C. Temperature andl
or supply voltages must be limited to ensuredissipation rating is not exceeded.

ELECTRICAL CHARACTERISTICS at Vs ; ±15V and T A ; +25°C, unless otherwise noted.
SSM·2134P
PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX
2

Input Offset Voltage

Vas

-40°C ~ T A ~ +85°C

0.3
0.4

Input Offset Current

los

-40'C ~ T A ~ +85°C

25

Input Bias Current

IB

-40'C ~ T A ~ +85'C

Large-Signal Voltage Gain

Ava

Supply Current

15

ISY

200

15

150

±12
±15

±13

No Load

(Note 1)

R'N

(Note 2)

Input Voltage Range

IVR

Common-Mode Rejection

CMR

mV

nA

nA

V/mV

4.5

V s =±15V, RL ~600n

Ise

Differential-Mode

2000

25

Output Short-Circuit Current
Input Resistance-

1500

500

RL ~600n, V o =±10V
-40°C ~ T A ~ +85°C

Va

300
400

350

RL ~600n, V o =±10V

Output Voltage Swing

3

UNITS

Vs = ±18V, RL ~ 600n

V cM =±12V

6.5

rnA
V

±16
65

rnA

30

100

kn

±12

±13

V

70

114

dB
~V!V

Power Supply Rejection Ratio

PSRR

Rise Time

t,

RL ~ 600n, C c = 22pF

20

ns

Overshoot

OS

C L = 100pF

20

%

Cc = 0, fa = 10kHz
C c = 22pF, fa = 10kHz

6
2.2

V/mV
MHz

ACGain
Unity-Gain Bandwidth

100

GBW

Cc = 22pF, C L = 100 P F

10

Slew Rate

SR

Cc=O
C c = 22pF

13

Full Power Bandwidth

BWp

Input Noise Voltage Density

e,

fo= 30Hz
fa = 1kHz

5.5

7.0

3.5

4.5

Input Noise Current Density

i

,

fa = 30Hz
fo= 1kHz

2.5
0.6

pAl-/Hz

0.7

dB

0.025

%

Va =±10V, C c = 22pF

95
200

Cc=O

Broadband Noise Figure

FN

Rs = 5kn, f = 10Hz to 20kHz

Total Harmonic Distortion

THD

Y'N = 3V RMS ' Av = +1000, RL = 2kn

NOTES:
1. Output may be shorted to ground at V s = ±15V, T A = +25'C. Temperature andl
or supply voltages must be limited to ensure dissipation rating is not exceeded.
2. Guaranteed by design.

2-328 OPERA TIONAL AMPLIFIERS

V/~s

6

kHz

nV/VHz

Specifications subject to change, Consult latest data sheet.

REV. A

SSM-2134
TYPICAL PERFORMANCE CHARACTERISTICS Continued

,·.omnmm

VOLTAGE NOISE DENSITY
vs FREQUENCY

CURRENT NOISE DENSITY
vs FREQUENCY

BROADBAND INPUT
NOISE VOLTAGE

~~4=P+Pm==+++P~~:r~~

TA= +25°C
VS=±15V

'02

1---H-t+I-l*---l-+1+1+Ht-~: ~ ::;

8

"

TA,=+25"C

,.

>
a

VS=±15V

w

"i!!
~

I
i ,.,.,

,.

,.

'~,~-U~~,._~~~,L.~~~~

••, L..-...J....Ju...LWIL_.L..I..L.L.I..LW...---'....LJu..&.JJII
100
1k
'Ok

FREQUENCY (Hz)

.

'.Hz.......

,0'

. /~
V

i8 ,.

. / "/

...

~ ,.,.,
,

. ,. ,.

,

Rs(Q)

CLOSED·LOOP GAIN
vs FREQUENCY

t,t,=.25OC

..zsoc

Vs=±1SV

'0'

i

'03

'20
TAS

~

,02

OPEN·LOOP GAIN
vs FREQUENCY

TOTAL INPUT NOISE DENSITY

,

...

,

FREQUENCY (Hz)

,.

.

"~

.. ,.

,

'\ '\..

10

100

1k

10k

100k

Ce=L. ~ V Ce.J,.,.,I
V('I Ce=·7pF
K'(

~,L.03~~~-'~"~~'''~-~'.~'-~''''
FREQUENCY (Hz)

..
..

,.
'20

Ii
~

f~= ....c
Vs=±15Y

r--

"

..

3 ..

PSR vs FREQUENCY

T.=ob·e
Vs st15Y

"

I

7D

•PO)
~

....

so

1M

10M

100M

•,.

,.

....!•

,

I"

40

20

~~

100k

100M

40

\\\
1Dk

1aM

CMR vs FREQUENCY

T.=+25°C
VS=(15V -

1k

1M

FREQUENCY (Hz)

'40

fREQUENCY (Hz)

REV. A

'\ ~

Ce=22pF

OUTPUT VOLTAGE SWING
vs FREQUENCY

,.
100

~=DPF

~

-4D

3D

•

""""

~

SOURCE RESISTANCE

'02

..

RL_1DIXl
CL_3OpF

i!!

V'THERMAL NOISE OF

~

Ii
~
z
C

T&=+25°C
Vs=±15Y

Vs=±1SV

.. = f::::;:: .......

3D
1k

10k

1C1C1k

FREQUENCY (Hz)

1M

'OM

1k

10k

lOOk

'M

FREQUENCY (Hz)

OPERA TlONAL AMPLIFIERS 2-329

SSM-2134
TYPICAL PERFORMANCE CHARACTERISTICS Continued

SLEW RATE vs

,.

COMPENSATION CAPACITOR

'2

r\

~
I........

2.

r---.

40

I'- t..

a.

I''00

Cc(pF)

TOTAL HARMONIC DISTORTION vs FREQUENCY

TOTAL HARMONIC DISTORTION vs FREQUENCY

."lIr:=-!·~PI~~~II~~~~Y"~~3~·~~""~.
'TA=+H-C_::
;"AL-2IUl
":

-,1,-

!:~:~:~il~i--'-~·~,+:~;!~;i~~~~·~,n:i~'~·~

•••1• . . ... ' .

TOTAL HARMONIC DISTORTION vs FREQUENCY

2-330 OPERA TIONALAMPLIFIERS

:; ..,

':iiij

*.

TOTAL HARMONIC DISTORTION vs FREQUENCY

REV. A

SSM-2134
TYPICAL PERFORMANCE CHARACTERISTICS Continued

INPUT COMMON-MODE
VOLTAGE vs SUPPLY VOLTAGE

OUTPUT VOLTAGE SWING
vs LOAD RESISTANCE

SUPPLY CURRENT

vs SUPPLY VOLTAGE

30

16

TA=+25°C

NEGATIVE

TA

Vs=±15V

14

POSITIVE

~

1

~

20

w

II

"~

~

g

~

10

;!;

~

TA=+2$°C

VS=I±1s~1

o

2

100

100k

lk
10k
LOAD RESISTANCE (0)

b

o

A-1-

V

posmVE-

'/

±lO

o

±30

±20

120

~

0.8

..........

~

0.3

"

Iii

~

I

""

I"

i'o..

g
0.2

0.1

±4

~

m

'-...I - , /

110
0.8

0.4

±6 ±8 ±lO ±12 ±14 H6 ±18 ±20
SUPPLY VOLTAGE (VOLTS)

CMR vs TEMPERATURE

Vs= ±15V

OA

a

±2

130

1.0
Vs=I±15V

:>

o

INPUT BIAS CURRENT
vs TEMPERATURE

O.S

L-- f.-

.- I-...... .-

SUPPLY VOLTAGE (VOLTS)

INPUT OFFSET VOLTAGE
vs TEMPERATURE

=+25°C

r---..~

i

iD

100

"'
"

90

-

Vs= ±15V

~

:0

......... i--

90

0.2
70

o
-55

-25

25

50

75

100

125

o

-25

-55

25

so

75

TEMPERATURE 1°C)

TEMPERATURE (OC)

PSR vs TEMPERATURE

SUPPLY CURRENT
vs TEMPERATURE

100

.0
-5S

125

-25

7.

so

2S

100

12S

TEMPERATURE rC)

SHORT-CIRCUIT CURRENT
vs TEMPERATURE
100

Vs='±15V

Vs='±15V

.,/

..-

""

.-...- ~

.-

- --

Vs= ±15V

80

i

i
0

25

50

75

TEMPERATURE (OC)

REV. A

i'o..

"

40

o

2

-25

'- ..........

60

~

0

-55

.........

100

125

-55

-25

25

50

75

TEMPERATURE «C)

100

125

-55

-25

25

50

f......

75

100

125

150

TEMPERATURE eel

OPERA T10NAL AMPLIFIERS 2-331

II

SSM-2134
APPLICATIONS INFORMATION
PREAMPLIFIER-RIAA/NAB COMPENSATION
+15V

O.22pF

INPUT~

>----.---0 OIITPUT

lRSI...
100kU

1MU:

NAB

1.1MU

16kn

O.003F

"SELECT TO PROVIDE SPECtFIED TRANSDUCER LOADING

OUTPUT NOISE O.8mVRMS (WITH INPUT SHORTED)

70

60

70

BODEPL~

60

I--'-~

50

50

i

40

~

30

'\.

"

..

{-ACTUAL
_RESPONSE _

.

~

30

"

~-

.. J.

.1.

::".~r:rUAL RESPONse -

BODE PLOT

"

'~

20

'0

'0'

~

iD

,-~

,

'0
102

103

1()4

FREQUENCY (Hz)

'0'

BODE PLOT OF RIAA EQUALIZATION AND THE
RESPONSE REALIZED IN AN ACTUAL CIRCUIT
USING THE SSM·2134

'0'

102

103

t()4

FREQUENCV (Hz)

'"

'05

BODE PLOT OF NAB EQUALIZATION AND THE
RESPONSE REALIZED IN THE ACTUAL CIRCUIT
USING THE SSM-2134

TEST CIRCUIT
FREQUENCY COMPENSATION
AND OFFSET VOLTAGE
ADJUSTMENT CIRCUIT

CLOSED-LOOP FREQUENCY RESPONSE
v.

J'OOpF

600n

v-

2-332 OPERA TlONAL AMPLIFIERS

REV. A

Dual, Low Noise, High-Speed
Audio Operational Amplifier (AvCL> 3)
SSM-2139 I

r.ANALOG
WDEVICES

FEATURES
• Ultra-Low Voltage Noise .................................. 3.2nV/.,I'Hi
• High Slew Rate ......................................................... 11 VI~s
• Excellent Gain Bandwidth Product ........................ 30MHz
• Low Supply Current (Both Amplifiers) •.••••..•..•.••.••.•.. 4mA
• Low Offset Voltage ................................................... 500~V
• High Gain ............................................................ 1,700V/mV
• Compensated for Minimum Gain of 3
• LowCost
• Industry Standard 8-Pln Plastic Dual Pinout
APPLICATIONS
• Microphone Preamplifiers
• Audio Line Drivers
• Active Filters
• Phono and Tape Head Preamplifiers
• Equalizers
ORDERING INFORMATION
PACKAGE
PLASnc
16-PIN

GENERAL DESCRIPTION
The SSM-2139 is a low noise, high-speed dual audio operational
amplifier which has been internally compensated for gains equal
to, or greater than three.
•
This monolithic bipolar op amp offers exceptional voltage noise
performance of 3.2nV/v'Hz (typical) with a guaranteed specification of only 5nV/v'HZ MAX@ 1kHz.
The high slew rate of 11 V/~s and the gain-bandwidth product of
30MHz is achieved without compromising the power consumption of the device. The SSM-2139 draws only 4mA of supply current for both amplifiers.
Continued

PIN CONNECTIONS

B-PlN

SOL

OPERATING
TEMPERATURE
RANGE

SSM2139P

SSM2139S

XINO'

• XINO = -40°C to +85°C
For availability on SOL package, contact your local sales office.

8-PIN
PLASTIC MINI-DIP
(P-Suffix)
16-PIN SOL
(S-Suffix)

SIMPLIFIED SCHEMATIC (One of two amplifiers is shown.)
r-.-------.-----~----_.--_.------------------------_.--~--~~~O~

OUT

-INo--~--+

~----------------~--~--------~--------~~--~--+-~--~-O~

REV. A

OPERATIONAL AMPLIFIERS 2-333

SSM-2139
These characteristics make the SSM-2139 an idea!.cho.iCe for
use in high quality professional audio equipment, instrumentation, and control circuit applications.
.
The low offset voltage Vos of 50011 V MAX (2011V typical) and offs~
voltage drift of only 2.511 V1°C MAX assures system accuracy and
eliminates the need for external Vos adjustments.
The SSM-2139's outstanding open-loop gain of 1,700,000 and
its exceptional gain linearity eliminate incorrectable system
nonlinearities and provides superior performance in high closedloop gain applications, such as preamplifiers.
The SSM-2139 is offered in an 8-pin plastic DIP and Small Outline (SO) package and its performance and characteristics are
guaranteed over the extended industrial temperature range of40°C to +85°C.

Input Voltage ......................•............................. Supply Voltage
Short-Circuit Duration ................................ Continuous
Storage Temperature Range .......................... -65°C to + 150C
Lead Temperature Range (Soldering, 60 sec) ............... 300°C
Junction Temperature (T) ............................. -65°C to +150°C
Operating Temperature Range
SSM-2139 (P, S) ............................................ -40°C to +85°C
O~put

PACKAGE TYPE

alA (Note t)

UNITS

a lc

8-Pin Plastic DIP (P)

96

37

°CIW

16-Pin SOL (5)

92

27

°elW

NOTES:
1. alA is specified for worst case mounting conditions, i.e., a.Ais specified fordevice
in socket for P-DIP package; a iA is specified for devihe soldered to printed
circuit board for SOL package.
2. The SSM-2139 inputs are protected by back-to-back diodes. Current limiting

resistors are not used in order to achieve low noise performance. If differential

ABSOLUTE MAXIMUM RATINGS

voltage exceeds ±1.0V, the input current should be limited to ±25mA.

Supply Voltage .................................................................. ±18V
Differential Input Voltage (Note 2) .................................. ±1.0V
Differential Input Current (Note 2) ................................. ±25mA

ELECTRICAL CHARACTERISTICS at V5 =±15V, T A =25°C, unless otherwise noted.
SSM-2139
PARAMETER

SYMBOL

CONDITIONS

Input Noise Voltage

9 np"p

O.IHzto 10Hz
(Note 1)

Input Noise
Voltage Density

en

Input Noise
Current Density

in

TYP

MAX

UNITS

80

200

nVp-p

fo = 10Hz
fo= 100Hz
fo= 1kHz
(Note 2)

3.6
3.2
3.2

6.5
5.5
5.0

fo = 10Hz
fO = 100Hz
fO= 1kHz

1.1
0.7
0.6
11

V/~s

30

MHz

130

kHz

Slew Rate

SR

Gain Bandwidth Product

GBW

fo= 100kHz

Full Power Bandwidth

BWp

Vo =27Vp_p
RL = 21<0 (Note 3)

Supply Current
(All Amplifiers)

ISY

No load

Total Harmonic Distortion

THO

RL =2kQ
VO =3V RMS ' fo= 1kHz

Input Offset Vo~age

Vos

Input Offset Current

los

Vc",=OV

Input Bias Current

18

Vc",=OV
Vo =±10V
RL= 10kQ

Avo

Output Voltage Swing

Vo
Vo +
V o-

RL ~2kQ
RL ~600Q

CMR

VCM =±12V

2-334 OPERATIONAL AMPLIFIERS

4

RL =2kQ
RL =600Q

5

nV/v'Hz

pAiv'Hz

6.5

0.002
20

Large-Signal
Voltage Gain

Common-Mode Rejection

MIN

mA

%
500

~V

50

nA

80

nA

1000
500

1700
900
900

V/mV

±12

±13.5
+13
-10

V

115

dB

RL~600Q

94

REV. A

SSM-2139
ELECTRICAL CHARACTERISTICS at Vs =±15V. TA =25°C. unless otherwise noted. Continued
SSM-2139
PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

Power Supply
Rejection Ratio

PSRR

Vs = ±4.5V to ±18V

105

120

dB

Input Voltage Range

IVR

±12.0

±12.5

V

20
40

rnA

(Note 4)

UNITS

Output Short·Circuit
Current

Isc

Input Resistance
Common·Mode

A1NCM

20

GO

Input Resistance
D'fferential·Mode

R'N

004

MO

Input Capacitance

C'N

3

pF

175

dB

Channel Separation

Sink

MAX

CS

Source

Va = 20V p_p
fo= 10Hz (Note 1)

125

NOTES:
1. Guaranteed but not 100% tested.
2. Sample tested.
3. BWp = SR/2n VPEAK .
4. Guaranteed by CMR test.

ELECTRICAL CHARACTERISTICS at Vs =±15V. -40°C S T AS 85°C. unless otherwise noted.
SSM-2139
PARAMETER

SYMBOL

CONDITIONS

Supply Current
(All Amplifiers)

ISY

No Load

Output Vonage Swing

Va

Large·Signal
Voltage Gain

Ava

MIN

TYP

MAX

UNITS

4.4

7.2

rnA

RL~2ka

±12

±13

V

Va = ±10V
RL = 10ka
RL =2kO

500
250

1400
700

VlmV

Input Offset Voltage

Vas

45

700

~V

Average Input
Offset Voltage Drift

TCVos

004

2.5

~V/'C

Input Offset Current

los

VCM=OV

1.5

60

nA

6

90

nA

Input Bias Current

I.

VCM=OV

Common·Mode
Rejection

CMR

VCM =±12V

Power Supply
Rejection Ratio

PSRR

Input Voltage Range

IVR

94

115

dB

Vs =±4.5to±18V

100

115

dB

(Note 1)

±12

±12.5

V

NOTES:
1. Guaranteed by CMR test.

REV. A

OPERA TIONAL AMPLIFIERS 2-335

II

SSM-2139
TYPICAL PERFORMANCE CHARACTERISTICS

VOLTAGE NOISE DENSITY
vs FREQUENCY

VOLTAGE NOISE DENSITY
vs SUPPLY VOLTAGE

O.lHz TO 10Hz NOISE

10

••

s;-

TA= +25OC

TA=+25"C
Ys =±15V

"

~

,~

o

"f
:.

4

w

~

r--....
,. po

z~

Hz

"~

AT 10kHz

g

3

..

w

AT 1kHz

0
z

:lI

~
g

10
TIME (SEC)

TA
1

10

1

,.

100

1

.

0

FREOUENCY (Hz)

"0

INPUT OFFSET VOLTAGE
vs TEMPERATURE

105E~1I
=
±15V

/V

ys=l t1SV
40

§l~"".g.~1
~I=

/

1--Hf+tHttt-H" 1ft CORNER =200Hz

100

lk

10k

....

-75

--50

-25

25

75

50

2
-75

100

V

-50

-25

25
~
TEMPERATURE re)

75

100

125

TOTAL SUPPLY CURRENT
vs SUPPLY VOLTAGE

T.I=.~C

!±15

Ys =±15V

V

.........
........

~

i-"""

I/~

INPUT BIAS CURRENT vs
COMMON-MODE VOLTAGE

VcM=OV

~

V

TEMPERATURE (OC)

INPUT OFFSET CURRENT
vs TEMPERATURE

o_

,/

I

FREQUENCY (Hz)

\Is

=±15V

VCM=OV

/

.. /

-10

10

Vs

/

~
i

0.1 '--'-J..J..J..LUl'::--'-J..J..J..LUl'--'-J..J..J.J.llJJ

INPUT BIAS CURRENT
vs TEMPERATURE

~

TA= +25"C

g

±20

"5

SUPPLY VOLTAGE (VOLTS)

CURRENT NOISE DENSITY
vs FREQUENCY
Vs

=+25OC

Vs =±15V

"'"

~

r~

n

-

~

m

TEMPERATURE COC)

2-336 OPERA TIONAL AMPLIFIERS

",.

,.

f

-

i
i

51--~---+--~--~

B

......,

~

~

2
-12.5 -10 -7.5 -5 -2.5

0

2.5

5

7.5

COMMON·MODE VOLTAGE (VOLTS)

10 12.5

3

2'---'---'---'--~

o

±5

±10

±15

±2D

SUPPLY VOLTAGE (VOLTS)

REV. A

SSM-2139
TYPICAL PERFORMANCE CHARACTERISTICS Continued

TOTAL SUPPLY CURRENT
vs TEMPERATURE

OPEN-LOOP GAIN
vsFREQENCY

.

I ••

TA=+2SOC

VS=±15V

".

--

. /V

..

""

60

'\..

""

""

~

~

~

~

~

~

•

m

1

10

100

1k

OPEN-LOOP GAIN
vs SUPPLY VOLTAGE

20

r-...

'\..

~

~
0

2.

3000

1000

V

••

/

±15

V~=±I'~

..

,

TA
Vs

13

----

.'"

t:

•. 1

'1.

~

..
0

10M

100M

15

=
=±15V

I.

THO= 1%

13

TA +2SOC
Vs

=

TA +25·C
Vs =+15V

POSITIVE

SWING

~
g

12

JY

!>

11

~

SWING

10

~EGATIVE

~ A,
Vo

6"

+25 0
±15V

,.

5
100.

1M

100

10M

H_

!:VRIIS =

Ii

10.

LOAD RESISTANCE (U)

FREQUENCY (Hz)

~
~

I--

1M

MAXIMUM OUTPUT VOLTAGE
vs LOAD RESISTANCE

TOTAL HARMONIC DISTORTION
vs FREQUENCY

SLEW RATE
vs TEMPERATURE

".. . /

100k

!

•,.

±2•

-8A

10k

FREQUENCY (Hz)

12

SUPPLY VOLTAGE (VOLTS)

"

....

10M 100M

/
±10

±5

""

1M

16

//

....

I.

1\

2'

~

"

,

28

....
~

lOOk

MAXIMUM OUTPUT SWING
vs FREQUENCY

5000

~

10k

"-

FREQUENCY (Hz)

TEMPERATURE ("C)

II

"-

40

2.

•_

TA~'~~
Vs=±15V

Vs =±15V

,
"
~ ••
"~
~ ••
g
••
iD

~ i--

CLOSED-LOOP GAIN
vs FREQUENCY

TOTAL HARMONIC DISTORTION
vs OUTPUT VOLTAGE

r--

•.5

r--r-,-....,-,.-r--r-,-....,

==

••1

f--+-+---+-+-f--+-+---+

-

-

AV= +100

.... 1--+-+--+-+-1--+-+--1

!: ::= --I--1-+-f--+--l

0.01

0.01

f-'O"-=r20"""'"ZT--i----1r-+-f--t--l

a:

l!...
i!
I;!

0.001

7

-75

-50

-25

0

25

50

75

TEMPERATURE ("C)

REV. A

100

125

150

1.

0.001
100

"

FREQUENCY (Hz)

10k 20k

I.....-'-_-'--1_..L..._'--'-_-'--I
1
OUTPUT VOlTAGE

Nt.. )

OPERA TIONAL AMPLIFIERS 2-337

SSM-2139
",
"11

-OUT

50n

",

",

2ka

",2ka

IN

",

",

10kn

2k"

",.
1ka

10kn

""

10kn

",

""

lkn

",

""

2ka

son

+OUT

",
tOkQ

FIGURE 1: High-Speed Differential Line Driver

APPLICATIONS INFORMATION
+15V

VIN o-~------'-I

200a

200a

200.0

HIGH·SPEED DIFFERENTIAL LINE DRIVER
The circuit of Figure 1 is a unique approach to a line driver circuit
widely used in professional audio applications. With ±18V supplies, the line driver can deliver a differential signal of 30Vp-p
into a 1.5kn load. The output of the differential line driver looks
exactly like a transformer. Either output can be shorted to ground
without changing the circuit gain of 5, so the amplifier can easily
be set for inverting, noninverting, or differential operation. The
line driver can drive unbalanced loads, like a true transformer.
LOW NOISE AMPLIFIER
A simple method of reducing amplifier noise is by paralleling
amplifiers as shown in Figure 2. Amplifier noise, depicted in Figure
3, is around 2nV/y'HZ@ 1kHz (R.T.I.). Gain for each paralleled
amplifier and the entire circuit is 1000. The 200n resistors limit
circulating currents and provide an effective output resistance
of50n.

SOkn

200a

SOka

FIGURE 2: Low Noise Amplifier

FIGURE 3: Noise Density of Low Noise Amplifier, G = tOOO

2-338 OPERA TlONAL AMPLIFIERS

REV. A

SSM-2139
VOLTAGE AND CURRENT NOISE
The SSM-2139 is a low noise, high-speed dual op amp, exhibiting a typical voltage noise of only 3.2nVfVHz@ 1kHz. The exceptionally low noise characteristics of the SSM-2139 is in part
achieved by operating the input transistors at high collector currents since the voltage noise is inversely proportional to the
square root of the collector current. Current noise, however, is
directly proportional to the square root of the collector current.
As a result, the outstanding voltage noise performance of the
SSM-2139 is gained at the expense of current noise performance, which is normal for low noise amplifiers.
To obtain the best noise performance in a circuit, it is vital to
understand the relationship between voltage noise (en)' current
noise (in)' and resistor noise (et ).

100

~

-

SSM~

./
1

En = "\j'(e n)2 + (in RS)2 = (et )2

..H1
RESISTOR

~~'~~ ~~LY
1k

lDO

TOTAL NOISE AND SOURCE RESISTANCE
The total noise of an op amp can be calculated by:

V

10k

lOOk

Rs - SOURCE RESISTANCE (U)

FIGURE 4: Total Noise vs. Source Resistance (Including
Resistor Noise) at 1kHz

where:
En = total input referred noise
en = op amp voltage noise

lDO

in = op amp current noise
et = source resistance thermal noise

i/

Rs = source resistance
The total noise is referred to the input and at the output would be
amplified by the circuit gain.
Figure 4 shows the relationship between total noise at 1kHz and
source resistance. For Rs < 1kQ, the total noise is dominated by
the voltage noise ofthe SSM-2139. As Rs rises above 1kQ, total
noise increases and is dominated by resistor noise rather than
by voltage or current noise of the SSM-2139. When Rs exceeds
20kQ, current noise of the SSM-2139 becomes the major contributor to total noise.
Figure 5 also shows the relationship between total noise and
source resistance, but at 10Hz. Total noise increases more
quickly than shown in Figure 4 because current noise is inversely
proportional to the square root of frequency. In Figure 5, current
noise ofthe SSM-2139 dominates the total noise when Rs > 5kQ.

V
~SSM-2139

...I'r

V
100

RESISTOR
NOIS~~~lY
1k

10k

lOOk

Rs - SOURCE RESISTANCE (U)

FIGURE 5: Total Noise vs. Source Resistance (Including
Resistor Noise) at 10Hz

From Figures 4 and 5, it can be seen that to reduce total noise,
source resistance must be kept to a minimum.

REV. A

OPERA TIONAL AMPLIFIERS 2-339

•

SSM-2139
Figure 6 shows peak-to-peak noise versus source resistance over
the 0.1 Hz to 10Hz range. Once again, at low values of Rs ' the
voltage noise of the SSM-2139 is the major contributor to peakto-peak noise with current noise the major contributor as Rs increases.

TABLE 1

Strain Gauge

<5000

Typically us!>d in low·frequency
applications.

For reference, typical source resistances of some signal sources
are listed in Table 1.

Magnetic
Tapehead,
Microphone

<1500n

Low I. very important to reduce
self·magnetization problems when
direct coupling is used. SSM·2139 I.
can be neglected.

Magnetic
Phonograph
Cartridge

<15000

Similar need for low I. in direct
coupled applications. SSM-2139 will not

For further information regarding noise calculations, see "Minimization of Noise in Op Amp Applications," Application Note AN-

15.

DEVICE

SOURCE
IMPEDANCE

COMMENTS

introduce any self-magnetization

problem.
Linear Variable

<15000

Used in rugged servo·feedback
applications. Bandwidth of interest is
400Hz to 5kHz.

Differential
Transformer

1000

NOISE MEASUREMENTSPEAK-TO-PEAK VOLTAGE NOISE
The circuit of Figure 7 is a test setup for measuring peak-to-peak
voltage noise. To measure the 200nV peak-to-peak noise
specification of the SSM-2139 in the 0.1 Hz to 10Hz range, the
following precautions must be observed:

/
SSM-2139

V

V
RESISTOR

'0

NOIS~~~LY
1k

'DO

10k

As - SOURCE RESISTANCE (J:!)

1. The device has to be warmed-up for at least five minutes. As
shown in the warm-up drift curve, the offset voltage typically
changes 211V due to increasing chip temperature after powerup. In the 1O-second measurement interval, these temperature-induced effects can exceed tens-of-nanovolts.

...

,

FIGURE 6: Peak-to-Peak Noise (0.1 Hz to 10Hz) vs. Source
Resistance (Includes Resistor Noise)

.,

2. For similar reasons, the device has to be well-shielded from
air currents. Shielding also minimizes thermocouple effects.

·3

.,

51>

.,

50

.,

c,

600kU

9090

2000

O.032p.F

=

":"

GAIN 50,000
Vs =±15Y

FIGURE 7: Peak-to-Peak Voltage Noise Test Circuit (0. 1Hz to 10Hz)

2-340 OPERA TlONAL AMPLIFIERS

REV. A

SSM-2139
3. Sudden motion in the vicinity of the device can also "feedthrough" to increase the observed noise.
4. The test time to measure 0.1 Hz to 1OHz noise should not exceed 10 seconds. As shown in the noise-tester frequencyresponse curve of Figure 8, the 0.1 Hz corner is defined by
only one pole. The test time of 10 seconds acts as a additional pole to eliminate noise contribution from the frequency
band below 0.1 Hz.

II

5. A noise-voltage-density test is recommended when measuring noise on a large number of units. A 10Hz noise-voltagedensity measurement will correlate well with a 0.1 Hz-to-1 OHz
peak-to-peak noise reading, since both results are determined
by the white noise and the location of the 1If corner frequency.
6. Power should be supplied to the test circuit by well bypassed
low-noise supplies, e.g. batteries. These will minimize output
noise introduced via the amplifier supply pins.

0.1

10

100

FREQUENCV (Hz)

FIGURES: O.1Hz to 10Hz Peak-to-Peak Voltage Noise Test
Circuit Frequency Response

CHANNEL SEPARATION TEST CIRCUIT
Sk"

> - - 4 - 0 V1 20Vp-p

5""
500<1

>---0 v,
CHANNEL SEPARATION = 20 tog (

REV. A

V2/~~ )

OPERA TIONAL AMPLIFIERS 2-341

2-342 OPERA TlONAL AMPLIFIERS

Audio AID Converters
Contents
Page

Audio AID Converters - Section 3 .............................................. 3-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
AD1876 - 16-Bit 100 kSPS Sampling ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
AD1878 - High Performance Stereo 16-Bit Oversampled ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
ADl879 - High Performance Stereo 18-Bit Oversampled ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
AD1885 - Low Cost Stereo 16-Bit Oversampled ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

AUDIO AID CONVERTERS 3--1

•

1>
...,
~

Selection Guide

~ Audio Analog-to-Digital Converters
~

Model

Res
Bits

Converter
Type

ADl876
ADl879
ADl878
ADl885

16
18
16
16

Sampling

(')

a
<:

hi:J::J
n:I
Vl

ka
ka
ka

'-0.05 dB Input, A-Weighted Filter

Channels

SNR
OdB-dB typ

THD+N
%typ

Input
Architecture

Input Range
Volts

Supplies
Volts

Power
mWtyp

Pins

Page

Single
Dual
Dual
Dual

No Spec
103
98
85

90'

Single-ended
Differential
Differential
Differential

±3V
±3V
±3 V
±3V

±5, ±12
±5
±5
±5

235
llOO
llOO
500

16
28
28
28

3-3
3-17
3-15
3-19

98
98
85

11IIIIIIII

l6-Bit 100 kSPS
Sampling ADC
AD1876 I

ANALOG

WDEVICES
FEATURES
Autocalibrating
0.002% THO
90 dB S/(N+DI
1 MHz Full Power Bandwidth
On-Chip Sample & Hold Function
2x Oversampling for Audio Applications
16-Pin DIP Package
Serial Twos Complement Output Format
Low Input Capacitance-typ 50 pF
AGND Sense for Improved Noise Immunity

FUNCTIONAL BLOCK DIAGRAM

AGNDSENSE 9
VREF

II

AGND

lEVEL TRANSLATORS

BUSY
DOUT ClK

PRODUCTION DESCRIPTION
The AD1876 is a 16-bit serial output sampling A/D converter
which uses a switched capacitor/charge redistribution architecture to achieve a 100 kSPS conversion rate (10 fLS total
conversion time). Overall performance is optimized by
digitally correcting internal nonlinearities through on-chip
autocalibration.

CAL
ClK

MICROCODED
CONTROllER

DOUT

AD1876

The circuitry of the ADI876 is partitioned onto two monolithic
chips, a digital control chip fabricated with Analog Devices'
DSP CMOS process and an analog ADC chip fabricated with
the BiMOS II process. Both chips are contained in a single
package.
The serial output interface requires an external clock and sample
command signal. The output data rate may be as high as 2.08
MHz, and is controlled by the external clock. The twos complement format of the output data is MSB first and is directly compatible with the NPC SMS805 digital decimation filter used in
consumer audio products. The ADI876 is also compatible with
a variety of DSP processors.
The AD1876 is packaged in a space saving 16-pin plastic DIP
and operates from + 5 V and ± 12 V supplies; typical power consumption is 235 mW. The digital supply (V DO) is isolated from
the linear supplies (VEE and Vee) for reduced digital crosstalk.
Separate analog and digital grounds are also provided.

REV. A

AUDIO AID CONVERTERS 3-3

AD1876-SPECIFICATIONS

(lmin tOlma••

Vee

= +12V ± 5%. VEE = -12V ± 5%. Voo = +5 V± 10%)1

Parameter

Min

TEMPERATURE RANGE

0

TOTAL HARMONIC DISTORTION (THDl'
-0.05 dB Input

AD1876J
Typ

Max

Units

70

·C

-88

1.0

dB
%
dB
%
dB
%

92

dB

92
90
73
70
34
31

dB
dB
dB
dB
dB
dB

-95
0.002
-78
0.01

-20 dB Input

0.004

-40

-60 dB Input
D-RANGE, -60 dB, A-WEIGHTED
SIGNAL-TO-NOISE AND DISTORTION (S/(N+D)) RATIO'
-0.05 dB Input, A-Weighted
-0.05 dB Input, 48 kHz Bandwidth
-20 dB Input, A-Weighted
- 20 dB Input, 48 kHz Bandwidth
-60 dB Input, A-Weighted
-60 dB Input, 48 kHz Bandwidth

83

PEAK SPURIOUS OR PEAK HARMONIC COMPONENT

-99

INTERMODULATION DISTORTION (IMD)4
2nd Order Products
3rd Order Products

-102
-98

FULL POWER BANDWIDTH

-89

dB
dB

1

VOLTAGE REFERENCE INPUT RANGEs (VREF)

3

MHz

5

ANALOG INPU'r
Input Range (VIN)
Input Impedance
Input Capacitance During Sample
Aperture Delay
Aperture Jitter

*
50*
6
100

POWER SUPPLIES
Operating Current
Icc
lEE
Inn
Power Consumption

9
9
3
235

dB

10.0

V

±VREF

V
pF
ns
ps

12

rnA

12

rnA
rnA

12
350

mW

NOTES
IVREF = 5.00 V; conversion rate = 96 kSPS; fIN = 1.06 kHz; VIN = -0.05 dB unless otherwise indicated. All measurements referred to a 0 dB
(10 Vpp) input signal. Values are post calibration.
'Includes first 19 harmonics.
'Minimum value of S/(N+D) corresponds to 5.0 V reference; typical values of S/(N+D) correspond to 10.0 V reference.
4f. = 1008 Hz; fb = 1055 Hz. See Definition of Specifications section and Figure 14.
'See Applications section for recommended voltage reference circuit and Figure 11 for performance with other reference voltage values.
·See Applications section for recommended input buffer circuit.
*For explanation of input characteristics, see "Analog Input" section.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test at worst case temperature. Results from those tests are used to calculate outgoing
quality levels. All min and max specifications are goaranteed. although only those shown in boldface are tested.

ORDERING GUIDE

Model

Temperature
Range

THD
dB

Package
Description

Package
Option*

ADl876JN

O·C to +70·C

-95

Plastic l6-Pin DIP

N-16

*N = Narrow Plastic DIP. For outline information see Package Information section.

3-4 AUDIO AID CONVERTERS

REV. A

AD1876
DIGITAL SPECIFICATIONS (1

min

= +12 V ±

5%, VEE

Test Conditions

Parameter
LOGIC INPUTS
VIH
High Level Input Voltage
Low Level Input Voltage
VIL
High Level Input Current
IIH
Low Level Input Current
IlL
Input Capacitance
CIN
LOGIC OUTPUTS
High Level Output Voltage
VOH
VOL

to 1m••, Vee

Low Level Output Voltage

= -12 V ±

5%, VDD

Min

= +5 V ±

10%)

Typ

2.4
-0.3
VIH = Voo
VIL = 0 V

-10
-10

IOH = 0.1 rnA
IOH = 0.5 rnA
IOL = 1.6 rnA

Voo-I V
2.4

Max

Units

0.8
+10
+10
10

V
V
J.1A
J.1A
pF

0.4

V
V
V

Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test at worst case temperature. Results from those tests are used to calculate outgoing
quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.

ABSOLUTE MAXIMUM RATINGS·
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . + 300°C, 10 sec
Vcc to VEE . . . . . . . . . . . . . . . . . . . . . -0.3 V to +26.4 V
Storage Temperature . . . . . . . . . . . . . . . . -60°C to + 100°C
Voo to DGND . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V
Vcc to AGND . . . . . . . . . . . . . . . . . . . . -0.3 V to +18 V
·Stresses greater than those listed under "Absolute Maximum Ratings" may
VEE to AGND . . . . . . . . . . . . . . . . . . . . -18 V to +0.3 V
cause permanent damage to the device. This is a stress rating only and
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
functional operation of the device at these or any other conditions above those
Digital Inputs to DGND . . . . . . . . . . . . . . . . . 0 V to 5.5 V
indicated in the operarional section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
Analog Inputs, VREF to AGND . . . . . . . . . (Vcc + 0.3 V) to
affect device reliability.
(VEE -0.3 V)
ESD SENSITIVITY _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
The ADI876 features input protection circuitry consisting of large "distributed" diodes and
polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and
fast, low energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the
AD1876 has been classified as a Category I Device.
Proper ESD precautions are strongly recommended to avoid functional damage or perfonnance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test
equipment, and discharge without detection. Unused devices must be stored in conductive foam
or shunts, and the foam discharged to the destination socket before devices are removed. For
further information on ESD precaution, refer to Analog Devices' ESD Prevention Manual.

TIMING SPECIFICATIONS

1
(Tmin

to 1m"., Vee

= +12 V ±

5%, VEE

Parameter

Symbol

Min

Sampling Rate2
Sampling Period2
Acquisition Time (Included in t s )
Calibration Time
CLK Period
CAL to BUSY Delay
CLK to BUSY Delay
CLK to DOVT Hold Time
CLKHIGH
CLKLOW
DouTCLKLOW
SAMPLE LOW to 1st CLK Delay
CAL HIGH Time
CLK to DOUT CLK
SAMPLE LOW

fs = lIts
ts = lIfs
tA
lcr
Ie
leALB
tCB
tco
tCH
leL
tOCL
tsc
tCALH
leDH
tSL

I

= -12 V ± 5%, VDD = +5 V ±
Typ

10

10%, VREF
Max

Units

100
1000

kSPS
I'-s
I'-S
Ie
ns
ns
ns
ns
ns
ns
ns
ns
Ie
ns
ns

2
5000
480
0
50

120

175

80

200

200

275

10

160
50
30
50
4
150
50

= 5.00 V)

NOTES
'See Figure 1 and Figure 2 and the Conversion Control and Autocalibration sections for detailed explanations of the above timing.
2Depends upon external clock frequency; includes acquisition time and conversion time. The minimum sampling rate/maximum sampling period is specified to
account for droop of the internal sample/hold. Operation at slower rates than specified may degrade performance.

REV. A

AUDIO AID CONVERTERS 3-5

•

AD1876
CAL

-.J

II

~~'~~---tC-A-l-B----------- tCT

BUSY

~

\I

I~ ~tl~ ~I

L

tCH tCl

j--tCB

CLK

Figure 1. AD1876 Calibration Timing

r-____

SAMPLE

~~I·~----------ts-(-~-~-)----~~r------------------------.,·I

1~.2-tA--1~......I=-"';;';;''''I--''-'"''~I~
~.'I.~:I~!l~~"-I-----j:t--. .-:. :. tA- I~!
Jt~tCB~CH.1 ~C~

BUSY

~ ~f---t-CB---------

ClK

PREVIOUS LSB

LSB

DOUTClK
Figure 2. Recommended AD1876 Conversion Timing

Definition of Specifications
NYQUIST FREQUENCY
An implication of the Nyquist sampling theorem, the "Nyquist
Frequency" of a converter is that input frequency which is onehalf the sampling frequency of the converter.

BANDWIDTH
The full power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.

TOTAL HARMONIC DISTORTION
Total harmonic distortion (THO) is measured as the ratio of the
rms sum of the first nineteen harmonic components to the rms
value of a I kHz full-scale sine wave input signal and is expressed in percent (%) or decibels (dB). For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.

INTERMODULATION DISTORTION (IMD)
With inputs consisting of sine waves at two frequencies, f. and
fb' any device with nonlinearities will create distortion products,
of order (m+n), at sum and difference frequencies of mf. ± nfb'
where m, n = 0, I, 2, 3 .... Intermodulation terms are those
for which m or n is not equal to zero. For example, the second
order terms are (f. + fb) and (f. - fb), and the third order
terms are (2f. + fb), (2f. - fb), (f. + 2fb) and (f. - 2fb ). The
IMD products are expressed as the decibel ratio of the rms sum
of the measured input signals to the rms sum of the distortion
terms. The two signals applied to the converter are of equal amplitude, and the peak value of their sum is -0.05 dB from full
scale. The IMO products are normalized to a 0 dB input signal.

SIGNAL-TO-NOISE PLUS DISTORTION RATIO
Signal-to-noise plus distortion (SIN + 0) is defined to be the ratio of the rms value of the measured input signal to the rms sum
of all other spectral components below the Nyquist frequency,
including harmonics but excluding dc.
D·RANGE DISTORTION
O-range distortion is the ratio of the distortion plus noise to the
signal at a signal amplitude of -60 dB. In this case, an A·
weight filter is used. The value specified for O-range perfor·
mance is the ratio measured plus 60 dB.

APERTURE DELAY
Aperture delay is the time required after SAMPLE. is taken
LOW for the internal sample-hold of the ADl876 to open, thus
holding the value of VJN.
APERTURE JITTER
Aperature jitter is the variation in the aperture delay from
sample to sample.

3-6 AUDIO AID CONVERTERS

REV; A

AD1876
PIN DESCRIPTION

Pin
No.

Name

Type

Description

SAMPLE

DI

VIN Acquisition Control Pin. During conversion, SAMPLE controls the state of the internal
Sample-Hold Amplifier and initiates conversion (see "Conversion Control" paragraph).
During calibration, SAMPLE is active HIGH, forcing DOUT (Pin 3) LOW. If SAMPLE is
LOW during calibration, DOUT will output diagnostic information (See "Autocalibration"
paragraph. )

2

CLK

DI

Master Clock Input. The ADI876 requires 17 clock pulses to execute a conversion. CLK is
also used to derive DOUT CLK (Pin 14). During calibration, 5000 clock pulses are applied.

3

DouT
DGND

DO

Serial Output Data, Twos Complement format.

4

P

Digital Ground.

5

Vee

P

6

NIC

7

NIC

8

AGND

PIAl

Analog Ground.

9

II

+ 12 V Analog Supply Voltage.
No Connection.
No Connection.

AGND SENSE

AI

Analog Ground Sense.

10

VIN

AI

Analog Input Voltage, referred the AGND SENSE.

11

VREF

AI

External Voltage Reference Input, referred to AGND.

12

VEE

P

-12 V Analog Supply Voltage.

13

Voo

P

+5 V Logic Supply Voltage.

14

DouTCLK

DO

The rising edge of DOUT CLK may be used to latch DouT (Pin 3). DOUT CLK is derived
fromCLK.

IS

BUSY

DO

Status Line for Converter. Active HIGH, indicating a conversion or calibration in progress.

16

CAL

DI

Calibration Control Pin (asynchronous).

Type:

AI = Analog Input.
DI = Digital Input.
DO = Digital Output.
P =- Power.

SAMPLE

CAL
BUSY

ClK
DOUT
DGND

DOUT elK
AD1876
TOP VIEW

VREF
AGNO

VOO

(Not to Scale)
VCC

VEE

NIC

VREF

NIC

VIN

BUSY
OOUTClK
CAL

DOUT

AGNDSENSE

AGND

ClK

Package Pinout

AD1876

Functional Block Diagram

REV. A

AUDIO AID CONVERTERS 3-7

AD1876
FUNCTIONAL DESCRIPTION
The AD1876 is a 16-bit analog-to-digital converter including a
sample/hold input circuit, successive approximation register,
ground sensing circuitry, serial output port and a microcon;
troller based autocalibration circuit. These functions are segmented onto two monolithic chips, an analog signal processor
and a digital controller. Both chips are contained within the
AD1876 package.
The ADl876 employs a successive-approximation technique to
determine the value of the analog input voltage. However, instead of the traditional laser-trimmed resistor-ladder approach,
the ADl876 uses a capacitor-array, charge-redistribution technique. An array of binary-weighted capacitors subdivides the
input value to perform the actual analog to digital conversion.
This capacitor array also serves a samplelhold function without
the need for additional external circuitry.
The autocalibration circuit within the AD1876 employs a microcontroller and calibration DAC to measure and compensate capacitor mismatch errors. As each error is determined, its value
is stored in on-chip memory (RAM). Subsequent conversions
use these RAM values to improve conversion accuracy. The autocalibration routine may be invoked at any time. Autocalibration insures high performance while eliminating the need for any
user adjustments, and is described in detail below.
The microcontroller controls all of the various functions within
the AD1876. These include the actual successive approximation
routine, the autocalibration routine, the sample/hold operation,
and the serial data transmission.
AUTOCALIBRATION
The ADI876 achieves rated performance without the need for
user trims or adjustments. This is accomplished through the use
of on-chip autocalibration.
In the autocalibration sequence, sample/hold offset is nulled by
internally connecting the input circuit to the ground sense circuit. The resulting offset voltage is measured and stored in
RAM for later use. Next, the capacitor representing the most
significant bit (MSB) is charged to the reference voltage. This
charge is then inverted and shared between the MSB capacitor
and one of equal size composed of all the least significant bits.
The difference in the summation of the charges in each of the
equally sized capacitors represents the amount of capacitor mismatch. A calibration D/A converter (DAC) adds an appropriate
value of error correction voltage to cancel the mismatch. This
correction factor is also stored in RAM. This process is repeated
for each of the capacitors representing the remaining bits. The
accumulated values in RAM are then used during subsequent
conversions to adjust conversion results.
As shown in Figure I, when CAL is taken HIGH the ADI876
internal circuitry is reset, the BUSY pin is driven HIGH and
the part prepares for calibration. This is a 'hard' reset and will
interrupt any conversion or calibration currently in progress. In
order to guarantee that all internal undefined states are cleared,
the CAL pin should be held HIGH for at least 4 CLK cycles.
Actual calibration begins when the CAL pin is taken LOW and
completes in less than 5000 clock cycles or about 2.5 msec with
a continuous 500 nsec clock.
During calibration the SAMPLE pin adopts an alternative function. If it is held LOW, DOUT provides diagnostic test information (not intended to be used by the customer). If SAMPLE is
held HIGH, DOUT will be forced LOW. In either case, DOUT
3-8 AUDIO AID CONVERTERS

CLK will continue pulsing. Since the SAMPLE pin has no control over the actual calibration process, normal conversion timing may also be used for calibration. In this case, however, the
DOUT pin will output test information during those periods that
SAMPLE is LOW. BUSY going LOW will always indicate the
end of calibration.
A calibration sequence should be followed by one "dummy"
conversion to clear the internal circuitry of the AD1876 in order
to guarantee subsequent conversion accuracy.
In most applications, it is sufficient to calibrate the AD1876
only upon power-up, in which case care should be taken that
the power supplies and voltage reference have stabilized first.

CONVERSION CONTROL
The AD1876 is controlled by two signals: SAMPLE and CLK,
as shown in Figure 2. It is assumed that the part has been calibrated and the digital I/O pins have the levels shown at the start
of the timing diagram.
A conversion consists of an input acquisition followed by 17
clock pulses which are required to run the 16-bit internal successive approximation routine. The analog input is acquired by
taking the SAMPLE line HIGH for a minimum acquisition time
of t A. The actual sample taken is the voltage present on VIN at
the instant the SAMPLE pin is brought LOW. Care should be
taken to ensure that this negative edge is well defined and jitter
free to reduce the uncertainty (noise) in ac signal acquisition.
On that edge the ADI876 commits itself to the initiated conversion-the input at VIN is disconnected from the internal capacitor array and the SAMPLE input will be ignored until the
conversion is completed (i.e., BUSY goes LOW). After a delay
of at least tse (SAMPLE to eLK setup) the 17 eLK cycles are
applied. BUSY is asserted after the first positive edge on CLK
and reset after the 17th. Both the DOUT and the DOUT CLK
outputs are generated in response to the rising edges of valid
CLK pulses. As indicated in the timing diagram, the 2s complement output data is presented MSB first. This data may be captured with the rising edge of DOUT CLK or the falling edge of
CLK provided leH ;,: leDH. The ADI876 will ignore CLK after
BUSY has gone LOW and not change DOUT or DOUT CLK
until a new sample is acquired. SAMPLE will no longer be ignored after BUSY goes LOW, and so an acquisition may be initiated even during the HIGH time of the 17th CLK pulse for
maximum throughput rate while enabling full settling of the
sample/hold circuitry. Note that if SAMPLE is already HIGH
when BUSY goes LOW, then an acquisition is immediately initiated and tA starts from that time.
During signal acquisition and conversion, care should be taken
with the logic inputs to avoid digital feedthrough noise. It is not
recommended that CLK be running during VIN sampling. If a
continuous CLK is used, then the user must avoid eLK edges
at the instant of disconnecting VIN' i.e., the falling edge of
SAMPLE (see the tse specifications). The LOW level time of
CLK (teLl should be at least lOOns to avoid the negative edge
transition disrurbing the internal comparator's settling (whose
decision is latched on the positive edge of each valid CLK). For
the same reason, it is also not recommended that the SAMPLE
pin change state during conversion (i.e., until after BUSY returns LOW).
Internal de error terms such as comparator voltage offset are
sampled, stored on internal capacitors and used to correct for
their corresponding errors when needed. Because these voltages

REV. A

AD1876
are stored on capacitors, they are subject to leakage decay and
so require refreshing. For this reason the part is required to be
run continuously-i.e., there is a minimum ts specification. If
the part has been idle for too long (i.e., ts has expired) then a
dummy conversion cycle is required to refresh these correction
voltages.
BUSY is HIGH during a conversion and goes LOW when the
conversion is completed. The twos complement output data is
presented MSB first, with MSB data valid on the rising edge of
the second DOUT CLK pulse. Subsequent data is valid on rising
edges of subsequent DOUT CLK pulses. Table I illustrates the
ADI876 output coding.
V IN

Output Code

-Full Scale
- Full Scale + I LSB
Midscale - I LSB
Midscale
Midscale + I LSB
Full Scale - I LSB
Full Scale

100... 00
100... 01
111. .. 11
000 ... 00
000 .... 01
OIl. .. 10
OIl. .. 11

Table I. Serial Output Coding Format (Twos Complement)
A simple method for generating the required signals for the
ADI876 is to connect one or more ADI876s to an NPC SM5805
digital filter. This device supplies all signals required to operate
the ADI876 at a 96 kHz sample rate, which is 2 x Fs for audio
applications. This is more fully discussed in the applications sec·
tion of this data sheet, accompanied by Figures 9 and 10.

APPLICATIONS
POWER SUPPLIES AND DECOUPLING
The ADI876 has three power supply input pins. VEE and Vee
provide the supply voltages to operate the analog portions of
the ADI876 including the ADC and SHA. Vnn provides the
supply voltage which operates the digital portions of the
AD 1876 including the serial output port and the autocalibration
controller.
Decoupling capacitors should be used on all power supply pins.
These capacitors should be placed as close as possible to the

package pins as well as the ground connections. The logic supply (V DO) should be decoupled to digitill common (DGND)
with a 0.1 iJoF ceramic capacitor, and the analog supplies (VEE
and Vee) should be decoupled to analog common (AGND) with
4.7 iJoF and 0.1 iJoF tantalum capacitors in parallel, represented
by CI. An effort should be made to minimize the trace length
between the capacitor leads and the respective converter power
supply and common pins. The recommended decoupling scheme
is illustrated in Figure 3.
As with most high performance linear circuits, changes in the
power supplies can produce undesired changes in the performance of the circuit. Analog Devices recommends that well
regulated power supplies with less than I % ripple be incorporated into the design of any system using these devices.
BOARD LAYOUT
Designing with high resolution data converters requires careful
attention to board layout. Trace impedance is a significant issue.
A 1.22 mA current through a 0.5 n trace will develop a voltage
drop of 0.6 mY, which is 4 LSBs at the 16 bit level for a 10 V
full-scale span. In addition to ground drops, inductive and capacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital signals. Finally, power supplies need to be decoupled in order to
filter ac noise.
Analog and digital signals should not share a common return
path. Each signal should have an appropriate analog or digital
return routed close to it. Using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise.
Wide PC tracks, large gauge wire, and ground planes are highly
recommended to provide low impedance signal paths. Separate
analog and digital ground planes are also desirable, with a single
interconnection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them, if at all, only at right angles. A solid analog
ground plane around the AD 1876 will isolate large switching
ground currents. For these reasons, the use of wire wrap circuit
construction is not recommended; careful printed circuit construction is preferred.
GROUNDING
The ADI876 has three grounding pins, designated ANALOG
GROUND (AGND), DIGITAL GROUND (DGND) and ANALOG GROUND SENSE (AGND SENSE). The analog ground
pin is the "high quality" ground reference point for the device.
The analog ground pin should be connected to the analog common point in the system.
AGND SENSE is intended to be connected to the input signal
ground reference point. This allows for slight differences in level
between the analog ground point in the system and the input
signal ground point. However, no more than 100 mV is recommended between the analog ground pin and the analog ground
sense pin for specified performance.

SYSTEM
DIGITAL
COMMON

SYSTEM
ANALOG
COMMON

Cl

12V -12V

The digital ground pin is the reference point for all of the digital
signals that operate the AD1876. This pin should be connected
to the digital common point in the system. As illustrated in
Figure 3, the analog and digital grounds should be connected
together at one point in the system.

Figure 3. Grounding and Decoupling the AD1876

REV. A

AUDIO AID CONVERTERS 3-9

•

AD1876
VOLTAGE REFERENCE
The AD 1876 requires the use of an external voltage reference.
The input voltage range is determined by the value of the reference voltage; in general, a reference voltage of n volts produces
an input range of ±n volts. Signal-to-noise performance is increased proportionately with input signal range. The AD1876 is
specified with as. 0 V reference and an analog input of ± 5 V.
In the presence of a fixed amount of system noise, increasing
the LSB size (which results from increasing the reference voltage) will increase the effective S/(N + D) performance for input
values below the point where input distortion occurs. Figure 11
illustrates S/(N + D) as a function of input amplitude and reference voltage.
During a conversion, the switched capacitor array of the
ADI876 presents a dynamically changing current load at the
voltage reference as the successive-approximation algorithm cycles through various choices of capacitor weighting. The output
impedance of the reference circuitry must be low so that the
output voltage will remain sufficiently constant as the current
drive changes. In most applications, this requires that the output of the voltage reference be buffered by an amplifier with
low impedance at relatively high frequencies. A (10 fJ.F or
larger) capacitor connected between VREF and AGND will reduce the demands on the reference by decreasing the magnitude
of high frequency components.
The following two sections represent typical design approaches.
VOLTAGE REFERENCE-AUDIO APPLICATIONS
Audio applications require optimal ac performance over a relatively narrow temperature range, with low cost being important.
Figure 4 shows one such approach towards attaining these goals.
A voltage reference, consisting of a Zener diode, capacitor, resistor and op amp with typical component values, is shown. This
simple circuit has the advantage of low cost, but the reference
voltage value is sensitive to changes in the + 12 V supply. Additionally, changes in the Zener value due to temperature variations will also be reflected in the reference voltage. RaPTION
may be required for other component selections if the Zener
requires more current than the op amp can supply.

range, the AD586L grade exhibits less than a 2.25 mV output
change from its initial value at + 25°C. A noise-reduction capacitor, eN' reduces the broadband noise of the AD586 output,
thereby optimizing the overall performance of-the AD1876.
+12V

1

Figure 5.
For higher performance needs, the AD588 reference provides
improved drift, low noise, and excellent initial accuracy. The
AD588 uses a proprietary ion-implanted buried Zener diode in
conjunction with laser-trimmed thin-film resistors for low offset
and gain. The AD588 output is accurate to 0.65 mV from its
value at + 25°C over the ooe to + 70°C range. The circuit shown
in Figure 6 includes a noise-reduction network on Pins 4, 6 and
7. The I fJ.F capacitors form low pass filters with the internal
resistance of the ADS 88 and external 3.9 kfl resistor. This reduces the wide-band (to I MHz) noise of the AD588, providing
optimum performance of the AD1876.

R OPTION

Figure 6.

Figure 4. Low Cost Voltage Reference Circuit
VOLTAGE REFERENCE-PRECISION MEASUREMENT
APPLICATIONS
In applications other than audio, parameters such as low drift
over temperature and static accuracy are important. Figure 5
shows a voltage reference circuit featuring the 5 V AD586. The
AD586 is a low cost reference which utilizes a buried Zener architecture to provide low noise and drift. Over the ooe to +70°C

3-10 AUDIO AID CONVERTERS

ANALOG INPUT
As previously discussed, the analog input voltage range for the
AD1876 is ±VREF • For purposes of ground drop and commonmode rejection, the VIN and VREF inputs each have their own
ground. VREF is referred to the local analog system ground
(AGND), and VIN is referred to the analog ground sense pin
(AGND SENSE) which allows a remote ground sense for the
input signal. If AGND SENSE is not used, it should be connected to the AGND pin at the package. The AGND SENSE
pin is intended to be tied to potentials within 100 mV of AGND
to maintain specified performance.
The AD1876 analog inputs (V IN , VREF and AGND SENSE)
exhibit dynamic characteristics. When a conversion cycle begins,
each analog input is connected to an internal, discharged 50 pF
capacitor which then charges to the voltage present at the corresponding pin. The capacitor is disconnected when SAMPLE is

REV. A

AD1876
taken LOW and the stored charge is used in the subsequent

. AID conversion. In order to limit the demands placed on the
external source by this high initial charging current, an internal
buffer amplifier is employed between the input and this capacitance for a few hundred nanoseconds. During this time the
input pin exhibits typically 20 kO input resistance, 10 pF input capacitance and ±40 !LA bias current. Next, the input is
switched directly to the now precharged capacitor and allowed
to fully settle, after which SAMPLE is taken LOW. During this
time the input sees only a 50 pF capacitor. Once the sample is
taken, the input is internally floated so that the external input
source sees a very high input resistance and a parasitic input
capacitance of typically only 2 pF. As a result, the only dominant input characteristic which must be considered is the high
current steps which occur when the internal buffers are switched
in and out.
In most cases, it is desirable to use external op amps to drive
the AD1876. For ac applications where low cost and low distortion are desired, the AD711 may be used as shown in Figure 7.
Another option is the 5532/5534 series. Care should always be
taken with op amp selection-many available op amps do not
meet the necessary low distortion requirements with even moderate loading conditions.

The test procedure consists of the following steps. First, the
device is calibrated by its on-board controller. Next, the'device
under test digitizes the input waveform. This conversion is performed at a 96 kSPS rate and transmits the resulting serial data
to the tester. The tester performs an FFT on the test data and
determines the actual performance of the device.
AC PERFORMANCE
Using the aforementioned test methodology, ac performance
of the ADI876 is measured. AC parameters, which include
S/(N + D), THD, etc., reflect the AD1876's effect on the spectral content of the analog input signal. Figures II through 15
provide information on the AD 1876's ac performance under a
variety of conditions.
As a general rule, averaging the results from several conversions
reduces the effects of noise and, therefore, improves such parameters as S/(N+D) and THD. ADI876 performance is optimized by operating the device at its maximum sample rate of
100 kSPS and digitally filtering the resulting bit stream to the
desired signal bandwidth. This succeeds in distributing noise
over a wider frequency range, thus reducing the noise density in
the frequency band of interest. This subject is discussed in the
following section.
OVERSAMPLING AND NOISE FILTERING
The Nyquist rate for a converter is defined as one-half its sampling rate. This is established by the Nyquist theorem, which
requires that a signal be sampled at a rate corresponding to at
least twice its widest bandwidth of interest in order to preserve
the information content. Oversampling is a conversion technique
in which the sampling frequency is an integral (2 or more) multiple of twice the frequency bandwidth of interest. In auclio applications, the ADl876 can operate at a 2x oversampling rate.
In quantized systems, the information content of the analog input is represented in the frequency spectrum from dc to the
Nyquist rate of the converter. Within this same spectrum are
higher frequency aliased noise components. Antialias, or lowpass, filters are used at the input to the ADC to remove the portion of these noise components attributed to high frequency
analog input noise. However, wideband noise contributed by the
ADI876 will not be reduced by the antiaIias filter. The ADI876
contributed noise is evenly distributed from dc to the Nyquist
rate, and this fact can be used to minimize its overall effect.

Figure 7.

TESTING THE ADl876
Analog Devices employs a high performance mixed signal VLSI
tester to verify the electrical performance of every AD1876. The
test system consists of two main sections, an input signal generator and a digital data and control section.
The stimulus section is responsible for providing a high purity,
noise-free, band limited tone to the input of the device. This
input frequency is 1.06 kHz. The test tone is passed through a
bandpass filter to remove distortion products and then buffered
by a high performance op amp. An external 5.000 V reference
voltage is also supplied by this section.
The control section of the test equipment provides an external
clock and the control signals for calibration, conversion and data
transmission. This section of the tester also contains the processing unit that calculates the actual performance of the device under test.

REV. A

The ADl876 contributed noise effects can be reduced by oversampling-sampling at a rate higher than defined by the
Nyquist theorem. This spreads the noise energy over a clistribution of frequencies wider than the frequency band of interest,
and by judicious selection of a digital filter, noise frequencies
outside the bandwidth of interest may be eliminated. The process of quantization inherently produces noise, known as quantization noise. The magnitude of this noise is a function of the
resolution of the converter, and manifests itself as a limit to the
theoretical signal-to-noise ratio achievable. This limit is described by S/(N+D) = (6.02 n + 1.76 + 10 log Fs/2 Fa) dB,
where n is the resolution of the converter in bits, Fs is the sampling frequency, and Fa is the signal bandwidth of interest. For
auclio bandwidth applications, the ADl876 is capable of operating at a 2 x oversample rate (96 kSPS), which typically produces
an improvement in S/(N + D) of 3 dB compared with operating
at the Nyquist conversion rate of 48 kSPS. Oversampling has
another advantage as well; the demands on the antialias filter are

AUDIO AID CONVERTERS 3--11

II

AD1876
lessened. In summary, system performance is optimized by run·
ning the ADI876 at or near its maximum sampling rate of 100
kHz and digitally filtering the resulting spectrum to eliminate
undesired frequencies.
DSP INTERFACE
Figure 8 illustrates the use of the Analog Devices ADSp-2101
digital signal processor with the ADl876. The ADSP-2101 FO
(flag out) pin of serial port I (SPORT 1) is connected to the
SAMPLE line and is used to control acquisition of data. The
ADSp-2101 timer is used to provide precise timing of the FO
pin.

SAMPLE

FO

SERIAL
PORT"

elK

{~

DOUT

DRO
RFSO
DTO
TFSO

SIGNAL PROCESSING

An audio spectrum analyzer can be produced by combining an
ADl876 and an ADSp-2101 signal processing microcomputer.
This system can analyze signals from dc to 50 kHz depending
on the sample rate. This is ideal for applications such as audio
analysis, but could also be applied to vibration analysis as well.
AUDIO DELAY LINE
A high performance, l6-bit stereo delay line can be constructed
from two ADI876 audio ADCs, a signal processing microcom·
puter and two ADl856 audio DACs. Depending on the length
of the internal buffer which produces the delay, a variable delay
is possible. Other applications are also possible with only a
change in software. For example, a reverb or echo effect could
be generated as well.

AD1876

ADSP-2101

can be programmed to generate an interrupt after the last data
bit is received. To maximize the conversion rate, SAMPLE
should be brought HIGH immediately after the last data bit is
received.

BUSY

Figure 8. ADSP-2101 Interface

The SCLK pin of the ADSP-2101 SPORTO provides the CLK
input for the AD1876. The clock should be programmed to be
approximately 2 MHz to comply with AD1876 specifications.
To minimize digital feedthrough, the clock should be disabled
(by setting Bit 14 in SPORTO control register to 0) during data
acquisition. Since .the clock floats when disabled, a pulldown
resistor of 12 k-15 k!l should be connected to SCLK to ensure
it will be LOW at the falling edge of SAMPLE. To maximize
the conversion rate, the serial clock should be eriabled immedi·
ately after SAMPLE is brought LOW (hold mode).
The ADI876 BUSY signal is connected to RFO to notify
SPORTO when a new data word is coming. SPORTO should be
configured in normal, external, noninverting framing mode and

ADl876 AND SM5805 DIGITAL FILTER @ 2 Fs
A simple method for generating the required signals for the
AD1876 is to connect one or more ADl876s to an NPC SM5805
digital filter. This device supplies all signals required to operate
the ADl876 at a 96 kHz sample rate, which is 2 x Fs for audio
applications.
To minimize group delay distortion, the input to the ADI876 is
filtered only by a low order analog filter. The ADl876 samples
the output of the filter at 2 Fs (96 kHz). To prevent aliasing,
the SM5805 filters the data with a sharp, linear phase filter roll·
ing off at 0.5 Fs. The resulting data is decimated to a sample
rate of 48 kSPS.
Interfacing the two chips is straight forward, as shown in Figure
9. The start signal for the ADl876 (for 96 kSPS operation) is
provided by the S/H pin of the SM5805, and CLK is derived
from the BCC pin. Figure 10 illustrates the corresponding tim·
ing diagram.

LEFT
CHANNEL

INPUT

DECIMATED

DATA. LEFT
DECIMATED

DATA. RIGHT
RIGHT
CHANNEL
INPUT
TO +5V

Figure 9. AD 1876 and SM5805 Digital Filter

I"

o~p~-'~----

~

In. (f. = 48kHz)

1

______________________________~r----1~__________________________________~
.

1

SBC
OUTPUT

DINR-;.......;.MS:;S;,."..v-::3"\r.4~.~::"'.v-::7v:8v:.:v.~;:V,::-,v.;I.~13:v.,";'.V,::'v:-::LS::;S-----VMS::;'Sr:'~3~";'4V-::5v::m~·;:V8-::V":"8v.;'.~I:"\1r.,::.V':;3v.;"~15:V-LS=B:---r---Figure 10. SM5805 Timing Diagram
3-12 AUDIO AID CONVERTERS

REV. A

Typical Dynamic Perfonnance -AD1876
90
......

80
70

lDao -

...
I

r---

,

C

~40

......

)~

iJj'
30

10

~V

,0

...... ~

VREF = 10V

50

20

~

~~
L

~

~ r\
~

...
ID

90

~~II~~ui

80

I II

70

~50

\·V REF =7V

40

V

30
20

-lIO -70
-60 -60 -40
-30 -20 -10
0
INPUT AMPLITUDE, REFERRED TO FULL-SCALE - dB

-60dB INPUT

I J1

o

100

lk

10k

lOOk

1M

Figure 12. SI(N+D) vs. Input Frequency and Amplitude

OdB

OdB
ID

-30dB

ID

-30dB

'"

-6OdB

'Y

-7OdB

g

-&OdB

::I

....
Q.

-9OdB

!::

r

INPUT FREQUENCY - Hz

Figure 11. SI(N+D) VS. VREF vs. Input Amplitude

Q

iY

S60
+

VREF = 5V

o

'Y

i\

12~~!~pJT

r

!:i

-70dB
-90dB

~

:E -11OdB
C

-llOdB
C -l3OdB

-l3OdB
-l50dB

-15OdB
0
FREQUENCY - Hz

FREQUENCY - Hz

Figure 13. 4096 Point FFT at 96 kSPS, f,N = 1.06 kHz

Figure 14. IMD Plot for f'N = 1008 Hz (f.), 1055 Hz (fb ) at
96kSPS

+5V

90

~7

80

.12V

70
-12V

ID

'Y

60

C

•

Z 50

iJj'

40
30
20

o

100

lk

10k

lOOk

1M

RIPPLE FREQUENCY - Hz

Figure 15. Power Supply Rejection (f,N = 1.06 kHz,
fSAMPLE = 96 kSPS, VRIPPLE = 0.3 V p-p)

REV. A

AUDIO AID CONVERTERS 3-13

II

3-14 AUDIO AID CONVERTERS

r.ANALOG
WDEVICES
FEATURES
Dual Channel
98 dB Signal-to-Noise Ratio
98 dB THD+N
0.0004 dB Passband Ripple
115 dB Stopband Attenuation
64x Oversampling
Unear Phase

High Performance Stereo
16-Bit Oversampled ADC
AD1878 I
FUNCTlONAL BLOCK DIAGRAM
WCK

DATA
CLOCK

51

APPLICATIONS
DAT and DCC Tape Players
Direct-to-Disc Recorders
Digital Audio Editors
Digital Mixing Consoles

RESET

DGND

DVDD

PRODUCT DESCRIPTION
The AD1878 is a two-channel, 16-bit oversampled digital audio
ADC. Each channel incorporates a high performance one-bit
noise shaping modulator and a digital decimating filter. An onboard voltage reference is also included. ADC output data is
transmitted from a flexible serial data port. The circuitry of the
AD1878 is segmented between two monolithic chips.

AVSs1
AVDD2

AV OD1
NC

The .voltage reference and one-bit modulators are fabricated
BiCMOS chip. The reference circuitry provides a reft
age that is stable over temperature and time. Us·
master clock, the one'bit modulators 0
sampling ratio. This oversampling ratio
ters to be simple resistor-capacitor combi
ns
linear phase throughout the passband. The mod
order and employ differential switched capacitor fil
to provide the required noise shaping characteristics and extremely
low distortion.
The digital decimating filters and serial port are fabricated using
a CMOS process. Using a proprietary technique, these singlestage digital filters provide a narrow transition band, deep stopband attenuation and low passband ripple.
The output port provides a single, serial bit stream which can
operate in several MASTER or SLAVE modes. It is controlled
by a clock and mode select pins. The format of the data is twos
complement, MSB first. The output signals are TTL and 5 volt
CMOS compatible. Output words may be transmitted in a rightjustified, I2 S or user-defmed format.

VINL-

VINL+
REFL

The AD1878 operates with ±5 volt power supplies. Separate
digital and analog power supplies and ground connections are
provided for reduced digital crosstalk. The AD1878 is guaranteed to operate over a temperature range of - 25°C to +70°C
and is packaged in a 28-pin plastic DIP.

PRODUCT HIGHLIGHTS
1. 64 x F s sampling rate.

2. From 2.5 kHz to 50 kHz output word rates.
3. Passband ripple is less than 0.001 dB.
4. Stopband attenuation is 115 dB.
5. Excellent low level signal performance is achieved.
6. No sample-and-hold circuits are required.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

REV. 0

AUDIO AID CONVERTERS ~15

•

AD1878 -SPECIFICATIONS

@ ± 5 volt Supplies. TA

= +25°C. Clock = lU88 MHz

PBrameter

Target

Units

RESOLUTION

18

Bits

OVERSAMPLING RATIO

64

DYNAMIC RANGE, 0 kHz to 20 kHz, No A-Weight Filter
Stereo Model
Mono Model

98
101

dB
dB

98

dB
dB
dB

SIGNAL TO (NOISE + DISTORTION)
o dB, 1 kHz
-20 dB, 1 kHz
-60 dB, 1 kHz

85
45

ANALOG INPUTS
Input Range
Input Impedance

V.
kG

REFERENCE OUTPUT
Output Voltage
Output Impedance

V

DC ACCURACY
Gain Matching
Gain Error
Gain Drift
Midscale Error
Midscale Drift

dB

%
ppml"C
LSBs
ppml"C

0
't

PHASE DEVIATION (Interchannel)

Degrees

CROSSTALK
20 kHz, EIAJ Method

dB

DIGITAL FILTER CHARACTERISTICS
Passband Ripple
Stopband Attenuation
12.288 MHz Master Clock'
Passband Edge
Stopband Edge
11.2896 MHz ClockS
Passband Edge
Stopband Edge
DIGITAL INPUTS AND OUTPUTS
V'H

,L

V
IIH @: V1H

=5V

I'L @: V'L = 0 V
VOH @: IOH = 4 mA
VOL @: IOL = 4 mA
NOMINAL MASTER CLOCK FREQUENCY
POWER SUPPLIES
Voltage, +VL and +Vs
Voltage, -VL and -Vs
Current, +IL and +Is
Current, - IL and - Is

0.001

115
21.7

dB
dB

26.2

kHz
kHz

20
24.1

kHz
kHz

2.0
0.8
10
10

4.5

0.5
12.288

MHz

5

V
V
mA
mA

-5
TBD
TBD

POWER DISSIPATION
Operation
Power Down APD = "I"

900

400

mW
mW

POWER SUPPLY REJECTION RATIO

67

dB

TEMPERATURE RANGE
Specification
Operation
Storage

25
-25 to +70

·C
·C
"C

NOTES
'Stereo Mode uses output of each channel independently.
2Mono Mode sums output words to derive higher Dynamic Range.

'l6-bit LSBs.

-60 to +100
4Master Clock Frequenty for 48 kHz sample rate.
'Master Clock Frequenty for 44.1 kHz sample rate.
Specifications subject to change without notice.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

. 3-16 AUDIO IVD CONVERTERS

REV. 0

11IIIIIIII ANALOG
WDEVICES
FEATURES
Dual Channel
103 dB Signal-to:Noise Ratio
98dBTHD+N
0.0004 dB Passband Ripple
115 dB Stopband Attenuation
64x Oversampling
Linear Phase

High Performance Stereo
l8-Bit Oversampled ADC
AD1879 I
FUNCTIONAL BLOCK DIAGRAM
WCK
DATA
CLOCK
SI

APPUCATIONS
Pro Audio Digital Tape Recorders
Direct-to-Disc Recorders
Digital Audio Editors
Digital Mixing Consoles

RESET
DGND

DYOD

PRODUCT DESCRIPTION
The AD1879 is a two-channel, l8-bit oversampled digital audio
ADC. Each channel incorporates a high performance one-bit
noise shaping modulator and a digital decimating fllter. An onboard voltage reference is also included. ADC output data is
transmitted from a flexible serial data port. The circuitry of the
AD1879 is segmented between two monolithic chips.
The voltage reference and one-bit modulators are fabricpted
BiCMOS chip. The reference circuitry provides a refer
age that is stable over temperature and time. Us·
master clock, the one-bit modulators 0
sampling ratio. This oversampling ratio
fllters to be simple resistor-capacitor co
linear phase throughout the passband. The m
to proorder and employ differential switched capacitor fll
vide the required noise shaping characteristics and extremely
low distortion.
The digital decimating fllters and seria1 port are fabricated using
a CMOS process. Using a proprietary technique, these singlestage digital fllters provide a narrow transition band, deep stopband attenuation and low passband ripple.
The output port provides a single, serial bit stream which can
operate in several MASTER or SLAVE modes. It is controlled
by clock and mode select pins. The format of the data is twos
complement, MSB fIrst. The output signals are TTL and 5 volt
CMOS compatible. Output words may be transmitted in a rightjustifIed, 12S or user-defmed format.

AVssl
AVoo2

AV DD1
NC
VINL-

VlNL+

REFL

PRODUCT HIGHLIGHTS
1. 64 x F s sampling rate.
2. Passband ripple

i~

less than 0.001 dB.

3. Stopband attenuation is 115 dB.
4. Excellent low level signal performance is achieved.
S. No sample-and-hold circuits are required.
6. Fully differential analog inputs.
7. Extremely flexible serial data output port.

The AD1879 operates with ±5 volt power supplies. Separate
digital and analog power supplies and ground connections are
provided for reduced digital crosstalk. The AD1879 is guaranteed to operate over a temperature range of -25°C to +70°C
and is packaged in a 28-pin plastic DIP.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
REV. 0

AUDIO AID CONVERTERS ~ 17

•

AD1879 -SPECIFICATIONS

@ ±5 VSupplies, T,

= 25°C, Clock = 12.288 MHz

Parameter

Target

Vilits

RESOLUTION

18

Bits

OVERSAMPLING RATIO

64

DYNAMIC RANGE, 0 kHz to 20 kHz, No A-Weight Filter
Stereo Mode'
Mono Mode'

106

dB
dB,

SIGNAL TO (NOISE + DISTORTION)
odB, 1 kHz
-20 dB, 1 kHz
-60 dB, 1 kHz

98
85
45

dB
dB
dB

103

ANALOG INPUTS
Input Range
Input Impedance

v

REFERENCE OUTPUT
Output Voltage
Output Impedance

V

kO

DC ACCURACY
Gain Matching
Gain Error
Gain Drift
Midscale Error
Midscale Drift

dB
%
ppmI"C
LSBs
ppmI"C

PHASE DEVIATION (Interchannel)

Degrees

CROSSTALK
20 kHz, EIAJ Method

dB

DIGITAL FILTER CHARACTERISTICS
Passband Ripple
Stopband Attenuation
12.288 MHz Master Clock'
Passband Edge
Stopband Edge
11.2896 MHz Clock'
Passband Edge
Stopband Edge

lI5

dB
dB

21.7
26.2

kHz
kHz

20
24.1

kHz
kHz

0.001

DIGITAL INPUTS AND OUTPUTS
V IH
V IL
I'H@VIH = 5 V
IIL@VIL = OV
VOH @ IOH = 4mA
VOL@IOL=4mA

2.0
0.8
10
10
4.5
0.5

NOMINAL MASTER CLOCK FREQUENCY

12.288

MHz

5
-5

V

V

IlA
IlA
V
V

POWER SUPPLIES
Voltage, +VL and +Vs
Voltage, -VL and -Vs
Current, + IL and + Is
Current, -IL and -Is

TBD
TBD

V
V
mA
mA

POWER DISSIPATION
Operation
Power Down APD = "1"

900
400

mW
mW

POWER SUPPLY REJECTION RATIO

67

dB

TEMPERATURE RANGE
Specification
25
"C
Operation
- 25 to + 70
"C
Srorage~________________________________________~_________-_60
__t_o_+_1_00________________- L_________o_C____

NOTES
IStereo mode uses output of each channel independently.
2Mono mode sums output words to derive higher dynamic range.
'l6-bit LSBs.

'Master Clock Frequency for 48 kHz sample rate.
SMaster Clock Frequency for 44.1 kHz' sample rate.
Specifications subject to change without notice.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

3-18 AUDIO AID CONVERTERS

REV. 0

Low-Cost Stereo
16-Bit Oversampled ADC
AD1885 I

r.ANALOG
WDEVICES
FEATURES
Dual Channel
85 dB Signal-to-Noise Ratio
85 dB THD+N
±0.01 dB Passband Ripple
80 dB Stopband Attenuation
64 Times Oversampling
Linear Phase

FUNCTIONAL BLOCK DIAGRAM
WCK
SERIAL OUTPUT INTERFACE

DATA
CLOCK

81
RESET

APPLICATIONS
RDAT Machines
High Performance Sampling Kevboards
Multimedia Workstations

DGND
DVDD

PRODUCT DESCRIPTION

AVDD2

The AD1885 is a two-channel, 16-bit oversam
ADC. Each channel incorporates a high perfo
e on
noise-shaping modulator and a digital decimating filte .
board voltage reference is also included. ADC output dat is
transmitted from a flexible serial data port. The circuitry of the
AD1885 is segmented between two monolithic chips.
The reference circuitry provides a reference voltage that is stable
over temperature and time. Using an external master clock, the
one-bit modulator operates at 64 x Fs oversampling rate. This
oversampling rate permits the antialias filters to be simple
resistor-capacitor combinations and results in linear phase
throughout the passband. The third-order modulators employ
differential switched capacitor filters to provide the required
noise-shaping characteristics and extremely low distortion.
The digital decimating filters and serial port are fabricated using
a CMOS process. Using a proprietary technique, these singlestage digital filters provide a narrow transition band, deep stopband attentuation and low passband ripple.
The output port provides right and left channel.data in a single,
serial bit stream controlled by user-supplied BCK, LRCK and
WCK signals. The twos complement, MSB first data can be
transmitted in a right-justified, left-justified or user-defined
format.

AVDDl

NC = NO CONNECT

The AD 1885 operates with ± 5 V power supplies. Separate digital and analog ground connections are provided for reduced digital crosstalk. The AD 1885 is guaranteed to operate over a
temperature range of -25·C to +70·C. The AD1885 is packaged in a 28-pin plastic SOIC.

PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
8.

64 x F s sampling rate.
44.1, 48 and 32 kHz output word rates.
Passband ripple is less than ±0.01 dB.
Stopband attenuation is 80 dB.
Excellent low-level performance.
No sample-and-hold circuits are required.
Analog inputs are fully differential.
Serial data output port.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

REV. 0

AUDIO AID CONVERTERS 3-19

II

AD1885 - SPECIFICATIONS

(@ ±5 VSupplies, TA

= +25°C, Clock = 18 x 432 MHz (= 384 x48 kHz»
Target

Parameter
RESOLUTION

16
64

Unit
Bits

OVERSAMPLING RATIO
DYNAMIC RANGE, 0 to 20 kHz, NO A-WEIGHT FILTER
Stereo Model

85

dB

THD+N (SIGNAL TO (NOISE + DISTORTION))
o dB, 1 kHz
-20 dB, 1 kHz
-60 dB, 1 kHz

85
TBD
TBD

dB
dB
dB

ANALOG INPUTS
Input Range
Input Impedance

±3
30

kO

REFERENCE OUTPUT
Output Voltage
Output Impedance

V

DC ACCURACY
Gain Matching
Gain Error
Gain Drift
Midscale Error
Midscale Drift
PHASE DEVIATION (INTERCHANNEL)

dB
%
ppmf'C
LSBs2
ppmf'C
Degrees

CROSSTALK
20 kHz, EIAJ Method
DIGITAL FILTER CHARACTERISTICS
Passband Ripple
Stopband Attenuation
18.432 MHz Master Clock3 (= 384 x 48 kHz)
Passband Edge
Stopband Edge
16.9344 MHz Master Clock4 (= 384 x 44.1 kHz)
Passband Edge
Stopband Edge

dB

DIGITAL INPUT AND OUTPUTS
V,H

±0.01
80

dB
dB

21.6
26.4

kHz
kHz

19.8
24.3

kHz
kHz

2.0
0.8
10
10
4.5

V,L

IIH @VIH = 5 V
I'L@V'L = 0 V
VOH @ IOH = 4 rnA
VOL @ IOL = 4 rnA
MASTER CLOCK FREQUENCY
POWER SUPPLIES
Voltage, AVDDI and AVDD2
Voltage, AVSSI and AVSS2
Current, + IL and Is
Current, - IL and - Is
POWER DISSIPATION
Operation
Power Down APD = "1"

0.5
18.432

MHz

5

V
V
rnA
rnA

-5
TBD
TBD

500
50

mW
mW
dB

+25
-25 to +70
-60 to +100

·C
·C
·C

375

POWER SUPPLY REJECTION RATIO (IN BAND)
TEMPERATURE RANGE
Specification
Operation
Storage
NOTES
lStereo mode uses output of each channel.
'16-bit LSBs.

v

'Master Clock Frequency for 48 kHz sample rate.
Master Clock Frequency for 44.1 kHz sample rate.
Specifications subject to change without notice.

4

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future- manufacture unless otherwise agreed to in writing.

3--20 AUDIO AID CONVERTERS

REV. 0

Video AID Converters
Contents
Page

Video AID Converters - Section 4 .............................................. 4-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
AD773 - lO-Bit 18 MSPS Monolithic AID Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
AD9020 - 10-Bit 60 MSPS AID Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
AD9048 - Monolithic 8-Bit Video AID Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
AD9060 - lO-Bit 7S MSPS AID Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39

a

VIDEO AID CONVERTERS 4-1

t Selection Guide
s
~ Video Analog-to-Digital Converters

0

~

8:c:
~

~

Model

Res
Bits

Sample
Rate
(MSPS)

Input
Bandwidth
MHz, -3 dB

Power
Dissipation
W

AD9048

8

35

15

0.55

AD773
AD9020

10
10

18
60

100
175

1.3
2.8

AD9060

10

75

175

2.8

i;:!

ill

Page
4-31
4-31
4-31
4-31
4-3
4-19
4-19
4-39
4-39

Comments

On-Board Track and Hold, Evaluation PCB
Evaluation PCB
Evaluation PCB

11IIIIIIII

ANALOG

WDEVICES
FEATURES
Monolithic 10-Bit 18 MSPS AID Converter
Low Power Dissipation: 1.2 W
Signal-to-Noise Plus Distortion Ratio
f'N
1 MHz: 55 dB
f'N = 8 MHz: 52 dB
Guaranteed No Missing Codes
On-Chip Track-and-Hold Amplifier
100 MHz Full Power Bandwidth
High Impedance Reference Input
Out of Range Output
Twos Complement and Binary Output Data
Available in Commercial and Military Temperature
Ranges

10-Bit 18 MSPS
Monolithic AID Converter
AD773 I
FUNCTIONAL BLOCK DIAGRAM

=

a
OTR MSB BIT 1 BIT 10
(MSB) (l.SB)

PRODUCT DESCRIPTION
The AD773 is a monolithic lO-bit, 18 MSPS analog-to-digital
converter incorporating an on-board, high performance trackand-hold amplifier (THA). The AD773 converts video bandwidth signals without the use of an external THA. The AD773
implements a multistage differential pipelined architecture with
output error correction logic. The AD773 offers accurate performance and guarantees no missing codes over the full operating
temperature range.
Output data is presented in binary and twos complement format. An out of range (OTR) signal indicates the analog input
voltage is beyond the specified input range. OTR can be
decoded with the MSB/MSB pins to signal an underflow or
overflow condition. The high impedance reference input allows
multiple AD773s to be driven in parallel from a single reference.
The combined dc precision and dynamic performance of the
AD773 is useful in a variety of applications. Typical applications
include: video enhancement, HDTV, ghost cancellation, ultrasound imaging, radar and high speed data acquisition.

PRODUCT HIGHLIGHTS
I. On-board THA
The high impedance differential input THA eliminates the
need for external buffering or sample and hold amplifiers.
The THA offers the choice of differential or single-ended
inputs. Input current is typically 5 fJ.A.
2. High Impedance Reference Input
The high impedance reference input (200 kO) allows direct
connection with standard + 2.5 V references, such as the
AD680, ADS80 and REF43.
3. Output Data Flexibility
Output data is available in bipolar offset and bipolar twos
complement binary format.
4. Out of Range (OTR)
The OTR output bit indicates when the input signal is beyond the AD773's input range.

The AD773 was designed using Analog Devices' ABCMOS-l
process which utilizes high speed bipolar and 2-micron CMOS
transistors on a single chip. High speed, precision analog circuits are now combined with high density logic circuits. Laser
trimmed thin film resistors are used to optimize accuracy and
temperature stability.
The AD773 is packaged in a 28-pin ceramic DIP and is available in commercial (O°C to + 70°C) and military (-55°C to
+ 125°C) grades.

REV. 0

VIDEO AID CONVERTERS 4-3

AD773 - SPECIFICATIONS
AVDD = +5 V ± 5%, AVss = -5 V ± 5%, DVDD = +5 V ±5%,
DC SPECIFIC".'JIONS DRVDDto=TMAl(+5with
V ± 5%, V = +2.500 V unless otherwise indicated)
(TMIN

REF

AD773)

Parameter

Min

RESOLUTION

10

DC ACCURACY (+ 25°C)
Integral Nonlinearity
TMINto TMAX
Differential Linearity Error
TMIN to T MAX
Offset
Gain Error
No Missing Codes

LOGIC INPUT
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = DVoo)
Low Level Input Current (VIN = 0 V)
Input Capacitance
LOGIC OUTPUTS
High Level Output Voltage (loH = 0.5 rnA)
Low Level Output Voltage (IoL = 1.6 rnA)
POWER SUPPLIES
Operating Voltages
AVoo
AVss
DVoo,DRV oo
Operating Current
IAVoo
IAVss
IDVoo
IDRVoo 1

AD773K
Max

Min

Max

1
5

±2

±0.75
±1
0.5
3.5
0.5
2.0
GUARANTEED
1
5

20
10

200
2.5

50

+3.5

20
10

-10
-10

+1.0
+10
+10

-10
-10

10

10

+2.4

+2.4

+5.25
-4.75
+5.25

Vp-p
j.LA
pF

V
V
j.LA
j.LA
pF

+0.4

V
V

+5.25
-4.75
+5.25

Volts
Volts
Volts

85
-140
15
10

100
-185
20
15

rnA
rnA
rnA
rnA

+0.4

+4.75
-5.25
+4.75

LSB
LSB
LSB
LSB
%FSR
%FSR

k!l
Volts

200
2.5

+3.5
+1.0
+10
+10

Units
Bits

±0.75

±1
0.5
0.5

50

Typ

10

±1

ANALOG INPUT
Input Range
Input Current
Input Capacitance
REFERENCE INPUT
Reference Input Resistance
Reference Input

Typ

+4.75
-5.25
+4.75

85
-140
15
10

100
-185
20
15

POWER CONSUMPTION2

1.2

1.5

1.2

1.5

W

POWER SUPPLY REJECTION

6

16

6

16

mVN

+70

°C

TEMPERATURE RANGE
Specified (J/K)

0

+70

0

NOTES
IC L = 15 pF typical.
'100% production t..ted.
Specifications subject to change without nOlice. See Definition of Specifications for additional information.

4-4 VIDEO AID CONVERTERS

REV. 0

AD773
to TMAl( with AVDD = +5 V ± 5%, AVss = -5 V ± 5%, DVDD = +5 V ± 5%, DRVDD = +5 V
AC SPEC IFI CAT10NS(TMIN
± 5%, V = +2.500 V unless otherwise indicated, fSAMPLE = 18 MSPS, fiN amplitude = -0.3 dB)
REF

AD773)
Parameter
DYNAMIC PERFORMANCE I
Signal-to-Noise plus Distortion
(SIN+D) Ratio
fiN = I MHz
fIN = 8.1 MHz
fIN = 9 MHz
Effective Number of Bits (ENOB)
fIN = I MHz
fIN = 8.1 MHz
fIN = 9 MHz
Total Harmonic Distortion (THD)
fIN = I MHz
fIN = 8.1 MHz
fIN = 9 MHz
Spurious Free Dynamic Range2
Full Power Bandwidth
Interrnodulation Distortion (IMD)3
Second Order Products
Third Order Products
Differential Phase
Differential Gain
Transient Response
Overvoltage Recovery Time

Min

Typ

52
45

56
53
53

AD773K

Max

Min

Typ

54
47

56
53
53

dB
dB
dB

9.0
8.5
8.5

Bits
Bits
Bits

9.0
8.5
8.5

-64
-55
-56
-67
100

-57

-64
-55
-56
-67
100

-46

-69
-63
0.2
0.8
25
25

-69
-63
0.2
0.8
25
25

Max

-59
-48

Units

dB
dB
dB
dB
MHz
dB
dB
Degree

%
ns
ns

NOTES
IFor typical dynamic performance curves at fSAMPLE = 16.2 MSPS and 18 MSPS, see Figures 2 through 13.
'fiN = I MHz.
'fa = 1.0 MHz, fb = 1.05 MHz.
Specifications subject to change without notice.

(for all grades TMIN to TMAl( with AVDD = +5 V ± 5%, A~ss ~ .-5 V ± 5%, DVDD = +5 V ± 5%,
TIMING SPECIFICATIONS
II
DRVDD = +5 V ± 5%, VREF = +2.500 V unless otherwise mdlcated, fSAMPLE = 18 MSPS)
Symbol
Conversion Rate
Clock Period
Clock High
Clock Low
Output Delay
Aperture Delay
Aperture Jitter
Pipeline Delay (Latency)

Typ

Min

Max

Units

18

MSPS
ns
ns
ns
ns
ns
ps
Clock Cycles

55
27
27

teLK

teH
teL
toD

20
7
9

32
4

N
N+1

VIN

CLOCK

ItCH

BIT 1-10
MSB.OrR

==x

::;j

I

tCL

X

X

X

~tOD

X

DATA
N

~
N+1

Figure 1. AD773 Timing Diagram

REV. 0

VIDEO AID CONVERTERS 4-5

II

AD773
CAUTION _________________________________________________
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted.

WARNING!

d

~~EDEVICE

ABSOLUTE MAXIMUM RATINGS*
Parameter

With Respect to

Min

Max

Units

AVoo
AVss
DVoo , DRVoo
AGND
AV oo , AVss
CLK
REFIN
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)

AGND
AGND
DGND,DRGND
DGND,DRGND
DVoo , DRVoo
DVoo , DRVoo
REFGND, AGND

-0.5
-6.5
-0.5
-1.0
-6.5
-6.5
-0.5

+6.5
+0.5
+6.5
+1.0
+0.5
+0.5
+6.5
+150
+150

V
V
V
V
V
V
V
°C
°C

-65

+300 °C

*Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect device reliability.

PIN CONFIGURATION
AGND
V INB
V 1NA

AVss

AD773
TOP VIEW
(Not to Scale)

DV OD
eLK

DRV OD
DAGND
OTA

ORDERING GUIDE

MSB

Model

Temperature
Range

Description

Package
Option*

AD773JD
AD773KD

O°C to +70°C
O°C to +70°C

28-Pin Ceramic DIP
28-Pin Ceramic DIP

D-28
D-28

*D

= Ceramic

BIT 1 (MSB)
BIT 2
BIT3

BIT 0

DIP. For outline information see Package Information section.

PIN DESCRIPTION
Symbol

Pin No.

Type

Name and Function

AGND
AVoo
AVss
BIT I (MSB)
BIT 2-BIT 9
BIT 10 (LSB)
CLK

5,28
4
3,25
18
17-10
9
23

P
P
P
DO
DO
DO
DI

DVoo
DRVoo
DGND
DRGND
MSB
OTR

24
7,22
8,21
19
20

P
P
P
P
DO
DO

I
2
26
27

AI
AI
AI
AI

Analog Ground.
+ 5 V Analog Supply.
-5 V Analog Supply.
Most Significant Bit.
Data Bit 2 through Data Bit 9.
Least Significant Bit.
Clock Input. The AD773 will initiate a conversion on the falling edge of the clock input. See the
Timing Diagram for details.
+5 V Digital Supply.
+ 5 V Digital Supply for the output drivers.
Digital Ground.
Digital Ground for the output drivers.
Inverted Most Significant Bit. Provides twos complement output data format.
Out of Range is Active HIGH on the leading edge of Code 0 or the trailing edge of Code 1023.
See Output Data Format Table II.
REF GND is connected to the ground of the external reference.
REF IN is the external 2.5 V reference input, taken with respect to REF GND.
( + ) Analog input signal to the differential input THA.
( - ) Analog input signal to the differential input THA.

REFGND
REF IN
V1NA
VINB

6

Type: AI = Analog Input; DI = Digital Input; DO = Digital Output; P = Power.

4-6 VIDEO AID CONVERTERS

REV. 0

Definitions of Specifications - AD773
INTEGRAL NONLINEARITY (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from "zero" through "full scale." The point
used as "zero" occurs 112 LSB before the first code transition.
"Full scale" is defined as a level I 112 LSB beyond the last code
transition. The deviation is measured from the center of each
particular code to the true straight line.
DIFFERENTIAL LINEARITY ERROR (DNL, NO
MISSING CODES)
An ideal ADC exhibits code transitions that are exactly I LSB
apart. DNL is the deviation from this ideal value.
OFFSET
The first transition should occur at a level 112 LSB above
"zero." Offset is defined as the deviation of the actual first code
transition from that point.
GAIN ERROR
The last code transition should occur for an analog value I 112
LSB below the nominal full scale. The gain error is the deviation of the actual level at the last transition from the ideal level.
POWER SUPPLY REJECTION
One of the effects of power supply variation on the performance
of the device will be a change in gain error. The specification
shows the maximum gain error deviation as the supplies are varied from their nominal values to their specified limits.
SIGNAL-TO-NOISE PLUS DISTORTION (SIN+D)
RATIO
SIN + D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components including
harmonics but excluding dc. The value for SIN+D is expressed
in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
ENOB is calculated from the following expression:
SIN+D = 6.02N + 1.76, where N is equal to the effective
number of bits.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com·
ponents to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
SPURIOUS FREE DYNAMIC RANGE
The peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. This
value is expressed in decibels relative to the rms value of a fullscale input signal.

REV. 0

INTERMODULATION DISTORTION (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m+n), at sum and difference frequencies of mfa±nfb,
where m, n = 0, 1,2,3 .... Intermodulation terms are those
for which m or n is not equal to zero. For example, the second
order terms are (fa+fb) and (fa-fb) and the third order terms
are (2fa+fb), (2fa-fb), (fa+2fb) and (fa-2fb). The IMD products are expressed as the decibel ratio of the rms sum of the
measured input signals to the rms sum of the distortion terms.
The two signals are of equal amplitude and the peak value of
their sums is -0.5 dB from full scale. The IMD products are
normalized to a 0 dB input signal.
DIFFERENTIAL GAIN
The percentage difference between the output amplitudes of a
small high frequency sine wave at two stated levels of a low frequency signal on which it is superimposed.
DIFFERENTIAL PHASE
The difference in the output phase of a small high frequency
sine wave at two stated levels of a low frequency signal on which
it is superimposed.
TRANSIENT RESPONSE
The time required for the AD773 to achieve its rated accuracy
after a full-scale step function is applied to its input.
OVERVOLTAGE RECOVERY TIME
The time required for the ADC to recover to full accuracy after
an analog input signal 150% of full scale is reduced to 50% of
the full-scale value.
APERTURE DELAY
The difference between the switch delay and the analog delay of
the THA. This effective delay represents the point in time, relative to the rising edge of the CLOCK input, that the analog input is sampled.
APERTURE JITTER
The variations in aperture delay for successive samples.
PIPELINE DELAY (LATENCY)
The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every clock cycle.
FULL POWER BANDWIDTH
The input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 dB for a full-scale input.

VIDEO AID CONVERTERS 4-7

a

AD773 - Dynamic Characteristics
o

60

F~N~~JEN~A~

-~r-50

...III

~~

-6dB

40

-20

~

I

~ 30

"

I\.

-o.3IIB

~

IL

--

THD

20

10

o

lOOk

1M

-100

100M

10M

lOOk

10-'"
2i

D

.,.

~

rii, i

1M

Nl

10M

rrrr
3RD

100M

FREQUENCY - Hz

FREQUENCY - Hz

Figure 2. SIN+D vs. Input Frequency, (eLK = 18 MSPS

Figure 5. Harmonic Distortion vs. Input Frequency,
feLK = 18 MSPS: Small Signal

o

Or-~r-~--~---r--'---~--~-'

-10r--ir---r---r-~r-~--~--~--~

-2O~-H---+--~--+-~~-+---r~

-20

...III

1/

...III -40
I

II:

~-60

~

.,.,... ~

V

I

I!I

~

~O~~~--~--r-~r-~--~--~--~

-40~~~--~--r-~r-~--~--~--~

~==

2

a:

...J

••
••
••
••
••
••
••
••
••
••
••
••
••••
••
• ••••••
••••

••
•
•••
••
••
••
•

•

Figure 29. Solder Side PCB Layout

REV. 0

VIDEO AID CONVERTERS 4-15

II

AD 773

•

c-

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4-16 VIDEO AID CONVERTERS

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Figure 31. Power Layer PCB Layout

REV. 0

AD773

a
Figure 32. Silkscreen Layer PCB Layout

REV. 0

VIDEO AID CONVERTERS 4-17

4-18 VIDEO AID CONVERTERS

10-Bit, 60 MSPS
AID Converter
AD9020 I

1IIIIIIII ANALOG

WDEVICES
FEATURES
Monolithic 10·Bit/60 MSPS Converter
TTL Outputs
Bipolar (:1.75 VI Analog Input
56 dB SNR @ 2.3 MHz Input
Low (45 pFllnput Capacitance
MIL·STD·883 Compliant Versions Available

FUNCTIONAL BLOCK DIAGRAM
. . . LSBS

INVPT INVI!AT

ANALOG IN

~:~----,

AD9020

APPLICATIONS
Digital Oscilloscopes
Medical Imaging
Professional Video
Radar Warning/Guidance Systems
Infrarad Systems

51 OVERFLOW

0. (M9a)

GENERAL DESCRIPTION
The AD9020 AID converter is a lO·bit monolithic converter capable of word rates of 60 MSPS and above. Innovative architec·
ture using 512 input comparators instead of the traditional 1024
required by other flash converters reduces input capacitance and
improves linearity.

Do
II,

Encode and outputs are TTL"compatible, making the AD9020 an
ideal candidate for use in low power systems. An overflow bit is
provided to indicate analog input signals greater than + VSENSE'
Voltage sense lines are provided to insure accurate driving of the
± VREF voltages applied to the units. Quarter-point taps on the
resistor ladder help optimize the integral linearity of the unit.
Either 68·pin ceramic leaded (gull wing) packages or ceramic
LCCs are available and are specifically designed for low thermal
impedances. Two performance grades for temperatures of both 0
to +70°C and -55°C to + 125°C ranges are offered to allow the
user to select the linearity best suited for each application. Dy·
namic performance is fully characterized and production tested
at + 25°C. MIL·STD·883 units are available.

-v,..
-,,",

The AD9020 AID Converter is available in versions compliant
with MIL·STD·883. Refer to the Analog Devices Military Products Databook or current AD9020/883B data sheet for detailed
specifications.

REV. A

VIDEO AID CONVERTERS 4-19

a

AD9020 -SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS·

3/4aEP' 1I2REP ' 1I4REP Current ..•...•• ,'... ' .... ±10 mA
Digital Output Current ... ,. . . . . . . . . . . . . . . . . . • 20 mA
Operating Temperature
AD9020JElKElJZlKZ . . . . . . . . . . . . . . . . . . 0 to +70"C
Storage Temperature . . . . . . . . . . . . . . . • -65"C to + 150"C
Maximum Junction Temperature2. • • • • • • • • • • • • • • + 175"C
Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . +300"C

+Vs . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . +6 V
-Vs . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . -6V
ANALOG IN . . . . . . . . . . . . . . . . . . . . . . . -2 V to +2 V
+VREP' -VREP' 3/4aEP' 1I2REP' 1I4REP . . . . . -2 V to +2 V
+VREP to -VREP . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
DIGITAL INPUTS . . . . . . . . . . . . . . . . . . -0.5 V to +Vs

ELECTRICAL CHARACTERISTICS (ds = ±5 v; ±V
Parameter (Conditions)

Temp

Test
Level

RESOLUTION
DC ACCURACy3
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
ANALOG INPUT
Input Bias Current·
Input Resistance
Input Capacitance·
Analog Bandwidth
REFERENCE INPUT
Reference Ladder Resistance
Ladder Tempco
Reference Ladder Offset
Top of Ladder
Bottom of Ladder
Offset Drift Coefficient
SWITCHING PERFORMANCE
Conversion Rate
Aperture Delay (tA )
Aperture Uncertainty (Jitter)
Output Delay (ton)'
Output Time Skew'
DYNAMIC PERFORMANCE
Transient Response
Overvoltage Recovery Time
Effective Number of Bits (ENOB)
fIN = 2.3 MHz
fIN = 10.3 MHz
fIN = 15.3 MHz
Signal-to-Noise Ratio'
fIN =2.3 MHz
fIN = 10.3 MHz
fIN = 15.3 MHz
Signal-to-Noise Ratio'
(Without Harmonics)
fIN = 2.3 MHz
fIN = 10.3 MHz
fIN = 15.3 MHz

4-20 VIDEO AID CONVERTERS

SEIISE

Min

= ±1.75 v; ENCODE = 40 MSPS unless otherwise notedj3
AD9020jElJZ
Typ
Max

10

Min

AD9020KFJKZ
Typ
Max

10

+25·C
Full
+ 25·C
Full
Full

I
VI
I
VI
VI

1.0

+25·C
Full
+25·C
+25·C
+25·C

I
VI
I
V
V

0.4

+25·C
Full
Full

I
VI
V

+25·C
Full
+25·C
Full
Full

I
VI
I
VI
V

+ 25°C
+25·C
+25·C
+ 25·C
+25·C

I
V
V
I
I

+25·C
+25·C

V
V

+25·C
+ 25·C
+ 25·C

I
IV
IV

8.6
8.0
7.5

9.0
8.4
8.0

+25·C
+25"C
+ 25·C

I
I
I

54
50
47

+25·C
+ 25·C
+25"C

I
I
I

54
51
48

l.25

1.25
1.5
2.0
2.5

Units
Bits

0.75
1.0

1.0
1.25
1.5
2.0

LSB
LSB
LSB
LSB

1.0
2.0

mA

Guaranteed

2.0

7.0
45
175

22
14

37

1.0
2.0

56
66

0.4
2.0

7.0
45
175

22
14

37

45
45

90
90
90
90

45

nt"C
90
90
90
90

50

I
5
10
3

MSPS
ns
PS. rms
ns
ns

60

60

I
5
10
3

13
5

6

n
n
mV
mV
mV
mV
V-VPC

45

50

6

56
66

0.1

0.1

mA
k!l
pF
MHz

13
5

10
10

ns
ns

8.6
8.0
7.5

9.0
8.4
8.0

Bits
Bits
Bits

56
53
50

54
50
47

56
53
50

dB
dB
dB

56
54
52

54
51
48

56
54
52

dB
dB
dB

10
10

REV. A

AD9020
Parameter (Conditions)
DYNAMIC PERFORMANCE
(CONTINUED)
Harmonic Distortion
fIN = 2.3 MHz
fIN = 10.3 MHz
fiN = 15.3 MHz
Two-Tone Intermodulation
Distortion Rejection7
Differential Phase
Differential Gain
ENCODE INPUT
Logic "1" Voltage
Logic "0" Voltage
Logic "1" Current
Logic "0" Current
Input Capacitance
Pulse Width (High)
Pulse Width (Low)
DIGITAL OUTPUTS
Logic "1" Voltage (loH = 2 rnA)
Logic "0" Voltage (loL = 10 rnA)
POWER SUPPLY
+ Vs Supply Current

Temp

Test
Level

Min

+25 DC
+ 25 DC
+25 DC

I
I
I

61
55
49

+ 25 DC
+25 DC
+25 DC

V
V
V

Full
Full
Full
Full

+ 25DC
+ 25 DC
+25 DC

VI
VI
VI
VI
V
I
I

Full
Full

VI
VI

+25"C

440

Full

I
VI
I
VI
I
VI

Full

VI

6

Full
- Vs Supply Current

+ 25DC
Full

Power Dissipation
Power Supply Rejection
Ratio (PSRR)8

+25"C

AD9020JElJZ
Typ
Max

67
59
53

AD9020KEIKZ
Min

Typ

61
55
49

67
59
53

dBc
dBc
dBc

70
0.5

dBc

I

%

70
0.5
1
2.0

Max

Degree

2.0
0.8
20
800

0.8
20
800

5

5

6
6

2.4

140
2.8

10

IIoA

V
V

0.4
530
542
170
177
3.3
3.4

V
V
/loA
pF
ns
ns

6
6

2.4

Units

440
140
2.8
6

rnA
rnA
rnA
rnA

530
542
170
177
3.3
3.4

W
W

10

rnVN

NOTES
I Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
'Typical thermal impedanct. (part soldered onto board): 6S·pin leaded ceramic chip carrier: 0JC = IOC/W; OJA = 170c/w (no air flow); OJA = ISoc/w
(air flow = 500 LFM). 68·pin ceramic LCC: 0JC = 2.6OC/W; 0JA = ISoc/w (no air flow); 0JA = 13"C1W (air flow = 500 LFM).
'3/4REF , 1I2REF , and 1I4REF reference ladder taps are driven from de sources at +0.875 V, 0 V, and -0.875 V, respectively. Accuracy of the overflow compara·
tor is not tested and not included in linearity specifications.
'Measured with ANALOG IN = +VSENSE.
'Output delay measured as worst·case time from 50% point of the rising edge of ENCODE to 50% point of the slowest rising or falling edge of Do-D•. Output
skew measured as worst-case difference in output delay among Do-D9'
6RMS signal to rms noise with analog input signal I dB below full scale at specified frequency.
'Intermodulation measured with analog input frequencies of 2.3 MHz and 3.0 MHz at 7 dB below full scale.
8Measured as the ratio of the worst-case change in transition voltage of a single comparator for a 5% change in +Vs or -Vs'
Specifications subject to change without notice.

REV. A

VIDEO AID CONVERTERS 4-21

a

AD9020
EXPLANATION OF TEST LEVELS
Test Level
I
II

-

III IV V VI -

100% production tested.
100% production tested at + 2SOC, and sample tested at
specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization
testing.
Parameter is a typical value only.
All devices are 100% production tested at +2SOC. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature extremes for commercial/industrial devices.

ORDERING GUIDE
Device
AD9020JZ
AD9020]E
AD9020KZ
AD9020KE
AD9020SZl883
AD9020SEl883
AD9020TZl883
AD9020TEl883
AD90201PCB

Temperature
Range

o to +70·C
o to +70OC
o to +70·C
o to +70·C
-S5OC to + 125·C
-55OC to + 125·C
- 550C to + 125·C
- 550C to + 125·C
o to +70·C

Description
68-Pin Leaded Ceramic
68-Pin Ceramic LCC
68-Pin Leaded Ceramic
68-Pin Ceramic LCC
68-Pin Leaded Ceramic
68-Pin Ceramic LCC
68-Pin Leaded Ceramic
68-Pin Ceramic LCC
Evaluation Board

Package
Option*
Z-68
E-68A
Z-68
E-68A
Z-68
E-68A
Z-68
E-68A

*E = Ceramic Leadless Chip Carrier; Z = Ceramic Leaded Chip Carrier.
For outline information see Package Information section.

DIE LAYOUT AND MECHANICAL INFORMATION
Die Dimensions . . . . . . . . . . . . . 206 x 140 x IS (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 4 x 4 mils
Metalization . • . . . • . . . . . . . . . . . . . . . . . . • . . . . . Gold
Backing . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . • . . . . . . . . . . . . • • . . . . • -Vs
Passivation . . . . . . . . . . . . . . . • . . . . . • . . . . . . . Nitride

+5.0V

.v.
D,
D,

n,

+Vs
GROUND

D.
D,(MSB)
OVERFLOW

.V.

•

-Ys
.Ys
ENCODE
GROUND
+VAEF

.v.....

GROUND

•

+Vs
-VRIF

-v...u
LSBolNVERT

STATIC: AD1 =-2V; AD2 • +lIAV
DYNAMIC: AD1 =t2V TRIANGLE WAVE
AD2 =TTL PULSE TRAIN

AD9020 Burn-In Circuit

4-22 VIDEO AID CONVERTERS

REV. A

AD9020

NC

NC
LSBslNVERT

+VSENSE

NC

+VREF

GND
ENCODE
+Vs
-'lis
GND
+Vs
(LSB)0,

-VSENSE
-VREF

AD9020
TOP VIEW

(Not to scale)

D,
D,
D,
D.

+vs
-VS
GND
+Vs
OVERFLOW
D,(MSB)

D,
D,
D.
D,

NC
+Vs

•

+Vs
NC

NC

AD9020 Pin Designations
AD9020 PIN DESCRIPTIONS
Pin No.

Name

Function

1I2REF

Midpoint of internal reference ladder.

2, 16, 28, 29, 35,
41, 42, 54, 64

- VS

Negative supply voltage; nominally -5.0 V ±5%.

3, 6, 15, 18, 25, 30,
33, 34, 37, 40, 45,
52, 55, 65, 68

+ VS

Positive supply voltage; nominally +5 V ±5%.

4,5, 13, 17,27,31,32
36, 38, 39, 43, 53, 66, 67

GROUND

All ground pins should be connected together and to lowimpedance ground plane.

7

3/~EF

Three-quarter point of internal reference ladder.

8,9

ANALOG IN

Analog input; nominally between ±1.75 V.

11

+VSENSE

Voltage sense line to most positive point on internal resistor
ladder. Normally +1.75 V.

12

+VREF

Voltage force connection for top of internal reference ladder.
Normally driven to provide + 1. 75 V at + VSENSE'

14

ENCODE

TTL-compatible convert command used to begin digitizing
process.

19-23,46-50

Do-D.

TTL-compatible digital output data.

51

OVERFLOW

TTL-compatible output indicating ANALOG IN >
+VSENSE'
Voltage force connection for bottom of internal reference
ladder. Normally driven to provide -1.75 V at -VSENSE'
Voltage sense line to most negative point on internal resistor
ladder. Normally -1.75 V.

56
57

-VSENSE

59

LSBs INVERT

NormaIiy grounded. When connected to + Vs, lower order
bits (00 -0 8 ) are inverted.

61

MSB INVERT

Normally grounded. When connected to + Vs' most
significant bit (MSB; D.) is inverted.

63

REV. A

One-quarter point of internal reference ladder.

VIDEO AID CONVERTERS 4-23

AD9020
THEORY OF OPERATION
Refer to the AD9020 block diagram. As shown, the AD9020
uses a modified "flash", or parallel, AID architecture. The analog input range is determined by an external voltage reference
(+VREF and -VREF), nominally ±1.75 V. An internal resistor
ladder divides this reference into 512 steps, each representing
two quantization levels. Taps along the resistor ladder (lI~F'
1I2REF and 3/~EF) are provided to optimize linearity. Rated
performance is achieved by driving these points at 114, 112 and
3/4, respectively, of the voltage reference range.
The AID conversion for the nine most significant bits (MSBs) is
performed by 512 comparators. The value of the least significant
bit (LSB) is determined by a unique interpolation scheme
between adjacent comparators. The decoding logic processes the
comparator outputs and provides a IO-bit code to the output
stage of the convener.
Flash architecture has an advantage over other AID architectures
because conversion occurs in one step. This means the performance of the converter is limited primarily by the speed and
matching of the individual comparators. In the AD9020, an
innovative interpolation scheme takes advantage of flash architecture but minimizes the input capacitance, power and device
count usually associated with that method of conversion.
These advantages occur because of using only half the normal
number of input comparator celli> to accomplish the conversion.
In addition, a proprietary decoding !>Cheme minimizes error
codes. Input control pins allow the user to select from among
Binary, Inverted Binary, Twos Complement and Inverted Twos
Complement coding (See AD9020 Truth Table).

APPLICATIONS
Many of the specifications ui>ed to describe analog/digital converters have evolved from system performance requirements in
these apppcations. Different systems emphasize particular specifications~ depending on how the part is ui>ed. The following
applications highlight some of the specifications and features
that make the AD9020 attractive in these systems.
Wideband Receivers
Radar and communication receivers (baseband and direct IF
digitization), ultrasound medical imaging, signal intelligence and
spectral analysis all place stringent ac performance requirements
on analog-to-digital converters (ADCs). Frequency domain characterization of the AD9020 provides signal-ta-noise ratio (SNR)
and harmonic distortion data to simplify selection of the ADC.
Receiver sensitivity is limited by the Signal-ta-Noise Ratio
(SNR) of the system. The SNR for an ADC is measured in the
frequency domain and calculated with a Fast Fourier Transform
(FFT). The SNR equals the ratio of the fundamental component of the signal (rms amplitude) to the rms value of the
"noise." The noise is the sum of all other spectral components,
including harmonic distortion, but excluding dc.
Good receiver design minimizes the level of spurious signals in
the system. Spurious signals developed in the ADC are the
result of imperfections in the device transfer function (nonlinearities, delay mismatch, varying input impedance, etc.). In
the ADC, these spurious signals appear as Harmonic Distortion.
Harmonic Distortion is also measured with an FFT and is specified as the ratio of the fundamental component of the signal
(rms amplitude) to the rms value of the worst case harmonic
(usually the 2nd or 3rd).

Two-Tone Intermodulation Distortion (IMD) is a frequently cited
specification in receiver design. In narrow-band receivers, thirdorder IMD products result in spurious signals in the pass band
of the receiver. Like mixers and amplifiers, the ADC is characterized with two, equal-amplitude, pure input frequencies. The
IMD equals the ratio of the power of either of the two input
signals to the power of the strongest third-order IMD signal.
Unlike mixers and amplifiers, the IMD does not always behave
as it does in linear devices (reduced input levels do not result in
predictable reductions in IMD).

4-24 VIDEO AID CONVERTERS

REV. A

AD9020 I
~erformance graphs provide typical harmonic and SNR data for
the AD9020 for increasing analog input frequencies. In choosing
an AID converter, always look at the dynamic range for the analog input frequency of interest. The AD9020 specifications provide guaranteed tninimum limits at three analog test frequencies.

Aperture Delay is the delay between the rising edge of the
ENCODE command and the instant at which the analog input
is sampled. Many systems require simultaneous sampling of
more than one analog input signal with multiple ADCs. In these
situations, titning is critical and the absolute value of the aperture delay is not as critical as the matching between devices.

Aperture Uncertainty, or jitter, is the sample-ta-sample variation
in aperture delay. This is especially important when sampling
high slew rate signals in wide bandwidth systems. Aperture
uncertainty is one of the factors which degrades dynamic performance as the analog input frequency is increased.
Digitizing Oscilloscopes
Oscilloscopes provide amplitude information about an obsel"lJed
waveform with respect to time. Digitizing oscilloscopes must
accurately sample this signal, without distorting the information
to be displayed.
One figure of merit for the ADC in these applications is Effective Number of Bits (ENOBs). ENOB is calculated with a sine
wave curve fit and equals:
ENOB = N - LOGz [Error (measured)/Error (ideal)]
N is the resolution (number of bits) of the ADC. The measured
error is the actual rms error calculated from the converter outputs with a pure sine wave input.
The Analog Bandwidth of the converter is the analog input frequency at which the spectral power of the fundamental signal is
reduced 3 dB from its low frequency value. The analog bandwidth is a good indicator of a converter's slewing capabilities.
The Maximum Conversion Rate is defmed as the encode rate at
which the SNR for the lowest analog signal test frequency tested
drops by no more than 3 dB below the guaranteed limit.

I
+FS~
I

I

-FS-

!

I

i

I

I

I

ENCODE~
Imaging Application Using AD9020
The actual resolution of the converter is limited by the thermal
and quantization noise of the ADC. The low frequency test for
SNR or ENOB is a good measure of the noise of the AD9020.
At this frequency, the static errors in the ADC detertnine the
useful dynamic range of the ADC.
Although the signal being sampled does not have a significant
slew rate, this does not imply dynamic performance is not
important. The Transient Response and Overvoltage Recovery
Time specifications insure that the ADC can track full-scale
changes in the analog input sufficiently fast to capture a valid
sample.

Transient Response is the time required for the AD9020 to
achieve full accuracy when a step function is applied. Overvoltage Recovery Time is the time required for the AD9020 to
recover to full accuracy after an analog input signal 150% of full
scale is reduced to the full-scale range of the converter.
Professional Video
Digital Signal Processing (DSP) is now common in television
production. Modern studios rely on digitized video to create
state-of-the-art special effects. Video instrumentation also
requires high resolution ADCs for studio quality measurement
and frame storage.
The AD9020 provides sufficient resolution for these demanding
applications. Conversion speed, dynamic performance and analog bandwidth are suitable for digitizing both composite and
RGB video sources.

Imaging
Visible and infrared imaging systems both require similar characteristics from ADCs. The signal input (from a CCD camera,
or multiplexer) is a time division multiplexed signal consisting of
a series of pulses whose amplitude varies in direct proportion to
the intensity of the radiation detected at the sensor. These varying levels are then digitized by applying encode commands at
the correct times, as shown below.
.

REV. A

VIDEO AID CONVERTERS 4-25

a

AD9020
USING THE AD9020
Voltage References
The AD9020.requires that .the user provide two voltage references: +VREF and -VREP • These two voltages are applied
across an internal resistor ladder (nominally 37 n) and set the
analog input voltage range of the converter. The voltage references should be driven from a stable, low impedance source. In
addition to these two references, three evenly spaced taps on the
resistor ladder (l/~EP' 1/2REF' 3/~p) are available. Providing
a reference to these quarter points on the resistor ladder will
improve the integral linearity of the converter and improve ac
perfOrtnance. (AC and dc specifications are tested while driving
the quarter points at the indicated levels.) The figure below is
not intended to show the transfer function of the ADC, but
illustrates how the linearity of the device is affected by reference
voltages applied to the ladder.

The select resistors (Rs) shown in the schematic (each pair can
be a potentiometer) are chosen to adjust the quarter-point voltage references, but are not necessary if RI-R4 match within
0.05%.

An alternative approach for defining the quarter-point references
of the resistor ladder is to evaluate the integral linearity error of
an individual device, and adjust the voltage at the quarter-points
to minimize this error. This may improve the low frequency ac
perfOrtnance of the converter.
Perfortnance of the AD9020 has been optimized with an analog
input voltage of ± I. 75 V (as measured at ± V SENS~. If the analog input range is reduced below these values, relatively larger
differential nonlinearity errors may result because of comparator
mismatches. As shown in the figure below, perfOrtnance of the
converter is a function of ± VSENSE.

...
III

1100000000

I_---+-----+-~'----'w:..-----l

8
~

~

56

I

zi" 50
!!?

w

w

1~1_---1__.~-~~--__l---~

10.0

62

1111111111 , - - - - , - - - - - , - - - - - . . , . . - - - . . . . , . .

~Z

V ....

/

/

--

9.0 iii'

~

~

!!:!.
8.0

....
C

w

III

7.0

44

0100000000

f---/----;;;;/F---

:Ii

::;)

Z

w

z

i

I&.

0

II:

*

o

Ii

6.0

38

~w
I&.
I&.

W

~&-----~------~----~~----~
-VSENSE
1/4REF
112REF
3/4REF
+VBENSE

Effect of Reference Taps on Linearity
Resistance between the reference connections and the taps of the
first and last comparators causes offset errors. These errors,
called "top and bottom of the ladder offsets," can be nulled by
using the voltage sense lines, + VSENSE and - VSENSE, to adjust
the reference voltages. Current through the sense lines should be
limited to less than 100 !lAo Excessive current drawn through
the voltage sense lines will affect the accuracy of the sense line
voltage.
The next page shows a reference circuit which nulls out the offset errors using two op amps and provides appropriate voltage
references to the quarter-point taps. Feedback from the sense
lines causes the op amps to compensate for the offset errors.
The two transistors limit the amount of current drawn directly
from the op amps; resistors at the base connections stabilize
their operation. The 10 kn resistors (RI-R4) between the voltage sense lines form an external resistor ladder; the quarter
point voltages are taken off this external ladder and buffered by
an op amp. The actual values of resistors RI-R4 are not critical,
but they should match well and be large enough (2:10 kn) to
limit the amount of current drawn from the voltage sense lines.

4-26 VIDEO AID CONVERTERS

32
0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

5.0
2.0

±VSENSE - Volts

AD9020 SNR and ENOB vs. Reference Voltage
Applying a voltage greater than 4 V across the internal resistor
ladder will cause current densities to exceed rated values, and
may cause pertnanent damage to the AD9020. The design of
the reference circuit should limit the voltage available to the
references.
Analog Input Signal.
The signal applied to ANALOG IN drives the inputs of 512
parallel comparator cells (see Equivalent Analog Input figure).
This connection typically has an input resistance of 7 kn, and
input capacitance of 45 pF. The input capacitanCe is nearly constant over the analog input voltage range, as shown in the graph
which illustrates that characteristic.
The analog input signal should be driven from a low distortion,
low noise amplifier. A good choice is the AD9617, a wide bandwidth, monolithic operational amplifier with excellent ac and dc
performance. The input capacitance should be isolated by a
small series resistor (24 n for the AD9617) to improve the ac
performance of the amplifier (see AD90201PCB Evaluation
Board Block Diagram).

REV. A

AD9020
ANALOG INPUT

,
I

~-

"'

101cU

I

I

AD9020 Equivalent Analog Input

+V.

20klJ

"'"
L...._...._

....... DIGITAL BITS

AND OVERFLOW·

-5V

AD9020 Reference Circuit
AD9020 Equivalent Digital Outputs

+S.OV

AD9020 Equivalent Encode Circuit

REV. A

VIDEO AID CONVERTERS 4-27

AD9020
N
ANALOG - - - -..
___
....

INPUT

1,t.
I~

ENCODE

N+1

~------.....---~

1_

-

_ _ _....

I

~ too

r-

I
I

Xl"-_______
DATA FOR N

DATA _ _ _- J .
OUTPUT

X

....I

_

DATA FOR N + 1

t. - Aperture Delay
too - Output Delay
AD9020 Timing Diagram

Timing
In the AD9020, the rising edge of the ENCODE signal triggers
the AID conversion by latching the comparators. (See the
AD9020 Timing Diagram.)
The ENCODE is TTUCMOS compatible and should be driven
from a low jitter (phase noise) source. Jitter on the ENCODE
signal will raise the noise floor of the converter. Fast, clean
edges will reduce the jitter in the signal and allow optimum ac
performance. Locking the system clock to a crystal oscillator
also helps reduce jitter. The AD9020 is designed to operate with
a 50% duty cycle; small (10%) variations in duty cycle should
not degrade performance.
Data Format
The fonnat of the output data (00- 0 9 ) is controlled by the
MSB INVERT and LSBs INVERT pins. These inputs are dc
control inputs, and should be connected to GROUND or + Vs.
The A09020 Truth Table gives information to choose from
among Binaty, Inverted Binary, Twos Complement and Inverted Twos Complement coding.
The OVERFLOW output is an indication that the analog input
signal has exceeded the voltage at + VSENSE. The accuracy of
the overflow transition voltage and output delay are not tested
or included in the data sheet Iitnits. Performance of the overflow
indicator is dependent on circuit layout and slew rate of the encode signal. The operation of this function does not affect the
other data bits (00-09 ). It is not recommended for applications
requiring a critical measure of the analog input voltage.

Analog signal paths should be kept as short as possible and be
properly terminated to avoid reflections. The analog input voltage and the voltage references should be kept away from digital
signal paths; this reduces the amount of digital switching noise
that is capacitively coupled into the analog section of the circuit.
Digital signal paths should also be kept short, and run lengths
should be matched to avoid propagation delay mismatch.
In high speed circuits, layout of the ground circuit is a critical
factor. A single, low impedance ground plane, on the component side of the board, will reduce noise on the circuit ground.
Power supplies should be capacitively coupled to the ground
plane to reduce noise in the circuit. Multilayer boards allow designers to layout signal traces without interrupting the ground
plane and provide low impedance power planes.
It is especially important to maintain the continuity of the
ground plane under and around the A09020. In systems with
dedicated digital and analog grounds, all grounds of the A09020
should be connected to the analog ground plane.
The power supplies (+ VS and - Vs) of the A09020 should
be isolated from the supplies used for external devices; this
further reduces the amount of noise coupled into the AlO converter. Sockets limit the dynamic performance and should be
used only for prototypes or evaluation-PCK Elastomerics
Part # CCS-68-55 is recommended for the LCC package.
(Tel. 215-672-0787)
An evaluation board is available to aid designers and provide a
suggested layout.

Layout and Power Supplies
Proper layout of high speed circuits is always critical but is
particularly important when both analog and digital signals are
involved.

4-28 VIDEO AID CONVERTERS

REV. A

AD9020

--

!II,50

....:::::

~~
~

i<

144

I:

8.0 (

II

8.0

~ ,/+25'C

i

7.0

~

-55"C & +125'C/\

~
\~

6.0

ii

fi

~
4.0 ..

4 6 810
20
40 60 100
INPUT FREQUENCY - MHz

1

26

200

4
6 8 10
20
40
CONVERSION RATE - MSPS

60

r-

,+I25'CL ~...

,

V /...

.....V

60

/.
......
1

~

1/ /~
....

v "..'
.. ..

r-....

+25'C

.,'

'

,

44

60

100

Range

1024
1023
1022

512
5Il
510

02
01
00

.......

V

r--.. I"- .......

l/
1

-1.2~.6

0
+0.6
+1.2
ANALOG INPUT (Ao. ) - Volts

+1.8

Input Capacitance/Resistance vs. Input Voltage

Offset Binary

0= -1.15 V
FS = +1.15 V

--

CAPACITANCE

~

-1.8

AD9020 Harmonics vs. Input Frequency

Step

RESISTANCE

II'

..

4
6 8 10
20
40
INPUT FREQUENCY - MHz

a

70

k1'

40

70

100

V

35

85

60

AD9020 SNR and ENOB vs. Conversion Rate

AD9020 SNR and ENOB vs. Input Frequency
30

1\

ANALOG INPUT = 2.3MHz

~
5.0

1\

26

20

10.0

10.0

ENcol,ERA~=I~

True
MSBINV = "0"
LSBs INV = "0"

Inverted

Twos Complement

MSB INV = "I"
LSBs INV = "1"

True
MSBINV = "I"
LSBs INV = "0"

MSBINV = "0"
LSBs INV = "1"

Inverted

>+ 1.7500
+ 1.7466
+ 1.7432

(l) III III III I

III III I III
1l1l1l1ll0

(I )0000000000
0000000000
0000000001

(1)01l1l1ll1l
01l1ll1l1l
OIl Il III 10

(I) 1000000000
1000000000
1000000001

+0.0034
0.000
.,.0.0034

1000000000
OIl III III I
01 III III 10

OllllIllIl
1000000000
1000000001

0000000000
1l1l1l1l1l
III III 1110

1ll1l1ll1l
0000000000
0000000001

-1.7432
-1.7466
<-1.7466

0000000010
0000000001
OOOOOOOOOO

1l1l1l1l01
1l1l1ll1l0
llllllllll

1000000010
1000000001
1000000000

OIl III 1101
OIl III 1110
01l1l1l1l1

The ovcrflow bit is always 0 except where noted in parentheses ( ). MSB INVERT and LSBs INVERT are considered de controls.

AD9020 Truth Table

REV,A

VIDEO AID CONVERTERS

~29

AD9020
AD90201PCB EVALUATION BOARD·
The AD9020IPCB· Evaluation Board is available from the factory
and is shown here in blgck diagram form. The board includes a
reference circuit that allows the user to adjust both references
and the quarter-point voltages. The AD9617 is included as the
drive amplifier, and the user can configure the gain from -I to

-IS.

On-board reconstruction of the digital data is provided through
the AD9713, a 12-bit monolithic DAC. The analog and reconstructed waveforms can be summed on the board to allow the
user to observe the linearity of the AD9020 and the effects of
the quarter-point voltages. The digital data and an adjustable
Data Ready signa1 are available through a 37-pin edge connector.
DAC
OUT

-5V

+5V

AD97130AC
D

D
ANALOG
INPUT

A09020

TO ERROR
WAVEFORM
CIRCUIT

OUT

+YR1F

.VSENSE
314 f1EF
REFERENCE
CIRCUIT

D.

0,
D.

0,

0,
(USB) D.
OVERFLOW

ENCODE

D
D
Q
D
D
TTL
D LATCHES
D

OUTPUT

1-------,(1

D
D
D
D

CO,::trOR
DATA
READY

i-----t<>t----ot

AD9020/PCB Evaluation Board Block Diagram

4-30 VIDEO AID CONVERTERS

REV. A

IIIIIIIIIIII ANALOG

WDEVICES
FEATURES

Monolithic 8-Bit
Video AID Converter
AD9048 I
FUNCTIONAL BLOCK DIAGRAM

35MSPS Encode Rate
16pF Input Capacitance
550mW Power Dissipation
Industry-Standard Pinouts
MIL-8TO-883 Compliant Versions Available
APPLICATIONS
Professional Video Systems
Special Effects Generators
Electro-Optics
Digital Radio
Electronic Warfare (ECM. ECCM. ESMI

•

GENERAL DESCRIPTION
The AD9048 is an 8-bit, 35MSPS flash converter, made on a
high speed bipolar process, which is an alternate source for the
TDCl048 unit but offers enhancements over its predecessor.
Lower power dissipation makes the AD9048 attractive for a
variety of system designs.

Because of its wide bandwidth, it is an ideal choice for real-time
conversion of video signals. Input bandwidth is flat with no
missing codes.
Clocked latching comparators, encoding logic and output buffer
registers operating at minimum rates of 35MSPS preclude a
need for a sample-and-hold (S/H) or track-and-hold (T/H) in
most system designs using the AD9048. All digital control inputs
and outputs are TTL compatible.
Devices operating over two ambient temperature ranges and
with two grades of linearity are available. Linearities of either
O.5LSB or O.75LSB can be ordered for a commercial range of 0
to + 70·C, or extended case temperatures of - 55"C to + l25·C.
Commercial versions are packaged in 28-pin DIPs; extended
temperature versions are available in ceramic DIP and ceramic
LCC packages. Both commercial units and MIL-STD-883 units
are standard products.
The AD9048 AID converter is available in versions compliant
with MIL-STD-883. Refer to the Analog Devices Military Products
Darabook or current AD9048/883B data sheet for detailed
specifications.

REV. A

VIDEO AID CONVERTERS 4-31

AD9048 ~ SPECIFICATIONS

!tJpicaJ willi nominal suppUes un. othIIWisa noIIId)

ABSOLUTE MAXIMUM RATINGS!
Vccto PGND ..
-O.5V de to +7.0V de
AGND toDGND . . . . . . . . . . . -O.5V de to +O.5V de
VEE to AGND • • . . . . . . . . . . . + O.5V de to -7.0V de
VIN, VRT or Vim to AGND . . . . . . . . . . . +O.5V to VEE
VRT to VRii . . . '• . . • . • . . • . . -2.2V de to +2.2V de
CONY, NMINV or NLINV to DGND. -O.SVdeto +5.5Vde
Applied Output Voltage to DGND. - O.5V de to + 5.5V de2
Applied Output Current, Extemally Forced
. . . . . . . . . . . . . . . . . . . -l.0rnA to + 6.0rnA 3, 4

Output Short-Circuit Duration . . . . . •
Operating Temperature Range (Ambient)
AD9048JNIKNIlJIKJIJQ/KQ . . . . .
AD9048SElSQrrEffQ . . • . . • . . •
Maximum Junction Temperature (Plastic)
Maximum Junction Temperature (Hermetic)
Lead Temperature (Soldering, 10sec)
Storage Temperature Range . . . . . . • . .

o to +70"C
- 55"C to + 125"C
+ 150"C6
. . . . . + 175"C6
. . . . . +300·C
- 65"C to +150"C

ELECTRICAL CHARACTERISTICS !Vee = +5.OV; V = -5.2Y; Differential RefII1IIIC8 Yofta&e=2.OV, IIIIess oIherwise _
EE

AD9048JNIJJIIQ
~(CoadiIioa)

Temp

Test
LeYeI

RESOLUTION
DC ACCURACY
DiffereDtiaI NcmJineority

+25"C
Full
Full

+25"C

+2S"C
Full
+25"C
Full
Full

I
VI
I
VI
V

Full

V

+25"C
Full
+ 25"C
Full
+25"C
+25"C

I
VI
I
VI
III
III

Full
Full
Full
Full
Full
+25"C

V
V
V
VI
V
VI
V

DYNAMIC PERFORMANCE"
Conversion Rate lZ , 14
Apenure Delay
Apenure Uncertainty (Jitter)
Output Delay (tro)" 12
Output Hold Time (toH)"
Transient Responsc"
OvervoItaseRecovery Time'7
RiseTime
FaUTime
OutputTimeSkew"'

+25"C
+ 25"C
+25"C
+25"C
+25"C
+25"C
+25"C
+25"C
+25"C
+ 25"C

I
III
III
I
I
I
V
I
I
I

NMINV and NUNV INPUTS" 12
+ 0.4V Input Current
+2.4VIDputCurrent
+5.5VlnputCurrent

Full
Full
Full

VI
VI
VI

CONVERT INPUT
J..osic: "I" Voltase
LoPe "0" Voltase
J..osic:"I"Cutrent(V,= +2.4V),,12
J..osic: "I" Current (V, = + 5.5V)'·12
Lope 110" CUJ'I'CIltl. 12
Input Clpocitaoce
Convert Puloe Width (LOW)
Convert Pulsc Width (HIGH)

Full
Full
FuU
Full
FuU
+25"C
+25"C
+25"C

VI
VI
VI
VI
VI
III
I
I

Full

No MissiDgCodes
INITIAL OFFSET JlRR.OR
Top of Reference Ladder
BottomofRefemx:e Ladder
Offset Drift CoeftiC:ient
ANALOG INPUT
Input Voltase Ranae
Input Bias Current" I,'
Input Rcsiswx:c
Input Clpacitaoce
Full Power Bandwidth'·
REFI!RENCEINPUT
PoIitiveRefemx:e Voltase"
Neptive Refereuce Voltase"
Differmtial Reference Voltase
Reference Ladder Resistaoce
LadderTemperatuteCoeflicient
Reference LadderCurrent 12
Reference InputllaDdwiclth

Typ

Ala

8
I
VI
I
VI
VI

Intep1ll NcmJineority

Mia

Full

4-32 VIDEO AID CONVERTERS

0.6

0.75
1.0
0.75
1.0

0.4

V"*
Bits

0.3

-2.1;
+0.1
36
60
100

-2.1;
+0.1
60
36
100

-2.1;
+0.1
60
36
100

-2.1;
+0.1
36
60
100

V
p.A
p.A

4

200
40

300

20
10

90

38
2.4
25
13
8
6
8

20
10

0.0
-2.0
2.0
125

50

40

35
5
50
15
5
20

90

9
14
7

125
40

38
2.4
25
9
8

5
50
IS

6
8

4.5

50

16
15

90

5
20
9
14
7

38
2.4
25
9
8
6
8
4.5

200
10
10

0.8
IS
15
500
6

4

20
10

16
15

125

SO

90

0.22
23
10

40

35
5
50
15
5
20
9
14
7

38
2.4
25
9
8
6
8
4.5

200
10
10

0.8
15
15
SOO
6

20

0.8
15
15
500
6

4
18
10

pF
MHz
V
V
V

125
40

n

nrc
mA

MHz
MHz
5
SO
IS

DB
pi

DB '
DB

9
14
7

ns
as
as
as
as

200
10
10

p.A
p.A
,..A

0.8
IS
15
500
6

V
V
p.A
p.A
p.A
pF

20

2.0

4
18
10

kG
kG

300

0.0
-2.0
2,.0

2.0

4
18
10

5

200
40

300

0.22
23
10
35

2.0

2.0

12
12
8
8

0.0
-2.0
2.0

0.22
23
10

200
10
10

4

4

200
40

300

16
15

5

12
12
8
8

-

LSB
LSB
LSB
LSB

20

4.5

18
10

Ala

0.5
0.75
0.4
0.5
0.75
GUARANTEED

0.75
1.0
0.6
0.75
1.0
GUARANTEED
0.4

12
12
8
8

Typ

8

20

0.22
23
10

5

0.5
0.75
0.5
0.75

AD9048TEITQ
Mia

20

16
15

5

0.0
-2.0
2.0

35

Ala

8
0.3

12
12
8
8

Typ

20

4

50

Mia

mV
mV
mV
mV
,..Vr'C

5

10

Ala

GUARANTEED

GUARANTEED

200
40

Tn>

8
0.4

AD9048SEISQ

AD9048KNIKJIKQ
Mia

DB

as

REV. A

AD9048
AD9048JN/JJ/JQ
l'uometot(CoIlditioa.)
ACUNEARITY
In-Bond HIrmoaic:s
de to Z.438MHz"
de to 9.35MHz'O
Sipal-to-Noioo Ratio (SNR)19
1.248MHzlnputFrequ.ncy21
2.438MHz Input Frequmcy'l
1.248MHz Input Frequ.ncy"
2.438MHz Input Freq\lOllCy"
SipaI-to-Noioo Ratio(SNR)20
1.248MHz Input Frequmcy'l
9.35MHzlnputFrequency"
Noioo Power Ratio (NPRr'
DifIotentiai ~.
DifIotentiai Gain"
DlGITALOUTPUTS
LotPc "I" VolllF"
l.oIic "0" VolllF" I.
Short Cin:uit Cunent'

POWER SUPPLY
PooitivcSupplyCurront( + 5.5V)
(VEE ~ - 5.5V)
Neptivc Supply Cu,mll ( - 5.5V)
Nominal Power DiIoipation
Rof_ Ladder Dissipation

To.t
Lnol

MiD

Tn>

+25'C
+25'C

I

47

+25'C
+25'C
+25'C
+25'C

I

+25'C
+25'C
+25'C
+25'C
+25'C

Ala

MiD

Tn>

50
48

49

43.5
43
52.5
52

44
44
53
53

I
V
III
III
III

43.5

44
40.5
39

Fun
Fun
Fun

VI
VI
VI

2.4

+25'C
Fun
+25'C
Fun
+25'C
+25'C

I
VI
I
VI
V
V

Tomp

V

I
I
I

36.5

Max

90

AD9048TEfJ'Q

Ala

u.

MiD

Tn>

50
48

49

55
48

dBc
dBc

44
44
53
53

45
44
54
53

46
46

55
55

43.5
43
52.5
52

dB
dB
dB
dB

45

46

43.5

46

36.5

44
40.5
39

45

40.5
39

36.5

40.5
39

MiD

Tn>

55
48

47

45
44
54
53

46
46

36.5

I

I

2

2

Max

55
55

1
2

1
2

dB
dB
dB
Dqxoo
'II.

0.5

0.5

0.5

0.5

V
V

30

30

30

30

mit.

34

46

90

48
110
120

mit.
mit.
mit.
mit.

2.4

34

AD9048SElSQ

AD9048KNIKJIKQ

2.4

46
48

34

46

110
120

90

48
110
120

550
45

SSO
45

2.4

34

46

90

48
110
120

S50
45

mW
mW

S50
45

NOTES:

I ~ ntinp .... limitins values, to be opplied iDdividuaUy, ODd beyond wbicb the ..rvia:ability of the device may be impoi.!od. FUDCtioDol operatioo UDder
conditioos is DOl lIOCOIIIrily implied. Ezpooure to absolute maaimum ratins conditioos for extended periods of tim. may affect device rdiabiJity.
'Applied
mUll be cuneat-limitecl to specif!ecl .......
'Forciq
mill! be limited '0 specif!ecl .......
'Cunen, is specif!ecl as _ri....boo flowirqj into the device.
'Outpul HiP; ODe pill to pouad; one sec:oad duratioD.
'Typic:aI rhermol impecl.mces (00 air flow) .... as fo1lows:
Conmic:DIP: '1' ~49'CIW;'lc~ 1S"CIW
LCC: ," ~69'CIW;6,c ~21"CIW
Plutic:DIP:',. ~51'C1W;'lc ~ 16"CIW
PLCC: '1' ~ 59;'lc~ 19
To c:ak:ulate iunction temperature (T,)' .... power diaipation (PD) ODd rhermol impedance:
T,~PD(6,.)+T'M'IEHT~PD('lcl~ +TCAS'
'MasweclwitbV,H ~ OVODdCONVERTlow(_plinsmode).
'Vee ~ +5.5V
'V•• ~ -5.5V
1"DourminecI bY bea, frequmoy testins for 00 miainec:odes.
"VaT ~ Vu UDderaJlcircwuEaDCCI.
IlVn = -".9V
"OutpUll terminated witb 40pF ODd lion puB-up miston.
l'Vee ~ +4.5V
l'Intervai from 50% point ofleadinseclse CONVERT puIso 'oc.,.",. in outpUt clara.
I·POl'IuD ICaIc ItepiDput, a..bit KCUnC)' anaiDc:d in specifaed. time.
17Recovcn to 8-bit ICCUraCY in specifted rime after - 3V inpu' ovcrvol.....
''ourput time skew iadudea hiah·ro-Iow UId Iow-ro.hiab rransitions as well as bit-to-bit time skew differences.
19Maswec1.t20MHz.DCOderate ..itb ....... inpu'lclBbelowfUUIIC4le.
lOMaswecI.,35MHzeDCOderate witb ....... inpu'lcIB belowfuU acaIo.

vol_
vol_

IIDY

of these

llRMSIipaI tol1DlDOiIe.
zzPeak, IipaI to I1DI noiJe.

"DC to 8MHz aoiao _width ..i,b 1.248MHz slot; four sipra losdiDs; ZOMHz oocode.
"CIookfrequency ~ 4 x NTSC ~ 14.32MHz. MaswecI witb4l).lREmocIuIa,ec1 ramp.
SpecilicatioDS ...bjoct tocbaD&e withou' notice.

EXPLANATION OF TEST LEVELS
- 100% production tested.
- 100% production tested at + 25"C and
sample tested at specified temperatures.
Test Level III - Sample tested only.
Test Level IV - Parameter is guaranteed by design and
characterization testing.
Test Levell
Test Level II

REV. A

Test Level V - Parameter is a typical value only.
Test Level VI - All devices are 100% production tested at
25"C. 100% production tested at temperature
extremes for military temperature devices;
sample tested at temperature extremes for
commercial/industrial devices.

VIDEO AID CONVERTERS 4-33

AD9048
ORDERING GUIDE
Model

Linearity

Temperature

Package
Option l

AD9048JN
AD9048KN
AD9048JJ
AD9048KJ
AD9048JQ
AD9048KQ
AD9048SE2
AD9048TE2
AD9048SQ2
AD9048TQ2

0.75LSB
0.5LSB
0.75LSB
0.5LSB
0.75LSB
O.sLSB
0.75LSB
o.sLSB
0.75LSB
0.5LSB

Oto +70oe
Oto +70oe
Oto +70"e
Oto +70oe
Oto +70oe
Oto +70oe
- 55°e to + 125°e
- 55°e to + 125°e
- 55°e to + 125°e
- 55°e to + 125°e

N-28
N-28
J-28
J-28
Q-28
Q-28
E-28A
E-28A
Q-28
Q-28

NOTES
'E = LeadlessCeramicChipCarrier;J = J-LeadedCeramic; N = Plastic DIP; Q = Cerdip.
For outline information see Package Information section.
'For specifications, refer to Analog Devices Military Products Databook.

MECHANICAL INFORMATION

127x 140x4 (±2) mils

Die Dimensions
Pad Dimensions
Metalization . .
Backing . . . .
Substrate Potential
Passivation
Die Attach
Bond Wire

Ii

a

•

II
3

a

•

DGNO •

Vee •
V.. 7
V. . .
VEE'

!
Ci
1

Iii

II

rl

C

28 27 21

..

~ ~
:I

.; .; 0

•

z «

25 "GND
.. Ne

Vee

NC

23 V.

V~

AD8048
TOP VIEW

VEE

•• He

VEE

NC

INot toSufe)

., He

VEE

NC

Vee

NC

20 He

,. AGND

DGND11

N"'V

I.

DO

~
Z

4-34 VIDEO AID CONVERTERS

J-Leaded Ceramic:

>

Vcc l0

NC=NOCONNECT

. VEE
. Nitride
Gold Eutectic
I mil Gold; Gold Ball Bonding

PIN CONFIGURATIONS
LCe

DIP

DO

4x4mils
. Gold
None

13 14 "

l!I 8

Ii

.

,. 17 11

!I
!

8

NC -NOCONNECT

c

c; 0

Iii

~

~

I
REV. A

AD9048
FUNCTIONAL DESCRIPTION
Pin
Name

Pin
Name

Description
Eight digital outputs. 01 (MSB) is the most
significant bit of the digital output word;
D8 (LSB) is the least significant bit.

AGND

One of two analog ground returns. Both grounds
should be connected together and to low impedance
ground plane near the AD9048.

DGND

One of two digital ground returns. Both grounds
should be connected together and to low impedance
ground plane near the AD9048.

Most positive reference voltage for internal
reference ladder.

Positive supply terminals; nominally

Negative supply terminals; nominally -S.2V.

CONVERT

Input for conversion signal; sampl,. of analog
input signal taken on rising edge of this pulse.

-5.2V

Analog input signal pin.

NMINV

"Not Most Significant Bit Invert." In normal
operation, this pin floats high; logic LOW at
NMINV inverts most significant bit of digital
output word [01 (MSB)].

NLINV

"Not Least Significant Bit Invert." In normal
operation, thi, pin floats high; logic LOW at
NLINV inverts the seven least significant bits of
the digital output word.

+5.0V

~~~

1r

0.'

v""

VEE

AD2

V 1N

+ S.OV.

Vee

,oon

Most negative reference voltage for internal
u,ference ladder.
Midpoint tap on internal reference ladder.

VEE

AD,

Description

RB

01-D8

(MSBID'

v..

D2

CONVERT

D4

D3

5,00

AD9048
-2.0V

D5

lie

De

r- RT

(LSII De

D7

DIGITAL
GROUND

1
20%

ANALOG
GROUND

~

'k

LOAD
RESISTORS

I
OPTION #1ISTATlCI: A
YNAMIC :

n n U n U nU n U n U n U n U r _- vVII.-..

AD2 .J U

--I5~'1-AD9048 Burn·ln Diagram

REV. A

VIDEO AID CONVERTERS 4-35

4

AD9048
THEORY OF OPERATION
Refer to the block diagram of the AD9048. The AD9048 comprises
three functional sections: a comparator array, encoding logic,
and output latches.
Within the array, the analog input signal to be digitized is compared
with 255 reference voltages. The outputs of all comparators
whose references are below the input signa1level will be high;
and outputs whose references are above that level will be low.

System timing which provides details on delays through the
AD9048, as well as the relationships of various timing events, is
shown in Figure 2, AD9048 Timing Diagram.
Dynamic performance of the AD9048, i.e., typical signa1-ta-noise
ratio, is illustrated in Figures 3 and 4.
nov

"'

The n-of-255 code which results from this comparison is applied
to the encoding logic where it is converted into binary coding.
When it is inverted with dc signals applied to the NLINV and/or
NMINV pins, it becomes twos complement.

CONV.....

After encoding, the. signa1 is applied to the output latch circuits
where it is held constant between updates controlled by the
application of CONVERT pulses.
The AD9048 uses strobed latching comparators in which comparator outputs are either high or low, as dictated by the analog
input level. Data appearing at the output pins have a pipeline
delay of one encode cycle.

r.~

Input signa1levels between the references applied to RT (Pin 18)
and RB (Pin 26) will appear at the output as binary numbers
between 0 and 255, inclusive. Signals outside that range will
show up as either full-scale positive or full-scale negative outputs.
No damage will occur to the AD9048
long as the input is
within the voltage range of VEE to +O.5V.

I
I

RI2

as

-5.ZV

The significantly reduced input capacitance of the AD9048
lowers the drive requirements of the input buffer/amplifier and
also induces much smaller phase shift in the analog input signal.

...

RI2

ANALOG
INPUT
I
I

Applications which depend on controlled phase shift at the
converter input can benefit from using the AD9048 because of
its inherently lower phase shift.

-S.2V

-1.2V

The CONVERT, analog input and digital output circuits are
shown in Figure 1, AD9048 Input/Output Circuits.

t-Ro

COMPARATOR

CELLS

Figure 1. InputiOutputCircuits

N+l
ANALOG

INPUT

CONVERT

OUTPUT
DATA

-rwI-toH

---.J-M

-I

N-l

N

N+l

1- ....
Figure 2. AD9048 Timing Diagram

4-36 VIDEO AID CONVERTERS

REV. A

AD9048
Ceramic 0.I ....F decoupling capacitors should be placed as close
as possible to the supply pins of the AD9048. For decoupling
low frequency signals, use IO ....F tantalum capacitors, also connected as close as practical to voltage supply pins.

50

.

" 1\

.
..

100kHz

Within the AD904R. reference currents may vary because of
coupling betwee'l the clock and input signals. Because of this, it
is important that the ends of the reference ladder, RT (Pin 18)
and RB (Pin 28), be connected to low impedances (as measured
from ground) .

1Mttz

10Mtb:

ANALOG INPUTFREOUENCY -1dB BELOWFUU SCALE

If the AD9048 is being used in a circuit in which the reference
is not varied, a bypass capacitor to ground is strongly recommended. In applications which use varying references, they
must ,be driven from a low impedance source.
0.1

Figure 3. AD9048 Dynamic Performance (20MHz Encode
Rate)

II

50

.
~.
..
!...
..
'Ii

~

::l

1\
01 (MSB)

Ii

100kHz

1MHz

10MHz

ANALOG INPUT mEQUENCY _ 1dB BELOW FULL SCALE

TTL

CONVERT ( . , : f . - - - - - - - - - j CONVERT
SIGNAL

DOILSB)

Figure 4. AD9048 Dynamic Performance (35MHz Encode
Rate)

LAYOUT SUGGESTIONS
Designs which use the AD9048 or any other high-speed device
must follow some basic layout rules to insure optimum
performance.

Figure 5. AD9048 Typical Connections

The first requirement is to have a large, low impedance ground
plane under and around the converter. If the system uses separate
analog and digital grounds, both should be connected solidly
together and to the ground plane as close to the AD9048 as
practical, to avoid ground loop currents.

REV. A

VIDEO AID CONVERTERS 4-37

AD9048
AD9048 Truth Table
Biliary
Step

000
001

···

True

R....

-2.oooVFS
7.843ImVStep

-2.0480VFS
8.000mVSlep

NMINV= I
NLINV = I

O.OOOOV
-0.0078V

O.OOOOV
-0.0080V

00000000
00000001

···

··
·

127
128
129

-O.996IV
-1.0039V
-1.0118V

-1.0160V
-1.0240V
-1.0320V

254
255

-1.992IV
-2.0000V

-2.0320V
-2.0400V

··
·

··
·

4-38 VIDEO AID CONVERTERS

··

·

··
·

Offset Twos
Complement
Inverted

Inverted

True

0
0

0
I

I
0

11111111
11111110

10000000
10000001

01111111
01111110

··
·

·

··

··

·

01111111
10000000
10000001

10000000
01111111
01111110

11111111
00000000
00000801

00000000
11111111
11111110

11111110
11111111

00000001
00000000

01111110
01111111

10000001
10000000

··
·

··
·

··
·

···

REV. A

lO-Bit, 75 MSPS
AID Converter
AD9060 I

11IIIIIIII ANALOG
L.III DEVICES
FEATURES
Monolithic 10-Bit/75 MSPS Converter
EClOutputs
Bipolar (±1.75 VI Analog Input
57 dB SNR @ 2.3 MHz Input
Low (45 pFllnput Capacitance
Mll-STD-883 Compliant Versions Available

FUNCTIONAL BLOCK DIAGRAM
IIIS.LHS
INVElilTIN'II!IIT

APPLICATIONS
Digital Oscilloscopes
Medical Imaging
Professional Video
Radar Warning/Guidance Systems
Infrared Systems

II
.

~(IIIS8J

D,

GENERAL DESCRIPTION
The AD9060 AID converter is a lO-bit monolithic converter capable of word rates of 75 MSPS and above. Innovative architecture using 512 input comparators instead of the traditional 1024
required by other flash converters reduces input capacitance and
improves linearity.
Inputs and outputs are ECL-compatible, which makes the
AD9060 the recommended choice for systems with conversion
rates > 30 MSPS, to minimize system noise. An overflow bit is
provided to indicate analog input signals greater than + VSENSE'

D.

D,

D,

'

1'DoIL88)

....

Voltage sense lines are provided to insure accurate driving of the
± VREF voltages applied to the units. Quarter-point taps on the
resistor ladder help optimize the integral linearity of the unit.
Either 68-pin ceramic leaded (gull wing) packages or ceramic
LCCs are available and are specifically designed for low thermal
impedances. Two performance grades for temperatures of both 0
to +70"C and - 55°C to + 1250C ranges are offered to allow the
user to select the linearity best suited for each application. Dynamic performance is fully characterized and production tested
at + 25°C. MIL-STD-883 units are available.

QROUt4D

The AD9060 AID converter is available in versions compliant
with MIL-STD-883. Refer to the Analog Devices Military
Products Darabook or current AD9060/883B data sheet for detailed specifications.

REV. A

VIDEO AID CONVERTERS 4-39

AD9060-SPECIFICATIONS
3/~, 1/2REP ' I/~p Current . . . . • . . . . . . . . . • :t 10 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature
AD9060JElKElJZIKZ . . . . . . . . . . . . . . . . . . 0 to + 7O"C
Storage Temperature . . . . . . . . . . . . . . . . -65"C to + 150°C
Maximum Junction Tempera~ . . . . . . . . . . . . . . +175"C
Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . + 300"C

ABSOLUTE MAXIMUM RATINGS'
+Vs . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
-.Vs • . . . . . • . • . . . . • . • . . . • . . • . . . . . . . . . . . -6 V
ANALOG IN ....................... -2 V to +2 V
+VIlEP' -VIlEP' 3/~EP' 1I21lEP' lI~p ..... -2 V to +2 V
+VIlEP to -VllEp • • • • • • • • • • • • • • • • • • • • • • • • • • 4.0 V
ENCODE, ENCODE . . . . . . . . . . . . . . . . . . . 0 V to -VS

Parameter (Conditions)

Temp

Test
Level

Integral Nonlinearity
No Missing Codes
ANALOG INPUT
Input Bias Current'
Input Resistance
Input Capacitance'
Analog Bandwidth
REFERENCE INPUT
Reference Ladder Resistance
Ladder Tempco
Reference Ladder Offset
Top of Ladder
Bottom of Ladder
Offset Drift Coefficient
SWITCHING PERFORMANCE
Conversion Rate
Aperture Delay (tA )
Aperture Uncertainty (Jitter)
Output Delay (toD)S
Output Rise Time
Output Fall Time
Output Time SkewS
DYNAMIC PERFORMANCE
Transient Response
Overvoltage Recovery Time
Effective Number of Bits (ENOB)
fIN = 2.3 MHz
fIN = 10.3 MHz
fIN = 29.3 MHz
Signal-to-Noise Ratio·
fIN = 2.3 MHz
fIN = 10.3 MHz
fIN = 29.3 MHz

4-40 VIDEO AlO CONVERTERS

Typ

Max

10

RESOLUTION
DC ACCURACy3
Differential Nonlinearity

AD9060JElJZ
Min

Min

AD9060KEIKZ
Typ
Max

10

+ 25°C
Full
+25"C
Full
Full

I
VI
I
VI
VI

1.0

+25"C
Full
+25"C
+25"C
+25°C

I
VI
I
V
V

0.4

+25"C
Full
Full

I
VI
V

+25°C
Full
+25"C
Full
Full

I
VI
I
VI
V

+25°C
+25°C
+25°C
+ 25°C
+25°C
+2S"C
+2SoC

I
V
V
I
I
I
I

+2S"C
+25°C

V
V

+2S"C
+2SoC
+2SoC

I
IV
IV

8.7
8.0
7.0

9.1
8.6
7.4

+2SoC
+ 25°C
+ 25°C

I
I
I

54
51

56
54
47

1.25

1.25
1.5
2.0
2.5

Units
Bits

0.75
1.0

1.0
1.25
I.S
2.0

LSB
LSB
LSB
LSB

1.0
2.0

mA
mA
ill
pF
MHz

56
66

n
n

Guaranteed

2.0

7.0
45
175

22
14

37

1.0
2.0

56
66

0.4
2.0

7.0
45
175

22
14

37

0.1
45
45

90
90
90
90

45

75

90
90
90
90

1
5
4
1
1
I.S

MSPS
ns
ps, rms
ns
ns
ns
ns

75
1
5
4
1
1
I.S

9
3
3
3

2

10

9
3
3
3

10
10

ns
ns

8.7
8.0
7.0

9.1
8.6
7.4

Bits
Bits
Bits

54
51

S6
54
47

dB
dB
dB

10

44

50

mV
mV
mV
mY
",VI"C

45

50

2

nt"C

0.1

44

REV. A

AD9060
AD9060KElKZ
Typ
Max

Temp

Test
Level

Min

+25"C
+25"C
+ 25"C

I
I
I

54
51
46

56
55
48

54
51
46

58
55
48

dB
dB
dB

+ 25"C
+25"C
+25"C

I
I
I

61
55
47

65
58
50

61
55
47

65
58
50

dBc
dBc
dBc

+25'C
+25'C
+25'C

V
V
V

70
0.5
I

dBc
Degree
%

ENCODE INPUT
Logic "I" Voltage
Logic "0" Voltage
Logic "1" Current
Logic "0" Current
Input Capacitance
Pulse Width (High)
Pulse Width (Low)

Full
Full
Full
Full
+25'C
+25'C
+25'C

VI
VI
VI
VI
V
I
I

DIGITAL OUTPUTS
Logic "I" Voltage
Logic "0" Voltage

Full
Full

VI
VI

+25'C
Full
+25'C
Full
+25'C
Full

VI
VI
VI
VI
VI
VI

420

Full

VI

6

Parameter (Conditions)
DYNAMIC PERFORMANCE
(CONTINUED)
Signal-to-Noise Ratio6
(Without Hannonics)
fIN = 2.3 MHz
fIN = 10.3 MHz
fIN = 29.3 MHz
Hannonic Distortion
fIN = 2.3 MHz
fIN = 10.3 MHz
fIN = 29.3 MHz
Two-Tone Intennodulation
Distortion Rejection7
Differential Phase
Differential Gain

POWER SUPPLY
+ Vs Supply Current
- Vs Supply Current
Power Dissipation
Power Supply Rejection
Ratio (PSRR)'

AD9060JElJZ
Typ
Max

Min

70
0.5
I

-1.1

-1.1
150
150
5

-1.5
300
300

6
6

150
150
5

-1.5
300
300

6
6

-1.1

-1.1
-1.5

150
2.8

500
500
180
190
3.3
3.5
10

-1.5
420
150
2.8

6

Units

V
V
fLA
fLA
pF
ns
ns
V
V

rnA

500
500
180
190
3.3
3.5

W
W

10

rnVN

rnA

rnA
rnA

NOTES
lAbsolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability afthe circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
'Typical thermal impedances (part soldered onto board): 68-pin leaded ceramic chip carrier: 6lC = I'CIW; 6lA = 17'CIW (no air f10W);6 IA = 15'CIW
(air flow = 5()() LFM). 68'pin ceramic LCC: 6lC = 2.6'CIW; 6lA = 15'CIW (no air flow); 6JA = l3'CIW (air flow = 500 LFM).
33J4REF , 1I2REF , and 1/4REF reference ladder taps are driven from de sources at +0.875 V, 0 V, and -0.875 V, respectively. Outputs terminated through 100 n
to -2.0 V; CL < 4 pF. Accuracy of the overflow comparator is not tested and not included in linearity specifications.
'Measured with ANALOG IN = +V'ENSE'
'Output delay measured as worst·case time from 50% point of the rising edge of ENCODE to 50% point of the slowest rising or falling edge of Do-D •. Output
skew measured as worst-case difference in output delay among Do-D9'
6RMS signal to rms noise with analog input signal I dB below full scale at specified frequency.
'Intermodulation measured with analog input frequencies of 2.3 MHz and 3.0 MHz at 7 dB below full scale.
8 Measured as the ratio of the worst-case change in transition voltage of a single comparator for a 5% change in + Vs or - Vs'
Specifications subject to change without notice.

REV. A

VIDEO AID CONVERTERS +-41

II

AD9060
EXPLANATION OF TEST LEVELS
Test Level
I
II

- 100% production tested.
- 100% production tested at + 25°C, and sample tested at
specified temperatures.
III - Sample tested only.
IV - Parameter is guaranteed by design and characterization
testing.
V - Parameter is a typical value only.
VI - All devices are 100% production tested at + 25°C.
100% production tested at temperature extremes for
extended temperature devices; sample tested at temperature extremes for commercial/industrial devices.

GROUND
D.

0,
0,
0,
D,(LSB)
GROUND
GROUND

.v.

ENCODE

EtiCliiiE
+VREF

GROUND
0,
0,

0.
0,
0, (MSB)
OVERFLOW
GROUND
GROUND

-v.

-v...

-v..lSBslNVERT

·v"EJil8£

ORDERING GUIDE

Device
AD9060JZ
AD9060JE
AD9060KZ
AD9060KE
AD9060SZ2
AD9060SE2
AD906OTZ 2
AD9060TE2
AD9060IPCB

Temperature
Range

Package
Option'

o to +700<:
o to +70OC
o to +70°C
o to +70°C

Z-68
E-68A
Z-68
E-68A
Z-68
E-68A
Z-68
E-68A
Evaluation Board

- 5SOC to +l2SoC
- SSOC to +l2SoC
-55°C to + 125°C
- SSOC to + 125°C
oto +1ooc

DIE LAYOUT AND MECHANICAL INFORMATION
Die Dimensions . . . . . . . . . . . . . 206 x 140 x IS (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 4 x 4 mils
Metalization .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . - Vs
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride

NOTES
IE = Ceramic Leadless Chip Carrier; Z = Ceramic Leaded Chip Carrier.
For outline information see Package Information section.
'For specifications, refer to Analog Devices Military Products Databook.

4-42 VIDEO AID CONVERTERS

REV. A

AD9060

NC

NC
LSBslNVERT
NC

+VSENSE

+VREF

ENCODE
ENCODE

-VSENSE
-VREF

+V.

NC

-Vs

AD9060
TOP VIEW
(Not to scale)

GND
GND
(LSB) Do

0,
0,
0,
D.

-v.
GND
GND

OVERFLOW

D,(MSB)

0,
0,
D.
0,

NC
GND

•

GND

NC

NC

AD9060 Pin Designations

AD9060 PIN DESCRIPTIONS
Pin No.

Name

Midpoint of internal reference ladder.

2, 16, 28, 29, 35,
41,42, 54,64

Negative supply voltage; nominally -5.2 V ±5%.

3,6, 15, 30, 33, 34,
37,40,65,68

Positive supply voltage; nominally +5 V ±5%.

4,5, 17, 18,25,27,
31, 32, 36, 38, 39, 43,
45, 52, 53, 66, 67

GROUND

All ground pins should be connected together and to lowimpedance ground plane.

7

3/4REF

Three-quarter point of internal reference ladder.

8,9

ANALOG IN

Analog input; nominaJly between ±1.75 V.

+VSENSE

Voltage sense line to most positive point on internal resistor
ladder. Normally + 1.75 V.

11

12

Voltage force connection for top of internal reference ladder.
Normally driven to provide + 1. 75 V at + VSENSE'

13

ENCODE

Differential ECL convert signal which starts digitizing process.

14

ENCODE

ECL-compatible convert command used to begin digitizing
process.

19-23, 46-50

Do-D.

ECL-compatible digital output data.

51

OVERFLOW

56

-VREF

57

-VSENSE

ECL-compatible output indicating ANALOG IN >
+VSENSE'
Voltage force connection for bottom of internal reference
ladder. Normally driven to provide -1.75 Vat -VSENSE'
Voltage sense line to most negative point on internal resistor
ladder. NoimaIly -1.75 V.

59

LSBs INVERT

Normally grounded. When connected to + V5' lower order
bits (00-08 ) are inverted. Not ECL-compatible.

61

MSBINVERT

Normally grounded. When connected to + V5' most
significant bit (MSB; D.) is inverted. Not ECL-compatible.

63

REV. A

FUDction

1

One-quarter point of internal reference ladder.
VIDEO AID CONVERTERS 4-43

AD9060
MIL-STD-883 Compliance Information
The AD9060 devices are classified within Microcircuits Group
57, Technology Group D (bipolar AID converters) and are constructed in accordance with MIL-STD-883. The AD9060 is
electrostatic sensitive and falls within electrostatic sensitivity
classification Class I. Percent Defective Allowance (PDA) is
computed based on Subgroup 1 of the specified Group A test
list. Quality Assurance (QA) screening is in accordance with
Alternate Method A of Method 5005.
The following apply: Burn-In per 1015; Life Test per 1005;
Electrical Testing per 5004. (Note: Group A electrical testing
assumes TA = Tc = TJ') MIL-STD-883-compliant devices are
marked with "c" to indicate compliance.

+S.ov

AD2
AD3
+2Vo-----('
-2Vo-----{:

STATIC: ADl =-2V; AD 2= ECl HIGH'-...:.....t~::::"T'"_ _ _ _ _ _- - '
AD3 =ECl lOW
T"
DYNAMIC: ADl ±2V TRIANGLE WAVE
ADZ,AD3 =ECl PULSE TRAIN
-S.2V

=

AD9060 Burn-In Connections

THEORY OF OPERATION
Refer to the AD9060 block diagram. As shown, the AD9060
uses a modified "flash," or parallel, ND architecture. The analog input range is determined by an external voltage reference
(+VREF and -VREF), nominally ± 1.75 V. An internal resistor
ladder divides this reference into 512 steps, each representing
rwo quantization levels. Taps along the resistor ladder (1I4REF'
112REF and 3/4REF) are provided to optimize linearity. Rated
performance is achieved by driving these points at 114, 112 and
3/4, respectively, of the voltage reference range.
The ND conversion for the nine most significant bits (MSBs) is
performed by 512 comparators. The value of the least significant
bit (LSB) is determined by a unique interpolation scheme
berween adjacent comparators. The decoding logic processes the
comparator outputs and provides a 10-bit code to the output
stage of the converter.
Flash architecture has an advantage over other ND architectures
because con version occurs in one step. This means the performance of the converter is limited primarily by the speed and
matching of the individual comparators. In the AD9060, an
innovative interpolation scheme takes advantage of flash architecture but minimizes the input capacitance, power and device
count usually associated with that method of conversion.
These advantages occur because of using only half the normal
number of input comparator cells to accomplish the conversion.
In addition, a proprietary decoding scheme minimizes error
codes. Input control pins allow the user to select from among
Binary, Inverted Binary, Twos Complement and Inverted Twos
Complement coding (See AD9060 Truth Table).

4-44 VIDEO AID CONVERTERS

APPLICATIONS
Many of the specifications used to describe analog/digital converters have evolved from system performance requirements in
these applications. Different systems emphasize particular specifications, depending on how the part is used. The following
applications highlight some of the specifications and features
that make the AD9060 attractive in these systems.
Wide band Receivers
Radar and communication receivers (baseband and direct IF
digitization), ultrasound medical imaging, signal intelligence and
spectral analysis all place stringent ac performance requirements
on analog-to-digital converters (ADCs). Frequency domain characterization of the AD9060 provides signal-to-noise ratio (SNR)
and harmonic distortion data to simplify selection of the ADC.
Receiver sensitivity is limited by the Signal-to-Noise Ratio
(SNR) of the system. The SNR for an ADC is measured in the
frequency domain and calculated with a Fast Fourier Transform
(FFT). The SNR equals the ratio of the fundamental component of the signal (rms amplitude) to the rms value of the
"noise." The noise is the sum of all other spectral components,
including harmonic distortion, but excluding dc.
Good receiver design minimizes the level of spurious signals in
the system. Spurious signals developed in the ADC are the
result of imperfections in the device transfer function (nonlinearities, delay mismatch, varying input impedance, etc.). In
the ADC, these spurious signals appear as Hannonic Distortion.
Harmonic Distortion is also measured with an FFT and is specified as the ratio of the fundamental component of the signal
(rms amplitude) to the rms value of the worst case harmonic
(usually the 2nd or 3rd).

REV. A

AD9060
Two-Tone Inrermodulation Distortion (IMD) is a frequently cited
specification in receiver design. In narrow-band receivers, thirdorder IMD products result in spurious signals in the pass band
of the receiver. Like mixers and amplifiers, the ADC is characterized with two, equal-amplitude, pure input frequencies. The
IMD equals the ratio of the power of either of the two input
signals to the power of the strongest third-order IMD signal.
Unlike mixers and amplifiers, the IMD does not always behave
as it does in linear devices (reduced input levels do not result in
predictable reductions in IMD).
Performance graphs provide typical harmonic and SNR data for
the AD9060 for increasing analog input frequencies. In choosing
an AID converter, always look at the dynamic range for the analog input frequency of interest. The AD9060 specifications provide guaranteed minimum limits at three analog test frequencies.

Aperture Delay is the delay between the rising edge of the
ENCODE command and the instant at which the analog input
is sampled. Many systems require simultaneous sampling of
more than one analog input signal with multiple ADCs. In these
situations, timing is critical and the absolute value of the aperture delay is not as critical as the matching between devices.
Aperture Uncertainty, or jitter, is the sample-to-sample variation
in aperture delay. This is especially important when sampling
high slew rate signals in wide bandwidth systems. Aperture
uncertainty is one of the factors which degrades dynamic performance as the analog input frequency is increased.
Digitizing Oscilloscopes
Oscilloscopes provide amplitude information about an observed
waveform with respect to time. Digitizing oscilloscopes must
accurately sample this signal, without distorting the information
to be displayed.
One figure of merit for the ADC in these applications is Effective Number of Bits (ENOBs). ENOB is calculated with a sine
wave curve fit and equals:
ENOB

=N-

LOG2 [Error (measured)/Error (ideal)]

N is the resolution (number of bits) of the ADC. The measured
error is the actual rms error calculated from the converter outputs with a pure sine wave input.
The Analog Bandwidth of the converter is the analog input frequency at which the spectral power of the fundamental signal is
reduced 3 dB from its low frequency value. The analog bandwidth is a good indicator of a converter's slewing capabilities.
The Maximum Conversion Rate is defined as the encode rate at
which the SNR for the lowest analog signal test frequency tested
drops by no more than 3 dB below the guaranteed limit.

REV. A

Imaging
Visible and infrared imaging systems both require similar characteristics from ADCs. The signal input (from a CCD camera,
or multiplexer) is a time division multiplexed signal consisting of
a series of pulses whose amplitude varies in direct proportion to
the intensity of the radiation detected at the sensor. These varying levels are then digitized by applying encode commands at
the correct times, as shown below.

+FS

-FS -

-~

------1
!
,

!!
I

I

~

!
,

ENCODE~
Imaging Application Using AD9060

The actual resolution of the converter is limited by the thermal
and quantization noise of the ADC. The low frequency test for
SNR or ENOB is a good measure of the noise of the AD9060.
At this frequency, the static errors in the ADC determine the
useful dynamic range of the ADC.
Although the signal being sampled does not have a significant
slew rate, this does not imply dynamic performance is not
important. The Transient Response and Overvoltage Recovery
Time specifications insure that the ADC can track full-scale
changes in the analog input sufficiently fast to capture a valid
sample.

Transient Response is the time required for the AD9060 to
achieve full accuracy when a step function is applied. Overvoltage Recovery Time is the time required for the AD9060 to
recover to full accuracy after an analog input signal 150% of full
scale is reduced to the full-scale range of the converter.
Professional Video
Digital Signal Processing (DSP) is now common in television
production. Modern studios rely on digitized video to create
state-of-the-art special effects. Video instrumentation also
requires high resolution ADCs for studio quality measurement
and frame storage.
The AD9060 provides sufficient resolution for these demanding
applications. Conversion speed, dynamic performance and analog bandwidth are suitable for digitizing both composite and
RGB video sources.

VIDEO AID CONVERTERS 4-45

•

AD9060
USING THE AD9060
Voltage References
The AD9060 requires that the user provide two voltage references: +VREP and -VREP.These two voltages are applied
across an internal resistor ladder (nominally 37 0) and set the
analog input voltage range of the convener. The voltage references should be driven from a stable, low impedance source. In
addition to these two references, three evenly spaced taps on the
resistor ladder (1I4REP ' 1/2REP ' 3/4REP ) are available. Providing
a reference to these quarter points on the resistor ladder will
improve the integral linearity of the converter and improve ac
performance. (AC and dc specifications are tested while driving
the quarter points at the indicated levels.) The figure below is
not intended to show the transfer characteristic of the ADC, but
illustrates how the linearity of the device is affected by reference
voltages applied to the ladder.
1111111111

The select resistors (Rs) shown in the schematic (each pair can
be a potentiometer) are chosen to adjust the quarter-point voltage references, but are not necessary if RI-R4 match within
0.05%.
10.0

62

56
III

'D

V V

I

i<
z
Ie 50
w

8z
g
.:.

.

~

--

e--

ii!

~

38

r----,----,----r--~

~

OA

0.6

0.8

1.0

1.2

tYSENSE -

1.4

1.6

1.8

~

2.0

von.

1100000000 1----+---+--""7"-"~~-_t

AD9060 SNR and ENOB vs. Reference Voltage

0100000000

i--+--:;tf'----

ooooooooooL-----~----~------~----~
-VSENSE
1/41U!F
112REF
3141&"
+V8eNBE

Effect of Reference Taps on Linearity
Resistance between the reference connections and the taps of the
first and last comparators causes offset errors. These errors,
called "top and bottom of the ladder offsets," can be nulled by
using the voltage sense lines, + V SENSE and - VSENSE' to adjust
the reference voltages. Current through the sense lines should be
limited to less than 100 ILA. Excessive current drawn through
the voltage sense lines will affect the accuracy of the sense line
voltage.
The next page shows a reference circuit which nulls out the offset errors using two op amps and provides appropriate voltage
references to the quarter-point taps. Feedback from the sense
lines causes the op amps to compensate for the offset errors.
The two transistors limit the amount of current drawn directly
from the op amps; resistors at the base connections stabilize
their operation. The 10 kG resistors (RI-R4) between the voltage sense lines form an external resistor ladder; the quarter
point voltages are taken off this external ladder and buffered by
an op amp. The actual values of resistors RI-R4 are not critical,
but they should match well and be large enough (2:10 kG) to
limit the amount of current drawn from the voltage sense lines.

4-46 VIDEO AID CONVERTERS

An alternative approach for defming the quarter-point references
of the resistor ladder is to evaluate the integral linearity error of
an individual device, and adjust the voltage at the quarter-points
to minimize this error. This may improve the low frequency ac
performance of the converter.
Performance of the AD9060 has been optimized with an analog
input voltage of ± 1.75 V (as measured at ± VSENSE)' If the analog input range is reduced below these values, relatively larger
differential nonlinearity errors may result because of comparator
mismatches. As shown in the figure below, performance of the
converter is a function of ± VSENSE'
Applying a voltage greater than 4 V across the internal resistor
ladder will cause current densities to exceed rated values, and
may cause permanent damage to the AD9060. The design of
the reference circuit should limit the voltage available to the
references.
Analog Input Signal
The signal applied to ANALOG IN drives the inputs of 512
parallel comparator cells (see Equivalent Analog Input figure).
This connection typically has an input resistance of 7 kG, and
input capacitance of 45 pF. The input capacitance is nearly constant over the analog input voltage range, as shown in the graph
which illustrates that characteristic.
The analog input signal should be driven from a low distortion,
low noise amplifier. A good choice is the AD9617, a wide bandwidth, monolithic operational amplifier with excellent ac and dc
performance. The input capacitance should be isolated by a
small series resistor (24 G for the AD9617) to improve the ac
performance of the amplifier (see AD9060/PCB Evaluation
Board Block Diagram).

REV. A

AD9060
ANALOG INPUT

.,

10kU

.2

.2

-Yu..,

AD9060 Equivalent Analog Input

20JHJ

GROUND~
201tll

~
I

I

DIGITAL BITS
AND OVERFLOW

AD9060 Equivalent Digital Outputs
AD9060 Reference Circuit

GROUND

AD9060 Encode and Encode
Equivalent Circuits

REV. A

VIDEO AID CONVERTERS 4-47

AD9060
ANALOG _ _-.N,-INPUT

-1~I'

ENCciiiE ----,;,'r - - -.....
N

ENCODE

\.. ______ .1 '--_ _-.J

-tloo r-

-4r-------~Xr-----

DATA
OUTPUT - - - "

DATA FOR N

DATA FOR N + 1

I. - Aperture Delay
tOD - OUlput Delay

AD9060 Timing Diagram

Timing
In the AD9060, the rising edge of the ENCODE signal triggers
the AJD conversion by latching the comparators. (See the
AD9060 Timing Diagram.) These ENCODE and ENCODE
signals are ECL compatible and should be driven differentially.
Jitter on the ENCODE signal will raise the noise floor of the
converter. Differential signals, with fast clean edges, will reduce
the jitter in the signal, and allow optimum ac performance. In
applications with a fixed, high frequency encode rate, converter
performance is also improved (jitter reduced) by using a crystal
oscillator as the system clock.
The AD9060 units are designed to operate with a 50% duty cycle encode signal; adjustment of the duty cycle may improve the
dynamic performance of individual devices. Since the ENCODE
and ENCODE signals are differential, the logic levels are not
critical. Users should remember, however, that reduced logic
levels will reduce the slew rate of the edges, and effectively increase the jitter of the signal. ECL terminations for the ENCODE and ENCODE signals should be as close as possible to
the AD9060 package to avoid reflections.
In systems where only single-ended signals are available, the use
of a high speed comparator (such as the AD96685) is recommended to convert to differential signals. An alternative is to
connect + 1.3 V (ECL midpoint) to ENCODE and drive the
ENCODE connection single ended. In such applications, clean,
fast edges are necessary to minimize jitter in the signal.
Output data of the AD9060, Do-D9 and OVERFLOW, are also
ECL compatible, and should be terminated through 100 n to
-2 V (or an equivalent load).
Data Format
The format of the output data (Do-D9) is controlled by the
MSB INVERT and LSBs INVERT pins. These inputs are dc
control inputs, and should be connected to GROUND or + Vs.
The AD9060 Truth Table gives information to choose from
among Binary, Inverted Binary, Twos Complement and Inverted Twos Complement coding.
The OVERFLOW output is an indication that the analog input
signal has exceeded the voltage at + VSENSE' The accuracy of
the overflow transition voltage and output delay are not tested

4-48 VIDEO AID CONVERTERS

or included in the data sheet limits. Performance of the overflow
indicator is dependent on circuit layout and slew rate of the encode signal. The operation of this function does not affect the
other data bits (Do-D9). It is not recommended for applications
requiring a critical measure of analog input voltage.
Layout and Power Supplies
Proper layout of high speed circuits is always critical but is particularly important when both analog and digital signals are
involved.
Analog signal paths should be kept as short as possible and be
properly terminated to avoid reflections. The analog input voltage and the voltage references should be kept away from digital
signal paths; this reduces the amount of digital switching noise
that is capacitively coupled into the analog section of the circuit.
Digital signal paths should also be kept short, and run lengths
should be matched to avoid propagation delay mismatch. Terminations for ECL signals should be as close as possible to the receiving gate.
In high speed circuits, layout of the ground circuit is a critical
factor. A single, low impedance ground plane, on the component side of the board, will reduce noise on the circuit ground.
Power supplies should be capacitively coupled to the ground
plane to reduce noise in the circuit. Multilayer boards allow designers to layout signal traces without interrupting the ground
plane and provide low impedance power planes.
It is especially important to maintain the continuity of the
ground plane under and around the AD9060. In systems with
dedicated digital and analog grounds, all grounds of the AD9060
should be connected to the analog ground plane.
The power supplies ( + Vs and - V,) of the AD9060 should
be isolated from the supplies used for external devices; this
further reduces the amount of noise coupled into the AID converter. Sockets limit the dynamic performance and should be
used only for prototypes or evaluation - PCK Elastomerics
Part No. CCS-68-55 is recommended for the LCC package.
(Tel. 215-672-0787)
An evaluation board is available to aid designers and provide a
suggested layout.

REV. A

AD9060
62

-

56

!l!I

-::::

5.

0.0

9.•

~

(44

!:

~

-55"C '+125"'<: / \

I

~

l

6 810

20

40

ul

60

4.0

60 100

65

v.........

+2r

7' .~::'+'--+-+-+----1--4-+-+-1

M'~~~--4L-~6-8~'.~-2O~--~~~60~~'OO

200

INPUT FREQUENCY - MHz

AD9060 SNR and ENOB vs. Input Frequency

AD9060 Harmonics vs. Input Frequency

,•..

62

-

..•

ANALOG INPUT = 2.3MHz

'\

~
z

8.• !!!

'1;,48

~

ID

~

IU

ID

::>

z

~

20

60

80

>

\I;

!i

$

'00

....... ........

02
01
00

True

= "0"
= "0"

0=-1.75V
FS
+1.75 V

MSBINV
LSBs INV

. IJ

!;

20\1;

,
-1.2

-0.6

0

.1.2

.0.6

+1.8

>+1.7500
+1.7466
+ 1.7432

(1) 1111111111

Twos Complement

Inverted

True

= "I"
= "0"

Inverted

MSBINV = "I"
LSBs INV = "I"

MSBINV
LSBs INV

1111111111
1111 III 110

(1 )0000000000
0000000000
0000000001

(1)0 111111111
0111111111
0111111110

(1)1000000000
1000000000
1000000001

+0.0034
0.000
-0.0034

1000000000
0111111111
0111111110

0111111111
1000000000
1000000001

OOOOOOOOOO
1111111111
1111lI1110

1ll111ll11
0000000000
0000000001

-1.7432
-1.7466
<-1.7466

0000000010
0000000001

111111lI01
1111 III 110
1111111111

1000000010
1000000001
1000000000

01l11lI101
0111111110
0111111111

=

512
511
510

/

Input Capacitance/Resistance vs. Input Voltage

Offset Binary

1024
1023
1022

..

3Oi!i

........ ........

ANALOG INPUT 1Au. ) - Yolts

AD9060 SNR and ENOB vs. Conversion Rate

Range

I

~~
V ~

t"-

CONVERSION RATE - USPS

Step

50~

CAPACITANCE

45

-1.8

60

1-

47

!;

IU

4 .•

_. .

RESISTANCE

5 r§46

6.• :II

26

r-

,.

I
IU

.

5.•

7

I

9.•

7 .• IL
0

20,.

'/./;

Z

INPUT FREQUENCY - MHz

56

1/

+'HOC

-55"C

so

6.• _

1\
4

--,- t-

4.

IL

7.0 0

\1\

,

I

8.• ~

/+25"C

26

20

,

ENCO~E RA~ =160~lpS

OOOOOOOOOO

MSBINV = "0"
LSBs INV "I"

=

The overflow bit is always 0 except where noted in psrenthes.. ( ). MSD INVERT and LSD. INVERT are considered de controls.

AD9060 Truth Table

REV. A

VIDEO AID CONVERTERS 4-49

•

AD9060
DAC
OUT

-SV

+SV

AD97120AC
-Vs

+Vs

GND

MSS INVERT
LSBslNVERT

A09060
OUT

TO ERROR
WAVEFORM
CIRCUIT

~EFERENCE

CIRCUIT

SV

(LSB)D.

D

D,
D,
D,

D

D.

D,
D,
D,

D

:r--o+
D
D
D
D
D

0

OUTPUT
DATA

1------,1'1 CONNECTOR

ECL
LATCHES
DATA
READY

D

D,

D

3f4 Uf

(MSB)D,

1/2A£F

OVERFLOW

D
D

CLK

1-----,

1/4REF

-V.....

-V"EF

ENCODE~----fo+---~--~--'
DIFFERENTIAL
ECLCLOCK

TIllING
CIRCUIT

ENCODE~----+O+---~

AD9060lPCB Evaluation Board Block Diagram

AD9060IPCB EVALUATION BOARD
The AD9060IPCB Evaluation Board is avaiiable from the factory
and is shown here in block diagram form. The board includes a
reference circuit that allows 'the user to adjust both references
and the quarter-point voltages. The AD%17 is included as the
drive amplifier, and the user can configure the gain from -1
to -IS.

4-50

VIDEO AID CONVERTERS

On-board reconstruction of the digital data is provided through
the AD9712, a l2-bit monolithic DAC. The analog and reconstructed waveforms can be summed on the board to allow the
user to observe the linearity of the AD9060 and the effects of
the quarter-point voltages. The digital data and an adjustable
Data Ready signal are available via a 37-pin edge connector.

REV. A

Audio OJA Converters
Contents
Page

Audio D/A Converters - Section 5 .............................................. 5-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
ADlS511ADlS61 - 16-BitlIS-Bit 16 x Fs PCM Audio DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
ADlS56 - 16-Bit PCM Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
ADlS60 - IS-Bit PCM Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
ADlS62 - Ultralow Noise, 20-Bit Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
ADlS64 - Complete Dual IS-Bit Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
ADlS65 - Complete Dual IS-Bir 16 x Fs Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55
ADlS66 - Single-Supply Dual 16-Bit Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65
ADlS6S - Single-Supply Dual IS-Bit Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67

II

AUDIO DIA CONVERTERS 5-1

~
~

§
0

Selection Guide
Audio Digital-to-Analog Converters

~
l:>

8
~
~

::l:j

nt
51

Model
ADl851
ADl856
ADl860
ADl861
ADl862
ADl864
ADl865
AD1866
ADl868

Res
Bits

16
16
18
18
20
18
18
16
18

Channels
Single
Single
Single
Single
Single
Dual
Dual
Dual
Dual

SNR

TIID+N

OdB-dBtyp

%typ

110
No Spec
No Spec
110
119
108
110
95
97.5

0.003
0.002
0.002
0.003
0.0012
0.0017
0.0017
0.005
0.004

Supplies
Volts
±5
±5
±5
±5
±5
±5
±5
5
5

to ±12
to ±12
to ±12
to ±12

Power

mWtyp

Pins

Page

100
110
110
100
288
225
225
45
50

16
16
16
16
16
24/28
24/28
16
16

5-3
5-13
5-21
5-3
5-33
543
5-55
5-65
5-67

11IIIIIIII ANALOG
WDEVICES
FEATURES
110 dB SNR
Fast Settling Permits 16x Oversampling
:!:3 V Output
Optional Trim Allows Super-Linear Performance
:!:5 V Operation
16-Pin Plastic DIP and SOIC Packages
Pin-Compatible with AD1856 & AD1860 Audio DACs
2s Complement. Serial Input

16-Bit/18-Bit, 16 x Fs
PCM Audio DACs
AD1851/AD1861 I
FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS
High-End Compact Disc Players
Digital Audio Amplifiers
DAT Recorders and Players
Synthesizers and Keyboards

PRODUCT DESCRIPTION
The ADI8511ADI861 is a monolithic PCM audio DAC. The
ADI851 is a 16-bit device, while the ADI861 is an 18-bit
device. Each device provides a voltage output amplifier, DAG,
serial-to-parallel register and voltage reference. The digital
portion of the ADI8511ADI861 is fabricated with CMOS logic
elements that are provided by Analog Devices' 2 11m ABCMOS
process. The analog portion of the ADI8511ADI861 is fabricated with bipolar and MOS devices as well as thin-film
resistors.
This combination of circuit elements, as well as careful design
and layout techniques, results in high performance audio playback. Laser-trimming of the linearity error affords low total harmonic distortion. An optional linearity trim pin is provided to
allow residual differential linearity error at midscale to be eliminated. This feature is particularly valuable for low distortion
reproductions of low amplitude signals. Output glitch is also
small, contributing to the overall high level of performance. The
output amplifier achieves fast settling and high slew rates, providing a full ±3 V signal at load currents up to 8 rnA. When
used in current output mode, the ADI8511ADI861 provides a
± I rnA output signal. The output amplifier is short circuit protected and can withstand indefinite shorts to ground.
The serial input interface consists of the clock, data and latch
enable pins. The serial 2s complement 'data word is clocked into
the DAC, MSB ftrst, by the external clock. The latch enable
signal transfers the input word from the internal serial input
register to the parallel DAC input register. The ADI851 input
clock can support a 12.5 MHz data rate, while the ADI861 input clock can support a 13.5 MHz data rate. This serial input
port is compatible with second generation digital filter chips
used in consumer audio products. These filters operate at oversampling rates of 2x, 4X, 8x and 16x sampling frequencies.

The ADI8511ADI861 operates with ±5 V power supplies, making it suitable for home use markets. The digital supply, VL,
can be separated from the analog supplies, Vs and - Vs, for reduced digital crosstalk. Separate analog and digital ground pins
are also provided. Power dissipation is 100 mW typical.
The AD18511AD1861 is available in either a 16-pin plastic DIP
or a 16-pin plastic SOIC package. Both packages incorporate the
industry standard pinout found on the AD1856 and ADI860
PCM audio DACs. As a result, the AD18511AD1861 is a dropin replacement for designs where ±5 V supplies have been used
with the AD1856/ADI860. Operation is guaranteed over the
temperature range of - 25·C to + 70·C and over the voltage supply range of ±4.75 V to ±s.25 V.
PRODUCT HIGHLIGHTS
1. ADI8s1 16-bit resolution provides 96 dB dynamic range.
AD1861 18-bit resolution provides 108 dB dynamic range.
2. No external components are required.
3. Operates with ±s V supplies.
4. Space saving 16-pin SOIC and plastic DIP packages.
5. 100 mW power dissipation.
6. High input clock data rates and 1.5 I1S settling time permits
2x, 4x, 8x and 16x oversampling.
7. ±3 V or ±I mA output capability.
8. THD + Noise and SNR are 100% tested.
9. Pin-compatible with ADI856 & ADl860 PCM audio DACs.

The critical specifications of THD+ N and signal-to-noise ratio
are 100% tested for all devices.

REV. A

AUDIO DIA CONVERTERS ~3

II

AD1851/AD1861-SPECIFICATIONS (T

A@

Min
DIGITAL INPUTS
VIH
VIL
IIH' VIH = VL
IlL> V1L = 0.4

+25°C and ±5 V supplies. unless otherwise noted)

Typ

2.0

Max

Units

+VL
0.8

V
V
I1A
I1A

1.0
-10

ACCURACY
Gain Error
Midscale Output Voltage

±I
±1O

%
mV

DRiFf WC to + 70°C)
Total Drift
Bipolar Zero Drift

±25
±4

ppm of FSRI"C
ppm of FSRf'C

1.5
1.0
9

I1S
I1S
V/l1s

350
350

ns
ns

SETTLING TIME (To ±0.0015% of FSR)
Voltage Output
6 V Step
I LSB Step
Slew Rate
Current Output
I rnA Step 10 fl to 100 fl Load
I kfl Load
OUTPUT
Voltage Output Configuration
Bipolar Range
Output Current
Output Impedance
Short Circuit Duration
Current Output Configuration
Bipolar Range (± 30%)
Output Impedance (±30%)
POWER SUPPLY
Voltage
+VL and +Vs
-Vs

:t2.88
±8

±3.12

±3.0
0.1
Indefmite to Common

fl

±1.0
1.7

4.75
-5.25

TEMPERATURE RANGE
Specification
Operation
Storage

0
-25

WARMUP TIME

I

-60

V
rnA

+25

rnA

kfl

5.25
-4.75

V
V

+70
+70
+100

°C
°C
°C
min

Spectficattons subJect to change without notice.

NC =NO CONNECT

AD1851 Functional Block Diagram

5-4 AUDIO DIA CONVERTERS

NC =NO CONNECT

AD1861 Functional Block Diagram

REV. A

AD1851/AD1861
AD1851
Min

Typ

Max

Units

16

Bits

0.003
0.004

0.004
0.008

%
%

0.009
0.009

0.016
0.040

%
%

0.9
0.9

1.6
4.0

%
%

RESOLUTION
TOTAL HARMONIC DISTORTION + NOISE
odB, 990.5 Hz
AD185IN-J, R-J
ADt85IN, R
-20 dB, 990.5 Hz
ADI85IN-J, R-J
ADt85IN, R
-60 dB, 990.5 Hz
AD185IN-J, R-J
ADt85IN, R
D-RANGE* (With A-Weight Filter)
-60 dB, 990.5 Hz AD185IN, R
AD185IN-J, R-J

88
96

SIGNAL-TO-NOISE RATIO

107

MAXIMUM CLOCK INPUT FREQUENCY

12.5

dB
dB
110

dB
MHz

ACCURACY
Differential Linearity Error

±O.OOI

% ofFSR

MONOTONICITY

14

Bits

POWER SUPPLY
Current
+1
-I
Power Dissipation

10.0
-10.0
100

13.0
-15.0

Typ

Max

Units

18

Bits

0.003
0.004

0.004
0.008

%
%

0.009
0.009

0.016
0.040

%
%

0.9
0.9

1.6
4.0

%
%

rnA
rnA

mW

AD1861
Min
RESOLUTION
TOTAL HARMONIC DISTORTION + NOISE
o dB, 990.5 Hz
AD1861N-J, R-J
AD186IN, R
-20 dB, 990.5 Hz
AD1861N-J, R-J
AD186IN, R
-60 dB, 990.5 Hz
AD186IN-J, R-J
AD186IN, R
D-RANGE* (With A-Weight Filter)
-60 dB, 990.5 Hz AD186IN, R
ADI86IN-J, R-J

88
96

SIGNAL-TO-NOISE RATIO

107

MAXIMUM CLOCK INPUT FREQUENCY

13.5

dB
dB
110

dB
MHz

ACCURACY
Differential Linearity Error

±0.001

% ofFSR

MONOTONICITY

15

Bits

POWER SUPPLY
Current
+1
-I
Power Dissipation

10.0
-10.0
100

13.0
-15.0

rnA
rnA

mW

'Tested in accordance with EIAJ Test Standard CP-307.
Specifications subject to change without notice.

REV. A

AUDIO DIA CONVERTERS 5-5

•

AD1851/AD1861
PIN ASSIGNMENTS

ABSOLUTE MAXIMUM RATINGS·
VL to DGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.50 V
Vs to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.50 V
-Vs to AGND . . . . . . . . . . . . . . . . . . . . . -6.50 V to 0 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . -0.3 V to VL
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Short Circuit . . . . . . . . . . . . . . . Indefmite Short to Ground
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . + 300°C, 10 sec
Storage Temperature . . . . . . . . . . . . . . . . . -60°C to + 100°C
"Stresses greater than those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a Slress rating only and
fum;tional operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affcct device reliability.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

. ANALOG NEGATIVE POWER SUPPLY
LOGIC GROUND
LOGIC POSITIVE POWER SUPPLY
NO CONNECTION
CLOCK INPUT
LATCH ENABLE INPUT
SERIAL DATA INPUT
NO INTERNAL CONNECTION"
V OUT
VOLTAGE OUTPUT
FEEDBACK RESISTOR
R.
SJ
SUMMING JUNCTION
ANALOG GROUND
AGND
CURRENT OUTPUT
lOUT
MSBADJ MSB ADJUSTMENT TERMINAL
TRIM
MSB TRIMMING POTENTIOMETER TERMINAL
ANALOG POSITIVE POWER SUPPLY
Vs
-Vs
DGND
VL
NC
CLK
LE
DATA
NC

·PIN 8 HAS NO INTERNAL CONNECTION; -V, FROM AD1856 OR AD1860
SOCKET CAN BE SAFELY APPLIED.

CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted.

c:J

WARNING!

~~EDEVICE

ORDERING GUIDE
Model

Resolution

THD+N

Package
Option·

ADl851N
ADI851N-J
ADl851R
ADl85IR-J
ADI861N
ADl86IN-J
AD1861R
ADl861R-J

16 Bits
16 Bits
16 Bits
16 Bits
18 Bits
18 Bits
18 Bits
18 Bits

0.008%
0.004%
0.008%
0.004%
0.008%
0.004%
0.008%
0.004%

N-16
N-16
R-I6A
R-I6A
N-16
N-16
R-16A
R-l6A

"N = Plastic DIP Package; R = Small Outline (SOIC) Package.
For outline information see Package Information section.

Typical Performance
10
175

-

150

-IOdB

125

~I

100

2

,,/

75

.01

50

~B

--

25

...

OdB
.001

10

.2

14

CLOCK FREQUENCY - MHz

Power Dissipation vs. Clock Frequency

~6

AUDIO DIA CONVERTERS

-30 -20 -10

0

10

20 30 40 50
TEMPERATURE _ °C

80

70

80 80

THD vs. Temperature

REV. A

AD1851/AD1861
TOTAL HARMONIC DISTORTION
Total harmonic distortion plus noise (THD+ N) is defined as
the ratio of the square root of the sum of the squares of the values of the first 19 harmonics and noise to the value of the fundamental input frequency. It is usually expressed in percent
(%).

THD+ N is a measure of the magnitude and distribution of linearity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depending on the amplitude of the output signal. Therefore, to be most
useful, THD+N should be specified for both large (0 dB) and
small signal amplitudes (-20 dB and -60 dB).
The THD+ N figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. This specification, therefore, provides a
direct method to classify and choose an audio DAC for a desired
level of performance.
SETTLING TIME
Settling time is the time required for the output of the DAC to
reach and remain within a specified error band about its final
value, measured from the digital input transition. It is a primary
measure of dynamic performance.
MIDSCALE ERROR
Midscale error, or bipolar zero error, is the deviation of the actual analog output from the ideal output (0 V) when the 2s complement input code representing half scale is loaded in the input
register.
D-RANGE DISTORTION
D-range distortion is equal to the value of the total harmonic
distortion + noise (THD+N) plus 60 dB when a signal level of
-60 dB below full scale is reproduced. D-range is tested with a
1 kHz input sine wave. This is measured with a standard Aweight filter as specified by EIAJ Standard CP-307.
SIGNAL-TO-NOISE RATIO
The signal-to-noise ratio (SNR) is defined as the ratio of the amplitude of the output when a full-scale output is present to the
amplitude of the output with no signal present. This is measured with a standard A-weight filter as specified by EIAJ
.
.
Standard CP-307.

REV. A

SERIAL-TO-PARALLEL
CONVERSION

Figure 1. AD18511AD1861 Functional Block Diagram

FUNCTIONAL DESCRIPTION
The AD18SlIAD1861 is a complete monolithic PCM audio
DAC. No additional external components are required for operation. As shown in Figure I above, each chip contains a voltage
reference, an output amplifier, a DAC, an input latch and a parallel input register.
The voltage reference consists of a bandgap circuit and buffer
amplifier. This combination of elements produces a reference
voltage that is unaffected by changes in temperature and age.
The DAC output voltage, which is derived from the reference
voltage, is also unaffected by these environmental changes.
The output amplifier uses both MOS and bipolar devices to produce low offset, high slew rate and optimum settling time.
When combined with the on-chip feedback resistor, the output
op amp converts the output current of the AD18SlIAD1861 to a
voltage output.
The DAC uses a combination of segmented decoder and R-2R
architecture to achieve consistent linearity and differential
linearity. The resistors which form the ladder structure are fabricated with silicon chromium thin film. Laser-trimming of
these resistors further reduces linearity error, resulting in low
output distortion.
The input register and serial-to-parallel converter are fabricated with CMOS logic gates. These gates allow the achievement
of fast switching speeds and low power consumption. This
contributes to the overall low power dissipation of the
ADl8SlIADl861.

AUDIO DIA CONVERTERS 5-7

5

AD1851/AD1861
Analog Circuit Considerations
GROUNDING RECOMMENDATIONS
The ADI8511ADI861has .two ground pins, designated Analog
and Digital gtound. The analog gtound pin is the "high quality" ground reference point for the device. The analog gtound
pin should be connected to the analog common point in the
system. The output load should also be connected to. that same
point.

However, three separate voltage supplies are not necessary for
good circuit performance. For example, Figure 3 illustrates a
system where only a single positive lind a single negative supply
are available.
In this example, the positive logic and positive analog supplies
must both be connected to + 5 V, while the negative analog supply will be connected to -5 V. Performance would benefit from
a measure of isolation between the supplies introduced by using
simple low pass ftIters in the individual power supply leads.

The digital ground pin returns ground {;urrent from the digital
logic portions of the ADI8511ADI861 circuitry. This pin should
be connected to the digital common point in the system.
As illustrated in Figure 2, the analog and digital grounds should
be connected together at one point in the system.
+5V

+5V

Figure 3. Alternate Recommended Schematic

-5V

Figure 2. Recommended Circuit Schematic

POWER SUPPLIES AND DECOUPLING
The AD1851/AD1861 has three power supply input pins. The
± V s supplies provide the supply voltliges to operate the linear
portions of the DAC including the voltage reference, output amplifier and control amplifier. The ± Vs supplies are designed to
operate at ± 5 V.
The + VL supply operates the digital portions of the chip including the input shift register and the input latching circuitry. The
+VL supply is designed to operate at +5 V.
Decoupling capacitors should be used on all power supply pins.
Furthermore, good engineering practice suggests that these capacitors be placed as close as possible to the package pins as
well as to the common points. The logic supply, +Vu should
be decoupled to digital common, while the analog supplies,
± Vs, should be decoupled to analog common.
The use of three separate power supplies will reduce feedthrough from the digital portion of the system to the linear portion of the system, thus contributing to improved performance.

As with most linear circuits, changes in the power supplies will
affecf the output of the DAC. Analog Devices recommends that
well regulated power supplies with less than 1% ripple be incorporated into the design of any system using the AD 18511
AD1861.

OPTIONAL MSB ADJUSTMENT
Use of an optional adjustment circuit allows residual differential
linearity error around midscale to be eliminated. This error is
especially important when low amplitUde signals are being reproduced. In those cases, as the signal amplitude decreases, the
ratio of the midscale differential linearity error to the signal amplitude increases, thereby increasing THD.
Therefore, for best performance at low output levels, the optional MSB adjust circuitry shown in Figure 4 may be used to
improve performance. The adjustment should be made with a
small signal input (---'20 dB or -60 dB).

T~
~

MSB
ADJUST

Figure 4. Optional THD Adjust Circuit

~8

AUDIO DIA CONVERTERS

REV. A

AD1851/AD1861
AD1851 DIGITAL CIRCUIT CONSIDERATIONS
AD1851 Input Data

AD1861 DIGITAL CIRCUIT CONSIDERATIONS
AD1861 Input Data

Data is transmitted to the AD 1851 in a bit stream composed of
16-bit words with a serial, MSB first format. Three signals must
be present to achieve proper operation. They are the Data,
Clock and Latch Enable (LE) signals. Input data bits are
clocked into the input register on the rising edge of the Clock
signal. The LSB is clocked in on the 16th clock pulse. When all
data bits are loaded, a low-going Latch Enable pulse updates the
DAC input. Figure 5 illustrates the general signal requirements
for data transfer to the AD 1851.

Data is transmitted to the AD1861 in a bit stream composed of
18-bit words with a serial, MSB first format. Three signals must
be present to achieve proper operation. They are the Data,
Clock and Latch Enable (LE) signals. Input data bits are
clocked into the input register on the rising edge of the Clock
signal. The LSB is clocked in on the 18th clock pulse. When all
data bits are loaded, a low-going Latch Enable pulse updates the
DAC input. Figure 7 illustrates the general signal requirements
for data transfer to the AD 1861.

CLOCK
DATA

CLOCK

~'UU'LJ'LJ'LJ'LJ'LJ'.

/\

LATCH~r
Figure 5. Signal Requirements for AD1851
Figure 6 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished properly. The input pins of the AD1851 are both TTL and 5 V
CMOS compatible. The input requirements illustrated in Figures 5 and 6 are compatible with data outputs provided by popular DSP filter chips used in digital audio playback systems.
The AD1851 input clock can run at a 12.5 MHz rate. This
clock rate will allow data transfer rates for 2 x, 4 x or 8 x or
16x oversampling reconstructions.

DATA

LATCH~r
Figure 7. Signal Requirements for AD1861
Figure 8 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished properly. The input pins of the AD1861 are both TTL and 5 V
CMOS compatible. The input requirements illustrated in Figures 7 and 8 are compatible with data outputs provided by popular DSP filter chips used in digital audio playback systems.
The AD1861 input clock can run at a 13.5 MHz rate. This
clock rate will allow data transfer rates for 2 x, 4x or 8 x or
16x oversampling reconstructions.

.7'"

.EXT
BITS CLOCkED
' -_ _ _ _...::::====~~===TOSHIFTREGIBTER

Figure 6. Timing Relationships of AD1851 Input Signals

REV. A

Figure 8. Timing Relationships of AD1861 Input Signals

AUDIO DIA CONVERTERS 5-9

•

AD1851/AD1861
APPLICATIONS
Figures 9 through 12 show connection diagrams for the AD1851
and ADl861 and the Yamaha YM3434 and the NPC
SM5813AP/APT digital ftIter chips.

ClK

Mf-O{) lATCH
DlO Q~HI--O DATA

AD1851

SCOO--+.....

YM3434

WCO
DRO

0---1--+--0 DATA
'-11--0 lATCH
ClK

AD1851

Figure 9. AD1851 with Yamaha YM3434 Digital Filter

+5V

ClK
lATCH
Xl

ST

DlO

DATA

AD1861

SCO

YM3434

wco
DRO

":"

DATA
LATCH
ClK

AD1861

Figure 10. AD1861 with Yamaha YM3434 Digital Filter

5-10 AUDIO DIA CONVERTERS

REV. A

AD1851/AD1861
ClK
~~-oLATCH

DOL
BCKO

o----tHI--Q DATA

AD1851

o--f....

SM5813AP/APT
WCKO
DOR

o----tHI--Q
L-j~-O

DATA
LATCH
ClK

+5V

AD1851

Figure 11. AD1851 with NPC SM5813APIAPT Digital Filter

•

ClK

r-Ir--o lATCH
DOL ()O--lH~-O DATA
BCKO

AD1861

0--+...

SM5813AP/APT
WCKO
DCR

o--IH--O DATA
~+--()

LATCH
ClK

AD1861

Figure 12. AD1861 with NPC SM5813APIAPT Digital Filter

REV. A

AUDIO DIA CONVERTERS 5-11

~12

AUDIO DIA CONVERTERS

16-Bit
PCM Audio DAC
AD1856 I

~ANALOG

WDEVICES

BLOCK DIAGRAM

FEATURES
0.0025% THD
Fast Settling Permits 2x, 4x or 8x Oversampling
:!:3V Output
Optional Trim Allows Superlinear Performance
:!:5V to :!:12V Operation
16-Pin Plastic DIP or SOIC Package
Serial Input
APPLICATIONS
Compact Disc Players
Digital Audio Amplifiers
DAT Recorders and Players
Synthesizers and Keyboards

PRODUCT DESCRIPTION
The AD1856 is a monolithic 16-bit PCM Audio DAC. Each device provides a voltage output amplifier, 16-bit DAC, 16-bit
serial-to-parallel input register and voltage reference. The digital
portion of the ADl856 is fabricated with CMOS logic elements
that are provided by Analog Devices' BiMOS. II process. The
analog portion of the AD1S56 is fabricated with bipolar and
MOS devices as well as thin film resistors.

The ADl856 can operate with ±5V to ± 12V power supplies
making it suitable for both the portable and home-use markets.
The digital supplies, VLand - V'-' can be separated from the
analog supplies, Vsand - Vs, for reduced digital crosstalk. Separate analog and digital ground pins are also provided.

This combination of circuit elements, as well as careful design
and layout techniques, results in high performance audio playback. Laser trimming of the linearity error affords extremely
low total harmonic distortion. An optional linearity trim pin is
provided to allow residual differential linearity error at midscale
to be eliminated. This feature is particularly valuable for low
distortion reconstructions of low amplitude signals. Output
glitch is also small contributing to the overall high level of performance. The output amplifier achieves fast settling and high
slew rates, providing a full ± 3V signal at load currents up to
SmA. The output amplifier is short circuit protected and can
withstand indefinite shorts to ground.

The AD1856 is packaged in a 16-pin plastic DIP or SOlC package and incorporates the industry-standard pinout. Operation is
guaranteed over the temperature range of - 25°C to + 70°C and
over the voltage supply range of ±4.75 to ± 13.2V.

The serial input interface consists of the clock, data and latch
enable pins. The serial 2s complement data word is clocked into
the DAC, MSB first, by the external data clock. The latch enable signal transfers the input word from the internal serial input register to the parallel DAC input register. The input clock
can support a lOMHz clock rate. This serial input port is compatible with popular digital filter chips used in consumer audio
products. These filters operate at oversampling rates of 2x, 4x
and 8 x sampling frequency.

REV. A

Power dissipation is llOmW typical with ±5V supplies and is a
typical 300mW when ± 12V supplies are used.

PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.

Total harmonic distortion is 100% tested.
MSB trim feature allows superlinear operation.
The AD1856 operates with ±5V to ± 12V supplies.
Serial interface is compatible with digital filter chips.
1.5fJ.s settling time permits 2x, 4x and 8x oversampling.
No external components are required.
96dB dynamic range.
±3V or ± ImA output capability.
16-bit resolution.
2s complement serial input words.
Low cost.
16-pin plastic DIP or SOlC package.

AUDIO DIA CONVERTERS 5-13

5

AD1856 -SPECIFICATIONS (typical at T, = +25"C and ±5V supplies unless otherwise noted)
Min

Typ

RESOLUTION
DIGITAL INPUTS

VIH
V1L
I,H,V1H=VL
IluVIL = 0.4

Clock Input Frequency

2.4
0

Max

Units

16

Bits

VL
0.8
1.0
-10

V
V
",A

10

,...A
MHz

ACCURACY
Gain Error
Bipolar Zero Error
Differential Linearity Error
Noise (rms, 20Hz to 20kHz) @ Bipolar Zero

±2.0
±30
±O.OOI
6

TOTAL HARMONIC DISTORTION
0dB, 99O.5Hz
ADl856N-K, R·K
ADl856N-J, R-J
ADl856N, R
-20dB,990.5Hz
ADl856N-K, R-K
ADl856N-J, R-J
ADl856N, R
ADl856N-K, R-K
-6OdB, 99O.5Hz
ADl856N-J, R-J
ADl856N, R

0.002
0.002
0.002
0.018
0.018
0.018
1.8
1.8
1.8

MONOTONICITY

IS

Bits

DRIFT (0 to + 70OC)
Total Drift
Bipolar Zero Drift

±25
±4

ppmofFSRrC
ppm ofFSRrC

SETTLING TIME (to ±0.006% of FSR)
Voltage Output
6V Step
ILSB Step
Slew Rate
Current Output
IrnA Step 100 to 1000 Load
IkO Load

1.5
1.0
9
350
350

",s
",s
VI",s
ns
ns

WARM-UP TIME
OUTPUT
Voltage Output Configuration
Bipolar Range
Output Current
Output Impedance
Short Circuit Duration
Current Output Configuration
Bipolar Range (±30%)
Output Impedance (±30%)
POWER SUPPLY
Voltage, +VL and +Vs
Voltage, -VL and -Vs
Current, +1, VL and Vs = +5V, 10MHz Clock
Current, -I, -VL and -Vs = -5V, IOMHz Clock
Current, +1, VLand Vs = +12V, 10MHzClock
Current, ~I, -VL and -Vs = -12V, 10MHz Clock

0.0025
0.004
0.008
0.020
0.040
11.040
2.0
4.0
4.0

I

±3

V
rnA
0

0.1
Indefinite to Common
1.0
1.7
4.75
-13.2

5
-5

10
-12
12
-15
110

rnA
kO
13.2
-4.75
15
-IS

V
V
rnA
rnA
rnA
mA

ISO

mW
mW

+70
+70
+100

°C
OC
°C

135
0
-25

-60

%
%
%
%
%
%
%
%
%

min

±8

POWER DISSIPATION
Vs and VL = ±5V, 10MHz Clock
VsandV L = ±12V, 10MHzClock
TEMPERATURE RANGE
Specification
Operation
Storage

%
mV
% ofpSR
",V

Specifications subject to change without notice.
Specifications sbown in boldface are tested on all production units at final test.

5-14 AUDIO DIA CONVERTERS

REV. A

AD1856
ABSOLUTE MAXIMUM RATINGS·
VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 13.2V
Vs to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 13.2V
-VL to DGND . . . . . . . . . . . . . . . . . . . . . . . -13.2 to OV
-Vs to AGND . . . . . . . . . . . . . . . . . . . . . . . - 13.2 to OV
Digital Inputs to DGND . . . . . . . . . . . . . . . . . -0.3 to VI.
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . ±O.3V
Short Circuit Protection . . . . . . . . Indefinite Short to Ground

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . + 300°C, 10sec
Storage Temperature . . . . . . . . . . . . . . . . -60°C to + 100°C
*Stresses greater than those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and fune·
tional uperation of the device at these or any other conditions above those
indicated in (he operational section of this specification is not implied. Exposure [0 absolute maximum rating conditions for extended periods may
affect device reliability.

PIN DESIGNATIONS

CONNECTION DIAGRAM

v.
TRIM
MSB ADJ
lOUT

AGND
SJ
R,

Pin
I
2
3
4
5
6
7

8
9
10
II
12
13
14
15
16

Function

Description

-Vs
DGND
VI.
NC
CLK
LE
DATA
-VL
VOUT
RF
SJ
AGND

Analog Negative Power Supply
Digital Ground
Logic Positive Power Supply
No Connection
Data Clock Input
Latch .Enable Input
Serial Data Input
Logic Negative Power Supply
Voltage Output
Feedback Resistor
Summing Junction
Analog Ground
Current Output
MSB Adjustment Terminal
MSB Trimming Potentiometer Terminal
Analog Positive Power Supply

lOUT

MSBADJ
TRIM
Vs

CAUTION ________________________~----~----~~----~~
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted.

WARNING!

cJ

~~EDEVICE

Definition of Specifications
TOTAL HARMONIC DISTORTION
Total Harmonic Distortion (THD) is defined as the ratio of the
square root of the sum of the squares of the values of the harmonics to the value of the fundamental input frequency. It is
expressed in percent (0/0) or decibels (dB).
THD is a measure of the magnitude and distribution of linearity
error and differential linearity error. The distribution of these
errors may be different, depending on the amplitude of the output signal. Therefore, to be most useful, THD should be specified for both large and small signal amplitudes.
SETTUNG TIME
Settling Time is the time required for the output to reach and
remain within a specified error band about its final value, measured from the digital input transition. It is the primary measure
of dynamic performance.
DYNAMIC RANGE
Dynamic Range is the specification that indicates the ratio of the
smallest signal the converter can resolve to the largest signal it is
able to produce. As a ratio, it is usually expressed in decibels

REV. A

(dB). The theoretical dynamic range of an n-bit converter is approximately (6xn) dB. In the case of the 16-bit AD1856, that is
%dB. The actual dynamic range of a convener is less than the
theoretical value due to limitations imposed by noise and quantization and other errors.
BIPOLAR ZERO ERROR
Bipolar Zero Error is the deviation in the actual analog output
from the ideal output (OV) when the 2scomplement input code
representing half scale (all Os) is loaded in the input register.
DIFFERENTIAL UNEARITY ERROR
Differential Linearity Error is the measure of the variation in
analog value, normalized to full scale, associated with a 1LSB
change in the digital input. Monotonic behavior requires that
the differential linearity error not exceed lLSB in the negative
direction.
MONOTONICITY
A DIA converter is monotonic if the output either increases or
remains constant as the digital input increases.

AUDIO DIA CONVERTERS 5-15

•

AD1856
FUNCTIONAL DESCRIPTION
The AD1856 is a complete, monolithic l6-bit PCM audio DAC.
No additional external components are required for operation.
As shown in the block diagram, each chip contains a voltage
reference, an output amplifier, a 16-bit DAC, a 16-bit input
latch and a 16-bit serial-to-parallel input register.
The voltage reference consists of a bandgap circuit and buffer
amplifier. This circuitry produces an output voltage that is
stable over time and temperature changes.
The 16-bit D/A converter uses a combination of segmented decoder and R-2R architectures to achieve consistent linearity and
differential linearity. The resistors which form the ladder structure are fabricated with silicon-chromium thin film. Laser trimming of these resistors further reduces linearity error
resulting in low output distortion.

The ± VL supplies are also designed to operate from ± 5V to
± 12V subject only to the limitation that - VL may not be more
negative than -Vs.
Decoupling capacitors should be used on all power supply pins.
Furthermore, good engineering practice suggests that these capacitors be placed as close as possible to the package pins as
well as the common points. The logic supplies, ± VL> should be
decoupled to digital common; and the analog supplies, ± Vs,
should be decoupled to analog common.
The use of four separate power supplies will reduce feedthrough
from the digital portion of the system to the linear portions of
the system, thus contributing to good performance. However,
+5V

The output amplifier uses both MOS and bipolar devices to
produce low offset, high slew-rate and optimum settling time.
When combined with the on-board feedback resistor, the output
op amp can convert the output current of the ADl856 to a voltage output.

ANALOG CIRCUIT CONSIDERATIONS
GROUNDING RECOMMENDATIONS
The AD1856 has two ground pins, designated ANALOG and
DIGITAL ground. The analog ground pin is the "high quality"
ground reference point for the device. The analog ground pin
should be connected to the analog common point in the system.
The output load should also be connected to that same point.
The digital ground pin returns ground current from the digital
logic portions of the ADl856 circuitry. This pin should be connected to the digital common point in the system.
As illustrated in Figure 1, the analog and digital grounds should
be connected together at one point in the system.
+5V

+5V

Figure 2. Alternate Recommended Schematic

four separate voltage supplies are not necessary for good circuit
performance. For example, Figure 2 illustrates a system where
only a single positive and a single negative supply are available.
Given that these two supplies are within the range of ± 5V to
± 12V, they may be used to power the AD 1856. In this case, the
positive logic and positive analog supplies may both be connected to the single positive supply. The negative logic and
negative analog supplies may both be connected to the single
negative supply. Performance would benefit from a measure of
isolation between the supplies introduced by using simple lowpass filters in the individual power supply leads.
A; with most linear circuits, changes in the power supplies will
affect the output of the DAC. Analog Devices recommends that
well regulated power supplies with less than 1% ripple be incorporated into the design of any system using these devices.

ANALOG
COMMON
-5V

-5V

Figure 1. Recommended Circuit Schematic

POWER SUPPLIES AND DECOUPLING
The ADl856 has four power supply input pins. ±Vs provide
the supply voltages to operate the linear portions of the DAC
including the voltage reference, output amplifier and control
amplifier. The ± Vs supplies are designed to operate from ± 5V
to ±12V.
The ± VL supplies operate the digital portions of the chip including the input shift register and the input latching circuitry.

5-16 AUDIO DIA CONVERTERS

TOTAL HARMONIC DISTORTION
The THD figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. The THD specification, therefore, provides a direct method to classify and choose an audio DAC for a
desired level of performance.
Analog Devices tests and grades all ADl856s on the basis of
THD performance. A block diagram of the test setup is shown
in Figure 3. In this test setup, a digital data stream, representing a Odb, - 20dB or -60dB sine wave is sent to the device under test. The frequency of this waveform is 990.5Hz. Input data
is sent to the ADl856 at a 4xFs rate (176.4kHz). The ADl856
under test produces an analog output signal with the on-board
op amp.

REV. A

AD1856

I--

4)(Fs

DATA
RATE
'I-BIT
DIGITAL
WAVEFORM
GENERATOR

,, , ,

0

L

,

0

,

0

,

0

4096PT.

.. ANIrvZER

o
,, ,
0

.--. ,

,,

o ,

o

0

1

23 CYCLES--l

f\./\.. .l\/\

AD1856
DATA
LATCH
VOUT
CLOCK

0

0
0
1

,,

%3V

l

99O.5Hz
NOTCH

u
:1--1

-~~

LOW PASS

10

Figure 3. Block Diagram of Distortion Test Circuit

The automatic test equipment digitizes 4096 samples of the output test waveform, incorporating 23 complete cycles of the sine
wave. A 4096 point FFf is performed on the results of the test.
Based on the first 9 harmonics of the fundamental 990.5Hz output wave, the total harmonic distortion of the device is calculated. Neither a deglitcher nor an MSB trim is used during the
THO test.
The circuit design, layout and manufacturing techniques employed in the production of the A01856 result in excellent
THO performance. Figure 4 shows the typical unadjusted THO
performance of the A01856 for various amphtudes of a 1kHz
output signal. As can be seen, the A01856 offers excellent performance, even at amplitudes as low as -60dB. Figure 5 illustrates the typical THO vs. frequency performance.

II

0.1

#'
I

I
i
~

0.5

O.U

1-2OdBI

0.01

O.ODS

~

O.OU

V

IFULL SCALEI

Jill

0.00 1
100

'000

10000

FREQUENCY - Hz

13.0

Figure 5. Typical THO vs. Frequency
#'
I

1.0

Ii

0.1

I

r.....

""'

I
~

OPTIONAL MSB ADJUSTMENT
Use of an optional adjustment circuit allows residual differential
linearity errors around midscale to be eliminated. These errors
are especially important when low amplitude signals are being
reproduced. In those cases, as the signal amplitude decreases,
the ratio of the midscale differential linearity error to the signal
amplitude increases and THO increases.

I'.
,. BITS........

f'...

0.0'

"'-...
0.001

-10

-so

-40

-30

-20

-10

VOUT - dB

NOTE
OdB:z:FULl SCALE

Therefore, for best performance at low output levels, the optional MSB adjust circuitry shown in Figure 6 may be used.
This circuit allows the differential linearity error at midscale to
be zeroed out. However, no adjustments are required to meet
data sheet specifications.

nuM~~~~~r---,~~~~~--~~~,_~.a~--~G)_v.
Figure 4. Typical Unadjusted THO vs. Amplitude

Msa ADJ

80n5

>30ns

Timing
Figure 7 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished properly. The input pins of the ADI860 are both TTL and SV
CMOS compatible, independent of the power supplies used.
The input requirements illustrated in Figures 6 and 7 are compatible with the data outputs provided by popular DSP filter
chips used in digital audio playback systems. The ADI860 input
clock can run at a 12.SMHz rate. This clock rate will allow data
transfer rates for 2x, 4x or 8x oversampling reconstruction.
The application section of this datasheet contains additional
guides for using the ADI860 with various DSP filter chips available from Sony, NPC and Yamaha.

---~
>30"5

CLK

>15"s

>60n5

>40n5

>4O"s
LATCH ENABLE (LEI

>40"5

INTERNAL DAC INPUT REGISTER
UPDATED WITH 18 MOST RECENT BITS

)
~

DATA

\_~~=~~~

BITS CLOCKED
TO SHIFT REGISTER

Figure 7. Timing Relationships of Input Signals

5-28 AUDIO DIA CONVERTERS

REV. A

AD1860
APPLICATIONS OF THE ADl860 PCM AUDIO DAC
The ADl860 is a versatile digital-to-analog converter designed
for applications in consumer digital audio equipment. Portable,
car and home compact disc player, digital audio amplifier and
DAT schemes can all use the ADI860. Various circuit architectures are popular in these systems. They include stereo playback
sections featuring one DAC per system, one DAC per audio

DATA
CLOCK

NONINVERTING
SHA
(OPTIONAL)
OUT

LATCH AD1860

SAMPLE
LEFT

channel (left/right) or multiple DACs per channel. Furthermore,
these architectures use different output reconstruction rates to
accomplish these functions including reproduction at the sample
rate Fs (Ix), at twice the sample rate (2xFs ), at four times
the sample rate (4xFs ) and even at eight times the sample rate
(8xFs )' Fs is 44. 1kHz for CD and 48kHz for DATapplications.

_-===::==~~~

LEFT
OUTPUT

___---1

RIGHT
OUTPUT

S~~ri~~---------------------~~---~~~-----~
Figure 8. AD1860 in a One DAC per System Architecture
One DAC per System
Figure 8 shows a circuit using one ADl860 per system to reproduce both channels of a typical first generation stereo digital
audio system. The input data is fed to the ADl860 in a format
which alternates between left channel data and right channel
data. The output of the ADl860 is switched between the left
channel and right channel output samplelhold amplifiers
(SHAs). The SHAs demultiplex and deglitch the output of the
AD1860. The timing diagram for the control signals for this circuit are shown in Figure 9.
However, when only two SHAs are used, the actual system performance is limited by the phase delay introduced by the demultiplexed format. This undesirable phase delay is caused by the
fact that the data words presented to the inputs of the DAC represent samples taken at precisely the same point in time. But

CLOCK

DATA

l----- LEFT WORD ----*'---- AtGHT WORO-------!

LATCHl~~r
g~ t'l"5~'
~ 1.5~s
m;n

m;n

~~~ ~------+I--------SA~~

L-J

when reconstructed and demultiplexed by a single DAC, these
same outputs occur at slightly diff~rent times.
By incorporating a noninverting SHA into the circuit, the phase
delay can be eliminated. In Figure 8, the optional SHA ensures
that the left channel output appears at the same time as the
right channel output. This minor change to the circuit eliminates the artificially induced phase delay by restoring simultaneous outputs.
Following the outputs of the SHAs are low pass filters. These
filters are required in any sampled data system to remove unwanted aliased components introduced by the sample and reconstruction operations.
One DAC per Channel
A second approach used to eliminate phase delay between left
and right channels employs one DAC per channel. In this architecture, the input data bitstream for each channel is transmitted
and then latched into the input register of each DAC. This "second generation" approach is illustrated in Figure 10. A standard
implementation of a low pass filter is shown at the output of
each DAC. An optional sampleihold amplifier could be connected between the DACs and the LPFs to deglitch th.: outputs.
This is not required, however, to achieve the specified performance.
Two DACs per Channel
Another architecture uses two DACs per channel. In this
scheme each DAC reproduces one half of the output waveform.
The advantage obtained with this structure is that midscale differentiallinearity error no longer affects the zero crossing points
of the waveforms. Its effects are shifted to the points where the
output waveform crosses 112 ± 114 full scale. The result is that
THD performance for low amplitude signals is greatly improved.

Figure 9. Control Signals for One DAC Circuit

REV. A

AUDIO DIA CONVERTERS 5-29

•

AD1860
CLOCK AD1860
LATCH
DATA AGND

DIGITAL
FILTER'
CHIP

DATA AGND
OUTo--JV""'...""'....~.,..,.....-I
LATCH
CLOCK AD1860

L
LOW PASS FILTER SECTION

OUTPUT SECTION
WITH MUTE CONTROL

Figure 10. One DAC per Channel Architecture with LPF

DIGITAL FILTERING AND OVERSAMPLING
Oversampling is a term which refers to playback techniques in
which the reconstruction frequency used is an integral (2 or
more) multiple of the original quantized data rate. For example,
in compact disc stereo digital audio playback units, the original
quantized data sample rate is 44. 1kHz. Popular oversampling
rates are 2x or 4xFs , yielding reconstruction rates of 88.2 and
176.4kHz, respectively.

68kHz. A 4xrate (176.4kHz) has unwanted components extending down to approximately 156kHz. The filter response needed
to remove these frequency components can now be less steep.
This means that a lower order filter may be used resulting in
less distortion at lower cost. Linear filters with 3 or 5 poles, as
shown in Figure 10, are adequate to do the job and are quite
common in digital audio products employing oversampling
techniques.

Oversampling is used to ease the performance constraints of the
low pass filters which follow the reconstruction DAC. In any
signal reconstructed from sampled data, unwanted frequency
components are introduced in the output spectrum; these components are centered at the reconstruction frequency. When a
44. 1kHz reconstruction frequency is used, the actual frequency
band of interest is 20Hz to 20kHz, and the band of unwanted
"image" frequency components extends from 44. 1kHz to
approximately 24kHz. These unwanted components must be
removed with a low-pass filter of very high order. First generation digital audio systems often used low-pass filters of 9, II and
even 13 poles. Linear implementations of these filters are expensive, difficult to manufacture and can produce distortion due to
varying group delay characteristics.

Oversampling techniques require the serial input data. stream to
run at the same integral multiple of the original data rate. So,
while the constraints on the output low-pass filter are eased, the
constraints on the serial digital input port and the settling time
of the output stage are not.

When a 2 x reconstruction frequency (88:2kHz) is used, the lowest frequency components now extend down to approximately

5-30 AUDIO DIA CONVERTERS

The actual oversampling operation takes place in the digital filter chip (DSP) which is located "upstream" from the DAC. The
digital filter accepts data from the media and adds the additional
reconstruction points according to the algorithm and coefficients
stored in the filter chip. Since the digital filters actually interpolate these additional reconstruction points, they have earned the
name "interpolation filters".
The AD 1860 is compatible with popular digital filter chips
used in digital audio products such as the Sony CXD1088, the
Yamaha YM3434 and the NPC SM5813.

REV. A

AD1860
DAC. The digital filter chip provides 18-bit data words to the
DACs at 4xFs ' Very high performance can be achieved.

Figure II illustrates the combihation of a second generation
digital filter chip, the Sony CXD1088, and the ADI860 audio

16.9344MHz

~

+5V

l---oCLOCK
LATCH
OUT
DATA AD1860

LEFT
OUTPUT

r--""--~

BCK ORES

Voo

03 0--+---1--1

D20-~--~----~-4

CXD1088Q

D10--+--4

DATA
LATCH
OUT
l--~ CLOCK AD1860

RIGHT
OUTPUT

,

,

OUTPUT
SECTION
24

24
BCK
LRCK ____

-I--------------------~

I

L ____ .J

L ____ .J
OPTIONAL
SHA SECTION

____________________

~-----

LRo~r~L~1~~~R~1~-Ir-~L2;-lL~R~2~~~L~3~1-~R~3--r-~L~4~L-~R~4__r_----1

J

L _ _ _ _ _~

LRo~r----------~~------------1-------------~R~1~-----=::~~r-----01
02
03

----.L__

LSB

MSB

~

____

~----------L_

APTL ________________

~------L_

LSB
MSB
________S_--------IL____

____________________

APTR __________________________

~

~

________

_________F------L________

Figure 11. 4xFs with the CXD1088Q

REV. A

AUDIO DIA CONVERTERS 5-31

II

AD1860
and right channel.output pins on the YM3434. This implementation does not require any external components to achieve the
full108dB dynamic range afforded by the 18-bit ADI860 audio
DAC. As before, optional samplelh'oICl signals are provided.

Figure 12 illustrates the combination of a Yamaha YM3434 digital filter chip and two ADI860 audio DACs. This combiIlation
of components results in 8 x F s oversampling reconstruction
rates. This rate allows the use of lower order output low pass
filters than would be required with lower oversampling rates,
without sacrificing performance. In this high performance CD
player application, the DAC input data is simultaneously transmitted to the input registers of the DACs through dedicated left

Figure 13 shows the schematic for 8xFs when two AD1860s are
used with an NPC SMS813AP/APT digital filter chip. As can be
seen, this application is very similar to the one shown in Figure
12. See Figure 10 for an example of a typical LPF.

CLOCK
LEFT
OUTPUT

LATCH
DLO r---11-- +7O"C
- 25"C to + 70"C

-92 dB, 0.0025%
-96 dB, 0.0016%

110 dB
113 dB

N-16
N-16

,
,
*N = Plastic DIP. ,For outline information see Package Information sectioo.

5-"36 AUDIO DIA CONVERTERS

REV. A

AD1862
TOTAL HARMONIC DISTORTION + NOISE
Total Harmonic Distortion plus Noise (THD+ N) is defined as
the ratio of the square root of the sum of the squares of the values of the harmonics and noise to the value of the fundamental
input frequency. It is usually expressed in percent (%) or decibels (dB).

TRIM

AGNO

D-RANGE DISTORTION
D-Range Distortion is the ratio of the signal amplitude to the
distortion plus noise at -60 dB. In this case, an A-Weight filter
is used. The value specified for D-Range performance is the ratio measured plus 60 dB.
SETTLING TIME
Settling Time is the time required for the output to reach and
remain within ± 112 LSB about its final value, measured from
the digital input transition. It is a primary measure of dynamic
performance and is usually expressed in nanoseconds (ns).

__~~__T ___,,>......__ g:=~T
.-__..1_...l=;-j-- +v,

DGNO

AD1862 Block Diagram

SIGNAL-TO-NOISE RATIO
The Signal-to-Noise Ratio is defined as the ratio of the amplitude of the output with full-scale present to the amplitude of the
output when no signal is present. It is expressed in decibels (dB)
and measured using an A-Weight filter.

FUNCTIONAL DESCRIPTION
The AD1862 is a high performance, monolithic 20-bit audio
DAC. Each device includes a voltage reference, a 20-bit DAC,
20-bit input latch and a 20-bit serial-to-parallel input register. A
special digital offset circuit, combined with segmentation circuitry, produces excellent THD+N and D-range performance.

GAIN LINEARITY
Gain Linearity is a measure of the deviation of the actual output
amplitude from the ideal output amplitude. It is determined by
measuring the amplitude of the output signal as the amplitude
of that output signal is digitally reduced to a low level. A perfect
D/A converter exhibits no difference between the ideal and actual amplitudes. Gain linearity is expressed in decibels (dB).

Extensive noise-reduction features are utilized to make the noise
performance of the AD1862 as high as possible. For example,
the voltage reference circuit is a low-noise, 9 volt bandgap cell.
This cell supplies the reference voltage to the bipolar offset circuit and the DAC. An external noise-reduction capacitor is connected to NRI to form a low-pass filter network.

MIDSCALE ERROR
Midscale Error, or bipolar zero error, is the deviation of the actual analog output from the ideal output when the 2s complement input code representing midscale is loaded in the input
register. The ADl862 is a current output D/A converter. Therefore, this error is expressed in fLA.

Additional noise-reduction techniques are used in the control
amplifier of the DAC. By connecting an external noise-reduction
capacitor to NR2 output noise contributions from the control
portion of the DAC are similarly reduced. The noise-reduction
efforts result in a signal-to-noise ratio of 119 dB.
The design of the AD1862 uses a combination of segmented decoder, R-2R topology and digital offset to produce low distortion at all signal amplitudes. The digital offset technique shifts
the midscale output voltage (0 V) away from the MSB transition
of the device. Therefore, small amplitude signals are not affected by an MSB change. An extra DAC cell is included to
avoid clipping the output at full scale.
The DAC supplies a ± I rnA output current to an external
I-to-V converter. An on-board 3 kO feedback resistor is also
supplied. Both the output current and feedback resistor. are
laser-trimmed to ±2% tolerance, simplifying the selection of
external filter and/or deemphasis network components." The input register and serial-to-parallel converter are fabricated with
CMOS logic gates. These gates allow the achievement of fast
switching speeds and low power consumption. Internal TTLto-CMOS converters are used to insure TTL and 5 V CMOS
compatibility.

REV. A

AUDIO DIA CONVERTERS 5-37

II

A01862
Analog Circuit Considerations
GROUNDING RECOMMENDATIONS
The ADI862 has two gro.und pins, designated analog ground
(AGND) and digital ground (DGND). The analog ground pin is
the "high-quaIity" ground reference for the device. The analog
ground pin should be connected to the analog common point in
the system. The reference bypass capacitor, the noninverting
tenninal of the current-to-voltage conversion op amp, and any
output loads should be connected to this point. The digital
ground pin returns ground current from the digital logic portions of the ADI862 circuitry. This pin should be connected to
the digital common point in the system.

EXTERNAL NOISE REDUCTION COMPONENTS
T~o external capacitors are required to achieve low-noise operation. Their correct connection is illustrated in Figure 8. Capacitor Cl is connected between the pin labeled NRl and analog
common. CI forms a low-pass filter element which reduces noise
contributed by the voltage reference circuitry. The proper
choice for this capacitor is a tantalum type with value of 10 tJ.F
or more. This capacitor should be connected to the package pins
as closely as possjble. This will minimize the effects
of parasitic inductance of the leads and connections circuit
connections.

As illustrated in Figure 7, AGND and DGND should be connected together at one point in the system.
-12V
ANALOG
SUPPLY

AD1862
TOP VIEW
(Not to Scala)

NOTE:
PIN 1 IS "HIGH QUALITY" RETURN
FOR BIAS CAP.

Figure 8. Noise Reduction Capacitors
Figure 7. Grounding and Bypassing Recommendations

POWER SUPPLmS AND DECOUPLING
The ADI862 has four power supply input pins. ±Vs provide
the supply voltages which operate the linear portions of the
DAC including the voltage reference and control amplifier. The
± Vs supplies are designed to operate with ± 12 volts.
The ± V L supplies operate the digital portions of the chip including the input shift register, the input latching circuitry and
the TTL-to-CMOS level shifters. The ±VL supplies are designed to be operated from ±5 V to ±12 V supplies subject only
to the limitation that -VL may not be more negative than -Vs.
Decoupling capacitors should be used on all power supply input
pins. Good engineering practice suggests that these capacitors be
placed as close as possible to the package pins and the common
points. The logic supplies, ± VL' should be decoupled to
DGND and the analog supplies, ±Vs, should be decoupled to
AGND.

5-38 AUDIO DIA CONVERTERS

Capacitor C2 is connected between the pin labeled NR2 and the
negative analog supply, - Vs. This capacitor reduces the portion
of output. noise contributed by the control amplifier circuitry.
C2 should be chosen to be a tantalum capacitor with a value of
about 1 ... F. Again, the connections between the AD1862 and
C2 should be made as short as possible;.
The recommended values for Cl and C2 are 10 tJ.F and 1 tJ.F,
respectively. The ratio between Cl and C2 should be approximately 10. Additional noise reduction can be gained by choosing
slightly higher values for Cl and C2 such as 22 ... F and 2.2 tJ.F.
Figure 2 illustrates the noise performance of the AD 1862 with
10 tJ.F and 1 tJ.F.
EXTERNAL AMPLIFIER CONNECTIONS
The ADl862 is a current-output D/A converter. Therefore, an
external amplifier, in combination with the on-board feedback
resistor, is required to derive an output voltage. Figure 9
illustrates the proper connections for an external operational amplifier. The output of the ADl862 is intended to drive the summing junction of an external current-to-voltage conversion op
amp. Therefore, the voltage on the output current pin of the
ADI862 should be approximately the same as that on the
AGND pin of the device.

REV. A

Testing the AD1862
The on-board 3 kO feedback resistor and the ± I rnA output
current typically have ± I % tolerance or less. This makes the
choice of external components very simple and eliminates additional trimming. For example, if a user wishes to derive an output voltage higher than the ± 3 V swing offered by the output
current and feedback resistor combination, all that is required is
to combine a standard value resistor with the feedback resistor
to achieve the appropriate output voltage swing. This technique
can be extended to include the choice of elements in the deemphasis network, etc.
TOTAL HARMONIC DISTORTION + NOISE
The THD figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. The THD specification, therefore, provides a direct method to classify and choose an audio DAC for a
desired level of performance.

By combining noise measurement with the THD measurement,
a THD+ N specification is realized. This specification indicates
all of the undesirable signal produced by the DAC, including
harmonic products of the test tone as well as noise.
Analog Devices tests all ADI862s on the basis of THD+ N performance. In this test procedure, a digital data stream representing a 0 dB, -20 dB or -60 dB sine wave is sent to the device
under test. The frequency of the waveform is 990.5 Hz. Input
data is sent to the ADI862 at an 8 x Fs rate (352.8 kHz). The
ADI862 under test produces an output current which is converted to an output voltage by an external amplifier. Figure 10
illustrates the recommended test circuit. Deglitchers and trims
are not used during this test procedure. The automatic test
equipment digitizes 4096 samples of the output test waveform,
incorporating 23 complete cycles of the sine wave. A 4096 point
FFT is performed on the test data.

•
AD1862
TOP VIEW

(NoIIO Scale)

I - - - -....-VOUT

Figure 9. External Amplifier Connections

Based upon the harmonics of the fundamental 990.5 Hz test
tone, and the noise components in the audio band, the total harmonic distortion + noise of the device is calculated. The
ADI862 is available in two performance grades. The ADI862N
produces a maximum of 0.0025% THD+ N at 0 dB signal levels. The higher performance ADI862N-J produces a maximum
of 0.0016% THD+ N at 0 dB signal levels.
SIGNAL-TO-NOISE RATIO
The Signal-to-Noise Ratio (SNR) of the ADI862 is tested in the
following manner. The amplitude of a 0 dB signal is measured.
The device under test is then set to midscale output voltage (0
volts). The amplitude of all noise present to 30 kHz is measured. The SNR is the ratio of these two measurements. The
SNR figure for the ADI862 includes the output noise contributed by the NE5534 op amp used in the test fixture but does
not include the noise contributed by the low-pass fllter used in
the test fixture.

The ADI862N has a minimum SNR of 110 dB. The higher performance ADI862N-J has a minimum SNR of 113 dB.
12V

-12V--....-...,

12V----,

17MHz

Il.JUUlJ1J1JUl.

352.8kHz ~

--+=::""-1
--+---

Il.JUUlJ1J1JUl. --1----1

OUTPUT
VOLTAGE

-12V-+---'

Figure 10. Recommended Test Circuit

REV. A

AUDIO DIA CONVERTERS 5-39

II

Testing the AD1862
OPTIONAL TRIM ADJUSTMENT
The AD1862 includes an external midscale adjust feature.
Should an application require improved distonion performance
under small and very small signal amplitudes (-60 dB and
lower), an adjustment is possible. Two resistors and one potentiometer form the adjustment network. Figure 11 illustrates the
correct configuration of the external components. Analog Devices recommends that this adjustment be performed with
-60 dB signal amplitudes or lower. Minor performance improvement is achieved with larger signal amplitudes such as
-20 dB. Almost no improvement is possible when this adjustment is performed with 0 dB signal amplitudes.

.----------~~-_+-- -12V

470kn

AD1862
TOP VIEW
(Nollo Scale)

100kn

470kll

Figure ". External Midscale Adjust

DIGITAL CIltCUIT CONSIDERATIONS
INPUT DATA
Data is transmitted to the AD 1862 in a bit stream composed of
20-bit words with a serial, 2s complement, MSB first format.
Three signals must be present to achieve proper operation. They
are the data, clock and latch enable signals. Input data bits are

clocked into the input register on the rising edge of the clock
signal (CLK). The LSB is clocked in on the 20th clock pulse.
When all data bits are loaded, a low going latch enable (LE)
pulse updates the DAC input. Figure 12a illustrates the general
signal requirements for data transfer for the AD1862.
MSB ___ WORD n+ 1-'"

MSB ..........- - - - - - - WORD n --------.~ LSB

CLOCK
LATCH
ENABLE

Figure 12a. Input Data

TIMING
Figure 12b illustrates the specific timing requirements that must

be met in order for the data transfer to be accomplished successfully. The input pins of the AD1862 are both TTL and 5 V
CMOS compatible, independent of the power supplies used in
the application. The input requirements illustrated in Fig-

ure l2b are compatible with the data outputs provided by popular digital interpolation filter chips used in digital audio playback systems. The AD1862 input clock will run at 17 MHz
allowing data to be transferred at a rate of 16 x Fs. Of course,
it will also function at slower rates such as 2 x, 4 x or 8 x Fs.

:..80n.

CLK

LATCH ENABLE (LE)

Figure 12b. Timing Requirements

!HW AUDIO DIA CONVERTEJS

REV. A

AD1862
The ADl862 is an extremely high performance DAC designed
for high-end consumer and professional digital audio applications. Compact disc players, digital preamplifiers, digital musical
instruments and sound processors benefit from the extended
dynamic range, low THD+Noise and high signa1-to-noise ratio.
For the first time, the D/A convener is no longer the basic limitation in the performance of a CD player.
The performance of professional audio gear, such as mixing consoles, digital tape recorders and multivoice synthesizers can utilize the wide dynamic range and signal-to-noise ratio to achieve
greater performance. And, the AD1862's space saving 16-pin
package contributes to compact system design. This permits a
system designer to incorporate more voices in multivoice synthesizers, more tracks in multitrack tape recorders and more channels in multichannel mixing consoles.

Funhermore, high-resolution signal processing and waveform
generation applications are equally well served by the AD1862.

HIGH PERFORMANCE CD PLAYER
Figure 13 illustrates the application of AD1862s in a high performance CD player. Two ADl862s are used, one for the left
channel and one for the right channel. The CXDllXX chip decodes the digital data coming from the read electronics and
sends it to the SM5813. Input data is sent to each ADl862 by
the SM5813 digital interpolating filter. This device operates at
8 times oversampling. The NE5534 op amps are chosen for
current-to-voltage converters due to their low distortion and
low noise. The output filters are S-pole designs. For the purpose of clarity, all bypass capacitors have been omitted from
the schematic.

II
LEFT
CHANNEL
OUTPUT

-SV~~~~~------~+-+-r-Hr---i_,~_ _ __ ' -

-12V

~:.~~

----------HH--t-t--i

SVDIGITAL
SUPPLY

SONY
CXD1125
1130
1135

XTAI
LACK

LRCI

DATA

DIN

C210

BCKI

BCKO

RIGHT
CHANNEL
OUTPUT

SM5813

WCKO

DOR

Figure 13. High Performance 20-Bit 8 x Oversampling CD Player Application

REV. A

AUDIO DIA CONVERTERS 5-41

AD1862
10GB-RESOLUTION SIGNAL PROCESSING
Figure 14 illustrates the ADl862 combined with the DSPS6000.
In high-resolution applications, the cOmbination of the 24-bit
architecture of the DSPS6000 and the low noise and high resolution of the ADI862 can produce high-resolution, low-noise
system.

a

As shown in Figure 14, the clock signal supplied by the DSP
processor must be inverted to be compatible with the input of
the ADI862. The exact architecture of the output low-pass ftlter

depends on. the sample rate of the output data. In general, the
higher the ovetsampling rate, the fewer number of ftlter poles
are required to prevent aliasing.
.
The 20-bit resolution is particularly suitable for professional audio, mixing or equalization equipment. Its resolution allows
24 dB of equalization to be performed on 16-bit input words
without signal truncation. Furthermore, up to sixteen 16-bit input words can be mixed and output directly to the ADl862. In
this case, no loss of sigDaI information would be encountered.

-12V

12V

ANALOG
SUPPLY

ANALOG
SUPPLY

5V

DIGITAL
SUPPLY

Vee

SCK
SC2~-----------r----~

DSP56001

OUTPUT
VOLTAGE

STD~----------+----;
-5V

~:?P~~~

__+-__

..J

VDD~----------~~--------------------~
DIGITAL

= COMMON
Figure 14. DSP56001 and AD1862 Produces High Resolution Signal Processing System

5-42 AUDIO DIA CONVERTERS

REV. A

Complete Dual
l8-Bit Audio DAC
AD1864* I

ANALOG
WDEVICES

11IIIIIIII

FEATURES
Dual Serial Input. Voltage Output DACs
No External Components Required
Operates at 8 x Oversampling per Channel
±5 Volt to :!:12 Volt Operation
Cophased Outputs
115 dB Channel Separation
±0.3% Interchannel Gain Matching
0.0017% THD+N
APPLICATIONS
Multichannel Audio Applications:
Compact Disc Players
Multi-Voice Keyboard Instruments
DAT Players and Recorders
Digital Mixing Consoles
Multimedia Workstations

PRODUCT DESCRIPTION
The ADI864 is a complete duall8-bit DAC offering excellent
THD+N, while requiring no external components. Two complete signal channels are included. This results in cophased voltage or current output signals and eliminates the need for output
demultiplexing circuitry. The monolithic ADl864 chip includes
CMOS logic elements, bipolar and MaS linear elements and
laser-trimmed thin-fIlm resistor elements, all fabricated on Analog Devices BiMOS II process.
The DACs on the ADI864 chip employ a partially-segmented
architecture. The first four MSBs of each DAC are segmented
into 15 elements. The 14 LSBs are produced using standard
R-2R techniques. Segment and R-2R resistors are laser-trimmed
to provide extremely low total harmonic distortion. This architecture minimizes errors at major code transitions resulting in
low output glitch and eliminating the need for an external
deglitcher. When used in the current output mode, the ADI864
provides two cophased ± I rnA output signals.
Each channel is equipped with a high performance output amplifier. These amplifiers achieve fast settling and high slew rate,
producing ±3 V signals at load currents up to 8 mAo Each output amplifier is short-circuit protected and can withstand indefinite short circuits to ground.
The AD 1864 was designed to balance two sets of opposing requirements, channel separation and DAC matching. High channel separation is the result of careful layout techniques. At the
same time, both channels of the ADI864 have been designed to
ensure matched gain and linearity as well as tracking over time
and temperature. This assures optimum performance when used
in stereo and multi-DAC per channel applications.

AD1864 DIP BLOCK DIAGRAM

SJ
RF
Vcur
-VL

DL
LR

LL
DGND

A versatile digital interface allows the ADI864 to be directly
connected to standard digital filter chips. This interface employs
five signals: Data Left (DL), Data Right (DR), Latch Left
(LL), Latch Right (LR) and Clock (CLK). DL and DR are the
serial input pins for the left and right DAC input registers. Input data bits are clocked into the input register on the rising .
edge of CLK. A low-going latch edge updates the respective
DAC output. For systems using only a single latch signal, LL
and LR may be connected together. For systems using only one
DATA signal, DR and DL may be connected together.
The ADI864 operates from ±S V to ±12 V power supplies.
The digital supplies, VL and - VL> can be separated from the
analog supplies, Vsand - Vs, for reduced digital feedthrough.
Separate analog and digital ground pins are also provided. The
ADI864 typically dissipates only 225 mW, with a maximum
power dissipation of 265 mW.
The ADI864 is packaged in both a 24-pin plastic DIP and a
28-pin PLCC. Operation is guaranteed over the temperature
range of - 250C to + 70°C and over the voltage supply range of
±4.7S V to ±13.2 V.
PRODUCT HIGHLIGHTS
I. The ADI864 is a complete duall8-bit audio DAC.
2. 108 dB signal-to-noise ratio for low noise operation.
3. THD+N is typically 0.0017%.
4. Interchannel gain and midscale matching.
5. Output voltages and currents are cophased.
6. Low glitch for improved sound quality.
7. Both channels are 100% tested at 8 x Fs.
8. Low Power - only 225 mW typ, 265 mW max.
9. 5-wire interface for individual DAC control.

·Covered by

u.s.

Pateab Nos: RE 30,586; 3,961,326; 4,141,004;
4,349,811; 4,855,618; 4,857,862

REV. A

AUDIO DIA CONVERTERS ~

•

AD 1864 - SPEC IFI CATIONS 0, =+25°C, :tV =:tVs = ±5 v, Fs =352.8 kHz, without lSI adjustment)
L

Min
RESOLUTION
DIGITAL INPUTS
VIH
VIL
IIH' VIH = +VL
IlL> VIL = 0.4 V
Clock Input Frequency
ACCURACY
Gain Error
Interchannel Gain Matching
Midscale Error
Interchannel Midscale Matching
Gain Linearity Error (0 dB to -90 dB)
DRIFT (O°C to + 700c)
Gain Drift
Midscale Drift
TOTAL HARMONIC DISTORTION + NOISE*
o dB, 990.5 Hz ADl864N, P
ADl864N-], P-]
ADl864N-K '
-20 dB, 990.5 Hz ADlS64N, P
ADlS64N-], P-]
ADlS64N-K
-60 dB, 990.5 Hz ADlS64N, P
ADlS64N-], P-]
ADlS64N-K
CHANNEL SEPARATION*
odB, 990.5 Hz
SIGNAL-TO-NOISE RATIO*
(20 Hz to 30 kHz) N,N-], N-K
P, P-]
D-RANGE* (WITH A-WEIGHT FILTER)
-60 dB, 990.5 Hz ADlS64N, P
ADlS64N-], P-]
ADl864N-K
OUTPUT
Voltage Output Configuration
Output Range (:t3%)
Output Impedance
Load Current
Short-Circuit Duration
Current Output Configuration
Bipolar Output Range (:t30%)
Output Impedance (:t30%)
POWER SUPPLY
+VL and +Vs
-VL and -Vs
+1, (+V L and +Vs = +5 V)
-I, (-VL and -Vs = -5 V)
POWER DISSIPATION, :tVL
TEMPERATURE RANGE
Specification
Operation
Storage
WARMUP TIME
NOTE

= :tVs =

Typ

Max

IS
2.0

Uaits
Bits

+VL
O.S
1.0
-10

V
V

!LA
!LA

MHz

12.7
0.4
0.3
4
5
<2

1.0
0.8

:t25
:t4
0.004
0.003
0.0017
0.010
0.010
0.010
1.0
1.0
1.0

% ofFSR
%ofFSR
mV
mV
dB
ppm of FSRf'C
ppm of FSRf'C

0.006
0.004
0.0025
0.040
0.020
0.020
4.0
2.0
2.0

%
%
%
%
%
%
%
%
%

110

115

dB

102
9S

108
lOS

dB

88
94
94

100
100
100

dB
dB
dB

±2.88

:t3.0
0.1

±3.I2

V
n

mA

:tS
Indefinite to Common
:tl
1.7
4.75
-13.2

:is V
0
-25
-60

mA
kn

5.0
-5.0
22
-23

13.2
-4.75
25
-28

V
V

225

265

mW

+25

+70
+70
+100

OC
OC
OC
min

I

mA
mA

Specifications shown in boldface are tested on production units at final test without optional MSB adjustment.
"Tested in accordance with ElAJ Test Standard CP-307 with IS-bit data.
Specifications subject to change without notice.

5-44 AUDIO DIA CONVERTERS

REV. A

Typical Perfonnance Data -AD1864
100

,----,----r--,-----r---.-----,
120 I - _ - - j - - - + - - - j - - - + - - - I - - - l

130

--OIIB

10
10

70

.
30

110
1,00
I

~

i

2Or---+--1---r---t--+--~

10r------j---+---j---+---r---1
0

•

4

°0~-~--~5---L-~,~0~--L--~,5
FREQUENCY - kHz

10

Figure 2. Channel Separation

Figure 1. THD+N vs. Frequency

100

VB.

Frequency

•

700

-

IS

800

•
E

I
Z

I

70
801----j---+---j---+---1---l

3Or---+--1---r---t--+--~

FREQUENCY - kHz

1I

: r--t--t--t--t--t-----l

I :I--+---+---+--+-~I---l

10
0

r-~"=+::::$:::;f;:=+=:t:d

i

I

10

500

~

IS

L

400

300

II:

V'

/

200

V

/

f--

100
80

..

0

o
10

40

8

10

12

SUPPLY VOlTAGE -..,

Figure 4. Power Dissipation vs. Supply Voltage'

Figure 3. THD+N vs. Temperature

100

10
",

10

80
70

1

o

TEMPERATURE-OC

I

/

/

I: .
80

I

....... r-

30
211

10

o

500

1000

1500

_

_

LOAD _ _ - Q

Figure 5. THD+N VB. Load Resistance

REV. A

-

-10
-100

-80

...

-70

-80

-50

_

_

...

-10

1NP\IT AIIPUTUDE - dB

Figure 6. Gain Linearity Error, VB. Input Amplitude

AUDIO DIA CONVERTERS

~

AQt864
ABSOLUTE MAXIMUM RATINGS·
VL toDGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to 13.2 V
VstoAGND . . . • . . . . . . . . . . . . . . . . . . . OVto13.2V
-VL toDGND . . . . . . . . . . . . . . . . . . . . . -13.2 V to 0 V
-Vs to AGND . . . . . . . . . . . . . . . . . . . . . -13.2 V to 0 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . :to.3 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . -0.3 V to VL
Short-Circuit Protection . . . . . . . . Indefinite Short to Ground
Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . + 300°C
·Stresses greater than those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational section of this -specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.

CAUTION _________________________________________________
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur oli unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are removed.

DIP Package
-Vo

3

LEFT
CHANNEL

4

AGND

SJ

SJ
RF
YOUT

+VL

-VL

DR

DL

LR

LL

.,

:IE

'":IE ii:...

'OUT 5

>1

u
Z

,:'"

1

28

!

.;-...

~

NC

24 AGND

RF

r

:~

AD1864

23 SJ

TOP VIEW

22 NC

(NoIIO Scale)

+Vl 11 (
12

13

14

15

a:

a:
....

"<>

u

0

Z

16
0

.'~.

17

18

........ ....0

0

NC

lOUT

AGND
SJ
Rp
VOUT
+VL
DR
LR
CLK
DGND
LL
DL
-VL

MSB
TRIM
+Vs

ORDERING GUIDE

21 RF

VOUT 10 [

"

Negative Analog Supply
Right Channel Trim Network Connection
Right Channel Trim Potentiometer Connection
Right Channel Output Current
Right Channel Analog Common Pin
Right Channel Amplifier Summing Junction
Right Channel Feedback Resistor
Right Channel Output Voltage
Positive Digital Supply
Right Channel Data Input Pin
Right Channel Latch Pin
Clock Input Pin
Digital Common Pin
Left Channel Latch Pin
Left Channel Data Input Pin
Negative Digital Supply
Left Channel Output Voltage
Left Channel Feedback Resistor
Left Channel Amplifier Summing Junction
Left Channel Analog Common Pin
Left Channel Output Current
Left Channel Trim Potentiometer Wiper Connection
Left Channel Trim Network Connection
Positive Analog Supply

lOUT
25 'OUT

AGND 6 (

SJ 7

DESCRIPTION

-Vs
TRIM
MSB

RF
SJ
AGND

III

...a: '":IE
27 26

IJ

=NO CONNECT

5-46 AUDIO DIA CONVERTERS

~~EDEVICE

SIGNAL

VOUT

PLCC Package
III

cJ

PIN DESIGNATIONS

PIN CONFIGURATIONS

RIGHT MSB
CHANNEL
lour

WARNING!

20 VOUT

Model

THD+N
@FS

Package
Option·

19 -VL

ADl864N
ADl864N-J
ADl864N-K
ADl864P
ADl864P-J

0.006%
0.004%
0.0025%
0.006%
0.004%

N-24
N-24
N-24
P-28A
P-28A

ON = Plastic DIP; P = Plastic Leaded
Chip Carrier. For outline infonnation see
Package Infonnation section.

REV. A

Definition of Specifications- AD1864
TOTAL HARMONIC DISTORTION + NOISE
Total Harmonic Distortion plus Noise (THD+ N) is defined as
the ratio of the square root of the sum of the squares of the
amplitudes of the harmonics and noise to the value of the fundamental input frequency. It is usually expressed in percent.
THD+ N is a measure of the magnitude and distribution of linearity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depending on the amplitude of the output signal. Therefore, to be most
useful, THD+ N should be specified for both large (0 dB) and
small (-20 dB, -60 dB) signal amplitudes. THD+N measurements for the AD IS64 are made using the first 19 harmonics
and noise out to 30 kHz.
SIGNAL-TO-NOISE RATIO
The Signal-to-Noise Ratio is defined as the ratio of the amplitude of the output when cide midscale is entered to the amplitude of the output when a cide full scale is entered. It is
measured using a standard A-Weight filter. SNR for the
ADIS64 is measured for noise components up to 30 kHz.
CHANNEL SEPARATION
Channel separation is defined as the ratio of the amplitude of a
full-scale signal appearing on one channel to the amplitude of.
that same signal which couples onto the adjacent channel. It is
usually expressed in dB. For the ADIS64 channel separation is
measured in accordance with EIAJ Standard CP-307, Section 5.5.
D-RANGE DISTORTION
D-Range distortion is equal to the value of the total harmonic
distortion + noise (THD+N) plus 60 dB when a signal level of
60 dB below full-scale is reproduced. D-Range is tested with a
1 kHz input sine wave. This is measured with a standard
A-Weight filter as specified by EIAJ Standard CP-307.
GAIN ERROR
The gain error specification indicates how closely the output of a
given channel matches the ideal output for given input data. It
is expressed in % of FSR and is measured with a full-scale output signal.
INTERCHANNEL GAIN MATCmNG
The gain matching specification indicates how closely the amplitudes of the output signals match when producing identical input data. It is expressed in % of FSR·(Full-Scale Range = 6 V
for the ADIS64) and is measured with full-scale output signals.
MIDSCALE ERROR
Midscale error is the deviation of the actual analog output of a
given channel from the ideal output (0 V) when the 2s complement input code. representing half scale is loaded into the input
register of the DAC. It is expressed in mY.

REV. A

INTERCHANNEL MIDSCALE MATCHING
The midscale matching specification indicates how closely the
amplitudes of the output signals of the two channels match
when the 2s complement input code representing half scale is
loaded into the input register of both channels. It is expressed in
mV and is measured with half-scale output signals.

,Vs
TRIM
MSB
lOUT

AGND

SJ
R,

Vour
-VL
DR

DL

LR

LL
DGND

AD1864 DIP Block Diagram

FUNCTIONAL DESCRIPTION
The ADIS64 is a complete, monolithic, dual IS-bit audio DAC.
No external components are required for operation. As shown in
the block diagram, each chip contains two voltage references,
two output amplifiers, two IS-bit serial input registers and two
IS-bit DACs.
The voltage reference section provides a reference voltage for
each DAC circuit. These voltages are produced by low-noise
bandgap circuits. Buffer amplifiers are also included. This combination of elements produces reference voltages that are unaffected by changes in temperature and time.
The output amplifiers use both MOS and bipolar devices and
incorporate an all NPN output stage. This design technique produces higher slew rate and lower distortion than previous techniques. Frequency response is also improved. When combined
with the appropriate on-chip feedback resistor, the output op
amps convert the output current to output voltages.
The IS-bit D/A converters use a combination of segmented decoder and R-2R architecture to achieve consistent linearity and
differential linearity . The resistors which form the ladder structure are fabricated with silicon chromium thin film. Laser trimming of these resistors further reduces linearity errors resulting
in low output distortion.
The input registers are fabricated with CMOS logic gates. These
gates allow the achievement of fast switching speeds and low
power consumption, contributing to the low glitch and low
power dissipation of the ADIS64.

AUDIO DIA CONVERTERS 5-47

II

AD1864 - Analog Circuit Considerations
GROUNDING RECOMMENDATIONS
The AD1864 has three ground pins, two labeled AGND and
one labeled DGND. AGND, the analog ground pins, are the
"high quality" ground references for the device. To minimize
distortion and reduce crosstalk between .channels, the analog
ground pins should be connected together only at the analog
common point in the system. As shown in Figure 7, the AGND
pins should not be connected at the chip.

Though separate positive and negative power supply pins are
provided for the analog and digital portions of the AD1864, it is
also possible to use the AD 1864 in systems featuring a single
positive and a single negative power supply. In this case, the
+ Vs and + VL input pins should be connected to the positive
power supply. -Vs and -VL should be connected to the single
negative supply. This feature allows reduction of the cost and
complexity of the system power supply.
As with most linear circuits, changes in the power supplies will
affect the output of the DAC. Analog Devices recommends that
well-regulated power supplies with less than I % ripple be 'incorporated intO the design of an audio system.

Vour - - - + - j

DIGITAL -

.....- - ;

SUPPLY

1-4----- VOUT

1--.._- -DIGITAL
SUPPLY

DIGITAL

COMMON

Figure 7. Recommended DIP Circuit Schematic

The digital ground pin returns ground current from the digital
logic portions of the AD 1864 circuitry. This pin should be connected to the digital common pin in the system. Other digital
logic chips should also be referred to that point. The analog and
digital grounds should be connected together at one point in the
system, preferably at the power supply.
POWER SUPPLIES AND DECOUPLING
The AD1864 has four power supply pins. ±Vs provide the supply voltages which operate the analog portions of the DAC including the voltage references, output amplifiers and control
amplifiers. The ± Vs supplies are designed to operate from
±5 V to ± 12 V. These supplies should be decoupled to analog
common using 0.1 ,...F capacitors. Good engineering practice
suggests that the bypass capacitors be placed as close as possible
to the package pins. This minimizes the parasitic inductive effects of printed circuit board traces.

DISTO~TION PERFORMANCE AND TESTING
The THD+ N figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. The THD+ N specification, therefore,
provides a direct method to classify and choose an audio DAC
for a desired level of performance. Figure I illustrates the typical THD+ N performance of the ADI864 versus frequency. A
load impedance of at least l.5 kG is recommended for best
THD+N performance.

Analog Devices tests and grades all AD 1864s on the basis of
THD + N performance. Ouring the distortion test, a high-speed
digital pattern generator transmits digital data to each channel of
the device under test. Eighteen-bit data is latched into the DAC
at 352.8 kHz (8 x Fs). The test waveform is a 990.5 kHz sine
wave with 0 dB, -20 dB and -60 dB amplitudes. A 4096 point
FFT calculates total harmonic distortion + noise, signal-to-noise
ratio, D-Range and channel separation. No deglitchers or MSB
trims are used.
OPTIONAL MSB ADJUSTMENT
Use of optional adjust circuitry allows residual distortion error
to be eliminated. This distortion is especially important when
low-amplitude signals are being reproduced. The MSB-adjust
circuitry is shown in Figure 8. The trim pot should be adjusted
to produce the lowest distortion using an input signal with a
-60 dB amplitude.

The ± VL supplies operate the digital portions of the chip including the input shift registers and the input latching circuitry.
These supplies should be bypassed to digital common using
0.1 ,...F capacitors. ± VL operates with ± 5 V to ± 12 V supplies.
In order to assure proper operation of the AD1864, -Vs must
be the most negative power supply voltage at all times.

Figure 8. Optional DIP THD+N Adjust Circuitry

5-48 AUDIO DIA CONVERTERS

REV. A

Digital Circuit Considerations - AD1864
CURRENT OUTPUT MODE

VOLTAGE OUTPUT MODES

One or both channels of the AD 1864 can be operated in current
output mode. lOUT can be used to directly drive an external
current-to-voltage (I-V) converter. The internal feedback resistor, R F, can still be used in the feedback path of the external
I-V converter, thus assuring that RF tracks the DAC over time
and temperature.

As shown in the ADI864 block diagram, each channel of the
ADI864 is complete with an I-V converter and a feedback resistor. These can be connected externally to provide direct voltage
output from one or both ADI864 channels. Figure 7 shows
these connections. lOUT is connected to the summing junction,
SJ. VOUT is connected to the feedback resistor, R F. This implementation results in the lowest possible component count and
achieves the performance shown on the specifications page while
operating at 8 x Fs.

Of course, the ADI864 can also be used in voltage output mode
utilizing the onboard I-V converter.

elK

Dl

DR

r

II

r

lR
Figure 9. AD1864 Control Signals

INPUT DATA

TIMING

Data is transmitted to the ADI864 in a bit stream composed of
I8-bit words with a serial, 2s complement, MSB first fonnat.
Data Left (DL) and Data Right (DR) are the serial inputs for
the left and right DACs, respectively. Similarly, Latch Left
(LL) and Latch Right (LR) update the left and right DACs.
The falling edges of LL and LR cause the last 18 bits which
were clocked into the Serial Registers to be shifted into the
DACs, thereby updating the DAC outputs. Left and Right
channels share the Clock (CLK) signal. Data is clocked into the
input registers on the rising edge of CLK.

Figure 10 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished properly. The input pins of the ADI864 are both TTL and 5 V
CMOS compatible.
The minimum clock rate of the ADI864 is at least 12.7 MHz.
This clock rate allows data transfer rates of 2 x, 4x, 8 x and
I6xFs (where Fs equals 44.1 kHz). The applications section of
this datasheet contains additional guidelines for using the
ADl864.

Figure 9 illustrates the general signal requirements for data
transfer for the AD1864.

eLK

LLlLR

INTERNAL DAC RECISTER
UPDATEP WITH 18110ST RECENT a1'8

I

•
~
NEXT

DlJDR
I

"-

(1 .... . "

WOAD

I

I

~

aTS CLOCKED
TOStlFT REGISTER

Figure 10. AD1864 Timing Diagram

REV. A

AUDIO DIA CONVERTERS 5-49

•

AD1864
+5V ANALOG SUPPLY

-$V ANALOG SUPPLY

LEFT
...-------~I_--l_- CHANNEL
OUTPUT
RIGHT

...--+-- CHANNEL
OUTPUT

+5V DIGITAL SUPPLY

-6V DIGITAL SUPPLY

Figure 11. Complete 8x Fs 18-8it CD Player

1S-BIT CD PLAYER DESIGN
Figure 11 illustrates an 18-bit CD player design incorporating an
ADI864 D/A converter, an AD712 or NESS32 dual opamp and
the SMS813 digital filter chip manufactured by NPC. In this
design, the SMS813 filter transmits left and right digital data to
both channels of the AD 1864. The left and right latch signals,
LL and LR, are both provided by the word clock signal
(WCKO) of the digital filter. The digital filter supplies data at
an 8 x F s oversample rate to each channel.
The digital data is converted to analog output voltages by the
output amplifiers on the AD1864. Note that no external components are required by the AD1864. Also, no deglitching circuitry is required.

5-50 AUDIO DIA CONVERTERS

An AD712 or NESS32 dual op amp is used to provide the output antialias filters required for adequate image rejection. One
2-pole filter section is provided for each channel. An additional
pole is created from the combination of the internal feedback
resistors (Rp) and the external capacitors CI and C2. For example, the nominal 3 kO Rp with a 360 pF capacitor for CI and
C2 will place a pole at approximately 147 kHz, effectively eliminating all high frequency noise components.
Close matching of the ac characteristics of the amplifiers on the
AD712 as well as their low distortion make it an ideal choice for
the task.
Low distortion, superior channel'separation, low power consumption and a low component count are all realized by this
simple design.

REV. A

Applications - AD1864
VOICE'
OUTPUT

VOICE 2
OUTPUT

VOICE 3
OUTPUT

VOICE'
OUTPUT

VOICE 5
OUTPUT

VOICE 6
OUTPUT

~V~~~-+------------------~+-----t----------------t-r-----r--------------~

~~~~p~-i---t---------------rt-----~~-------------i-+-----t,

ANALOG
COMMON

VOICE 6 LOAD

VOICE'LOAD

VOICE 2 LOAD

VOICES LOAD

VOICE 3 LOAD

VOICE 4 LOAD

DATA
CLOCK
DIGITAL COMMON

-5V DIGITAL COMMON
+5V DIGITAL COMMON

Figure 12. Cascaded AD 1864s in a Multichannel Keyboard
Instrument

MULTICHANNEL DIGITAL KEYBOARD DESIGN
Figure 12 illustrates how to cascade ADI864s to add multiple
voices to an electronic musical instrument. In this example, the
data and clock signals are shared between all six DACs. As the
data representing an output for a specific voice is loaded, the
appropriate DAC is updated. For example, after the 18 bits representing the next output value for Voice #4 is clocked out on
the data line, then "Voice 4 Load" is pulled low. This produces
a new output for Voice 4. Funhermore, all voices can be returned to the same output by pulling all six load signals low.
In this application, the advantages of choosing the ADI864 are
clear. Its flexible digital interface allows the clock and data to be
shared among all DACs. This reduces printed circuit board area
requirements and also simplifies the actual layout of the board.
The low power requirement of the ADI864 (typically 215 mW)
is an advantage in a mUltiple DAC system where its power advantage is multiplied by the number of DACs used. The

REV. A

ADI864 requires no external components, simplifying the design, reducing the total number of components required and
enhancing reliability.

ADDITIONAL APPLICATIONS
Figures 13 through 16 show connection diagrams for the
ADI864 and a number of standard digital filter chips from Yamaha, NPC and Sony. Figure 13 shows the SM5814AP operating with pipelined data. Cophase operation is not available with
the SM5814AP in 18-bit mode. Figures 14 through 16 are all
examples of cophase operation. Each application operates at
8 x F s for each channel. The 2-pole Rauch low pass filters
shown in Figure II can be used with all of the applications
shown in this data sheet. The AD711 single op amp can also be
used in these applicatiollti in order to ensure maximum channel
separation.

AUDIO DIA CONVERTERS 5-51

II

AD1864
~VANALOG

+5VANALOG

SUPPLY

SUPPLY

RIGHT

CHANNEL
OUTPUT

LEFT
CHANNEL
OUTPUT

.5VOIGITAL

~DIGITAL

SUPPLY

SUPPLY

Figure 13. AD1864 with NPC SM5814AP Digital Filter

-5VANALOG
SUPPLY

.SVANALOG
SUPPLY

RIGHT
CHANNEL
OUTPUT

LEFT
CHANNEL
OUTPUT

+SY DIGITAL
SUPPLY

-5V DIGITAL
SUPPLY

Figure 14. AD1864 with Yamaha YM3434 Digital Filter

5-52 AUDIO DIA CONVERTERS

REV. A

Applications-AD1864

RIGHT
CHANNEL
OUTPUT

LEFT
CHANNEL
OUTPUT

• SVDIGITAL
SUPPLY

-5VDIGITAL
SUPPLY

Figure 15. AD1864 with Sony CXD1244S Digital Filter

-SVANALOG
SUPPLY

.SVANALOG
SUPPLY

RIGHT
CHANNEL
OUTPUT

LEFT
CHANNEL
OUTPUT

.SVDIGITAL
SUPPLY

-SV DIGITAL
SUPPLY

Figure 16. AD1864 with NPC SM5818AP Digital Filter

REV. A

AUDIO DIA CONVERTERS 5-53

•

5-54 AUDIO DIA CONVERTERS

Complete Dual 18-Bit
16 x Fs Audio DAC
AD1865* I

11IIIIIIII ANALOG
WDEVICES
FEATURES
Dual Serial Input, Voltage Output DACs
No External Components Required
110dB SNR
0.003% THD+N
Operates at 16 x Oversampling per Channel
±5 Volt Operation
Cophased Outputs
116 dB Channel Separation
Pin Compatible with AD1864
DIP or SOIC Packaging
APPLICATIONS
Multichannel Audio Applications:
Compact Disc Players
Multivoice Keyboard Instruments
DAT Players and Recorders
Digital Mixing Consoles
Multimedia Workstations

PRODUCT DESCRIPTION
The ADI865 is a complete, dual 18-bit DAC offering excellent
THD+N and SNR while requiring no external components.
Two complete signal channels are included. This results in
cophased voltage or current output signals and eliminates the
need for output demultiplexing circuitry. The monolithic
AD1865 chip includes CMOS logic elements, bipolar and MOS
linear elements and laser-trimmed thin-film resistor elements, all
fabricated on Analog Devices' ABCMOS process.
The DACs on the ADIS65 chip employ a partially segmented
architecture. The first four MSBs of each DAC are segmented
into IS elements. The 14 LSBs are produced using standard
R-2R techniques. Segment and R-2R resistors are laser trimmed
to provide extremely low total harmonic distortion. This architecture minimizes errors at major code transitions resulting in
low output glitch and eliminating the need for an external
deglitcher. When used in the current output mode, the ADI865
provides two ± I rnA output signals.
Each channel is equipped with a high performance output amplifier. These amplifiers achieve fast settling and high slew rate,
producing ±3 V signals at load currents up to 8 rnA. Each output amplifier is short-circuit protected'and can wi.thstand indefinite short circuits to ground.
The AD 1865 was designed to balance two sets of opposing requirements, channel separation and DAC matching. High channel separation is the result of careful layout. At the same time,
both channels of the AD1S65 have been designed to ensure
matched gain and linearity as well as tracking over time and
temperature. This assures optimum perfortnance when used in
stereo and multi-DAC per channel applications.

FUNCTIONAL BLOCK DIAGRAM
(DIP Package)
+Vs
TRIM
MSB
lOUT
AGND

SJ
RF

VOUT
NC
DR

Dl

LR

II
DGND

ClK
NC = NO CONNECT

A versatile digital interface allows the AD1865 to be directly
connected to standard digital filter chips. This interface employs
five signals: Data Left (DL), Data Right (DR), Latch Left
(LL), Latch Right (LR) and Clock (CLK). DL and DR are the
serial input pins for the left and right DAC input registers. Input data bits are clocked into the input register on the rising
edge of CLK. A low-going latch edge updates the respective
DAC output. For systems using only a single latch signal, LL
and LR may be connected together. For systems using only one
DATA signal, DR and DL may be connected together.
TheADI865 operates with ±5 V power supplies. The digital supply, VL> can be separated from the analog supplies, Vsand - Vs,
for reduced digital feedthrough. Separate analog and digital
ground pins are also provided. The AD 1865 typically dissipates
only 225 mW, with a maximum power dissipation of 260 m W.
The ADI865 is packaged in both a 24-pin plastic DIP and a
2S-pin SOIC package. Operation is guaranteed over the temperature range of - 25°C to + 70°C and over the voltage supply
range of ±4.75 V to 0:5.25 V.

PRODUCT HIGHLIGHTS
1. The AD1S65 is a Complete Dual IS-Bit Audio DAC.
2. 110 dB Signal-To-Noise Ratio for low noise operation.
3. THD+ N is typically 0.003%.
4. Interchannel gain and midscale matching.
5. Output voltages and currents are cophased.
6. Low glitch for improved sound quality.
7. Both channels are 100% tested at 16 x Fs.
S. Low Power-only 225 mW typ, 260 mW max.
9. Five-wire interface for individual DAC control.
10. 24-pin DIP or 28-pin SOIC packages available.

"Protected by U.S. Patents Nos.: RE 30,586; 3,961,326; 4,141,004;
4,349,811; 4,855,618. 4,857,862.

REV. 0

AUDIO DIA CONVERTERS 5-55

II

.'JIONS = +25°C,or deghtcher)
= +Vs = +5 Vand -Vs = -5 V, Fs = 105.6 kHz, no MSB
AD1865 - SPECIFIC"adJustment
(lA.

Parameter

+V~

Min

RESOLUTION
DIGITAL INPUTS

VIH
VIL
IIH' VIH = +VL
IlL' VIL = 0.4 V
Clock Input Frequency

Typ

Max

Unit

18
2.0

Bits
V
V
/LA

+VL
0.8
1.0

-10

!LA

13.5

MHz

ACCURACY
Gain Error
Interchannel Gain Matching
Midscale Error
Interchannel Midscale Matching
Gain Linearity (0 dB to -90 dB)

0.2
0.3
4
5
<2

DRIFT (O°C to + 70°C)
Gain Drift
Midscale Drift

±25
±4

TOTAL HARMONIC DISTORTION + NOISE*
ADl865N, R
o dB, 990.5 Hz
ADl865N-J, R-J
-20 dB, 990.5 Hz AD1865N, R
ADl865N-J, R-J
-60 dB, 990.5 Hz ADl865N, R
ADl865N-J, R-J

0.004
0.003
0.010
0.010
1.0
1.0

1.0
0.8

%ofFSR
% ofFSR
mV
mV
dB
ppm of FSRI"C
ppm of FSRI"C

0.006
0.004
0.040
0.020
4.0
2.0

%
%
%
%
%
%

CHANNEL SEPARATION*
o dB, 990.5 Hz

lIO

116

dB

SIGNAL-TO-NOISE RATIO* (20 Hz to 30 kHz)

107

110

dB

D-RANGE* (with A-Weight Filter)
-60 dB, 990.5 Hz ADl865N, R
ADl865N-J, R-J

88
94

100
100

dB
dB

±2.94

±3.0
0.1

OUTPUT
Voltage Output Configuration
Output Range (± 1%)
Output Impedance
Load Current
Short Circuit Duration
Current Output Configuration
Bipolar Output Range (±30%)
Output Impedance (±30%)
POWER SUPPLY
+VL and +Vs
-Vs
+1, +VL and +Vs = +5 V
-I, -Vs = -S V

±3.06

V
0

rnA

±8
Indefinite to Common

rnA
kO

±I
1.7
4.75
-5.25

POWER DISSIPATION, +VL = +Vs = +5 V, -Vs = -S V
TEMPERATURE RANGE
Specification
Operation
Storage

0
-25
-60

WARMUP TIME

I

I

5.0
-5.0
22
-23

5.25
-4.75
26
-26

225

260

mW

+25

+70
+70
+100

°C
°C
°C

V
V
rnA
rnA

min

Specifications shown in boldface are tested on production units at final test without optional MSB adjustment.
*Tested in accordance with EIAJ Test Standard CP-307 with 18-bit data.
Specifications subject to change without notice.

5-56 AUDIO DIA CONVERTERS

REV. 0

A01865
*Stresses greater than those listed under "Absolute Maximum Ratings" may
ABSOLUTE MAXIMUM RATINGS*
cause permanent damage to the device. This is a stress rating only and
VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 6.0 V
functional operation of the device at these or any other conditions above those
Vs to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 6.0 V
indicated in the operational section of this specification is not implied.
-Vs to AGND . . . . . . . . . . . . . . . . . . . . . . . -6.0 to 0 V
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . -0.3 to V L
Short Circuit Protection . . . . . . . . Indefmite Short to Ground
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C, 10 sec
CAUTION _________________________________________________

ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, pertnanent damage may occur on unc,onnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are removed.
PINOUT
(24-Pin DIP Package)

ORDERING GUIDE
Model

Temperature
Range

ADl86SN
ADI86SN-J
AD186SR
AD I 865R-J

- 25°C
- 25°C
- 25°C
-25°C

to
to
to
to

THD+N@FS

+ 70°C
+ 70°C
+ 70°C
+70°C

*N = Plastic DIP, R = Small Oudine
see Package Information section.

0.006%
0.004%
0.006%
0.004%

Ie Package.

Package
Option*
N-24
N-24
R-28
R-28

For outline information

+Vs

TRIM
RIGHT
CHANNEL

TRIM
MSB

MSB

lOUT

AGND

AGND

SJ

SJ
RF

PIN DESIGNATIONS

RF

VOUT

VOUT

NC

DIP SOiC
1
2
3
4
5
6
7
8
9

10
11

12
13
14
IS
16
17
18
19
20
21
22
23
24

22
23
24

LEFT
CHANNEL

-Vs
TRIM
MSB

Negative Analog Supply
Right Channel Trim Network Connection
Right Channel Trim Potentiometer
Wiper Connection
26
Right Channel Output Current
lOUT
28
AGND Analog Common Pin
I
Right Channel Amplifier Summing Junction
SJ
2
Right Channel Feedback Resistor
RF
VOUT Right Channel Output Voltage
3
4
Positive Digital Supply
+VL
5
DR
Right Channel Data Input Pin
6
LR
Right Channel Latch Pin
7
CLK
Clock Input Pin
8
DGND Digital Common Pin
9
LL
Left Channel Latch Pin
10
DL
Left Channel Data Input Pin
11, 16, 18 NC
No Internal Connection *
25,27
12
VOUT Left Channel Output Voltage
13
Left Channel Feedback Resistor
RF
14
Left Channel Amplifier Summing Junction
SJ
IS
AGND Analog Common Pin
17
Left Channel Output Current
lOUT
19
MSB
Left Channel Trim Potentiometer
Wiper Connection
20
TRIM Left Channel Trim Network Connection
21
Positive Analog Supply
+Vs

*Pin 16 has no internal connection; -VL from ADI864 DIP socket can be safely applied.

DR

DL

LR

LL
DGND
NC = NO CONNECT

(28-Pin SOiC Package)

DGND
LL

SJ
NC = NO CONNECT

REV. 0

AUDIO DIA CONVERTERS 5-57

II

AD1865-Definition of Specifications
TOTAL HARMONIC DISTORTION + NOISE
Total harmonic distortion plus noise (THD+ N) is defined as
the ratio of the square root of the Sl'm of the squares of the amplitudes of the harmonics and noise ,,' the value of the fundamental input frequency. It is usually expressed in percent.
THD+ N is a measure of the magnitude and distribution of linearity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depending on the amplitude of the output signal. Therefore, to be most
useful, THD+ N should be specified for both large (0 dB) and
small (-20 dB, -60 dB) signal amplitudes. THD+N measurements for the ADI865 are made using the first 19 harmonics
and noise out to 30 kHz.
SIGNAL-TO-NOISE RATIO
The signal-to-noise ratio is defined as the ratio of the amplitude
of the output when a full-scale code is entered to the amplitude
of the output when a midscale code is entered. It is measured
using a standard A-Weight fllter. SNR for the AD1865 is measured for noise components out to 30 kHz.
CHANNEL SEPARATION
Channel separation is defined as the ratio of the amplitude of a
full-scale signal appearing on one channel to the amplitude of
that same signal which couples onto the adjacent channel. It is
usually expressed in dB. For the AD 1865 channel separation
is measured in accordance with EIAJ Standard CP-307, Section
5.5.
D-RANGE DISTORTION
D-Range distortion is equal to the value of the total harmonic
distortion + noise (THD+ N) plus 60 dB when a signal level of
-60 dB below full scale is reproduced. D-Range is tested with a
1 kHz input sine wave. This is measured with a standard
A-Weight fllter as specified by EIAJ Standard CP-307.
GAIN ERROR
The gain error specification indicates how closely the output of a
given channel matches the ideal output for given input data. It
is expressed in % of FSR and is measured with a full-scale output signal.
INTERCHANNEL GAIN MATCHING
The gain matching specification indicates how closely the amplitudes of the output signals match when producing identical input data. It is expressed in % of FSR (Full-Scale Range ~ 6 V
for the AD1865) and is measured with full-scale output signals.
MIDSCALE ERROR
Midscale error is the deviation of the actual analog output of a
given channel from the ideal output (0 V) when the twos complement input code representing half scale is loaded into the input register of the DAC. It is expressed in mV and is measured
with half-scale output signals.

INTERCHANNEL MIDSCALE MATCHING
The midscale matching specification indicates how closely the
amplitudes of the output signals of the two channels match
when the twos complement input code representing half scale is
loaded into the input register of both channels. It is expressed in
mV and is measured with half-scale output signals.
FUNCTIONAL DESCRIPTION
The ADI865 is a complete, monolithic, dual 18-bit audio DAC.
No external components are required for operation. As shown in
the block diagram, each chip contains two voltage references,
two output amplifiers, two 18-bit serial input registers and two
18-bit DACs.
The voltage reference section provides a reference voltage for
each DAC circuit. These voltages are produced by low-noise
bandgap circuits. Buffer amplifiers are also included. This combination of elements produces reference voltages that are unaffected by changes in temperature and age.
The output amplifiers use both MOS and bipolar devices and
incorporate an all NPN output stage. This design technique produces higher slew rate and lower distortion than previous techniques. Frequency response is also improved. When combined
with the appropriate on-chip feedback resistor, the output op
amps convert the output current to output voltages.
The 18-bit D/A converters use a combination of segmented decoder and R-2R architecture to achieve consistent linearity and
differential linearity. The resistors which form the ladder structure are fabricated with silicon chromium thin fllm. Laser trimming of these resistors further reduces linearity errors resulting
in low output distortion.
The input registers are fabricated with CMOS logic gates. These
gates allow the achievement of fast switching speeds and low
power consumption, contributing to the low glitch and low
power dissipation of the AD1865.

-Vs

+Vs

TRIM

TRIM

MSB

MSB

lOUT

lOUT

AGND

AGND

SJ

SJ

RF

RF

VOUT

VOUT

+VL

NC

DR

Dl

lR

II

ClK

DGND
NC

= NO CONNECT

AD1865 Block Diagram (DIP Package)

5-58 AUDIO DIA CONVERTERS

REV. 0

Typical Performance Data -AD18S5
100

ID

...

I
I
I

I

""- I"--

ID

-

Z

~

...

OdB_

-

'"

90

120

110

I

z

o

~

~

100

rn

.......

""- .......

a:

...J

w

80

Z

z

;!

o

8

4

80

16

12

...........

90

o
70

-

o

4

FREQUENCY - kHz

8

12

16

FREQUENCY - kHz

Figure 1. THD+N (dB) vs. Frequency (kHz)

Figure 2. Channel Separation (dB) vs. Frequency (kHz)

•

10

r~OdB

.1

.01

.:L

-20dB

.001
-30 -20 -10

_

OdB
I

0

10

20

30

40

50

60

70

80

90

TEMPERATURE _ °C

Figure 3. THD+N (%) vs. Temperature rOC)

10

100

8

90

6
4

...

80

Z

70

ID

2

Z

+

0

:E:
I-

-2

ID
I

I

+

Q

...

r-.......

Q

:E:
I-

60

-4
-6

50
-6
40

0

500

1000

1500

2000

2500

3000

LOAD RESISTANCE - Q

Figure 4. THD+N (dB) vs. Load Resistance (ll)

REV. 0

-10
-100 -90 -60 -70 -60 -50 -40 -30 -20 -10

0

INPUT AMPLITUDE - dB

Figure 5. Gain Linearity (dB) vs. Input Amplitude (dB)

AUDIO DIA CONVERTERS 5-59

AD1865-Analog Circuit Consideration
GROUNDING RECOMMENDATIONS
The ADI865 has three ground'pins, two labeled AGND and
one labeled DGND. AGND, the analog ground pins, are the
"high quality" ground references for the device. To minimize
distortion and reduce crosstalk between channels, the analog
ground pins should be connected together only at the analog
common point in the system. As shown in Figure 6, the AGND
pins should nor be connected at the chip.

be connected to the single + 5 V power supply. This feature allows reduction of the cost and complexity of the system power
supply.
As with most linear circuits, changes in the power supplies will
affect the output' of the DAC. Analog Devices recommends that
well regulated power supplies with less than I % ripple be incorporated into the design of an audio system.

DISTORTION PERFORMANCE AND TESTING
The THD + N figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. The THD+ N specification, therefore,
provides a direct method to classify and choose an audio DAC
for a desired level of performance. Figure I illustrates the typical THD+ N performance of the ADI865 versus frequency. A
load impedance of at least 1.5 kO is recommended for best
THD+N performance.

-I

VOUT--....

H~--VOUT

DIGITAL --._-l
SUPPLY

Analog Devices tests and grades all ADI865s on the basis of
THD+N performance. During the distortion test, a high-speed
digital pattern generator transmits digital data to each channel of
the device under test. Eighteen-bit data is transmitted at
705.6 kHz (16 x Fsl. The test waveform is a 990.5 Hz sine
wave with 0 dB, -20 dB and -60 dB amplitudes. A 4096 point
FFT calculates total harmonic distortion + noise, signal-to-noise '
ratio, D-Range and channel separation. No deglitchers or MSB
trims are used in the testing of the AD1865.

DIGITAL

COMMON

Figure 6. Recommended Circuit Schematic

The digital ground pin returns ground current from the digital
logic portions of the ADI865 circuitry. This pin should be connected to the digital common pin in the system. Other digital
logic chips should also be referred to that point. The analog and
digital grounds should be connected together at one point in the
system, preferably at the power supply.

OPTIONAL MSB ADJUSTMENT
Use of optional adjust circuitry allows residual distortion error
to be eliminated. This distortion is especially important when
low amplitude signals are being reproduced. The MSB adjust
circuitry is shown in Figure 7. The trim potentiometer should
be adjusted to produce the lowest distortion using an input signal with a -60 dB amplitude.

POWER SUPPLIES AND DECOUPLING
The ADl865 has three power supply input pins. :tVs provides
the supply voltages which operate the analog portions of the
DAC including the voltage references, output amplifiers and
control amplifiers. The :t Vs supplies are designed to operate
from :t5 V supplies. Each supply should be decoupled to analog
common using a 0.1 ",F capacitor in parallel with a 10 ",F capacitor. Good engineering practice suggests that the bypass capacitors be placed as close as possible to the package pins. This
minimizes the parasitic inductive effects of printed circuit board
traces.
The + VL supply operates the digital portions of the chip including the input shift registers and the input latching circuitry.
This supply should be bypassed to digital common using a
0.1 ",F capacitor in parallel with a 10 ",F capacitor. + VL operates with a + 5 V supply. In order to assure proper operation of
the AD1865, -Vs must be the most negative power supply voltage at all times.
Though separate positive power supply pins are provided for
the analog and digital portions of the AD 1865, it is also possible
to use the AD 1865 in systems featuring a single + 5 V power
supply. In this case, both the +Vs and +VL input pins should

5-60 AUDIO DIA CONVERTERS

Figure 7. Optional THD+N Adjust Circuitry

REV. 0

Digital Circuit Considerations - AD18S5
CURRENT OUTPUT MODE
One or both channels of the AD 1865 can be operated in current
output mode. louT can be used to directly drive an external
current-to-voltage (I-V) converter. The internal feedback resistor, RF, can still be used in the feedback path of the external
I-V converter, thus assuring that RF tracks the DAC over time
and temperature.
Of course, the AD1865 can also be used in voltage output mode
in order to utilize the onboard I-V converter.

VOLTAGE OUTPUT MODES
As shown on the block diagram, each channel of the ADI865 is
complete with an I-V converter and a feedback resistor. These
can be connected externally to provide direct voltage output
from one or both AD1865 channels. Figure 6 shows these connections. lOUT is connected to the Summing Junction, SJ.
VOUT is connected to the feedback resistor, RF. This implementation results in the lowest possible component count and
achieves the specifications shown on the Specifications page
while operating at 16 x Fs.

elK

Dl

DR

II

II

lR

Figure 8. AD1865 Control Signals

INPUT DATA
Data is transmitted to the AD 1865 in a bit stream composed of
18-bit words with a serial, twos complement, MSB first format.
Data Left (DL) and Data Right (DR) are the serial inputs for
the left and right DACs, respectively. Similarly, Latch Left
(LL) and Latch Right (LR) update the left and right DACs.
The falling edge of LL and LR cause the last 18 bits which
were clocked into the Serial Registers to be shifted into the
DACs, thereby updating the DAC outputs. Left and Right
channels share the Clock (CLK) signal. Data is clocked into the
input registers on the rising edge of CLK.

TIMING
Figure 9 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished properly. The input pins of the AD1865 are both TTL and 5 V
CMOS compatible.
The minimum clock rate of the ADI865 is at least 13.5 MHz.
This clock rate allows data transfer rates of 2 x, 4 x, 8 x and
16 x Fs (where Fs equals 44.1 kHz).

Figure 8 illustrates the general signal requirements for data
transfer for the AD 1865.
:.74.1nl

ClK

lLllR

-----+------+----{J:.....oUifLoLJI

DllDR

"

"
~ TO
BITS CLOCKED
....-----===========
SHIFT REGISTER

Figure 9. AD1865 Timing Diagram

REV. 0

AUDIO DIA CONVERTERS 5-61

AD1865
-sv ANALOG SUPPLY

.sv ANALOG SUPPLY

...-______+ __+_ LEFT
CHANNEL
OUTPUT

RIGHT

...--+-- CHANNEL
OUTPUT

+SV DIGITAL SUPPLY

Figure 10. Complete 8 x Fs 18-Bit CD Player

IS-BIT CD PLAYER DESIGN
Figure 10 illustrates an 18-bit CD player design incorporating an
ADI865 D/A converter, an NE5532 dual op amp and the
SM5813 digital filter chip manufactured by NPC. In this design,
the SM5813 filter transmits left and right digital data to both
channels of the AD1865. The left and right latch signals, LL
and LR, are both provided by the word clock signal (WCKO) of
the digital filter. The digital filter supplies data at an 8 x F s
oversample rate to each channel.

The digital data is converted to analog output voltages by the
output amplifiers on the AD1865. Note that no external components are required by the AD1865. Also, no deglitching circuitry is required.

5-62 AUDIO DIA CONVERTERS

An NE5532 dual op amp is used to provide the output antialias
filters required for adequate image rejection. One 2-pole filter
section is provided for each channel. An additional pole is created from the combination of the internal feedback resistors
(RF) and the external capacitors Cl and C2. For example, the
nominal 3 kG RF with a 360 pF capacitor for Cl and C2 will
place a pole at approximately 147 kHz, effectively eliminating all
high frequency noise components.
Low distortion, superior channel separation, low power consumption and a low parts count are all realized by this simple
design.

REV. a

AD1865
MULTICHANNEL DIGITAL KEYBOARD DESIGN
Figure 11 illustrates how to cascade AD186S's to add multiple
voices to an electronic musical instrument. In this example, the
data and clock signals are shared between all six DACs. As the
data representing an output for a specific voice is loaded, the
appropriate DAC is updated. For example, after the 18-bits representing the next output value for Voice 4 is clocked out on the
data line, then "Voice 4 Load" is pulled low. This produces a
new output for Voice 4. Furthermore, all voices can be returned
to the same output by pulling all six load signals low.

VOleEl

VOICE 2
OUTPUT

OUTPUT
.5V~~~~~-+

In this application, the advantages of choosing the AD1865 are
clear. Its flexible digital interface allows the clock and data to be
shared among all DACs. This reduces PC board area requirements and also simplifies the actual layout of the board. The
low power requirements of the ADI865 (approximately
225 mW) is an advantage in a multiple DAC system where any
power advantage is multiplied by the number of DACs used.
The ADl86S requires no external components, simplifying the
design, reducing the total number of components required and
enhancing reliability.

__________________

~+-

VOICE 3
VOICE 4
VOICE 5
VOICE 6
OUTPUT
OUTPUT OUTPUT
OUTPUT
____
______________
____
______________- - ,
~

~~

~

-5V~~~~~-t---'--------------~~-----r'-------------~~-----+,

•

ANALOG
COMMON

VOICE 1 LOAD

VOICE HOAD

VOICE 6 LOAD

-.w~---=====~...jJ

VOICE3LOAD-~-+--------------~--~~

w---,=====:..-t-i--

'-~+-~---------------+~--

VOICE 5 LOAD
VOICE 4 LOAD

DATA -~~--------------~---4~--r-------------~~--~~~--------------~
CLOCK-+-~--------------~----~~~------------~~--~~~

r-.....----j-----------------....----+--------------------- DIGITAL COMMON
'-----------------------.....-----------------------4----------------------- .5V DIGITAL SUPPLY

Figure 11. Cascaded AD 1865s in a Multichannel Keyboard
Instrument

REV. 0

AUDIO DIA CONVERTERS 5-63

AD1865
ADDITIONAL APPLICATIONS
Figures 12 through 14 show connection diagrams for the
AD1865 and standard digital filter chips from Yamaha, NPC
and Sony. Each figure is an example of cophase operation operating at 8 x Fs for each channel. The 2-pole Rauch low pass
filters shown in Figure 10 can be used with all of the applications shown in this data sheet.

-5V ANALOG
SUPPLY

.SV ANALOG
SUPPLY

RIGHT
CHANNEL
OUTPUT

L"EFT
CHANNEL
OUTPUT

.SV DIGITAL SUPPLY

Figure 72. AD7865 with Yamaha YM3434 Digital Filter

RlGIIT
CHANNEL
OUTPUT

LEFT
CHANNEL
OUTPUT

-5VANALOG
SUPPLY

.SV ANALOG
SUPPLY

RIGHT
CHANNEL
OUTPUT

LEFT
CHANNEL

.SV DIGITAL SUPPLY

OUTPUT

Figure 73. AD7865 with Sony CXD7244s Digital Filter

+5V DIGITAL SUPPLY

Figure 14. AD1865 with NPC SM5818AP Digital Filter

5-64 AUDIO DIA CONVERTERS

REV. 0

r.ANALOG
WDEVICES
FEATURES

Single Supply
Dual 16-Bit Audio OAe
A01866* I
FUNCTIONAL BLOCK DIAGRAM

Dual Sarlal Input, Voltage Output DACs
Singla +5 Volt Supply
0.005% THD+N
Low Power-45 mW
115 dB Channel Separation
Openrtlls at 8)( Ove,.ampling
16-Pln Plestic DIP or SOIC Packaga

Vs

APPUCAnONS
Multimedia Workstations
PC Audio Add-In Boards
Portable CD and DAT Playe,.
Automotive CD and DAT Players
Noise Cancellation

PRODUCT DESCRIPTION
The ADI866 is a complete dual 16-bit DAC offi
ent
performance while requiring a single + 5 V power supply. It is
fabricated on Analog Devices' ABCMOS wafer fabrication process. The monolithic chip includes CMOS logic elements,
bipolar and MOS linear elements and laser trimmed, thin flim
resistor elements. Careful design and layout techniques have
resulted in low distortion, low noise, high channel separation
and low power dissipation.
The DACs on the ADI866 chip employ a partially segmented
architecture. The fll'St three MSBs of each DAC are segmented
into 7 elements. The 13 LSBs are produced using standard
R-2R techniques. The segments and R-2R resistors are laser
trimmed to provide extremely low total harmonic distortion.
The ADI866 requires no deglitcher or trimming circuitry.
Each DAC is equipped with a high performance output amplifier. These amplifiers achieve fast settling and high slew rate,
producing ± 1 V signals at load currents up to ± 1 mAo The
buffered output signal range is 1.5 V to 3.5 V. The 2.5 V reference voltages eliminate the need for "false ground" networks.
A versatile digital interface allows the ADl866 to be directly
connected to all digital filter chips. Fast CMOS logic elements
allow for an input clock rate of up to 16 MHz. This allows for
operation at 2 x, 4 x, 8 x, or 16 x the sampling frequency
(where Fs = 44.1 kHz) for each channel. The digital input pins
of the ADl866 are TIL and + 5 V CMOS compatible.

HRL
AGHD

HRR

II
The ADI866 operates on +5 V power supplies. The digital supply, VL , can be separated from the analog supply, Vs , for
reduced digital feedthrough. Separate analog and digital ground
pins are alsO provided. In systems employing a single + 5 volt
power supply, VL and Vs should be connected together. In battery operated systems, operation will continue even with
reduced supply voltage. Typically, the ADI866 dissipates
45mW.
The ADl866 is packaged in either a 16-pin plastic DIP or a
16-pin plastic SOIC package. Operation is guaranteed over the
temperature range of - 35°C to + 85°C and over the voltage supply range of 4.75 V to 5.25 V.
PRODUCT HIGHUGHTS
1. Single supply operation @ +5 V.
2. 45 mW power dissipation.
3. THD+N is 0.005% (typical).
4. Signal-ta-Noise Ratio is 95 dB (typical).
5. 115 dB channel separation (typical).
6. Compatible with all digital filter chips.
7. 16-pin DIP and 16-pin SOIC packages.
8. No deglitcher required.
9. No external adjustments required.

·Protected by U.S. Pateat Nos: 3,961,326; 4,141,004; 4,349,811; 4,857,862;
IUId patents ~.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

REV. 0

AUDIO DIA CONVERTERS 5-65

AD1866 ....... SPECIFICATIONS

(T.

=25"C and +5 Vsupplies unlass otherwisa. noted)
Min

Typ

Max

16

RESOLUTION
DIGITAL INPUTS Vm
V1L
1m , Vm = VL
IlL' VIL = DGND
Maximum Clock Input Frequency

2.4
0.8

MHz

13.5
±3
±3
±30

%,ofFSR
%ofFSR
mV
mV
dB

DRIFr (O"C to 7O"C)
Gain Drift
Midscale Drift

ppmf'C

jJ.vrc

TOTAL HARMONIC DISTORTION + NOISE
o dB, 990.5 Hz
ADl866N
ADl866R
-20 dB, 99O.5/Hz ADI866N
ADI866R
-60 dB, 990.5 Hz ADI866N
ADI866R
CHANNEL SEPARATION

V
V

!LA
!LA

1.0
-10.0

ACCURACY
Gain Error
Gain Matching
Miscale Error
Midscale Error Matching
Gain Linearity Error

Vait
Bits

0.01
0.01

I kHz, 0 dB

115

%
%
%
%
%
%
dB

SIGNAL-TO-NOISE RATIO (with A-Weight Filter)

95

dB

D-RANGE (with A-Weight Filter)

90

dB

±l
0.1
±I

V

mA

+2.5
350

n

OUTPUT
Voltage OutpUt Pins (VOL' VorJ
Output Rauge (±3%)
Output Impedance
Load Current
Bias VoltBge Pins (VBL' VBrJ
OutpUt Rauge
Output Impedance
POWER SUPPLY
Specification, VL aDd V s
Operation, VL and Vs
+1, VLandVs = 5V
POWER DISSIPATION
TEMPERATURE RANGE
Operation
Storage

4.75
3.5

-35
-60

5

n

V

9

5.25
5.25
13

V
V
mA

45

65

mW

85
100

"C
"C

Specifications subject to cbanse without notice.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

5-66 AUDIO DIA CONVERTERS

REV. 0

-.ANALOG
WDEVICES
FEATURES
Dual Sariallnput, Voltage Output DACs
Single +5 V Supply
0.004% THD+N (typical)
Low Power: 50 mW (typical)
>115 dB Channel Separation (typical)
Operates at ax Oversampling
16-Pln Plastic DIP or SOIC Package

Single Supply
Oual18-Bit Audio OAC
A01868* I
FUNCTIONAL BLOCK DIAGRAM

APPUCAnONS
Portable Compact Disc Players
Portable DAT Players and Recorders
Automotive Compact Disc Players
Automotive DAT Players
Multimedia Workstations

PRODUCT DESCRIPTION
The ADI868 is a complete dual 18-bit DAC offering excellent
performance while requiring a single + 5 V power supply. It is
fabricated on Analog Devices' ABCMOS wafer fabrication process. The monolithic chip includes CMOS logic elements, bipolar and MOS linear elements, and laser-trimmed thin-fUm
resistor elements. Careful design and layout techniques have
resulted in low distortion, low noise, high channel separation,
and low power dissipation.
The DACs on the ADI868 chip employ a partially segmented
architecture. The first three MSBs of each DAC are segmented
into seven elements. The 15 LSBs are produced using standard
R-2R techniques. The segments and R-2R resistors are lasertrimmed to provide extremely low total harmonic distortion.
The ADI868 requires no deglitcher or trimming circuitry.

Each DAC is equipped with a high performance output amplifier. These amplifiers achieve fast settling and high slew rate,
producing ± I V signals at load currents up to ± I mAo The
buffered output signal range is 1.5 V to 3.5 V. Reference voltages of 2.5 V are provided, eliminating the need for "False
Ground" networks.
A versatile digital interface allows the ADl868 to be directly
connected to all digital filter chips. Fast CMOS logic elements
allow for an input clock rate of up to 13.5 MHz. This allows for
operation at 2x, 4x, 8x, or 16x the sampling frequency
(where Fs equals 44.1 kHz) for each channel. The digital input
pins of the ADl868 are TTL and +5 V CMOS compatible.

II
The ADI868 operates on +5 V power supplies. The digital supply, VL> can be separated from the analog supply, Vs' for
reduced digital feedthrough. Separate analog and digital ground
pins are also provided. In systems employing a single +5 volt
power supply, VL and Vs should be connected together. In
battery-operated systems, operation will continue even with
reduced supply voltage. Typically, the ADI868 dissipates
SOmW.
The AD 1868 is packaged in either a 16-pin plastic DIP or a
16-pin plastic SOIC package. Operation is guaranteed over the
temperature range of -3S"C to +85°C and over the voltage supply range of 4.75 V to 5.25 V.
PRODUCT HIGHLIGHTS
I. Single-supply operation @ + 5 V
2. SO mW power dissipation (typical)
3. THD+N is 0.004% (typical)
4. Signal-to-Noise Ratio is 97.5 dB (typical)
5. > 115 dB channel separation (typical)
6. Compatible with all digital filter chips
7. 16-pin DIP and 16-pin SOIC packages
8. No deglitcher required
9. No external adjustments required

·Protected by u.s. Pateata Numben: 3,961,326; 4,141,004; 4,349,811;
4,857,862; ucI pIdeIl18 peadiaa.

REV. A

AUDIO DIA CONVERTERS 5-67

AD1868-SPECIFICATIONS

(TA

= +25°C and +5 Vsupplies unless otherwise noted)
Min

RESOLUTION

Typ

Mas

18

DIGITAL INPUTS

Vm
VIL
IIH' Vm = VL
IlL, VIL = DGND
Maximum Clock Input Frequency

Bits

2.4
0.8

V
V

!IA
!IA

1.0
1.0

Mllz

13.5

ACCURACY
Gain Error
Gain Matching
Midscale Error
Midscale Error Matching
Gain Linearity Error

Units

±1
±1
±15
±10
±3

dB

±100
±100

ppmf'C
JLVre

% ofFSR

% ofFSR
mV
mV

DRIFT (OOC to +700c)

Gain Drift
Midscale Drift
TOTAL HARMONIC DISTORTION + NOISE
o dB, 990.5 Hz
AD1868N, R
ADl868N-J, R-J
-20 dB, 990.5 Hz

ADl868N, R
ADl868N-J, R-J

-60 dB, 990.5 Hz ADl868N, R
ADl868N-J, R-J

0.004
0.004

0.008
0.006

%
%

0.020
0.020

0.08
0.08

%
%

2.0
2.0

5.0
5.0

%
%

CHANNEL SEPARATION 1 kHz, 0 dB

108

>115

SIGNAL-TO-NOISE RATIO (with A-Weight Filter)

9S

97.5

D-RANGE (with A-Weight Filter)

86

92

OUTPUT
Voltage Output Pins (VoL, VoR)
Output Range (±3%)
Output Impedance
Load Current
Bias Voltage Pins (VBL, VBR)
Output Voltage
Output Impedance
POWER SUPPLY
Specification, VL and V s
Operation, VL and V s
+1, V L and Vs = 5 V
POWER DISSIPATION
TEMPERATURE RANGE
Operation
Storage

dB
dB
dB

V

±1
0.1
±1

n
mA

+2.5
350
4.75
3.5

V

n

10

S.2S
5.25
14

mA

50

70

mW

85
100

"C
"C

5

-35

-60

V

V

Specifications subject to chapge witbout notice.
·Stresses greater than tbOse listed under "Absolute MaximUm Ratings" may
ABSOLUTE MAXIMUM RATINGS·
cause permanent damaIe to tbe device. This is a suess rating only and
V L to DGND . . . . . . . . . . . . . . . • . . . . . . . . . . . 0 to 6 V
functional operation of tbe device at tbese or any olber conditions above tbose
Vs to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 6 V
indicated in tbe operational section of tbis specification is not implied.
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Exposure to absolute maximum rating conditions for extended periods may
Digital Inputs to DGND . . . . . . . . . . . . . . . . . -0.3 to VL
affect device reliability.
Soldering • . . . . . . . . . . . . . . . . . . . . . . . . . 3000c, 10 sec
CAUTION _________________________________________________

ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high 'energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are removed.

5-68 AVDIO DIA CONVERTERS

REV. A

AD1868
Typical Performance of the AD1868
-30

t-

-60dB -

-40

I--

140 H-++----jL..-+--+-++---+--_
_


rg
I

z
o

-50

...

~ 130r+-+~-~--+--+-+~--+--~

III

-60

I

z+

20dB._ f - -

~ -70

-

-80
-90

z

-IOdBI- f - -

-100

M

~

U

~

~

m 120H-+~--4--+--+-++--+---I-I

iilz

o«

110H-++----j~-+-_+-++---+--_I_I

U1Ml~lUl~lU~5

104

FREQUENCY - kHz

FREQUENCY - Hz

Figure 1. THD+N vs. Frequency

Figure 2. Channel Separation vs. Frequency

-6~B

...

6

a:

4

-50

ffi

z

+

~

2

~ -60

w

-30

III
I

-40

...,

II

8

-20

li!

III

~

~

~

-80

t\.\
25"C' \

0

Z

-2OdB

-70

I\o·c

-2

-4

" b-..
r,/

V

I~o·c

OdS

-90
4.4

5.0

4.8

4.6

5.2

-6
-100

5.4

-80

-60

-20 -10

-40

0

INPUT AMPLITUDE - dB

VOLTAGE SUPPLY

Figure 4. Gain Linearity Error vs. Input Amplitude

Figure 3. THD+N vs. Supply Voltage

90

y

-20

80

60dS

"-....

-40

...
III

C

-~
f---idS

%
....

-t-- r-

-100
-50 -30 -10

10

30

50

70

~

90

:e

60

l'

['\.

TEMPERATURE - 'C

I\.

"

50
f--

110 130 140

Figure 5. THD+N vs. Temperature

REV. A

70

a:
a:

I

z -60
+

-80

rg,

40
10 2

10 3

104

10 5

SUPPLY MODULATION FREQUENCY - Hz

Figure 6. Power Supply Rejection Ratio vs. Frequency

AUDIO DIA CONVERTERS

~69

AD1868
PIN CONFIGURATIONS

AD1868
TOP VIEW
(Not To Scale)

PIN DESIGNATIONS
1

2
3
4
5
6
7
8
9
10
11

12
13
14
15
16

VL

LL
DL
CK
DR
LR
DGND
VBR
Vs
VoR
NRR
AGND
NRL
VoL
Vs
VBL

Digital Supply (+5 Volts)
Left Channel Latch Enable
Left Channel Data Input
Clock Input
RIGHT Channel Data Input
RIGHT Channel Latch Enable
Digital Common
Right Channel Bias
Analog Supply (+5 Volts)
Right Channel Output
Right Channel Noise Reduction
Analog Common
Left Channel Noise Reduction
Left Channel Output
Analog Supply (+5 Volts)
Left Channel Bias

Midseale Error
Midscale error is the difference between the analog output and
the bias when the twos complement input code representing
midscale is loaded in the input register. Midscale error is
expressed in mV.
FUNCTIONAL DESCRIPTION
The ADI868 is a complete, voltage output dual 18-bit digital
audio DAC which operates with a single +5 volt supply. As
shown in the block diagram, each channel contains a voltage
reference l8-bit, serial-to-parallel input register, 18-bit inPUtlatch, 18-bit DAC, and an output amplifier.
The voltage reference section provides a reference voltage and a
false ground voltage for each channel. The low noise bandgap
circuits produce reference voltages that are unaffected by
changes in temperature, time, and power supply.
The output amplifier uses both MOS and bipolar devices and
incorporates an NPN class-A outpUt stage. It is designed to produce high slew rate, low noise, low diatortion, and optimal frequency response.
Each 18-bit DAC uses a combination of segmented decoder and
R-2R architecture to achieve good integral and differentia1linearity. The resistors which form the ladder structure are fabricated with silicon-chromium thin film. Laser-trimming of these
resistors further reduces linearity error, resulting in low outpUt
distortion.
The input registers are fabricated with CMOS logic gates. These
gates allow fast switching speeds and low power consumption,
contributing to the fast digital timing, low glitch, and low power
dissipation of the ADl868.

DEFINmON OF SPECIFICATIONS
Total Harmonie Diatortion + Noise
Total harmonic distortion plus noise (THD+ N) is defmed as
the ratio of the sqUare root of the sum of the squares of the
amplitudes of the harmonics and noise to the amplitude of the
fundamental input frequency. It is usually expressed in percent
(%) or decibels (dB).
D-RaDge Diatortion
D-range distortion is the ratio of the amplirude of the signal at
an amplitude of -60 dB to the amplitude of the diatortion plus
noise. In this case, an A-weight fllter is used. The value specified for D-range performance is. the ratio measured plus 60 dB.

Signal-to-Noise Ratio
The signal-ta-noise ratio is defmed as the ratio of the amplitude
of the output when a full-scale output is present to the amplitude of the output with no signal present. It is expressed in
decibels (dB) and measured using an A-weight fllter.

AD1868 Functional Block Diagram

Gain Linearity
Gain linearity is a measure of the deviation of the aetua1 outpUt
amplitude from the ideal output amplitude. It is determined by
measuring the amplitude of the output signal as the amplirude
of that output signal is digitally reduced to a lower level. A perfect DIA converter exhibits no difference between the ideal and
aetua1 amplitudes. Gain linearity is expressed in decibels (dB).

5-70 AUDIO DIA CONVERTERS

REV. A

Circuit Considerations-AD1868
ANALOG CIRCUIT CONSIDERATIONS

POWER
SUPPLY

GROUNDING RECOMMENDATIONS
The AD1868 has two ground pins, designated as AGND (Pin
12) and DGND (Pin 7). The analog ground, AGND, serves as
the "high quality" reference ground for analog signals and as a
return path for the supply current from the analog portion of
the device. The system analog common should be located as
close as possible to Pin 12 to minimize any voltage drop which
may develop between these two points, although the internal
circuit is designed to minimize signal dependence of the analog
return current.
The digital ground, DGND, returns ground current from the
digital logic portion of the device. This pin should be connected
to the digital common node in the system. As shown in Figure 7, the analog and digital grounds should be joined at one
point in the system. When these two grounds are remotely connected such as at the power supply ground, care should be
taken to minimize the voltage difference between the DGND
and AGND pins in order to ensure the specified performance.
POWER SUPPLmS AND DECOUPLING
The ADI868 has three power supply input pins. Vs (Pins 9 and
IS) provide the supply voltages which operate the analog portion
of the device including the 18-bit DACs, the voltage references,
and the output amplifiers. The Vs supplies are designed to operate with a +5 V supply. These pins should be decoupled to analog common using a 0.1 ...F capacitor. Good engineeringpractice
suggests that the bypass capacitors be placed as close as possible
to the package pins. This minimizes the inherent inductive
effects of printed circuit board traces.
VL (Pin I) operates the digital portions of the chip includiog the
input shift registers and the input latching circuitry. VL is also
designed to operate with a +5 V supply. This pin should be
bypassed to digital common using a 0.1 ... F capacitor, again
placed as close as possible to the package pin. Figure 7 illustrates the correct connection of the digital and analog supply
bypass capacitors.

An imponant feature of the ADI868 audio DAC is its ability to
operate at reduced power supply voltages. This feature is vety
imponant in portable battety-operated systems. As the batteries
discharge, the supply voltage drops. Unlike any other audio
DAC, the ADI868 can continue to function at supply voltages
as low as 3.5 V. Because of its unique design, the power
requirements of the ADI868 diminish as the battery voltage
drops, funher extendiog the operating time of the system.

Figure 7. Recommended Circuit Schematic
NOISE REDUCTION CAPACITORS
The AD1868 has two noise-reduction pins designated as NRL
(Pin 13) and NRR (Pin 11). It is recommended that external
noise-reduction capacitors be connected from these pins to
AGND to reduce the output noise contributed by the voltage
reference circuitry. As shown in Figure 7, each of these pins
should be bypassed to AGND with a 4.7 ...F or larger capacitor.
The connections between the capacitors, package pins and
AGND should be as shon as possible to achieve the lowest
noise.
USING VBL AND VBR
The AD 1868 has two bias voltage reference pins, designated as
VBR (Pin 8) and VBL (Pin 16). These pins supply a dc reference voltage equal to the center of the output voltage swing.
These bias voltageS replace "False Ground" networks previously
required in single-supply audio systems. At the same time, they
allow dc-coupled systems, improving audio performance.
Figure 8a illustrates the traditional approach used to generate
False Ground voltages in single-supply audio systems. This circuit requires additional power and circuit board space.

VoL

VoR

Figure 8a. Schematic Using False Ground

REV. A

AUDIO DIA CONVERTERS 5-71

II

AD1868
Figure I illustrates the typical THD+ N versus frequeney performauce m the AD1868. It is evident that the THD+ N performance of the ADl868 remains stable at all three levels through a
wide range of frequencies. A load impedance of at least 2 kG is
recommended for best THD+ N performauce.

Analog Devices tests and grades all AD 1868& OD the basis of
THD+N performauce. During the distortion test, a high speed
digital pattern generator transmits digital data to each channe1 of
the device under test. Eighteen-bit data is latched into the DAC
at 352.8 kHz (8x Fs). The test waveform is a 990.5 Hz sine
wave with 0 dB, -20 dB, and -60 dB amplitudes. A 4096-point
FFT calculates total harmonic distortion + noise, signal-tei-Doise
ratio, and D-range. No deglitchers or external adjustments are
used.

DIGITAL CIltCUIT CONSIDERATIONS
Figure 8b. Circuitry Using Voltage Biases
The ADl868 eliminates the need for "False Ground" circuitry.
VBR and VBL generate the required bias voltages previously
generated by the "False Ground." As shown in Figure 8b, VBR
and VBL may be used as the reference point in each output
channel. This permits a dc-coupled output signal path. This
eliminates ac-coupling capacitors and improves low frequency
performauce. It should be noted that these bias outputs have
relatively high output impedance and will not drive output
currents 1arger than 100 f,IA without degrading the specified
performauce.

DISTORTION PERFORMANCE AND TESTING
The THD+ N fJgUre of an audio DAC represents the amount of
undesirable signal prodUced during reconstruction and playbaCk
of an audio waveform. Therefore, the THD+ N specification
provides a direct method to classify and chOOse an audio DAC
fur a desuedlevel mperformauce.

INPUT DATA
The ADI868 digital input port employs five signals: Data Left
(DL), Data Right (DR), Latch Left (LL), Latch Right (LR) .
and Clock (CLK). DL and DR are the seria1 inputs for the left
and right DACs, respectively. Input data bits are clocked into
the input register on the rising edge of CLK. The falling edges .
of LL and LR cause the last 18 bits which were clocked into the
seria1 registers to be shifted into the DACs, thereby updating
the respective DAC outputs. For systems using only a sing1e
latch signal, LL and LR may be connected together. For systems using only one DATA signal, DR and DL may be connected together. Data is transmitted to the ADl868 in a bit
stream composed of 18-bit words with a serial, twos complement, MSB first format. Left and right channe1s share the
Clock (CLK) signal.
Figure 9 illustrates the general signal requUements for data
transfer for the ADl868.

eLK
DL

DR

LL

LLI

~~__________~~~______~ILL
Figure 9. AD1868 Control Signals

5-72 AUDIO DIA CONVERTERS

REV. A

Applications -AD1868
TIMING
Figure 10 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished properly. The input pins of the ADl868 are ITL and S V CMOS
compatible.
The maximum clock rate of the ADI868 is specified to be at
least 13.S MHz. This clock rate allows data transfer rates of 2 x,
4x, 8x, and 16x Fs (where Fs equals 44.1 kHz). The applications section of this data sheet contains additional guidelines for
using the AD1868.

ADl868 drops. This extends the usable battery life. Finally, as
the battery supply voltage drops, the bias voltages and signal
swings also drop, preventing signal clipping and abrupt degradation of distortion. Figure 3 illustrates that THD+ N performance of the ADl868 rentains constant through a wide range of
supply voltages.
Automotive equipment rely on components which are able to
consistently perform in a wide range of temperatures. In addition, due to the limited space available in automotive applications, small size is essential. The ADl868 is able to satisfy both
of these requirements. The device has guaranteed operation
between -3S"C and +8S"C, and the 16-pin DIP or 16-pin SOIC
package is particularly attractive where overall size is
important.
Since the AD1868 provides de bias voltages, the entire signal

chain can be dc-coupled. This eliminate ac-coup!ing capacitors
from the signal path, improving low frequency performance and
lowering system cost and size.

IITS CLOCKED
'-____,..::,,====="""""'''''''' TOIHFTRECIISTI!R

Figure 10. AD1868 Input Signal Timing

In summary, the ADI868 is an excellent choice for batteryoperated portable or automotive digital audio systems. In the
following sections, some examples of high performance audio
applications featuring the ADl868 are described.

ADl868 with Sony CXD2550P Dqptal Filter
APPUCATIONS OF THE ADl868
The ADl868 is a high performance audio DAC specifically
designed for portable and automotive digital audio applications.
These market segments have technical requirements fundamentally different than those found in the high end or home-use
market segments. Portable equipment must rely on components
which require low amounts of power to offer reasonable playing
times. Also, battery voltages drop as the end of the discharge
cycle is approached. The AD1868's ability to operate from a
single + S V supply makes it a good choice for battery-operated
gear. As the battery voltage drops, the power dissipation of the

Figure 11 illustrates an 18-bit CD player design incorporating an
ADI868 DAC, a Sony CXD2SS0P digital filter and 2-pole antialias filters. This high performance, single-supply design operates at 8 x F s and is suitable for portable and automotive
applications. In this design, the CXD2SS0P filter transmits left
and right channel digital data to the AD1868. The left and right
latch signals, LL and LR, are both provided by the word clock
signal (LRCKO) of the digital filter. The digital data is converted to low distortion output voltages by the output amplifiers
on the AD1868. Also, no deglitching circuitry or external
adjustments are required. Bypass capacitors, noile-reduction
capacitors and the antialias filter details are omitted for clarity .

• 5VPOWER

...PL.

-

.....---1---..
OUTI'IIT

Figure 11. AD1868 with Sony CXD2550P Digital Filter

REV. A

AUDIO DIA CONVERTERS 5-73

II

AD1868- Applications
ADDITIONAL API'LICATIONS
In addition to CD player designs, the ADl868 is suitable for
similar applications such as DAT, portable musical instruments,
Laptop and Notebook personal computers, and PC audio 1/0
boards. The circuit techniques illustrated are directly applicable
in those applications.

Figures 12, l3, and 14 show connection diagrams for the
AD1868 with popular digital filter chips from NPC and
Yamaha. Each application operates at 8x Fs operation, Please
refer to the appropriate sections of this data sheet for additional
information.

+5V
POWER
SUPPLY

SM5813
LEFT
CHANNEL
OUTPUT

LOW
PASS
FILTER

RIGHT
CHANNEL
OUTPUT

Figure 12. AD1868 with NPC SM5813 Digital Filter

+5VPOWER
SUPPLY

SM5818AP

AD1868
LOW
PASS
FILTER

LEFT
CHANNEL
OUTPUT

AGND
NRR

VoR
LOW
PASS

FILTER

RIGHT
CHANNEL
OUTPUT

Figure 13. AD1868 with NPC SM5818AP Digital Filter

5-74 AUDIO DIA CONVERTERS

REV. A

AD1868
+SVPOWER

SUPPLY

YM3434

AD1888

LOW

PASS
FILTER

LOW

PASS
FILTER

LEFT

CHANNEL
OUTPUT

RIGHT

CHANNEL
OUTPUT

II

Figure 14. AD1868 with Yamaha YM3434 Digital Filter

ORDERING GUIDE
Model

THD+N
Package
SNR Option*
@Fs

ADl868N
ADl868R
ADl868N-J
ADl868R-J

0.008%
0.008%
0.006%
0.006%

95
95
95
95

dB
dB
dB
dB

N-16
R-16
N-16
R-16

ON = Plastic DIP; R = sOle. For outline
information see Package Information section.

REV. A

AUDIO DIA CONVERTERS 5-75

5-76 AUDIO DIA CONVERTERS

Video OfA Converters
Contents
Page

Video D/A Converters - Section 6 .............................................. 6-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
ADV453 - CMOS 66 MHz Monolithic 256 x 24 Color Palette RAM-DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
ADV476 - CMOS Monolithic 256 x 18 Color Palette RAM-DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
ADV478/471 - CMOS 80 MHz Monolithic 256 x 24 (18) Color Palette RAM-DACs . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
ADV7120 - CMOS 80 MHz Triple 8-Bit Video DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
ADV7121nl22 - CMOS 80 MHz Triple 10-Bit Video DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37
ADV714117146nl48 - CMOS Continuous Edge Graphics RAM-DACs (CEGIDAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49

•

VIDEO DIA CONVERTERS 6-1

~

'"

:s
~

0

Selection Guide

Video Digital-to-Analog Converters

R
):>

8<:
i!ii
~

~

(I)

Model

OockRate
MHZ

D/A Converter
Organization

ADV471
ADV476
ADV7141
ADV7146
ADV453
ADV478
ADV7148
ADV7I20
ADV7I21
ADV7122

35, 50, 66, 80
35, 40, 50, 66, 80, 100
35,50,66
35,50,66
40
35, 50, 66, 80, 100
35,50,66
35,50,80
35,50,80
35,50,80

Triple 6-Bit
Triple 6-Bit
Triple 6-Bit
Triple 6-Bit
Triple 8-Bit
Triple 8-Bit
Triple 8-Bit
Triple 8-Bit
Triple 10-Bit
Triple 10-Bit

RAM
(Color Palette)
Size
256
256
256
256
256
245
256

x
x
x
x
x
x
x

18
18
18
18
24
24
24

Overlays

Page

Comments

IS x 18

6-19
6-9
6-49
6-49
6-3
6-19
6-49
6-31
6-37
6-37

ADV478 Pin-Compatible
Triple 6-Bit RAM-DAC
CEG - Effective 24-Bit True Color
CEG - Effective 24-Bit True Color
Triple 8-Bit RAM-DAC
Triple 8-Bit RAM-DAC
CEG - Effective 24-Bit True Color
True Color DAC
True Color DAC
True Color DAC

3 x 24
IS x 24

1IIIIIIII ANALOG

WDEVICES

CMOS 66 MHz Monolithic 256 x 24
Color Palette RAM-OAC
AOV453 I

FEATURES
66MHz Pipelined Operation
Triple 8-Bit D/A Converters
256x24 Color Palette RAM
3x24 Overlay Registers
RS-343A/RS-170 Compatible Outputs
+5V CMOS Monolithic Construction
4O-Pin DIP or Small 44-Pin PLCC Package
Power Dissipation: 1000mW
APPLICATIONS
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Desktop Publishing
AVAILABLE CLOCK RATES
66MHz
40MHz

GENERAL DESCRIPTION
The ADV453 (ADV®) is a complete analog video output RAMDAC on a single monolithic chip. It is specifically designed for
high resolution color graphics systems. The pan contains a
256x24 color lookup table, a 3x24 overlay palette as well as
triple 8-bit video D/A conveners. The ADV453 is capable of
simultaneously displaying up to 259 colors, 256 from the lookup
table and three from the overlay registers, out of a total color
palette of 16.8 million addressable colors.
The three overlay registers allow for the implementation of overlaying cursors, pull down menus and grids. There is an independent, asynchronous MPU bus which allows access to the color
lookup table without affecting the input of video data via the
pixel pon. The ADV453 is capable of generating RGB video
output signals which are compatible with RS-343A and RS-170
video standards, without requiring external buffering.

FUNCTIONAL BLOCK DIAGRAM

COMP

IDA
'SYNC

SVNC

lOG
BLANK

OLO

lOB

GNO

D1

00

PRODUCT HIGHLIGHTS
I. Fast video refresh rate, 66MHz.
2. Compatible with a wide variety of high resolution color
graphics systems including VGA· and Macintosh II··.
3. Three overlay registers allow for implementation of overlaying cursors, pull down menus and grids.
4. Guaranteed monotonic. Integral and differential nonlinearities
guaranteed to be a maximum of ± lLSB.
5. Low glitch energy, 50pV secs.

The ADV453 is fabricated in a +5V CMOS process. Its monolithic CMOS construction ensures greater functionality with low
power dissipation. The pan is packaged in both a 0.6", 4O-pin
DIP and a 44-pin plastic leaded (J-lead) chip carrier, PLCC.

ADV is • registered trademark of Analog Devices, Inc.
*VGA is a trademark of Internationalllusiness Machines Corp.
**Macintosh II is • registered trademark of Apple Computer Inc.

REV. A

VIDEO DIA CONVERTERS 6-3

II

(VM=~~Y =7 5%. Y =+1.235Y. RS£T=28~O.ISYllc connected to lOG.
AO"A53
,At -:SPECIFIC.'JIONS
" A l l specifications T to T unless otIIBI'WISe noted.)
REF
min

Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
Gray Scale Error
Coding
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, lIN
Input Capacitance, CIN
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating State Leakage Current
Floating State Output Capacitance
ANALOG OUTPUTS
Gray Scale Current Range
Output Current
White Level Relative to Blank
White Level Relative to Black
Black Level Relative to Blank
Blank Level on lOR, lOB
Blank Level on lOG
Sync Level on lOG
LSB Size
DAC to DAC Matching
Output Compliance, VDC
Output Impedance, RoUT
Output Capacitance, COUT
VOLTAGE REFERENCE
Voltage Reference Range, VREF
Input Current, IVREF
POWER SUPPLY
Supply Voltage, VAA
Supply Current, IAA
Power Supply Rejection Ratio
Power Dissipation
DYNAMIC PERFORMANCE
Clock and Data Feedthrough2 ,3
Glitch Impulse2 ,3
DAC to DAC Crosstalk

mill

All Versions

Units

8

Bits

±I
±I
±5%

LSB max
LSB max
Gray Scale max
Binary

2
0.8
± I
10

V min
V max
!LA max
pF typ

2.4
0.4
20
20

V min
V max

15
22

mAmin
mAmax

17.69
20.40
16.74
18.50
0.95
1.90
0
50
6.29
8.96
0
50
69.1
5
-1
+1.4

mAmin
mAmax
mAmin
mAmax
mAmin
mAmax

Typically 19.05mA

~min
~max

Typically 5!LA

mAmin
mAmax

Typically 7.62mA

~min

Typically

10
30

1.1411.26
-5

4.75/5.25

Test ConditionslConiments

Guaranteed Monotonic

VIN = 0.4V or 2.4V

IsouReE = 400~
ISINK = 3.2mA

~max

pF typ

!LA max
!LA typ
% max
V min
V max
kOtyp
pF typ

Typically 17.62mA
Typically l.44mA

5~

Typically 2%

lOUT = OmA

V minIV max
mA typ

275
250
0.5
1375
1250

V minIV max
mAmax
mAmax
%1% max
mWmax
mWmax

-30
50
-23

dB typ
pV sees typ
dBtyp

Typically 220mA, 66MHz Parts
Typically I9OmA, 40MHz Parts
Typically 0.12%1%, f = 1kHz, COMP =O.I!LF
Typically lOOOmW, 66MHz Parts
Typically 900mW, 40MHz Parts

NOTE
'Temperature Range (Tm;n to T _,); 0 to + 70'C
'TTL input values are 0 to 3 volts, with input rise/fall times :s;3ns, measured between the 10% and 90% points. Timing reference points at SO% for inputs and
outputs. Analog output losd :s;lOpF, 37.Sn. DO-D7 output load :s;SOpF. See timing notes in Figure 2.
'Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. For this test, the digital inputs bave a lkfi resistor
to ground and are driven by 74HC logic. Glitch impulse includes clock and data feedthrough, - 3dB test bandwidth = 2 x clock rate.
Specifications subject to change without notice.

6-4 VIDEO DIA CONVERTERS

REV. A

ADV453
TIMING CHARACTERISTICS 1 (VU =

+5V ±5%, VREF =+1.235V, RSET = 2800.l sYNC
connected to lOG. All Specifications Tmin to Tme/I.

Parameter

66MHz Version

40MHz Version

Units

Conditions/Comments

f max
tl
tz
t,
t,
t,

66

40
35
35
25

MHz max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
nsmin
ns min
nstyp
ns max
ns typ
ns typ
nsmax
ns typ
ns max

Clock Rate
CS, CO, Cl Setup Time
CS, CO, Cl Hold Time
RD, WR High Time
RD Asserted to Data Bus Driven
RD Asserted to Data Valid
RD Negated to Data Bus Three Stated
WR Low Time
Write Data Setup Time
Write Data Hold Time
Pixel & Control Setup Time
Pixel & Control Hold Time
Clock Cycle Time
Clock Pulse Width High Time
Clock Pulse Width Low Time
Analog Output Delay

t,;

t7
ts

t..
tlO
til
tlZ
tl3
tl'
tIS
t l•
tl7'
tpo
tSK

35
35
25

10

10

100
15
50
35
0
5
2
15
5
5
20
30
3
25
2 x t lz
I
2

100
15
50
35
0
7
3
25
7
7
20
30
3
25
2x[IZ
I
2

Analog Output Rise/Fall Time
Analog Output Settling Time
Pipeline Delay
Analog Output Skew

NOTES
ITfL input values are 0 to 3 volts, with input rise/fall times <;3n5, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load -..,___ +5V (PCB POWER PLANE)
C1

ADV476
GND

GROUND
R1

R2

R3

REDr_------~~--r__t--_I--------

TO
VIDEO
CONNECTOR

BLUE~--------~----_J--~~~~~
COMPONENT

DESCRIPTION

VENDOR PART NUMBER

C1--(:4
C5
C6
L1
R1,R2,R3

0.11lF CERAMIC CAPACITOR
10llF TANTALUM CAPACITOR
471lF TANTALUM CAPACITOR
FERRITE BEAD
750 1% METAL FILM RESISTOR

ERIE RPE112Z5U104M50V
MALLORY CSR13G106KM
MALLORY CSR13F476KM
FAIR-RITE 2743001111
DALE CMF-55C

Figure 7_ ;ADV476 Typical Connection Diagram and Component List

O.l~F

Vee ~~_..;A,;;;N;;.;AL;;.;OG~POW=E;;;;R~P,;;;LAN=E_ _

G.1~F

IREF

~-.----------

COMP

Figure 8. Connection of VREF and COMP with the
ADV476KP (44-Pin PLCC)

6-18 VIDEO DIA CONVERTERS

REV. A

11IIIIIIII ANALOG
WDEVICES

CMOS 80MHz Monolithic 256 x 24(18)
Color Palette RAM-DACs
ADV478/ADV471 I

FEATURES
Personal System/2* Compatible
80MHz Pipelined Operation
Triple II-Bit (6-Bit) D/A Converters
256 x 24(18) Color Palette RAM
15 x 24(18) Overlay Registers
RS-343A1RS-170 Compatible Outputs
Sync on All Three Channels
Programmable Pedestal (0 or 7.5 IRE)
External Voltage or Current Reference
Standard MPU Interface
+ 5V CMOS Monolithic Construction
44-Pin PLCC Package
Power Dissipation: SOOmW

FUNCTIONAL BLOCK DIAGRAM

OPA

OLl

APPLICATIONS
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Desktop Publishing
AVAILABLE CLOCK RATES
SOMHz
66MHz
SOMHz
35MHz

GENERAL DESCRIPTION
The ADV478 (ADV®) and ADV471 are pin compatible and
software compatible RAM-DACs designed specifically for Personal
Systeml2 compatible color graphics.
The ADV478 has a 256 x 24 color lookup table with triple 8-bit
video D/A converters. It may be configured for either 6 bits or
8 bits per color operation. The ADV471 has a 256 x 18 color
lookup table with triple 6-bit video D/A converters.
ADV is a registered trademark of Analog Devices, Inc.
*Peraonal Systeml2 is a trademark of International Business Machines
Corp.

REV. A

GND

GND

07

AD Wii

RSO AS' RS2

NOTES
1. NUMBERS IN PARENTHESIS INDICATE PIN NAMES FOR THE ADV471.
2. Ne", NO CONNECT

Options on both parts include a programmable pedestal (0 or
7.5 IRE) and use of an external voltage or current reference.
Fifteen overlay registers provide for overlaying cursors, grids,
menus, EGA emulation, etc. Also. supported is a pixel read
mask register and sync generation on all three channels.
The ADV478 and ADV471 generate RS-343A compatible video
signals into a doubly terminated 750 load, and RS-170 compatible
video signals into a singly terminated 750 load, without requiring
external buffering. Differential and integral linearity errors are
guaranteed to be a maximum of ± ILSB for the ADV478 and
± 1I4LSB for the ADV471 over the full temperature range.

VIDEO DIA CONVERTERS 6-19

Parameter

AU Versions

Units

8(6)

Bits

± 1(1/4)
± 1(1/4)
±S
Binary

LSBmax
LSBmax
% Gray Scale max

DIGITAL INPUTS
Input High Voltage, V1NH
Input Low Voltage, V1NL
Input Current, lIN
Input Capacitance, C m

2
0.8
±I
7

V min
V max
.,.A max
pFmax

DIGITAL OUTPUTS
Output High Voltage, V OH
Output Low Voltage, VOL
Floating-$tate Leakage Current
Floating-State Output Capacitance

2.4
0.4
50
7

V min
V max
Il-Amax
pFmax

20

mAmax

17.69
20.40
16.74
IS.50
0.95

mAmin
mAmax
mAmin
mAmax
mAmin
mAmax
Il-Amin
Il-Amax
mAmin
mAmax
Il-Amin
Il-Amax
Il-Atyp

STATIC PERFORMANCE
Resolution (Each DAC)3
Accuracy (Each DAC)3
Integral Nonlinearity
Differential Nonlinearity
Gray Scale Error
Coding

ANALOG OUTPUTS
Gray Scale Current Range
Output Current
White Level Relative to Blank
White Level Relative to Black
Black Level Relative to Blank
(SETUP = V AA)
Black Level Relative to Blank
(SETUP = GND)
Blank Level
Sync Level
LSBSize'
DAC to DAC Matching
Output Compliance, Voc
Output Impedance, ROUT
Output Capacitance, COUT
VOLTAGE REFERENCE
Voltage Reference Range, V REF
Input Current, IVREF
POWER SUPPLY
Supply Voltage, V AA
Supply Current, IAA
Power Supply Rejection Ratio
Power Dissipation
DYNAMIC PERFORMANCE
Clock and Data Feedthrough4 •s
Glitch Impulse4 ,s
DAC to DAC Crosstalk"

1.90
0
50
6.29
S.96
0
50
69.1 (279.6S)
5
-I
+ 1.5
10
30
1.14/1.26

10

Guaranteed Monotonic

VIN = O.4Vor 2.4V

ISOURCE = 4OOll-A
ISINK = 3.2mA

Typically 19.0SmA
Typically 17 .62mA
Typically l.44mA
Typically SIl-A
Typically 7.62mA
Typically SIl-A

%max

8/6 = Logical I for ADV478
Typically 2%

Vmin
V max
kHtyp
pFmax

IouT=OmA

V minlV max
Il-Atyp

1100

V minIV max
VminlVmax
mAmax
%1% max
mWmax

-30
75
-23

dBtyp
pVsecstyp
dBtyp

4.75/5.25
4.50/5.50
220
0.5

Test Conditions/Comments

Tested in Voltage Reference
Configuration with V REF = 1.23SV
SOMHz and 66MHz Parts
SOMHz and 3SMHz Parts
Typically 180mA
f= lkHz,COMP=O.lIl-F
Typically 900mW, VAA = SV

NOTES
I " 5% for 80MH7. and 66MH7. parts; ,,\0% for 50MH7. and 35MH7. parts.
2Temperature Range (Tmin to Tmax); 0 to + 70°C.
3Numbers in parentheses indicate ADV471 parameter value.
'Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. For this test, the digital inpurs have a
Ik!l resistor to ground and are driven by 74HC logic. Glitch impulse includes clock and data feedthrough, -3dB test bandwidth = 2xclock rate.
'TTL input values are 0 to 3 volts, with input rise/fall times s3ns, measured between the 10% and 90% points. Timing reference poinrs at 50%
for inputs and outputs. Analog output load sIOpF, 00- D7 output load s5OpF. See timing.notes in Figure 2.
6DAC to DAC crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions.
Specifications subject to change without notice.

6-20 VIDEO DIA CONVERTERS

REV. A

ADV478/ADV471

Parameter

KPSO Version

KP66 Version

KP50 Version

KP35 Version

Units

Conditions/Comments

f max
tl
tz
t3

80
10
10
5
40
20
10
10
50
6xtlz
3
3
12.5
4
4
30
3
13
2
4Xt l2

66

50
10
10
5
40
20
10
10
50
6Xtl2
3
3
20
6
6
30
3
20
2
4Xt l2

35
10
10
5
40
20
10
10
50
6Xtl2
3
3
28

MHz
nsmin
nsmin
nsmin
nsmax
nsmax
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
nsmin
nsmax
nstyp
nstyp
nsmax
nsmin

Clock Rate
RSO - RS2 Setup Time
RSO - RS2 Hold Time
RD Asserted to Data Bus Driven
RD Asserted to Data Valid
RD Negated to Data Bus 3-Stated
Write Data Setup Time
Write Data Hold Time
RD, WR Pulse Width Low
RD, WR Pulse Width High
Pixel and Control Setup Time
Pixel and Control Hold Time
Clock Cycle Time
Clock Pulse Width High Time
Clock Pulse Width Low Time
Analog Output Delay
Analog Output RiselFall Time
Analog Output Settling Time
Analog Output Skew
Pipeline Delay

4
ts
1,;

t7
t8
t9
tlO
til
tl2
tl3
tl4
tiS
tl6
tl74
tl8
tpo

10
10
5
40
20
10
10
50
6X11z
3
3
15.3
5
5
30
3
15.3
2
4x tl2

7
9
30
3
28
2
4x tl2

NOTES
'TTL input values are 0 to 3 volts, with input rise/fall times ,,;3ns, measured between the 10% and 90% points. Timing reference
points at 50% for inputs and outputs. Analog output load ,,;IOpF, 37.Sn. DO - D7 output load sSOpF. See timing notes in Figure 2.
2 ± 5% for BOMHz and 66MHz parts; ± 5% for SOMHz and 3SMHz parts.
3Temperature Range (Tmin to T~ax); 0 to + 70°C.
'Settling time does not include clock and data feedthrough. For this test, the digital inputs have a lill resistor to ground and are
driven by 74HC logic.
Specifications subject to change without notice

TIMING DIAGRAMS

READIDO-D7)

----------~::~~~~t=========~~~L--------------

Figure 1. MPU ReadlWrite Timing

-r-

CLOCK
PO - P7, OLD - OLl,

~~§~~~~§§~C:J§:~t:)~~~I~~~>-..--+SV (Ved
Cl

GND~~f---~--~~-1

Rl

R2

____-4________"

R3

IOR~-__-~-_T-~---

lOG

r - - -...--Ir-+---

IOBr------~----

COMPONENT
Cl-CS

0.1 p.F Ceramic Capacitor

C6

DESCRIPTION
10... F Tantalum Capacitor

C7
Ll
Rl.R2.R3

47 .... FT.ntalum Capacitor
Ferrite Bead

7SI1 1% Metal Film Rosistor

J

____ GROUND

v~~o

CONNECTOR

VENDOR PART NUMBER
Erie RPEII22SU104MSOV
MaUory CSR13G106KM
MaUory CSRI3F476KM
Fair·Rite 2743001111
Dale CMF·SSC

Figure 6. Typical Connection Diagram and Component List
(External Current Reference)

APPLICATION INFORMATION
External Voltage vs. Current "Reference
The ADV4781ADV471 is designed to have excellent performance
using either an external voltage or current reference. The voltage
reference design (Figure 5) has the advantages of temperature
compensation, simplicity, lower cost and provides excellent
power supply rejection. The current reference design (Figure 6)
requires more components to provide adequate power supply
rejection and temperature compensation (two transistors, three
resistors and additional capacitors).

REV. A

RS-170 Video Generation
For generation of RS-170 compatible video, it is recommended
that the DAC outputs be connected to a singly terminated 7S!lIoad.
If the ADV478/ADV471 is not driving a large capacitive load,
there will be negligible difference in video quality between
doubly terminated 750 and singly terminated 750 loads.
If driving a large capacitive load (load RC> 1I(21Tfe»), it is recommended that an output buffer (such as an AD848 or AD9617
with an unloaded gain>2) be used to drive a doubly terminated
750 load.

VIDEO DIA CONVERTERS 6-29

II

6-30 VIDEO DIA CONVERTERS

r.ANALOG
WDEVICES
FEATURES
80 MHz Pipelined Operation
Triple 8-Bit D/A Converters
RS-343A/RS-170 Compatible Outputs
TTL Compatible Inputs
+5 V CMOS Monolithic Construction
4O-Pin DIP or 44-Pin PLCC Package
Power Dissipation: 400 mW
APPLICATIONS
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Video Signal Reconstruction
Desktop Publishing
Direct Digital Synthesis (DDS)
SPEED GRADES
BOMHz
50 MHz
30 MHz

CMOS
80 MHz, Triple 8-Bit Video OAC
A0V7120 I
FUNCTIONAL BLOCK DIAGRAM
FS

v"

ADJUst

VREF

CLOCK

COMP

RO

lOA

R7

PIXEL
INPUT
PORT

GO

lOG

G7

BO

lOB

B7

REF WHITE

'SYNC

BLANK
SYNC

GND

GENERAL DESCRIPTION
The ADV7120 (ADV®) is a digital to analog video converter on
a single monolithic chip. The pan is specifically designed for
high resolution color graphics and video systems. It consists of
three, high speed, 8-bit, video DIA converters (RGB); a standard TTL input interface and high impedance, analog output,
current sources.
The ADV7120 has three separate, 8-bit, pixel input ports, one
each for red, green and blue video data. Additional video input
controls on the part include composite sync, blank and reference
white. A single + 5 V supply, an external 1.23 V reference and
pixel clock input are all that are required to make the part
operational.

PRODUCT HIGHLIGHTS
1. Fast video refresh rate, 80 MHz.
2. Compatible with a wide variety of high resolution color
graphics video systems.
3. Guaranteed monotonic with a maximum differential nonlinearity of ±0.5 LSB. Integral nonlinearity is guaranteed to
be a maximum of ± 1 LSB.

The ADV7120 is capable of generating RGB video output signals, which are compatible with RS-343A and RS-170 video
standards, without requiring external buffering.
The ADV7120 is fabricated in a +5 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with low power dissipation. The part is packaged in both a 0.6",
4O-pin plastic DIP and a 44-pin plastic leaded (Head) chip carrier, PLCC.

ADV is • registered trademark of Analog Devices Inc.

REV. A

VIDEO DIA CONVERTERS 6-31

•

(VAl

= +5 V±5%; VREF = + 1.235 V; RL = 37.5 n, CL = 10 pF; Rm =

ADV7120 _ SPECIFICATIONS :e:!s~"::~:~nected to lOG. All Specifications
Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity, INL
Differential Nonlinearity, DNL
Gray Scale Error
Coding

DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, lIN
Input Capacitance, C IN2
ANALOG OUTPUTS
Gray Scale Current Range
Output Current
White Level Relative to Blank
White Level Relative to Black
Black Level Relative to Blank
Blank Level on lOR, lOB
Blank Level on lOG
Sync Level on lOG
LSB Size
DAC to DAC Matching
Output Compliance, Voc
Output Impedance, Rou/
Output Capacitance, C01;T2
VOLTAGE REFERENCE
Voltage Reference Range, VREF
Input Current, IVREF
POWER REQUIREMENTS
VAA
lAA
Power Supply Rejection Ratio
Power Dissipation
DYNAMIC PERFORMANCE
Glitch Impulse2 • 3
DAC Noise2 , 3, 4
Analog Output Skew

All Vnons

Units

8

Bits

±1
±0.5
±5

LSBmax
LSBmax
% Gray Scale max

TMIII

to

TIUX!

unless

Test Conditions/Comments

Guaranteed Monotonic
Max Gray Scale Current: lOG = (VREF* 12,0821RsET) mA
lOR, lOB = (VREF* 8,627IRsET) mA

Binary
2
0.8
±1
10

V min
V max
.,A max
pFmax

15
22

mAmin
mAmax

17.69
20.40
16.74
18.50
0.95
1.90
0
50
6.29
9.5
0
50
69.1
5
-I
+1.4
100
30

mAmin
mAmax
mAmin
mAmax
mAmin
mAmax
.,A min
.,A max
mAmin
mAmax
.,A min
.,A max
.,A typ
% max
V min
V max
ldl typ
pFmax

I.l4/1.26
-5

V minIV max
mAtyp

5
125
100
0.5
625
500

V nom
mAmax
rnA max

%1% max
mWmax
mWmax

50
200

pV secs typ
pV sees typ

2

nsmax

VIN

= 0.4 V or 2.4 V

Typically 19.05 mA
TypicaUy 17.62 mA
TypiCally 1.44 mA
Typically 5 jJ.A
Typically 7.62 mA
Typically 5 jJ.A

TypicaUy 2%

lOUT

= 0 rnA

VREF

= 1.235 V for Specified Performance

Typically 80 mA: 80 MHz Pans
Typically 70 mA: 50 MHz & 35 MHz Pans
Typically 0.12%1%: f = 1 kHz, COMP = 0.1 jJ.F
Typically 400 mW: 80 MHz Pans
Typically 350 mW: 50 MHz & 30 MHz Parts

Typically I ns

NOTES

ITemperature Range (Tmin to T miX); 0 to + 70OC.
'Sample t..ted at + 25'C to ensure compliance.
'TTL input values are 0 to 3 volts, with input rise/falltimes ,;3 ns, measured between the 10% ~nd 90% points. Timing reference points at 50% for inputs and
outputs. See timing notes in Figure I.
'This includ.. effects due to clock and data feedthrough as well as RGB analog crosstalk.
Specifications subject to change without notice.

6-32 VIDEO DIA CONVERTERS

REV. A

ADV7120
+5 V ±5%; VREf = +1.235 V; =37.5 n, C =10 pF;
=5600.
TIMING CHARACTERISTICS' (VAl =connected
to 'OG. All Specifications Tmin to Tm./ unless otherwise noted.)
RL

L

RSEI

'SYNC

Parameter

80 MHz Version

SO MHz Version

30 MHz Version

Units

Conditions/Comments

f,..,.
t.
t2
t3

80

50
6
2
20

30

MHz max
nsmin
nsmin
nsmin
nsmin
nsmin
nsmax
nstyp
nsmax
nstyp

Clock Rate
Data & Control Setup Time
Data & Control Hold Time
Clock Cycle Time
Clock Pulse Width High Time
Clock Pulse Width Low Time
Analog Output Delay

4
ts
t,;

t7
t a3

3
2
12.5
4
4
30
20
3
12

7
7

30
20
3
IS

8

2
33.3
9
9
30
20
3

IS

Analog Output Rise/Fall Time
Analog Output Transition Time

NOTES
'TIL input values are 0 to 3 volts, with input rise/fall times ,,;3no, measured between the 10% and 90% points. Timing refeteDce points at 50% for inputs ODd
outputs. See timing notes in Figure 1.
'Templ,roture range (T..in to T_): 0 to +70"C
'Sample tested at + 25"C to ensure compliance.
Specifications subject to chan&e without notice.

II
CLOCK

DIGITAL INPUTS ~~~~~~~~ r---I~ ~~~~~~~~

(RO-R7, GO-G7, BO-B7;

SYNC,~, ~~~~~~~~ ~----~~ ~~~~~~~~~

REF WHITE)

ANALOG OUTPUTS
(lOR, lOG, lOB, ISYNcI _____________________________-{

NOTES
1. OUTPUT DELAY (t6) MEASURED FROM THE 500/0 POINT OF THE RISING EDGE OF
CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.
2. TRANSITION TIME (ta) MEASURED FROM THE 500/0 POINT OF FULL-SCALE
TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE.
3. OUTPUT RISE/FALL TIME (t 7 ) MEASURED BETWEEN THE 10% AND 90% POINTS
OF FULL TRANSITION.

Figure 1. Video Input/Output Timing

REV. A

VIDEO DIA CONVERTERS 6-33

ADV7120
RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS·

Parameter

Symbol

Min

Typ

Max

Units

Power Supply
Ambient Operating
Temperature
Output Load
Reference Voltage

VAA

4.75

5.00

5.25

Volts

TA
RL
VREF

0

+70

°C

1.26

Volts

1.14

37.5
1.235

n

VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
. Voltage on Any Digital Pin .... GND -0.5 V to VAA +0.5 V
Ambient Operating Temperature (TA) " . . . . . . . 0 to +70°0
Storage Temperature (Ts) . . . . . . . . . . . . . -65°C to + 150°C
Junction Temperature (TJ ) • . . . . . . . . . . . . . • . . . • + 175°C
Soldering Temperature (10 secs) . . . . . . . . . . . . . . . . 300°C
Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . 220°C
lOR, lOB, lOG, IsyNC to GND' . . . . . . . . . . . . 0 V to VAA
NOTES
·Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
oPeration of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
1Analog Ootput Short Circuit to any Power Supply or Common can be of an
indefinite duration.

CAUTION ________________________________________________
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted.

ORDERING GUIDE

Model

Speed

Temperature
Range

Package
Option·

ADV7120KN80
ADV7120KN50
ADV7120KN30
ADV7120KP80
ADV7120KP50
ADV7120KP30

80
50
30
80
50
30

O°C
O°C
O°C
O°C
O°C
O°C

N-40A
N-40A
N-40A
P-44A
P-44A
P-44A

MHz
MHz
MHz
MHz
MHz
MHz

to
to
to
to
to
to

+7000
+7OOC
+70°C
+70°C
+70°C
+70°C

*N = Plastic DIP; P = Plastic Leaded Chip Carrier. For outline information
see Package Information section.

PIN CONFIGURATIONS

DIP

PLCC

Iii
." ....
i3

Ii: II! II! D! Ii! Ii!

a:

~

~

~

;J'

0

"

•
ADV7120
TOP VIEW
(Not to Seale)

ADV7120
TOP VIEW
(Not to Scale)

6-34 VIDEO DIA CONVERTERS

REV. A

ADV7120
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
BLANK

Function
Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs, lOR,
lOB and lOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While BLANK
is a logical zero, the RO-R7, GO-G7, RO-R7 and REF WHITE pixel and control inputs are ignored.
Composite sync control input (TTL compatible). A logical zero on the SYNC input switches off a 40 IRE current
source on the I SYNC output. SYNC dOes not override any other control or data input; therefore, it should only be
asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK.

CLOCK

Clock input (TTL compatible). The rising edge of CLOCK latches the RO-R7, GO-G7, BO-B7, SYNC, BLANK
and REF WHITE pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should
be driven by a dedicated TTL buffer.

REF WHITE

Reference white control input (TTL compatible). A logical one on this input forces the lOR, lOG and lOB
outputs to the white level, regardless of the pixel input data (RO-R7, GO-G7 and BO-B7). REF WHITE is
latched on the rising edge of clock.

RO-R7,
GO-G7,
BO-B7

Red, green and blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of CLOCK. RO,
GO and BO are the least significant data bits. Unused pixel data inputs should be connected to either the regular
PCB power or ground plane.

lOR, lOG, lOB

Red, green, and blue current outputs. These high impedance current sources are capable of directly driving
a doubly terminated 75 n coaxial cable. All three current outputs should have similar output loads whether or not
they are all being used.

I SYNC

Sync current output. This high impedance current source can be directly connected to the lOG output. This
allows sync information to· be encoded onto the green channel. I SYNC does not output any current while SYNC is
at logical zero. The amount of current output at ISYNC while SYNC is at logical One is given by:
[SYNC

(mA) = 3,455 x V REF (V)/

RSET

(n)

If sync information is not required on the green channel, I SYNC should be connected to AGND.
FS ADJUST

Full-scale adjust control. A resistor (R sET ) connected between this pin and GND, controls the magnitude of the
full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current.
The relationship between RSET and the full-scale output current on lOG (assuming I SYNC is connected to lOG) is
given by:
RSET (n) = 12,082 x V REF (V)/IOG (mA)
The relationship between RSET and the full-scale output current on lOR and lOB is given by:
lOR, lOB

CaMP

(mA) = 8,628 x V REF (V)/

RSET

(n)

Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 jJ.F ceramic capacitor
must be connected between CaMP and VAA.
Voltage reference input. An external 1.2 V voltage reference must be connected to this pin. The·use of an
external resistor divider network is not recommended. A 0.1 jJ.F decoupling ceramic capacitor should be connected
between VREF and VAA.
Analog power supply (5 V ± 5%). All VAA pins on the ADV7120 must be connected.
Ground. All GND pins must be connected.

REV. A

VIDEO DIA CONVERTERS 6-35

•

ADV7120
TERMINOLOGY
Blanking Level
The level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level which will shut off the picture tube, resulting in the blackest possible picture.
Color Video (RGB)
This usually refers to the technique of combining the three primary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
Sync Signal (SYNC)
The position of the composite video signal which synchronizes
the scanning process.
Gray Scale
The discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different levels while a 6-bit DAC contains 64.

6-36 VIDEO DIA CONVEFfTEFfS

Raster Sean
The most basic method of sweeping a'CRT one line at a time to
generate and display images.
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Reference White Level
The maximum positive polarity amplitude of the video signal.
Sync Level
The peak level of the SYNC signal.
Video Signal
That portion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion which may
be visually observed.

REV. A

CMOS
80 MHz, Triple 10-Bit Video OACs
AOV7121/AOV7122 I

r.ANALOG
WDEVICES
FEATURES
80 MHz Pipelined Operation
Triple 1D-Bit D/A Converters
RS-343A/RS-170 Compatible Outputs
TTL Compatible Inputs
+5 V CMOS Monolithic Construction
4O-Pin DIP Package (ADV7121)
44-Pin PLCC Package (ADV7122)
Power Dissipation: 400 mW
APPUCAnONS
High Definition Television (HDTV)
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Video Signal Reconstruction
Direct Digital Synthesis (DDS)

..

Vu

..",IIST

"CCIIP

Cl.OCK

lOR

-[=..

INPUT
POfIT

,

100

BO,

100

..

aND

SPEED GRADES
80 MHz
50 MHz
30 MHz

ADV7121 Functional Block Diagram

fS
ADJUST

Vu

v",

GENERAL DESCRIPTION
The ADV71211ADV7122 (ADViII) is a video speed, digital-toanalog converter on a single monolithic chip. The part is
specifically designed for high resolution color graphics and video
systems including high definition television (HDTV). It consists
of three, high speed, lO-bit, video D/A converters (RGB), a
standard TTL input interface and high impedance, analog output, current sources.
The ADV71211ADV7122 has three separate, lO-bit, pixel input
ports, one each for red, green and blue video data. A single + 5
V power supply, an external 1.23 V reference and pixel clock
input is all that is required to make the part operational, The
ADV7122 has additional video control signals, composite SYNC
and BLANK.
The ADV71211ADV7122 is capable of generating RGB video
output signals which are compatible with RS-343A, RS-170 and
most proposed production system HDTV video standards, including SMPTE 240M,
The ADV71211ADV7122 is fabricated in a +5 V CMOS process. Its monolithic CMOS construction. ensures greater functionality with low power dissipation. The ADV7121 is packaged
in a 0.6", 4O-pin plastic DIP package. The ADV7122 is packaged in a 44-pin plastic leaded (J-lead) chip carrier, PLCC.

REV. A

CCIIP

CLOCK

-[=

""""
POfIT

..

lOR

"

lOG

"

'

BO,

108

"

II

iLliiiiiO-----I
iffiiCn-----L_....l
aND

ADV7122 Functional Block Diagram

PRODUCT HIGHUGHTS
1. Fast video refresh rate, 80 MHz.
2. Guaranteed monotonic to 10 bits. Ten bits of resolution allows for implementation of linearization functions such as
gamma correction and contrast enhancement.
3. Compatible with a wide variety of high resolution color
graphics systems including RS-343A/RS-170 and the proposed SMPTE 240M standard for HDTV.

VIDEO DIA CONVERTERS 6-37

•

.'TIONS = +5 V± 5%; V = +1.235
V; =37.5.n, C =10 pF;
ADV7121
..•. .
- SPECIFIC" 5 6 0 . n . All Specifications
to
unless otharwise ..oted:) .
(VAA

,"'

RL

REF

Tmot

Tmin

.:

J Version

Par~ter

STATIC PERFORMANCE
Resolution (Each DAC)
AcCl1nlCY (Each DAC)
Integral Nonlinearity, INL
Differential Nonlinearity, DNL
Gray Scale Error
Coding

K Vel$i~D

.Units

L

',' ~

'.

'.

,""

Test CoDditions/C~en!S

RSET

-:~

'j.

,

Output Current
White Level
Black Level
LSB Size
DAC to DAC Matching
Output Compliance, Voc

,
,

Output Impedance, ROUT
Output Capacitance, COUT

VOLTAGE REFERENCE
Voltage Reference Range, VREF
Input Current, IVREF
POWER REQUIREMENTS
VAA
IAA
Power Supply Rejection Ratio'
Power Dissipation
DYNAMIC PERFORMANCE
Glitch Impulse" 3
DAC Noise" 3, 4
Analog Output Skew

··:i>;

.~,.

10

10

Bits

±3
+1.5/-1.0
±5

±2
±I
±5

LSB max
LSB max
% Gray Scale max
Binaty

Guaranteed Monotonic
Max Gray Scale Current

= (VREF* 7,969/ RsET)mA
.,

DIGITAL INPUTS
Input High Voltage, V,NH
Input Low. Voltage, V ,NL
Input Current, l'N
Input Capacitance, C 'N
ANALOG OUTPUTS
Gray Scale Current Range

=

. .',

.
.. .

2
0.8
±I
10

2
0.8
±I
10

V min
V max
fLAmax
pFmax

15
22

15
22

mAmin
mAmax

16.74
18.50
0
50
17.28
5
-1
+1.4
100
30

16.74
18.50
0
50
17.28
5
-1
+1.4
100
30

mAmin
mAmax
fLA.min
fLAmax
fLAtyP
% max
V min
V max
ill typ
pFmax

Typically 17.62 mA

1.1411.26
-5

1.14/1.26

V minIVmax
mAtyp

VREF

-5

5
125
100
0.5
625
500

5
125
100
0.5
625
500

V nom
mAmax
mAmax
%I%max
mWmax
mWmax

Typically 80 mA: 80 MHz Parts
Typically 70 mA: 50 MHz & 35 MHz Parts
Typically 0.12 %1%: f = I kHz, COMP = 0.1 fLF
TypiCally 400 mW: 80 MHz Parts
Typically 350 mW: 50 MHz & 35 MHz Parts

50
200
2

50
200
2

pV secs typ
pV secs typ
ns max

Typically I ns

Y'N

= 0.4 V or2.4 V·

Typically 5 fLA

Typically 2%

lOUT': 0 mA

= 1.235 V for

Specified Performaitce

NOTES
'Temperature Range (Tmin to T m . .): 0 to + 70'C.
'Sample tested at 25"C to ensure compliance.
'TTL input values are 0 to 3 volts, with input rise/fall times ;,,;3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. See timing notes in Figure 1.
"This includes effects due to clOCk and data feed~hrough as well as RGB analog crosstalk.

Specifications subject to change

~ithout

notice.

6-38 VIDEO DIA CONVERTERS

REV. A

ADV7121/ADV7122
V ± 5%; VREf = +1.235 V; = 37.5 n, C = 10 pF;
ADV7122 - SPECIFICATIONS 560 n.= +5All Specifications
T to Tmax unless otherwise noted.)
(VAA

RL

mln

Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Noti1inearity, INL
Differential Nonlinearity, DNL
Gray Scale Error

IVenion

K Venioo

Units

\0

\0

Bits

±3

±2
±1
±5

LSBmax
LSBmax
% Gray Scale max

+ 1.5/-1.0
±5

Coding

L

RSET

=

1

Test Con4itionsiComments

Guaranteed Monotonic
Max Gray Scale Current: lOG = (VREF*12.0S2!RsET) rnA
lOR, lOB = (VREF*S,627IRsET) rnA

Binary

DIGITAL INPUTS
Input High Voltage, V INH
Input Low Voltage, V INL
Input Current, liN
Input Capacitance, C IN

,

ANALOG OUTPUTS
Gray Scale Currenl Range
Output Current
White Level Relative to Blank
White Level Relative to Black
Black Level Relative to Blank
Black Level on lOR, lOB
Black Level on lOG
Sync Level on lOG
LSB Size
DAC to DAC Matching
Output Compliance, Voc
Output Impedance, RoUT'
Output Capacitance, C OUT'
VOLTAGE REFERENCE
Voltage Reference Range, VREF
Input Current, IVREF
POWER REQUIREMENTS
VAA
IAA
Power Supply Rejection Ratio'
Power Dissipation
DYNAMIC PERFORMANCE
Glitch Impulse" 3
DAC Noise" 3. 4
Analog Output Skew

2
O.S
±1
\0

2
O.S
±1
\0

V min
V max
fLAmax
pFmax

15
22

15
22

mAmin

17.69
20.40
16.74
IS.50
0.95
1.90
0
50
6.29
9.5
0
50
17.2S
5
-1
+1.4
100
30

17.69
20.40
16.74
IS.50
0.95
1.90
0
50
6.29
9.5
0
50
17.2S
5
-1
+1.4
100
30

rnA
rnA
rnA
rnA

1.1411.26
-5

1.14/1.26
-5

V minIV max
mAtyp

5
125
100
0.5
625
500

5
125
100
0.5
625
500

V nom
rnA max
rnA max
%1% max
mWmax
mWmax

Typically SO rnA: SO MHz Parts
Typically 70 rnA: 50 MHz & 35 MHz Parts
Typically 0.12%1%: f = 1 kHz, COMP = 0.01 fLF
Typically 400 m W: SO MHz Parts
Typically 350 mW: 50 MHz & 35 MHz Pans

50
200
2

50
200
2

pV sees typ
pV secs typ
ns max

Typically 1 ns

V IN

= 0.4 V or 2.4 V

rnA max

min

max
min
max
rnA min
rnA max
fLAmin
fLAmax
rnA min
rnA max
fLAmin
fLAmax
fLA Iyp
% max
V min
V max
kG typ
pFmax

Typically 19.05 rnA
Typically 17.62 rnA
Typically 1.44 rnA

II

Typically 5 fLA
Typically 7.62 rnA
Typically 5 fLA

Typically 2%

lOUT

= OmA

V REF

=

1.235 V for Specified .Performance

NOTES
'Temperature Range (T min to T m~): 0 to + 70"<:.
'Sample tested at 2S'C to ensure compliance.
'TTL input values are 0 to 3 volts, with input rise/fall times '" 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. See timing notes in Figure 1.
'This includes effects due to clock and data feedthrOligh as weD as RGB analog crosstalk.
Specifications subject to change without notice.

REV. A

VIDEO DIA CONVERTERS 6-39

ADV71211ADV7l22

TIMING CHARACTERISTICS1 All(VAlSpecifications
= +5 V± 5%; VREF = +1.235 V; RL =37.5 n, CL = 10 pF; Rsrr = 5600.
T to Tm./ unless otherwise· noted.)
min

Parameter

80 MHz Versions

50 MHz Versions

30 MHz Versions

Units

ConditioulComments

fmax
t,
t2
t3

80
3
2
12.5
4
4
30
20
3
12

50
6
2
20
7
7
30
20
3
15

30
8
2
33.3

MHz max
nsmin
nsmin
nsmin
nsmin
nsmin
nsmax
nstyp
nsmax
nstyp

Dock Rate
Data & Control Setup Time
Data & Control Hold Time
Dock Cycle Time
Dock Pulse Width High Time
Clock Pulse Width Low Time
Analog Output Delay

~

t,
t.
t7
ts'

9
9
30
20
3
15

Analog Output RiseJFaII Time
Analog Output Transition Time

NOTES
'TIL input values are 0 to 3 volts, with input rise/fall times ,;3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. See timing notes in Figure 1.
'Temperature range (Tm;n to T ~,): 0 to + 70'C.
'Sample tested at +2S'C to ensure compliance.
Specifications subject to change without notice.

ANALOG OUTPUTS
(lOR, lOG, lOB) _ _ _ _ _ _ _ _ _ _ _ _- - (

NOTES

1. OUTPUT DELAY (t, ) MEASURED FROM THE 50% POINT OF THE
RISING EDGE OF THE CLOCK TO THE 50% POINT OF
FULL-SCALE TRANSITION.
2. TRANSITION 11ME (t. ) MEASURED FROM THE 50% POINT OF
FULL-SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT
VALUE.
3. OUTPUT RlSEIFALL nME ( t, ) MEASURED BETWEEN THE 10%
AND 110% POINTS OF FULL-scALE TRANSITION.
4. SYNC AND BLANK DIGITAL INPUTS ARE NOT PROVIDED ON
THE ADV7121.

Figure 1. Video Input/Output Timing

RECOMMENDED OPERATING CONDITIONS

tHW VIDEO DIA CONVERTERS

Parameter

Symbol

Min

Typ

Max

Units

Power Supply
Ambient Operating
Temperature
Output Load
Reference Voltage

VAA

4.75

5.00

5.25

Volts

TA
RL
VREP

0
1.14

+70
37.5
1.235

1.26

"C

n

Volts

REV. A

ADV7121/ADV7122
ORDERING GUIDE

Model

Speed

Accuracy
DNL INL

Temperature

Package
Option'

ADV7121JN80
ADV7121JN50
ADV7121JN30
ADV7121KN80
ADV712IKN50
ADV7121KN30

80 MHz
50 MHz
30 MHz
80MHz
50MHz
30 MHz

+1.5
+1.5
+1.5
±1
±1
±1

±3
±3
±3
±2
±2
±2

O"C
OOC
O"C
OOC
OOC
O"C

to
to
to
to
to
to

+ 70·C
+ 70"<:
+ 7O"C
+70·C
+7O"C
+70"<:

N-40A
N-40A
N-40A
N-40A
N-40A
N-40A

ADV7122JP80
ADV7122JP50
ADV7122JP30
ADV7122KP80
ADV7122KP50
ADV7122KP30

80 MHz
80 MHz
80 MHz
80 MHz
50 MHz
30 MHz

+1.5
+ 1.5
+1.5
±1
±1
±1

±3
±3
±3
±2
±2
±2

O"C
O"C
O"C
O"C
0"<:
O"C

to
to
to
to
to
to

+ 700C
+70"<:
+ 70·C
+ 70"<:
+70"<:
+ 700C

P-44A'
P-44A'
P-44A'
P-44A'
P-44A'
P-44A'

ABSOLUTE MAXIMUM RATINGS·
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Voltage on Any Digital Pin ..... GND -0.5 V to VAA +0.5 V
Ambient Operating Temperature (TA ) • • • • • • • • • 0 to +70"C
Storage Temperature (Ts) . . . . . . . . . . . . . -65°C to + 150"C
Junction Temperature (TJ) . • . • • • . . • . • • . . • • • • • +175°C
Soldering Temperature (5 sees) . . . . . . . . . . . . . . . . . 220·C
Vapor Phase Soldering (I minute) . . . . . . . . . . . . . . . 220"C
lOR, lOB, lOG to GNDI . . . . . . . . . . . . . . . . . 0 V to VAA
NOTES
·Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions ahove those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
1 Analog output short circuit to any power supply or common can be of an
indefinite duration.

NOTES
IN = Plastic DIP; P = Plastic Leaded Chip Carrier. For outline information see

Package Information section.
'PLCC: Plastic Leaded Chip Conier (J-Iead).

CAUTION _________________________________________________
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted.

PIN CONFIGURATIONS
PLCC (P-44A) Package

DIP (N-40A) Package

ADV7121 DIP
ADV7122 PLCC
TOP VIEW
(Not to Scale)

REV. A

TOPYIEW
(Not to Scale)

VIDEO DIACONVERTERS 8-41

•

ADV7121/ADV7122,
PIN, J1(]NCTION -DESCRIPTION

Pin
Mnemonic

Function

BLANK*

Composite blank control 'input (TIL compatible). A logic zero on this control input drives the analog outputs,
lOR, lOB and lOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While
BLANK is a logical zero, the R~R9, ~9 and R~R9 pixel inputs are ignoted,
Composite sync control input (TIL compatible). A logical zero on the SYNC input switches off a 40 IRE
current source. This is internally connected to the lOG analog output. SYNC does not override any other
control or data input, therefore, it should only be asserted during the blanking interval. SYNC is latched on the
rising edge of CLOCK.
If sync information is not required on,the
channel, the SYNC input should be tied to logical zero.

Iireen

CLOCK

Clock input (TIL compatible). The rising edge of CLOCK latches the R~R9, ~9, B~B9, SYNC and
BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be
driven by a dedicated TTLbuffer.
'

R~R9,

Red, green and blue pixel data inputs (TIL compatible). Pixel data is latched on the rising edge of CLOCK.
RO, GO and BO are the least significant data bits. Unused pixel data inputs should be connected to either the
regular PCB power or ground plane.

GO-G9,
B~B9

lOR, lOG, lOB

Red, green, and blue current outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75 0 coaxial cable. All three current outputs should have similar output loads whether or not
they are all being used.
"

FSADJust

FUn-scale adjust control. A resistor (RSBT) connected between this pin and GND, controls the magnitude of the
full-scale "Video signal. Note that the IRE relationships are maintained, regardless of the full-scale output

.,

.. '

clirreiit:
The relationship between RSBT and the full-scale output current on lOG (assuming ISYNe is connected to lOG)
is given by:
RSBT (0)

"12,082

X

VRBF (V)IIOG (mA)

The relationship between RSBT and the full-scale output current on lOR, lOG and lOB is given by:
IOG* (mA)
lOR, lOB (mA)

12,082 x VRBF CV)/RSBT (0)
8,628 x VRBF CV)/RSBT (0)

(SYNC being asserted)

The equation for lOG will be the same as that for lOR and lOB when SYNC is not being used, i.e., SYNC
tied permanently low. For the ADV7121, all three analog output currents are as described by:
COMP

lOR, lOG, lOB (mA)
7,969 x VRBF (V)/RSBT (0)
Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 ",F ceramic capacitor
must be connected between COMP and VAA'
Voltage reference input. An external 1.23V voltage reference must be connected to this pin. The use of an
external resistor divider network is not recommended. Pi: 0.1 fLF decoupling ceramic capacitor should be
connected between VRBF and VAA'
"

VAA

Analog power supply (5 V ± 5%). All VAA pins on the ADV71211ADV7122 must be connected.

GND

Ground. All GND pins mUl;t be connected.

·SYNC and BLANK functions are not provided on the ADV7121.

~2

VIDEO DIA CONVERTERS

REV. A

ADV7121/ADV7122
TERMINOLOGY
Blanking Level
The level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level which will shut off the picture tube, resulting in the blackest possible picture.
Color Video (RGB)
This usually refers to the technique of combining the three primary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
Sync Signal (SYNC)
The position of the composite video signal which synchronizes
the scanning process.
Gray Scale
The discrete levels of video signal between reference black and
reference white levels. A IO-bit DAC contains 1024 different
levels, while an 8-bit DAC contains 256.

CIRCUIT DESCRIPTION & OPERATION
The ADV71211ADV7122 contains three 10-bit D/A converters,
with three input channels, each containing. a 10-bit register. Also
integrated on board the part is a reference amplifier. CRT control functions BLANK and SYNC are integrated on board the
ADV7122.
Digital Inputs
Thirty bits of pixel data (color information) RO-R9, GO-G9 and
BO-B9 are latched into the device on the rising edge of each
clock cycle. This data is presented to to the three IO-bit DACs
and is then converted to three analog (RGB) output waveforms.
See Figure 2.
The ADV7122 has two additional control signals, which are
latched to the analog video outputs in a similar fashion.
BLANK and SYNC are each latched on the rising edge of
CLOCK to maintain synchronization with the pixel data stream.
The BLANK and SYNC functions allow for the encoding of
these video synchronization signals onto the RGB video output.
This is done by adding appropriately weighted current sources
to the analog outputs, as determined by the logic levels on the
BLANK and SYNC digital inputs. Figure 3 shows the analog
output, RGB video waveform of the ADV71211ADV7122 . The
influence of SYNC and BLANK on the analog video waveform
is illustrated.

Raster Scan
The most basic method of sweeping a CRT one line at a time to
generate and display images.
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Reference White Level
The maximum positive polarity amplitude of the video signal.
Sync Level
The peak level of the SYNC signal.
Video Signal
That portion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion which may
be visually observed.

Table I details the resultant effect on the analog outputs of
BLANK and SYNC.
All these digital inputs are specified to accept TTL logic levels.
Clock Input
The CLOCK input of the ADV71211ADV7i22 is· typically the
pixel clock rate of the system. It is also known as the dot rate.
The dot rate, and hence the required CLOCK frequency, will
be determined by the on-screen resolution, according to the following equation:
Dot Rate = (Horiz Res) x (Vert Res) x (Refresh Rate )/
(Retrace Factor)

Horiz Res

Number of Pixels/Line.

Vert Res

Number of LineslFrame.

Refresh Rate

Horizontal Scan Rate. This is the rate at
which the screen must be refreshed, typically 60 Hz for a noninterlaced system
or 30 Hz for an interlaced system.

Retrace Factor

Total Blank Time Factor. This takes
into account that the display is blanked
for a certain fraction of the total duration of each frame (e.g., 0.8).

CLOCK

ANALOG OUTPUTS
(lOR. lOG. lOB)

-------------1r----J
Figure 2. Video Data lriput/Output

REV. A

VIDEO DIA CONVERTERS 6-43

6

ADV71211ADV7122
If we therefore have a graphics system with a 1024 x 1024 resolution, a noninterlaced 60 Hz refresh rate and a retrace factor of
0.8, then:
1024 x 1024 x 60/0.8
78.6 MHz

Dot Rate

RED,BLUE

The required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the
ADV71211ADV7122 on the rising edge of CLOCK, as previously described in the "Digital Inputs" section. It is recommended that the CLOCK input to the ADV7121/ADV7122 be
driven by a TTL buffer (e.g., 74F244).

GREEN

mA

V

mA

V

19.05

0.714

26.67

1.000

-.---"",c---~--------~...-----

WHITE LEVEL

1.44

0.054

9.05

0.340

;-------t----T----------

BLACK LEVEL

7.62

0.286

;------~--,-~--~----------

BLANK LEVEL

~-------~~--------~--

SYNC LEVEL

0

0

0

0

NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 7SU LOAD.
2. VREF = 1.235V, RSET =560U •
3.R&-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.

Figure 3. RGB Video Output Waveform

Description

lOG
(mA)'

lOR, lOB
(mA)

SYNC

BLANK

DAC
Input Data

WHITE LEVEL
VIDEO
VIDEO to BLANK
BLACK LEVEL
BLACK to BLANK
BLANK LEVEL
SYNC LEVEL

26.67
video + 9.05
video + 1.44
9.05
1.44
7.62
0

19.05
video + 1.44
video + 1.44
1.44
1.44
0
0

1
1
0
1
0
I
0

I
1
1
1
1
0
0

3FFH
data
data
OOH
OOH
xxH
xxH

NOTE
'Typical with full-scale lOG

= 26.67 mAo VREF = 1.235 V, RSET = 560 fl. ISYNC connected to lOG.

Table la. Video Output Truth Table for the ADV7122

Description

lOR, lOG, lOB (mA)'

DAC Input Data

WHITE LEVEL
VIDEO
VIDEO to BLACK
BLACK LEVEL

17.62
video
video

3FF
data
data
OOH

NOTE
'Typical with full-stale

o

= 17.62 mAo VREF = 1.235 V. RSET = 560 fl.

Table lb. Video Output Truth Table for the ADV7121

6-44 VIDEO DIA CONVERTERS

REV. A

ADV7121/ADV7122
Video Synchronization & Control
The ADV7122 has a single composite sync (SYNC) input control. Many graphics processors and CRT controllers have the
ability of generating horizontal sync (HSYNC), vertical sync
(VSYNC) and composite SYNC.
In a graphics system which does not automatically generate a
composite SYNC signal, the inclusion of some additional logic
circuitry will enable the generation of a composite SYNC signal.
The sync current is internally connected directly to the lOG
output, thus encoding video synchronization information onto
the green video channel. If it is not required to encode sync information onto the ADV7122, the SYNC input should be tied to
logic low.
Reference Input
An external 1.23 V voltage reference is required to drive the
ADV7121/ADV7122. The AD589 from Analog Devices is an
ideal choice of reference. It is a two-termina1, low cost, temperature compensated bandgap voltage reference which provides a
fixed 1.23 V output voltage for input currents between 50 ...A
and 5 mAo Figure 4 shows a typical reference circuit connection
diagram. The voltage reference gets its current drive from the
ADV71211ADV7122's VAA through an on-board I kO resistor to
the VREF pin. A O.I ...F ceramic capacitor is required between
the COMP pin and VAA. This is necessary so as to provide compensation for the internal reference amplifier.
A resistance RSET connected between FS ADJUST and GND
determines the amplitude of the output video level according to
Equations I and 2 for the ADV7122 and Equation 3 for the
ADV7121:
IOG* (mA) = 12,082 x V REF (V)IR SET (0) . . . . . . . . . (I)
lOR, lOB (mA)

= 8,628 x V REF (V)lRSET (0) . . . . . . (2)
= 7,969 x V REF (V)IRSET (0) .. (3)

lOR, lOG, lOB (mA)

*Only applies to the ADV7122 when SYNC is being used. If
SYNC is IIOt being encoded onto the green channel, then

Using a variable value of RSET> as shown in Figure 4, allows for
accurate adjustment of the analog output video levels. Use of a
fixed 560 0 RSET resistor yields the analog output levels as
quoted in the specification page. These values typically correspond to the RS-343A video waveform values as shown in
Figure 3.
D/A Converters
The ADV71211ADV7122 contains three matched IO-bit D/A
converters. The DACs are designed using an advanced, high
speed, segmented architecture. The bit currents corresponding
to each digital input are routed to either the analog output
(bit = "I") or GND (bit = "0") by a sophisticated decoding
scheme. As all this circuitry is on one monolithic device, matching between the three DACs is optimized. As well as matching,
the use of identical current sources in a monolithic design guarantees monotonicity and low glitch. The on-board operational
amplifier stabilizes the full-scale output current against temperature and power supply variations.
Analog Outputs
The ADV71211ADV7122 has three analog outputs, corresponding to the red, green and blue video signals.
The red, green and blue analog outputs of the ADV71211
ADV7122 are high impedance current sources. Each one of
these three RGB current outputs is capable of directly driving a
37.5 0 load, such as a doubly terminated 75 0 coaxial cable.
Figure 5a shows the required configuration for each of the three
RGB outputs connected into a doubly terminated 75 0 load.
This arrangement will develop RS-343A video output voltage
levels across a 75 0 monitor.
A suggested method of driving RS-170 video levels into a 75 0
monitor is shown in Figure 5b. The output current levels of the
DACs remain unchanged, but the source termination resistance,
Zs, on each of the three DACs is increased from 75 0 to 150 o.
...----.. lOR, lOG, lOB
~

Zo = 75n

n-----~~~--~

Equation 1 will be similar to Equation 2.
(CABLE)
ANALOG POWER PLANE

Zs= 751!
(SOURCE
TERMINATION)

.5V
COMP

ZL=75n
(MONITOR)

t----'

TERMINATION REPEATED THREE TIMES
FOR RED, GREEN AND BLUE DACs

IAliF==5mA

Figure 5a. Analog Output Termination for RS-343A
...-----....
500U
R... {
560U

AD5119
(1.235V
VOLTAGE
REFERENCE)

I~, IOB,.._-......:Z;::o.:;.=.:;75:::1l=--__..
(CABLE)

10011

ZL=75n
(MONITOR

ADV7121IADV7122"

'ADDITIONAL CIRCUITRY. INCLUDING
DECOUPLING QOMPONENTS,
EXCLUDED FOR CLARITY

Figure 4. Reference Circuit

REV: A

TERMINATION REPEATED THREE TIMES
FOR RED, GREEN AND BLUE DACe

Figure 5b. Analog Output Termination for RS-170
VIDEO DIA CONVERTERS ~

II
I

ADV7121/AQV7122
More detailed information regarding load. terminations for various output configurations, indudillg RS-.343A and RS-170, is
available in
Application Note entitled "Video Formats &
Required Load Terininations"av8ilable f~m Analog Devices,
"
publicatIon no. EI228-l5":1I89.

an

Figure 3 shows the video waveforms associated with the three '
RGB outputs driving the doubly terminated 7S 0 load of Figure 5a. As well as the gray scale levels, Black Level to White
Level, the diagram also shows the contributions of SYNC and
BLANK for the ADV7122. These control inputs add approc
priately weighted currents to the analog outputs, producing
the specific output level requirements for video applications.
Table la details how the SYNC and BLANK inputs modify
the output levels.
Gray Scale Operation
The ADV7121lADV7I22 can rn.: used fQ~~tand-al(Jne, gray scale
(monochrome) or composite video applications (i.e., only one
channel used for video information). Anyone of the three channels, RED, GREEN or BLUE can be used to input the digital
video data. The two unused video.data channels should be tied
to logical zero. The unused analog outputs should be terminated
with the same load as thai for the used channel. In other words,
if the red channel is used and. lOR is terminated with a doublyterminated 75 0 load.(37.5 0), lOB and lOG should be terminated with 37.5 0 resistors. See Figure 6.

Video Output Buffers
.
The ADV712llADV7122 is speCified t6 dnve transmi$Sion line
loads, which is what most monitors are rated as. The aDaJog ,
output configurations to 

80

Rl

R2

R3

75,U

75u

7511

~

~~""'-GRDUND
L2 (FERRITE BEAD)

RGB

VIDEO
OUTPUT

INPUTS

L-_ _ _ _ _ _.J ·SYNC and BLANK functions are not provided on the ADV7121.
COMPONENT
C1
C2
C3. C4. CS.C6
Lt, L2
Rl. R2. R3

Rm
Z1

DESCRIPTION
33.F TANTALUM CAPACITOR
10.F TANTALUM
0.1.F CERAMIC CAPACITOR
FERRITE BEAD

7512 1% METAL FlUI RESISTOR
560U 1% METAL FILM RESISTER
1.23SV VOLTAGE REFERENCE

VENDOR PART NUMBER

FAIR·AITE 274300111 OR MURATA BL01t02103
DALE CMF·SSC
DALE CMF·SSC
ANALOG DEVICES AD589JH

Figure 8. ADV7121IADV7122 Typical Connection Diagram and Component List

REV. A

VIDEO DIA CONVERTERS 6--47

II

6-48 VIDEO DIA CONVERTERS

ANALOG
WDEVICES

11IIIIIIII

CMOS Continuous Edge Graphics
~-DACs{CEGIDACs)

ADV7141/ADV7146/ADV7148* I
FEATURES
Proprietary Antialiasing Function
Deiagging of Lines. Arcs. Circles. Fonts. atc.
Effective 24-Bit True Color Performance
Dynamic Palette Load (DPL) Function
Plug-in Upgrade for Standard VGA RAM-DACs
ADV4781ADV471. ADV476 (ADV3) & Inmos 1711176t
Fully PS/2t. VGAt and 8514/At Compatible
66 MHz Pipalinad Operation
Triple 8-Bit/6-Bit D/A Converters
256 x 24 (18) Color Palette RAM
On-Board Gamma-Correction
On-Board Antisparkle Circuit
RS-343A/RS-170 Compatible Outputs
External Voltaga or Current Reference
Standard MPU Interface
+5 V CMOS Monolithic Construction
APPLICATIONS
High Resolution Color Graphics
True Color Graphics
Digital Typography (Smooth Fonts)
Scientific Visualization
3-D Solids Modeling
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Desktop Publishing
AVAILABLE CLOCK RATES
66 MHz
50 MHz
35 MHz

GENERAL DESCRIPTION
The Analog Devices' Continuous Edge Graphicst RAM-DAC
(CEGtIDAC) dramatically improves image quality of standard
analog color systems, by eliminating the jagged edges of computer generated images (antia1iasing) and by providing an
extended color palette for 3D modeling. This increased performance is achieved while at the same time maintaining full pin
and functional compatibility with existmg video RAM-DACs
and color palettes used in VGA graphics systems.
The CEG/DAC implements a proprietary antialiasing or
"dejagging" function. This is used to smooth the jagged edges
associated with lines, circles and other nonrectangular objects
displayed on a regular CRT screen. The part also allows for the
effective display of 24-bit true color images on a standard 8-bit
system, without the requirement of increased memory. More
than 740,000 colors can be simultaneously displayed on an
8-bitlpixel system as against the 256 colors normally associated
with 8-bitlpixel systems. This is achieved by a combination of
the antia1iasing function and a unique dynamic palette load

REV. 0

FUNCTIONAL BLOCK DIAGRAM

(DPL) feature. DPL allows for color palette writes (color alterations) during a single frame image.
The CEG/DAC combines a color lookup table (CLUT), three
matched video speed computational units and associated control
logic as well as three digital-to-analog converters (DACs). These
all combine to significantly enhance the video image display
quality of standard 8-bitlpixel graphics systems.
The ADV7148 and ADV7141 are pin and functional compatible
with the ADV478 and ADV471, with the exception that the
ADV7148 and the ADV7141 do not contain the overlay palette.
The ADV7146 is pin and functional compatible with the
ADV476 and the Inmos IMSGl7l/176.
CEG requires two closely connected components-the CEGI
DAC chip and the software driver. Conventional antia1iasing
schemes are implemented entirely in software and operate on
the pixel data in the graphics pipeline, resulting in a significant
speed performance penalty. In contrast, the CEG software
-driver takes application software information and encodes the
frame buffer with a sequence of data and commands for the
CEG/DAC. The CEGIDAC hardware performs all of the antialiasing calculations. In this way, the visual benefits _of antialiased graphics are provided with a minima1 increase in
software overhead.
"Proteeted by U.S. Patent Nos. 4,482,893 and 4,704,605.
tlnmos is a trademark of lnmosLtd.
PenonaJ Systeml2, VGA and 85141A are trademarks of Intematicmal
Business Machines Corp.
Edsun Continuous Edae Graphics and CEG are rqisterecI trademarks of
Edsun Laboratories, Inc.
ADV is a rqisterecI trademark of ADalog Devices, Inc.

VIDEO DIA CONVERTERS

~

II

ADV7141/ADV7146/ADV7148-SPECIFICATIONS ~~:1:}2~5S:~~:Y~'::A~7~4~);
IREF ,;, -'8,,39 IhA~ADVn46); RL

= 37.5 n, cL = 10 pF; Rsri '::: 147·0. All Specifications 1mln to 1max

2

Patameter
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Eatlt:"DAC)
Integral Non1lp~rity'
Differential Nonlinearity
Gray Scale Error
Coding
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, lIN
Input Capacitan!=t!; CIN
DIGITAL OUTPUTS
Output High V.oltage, VOH
Output Low Voltage; VOL
Floating-SiateLeakage Current
Floating-State Leakage. Capacitance
ANALOG OUTPUTS
Gray Scale Current Range
Output Current
White Level Relative to Blank/Black
White Level Relative to Black"
Black Leve1.Relative to Blank"
(Pedestal = 7.5 IRE)
Black Level Relative to Blank
(Pedestal = 0 IRE)
Blank Level'
(Sync Enabled)
Blank Level
(Sync Disabled)
Sync Level'
LSB size
DAC to DAC Matching
Output Compliance, Voc
Output Impedance, RoUT
Output Capacitance, COOT
VOLTAGE REFERENCE
Voltage Reference Range
Input Current, IVREF
CURRENT REFERENCE
Input Current (IREF) Range
Voltage at IREF
POWER SUPPLY
Supply Voltage, VAl.

..

All Versions

Units

8

Bits

± I (± 112)
±I
±5

LSBmax
LSBmax
% Gray Scale
Binary

2
0.8
±l
7

V min
V max
!LA max
pFmax

2.4
0.4
50
7

V min
V max
/.LA max
pFmax

20

mAmax

17.4/20.40
16.5/18.50
0.95

rnA
rnA
rnA
rnA

0
50
6.29
8.96
0
50
0
50
69.1
5
0/+ 1.5
10
30

minlrnA max
minlrnA max
min
max
!LA min
!LA max
rnA min
rnA max
/.LA min
!LA max
!LA min
/.LA max
/.LA typ
% max
V minIV max
kG typ
pFmax

1.14/1.26
10

V minIV max
/.LA typ

-3/-10
V= - 31V=

rnA minlrnA max
V minimax

4.7515.25
4.50/5.50
350
0.5

V minIV max
V minlVmax
rnA max
%1% max

-30
75
-23

dBtyp
pV sees typ
dB typ

1.90

ulilessl!tberwise noted.)

.

Test Conditions/Comments

Guaranteed 'Monotonic

= 0.4 Vor 2.4 V
= I MHz, VIN = 2.4 V

VIN

f

ISOURCE = 400 /.LA
Isn./K = 3.2 rnA

Typically 19.05 rnA
Typically 17.62 rnA, SETUP = VAA
Typically 1.44 rnA,. SETUP = VAA
Typically 5 !LA, SETUP = GNP
Typically 7.62 rnA
Typically 5 /.LA .
Typically 5 /.LA
Typically 2%

ADV7148 & ADV7141 Only

ADV7146 Only

Supply Current, IAA
Power Supply Rejection Ratio
DYNAMIC PERFORMANCE
Clock and D.ata FeedthroughS' 6
Glitch ImpulseS. 6
DAC to DAC Crosstalk7

..

66 MHz Parts
50 & 35 MHz Parts
TypicaUy 200 rnA
f =1 kHz, COMP ,,; 0.1 /.LF

NOTES
'",5% for 66 MHz parts; ",10% for 50 MHz & 35 MHz pans.
2Temperature tange (T~in to T mix): 0 to + 700(:.
'Tested to g-bitlinearity (tested to 6-bitlinearity, ADV7146 only).
'ADV7l4l andADV714g·only.
'Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and' data feedthrough.
'TTL input values are 0 to 3 volts, with input riselfalltimes 53 ns, measured at the 10% and 90% points. Timing reference poiots at 50% for inputs andoulputs.
'DAC to DAC crosstalk is measured by holding one DAC high while the other two are makiog low to high and high 10 low transitions.
Specificatioos subject to change without notice.

(J...50 VIDEO DIA CONVERTERS

REV. 0

ADV7141/ADV7146/ADV7148
= 5 V; SETUP = Blii = vAA; V = 1.235 V (~~V71.4B/ADV7141); IRV = -B.39 m~ (ADV7146);
TIMING CHARACTERISTICS1 (VAA2
RL = 3750, CL= 10 pF· RSET = 147 0. All Specifications Tm·. to Tm". unless otherwise noted.)
REF

I

Parameter

f max
t,
t,
t:
t:
tss
tos
t7
t8
to
tlO
tll
t"
t13

66 MHz
Version

50 MHz
Version

35 MHz
Version

Units

Conditions/Comments

66
10
10
2
40
20
5
10
15
50
6 X t13
3
3
IS

35
15
15
2
40
20
5
15
15
SO
6 X t13
4
4
28
7
9
30
3
28
2

MHz
nsmin
ns min
ns min
ns max
ns max
nsmin
nsmin
nsmin
nsmin
nsmin
ns min
nsmin
nsmin

30
3
13
2

50
10
10
2
40
20
5
10
15
SO
6 X t13
3
3
20
6
6
30
3
20
2

Qock Rate
RSO-RSI Setup Time
RSO-RSI Hold Time
RD Asserted to Data Bus Driven
RD Asserted to Data Valid
RD Negated to Data Bus 3-Stated
Read Data Hold Time
Write Data Setup Time
Write Data Hold Time
RD, WR Pulse Width Low
RD, WR Pulse Width High
Pixel & Control Setup Time
Pixel & Control Hold Time
Clock Cycle Time
Clock Pulse Width High Time
Clock Pulse Width Low Time
Analog Output Delay
Analog Output Rise/Fall Time
Analog Output Settling Time
Analog Output Skew
Pipeline Delay

3 x t13
6 x t13

3
6

3
6

nsmin
nsmin

5
5

t'4
tIS
t,o
t17
(18 6

t5K
tpD
Compatibility Mode
CEGMode

X
X

t13
t13

X
X

t13
t13

nsmin
nsmin
os max

ns typ
os max
nsmax

NOTES
ITIL input values are 0 to 3 volts, with input rise/fall times $3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load $10 pF, DO-D7 output load ==50 pF. See timing notes in Figure 2.
2:!:S% for 66 MHz parts; ::!: 10% for 50 MHz & 35 MHz parts; tiS measured at VAA :: 5 V for 66 MHz parts.
3Temperature Range (Tmin to T max): 0 to + 70°C.
4t3 and t4 are measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.4 V or 2.4 V.
Sts and 16 are derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging the SO pF capacitor. This means that the times, ts and t 6 , quoted in the timing characteristics are the (rue values for the
device and as such are independent of external bus loading capacitances.
6Settling time does not include clock and data feedthrough.
Specifications subject to change without notice.

RD,WR

00-D7
(READ)

-----.!:~~~~===tj

Figure 1. MPU ReadIWrite Timing

CLOCK

Figure 3. Load Circuit for Bus Access and Relinquish Time

NOTES
1. OUTPUT DELAY MEASURED FROM THE 50% POINT OF THE RISING
EDGE OF CLOCK TO THE 50% POINT OF FULL SCALE TRANmoN.
2. SEn'UNG TIME MEASURED FROM THE 50% POWT OF FULL SCALE
TRANSmoN TO THE OUTPUT REMAINING WITHIN :1:.1 LSI.
3. OUTPUT RISE/FALL nUE MEASURED BETWEEN THE 10%
AND ICI'% POINTS OF FULL SCALE TRANSITION.

ANALOG

~OR~~': - - - - - - - - - - -....II---:::o(
Figure 2. Video Input/Output Timing

REV. 0

VIDEO DIA CONVERTERS 6-51

II

ADV7141/ADV7146/ADV7148
RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol

POWER SUPPLY
66 MHz Parts
50, 35 MHz Parts

VAA

AMBIENT OPERATING TEMPERATURE

TA

OUTPUT LOAD

RL

Min

Typ

Max

Units

4.75
4.5

5.00
5.00

5.25
5.5

Volts
Volts

+70

OC
0

1.26

Volts

-10
-10

rnA
rnA

0
37.5

VOLTAGE REFERENCE CONFIGURATION
Voltage Reference

cJ

N

O

~

A

C

1.14
1.235
VREF
CURRENT REFERENCE CONFIGURATION
IREF CURRENT
IREF
-3
-8.39
STANDARD RS-343A
-3
-8.88
PS/2 Compatible
_________________________________________________

ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted.
ABSOLUTE MAXIMUM RATINGS
VAA to GND . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +7 V
Voltage on Any Digital Pin .... GND -0.5 V to VAA + 0.5 V
Ambient Operating Temperature (T A) ..... -55°C to + 125°C
Storage Temperature (Ts) . . . . . . . . . . . . . -45°C to + 125°C
Junction Temperature (TJ ) . . . • • • • • . . . . • . . . . . • +175°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . + 300°C
Vapor Phase Soldering (2 minutes) . . . . . . . . . . . . . . +22.0°C
lOR, lOG, lOB to GND' . . . . . . . . . . . . . . . . . 0 V to VAA

WARNING!

~~'DUI(E

PIN CONFIGURATIONS
28-Pin DIP
VAA
RSI

RSO

D7

NOTES
*Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
I Analog output shon circuit to any power supply or common can be of an
indefinite duration.

D5
D4
D3
P5

D2

P6

Dl

P7

ORDERING GUIDE

DO
BLANK

CLOCK

Model'

Speed

Resolution'

Package
Option" •

ADV7146KN66
ADV7146KN50
ADV7146KN35

66 MHz
50 MHz
35 MHz

6-Bit
6-Bit
6-Bit

N-28
N-28
N-28

ADV714IKP66
ADV714IKP50
ADV7141KP35

66 MHz
50 MHz
35 MHz

6-Bit
6-Bit
6-Bit

P-44A
P-44A
P-44A

ADV7148KP66
ADV7148KP50
ADV7148KP35

66 MHz
50 MHz
35 MHz

8-Bit/6-Bit
8-Bit/6-Bit
8-Bit/6-Bit

P-44A
P-44A
P-44A

NOTES
°All devices are specified for oce to + 70ce operation.
2Refers to "Compatibility Mode." In "CEG Mode," resolution for all options
is 8 bits.
'28·pin DIP devices are packaged in 28-pin 0.6" plastic dual-in-Iine packages.
44-pin PLCC devices are packaged in 44-pin plastic leaded a-lead) chip
carriers.
4N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC). For outline
information see Package Information section.

AD

GND

44·Pin PLCC

IU

.

Iii! ~ ,1 ~

ii:iNK

G"
z ~

oS

..

g
!l II !! !! II G

7

DO •

ADV7141/ADV7148
TOP VIEW

PO

(Not to Sealo)

He • NO CONNECT; THESE PlMlIlAY eE LEFT UNCONNECTED
.(NC) INDtCATESTMEADV'I'141 ONLY

6-52 VIDEO DIACONVERTERS

REV. 0

ADV7141/ADV7146/ADV7148
PIN FUNCTION DESCRIPTION
Pin
Mnemonic

Function

BLANK

Composite blank control input (TTL compatible). A Logic 0 drives the analog outputs to the blanking level. It is
latched on the rising edge of CLOCK. When BLANK is a logical zero, the pixel and overlay inputs are ignored.

SETUP

Setup control input. Used to specify either a 0 IRE (SETUP
(ADV714I1ADV7148 only).

= GND) or 7.5 IRE (SETUP = VAA) blanking pedestal

Composite sync control input (TTL compatible). A logical zero on this input switches off a 40 IRE current source oli
the analog outputs. SYNC does not override any other conltol or data input, therefore it should be asserted only during
the blanking interval. It is latched on the rising edge of CLOCK (ADV714I1ADV7I48 only).
CLOCK

Clock input (TTL compatible). The rising edge of CLOCK latches the PO-P7, SYNC, and BLANK inputs. It is typically the pixel clock rate of the video system. It is recommended that CLOCK be driven by a dedicated TTL buffer.

PO-P7

Pixel select inputs (TTL compatible). These inputs specify, on a pixel basis, which one of the 256 entries in the color
palette RAM is to be used to provide color information. They are latched on the rising edge of CLOCK. PO is the LSB.
Unused inputs should be connected to GND.

lOR, lOG, lOB

Red, green, and blue current outputs. These high impedance current sources are capable of directly driving a doubly
terminated 75 n coaxial cable.
Current Reference input (Current Reference configuration)lFull-scale adjust control (Voltage Reference configuration).
When using an external voltage reference, a resistor (RsET ) connected between this pin and GND controls the magnitude of the full-scale video signal. The relationship between RSET and the full-scale output current on each output is:
RSET (n) = K x 1,000 x V REF (V)/IOUT (mA)
K is defined in the table below, along with corresponding RSET values for doubly terminated 75 n loads.
When using an external current reference, the relationship between IREF and the full-scale output current on each
output is:
IREF (mA) = lOUT (mA)/K
Mode

Pedestal

K

6-Bit
8-Bit
6-Bil
8-Bil

7.5 IRE
7.5 IRE
o IRE
o IRE

3.170
3.195
3.000
3.025

"For PS/2 applicalions (i.e., 0.7 V inlO 50
a 182 n RSET resistor is recommended..

RoETen)"
147
147
147
147

n with no SYNC),

COMP

Compensation pin. If an external voltage reference is used, this pin should be connected to OPA. If an external current
reference is used, this pin should be connected to IREF' A 0.1 ,...F ceramic capacitor must always be used to bypass this
pin to VAA (ADV7141/ADV7148 only).
Voltage reference input. If an external voltage reference is used, it must supply this input with a 1.2 V (typical) reference. If an external current reference is used, this pin should be left floating, except for the bypass capacitor. A O. I ,...F
ceramic capacitor must always be used 10 decouple this input to VAA (ADV7141/ADV7148 on{y).

OPA

Reference amplifier output. If an external voltage reference is used, this pin must be connected to COMPo When using
an external current reference, this pin should be left floating (ADV714I1ADV7148 onM.
Analog power. All VAA pins must be connected.
Analog ground. All' GND pins must be connected.
Write control input (TTL compatible). DO-D7 data is latched on the rising edge of WR, and RS~RSI are latched on
the falling edge of WR during MPU write operations.
Read control input (TTL compatible). To read data from the device, RD must be a logical zero. RS~RSI are latched
on the falling edge of RD during MPU read operations.

RSO, RSI

Register select inputs (TTL compatible). RS~RSI specify the type of read or write operation being performed.

DO-D7

Data bus (TTL compatible). Data is transferred into and out of the device over this 8-bit bidirectional data bus. DO is
the least significant bit.
8-bitl6-bit select input (TTL compatible). This input specifies whether the MPU is reading and writing 8 bits (logical
one) or 6 bits (logical zero) of color information each cycle. For 8-bit operation, D7 is the most significant bit (MSB)
while for 6-bit operation, D5 is the MSB. D6 and D7 are ignored during 6-bit operation. All parts operate in 8-bit format while in CEG mode. 6-Bit operation is the default VGA mode on the ADV7146 and ADV7141. The 8/6 bit must be
set to LOgical 0 on the ADV7148 to miake it VGA compatible. If left unconnected, this pin remains in a low state.

8/6

CEGDlS

REV. 0

CEG disable (TTL compatible). Driving this pin active high disables all CEG functions. Software will detect a non-CEG
device if this pin is high (ADV7141/ADV7148 only). If left unconnected, this pin remains in a low state.

VIDEO DIA CONVERTERS 6-53

•

ADV7141/ADV7146/ADV7148

CLOCK

>--t-00PA*

BLANK

SYNC·

t---+()

COMP *

256 X 24(18) COLOR

PALETIE

PO-P7

lOR

GREEN

o

256 x 8(6)
RAM

lOG

BLUE
256 x 8(6)

RAM
lOB

00-D7

AD WR

RSO

RS1

8Ii..

SETUP"

CEGDIS·

• NOT AVAILABLE ON THE ADV7146
.... NOT AVAIlABLE ON THE ADV7146; NO CONNECT ON THE ADV7141

Functional Block Diagram of CEGIDAC

6-54 VIDEO DIA CONVERTERS

REV. 0

ADV7141/ADV7146/ADV7148

Color Video (RGB)
This usually refers to the technique of combining the three primary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs
would be required, one for each color.

COLOR 1

B

A

Gray Scale
The discrete levels of video signal between Reference Black and
Reference White levels. An 8-bit DAC contains 256 different
levels while a 6-bit DAC contains 64.
Raster Scan
The most basic method of sweeping a CRT one line at a time to
generate and display images.
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Reference White Level
The maximum positive polarity amplitude of the video signal.
Setup
The difference between the reference black level and the blanking level.
Sync Level
The peak level of the composite SYNC signal.
Video Signal
That portion of the composite video signal which varies in gray
scale levels between Reference White and Reference Black. Also
referred to as the picture signal, this is the portion which may
be visually observed.
ANTIALIASING
Antialiasing is a technique used to smooth the jagged edges associated with lines, circles, and other nonrectangular objects represented on a CRT screen. Without antialiasing, each pixel (picture
element) on a CRT is either "on" or "off." If the edge of a smooth
shape passes through a pixel, the software is forced to approximate the edge as best it can (i.e., the pixel is "on" if more than
half of the pixel is covered by the object). Even when a large
number of pixels are used to represent an object, the eye quickly
detects the series of "on" and "off' dots along the picture edge.
CEG achieves antialiasing by allowing the software to choose not
only the discrete palette colors, but also a linear mix of those
colors. For example, if only 113 of the pixel is covered by an
object, the pixel would be displayed in the ratio of 33:67 between the object color and the background color. The eye
perceives the new boundary as a completely smooth edge. The
software driver defines the value of every pixel on a shape
boundary, thereby dramatically increasing the perceived resolution of any computer display. By mixing colors in real time, the
CEG/DAC can generate up to 800,000 simultaneously display-

REV. 0

-

C

~F

D

f.--I-

G

H

I

J

f...K

COLOR 2

Composite Sync Signal (SYNC)
The position of the composite video signal which synchronizes
the scanning process.
Composite Video Signal
The video signal with or without setup, plus the composite
SYNC signal.

•

SCAN LINE DIRECTION

TERMINOLOGY
Blanking Level
The level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level which will shut off the picture tube, resulting in the blackest possible picture.

~

3

~

~

~

~

~100~

ACTUAL COLOR 2 - ...

Figure 4. An Edge Crossing Scan Line

able colors without altering the contents of the standard 256
color look-up-table.
Figure 4 shows an enlargement of an object edge, with each
square representing a screen pixel. An object is drawn in Color
2 on a background of Color 1- the actual colors are determined
by the contents of the CLUT.
Without CEG, pixels labelled "A" through "E" will be displayed
as Color 1 (Figure 5). Pixels are defined as Color 2 when more
than 50% of the pixel is defined by that color, as shown
in pixels "F" through "}." CEG blends colors to more closely
approximate the intended color boundary as shown in Figure 6.

•

SCAN LINE DIRECTION

COLOR 1

A

I-"

B

C

D

~

.l- f-F r-;

H

I

-J

K

COLOR 2

3

21

38

57

75

~

100

100 100

ACTUAL COLOR 2 - %

Figure 5. Traditional Pixel Coverage (Aliasing)

3

21 38 57 75 93 100 100 100
ACTUAL COLOR 2 - ...

Figure 6. Dejagging or Antialiasing Using CEG

VIDEO DIA CONVERTERS 6-55

6

ADV7141/ADV7146/ADV7148
CEG FUNCTIONAL DESCRIPI10N
CEG uses two data ports, a pixel pon and an MPU data pon.
Three analog signals are produced which can directly drive the
red, green, and blue inputs of a standard analog display monitor. The CEGIDAC consists of four major blocks: CEG logic,
three 8-bit DACs, 256 x 24 lookup table RAM, and MPU
control.
The CEG/DAC is a real-time signal processor which interprets
data in the frame buffer as either colors, mix commands, or
both. CEG uses a special sequence of lookup table acCesses to
enable and disable the CEG logic. The nonCEG mode allows
full backward compatibility with current video palette products.
The circuit is powered-up in nonCEG mode. CEG-aware software activates CEG modes and provides the advantages of aliasfree images.

Systems which use only 4 bits per pixel should be connected to
P3-PO, tying P7-P4 to ground. This fYpe of system must use
the "panial shading" Advanced-4 Method, which allows 8 colors
(0-7) and 8 mix commands (8-15) in increments of 12%.
CEG PROGRAMMING BASICS
CEG Computation
When CEG is active, the CEG/DAC computes a real time
weighted average on each of the primary colors which are read
out of the palette RAM. This calculation, as represented by the
generalized diagram of Figure 7, is expressed by the following
equation:
P MC

where:

= [(Color B x Mix) +
P Me = mixed color.

x

(Color A

In nonCEG systems and software applications, the CEGIDAC

Or alternatively, it can be described by:

behaves identical to normal palette DACs, providing complete
physical and functional compatibility with all VGA compatible
PCs. The CEG/DAC is available in packages compatible with
the most popular palerte DACs, including ADV471, ADV476,
and ADV478 devices.

Mixed color = (ratio of previous color
(ratio of new color x new color)

(31-Mix)

+ 16)] 131

x previous color) +

The mixed colors, one mixed color each for red, green and blue
are then input to a gamma correction circuit. The output of this
circuit drive each of the three RGB-DACs.

MPU Data Port
The MPU data pon allows the system processor to access the
color palerte address register, color palette RAM and pixel mask
register. Register selection is identical to the associated noil'
CEG, VGA compatible parts.

If the CEG device is operating in 8-bit mode, all 8 bits of the
lookup table color data register are significant. In 6-bit modes,
lookup table color data should be written and read back rightjustified to/from D5-DO. During readback, in 6-bit modes, D6
and D7 are forced to Logic O.
Pixel Port
Pixel information is latched into the CEGIDAC via the pixel
pon. For each clock cycle, the state of the P7-PO, BLANK and
SYNC defme the state of the DAC outputs.

CEGMODES
Although there is one algorithm in the CEGIDAC, there are
three ways of encoding the pixels in the frame buffer, namely,
the Basic-8, Advanced-4 and Advanced-8 methods. These are
described as follows:
Basic:-8

16 drawing colors with 8 mixes plus explicit
loading of new or old color (suitable for CAD
type applications where few colors are needed).

Advanc:ed-4

8 drawing colors with 8-mix shading (suitable for
antia1iasing in 4-bitslpixel systems).

Advanc:ed-8

223 drawing colors with full 32-mix shading
(suitable for 3-D solid modeling and true-color
image rendition).

Pixel pon inputs are logically "AND"ed with the contents of the
pixel mask register, for simple animation applications. The pixel
mask register is accessed via the MPU interface. In general, the
pixel mask register should be set to ,FFH for any of the CEG
modes. See Appendix A for sample code to access the pixel
mask register.
Two selectable features in CEG mode are "panial shading" and
"pixel replication." Certain video controllers repeat each pixel
twice in low resolution modes. In these modes, the pixel data is
sampled every other CLOCK.
j' - - - - - - - - - - - - - - - - - - - - - - - -I
INTENSIlY

I,

I

I

GAMMA

CORRECTION

~
I
VIDEO
I

'I

~---~------------~------Figure 7. Block Diagram Representation of the CEG Algorithm

6-56 VIDEO DIA CONVERTERS

REV. 0

ADV7141/ADV7146/ADV7148
CIRCUIT DESCRIPTION
MPU Interface
As illustrated in the functional block diagram, the ADV71411
ADV7146/ADV7148 supports a standard MPU bus interface,
allowing the MPU direct access to the color palette RAM, pixel
mask register and address register.
The RSO-RSI select inputs specify whether the MPU is accessing the address register, color palette RAM, or pixel mask register, as illustrated in Table I. The 8-bit address register is used
to address the color palette RAM.
Table I. Control Input Truth Table
RSI

RSO

Addressed by MPU

o

0
I
I
0

Address Register (RAM Write Mode)
Address Register (RAM Read Mode)
Color Palette RAM
Pixel Read Mask Register

I

o
I

To write color data, the MPU writes the address register with
the address of the color palette RAM location to be modified.
The MPU performs three successive write cycles (8 or 6 bits
each of red, green and blue). During the blue write cycle, the
three bytes of color information are concatenated into a 24-bit
word (l8-bit word for VGA backward compatible data). This
color value is then written to the location in the palette RAM
pointed to by the address register. The address register then
increments and points to the next palette RAM location which
the MPU may modify by simply writing another sequence of
red, green and blue data. See Appendix A for sample code to
write to the palette.
To read color data, the MPU loads the address register with the
address of the color palette RAM location to be read. The MPU
performs three successive read cycles (8 or 6 bits each of red,
green, and blue), using RSO-RSI to select the color palette
RAM. Following the blue read cycle, the address register increments to the next location which the MPU may read by simply
reading another sequence of red, green, and blue data. See Ap-pendix A for sample code to read from the palette.
When accessing the color palette RAM, the address register resets to OOH following a blue read or write cycle to RAM location
FFH.
For 8-bit operation, DO is the LSB, and D7 is the MSB of color
data.
For 6-bit operation, color data is contained on the lower six bits
of the data bus, with DO being the LSB and D5 the MSB of
color data. When writing color data, D6 and D7 are ignored.
During color read cycles, D6 and D7 will be a logical zero.
See Compatibility section for details of 618-bit operation.

REV. 0

Table II. Address Register (ADDR) Operation
Value

RSI RSO Addressed by MPU

ADDRa, b
Counts Modulo 3 00
01

Red Value
Green Value
Blue Value

10

ADDR0-7
Counts Binary

OOH-FFH 0

I

Color Palette RAM

The MPU interface operates asynchronously to the pixel clock.
Data transfers between the color palette RAM and the color registers (R, G, and B in the block diagram) are synchronized by
internal logic, and occur in the .period between MPU accesses.
As only one pixel clock cycle is required to complete the transfer, the color palette RAM may be accessed at any time with no
noticeable disturbance on the display screen.
To keep track of the red, green, and blue read/write cycles, the
address register has two additional bits (ADDRa, ADDRb) that
count modulo three, as shown in Table II. They are reset to
zero when the MPU writes to the address register, and are not
reset to zero when the MPU reads the address register. The
MPU does not have access to these bits. The other eight bits of
the address register (ADDR0-7), incremented following a blue
read or write cycle, are accessible to the MPU, and are used to
address color palette RAM locations, as shown in Table II.
ADDRO is the LSB when the MPU is accessing the RAM. The
MPU may read the address register at any time without modifying its contents or the existing read/write mode.
Figure I illustrates the MPU read/write timing.
Frame Buffer Interface
The PO-P7 inputs are used to address the color palette RAM, as
shown in Table III.
Table III. Pixel Input Truth Table (Pixel Read Mask
Register FFH)

=

PO-P7

Addressed by Frame Buffer

OOH
OIH

Color Palette RAM Location OOH
Color Palette RAM Location OIH

FFH

Color Palette RAM Location FFH

The contents of the pixel read mask register, which may be accessed by the MPU at any time, are bit-wise logically ANDed
with the PO-P7 inputs. Bit DO of the pixel read mask register
corresponds to pixel input PO. The addressed location provides
24 bits (18 bits in compatibility mode) of color information to
the three DIA converters.
(See Application Note entitled "Animation Using the Pixel Read
Mask Register of the ADV47X Series of Video RAM-DACs"
available from Analog Devices, Publication No. E1316-15-10l89.)

VIDEO DIA CONVERTERS 6-57

•
I

ADV7141/ADV7146/ADV7148
MA
26.87

V
1.000

9.05

0.340

7.&2

0.268

BLANK LEVEL

0.00

0.000

SYNC LEVEL

WHITE LEVEL

BLACK LEVEL

NOTES
1. CONNECTED WITH A 75 Q DOUBLY TERMINATED LOAD.
2. EXTERNAL VOLTAGE OR CURRENT REFERENCE ADJUSTED FOR 26.87 mA FULL SCALE OUTPUT.
3. RS • 343A LEVELS A"ND TOLERANCES ASSUMED ON ALL LEVELS.

Figure 8. ADV7141IADV7148 RGB Video Output Waveform (SETUP = VAA )

Table IV. ADV7141/ADV7148 RGB Video Output Truth Table (SETUP

= VAA)

Description

10m (mA)l

SYNC

BLANK

DAC Input Data

WHITE
DATA
DATA·SYNC
BLACK
BLACK·SYNC
BLANK
SYNC

26.67
Data + 9.05
Data + 1.44
9.05
1.44
7.62
0

1
I
0
1
0
1
0

1
1
1
1
1
0
0

FFH
Data
Data
OOH
OOH
xxH
xxH

NOTES
'Typical with full·scale JOG = 26.67 mAo
External voltage or current -reference adjusted for 26.67 rnA full·scale output.

The SYNC and BLANK inputs, also latched on the rising edge
of CLOCK to maintain synchronization with the color data, add
appropriately weighted currents to the analog outputs, produc·
ing the specific output levels required for video applications, as
illustrated in Figures 8, 9 and 10. Tables IV, V and VI detail
how the SYNC and BLANK inputs modify the output levels.

The SETUP input, on the ADV7141 and ADV7148, is used to
specify whether a 0 IRE (SETUP = GND) or 7.5 IRE (SETUP
= VAA) blanking pedestal is to be used.

MA
26.87

V
1.000

WHITE LEVEL

8.OS

0.302

BLACK LEVEU
BLANK LEVEL

0.00

0.000

SYNC LEVEL

NOTES
1. CONNECTED WITH A 75 Il DOUBLY TERIlINATED LOAD.
2. EXTERNAL VOLTAGE OR CURRENT REFERENCE ADJUSTED FOR 26.67 mA FULL SCALE OUTPUT.
3. AS· 343A LEVELS AND TOLERANCES ASSUIIED ON ALL LEVELS.

Figure 9. ADV7141IADV7148 RGB Video Output Waveform (SETUP = GND)

6-58 VIDEO DIA CONVERTERS

REV. 0

ADV7141/ADV7146/ADV7148
Table V. ADV7141/ADV7148 KGB Video Output Truth Table (SETUP
Description

lOUT

WHITE
DATA
DATA-SYNC
BLACK
BLACK-SYNC
BLANK
SYNC

26.67
Data + 8.05
Data
8.05
0
8.05
0

(mA)'

= GND)

SYNC

BLANK

DAC Input Data

1
I
0
1
0
I
0

1
1
1
1
I
0
0

FFH
Data
Data
OOH
OOH
xxH
xxH

NOTE
'Typical wirh full-scale lOG = 26.67 rnA.
External voltage or current reference adjusted for 26.67 rnA full-scale output.
MA
19.05

V
0.714

0.00

0.000

WHITE LEVEL

BLACK LEVEll
BLANK LEVEL

•

NOTES
1. CONNECTED WITH A 75" DOUBLY TERMINATED LOAD.
2. EXTERNAL CURRENT REFERENCE ADJUSTED FOR 19.05 mA FULL SCALE OUTPUT.
3. RS - 343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.

Figure 10. ADV7146 RGB Video Output Waveform

Table VI. ADV7146 KGB Video Output Truth Table
Description

lOUT

WHITE Level
VIDEO
BLACK Level
BLANK Level

19.05
Video
0
0

(mA)'

BLANK
1
1
I
0

DAC Input Data
FFH
Data
OOH
xxH

NOTE
'Typical wirh full-scale lOR, lOG, lOB = 19.05 rnA,

REV. 0

IREF

= 8.88 rnA.

VIDEO DIA CONVERTERS 6-59

ADV7141/ADV7146/ADV7148
PC BOARD LAYOUT CONSIDERATIONS
The ADV7141, ADV7146and ADV7148 CEGIDACs are optimally designed for lowest noise performance, both radiated and
conducted noise. To complement the excellent noise performance of these parts, it is imperative that great care be given to
the PC board layout. Figures 11, 12 and 13 show recommended
connection diagrams for the ADV71411ADV7148 in voltage reference and current reference modes and the ADV7146.

ANALOG POWER PLANE

ADV7148
Cl
O.l.F
GND~~--t---~~~~t-~----~ GROUND

OPA
75Q

COMP

~Go------'--+--'F~

lOB

V OEF C>~f----""--~

Cl
O.l.F
__,-~__~~,-~~",,____~GROUND

IREF

lOR c>----....--+--+----"F~ RGB
lOG c>--------....--+----"F~ VIDEO

lOB
OUTPUT
L____~~r-----------4I--==~
COMPONENT DESCRIPTION
Cl-CS
C8
Ll

VENDOR PART NUMBER

0.1 "F CERAMIC CAPACITOR
10"F TANTALUM CAPACITOR
FERRITE BEAD

FAIR·RITE 274300111 ORI
MURATA BL01/02/03
7S0 1% METAL RLM RESISTOR DALE CMF·sse
1470 1% METAL RLM RESISTOR DALE CMF·sse
1.235V VOLTAGE REFERENCE
ANALOG DEVICES ADS89JH

Rl. R2. R3

Rsn
ZI

Figure 11. ADV7148/ADV7141 Typical Connection Diagram
and Component List (Voltage Reference Configuration)

VAA~~~-------t---,
ADV7141/
ADV7148
10EF

0'.,..----1---.-:::

COMP
,~~

__, -__,-~~~,-~____~_ GROUND

o-----...

lOR
--+---+---F=@ RGB
lOG c>--------.....--+---F~ VIDEO
1 0 B I c > - - - - - -....-=~ OUTPUT
COMPONENT DESCRIPTION
Cl-C5
C8-C7
L1

Rl. R2. R3

7S0

~RC>---~-I--+----"F~

VAA~~----'---~~--'
ADV7141/
ADV7148

GND~

750

VENDOR PART NUMBER

0.1 "F CERAMIC CAPACITOR
10"F TANTALUM CAPACITOR
FERRITE BEAD

FAIR·RITE 274300111 ORI
MURATA BL01/02/03
7511 1% METAL FILM RESISTOR DALE CMF·55C

COMPONENT DESCRIPTION
Cl-C4
C5-C6
L1
Rl. R2. R3

RGB
VIDEO
OUTPUT

VENDOR PART NUMBER

O.I"F CERAMIC CAPACITOR
10"F TANTALUM CAPACITOR
FERmTE BEAD

FAIR·RITE 274300111 ORI
MURATA BLOl/02/03
750 1% METAL RLM RESISTOR DALE CMF·55C

Figure 13. ADV7146 Typical Connection Diagram and
Component List (Current Reference Configuration)
The layout should be optimized for lowest noise on the CEG/
DAC power and ground lines. This is achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of VAA and GND pins should by minimized so
as to minimize inductive ringing.
Ground Planes
The ground plane should encompass all the CEGIDAC ground
pins, current/voltage reference circuitry, power supply bypass
circuitry, the analog output traces, any output amplifiers and all
the digital signal traces leading up to the CEGIDAC.
Power Planes
The PC board layout should have two distinct power planes, one
for analog circuitry and one digital circuitry. The analog power
plane should encompass all the CEG/DAC power pins and all
associated analog circuitry. This power plane should be connected to the regular PCB power plane (Vcel at a single point
through a ferrite bead, as illustrated in Figures 11, 12 and 13.
This bead should be located within three inches of the part.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all the CEG/DACs power pins, voltage reference circuitry and any output amplifiers.
The PCB power and ground planes should not overlay portions
of the analog power plane. Keeping the PCB power and ground
planes from overlaying the analog power plane will contribute to
a reduction in plane-to-plane noise coupling.
Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors.

Figure 12. ADV7148IADV7141 Typical Connection Diagram
and Component List (Current Reference Configuration)

6-60 VIDEO DIA CONVERTERS

REV. 0

ADV7141/ADV7146/ADV7148
Optimum performance is achieved by the use of 0.1 fLF ceramic
capacitors. Each of the two groups of VAA (ADV71411AD7148)
should be individually decoupled to ground. This should be
done by placing the capacitors as close as possible to the device
with the capacitor leads as short as possible, thus minimizing
lead inductance.
It is important to note that while the CEG/DAC contains circuitry to reject power supply noise, this rejection decreases with
frequency. If a high frequency switching power supply is used,
the designer should pay close attention to reducing power supply noise. A dc power supply filter (Murata BNXOO2) will provide EMI suppression between the switching power supply and
the main PCB. Alternatively, consideration could be given to
using a three terminal voltage regulator.

Digital Signal Interconnect
The digital signal lines to the CEG/DAC should be isolated as
much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power
plane.

REGISTER LEVEL PROGRAMMING OF THE CEGIDAC
Compatibility
CEGIDACs are available in several plug-in compatible replacements for most popular palette DACs including the Analog
Devices ADV471, ADV476 and ADV478, the Inmos IMSGI71
and IMSGl76 and the Brooktree BT471 and BT478. All are
compatible with standard VGA controllers.
The CEGIDAC powers-up in compatibility mode with the CEG
circuitry bypassed. CEG mode is enabled with a software key'
sequence of reserved palette accesses. See Appendix A for a software example of setting the CEG mode.
In compatibility mode the ADV7141 and ADV7146 always use
six bits for each red, green and blue palette component. The
ADV7l48 uses either 6 or 8 bits, depending on the setting of
the 8/6 pin (see Table VII below).
Table VII. CEGIDAC Bits per Color Component
Compatibility Mode

Due to the high clock rates used, long clock lines to the CEGI
DAC should be avoided so as to minimize noise pickup.
Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane (Vcc), and
not the analog power plane.
Analog Signal Interconnect
The CEGIDAC should be located as close as possible to the output connectors thus minimizing noise pick-up and reflections
'due to impedance mismatch.
The video output signals should overlay the ground plane, and
not the analog power plane, thereby maximizing the high frequency power supply rejection.
For optimum performance, the analog outputs should each have
a source termination resistance to ground of 75 n (doubly
terminated 75 n configuration). This termination resistance
should be as close as possible to the CEGIDAC so as to minimize reflections.
Additional information on PCB design is available in an Application Note entitled "Design and Layout of a Video Graphics System for Reduced EMI." This application note is available from
Analog Devices, Publication No. E1309-l5-10/89.

CEGIDAC

6·Bit Colors

ADV7141
ADV7146
ADV7148

*
*
*

CEGMode

8·Bit Colors

8·Bit Colors

*

*
*
*

In 6-bit compatibility mode the CEG/DAC shifts color data as it
writes to and reads from the palette. The microprocessor writes
right justified data in bits D5 to DO into the palette. In the palette the data is stored left justified with bits D I and DO set to O.
During palette read operations the data is returned to the microprocessor in bits D5 to DO with bits D7 and D6 set to O.
The CEG mode byte, which is written to the blue palette location 223, is also shifted when it is written, but not when read.
All eight bits of the palette data register are significant when
CEG is enabled. Set the CEG mode before writing CEG 8-bit
palette information to avoid the shifting operations that occur
when the chip is in compatibility mode.
The Encoding Methods
The Continuous Edge Graphics Level 3 specification describes
in detail the two advanced encoding methods. Table VIII lists
the characteristics of each CEG encoding method.
Basic-8 encoding provides 16 colors with g mixes, plus explicit
loading of the A or B color registers. The Basic·g method is appropriate for applications where 8-bits per pixel are available
and a moderate number of colors are required, such as CAD
applications.

Table VIII. CEG Encoding Methods
Encoding
Method

Bits per
Pixel

Mixes
8

16 x 16 x 8 = 2048

8

g x 8 x 7/2 = 224

Yes

Mixes and Colors in Different Pixels

223 x 222 x 32/2 = 792,096

Yes

Mixes and Colors in Different Pixels

Basic-8

8

16 + 16

Advanced-4

4

8

Advanced-8

8

223

REV. 0

CEG
Colors

Palette
Colors

32

DPL

Notes
Mixes and Colors in the Same Pixel

VIDEO DIA CONVERTERS 6-61

•

ADV7141/ADV7146/ADV7148
The two Advanced methods store colors and op codes in different pixels. The Advanced-4 encoding supports 4-bits,per-pixel
. graphics, making it the CEG method to use in 4-bit systems
such as the standard IBM VGA. Advanced-4 provides eight palette colors and eight mixes. Advanced-8 provides 223 drawing
colors with full 32-mix shading. Use the Advanced-8 encoding
method when there is a requirement for many colors, such as
solid model rendering and computer imaging.
In the Advanced methods, an entry in the palette can also be
reserved for the DPL op code. The dynamic palette further expands the number of colors available.
Basic-8 Encoding
The Basic-8 method encodes the 16 drawing colors and eight
mixes into the eight bit pixel as shown in Figure 14. Table IX
below shows the mix ratios that correspond to each pixel value
in the mix field.
P7

1P6

P4

Ips

<_.- MIX 0-7 -_.>

P3

1P2

Ip1

Table IX. Basic-8 Mix Values

0

I
2
3
4
5
6
7

Ratio
ColorA ColorB
31131
27/31
·22/31
18/31
13/31
9131
4131
0/31

0/31
4131
9131
13131
18/31
22/31
27/31
31131

The register bit selects whether the color is placed in the A register or the B register. When the register bit is set to 0, the A
register is used. When the register bit is set to 1, the B register
is used. The register bit also selects which portion of the palette
is accessed by the color field, because the A and B registers use
different palette ranges.
The color field of the pixel data refers to the first 16 colors in
the palette (Colors 0-15) when the register bit equals 0 (for the
A register). When the register bit equals I (for the B register),
the color field refers to the second 16 colors in the palette (colors 16 to 31). To find the palette location for the B register, add
16 to the color bits in PO-P3 (e.g., when the register bit = I,
color 0 refers to palette location 16). Generally, these two palette
banks are loaded with the same sets of colors, but different colors can be used to increase the possible number of colors.

~2

VIDEO DIA CONVERTERS

As shown in the Figure 15, when using the Advanced-4 encoding, inputs P3-PO contain data and inputs P7-P4 are ignored.

Figure 15. Pixel Encoding for Advanced-4

IPO

< ••_-_.>
< •••- COLOR 0-15 -_•• >
REGISTER

Figure 14. Pixel Encoding for Basic-B

Mix
Value

Advanced Encoding
In the two Advanced encoding methods, the pixel contains
either a color Or an op code. Mix op codes operate on the
colors in the A and B registers. The companion publication,
Continuous Edge Graphics Level 3, describes how the two colors are stored in the registers and how they are displayed. The
Advanced-4 encoding method combines eight palette colors with
eight mixes in the 4-bit pixel, providing 224 CEG colors. The 4
LSBs of the pixel value refer to either palette locations 0-7 or a
mix op code as shown in Table X below.

Table X. Advanced-4 Mix Values
Mix
Value

Ratio
ColorA Color B

0
I
2
3
4
5
6
7

-

-

31/31
27/31
22/31
18/31
13/31
9/31
4131
0131

0/31
4131
9131
13131
18/31
22/31
27/31
31131

8
9

10
11
12
13
14
15

-

Description
Palette Color 0
Palette Color I
Palette Color 2
Palette Color 3
Palette Color 4
Palette Color 5
Palette Color 6
Palette Color 7
or DPL Op Code
Mix Op Code
MixOp Code
Mix Op Code
Mix Op Code
Mix Op Code
Mix Op Code
Mix Op Code
Mix Op Code

Advanced-8 encoding uses 8-bit pixels and offers 223 palerte
colors with 32 mixes, resulting in 792,096 CEG colors. The
eight bits of the pixel value refer to either a color in the palette
or to an op code as shown in Table XI.
Table XI. Advanced-8 Mix Values

Mix
Value

Ratio
ColorA Color B

-

0-190
191

-

-

-

192
193
194
195

31/31
30/31
29/31
28/31

0131
1131
2131
3131

221
222
223
224-255

2/31
1/31
0131

29/31
30/31
31131

-

-

Description
Palette Colors
Palette Color
or DPL Op Code
MixOp Code
Mix Op Code
Mix Op Code
MixOp Code

Mix Op Code
Mix OpCode
Mix Op Code
Palette Colors

REV. 0

ADV7141/ADV7146/ADV7148
DYNAMIC PALETTE LOADING (DPL)
The two Advanced CEG encoding methods can use dynamic
palette loading, allowing the CEG/DAC to load palette colors
from the bit map. With DPL enabled, an entry from the color
palette is reserved as the DPL op code (7 in Advanced-4, 191 in
Advanced-8). The data following this op code describes the new
color to load and specifies the palette address. Note that CEGI
DAC addresses are ANDed with the pixel mask register. To
avoid misaddressing a DPL entry, load the mask with 255. See
Mask Register for more information.

Figure 16 shows an example of a DPL op code sequence in the
Advanced-4 encoding method and how the op code alters the
palette and affects the display. In this example the color at palette address 2 is reassigned with the DPL. As the new color is
loaded into the palette the CEG chip displays the pixel color to
the left of the op code, Color 3, on the screen. Mter CEG loads
the new color (shown as R2G2B2) at palette address 2, it is displayed whenever Color 2 is used.
Pixel Replication Compensation
Some VGA controllers repeat each pixel rwice in low resolution
displays (such as 320 x 200). The CEG chip, however, expects
pixels in sequences and therefore it provides pixel replication
compensation to undo this duplication. When pixel replication
compensation is enabled, the CEG/DAC chip samples P7-PO on
every second CLOCK to ignore the repeated data (see Figure
17). Because the CEGIDAC is reversing a duplication made by
the controller hardware, the compensation does not affect the
graphics programmer. The bit map is written as before.

The DPL op code and data are not displayed on the screen. Instead, the color value preceding the DPL op code is repeated in
place of the palette load sequence pixels. The rwo pixels preceding the DPL op code must be of the same kind (rwo colors or
two mixes). For example, Color I Color 2 DPL is a valid sequence but Color Mix DPL is not.
DPL Examples
In the Advanced-8 encoding method, a DPL sequence requires
five pixels, one for the op code, three for the new color and one
for the palette address. Table XII below shows the sequence.

If the scan line period (video time plus BLANK time) has an
even number of clock cycles, then even numbered pixels are
displayed. That is, after the end of BLANK, the first pixel is
ignored, the second displayed, the third ignored, the founh displayed etc. If the scan line period has an odd number of clock
periods, then the first pixel after the end of BLANK is displayed, and the second is also displayed, and thereafter only
even numbered pixels are displayed (the fourth, the sixth, etc.).

Table XII. DPL Op Code Sequence for Advanced-8
Pixel No.

1

2

3

4

5

Contents

DPL
Op Code

New
Red

New
Green

New
Blue

Palette
Address

In 4-bits-per-pixel graphics two pixels are needed to specify one
8-bit color value. Therefore, in the Advanced-4 encoding, a
DPL requires eight pixels; one for the op code, six for the new
color (two each red, green and blue), and one for the palette
address. Table XII shows the DPL op code sequence.
EDP
Opcode

,

BITMAP

12 I 3 I

New

fRed

V

New

New

Palene

Green Y-Blue""\ AJdr•••

7

0

0
1

1

2 R,R, G,G, B,B,
3

2

•

..,./

AaRz G,G

8 28 2

3

•

LN V

N/

..,./

PALETTE BEFORE
EDP

PALETTE AFTER
EDP

Figure 16. DPL Op Code in the Bit Map

Table XIII. DPL Op Code Sequence for Advanced-4
Pixel No.

1

2

3

4

7

8

DPL
Op code

New
Red

New
Red

New
Green

5
New
Green

6

Contents

New
Blue

New
Blue

Palette
Address

R7-R4

R3-RO

G7-G4

G3-GO

B7-B4

B3-BO

Color bits

REV. 0

VIDEO DIA CONVERTERS 6--63

•

ADV7141/ADV7146/ADV7148
BITMAP

CEGJDAC

Ip1]P2lp3Ip4Ip4 P3 P2 PI
I

I

II

VGA

P4 P4 P3 P3 P2 P2 PI PI

I CONTROLLER I

I

Figure

17.

I

II

P4P3P2Pl

REPUCATION
PIXEL
I COMPENSAnON

Pixel Replication Compensation

CEGIDAC MODES
The CEG/DAC supports a number of modes. A mode is a combination of attributes. The possible attributes are:
• CEG Encoding (Basic-8 or Advanced-4 or Advanced-8)
• Dynamic Palette Loading (DPL)
• Pixel Replication Compensation
The mode is selected under software control by a key sequence
followed by a mode byte.
EnablingCEG
The CEG/DAC employs an unused sequence of palette accesses
to enable the CEG logic. This long sequence was specially designed to prevent accidental mode changes. To enable the CEGI
DAC the software must perform the following steps:

1. Write a palette read address (222).
2. Write three specific bytes of palette RAM data.
3. Repeat Steps I and 2 twice more.
There are eight bytes of special palette RAM data followed by
the CEG mode byte. The mode byte determines the CEG functionality. Table XIV shows the special palette RAM data and
the mode byte. The CEG/DAC Modes table shows the mode
byte values. Appendix A contains sample software routines to
set the VGA CEG/DAC mode.
Table XIV. CEG Key Sequence (Decimal Values)
Byte 1

Byte 9

67

Mode

The key sequence must be written exactly as shown and cannot
be interrupted by any other palette accesses. The entire key
sequence must be reentered to change CEG modes. If the key
sequence is wrong or the CEGDIS pin is high, the chip retnains
in compatibility mode. After the mode is set it can be read from
palette location 223 blue. Note that, as with other palette data,
the mode byte is shifted as it is written to the palette (see Compatibility section).

Writing palene data to location 223 immediately disables CEG
operations. and returns the device to full power-up compatibility
mode (there are no side effects to this and no need to clear any
registers). Appendix A contains sample software that clears the
CEG/DAC mode and returns the hardware to its initial powerup compatibility mode (in a VGA system).
Gamma Conection
The CEG/DAC autotnatically applies full gamma correction in
all CEG modes. Gamtna correction is required to compensate for
the nonlinear relationship between the CEG/DAC outputs and
the CRT display. To avoid any incompatibility, gamtna correction is disabled in compatibility mode. The CEGIDAC uses a
gamtna value of 2.3 to perform this correction.
Identifying a CEGIDAC
Software determines whether a CEGIDAC is present by reading
the mask register. Whenever a CEG mode set is selected, the
four most significant bits of the mask register become write
only. When read, these four MSBs do not relay the contents of
the mask, but rather, give infortnation about the CEG hardware
installed.
Mask register Bit D7 is reserved and Bits D6-D4 read back the
revision code of the CEGIDAC chip. The revision number always contains at least one "0" to allow software to distinguish
CEG/DAC chips from other DACs. An ordinary palette DAC
returns the full eight bits of the tnask register.
In other words, by enabling CEG, loading the mask register
with 255 and then reading the mask register, the software can
determine whether or not the hardware uses a CEG/DAC. Devices that return the value loaded (those -which read back 255)
do not have CEG. Those that return a different value use a
CEGIDAC. Appendix A contains sample software which determines the version by inspecting the mask register.

Table XV shows the CEG/DAC modes. Unpredictable results
can occur if a mode not listed in the table is used.
Table XV. CEGIDAC Modes
Mode

5
6

9
10

II
13
14

IS

CEG Encoding
Method
Basic-S
Basic-S
Advanced-4
Advanced-4
Advanced-4
Advanced-S
Advanced-S
Advanced-S

6-64 VIDEO DIA CONVERTERS

DPL

Pixel
Replication

*
*
*

*
*

REV. 0

ADV7141/ADV7146/ADV7148
APPENDIX A. CEG SAMPLE CODE
The following code samples are available on diskette
Setting the CEGIDAC Mode
SET_CEG...MODE:

; Set the CEG/DAC mode by entering a key sequence.
; 8086/286/386/486 assembler for a CEG/DAC in a VGA
; Desired MODE is passed in AL

PUSH
PUSH AX

DX

equ

0000 I OOOb

MOV

DX,

03DAH

; Set to Video status port

IN
TEST
JNZ

AL,
AL,
SYNCO

DX
RVRT

; Get from Status Port
; Are we in vertical retrace ?
; Yes, wait until we aren't

IN
TEST
JZ
ENTER_KEY:
MOV
MOV
OUT

AL,
AL,
SYNC!

DX
RVRT

; Get from status port
; Are we in vertical retrace ?
; No, loop until we are

DX,
AL,
DX,

03C7H
222
AL

; Set up DAC for read from 222

MOV

DX,

03C9H

; Put write data address in DX

MOV
OUT

AL,
DX,

67
AL

; Write key byte 1

MOV
OUT

AL,
DX,

69
AL

; Write key byte 2

MOV
OUT

AL,
DX,

7!
AL

; Write key byte 3

MOV
MOV
OUT

DX,
AL,
DX,

03C7H
222
AL

; Set up DAC for read from 222

MOV
MOV
OUT

DX,
AL,
DX,

03C9H
69
AL

; Put write data address in DX
; Write key byte 4

MOV
OUT

AL,
DX,

68
AL

; Write key byte 5

MOV
OUT

AL,
DX,

83
AL

; Write key byte 6

MOV
MOV
OUT

DX,
AL,
DX,

03C7H
222
AL

; Set up DAC for read from 222

MOV

DX,

03C9H

; Put write address in DX

RVRT
SYNCO:

SYNC!:

REV. 0

; Save DX
; Save MODE for later
; Vertical retrace bit

MOV
OUT

AL,
DX,

85
AL

; Write key byte 7

MOV
OUT

AL,
DX,

78
AL

; Write key byte 8

POP
OUT
POP
RET

AX
DX,
DX

AL

;
;
;
;

•

Retrieve desired MODE
Write the MODE
Restore DX
return from subroutine

VIDEO DIA CONVERTERS 6-65

ADV7141/ADV7146/ADV7148
Clearing the CEGIDAC Mode
; Clear CEG mode and return to
; power-up compatibility mode
; 8086/286/386/486 assembler code to clear the CEGIDAC mode and
; return the hardware to its initial power-up Compatibility mode
; (in a VGA system)

To clear CEG mode:
I) Wait for the Beginning of a vertical retrace
2) Write to palette location 223d

R\,RT

PUSH
PUSH

DX
AX

; Save DX
; Save MODE for later

equ

OOOOIOOOb

; Vertical retrace bit

; Trigger during vertical retrace so DPLs won't interrupt reset
MOV

DX,

03DAH

; Set to Video status port

SYNCO:

IN
TEST
JNZ

AL,
AL,
SYNCO

DX
RVRT

; Get from Status Port
; Are we in vertical retrace ?
; Yes, wait until we aren't

SYNCI:

IN
TEST
JZ

AL,
AL,
SYNC I

DX
RVRT

;
;
;
;

MOV
MOV
OUT

DX,
AL,
DX,

03C8H
223
AL

MOV
MOV
OUT

DX,
AL,
DX,

03C9H
0
AL

POP
POP
RET

AX
DX

Get from status port
Are we in vertical retrace ?
No, loop until we are
Safe to write

; Set write address

; Clear CEG mode
; Write the byte
; Restore AX
; Restore DX

Determining the CEGIDAC Version (Reading the Mask Register)
GET_VERSION:

; Identify CEG version number

; 8086\286\386\486 assembler code for the VGA sequence to
; determine the version by inspecting the mask register
MOV
CALL

AL,
OI3DH
SELCEG.-MODE

; Any legal mode will do
; Set the mode

MOV
MOV
OUT
IN
SHR
SHR
SHR
SHR
AND

DX,
AL,
DX,
AL,
AL,
AL,
AL,
AL,

; Set DX to mask reg. address
; Write mask bits to all ones

AX,

03C6H
255
AL
DX
I
I
I
I
7

; Read contents of mask reg
; Shift result to lowest bits

; Mask to keep only three bits

; The revision code is now in the low nibble of AL
; Valid revision codes are 0-6
; Revision code 7 indicates Non CEG compatible device
; This specification refers to chip revision 00

{f-66 VIDEO DIA CONVERTERS

REV. 0

ADV7141/ADV7146/ADV7148
Writing the Palette

; 8086128613861486 assembler code for the VGA sequence to
; write to the palette
WRITE...PAL:

; Write to Palette locations
; Set up CEGIDAC for Write
; Will write location zero

MOV
MOV
OUT

OX,
AL,
OX,

03C8h
0
AL

MOV
OUT
OUT
OUT

OX,
OX,
OX,
OX,

03C9h
AL
AL
AL

;
;
;
;

AL
AL
AL

; Write Red Byte
; Write Green Byte
; Write Blue Byte

; Palette Address will Auto-increment - keep writing
OUT
OX,
OUT
OX,
OUT
OX,

Put data address into OX
Write Red Byte
Write Green Byte
Write Blue Byte

Location 0
Location 0
Location 0
Location I
Location I
Location I

Reading the Palette

; 8086128613861486 assembler code for the VGA sequence to
; read from the palette
READJ>AL:
MOV
MOV
OUT

OX,
AL,
OX,

03C7h
50
AL

MOV
IN
IN

OX,
AL,
AH,
BL,

03C9h
DX
OX
OX

IN

; Palette Address will Auto-increment - keep reading
IN
AL,
DX
IN
AH, OX
IN
BL,
DX

; Read From Palette locations
; Set up CEG/DAC for read
; Will read from location 50
;
;
;
;

Put Data address into DX
Read Red Byte into AL
Read Green Byte into AH
Read Blue Byte into BL
Location 51
Location 51
Location 51

; Read Red Byte
; Read Green Byte
; Read Blue Byte

Accessing the Pixel Mask Register

; 8086128613861486 assembler code for the VGA sequence to access the
; Pixel Mask Register
ACCESS....REG

REV. 0

MOV
MOV
OUT

OX,
AL,
OX,

3C6h
255
AL

; Pixel Mask Register Port Address
; Write all ones to register

IN

DX,

AL

; Read back contents of register

VIDEO DIA CONVERTERS 6-67

--

6-68 VIDEO DIA CONVERTERS

'

Special Function Audio Products
Contents
Page

Special Function Audio Products - Section 7 ................................... 7-1
Selection Guides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
AD600/602 - Dual, Low Noise, Wideband Variable Gain Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-S
AD71I1- LOGDAC CMOS Logarithmic D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
AD71l8 - LOGDAC CMOS Logarithmic D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-IS
MAT-04 - Matched Monolithic Quad Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
PKD-OI - Monolithic Peak Detector with Reset-and-Hold Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
SSM-2013 - Voltage-Controlled Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-S1
SSM-2014 - Voltage-Controlled Amplifier/OVCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-S7
SSM-20IS - Low Noise, Microphone Preamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-S9
SSM-2016 - Ultraiow Noise, Differential Audio Preamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6S
SSM-2017 - Self-Contained Audio Preamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-73
SSM-2018 - Voltage-Controlled Amplifier/OVCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-81
SSM-2024 - Quad Current-Controlled Amplifier .... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-93
SSM-21l0 - True RMS-to-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-99
SSM-2120/2122 - Dynamic Range Processors/Dual VCAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-111
SSM-212S/2126 - Dolby Pro-Logic Surround Matrix Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-123
SSM-2141 SSM-2142 SSM-2143 SSM-2210 -

High Common-Mode Rejection Differential Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Balanced Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-6 dB Differential Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Dual Matched NPN Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-133
7-139
7-145
7-147

SSM-2220 - Audio Dual Matched PNP Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-IS9
SSM-2402I2412 - Dual Audio Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-167
SSM-2404 - Quad Audio Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-177

SPECIAL FUNCTION AUDIO PRODUCTS 7-1

'j'J

""

til

ril(")
~

Selection Guide
Special Function Audio Products

.....

~

~

Audio Preamplifiers (All Values Typical)
Model

Input Voltage Noise
nVJVHZ, G = 1000

THD+N
%, G = 1000,
f=lkHz

Slew
Rate
V/".s

Gain
Bandwidth
MHz, G = 1000

CMRR
dB, G = 1000
f= 60Hz

Page

Comments

§

SSM-2015

I.3

0.007

8

0.7

100

7-59

~

SSM-2016
SSM-2017

0.8
0.95

0.009
0.012

10
17

0.55

100
112

7-65
7-73
7-73

Programmable Input Stage for Noise
vs. Source Impedance Optimization
±9 V to ±36 V Operation
Only One External Component Required

::::!

~
h

8

1

~

(jj

Volume Control
Voltage Controlled Amplifiers (All Values Typical)
#
Model

Channels

Audio
Dynamic Range
dB

THD+N

%,@ 1 kHz
G= 1

GainlAtten
Range
dB

Gain
Bandwidth

MHz

0.8
0.004
1lS
106
Discontinued - Specify Pin-Compatible Upgrade SSM-2018
1171
10
0.0062
140

SSM-20B
SSM-2014
SSM-2018

Comments

7-51

Includes Mute Function

NAB

7-81
7-81
7-93
7-111
7-111
7-5
7-5
7-5
7-5

Programmable Gain Core Class

0.25

A
A

98

40

3980

A

2

108

40

1258

A

Channels

Step
Resolution
dB

Attenuation
Range
dB

Page

Comments

0.375
1.5

89.6
88.5

7-9
7-15

8-Bit Control Input
6-Bit Control Input

4
2

82
100

AD600

2

AD602

0.05
0.005

LogDACs
#
AD7111
AD7118

Page

A

140

SSM-2120/2

SSM-2024

Model

Gain
Core
Class

Lowest Cost Per VCA
SSM-2120 Contains Two Level
Detection Side Chains On-Chip
32 dBN Scale Factor
32 dBN Scale Factor

Dolby* Pro-Logic Decoders** (All Values Typical Unless Otherwise Noted)
Model

Audio
Dynamic
Range
dB

THD+N
%,@ 1 kHz,
o dBd = Soo mV nos

Min Channel
Separation
dB
CIN to L, RouT

Min Channel
Separation
dB
All Other Channels

Page

Comments

SSM-2125
SSM-2126

103
103

0.02
0.02

35
25

25
25

7-123
7-123

Autobalance, Noise Sequencer On"Chip
Autobalance, Noise Sequencer On-Chip

Audio Line Driver and Receivers (All Values Typical)
Balanced Line Driver

Model

Audio
Dynamic
Range
dB

THD+N
%,@ 1 kHz
VIN = IOV nos

Output
CMRR
dB, f = 1 kHz

V/!'-s

Page

Comments

SSM-2142

ll6

0.006

-45

15

7-139

No External Components Required, Drives Difficult Loads

Slew
Rate

Differential Line Receivers

~

~r-

~

Model

Audio
Dynamic
Range
dB

THD+N
%,@ 1 kHz,
IOV nos

SSM-2141
SSM-2143

126
128

0.001
0.0008

InputCMRR
dB,f=60Hz
100
90

Slew
Rate
VI!,-s
9.5
10

Gain

Page

Comments

112 or 2

7-133
7-145

No External Components Required
No External Components Required

'Class AB.
2Trimmed, Class AB.
*Dolby is a registered trademark of Dolby Laboratories Licensing Corporation, San Francisco, CA.
**Available only to licensees of Dolby Laboratories

:::!

~

l>

~

g~
~

(jj

'i"

t.)

II

r Selection Guide

~ Special Function Audio Products
,...
~

~

Audio Switches (All Values Typical)

:::!

~

OFF
Model

Switches

Noise
Voltage
nVv'iii

SSM-2402
SSM-2404
SSM-2412

2
4
2

1
0.8
1

~

5

(5

;g

~

til

#

THD+N
%
@lkHz

Isolation
dB
20 Hz to 20 kHz

Charge
Injection
pC

Page

Comments

0.003
0.0009
0.003

120
100
120

50
35
150

7-167
7-181
7-167

Handles +24 dBu Signals (20 V supplies)
Lowest Cost-Per-Switch
Faster Version of SSM-2402 (toN = 4 InS)

Matched Transistors
Model

Type

Voltage Noise Max
nVtvHi, f
1 kHz

SSM-2210
SSM-2220
MAT-04

DualNPN
DuaJPNP
QuadNPN

1
1
2.5

=

HfeMin

AhfeMax
%,Ic lmA

300
80
400

5
6
2

Other Special Function Audio Products
Model

Page

Coriunents

PKD-Ol
SSM-2UO

7-33
7-99

Monolithic Peak Detector
RMS-to-OC Converter

=

Unity Gain
Bandwidth

MHz, Ie = 10 mA (typ)

Voltage
Offset Max
JAoV

Page

Comments

200
180
300

200
200
200

7-147
7-159
7-21

Low Cost
Low Cost
Low Cost

1IIIIIIII ANALOG

WDEVICES
FEATURES
Two Channels with Independent Gain Control
"Linear in dB" Gain
Two Gain Ranges:
AD600: 0 dB to +40 dB
AD602: -10 dB to +30 dB
Accurate Absolute Gain: :1:0.5 dB
Low Input Noise: 1.4 nVlVHZ
Low Distortion: -60 dBc THD at:l:1 V Output
High Bandwidth: DC to 35 MHz (-3 dB)
Stable Group Delay: :1:2 ns
Low Power: 125 mW (Max) per Amplifier
Signal Gating Function for Each Amplifier
Drives AID Converter Directly
APPUCATIONS
Ultrasound and Sonar Time-Gain C
rol
High Performance Audio and RF AGC Syste
Signal Measurement
Range Extension for AID Converters
PRODUCT DESCRIPTION
The AD600 and AD602 are dual channel, low noise variable
gain amplifiers, based on Analog Devices' proprietary X-AMP"
technique. They are optimized for use in ultrasound imaging
systems, but are applicable to any application requiring very
precise gain, low noise and distortion, and wide bandwidth.
Each channel provides a gain of 0 to +40 dB in the AD600
and -10 dB to +30 dB in the AD602. The lower gain of the
AD602 results in an improved signal-to-noise ratio at the output. However, both products have the same 1.4 nV/YHz input
noise spectral density. The decibel gain is directly proportional
to a control voltage, and is accurately calibrated and temperature
stable.
To achieve the difficult performance objectives, a new circuit
fonn-the X-AMP-has been developed. Each channel of the
X-AMP comprises a variable attenuator of 0 dB to -42.14 dB
followed by a high-speed fixed-gain amplifier. In this way, the
amplifier never has to cope with large inputs, and can benefit
from the use of negative feedback to precisely defme the gain
and dynamics. The attenuator is realized as a seven-stage R-2R
ladder network having an input resistance of 100 n, lasertrimmed to :t2%. The attenuation between tap points is
6.02 dB; the gain-control circuit provides continuous interpolation between these taps. The resulting gain is very exact,
although there is a small ripple (about :1:0.2 dB) in the gain
error.
The gain-control interfaces are fully differential, providing an
input resistance of -15 Mn and a scale factor of 32 dBN (that
is, 31.25 mV/dB) defmed by an internal voltage reference. The
response time of this interface is less than 1 ,...s. Each channel
*Patent pending.
X-AMP is a trademark of Analog Devices, Inc.

Dual, Low Noise, Wideband
Variable Gain Amplifiers
AD600/AD602* I
FUNCTIONAL BLOCK DIAGRAM

cnll
Ale..

A10P

VPOS

VNEG

A20P

also has an independent gating facility which optionally blocks
signal transmission and sets the dc output level to within a few
millivolts of the outpUt ground. The gating control input is
TTL and CMOS compatible.
The gain of the AD600 is 41.07 dB and that of the AD602 is
31.07 dB; the -3 dB bandwidth of both the AD600 and AD602
is nominally 35 MHz, essentially independent of the gain. The
instantaneous signal-ta-noise ratio (ISNR) for a 1 V nns output
and a 1 MHz noise bandwidth is typically 76 dB for the AD600
and 86 dB for the AD602. The amplitude response is within
:1:0.5 dB from 100 kHz to 10 MHz; over this frequency range
the group delay varies by less than :t2 ns at all gain settings.
Each amplifier section can drive a variety of load impedances
with low distortion. The peak specified output is :t2.5 V minimum into a 500 n load, or :tl V into a 100 n load. For a
200 n load in shunt with 5 pF, the total harmonic distortion for
a :t 1 V sinusoidal output at 10 MHz is typically -60 dBc.
With appropriate precautions, amplifier sections may be cascaded to provide a gain-control range of 80 dB. A variety of
control options can then be employed. For example, the gaincontrol inputs can be driven in simple parallel to provide a scaling of 64 dBN, when the ISNR decreases essentially linearly as
the gain is increased. A gain offset of just 3 dB between the two
sections results in the lowest ripple in the gain error. Alternatively, the gain-control inputs may be offset by 40 dB to achieve
the highest possible ISNR at any gain within the full gain range.
The AD600 and AD602 are available in either a 16-pin plastic
DIP or 16-pin SOIC, and are guaranteed for operation over the
commercial temperature range of O·C to + 700C.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

REV. 0

SPECIAL FUNCTION AUDIO PRODUCTS 7-5

•

AD600/AD602
-SPECIFICATIONS (Each VGA, at TA = +25°C, Vs = ±5V, -625 ",V,:5¥s:5
+625"mV,
O,andC =5 p'F', unless iJtherMse noted. Specifications for AD600 and AD602 are identical. unless
R~,*50It

AMPLIFIER INPUTGIcIARACTERISTICS
Input ReSistance
Input Capacitance .
Input Noise Spectral DellJ!ityl
Peak Input Voltage
Common-Mode Rejection Ratio
AMPLIFIER OUTPUT CHARACTERISTICS
- 3 dB Bandwidth
Slew Rate
Peak Output2
Output Impedance
Output Short-Circuit Current
Group Delay Change vs. Gain
Group Delay Change vs. Frequency
Distortion

Conditions

Min

Pin 2 to 3; Pin 6 to 7

98

. -625 mV :=; VG :=; +625 mV

OutpUt OffsetVoltage3
Output Offset Variation
GAIN CONTROL INTERFACE
Gain Sca1ing Factor
Input VojtageRIinge
Input BiaS Current
Input Offset Current
Differential Input Resistance
Response Time
SIGNAL GATING INTERFACE
Logic Input "LO" (Output ON)
Logic Input "HI" (Output OFF)
Response Time.
Input Resistance
Output Gated OFF
OutpUt Offset Voltage
Output Noise Spectral Density
Signal Feedthrough
POWER SUPPLY
Specified Operatiilg Range
Quiescent Current
Power Supply Rejection Ratio

AD6OOJ/AD6Olr
Typ
Max
100
2
1.4

102

±2
f=IMHz

TBD

VOUT= 100 mV rms

35
275
. ±3
2
TBD
±2
±2

RL ;;,: 5000
f:=;IOMHz

-0.5
19.8
39.5

VG =
VG =
VG =
VG =
-625

- 625 mV
OV
+ 625 mV
0
mV:5 VG :=; +625 mV

-10.5
9.8
29.5

31.7
-0.75

TBD

0
mA
ns
ns
dBc

+0.5
20.2
40.5
30
TBD

dB
dB
dB
mV
mV

-10

-9.5
10.2
30.5
10
TBD

dB
dB
dB
mV
mV

32.3
2.5
1
TBD

dBN
V

10
30
5

32

0.8
1
30

mV
nV/YHz
dB

THD

22
TBD

V
V
JLS

±10

;t4.75

JLA

riA
MO
dB/JLs

kO

II

±4.75 V :=; Vs :=; 5.25 V

0
pF
nV/yHz
V
dB

V

2.4
ON to OFF, OFF to ON
Pin 4 to 3; Pin 5 to 6

UBits

0
20
40
15

0.15
10
15
40

Pins 1 to 16; Pins 8 to 9
. Full 40 dB Gain Change

:

MHz
V/JLs

-60"

AMPLIFIER GAIN ACCURACY
AD600
Gain Accuracy

Output Offset Voltage3
Output Offset Variation
AD602
Gain Accuracy

, ,

oth&lWisli~oted.)

l

±5.25
25

V
rnA

dB

NOTES
IOpen or shortRcircuited input; noise· is lower whe~ system is set to maximum, gain and: input is'short-circuited.
'Using resistive loads of
or greater, or with the addition of a I
pull-down resistor when driving lower loads.
'Note that because the amplifier's gain is X113 (41 dB) in the AD600, an input offset of only 100 ,..V becomes an 11.3 mV offset atthe output; in the AD602,
the amplifier's gain i. 35.7 (31 dB), and an input offsaof 100 ,..V~mes a 3.57 mV offset at the output.
'.'
.
Specifications shown .in boldface are tested on all production unilS at· final electrical test. Results from those tests are used to calculate outgOing quality levels.
All min and max specifications are guaranteed, although ouly those shown in boldface are tested on all production units.
Specifications subject to change without notice.

soon

kn

This information applies to a product under development. Its characteristics and'specifications are subject to. change without notice.
Analog Devices assumes nO'obligation regarding future manufacture unless·othetwise agreed to in writing. '

7-6 SPECIAL FUNCTION AUDIO PRODUCTS

REV. 0

AD600/AD602
ABSOLUTE MAXIMUM RATINGS l
Supply Voltage ±Vs . . . . . . . . . . . . . . . • . . . . . . ±7.5 V
Input Voltages
Pins I, 8, 9, 16 . . . . . . . . . . . . . . . . . . . . . . . . ±XX V
Pins 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . . . .. ±XX V
Pins 4, 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±Vs

NOTE
lStresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated
in the operational section of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics:
l6-Pin J;>lastic Package: alA = 8S"CIWatt
16-Pin SOIC Package: alA = IOOOClWatt

Internal Power Dissipation . . . . . . . . . . . . . . . . . . 600 mW
Operating Temperature Range . . . . . . . . . . . . O°C to +70°C
Storage Temperature Range . . . . . . . . . . . -65°C to + 150°C
Lead Temperature, Soldering 60 sec . . . . . . . . . . . . + 300°C
CAUTION __________________________________________
ESD (electrostatic discharge) sensitive device. Permanent damage may occur
devices subject to high energy electrostatic fields. Unused devices must be
foam or shunts. The protective foam should be discharged to the des .
are removed.

-,~-----

ected

WARNING!

c:J

~~EDEVICE

CONNECTION DIAG
16-Pin Plastic DIP (N) Pa ge
16-Pin Plastic SOIC (R) paCkage~

Description

\\\

AIHI
Pin 3

AILO

Pin 4

GAT!

Pin 5

GAT2

Pin 6

A2LO

Pin 7

A2HI

Pin 8

C2LO

Pin 9

C2HI

Pin 10 A2CM

ORDERING GUIDE
Model
AD600JN
AD600JR
AD602JN
AD602JR

Gain
Range

Temperature
Range

Package
Option·

o dB to
o dB to

O°C
O°C
O°C
O°C

N-16
R-16
N-16
R-16

+40 dB
+40 dB
-10 dB to +30 dB
-10 dB to +30 dB

to
to
to
to

+70°C
+70°C
+70°C
+70°C

Pin
Pin
Pin
Pin
Pin

11
12
13
14
IS

A20P
VNEG
VPOS
AlOP
AICM

Pin 16 CIHI

CHI Gain-Control Input "LO" (Positive
Voltage Reduces CHI Gain).
CHI Signal Input "HI" (Positive Voltage
Increases CHI Output).
CHI Signal Input "LO" (Usually Taken to
CHI Input Ground).
CHI Gating Input (A Logic "HI" Shuts Off
CHI Signal Path).
CH2 Gating Input (A Logic "HI" Shuts Off
CH2 Signal Path).
CH2 Signal Input "LO" (Usually Taken to
CH2 Input Ground).
CH2 Signal Input "HI" (Positive Voltage
Increases CH2 Output).
CH2 Gain-Control Input "LO" (Positive
Voltage Reduces CH2 Gain).
CH2 Gain-Control Input "HI" (Positive
Voltage Increases CH2 Gain).
CH2 Common (Usually Taken to CH2
Output Ground).
CH2 Output.
Negative Supply for Both Amplifiers.
Positive Supply for Both Amplifiers.
CHI Output.
CHI Common (Usually Taken to CHI
Output Ground).
CHI Gain-Control Input "HI" (Positive
Voltage Increases CHI Gain).

*N = Plastic DIP; R = Small Outline IC (SOIC). For outline information
see Package Information section.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

REV. 0

SPECIAL FUNCTION AUDIO PRODUCTS 7-7

•

AD600lAD602

=~,--(8IAS_AEFE_,:e

GAT1

__
WOR_K)--,

C1H1~ _ _

>_---A1OP

C1LO~GAIN

CONTROL
Z.24KQ

INTERFACE

--.,...--_

....oIdS -12.04dB

CONTINUOUS INTERPOLATION -

-1'-- -a.G8dB

-

-30.1dB .....1_

_

-42.14

L-_ _ _ _ _ A1CII

MRLAliDERIETWORK
(llPUT ATTEWATOR)

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

7-8 SPECIAL FUNCTION AUDIO PRODUCTS

REV. 0

1IIIIIIII ANALOG

WDEVICES

LOGOAC
CMOS Logarithmic OfAConverter
A07111* I
FUNCTIONAL BLOCK DIAGRAM

FEATURES
Dyn_ic Range: 88.5dB
Resolution: 0.375dB
On-Chip Data Latches
Full ±25V Input Range Multiplying DAC
Low Distortion
Single +5V Supply
Latch-Up Free (No Protection Schottky Requiredl
APPLICATIONS
Dillitally Controlled AGC Systams
Audio Attenuaton
Wide Dynamic Range AJD ConverteR
Sonar Systams
Function Generator.

GENERAL DESCRIPTION
The LOGDAC™ AD7111 is a CMOS multiplying DfA converter which can attenuate an analog input signal over the
range 0 to -88.SdB in O.37SdB steps.
The degree of attenuation is determined by an 8-bit data word
which is latched into on-chip data latches using microprocessor compatible control signals CS and WR. Operating frequency range of the device is from de to several hundred kHz.
The device is available in a standard 16-pin DIP and in a
ZOoterminal surface mount package.

ORDE1UNG GUIDE
Specified

Accuracy
llqe

I'ac:bae

Model

Temperature
llqe

AD7IllKN
AD71l1BQ
AD7111TQ
AD7111LN
AD71l1CQ
AD71l1UQ
AD71l1TE1883B

O"C to + 7O"C
- 2S"C to + 85"C
- SS"C to + 12S"C
O"C to + 7O"C
- 25"C to + 85"C
- SS"C to + 12S"C
- SS"C to + 125"C

OdBt06OdB
OdBt06OdB
OdBt06OdB
OdBto72dB
OdBt072dB
OdB to 72dB
OdBt06OdB

N-16
Q-16
Q-16
N-16
Q-16
Q-16
E-20A

*E = Leadless Ceramic Chip Curler; N = Plastic DIP; Q
For outl.iDe information see 1'ackaac lDformation section.

0pIi0a*

= Cerdip.

-v.S. ' - No. 4511764

LOGDAC is • tndeatarIc of AaaIot om- lac.

REV. A

SPECIAL FUNCTION AUDIO PRODUCTS 7-9

•

.

",'

~ A

<,c,

,

':'""

"

I

Parameter

.-AD7111K/BIT GIIADES
TA = +2SDC
TA=TmD.T~.

NOMINAl- R.ESOLUTION

0.375

0.375

0.375

0.37;

dB

Oto 36

Oto 30
Ot048

o to 48

Oto 30

dB-min
dB min

o to 36

dB min
dB min

::

'"

.-

AD7111UCIV, GIIAD~S
TA. +2'oC TAo = Tmin I Tmax

",1'

"

'

ACCURACY RELATIVE TO OdS ATTENUATION
0,375dBSrep"
, .Accuracy "" ±O~17dB
Monotonic
,,'
:
O.7SdB Steps:
Accuracy '" ±O.35d8
Monotonic
'.
l.SdBSreps:
Accuracy <; to.7dB
Monotonic'
3.OdB Steps,
Accuracy'" ±l.4d8
Monotonic
6.OdB Steps,
ACCUracy '" :f;2~7dB
Monotonic

I'

Oto 36
'0"1 54

~toS4

Units

'

(::

"

Conditions/Commenu

Guaranteed attenuation ranges
for specified step sizes

Ot048

Ot042

o to 72

Ot066

o to 42
Oto 72

Ot060

Oto S4
Full ~ange

Ot048
Oto 78

Ot048
Oto 85.5

o to 72

Oto 66
Full Range

o to S4

Ot060

Full Range

Full Range

Ot072
Full Range"

Ot060
Full Range

Ot060
Full Range

GAIN ERROR

to.1

±O.IS

VIN INPUT RESISTANCE
(PIN 15)

9111/15

9111/15

RFB INPUT RESISTANCE
(PIN 16)

9.-3/11:5115.7 '9.3111.5/15.7

7.3/1U/18.8 7.3/11.5/18.8

kG min/typ/max

DIGITAL INPUTS
VIH (Jnput High Voltage)
VIL (Input Low Voltage)
Input Leakage Current

2.4
0.8
,,1

2.4
0.8
t10

2,4
0.8
±1

2.4
0.8
±10

V max
/lA max

0
0
350
175
10

0
0
500
250
10
4.5

0
0
350
175
10
3

0
.. 0
500
250
10,'
4.5

#Jsmin

Data Valid to Write Setup Time
Data Valid to Write Hold Time
Refresh Time

+5
1
500

'+5
4
1000

V
mAmax
/lAmax

Digital Inputs = VIH or Vn.
Digital Inputs .. OV or VDD. See Figure 7.

SWITCHING CHARACTERISTICS'
tes
teH
'WR

'oS

'DH

tRPSH

3

Ot042

dB min
dB min

Ot048
Full Range

dB min

Ot048

dB min

±0.15

Full Range
to.20

dB max

7111118

7111/18

kO min/typ/max

Full Ra,nge is from Q to 88;SdB

v min

nsman
nsmin
nsnUn
nsmin
nsm!n

Digitallnp.uts .. VDn
Chip SeICct to Write Setup Time
Chip Select to Write Hold Time

Write Pulse Width

POWER SUPPLY

Voo

+5

IDD

1

+5
4

500

lOOP

.

NOTE
I Sample tested Il1: +2SoC to ensure comp1ianci.
Specifications subject to chlDJe without:notice.

AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance only and arc not subject to tesl.
Von = +SV, VIN = -IOVdcexceptwheresblted,IoUT = AGND = DGND = OV,outpUtamplifierAD544exceptwherestated.

AD7111UC/U GIIADES
TA = 2'oC
TA· Tmin. TID.

AD7111K/BIT GRADES
TA = +2'oC
TA""Tmin.Tma;

Units

Conditions/Comments

Propagation Delay

0.001
3.0

0.005
4,5

0.001
3,0

0.005
4.5

dB per % max
",max

Digital-to-Analog Glitch Impulse

100

-

100

-

nV sees typ

[WDD = ±lO%, Input Code = 00000000
FuD Scale Chan~Measured from
\Vii. going high. • OV.
Measured with ADLHOO32CG as Output
Amplifier for Input Code Transition
10000000'000000000.
Cl of Figure 1 is OpF

185
7
-92
-91
70
7

185
7
-68
-91
70
7

pFmax
pFmax
dB max

Parameter
DC Supply Rejection, AGain/AVDD

Output Capacitance. Pin 1
Input Capacitance, Pin 15 and Pin 16
Feedthrough at 1kHz
Total HannonM: Distortion
Output Noise Voltage Density
Digital Input Capacitance

185
7
-94
-91
70
7

185
7

-72
-91
70
7

dB~

nVI Hzmax
pFmax

Fecdthrough is also detennined by circuit
layout (see Figure 4).
VIN = 6V nns at 1kHz
Includes AD544 Amplifier Noise

SpcclficaCiOns subJCCt to ch. . wilhout notiCe.

7-'10 SPECIAL FUNCTION AUDIO PRODUCTS

REV. A

AD7111
ABSOLUTE MAXIMUM RATINGS·
(TA = + 2S"C unless otherwise noted)
Voo (to DGND) . . . . . . .
VIN (to AGND) . . . . . . . .
Digital Input Voltage to DGND
lour to AGND .
VIN toAGND ..
AGNDto DGND
DGNDtoAGND
Power Dissipation (Any Package)
To +7SoC . . . . . . .
Derates above + 7S·C by

. . . . . . . . . . +7V
. . . . . . . . . +3SV
-O.3V to Voo +O.3V
-O.3V to Voo
.. ±35V
.0 to Voo
.0 to Voo
450mW
6mWrC

Operating Temperature Range
Commercial (K, L Versions)
Industrial (B, C Versions)
Extended (T, U Versions)
Storage Temperature . . . .
Lead Temperature (Soldering, 10secs)

·Stresses above those listed under "Absolute Maximum Ratings" may
cause pennanent damage to the device. This is a sttess rating only and
functional operation of the device at these or any other conditions
above those indicated in the operational sections of this speciflC8tion
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device re1isbility.

CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.

TERMINOLOGY
RESOLUTION: Nominal change in attenuation when moving
between two adjacent codes.
MONOTONlCITY: The device is monotonic if the analog output decreases (or remains constant) as" the digital code increases.
FEEDTHROUGH ERROR: That portion of the input signal
which reaches the output when all digital inputs are high. See
section on Applications.
OUTPUT LEAKAGE CURRENT: Current which appears on
the loUT terminal with all digital inputs high.
TOTAL HARMONIC DISTORTION: A measure of the harmonics introduced by the circuit when a pure sinusoid is applied to the input. It is expressed as the harmonic energy
divided by the fundamental energy at the output.
ACCURACY: The difference (measured iIi dB) between the
ideal transfer function as listed in Table I and the actual transfer function as measured with the device.

o to +700c
- 25"C to + 85°C
- S5"Cto + 125"C
-65"C to + 1500c
. . . . . +3000c

WARNING!

cJ

~~EDEVICE

DlGITAL-TO-ANALOG GLITCH IMPULSE: The amount of
charge injected from the digital inputs to the analog output
when the inputs change state. This is normally specified as
the area of the glitch in either pA-Secs or nV-Secs depending
upon whether the glitch is measured as a current or voltage
signal. Glitch impulse is measured with VIN = AGND.
PROPAGATION DELAY: This is a measure of the internal
delays of the circuit and is defined as the time from a digital
input change to the analog output current reaching 90% of its
final value.
WRITE CYCLE TIMING DIAGRAM

*

II~
'<"!r- lito.

--\l~

NOTES:
1. ALL INPUT SIGNAL RISE AND FALL TIMES

MEASURED FROM 10'lI0 TO 90% OF VoD. VoD
~ +S\I, 1," 11" 2Ons.

~~-

:~:c,'

DATA IN

~, t",,"~~.

_ ' D S _ 1DM

J.r:V""'"-D-"-'-'N';;-=\L

(00-071

\IlL

2. TIMING MEASUREMENT REFERENCE LEVEL
ISV1H ;VIL .

.

v..

STABLE

OUTPUT CAPACITANCE: Capacitance from loUT to ground.
PIN CONFIGURATIONS
LCCC

DIP
Q

R..

Z

.'"

j

u
Z

J J

3

2

1

2.

v,.

..

,.

,,

V..

OGNO 4

\Vii

07(MSBJ 5

os

Ne 6

"

18 V DD

17WR

AD71"
TOP VIEW
(Not

06 7

to Scale)

05 8

16NC
15

Ci

14 DO {LSBj

01

• ,.S

~
Ne = NO CONNECT

REV. A

11 12 13
u
;;

z

a

SPECIAL FUNCTION AUDIO PRODUCTS 7-11

•

AD7111
CIRCUIT DESCRIPTION
GENERAL CIRCUIT INFORMA110N
The AD7111 consists'of a 17-bit 1t-21t CMOS multiplying
D/A convener with extensive digital logic. The lpgic translates the 8-bit binary input into a 17-bit word which is used
to drive the D/A converter. Input data on the D7-DO bus'is
loaded into the input data latches using CS and WR control
signals. The rising edge of Wit latches the input data and initiates the internal data transfer to the decoder. A minimum
time tRFSH, the refresh time, is required for the data to propagate through the decoder before a new data write is
attempted.

that the attenuation step size at any point is consistent with
the step size guaranteed for monotonic operation at that
point.
EQUIYALENT CIRCUIT ANALYSIS
Figure 2 shows a simplified circuit of the D/A converter
section of the AD7111 and Figure 3 gives an approximate
equivalent circuit.
The current source ILEAKAGB is composed of surface and
junction leakages and as with most semiconductor devices,
approximately doubles every lOoC-see Figure 11. The resistor
RO as shown in Figure 3 is the equivalent output resistance of
the device which varies with input code (excluding all O's
code) from O.SR to 2R. R is typically llkO. COUT is the
capacitance due to the N channel switches and varies from
about 60pF to 185pF depending upon the digital input. For
further information on CMOS multiplying D/A converters
refer to "Application Guide to CMOS Multiplying D/A converters" which is available from Analog Devices, Publication Number G479-15-SI7S.

The transfer function for the circuit of Figure 1 is given by:
Yo = -YIN 10 exp _ 0.375 N
20

I:~I

or

dB=-0.375N

Where 0.375 is the step size (resolution) in dB and N is the
input code in decimal for values 0 to 239. For 240EtN";25S
the output is zero. Table I gives the output attenuation
relative to OdB for all possible input codes.
The graphs on the last page give a pictorial representation of
the specified accuracy and monotonic ranges for all grades of
the AD7111. High attenuation levels are specified with less
accuracy than low attenuation levels. The range of monotonic
behavior depends upon the attenuation step size used. For
example, the AD7111L is guaranteed monotonic in 0.375dB
steps from 0 to -54dB inclusive and in 0.75dB steps from 0
to -72dB inclusive. To achieve monotonic operation over the
entire 88.5dB range it is necessary to select input codes so

.F.

L-i-I--+i-f-....+-f ,........;..+--1-....--""'.
~~~--~-1:.-~~--~----_AGND
SWITCH DRIVERS

Figure 2. Simplified DIA Circuit of AD7111
~.-.---

...

VIN

Figure 3. Equivalent Analog Output Circuit of AD7111

Figure 1. Typical Circuit Configuration

""

D7-D4 0000

0001

0010

0011

0100

0101

0110

0111

1010

1011

1100

1101

1110

1111

0.0
6.0
12.0
18.0
24.0
30.0
36.0
42.0

0.375
6.375
12.375
18.375
24.375
30.375
36.375
42.375

0.75
6.75
12.75
18.75
24.75
30.75
36.75
42.75

1.125
7.125
13.125
19.125
25.. 125
31.125
37.125
43.125

1.5
7.5
13.5
19.5
25.5
31.5
37.5
43.5

1.875
7.875
13.875
19.875
25.875
31.875
37.875
43.875

2.25
8.25
14.25
20.25
26.25
32.25
38.25
44.25

2.625
8.625
14.625
20.625
26.625
32.625
38.625
44.625

1000
3.0
9.0
15.0
21.0
27.0
33.0
39.0
45.0

1001

0000
0001
0010
0011
0100
0101
0110
0111

3.375
9.375
15.375
21.375
27.375
33.375
39.375
45.375

3.75
9.75
15.75
21.75
27.75
33.75
39.75
45.75

4.125
10.125
16.125
22.125
28.125
34.125
40.125
46.125

4.5
10.5
16.5
22.5
28.5
34.5
40.5
46.5

4.875
10.875
16.875
22.875
28.875
34.875
40.875
46.875

5.25
11.25
17.25
23.25
29.75
35.25
41.25
47.25

5.625
11.625
17.625
23.625
29.625
35.625
41.625
47.625

1000
1001
1010
1011

48.0
54.0
60.0
66.0

48.375
54.375
60.375
66.375

48.75
54.75
60.75
66.75

49.125
55.125
61.125
67.125

49.5
55.5
61.5
67.5

49.875
55.875
61.875
67.875

50.25
56.25
62.25
68.25

50.625 51.0
56.625 57.0
62.625 63.0
68.625 69.0

51.375
57.375
63.375
69.375

51.75
57.75
63.75
69.75

52.125
58.125
64.125
70.125

52.5
58.5
64.5
70.5

52.875
58.875
64.875
70.875

53.25
59.25
65.25
71.25

53.625
59.625
65.625
71.625

1100
1101
1110
1111

72.0
72.375
78.375
78.0
84.0
84.375
MUTB MUTB

73.875
79.875
85.875
MUTB

74.25
80.25
86.25
MUTB

74.625
80.625
86.625
MUTB

75.75
81.75
87.75
MUTE

76.125
82.125
88.125
MUTE

76.5
82.5
88.5
MUTE

76.875
82.875
88.875
MUTE

77.625
77.25
83.25 83.625
89.25 89.625
MUTE MUTE

72.75 73.125 73.5
78.75 79.125 79.5
84.75 85.125 85.5
MUTB MUTB MUTB

75.0
75.375
81.375
81.0
87.375
87.0
MUTE MUTE

Table I. ldeel Attenuation in dB

7-12 SPECIAL FUNCTION AUDIO PRODUCTS

1/1.

Input Code

REV. A

Applications Information - AD7111
DYNAMIC PERFORMANCE
The dynamic performance of the AD7ll1 will depend upon
the gain and phase characteristics of the output amplifier,
together with the optimum choice of PC board layout and
decoupling components. Figure 4 shows a printed circuit layout which minimizes feedthrough from VIN to the output in
multiplying applications. Circuit layout is most i~ortant if
the optimum performance of the AD7ll1 is to be achieved.
Most application problems stem from either poor layout,
grounding errors, or inappropriate choice of amplifier.

Vio jvo 0 .....0'.....'
PlN1

OUTPUT

~n~:;-

-- -- GNO
v'''rO
- -

INPUT~

AGNO

_

_

DIGITAL

INPUTS

LAYOUT SHOWS COPf'ER SIDE II .... BOTTOM VIEWI

GAIN TRIM RESISTORS Rl AND R2 Of FIGURE 1

ARE NOT INCLUDED.

Figure 4. Suggested Layout for AD7111 and Op-Amp

It is recommended that when using the AD7111 with a high
speed amplifier, a capacitor (C1) be connected in the feedback
path as shown in Figure 1. This capacitor, which should be
between 30pF and SOpF, compensateS for the phase lag introduced by the output capacitance of the D/A converter. Figures
S and 6 show the performance of the AD7ll1 using the
AnSi7, a fully compensated high gain superbeta amplifier,
and the ADS44, a fast FET input amplifier. The performance
without C1 is shown in the middle trace and the response with
C1 in circuit is shown in the bottom trace.
500-,v

I
C1 =OpF

\loUT

C1 = 47pF

VOUT

'5>'

toilS

DATA CHANGE FROM 80H toOOH

Figure 5. Response of AD7111 with AD517

Cl =OpF

C1 = 47pr

DATA CHANGE fROM 8CI4 TO 0011

Figure 6. ResponlJ8 of AD7111 with AD544

In conventional CMOS D/A converter design parasitic capacitance in the N-channel D/A converter switches can give rise to
glitches on the D/A converter output. These glitches result

REV. A

from digital feedthrough. The AD7111 has been designed to
minimize these glitches as much as possible.
For operation beyond 250kHz, capacitor C1 may be reduced
in value. This gives an increase in bandwidth at the expense of
a poorer transient response as shown in Figures 6 and 12. In
circuits where C1 is not included the high frequency roll-off
point is primarily determined by the characteristics of the
output amplifier and not the AD7111.
Feedthrough and absolute accuracy are sensitive to output
leakage current effects. For this reason it is recommended that
the operating temperature of the AD7111 be kept as close to
25°C as is practically possible, particularly where the device's
performance at high attenuation levels is important. A typical
plot of leakage current vs. temperature is shown in Figure 11.
Some solder fluxes and cleaning materials can form slightly
conductive fibns which cause leakage effects between analog
input and output. The user is cautioned to ensure that the
manufacturing process for.circuits using the AD7111 does not
allow such films to form. Otherwise the feedthrough, accuracy
and maximum usable range will be affected.
STATIC ACCURACY PERFORMANCE
The D/A converter section of the AD7111 consists of a 17-bit
R-2R type converter. To obtain optimum static performance
at this level of resolu tion it is necessaty to pay great attention
to amplifier selection, circuit grounding, etc.
Amplifier input bias current results in a dc offset at the output
of the amplifier due to the current flowing through the feedback resistor RFB. It is recommended that an amplifier with
an input bias current of less than 10nA be used (e.g., ADS 17
or ADS44) to minimize this offset.
Another error arises from the output amplifier's input offset
voltage. The amplifier is operated with a fixed feedback resistance, but the equivalent source impedance (the AD7ll1
output impedance) varies as a function of attenuation level.
This has the effect of varying the "noise" gain of the amplifier,
thus creating a varying error due to amplifier offset voltage.
It is recommended that an amplifier with less than SOIlV of
input offset be used (such as the ADS17 or AD OP-(7) in
dc applications. Amplifiers with higher offset voltage may
cause audible "thumps" in ac applications due to dc output
changes.
The AD7ll1 accuracy is specified and tested using only the
internal feedback resistor. Any Gain Error (i.e., mismatch of
RFB to the R-2R ladder) that may exist in the AD7ll1 D/A
converter circuit results in a constant attenuation error over
the whole range. The AD7111 accuracy is specified relative
to OdB attenuation, hence "Gain" trim resistors-R1 and R2
in Figure 1-can be used to adjust VOUT =VIN precisely (i.e.,
OdB attenuation) with input code 00000000. The accuracy
and monotonic range specifications of the AD7111 are not
affected in any way by this gain trim procedure. For the
AD7ll1L/C/U grades, suitable values for R1 and R2 of
Figure 1 are R1 =5000, R2 = 1800; for the K/BIT grades
suitable values are R1 = 10000, R2 = 2700. For additional
information on gain error the reader is referred to Application
Note "Gain Error and Gain Temperature Coefficient. of C..MOS
Multiplying DACs" by Phil Burton available from Analog
Devices Inc., Publication Number E630-10-6/81.

SPECIAL FUNCTION AUDIO PRODUCTS 7-13

7

AD7111 -TypicaiPerfo,nna"ce Characteristics

L....
TA

~

J

-+uoc

"".!,ov

/

1

DATA INPUT n11X)!;XX

V
/'

Al'f'LlED TO ALL DATA INPUTS

. . . . oy

o.
B

,

V

/

,

1• OA

.. /
10

ztj

'J \
.V

0.'
0

,

75

TEMPERATURE

100

_·c

Figure .11. Output Leakage Current, VB. Temperature

..

.,

.,'

INPUT VOLTAGE - Volts

....
~r· ...

..

.I

T""',,,a·c 1

-JP"TA INPUT CODE· oooooooo

A

1\
/ \

CI .• ~

'v."WR115

Figure 7. Typical Supply Current VB. Logic Input Level

J..7
-,-........,

-.......

\ ~;~f~
\
\

ADO"

CI·O .....

"'p, A

\

\

\

\
\

\
·18
·18

1.1

12
IS
18
ATTENUATION - dB

Figure 8. Typical Attenuation Error for 0.75dB Steps

,

0

-

~~

,- VoD.'.5V

TA"+7O"C

,

!'.. ['.
~

T,,-"'Z,",C

\

,

-J-,

"

...

~-Vc

fREQUENCV - Hz

.

I
Vw-IV,..

r--!NPUT CODt· OOOD 0000
T... ".WC

C,-47pF

'\ '\

."

l'\.

-so

V

\

..

.,.,

,

10

'"

...

MONOTONICITV FOR '.5d8ATUNl,IATtoNSTEPS

\..\.'

I..\~

'1IO.375dBATTENUATIONSTEI'SIIJ'lli

--r- ,...

'h

(h

"sl-+--+-+--+-I--+===F=:;J:--+-+--+-I--+-+-+-H
.....,

~

na

»

••

"

•••

n

~

.o.,~

0_- ~-- .-

---

....;

1-"' '-.

I""'"

-

1-

.-- -- ._-

I-'

,-- ri.,.;",
~

M~

ATTlNUATION- . .

Figure 10. Accuracy Specification for K/B/T Grade Devices
at TA=+25'c
.

7-14 SPECIAL FUNCTION AUDIO PRODUCTS

,....

§§~U."h
...

".,1-1--+---+---+-+--+-+---11--1""""--1--+---+---+-+-+-++1
~ "'''~,",I-+""",_+,--+~r-I-'
! .0·"iF-r.;-;.;-~-;;-;,;;-..p;.--;,;-~-.;.-~-~-~~ --- ---

0

Figure 13. Distortion·vs. Frequency Using AD544
Amplifier

Figure 9. Typical Attenuation Error for 3dB Steps VI.
Temperature
\.\.\.\\\\\O.1MIATTENUATtOlf'STEPS \ '

/

/

fREQUENCY - Hz

ATTENUATION - dB

OOOC

,.... \

,...

Figure 12. Frequency RlI$ponse with AD544 and AD517
Amplifiers

,

'I'.

,

\

.

,

AnENUATION-d8

FigUre 14. Accuracy Specification for LICIU Grade Devices
at TA = +25'C
.
.

REV. A

LOGDAC
CMOS Logarithmic D/A Converter
AD7118* I

1IIIIIIII ANALOG

WDEVICES
FEATURES
Dynamic Range 85.5dB
Resolution 1.5dB
Full ±25V Input Range Multiplying DAC
Full Military Temperature Range -55°C to +125°C
Low Distortion
Low Power Consumption
Latch Proof Operation (Schottky Diodes Not Required)
Single 5V to 15V Supply
APPLICATIONS
Digitally Controlled AGC Systems
Audio Attenuators
Wid. Dynamic Range AID Converters
Sonar Systems
Function Generators

FUNCTIONAL DIAGRAM

Vo

D4

03

02

01

'---::O"'.G"'IT""A':"'L""N::::pu':::r=-s---'

GENERAL DESCRIPTION
The LOGDAC" AD7l18 is a CMOS multiplying D/A converter which attenuates an analog input signal over the range
o to -85.5dB in 1.5dB steps. The analog output is determined
by a six-bit attenuation code applied to the digital inputs. Operating frequency range of the device is from dc to several
hundred kHz.

PIN CONFIGURATION (Not to Scale)

II

The device is manufactured using an advanced monolithic silicon gate thin-film on CMOS process and is packaged in a l4-pin
dual-in-line package.
ORDERING GUIDE

Model
AD7118KN
AD7118LN
AD7ll8BQ
AD71l8CQ
AD7118TQ2
AD7118UQ2

Temperature
Range

o to
o to

+70°C
+70°C
- 25°C to + 85°C
- 25°C to + 85°C
-55°C to + 125°C
-55°C to + 125°C

Specified
Accuracy
Range

Package
Option'

o to 42dB
o to 48dB
o to 42dB
o to 48dB
o to 42dB
o to 48dB

N-16
N-16
Q-16
Q-16
Q-16
Q-16

NOTES
IN = Plastic DIP; Q = Cerdip. For outline information
see Package Infonnation section.
2To order MIL·STD-883, Class B processed parts, add
1883B to·part number.

'Protected by U.S. Patent No. 4521,764.
LOGDAC is a trademark of Analog Devices, Inc.

REV. A

SPECIAL FUNCTION AUDIO PRODUCTS 7-15

(You = +5Vor +15V, VIN = -lOY dc,l
AD7118 -SPECIFICA'JIONS
"
amplifier AD544 except where stated)
TAo. +Z5°C
PARAMETER

VD»- +5V

NOMINAL RESOLUTION
ACCURACY RELATIVE TO VIN
AD7118L/C/U
Oto-3OdB
-31.5 to -42dB
-43.5 to -48dB
AD7118K1BfI'
a to-3OdB
-31.5 to -42dB
MONOTONIC RANGE
Nominall.SdB Steps

oUT

TA, .. T..... ,T...

VDD -+15V

VoD. +5V VoD a+15V

UNITS

1.5

dB

1.5

1.5

1.5

to.35
to.7
tl.0

to.35
to.5

to.4

to.4

dB max

ZO.8
±1.3

ZO.7

±0.7

tl:0

dB max
dB max

±D.5
±D.75

±0.5
±D.75

zO.S

to.5

dB max

tl.0

±D.8

dB max

Oto-72

a to-66

dB
dB

Oto-72
a to-66
CodeRanse
Monotonic Over Full Code Range

Monotonic OVer Full

VIN INPUT RESISTANCE
(PIN 12)

All Grade.
L/C/UGrade
KlBfI' Grade

9
17
21

9
17
21

9
17
21

9
17
21

kOmin
kOmax
kOmax

ROB INPUT RESISTANCE
(PIN 13)

All Grades
LlC/UGrade
K/BfI' Grade

9.45
18
22

9.45
18
22

9.45
18
22

9.45
18
22

kOmax
kOmax

3.0
0.8
±l

13.5
1.5
±1

3.0
0.8

13.5
1.5

V max:

tl0

tl0

""max

5

-

5

-

1

15
2

V min
V max
mAmax

DIGITAL INPUTS
Input High Volt. Requirements VIH
Input Low Voltage Requirements VIL
Input Leakage Current
POWER SUPPLY
VDD for Specified Accuraey

-

-

15
1

0.5

IDD

TEST CONDITIONSI
COMMENTS

Accuracy is me_Ired using
cittuit of Figure:. 1 and includes
any effects due to mismatch
be""",, RFa and the R·2R
laddet circuit.

Digital Inputs 00000o to 110000
Digital Inputs 00000o to 101100

L/C/UGrade
K/BfI' Grade
All Grades

Nominal 3dB Steps

=AGND =DGND =OV, output

k,omin

V min

Digital Inputs = VDD

Digital Inputs =- OV or VDn
(See Fipre 7)

Speclficadons subJect to chaqe Without nouce:,

AC PERFORMANCE CHARACTERISTICS
These characteristics are included f~r design guidance only and are not subject to test.

Von = +SVor + lSV, VIN == -lOY except where stated, IOlTI'

= AGND = DGND ==

TA=+2SOC

PARAMETER

VDD=+5V

OV, output amplif)eI' ADS44 except where stated.

TA·T...........

VOD-+1SV

VOD=+SV

UNITS

VOO= +15V

DC Supply Rejection.acain/AVDD

0.Q1

O.OOS

0.01

0.005

dBper% max

Propagation Delay
Digital to Analog Glitch Impulse

1.8
225

0.4
1200

2.2

0.5

".max

Output Capa.citance (Pin 14)
Input Capacitance Pin 12 and Pin 13
Feedthrough at 1kHz
L/C/U Grade
KlBfI' Grade
Total Hannonic Distortion
Intennodulation Distortion
Output Noise Voltage Density
Digital Input Capacitance

100
7
-86
-80
-85
-79
70
7

100
7
-86
-80
-85
-79
70
7

100
7
-68
-63
-85
-79
70
7

-

-

6Voo= ±10%,
Input code = 100000
Full Scale Change
Measured with ADLH0032CG
as output amplifier for input
code transition 100000 to 000000.
CI of FiJUre 1 is OpF.

nV secs typ

pFmax

100
7
-68
-63
-85
-79
70
7

pFmax
dB max
dB max
dB typ

Feedthrough is also de..r·
mined by circuit layout
VIN=6Vrm,
per DIN 45403 Bla" 4
Includes ADS44 amplifier noise

dBZ'irz
nV
z max
pFmax

-,....---,..----,---r---.---.-....,.-'"T-'"T-....,.-..,

+1.5 ....

~

Voo -+1N.+1&V

+... t--I-----0 louT
L......;..~~4-4J--;.+.-4---.... AGND
SWITCH DRIVERS

Figure 2. Simplified D/A Circuit of AD7118
.c, -33pF TYPICAL

...................

,.-

DIGITAL INPUT
DS - DO (PINS 2-1'

Figure 1. Typical Circuit Configuration

CouT

EQUIVALENT CIRCUIT ANALYSIS
Figure 2 shows a simplified circuit of the DIA converter section
of the AD 71 18 and Figure 3 gives an approximate equivalent
circuit.
N

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Digital Input
D5
DO

000000
000001
000010
00 0011
000100
00 01 01
00 0110
00 0111
001000
001001
001010
001011
00 11 00
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
0111 00
0111 01
011110

Attenuation
dB
0.0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0
13.5
15.0
16.5
18.0
19.5
21.0
22.5
24.0
25.5
27.0
28.5
30.0
31.5
33.0
34.5
36.0
37.5
39.0
40.5
42.0
43.5
45.0

VOUT

L...---4>----<~-oAGND
"YIN. NilS THE THEVEN'N EQUIVALENT VOLTAGE GENERATOR
DUE TO THE INPUT VOLTAGE VIN. THE BINARY ATTENUATION
FACTOR N AND THE TRANSfER FUNCTION OF THE R·2ft LADDER.

Figure 3. Equivalent Analog Output Circuit of AD7118
I

10.00
8.414
7.079
5.957
5.012
4.217
3.548
2.985
2.512
2.113
1.778
1.496
1.259
1.059
0.891
0.750
0.631
0.531
0.447
0.376
0.316
0.266
0.224
0.188
0.158
0.133
0.112
0.0944
0.0794
0.0668
0.0562

N

31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

Digital Input

011111
100000
100001
100010
100011
100100
100101
10 0110
100111
101000
10 1001
10 10 10
10 10 11
101100
10 11 01
10 11 10
101111
11 0000
11 00 01
11 00 10
110011
11 01 00
11 01 01
11 01 10
11 01 11
1110 00
111001
11 1010
111011
1111 XX'

Attenuation
46.5
48.0
49.5
51.0
52.5
54.0
SS.5
57.0
58.5
60.0
61.5
63.0
64.5
66.0
67.5
69.0
70.5
72.0
73.5
75.0
76.5
78.0
79.5
81.0
82.5
84.0
85.5
87.0
88.5

VOUT

I

0.0473
0.0398
0.0335
0.0282
0.0237
0.0200
0.0168
0.0141
0.0119
0.0100
0.00841
0.00708
0.00596
0.00501
0.00422
0.00355
0.00299
0.00251
0.00211
0.00178
0.00150
0.00126
0.00106
0.000891
0.000750
0.000631
0.000531
0.000447
0.000376

00

NOTES
1 VIN = -lOY de
I X = 1 or O. Output is fully muted for N;;;t60
J Monotonic operation is not guaranteed for N = 58, 59

Table I. Ideal Attenuation
7-18 SPECIAL FUNCTION AUDIO PRODUCTS

lIS.

Input Code

REV. A

Applications Information-AD7118
DYNAMIC PERFORMANCE
The dynamic performance of the A07118 will depend upon
the gain and phase characteristics of the output amplifier,
together with the optimum choice of PC board layout and
decoupling components. Figure 4 shows a printed circuit layout which minimizes feedthrough from VIN to the output in
multiplying applications. Circuit layout is most important if
the optimum performance of the A07118 is to be achieved.
Most application problems stem from either poor layout,
grounding errors, or inappropriate choice of amplifier.
o
~AMPPIN1
v+

f@....o

OUTPUT

AD711. PIN I

0

el LOCATION - " " I

AGND

INPUT - - - NOTE INPUT SCREEN
TO REDUCE FEEDTHROUGH

v-

0
0

:::: }
0--0-

DIGITAL
INPUTS

DGND
~
LAVOUT SHOWS COPPER SIDE Ii.•.. BOTTOM VIEW)

Figure 4. Suggested Layout for AD7118 and Op Amp

It is recommended that when using the A07118 with a high
speed amplifier, a capacitor Cl be connected in the feedback
path as shown in Figure 1. This capacitor, which should be
between 30pF and SOpF, compensates for the phase lag intI'oduced by the output capacitance of the DIA converter. Figures
5 and 6 show the performance of the AD7118 using the
ADSI7, a fully compensated high gain superbeta amplifier,
and the ADS44, a fast FET input amplifier. The performance
without Cl is shown in the middle trace and the response with
Cl in circuit is shown in the bottom trace.
DIGITAL
INPUTS

Vo

Vo

Figure 5. Response of AD7118 with AD517L

Figure 6. RBlponlll of AD7118 with AD544S

In conventional CMOS D/A converter design parasitic capacitance in the N-channel 01 A converter switches can give rise to
glitches on the D/A converter output. These glitches result
from digital feedthrough. The AD7118 has been designed to
minimize these glitches as much as possible. It is recommended
that for minimum glitch energy the AD7118 be operated with
Voo = SV. This will reduce the available energy for coupling

REV. A

across the parasitic capacitance. It should be noted that the
accuracy of the A07118 improves as VDO is increased (see
Figure 8) but the device maintains monotonic behavior to at
least -66dB in the range S ";;VOO";; 1 S volts.
For operation beyond 2S0kHz, capacitor Cl may be reduced
in value. This gives an increase in bandwidth at the expense of
a poorer transient response as shown in Figures 6 and 11. In
circuits where C 1 is not included the high frequency roll-off
point is primarily determined by the characteristics of the
output amplifier and not the A07118.
Feedthrough and absolute accuracy for attenuation levels
beyond 42dB are sensitive to output leakage current effects.
For this reason it is recommended that the operating temperature of the A07118 be kept as dose to 2SoC as is practically
possible, particularly where the device's performance at bigh
attenuation levels is important. A typical plot of leakage current VI. temperature is shown in Figure 10.
Some solder fluxes and deaning materials can form slightly
conductive films which cause leakage effects between analog
input and output. The user is cautioned to ensure that the
manufacturing process for circuits using the A07118 does not
allow such films to form. Otherwise the feedthrough, accuracy
and maximum usable range will be affected.
STATIC ACCURACY PERFORMANCE
The O/A converter section of the AD7118 consists of a 17-bit
R-2R type converter. To obtain optimum static performance
at this level of resolution it is necessary to pay great attention
to amplifier selection, circuit grounding, etc.
•
Amplifier input bias current results in a dc offset at the output
of the amplifier due to the current flowing through the feedback resistor RFB. It is recommended that an amplifier with
an input bias current of less than 10nA be used (e.g., ADS 17
or AOS44) to minimize this offset.
Another error arises from the output amplifier's input offset
voltage. The amplifier is operated with a fixed feedback resistance, but the equivalent source impedance (the AD7118
output impedance) varies as a function of attenuation level
This has the effect of varying the "noise" gain of the amplifier,
thus creating a varying error due to amplifier offset voltage. To
achieve an output offset error less than one half the smallest
step size, it is recommended that an amplifier with less
than SO~V of input offset be used (such as the AOS 17 or
AD OP-07).
If dc accuracy is not critical in the application, it should be
noted that amplifiers with offset voltage up to approximately
2 millivolts can be used. Amplifiers with higher offset voltage
may cause audible "thumps" due to dc output changes.
The A07118 accuracy is specified and tested using only the
internal feedback resistor. It is not recommended that "gain"
trim resistors be used with the A07118 because the internal
logic of the circuit executes a proprietary algorithm which
approximates a logarithmic curve with a binary 01 A converter:
as a result no single point on the attenuator transfer function
can be guaranteed to lie exactly on the theoretical curve. Any
"gain-error" (i.e., mismatch of RFB to the R-2R ladder) that
may exist in the AD7118 D/A converter circuit results in a
constant attenuation error over the whole range. Since the
gain-error of CMOS multiplying O/A converters is normally
less than 1%, the accuracy error contribution due to "gainerror" effects is normally less than O.09dB.
SPECIAL FUNCTION AUDIO PRODUCTS 7-19

AD7118-Typical Peliormance Characteristics
,00r------,------r-----,------,------,-----71

600

I
TA =+26°C

,/'

/'

,

.9,0.01----t-----j--j----t----+7.l~

LOGIC THRESH7
VOLT~

/

/'

VIN = -10V

V
n

c:

/

:0

300~

V
v:

~

i
200

...t.

INPUTS AT OV

./

/'
",

••

,

I

,.

~
~ 1.01-----j------,f------.II~--_+---+--_j

§

00

-:!-__~~---:'::__--~---_==--_:~

O.,L-_ _

'4

'2

POWER SUPPLY - Votu

w

5

100 ALL DIGITAL

,

~

a

'6

TEMPERATU RE _ °C

Figure 7. Digital Threshold & Power Supply Current vs
Power Supply

,
!!i, ,
i

O. 4

O. 2

-.......

0

~

""'"

-0. >
-0. 4

-0.6
-0.8

Veo'" 15V

'\.'\.

"

I
Veo = 10V

~

-,.

0

\\

36

48

Veo'" +6V
-5 -TA =+25°C

i!:
;;

-6

z
;;:

7

"

-
iii
~

/'

-10

l

-5

/

~ -20

iii
i

-10

-15

V CONTROL

--40

-20
-25
10

-so
100

,.
FREQUENCY (Hz)

10k

100.

-61l
-3

V

/

-30

/~

S

= -1V

..---

/
-2

-1

CONTROL VOLTAGE (VOLTS)

•

REV.C

SPECIAL FUNCTION AUDIO PRODUCTS 7-31

7-32 SPECIAL FUNCTION AUDIO PRODUCTS

Monolithic Peak Detector
with Reset-and-Hold Mode
PKD-Ol I

r.ANALOG
WDEVICES
FEATURES
• Monolithic Design for Reliability and Low Cost
• High Slew Rate .............................. O.SVlIIS
• Low Droop Rate
TA=2SoC ............................... O.1mV/ms
TA = 12SoC .............................. 10mV/ms
• Low Zero-Scale Error . .. . . . . . . . . . . . . . . . . . . . . . . ... 4mV
• Digitally Selected Hold and ReHt Modes
• Reset to Positive or Negative Voltage Levels
• Logic Signals TTL and CMOS Compatible
• UncommlHed Comparator on Chip
• Available in Die Form

Through the DET control pin. new peaks may either be
detected or ignored. Detected peaks are presented as positive output levels. Positive or negative peaks may be detected
without additional active circuits since amplifier A can operate as an inverting or noninverting gain stage.
An uncommitted comparator provides many application
options. Status indication and logic shaping/shifting are typical examples.

PIN CONNECTIONS

ORDERING INFORMATIONt
ZSOC

PACKAGE

Vzs
(mV)

14-PIN DUAL-IN-LiNE PACKAGE
HERMETIC'
PLASTIC

4
4
7
4
7
•

PKD01AY'
PKD01EY
PKD01FY
PKD01EP
PKD01FP

14-PIN HERMETIC DIP
(V-Suffix)

OPERATING
TEMPERATURE
RANGE

EPOXV DIP
(P-Sufflx)

MIL
IND
IND
COM
COM

For devices processed in total compliance to MIL·5TD·883. add 1883 after part
number. Consult factory for 883 data sheet.
Burn-in is available on commercial and industrial temperature range parts in
CsrDIP. plastic DIP. and TO·can packages.

•

FUNCTIONAL DIAGRAM
+IN

-IN

OUTPUT

V+

v-

GENERAL DESCRIPTION
The PKD-01 tracks an analog input signal until a maximum
amplitude is reached. The maximum value is then retained as
a peak voltage on a hold capacitor. Being a monolithic circuit,
the PKD-01 offers significant performance and package density advantages over hybrid modules and discrete designs
without sacrificing system versatility. The matching characteristics attained in a monolithic circuit provide inherent
advantages when charge injection and droop rate error
reduction are primary goals.
Innovative design techniques maximize the advantages of
monolithic technology. Transconductance (gm) amplifiers
were chosen over conventional voltage amplifier circuit
building blocks. The "gm" amplifiers simplify internal
frequency compensation, minimize acquisition time and
maximize circuit accuracy. Their outputs are easily switched
by low glitch current steering circuits. The steered outputs
are clamped to reduce charge injection errors upon entering
the hold mode or exiting the reset mode. The inherently low
zero-scale error is reduced further by active "Zener-Zap"
trimming to optimize overall accuracy.
The output buffer amplifier features an FET input stage to
reduce droop rate error during lengthy peak hold periods. A
bias current cancellation circuit minimizes droop error at
high ambient temperatures.

REV. A

L~c;!~

O-,---I>lr------'

OUTPUT
·IN
.IN

-IN
.IN

RST

0--'-1---1
PKD-Ol

RST

o

o

DEf

OPERATIONAL MODe

0 PEAK DETECT
1 PEAK HOLD
RESET

Indeterminat.

SWITCHES SHOWN FOR:

AS1", "0",

DEl = "0"

SPECIAL FUNCTION AUDIO PRODUCTS 7-33

PKD,.Ol
ABSQLUTE MAXIMUM RATJ,NGS (Note 1)
Supply Voltage ; .•••.••••••• ;••.•. ; ........ :.;~ ••••.••.•• : ...... ; ................ ±18V
Input Voltage ........ ; ......................... ; ... Equal to Supply Voltage
Logic and Logic.Ground
Voltage ... ; ....................................... Equal to Supply Voltage
Output Short·Circuit Duration- .... : ............................... Indefinite
Amplifier A or B Differential Input Voltage ....................... ±24V
Comparator Differential Input Voltage ............................. ±24V
Comparator Output VQltage
............... , ...................... , ...... Equal to Positive Supply Voltage
Hold Capacitor Short-Circuit Duration ...................... Indefinite
Lead Temperature (Soldering, 60 sec) .......................... 300°C
Storage Temperature Range
PKD-01AY, PKD-01EY, PKD-01FY .......... -as·Cto +1S0·C
PKD-01EP, PKD-01FP .............................. -6S·C to +12SoC

ELECTRICAL CHARACTERISTICS

at Vs

Operating Temperature Range
PKD-01AY .................................................. -SS·Cto +12S·C
PKO-01 EY, PKD-01 FY ................................ -2S·C to +8S·C
PKO-01 EP, PKO-01 FP .................................... O·C to +70·C.
Junction Temperature ................... : ............... -6S·C to + 1S0·C
e lc

UNITS

14·Pin Hermetic DIP (Y)

99

12

'CIW

14·Pin Plastic DIP (P)

76

33

'CIW

e lA (Note 2)

PACKAGE TYPE

NOTES:
I. Absolute maximum ratings apply to both DICE and packaged parts. unless
otherwise noted.
2. a JA is specified for worst case mounting conditions. i.B., 9 1A is specified for

device in socket for CerDIP and P·DIP packages.

= ±1SV, CH = 1000pF, TA = 2S·C.
PKD-01A1E

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

PKD-01F

MAX

MIN

TYP

MAX

UNITS

"8m" AMPLIFIERS A, ..
Zero-Scale Error

Vzs

4

3

7

mV

Input Offset Voltage

Vos

3

3

6

mV

Input Bias Current

I.

80

150

80

250

nA

Input Offset Current

los

20

40

20

75

Voltage Gain

Av

RL = lOkfl, Vo = ±IOV

Open-Loop
Bandwidth

BW

Av=1

Common-Mode
Rejection Ratio

CMRR

-IOV:5 VCM :5 +IOV

Power Supply
Rejection Ratio

PSRR

±9V~VsS±18V

Input Voltage Range

VCM

Slew Rate

SR

Feedthrough Error

(Note.! I

18

to

25
0.4

80

90

74

V/mV

0.4

MHz

90

dB
dB

86

96

76

96

±IO

±II

±IO

±II

V

0.5

V/"s

0.5
.1V'N= 20V, DET = I, RST = O. (Note I I

nA

25

66

80

Acquisition Time to
0.1% Accuracy

taq

20V Step. AVCL = + I. (Note II

41

Acquisition Time to
0.01% Accuracy

taq

20V Step. AVCL = + I. (Note I I

45

66
70

80
41

dB
70

45

p.S

"s

COMPARATOR
Input Offset Voltage

Vas

0.5

1.5

3

mV

Input Bias Current

18

700

1000

700

1000

nA

Input Offset Current

los

75

300

75

300

Voltage Gain

Av

2kfl Pull-up Resistor to 5V

Common-Mode
Rejection Ratio

CMRR

-IOV:5VCM :5+IOV'

Power Supply
Rejection Ratio

PSRR

±9V:5Vs :5±18V

VCM

(Note 1)"

Input Voltage Range

NOTES:
I. Guaranteed by design.
2. Due to limited production test times. the drQOp current corresponds to
junction temperature (Til. The droop current vs. time lafter power-ani

82

3.5

7.5

VlmV

106

82

106

dB

76

90

76

90

dB

±11.5

±12.5

±II.5

±12.5

V

warmed-up (TA) droop current specifitatlon is correlafed to the junction

temperature (Tjl value. PMI has a droop current cancellat.ion circuit which
minimizes droop current at high temperature. Ambient (TA) temperature
are not subject to production testing.

curve clarifies this point. Since most devices (in use) are on for more than

~ifications

I second, PMlspecllles droop rate lor aMbient temperature (TAl also. The

3. DET= I. RST=O.

7-34 SfECIAL FUNCTION AUDIO PRODUCTS

nA

7.5

REV.

A

PKO-Ol
ELECTRICAL CHARACTERISTICS at Vs = ±15V, CH = 1000pF, TA = 25°C. (Continued)
PKO-D1F

PKO-01A/E
SYMBOL

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

Low Output Voltage

VOL

I SINK " SmA, Logic GND = OV

-0.2

0.15

0.4

-0.2

0.15

0.4

V

"OFF" Output
Leakage Current

IL

VOUT = 5V

25

80

25

80

~A

Output ShortCircuit Current

Ise

VOUT = 5V

12

45

12

45

mA

Is

SmV Overdrive, (Nole 3)
2kn Pull-up Resislor 10 SV

PARAMETER

Response Time

150

ISO

UNITS

ns

DIGITAL INPUTS-RIT, DET (See Nole 3)
2

2

Logic "1" Inpul Voltage

VH

logiC "0" Inpul Voltage

VL

V

logic "1" Input Current

I'NH

VH =3.5V

0.02

Logic "0" Input Current

IINL

VL =0.4V

1.6

10

1.6

10

~A

0.01
0.02

0.07
0.15

0.01
0.03

0.1
0.20

mVlms

0.8

0.8

V
~A

0.02

MISCELLANEOUS
Tj =2So C,

(See Note 2)

Droop Rete

VDR

Output Voltage Swing:
AmplilierC

VoP

Short-Circuit Current:
AmplifierC

Ise

Switch Aperture Time

tap

75

7S

ns

Switch Switching Time

Is

50

50

. ns

Slew Rete: Amplifier C

SR

RL = 2.Sk

Power Supply Current

Isv

No Load

TA =2So C
W=1
RL = 2.5k

±l1.S

±12.S

7

15

TA

±12

7

IS

2.5

=:l:15V, CH =1000pF, -55°C s
s +70·C for PKD-01EP, PKD-Ol FP.

TA

7

SYMBOL

CONDITIONS

MIN

40

s +125·C for PKD-01AY, -25·C s

TYP

rnA

VIps

9

6

TA

mA

s +85·Cfor

PKD-01F

PKD-01A1E
PARAMETER

V

2.5

5

ELECTRICAL CHARACTERISTICS at Vs
PKD-01EY, PKD-OIFY and O·C s

40

±11

MAX

MIN

TYP

MAX

UNITS

mV

"gm" AMPLIFIERS A, B
Zero·Scale Error

Vzs

6

12

I npul Offsel Voltage

Vos

5

10

mV

Average Input
Offset Drifl

TCVos

Input Bias Current

I.

Input Offset Current

los

Voltage Gain

Av

R L = 10kl!, Vo = ±10V

CMRR

-10V" Ve .. "

Power Supply
Rejection Ratio

PSRR

±9V

I nput Voltage Range

Ve ..

INote 11

Slew Rale

SR

Acquisition Time to
0.1 % Accuracy

taq

Common-Mode
Rejection Ratio

I Note 11

~

74

Vs:S ±18V

+ 1.

-24

-9

-24

~V/oC

160

250

160

500

nA

30

100

30

150

7.5

+ IOV

20V Step. AveL =

-9

,Note 1 ,

nA
V/mV

82

72

80

dB
dB

80

90

70

90

±10

±11

±10

±11

V

0.4

0.4

V/~s

60

60

~s

COMPARATOR
Input Offset Voltage

Vos

Average Input
Offset Drift

TCVos

Input Bias Current

18

REV. A

2.5
,Note 1,

mV

-4

-6

-4

-6

~V/oC

1000

2000

1100

2000

nA

SPECIAL FUNCTION AUDIO PRODUCTS 7-35

II

PKO-Ol
ELECTRICAL CHARACTERISTICS atVs = :t1SV; CH = 1000pF, -5S'CsTA s +12S'Cfor PKD-01AY, -2S'CsTA s +85'Cfor
PKD-01 EY, PKD-01 FY and O'C s TA S +70'C for PKD-01 EP, PKD-01 FP. Continued

PKD-01F

PKD-01A1E
PARAMETER

SYMBOL

Input Offset Current

los

Voltage Gain

Av

2kO Pull-up Resistor to 5V

Common-Mode
Rejection Ratio

CMRR

Power Supply
Rejection Ratio

CONDITIONS

MIN

TYP

MAX

100

600

MIN

TYP

MAX

100

600

UNITS
nA

4

6.5

2.5

6.5

VlmV

-10V S VCMs +10V

SO

100

80

92

dB

PSRR

±9V S Vs S ±lSV

72

82

72

86

dB

Input Voltage Range

VCM

I Note 1)

±11

Low Output Voltage

VOL

ISINK S SmA. Logic GND = OV

-0.2

"OFF" Output
Leakage Current

IL

VouT =5V

Output ShortCircuit Current

Isc

VouT =5V

Response Time

ts

5mV Overdrive.
2kO Pull-up Resistor to 5V

6

±11
0.15

0.4

25

100

10

45

-0.2

6

V
0.15

0.4

V

100

180

"A

10

45

mA

200

200

ns

DIGITAL INPUTS-RST, DET ISee Note 3)
Logic "1" Input Voltage

VH

Logic "0" Input Voltage

VL

Logic "I" Input Current

I'NH

VH = 3.5V

0.02

Logic "0" Input Current

I'NL

VL =0.4V

2.5

15

2.5

15

,.A

Droop Rate

VOR

Tj = Max. Operating Temp
TA = Max. Operating Temp.
DET = 1. I Note 2)

1.2
2.4

10

20

3
6

15
20

mVims

Output Voltage Swing:
AmplillerC

VOP

RL =2.5k

Short-Circuit Current:
AmplllierC

lac

2

2

V

0.8

O.S
0.02

V
,.A

MISCELLANEOUS

±11
6

±12
12

Switch Aperture Time

tap

Slew Rate: Amplifier C

SR

RL = 2.5k

2

Power Supply Current

ISY

No Load

5.5

±10.5
40

75

6

±12
12

V
40

75

mA
ns

V/"s
8

6.5

10

mA

NOTES:
1. Guaranteed by design.
2. Due to limited production test times, the droop current corresponds to
junction temperature ITj)' The droop current vs. time lalter power-on)
curve clarifies this point. Since most devices lin use) are on lor more than
1 second. PMI specifies droop rate lor ambienttemperature ITA) also. The
warmed-up ITA) droop current specification is correlated to the junction
temperature ITj ) value. PMI has a droop current cancellation circuit which
minimizes droop current at high temperature. Ambient ITAI temperature
~ificatlon8 are not subject to production testing.
3. DET=l.RST=O.

7-36 SPECIAL FUNCTION"AUDIO PRODUCTS

REV. A

PKD-Ol
DICE CHARACTERISTICS
1. RST (RESET CONTROL)

8. INVERTING INPUT (B)

2. V+

10. COMPARATOR NONINVERTING INPUT

3.
4.
5.
8.
7.
••

11. COMPARATOR INVERTING INPUT
12. COMPARATOR OUTPUT
13. LOGIC GROUND
14. DET (PEAK DETECT CONTROL)
A,B(A) NULL
C,D(B) NULL

OUTPUT
C H (HOLD CAPACITOR)
INVERTING INPUT (A)
NONINVERTING INPUT (A)
VNON INVERTING INPUT (B)

DIE SIZE 0.101 x 0.091 inch, 9191 sq. mils
(2.565 x 2.311mm, 5.93 sq mm)

WAFER TEST LIMITS at Vs = ±15V, CH = 1000pF, TA = 25°C.
PKD-01N
PARAMETER

SYMBOL

CONDITIONS

LIMIT

UNITS

"8m" AMPLIFIERS A, B
Zero-Scale Error

Vzs

Input Offset Voltage

Vos

Input Bias Currant

Is

Input Offset Currant

lOS

Voltage Gain

Av

Common-Mode
Rejection Ratio

CMRR

Power Supply
Rejection Ratio

PSRR

mVMAX

RL = 10k!!. Vo= ±10V

±9V:S Vs:S ±lBV

Input Voltage Range

(Notel)

Feedthrough Error

<1V ,N = 20V. l5ET = 1. RST = O. (Note 1)

6

mVMAX

250

nAMAX

75

nAMAX

10

VlmV MIN

74

dBMIN

76

dBMIN

±".5

VMIN

66

dBMIN

3

mVMAX

1000

nAMAX

COMPARATOR
Input Offset Voltage

Vos

Input Bias Current

300

nAMAX

2k!! Pull-up Resistor to 5V. (Note 1)

3.5

VlmVMIN

CMRR

-lOV:S VOM:S +10V

62

dBMIN

PSRR

±9V:SVs :S±lBV

76

dBMIN

Input Offset Current

lOS

Vollege Gain

Av

Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio
Input Vollege Range
Low Output Vollege

(Note 1)
VOL

ISINK:S 5mA. Logic GND = 5V

±".5

VMIN

0.4
-0.2

V MAX
VMIN

"OFF" Output
Leakage Currant

60

"A MAX

Output ShortCircuit Currant

45
7

mAMAX
mAMIN

ISC

VOUT=5V

NOTES:
1. Guaranteed by design.
2. Due to limited produc1lon test times. the droop current corrasponds to
junction temperatura (T,). The droop currant vs. time (after power-on)
curve clarifies this pOint. Since most devices (In use) ara on for mora than
1 second. PMI specifies droop rate for ambienttemperatura (T...) also. The

REV. A

warmed-up (TA) droop currant specification is corralated to the junction
temperatura (Tj ) value. PMI has a droop currant cancellation circuit which
minimizes droop currant at high temperatura. Ambient (T...) temperature
specifications ara not subject to production testing.
3. ~=1. RST=O.

SPECIAL FUNCTION AUDIO PRODUCTS 7-37

II

PKO-Ol
WAFER TEST LIMITS at \Is = ±15V, CH= 1000pF, TA= 25°C. (Continued)
PKD-01N
PARAMETER

SYM.OL

CONDInONS

LIMIT

UNITS

DIGITAL INPUTS-RIT, DET I See Not, 3) .
Logic "I" Input Voltage

'VH

2

VMIN

Logic ''0" Input Voltage

.VL

0.8

V MAX

Logic "I" Input Current

IINH

VH =3.SV

Logic "0" Input Current

IINL

VL =0..4V

Droop Rate

VCR

Output Voltage Swing:
AmpliflerC

VOP

Short-Circuit Current:
AmpliflerC

Isc

Power Supply Current

Isv

pAMAX
10

pA MAX

T j =2SoC.
TA = 2SoC (See Note 21

0.1
0.20

mVlmsMAX
",VlmsMAX

RL =2.Sk

±11

VMIN

·40

7

mAMAX
mAMIN

9

mAMAX

MISCELLANEOUS

No Load

1 second. PMI specifies droop rate for ambient temperature j TA ) also. The
warmed-up (TAJ droop current specification is correlated to the junction
temperature (Tjl value. PMI has a dro.op current cancellation circuit which
minimizes droop current at high temperatures. Ambient t TAl temperature
specifications are not subject to production testing.
3. l5ET 1. AST O.
Electrical tests are performed at wafer probe t!) the limits shown. Due to variations in assembly methods and normal yield loss. yield after packaging is not
guarenteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
NOTES:
1. Guaranteed by design.
2. Due to limited production test times, the droop current corresponds to
junction temperature (T;). ~he droop current va. time (after power-on)
curve clarifies this pOint. Since most devices (in use) are on for more than

=

=

TYPICAL ELECTRICAL CHARACTERISTICS at Vs = ±15V, CH = 1000pF, and TA = 25°C, unless otherwise noted.
PKD-01N
PARAMETER

SYMBOL

CONDITIONS

TYPICAL

UNITS

..... AMPLIFIERS A, B
SIIWR.te

SR

0.5

VIpS

Acquisition Time

t.

0.1'110 Accuracy. 20V step. AVCL = 1. (Note 11

41

,,8

Acquisition Time

t.

0.01'110 Accuracy. 20V step. AVCL = 1. (Note 11

45

pS

150

n8

n8

COMPARATOR
SmV Overdrive.
2kO Pull-up Resistor to +SV

Respon.. Time
MISCELLANEOUS
Switch Aperature Time

tal!

75

Switching Time

ts

50

n8

Buffer Slew Rate

SR

2.S

VI,.s

RL =2.SkO

7-38 SPECIAL FUNCTION AUDIO PRODUCTS

REV. A

PKD-Ol
TYPICAL PERFORMANCE CHARACTERISTICS

,.
~0

-..

"
10

l'i
w

":i
...'"
~

---

-2
-6
-10

35

j

•

w

~ 25

.2

:.

0

>

t;;

~

20

"- ........ i'....

15

....r-. r-

-2

0

~

12

30

"~

_56°C
+2SoC

..

;;

!

~~ +125°C_

r-- V- SUPPLY

-14

-1.

..i"'"

-ss<>c 5 TA ~ +12SoC

'"u:w

A,BlosvsTEMPERATURE
40

~NPUT + RANGE = V+

~

~

A AND B AMPLIFIERS OFFSET
VOLTAGE VI TEMPERATURE

A AND B INPUT RANGE
VB SUPPLY VOLTAGE

10

-4

...,.

15

-6~~~~~~~~~__~~
-75 -50 -25
25
50
75
100 125

o

-75 -50

-25

INPUT SPOT NOISE
vs FREQUENCY

0

25

50

75

100

125 150

TEMPERATURE (DC)

TEMPERATURE (DC)

SUPPLY VOLTAGE +V AND -V (VOLTS)

WIDEBAND NOISE
vs BANDWIDTH

AMPLIFIER B CHARGE INJECTION
ERROR VB INPUT VOLTAGE
AND TEMPERATURE
"

+1.0

-+-+-+;+-1-++-<.,....+5+-+-+-+-+-i +10

-101--+-+-1-+....
-+.

V1N·(VOLTS)

100

10

1.0

1k

FREQUENCY 1Hz)

BANDWIDTH (kHz)

OUTPUT VOLTAGE SWING va
SUPPLY VOLTAGE (DUAL
SUPPLY OPERATION)

AMPLIFIER A CHARGE INJECTION
ERROR VB INPUT VOLTAGE
AND TEMPERATURE
+1.0
POLARITY OF
ERROR MAY BE
POSITIVE OR
NEGATIVE

CH'= 1000pF
TA.,~ +2SoC

+0.5

-10

-5

+5

VIN (VOLTS)

+10

p-2

t-...

+12SoC

-
~

:J

0

TIME 12O.usIDIV.1

LARGE-SIGNAL
NONINVERTING RESPONSE

SETTLING TIME FOR + 10V
TO OV STEP INPUT

SETTLING TIME FOR -10V
TO OV STEP INPUT
ov

~

~

l

~
w

~>

ov

~

6

...
...~

...>
:J
I!:

5

ov

5

TIME (101ls/DIV.J

7-40 SPECIAL FUNCTION AUDIO PRODUCTS

TIME 120/As/OIV.1

TIME (201ls/DIV.I

REV. A

PKO-Ol
TYPICAL PERFORMANCE CHARACTERISTICS

.

OFF ISOLATION
VI FREQUENCY

CHANNEL TO CHANNEL
ISOLATION VI FREQUENCY

SMALL-SIGNAL OPEN LOOP
GAIN/PHASE VI FREQUENCY

100

120
TA = +2SOC

TA" +2SoC

RL " 10kSl

C L • 3DpF

100

.......

BO

..

,

180

"1\

60

...

TEST CONDITION:
C H = l000pF

AMPI'FIER
20

-30 L---L.__..I---I__-'-__~--I.~
,

10

100

lk

10k

lOOk

1M

10M

fREQUENCY (Hz)

o

i i
AND

I--

A,Ay°_'

r-..... ~

CONjECTE01IN

1\f'..I

...

+1.iA'N

20

AMPLifiER AlB) OFF, INPUT = 20V PK-PK

,

AMP~IFIER ~'.' o~' INPuT' ov I
10

100

lk

10k

TOOk

I

0

1M

10

10M

100

Tk

10k

tOOk

1M

10M

FREQUENCV (Hz)

FREQUENCV IHzt

DROOP RATE VI TIME AFTER
POWER ON

ACQUISITION TIME VI EXTERNAL
HOLD CAPACITOR AND
ACQUISITION STEP

T1· "~5'C'

CH " l000pF

ACQUISITION TIME VI INPUT
VOLTAGE STEP SIZE

. .----------.--....,..--...
... ~----+_----4_----~~~~

400~~-+----+----+----4-~~

/V

I

BO

~

4S

~--~~--~~~4"

A.A)=+1

I'.....

B, AV= tl

BO

!
!!
g::!

V

30

~----I__

20

~----+___'~;jZ'-----~----_l

,0~~~~----4_----~----_l

00

2

3

5

• '0

6

TIME AFTER POWER APPLIED (MINUTES)

VI

5

DROOP RATE
TEMPERATURE

10

15

20

INPUT STEP (VOL lSI

HOLD CAPACITANCE IpF)

ACQUISITION OF
SINEWAVE PEAK

ACQUISITION OF STEP INPUT

10000

+10V

"

+IOY

OY
-lOY

~:;~:~TURE J

ov

+IOY
OY

JUNCTlON......-::K.TEMPERATURE!!!!!!!!!

-lOY

-IOV

1

-100

-60

+60

+100

+150

TEMPERATURE reI

REV. A

SPECIAL FUNCTION AUDIO PRODUCTS 7-41

I

PKO-Ol
TYPICAL PERFORMANCE CHARACTERISTICS
cOMPARATOR OUTPUT
RESPONSE TIME
(2kO PULL-UP RESISTOR, TA = +250 C)

COMPARATO,(I O,UTPUT
RESPONSE TIME
(2kO PULL-UP RESISTOR, TA = +25 0 C)

INPUT LOGIC RANGE ~B
SUPPLY VOLTAGE

,. r=+==+=+=~;.:;;~

~

~
w

'41-,-~--~--+--~~~~F-~-4

•
+5

~w

"~

"

3

0

>

,

2

-5 >-

~

5

!50

+5

-.

g

i
;;:

~

'0 1-,-~---t:7"'-'=+VIf~::;V+ FOR
1-~-~--:::o""'f-----55°C SrA.s

i~

+l2S'C

0

>

~

;;:

0,
TIME (50nS/DIV.)

_,. '------L_ _--'-_ _-'-_ _'--_~..::~'"

,.

15

'2

SUPPL V VOL rAGE +V AND -v (VOL TSI

INPUT RANGE OF LOGIC
GROUND vs SUPPLY VOLTAGE

LOGIC INPUT CURRENT vs
LOGIC INPUT VOLTAGE

,.
~

~,

0

'4
'0

Z

"a:0

,
"'1"'"

"
!,!

".9
0
w

"a:
">-

-2
~

-6

.

+25°C

-5"C

-'4

I

~

_+25°C

ACCEPTABLE GROUND

+25°C

I!!oo,;

--

+l25°C

·i'i'C

-

""

4

/I,t

-5"C

PIN POTENTIAL IS
BETWEEN SLICE LINES

12

15

,.

I

-2

SUPPLY VOLTAGE +V AND -V (VOL TSI

-1

,I

I

1\

-5"C
....C

+125°(:

I

LOGIC 0

-3

'"

f-'

I

...

+12SoC
-5So C

,I

LOGIC , _

~

:~... l..!1iI"

V~ '5!!1

-10

-,.

...

~

Z

~

I I

~
~

SUPPLY CURRENT VB
SUPPLY VOLTAGE

LOGIC GROUND = ()V

I

I

I

4

,4
LOGIC INPUT VOLTAGE (VOLTS)

o

12
SUPPLY +V AND

15

,.

-v {VOL TSI

HOLD MODE POWER SUPPLY
REJECTION vs FREQUENCY

'00 r-'"---,---,.----,---.,---,
801-,--4--,-,.,--1-----+-

'0

7-42 SPECIAL FUNCTION AUDIO PRODUCTS

'00

1k
'Ok
FREQUENCY IHzl

,00k

'M

REV. A

PKO-Ol
TYPICAL PERFORMANCE CHARACTERISTICS
COMPARATOR INPUT BIAS
CURRENT VB DIFFERENTIAL
INPUT VOLTAGE
+3

~.,

I

Vs '" If15V
TA = +2S D C

I

COMPARATOR OFFSET VOLTAGE
vs TEMPERATURE

COMPARATOR los
VB TEMPERATURE
110

I

,

INPUT CURRENT

~~SLTE:: TL~:~T~~A

100

--to

~

ffi +2
j!:

1

!i!

-

;;
.3
t- +1

'"
'"~

0

:Ii

I--

~

1l

!<

I.-- INPUT
~THER

OTHER
INPUT
AT -TOV

AT OV

90

""

80

"-

70

0

u

~ 0

;;

OTHER
INPUT

t-

:J

80

..........

r---.. t--...

AT +lOV

~

-

I

-1

-15

-10

50

-5
+5
+10
INPUT VOLTAGE (VOL lSI

-75 -50

+15

OUTPUT SWING OF
COMPARATOR vs
SUPPLY VOLTAGE

COMPARATOR Is
vs TEMPERATURE

,.

'8

1200

~
0
~

1000

'\.

10

0:

"- r......
400

S
1t
"8

"

........

~.-

,

Z

-6

--~ Ii!!w'

-,

g -,. -'0

V-

-18

-25

a

25

50

75

100

125

150

TA '-55

,

~

o

~
w

'"":;

g

.

\
~~ ::~n '*

~ 2

INVERTING INPUT = VIN
NON INVERTING INPUT

l'\-

\
\

§

1.5

t-

=ov

3

t-

1l
~

1.D

0.5

:J
0

w

""5

RL = TkO

TO+5V

"

0.5

1.0

INPUT VOLTAGE (mV)

REV. A

~

J I

--

•

-

1.5

2.0

150

I

VI

V

VI

0

~/

'2

-

,.~

'5

18

50

100

150

200

250

300

TIME (ns)

-v (VOL lSI

COMPARATOR RESPONSE
TIME VB TEMPERATURE

+~25"C
w

'25°~~

:l
~Ui 31----l--t-+\--'\t---t---I1-----l
g!:i

_55°C~

O.S

D.'

...., ~

0.2

-0.2

125

E'I!!..

0.8

~
0
>

100

+125°C,_

~

'0
Vs = ±15V
TA = +25°C

I

75

r--l~
r-j / ~''''5OC-

COMPARATOR OUTPUT VOLTAGE
VB OUTPUT CURRENT AND
TEMPERATURE

COMPARATOR TRANSFER
CHARACTERISTIC

I

TA = .2S"C

.,25°C I -

_+2SoC

SUPPLY VOLTAGE +V AND

TEMPERATURE fel

50

+25°C

0

-75 -60

P~LL-U;

-5S"C

:J

200

25

I-- RESIST~R • 2k!! /

I

:5

~

r-...

V+

~ tJIIf!'I';_55°C
-2

~

f---

,

0

COMPARATOR RESPONSE
TIME vs TEMPERATURE

~~
.-t'__

,

-25

TEMPERATURE reI

TEMPERATURE (OCI

J)
;/
~~

~~

5o

2

P'"

~
10

12

10 - OUTPUT SINK CURRENT (mAl

,.

50

100

150

200

250

300

TIME (ns)

SPECIAL FUNCTION AUDIO PRODUCTS 7-43

•

PKO-Ol
THEORY OF OPERATION
The typical peak detector uses voltage amplifiers and a diode
or an emitter follower to charge the hold capacitor, C H,
unidirectionally (Figure 1). The output impedance of A plus
0, 's dynamic impedance, r d, make up the resistance which
determines the feedback loop pole. The dynamic impedance

by providing the output buffer with an FET input stage. A
current cancellation circuit further reduces droop current
and minimizes the gate current's tendency to double for
every 10·C temperature change.

is r d =.!!!.. Id is the capacitor charging current.
qld
The pole moves toward the origin of the 5 plane as Id goes to
zero. The pole movement in itself will not significantly
lengthen the acquisition time since the pole is enclosed in the
system feedback loop.
When the moving pole is considered with the typical frequency compensation of voltage amplifiers there is however,
a loop stability problem. The necessary compensation can
increase the required acquisition time. PMl's approach
replaces the input voltage amplifier with a transconductance
amplifier; Figure 2.

Figure 1. Conventional Voltage Amplifier Peak Detector

The PKD-D1 transfer function can be reduced to:
VOUT
1 + ..!9.ti

gm
Where:

gm~

+

_1_

gmROUT

1,.AlmV,

ROUT~

1+~
gm

Figure 2. Trensconductance Amplifier Peak Detector

20MO.

The diode in series with A's output (Figure 2) has no effect
because it is a resistance in series with a current source. In
addition to simplifying the system compensation, the input
transconductance amplifier output current is switched by
current steering. The steered output is clamped to reduce
and match any charge injection.
Fig. 3 shows a simplified schematic of the reset "gm" amplifier, B. In the track mode, 0, & 04 are ON and 02 & 03 are
OFF. A current of 21 passes through 0" I is summed at "B"
and passes through 0" and is summed with gmVIN' The
current sink can absorb only 31, thus, the current passing
through 02 can only be: 2K -gmVIN. The net current into the
hold capacitor node then, isgmV1N (C H=21-(21-g mV1N ). The
hold mode, O 2 & 03 are ON while 0, & 04 are OFF. The net
current intothetopof 0, is-I until D3turns ON. With 0, OFF,
the bottom of 02 is pulled up with a current I until 04 turns
ON, thus 0, & O 2 are reverse biased by ~O.6V and charge
injection is independent of input level.

A

~:::I--t==1==:'-.---! }~~~;:ROL
A :> B '" PEAK DETECT

A<.", PEAK HOLD

Figure 3. Transconductance Amplifier with Low GIHch
Current Switch

The monolithic layout results in pOints A and B having equal
nodal capacitance. In addition, matched diodes 0, and 02
have equal diffusion capacitance. When the transconductance amplifier outputs are switched open, pOints A and Bare
ramped equally but in opposite phase. Diode clamps 03 and
04 cause the swings to have equal amplitudes. The net
charge injection (voltage change) at node C is therefore zero.
A

The peak transconductance amplifier, A, is shown in Figure
4. Unidirectional hold capacitor charging requires diode 0,
to be connected in series with the output. Upon entering the
peak hold mode 0, is reverse biased. The voltage clamp
limits charge injection to approximately 1pC and the hold
step to O.6mV.
Minimizing acquisition time dictated a small CHcapacitance.
A 1000pF value was selected. Droop rate was also minimized

7-44 SPECIAL FUNCTION AUDIO PRODUCTS

~:::t---t=~I==:"'--!} ~~;:'OL
_ . ._ _ _~'-- v-

A >8 .. pEAK DETECT

A<,,, PEAK HOLD

Figure 4. Peak Detecting Transconductance Amplifier with
Switched Output

REV. A

PKO-Ol
APPLICATIONS INFORMATION
OPTIONAL OFFSET VOLTAGE ADJUSTMENT
Offset voltage is the primary zero scale error component
since a variable voltage clamp limits voltage excursions at
01'S anode and reduces charge injection. The PKO-Ol circuit
gain and operational mode (positive or negative peak
detection) determine the applicable null circuit. Figures A
through 0 are suggested circuits. Each circuit corrects
amplifier C offset voltage error also.
A. NULLING GATED OUTPUT gm AMPLIFIER A. Diode 01
must be conducting to close the feedback circuit during

''''0

Vs+

amplifier A Vos adjustment. Resistor network RA - Rccause
0 1 to conduct slightly. With OET=OandVIN=OVmonitorthe
PKO-Ol output. Adjust the null potentiometer until VOUT= OV.
After adjustment, disconnect Rc from CH.
B. NULLING GATED gmAMPLIFIER B. Set amplifier B signal
inputto V1N = OV and monitor the PKO-Ol output. Set OET= 1,
RST = 1 and adjust the null potentiometer for VOUT= OV. The
circuit gain - inverting or noninverting - will determine
which null circuit illustrated in Figures A through D is
applicable.

Vs-

R,

"0

R,
VIN-

>~--4>--o VOUT

R,
YIN+
R,

v..

VOUT

"0

R.

Vs-

"'0

-15V

R.

Vs+

r~"F

-15V

PK"·'4:':..0
I

NOTES:

CH=1000pF

-=-

1. NULL RANGE = =Vs(';;)

2MO

I

NOTES:

R
1:n

c

-=

c

2Mn

PK"·'4~o

200

1. NULL RANGE", ::tVs (;;)(R,~1Ra)

R,

CH=1000pF

1kD

-=

-=-

2. DISCONNECT ftc FROM eH AFTER AMPLIFtER A ADJUSTMENT.
3. REPEAT NULL CIRCUIT FOR RESET BUFFER AMPLIFIER 8 IF REQUIRED.

":"

2. DISCONNECT He FROM eN AFTER AMPUFIER A ADJUSTMENT.
3. REPEAT NULL CIRCUIT FOR RESET BUFFER AMPLIFIER B IF REQUIRED.
R..,. R, AND He NOT NECESSARY FOR AMPLIFIER B ADJUSTMENT.

Figure B. Vos Null Circuit for Differential Peak Detector

Figure A. Vos Null Circuit for Unity Gain Positive Peak
Detector
Vs-

R,
GAIN=1+ A,+R3

R,

R,

25'0

R,

V,. 0--00(\1..,...-...,-------1\1'1'------,

Vs+

V,-

>"T"iI--6--o VOUT

R.
Your

Y'N

R,R,
V.+

R.... R1+A2

-15V

-15V

PK""40:':..0

PKD. '4::'.0
NOT...

1. NUll RANGE = ::I:Va(':;)

I

2Mn

-=

,:n

-=

2. DtSCONNECT He FROM eM AFTER AMPLIFIER A ADJUSTMENT,
3. REPEAT NULL CIRCUIT FOR RESEr BUFFER AMPLIFIER 8 IF REQUIRED.

Figure C. Vos Null Circuit for Negative Peak Detector

REV. A

I

R

eM =1000pF

NOTES:

1. NULL RANGE= :t:Vs(~)

-=

CH=1000pF

2M"

2. DISCONNECT Re FROM eH AFTER AMPLIFIER A ADJUSTMENT.
3. RePEAT NULL CIRCUIT FOR RESET BUFFER AMPLIFIER 8 IF REQUIRED.

A

8

1k0

"':"

Figure D. VOS Null Circuit for Positive Peak Detector With
Gain

SPECIAL FUNCTION AUDIO PRODUCTS 7-45

7

PKO-Ol
PEAK HOLD CAPACITOR RECOMMENDATIONS
The hold capacitor (CH) serves as the peak memory element
and compensating capacitor. Stable operation requires a
minimum value of 1000pF. Larger capacitors may be used to
lower droop rate errors, but acquisition time will increase.

With the comparator in the low state (VOL), the output stage
will be required to sink a current approximately equal to
Vc /R 1'

Vc

COMPARATOR INPUT

Zero scale error is internally trimmed for CH == 1000pF. Other
CH values will cause a zero scale shift which can be approximated with the following equation.

ft.
VOH

~Vzs(mV) = 1 x 1()3(PC) -O.6mV
CH(nF)

ft_

.'

The peak hold capacitor should have very high insulation
resistance and low dielectric absorption. For temperatures
below 85° C, a polystyrene capacitor is recommended, while
a Teflon capacitor is recommended for high temperature
environments.
CAPACITOR GUARDING AND GROUND LAYOUT
Ground planes are recommended to minimize ground path
resistance. Separate analog and digital grounds should be
used. The two ground systems are tied together only at the
common system ground. This avoids digital currents returning to the system ground through the analog ground path.

The C H terminal (Pin 4) is a high-impedance point. To
minimize gain errors and maintain 'the PKD-01's :inherently
low droop rate, guarding Pin 4 as shown in Figure 2 is
recommended.

INVERTING
COMPARATOR INPUT

DIGITAL

V-

aND

Figure 1
Table I.
Yc VOH

R1

R2

5

3.5 2.7K 6.2K

5

5.0 2.7K

15

R1"~
ISINK

3.5 4.7K 1.5K

15

5.0 4.7K 2.4K

15

7.5 7.5K 7.5K

15

10.0 7.5K 15K

R2'"

(V: )
VOH -1

PEAK DETECTOR LOGIC CONTROL (AST, DI'i')
The transconductance amplifier outputs are controlled by
the digital logic Signals RST and i5ET. The PKD-01 operational mode is selected by steering the current (11) through
01 and 02, thus providing high-speed switching and a predictable logic threshold. The logic threshold voltage is 1.4
volts when digital ground is at zero volts.

Other threshold voltages (VTH) may be selected by applying
the formula:
.
VTH" 1.4V + Digital Ground Potential.
Figure 2. CH terminal (Pin 4) guarding. See text.
COMPARATOR
The comparator output high level (Vo H) is set by external
resistors. It's possible to optimize nOise immunity while interfacing to all standard logic families - TTL, DTL, and CMOS.
Figure 1 shows the comparato~ output with external level
setting resistors. Table I gives typical R1 and R2 values for
common circuit conditions,

The maximum comparator high output voltage (V OH ) should
be limited to:

For proper operation, digital ground must always be at least
3.5V below the positive supply and 2.5V above the negative
supply. The RST or DETsignal must always be at least 2.8V
above the negative supply.
Operating the digital ground at other than zero volts does
influence the comparator output low voltage. The VOL level is
referenced to digital ground and will follow any changes in
digital ground potential:
VOL"' 0.2V + Digital Ground Potential.

VoH(maximum) < V+ -2.0V

7-46 SPECIAL FUNCTION AUDIO PRODUCTS

REV. A

PKO-Ol
BURN-IN CIRCUIT

PKD-01 LOGIC CONTROL

56kH
5%

,.

r---------~----Ov+

PKO·Ol

o.

ffi

+lBV

18kU

AST

DIGITAL
GROUND

13
12

361<1l

11

5%

10

~

CURRENT TO
CONTROL MODES

TYPICAL CIRCUIT CONFIGURATIONS
UNITY GAIN POSITIVE PEAK DETECTOR
v+

DETjRST
~----,---

v-

---, T -,---,

"

-+10V

PKD-O'J.

INPUT

III11IIII1I1II

OUTPUT

ov
+IOV

-ov

OUTPUT

TIME (50,us/DIV)

C.

~1000PF

POSITIVE PEAK DETECTOR WITH GAIN
v+

tOll!
1%

INPUT

INPUT

v-

14

OUTPUT

o-""'V'-+--t-+-I

>-rt=-+--<>

(GAIN", +2)

0-""'1'-+----'+-1

RESET
VOLTAGE"" ... tV
(RESETS TO - 4V)

OUTPUT

TIME (50,us/DIV!
RST

REV. A

J

CH

l000pF

SPECIAL FUNCTION AUDIO PRODUCTS 7-47

II

PKO-Ol
NEGATIVE PEAK DETECTOR WITH GAIN

v-

v+

DEi/ABY

"'0
''I.

INPUT

,.
PKD-Ol

1ot{J1%

o-""II'-+-"'-'=t--I

INPUT
(GAIN = -2)

OUTPUT

>-...--.=-+--0

3O.1kQ

,%
10kD1%
OUTPUT

TIME

RESET
VOLTAGE", -W

(50~DIV)

(RESETS TO - 4V)
RBY

UNITY GAIN NEGATIVE PEAK DETECTOR
v+

'''0
''I.

-ov

INPUT

v-

,.
PKO..ol

' ..0
v,. ~MI't-lr........,-t
''I.

--lOV
-+1DV

-ov

OUTPUT

AGAlN=-1

13

B GAIN = +1

TIME (60IlSIDIVI

J,c......
ALTERNATE GAIN CONFIGURATION
R,

PKO-Ol
>"1"iI-~-<> OUTPUT

R,
INPUT

<>-N>I'--I-+-I

NOTE:

vo~::~ O-NR'>I'-+-+-I
R,

IF 80TH INPUT SIGNAL (AMPLIFIER A INPUT) AND THE RESET

VOLTAGE (AMPLIfiER B INPUT HAVE THE SAME POSITIVE VOL TAGE GAIN THE GAIN CAN BE SET BY A SINGLE VOLTAGE DIVIDER
FOR BOTH INPUT AMPLifiERS.

R1, R2. R3 AND R4> SkU

J

~H;::1000pF

A3=R4=rt

7-48 SPECIAL FUNCTION AUDIO PRODUCTS

ift+1f2

REV. A

PKO-Ol
PEAK·TO·PEAK DETECTOR
PKDo01
POSlTtvE

.....

VPIC+

DETECTOR

1011t!

V,.
1011l!

PK[).Q1

.....

NEGATIVE

YPk-

DETECTOR
10ltll

POSITIVE PEAK DETECTOR WITH SELECTABLE RESET VOLTAGE

PKD.(Jl

V,N

0----------+"1---1

>---1r-t=-........, Vour
OV

av
VRS4

13

av

A1

A2

A3o-----'
... 0 - - - - - - '
PJrIIET'RST

REV. A

o---£>c------.J

NOTES:
RESET VOLTAGE = -l.OV

+1OY

LOGIC

GND

TRACE 1 '" 2V/DIV.
TRACE 2 = 5V/DIV.
TRACE 3 = 2V/DIV.

SPECIAL FUNCTION AUDIO PRODUCTS 7-49

I

7-50 SPECIAL FUNCTION AUDIO PRODUCTS

Voltage-Controlled
Amplifier
SSM-2013 I

r.ANALOG
WDEVICES

outputs, the SSM-2013 is ideal when logarithmic control of gain
is needed. The output current gain or attenuation is controlled
by applying a control voltage to the EXPO pin 9. The amplifier
offers wide bandwidth, easy Signal summing and minimum external component count.

FEATURES
o

o
o
o

o
o
o
o

0.01% THD Typ
0.03% IMD Typ
800kHz Unity-Gain Bandwidth
12dB Headroom (at Rating)
40dB Gain Capability
106dB Dynamic Range (17.5 Bits)
Full Class A Performance
Mute and Exponential Controls

The SSM-2013 can operate with more than 12dB of headroom
at the rated specifications or be configured for gains as high as
40dB. Inherently low control feedthrough and 2nd harmonic
distortion make trimming unnecessary for most applications. An
extremely wide control range of 11 OdB regulated by a flexible
antilogarithmic control port make this VCA a versatile analog
building block. With 800kHz bandwidth and 94dB SIN ratio at
0.01 % THD, the SSM-2013 provides a useful solution for a variety of signal conditioning needs in applications ranging from
professional audio to analog instrumentation, process controls
and more.

APPLICATIONS
o

o
o

o
o

Compressor/Limiters
Noise Gates
Automatic Gain Control
Noise Reduction Systems
Telephone Line Interfaces

ORDERING INFORMATION

PIN CONNECTIONS

PACKAGE
PLASTIC
14-PIN

OPERATING
TEMPERATURE
RANGE

14-PIN
PLASTIC DIP
(P-Suffix)

SSM2013P

GENERAL DESCRIPTION
The SSM-2013 is a high-performance monolithic Class A Voltage Controlled Amplifier. Operating with current mode inputs and

SIMPLIFIED SCHEMATIC

, - - - - - - - - 1.....- - - -......- _ - -...
·0.REF

+---1-"-0 OUT
>--_--+--f~BAL

IIUTECAP

12

GND 0'''',5'--.._ _- ,

SUB

REV. A

+-----_-.....----''-Q-REF

v-

SPECIAL FUNCTION AUDIO PRODUCTS 7-51

•

SSM-20l3
ABSOLUTE MAXIMUM RATINGS

PACKAGE TYPE

Supply Voltage ...................................................... 36V or ±18V
Junction Temperaturj! .................................................. +150°C
Operating Temperature Range ....................... -10°C to +55°C
Storage Temperature Range ........................ -65°C to + 150°C
Maximum Current into any Pin ........................................ 10mA
Lead Temperature Range (Soldering 60 sec) ................ 300°C

8jA(NOTE1)

14·Pin Plastic DIP (P)

UNITS
47

90

·CIW

NOTE:
1. 9 .• isspeclfledforworstcase mounting conditions, i.e., 9 1, is specified fordevios
irl socket for P·DIP package.

ELECTRICAL CHARACTERISTICS at Vs = ±15V and TA = 25°C, unless otherwise noted.
SSM-2013
PARAMETER

CONDITIONS

Positive Supply Voltage
Negative Supply Voltage (Note 1)
Positive Supply Currant
Negative Supply CUrrant
NegatIve Supply Bias Resistor

(Pin 7 to Pin 8)
Expo Input Bias

V0 = GND (Note 2)

Expo Control SsnsllMty

at Pin 9

MIN

TYP

MAX

+12
-7.9

+15
-8.5

+18

5.4
S.O

8.7

10.4
11.0

mA

675

900

1170

Cl

1.0

3.2

8.7

-00

-10

Mute Off (Logic Low)

0.0

Mute On (Logic High)

3.0

V

IIA
mVIdB

1.0
5

UNITS

15

-eo

V
V

Mute Attenuation

(@lkHz,VpIN10=+5V)

Currant Galn

Vo =GND
.

0.90

1.0

1.1

Current Output Offset

Vo=GND

-7.5

0

+7.5

Output Leakage

Vo=+600mV

-50

0

+50

Max Available Output Current

Vo -GND,I5k(pin3to-V)

±1.2

Current Bandwidth (3dB)

Vo-GND

800

kHz

Signal Feedthrough

Vo=+1.2V

-00

dB

Signal to Noise (20Hz· 20kHz)
(Notes3,4)

V0 = GND, No Signal

-114

dB

THO (Untrimmed)
(Note 4)

V0 = GND, lIN = 6OOIIAp-p

0.01

THO (Trimmed)

V0 = GND, lIN = SOOIIAp-p

0.004

IMD (Untrimmed) SMPTE
(Note 4)

V0 = GND, liN = 60011Ap-p

0.03

IMD (Trimmed) SMPTE

V0 = GND, I'N = 600llAp-p

0.012

92.5

dB

IIA
nA
mA

0.06

%
%

0.12

%
%

NOTES:
1.
2.
3.
4.

Measured at pin 8, pin 7 --I5V.
Vo Is voltage on pin 9 (VEXPd .
Referred to a 4OOIIAp-p input level.
Parameter Is sample tested to max limit (0.4% AQL).

7-52 SPECIAL FUNCTION AUDIO PRODUCTS

REV. A

SSM-20l3
+SUPPLY

MUTE

VUUTE S; +1V (VeA "ON"
~ +l.OV (VCA "OFF")

VMUTE

~CM
MUTE MUTE CAP

10

2

YOUT

-I
.".

-SUPPLY

FIGURE 1: Typical Connection

THEORY OF OPERATION
••300

The SSM-2013 is a current input/current output device. It is essentially a current mode amplifier where the output current/input
current transfer function is controlled by a control voltage applied
at the EXPO pin (9). Current mode operation allows easy adaptation to various voltage ranges at the input, output and control port. As configured, it offers large attenuation plus moderate
gain capability.

CHOOSING

~

"j!:
"

.....

!!

RIN
0.010

Most applications use the typical connection of Figure 1. In this
configuration, The SSM-2013 will accomodate input currents up
to 1.2mA without significant distortion or clipping. To set the
maximum operating current to 1.2mA, select RIN to equal VpeakJ
1.2mA.
As an example: For a 7Vp-p nominal signal level (±3.5V), select
RIN = 12kn. Here, liN operating is: 3.5V/12k = 30011A, which yields
12dB headroom from 1 .2mA. In some applications such as
broadcast equipment, 16 - 24dB headroom may be required.
Selecting ±300I1A nominal operating current yields 12dB headroom. Figure 2 shows the IMDITHD (Intermodulation and Total
Harmonic Distortion) characteristics of the SSM-2013 at this
300l1A or 600l1A peak-to-peak operating level.
Operation at higher input currents will increase distortion effects
whereas operation at lower currents will improve distortion but
decrease the SIN ratio. For example, operation with 20dB
headroom versus 12dB will improve the relative effects of IMDI
THO shown in Figure 2 by 2.5 times. For 20dB headroom, use
±120I1A nominal operating input current. At this level, the signal-to-noise ratio will be 86dB.
The SSM-2013 is capable of 40dB gain and as much as -95dB
attenuation. Gain or attenuation levels are set by the EXPO

REV. A

II

0.100

....

•.003

+20
-20
-40
CURRENT GAiNIATTENUAnON@12dB HEADROOM (dB)

1kHz (BANDWlD'nI2ClkHz)
(6OOp.A P1I CONSTANT OUTPUT LEVEL) OdS TO +4OdB

(6OOJLAH CONSTANT INPUT LEVEL) OdS TO -4Od8

FIGURE 2:
control pin as described in the next section. Figure 2 shows how
IMDITHD performance degrades with current gain and attenuation. Note also that distortion in the SSM-2013 is nearly all 2nd
harmonic. From a sonic standpoint, this is much less objectionable than other types of distortion.
For best performance, choose C'N and R'N for a cutoff frequency
below the audio band. C 'N will block DC offsets from previous
stages.

OUTPUT SECTION
When establishing circuit gain or attenuation, it is important to
consider the tradeoffs between gain/attenuation for the SSM2013 versus the gain of the output amplifier/current to voltage

SPECIAL FUNCTION AUDIO PRODUCTS 7-53

SSM-2013
converter. Operating the SSM-2013 with current gain above 20
or 30dB increases distortion as shown in Figure 2. Gain in the
output amplifier amplifies the VCA noise. This will directly in~
crease the equivalent VCA noise floor by the amplifier gain. A
compromise within these constraints will determine the best
tradeoff between SSM-2013 current gain and the amplifiergain.
Figure 3 shows how output noise increases as current gain
increases.

,,

40

..
30

~

i

~
i

CONTROL PIN EXPO
The control port EXPO (pin 9) is a high impedance input with an
exponential control sensitivity of -1 dB/l OmV or -10m V/dB. The
overall control range is +40dB to -95dB. This pin is easily adaptable to any control voltage range by selecting the R, and R2 di-

~

~~
"-

"

-400 -300 -200 -100

~

10

100

200

300

40D

-10

-20

'-

-30

'-

-40

'-

VEXPO(mV)

-GO
-70

i'
!!

~z

I

FIGURE 4: Circuit Gain/Attenuation vs. VEXPO

r\

-GO

....
-100

-110

-120
+40

\

1\,
r\

,otcn

2.2kn

,otcn

4.7k.O:

V,

V.

'\

"- .....

+20
0
-2D
-40
-60
CURRENT GAlN/ATTENUATION (dB)
NOISE BANDWIDTH (20Hz. 20kHz)

Vn

'0""
/

......-,f\j'V'-~--o TO PIN.

'""

-80

(REFERRED TO &OOJ1AP1I INPUT SIGNAL
12dB OF HEADROOM)

FIGURE 3

vider appropriately. Note the negative control relationship where
positive voltages at pin 9 result in signal attenuation whereas
negative voltages yield gain. The control pin is accurate to within
±1.5dB over a ±36dB range.
The transfer characteristics for the control pin is shown in Figure
4. Note the dotted line showing an optional improvement in gain
accuracy. To achieve this improved transfer characteristic, refer
to the circuit of Figure 5. As the recommended circuit for control
summing applications, this technique offers a significant improvement in linearity over a wider control voltage range.
The control port sensitivity has a -3300ppm/oC temperature
coefficient. To compensate for this drift, use a +3300ppm/oC
tempsistor* in place of R, shown in Figure 1.

MUTING FUNCTION
The mute circuit turns the device on or off independent of the
control pin EXPO. Muting is activated when the MUTE (pin 10) is
raised above 3.0V and is compatible up to 15V. Muting is off when
MUTE is below 1.0V.

+1OdBN

(INPUT CONTROL SENSITIVITY)

FIGURE 5: Control Summer with Improved Linearity over
Wider Control Range

A selectable MUTE CAP connected between pin12 and ground
determines the controlled turn onlturn off rate. The recommended
11lF mute cap and internal 1aka impedance gives a lams time
constant. This transition timing is considered quick without being
too abrupt or "poppy."
To disable the muting function, simply ground pin 10.

APPLICATIONS INFORMATION
OUTPUT AMPLIFIER
Note the importance of including COUT in parallel with ROUT to
ensure stability under all signal and output loading conditions. A
corner frequency of 300kHz for the ROUT' COUT combination is
sufficient, but a lower frequency may also be chosen to limit noise
output the audio band. This, however will result in a slower
transient response.

* ReO Components, Inc. Part Number LPl/4, 3301 Bedford Street, Manchester, NH U.S.A., (603) 669-0054, Telex 943512

7-54 SPECIAL FUNCTION AUDIO PRODUCTS

REV. A

SSM·2013
CONTROL FEEDTHROUGH TRIMMING
Control feedthrough is defined as the portion of the control signal fed to the output in the absence of an input signal. A single
shunt resistor across pins 2 and 6 will reduce both control
feedthrough and noise (see Figure 6). Values from 3.31<0 to 5.41<0
offer an improvement in control feedthrough from 20dB to 10dB,
respectively.

COMPENSATION
To compensate, connect a 50pF capacitor from pin 11 (COMP)
to GNO as shown in the typical connection.
ON·BOARD REFERENCE
An on-chip zener diode helps establish the -8V available at the
SUB output (pin 8). This is a general purpose reference that can
be used to introduce OC offsets.

fM""
5.4kn

6

FIGURE6

FIGURE 7

This trim will tradeoff an increase in THO by roughly 3 to 5 times.
THO increases slightly more using a lower resistor value. With
3.3kQ, the worst case is about 0.4% over gain and attenuation.
By comparison, THO ranges from 0.05% to 0.1 % with no shunt
resistor.
TRIMMING DISTORTION
The SSM-2013 has very good distortion, offset and control
feedthrough at unity current gain. For applications requiring over
10dB to 20dB gain, trimming allows the best overall distortion
versus gain.

BREADBOARDING THE SSM·2013
A typical connection identical to Figure 1 and redrawn for breadboarding purposes is shown in Figure 8.
MEASURING NOISE
When measuring audio noise in the SSM-2013, bandwidth should
be limited to 20kHz to 30kHz. This is due to the presence of
broadband noise which is caused by a zero at 600kHz. The zero
results from the 5000pF-47Q network at the input. Beyond 30kHz,
the noise floor increases at approximately 6dB per octave from
45kHz to 600kHz where it rolls off.

Distortion Trim Procedure for High Gain Applications:
1. Apply voltage at pin 9 corresponding to maximum current gain.
2. Set input level so output is just below clipping.
3. Adjust trimming per Figure 7 until distortion is at a minimum.

SOOOpF

'50pF±'O%

-11-----,
AIN

47n

elM

"'-..,fVV'---l f-o SIG IN

15kU

v.
'3
ROUT

1-"'2'--_-,+
SSM-2013

11

*'.F

YUUTE ~ +1V (VeA "ON")
VYUTE > +3.0V (VeA "OFF")

P'O~~----------------oMmc

OUT

v-

FIGURE 8: Typical Connection for Breadboarding

REV. A

SPECIAL FUNCTION AUDIO PRODUCTS 7-55

II

7-56 SPECIAL FUNCTION AUDIO PRODUCTS

Voltage-Controlled
Amplifier/OVCE
SSM-2014* I

fIIIIIII ANALOG

WDEVICES

FEATURES

DESCRIPTION

• Wide Dynamic Range ............................ 116dB (Class AB)
.............................. 104dB (Class A)
• 12MHz Effective Gain·Bandwidth Product
• 1OOdB Open·Loop Gain
• 0.01% THO Class A (Any Gain/Signal) @ = 1OdBVINIOUT
• Minimum External Component Count
• No Trimming in Many Applications
• Low Cost

The SSM-2014 is an extremely flexible VCA building block that
rivals the best monolithic VCAs while approaching the performance of modular devices. This versatile device acts as a VCA or
OVCE (Operational Voltage-Controlled Element) and has inputs
and outputs that can operate either in the current or voltage
domain. To optimize performance at different signal levels, the
SSM-2014 features programmable Class A or Class AB operation. This feature, along with the many configurations possible
for operation make the SSM-2014 a unique and powerful signal
processing tool. The device can be configured as a VCA or VCP
(Voltage-Controlled Panner) and can replace a standard VCA
and two or more operational amplifiers. Operation as a standard
VCA provides up to SOdB gain and excellent specifications at
any signal level.

Not recommended for new designs; replace with SSM-201S.

ABSOLUTE MAXIMUM RATINGS
Supply Voltage ..................................................... 36V or ±ISV
Junction Temperature ....... ,.......................................... + IS0°C
Operating Temperature Range ....................... -10°C to +SsoC
Storage Temperature Range ......................... -6SoC to +IS0°C
Maximum Current Into Any Pin ....................................... 10mA
Lead Temperature Range (Soldering, 60 sec) ............ +300°C

The SSM·2014 is not recommended for new designs or pur·
chases - the SSM·2018 Is a pin·compatible upgrade at a
lower cost.

BLOCK DIAGRAM
ORDERING INFORMATION

PACKAGE
16-PIN

OPERATING
TEMPERATURE
RANGE

SSM2014P

-10°C to +55°e

PLASTIC

I

PIN CONNECTIONS

16·PIN
PLASTIC DIP
(P·Suffix)

• Protected by U.S. Patents: 4,471,320 and 4, 560, 947. Other Patents pending. Mask work protected under the Semiconductor Chip Protection Act of 1983.

REV. A

SPECIAL FUNCTION AUDIO PRODUCTS 7-57

SSM-2014
ELECTRICAL CHARACTERISTICS at Vs = ±15V and TA = ±25°C. unless otherwise specified:
SSM-2014
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

nA

INPUT AMPLIFIER
100

300

Input Offset Current

15

30

nA

Inpul Offset Voltage

0.5

2

mV

Bias Current

Input Impedance
Equivalent Input Noise

0.5
@1kHz

Common-Mode Range
Open-Loop Gain

75

Effective Gain BW Producl

VCA Configuration
VCP Configuration

Slew Rate

VCA Configuration

MQ
18

nVi.,!'RZ

+13,-13

V

100

VimV

12

MHz

.5

Vi~s

6

Supply Current - Positive

7.5

Supply Current - Negative

9

mA

10

12

mA

10

20

mV

OUTPUT AMPLIFIERS
Offset Voltage
Minimum Load Aesistor

For Full Output Swing

10

Output Voltage Swing
Noise Aesidual

20kHz Bandwidth

kQ

9
±13.5

V

8

~V

CONTAOL PORT
Bias Current

150

300

Gain Constant

Aatio of Oulputs

Gain Constant
Temperature Coefficienl
Gain Linearity
COnlrol Feedthrough (Trimmed)
Class A
ClassAB
Intermediate

100Hz Sine Wave Applied
to Control Port Causing
-30dB to +20dB of Gain

Conlral Feedthrough (Untrimmed)
Class A
Class AB (Note 1)
Intermediate (Note 1)

100Hz Sine Wave Applied
to Control Port Causing
-30dB to +20dB of Gain

Off Isolation

@1kHz

Channel Specifications
Noise - Class A (Note 2)
Noise - Class AB (Note 2)
Noise - Intermediate (Note 2)
THO - A@Av=OdB (Note 3)
THO - A @Ay=±20dB (Note 3)
THO - AB@Av=OdB(Note3)
THO - AB @Ay=±20dB (Note 3)
THO - Intermediate@ Av = OdB (Note 3)
THO - Intermediate@ Ay = ±20dB (Note 3)

nA
MQ

Input Impedance

AplN 12 = 33kQ, 20kHz BW
AplN 12 = 330kQ, 20kHz BW
AplN 12 = 43kQ, 20kHz BW
RplN 12 = 33kn

AplN 12 = 33kQ
AplN 12 = 330kQ
AplN 12 ;' 330kQ
AplN 12 = 43kQ
AplN 12 = 43kQ

-30

mV/dB

-3300

ppmf'C

0.5

%

2
0.5

mV

25
5
15
100

75
15
45

105

-85
-95
-88
0.005
0.02
0.02
0.06
0.01
0.03

mV

dB

-81
-92
-85
0.02
0.04
0.05
0.12
0.03
0.06

dBV
dBV
dBV

%
%
%
%
%
%

NOTES:
1. Symmetry trim only.
2. Parameter sample lot tested to maximum limits
3. V,N andior VOUT = + 1OdBV. Specifications may be subjectto change without
notice.

7-58 SPECIAL FUNCTION AUDIO PRODUCTS

REV. A

Low Noise Microphone
Preamplifier
SSM-2015 I

1IIIIIIII ANALOG

WDEVICES

FEATURES
•
•
•
•
•
•
•
•

The SSM-2015 also offers high slew rate of about 8V/~s and full
DC coupling without any crossover distortion.

Ultra Low Voltage Noise .................................•. 1.3nV/v'Hz
Wide Bandwidth .................................... 700kHz @ G 100
High Slew Rate ........................................................... 8V/~s
Very Low Harmonic Distortion ...•..•..... 0.007%@G = 100
ExcelientCMR ........................................................... 100dB
True Differential "Instrumentation" Type Inputs
Programmable Input Stage Optimizes en vs R'N
LowCost

=

This device is packaged in a 14-pin epoxy DIP and is guaranteed over the operating temperature range of -10°C to +55°C.

PIN CONNECTION
COMP1 1

ORDERING INFORMATION

14-PIN EPOXY DIP
(P-Suffix)

OPERATING TEMPERATURE
RANGE
COMP2 6

SSM-2015P

-10°Cto +55°C

Storage Temperature

-55°C to + 125'C

COMP3 7

GENERAL DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

The SSM-2015 is an ultra-low noise audio preamplifier particularly suited to microphone preamplification. Gains from 10 to over
2000 can be selected with wide bandwidth and low distortion over
the full gain range.

Supply Voltage ................................................................. ±18V
Operating Temperature Range ....................... -10°C to +55°C
Junction Temperature .................................................... +150C
Storage Temperature .................................... -55°C to + 125°C
Lead Temperature Range (Soldering, 60 sec) ............ +300°C

The very low voltage noise performance (1.3nV!v'HZi of the SSM2015 is enhanced by a programmable input stage which allows
overall noise to be optimized for source impedances of up to 4kQ.

PACKAGE TYPE

The SSM-2015's true differential inputs with high common-mode
rejection provide easy interfacing to flotation transducers such
as balanced microphone outputs, as well as single ended
devices.

1.

e'A is specmed for worst case mounting conditions, Le., ajA isspecifiedfordevice
irl socket for P-DIP package.

BLOCK DIAGRAM
+v

COMP1

4""

4""

14
BIAS

REV. B

-v

SPECIAL FUNCTION AUDIO PRODUCTS 7-59

SSM·2015
ELECTRICAL CHARACTERISTICS at Vs = ±15V, TA = 25°C, RSIAS = 33k.Q, unless otherwise noted;
SSM-2015
PARAMETER

Total Harmonic Distortion
(Note 1)

Input Aeferred
Voltage Noise
(Note 1)

SYMBOL

CONDITIONS

THO

V~ur = 7V AMS, AL • 10k1l
= 1000
f= 1kHz
f=10kll
G.l00
f=.lkHz
f.l0kHz
GelD
f= 1kHz
f.l0kHz

En

Input Current Noise
(Note 1)

In

Error From Gain Equation

~G

Input Offset Voltage

Vos

Input Bias Current

I.

Input Offset Current

los

Common-Mode
Aejection Aatio

CMAA

Power Supply
Aejection Aatio

PSAA

Common-Mode
Voltage Aange

CMVA

Common-Mode
Input Impedance

A 'NCM

MAX

0.007
0.015

0.01
0.02

0.007
0.007

0,01
0,01

0.01
0.01

0.015
0.015

UNITS

%

0.2
0.3
1.1

0.3
0.5
1.7

0.28
0.41
1.1

0.45
0.65
1.7

20kHz Bandwidth
A.,AS = 33k1l
A.,AS • 68k1l
A. ,AS = 150kll

250
200
130

380
300
200

pAAMS

A, = A. = 10k1l
G= 1000
G= 100
G=10

0.1
0.1
0.2

0.3
0.3
0.8

dB

A, = A. = 10k1l
G= 1000
G= 100
G=10

0.25
0.3
3

2
7
70

mV

VCM=OV
A.,AS = 33k1l
AalAs = 150kll

4.5
1

15
4

~

VCM=OV
A.,AS = 33k1l
AalAs = 150k1l

0.5
0.15

2.5
0.7

~A

A, = A. =10kll
G= 1000
G=100
G.l0

90
70
60

Vs =±12to±17V
±4

Output Voltage Swing

Vo

AL = 2k1l

lOUT

Source
Sink

GBW

G= 1000
G= 100
G= 10

100
95
75

dB

100

dB

±5.5

V

50

Mil

Mil

±10.5

±12.5

V

15

25
14

mA

150
700
1000

kHz

8

Slew Aate

SA

8

Supply Current

ISY

12

NOTES:
1. Parameter is sample tested to maximum limits.
2. Output is protected from short circuits to ground or either supply.

7-60 SPECIAL FUNCTION AUDIO PRODUCTS

~VAMS

0.5
5
20

G= 1000
G.l00
G= 10

A'N

-adB Bandwidth

TYP

Inputs Shorted to GND
20kHz Bandwidth
A.,AS • 33K1l
G= 1000
G= 100
G=10
A.,AS = 150kll
G= 1000
G=loo
G=10

Differential-Mode
Input Impedance

Output Current
(Note 2)

MIN

VI~s

16

mA

Specifications subject to change; consult latest data sheet.

REV. B

SSM-2015

10k0: 1%

C,

r

C,

1 1~14
!

N.C.

+NULL

3 OUT
4 -v

..!!...

"~ t

+IN 12

SSM-2015
+R.

+15V

---. R.

200pF

.1L.

-R•

5 +v

+INPUT

-IN 9

8 COMP2

Fib

7 COMP3

-NULL

-INPUT

.!..
R,
tOka 1'%

fO.1 I1F

R....

.".

VOLTAGEGAIN=

0

~ .3.5
R.

-15V

FIGURE 1: Typical Application

APPLICATIONS INFORMATION
PRINCIPLE OF OPERATION
Figure 1 shows a typical application for the SSM-201S. This
device operates as a true differential amplifier with feedback
returned directly to the emitters of the input stage transistors by
R,. This system produces both optimum noise and commonmode rejection while retaining a very high input impedance at
both input terminals. An internal feedback loop maintains the input
stage current at a value controlled by an external resistor (R aIAs )
from pin 14 to V-. This provides a programmability function which
allows noise to be optimized for source impedances of up to 4kO.

TABLE 1: RG Values for Commonly Used Gains

7

RG=R,+A2
G - 3.S
--=----".--=~

GAIN

RG

ERROR

10

3kO

+0.14dB

50

430(,)

+0.002dB

100

200(,)

+0.3dB

SOO

390

+0.2SdB

1000

200

+0.03dB

GAIN SETTING
The nominal gain of the SSM-2015 is given by:
G=R, +A2 +R, +A2 + 1
RG
SkO
or
G = 20kO + 3.S ForR" A2 = 10kO

RG

R, and R2 should be equal to 1OkO for best results (see Figure
1). It is vital that good quality resistors be used in the gain setting
network, since low quality types (notably carbon composition)
can generate significant amounts of distortion and, under some
conditions, low frequency noise. The SSM-2015 will function at
gains down to 3.S, butthe best performance is obtained at gains
above 1O. Table 1 gives RG values for most commonly used gains.

REV. B

FREQUENCY COMPENSATION
Referring to Figure 1, C3 (50pF) provides compensation for the
input stage current regulator, while C, and C2 compensate the
overall amplifier. The latter two depend on the value of RalAs
chosen. Table 2 shows the recommended values for C, and C2
at various RalAs levels. These values are valid for all gain settings.

TABLE 2: Recommended Compensation Values

C1
27kO-47kO

1SpF

1SpF

47kO-6SkO

1SpF

10pF

6SkO-1S0kO

30pF

5pF

SPECIAL FUNCTION AUDIO PRODUCTS 7-61

SSM-2015
The SSM-2015 has a bandwidth of at least 70kHz under worst
case conditions (G = 1000, RBIAS = 150kn) and considerably
greater at higher set currents and lower gains. This excellent
performance is supplemented by a highly symmetric slew rate
for optimum large signal audio performance. The SSM-2015
provides stable operation with load capacitances of up to 150pF;
larger capacitances should be decoupled with a 1oon resistor in
series with the output (R, in Figure 1 should remain connected
to pin 3).

200

.!LANCED

/

I~PZ

V

~NGLE

... ...

10
100

/'~

ENDED INPUT

,.

'.5.

SOURCE RESISTANCE (0.)

NOISE
The programmability ofthe SSM-2015 provides close to optimum
performance for source impedances of up to 4kn, and is within
1dB ofthe theoretical minimum value between 500n and 2.5kn.
Figure 2 shows the recommended bias resistor (R BIAS ) versus
source impedance, for balanced or single-ended inputs.

INPUTS
Although the SSM-2015 inputs are fully floating, care must be
exercised to ensure that both inputs have a DC bias connection
capable of maintaining them within the input common-mode
range. The usual method of achieving this is to ground one side
of the transducer as in Figure 3(a), but an alternative way is to
float the transducer and use two resistors to set the bias point as
in Figure 3(b). The value of these resistors can be up to 10kn,
but they should be kept as small as possible to limit commonmode noise. Noise generated in the resistors themselves is
negligible since it is attenuated by the transducer impedance.
Balanced transducers give the best noise immunity, and interface directly as in Figure 3(c).
TRIMMING
The gain of the SSM-2015 can be easily trimmed by adjustment
of RG . However, two further trims may be desirable: Offset Voltage and Common-mode Rejection, although the SSM-2015
provides excellent untrimmed performance in both respects.

.

,

FIGURE 2: Optimum RslAS VS. Source Resistance

13
13
12

1-"-,-'-F=-'-'=,,~
os....."

- -

l

SSM-2015

11

;?-

11

200pF

TRANSDUCER

10

TRANSDUCER

10

(NONINVERTlNG)

-

-

l

.,!;,
13

(e)

(a)
12
88M-2015

11

200pF

TRANSDUCER

10

FIGURE 3: Three Ways of Interfacing Transducers for High Noise Immunity
(a) Single Ended (b) Pseudo Differential (c) True Differential

7-62 SPECIAL FUNCTION AUDIO PRODUCTS

REV. B

SSM-2015
The oflset trim can also be used to null out the gain control
feedthrough. The output offset at low gains is determined by
matching of the feedback resistors while at high gains it is determined by the matching 01 the input resistors. lIthe gain setting is
changed rapidly, the output shift can cause an (audible) click or
thump. To reduce or eliminate this, the offset at high gains is
adjusted to be equal to the offset at low gains.

ft,
10""

14
13
12

SSll-2015

.v

11

R.

TABLE 3: Recommended Values for the Offset Voltage Trim

VR,

RB1AS

10

FIGURE 4: Trimming the SSM-2015

Figure 4 shows the trimming method for both parameters.
VR, is the CMR trim and should be adjusted for minimum output
with an 8Vp-pamplitude 60Hz Sine Wave common to both inputs.
VR2 is the offset voltage trim, and should be selected from Table
3. The offset trim should follow the CMR trim, since there is a
small (non-reciprocal) interaction.

27kn·47kn

47kn· 68kn

68kn • 150kn

VR2 ,
G=10

500kn

250kn

250kn

VR2 ,
G = 100

500kn

100kn

100kn

VR2 ,
G = 1000

250kn

100kn

50kn

PHANTOM POWER
A recommended circuit lor phantom microphone powering is
shown in Figure 5. Z, through Z4 provide transient overvoltage
protection for the SSM-2015 whenever microphones are plugged
in and out.

The offset trim can also be used to null out the gain control

13

c,
~_--_-_----~II"-,,--_o.INPIIT

S5M-2015

R,

R,

100<>

6.8k01%

.......-_o-INPUT

I"-'--......:--------~rf.±2 1 -Z 4 S.6V 400mW

C 1 - C2 47}1F SOY TANTALUM

FIGURE 5: SSM-2015 with Phantom Power

REV. B

SPECIAL FUNCTION AUDIO PRODUCTS 7-63

I

7-64 SPECIAL FUNCTION AUDIO PRODUCTS

Ultra Low Noise Differential
Audio Preamplifier
SSM-2016 I

r.ANALOG
WDEVICES
FEATURES

GENERAL DESCRIPTION

• Ultra Low Voltage Noise .•••••...••..•••••.••.••.. 800pV/$zTyp
• High Slew Rate .................................................. 10VIllS Typ
• Very Low
Harmonic Distortion ••••••••••••••••••• @ G = 1000 0.009% Typ
• Wide Bandwidth •..••••.••••••••••.•••.••• @ G = 1000 650kHz Typ
• VeryWlde
Supply Voltage Range .................................... ±9V to ±36V
• High Output Drive capability ••.•.••••.••••••...••.•.•• ±40mA Min
• High Common-Mode Rejection ........................ 100dB Typ
• LowCost

The SSM-2016 is an ultra low noise, low distortion differential
audio preamplifier. The input referred noise of the SSM-2016 is
about 800pV/..;'Hz which will result in a noise figure of 1dB when
operated with a 1500 source impedance. This ensures that a
large number of inputs can be paralleled without seriously degrading the signal-to-noise ratio. In addition, this device provides
exceptionally low harmonic distortion of only 0.009%(G = 1000,
f = 1kHz) Typ.

APPLICATIONS
•
•
•
•

Low Noise High-Gain Microphone Preamplifier
Bus Summing Amplifier
Differential Line Receiver
Low Noise Instrumentation Amplifier

ORDERING INFORMATION
PACKAGE
PLASTIC

16-PIN

Fabricated on a high voltage process, the SSM-2016 is capable
of operating from a wide supply voltage range of ±9V to ±36V. A
copper lead- frame DIP package is used to permit 1.5W of dissipation when driving heavy loads or operating from elevated
supplies.
Continued

PIN CONNECTIONS

16-PIN PLASTIC DIP
(P-Suffix)

OPERATING
TEMPERATURE
RANGE
-25°C to +55°C

SSM2016P

BLOCK DIAGRAM
9
COMP2

11

~

v+

______~~~~__________4-__~.D~~~.

NULL'
Your

NULL 2

-IN

+IN

oR.

-Ro
'2

A· our

v-

The SSM-2016 has been granted mask work protection under the Semiconductor Chip Protection Act of 1983.

REV. A

SPECIAL FUNCTION AUDIO PRODUCTS 7-65

SSM·2016
GENERAL D~SCRIPTION Continued .
The SSM-2016 can source or sink a minimum of 40mA allowing
a jack-field to be driven directly.

At low gains. the SSM-2016 offers a bandwidth of about 1MHz
and 650kHz at 60dS of gain. Slew rate is typically 10VIllS at all
gains ..
The SSM-2016 is packaged in a 16-pin epoxy DIP and performance and characteristics are guaranteed over the operating
temperature range of -25°C to +55°C.

ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage ...................................................;............. ±38V
Recommended Supply
Voltage Range ...................................................... ±9V to ±36V
ELECTRICAL CHARACTERISTICS at Vs =±18V. R,

Current Into Any Pin
(Except Pins 2. 11. and 15) ............................................. 40mA
Lead Temperature (Soldering. 60 sec) .......................... 300°C
Storage Temperature .................................... -65°C to +150°C
Package Dissipation ........................................................... 2W
Short-Circuit Duration (Note 1) .................................. Indefinite
Operating Temperature Range .......................,.-25°C to 55°C
PACKAGE TYPE

UNITS

alA (Note 2)

t .6-Pin Plastic DIP (P)

76

33

'CIW

.NOTES:
1. Short-circuit duration is indelinite, provided dissipation limit Is not exceeded.
2. ajA isspec~led lorworstcase mounting condltions,l.e., ajA is specified lor device
in socket lor P-DIP package.

= R2 =5kn. R3 =R4 =2kn. TA =+25°C. unless otherwise noted.
SSM-2016

PARAMETER

Total Harmonic Distortion

SYMBOL

THD

MIN

TYP

MAX

Vo= 10VRMS ' RL =2kO
G = 1000
1=lkHz
I. 10kHz

0.009
0.015

0.015
0.02

G=100
1=lkHz
1= 10kHz

0.003
0.005

0.005
0.007.

G=10
1= 1kHz
1= 10kHz

0.002
0.003

0.003
0.005

Vo -10VRMS ' RL = 6000, Vs =±20V
G .1000
1=lkHz
1= 10kHz

0.025
0.06

0.04
0.09

G=100
1=lkHz
I. 10kHz

0.008
0.02

0.015
0.04

G.l0
1= 1kHz
l.l0kHz

0.005
0.008

0.008
0.015

CONDITIONS

UNITS

%

en

20kHz Bandwidth
G= 1000
G=100
G.l0

0.11
0.20
0.80

0.16
0.30
1.2

..V RMS

Input Current Noise (Note 1)

In

20 kHz Bandwidth

350

550

pAlRI!~

Slew Rate

SR

Input Relerred Voltage Noise
(Note 1)

V/..s

10

GBW

G= 1000
G,;100

0.55
1

Input Offset Voltage

Vos

G .1000
G=100
G=10

0.5
1.5
5

Input Bias Current

I.

VCM=OV

9

25

Input Offset Current

los

VCM=OV

1.5

5.0

Common-Mode Rejection Ratio

CMRR

G=1000
G.l00
G=10

Power Supply Rejection Ratio

PSRR

Vs =±9Vto±36V

Common-Mode Voltage Range

CMVR

-3dB Bandwidth (Note 2)

7-66 SPECIAL FUNCTION AUDIO PRODUCTS

MHz
2.5
10
8

mV

J1A
J1A

100
95
75

dB

90

100

dB

±7

±10

V

96
80.5
64

REV. A

SSM-2016
ELECTRICAL CHARACTERISTICS at Vs =±18V, R, = R2 = 5kQ, R3 = R4 = 2kQ, TA = +25°C, unless otherwise noted.
Continued
SSM-2016
SYMBOL

PARAMETER
Common-Mode Input Impedance

CONDITIONS

MIN

R'NEM
G = 1000
G= 100
G= 10

Differential-Mode
Input Impedance

R'N

Output Vo~age Swing (Note 1)

Vo

RL = 2k.Q
RL = 600n, Vs = ±20V

Output Current (Note 3)

lOUT

Supply Current

ISY

MAX

UNITS

20

Mn

0.3
3

Mn

10
±15
±15

±17
±17

V

Source
Sink

40
40

70
70

mA

VCM=OV

10

Error From Gain Equation
NOTES:
1. Sample tested.
2. Bandwidth will be slew-rate limited at high output levels.
3. Output is protected from short circuits to ground or either supply .

•

TYP

12

16

mA

0.1

0.3

dB

Specifications subject to change; consult latest data sheet.

COMP2

------------------------------------'0

~------~--~~------------+_~--~--------------~--------_QCOMP'

NULL 10-''---;-I------I-----------......----t---------;

120pF

1S

;>--T-~-----Q~~

NULL20-''---l-l------I-----------+---......--------;

C.

50pF

470pP

+~o-'~~-I------I-----------+----+_-------

A1_

*'

L~~:_~_-_-_-_-_-_-_--_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-.-_-_-_-_-_-_._-_-_-_-_-_-_~--~~~~
'47OpF CAPACITOR SHOULD BE MOUNTED CLOSE TO TIE PACKAGE

0.1.F

FIGURE 1: Typical Preamplifier Amplification

APPLICATIONS INFORMATION
PRINCIPLE OF OPERATION
The SSM-2016 operates as a true differential amplifier with
feedback returned directly to the emitters of the input stage transistors by R, (See Figure 1). The differential pair is fed by a
current source at the collectors and the required emitter current

REV. A

is supplied by a nulling (servo) amplifier through the external
resistors R3 and R4 (Figure 1). This system produces both optimum noise and common-mode rejection while retaining a very
high input impedance. The internal "servo" amplifier is used to
control the input stage current independently of common-mode
voltage and its output is accessible via pin 12.

SPECIAL FUNCTION AUDIO PRODUCTS 7-67

•

GAIN SETTING
The nominal gain of the SSM-2016 is given by:

Rl + R2
Rg

R'1 + R2
R3+ R4

G= - - - + ---+1
or
G=

10kn
R
+ 3.5

For Rl = R2 = 5kO, R3 = R4 = 2kn

9

Rl and R2 should be equal to 5kn for best results. It is vital that
good quality resistors be used in the gain setting network, since
low quality types (notably carbon composition) can generate
significant amounts of distortion and, under some conditions,low
frequency noise.
The SSM-2016 is capable of operating at gains down to 3.5 at
full performance. Gain range can be extended further by increasing R3 arid R4 in Figure 1, but at the penalty of reduced
common-mode input range. Gains below 2.5 are not practical
unless the negative supply voltage is increased.

TOTAL ttARMONIC DISTORTION
Figures 2 - 5 show the distortion behavior of SSM-2016. All
measurements were taken at a 1OVRMS output to ensure a true
''worst case" condition. No crossover distortion is observed at
lower ouput levels. At 20dBof gain (Figure 2) total harmonic
distortion (plus noise) is well below 0.01% at all audio frequencies. At 40dB of gain (Figure 3) some loading effects are evident,
especially at higher frequencies, but the overall TH,D is still very
low. The measurements at 60dB of gain (Figure 4) are a little
misleading because the noise floor is at an equivalent level of
0.0085% at this gain. In fact, the real distortion components are
not greatly increased from the 40dB case.
Figure 5 shows the intermodulation distortion performance of the
SSM-2016. A basic SMPTE type test was performed with the main
generator swept from 2.5kHz to 20kHz. The 60dB reading is once
more mostly noise.

OVERALL DISTORTION
AT +2OdB GAIN

Note that tolerance of Rl - R4 directly affects the gain error and
that good matching between Rl - R4 is essential to prevent
degradation of the common-mode rejection performance.
The SSM-2016 provides internal 1kO resistors to replace R3 and
R4 in applications where distortion is not too critical.
FREQUENCY COMPENSATION
The SSM-2016's internal ·servo" amplifier is compensated by
C3 , while C1 and C2 (see Figure 1) compensate the overall amplifier. The values shown maintain a very wide bandwidth with a
good symmetrical slew rate. If desired, the bandwidth can be
reduced by increasing the value of C1 •
NOISE PERFORMANCE
The SSM-2016's input referred noise is 0.11I1VRMS (20kHz
bandwidth) at 60dB of gain, O.2I1VRMS at 4OdB, and 0.811VRMS at
20dB. The apparent increase at low gains is due to noise incurred
in the feedback resistors and second stage becoming dominant.
This noise is actually present at all times but becomes masked
by input stage noise as the gain is increased.
The SSM-2016 is optimized for source impedances of 1kn or
less and under these conditions, the noise performance is equal
to the best discrete component designs. Considering that a
·standard" microphone with impedance of 1500 generates
1.6nV/-/HZ of thermal noise, the SSM-2016's 800pV/-/HZ of
voltage noise or the corresponding noise figure of typically 1dB
make the device virtually transparent to the user.
In applications where higher source impedances than 1kn are
desired, the SSM-2015 preamplifier is recommended.
Another source of noise degradation is the chip's total power
dissipation, since any increase in temperature will increase the
noise. This effect is more pronounced at higher gains. As a result, the SSM-2016 uses a copper lead-frame package which
greatly helps the power dissipation and the noise performance.
The best noise performance of the SSM-2016 can be achieved
at low supply voltages while driving light loads.

7-68 SPECIAL FUNCTION AUDIO PRODUCTS

0.1

~
z

I

~~IJl...o

0.010

"L=2kO

liLli i

O 1I
•

0.001
20

1.

100

10k

20k

FREQUENCY (Hz)

FIGURE 2

OVERALL DISTORTION
AT +40dB GAIN

O,'~~~
~

~D;

I

Ii

.!:g-

RL •

RL =2kU

0 010

Rl = tOka

15

.

.

.....

"

0.001
20

100

"

10k

2011.

FREQUENCV (Hz)

FIGURE 3

REV. A

SSM-2016
OVERALL DISTORTION
AT +SOdB GAIN

TYPICALIMD
PERFORMANCE

0·'111111~
R L " 600Q

°m-nllltm
~

OI
O.

ffim

RL~10kQ

0.1

60dB GAIN

;:

0.010

0

40dB GAIN

!

20dB GAIN

0.001
.0005
2k

20

100

10k

20k

FREQUENCY (Hz)

lk
FREQUENCY (Hz)

FIGURE 4
DRIVE CAPABILITY
Fabricated on a high voltage process, the SSM-201S is capable
of operating from ±9V to ±36V supplies. In addition, the powerful
output stage is designed to drive a jack-field directly. The SSM2016 is capable of driving a 1OV RMS sine wave into SOOO load
using ±18V supplies. However, ±20V or greater supplies are
recommended to give a more comfortable headroom. A copper
lead-frame DIP package is used to permit 1.5W of dissipation
when driving heavy loads or operating from elevated supplies.

FIGURE 5

16
15

,.
I

I
I

470pF 5

SS~2016

12
11
10

(NONINVERTlNG)

.;"

INPUTS
The SSM-2016 offers protection diodes across the base-emitter
junctions of the input transistors. These prevent accidental
avalanche breakdown which could seriously degrade noise
performance. Additional clamp diodes are also provided to prevent the inputs from being forced too far beyond the supplies.
Although the SSM-2016's inputs are fully floating, care must be
exercised to ensure that both inputs have a DC bias connection
capable of maintaining them within the input common-mode
range. The usual method of achieving this is to ground one side
of the transducer as in Figure Sa, but an alternative way is to float
the transducer and use two resistors to set the bias point as in
figure Sb. The value of these resistors can be up to 10kO, but
they should be kept as small as possible to limit common-mode
pickup. Noise contribution by resistors themselves is negligible
since it is attenuated by the transducer's impedance. Balanced
transducers give the best noise immunity, and interface directly
as in Figure Sc.

13

-;;.TRANSDUCER

a) SINGLE ENDED

R

16
15

,.
13

410pF

TRANSDUCER

5 SSM-2016 12
11
10

b) PSEUDO DIFFERENTIAL

16

,.

15

TRANSDUCER

>-------,

470pF

13
5 SSM-2016 12
11
10

9

c) TRUE DIFFERENTIAL

FIGURE 6: Three Ways of Interfacing Transducers for HighNoise Immunity

REV. A

SPECIAL FUNCTION AUDIO PRODUCTS 7-69

•

SSM-2016,

15
+48V

c,

14

R. + I N P U T o - - + - - - ' i I I - - - - _ - - _ - _ - - - \
1001l

R.

13

6.Bk01%

SSII-2016
200pF 5

+1

11

471 Vs = ±15 V; RL = 5 kn; TA = +25°C

Figure 2. Typical THD+Noise* at G = 2, 10, 100, 1000;
Va = 10 VRMS' Vs = ±1B V, RL = 5 kn; TA = +25°C

*80 kHz low-pass filtet used for Figures 1-2.

REV. A

SPECIAL FUNCTION AUDIO PRODUCTS 7-75

SSM~2017

~ 1000

III I I I
TA = +2S·C
VS± 1SV
G = 1000

200

~

TA= +25·C

c
I

~

100

I

I

r"'-,

w

....

Cl

10

~w

W
U
Z

1= 1kHz

I?i
w

...

' - l-

c:J

!

I = 10kHz

lk

10k

I 25
w
c:J

~20
g
~

I;-

VS.

10

~

!:i
o

~

>

>

i

o

100

1k
10k
100k
FREQUENCY - Hz

10

100

lk

10k

Figure 6. Maximum Output Swing
Frequency

120

.15

=:z

/

.10

I-

:;)

±5

/
±5

/

V

/

...III

80

G =100
II I I

iii

80

~=110

40

G=1

I

:1:15

o

GI=\

Figure 9. Output Voltage Range
vs. Supply Voltage

10

100

lk

Figure 10. CMRR

7-76 SPECIAL FUNCTION AUDIO PRODUCTS

VS.

A~sl= 100mV

20

10k

tOOk

FREQUENCY - Hz

SUPPLYVOLTAGE-V

rr-

GI=~O

AVCM .100mV
TA= +2S·C
Vs= ±15V

20

::1:10

GI=!~

:Ii
U

Frequency

VS.

GI=;~

100

100

/

.15

Figure 8. Input Voltage Range
Supply Voltage

120

~=11~

TA = +2S·C

c:J

.10

SUPPLY VOLTAGE - V

Figure 7. Maximum Output Voltage
VS. Load Resistance

±lIO

0

/

lOOk

LOAD RESISTANCE

VS.

!
...!;

,/

2

o

/

V

i

~

5

VS.

V

/

~ :1:10

I
1/

II

::1:15

I
W

G=1

II

8

tOM

1M

TA= +25·C

I II

w 10

\

lOOk

Figure 5. Output Impedance
Frequency

I

~~110

12

10k

FREQUENCY - Hz

I

TA = +25·C
Vs = ±15V

14

G=1

10

...I1i

lk

1000

100

Figure 4. RTI Voltage Noise Density VS. Gain

TA= +2S·C
Vs= ±1SV
RL=5kQ

~ 15

80

o

~

18

~~11!

100

GAIN

Figure 3. Voltage Noise Density
Frequency

30

120

20

FREQUENCY - Hz

>

Vs= .1SV

140

40

g
100

~A~l~.J

80

~
oJ

10

t80
180

TA = +2S·C
vs= .1SV

o
10

100

lk

10k

lOOk

FREQUENCY - Hz

Figure 11. +PSRR

VS.

Frequency

REV. A

Typical Performance Characteristics-SSM-2017
120

160

I±!J-

1~ r-~---+--~--~--+---;

G'=';'ooo-j::=

100

III

120

G=1;;-

1I
GT=Tci
_I

j::=

r--

,

80

>~

AVs= 100mV
TA= +25·C
V1=·15V

o
10

100

1k

10k

r-~---+--~--~--+---;

80 r-~---+--~--~--+---;

G=1
20

1-.:1==t==+==:i:=+'~

100 r-~---+--~--~--+---;

>:<

120
100

>:<

,

II)

80

~

20

oL-~--~--~--~~--~

0

FREQUENCY - Hz

0

25

so

75

.5

100

TEMPERATURE _·C

Figure 12. -PSRR VS. Frequency

/

60

2Of---+--+--+--t---+---J
-25

Y'

0

>-

~ r-~---+--~--~--+---;

-50

100k

--

TA = +2S·C

1~

SUPPLYVOLTAGE-V

Figure 13. V,OS VS. Temperature

Figure 14. V,OS VS. Supply Voltage

10.0
10

o

o

7.5

-10

>E-2D

,

:g-30

..........

........

~-40
-50

-eo

15

-

,

""-

"'-

10

"1,

J-2D

5.0

~
.........

.!!'

-30

..,-- r-...

-40

-70

r-

2.5

r---

- II

-so
-50

-25

0

25

50

75

:t5

100

TEMPERATURE - ·C

Figure 15. Voos VS. Temperature

:10

:15

:20

~

SUPPLY VOLTAGE-V

-""1"---

,

E

"1

,

...

4

Z

W

~

100

14

E 12

14

!zW

12

a.
a.

6

til

4

::I

75

TA= +2S·C
00(

16

II:
II:
::I
U

II:
II: 10
::I
U
8

~ 3

50

16

18
00(

25

Figure 17. Is vs. Temperature

20
~

0

TEMPERATURE - ·C

Figure 16. Voos VS. Supply Voltage

TA = +25·C

-25

~

a.

Q.

10
8

V

6
4

::I

21----1----+---+---+---+---1

til

oL-~--~--~--~~--~

.5

.10

SUPPLYVOLTAGE-V

Figure 18. Is VS. Supply Voltage

REV. A

-50

-25

0

25

50

75

100

TEMPERATURE - ·C

.10

.15

SUPPLY VOLTAGE-V

Figure 19. Isy VS. Temperature

Figure 20. Isy vs.Supply Voltage

SPECIAL FUNCTION AUDIO PRODUCTS 7-77

SSM-2017 - Applications Information
v+
+INo----{:

III

"t>

~

40 H+t-H-+t-ttt-t+t-H-+t+ll~'H-H

-----'+'H---~~--__-~~----'
Cl, C2:

47~F,

60V, TANTALUM

-lHV

ZI- Z4: 12V, l/2W

Figure 23. SSM-2017 in Phantom Powered Microphone Circuit

REV. A

SPECIAL FUNCTION AUDIO PRODUCTS 7-79

•

SSM-2017
BUS SUMMING AMPLIFIER
In addition to is use as a microphone preamplifier, the SSM2017 can be used as a very low noise summing amplifier. Such a
circuit is particularly useful when many medium impedance oUtputs are summed together to produce a high effective noise gain.

+IION~________________-4-f'

-IION__~~____________~~

The principle of the summing amplifier is to ground the SSM2017 inputs. Under these. conditions, Pins 1 and 8 are ac virtual
grounds sitting about 0.55 V below ground.
To remove the 0.55 V offset, the circuit of Figure 24 is
recommended.

A2 forms a "servo" amplifier feeding the SSM-2017's inputs.
This places Pins 1 and 8 at a true dc virtual ground. R4 in conjunction with C2 remove the voltage noise of A2 , and in fact just
about any operational amplifier will work well here since it is
removed from the signal path. If the dc offset at Pins 1 and 8 is
not too critical, then the servo loop can be replaced by the diode
biasing scheme of Figure 24. If ac coupling is used throughout,
then Pins 2 and 3 may be directly grounded.

7-80 SPECIAL FUNCTION AUDIO PRODUCTS

5~:Q

TO PINS
2AND3

+ C2
I200!!F

Figure 24. Bus Summing Amplifier

REV. A

r'IIII ANALOG

WDEVICES

Voltage-Controlled Amplifier/OVCE

SSM-20l8
FEATURES
Wide Dynamic Range
118 dB typ (Class AB)
108 dB typ (Class A)
Wide Gain Range
140 dB typ
Excellent THD and IMD Performance Over Gain.
Attenuation and Frequency
Low Control Feedthrough
1 mV typ (Class AB)
Buffered Control Port and Current and Voltage
Outputs
.
Accepts Low or High Impedance Inputs
Low External Parts Count
Low Cost

I

FUNCTIONAL DIAGRAM

APPLICATIONS
Voltage~ontrolled

Amplifiers
Mixing Console Fader Automation Systems
Compressors/Limiters
Noise Gates
Noise Reduction Systems
Telephone Line Interfaces
Automatic or Remote Volume Controllers
Voltage-Controlled Equalizers
Voltage-Controlled Panners

GENERAL DESCRIPTION
The SSM-20l8 voltage-controlled amplifier is an advanced integrated audio gain block featuring exceptional performance in
voltage-controlled amplifier, panner, equalizer, and preamplifier
functions. An extremely flexible architecture features inputs and
outputs which can be configured for differential and singleended signals, in both current and voltage modes. Also, the
control pon input and voltage outputs of the SSM-20l8 are
buffered, assuring optimal performance while significantly reducing the external pans count compared to other VCA products. The internal gain core can be programmed by the user for
Class· A, Class AB, or Intermediate operation by the selection of
an external resistor. The SSM-20l8 features excellent noise performance and exhibits negligible increase in distonion in Class
AB operation over Class A, resulting in unusually low noise and
distonion simultaneously.

REV. A

II
The SSM-2018's unique operational voltage-controlled element
(OVCE) architecture is easily configu[l:d into many voltagecontrolled functions by utilizing the simple feedback connections. Existing SSM-20l4 sockets can be directly upgraded to
the SSM-20l8, with the additional benefit of a significant reduction in the number of external components needed to achieve
full performance.
Combined with a voltage output DAC and multiplexed sampleand-hold circuit such as the DAC-7224 and SMP-08, or a multiple DAC such as the DAC-8800, high quality digital control of
many audio functions can be realized with very low pans count,
and at low cost.

SPECIAL FUNCTION AUD/O PRODUCTS 7-81

(Vs

= ±15 Vand -40°C :s TA :s +85°C with 18 kG feedback resistors,

SSM-2018 -SPECIFICATIONS ~:I=S:~~~~:se specified. Typical specifications apply to operation at
. Symbol

Parameters
INPUT AMPLIFIER
Bias Current
Input offset Voltage
Input Offset Current
Input Impedance
Equivalent Input Noise
Common-Mode Range
Gain Bandwidth

IB
VIOS
lIOS

ConditiOlis

Min

VCM = 0 V
VCM = oy
VCM = 0 V

ZIN

en
CMR
GBW

Slew Rate
Supply Current

SR
Isy

OUTPUT AMPLIFIERS
Offset Voltage
Minimum Load Resistor
Output Voltage Swing

Voos
RL

CONTROL PORT
Bias Current
Input Impedance
Gain Constant
Gain Constant
Temperature Coefficient
Control Feedthrough (Untrimmed)
Class A

f=lkHz
VCA Configuration (See Figure 18)
VCP Configuration (See Figure 22)
VCA Configuration (See Figure 18)
No Load
VIN = 0 V
For Full Output Swing
lOUT = 1.5 rnA

+10
'-10

IB
ZIN

G/(1-G)
G/(I-G)TC

Ratio of Outputs

60 Hz Sine Wave Applied to
Control Port, Causing
-30 dB to +20 dB of Gain
f = 1 kHz, VC = +4 V

Class ABI
Maximum Attenuation

Typ

Max

0.25
1
10
4
14
+13, -13
12
0.7
10

I
20
100

11

15

-1.0
9
+13.0
-14.0

20

mV
kG
V
V

0.36
1
-28
-2700

1

flo A
MG
mY/dB
ppmfC

Units

!LA
mV
nA
MG
nV/\/Hz
V
MHz
MHz
V/".s
mA

-10

mV

-1
100

mV
dB

AUDIO SPECIFICATIONS2
Parameter
Noise
Class A
Class AB
THD-A @ Av = 0 dB
THD-A @ Av = ±20 dB
THD-AB @ Av = 0 dB
THD-AB @ Av = ±20 dB

Conditions

Min

RB = 30 kG, BW = 20 Hz - 20 kHz,
OdBV = 1 Vrms,Av = OdB
RB = 150 kG, BW = 20 Hz - 20 kHz,
OdBV= IVrms,Av =OdB
R B= 30 kG, VIN = + 10 dBV @ 1 kHz
RB = 30 kG, VIN = + 10 dBV @ 1 kHz
RB = 150 kG, VIN = + 10 dBV @ 1 kHz, w/Sym Trim
RB = 150 kG, VIN = +10 dBV @ 1 kHz, w/Sym Trim

Typ

Max

Units

-88

-85

dBV

-97

-95

dBV

0.006
0.009
0.006
0.013

0.015
0.025
0.02
0.04

%
%
%
%

NOTES
'Symmetry trim only.
2Guaranteed specifications, based on characterization data.
Specifications subject to change without notice.

ORDERING GUIDE
Model

Operating
Temperature Range

Package
Option l

SSM-2018P
SSM-2018S

XIND2
XIND

16-Pin Plastic
16-Pin SOIC

NOTES
'For outline information see Package Information section.
'XIND ~ -40'C to +85"C.

7~82

SPECIAL FUNCTION AUDIO PRODUCTS

REV. A

SSM-2018
ABSOLUTE MAXIMUM RATINGS·
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ± IS V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . Supply Voltage
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . + lSO°C
Operating Temperature Range . . . . . . . . . . . -40°C to +SsoC
Storage Temperature . . . . . . . . . . . . . . . . -6SoC to + ISO°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . + 300°C

SSM-2018 PIN CONFIGURATION
16-Pin Plastic Dip-P SuffIX
16-Pin SOIC-S Suffix
+Il-G

V l -G

BAL
-IG

*Stresses above those listed under "Absolute Maximum Ratings" may cause
pennanent damage to the device. These are stress ratings only; the functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.

VG

-I l -G

SSM-2018

COMPI

TOP VIEW
(Not to Scala)

GND
MODE

+IN

Vc
-VEE

-IN

Typical Performance Characteristics
35

COMP2

COMP3

...

RF = 18k

RL="'/ V /

//

CLASS A

V/

//

crsr -

RL = 10k

~
o

o

:1:5

:t:15

:!:10

.20

SUPPLVVOLTAGE - Volts

Figure 1. Maximum Output Swing vs. Supply Voltage
30

--

o

-60 -40 -20 0
20 40 80
TEMPERATURE _ °C

Figure 3. Trimmed Feedthrough

80

100

Temperature

VS.

o

25

t
> 20
I

"j
!II

\

15

:IE

"r----.. r----..

:::J

!

10

:IE

Vr'l~V

o
lk

R F = 18kQ

RL

=10kQ

10k
FREQUENCY - Hz

Figure 2. Maximum Output Swing

REV. A

lOOk

VS.

Frequency

r-... I'-....

I"""--

r-...

-40

-60 -40 -20 0
20 40 80
TEMPERATURE - ·c

80

100

Figure 4. Gain Constant vs. Temperature

SPECIAL FUNCTION AUDIO PRODUCTS 7-83

•

SSM-2018
,------------('

+I'-G

BAL

11 Vc
1.SkQ
200Q

}4~----~~------{'2

MODE

1M

Figure 5. SSM-201B Functional Diagram

OPERATIONAL VOLTAGE-CONTROLLED ELEMENT
THEORY OF OPERATION
The operational voltage-controlled element, or OVCE, is a new
analog functional building block. It combines the function of an
op amp and a voltage-controlled amplifier into a single integrated device. However, because of the special circuit topology
used, this design offers higher performance than would be possible with two separate circuits. The OVCE can replace any VCA
in any application simply by reconfiguring the external feedback
connection. Additionally, it can perform numerous circuit functions not readily achievable with conventional VCAs.
As shown in Figure 5, the OVCE consists of three basic sections, which are:
I. The input differential pair, with compensation network;

Pin 12, which is determined by a user-selected external bias resistor. Under small-signal conditions, there is a tradeoff between
1M and the noise produced in the gain core transistors.
The gain core consists of two very carefully matched differential
pairs, utilizing large-geometry, high gain transistors designed to
produce minimum noise and distortion. Examining Figure 6, it
can be seen that a differential pair (which is forward-biased by
the current source) divides the tail current I into two currents
lei and Ie2 according to the applied voltage VB' With the high
beta of these devices, we can assume that the emitter current is
equal to the collector current, expressed as Ie = Is X exp(aV BE ),
where Is is the reverse saturation current. Then, since lei + Ie2
= I and VB = VBEI - VBEl , the ratio of currents can be expressed as:

2. A programmable current splitter which generates the biasing
current for the gain core;

G =

3. The four-transistor gain core (essentially a dual two-quadrant
multiplier) and the output buffers.

These relationships are precisely reproduced in both pairs of the
gain core, resulting in differential collector currents which accurately correspond to a function of the applied control voltage.
The SSM-ZOI8 is unique in providing both gain-multiplied and
remainder-multiplied outputs, resulting in an infinitely flexible
gain block.

The differential input pair structure is the same as that used in
operational amplifiers, and generates a single-ended output current corresponding to the differential input voltage. Variablegain amplifiers face a unique problem in maintaining optimal
compensation over a wide range of selected gains. In the OVCE,
an adaptive network following the input section effectively divides the external compensation capacitor by a value corresponding to the current value of VCA gain. In voltage-controlled
potentiometer configurations, the adaptive network is not used
because the global feedback is constant with changes in gain,
requiring fixed compensation only.
The current generated by the input differential pair is split to
drive the gain core transistors with currents containing equal
and opposite signal components. The common-mode component
of these currents (1 M ) determines the class of operation of the
OVCE. This current corresponds to the current injected into

IC2

I

=

explaVBI

1

+ exPlaVBI

and 1 _ G =

ICI

I

= :---:--;-;-:1 + explaVBI

~I
Figure 6. The OVCE Gain Core Differential Pair

7-84 SPECIAL FUNCTION AUDIO PRODUCTS

REV. A

SSM-2018
The differential outputs of the gain core transistor pairs are applied to differential current-to-single ended voltage converters,
composed of buffers Al through A4 in Figure S. Amplifiers Al
and A2 act as precision current mirrors, while A3 and A4 are
current-to-voltage converters. Additionally, connections to A2
allow the user to balance the current mirror gain to achieve perfect symmetry in the positive and negative half-cycles of the output waveforms. Note that the noninverting inputs of A3 and A4
are connected to the inverting inputs of Al and A2 respectively,
thus cancelling the error contributions of the current mirror circuitry. For this reason it is recommended that in applications
requiring additional output drive, external amplifiers be connected outside the feedback loops as voltage followers for best
OVCE response and dynamic range.

Therefore, this OVCE configuration provides the function of a
voltage follower at the V 1- G output, and the function of an exponential VCA at the VG output. The direct feedback connection between the VI _G output and the inverting input could be
easily replaced with any general feedback network, as is commonly done in op amp circuits.

v+

Figure 8. OVCE FollowerlVCA Connection

DIFFERENTIAL
INPUT

A wide variety of transfer functions from the input to the V I-"G
output are possible, independent of the control voltage input. At
the same time, as discussed above the signal seen at the VG output will then be equal to the transfer function times the control
voltage exponential. As demonstrated in the two examples in
Figure 9, this configuration provides the functions of both an
operational amplifier and exponential VCA in a single device,
allowing considerable flexibility in applications.

vFigure 7. The OVCE Symbol

USING THE OVCE
The symbol for the OVCE is shown in Figure 7. The OVCE has
two outputs, VG and VI~G' Both respond to the input, but in
addition are in a ratio determined by the control port voltage,
Vc, applied to Pin 11. Specifically,
Va = (V( +) - V( -)) x G x A

I

and
Vl~a =

(V(+) - V(-))

x

(I-G)

x

A

where A is the open-loop gain of the circuit and

G =

expla x Vel
1 + expla x Vel

As a result, the ratio of the outputs is
VG
VI~a = expla x Vel

a. Voltage-Controlled Preamplifier
Cl

The control constant a is approximately -4 at room temperature.
Application circuits are easily understood if it is assumed that
the voltages at the inputs of the OVCE are equal, as is commonly done with op amps when simplifying a negative-feedback
circuit with high open-loop gain. Consider the basic follower!
VCA connection for the OVCE shown in Figure 8. In this example, the input signal VIN drives the noninverting input, and
the V 1 ~G output is tied back to the inverting input. In closedloop operation we can simplify by saying that the inputs are approximately equal, and so the VI~G output follows the input for
all control inputs. However, since from above
Va =

VI~G

x expla x Vel

v1-G
R2

b. Voltage-Controlled Inverting Bandpass Filter
Figure 9. OVCE Configurations

then
VG

REV. A

C2
R3
Rl
~N~~~+-~r-1--------~~---------i

VlN x expla x Vel

SPECIAL FUNCTION AUDIO PRODUCTS 7-85

SSM-2018
error. The user should take care to avoid coupling stray signals
and ground errors into the control pin, which will directly affect
the performance of the device. As shown in the application
examples, a 1 f-LF capacitor is recommended, located near the
pin. Noisy environments may require that this value be
increased to 10 f-LF.

18kQ

Figure 10. Basic VCP Connection
Figure 10 shows the OVCE configured with feedback applied
from both outputs. Here the signal returned to the inverting
input is one half of the sum of the two outputs, which must be
equal to VIN if we remember the approximation that the difference between the inputs is zero. The two outputs are then given
by:
.

Va

=

2G

X

VlN and V, - a

=

211 - GI x V lN

It can be seen that this provides a panning function as Granges
between 0 and Iwhen Vc sweeps through its range. For
instance, when Vc = 0, VG = V, - G = VIN • This configuration
is called a voltage-controlled potentiometer (VCP). Note that the
VCP shares the quasi-exponential gain characteristics of VCAs
which operate as attenuators only. An endless variety of VCA
and VCP configurations are possible using the SSM-20I8, in
both inverting and noninverting operation. The applications
discussion below demonstrates the performance of a number of
circuits.

INPUT SECTION
The differential inputs are similar to those seen in an operational
amplifier. The user may wish to utilize clamp diodes to avoid
overdriving the input stage by high speed transients.

SETTING THE GAIN CORE CLASS OF OPERATION
The mode of operation is determined by the user by programming the gain core bias current with resistor R B. The positive
supply can be used to provide a current into Pin 12, which
must be between 90 f-LA and 500 f-LA for proper operation. The
suggested value for the set resistor RB is 30 kO for Class A
operation and 150 kO for Class AB. Without this current input,
the output signal will appear half-wave rectified. In earlier
designs, Class AB operation has always been preferred for lower
noise operation, while Class A was the choice where distortion
performance was the greater concern. However, as the distortion
graphs below demonstrate, the SSM-20I8 offers Class AB performance rivaling that of Class A. Most applications, except
those demanding the lowest possible distortion performance, will
bias the gain core as Class AB. Note that control feedthrough in
the SSM-2018 will be significantly lower in Class AB operation.
Alternatively, Intermediate Class operation offers an excellent
compromise between the low noise of Class AB and the superior
distortion of Class A.

CONTROL SECTION
The sensitivity of the control port is - 28 m VIdB at the input
(Pin 11). A resistive divider is commonly used to scale the control voltage source range. Since this input can draw as much as
250 nA of bias current, it is recommended that the impedance
of the divider to ground be kept under 10 kfl to minimize gain

7-86 SPECIAL FUNCTION AUDIO PRODUCTS

Due to temperature effects on the gain core transistors, the control port has a - 2700 pprnl°C temperature coefficient which can
be compensated with a single + 2700 ppmf'C tempsistor (RCD
Components, Inc., Manchester, NH, (605) 669-0054) in the control voltage divider chain.

COMPENSATION
In the VCA configuration, the SSM-20I8 utilizes a unique adaptive compensation network to maximize the internal closed-loop
gain of the device independent of overall system gain. As shown
in the application circuits, a compensation capacitor is connected between Pins 5 and 8, and Pin 9 is unconnected. In VCP
circuits, the feedback of the system is constant with gain and
the adaptive circuit is defeated by connecting Pin 9 to ground.
In circuits requiring moderate gain, the value of the compensation capacitor can be reduced in order to obtain wider signal
bandwidth.

OUTPUT SECTION
The SSM-20I8 has two voltage outputs, and three current outputs which can deliver a minimum of 750 f-LA when operating
from ± 15 V supplies. Feedback resistors for the internal or
external op amps which convert the currents to a desired voltage
should be greater than 17 kO with ± 15 V supplies. As shown in
the functional diagram, the current outputs are virtual grounds
in normal operation. Amplifiers Al and A2 act as current mirrors which maintain the +I, - G potential to ground. A3 and A4
are current-to-voltage converters which keep the outputs - IG
and - I, - G at ground potential, with current outputs capable of
sinking greater than 10 rnA and sourcing a minimum of
1.65 mAo

TRIMMING THE SSM-2018
The network recommended for correcting waveform symmetry
and trimming offset is shown in Figure 11. Both trims affect
offset and control feedthrough. The symmetry trim also controls
distortion performance and is mandatory for Class AB operation,
but may not be necessary in less critical applications operating in
Class A. The offset trim is appropriate in those situations requiring improved control feedthrough.
4}------,
10MQ
, -__~~__~
......::>

0

c~ss1:'.

-30

-40

.......

-50

.......

-50

s:
"-

-70
v,. =ov

-80

r-- TA =25'C

-80
-100
-40

-30 -20 -10

0

10

20

30

40

GAIN-dB

Figure 17. OVCE Output vs. Gain

Figure 16. OVCE THD+N vs. Frequency, Class AB Operation
V.

USING THE OVCE TO BUILD A SIMPLE VCA
This circuit demonstrates the flexibility of the SSM-2018 by
using differential current feedback to realize a complete, minimum parts count voltage-controlled amplifier with differential or
single-ended inputs. Amplifier A4 is defeated to .allow current
feedback to the OVCE input and enhance the frequency response and slew rate. See Figure 18. Feedback from the +I 1 - G
output to the inverting input and from -I 1 - G to the noninverting input creates differential virtual ground inputs. Singleended operation allows inverting or noninverting gain, with the
unused input unconnected. The output from amplifier A3 is
available at Pin 14. A capacitor of any value can be connected
across buffer A3 (Pin 3 to Pin 14) to band-limit the output signal as desired. Refer to Figures 19 through 21 for the typical
performance obtained with this implementation.

OffSET
TRIll
1lIII0

ll1111dl

v-

TRIll

v.o-+-++fil

-

IID-t-'M-ov.

""
R.=3CIIQ FOR CLASS A
1~ FOR CLASSA.

Figure 18. Simple VCA Application Circuit

7-88 SPECIAL FUNCTION AUDIO PRODUCTS

REV. A

• • _IIIM IIIt1Nxl . . . .'
I;. ", ':'1 .•. ;~ ... : ":""

::!:,::I:

-

5 • • 13:31:51

~'~'~i:il:: '''::'·,:':'/~:;'::';~f'Y~~H :.~"

...; .. '"' ,,.,

SSM-20l8
~=~Z_~HzI

V

-70

~

.
>

'D

I
Z

w

-to

';::Fiit;i:l
•

•

-100

Figure 19. VCA THD+N vs. Frequency, Class A Operation

V!
V
V ./V

-40 -30 -20 -10 0
10
GAIN-dB

• •

"

~

Figure 20. VCA THD+N vs. Frequency, Class AB Operation

~

20

30

40

Figure 21. VCAlOVCE Noise vs.
Gain

A VOLTAGE-CONTROLLED PANNER
The ratiometric outputs of the SSM-20IS allow the user to realize an excellent potentiometer with minimal external components, as shown in Figure 22. As first shown in Figure 10, the
outputs are summed and fed back to the noninverting input to
perform the basic panning function. Figures 23 through 29 demonstrate the performance observed with this configuration.

II
SYIIIIIElRY
TRIM

V-

SpF

SSM-2018
V..

o--I---j

18kll

18kll
R B ' 30Icll FOR CLASS A

lli01cll FOR CLASS AB

• A LARGER VALUE (11JilF-2Did'l WILL RESULT 1M
SLIGHTLY IMPROVED LOW FREQUENCY DISTORlION.

Figure 22. VCP Application Circuit

REV. A

SPECIAL FUNCTION AUDIO PRODUCTS 7-89

SSM-20l8
0.10
~CLASSAB

-,.......,
~
I
Z

f"""'-....

_CLASSA-"""""

0.010

.'"

~

+

i!'"

.\

"\

0.001

-'1 1kHZ
I
-40

Figure 23. VCP THD+N vs. Frequency, Class A Operation

0.10

0.010
~
I

---- -

%

........

\

'\

,\

""

~~

0.001

"....

\

- ' I ' 1kHz

I
-40

-30

-20

-10

+10

1\

r--

CLASSAB _

-20
-10
GAIN-dB

Figure 25. VCP THD+N vs. Gain

Figure 24. VCP THD+N vs. Frequency, Class AB Operation

t--

-CLASSA

"...

-30

o

-9
lk

+10

10k

lOOk

~I\
\

~
1M

10M

FREQUENCY - Hz

GAIN-dB

Figure 26. VCP THO vs. Gain

Figure 27. VCP Bandwidth vs.
Gain, Class A Operation

-90

9r-r-rrrr""T""T"'T"TT""'-I"T'I'T""T""T""""

."

-90

>
I

Z

au

-100

-9L-L...I..JUl.....L...u..l..L.-J....J.....L..LJ'-L...J..J.-U
lk

10k
lOOk
1M
FREQUENCY - Hz

10M

Figure 28. VCP Bandwidth vs. Gain,
Class AB Operation

7-90 SPECIAL FUNCTION AUDIO PRODUCTS

-110
-24

~~

-18

-12
-9
GAIN-dB

/

o

Figure 29. VCP Noise vs. Gain,
Class AB Operation

REV. A

SSM-20l8
A HIGH QUALITY VOLTAGE-CONTROLLED
EQUALIZER USING THE SSM-20IS
Figure 30 shows the SSM-201S in the VCEQ configuration,
utilizing a simple RC high pass filter network to generate a
basic reciprocal high frequency equalizer with excellent noise
and distortion characteristics. The noise and gain performance
obtained with this circuit is shown in Figures 31 through 34.
The user is free to replace the filter network in order to obtain
the desired gain characteristics. Any other noninverting filter,
including low-pass or bandpass functions, will yield a voltagecontrolled equalizer with the form of the filter transfer function.
The addition of voltage control to the equalization function creates an extremely attractive alternative.

UPGRADING SSM-20I4 SOCKETS WITH THE SSM-20IS
The SSM-20IS is a drop-in replacement for the SSM-2014,
offering noticeable performance improvements with minor
changes in the original circuitry. The SSM-2014 requires external compensation to assure optimal performance, including RC
networks on Pins 1,3, and 4, and a capacitor on Pin 9. These
components are not necessary when using the SSM-20IS, and
should be removed in order to realize the full performance of
the device. For best results, the SSM-20IS should not be evaluated in an SSM-2014 evaluation board. An SSM-20IS evaluation
board is available through your local sales office.

v+
SpF

OFFSET
TRIM
10MQ

V1_G

100kn
4701--,..----Q---I

200Q

FIGURE 7: Exponential Cross-Fade Controller

..

.1•

i"".. . /

J

II "-

~

\vcu

veAl/

\

/

V

-00
-2DD -150 -100

1\
-so

0
50
V_ImV)

\
100

150

zoo

FIGURE 8: Normalized Transfer Characteristic of a Exponential Cross-Fade Controller

7-98 SPECIAL FUNCTION AUDIO PRODUCTS

REV. A

True RMS-to~DC
Converter
SSM-2110 I

r.ANALOG
WDEVICES
FEATURES

GENERAL DESCRIPTION

• Multiple Output Options (Absolute Value, RMS, Log RMS,
Log Absolute Value, Average Absolute Value)
• Wide Dynamic Range ............................................... 100dB
• Prebias Option for Fast Response at Low Signal Levels
• On-Chip Log Output Amplifier
• Optional Internal Log Output Temperature
Compensation
• Low Drift Internal Voltage Reference
• LowCost

The SSM-211 0 is a true RMS-to-DC converter designed to provide multiple linear and logarithmic.output options. The linear
outputs, true RMS and absolute value, can be obtained simultaneouslywith the absolute value output configurable to give a peak
function. The logarithmic outputs can provide log RMS, log absolute value or log average absolute value. Full on-chip temperature compensation is available for each output option.

Continued

PIN CONNECTIONS
APPLICATIONS
•
•
•
•
•
•
•

ABSOLUTE VALUE

Audio Dynamic Range Processors
Audio Metering Systems
Digital Multimeters
Noise Testers
Panel Meters
Power Meters
Process Control Systems

LOGABS·YAL

18-PIN PLASTIC DIP
(P-Suffix)

FUNCTIONAL DIAGRAM

,-----------'-----------,
LOGOUT

ABSOLUTE
VALUE

COMS

13
LOG
RECOVERY
AMPUFIER

0-:.:
'

-LOG IN

0-:.:"+-__-1

LOG SCALE

16

+II'NI

°+-__;

.LOG IN

RMS

V.

5.41<0

LOG
RECOVERY
TRANSISTOR

12

0"'+--------'

.:I--+'-<> BASE
"----+=-<> EMITTER

INPUT <>-,,'7+-+--1

0,

r----+=-<>GND

AMS
COMPunNG
LOOP

V~F~+_------------~~----~--+-~~---+--~~--~~

SSM-2110

V-

LOGABSVAL

PREBIAS

The SSM-211 0 has been granted mask work protection under the Semiconductor Chip Protection Act of 1983.

REV. A

SPECIAL FUNCTION AUDIO PRODUCTS 7-99

•

SSM-2110
GENERAL DESCR.IPTION Continued

ABSOLUTE MAXIMUM RATINGS

The SSM-211 0 has a dynamic range of 1OOdB. A unique on-chip

Supply Voltage ........................................... ; •.••••••••••••••.••.. ±18V

prebias circuit enables the users to trade dynamic range at low

Storage Temperature Range •.•.•.••••.••••••..••••• -65°C to + 150°C

signal levels for a faster response time. As a precision level

Lead Temperature Range

detector, the SSM·2110 has applications in digital multimeters,

(Soldering, 60 sec) •••••••.•••••••••.•.••••.••••••.••.•••••••••••••••••••. +3OO°C

panel meters, process control and audio systems.

Junction Temperature ••....••••••.•..••.••••....••.••••••••••••••••.••• + 150°C
.operating Temperature Range ••••••••••••••••••••••• -25°C to +75°C
PACKAGE TYPE

ORDERING INFORMATION
PACKAGE

OPERATING
TEMPERATURE

PLASTIC
la-PIN

75

33

·CIW

NOTE:
1. alA is specified forworstcase mounting conditions. I.e .• alA Is specified fordevice
In socket for P·DIP.

RANGE

SSM2110P

UNITS

alA (Note 1)

la·Pln Plastic DIP (P)

-25·C 10 +75·C

ELECTRICAL CHARACTERISTICS atVs =±

15V, TA

=+25°C and RSCALE =4.7kn, unless otherwise noted.
SSM-2110

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

Dynamic Range

DR

3OnAp-p S I'Np.p S 3mAp-p

100

110

0.95

1.0

Unadjusted Gain

I'N=±lmA

Error (Mean or RMS)

MAX

UNITS
dB

1.05
±C.5

dB

5

15

nA

120

nA

Output Offset Current

1008

I'N=±lmA

los Shift

boloos

RPREBIAS = 3M!.!

50

Crest Factor@ 1mARMS

CF

For 0.1 dB Additional Error
For O.5dB Additional Error
For 1.0dB Additional Error

2.5
5
a

RMS Alter Time Constant

'coN

IRMS>10~MS

l1knX C'NT

Frequency Response (Sine Wave)
For O.ldB Additional Error

For 0.5dB Additional Error

BW

I'N> lmARMS
I'N > 10JlARMS
I'N > 1JlARMS

400
10
2

I'N> lmARMS
I'N > 10JlARMs
I'N > 1JlARMS

1000
50
7.5

I'N> lmARMS

1500
300
50

I'N>I~MS

-3dB Bandwidth

I'N > 1JlARMS
Log Amp Output Offset Current
(Pin 9)

IOOS-LOG

Max Log Amp Output (Pin 9)

1000-LOO

±250

Log Scale FaClor
(Pin 2 or Pin 6)
Log Mode Zero Crossing
(Mean or RMS, Pin 9)

RMS In To Get Zero Out (See Figure 7)

Log Amp Llnear~y (Pin 9)

Log Output Tempeo

Tc

±3.3

±13

JIA

±265

±2aa

JIA

+6

mY/dB

10

JlA

-240mV < V"N 10 - V"N 11 < +240mV

0.1

O·C < TA < +70·C

±75

VREF (Pin 3 to V-)

7-100 SPECIAL FUNCTION AUDIO PRODUCTS

6.7

kHz

7.5

0.25

dB
ppmfOC

7.8

V

REV. A

SSM-2nD
ELECTRICAL CHARACTERISTICS at VS =± 15V, TA=+25°C and RSCALE = 4.7kU, unless otherwise noted. Continued
SSM·2110
PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Positive Supply Current
Negative Supply Current

480
2.1

920
3.3

mA

Supply Vollage Range

±12

±18

v

IiA

Specifications subject 10 change; consult latest data sheet.

1 ABSOLUTE YAWE PREBIAS 11!.. - - - - - -

RMI.

Rit

elM

--+../II\Hr-o YIN

'
INPUT 1-":..7...:-:......:1'°"---7

2 LOGARS VAL

1-"'---_~

-15V

Cooos 13
LOG SCALE ..,1"'2_ _ _-.
-LOGIN

11

LOGOUT

c

VL·OG(I_o-......

WHERE

~o-~~-

_

__-------------~

PAEIIAB CONNECTION. SEE TEXT

IRIF1 •

Ra.!~t

IREF2 •

~ + 3f'A

TYPICAL VALUES:
"",.101U1

c,..o.....

" - =15.IIIQ

Rsc.w;.4.-

....,=I.5111l

....,.=43OIUI
Cooos=Ijd'
VLOG(RM.l

== log

nVINRllal)
l00mV

t

FIGURE 8: Log of RMS

REV. A

SPECIAL FUNCTION AUDIO PRODUCTS 7-105

SSM..2110
range' of the-device will be roughly symmetrical about the internal negative voltage reference. Also, the output impedance will
be low enough to drive the log amplifier's input(s) without introducing significant errors. The bias current into the pins of the log
amplifier is typically less than 1IlA but can be as high as 21lA. For
this reason the current through the log recovery transistor all
should always be set higher than 51lA. The current IREFl should
not be set too high (above 501lA) because the base current of
0 10 induces errors inthe RMS computing loop. If higher reference
currents are. required then they should be taken care of by
changing the currentthrough all' This can be done by changing
RREF2' The Log Recovery Amplifier Section explains this in more
detail.
The output sensitivity at EMITTER (pin 8) is about +60mV for
every 1OdB of signal level increase at 25°C. This sensitivity has.
a temperature coefficient of +3300ppm/oC.
The log of absolute value output can be converted to a log of
mean value by connecting a capacitor between LOG ABS VAL (pin
2) and V- (see Figure 7). Since this is an emitter follower output,
the response to a large-signal level increase will be fast while
the time constant of the output following a large-signal level decrease will be determined by the product of capacitor CAVG and
resistor RREF1'
One might think that connecting a capaCitor to the log output
would produce the average of the log of the absolute value.
However, since the capacitor enforces an AC ground at the
emitter of the output transistor, the capacitor charging currents
are proportional to the antilog olthe signal atthe base. Since the
base voltage is the log of the absolute value, the log and the
antilog terms cancel, and the capacitor is charged as a linear
integrator with a current directly proportional to the absolute value
of the input current. This effectively inverts the order of the averaging and logging operations. The signal at the output, therefore, is the log of the average of the absolute value of the input
signal.

LOG RECOVERY AMPLIFIER (PINS 9,10, 11 AND 12)
The log recovery amplifier is a linearized voltage-to-current
transconductor whose gain can be made proportional to absolute temperature. It is used to reference the log output(s) to ground
and also to temperature compensate the VT (KT/q) terms in the
log output recovery transistors (0/0 10 and all)'
One input of the log recovery amplifier is usually connected to
EMITTER (the emitter of the log recovery transistor-pin 8) while
the other is connected to VREF (pin 3).
'
Figure 6 shows the internal and external connections used to
obtain an output voltage equal to VLOG(RMS), The transfer characteristic of the log recovery_transistors is given by the following
equation:

The transfer characteristic of the log recovery amplifier is given
by the following equation:
lOUT = 64mV 8 VIN
RscALEVT

two

Combining the
equations yields the overall transfer charac. t~ristic for the ouput voltage VlOG(RMS):
V LOG (RMS) = 0.14.8 x RRMS x Iog (VIN/RIN)2
,. ._-';;".,;"-'~-I
,RSCALE
I REFl X I REF2
where,

Ideally this voltage is completely independent of temperature.
However, due to the temperature coefficient of several transistors internal to the SSM-211 0, this is not entirely true. The temperature coefficient is approximately ±75ppm/oC.
.

,

With the values shown in Figures 7 and 8, this transfer function
corresponds to an output change of 50mVldB. The reference
current is set to 10llA to provide the widest possible dynamic
range. The following results can be expected for the circuit in
Figure 8:
VIN(RMS)

100llV

lmV

10mA

100mV

IV

10V

I'N(RMS)

10nA

100nA

lIlA

lOIlA

1001lA

lmA

-3V

-2V

-IV

OV

lV

2V

VLOGOUT

.An RSCALE value of approximately 4.7kQ gives the best overall
linearity and temperature compensation performance. This is an
improvement of.about a factor of 40 over the uncompensated
drift. A 2kQ resistor in series with asilicon diode can be connected
from LOG SCALE (pin 12) to the negative supply to defeat the
temperature compensation for certain applications such as
cornpressorllimiters where the log di'ift will cancel the thermal
gain drift of a VCA's dB/volt control port.
The maximum output current for both the compensated and
uncompensated examples above is ±250IlA. This output current
is converted to a voltage with the circuits in Figures 7 and 8. For
these circuits this corresponds to a maximum output voltage of
±3.975V. If RSCALE is changed from the nominal value of 4.7kQ
the maximum output current will also change by the following
equation:
!LOG OUT (MAX) =

1.18V
RSCALE

8VIN = VT x In(----o-15V
19

e,..

LOG SCAl.E 12

+15V

8 EMITTER

-LOG ..

9 LOGOUT

+lOGIN

11
10

V....

FIGURE 10: Offset Trimming

WAVEFORM

VpT~

-

"-.7

RMS

AVERAGE OF
ABSOLUTE
VALUE
(AAV)

Vp

2 ·Vp

CREST
FACTOR
Vp
= RMS

V2 =1.414

J2

11:

Vp

Vp

1

Vp

v'3 =1.732

SINE WAVE

n

vp-t-

0

SQUARE WAVE
Vp

t

A

'\7

Vp

Va

v'2

TRIANGLE WAVE

2V,1 A

r

\;;J

RMS

~XRMS

Typically varies from 1 to 6 depending on the characteristic of
the noise. Theoretically, the
crest factor is unlimited. .

GAUSSIAN NOISE
FIGURE11: RMS, Average of Absolute Value and Crest Factors for Different Waveforms

7-108 SPECIAL FUNCTION AUDIO PRODUCTS

REV. A

SSM-2110
lDOpF
4.B4ka 22

-15V

GAIN
REDUCTION
RAOO

10kll

DIST
NULL

10ka 10

151cll

15k

r-------------------------

I
I
RIN

INPUTo--vW-j

CONOUT I

r-o..............,fW'-'I>-O TO Vc

RE<;N I

r='(>-<....,

I
I

I
I

I
I
I
I
I
I

I
I

:
I

+

~2V

'1

II

THRESH----------:

-

1_ _ _ _ _ _ - - - - - - - - - - - - - - - - -

200U

I

I

~o~~v____________ ~_:

V-

FIGURE 2: Level Detector

7-114 SPECIAL FUNCTION AUDIO PRODUCTS

REV. B

SSM-2120/sSM-2122
VLOG AV = kT In(

q

lli:!1)
IREF

With the use of the LOG AV capacitor the output is then the log
of the average of the absolute value of liN'
(The unfiltered LOG AV output has broad flat plateaus with
sharp negative spikes at the zero crossing. This reduces the
"work" that the averaging capacitor must do, particularly at low
frequencies. )
Note: It is natural to assume that with the addition of the averaging capacitor, the LOG AV output would become the average of
the log of the absolute value of liN' However, since the capacitor forces an AC ground at the emitter of the output transistor,
the capacitor charging currents are proportional to the antilog
olthe voltage althe base olthe output transistor. Since the base
voltage of the output transistor is the log of the absolute value of
liN' the log and antilog terms cancel, so the capacitor becomes a
linear integrator with a charging current directly proportional to
the absolute value of the input current. This effectively inverts
the order of the averaging and logging functions. The signal at
the output therefore is the log of the average of the absolute
value of liN'

USING DETECTOR PINS RECIN , LOGAV ' THRESH
ANDCON oUT
When applying signals to REC IN (rectifier input) an input series
resistor should be followed by a low leakage blocking capacitor
since REC IN has a DC voltage of approximately 2.1 V above
ground. Choose RIN for a±1.5mA peak signal. For±15Voperation this corresponds to a value of 10kn.
A 1.5MOvalueof RREF from log average to-15V will establish a
10J.1A reference current in the logging transistor (01), This will
bias the transistor in the middle of the detector's dynamic current range in dB to optimize dynamic range and accuracy. The
LOG AV outputs are buffered and amplified by unipolar drive op
amps. The 39kn, 1kO resistor network at the THRESH pin provides a gain of 40.
An attenuator from the CON oUT (control output) to the appropriate VCA control port establishes the control sensitivity. Use
2000 for the attenuator resistor to ground and choose RCON for
the desired sensitivity. Care should be taken to minimize capacitive loads on the control outputs CONour If long lines or capacitive loads are present, it is best to connect the series resistor
RCON as closely to the CON oUT pin as possible.
DYNAMIC LEVEL DETECTOR CHARACTERISTICS
Figures 3 and 4 show the dynamic performance of the level
detector to achange in signal level. The inpulto the detector (not
shown) is a series of 500ms tone bursts at 1kHz in successive
1OdBV steps. The tone bursts start at a level of -60dBV (with
RIN =1 Ok) and return to -60dBV aiter each successive 10dB
step. Tone bursts range from -60dBV to +10dBV. Figure 3
shows the logarithmic level detector output. The output of the
detector is 3mV/dB at LOG AV and the amplifier gain is 40 which
yields 120mV/dB. Thus, the output at CONoUT is seen to increase by 1.2V for each 1OdBV increase in input level.
DYNAMIC ATTACK AND DECAY RATES
Figure 4 shows the output levels overlayed using a storage

REV.B

FIGURE 3: Detector Output

FIGURE 4: Overlayed Detector Output
scope. The attack rate is determined by the step size and the
value of CA V' The attack time to final value is a function of the
step size increase. The chart of Figure 5 shows the values of
total settling times to within 5, 3, 2 and 1dBof final value with
CAV = 10IlF. When step sizes exceed 40dB, the increase in settling time for larger steps is negligible. To calculate the attack
time to final value for any value of CAV' simply multiply the value
in the chart by CA v /1 OIlF.
The decay rates are linear ramps that are dependent on the
current out olthe LOG AV pin (set by RREF) and the value of CAV '
The integration or decay time of the circuit is derived from the
formula:
Decrementation Rate (in dB/s) = I REF x 333
CAV

5dB

3dB

2dB

1dB

10dBSIep

11.28ms

21.46

30.19

46.09

20dBStep

16.65

26.83

35.56

51.46

30dBStep

18.15

28.33

37.06

52.96

40dBStep

18.61

27.79

37.52

53.42

50dBStep

(+I44l's)

60dBStep

(+46I's)

FIGURE 5: Settlmg Time (ts) forCAV = 1~F, ts ' = ts (CAV /
1~F)

SPECIAL FUNCTION AUDIO PRODUCTS 7-115

II

SSM-2120/ssM-2122
a) CONTROL CIRCUIT

b)

TYPICAL DOWNWARD EXPANDER
CONTROL CURVE
THRESHOLD

...

r
r
r
r
r
r
r

ntRESHOLD CONTROL

LQ.-,/W'-

MONO~!"1'~ RIc,.
ORR....,.yy~

+

+---N{L--Q--M~OTO+YC

....,

YCON

V

=

MONO-RIN 10k0
STEREO - "-N" 20kn

Y-

"LOWER ullrr CAN

V.(dS)"

a.e FIXED BY CONNECTING

A RESISTOR Ru.. FROM RECIN TO GROUND

FIGURE 6: Noise Gate/Downward Expander Control Circuit and Typical Response

a) CONTROL CIRCUIT

b)

TYPICAL COMPRESSOR/LIMITER
CONTROL CURVE

i/

THRESHOlD

Y.

....

L~

~~. 1"1 RECIN
ORR~+

IIONO_

Yccol------l--.....iL--l

Y-

VI,.(dB)

·UPPER UMIT CAN 8E FIXED BY VALUE OF PULL UP
RESISTOR (1Ipy) CONNECTED TO POSITIYE SUPPLY

FIGURE 7: Compressor/Limiter Control Circuit and Typical Response

APPLICATIONS
The following applications for the SSM-2120 use both the yeAs
and level detectors in conjunction to assimilate a variety of functions.
The first section describes the arrangement of the threshold
control in each control circuit configuration. These control circuits form the foundation for the applications to follow which
include the downward expander, compressor/limiter and compandor.
THRESHOLD CONTROL
Figure 6a shows the control circuit for a typical downward expander while Figure 6b shows a typical control curve. Here, the
threshold potentiometer adjusts VT to provide a negative unipo-

7-116 SPECIAL FUNCTION AUDIO PRODUCTS

lar control output. This is typically used in noise gate, downward
expander, and dynamic filter applications. This potentiometer is
used in all applications to control the signal level versus control
voltage characteristics.
In the noise gate, downward expander and compressor/limiter
applications, this potentiometer will establish the onset of the
control action. The sensitivity of the control action depends on
the value of RT'
For a positive unipolar control output add two diodes as shown
in Figure 7a. This is useful in compressor/limiter applications.
Figure 7b shows a typical response.
Bipolar control outputs can be realized by adding a resistor from
the op amp output to V+. This is useful in compandor circuits as

REV.S

SSM-2120/sSM-2122
TYPICAL COMPANDOR
CONTROL CURVES

b)

a) CONTROL CIRCUIT
v.

MONO - RtN. 10kD
STEREO - RII • 2CIkn

v-

vVI,.{dB)
*UPPER AND LOWER LIMITS CAN BE ESTABUSHI!D BY

VAWES OF flpy AND fiLL. RESPECTIVELY

FIGURE 8: Compandor Control Circuit and Typical Curves

a) CONTROL CIRCUIT

b)
THRESHOLD EXP.

INPUT/OUTPUT CURVE
E......SION
THREEHOlD

COMPRESSION
THRESHOLD

FIGURE 6

LO- - __
I

Vcurl"B) I----'--~'------I

THRESHOLD COM.

FIGURE 7
/
/

FIGURE 9: Control Circuit for Stereo Compressor/Limiter with Noise Gating and Input/Output Curve

shown in Figure 8a, with its response in Figure 8b. The value of
the resistor Rpv will determine the maximum output from the
control amplifier.
STEREO COMPRESSOR/LIMITER
The two control circuits of Figures 6 and 7 can be used in conjunction to produce composite control voltages. Figures 9a and
9b show this type of circuit and transfer function for a stereo

REV. B

compressor/limiter which also acts as a downward expander for
noise gating. The output noise in the absence of a signal will be
dependent on the noise of the current-to-voltage converter
amplifier if the expansion ratio is high enough.
As discussed in the Threshold Control section, the use of the
control circuit of Figure 5, including the Rpv to V+ and two diodes, yields positive unipolar control outputs.

SPECIAL FUNCTION AUDIO PRODUCTS 7-117

•

SSM-2120/ssM-2122

4.7MC

v-

v-

FIGURE 10: Companding Noise Reduction System
COMPANDING NOISE REDUCTION SYSTEM
A complete companding noise reduction system is shown in
Figure 10. Normally, to obtain an overall gain of unity, the value
of Rc is equal to RE. The values of RCIE will determine the compression/expansion ratro.

20

IREF::: 311A
RREF=4.7MO

iD
~

Table 1 shows compression/expansion ratios ranging from
1.5:1 to full limiting with the corresponding values of RCIE"

§

An example of a 2:1 compression/expansion ratio is plotted in
Figure 11. Note that signal compression increases gain for low
level signals and reduces gain for high levels while expansion
does the reverse. The net result for the system is the same as
the original input signal except that it has been compressed
before being sentlo a given medium and expanded' after recovery. The compression/expansion ratio needed depends on the
medium being used. As an extreme example, a household tape
player would require a higher compression/expansion ratio than
a professional stereo system.

52

-20

;;I
z

..
~

-40

0

-60

-60

-40

-20

20

INPUT SIGNAL LEVEL (dS)

FIGURE 11: Companding Noise Reduction with 2:1 Compression/Expansion Ratio

TABLE 1
GAIN
(REDUCTION
OR INCREASE)
(dB)

COMPRESSOR
ONLY
OUTPUT SIGNAL
INCREASE (dB)

EXPANDER
ONLY
OUTPUT SIGNAL
INCREASE (dB)

20

6.67

13.33

22.67

1.5:1

11,800

2.0

20

10.00

10.00

30.00

2:1

7,800

3.0
4.0

INPUT SIGNAL
INCREASE (dB)

COMPRESSIONI
EXPANSION RATIO

Re/E !l

.l.VCONTROC
(mV/dB)

20

13.33

6.67

33.33

3:1

5,800

20

15.00

5.00

35.00

4:1

5,133

4.5

20

16.00

4.00

36.00

5:1

4,800

4.8

20

17.33

2.67

37.33

7.5:1

4,415

5.2

20

18.00

2.00

38.00

10:1

4,244

5.4

20

20.00

0

40.00

AGC'/Umiter

3,800

6.0

• AGC for Compression Only

7-118 SPECIAL FUNCTION AUDIO PRODUCTS

REV.S

SSM-2120ISSM-2122
v+

THRESHOLD
CONTROL

10ke

~--N-.t----ov-

2.2J.tF REC 1N

~~~~~ <>-

*

AUDIO
OUTPUT

2200pF
200

I22GOpF

200<>
DOWNWARD EXPANDER

vv.

'&Ok<>

v-

39kn

200<>

38k"

FIGURE 14: Dynamic Filter with Downward Expander
DYNAMIC FILTER WITH DOWNWARD EXPANDER
A composite single-ended noise reduction system can be realized by a combination of dynamic filtering and a downward expander. As shown in Figure 14, the output from the wideband
detector can also be connected to the + Vc control port of the
second VCA which is connected in series with the sliding filter.
This will act as a downward expander with a threshold that
tracks that of the filter. Although both of these techniques are
used for noise reduction, each alone will pass appreciable
amounts of noise under some conditions. When used together,
both contribute distinct advantages while compensating for
each other's deficiencies.
Downward expansion uses a VCA controlled by the level detector. This section maintains dynamic range infegrity for all levels
above the user adjustable threshold level. As the input level
decreases below the threshold, gain reduction occurs at an increasing rate (see Figure 15). This technique reduces audible
noise in fade outs or low level signal passages by keeping the
standing noise floor well below the program material.
This technique by itself is less effective for signals with predominantly low frequency content such as a bass solo where wideband frequency noise would be heard at full level. Also, since
the level detector has a time constant for signal averaging, percussive material can modulate the noise floor causing a "pump_
ing" or "breathing" effect.

REV. B

The dynamic filter and downward expander techniques used together can be employed more subtly to achieve a given level of
noise reduction than would be required if used individually. Up
to 30dB of noise reduction can be realized while preserving the
crisp highs with a minimum of transient side effects.

.20

I

1.•

0

-30

-30

-40

-45

iii

iii

..

!1.

!1. -50

!;

!:

-60

-60

~

0

-75

FIGURE 15: Typical Downward Expander 110 Characteristics
at -30dB Threshold Level (1:1.5 Ratio)

SPECIAL FUNCTION AUDIO PRODUCTS 7-121

•

SSM-2120/SSM~2122

10pF

SIOOUT ,

2201cIl

200Il

v-

-Ve'o--36-IcIl--------'
SININ1

0-./II\1'-<.._---..,.-----"-I

I

2000pF

v.

1S01c1l

":" 4711

1

2000pF
4711

-15V

* OPTIONAL CONTROL FEEDTHROUOH TRIM

FIGURE 16: SSM-2122 Basic Connection (Control Ports at OV)
FADER AUTOMATION
The SSM-2120 can be used in fader automation systems to
serve two channels. The inverting control port is connected
through an attenuator to the VCA control voltage source. The
.noninverting control port is connected to a control circuit (such
as Figure 6) which senses the input signal level to the VCA.
Above the threshold voltage, which can be set quite low (for
example -60dBV), the VCA operates at its programmed gain.
Below this threshold the VCA will downward expand at a rate
determined by the +Vc control port attenuator. By keeping the
release time constant in the 10 to 25ms range, the modulation of
the VCA standing noise floor (-80dB at unity-gain), can be kept
inaudibly low.

Figure 16 shows the basic connection for the SSM-2122 operating as a unity-gain VCA with its noninverting control ports
grounded and access to the inverting control ports. This is typical for fader automation applications. Since this device is a pinout option of the SSM-2120, the VCAs will behave exactly as
described earlier in the VCA section.
The SSM-2122 can also be used with two or more op amps to
implement complex voltage-controlled filter functions. Biquad
and state-variable two-pole filters offering lowpass, bandpass
and highpass outputs can be realized. Higher order filters can
also be formed by connecting two or more such stages in series.

The SSM-2300 8-channel multiplexed sample-and-hold IC
makes an excellent controller for VCAs in automation systems.

7-122 SPECIAL FUNCTION AUDIO PRODUCTS

REV. B

Dolby Pro-Logic
Surround Matrix Decoder
SSM-2125/SSM-2126 I

1IIIIIIII ANALOG

WDEVICES

Over 2000 major films and an increasing number of broadcasts
are available in Dolby Surround. Surround encoding is preserved in the stereo audio tracks of normal video discs, video
cassettes, and television broadcasts, permitting the decoding to
multichannel audio in the home.

FEATURES
Noise Generator and Autobalance Circuits are Contained On-Chip
Autobalance On/Off Control
4-Channel Pro-Logic and Dolby 3 (Surround Channel
Defeat) Modes Available
Selectable Center Channel Modes-Normal. Wideband.
Phantom. Off
Direct Path Bypass (Normal 2-Channel Stereo Mode)
Wide Channel Separation
Center to Left. Right Channels-35 dB min
(SSM-2125)
Any Channel to Another-25 dB min (SSM-2126)
Wide Dynamic Range-103 dB typ
Low Total Harmonic Distortion-O.02% typ
Available in a 48-Pin Plastic DIP
CMOS and TTL Compatible Control Logic

Major design considerations of the SSM-2125!SSM-2126 are excellent audio performance and a high level of integration. In addition to the Adaptive Matrix and Center Mode Control, also
included on-chip are the Automatic Balance Control and Noise
Generator functions. A complete Pro-Logic system can be realized using the SSM-2125!SSM-2126 and few external components. Using SSM's extensive experience in the design of
professional audio integrated circuits, the SSM-2125!SSM-2126
offers typical 103 dB dynamic range and 0.025% THD. A direct
path bypass mode allows normal stereo operation with high fidelity without the need for external switching or parallel signal
paths.

APPLICATIONS
Direct View and Projection TV
Integrated AIV Amplifiers
Laserdisc and CD-V Players
Video Cassette Recorders
Stand-Alone Surround Decoders
Home Satellite Receiver/Descramblers

The SSM-2l25 is a premium grade that is selected to a minimum channel separation specification of 35 dB for the center to
left and right channels, and 25 dB for the remaining channels.
The standard grade, the SSM-2126, provides minimum channel
separation of 25 dB from any channel to another.
The SSM-2125!SSM-2126 is available only to licensees of Dolby
Licensing Corporation, San Francisco, California, from whom
licensing and application information must be obtained.

GENERAL DESCRIPTION
The SSM-2125 and SSM-2126 are Dolby* Pro-Logic Surround
Decoders developed to provide multichannel outputs from
Dolby Surround encoded stereo sources.

FUNCTIONAL BLOCK DIAGRAM

I
INPUTS
LEFT

RIGHT

of
ot

LEVEL
METERS

-------~1- -----------------------,
AUTO·
BALANCE,

j

BUFFERS

I

NOISE
GENERATOR

I

ADAPTIVE

L
C

MATRIX

R

r---r--------------------.
I
I
I

1______ - - - - - '

ANTI~

ALIAS
FILTER

AUDIO
DELAY

~

:

I---

l-

MODIFIED
B·TYPE
DECODER

C
R

:~

SSM-2125!SSM-2126

7kHz
LOW·PASS
FILTER

OUTPUTS

I L

CENTER
MODE
CONTROL

MASTER
LEVEL
CONTROL

~
~

LEFT
CENTER
RIGHT
SURROUND

*Dolby is a registered trademark of Dolby Laboratories Licensing Corporation, San Francisco, California.

REV. 0

SPECIAL FUNCTION AUDIO PRODUCTS 7-123

•

(V = ±6 v, TA =
V
0 dBd at 1kHz,'
SSM - 2125I,"SSM - 2126 - SPECIFIC.'IIONS
It
Center Mode Control: Wide, unless otherwise noted.)
s

+25°C, IN ",;

SSM-2125
Parameter

Symbol

CHANNEL SEPARATION
Center
Right
Left
Surround
CHANNEL OUTPUT LEVEL

Conditions

Min

Typ

C Input; R, L Outputs
C Input; S Output
R Input; L, C, S Outputs
L Input; C, R, S Outputs
S Input; L, R, C Outputs

35
25
25
25
25

48
35
35
35
35

VIN = 0 dB; L, R, C, S Output

SSM-2126
Max

Min

Typ

25
25
25
25
25

35
35
35
35
35

±0.5

Max

Units
dB
dB
dB
dB
dB

±0.5

dBd

0.1

%

TOTAL HARMONIC
DISTORTION

THD

All Channels

SIGNAL-TO-NOISE RATIO

SNR

VIN = 0 V, CCIR2K1ARM
All Channels

-83

-87

-80

-87

dBd

HEADROOM

HR

Clipping = 3% THD
All Channels

15

16

15

16

dBd

0.02

0.1

0.02

BYPASS MODE
DYNAMIC RANGE

Clipping to Noise Floor

104

104

dB

NOISE SOURCE
OUTPUT LEVEL

All Channels

-13.5

-13.5

dBd

NOISE SOURCE OUTPUT
LEVEL MATCHING

Any Channel to Another

1

1

dB

±3.8

dB

AUTO BALANCE
CAPTURE RANGE

±3

LOGIC THRESHOLD HI
LO

±3.8

±6

+2.4

Relative to LREF

+2.4
+0.8

OPERATING SUPPLY
VOLTAGE

Vs

Single Supply
Dual Supply

+12
±6

+0.8
+12
±6
40

V
V
V
V

SUPPLY CURRENT

Isv

No Input Signal

40

INPUT IMPEDANCE

ZIN

L, R Inputs

5

5

kG

OUTPUT IMPEDANCE

ZOUT

L, R, C, S Outputs

600

600

G

50

50

mA

NOTE
'0 dBd ~ 500 mV rms Dolby level output at any channel; Left and Right inputs: 500 mV rms (0 dBd); Center input: L ~ R ~ 354 mV rms (-3 dBd);
Surround input: L ~ -R ~ 354 mV rms (-3 dBd).

ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . , . . . . . . . . . . . + 16 V or ±8 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . V + to VStorage Temperature Range . . . . . . . . . . . -55°C to + 125°C
Operating Temperature Range . . . . . . . . . . . -20°C to +70OC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . + 1500C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300OC
Thermal Resistance'
aJA : • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 38°C/W
aJc • • • • • • • • • • • • • . • . • • • • • • • • • • • • . • • . • 14°C/W
NOTE
le JA

ORDERING GUIDE
Model

Temperature
Range

Package
Option

SSM2125XXXP*
SSM2126XXXP*

-20°C to +70°C
- 20°C to + 70°C

48-Pin P-DIP
48-Pin P-DIP

NOTES
IFor outline information see Package Information section.
'The SSM·2125/SSM·2126 is available only to licensees of Dolby Laborato·
ries. Each customer will be assigned a special part number for ordering purposes. Contact local ADI sales office for further details.

is specified for worst case mounting conditions, i.e., devic;e in socket.

7-124 SPECIAL FUNCTION AUDIO PRODUCTS

REV. 0

SSM-2125/ssM-2126
Table I. External Component List
Component Value
CI
C2
C3
C4
CS
C6
C7
C8
C9
CIO
Cll
CI2
C13
CI4
CIS
CI6
CI7
CI8
CI9
C20
C21
C22
C23
C24
C2S
C26
C27
C28
C29**
C30**
C31
C32
Rl
R2
R3
R4
RS
R6
R7
R8
R9
RIO
Rll
R12

Comment (Noncritical
Tolerance* Unless Otberwise Noted)

0.1 fLF
0.1 fLF
680 pF
0.1 fLF
0.1 fLF
680 pF
4.7 fLF 20%
0.22 fLF
0.22 fLF
0.33 fLF
0.33 fLF
0.33 fLF
0.33 ....F
22 nF
22 nF
22 nF
22 nF
0.1 fLF
20%
4.7 ....F
0.22 fLF
0.22 .... F
20%
10 fLF

10 nF
10 nF
10 nF
100 ....F
O.I .... F
100 .... F
0.1 fLF
100 fLF
O.I ....F
IS kfl
47 kfl
IS kfl
47 kfl
7.5 kO
7.5 kO

PIN CONNECTIONS

-

CT2
CT3
CT6
CFWR
CFWL

Standard Electrolytic

CFWC

Film
Film
Film
Film
Film
Film
Film
Film

BPLIN

CFWS

Standard Electrolytic

Standard Electrolytic
Not Needed

;,oIOO .... F

Standard Electrolytic

;,o100 .... F

Standard Electrolytic

;,oIOO .... F

Standard Electrolytic

ACL2
RIN

ACLI

SSM-2125!
SSM-2126

NIN
NC

TOP VIEW
(Not to Scale)

V-

-

-

-

-

22kO
22 kO
IOMO
22 kfl

5%
5%
5%
5%

BPR IN
ACR2

NOUT

ACRI

VREF

ACC2

DMI

ACCI

DM2

ACS2

DM3

ACSI

DM4

SOUT

CMl

CCI

CM2

CC2

LREF

V-

VRO

ROUT
COUT

LoUT

5%
5%
5%
5%
5%
5%

VREF

NC

= NO CONNECT

Not Needed
Not Needed

NOTES
*10% unless otherwise indicated.
**Used only in Dual Supply Application Circuit.

REV. 0

SPECIAL FUNCTION AUDIO PRODUCTS 7-125

•

SSM-2125/sSM-2126
PIN DESCRIPTION

Pin # Name

Function

Pin # Name

1
2
3
4
5
6
7
8
9
10

Long Time Constant, CIS
Short Time Constant, LIR Comparators
Reference Voltage: Ground or Pseudoground
Positive Supply
Short Time Constant, CIS Comparators
Autobalance Time Constant
Buffered, Autobalanced Right <;:hannel Signal
Buffered, Autobalanced Left Channel Signal
Left Channel Input
Right Channel Input
Filtered Noise Input
Do Not Connect
Negative Supply (Ground in Single Supply)
Noise Output
Reference Voltage: Ground or Pseudoground
Digital Operating-Mode Control Input
Digital Operating-Mode Control Input
Digital Operating-Mode Control Input
Digital Operating-Mode Control Input
Digital Center-Mode Control Input
Digital Center-Mode Control Input
Logic Reference Voltage
(Threshold = LREF + 1.4 V)
VREF Out-Pseudoground Output
Left Channel Output
Center Channel Output
Right Channel Output
Negative Supply (Ground in Single Supply)
Center Normal-Mode Filter Input (Z = IS ko')
Center Normal-Mode Filter Output
Surround Channel Output
Surround Channel Steering Signal
AC Coupling and High-Pass Filter
Surround Channel Steering Signal
AC Coupling and High-Pass Filter
Center Channel Steering Signal
AC Coupling and High-Pass Filter
Center Channel Steering Signal
AC Coupling and High-Pass Filter
Right Channel Steering Signal
AC Coupling and High-Pass Filter
Right Channel Steering Signal
AC Coupling and High-Pass Filter
Filtered Right Channel Input to Steering
Signal Generator
Reference Voltage: Ground or Pseudoground

39

ACLI

40

ACL2

41

BPL1N

42

CFWS

43

CFWC

44

CFWL

45

CFWR

46
47
48

CT6
CT3
CT2

12
13
14
15
16
17
18
19
20
21
22

CT5
CTl
VREF
V+
CT4
CAB
RT
LT
LIN
RIN
NIN
NC
VNOUT
VREF
DMI
DM2
DM3
DM4
CMl
CM2
LREF

23
24
25
26
27
28
29
30
31

VRO
LOUT
COUT
ROUT
VCC2
CCI
SOUT
ACSI

32

ACS2

33

ACCI

34

ACC2

35

ACRI

36

ACR2

37

BPR1N

38

VREF

11

7-126 SPECIAL FUNCTION AUDIO PRODUCTS

Function
Left Channel Steering Signal AC Coupling
and High-Pass Filter
Left Channel Steering Signal AC Coupling
and High-Pass Filter
Filtered Left Channel Input to Steering
Signal Generator
Surround Channel Full-Wave Reetifier
Low-Pass Filter
Center Channel Full-Wave Rectifier
Low-Pass Filter
Left Channel Full-Wave Rectifier
Low-Pass Filter
Right Channel Full-Wave Rectifier
Low-Pass Filter
Short Time Constant, CIS
Short Time Constant, LlR
Long Time Constant, LlR

REV. 0

SSM-2125/sSM-2126
SS11-2IZ5fZIZIi : Center. Surround Distortion Z21fz:-Z8WIz H-NC") ... FRIlICHz)

SSII-21ZS : Cent.. Channel Nor.. 1 !lode Response AIIPWBr) .. FREQ(Hz)
2.l18li8 r
1.l18li8
B.B

-s .•
188

ZB

Figure 1. THD+N vs. Frequency, * Center and Surround
Channels (V,N = 0 dBd, RL = 100 kf1)

SSII-ZIZ5fZIZIi : Lr:rt. Right Distortion Z21fz:-Z_ ntD'"Cx) us FREQCHr)

18k

lk

Figure 3. Bass-Splitting Filter Response (Center Channel
Normal and Wide Modes)

SSII-ZIZ5fZIZIi : Hedr.... !ItD-NCx) us All'LCdi!I')
18

,·z· .. ·

:.....

'J !f

;

\

!

.......

t..·

11

;............

.,RlG:HTj

".

.. .......

8.1

..........

;.........

:

;

........ i ....
...,

.. ::.::::: :: .. ::::::::::: !:: .. ::

V

V
7=

i f ..
~

i -f-!
!
8.818
B.1II5
B.B

t·::::

11-' ;.....

.............

.......

lJ

...
tL

:::::::.

:.::::.:,.........
,.... ..::::::.j ...............
;

Figure 2. THD+N vs. Frequency, * Left and Right Channels
(VIN = 0 dBd, RL = 100 kfl)

ZBk

""'-CENTE.R

V

f"L
:"':::::::: .

:
:::::::
...........

/

~IAAnIlNn

Z.BIII 1.888 6.888 8.888 18 .• 1Z •• Ii •• 16 .• lB .• ZB .•

Figure 4. Headroom THD+N vs. Amplitude (0 dBr =
500 mV rms)

o dBd =

*80 kHz low-pass ftIter used for Figures 1 and 2.

REV. 0

SPECIAL FUNCTIONAUDIO PRODUCTS 7";'127

•

SSM-2125ISSM-2126
+12V

C31

+

1

l00"F
C28

Cl
C2

O.1~IF

Rl

O.1~IF

15kU

R2
C3

C4
CIB

r----\

+-+-+-~~~+~~~~rrl

H-+...;:4::.:..7!:.:"F_-l1-'t+-~

r--

'-'

....

O.22"F

o..!

~ C2~
1

~

, ~'-'-B

~F

4Ot-It---+t------i
~ 22nF

....

R,. ~

~:g

~F ~! l

~~ll

~
~

+-~C2~4~~--------~~
RB
r,4
lGnF

22k!l;::::

~

DM1.........J18
.~

DM2o--@

DM3~
DM4

<>--E!

CM:~

CM2....--.!!

L-_+----~~

:::
L.-_ _ _ _-I~
LOUT

~

R5
7.Sk!.l

~C14

.n.......r.;;

C28
~

o.22"F

~rO~.33~"F____~____~

L'N

C25

C5

O.1!,F

R3

~ C13 0.33 ,F

~r----------I~

~-I-....-+--+-----i'1i

;

C8

~t-:::4~~7'::..F-II~

47k1l

....H-+-=::~+--iH 5
C,22+
O.22"F ~
IO"F

C7

~

680pF

O.1!,F

R4
F.; 0.22 ,F Cl0 ~
C6
F.;~C~I~:
44r ~O.~33~'~Ft~E;1
680pF
~O.33"F C12

1""0"

Rll

~+

47kU

RS
7.Skll

~t-==--+t----SSM-2125!
SSM-2126

twl-'--+'

~J-:::::---t--------+----'

f:1

C15

~r-I!-----r---------------~

r-____________~

~~22~n~F____

~GJC1S
34

33 22nF
C17

~t,

~
@-oSOUT

~~8
~

~'r-----""
~
_ ROUT
~

l!!J-o

COUl

Figure 5. Single Supply Application Circuit

7-128 SPECIAL FUNCTION AUDIO PRODUCTS

REV. 0

SSM-2125/sSM-2126

-

+6V

C27

+

~:~
~t100t.IF

.".

100,IF

C28
O.111F

O.1!.F

C19

+-~~--II"+----+-~~
4.7"F C21
~

----,.,..--

'-'

s:

+-H-+....::.:."'--i~-+-; 2
0.22 ,F

HN'r-,

!O

110M" I
C22+

47

C20

~

'~
45'F':;";"-'1t--t.L.:ii.-..l
c~~1 0.33 ,F

'5

1 O.22"F ~

5o.~"F C12
43 r.:::='--i
~ C13o.33uF

t-.

t-i 1"'.......-=""-1 6

~~----------l~

lOnF

Lji
lOnF

~

Rl0

22k!! "--:".,..-t----------ir.:;13

~~

R121
22k!!

t

~

R9

lOnF • ____22
__k'_'__......,~l1!J
15

DM1~

DM2

<>--ill

DM3~

DM4~

CM1~

-

,n......J;;'

CM2~

.....--~__------4~
C29+
C30.1

~~O=.33=,~,F----H----~

5404C)t--l1r----++--------....
~~4

o--i!L.:.9

. ..........r;;;
C25
R,M ..--.!!
.....~~....--__+----+--------_;'i1

~

~

~"It-..;.l00="F~·1 LOUT~

C9 0.22uF

E!O~uF Cl0

yH-l:.:..l::,F:........------l~

LINI

r.::'"-H-.

~

y.

Rll

C7

~~+~~--~.
~ 4~;uF C8

b22nF

~I-"';.;.;;..----H--------........

SSM-2125/
SSM-2126

I;i'~----_+....J

~I-:"""'----~--------------+_--....J
~HCllt5----+--------------......
~r.:~:::\n:_·F----~--------------'
P~C16
34

33 22nF

~~

~

~.SOUT
~Cl18
28

O.1I1F

.

~~----~
~
~

_ROUT

§-.oCOUT

O.1!IF

Figure 6. Dual Supply Application Circuit

REV. 0

SPECIAL FUNCTION AUDIO PRODUCTS 7-129

SSM-2125/SSM,.2l26

LT •

Lou,
C.IIl"

FIolll"
SOll1"

28 CC2 r---lI
C::~A

29 CCl I FILTER :

1l---...r~TIL£~_J

11

NIN

-----,

I BANDPASS I
I

NOISE

I

I FILTER I
I (e24, 25, 26 I
14

Nour I R9, 10. 12) :

L ___ .J

. DM2

DM4

CM2

Figure 7. SSM-2125/SSM-2126 Block Diagram Showing External Component Functions

APPLICATIONS INFORMATION
POWER SUPPLIES
The SSM-212S/SSM-2126 is designed to use either a dual ±6 V
or single + 12 V supply, with a tolerance of ± 10%. Internal reference points on the IC and a 6 V reference, generated on-chip,
are brought to external pins. When operated in dual supply
mode, the reference inputs (labeled VREF) are connected .to the
external ground. In single supply mode, the internal 6 V reference (labeled VRO) is wired to the VREF pins, providing a
pseudoground reference. In either mode, the internal reference
VRO should be decoupled with a 100 IJ-F electrolytic capacitor
in parallel with a 0.1 IJ-F ceramic capacitor.
Dual supply mode offers the highest fidelity operation and eliminates the necessity for input and output decoupling capacitors.
All signals are ground referenced in dual supply mode, allowing
de coupling of the inputs and outputs. Additionally, the power
on settling time is reduced when operating with dual supplies.
In single supply mode, decoupling capacitors are required, as
the signals are referenced to the +6 V pseudoground reference.
Any noise introduced onto the V REF line will appear at the output, so careful decoupling of the reference is required to maintain excellent noise and distortion performance. The 100 IJ-F
VREF decoupling capacitors should be placed close to the VRO
pin (Pin 23), and 0.1 IJ-F capacitors close to each VREF pin.

7-130 SPECIAL FUNCTIDN AUDIO PRODUCTS

DOLBY LEVEL
The discrete implementation of Dolby Pro-Logic Surround used
a Dolby'level of 500 mY. To maintain high audio quality and
excellent signal-to-noise ratio, the SSM-i12S/SSM-2126 was designed to operate with a 500 mV Dolby level. With this level,
the SSM-212S/SSM-2126 provides 87 dBd SNR (CCIR2K1ARM)
and 16 dB of headroom. In addition, the SSM-212S/SSM-2126
is capable of operation to the Pro-Logic specification at a Dolby
level of 300 mY, with the result of reduced SNR and increased
headroom. At the 300 mV level, SNR is typically 83 dBd with
20 dB of headroom. Either way, total dynamic range of the
device is 103 dB (0 dBd = 500 mY).
AUTOBALANCE
Left and right signals with an imbalance less than ±3.8 dB will
activate the autobalance circuitry when DM3 = I. Once activated, the circuit will correct up to 4 dB of balance error. Autobalance is available in both the Pro-Logic and stereo bypass
modes. When autobalance is OFF, the autobalance VCAs are
bypassed.
NOISE GENERATOR AND SEQUENCING
The SSM-212S/SSM-2126 noise source is best described as white
noise passed through a 0.2 Hz comb filter and a 10 kHz lowpass filter. Thus, the noise is comprised of separate equalamplitude peaks spaced at 0.2 Hz apart, as shown in Figure 8.
Figure 9 shows overall frequency response of the filtered noise
source.

REV. 0

SSM-2125/sSM-2126

n
.J \.
0.2

n

J \. J \.
0.4

For systems that are not microprocessor controlled, Figure 10
suggests one option (0 implement automatic noise sequencing
using standard logic. The CD4060 (or equivalent), although only
partially used, was selected since it contains a clock and 2-bit
binary counter on-chip. The timing interval is set by:

n

n

n

J\

J \

J\

1.0

1.2

0.8

0.6

where 2RI < R2 < IOR I .
The values shown in Figure 10 will provide a frequency of
2.9 Hz. One half of a CD4556 can be used to drive LED panel
indicators if desired, as shown.

FREQUENCY - Hz

Figure 8. Comb-Filtered Noise Source Characteristics

FUNCTIONAL MODES
The SSM-2125/SSM-2126 uses a positive logic system, whereby
a voltage greater than 2.4 V above LREF is considered a "I,"
and voltage levels between LREF and 0.8 V are considered a
"0." Tables II and III provide truth tables for logic inputs DMI
through DM4, and CMI and CM2. "Dolby 3" mode, which
disables surround steering, is available as shown. Normal operating mode for the decoder is with a .. I" on all logic inputs.
This provides 4-channellogic, autobalance ON, and center normal mode. Internal pullups will automatically set the chip into
this state if the inputs are left unconnected.

10kHz
FREQUENCY

Figure 9. Overall Frequency Response of Filtered
Noise Source

•

Vee
Vee

Vee

e1

e.

~O.1!'F

U1
11

1.

~

~

.3
TBo

LED3

CENT

•• ••

TBo

TBo

LEQ4

.0

TBo

He

Q4

P1

LED2

LEFT

~ O.111F
16

LEo1

Q5

-=-

"

RST

06
07

as
Q9

01.
01'
013
01.
PO

PO
4060

••

51k!!

-=-

,.
1.
13
1

Ne

He
He
He
He

L..f---------

'--t---------

TO DM4(SSM-2125/SSM-21261
TO DM3(SSM-2125/SSM-2126)

Ne

,.

Ne
NC

Ne

.,

NC

C3
1,.F

He

Me '" NO CONNECT

Figure 70. Automatic Noise Sequencing Circuit

REV. 0

SPECIAL FUNCTION AUDIO PRODUCTS 7-131

SSM-2125/sSM-2126 .
Table U. Control States for DMl-DM4

Table DI. Center Channel Functional Modes

DMl

DM2

DM3

DM4

Operating State

CMl

CM2

Mode

I

I

I

I

I

I

0

I

0
0
I
I

0
I
0
I

Center Channel Off
Center Channel Wideband
Phantom Center Channel
Normal Center Mode

I

0

I

I

I

0

0

I

0
0
0
0
0
0
0

I
I
I
I
0
0
0

I
I
0
0

I
0
I
0
I
0
0

Dolby 4-Channel ("Pro-Logic"),
Autobalance On
Dolby 4-Channel ("Pro-Logic"),
Autobalance Off
Dolby 3-Channel ("Dolby 3"),
Autobalance On
Dolby 3-Channel ("Dolby 3"),
Autobalance Off
Surround Channel Noise
Right Channel Noise
Center Channel Noise
Left Channel Noise
Mute
Stereo Bypass, Autobalance On
Stereo Bypass, Autobalance Off

X
I
0

7-132 SPECIALFUNCnONAUDIOPRODUCTS

REV. 0

High Common-Mode Rejection
Differential Line Receiver
SSM-2141 I

1IIIIIIII ANALOG

WDEVICES

FEATURES

GENERAL DESCRIPTION

• High Common-Mode Rejection
DC ...••••••.••••••••••••.••••••••••••••.••••••••••••••.•.•••••••••••.•• 100dB Typ
60Hz .................................................................. 100dB Typ
20kHz •••••••••••••••••.•••••••.••••••••••••.•••••••••••••••••••.••••••• 70dB Typ
40kHz •.•••.•••••••••••••••••.••.•..••••••.••••••..•.•••••.••••...••••.• 62dB Typ
• Low Distortion .................................................. 0.001% Typ
• Fast Slew Rate ................................................. 9.5V/~s Typ
• Wide Bandwidth .................................................. 3M Hz Typ
• Low Cost
• Complements SSM-2142 Differential Line Driver

The SSM-2141 is an integrated differential amplifier intended to
receive balanced line inputs in audio applications requiring a high
level of noise immunity and optimum common-mode rejection.
The SSM-2141 typically achieves 1OOdB of common-mode rejection (CMR), whereas implementing an op amp with four offthe-shelf precision resistors will typically achieve only 40dB of
CMR - inadequate for high-performance audio.

APPLICATIONS
• Line Receivers
• Summing Amplifiers
• Buffer Amplifiers - Drives 6000 Load

The SSM-2141 achieves low distortion performance by maintaining a large slew rate of 9.5V/l1s and high open-loop gain.
Distortion is less than 0.0020/0 over the full audio bandwidth. The
SSM-2141 complements the SSM-2142 balanced line driver.
Together, these devices comprise a fully integrated solution for
equivalent transformer balancing of audio signals without the
problems of distortion, EMI fields, and high cost.
Additional applications for the SSM-2141 include summing signals, differential preamplifiers, and 6000 low distortion buffer
amplifiers.

ORDERING INFORMATION
PACKAGE

OPERATING
TEMPERATURE
RANGE

PLASTIC
s-PIN
SSM2141P

XINO"

PIN CONNECTIONS

REFERENCE
-IN

.IN

a-PIN
PLASTIC MINI-DIP
(P-Suffix)

FUNCTIONAL DIAGRAM

-IN

25""

2

SENSE

OUTPUT

L..--f'CO -VEE
+IN

REV. A

3

25""

REFERENCE

SPECIAL FUNCTION AUDIO PRODUCTS 7-133

•

SSM-2141
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Volt~ge ., ..........,...... ~ ... ,~.: ...... ,~ .................... ~: ......... ±18V
Input Voltage (Note 1) ....................... :............... Supply Voltage
Output Short-Circuit Duration ........................:....... Continuous
StorageTemperature Range
P Package .......... :.................. ,................... -65°C to +150°C
Lead Temperature (Soldering, 60 sec) ........................ +300°C
Junction Temperature .................................................. +1.50°C
Operating Temperature Range ........................ -40°C to +85°C

PACKAGE TYPE

UNITS

B·Pin Plastic DIP (P)

103

NOTES:
1. For supply voltages less than ±lBV, the absolute maximum input voltage is
equal to the supply voltage.
2. ajA is specified forworstcase mounting conditions, i.e., ajA is specifledfordevice
in socket for P-DIP package.

ELECTRICAL CHARACTERISTICS at V s = ±18V ~r A = +25°C, unless otherwise noted.
SSM-2141
PARAMETER

SYMBOL

CONDITIONS

Offset Voltage

Vos

VCM=OV

MIN
-1000

No Load, Y'N = ±10V, Rs = 00

Gain Error
Input Vonage. Range

IVR

(Note 1)

Common-Mode Rejection

CMR

VcM =±10V

Power Supply Rejection Ratio

PSRR

Vs =HiVtO±lBV

Output Swing

Vo

RL = 2kO

Short-Circuit Curr.ent Limit.

Ise

Output Shorted To Ground

Small-Signal Bandwidth (-3dB)

BW

RL = 2kO

Slew Rate

SR

RL = 2kO

Total Harmonic
Distortion

THO

RL = 100kO
RL = 6000.

Capacitive Load Drive Capability

CL

No Oscillation

Supply Current

ISY

No Load

TYP

MAX

25

1000

0.001

0.01

%

V

±10

BO

100

±13

±14.7

0.7

dB
15

V

+451-15

mA

MHz

3
6

UNITS

9.5
0.001
0.01

%

300
2.5

pF
3.5

mA

TYP

MAX

UNITS

200

2500

0.002

0.02

NOTE:
1. Input voltage range guaranieed by CMR test.
Specifications subject to change; consult latest data sheet.

ELECTRICAL CHARACTERISTICS at V s = ±18V. -40°C S T AS +85°C.
SSM-2141
PARAMETER
OIIset Vonage

SYMBOL
Vos

CONDITIONS
VCM=OV

Gain Error

No Load, Y'N = ±10V, Rs = 00

Input Voltage Range

IVR

(Note 1)

Common-Mode Rejection

CMR

VCM =±10V

Power Supply Rejection Ratio

PSRR

Vs ·HiVtO±lBV

Output Swing

Vo

RL ·2kO

MIN
-2500

%

V

±10
75

90

±13

±14.7

1.0

Slew Rate

SR

RL =2kO

9.5

Supply Current

ISY

No Load

2.6

dB
20

V

4.0

mA

NOTE:
1. Input voltage range guaranteed by CMR test.
Specifications subject to change; consult latest data sheet.

7-134 SPECIAL FUNCTION AUDIO PRODUCTS

REV. A

SSM-2141
TYPICAL PERFORMANCE CHARACTERISTICS Continued

LARGE-SIGNAL TRANSIENT
RESPONSE

SMALL-SIGNAL TRANSIENT
RESPONSE

TA = +25°C
Vs = ±15V

TA =+25°C
Vs=±15V

COMMON-MODE REJECTION
vs FREQUENCY

12.

~~~1~5°C

".

iD
~

~

~

;;J
a:

l!I
!i1

iD

••
••7.

~
Z

0

~
;;J
a:

60

':l

5.

50

~llW~~~~~~~llW~WW

1

10

100

lk

10k

100k

1M

iii

111111111
-PSRR

.

3.

2.
,
•,

10

100

FREQUENCY (Hz)

lk

10k

lOOk

1M

FREQUENCY (Hz)

DYNAMIC INTERMODULATION
DISTORTION vs FREQUENCY

TOTAL HARMONIC DISTORTION
vs FREQUENCY

~:c::,",,:,ccAP
~J _?, ~~ ~~~~0,,'~I.B~,5
,.,

,

..-._-----,

fi!croio

PP.[CI5WK-Olt1(i':!

1 0.1,.
:

.

1IIIIIm

60

40

~

,.

••
7.••

a:

w

Y~I~II~15V

'00

I!:

iil

••
""u 3.
2.
Z

•

~~~1~25°C

".

VS=±15V

'00

0
0

POWER SUPPLY REJECTION
vs FREQUENCY

12.

,,,,,C;RL~60~
t

/,"':

'-+'~r-"--'

:~~~~~:~~

TA=+25~C

vs

fRf:udiz")
0--

Vs =±15V
Ay =-1

l .''''.

1.

00

,:

C-o~~--,-~,,:-~~==:-"':

I

\ ,(.t'JA1 2k - .___ ~~ ___.._ _ _ _l!""'''''_ _ _ _ _
-_'~_·-_·'_-_-.Ji50k'U'

REV. A

SPECIAL FUNCTION AUDIO PRODUCTS 7-135

•

SSM..2141
TYPICAL PERFORMANCE CHARACTERISTICS Continued

INPUT OFFSET VOLTAGE
vs TEMPERATURE

...

1GOO

.

CLOSED-LOOP GAIN
vsFREQUENCY

,

50 rTTTTT..--nT1rmr-'TT1nmr..,.,."",r-rTm,.

••I."IIV

±i!~·c

f- Ys·±15Y I-++IHII--++HHII--hI-HllH+HIHi

40

CLOSED-LOOP
OUTPUT IMPEDANCE
vs FREQUENCY

T~~Wb

VS_±15Y

..

aoH-ttlIHI--++tHlll--HHIlIII-+f+HjH+ltHi

Ii

i

- '"

.......

8 ,. I--+ttlIlIHHlIltl--t1ft11l1H-l-tlllll,-tj-H/III

I -1.

.......

----

aoH+HIIIII--++tIHB--++HHllr-+H-liIH-++IHI

H-ttlIIII-++t!HI--HHHlI-+f+HjH-+N:HII

.... H+HIIII-++tIHB--++

.-

0
ZS 50 75
TEMPERATURE ("C)

1DO

125 150

100

1k

10k

,.

1M

10M

100

.

'.~"IIV
, f- ....

••1.,,':'

. . . 00

,.,...

V,.:t15Y



ys=I:t15Y

-12.5

l

VI. il2Y
-10.0

§
~
.....
ys.Jv
I
!;

•• .1... -

-7.S

i

.~--~----~----~----~
±5
±10
±11

•

SUPPLY VOLTAGE M

7.., 136 SPECIAL FUNCTION AUDIO PRODUCTS

••

T.., =+25'"<:

&

T'-

12
18
M
~
OUTPUT SOURCE CURRENT (mA)

H

I
• ••1",.

....5

••

TA:II+2rC

-2

J

....
-6
....
-10
OUTPIIT SINK CURRENT (mAl

-12

REV. A

SSM-2141
TYPICAL PERFORMANCE CHARACTERISTICS Continued

LOW FREQUENCY
VOLTAGE NOISE

VOLTAGE NOISE DENSITY
vs FREQUENCY
'20

if

T..,=+2S"C
Vs_:t:15V

.00

-

iI :

1\

~

g
>

..
20

••

+1,1V

-ov
--111V

~

••

0.1 TO 10Hz PEAK-To-PEAK NOISE

'00
FREQUENCY (HI)

••

'Ok

VOLTAGE NOISE FROM
OT01kHz

VOLTAGE NOISE FROM
OTO 10kHz

+1C1!tV
-OV
- -10IlV

TA=+25·C
Vs=±15V
NOTE: EXTERNAL AMPLIFIER GAIN = 1000;
THEREFORE, VERTICAL SCALE = 1C1!tV/DIV.

SLEW RATE TEST CIRCUIT

TA=+25·C
Vs =±15V
NOTE: EXTERNAL AMPLIFIER GAIN = 1000;
THEREFORE, VERTICAL SCALE = 1C1!tV/DlV.

APPLICATIONS INFORMATION
The SSM-2141 represents a versatile analog building block. In
order to capitalize on fast settling time, high slew rate, and high
CMR, proper decoupling and grounding techniques must be
employed. Fordecoupling, place O.1IlF capacitor located within
close proximity from each supply pin to ground.

.15V

>--F-_OVour

MAINTAINING COMMON·MODE REJECTION
In order to achieve the full common-mode rejection capability of
the SSM-2141, the source impedance must be carefully controlled. Slight imbalances of the source resistance will result in
a degradation of DC CMR - even a 50 imbalance will degrade
CMR by 20dB. Also, the matching of the reactive source impedance must be matched in order to preserve theCMRR over frequency.

-1SY

REV. A

SPECIAL FUNCTION AUDIO PRODUCTS 7-137

•

APPLICATION CIRCUITS

SSM-2141

It,

Eo=Eo-E,

FIGURE 1: PrepisioriWfte/-I
E,o-,,+-.../IIII'---'

FIGURE 3: Precision Summing Amplifier

FIGURE 4: Precision Summing Amplifier with Gain

>--f'.....-o~TPUT

FIGURE 5: Suitable instrumentation amplifier requirements
can be addressed by using an input stage consisting of Al'
A2' R, and R2 •

7.,..138 SPECIAL FUNCTION AUDIO PRODUCTS

REV. A

1IIIIIIII ANALOG

WDEVICES
FEATURES
Transformer-Like Balanced Output
Drives 10 V RMS Into a 600 0 Load
Stable When Driving Large Capacitive Loads and Long
Cables
Low Distortion
0.006% typ 20 Hz-20 kHz, 10 V RMS into 600 0
High Slew Rate

Balanced Line Driver
SSM-2142 I
FUNCTIONAL BLOCK DIAGRAM
V,N

>-w..-o .OUT FORCE
.OUTSENSE

15 V/lJ.s typ

-OUT SENSE

Low Gain Error
(Differential or Single-Ended); 0.7% typ
Outputs Short-Circuit Protected
Available In Space-Saving 8-Pin Mini-DIP Package
Low Cost
APPLICATIONS
Audio Mix Consoles
Distribution Amplifiers
Graphic and Parametric Equalizers
Dynamic Range Processors
Digital Effects Processors
Telecommunications Systems
Industrial Instrumentation
Hi-Fi Equipment

GENERAL DESCRIPTION
The SSM-2142 is an integrated differential-output buffer amplifier that converts a single-ended input signal to a balanced output signal pair with high output drive. By utilizing low noise
thermally matched thin film resistors and high slew rate amplifiers, the SSM-2142 helps maintain the sonic quality of audio
systems by eliminating power line hum, RF interference, voltage
drops, and other externally generated noise commonly encountered with long audio cable ruils. Excellent rejection of
common-mode noise and offset errors is achieved by laser
trimming of the onboard resistors, assuring high gain accuracy.
The carefully designed output stage of the SSM-2142 is capable
of driving difficult loads, yielding low-distortion performance
despite extremely long cables or loads as low as 600 n, and is
stable over a wide range of operating conditions.

REV. A

>+"VIII.....o - OUT FORCE

ALL RESISTORS 3Ok1l
UNLESS OTHERWISE
INDICATED
GND

Based on a cross-coupled, electronically balanced topology,
the SSM-2142 mimics the performance of fully balanced
transformer-based solutions for line driving. However, the SSM2142 maintains lower distortion and occupies much less board
·space than transformers while achieving comparable commonmode rejection performance with reduced parts count.
The SSM-2142 in tandem with the SSM-2141 differential receiver establishes a complete, reliable solution for driving and
receiving audio signals over long cables. The SSM-2141 features
an Input Common-Mode Rejection Ratio of 100 dB at 60 Hz.
Specifications demonstrating the performance of this typical system are included in the data sheet.

SPECIAL FUNCTION AUDIO PRODUCTS 7-139

•

(Vs = ±18 V, -40·C s TA s +85'C, operating in differentiai mode

SSM-2142 - SPEC IFI CAli 0NS ;:I=S1~~~~.~ed otherwise. Typical characteristics apply to operation at
Parameter

Symbol

INPUT IMPEDANCE

ZIN

INPUT CURRENT

lIN

Conditions

Typ

Min

Max

10
VIN = ±7.071 V

±750
5.8

GAIN, DIFFERENTIAL
GAIN, SINGLE-ENDED

Single-Ended Mode

GAIN ERROR, DIFFERENTIAL

RL = 600 n

±900

5.98

5.7

Units
kn
I1A
dB

5.94

dB

0.7

2

%

POWER SUPPLY REJECTION
RATIO STATIC

PSRR

Vs = ± 13 V to ± IS V

60

SO

dB

OUTPUT COMMON-MODE REJECTION

OCMR

See Test Circuit; f - I kHz

-38

-45

dB

OUTPUT SIGNAL BALANCE RATIO

SBR

See Test Circuit; f = I kHz

-35

-40

dB

TOTAL HARMONIC DISTORTION
Plus Noise

THD+N

20 Hz to 20 kHz,
Vo = 10 V rms, RL = 600 n

0.006

%

VIN = 0 V, 0 dBu = 0.775 V rms
CLIP Level = 10.5 V rms

-93.4

dBu

+22.6

dBu

SIGNAL-TO-NOISE RATIO

SNR

HEADROOM

HR

SLEW RATE

SR

OUTPUT COMMON·MODE
VOLTAGE OFFSET!

Voos

RL = 600 n

-250

25

250

mV

DIFFERENTIAL OUTPUT
VOLTAGE OFFSET

VOOD

RL = 600 n

-50

15

50

mV

VIN = ±7.071 V

±13.S

±14.14

45

50

55

n

5.5

7.0

mA

IS

DIFFERENTIAL OUTPUT
VOLTAGE SWING
OUTPUT IMPEDANCE

Zo

SUPPLY CURRENT

Isy

OUTPUT CURRENT, SHORT CIRCUIT

Isc

Unloaded, VIN = 0 V

60

Vll1s

V

70

rnA

NOTE
lQutput common~mode offset voltage can be removed by inserting de blocking capacitors in the sense lines. See the Applications Information.
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ±IS V
Storage Temperature . . . . . . . . . . . . . . . . -60°C to + 150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . + 300°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . + 150°C
Operating Temperature Range . . . . . . . . . . . -40°C to +S5°C
Output Short Circuit Duration (Both Outputs) ..... Indefinite
*Srresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. These are stress ratings only; the functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.

PIN CONNECTIONS
S-Pin Plastic DIP
(P Suffix)
8·Pin Cerdip

16-Pin SOIC
(S SuffIX)

(Z SuffIx)
NC

-FORCE 3

4 + FORCE

-SENSE 4
GROUND 5

ORDERING GUIDE
Model

Operating
Temperature Range

Package
Option l

SSM2142P
SSM2142Z
SSM2142S 2

-40°C to +85°C
-40°C to +S5°C
-40°C to +S5°C

Plastic DIP
Cerdip
SOIC

NOTES
IPor outline information see Package Information section.
'Por availability of SOle package, contact your local sales office.

7-140 SPECIAL FUNCTION AUDIO PRODUCTS

REV. A

SSM-2142
3000

8000
V,N

=IOV p-p

V.=OV

SBR = 20 LOG AVOUT
V,N

OCMR = 20 LOG AVOUT
VeMR

Figure 2. Signal Balance Ratio (BBC Method) Test Circuit

Figure 1. Output CMR Test Circuit

Typical Performance Characteristics
140
120

i~
I 100

~

"~

-Ps~

~

v.

~+~'c'

= :t:18V
RL =60CK2

DIFF.UODE

C'\.'% DISTORTION

0.01% DISTORTIO:\

~

~

~
a:
~

'TA

=
AVs =:t.1V

~

'II

12

I't=~~·b"
Vs :t18V

" I'- :::::~

40

20

o

o

10k

lk

100

10

10

lOOk

20

FREQUENCY - Hz

Figure 3. Power Supply Rejection vs. Frequency
12

TA

~

>

10

Il!I

V
L

l/

V

~'r

~

g
/
,2

...z
I

::>

u

=OV
NO LOAD

5.5

~

5.0

~

......::>

./

Frequency

~+25'C'

W

II:
II:

VS.

t-- V,N

E

~

---

4.5

III

4.0

.10

.18

SUPPLV VOLTAGE - Voila

Figure 5. Output Voltage Swing vs. Supply Voltage

REV. A

6.0

c

0.1% DISTORTION

I

TA

.J'

FREQ. :& 20kHz

I

100

50

Figure 4. Maximum Output Voltage Swing
6.5

~ +25'c '
t-~I~;.=E

30
FREQUENCY - kHz

3.5

.2

.10

.14

SUPPLY VOLTAGE - Voila

Figure 6. Supply Current VS. Supply Voltage

SPECIAL FUNCTION AUDIO PRODUCTS 7-141

SSM"72142. "
THD PERFORMANCE
The following data, taken from the TH.D test circuit on an' Audio Precision System One using the internal 80 kHz noise filter,
demonstrates the typical performance of a balanced-pair system
based on the SSM-2142/SSM-2141 chip set. Both differential
and single-ended modes of opemtion are shown, under a number of output load conditions which simulate various application
situations. Note also that there is no adverse effect on system
performance when using the optional series feedback capacitors,
which reject dc cable offsets in order to IillIintain optimal ac
noise rejection. The large signal transient response of the system
to a 100 kHz square wave input is also shown, demonstrating
the stability of the SSM-2142 under load.
Vo ;= 10 V .ml, WITH 500 FEET CABLE
A:Rl=R2=RL='"
B: R1 = R2 = 600 0, RL = '"
C: Rl = R2 = "', RL = 600 0
D: R1 = R2 = RL = "', WITH SERIES FEEDBACK CAPACITORS

Figure 9. THD+N vs. Frequency at Point B
(Differential Mode)

·USED ONLV IN THO PLOTS AS NOTED.
ALL CABLE MEASUREMENTS USE BELDEN 8451 CABLE.

Figure 7. THO Test Circuit

Vo = 10V .ml, R2 = OO,RL = '"
A: R1 = 600 0, WITH 250 FEET CABLE
B: Rl = ", NO CABLE

Figure 10. THD+N vs. Frequency at Point A
(Single Ended)

Vo = 10 V 'ms, NO CABLE
A: Rl = R2 = RL = "
B: Rl = R2 = 6000, RL ="
C: Rl = R2 = ", RL 600 0

=

Figure 8. THD+N vs. Frequency at Point
(Differential Mode)

B

Vo = 10 V .ms, NO CABLE
A: R1 = R2 = ", RL = 600 0

Figure ". THD+ N vs. Frequency at Point C
(SSM-2141 Output)

7-142 SPECIAL FUNCTION AUDIO PRODUCTS

REV. A

SSM-2142
II,

I

III··

I

-+

IU

.1' ---+-

•I

rl

'

...

I

II
II
-'I

•

WI

i~

.... .

.

,

~

I

.

·I---~

'"

. ... I·

I
I

I

.--

H.

I

I

1111

' II

I

-t--

,

II

I

I

--

II

Figure 12. 100 kHz Square Wave Observed at Point B
(Differential Mode). Va = 10 V rms, R1 = R2 = x, RL = 600 a

.I.I~I
~-

u-

•

.

II,

-

IH

,

.'11...

' ..

---

lin

I

:

l'

,- ==

111
... '11.

..

1.

,

...
t--+II"

I

i

•

Figure 13. 100 kHz Square Wave at Point B (Differential
Mode). Va = 10 V rms, R1 = R2 = co, RL = 600 a, with
Series Feedback Capacitors
+15V

V,N

Figure 14. Typical Application of the SSM-2142 and
SSM-21411SSM-2143

APPLICATIONS INFORMATION
The SSM-2142 is designed to provide excellent common-mode
rejection, high output drive, and low signal distortion and noise
in a balanced line-driving system. The differential output stage
consists of twin cross-coupled unity-gain buffer amplifiers with

REV. A

on-chip 50 n series damping resistors. The impedances in the
output buffer pair are precisely balanced by laser trimming
during production. This results in the high gain accuracy
needed to obtain good common-mode ;"oise rejection, and
excellent separation between the offset error voltages common to
the cable pair and the desired differential input signal. As shown
in the test circuit, it is suggested that a suitable balanced, high
input-impedance differential amplifier such as the SSM-2141 or
SSM-2143 be used at the receiving end for best system performance. The SSM-2143 receiver output is configured for a gain
of one half following the 6 dB gain of the SSM-2142, in order to
maintain an overall system gain of unity.
In applications encountering a large dc offset on the cable or
those wishing to ensure optimal rejection performance by
avoiding differential offset error sources, dc blocking capacitors
may be employed at the sense outputs of the SSM-2142. As
shown in the test circuit, these components should present as
little impedance as possible to minimize low-frequency errors,
such as 10 ILF NP (or tantalum if the polarity of the offset is
known).
SYSTEM GROUNDING CONSIDERATIONS
Due to ground currents, supply variations, and other factors,
the ground potentials of the circuits at each end of a signal cable
may not be exactly equal. The primary purpose of a balancedpair line is to reject this voltage difference, commonly called
"longitudinal error." A measure of the ability of the system to
reject longitudinal error voltage is output common-mode
rejection. In order to obtain the optimal OCMR and noise
rejection performance available with the SSM-2142, the user
should observe the following precautions:

1. The quality of the differential output is directly dependent
upon the accuracy of the input voltage presented to the
device. Input voltage errors developed across the impedance
of the source must be avoided in order to maintain system
performance. The input of the SSM-2142 should be driven
directly by an operational amplifier or buffer offering low
source impedance and low noise.
2. The ground input should be in close proximity to the singleended input's source common. Ground offset errors encountered in the source circuitry also impair system performance.
3. Make sure that the SSM-2142 is adequately decoupled with
0.1 ILF bypass capacitors located close to each supply pin.
4. Avoid the use of passive circuitty in series with the SSM2142 outputs. Any reactive difference in the line pair will
cause significant imbalances and affect the gain error of the
device. Snubber networks or series load resistors are not
required to maintain stability in SSM-2142-based systems,
even when driving signals over extremely long cables.
5. Efforts should be made to maintain a physical balance in the
arrangement of the signal pair wiring. Capacitive differences
due to variations in routing or wire length may cause unequal
noise pickup between the pair, which will degrade the system
OCMR. Shielded twisted-pair cable is the preferred choice in
all applications. The shield should not be utilized as a signal
conductor. Grounding the shield at one end, near the output
common, avoids ground loop currents flowing in the shield
which increase noise coupling and longitudinal errors.

SPECIAL FUNCTION AUDIO PRODUCTS 7-143

•

SSM-2142
THE CABLE PAIR
The SSM-2142 is capable of driving a 10 V rms signal into
600 n and will remain stable despite cable capacitances of up to
0.16 ,...F in either balanced or singJe-ended configurations. Lowimpedance shielded audio cable such as the standard Belden
8451 or similar is recommended, especiaJJy in applications
traversing considerable distances. The user is cautioned that
the so-called "audiophile" cables may incur four times the
capacitance per unit length.of the standard industrial-grade
product. In situations of extreme load and/or distance, adding
a second parallel cable allows the user to trade off half of the
total line resistance against a doubling in capacitive load.
SINGLE-ENDED OPERATION
The SSM-2142 is designed to be compatible with existing
balanced-pair interface systems. Just as in transformer-based
circuits, identical but opposite currents are generated by the
output pair which can be ground-referenced if desired and
transmitted on a single wire. Single-ended operation requires
that the unused side of the output pair be grounded to a solid
return path in order to avoid voltage offset errors at the nearby
input common. The signal quality obtained in these systems is
directly dependent on the quality of the ground at each end of
the wire. Also note that in single-ended operation the gain
through the device is still 6 dB, and that the SSM-2142 incurs

7-144 SPECIAL FUNCTION AUDIO PRODUCTS

no significant degradation in signal distortion or output drive
capability, although the noise rejection inherent in balanced-pair
systems is lost.
POWER SUPPLY SEQUENCING
A problem occasionally encountered in the interface system
environment involves irregular application of the supplies. The
user is cautioned that applying power erraticaJIy can inadvenently bias pans of the circuit into a latchup condition. The small
geometries of an integrated circuit are easily breached and damaged by shon-risetime spikes on a supply line, which usually
demonstrate considerable overshoot. The questionable practice
of exchanging components or boards while under power can
create such an undesirable sequence as well. Possible options
which offer improved board-level device protection include:
additional bypass capacitors, high-current reverse-biased steering
diodes between both supplies and ground, various transient
surge suppression devices, and safety grounding connectors.
Likewise, power should be applied to the device before the output is connected to "live" systems which may carry voltages of
sufficient magnitude to turn on the output devices of the SSM2142 and damage the device. In any case, of course, the user
must always observe the absolute maximum ratings shown in the
specifications.

REV. A

r'IIII ANALOG

- 6 dB Differential
Une Receiver
SSM-2143 I

WDEVICES
FEATURES
High Common-Mode Rejection
DC: 90 dB typ
60 Hz: 90 dB typ
20 kHz: 85 dB typ
Ultralow THO: 0.0006% typ @ 1 kHz
Fast Slew Rate: 10 V//J.s typ
Wide Bandwidth: 7 MHz typ (G = 112)
Two Gain Levels Available: G
112 or 2
Low Cost

FUNCTIONAL BLOCK DIAGRAM
12kQ

61<0

-IN

SENSE
V+
VOUT

=

V12kQ

+IN

GENERAL DESCRIPTION
The SSM-2143 is an integrated differential amplifier intended to
receive balanced line inputs in audio applications requiring a
high level of immunity from common-mode noise. The device
provides a typical 90 dB of common-mode rejection (CMR),
which is achieved by laser trimming of resistances to better than
0.005%.
Additional features of the device include a slew rate of 10 V/ ",s
and wide bandwidth. Total harmonic distortion (THO) is less
than 0.004% over the full audio band, even while driving low
impedance loads. The SSM-2143 input stage is designed to handle input signals as large as +28 dBu at G = 112. Although primarily intended for G = 112 applications, a gain of 2 can be
realized by reversing the + IN/ - IN and SENSEIREFERENCE
connections.
When configured for a gain of 112, the SSM-2143 and SSM-2142
Balanced Line Driver provide a fully integrated, unity gain solution to driving audio signals over long cable runs.

REFERENCE

SSM-2143

PIN CONNECTIONS
Epoxy Mini-DIP (P Suffix)
and
SOIC (S Suffix)

NC = NO CONNECT

This is an abridged version of the data sheet. To obtain a
complete data sheet, contact your nearest sales office.

REV. 0

SPECIAL FUNCTION AUDIO PRODUCTS 7-145

•

(Vs.= ±15 Y: -~O°C T +85°C, G = 1/2, unless otheiWise specified.
SSM - 21-43 - SPECIFICAY-IONS TYPical
specifications apply at TA = +25°C.)
:5

Parameter

Symbol

Conditions

AUDIO PERFORMANCE
Total Harmonic Distortion Plus Noise
Signal-to-Noise Ratio
Headroom

THD+N
SNR
HR

o dBu =

DYNAMIC RESPONSE
Slew Rate
Small Signal Bandwidth

SR
BW_ 3dB

INPUT
Input Offset Voltage
Common-Mode Rejection

Power Supply Rejection
Input Voltage Range
OUTPUT
Output Voltage Swing
Minimum Resistive Load Drive
Maximum Capacitive Load Drive
Short Circuit Current Limit

VIOS
CMR

PSR
IVR

Vo

A :5

Min

VIN = IOV rms, RL = 10kO, f = I kHz
0.775 V rms, 20 kHz BW, RTI
Clip Point = 1% THD+N

Max

0.0006
-107.3
+28.0

%
dBu
dBu

10

V/lLs

7
3.5

MHz
MHz

6

VCM = 0 V, RTI, G = 2
VCM = ±IOV,RTO
f = de
f = 60 Hz
f = 20 kHz
f = 400 kHz
Vs =±6Vto±18V
Common Mode
Differential

-1.2

0.05

70

90
90
85
60
110
±15
±28

dB
dB
dB
dB
dB
V
V

±13

±14
2
300
+45, -20

V
kO
pF
rnA

-0.1

0.03

RL = 2 kO

90

Isc

REFERENCE INPUT
Input Resistance
Voltage Range

+1.2

0.1

18
±IO
Vs
ISY

Units

RL = 2 kO, CL = 200 pF
RL = 2 kO, CL = 200 pF
G = 112
G=2

GAIN
Gain Accuracy

POWER SUPPLY
Supply Voltage Range
Supply Current

Typ

±18
±4.0

±2.7

ox;

%
kO
V

±6
VCM = 0 V, RL =

mV

V
rnA

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . ±22 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . ±44 V
Output Short Circuit Duration . . . . . . . . . . . . . . . Continuous
Operating Temperature Range . . . . . . . . . . . . -40°C to + 85°C
Storage Temperature Range . . . . . . . . . . . . -65°C to + 150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . + 150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . + 300°C
Thermal Resistance
8-Pin Plastic DIP (P): OJA = 103, 0JC = 43 . . . . . . . . . oC/W
8-Pin sorc (S): OJA = 150,OJC = 43 . . . . . . . . . . . . oC/W

7-146 SPECIAL FUNCTION AUDIO PRODUCTS

ORDERING GUIDE
Model

Operating Temperature Range Package'

SSM-2143P -40°C to +85°C
SSM-2143S 2 -40°C to +85°C

8-Pin Plastic DIP
8-Pin sorc

lPor outline information see Package Information section.
2Contact sales office for availability.

REV. 0

Audio Dual Matched
NPN Transistor
SSM-2210 I

~ANALOG

WDEVICES
FEATURES
•
•
•
•
•
•
•

Very Low Voltage Noise •.•••.•.•••.• @ 100Hz,1nV/.,fHz MAX
Excellent Current Gain Match ............................ 0.5% TYP
Tight VBE Match (Vos) ...................................... 200~ V MAX
Outstanding Offset Voltage Drift ...•...•...... 0.03~V/oC TYP
High Gain-Bandwidth Product ..................... 200MHz TYP
LowCost
Direct Replacement For LM394BN/CN

ORDERING INFORMATION t
PACKAGE
PLASTIC
&-PIN
SSM2210P

so
B-PIN
SSM2210St

The SSM-221 0 is also an ideal choice for accurate and reliable
current biasing and mirroring circuits. Furthermore, since a current mirror's accuracy degrades exponentially with mismatches
of V BE'S between transistor pairs,Jhe low Vos of the SSM-221 0
will preclude offset trimming in most circuit applications.
The SSM-221 0 is offered in an 8-pin epoxy DIP and 8-pin SO, its
performance and characteristics are guaranteed over the extended industrial temperature range of -40°C to +85°C.

PIN CONNECTIONS
OPERATING
TEMPERATURE
RANGE

8-PIN
PLASTIC DIP
(P-Suffix)

XINO'

• XINO = -40·C to +85·C

t For availability on SO package, contact your local sales office.

8-PINSO
(S-Sufflx)

GENERAL DESCRIPTION
The SSM-2210 is a dual NPN matched transistor pair specificially designed to meet the requirements of ultra·low noise audio systems.
With its extremely low input base spreading resistance (rbb' is
typically 280), and high current gain (hFI; typically exceeds 600
@ Ic = 1mAl, systems implementing the SSM-221 0 can achieve
outstanding signal-to-noise ratios. This will result in superior
performance compared to systems incorporating commercially
available monolithic amplifiers.
The equivalent input voltage noise of the SSM-221 0 is typically
only 0.8nVtVl1zOverthe entire audio bandwidth of 20Hz to 20KHz.
Excellent matching of the current gain (~hFE) to about 0.5% and
low Vos of less than 50~ V (typical) make it ideal for symmetrically balanced designs which reduce high order amplifier harmonic distortion.
Stability of the matching parameters is guaranteed by protection diodes across the base-emitter junction. These diodes prevent degradation of Beta and matching characteristics due to
reverse biasing of the base-emitter junction.

REV. 8

ABSOLUTE MAXIMUM RATINGS
Collector Current (Ie) ....................................................... 20mA
Emitter Current (IE) .......................................................... 20mA
Collector-Collector Voltage (BVee) ............•........................ 40V
Collector-Base Voltage (8V CBO) ........................................ 40V
Collector-Emitter Voltage (8V CEO) ..................................... 40V
Emitter-Emitter Voltage (8V EE) .......................................... 40V
Operating Temperature Range ........ ,.............. -40°C to +85°C
Storage Temperature .................................... -65°C to + 125°C
Junction Temperature ................................... -65°C to + 150°C
Lead Temperature (Soldering, 60 sec) ........................ +300°C
PACKAGE TYPE

alA (NOTE 1)

alc

UNITS

8-Pin Plastic DIP (P)

110

50

·CIW

8-PinSO (S)

160

44

·CIW

NOTE:
1. 9jA is specified for worst case mounting conditions. I.e .• 9 JA is specified fordevice
in socket for P-OIP packages; 9.A is speCified for deVice soldered to printed
circuit board for SO packages. J

SPECIAL FUNCTION AUDIO PRODUCTS 7-147

7

SSM-2210
ELECTRICAL CHARACTERISTICS at VCB = 15V, 'c = 1OIlA, TA =25°C, unless otherwise. noted.
SSM·2210
SYMBOL

CONDITIONS

MIN

TYP

Current Gain

hFE

Ic=1mA (Note1)
Ic = 1011A

300
200

605
550

Current Gain Match

~hFE

10llASlcS1mA (Note2)

Noise Voltage Density

en

Ic=1mA,Vca=0 (Note3)
lo=10Hz
1.= 100Hz
1.= 1kHz
1.= 10kHz

Offset Voltage

Vos

Offset Voltage
Change VB Vca

~VoJ~Vca

Offset Vo~age Change
VB Collector Current

~VoJ~le

Breakdown Vo~ge

BVeEo

PARAMETER

MAX

UNITS

0.5

5

%

1.6
0.9
0.85
0.85

2

Vca=O
Ic=1mA

10

200

OSVcaSVMAX (Note4)
111ASlcS1mA (NoteS)

10

Vea=OV
1~ASleS1mA

nvrJRz

IlV

5

(NoteS)
40

V

Gain-Bandwidth Product

IT

le=10mA,VeE =10V

Collector-Base
Leakage Current

leBO

Vea=VMAl(

25

500

pA

Collector-Collector
Leakage Current

Icc

Vcc=VMAl( (Notes 6, 7)

35

500

pA

Collector-Emitter
Leakage Current

Ices

VeE=VMAl( (Notes 6, 7)
VaE=O

35

500

pA

Input Bias Current

la

le=1~A

50

nA

6.2

nA

0.2

V

Input Offset Current

los

le= 1011A

Collector Saturation
Voltage

VeEISAn

le=1mA
la= 100llA

Output Capacitance

200

0.05

COB

Vea =15V,I E=0

23

Bulk Resistance

raE

10IlASle,,10mA (NoteS)

0.3

Collector-Collector
capacitance

Ccc

Vcc=O

35

MHz

pF

1.6
pF

NOTES:

1. Current gain is guaranteed with Collector-Base Voltage (Vea) swept Irom 0 to
VMAX at the indicated collector currents.
2. Current Gain Match (~hFE) is defined as:
~hFE =

5. Measured at Ie ~ 1OIlA and guaranteed by design over the specified range of Ie'
6. Guaranteed by design.
7. Ice and leES are verified by measurement of leBO'

1OO(~la) (hFEmin)
Ic

3. Noise Voltage Density is guaranteed, but not 100% tested.
4. This is the maximum change in Vos as VeB issweptlrom OVto 40V.

7-148 SPECIAL FUNCTION AUDIO PRODUCTS

REV. B

SSM-2210
ELECTRICAL CHARACTERISTICS at VCB = 15V, -40°C S TA S +85°C, unless otherwise noted.
PARAMETER

SSM·2210
TYP

MAX

UNITS

220

~V

1
0.3

~vrc

Ic = 101lA

50

nA

Ic = 101lA

13

nA

150

pArC

SYMBOL

CONDmONS

MIN

Current Gain

hFE

Ic=lmA (Note t)
Ic = 101lA

300
200

Offset Voltage

Vos

VCB=O
Ic=lmA

Average Offset
Voltage Drift

TCVos

Vos Trimmed to Zero (Note 3)

Input Bias Current

IB

Input Offset Current

los

Input Offset
Current Drift

TClos

Ic = 101lA (Note4)

Coliector·Base
Leakage Current

Icee

VCB = VMAX

3

nA

Collector-Emitter
Leakage Current

ICES

VCE=VMAx'Vee=O

4

nA

Collector-Collector
Leakage Current

Icc

Vcc = VMAX

4

nA

1011A~lc~lmA,O~VCB~VMAX

0.08
0.03

(Note 2)

40

NOTES:

1. Current gain is guaranteed with Collector-Base Voltage (VCB) swept from 0 to
VMAX at the indicated collector current.
Vos VBE)' T = 298K for TA = 25°C.
2. Guaranteed by Vos test (TCVos = T"
3. The initial zero offset voltage is established by adjusting the ratio of ICl to IC2 at
TA = 25°C. This ratio must be held to 0.003% over the entire temperature range.
Measurements are taken at the temperature extremes and 25°C.
4. Guaranteed by design.

•

TYPICAL PERFORMANCE CHARACTERISTICS

LOW FREQUENCY NOISE
(0.1 Hz TO 10 Hz)

NOISE FIGURE vs
COLLECTOR CURRENT

,.
,. \RS=1kn
\

EMmER·BASE
LOG CONFORMITY

15

TA =2PC
Fo .1kHz

13

~

"

11

i

..

!l§

ii'10

!! •

~

II
~

'-

t.la/DIY

_"s=1

•

0.001

0.2

/

ffi
~ 0.1
§

7

z 5

REV. B

Vea =ov

TA=+25~C

..3

--

-

0.01
0.1
COLLECTOR CURRENT (rnA)

-0.1
1.•

/

V

../
-

10 8

-

-

-

-

10 7
10 I
10 5
10 4
COUECTOR CURRENT (A)

-

10 3

SPECIAL FUNCTION AUDIO PRODUCTS 7-149

SSM-2210
TYPICAL PERFORMANCE CHARACTERISTICS
NOISE VOLTAGE DENSITY

NOISE VOLTAGE
DENSITY vs FREQUENCY

NOISE CURRENT
DENSITY vs FREQUENCY

vs COLLECTOR CURRENT
1.0

1000

~••+:C=

~;;

100

~

i

./

I

s

IC=lpA=

~

10

IC"~

"-

OU

~

......

g

!!l

,-

V
k

V
......

/

./

le=lmA

~

1

0.1
10

0.1

100

1k

10k

0.0
tOOk

0.01

o

9

..
~ ..
;;

s

!!l
~

~

.......

iz

~

900

C

"
..~

II
II

"u

"~.I,Okn

t--.

I--'"

0.01

~
I

/

~

"~

.
"
u

iiiil
0.01

600

sao
4DO

300

V

VoC=1I1A

/" /"
,/ / '
./

(EXCLUDES leBO)

200
100

III

0.001

./ V~

TOO

/

100k

le=lmAA

800

~ .25'e

300

10k

CURRENT GAIN

IJ.Io!I

+12S"C

1k

vs TEMPERATURE

400

0.1

100

900

I IIIIL~

IIII11

100

0.001

10

FREQUENCY (Hz)

500

200

. . . ,kD

o

IUI I

700

II!

I I

I~S.l00kn

Ye•• OY

900

f=1kHz

40

20

9DO

~
1111

L----''----'_--l._-'-_-"-_..J
0.1

CURRENT GAIN vs
COLLECTOR CURRENT

TOTAL NOISE vs
COLLECTOR CURRENT
100

12

COLLECTOR CURRENT (rnA)

FREQUENCY (Hz)

o

0.1

-75

-25

25

75

125

175

COLLECTOR CURRENT CmA)

COLLECTOR CURRENT (mA)

TEMPERATURE COC)

GAIN BANDWIDTH
vs COLLECTOR CURRENT

BASE·EMITIER·ON·
VOLTAGE vs COLLECTOR
CURRENT

SMALL·SIGNAL INPUT
RESISTANCE vs COLLECTOR
CURRENT

0.7

1000

,'.!!~~
VcE=5V

,/
0.6

".

~

/

~
I

IE

,/

:,....
0.'

~

l?-ou

:'
0.4

0.1
0.001

0.01

0.1

10

100

COLLECTOR CURRENT (mA)

7-150 SPECIAL FUNCTION AUDIO PRODUCTS

0.'0.001

0.01

0.1

COLLECTOR CURRENT (rnA)

10

0.01

0.1

1

10

100

COLLECTOR CURRENT (mA)

REV. B

SSM-2210
TYPICAL PERFORMANCE CHARACTERISTICS Continued
SMALL·SIGNAL OUTPUT
CONDUCTANCE vs
COLLECTOR CURRENT

SATURATION VOLTAGE
vs COLLECTOR CURRENT
10

1000

I

100

g
a

10

COLLECTOR·TO·BASE

LEAKAGE vs TEMPERATURE
100

~

10

~
w

~

"e
0

Iiu

/'

>

z

0

I

~

~
2

0.1

,

0.1

~

0.1

0.01
0.01

0.1

1

25

10

50

COLLECTOR· BASE

COLLECTOR·TO-COLLECTOR
CAPACITANCE vs COLLECTOR·
TO·SUBSTRATE VOLTAGE

CAPACITANCE vs
REVERSE BIAS VOLTAGE
40

75

100

COLLECTOR·TO·COLLECTOR
LEAKAGEvsTEMPERATURE

50

100

J

TA = +25'"C

TA =+25'"C
40

IL

a
I!l
~

~

1l

.,I

8

30

I!lz

o

30

~

"- ..........

u

:f
e

~

10

o

~

-

-

20

10

30

40

REVERSE BIAS VOLTAGE (VOLTS)

u

I

20

8

u

0.1
10

.

o

o

10

20

30

.

TA =+25"C

I
e
u

I

1.'

1.0

8
u

82

~ so
I!l 7.

"-

-

0.'

o

REV. B

o

.

50

25

10
30
40
REVERSE BIAS VOLTAGE (VOLTS)

I
e
u

125

TA=+25"C

I,
........

" "-

76
7.
7.

.

....... .......

70

66
50

100

EMITTER·BASE CAPACITANCE
vs REVERSE BIAS VOLTAGE

I

~

75
TEMPERATURE (OC)

84

~

\

0.01

~

40

COLLECTOR-TO-SUBSTRATE VOLTAGE (VOLTS)

2.'

~

II

/'

COLLECTOR·TO·COLLECTOR
CAPACITANCE vs
REVERSE BIAS VOLTAGE

'.0

/'

10

i

. \\.

,.5

TEMPERATURE (OCl

COLLECTOR CURRENT (rnA)

COLLECTOR CURRENT (rnA)

o

10

20

30

r-....

40

50

REVERSE BIAS VOLTAGE (VOLTS)

SPECIAL FUNCTION AUDIO PRODUCTS 7-151

SSM-2210
COMPENSAllQN
200Q O.001pF

+15V

1MO

"2

GAIN

=(~+1\
'"211101c1l ')
=(...!... • ...!... \R1+1

,A2 1~

-15V

R1 =19kn

R2 =1092n

FIGURE 1: A Low-Noise Wideband Amplifier

A VERY LOW-NOISE, WIDEBAND AMPLIFIER
Figure 1 illustrates a low-noise, wide-band amplifier consisting
of a high slew rate JFET amplifier, the OP-44, and a cascoded
differential preamplifier using the SSM-221 0 transistor pair. The
SSM-221 0 achieves extremely low input voltage noise performance (en ~ 0.7nV/v'RZ) via a large geometry transistor design
which minimizes the base-spreading resistance. This, however,
results in relatively higher collector-to-base capacitance (COB)
than ordinary small-signal transistors. For high gain stages, the
Miller effect of COB will limit the voltage gain bandwidth; resorting to a cascode configuration reduces the Miller feedback capacitance, improving stability, bandwidth, and reducing distortion due to base-width modulation. Additionally, cascoding does

7-152 SPECIALFUNCnONAUDIOPRODUCTS

not increase the noise figure of the overall amplifier system and
reduces the high order harmonic distortion.
The circuit in Figure 1 balances the impedance symmetrically in
the differential preamp. This serves to reject common-mode noise
injected from the power supplies.
Although the SSM-2210's transistors are closely matched, an
offset voltage error can still be created by imbalanced source
impedances. Accordingly, a precision low-power amplifier (OP97), configured as a noninverting integrator is implemented which
servos-out the offset voltage to less than 1001!V referred to the
input of the amplifier.

REV. B

SSM-2210
iLIJIIIIISEAII',Av::.:z. Uout:I8Up-p

!
I

'.1._

25 FEB 89 15:7&:011

. !
I

i

I~..,c~:~_:_;..-::_~. ~_. _._.~_-~·-=I·.:.... --- -_.-- •. ~:~ II

11 .
·.
·.
·. .

. __
FIGURE 2: Spectrum Analyzer Display of Wideband Amplifier
Noise Spectral Density. en Z 1.7n wtFfZ
Figure 2 illustrates the composite amplifier's low voltage noise
density of only 1.7nV/VRZ @ 1kHz. Figure 3 and Figure 4 show
the excellent pulse response and an extremely low distortion of
only 0.0015% over the audio bandwidth, respectively.

m o u_ _ _

2jo

FIGURE 5: D.I.M. vs Frequency
A special test was performed to check for dynamic or transient
intermodulation distortion. A square wave of 3.15kHz is mixed
with a sine wave probe tone, and the resulting intermodulation
distortion was found to be less than 0.002% (Figure 5). This is
an impressively low value considering the amplifier's gain of
26dB. Interestingly. the GBW product of the composite amplifier
was 63MHz which is much larger than that olthe OP-44 by itself.
This is made possible by the SSM-2210's cascoded preamplifier having a wide bandwidth and large signal gain.
The measured performance of this amplifier is summarized in
Table 1.

TABLE 1: Measured Performance of the Low-Noise Wideband •
Amplifier

FIGURE 3: Small-Signal Pulse Response

Slew-Rate

40V/IlS

Gain-Bandwidth

63.6 MHz

Input Noise Voltage Density @ 1kHz

1.7nV/VRZ

Output Voltage Swing

±13V

Input Offset Voltage

FIGURE 4: Total Harmonic Distortion vs Frequency

REV.B

SPECIAL FUNCTION AUDIO PRODUCTS 7-153

SSM-2210
500pV/-#fz AMPLIFIER

r-------------.-------~-----o~

In situations where low output, low-impedance transducers arlil
used, amplifiers must have very low voltage noise to maintain a
good signal-to-noise ratio. The design presented in this application is an operational ~mplifier with only 500pVl-YFrz of ,broadband noise. The front end uses SSM-221 0 low-noise dual transistors to achieve this exceptional performance. The op amp has
superb DC specifications compatible with high-precision transducer requirements, and AC specifications suitable for professional audio work.
PRINCIPLE OF OPERATION

The design configuration in Figure 6 uses an OP-27 op amp
(already a low-noise design) preceded by an amplifier consisting of three parallel-connected SSM-221 0 dual transistors. Base
spreading resistance (rbb) generates thermal noise which is
reduced by a factor of "';3 when the input transistors are parallel
connected. Schottky noise, the other major noise-generating
mechanism, is minimized by using a relatively high collector
current (1 mA per device). High current ensures a low dynamic
emitter resistance, but does increase the base current and its
associated current noise. Higher current noise is relatively uniinportant when low-impedance transducers are used.

v-

.IN

v-

vFIGURE 6: Simplified Schematic

7-154 SPECIAL FUNCTION AUDIO PRODUCTS

REV. B

SSM-2210
CIRCUIT DESCRIPTION
Thedetailedcircuitis shown in Figure 7. A total input-stage emitter
current of 6mA is provided by 04' The transistor acts as a true
current source to provide the highest possible common-mode
rejection. R1 , R2 , and R3 ensure that this current splits equally
among the three input pairs. The constant current in 04 is set by
using the forward voltage of a GaAsP light-emitting diode as a
reference. The difference between this voltage and the baseemitter voltage of a silicon transistor is predictable and constant
(to within a few percent) over the military temperature range. The
voltage difference, approximately 1V, is impressed across the

emitter resistor
ter current.

R12

which produces a temperature-stable emit-

Rs and C 1 provide phase compensation for the amplifier and are
sufficient to ensure stability at gains of ten and above.

R7 is an input offsettrim that provides approximately±3001lV trim
range. The very low drift characteristics of the SSM-221 0 make
it possible to obtain drifts of less than O.1IlV/oC when the offset
is nulled close to zero. If this trim is not required, the R4, R7 , and
Rs network should be omitted and R5/R9 connected directly to V+.

~----~----,-------------------------,-------------~-o.lW

".

"022!>

221>

NULL

"7

R,
1.5K.a,O.1%

".

loon

1.5Kn,0.1%

".

C,

1501>

0.0111'

~l00nF

.'J-_......I.---() -IN

.IN o----.~__1t::

I 9SM-2210

~l00nF

27kll

I SSM-2210

____ I 9SM-2210

",.

1801l

"ED
LED

55

'--------+------.....- 0 -15V
FIGURE 7: Complete Amplifier Schematic

REV. B

SPECIAL FUNCTION AUDIO PRODUCTS 7-155

•

SSM-2210
AMPLIFIER PERFORMANCE
The measured performance ofthe op amp is summarized in Table
2. Figure 8 shows the broadband noise spectrum which is flat at
about 500.pV/,IHz. Figure 9 shows the low-frequency spectrum
which illustrates the low 1/f noise corner at 1.5Hz. The low-frequency characteristic in the time domain from 0.1 Hz to 10Hz is
shown in Figure 10; peak-to-peak amplitude is less than 40nV.

TABLE 2: Measured Performance of the Op Amp
Input Noise
Voltage Density at 1kHz

500pV/-YHz

Input Noise
Voltage from 0.1 Hz to 10Hz

40nV~.p

Input Noise Current at 1kHz
Gain-Bandwidth

1.5pA/v'RZ
G= 10
G= 100

3M Hz
600kHz

G = 1000

150kHz

Slew Rate

2V/I!s

Open-Loop Gain

3 x 107

Common-Mode Rejection

130dB

Input Bias Current

31!A

Supply Current

10mA

0.11!V/oC Max

Nulled TCVos
T.H.D. at 1kHz

FIGURE 9: Spectrum Analyzer Display - Low Frequency

G = 1000

FIGURE 10: Oscilloscope Display

0.002%

CONCLUSION
Using SSM-2210 matched transistor pairs operating at a high
'current level, it is possible to construct a high-performance, lownoise operational amplifier. The circuit uses a minimum of components and achieves performance levels exceeding monolithic
amplifiers.

FIGURE 8: Spectrum Analyzer Display - Broadband

7-156 SPECIAL FUNCTION AUDIO PRODUCTS

REV.B

SSM-221O

+15V
' ••k"

~-_-OVo

330pF -15V

.,

7.SkU

330pF
+15V

.,

50012

R2 = TEL LABS Q81E (+0.35%1"C)

-15V

•

FIGURE 11: Fast Logarithmic Amplifier

FAST LOGARITHMIC AMPLIFIER
The circuit of Figure 11 is a modification of a standard logarithmicamplifierconfiguration. Running the SSM-221 0 at2.5mA per
side (full-scale) allows a fast response with wide dynamic range.
The circuit has a 7 decade current range, a 5 decade voltage
range, and is capable of 2.511S settling time to 1% with a 1 to 10V
step.
The output follows the equation:

Vo =

A3+A2 kT
A2
q

In VREF
VIN

To compensate for the temperature dependence ofthe kTIq term,
a resistor with a positive O.35%/oC temperature coefficient is
chosen for R2 .
The output is inverted with respect to the input, and is nominally
-1 V/decade using the component values indicated.

REV.

B

SPECIAL FUNCTION AUDIO PRODUCTS 7-157

7-158 SPECIAL FUNCTIONAUOIO PRODUCTS

~ANALOG

Audio Dual Matched
PNP Transistor
SSM-2220 I

WDEVICES
FEATURES
• Very Low Voltage Noise ............. @ 100Hz, 1nV/v'Hz Max
• High Gain Bandwidth ..................................... 190MHz Typ
• Excellent Gain ................................... @ Ic = 1mA, 165 Typ
• Tight Gain Matching ............................................... 3% Max
• Outstanding Logarithmic Conformance ... raE 0.3n Typ
• Low Offset Voltage ........................................... 200,N Max
• LowCost

=

APPLICATIONS
• Microphone Preamplifiers
• Tape-Head Preamplifiers
• Current Sources and Mirrors
• Low Noise Precision Instrumentation
• Voltage Controlled Amplifiers/Multipliers
ORDERING INFORMATION
&-PIN EPOXY DIP

&-PINSO'

SSM2220P

SSM2220S

The SSM-2220 also offers excellent matching olthe current gain
(.1.h FE ) to about 0.5% which will help to reduce the high order
amplifier harmonic distortion. In addition, to insure the long-term
stability of the matching parameters, internal protection diodes
across the base-emitter junction were used to clamp any reverse
base-emitter junction potential. This prevents a base-emitter
breakdown condition which can result in degradation of gain and
matching performance due to excessive breakdown current.
Another feature of the SSM-2220 is its very low bulk resistance
of 0.3n typically which assures accurate logarithmic conformance.
The SSM-2220 is offered in B-pin plastic, dual-in-line, and SO
and its performance and characteristics are guaranteed overthe
extended industrial temperature range of -40°C to +B5°C.

PIN CONNECTIONS
OPERATING
TEMPERATURE
RANGE

For availability of SO package, contact your local sales office.

GENERAL DESCRIPTION

B-PIN
EPOXY DIP
(P-Suffix)
B-PIN
SO
(5-Suffix)

The SSM·2220 is a duallow.noise matched PNP transistor which
has been optimized for use in audio applications.
The ultra·low input voltage noise of the SSM·2220 is typically
only O. 7nVI/RZoverthe entire audio bandwidth of 20Hz to 20kHz.
The low noise, high bandwidth (190MHz), and Offset Voltage of
(200!1V Max) make the SSM-2220 an ideal choice for demanding low noise preamplifier applications.

REV. A

SPECIAL FUNCTION AUDIO PRODUCTS 7-159

I

SSM-2220
ABSOLUTE MAXIMUM RATINGS
Collector-Ba~e

Voltage (BVQIlO) ........................................ 36V
Collector-Emitter Voltage (BVCEO) •••.•••••••••.•.••••••••...•••.••••.. 36V
Collector-Collector Voltage (BV cc) .................................... 36V
Emitter-Emitter Voltage (BV EE ) .......................................... 36V
Collector Current (lc) ....................................................... 20mA
Emitter Current (IE) .......................................................... 20mA
Operating Temperature Range
SSM-2220P .............. :................................... -40°C to +85°C
SSM-2220S .................................................. -40°C to +85°C
Operating Junction Temperature .................. -55°C to + 150°C

Storage Temperature .................................... -65°C to + 150°C
Lead Temperature (Soldering. 60 sec) ..........•............. +300°C
Junction Temperature ................................... -65°C to + 150°C
SjC

UNITS

8-Pin Plastic DIP (P)

PACKAGE TYPE

103

43

·CIW

8-PinSO(S)

158

43

·CIW

alA (Note 1)

NOTE:
1. SjA is specified forworst case mounting conditions, i.e.. ajA isspecifiedfordevice
in sockel for P·DIP package; alA is specified for device soldered to printed
circuit board for SO packages.

ELECTRICAL CHARACTERISTICS at T A = +25°C. unless otherwise noted.
SSM-2220
PARAMETER

SYMBOL

CONDITIONS

Current Gain
(Note 1)

hF•

Vea = OV, -{lSV
le=lmA
Ie = 1001lA
Ie = 101lA

Current Gain Matching
(Note 2)

Ah F•

le=100~A, Vea=OV

Noiss Voltage Density
(Note 3)

eN

le=lmA,Ves=OV
fo= 10Hz
fo =I00Hz
fo=lkHz
fo= 10kHz

Offset Voltage
(Note 4)

Vos

Offset Voltage Change
vs. Collectcr Voltage

MIN

TYP

80
70
SO

165
150
120

MAX

UNITS

0.5

6

%

0.8
0.7
0.7
0.7

2
1
1

nVlv'FiZ

Vcs=OV,le= 100llA

40

200

~V

AVcdAVcs

le= 1001lA
Vcat =OV
VCB2 =-,36V

II

200

~V

Offset Voltage Change
vs. Collectcr Current

AVcdAle

Vea=OV
let = 10llA,Ie2 = I rnA

12

75

~V

Offset Current

los

le= 100llA, Vea=OV

6

45

nA

Colieclor·Base
Leakage Current

leBO

Vea =-{lSV = VMAX

50

400

pA

Bulk Resistance

rSE

Vca=OV,
101lA$lc 51mA

0.3

0.75

11

Collectcr Saturaiion
Voltage

VCE(SAT)

Ie = I rnA, Is = 1001lA

0.026

0.1

V

NOTES:
1. Current gain is measured at eolleclor-base voltages (Vea) swept from 0 to
VMAX at indieated collector current. Typicals are measured at Vcs = OV.
2. Current gain matehing (Ah FE) is defined as:
100(AIB) hFE (MIN)
Ic
3. Sample tested. Noise tested and specified as equivalent input voltage for
each transistor.
AhFE

7-160 SPECIAL FUNCTION AUDIO PRODUCTS

4. Offset voltage is defined as:
VOS·VBE1-VBE2·

where Vos is the differential voltage for
IC2 =IC2 :VOS =VBEI - VsE2

=!IT
q

In

I~
Ic

REV. A

SSM-2220
ELECTRICAL CHARACTERISTICS at -40°C :S TA :S +85°C, unless otherwise noted.
SSM-2220
SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

60
50
40

120
lOS
90

VeB =OV,-36V
le=lmA
le= lOOjlA
le= 101lA

MAX

UNITS

Currenl Gain

hFE

Offset Voltage

Vos

Ie = lOOIlA. VeB = OV

30

265

IlV

Offset Voltage Drift
(Note I)

TCVos

Ie = lOOIlA, VeB = OV

0.3

1.0

Ilvrc

Ie = lOOIlA. VeB =OV

10

200

nA

Offset Currenl

los

Breakdown Voltage

BVeEo

36

V

NOTE:
I. Guaranteed by Vos test (TCVos = Volf for Vos « VBE)
where T = 29soK for TA = 25°C.

TYPICAL PERFORMANCE CHARACTERISTICS
NOISE FIGURE vs
COLLECTOR CURRENT

LOW FREQUENCY NOISE
14

D.'

""

VeE =5V

T" =+:Z5OC

0.4

'.1kHz

12

EMITTER-BASE
LOG CONFORMITY
Vee =OY

0.3
10

=

~

Rs =1kn

I/'Rs =100""

"

VERTICAL 4QnV/DIV
HORIZONTAL 11/D1Y

=

f'.

~E=5V

Ic· tmA
TA 1II+25°C

o

0.001

TOTAL NOISE vs
COLLECTOR CURRENT

!
j

Rs

l1li

101en

lJJlI

I

0.1

...

-0.2

I

f\'~

"

.L

0.2

....

-0.1

-0.3
-0.4
-0.5'0'"

0.01
0.1
COLLECTOR CURRENT (mA)

10-7

10.....

10-5

10-4

10-3

COLLECTOR CURRENT CA)

NOISE VOLTAGE DENSITY

NOISE VOLTAGE DENSITY
vs FREQUENCY

vs COLLECTOR CURRENT
1000

"'I-+-H-++t

~~

150

~.~
. • ~1.. 1kHz

T" =25'C

TA

Yca=OV

Yca=OV

I

10Hf

l-+ttttlffi~+t+t1H1tt-~Vt-tttHtl

I

roo
c::::;;:;:
o Liltl!lllE::3333:I:IIII::::t:~
1

10

100

COLLECTOR CURRENT fIlA)

REV. A

1GOO

=zs'c

o

V

~'\.

/

Ie =1DpA

100Hz/

-.....

Ie 1: 100pA

Ic=lmA

,,/

o

12

COLLECTOR CURRENT (mA)

D. 1
0.1

10

100

1k

====

-

=
10k

100k

FREQUENCY CHz)

SPECIAL FUNCTION AUDIO PRODUCTS 7-161

II

SSM-2220
TYPICAL PERFORMANCE CHARACTERISTICS Continued

CURRENT GAIN
vs TEMPERATURE

CURRENT GAIN vs
COLLECTOR CURRENT

3D.

700

...

l

~

.25"C

I-- t-

~Ie

....·c

!!iu

50

.,.

..

~
li
IiIe

... i-"'"

0.01

-15

..,

•

5
25
45 65
TEMPERATURE rC)

105

125

0.'
0.001

0.01

i

·I'~
....·c

~

.

III ,

COLLECTOR CURRENT (rnA)

'00

COLLECTOR-BASE
CAPACITANCE vs VeB

T A =25·C

.. 1\

00

T" =25"C

0

\

.

• .55

,/

....
0...

10

50

wOo..

>G

0.1

COLLECTOR CURRENT (mA)

BASE-EMITTER VOLTAGE
vs COLLECTOR CURRENT

....
....

I 11111

/

,
85

0.70

...·c~

iF

-~

Vca=OV

~

-55 -35

~

~"

/

-- ---

300

•

~

..,

./

~

, /~

COLLECTOR CURRENT (pA)

~~
f=

• .0'

,/

400

'000

g
III

.00

'00

,

~VCB=·V

~.=~ ~~

SATURATION VOLTAGE
vs COLLECTOR CURRENT

,.
I!

t}'="'C

.00

f...- fo""

~

'000

Icl.'m~

VCB=OV

+125"C

GAIN BANDWIDTH vs
COLLECTOR CURRENT

.... ,

10
.100
1000
COLLECTOR CURRENT (pA)

SMALL-SIGNAL INPUT
RESISTANCE (hie> vs
COLLECTOR CURRENT

,....

•o

~

.

1.

V

-5
-10
-15
-20
-25
-30
COLLECTOfWlASE VOLTAGE (VOLTS)

-35

SMALL-SIGNAL OUTPUT
CONDUCTANCE(h~)vs

COLLECTOR CURRENT

: 1000
TA

"-. ~

""

=25·C

'00

'-

r..
'-

r..

,
10

100

COLLECTOR CURRENT (pA)

7-162 SPECIAL FUNCTION AUDIO PRODUCTS

'000

10
100·
" ,.
COLLECTOR CURRENT (a&A)

1000

REV. A

SSM-2220
PULSE RESPONSE
-15V
+15V

IO.OO'pF

'.5k!l

Ukn

0.01%

0.01"-

Vour

,son

O.O'pF

-15V
~=10

+

C,=30pF
SSM-2220 PAIRS:
Q,-Q2

0 3 -0 4
0 5 -0 6

~

RED
LED

B3n

+15V

f~f-l

FIGURE 18: Super Low Noise Amplifier

APPLICATIONS INFORMATION

.---------.,B
0.'

SUPER LOW NOISE AMPLIFIER
The circuit in Figure 1a is a super low noise amplifier with
equivalent input voltage noise of 0.32nVIy'Hz. By paralleling
SSM·2220 matched pairs, a further reduction of amplifier noise
is attained by a reduction of the base spreading resistance by a
factor of 3, and consequently the noise by-/3. Additionally, the
shot noise contribution is reduced by maintaining a high collec·
tor current (2mA/device) which reduces the dynamic emitter
resistance and decreases voltage noise. The voltage noise is
inversely proportional to the square root of the stage current, and
current noise increases proportionally to the square root of the
stage current. Accordingly, this amplifier capitalizes on voltage
noise reduction techniques at the expense of increasing the
current noise. However, high current noise is not usually impor·
tant when dealing with low impedance sources.
This amplifier exhibits excellent full power AC performance,
0.08% THO into a 600n load, making it suitable for exacting audio
applications (see Figure 1b).

REV. A

l

Ii

';"'~O~
0.01
NO LOAD

r-

~
0.001

10

100

1k

10k

,00k

FREQUENCY (Hz)

FIGURE 1b: Super Low Noise Amplifier- Total Harmonic
Distortion

SPECIAL FUNCTION AUDIO PRODUCTS 7-163

FIGURE 2: Super Low Noise Amplifier
LOW NOISE MICROPHONE PREAMPLIFIER

Figure 2 shows a microphone preamplifier that consists of a SSM2220 and a low noise op amp. The input stage operates at a
relatively high quiescent current of 2mA per side, which reduces
the SSM-2220 transistor's voltage noise. The 1// corner is less
than 1Hz. Total harmonic distortion is under 0.005% for a
1OVp-p signal from 20Hz to 20kHz. The preamp gain is 100, but
can be modified by varying R5 or Rs (VOUIVIN = RsfR s + 1).

7-164 SPECIAL FUNCTION AUDIO PRODUCTS

A total input stage emitter current of 4mA is provided by 02' The
constant current in 02 is set by using the forward voltage of a
GaAsP LED as a reference. The difference between this voltage
and the VBE of a silicon transistor is predictable and constant (to
a few percent) over a wide temperature range. The voltage difference, approximately 1V, is dropped across the 2500 resistor
which produces a temperature stabilized emitter current.

REV. A

SSM-2220

+15V

ADJUST POT

(2vFfc'J.=.
1knRES)
SPOT NOISE FOR
en
EACH TRANSISTOR = 10,000 x.f2

FIGURE 3: SSM-2220 Voltage Noise Measurement Circuit

SSM·2220 NOISE MEASUREMENT
All resistive components (Johnson noise, en2 = 4kTBR, or en =
0.13 v'R nV/.vHz, where R is in kQ) and semiconductor junctions (Shot noise, caused by current flowing through a junction,
produces voltage noise in series impedances such as transistor-collector load resistors,l n= 0.55&/TpAlvRZwhere I is in ~A)
contribute to the system input noise.
Figure 3 illustrates a technique for measuring the equivalent input noise voltage olthe SSM-2220. 1mA of stage current is used
to bias each side of the differential pair. The 5kQ collector resistors noise contribution is insignificant compared to the voltage
noise of the SSM-2220. Since noise in the signal path is referred
back to the input, this voltage noise is attenuated by the gain of
the circuit. Consequently, the noise contribution of the collector
load resistors is only 0.048nVly"Hz. This is considerably less
than the typical 0.8nV/v'RZinput noise voltage olthe SSM-2220
transistor.
The noise contribution of the OP-27 gain stages is also negligible due to the gain in the signal path. The op amp stages amplify the input referred noise of the transistors to increase the
signal strength to allow the noise spectral density (e in x 10000)
to be measured with a spectrum analyzer. And, since we assume
equal noise contributions from each transistor in the SSM-2220,
the output is divided by v'2 to determine a single transistor's
input noise.
Air currents cause small temperature changes that can appear
as low frequency noise. To eliminate this noise source, the
measurement circuit must be thermally isolated. Effects of extraneous noise sources must also be eliminated by totally
shielding the circuit.

REV. A

I
FIGURE 4: Cascade Current Source

CURRENT SOURCES
A fundamental requirement for accurate current mirrors and
active load stages is matched transistor components. Due to the
excellent VeE matching (the voltage difference between VeE'S
required to equalize collector current) and gain matching, the
SSM-2220 can be used to implement a variety of standard current mirrors that can source current into a load such as an amplifier stage. The advantages of current loads in amplifiers versus
resistors is an increase of voltage gain due to higher impedances,
larger signal range, and in many applications, a wider signal
bandwidth.
Figure 4 illustrates a cascode current mirror consisting of two
SSM-2220 transistor pairs.

SPECIAL FUNCTION AUDIO PRODUCTS 7-165

SSM-2220.
The cascode current source has· a common base transistor in
series with the output which causes an increase in output impedance of the current source since VCE stays relatively constant. High frequency characteristics are improved due to a reduction of Millercapacitance. The small-signal output impedance
can be determined by consulting "hoe vs. Collector Current"
typical graph. Typical output impedance levels approach the
performance of a perfect current source.

(

----,

I A CLOSELY MATCHED

) TRANSISTOR PAIR

Considering a typical collector current of 1001JA. we have:
1
rOm =
=1MO.
1.0IlMHOS
02 and 03 are in series and operate at the same current level. so
the total output impedance is:
Ro = hFE rOQ3 ~ (160)(1 MO)= 160Mn.

CURRENT MATCHING
The objective of current source or mirror design is generation of
currents that are either matched or must maintain a constant ratio. However. mismatch of base-emitter voltages cause output
current errors. Consider the example of Figure 5. If the resistors
and transistors are equal and the collector voltages are the same.
the collector currents will match precisely. Investigating the
current-matching errors resulting from a non-zero Vos' we define al c as the current error between the two transistors.
Graph 5 describes the relationship of current matching errors
versus offset voltage for a specified average current Ic. Note that
since the relative error between the currents is exponentially
proportional to the offset voltage. tight matching is required to
design high accuracy current sources. For example. if the offset
voltage is 5mVat 1OOIlA collector current, the current matching
error would be 20%. Additionally. temperature effects such as
offset drift (3IlV/oC per mV of Vos) will degrade performance if
01 and 02 are not well matched.

7-166 SPECIAL FUNCTION AUDIO PRODUCTS

FIGURE Sa: Current Matching Circuit

1.2

IC= ~"i-A

Ic=1~

1.0

0.8
SSU-2220 Vas

PERFORMANCE

I

J

II

R.3IUl
h FE .. 200

0.2

o

0.001

....
0.01

0.1

.I e = IC1; ICZ

~Ic = 1rnA

&I .IC1-1C2

10

Vos (mY)

FIGURE 5b: Current Matching Accuracy % vs. Offset Voltage

REV. A

Dual Audio
Analog Switches
SSM-2402/SSM-2412 I

~ANALOG

WDEVICES
FEATURES
•
•
•
•
•
•
•

"Clickless" Bilateral Audio Switching
Guaranteed "Break-Before-Make" Switching
Low Distortion ................................................. 0.003% Typ
Low Noise .....................................•.•..•.•................ 1nV/..,f'Hz
Superb OFF-Isolation ....................................... 120dB Typ
Low ON-Resistance .............................................. 60n Typ
Wide Signal Range:
Vs = ±18V ............................................................. 10V RMS
• Wide Power Supply Range ............................. ±9V to ±20V
• Available in Dice Form

ORDERING INFORMATION
PACKAGE
PLASTIC
14·PIN

SOL
16·PIN

OPERATING
TEMPERATURE
RANGE

SSM2402P
SSM2412P

SSM2402S
SSM24'2S

XINO'
XINO'

new circuit topology that optimizes audio performance, the
SSM-2402/2412 make use of a proprietary bipolar-JFET process with thin-film resistor network capability. Nitride capacitors,
which are very area efficient, are used for the proprietary ramp
generator that controls the switch resistance transition. Very
wide bandwidth amplifiers control the gate-to-source voltage
over the full audio operating range for each switch. The ONresistance remains constant with changes in signal amplitude
and frequency, thus distortion is very 10w,Iess than 0.01 % Max.
The SSM-2402 is the first analog switch truly optimized for highperformance audio applications. For broadcasting and other
switching applications which require a faster switching time, we
recommend the SSM-2412 - a dual analog switch with one-third
of the switching time of the SSM-2402.

PIN CONNECTIONS

'XINO = -40'C to +85'C

14-PIN
PLASTIC DIP
(P-Suffix)

GENERAL DESCRIPTION
The SSM-2402/2412 are dual analog switches designed specifically for high-performance audio applications. Distortion and
noise are negligible over the full audio operating range of 20Hz
to 20kHz at signal levels of up to 10VRMs ' The SSM-2402/2412
offer a monolithic integrated alternative to expensive and noisy
relays or complex discrete JFET circuits. Unlike conventional
general-purpose CMOS switches, the SSM-2402/2412 provide
superb fidelity without audio "clicks" during switching.
Conventional TTL or CMOS logic can be used to control the
switch state. No external pull-up resistors are needed. A "T"
configuration provides superb OFF-isolation and true bilateral
operation. The analog inputs and outputs are protected against
overload and overvoltage.
An important feature is the guaranteed "break-before-make" for
all units, even IC-to-IC. In large systems with multiple switching
channels, all separate switching units must open before any
switch goes into the ON-state. With the SSM-2402/2412, you
can be certain that multiple circuits will all break-before-make.
The SSM-2402/2412 represent a significant step forward in
audio switching technology. Distortion and switching noise are
significantly reduced in the new SSM-2402/2412 bipolar-JFET
switches relative to CMOS switching technology. Based on a

REV. A

GROUND

1

SW1 CONTROL

2

SW1 1N

4

15 SW 2 CONTROL

16-PIN SOL
(S-Suffix)

N.C.'
SW1 0UT

6

11 SW 2 0UT

• GUARD PINS FOR INPUT/OUTPUT ISOLATION
(GROUND FOR BEST PERFORMANCE)

CONTROL LOGIC
Logic In

Switch State

o

OFF
ON

Logic "0" S 0.8V
Logic •• , •• "2.0V

SPECIAL FUNCTION AUDIO PRODUCTS 7-167

I

SSM-2402!SSM-2412
FUNCTIONAL DIAGRAM

TIMING DIAGRAM

V+ 0--.
GND~

MAIN SWITCH OPEN!
SHUNT SWITCH CLOSED
I
I I
. . tON --+-j

IN

0--+......-------'

....,

tOFF

I

c~~HJ

' - - - - - -.....-+--0 OUT

t4-

LOW

....- - - - - -

TIME
SWITCH TIMING

V-o--.....----+----+---~---~

ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range ....................... -40°C to +85°C
Operating Supply Voltage Range ....•....................•.......•.. ±20V
Analog Input Voltage Range
Continuous ....••....•...•................... V- +3.5V $ VA $ V+ -3.5V
Maximum Current Through Switch ................................. 20mA
Logic Input Voltage Range •.......•.................. V+ Supply to -2V
VA to V- Supply ................................................................ +36V
PACKAGE TYPE

co~:~

0--.

~------------------'

LOGIC HIGH = ON
LOGtc LOW :I OFF
51' $2 = MAIN SWITCHES
53
SHUNT SWITCH

=

alA (Note 1)

14'Pin Plastic DIP (P)

76

SIC

UNITS

33

·CIW

16'Pin SOL (5)
92
27
·CIW
NOTE:
1. a jA is specified for worst case mounting condition~. i.e .• a'A is specified for
device in socket for P·DIP package; a jA is specified for di.vice soldered to
printed circuit board for SOL package,

ELECTRICAL CHARACTERISTICS at V s = ±18V, RL = OPEN, and -40°C $

T A $ +85°C, unless otherwise noted.

All specifications, tables, graphs, and application data apply to both the SSM-2402 and SSM-2412, unless otherwise noted.

SSM-2402l2412
PARAMETER

SYMBOL

CONDITIONS

TYP

MAX

UNITS

+ISY

V,L =0.8V. 2.0V
(Note t)

6.0

7.5

mA

-ISY

V,L =0.8V. 2.0V
(Note 1)

4.8

6.0

mA

GrouQd Current

IGND

V,L - 0.8V. 2.0V
(Note 1)

0.6

1.5

mA

0.8

V

5.0

~A

+14.2

V

Positive Supply
Current
Negative Supply
Current

Digital Input High

V,NH

TA = Full Temperature Range (Note 2)

Digital Input Low

V,NL

TA = Full Temperature Range

Logic Input
Current

ILOGIC

V,N = Oto 15V
(Note 3)

Analog Voltage
Range (Note 3)

VANALOG

7-168 SPECIAL FUNCTION AUDIOPRODUCTS

MIN

2.0

V

1.0
-14.2

REV.

A

SSM-2402lSSM-2412
ELECTRICAL CHARACTERISTICS at Vs

=±18V, RL =OPEN, and -40°C:s TA:S +85°C, unless otherwise noted. Continued
SSM·240212412

PARAMETER

SYMBOL

Analog Current
Range (Note 3)

IANALOG

Overvoltage Input
Current

CONDITIONS

MIN

TYP

-10

MAX

UNITS

+10

mA

±40

V'N=±VSUPPlY

mA

-14.2 S VAS +14.2V
Switch ON

Resistance

RON

IA = ±10mA, V'L = 2.0V
TA = +25°C
T A = Full Temperature Range

60

RONMATCH

Switch ON
Leakage Current
(Notes I, 3)

ISION )

Switch OFF
Leakage Cu rrent
(Notes 1, 3)

ISIOFF)

-14.2 S VAS +14.2V

VA =OV
V'L =0.8V
-14.2V S V AS +14.2V
VA =OV

Turn-On Time

5

%

0.05
0.05

1.0
10.0

~A

0.05
0.05

1.0
10.0

~A

IA = ±10mA, V'L = 2.0V
V'L =2.0V
-14.2V S VA S +14.2V

Q
Q

WOC

0.2

Tempco (/II'--""'--I

TIME (ms)

VO=-100VS WITH
SWITCH OPEN

SSM·2412 TONITOFF SWITCHING RESPONSE

SWITCH ON/OFF TRANSITION TEST CIRCUIT
10

OUTPUT (Vo)

CONTROL LOGIC
INPUT (IN,)

TlME(ms)

Slcu
$,

5SM·2402

50U

Vs =-O.1Vo--~>/II'--""'--I

SWITCHING ON/OFF TRANSITION

55M·2412

Vo

R,

=-Soii (-D.1V), WHERE

AF=

RsxSkU
As + SkU

RS:I: SWITCH RESISTANCE

"OFF" ISOLATION TEST CIRCUIT

1\

2lcu

V1L " HIGH TO LOW

VIL. HIGH TO LOW

7-172 SPECIAL FUNCTION AUDIO PRODUCTS

"OFF" tsOLATION. 20 LOG [

v"':ur ]

REV. A

SSM-2402/SSM-2412
SWITCHING TIME TEST CIRCUIT
.18V

SWITCH
INPUT 51
~ . .'OV 0--1-------<>":

V.

"'-

"'-

-18V

LOGIC
INPUT

SWITCH
OUTPUT
Vo

1r c100ma

0,

2lU1

REPEAT TEST FOR IN2

Vo= Vs RL • RON

r

V

1.4Y

ltoC100ma

~~~

Vs

SWITCH 0
OUTPUT
'ON

'OFF

SIMPLIFIED SCHEMATIC
II10tl

101<1>

II
i--

I V+~~----~------,
I
I
I
I RAMP
I
I
I
I
I
MAIN

I~

I
I
I
I
L~

REV. A

I
I
I
I
I
I
I
I
SHUNT
I
SWITCH I
CONTROL I

I
I
I

.".

______________________

II

SPECIAL FUNCTION AUDIO PRODUCTS 7-173

SSM-2402lSSM-2412
APPLICATIONS INFORMATION
FUNCTIONAL SECTIONS
Each half of the SSM-2402/2412 are made up of three major
functional blocks:
1.

"T" Switch
Consists of JFET switches SI and S2 in series as the main
switches and switch S3 as a shunt.

2.

Ramp Generator
Generates a ramp voltage on command olthe Control Input
(see Figure 1). A LOW-to-HIGH TIL input at Control Input
initiates a ramp that goes from approximately -7V to +7V in
12ms for the SSM-2402, and 4ms for the SSM-2412. Conversely, a HIGH-to-LOW TTL transition at Control Input will
cause a downward ramp from approximately +7V to -7V in
12ms for the SSM-2402, and 4ms for the SSM-2412. The
Ramp Generator also supplies the +3V and -3V reference
levels for Switch Control.

3.

Switch Control
The ramp from the Ramp Generator section is applied to
two differential amplifiers (DAI and DA2) in the Switch Control block. (See Simplified Schematic). One amplifier is referenced to -3V and the other is referenced to +3V. Switch
Control Outputs are:
-

-

Main Switch Control - Drives two 0.25mA current
sources that control the inverting inputs of each op amp.
When ON, the current sources cause a gate-to-source
voltage of approximately 2.5V which is sufficient to turn
off SI and S2' When the current sources from Main
Switch Control are OFF, each op amp acts as a unitygain follower (Vas = 0) and both switches (SI and S2)
will be ON.

v+o-----.-----~~--~~--~_.----,

FIGURE 1: RAMP Generator

HIGH
CONTROL
INPUT

,...------------,

~

LOW

+1V
.

-I
1

RAMP

Shunt Switch Control - Controls the Shunt Switch of
the "T" configuration.
1

SWITCH OPERATION
To see how the SSM-2402/2412 switches work, first consider
an OFF-to-ON transition. The Control Input is initially LOW and
the Ramp Output is at approximately -7V. The Main Switch
Control is HIGH which drives current sources 03 and 04 to
0.25mA each. These currents generate 2.5V gate-to-source
back bias for each JFET switch (SI and S2) which holds them
OFF.
The Shunt Switch Control is negative which holds the shunt
JFET S3 ON. Undesired feedthrough signals in the series JFET
switches SI and S2 are shunted to. the negative supply rail
through S3'

.~Ff' FOR

-TV

r
91's"

ON

OFF

1

i -I

I

1

-1-

I

.

9, 0: 1"1

: II

...,

1

I

, - _.......
1__

1

I

_--Ir

.1-_ _--:-:

~:-L
_
1

1
1

9 •• s"

• OFf'

FOR $3

I

J

'ON

FORS 3

FIGURE 2: Switch Control

7--174 SPECIAL FUNCTION AUDIO PRODUCTS

REV. A

SSM-2402lSSM-2412
When the Control Input goes from LOW to HIGH, the Ramp
Generator slews in the positive direction as shown in Figure 2.
When the ramp goes more positive than -3V, the Shunt Switch
Control is pulled positive by differential amplifier DA2 which
thereby puts shunt switch S3 into the OFF state. Note that Sl
and S2 are still OFF, so at this time all three switches in the "T"
are OFF.
When the Ramp Output reaches +3V, and the drive for the Main
Switch Control output is gated OFF by differential amplifier DA1 ,
current sources 03 and 04 go to the OFF state and the VGS of
each main switch goes to zero. The high-speed op amp followers provide essentially zero gate-to-source voltage over the full
audio signal range; this in turn assures a constant low impedance in the ON state over the full audio signal range. Total time
to turn on the SSM-2402 switch is approximately 1O.Oms and
3.5ms for the SSM-2412.
In systems using a large number 01 separate switches, there are
advantages to having faster switching into OFF state than into
the ON state. Break-belore-make can be maintained at the
system level. To see how the SSM-2402/2412 guarantee breakbefore-make, consider the ON-to-OFF transition.
A Control Input LOW initiates the ON-to-OFF transition. The
Ramp Generator integrates down from approximately +7V towards -7V. As the ramp goes through +3V, the comparator
controlling the Main Switches (Sl and S2) goes HIGH and turns
on current sources 03 and 04 which thereby puts Sl and S2 into
the OFF state. Atthistime, all switches in the "T" are OFF. When
the ramp integrates down to -3V, the Shunt Switch Control
changes state and pulls shunt switch S3 into the ON state. This
completes the ON-to-OFF transistion; Sl and S2 are OFF, and
S3 is ON to shunt away any undesired feedthrough. Note though
that the ON-to-OFF time for main switches Sl and S2 is only the
time interval required for the ramp to go from +7V to +3V, about
4ms for the SSM-2402, and 1.5ms lor the SSM-2412. The time
to turn on is about 2.5 times as long as the time to turn off.

The SSM-2402/2412 are much more than a simple single solidstate switches. The "T" configuration provides superb OFF-isolation through shunting of feedthrough via shunt switch S3'
Break-before-make is inherent in the design. The ramp provides
a controlled gating action that softens the ON/OFF transitions.
Distortion is minimized by holding zero gate-to-source voltage
forthe two main FET switches, Sl and S2' using the two op amp
followers. Figure 3 shows a distortion comparison between the
SSM-2402 and a typical CMOS switch. In summary, the SSM2402/2412 are designed specifically for high-performance audio system usage.
OVERVOLTAGE PROTECTION
The SSM-2402/2412 are designed to guarantee correct operation with inputs of up to ±14.2V with ±18V supplies. The switch
input should never be forced to go beyond the supply rails. In the
OFF condition, il the inputs exceeds + 14.2V, there is a risk of
turning the respective input pass FET "ON." When the input
voltage rises to within 3.8V of the. positive supply, the op amp
follower saturates and will not be able to maintain the full2.5Vof
back bias on the gate-to-source junction. Under this condition,
current will flow from tile input through the shunt FET to the
negative supply. This current is substantial, but is limited by the
FET loss' Although this current will not damage the device, there
is a danger of also turning on theoutpulpass FET, especially if
the output is close to the negative raiL
This risk 01 signal "breakthrough" for inputs above +14.2V can
be eliminated by using a source resistor of 100-500n in series
with the analog input to provide additional current limiting.
Near the negative supply, transistors 0 3 and 04 saturate and
can no longer keep the switch OFF. Signal breakthrough cannot happen, but the danger here is latch-up via a path to Vthrough the shunt FET. Additional circuitry (n9t shown) has
been incorporated to turn OFF the shunt FET Linder these conditions, and the potential for latch-Up is thereby eliminated.

TYPICAL CONFIGURATION

~~~~~~l

LOW

=OFF

+18V

o-------=-f-

I

I
I

:r-+"----'VItv--<> ~N~UfH

* OPTIONAL INPUT RESISTORS

SEE SECTION ON OVERVOLTAGE PROTECTION
•• OPTIONAL LOAD RESISTORS
LOWER VALUES WILL MINIMIZE "ClICKS" BUT WITH A 10V AMS INPUT
IT IS RECOMMENDED THAT THEY BE GREATER THAN 2kH

REV. A

SPECIAL FUNCTION AUDIO PRODUCTS 7-175

I

SSM-2402ISSM-2412

10k£1

200k1l

2kU

20ku

FIGURE 4

........, V1N =20Vp-p
i= 10Hz

SSY·2402

R,

TYPICAL CMOS SWITCH

IN

O---.NV'----500
1
DC
1

20 VI",s
450 V/",s

1 mAI",s
1.3 V/",s
1.3 V/",s

Peak Signal
Amplitude
Vp,Ip

Power
Supplies
Volts

Page

Comments

±I rnA Out, ±2 V In
±IOV
±IOV
±4 rnA Out, ±I V In
±I rnA Out, ±IO V In
Vss to VDD -4 V
±3 V
OVto+3V

±5 to ±15
±8.5 to ±15
±8.5 to ±15
±5
+5
(VnD-Vss )<18
VnD = +5, Vss = -5
VDD = +5, Vss = -5

8-3
8-11
8-21
8-33
8-49
8-63
8-77
8-87

2 CR, Current Output
VOUT
VOUT
Current Output
4 CR, lOUT> Parallel Data In
8 CR, 10 kn, RoUT> Serial Data In
8 CR, VOUT> Serial Data In
8 CR, VOUT> Serial Data In

Other Special Function Video Products
Model

Page

Comments

AD720
AD9300

8-19
8-41

RGB to NTSC and PAL Converter
4 x 1 Video Multiplexer

11IIIIIIII

ANALOG

WDEVICES
FEATURES
Two Quadrant Multiplication/Division
Two Independel:1t Signal Channels
Signal Bandwidth of 60MHz (lOUT)
Linear Control Channel Bandwidth of 5MHz
Low Distortion (to 0.01%)
Fully-Calibrated. Monolithic Circuit
APPLICATIONS
Precise High Bandwidth AGC and VCA Systems
Voltage-Controlled Filters
Video-Signal Processing
High-Speed Analog Division
Automatic Signal-Leveling
Square-Law Gain/Loss Control

Wideband Dual-Channel
Linear Multiplier/Divider
AD539 I
PIN CONFIGURATION
VX ICONTROLI L''-O---l
HFCOMP

2

BASE

COMMON

Vy2 1CHAN

2INPUTIl'6'J--o<:}---.---i""J g~~T

OUTPUT
COMMON

PRODUCT DESCRIPTION
The AD539 is a low-distortion analog multiplier having two
identical signal channels (YI and Y2), with a common X-input
providing linear control of gain. Excellent ac characteristics up
to video frequencies and a 3dB bandwidth of over 60MHz are
provided. Although intended primarily for applications where
speed is important the circuit exhibits good static accuracy in
"computational" applications. Scaling is accurately determined
by a band-gap voltage reference and all critical parameters are
laser-trimmed during manufacture.
The full bandwidth can be realized over most of the gain range
using the AD539 with simple resistive loads of up to 100H.
Output voltage is restricted to a few hundred millivolts under
these conditions. Using external op amps such as the ADSS39 in
conjunction with the on-chip scaling resistors, accurate multiplication can be achieved, with bandwidths typically as high as
50MHz.
The two channels provide flexibility. In single-channel applications
they may be used in parallel, to double the output current, or in
series, to achieve a square-law gain function with a control
range of over lOOdB, or differentially, to reduce distortion.
Alternatively, they may be used independently, as in audio
stereo applications, with low crosstalk between channels. Voltagecontrolled filters and oscillators using the "state-variable" approach
are easily designed, taking advantage of the dual channels and
common control. The AD539 can also be configured as a divider
with signal bandwidths up to ISMHz.
Power consumption is only 13SmW using the recommended
± 5V supplies. The ADS39 is available in three versions: the
"1" and "K" grades are specified for 0 to + 70°C operation and
"S" grade is gnaranteed over the extended range of - 55°C to
+ 12SoC. The J and K grades are available in either a hermetic
ceramic DIP (D) or a low cost plastic DIP (N), while the S
grade is available only in ceramic. ADS39 J-grade chips are also
available.

REV. A

DUAL SIGNAL CHANNELS
The signal voltage inputs, VYI and VY2 , have nominal full-scale
(FS) values of ± 2V with a peak range to ± 4.2V (using a negative
supply of7.SV or greater). For video applications where differential
phase is critical a reduced input range of ± I volt is recommended,
resulting in a phase variation of typically ± 0.20 at 3.S79MHz
for full gain. The input impedance is typically 4OOk.o. shunted
by 3pF. Signal channel distortion is typically well under 0.1% at
10kHz and can be reduced to 0.01% by using the channels
differentially.

COMMON CONTROL CHANNEL
The control channel accepts positive inputs, Vx , from 0 to + 3V
FS, ± 3.3V peak. The input resistance is 500.0.. An external,
grounded capacitor determines the small-signal bandwidth and
recovery time of the control amplifier; the minimum value of
3nF allows a bandwidth at mid-gain of about SMHz. Larger
compensation capacitors slow the control channel but improve
the high-frequency performance of the signal channels.

FLEXIBLE SCALING
Using either one or two external op amps in conjunction with
the on-chip 6k.o. scaling resistors, the output currents (nominally
± ImA FS, ± 2.2SmA peak) can be converted to voltages with
accurate transfer functions of Vw = - Vx Vy/2, Vw = - VxVy
or Vw = -2VxVy (where inputs Vx and Vy and output Vw
are expressed in volts), with corresponding full-scale outputs of
±3V, ±6V and ± l2V. Alternatively, low-impedance grounded
loads can be used to achieve the full signal bandwidth of 6OMHz,
in which mode the scaling is less accurate.

SPECIAL FUNCTION VIDEO PRODUCTS 8-3

II

AD539 -SPECIFICATIONS ( @TA=25"&, Vs = ± 5V, unless otherwise specified)

-

A.D539J
ConditiOns

SIGNAL·CHANNEL DYNAMICS
Minimal Configuration
Bandwidth. - 3d~
Maximum Output
Fecdthrougb,r< IMHz
f=lOMHz
Differential P~se Linearity
- IV
where RL is expressed in kilohms. For example, when RL =
lOOn, Vu ' = 67.5V. Table II provides more detailed data for
the case where both channels are used in parallel. The ADS39
can also be used with no external load (output pin 11 or 14
open-circuit), when Vu ' is quite accurately SV.

~

1

"- ....

L I-- ......
iii

i

A0638J ••

SPECS

SPECS

-1

/

-, V /

BASIC MULT1PLmR CONNECTIONS
Figure 2 shows the connections for the standard two-channel
multiplier, using op amps to provide useful output power and
the ADS39 feedback resistors to achieve accurate scaling. The
transfer function for each channel is

-, I
+0.01

+0.'

+1

+1.

CONTROL VOLTAGE - VIC

Figure 3a. Maximum ac Gain Error Boundaries

Vw = -VxVy
where inputs and outputs are expressed in volts (see TRANSFER
FUNCTION). At the nominal full-scale inputs of Vx = + 3V,
Vy = ±2V the full-scale outputs are ±6V. Depending on the
choice of op amp, their supply voltages usually need to be about
2V more than the peak output. Thus, supplies of at least ± 8V
are required; the ADS39 can share these supplies. Higher outputs
are possible if Vx and Vy are driven to their peak values of
+ 3.2V and ± 4.2V respectively, when the peak output is ± B.4V.
This requires operating the op amps at supplies of ± ISV. Under
these conditions it is advisable to reduce the supplies to the
ADS39 to ±7.SV to limit its power dissipation; however, with
some form of heat sinking it is permissible to operate the ADS39
directly from ± ISV supplies.

>--'-"'V.,=

-Yx·Vy,

>--.... V_=

Distortion is a function of the signal input level (Vy) and the
control input (V0. It is also a function of frequency, although
in practice the op amp will generate most of the distortion at
frequencies above 100kHz. Figure 3b shows typical results at
f = 10kHz as a function of Vx with Vy = 0.5 and 1.5V rms.

#

If" r---T--r------r------i
~ O.051--"..--~f_-"7'oL---+-------"'..t

.~.-----~,~----~'-------~
CONTROL VOlTAGE - V

-V.VV2

Figure 3b. Total Harmonic Distortion vs. Control Voltage

NOTE;
AU DECOUPUNG CAPACITOftS ARE O.47,.F CERAMIC.

Figure 2. Standard Dual-Channel Multiplier
Viewed as a voltage-controlled amplifier, the decibel gain is
simply
G

= 20 log Vx

where Vx is expressed in volts. This results in a gain of 10dB at
Vx = +3.l62V,OdBat Vx = +IV, -20dBat Vx = +O.IV,
and so on. In many ac applications the output offset voltage (for
Vx = 0 or Vy = 0) will not be of major concern; however, it
can be eliminated using the offset nulling method recommended
for the particular op amp, with Vx = Vy = O.
8-6 SPECIAL FUNCTION VIDEO PRODUCTS

In some cases it may be desirable to alter the scaling. This can
be achieved in several ways. One option is to use both the Z
and W feedback resistors (see Figure 1) in parallel, in which
case Vw = - V x V y/2. This may be preferable where the output
swing must be held at ± 3V FS (± 6.7SV pk), for example, to
allow the use of reduced supply voltages for the op amps. Alternatively, the gain can be doubled by connecting both channels
in parallel and using only a single feedback resistor, in which
case Vw = -2VxYyand the full-scale output is ± 12V. Another
option is to insert a resistor in series with the control-channe1
input, permitting the use of a large (for example, 0 to + lOY)
control voltage. A disadvantage of this scheme is the need to

REV. A

AD539
adjust this resistor to accommodate the tolerance of the nominal
soon input resistance at pin I. The signal channel inputs can
also be resistively attenuated to permit operation at higher values
ofVy , in which case it may often be possible to partially compensate
for the response roll-off of the op amp by adding a capacitor
across the upper arm of this attenuator.

output at low frequencies and to - 60dB up to 20MHz with
careful board layout. The corresponding pulse response is shown
in Figure 4b for a signal input of Vy of :t IV and two values of
Vx (+ 3V and +O.IV).

Signal-Channel aC'and Transient Response
The HF response is dependent almost entirely on the op amp.
Note that the "noise gain" for the op amp in Figure 2 is determined
by the value of the feedback resistor (6kn) and the 1.2SkH
control-bias resistors (Figure I). Op amps with provision for
external frequency compensation (such as the AD301 and ADSI8)
should be compensated for a closed-loop gain of 6.
The layout of the circuit components is very important if low
feed through and flat response at low values of Vx is to be maintained (see GENERAL RECOMMENDATIONS).
For wide-bandwidth applications requiring an output voltage
swing greater than :t IV, the LH0032 hybrid op-amp is recommended. Figure 4a shows the HF response of the circuit of
Figure 2 using this amplifier with Vy = IV rms and other
conditions as shown in Table I. CF was adjusted for IdB peaking
at Vx = + IV; the - 3dB bandwidth exceeds 2SMHz. The
effect of signal feed through on the response becomes apparent
at Vx = +O.OIV. The minimum feedthrough results when Vx
is taken slightly negative to ensure that the residual control-channel
offset is exceeded and the dc gain is reliably zero. Measurements
show that' the feed through can be held to - 90dB relative to full

Vx = +3V

Vx = +O.IV

Figure 4b. Multiplier Pulse Response Using LH0032 Op
Amps
Table I. Summary of Operating Conditions and Per[ormance for the AD539 When Used with Various External
Op-Amp Output Amplifiers
OpAmpSupplyVoltages
Op Amp Compensation Capacitor
Feedback Capacitor, C p
-3dBBandwidth,Vx = +lV
Load Capacitance
HF Feedthrnugh,
Vx = -O.OlV,f = 5MHz
rIDS Output Noise,
Vx = + lV,BW 10Hz-10kHz
Vx = + lV,BWlOHz-5MHz

AD7U'

AD5539'

LH0032'

±15V
None
None
900kHz
3000

Figure 5a. Minimal Single-Channel Multiplier

-~~,-~-~-~-~,-~--+-~-~
SIGNAL INPUT BIAS VOLTAGE - V

Figure Sb shows the HF response for Figure Sa with the ADS39
in a carefully-shielded son test-environment; the test system
response was first characterized and this background removed
by digital signal processing to show the inherent circuit response.

Differential Configurations
When only one signal channel must be handled it is often advantageous to use the channels differentially. By subtracting the
CHI and CH2 outputs any residual transient control feedthrough
is virtually eliminated. Figure 6a shows a minimal configuration
where it is assumed that the host system uses differential signals
and a son environment throughout. This figure also shows a
recommended control-feedforward network to improve large-signal

V,,_+3.1UV

v.

m

Figure 5d. Differential Phase Linearity in Minimal
Configuration for a Typical Device

+O.31IV

Figure 5b. HF Response in Minimal Configuration
In many applications phase linearity over frequency is important.
Figure Sc shows the deviation from an ideal linear-phase response
for a typical ADS39 over the frequency range dc to IOMHz, for

,
f--.,.

'-,

/

/

.

FREQUENCY

/- r-~

Figure 6a. High-Speed Differential Configuration

response time. The control feedthrough glitch is shown in Figure
6b, where the input was applied to CHI and only the output of
CHI was displayed on the oscilloscope. The improvement obtained
when CHI and CH2 outputs are viewed differentially is clear in
Figure 6c. The envelope rise-time is of the order of 4Ons.
Lower distortion results when CHI and CH2 are driven by

~

Mit!

Figure 5c. Phase Linearity Error in Minimal Configuration
8-8 SPECIAL FUNCTION VIDEO PRODUCTS

complementary inputs and the outputs· are utilized differentially,
using a circuit such as Figure 7a. Resistors RI and R2 should
have a value in the range 100 to loOon.

REV. A

AD539
,C

0fIU

,'*"

•

I

t

1

.

.....

~

~-

i

I

t

t

,~

.

j ~

1
Figure 6b. Control Feedthrough One Channel of
Figure 6a

I

: .. ,'

- +-1

'--1-'

1-

I

I • I

I

Figure 6e. Control Feedthrough Differential Mode,
Figure 6a

They minimize a secondary distortion mechanism caused by a
collector-modulation effect in the controlled cascodes (see CIRCUIT DESCRIPTION) by keeping the voltage-swing at the
outputs to an acceptable level. Figure 7b shows the improvement
in distortion over the standard confIguration (compare Figure
3b). Note that the Z nodes (pins 10 and 15) are returned to the
control input; this prevents the early onset of output-transistor
saturation.

A 50MHz VOLTAGE-CONTROLLED AMPLIFIER
Figure 8 is a circuit for a 50MHz voltage-controlled amplifier
(VCA) suitable for use in high-quality-video-speed applications.
The outputs from the two-signal channels of the ADS39 are
applied to the op-amp in a subtracting confIguration. This connection has two main advantages: fIrSt, it results in better rejection
of the control voltage, particularly when over-driven (Vx3.3V). Secondly, it provides a choice of either non-inverting
or inverting responses, using either' inputs V Y1 or V Y2 respectively.
In this circuit, the output of the op-amp will equal:
VOUT = Vx

~Vl-VY2)

forVx>O

Hence, the gain is unity at Vx = +2V. SinceVx can over-range
to +3.3V, the maximum gain in this confIguration is about
4.3dB. (Note: If pin 9 of the ADS39 is grounded, rather than
connected to the output of the 5539N, the maximum gain becomes
IOdB.)

v,o----*-I
v"o-"':"'---l

v"o---:....r61

Figure 7a. Low-Distortion Differential Configuration

01: THOMPSON·CSF BAR·l00R SIMILAR SCHOTIKV DIODE
'¢'
SHORT, DIRECT CONNECTION TO GROUND PLANE.
~9V

0.05 ....- - - - - . , . . - - - - - - . . . , . . . . . - - - - - - . . ,

,

i!

I
~

~

0,0251-------+-------+-------1

~

Figure 8. A Wide Bandwidth Voltage-Controlled Amplifier

The - 3dB bandwidth of this circuit is over 50MHz at full gain,
and is not substantially affected at lower gains. Of course, when
Vx is zero (or slightly negative, to override the residual input
offset) there is still a small amount of capacitive feedthrough at
high frequencies; therefore, extreme care is needed in laying out
the PC board to minimize this effect. Also, for small values of
Vx , the combination of this feedthrough with the multiplier
output can cause a dip in the response where they are out of
phase. Figure 9a shows the ac response from the noninverting
v~'"'

+3.162V

v,

>IV

v~""

+D.316V

..=-,

°o~------~,-------+----------~
CONTROL VOLTAGE - Vx

Figure 7b. Distortion in Differential Mode Using
LH0032 Op Amp

~

m

REV. A

"-

ijj -20

~

~
Even lower distortion (0.01%, or -80dB) has been measured
using two output op amps in a confIguration similar to Figure 2
connected as virtual-ground current-summers (to prevent the
modulation effect). Note that to generate the difference output
it is merely necessary to connect the output of the CHI op amp
to the Z node of CH2. In this way, the net input to the CHZ op
amp is the difference signal, and the low-distortion resultant
appears as its output.

."l.

z"

-30

~

..

V~=

+O.lV

V~_

+D.032V

V~_

+O.OlV

.......

VJ~O.01V

."l..~

-'"
I-""""V
FRfOUENCY _ MHz

Figure 9a. AC Response of the VCA at Different Gains
Vy =O.5VRMS
SPECIAL FUNCTION VIDEO PRODUCTS 8-9

II

AD539
input, with the response from the inverting input, Vyz, essentially
identical. Test conditions: VY1 =O.5V rms for values of Vx from
+ IOmV to +3.16V; this is with a 7Sn load on the output. The
feedthrough at Vx = -10mV is also shown.

NUMEAA"rOR1

v••

The transient response of the signal channel at Vx = + 2V,
Vy=VoUT = ± IV is shown in Figure 9b; with the VCA driving
a 7Sn load. The rise and fall-times are approximately 7ns.

NOlf.: OECOUPll

or,.". SUI'PUES

NUMERATOR!

v.

Figure 10a. Two-Channel Divider with 1V Scaling

Figure 9b. Transient Response of the Voltage-Controlled
Amplifier Vx = +2 Volts Vy =;!: 1 Volt
A more detailed description of this circuit, including differential
gain and phase characteristics, is given in the application note
"Low Cost, Two Chip Voltage-Controlled Amplifier and Video
Switch" availabk from Analog Devices.
BASIC DIVIDER CONNECTIONS
Standard Scaling
The ADS39 provides excellent operation as a two-quadrant
analog divider in wide-band wide gain-range applications, with
the advantage of dual-channel operation. Figure lOa shows the
simplest connections for division with a transfer function of
Vy = -VuVwNx
Recalling that the nominal value ofVu is IV, this can be
simplified to
Vy

=

-VwlVx

where all signals are expressed in volts. The circuit thus exhibits
unity gain for Vx = + IV and a gain of 40dB when Vx =
+O.OIV.
The output swing is limited to ± 2V nominal full-scale and
±4.2V peak (using a - Vs supply of at least 7.SV for the ADS39).
Since the maximum ioss is lOdB (at Vx = 3.l62V), it follows
that the maximum input to Vw should be ±6.3V (4.4V rms)
for low distortion applications, and no more than ± 13.4V (9.5V
rms) to avoid clipping. Note that offset adjustment will be needed

8-10 SPECIAL FUNCTION VIDEO PRODUCTS

Figure 1Ob. HF Response of Figure 70a Divider
for the op amps to maintain accurate de levels at the output in
high gain applications: the "noise gain" is 6VlVx , or 600 at Vx
= +O.OIV.
The gain-magnitude response for this configuration using the
LHOO32 op amps with nominally 12pF compensation (pins 2 to
3) and C F = 7pF is shown in Figure lOb; of course, other
amplifiers !nay also be used. Since there is some manufacturing
variation in the HF response of the op amps, and load conditions
will also affect the response, these capacitors should be adjustable:
5-15pF is recommended for both positions. The bandwidth in
this configuration is nominally 17MHz at Vx = +3.162V,
4.5MHzatVx = +IV,3S0kHzatVx = +0.IVand3SkHzat
Vx = +O.OIV. The general recommendations regarding the use
of a good ground plane and power-supply decoupling should be
carefully observed.

REV. A

Low Cost
Analog Multiplier
AD633 I

r.ANALOG
WDEVICES
FEATURES
Four-Quadrant Multiplication
Low Cost a-Pin Package
Complete-No External Components Required
Laser-Trimmed Accuracy and Stability
Total Error Within 2% of FS
Differential High Impedance X and V Inputs
High Impedance Unity-Gain Summing Input
Laser-Trimmed 10 V Scaling Reference
APPLICATIONS
Multiplication, Division, Squaring
Modulation/Demodulation, Phase Detection
Voltage-Controlled Amplifiers/ Attenuators/Filters

AD633 CONNECTION DIAGRAMS
8-Pin Plastic DIP (N) Package
X1

+Vs

X2

W

Y1

z

Y2

-VS

8-Pin Plastic SOIC (R) Package
PRODUCT DESCRIPTION
The AD633 is a functionally complete, four-quadrant, analog
multiplier. It includes high impedance, differential X and Y
inputs and a high impedance summing input (Z). The low
impedance output voltage is a nomina110 V full scale provided
by a buried Zener. The AD633 is the first product to offer
these features in modestly priced S-pin plastic DIP and SOle
packages.
The AD633 is laser calibrated to a guaranteed total accuracy of
2% of full scale. Nonlinearity for the Y-input is typically less
than 0.1 % and noise referred to the output is typically less than
100 ,...V rms in a 10 Hz to 10 kHz bandwidth. A 1 MHz bandwidth, 20 V/,...s slew rate, and the ability to drive capacitive
loads make the AD633 useful in a wide variety of applications
where simplicity and cost are key concerns.
The AD633's versatility is not compromised by its simplicity.
The Z-input provides access to the output buffer amplifier, enabling the user to sum the outputs of two or more multipliers,
increase the multiplier gain, convert the output voltage to a current, and configure a variety of applications.
The AD633 is available in an S-pin plastic mini-DIP package
(N) and S-pin SOle (R) and is specified to operate over the ooe
to +70"e commercial temperature range.

PRODUCT HIGHLIGHTS
1. The AD633 is a complete four-quadrant multiplier offered in
low cost S-pin plastic packages. The result is a product that
is cost effective and easy to apply.
2. No external components or expensive user calibration are
required to apply the AD633.
3. Monolithic construction and laser calibration make the device
stable and reliable.
4. High (10 Mn) input resistances make signal source loading
negligible.
5. Power supply voltages can range from ±S V to ±lS V. The
internal scaling voltage is generated by a stable Zener diode;
multiplier accuracy is essentially supply insensitive.

REV. 0

SPECIAL FUNCTION VIDEO PRODUCTS 8-11

•

AD633 - SPECIFICATIONS

(TA

= +25°C, Vs = ±15 v, RL 2: 2 kO)

Model

AD633J

w

TRANSFER FUNCTION
Parameter
MULTIPLIER PERFORMANCE
Total Error
T min to T max
Scale Voltage Error
Supply Rejection
Nonlinearity, X
Nonlinearity, Y
X Feedthrough
Y Feedthrough
Output Offset Voltage
DYNAMICS
Small Signal BW
Slew Rate
Settling Time to 1%
OUTPUT NOISE
Spectral Density
Wideband Noise

Min

Conditions
-10 V

5

X, Y

5

+ 10 V

SF = 10.00 V Nominal
Vs = ±14 V to ±16 V
X = ±IOV, Y = +IOV
Y = ±IO V, X = +10 V
Y Nulled, X = ±IO V
X Nulled, Y = ±IO V

Offset Voltage X, Y
CMRRX, Y
Bias Current X, Y, Z
Differential Resistance
POWER SUPPLY
Supply Voltage
Rated Performance
Operating Range
Supply Current

Typ

Max

Unit

±I
±3
±0.2S%
±0.01
±0.4
±O.I
±0.3
±O.I

±2

%
%
%
%
%
%

Va = 0.1 V rms,
Va = 20 V p-p
l1Vo=20V

f = 10 Hz to 5 MHz
f = 10 Hz to 10 kHz

Full
Full
Full
Full
Full
Full
% Full
% Full
mV

±l
±O.4
±l
±O.4
±SO

±s

OUTPUT
Output Voltage Swing
Short Circuit Current
INPUT AMPLIFIERS
Signal Voltage Range

=

I
20

MHz
V/",s

2

",s

0.8
I
90

",V/y'Hz
mVrms
",Vrms

±ll
30
Differential
Common Mode

±10
±10

VCM = ±IOV,f=SOHz

60

V
rnA

40

V
V
mV
dB
",A
MO

±30

±S
80
0.8
10

2.0

±lS

V
V

6

rnA

±IS

±s
Quiescent

4

NOTES
Specifications shown in boldface afe tested on all production units at electrical test. Results from those tests are used
min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS'
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2 • • • • • • • • • . • • • • • • • • 500 mW
Input Voltages' . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Output Short Circuit Duration . . . . . . . . . . . . ... Indefinite
Storage Temperature Range . . . . . . . . . . . -65°C to + 150°C
Operating Temperature Range . . . . . . . . . . . . . O°C to + 70°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . + 300°C

Scale
Scale
Scale
Scale
Scale
Scale
Scale
Scale

to

calculate outgoing quality levels. All

AD633 ORDERING GUIDE
Model

Description

Package
Option*

AD633JN
AD633JR

8-Pin Plastic DIP
8-Pin Plastic SOIC

N-8
R-8

*N = Plastic DIP; R = Small Outline IC (SOlC).
For outline information see Package Information
section.

NOTES
IStresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational section of this specification is not implied.
'g. Pin Plastic Package: ij]A ~ l6S oCIW; g·Pin Small Outline Package: ij]A ~
ISSoC/W.
3For supply voltages less than :t 18 V, the absolute maximum input voltage is
equal to the supply voltage.

8-12 SPECIAL FUNCTION VIDEO PRODUCTS

REV. 0

AD633
FUNCTIONAL DESCRIPTION
The AD633 is a low cost multiplier comprising a translinear
core, a buried Zener reference, and a unity gain connected output amplifier with an accessible summing node. Figure I shows
the functional block diagram. The differential X and Y inputs
are converted to differential currents by voltage-to-current converters. The product of these currents is generated by the multiplying core. A buried Zener reference provides an overall scale
factor of 10 V. The sum of (X • Y)/IO + Z is then applied to
the output amplifier. The amplifier summing node Z allows the
user to add two or more multiplier outputs, convert the output
voltage to a current, and configure various analog computational
functions.

X1

+Ifs

X2

W

APPLICATIONS
The AD633 is well suited for such applications as mOdulation
and demodulation, automatic gain control, power measurement,
voltage controlled amplifiers, and frequency doublers. Note that
these applications show the pin connections for the AD633JN
pinout (8-pin DIP), which differs from the AD633JR pinout
(8-pin SOle).
Multiplier Connections
Figure 3 shows the basic connections for multiplication. The X
and Y inputs will normally have their negative nodes grounded,
but they are fully differential, and in many applications the
grounded inputs may be reversed (to facilitate interfacing with
signals of a particular polarity, while achieving some desired
output polarity) or both may be driven.
+15V
O.111F

r-v

(+
X
INPUT

Y1

Z

Y2

-Vs

(X1-X2) (Y1-Y2)

l-

W=

10V

+Z

OPTIONAL SUMMING
INPUT,Z

Figure 1. AD633 Functional Block Diagram (AD633JN
Pinout Shown)
Figure 3. Basic Multiplier Connections

Inspection of the block diagram shows the overall transfer function to be:
(Eq.l)
ERROR SOURCES
Multiplier errors consist primarily of input and output offsets,
scale factor error, and nonlinearity in the multiplying core. The
input and output offsets can be eliminated by using the optional
trim of Figure 2. This scheme reduces the net error to scale factor errors (gain error) and an irreducible nonlinearity component
in the multiplying core. The X and Y nonlinearities are typically
0.4% and 0.1% of full scale, respectively. Scale factor error is
typically 0.25% of full scale. The high impedance Z input
should always be referenced to the ground point of the driven
system, particularly if this is remote. Likewise, the differential
X and Y inputs should be referenced to their respective grounds
to realize the full accuracy of the AD633.

Squaring and Frequency Doubling
As Figure 4 shows, squaring of an input signal, E, is achieved
simply by connecting the X and Y inputs in parallel to produce
an output of E2 /10 V. The input may have either polarity, but
the output will be positive. However, the output polarity may
be reversed by interchanging the X or Y inputs. The Z input
may be used to add a further signal to the output.
+1SV
O.111F

~2E

W=1-OV---

+Ifs
±SOmV
SOkU

::..>-"""v--......--o TO APPROPRIATE

Figure 4. Connections for Squaring

INPUT TERMINAL

1kQ

( E.g., X2,X 2,Z)

When the input is a sine wave E sin wt, this squarer behaves as
a frequency doubler, since

IE sin wl)2
10 V
Figure 2. Optional Offset Trim Configuration

REV. 0

E2
=

20 V 11 - cos 2 WI)

(Eq. 2)

Equation 2 shows a de term at the output which will vary
strongly with the amplitude of the input, E. This can be

SPECIAL FUNCTION VIDEO PRODUCTS 8-13

II

· AD633
avoided using the connections shown in Figure 5, where an RC
nerwork is used to generate two signals whose product has no dc
term. It uses the identity:
cos 6 sin 6 =

I

2 (sin 2 61

The amplitude of the output is only a weak function of frequency: the output amplitude will be 0.5% too low at
w = 0.9 Wo and w = 1.1 woo

(Eq.3)
+15V

At Wo = lICR, the X input leads the input signal by 45° (and
is attenuated by y'Z), and the Y input lags the X input by 45°
(and is also attenuated by y'Z). Since the X and Y inputs are
90° out of phase, the response of the circuit will be (satisfying
Equation 3.):

which has no dc component. Resistors RI and R2 are included
to restore the output amplitude to 10 V for an input amplitude
of 10 V.

O.l~F

~ w= 10

E

E'

Rl
lkll

Figure 5. "Bounceless" Frequency Doubler

R
10kll

'--------------ow=.J_ (10V )E
Figure 6. Connections for Squaring Rooting
Generating Inverse Functions
Inverse functions of multiplication, such as division and square
rooting, can be implemented by placing a multiplier in the feedback loop of an op amp. Figure 6 shows how to implement a
square rooter with the transfer function
W = V-(IOVIE

Likewise, Figure 7 shows how to implement a divider using
a multiplier in a feedback loop. The transfer function for the
divider is

(Eq.5)

E
Ex

W= -(lOVI-

(Eq.6)

for the condition E(IOV)

cos ro'

1-----...........--... (IOV) slnro'
RS

1-____-t--+ '61111

f

=:.:;

11Hz

Figure 13. Voltage Controlled Quadrature Oscillator

8-16 SPECIAL FUNCTION VIDEO PRODUCTS

REV. 0

Typical Characteristics-AD633
R2

R3

R4

lkG

IOkG

10kll
+15V

1---.-0 E OUT

1~
Eo--+-I-I

R9
10kll

lN4148

Figure 14. Connections for Use in Automatic Gain Control Circuit
800

I,l OdS =O.1V rms, RL = 2k!l I

700

cu}

.,...

~CL"000PF

600

':!

..........

I 500

I

r'o

ffi

~400

\

a:

~-20

200

crTT
lOOk

100

10M

1M

o

-60

-40

20

-20

FREQUENCY - Hz

/

//

90

120

140

t)..
TYPICAL
FORX,Y
INPUTS

., 60

~LINPUTS

"i' 50

1"\
'\

a:

!l!4O
o
30

20
10
12

14

16

18

20

PEAK POSITIVE OR NEGATIVE SUPPLY - Volts

Figure 17. Input and Output Signal Ranges vs. Supply
Voltages

REV. 0

100

....

70

2~ '/

/

10

80

80

4

8

60

Figure 16. Input Bias Current vs. Temperature (X, Y, or Z
Inputs)

/

/

40

TEMPERATURE _ DC

Figure 15. Frequency Response

OUTPUT, RL"

II

r- r-

o

.,; 300

NORMAL

-30
10k

r-. r-

:::I

o

100

lk

10k

lOOk

1M

FREQUENCY - Hz

Figure 18. CMRR vs. Frequency
SPECIAL FUNCTION VIDEO PRODUCTS 8-17

AD633
1000

IY-~llJJm~II

~;;

i t1r-.1ttT~:t+=t:+m:~
I
1

X·FEEDTHAOUGH

"

0.5

...

1--+-+-I-+t--+--t-H-t--t--t-I-H-l-lH-H

I

0 1'-0.....J..-I.....L..L1J..oo-l.---L....L.J.J.lk---L-I.....L..oU10k-l......JL..J..1Uook

FREQUENCY - Hz

Figure 19. Noise Spectral Density vs. Frequency

8-18 SPECIAL FUNCTION VIDEO PRODUCTS

1\

1\

II

o

10

100

lk

I

I

10k
lOOk
FREQUENCY - Hz

1M

10M

Figure 20. AC Feedthrough vs. Frequency

REV. 0

1IIIIIIII ANALOG

WDEVICES

RGB to NTSCIPAL Encoder
AD720 I

FEATURES
Separate Chrominance. Luminance. and Composite
Video Outputs
Drives 75 n Reverse-Terminated Loads
No External Filters or Delay Lines Required
Comes in Compact 28-Pin PLCC
Logic Selectable NTSC or PAL Encoding Modes
Logic Selectable Power-Down Mode

PIN CONFIGURATION

APPUCATIONS
RGB to NTSC or PAL Encoding

AGND 7

AD720
TOPV1EW
(Not To seole)

PRODUCT DESCRIPTION
The AD720 RGB to NTSCIPAL Encoder is a BiCMOS LSI
circuit that converts red, green and blue color component signals into their corresponding luminance (baseband amplitude)
and chrominance (subcarrier amplitude/phase) signals in ace dance with either NTSC or PAL standards. These t
are also combined to provide a composite video
three outputs are available separately at
standard signal levels as required for dri
terminated cables.
The AD720 provides a complete, fully ca1ibrat
quiring only termination resistors, decoupling netw s, a cl
input at four times the subcarrier frequency, and a composite
sync pulse. The AD720 also has two control inputs: one input
selects the TV standard (NTSClPAL) and the other (ENCD)
powers down most sections of the chip when the encoding function is not in use. All logical inputs are CMOS compatible. The
chip operates from ± S V supplies.

All required low-pass filters are on chip. After the input signals
pass through a precision RGB to YUV encoding matrix, two
on-chip low-pass filters limit the bandwidth of the U and V
color-difference signals to 1.2 MHz prior to binary modulation;
a third low-pass filter at S. S MHz follows the modulators to
limit the harmonic content of the output. The U and V signal
delays in the chroma filters are matched by an on-chip sampleddata delay line in the Y signal path; to prevent aliasing, a prefilter at S MHz is included ahead of the delay line and a second
S MHz filter is added after the delay line to suppress harmonics
in the output. The low-pass filters are optimized for minimum
pulse overshoot.
The AD720 is available in a 28-pin plastic leaded chip carrier
for the O"C to 70"C commercial temperature range.

NS

GRIN
BLIN

CRMA

CMPS

LUMA
AGND
DGND

APOS
DPOS
VNEG

·callow level powers down chip when not in use.
A logical high level input selects NTSC encoding;
10gica1low level selects PAL encoding.
k input at four times subcarrier frequency.
Input pin for composite television synchronization
pulses.
Red Component Input.
Green Component Input.
Blue Component Input. These three analog inputs are
oto +700 mV for PAL or 0 to 714 mV for NTSC.
Chrominance Output (Subcarrier Only).
900 mV p-p plus burst (286 mV p-p for NTSC,
300 mV p-p for PAL).*
Composite video output,
-300 mV to +700 mV peak (PAL)
or -286 mV to 9S0 mV (NTSC).*
Luminance plus SYNC output,
-300 mV to +714 mV peak (PAL)
or -286 mV to 714 mV (NTSC).*
Analog Ground Connections (4).
Digital Ground Connections (3).
Analog Positive Supply (+S V ±S%) (3).
Digital Positive Supply (+ 5 V ± 5%) (2).
System Negative Supply (-S V ±S%) (2).

"Measured at 75

n reverse-tenninated load; double these values at Ie pins.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

REV. 0

SPECIAL FUNCTION VIDEO PRODUCTS 8-19

II

AD720
+liV

-5V

ENCODE

R -.........- - - - I

I--.;....._~~-- C-SYNC

+liV

VIDEO
INPUTS

TIMING
INPUTS

0 ...............- - - - 1

8 -.........-.......;--1

_

....---4FSC

N~j[--...----~
ENCODED
OUTPUTS

+liV

-5V

Typical Application

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

8-20 SPECIAL FUNCTION VIOEO PRODUCTS

REV. 0

10 MHz, 4-Quadrant
Multiplier/Divider
AD734 I

r.ANALOG
WDEVICES
FEATURES
High Accuracy
0.1% Typical Error
High Speed
10 MHz Full-Power Bandwidth
450 V/p.s Slew Rate
200 ns Settling to 0.1 % at Full Power
Low Distortion
-80 dBc from Any Input
Third-Order IMD Typically -75 dBc at 10 MHz
Low Noise
94 dB SNR, 10 Hz to 20 kHz
70 dB SNR, 10 Hz to 10 MHz
Direct Division Mode
2 MHz BW at Gain of 100
APPLICATIONS
High Performance Replacement for AD534
Multiply, Divide, Square, Square Root
Modulator, Demodulator
Wideband Gain Control, RMS-DC Conversion
Voltage-Controlled Amplifiers, Oscillators, and Filters
Demodulator with 40 MHz Input Bandwidth

PRODUCT DESCRIPTION
The AD734 is an accurate high speed, four-quadrant analog
multiplier that is pin-compatible with the industry-standard
AD534 and provides the transfer function W = XYIU. The
AD734 provides a low-impedance voltage output with a fullpower (20 V pk-pk) bandwidth of 10 MHz. Total static error
(scaling, offsets, and nonlinearities combined) is 0.1 % of Full
Scale. Distortion is typically less than - 80 dBc and guaranteed.
The low-capacitance X, Y and Z inputs are fully differential. In
most applications, no external components are required to define
the function.
The internal scaling (denominator) voltage U is 10 V, derived
from a buried-Zener voltage reference. A new feature provides
the option of substituting an external denominator voltage,
allowing the use of the AD734 as a two-quadrant divider with a
1000: I denominator range and a signal bandwidth that remains
10 MHz to a gain of 20 dB, 2 MHz at a gain of 40 dB and
200 kHz at a gain of 60 dB, for a gain-bandwidth product of
200 MHz.
The advanced performance of the AD734 is achieved by a combination of new circuit techniques, the use of a high speed
complementary bipolar process and a novel approach to laser·
trimming based on ac signals rather than the customary dc
methods. The wide bandwidth (>40 MHz) of the AD734's input stages and the 200 MHz gain-bandwidth product of the
multiplier core allow the AD734 to be used as a low distortion

REV. A

CONNECTION DIAGRAM
14-Pin DIP
(Q Package)

X INPUT [

Xl

1 •

VP POSITIVE SUPPLY
DD DENOMINATOR DISABLE

X2
UO

W -OUTPUT

3

DENOMINATOR [ Ul
INTERFACE

Zl ] ZINPUT
Z2

U2

9

ER REFERENCE VOLTAGE.

8

VN - NEGATIVE SUPPLY

demodulator with input frequencies as high as 40 MHz as long
as the desired output frequency is less than 10 MHz.
The AD734AQ and AD734BQ are specified for the industrial
temperature range of -40°C to +85°e and come in a 14-pin
ceramic DIP. The AD734SQl883B, available processed to MILSTD-883B for the military range of -55°e to + 12Soe, is available in a 14-pin ceramic DIP.
PRODUCT HIGHLIGHTS
The AD734 embodies more than two decades·of experience in
the design and manufacture of analog multipliers, to provide:
1. A new output amplifier design with more than twenty times
the slew-rate of the AD534 (450 V/tJ-s versus 20 V/tJ-s) for a
full power (20 V pk-pk) bandwidth of 10 MHz.
2. Very low distortion, even at full power, through the use of
circuit and trimming techniques that virtually eliminate all of
the spurious nonlinearities found in earlier designs.
3. Direct control of the denominator, resulting in higher multiplier accuracy and a gain-bandwidth product at small denominator values that is typically 200 times greater than that of
the AD534 in divider modes.
4. Very clean transient response, achieved thrt;lugh the use of a
novel input stage design and wide-band output amplifier,
which also ensure that distortion remains low even at high
frequencies.
5. Superior noise performance by careful choice of device ~m­
etries and operating conditions, which provide a guaranteed
88 dB of dynamic range in a 20 kHz bandwidth.

SPECIAL FUNCTION VIDEO PRODUCTS 8-21

8

AD734-SPECIFICATIONS ITA = +25"C, +Ys =YP = +15 Y, -Ys =YN = -15 Y, RL 22 k(ll
TRANSFEll FUNCll0N

Parameter
MULTIPLIER PERFORMANCE
Transfer Function
Total Static Error'
Over T .... to T_
VI. Temperature
VI. Either Supply
Peak Nonlinearity
THO'

Feedthrough
Noise (RTO)
Spectral Density
Total Output Noise

CoadiIioas

A
Min Typ

Tmin to Tmax
:tV. = 14 V to 16 V
-IOV:s; X:s; +IOV, Y = +IOV
-IOV:s;Y:s; +IOV,X= +IOV
X = 7 V rms, Y = + io V, f :s; 5 kHz
Tmin toT_
Y = 7V rms, X = +IOV, f:s; 5 kHz
TmiP, to TI:DQ:
X = 7V rms' Y = nulled, f:s; 5 kHz
Y = 7 V rms, X = nulled, f:s; 5 kHz
X=Y=O
100 Hz to I MHz
10 Hz to 20 kHz

-85

Il

Tmin to Tnwc
70
85
50

Differential
Differential

DENOMINATOR INTERFACES CUO, UI, & U2)
Operating Rsnge.
Denominstor Rsnge
Interface Resistor
Ui to U2

X = Y = 0, Input to Z
From X or Y Input, CL :s; 20 pF
W:s; 7Vrms

POWER SUPPUES, :tV.
Operating Supply Rsnge
Quiescent Current

-94

-94

66
56

70

70

85
50

.,.V/yHZ

70

SO
85

2

2

2

VNto VP-3
1000:1
28
:t12

300

SOO

SO

:t12

450

10
450

125
200

125
200

8

dBc

%
V
%
%
ns
MHz
V
mV
mV
mV
mV
mV
mV
dB
dB
dB
nA
nA

kO
pF

VNto VP-3
1000:1
28

72
8

dBc

20

sO

10

-88
-85

!lO

50

72

dBc
dBc

SO

SO

dBc
dBc

-60
-66

15
25
10
12

70

%
%

dBc

5
15
5
6
10

ISO

%I'C
%IV

dBc

40
:t12.5

300

%
%

-57

W= XYIU
I
1.25 x U
0.3
1
100

54

Uails

-60

1.0

-88

W= XYIU
I
1.25 x U
0.15
8.65
100

300
400

:t12

8

-85
-85

-85

VNtoVP-3
1000:1
28

Slew Rate
Settling Time
To 1%
To 0.1%
Short-Circuit Current

-55

40
:t12.5

20
50

54
50
70

-58

1.0

-88

Tmin to T_

TmiD to Tmax

-85

15
25
10

Tmin to T_

OUTPUT AMPUFIER (W)
Output Voltage Swing
Open-Loop Voltage Gain
Dynamic Response
3 dB Bandwidth

-85

-60
-66

40
:t12.S

Z Input Offset Voltage

Input Resistance
.Input Cspscirance

-74
-70
-76

W= XYIU
I
1.25 x U
0.3
0.8
100

Tmin toTIJWI:

CMRR
Input Bias Current (X, Y, Z Inputs)

-so

-57

-85

Y Input Offset Voltage

O.OS

-60

Max

W = XY/IO
0.1
0.4
1.25
0.004
0.01
0.05
0_05
0.025

-66
-63

1.0

-94

S
Min Typ

0.05
O.D2S

-55

Differential or Common Mode

f:s; I kHz
T min to Tmu:
f= 5 kHz

om

-58

-85

Max

W= XY/IO
0.1
0.25
0.6
0.003

0.025

DMDER PERFORMANCE (y = 10 V)
Transfer Function
Gain Error
Y = 10 V, U = 100 mV to 10 V
y:s; 10V
X Input Clipping Level
U Input ScsliDg Error'
T roin to Tmax
(Output to 1%)
U = I V to 10 V Step, X = I V

Z Input PSRR (Either Supply)

Min Typ

W = XY/IO
0.1
0.4
1
0.004
0.01
0.05
0.05

-IOV:s;X,Y:s;IOV

Tmin toTnwr:

INPUT INTERFACES (X, Y, & Z)
3 dB Bandwidth
Operating Rsnae
X Input Offset Voltage

B
Max

V

kO

72

V
dB

10
450

MHz
VI.,.s

125

ns
ns
mA

+ 20 V or - 20 V Output Step

Tmin to Tmin

TOlin

toTmu

20

SO

SO

:t8
6

9

:t16.5 :t8
12
6

20

SO

SO

9

:t16.5 :t8
12
6

20

200
SO

SO

9

:t16.5 V
12
mA

NOTES
'Fisures given are percent of full scale (e.g., 0.01% = I mV).
'dBc refers to deciBels relstive to the full scale input (carrier) level of 7 V rms.
'See Figure 10 for test circuit.
All min and max specifications are guaranteed. Specifications in Boldface are tested on sO production ullits at final electrical test.
Specifications subject to change without notice.

8-22 SPECIAL FUNCTION VIDEO PRODUCTS

REV. A

AD734
ABSOLUTE MAXIMUM RATINGS'
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2
for T J max = 175°C ..................... 500 mW
X, Y and Z Input Voltages . . . . . . . . . . . . . . . . . VN to VP
Output Short Circuit Duration . . . . . . . . . . . . . . . Indefmite
Storage Temperature Range
Q ........................... -65°C to + 150"C
Operating Temperature Range
AD734A, B ..................... -40°C to +85°C
AD734S ....................... -55°C to + 125°C
Lead Temperature Range (soldering 60 sec) . . . . . . . . +30QoC
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

ORDERING GUIDE
Model

AD734AQ
AD734BQ
AD734SQ/883B

Temperature
Range

Package
Option·

-40°C to +85°C
-40°C to +85°C
- 55°C to + 125°C

Q-14
Q-14
Q-14

*Q = Cerdip. For oudine information see Package Information section.

NOTES
IStresses above those listed under "Absolute Maximum Ratings" may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational section of this specification is not implied.
'14-Pin Ceramic DIP: 8JA = 1l0"C/W

•

REV. A

SPECIAL FUNCTION VIDEO PRODUCTS 8-23

AD734
ac-coupled and the other is grounded, the residual offset voltage
is typically less than 5 m V, which corresponds to a bias current
of only 100 nA. This low bias current ensures that mismatches
in the sources resistances at a pair of inputs does not cause an
offset err~r. These currents remain low over the full temperature range and supply voltages.

Xl
X2

UO
Ul

The common-mode range of the X, Y and Z inputs does not
fully extend to the supply rails. Nevertheless, it is often possible
to operate the AD734 with one terminal of an input pair connected to either the positive or negative supply, unlike previous
multipliers. The common-mode resistance is several megohms.

U2

Yl

Y2

Figure 1. AD734 Block Diagram

FUNCTIONAL DESCRIPTION
Figure I is a simplified block diagram of the AD734. Operation
is similar to that of the industry-standard AD534 and in many
applications these parts are pin-compatible. The main functional
difference is the provision for direct control of the denominator
voltage, V, explained fully on the following page. Internal signals are actually in the form of currents, but the function of the
AD734 can be understood using voltages throughout, as shown
in this figure. Pins are named using upper-case characters (such
as X I, Z2) while the voltages on these pins are denoted by subscripted variables (for example, Xl' Zz).
The AD734's differential X, Y and Z inputs are handled by
wideband interfaces that have low offset, low bias current and
low distortion. The AD734 responds to the difference signals
X = Xl - Xz, Y = Y l - Y z andZ = Zl - Zz, and rejects
common-mode voltages on these inputs. The X, Y and Z interfaces provide a nominal full-scale (FS) voltage of ± 10 V, but,
due to the special design of the input stages, the linear range of
the differential input can be as large as ± 17 V. Also unlike previous designs, the response on these inputs is not clipped
abruptly above ± 15 V, but drops to a slope of one half.
The bipolar input signals X and Yare multiplied in a translinear
core of novel design to generate the product XYIV. The denominator voltage, V, is internally set to an accurate, temperaturestable value of 10 V, derived from a buried-Zener reference. An
uncalibrated fraction of the denominator voltage V appears
between the voltage reference pin (ER) and the negative supply
pin (VN), for use in certain applications where a temperaturecompensated voltage reference is desirable. The internal denominator, V, can be disabled, by connecting the denominator
disable Pin 13 (DD) to the positive supply pin (VP); the denominator can then be replaced by a fixed or variable external voltage ranging from 10 m V to more than 10 V.
The high-gain output op-amp nulls the difference between
XYIV and an additional signal Z, to generate the final output
W. The actual transfer function can take on several forms, depending on the connections used. The AD734 can perform all of
the functions supported by the AD534, and new functions using
the direct-division mode provided by the V-interface.
Each input pair (Xl and X2, Yl and Y2, Zl and Z2) has a differential input resistance of 50 kO; this is formed by "real" resistors (not a small-signal approximation) and is subject to a
tolerance of ±200/0. The common-mode input resistance is several megohms and the parasitic capacitance is about 2 pF.
The bias currents associated with these inputs are nulled by
laser-trimming, such that when one input of a pair is optionally
8-24 SPECIAL FUNCTION VIDEO PRODUCTS

The full-scale output of ± 10 V can be delivered to a load resistance of 1 kO (although the specifications apply to the standard
multiplier load condition of 2 kO). The output amplifier is
stable driving capacitive loads of at least 100 pF, when a slight
increase in bandwidth results from the peaking caused by this
capacitance. The 450 V/J.1s slew rate of the AD734's output amplifier ensures that the bandwidth of 10 MHz can be maintained
up to the full output of 20 V pk-pk. Operation at reduced supply voltages is possible, down to ±8 V, with reduced signal
levels.
Available Transfer Functions
The uncommitted (open-loop) transfer function of the AD734 is
W

=

Ao {

IXI - XZliYl - Yzi
}
U
- (Zl - Zzl ,

(I)

where Ao is the open-loop gain of the output op-amp, typically
72 dB. When a negative feedback path is provided, the circuit
will force the quantity inside the brackets essentially to zero,
resulting in the equation
(2)

This is the most useful generalized transfer function for the
AD734; it expresses a balance between the product XY and the
product VZ. The absence of the output, W, in this equation
only reflects the fact that we have not yet specified which of the
inputs is to be connected to the op-amp output.
Most of the functions of the AD734 (including division, unlike
the AD534 in this respect) are realized with Zl connected to W.
So, substituting W in place of Zl in the above equation results
in an output.
W = IXI - XZliYl - Yzi
U
+ Zz.

(3)

The free input Z2 can be used to sum another signal to the output; in the absence of a product signal, W simply follows the
voltage at Z2 with the full 10 MHz bandwidth. When not
needed for summation, Z2 should be connected to the ground
associated with the load circuit. We can show the allowable polarities in the following shorthand form:
I ± WI

=

I±XII±YI
I+UI
+ ±Z.

(4)

In the recommended direct divider mode, the Y input is set to a
fixed voltage (typically 10 V) and V is varied directly; it may
have any value from 10 mV to 10 V. The magnitude of the ratio
XIV cannot exceed 1.25; for example, the peak X-input for V
= 1 V is ± 1.25 V. Above this level, clipping occurs at the positive and negative extremities of the X-input. Alternatively, the
AD734 can be operated using the standard (AD534) divider connections (Figure 8), when the negative feedback path is established via the Y z input. Substituting W for Y z in Equation (2),

REV. A

Understanding the AD734
we get
(5)

In this case, note that the variable X is now the denominator,
and the above restriction (XIU ,;; 1.25) on the magnitude of the
X input does not apply. However, X must be positive in order
for the feedback polarity to be correct. Y I can be used for summing purposes or connected to the load ground if not needed.
The shorthand form in this case is
(± W) = (

+

(±Z)
U) (+X)

+

(6)

(± Y).

In some cases, feedback may be connected to two of the available inputs. This is true for the square-rooting connections (Figure 9), where W is connected to both XI and Y2 • Setting
X, = Wand Y2 = W in Equation (2), and anticipating the possibility of again providing a summing input, so setting X 2 = S
and Y, = S, we find, in shorthand form
( ± W) = V (

+

UI(

+

Z)

+ (±

(7)

S).

This is seen more generally to be the geometric-mean function,
since both V and Z can be variable; operation is restricted to
one quadrant. Feedback may also be taken to the V-interface.
Full details of the operation in these modes is provided in the
appropriate section of this data sheet.

Direct Denominator Control
A valuable new feature of the AD734 is the provision to replace
the internal denominator voltage, V, with any value from
+ 10 mV to + 10 V. This can be used (I) to simply alter the
multiplier scaling, thus improve accuracy and achieve reduced
noise levels when operating with small input signals; (2) to implement an accurate two-quadrant divider, with a 1000: I gain
range and an asymptotic gain-bandwidth product of 200 MHz;
(3) to achieve certain other special functions, such as AGe or
rms.

After temperature-correction (block TC), the reference voltage is
applied to transistor Qd and trimmed resistor Rd, which generate the required reference current. Transistor Qu and resistor
Ru are not involved in setting up the internal denominator, and
their associated control pins VO, VI and V2 will normally be
grounded. The reference voltage is also made available, via the
100 kfl resistor Rr, at Pin 9 (ER); the purpose of Qr is explained below.
When the control pin DD (denominator disable) is connected to
VP, the internal source ofIu is shut off, and the collector current of Qu must provide the denominator current. The resistor
Ru is laser-trimmed such that the multiplier denominator is exactly equal to the voltage across it (that is, across pins VI and
V2). Note that this trimming only sets up the correct internal
ratio; the absolute value of Ru (nominally 28 kfl) has a tolerance
of ±20%. Also, the alpha of Qu, (typically 0.995) which might
be seen as a source of scaling error, is canceled by the alpha of
other transistors in the complete circuit.
In the simplest scheme (Figure 3), an externally-provided
control voltage, VG> is applied directly to VO and V2 and the
resulting voltage across Ru is therefore reduced by one VBE' For
example, when VG = 2 V, the actual value of V will be about
1.3 V. This error will not be important in some closed-loop applications, such as automatic gain control (AGe), but clearly is
not acceptable where the denominator value must be welldefmed. When it is required to set up an accurate, fixed value
of V, the on-chip reference may be used. The transistor Qr is
provided to cancel the VBE of Qu, and is Qiased by ari external
resistor, R2, as shown in Figure 4. RI is chosen to set the desired value of V and consists of a fixed and adjustable resistor.

•

+

Figure 2 shows the internal circuitry associated with denominator control. Note first that the denominator is actually proportional to a current, Iu, having a nominal value of 356 ....A for
U = 10 V, whereas the primary reference is a voltage, generated
by a buried-Zener circuit and laser-trimmed to have a very low
temperature coefficient. This voltage is nominally 8 V with a
tolerance of ± 10%.

Figure 3. Low-Accuracy Denominator Control
lu

NOMINALLY
356fJAfor
U=10V

LINK TO

DISABLE

(
R1

l
Figure 2. Denominator Control Circuitry
Figure 4. Connections for a Fixed Denominator

REV. A

SPECIAL FUNCTION VIDEO PRODUCTS 8-25

AD734
Table I shows useful values of the external components for setting up nonstandard denominator values.

X-INPUT
~IOYFS

Denominator

Rl (Fixed)

Rl (Variable)

R2

5V
3V
2V
IV

34.8 kn
64.9 kn
86.6 kn
l74kn

20kn
20kn
50kn
100kn

120kn
220kn
300kn
620kn

100.....+--- w=(X,-X,)(Y, LOAD
GROUND
i1-~f---'-~..

Vol

+ Z,

lOY

z,
OPnONAL
SUMMING
INPUT

Y-INPUT
:t1OYFS

~IOYFS

Table I. Component Values for Setting Up Nonstandard
Denominator Values

Figure 5. Basic Multiplier Circuit

The denominator can also be cunent controlled, by grounding
Pin 3 (VO) and withdrawing a current of lu from Pin 4 (UI).
The nominal scaling relationship is V = 28 x lu, where u is
expressed in volts and lu is expressed in milliamps. Note,
however, that while the linearity of this relationship is very
good, it is subject to a scale tolerance of ±20%. Note that the
common mode range on Pins 3 through 5 actually extends from
4 V to 36 V below VP, so it is not necessary to restrict the
connection of VO to ground if it should be desirable to use some
other voltage.

with moderately good control of the high-pass (HP) corner frequency; a capacitor of 0.1 ",F provides a HP comer frequency
of 32 Hz. When a tighter control of this frequency is needed, or
when the HP comer is above about 100 kHz, an external resistor should be added across the pair of input nodes.

The output ER may also be buffered, re-scaled and used as a
general-purpose reference voltage. It is generated with respect to
the negative supply line Pin 8 (VN), but this is acceptable when
driving one of the signa1 interfaces. An example is shown in Figure 12, where a fixed numerator of 10 V is generated for a divider application. There, Y2 is tied to VN but Y I is 10 V above
this; therefore the common-mode voltage at this interface is still
5 V above VN, which satisfies the internal biasing requirements
(see Specifications Table).
OPERATION AS A MULTIPLIER
All of the _connection schemes used in this section are essentially
identical to those used for the AD534, with which the AD734 is
pin-compatible. The only precaution to be noted in this regard
is that in the AD534, Pins 3, 5, 9, and 13 are not internally connected and Pin 4 has a slightly different purpose. In many cases,
an AD734 can be directly substituted for an AD534 with immediate benefits in static accuracy, distortion, feedthrough, and
speed. Where Pin 4 was used in an AD534 application to
achieve a reduced denominator voltage, this function can now be
much more precisely implemented with the AD734 using alter-native connections (see Direct Denominator Coptrol, page 5).
Operation from supplies down to ±8 V is possible. The supply
current is essentially independent of voltage. As is true of all
high speed circuits, careful power-supply decoupling is important in maintaining stability under all conditions of use. The
decoupling capacitors should always be connected to the load
ground, since the load current circulates in these capacitors at
high frequencies. Note the use of the special symbol (a triangle
with the letter 'L' inside it) to denote the load ground.
Standard Multiplier Connections
Figure 5 shows the basic connections for multiplication. The X
and Y inputs are shown as optionally having their negative
nodes grounded, but they are fully differential, and in many
applications the grounded inputs may be reversed (to facilitate
interfacing with signals of a particular polarity, while achieving
some desired output polarity) or both may be driven.
The AD734 has an input resistance of 50 kn ± 20% at the X,
Y, and Z interfaces, which allows ac-coupling to be achieved

8-26 SPECIAL FUNCTION VIDEO PRODUCTS

At least one of the two inputs of any pair must be provided with
a de path (usually to ground). The careful selection of ground
returns is important in realizing the full accuracy of the AD734.
The Z2 pin will normally be connected to the load ground,
which may be remote, in some cases. It may also be used as
an optional summing input (see Equations (3) and (4), above)
having a nominal FS input of ±10 V-and the full 10 MHz
bandwidth.
In applications where high absolute accuracy is essential, the
scaling error caused by the finite resistance of the signal
source(s) may be troublesome; for example, a 50 n source resistance at just one input will introduce a gain error of -0.1%; if
both the X- and V-inputs are driven from 50 n sources, the
scaling error in the product will be -0.2%. Provided the source
resistance(s) are known, this gain error can be completely coinpensated by including the appropriate resistance (50 n or
100 n, respectively, in the above cases) between the output W
(Pin 12) and the Zl feedback input (Pin 11). If Rx is the total
source resistance associated with the Xl and X2 inputs, and Ry
is the total source resistance associated with the Y1 and Y2 inputs, and neither Rx nor Ry exceeds 1 kn, a resistance of
Rx+ Ry in series with pin Zl will provide the required gain
restoration.
Pins 9 (ER) and 13 (DD) should be left unconnected in this application. The V-inputs (Pins 3, 4 and 5) are shown connected
to ground; they may alternatively be connected to VN, if desired. In applications where Pin 2 (X2) happens to be driven
with a high-amplitude, high-frequency signal, the capacitive
coupling to the denominator control circuitry via an ungrounded
Pin 3 can cause high-frequency distortion. However, the AD734
can be operated without modification in an AD534 socket, and
these three pins left unconnected, with the above caution noted.

X-INPUT
~IOYFS

Y-INPUT

:t1OYFS

~10mA1WC

FS

~IOY

MAXIMUM
LOAD VOLTAGE

Figure 6. Conversion of Output to

a Current

REV. A

AD734
Current Output
It may occasionally be desirable to convert the output voltage to
a current. In correlation applications, for example, multiplication is followed by integration; if the output is in the form of a
current, a simple grounded capacitor can perform this function.
Figure 6 shows how this can be achieved. The op-amp forces
the voltage across Zl and Z2, and thus across the resistor R s , to
be the product XY/u. Note that the input resistance of the
Z interface is in shunt with Rs , which must be calculated
accordingly.
The smallest FS current is simply ±10 V/50 kG, or ±200!IA,
with a tolerance of about 20%. To guarantee a 1% conversion
tolerance without adjustment, Rs must be less than 2.5 kG. The
maximum full scale output current should be limited to about
± 10 rnA (thus, Rs = 1 kG). This concept can be applied to all
connection modes, with the appropriate choice of terminals.
Squaring and Frequency-Doubling
Squaring of an input signal, E, is achieved simply by connecting
the X and Y inputs in parallel; the phasing can be chosen to
produce an output of E2/U or - E2/U as desired. The input may
have either polarity, but the basic output will either always be
positive or negative; as for multiplication, the Z2 input may be
used to add a further signal to the output.
When the input is a sinewave, a squarer behaves as a frequency
doubler, since

(Esinwt)2 = E2 (l - cos2wt)/2

(8)

Equation (8) shows a dc term at the output which will vary
strongly with the amplitude of the input, E. This de term can
be avoided using the connection shown in Figure 7, where an
RC-network is used to generate two signals whose product has
no dc term. The output is

W=

4{~sin(wt+ ~)}{~sin(WI- ~)}(I~V)<9)

for

= lICRl, which is just

W

W

=

E 2(cos2wl)/(lO V)

r

R3
13k

Esinl.It

l

R4
4.32k
C

1

E:i!cos2rotl1DV

J

Figure 7. Frequency Doubler

OPERATION AS A DMDER
The AD734 supports two methods for performing analog division. The first is based on the use of a multiplier in a feedback
loop. This is the standard mode recommended for multipliers
having a fixed scaling voltage, such as the AD534, and will be
described in this Section. The second uses the AD734's unique
capability for externally varying the scaling (denominator) voltage directly, and will be described in the next section.
Feedback Divider Connections
Figure 8 shows the connections for the standard (AD534) divider mode. Feedback from the output, W, is now taken to the
Y2 (inverting) input, which, provided that the X-input is positive, establishes a negative feedback path. Yl should normally
be connected to the ground associated with the load circuit, but
tnay optionally be used to sum a further signal to the output. If
desired, the polarity of the V-input connections can be reversed,
with W connected to Yl and Y2 used as the optional summation
input. In this case, either the polarity of the X-input connections must be reversed, or the X-input voltage must be negative.

X INPUT
+O.1V TO +10V _ _--""

(10)

which has no dc component. To restore the output to ± 10 V
when E = 10 V, a feedback attenuator with an approximate ratio of 4 is used between W and Zl; this technique can be used
wherever it is desired to achieve a higher overall gain in the
transfer function.

y,
OPTIONAL
SUMMING
.INPUT
±10V FS

In fact, the values of R3 and R4 include additional compensation for the effects of the 50 kG input resistance of all three interfaces; R2 is included for a similar reason. These resistor
values should not be altered without careful calculation of the
consequences; with the values shown, the center frequency fo is
100 kHz for C = 1 nF. The amplitude of the output is only a
weak function of frequency: the output amplitude will be 0.5%
too low at f = 0.9fo and f = l.lfo. The cross-connection is simply to produce the cosine output with the sign shown in Equation (10); however, the sign in this case will rarely be important.

REV. A

Figure 8. Standard (AD534) Divider Connection

The numerator input, which is differential and ('an have either
polarity, is applied to pins Zl and Z2. As wim all dividers based
on feedback, the bandwidth is directly proportional to the denominator, being 10 MHz for X = 10 V and reducing to
100 kHz for X = 100 mV. This reduction in bandwidth, and
the increase in output noise (which is inversely proportional to
the denominator voltage) preclude operation much below a denominator of 100 mV. Division using direct control of the denominator (Figure 10) does not have these shortcomings.

SPECIAL FUNCTION VIDEO PRODUCTS 8-27

II

AD734
This connection scheme may also be viewed as a variable-gain
element, whose output, in response to a signal at the X input, is
controllable by both the Y input (for attenuation, using Y less
than V) and the V input (for amplification, using V less than
V). The ac performance is shown in Figure II; for these results,
Y was maintained at a constant 10 V. At V = 10 V, the gain is
unity and the circuit bandwidth is a full 10 MHz. At V = IV,
the gainis 20 dB and the bandwidth is essentially unaltered. At
V = 100 mY, the gain is 40 dB and the bandwidth is 2 MHz.
Finally, at V = 10 mY, the gain is 60 dB and the bandwidth is
250 kHz, corresponding to a 250 MHz gain-bandwidth product.

S
OPTIONAL
SUMMING
INPUT

:!:10V FS

Figure 9. Connection for Square Rooting

Connections for Square-Rooting
The AD734 may be used to generate an output proportional to
the square-root of an input using the connections shown in
Figure 9. Feedback is now via both the x and Y inputs, and is
always negative because of the reversed-polarity between these
two inputs. The Z input must have the polarity shown, but
because it is applied to a differential port, either polarity of
input can be accepted with reversal of ZI and Z2, if necessary.
The diode D, which can be any small-signal type (IN4148 being
suitable) is included to prevent a latching condition which could
occur if the input momentarily was of the incorrect polarity of
the input, the output will be always negative.
Note that the loading on the output side of the diode will be
provided by the 25 kO of input resistance at XI and Y2, and by
the user's load. In high speed applications it may be beneficial
to include further loading at the output (to I kD. minimum) to
speed up response time. As in previous applications, a further
signal, shown here as S, may be summed to the output; if this
option is not used, this node should be connected to the load
ground.
DIVISION BY DIRECT DENOMINATOR CONTROL
The AD734 may be used as an analog divider by directly varying the denominator voltage. In addition to providing much
higher accuracy and bandwidth, this mode also provides greater
flexibility, because all inputs remain available. Figure 10 shows
the connections for the general case of a three-input multiplier
divider, providing the function
IX I

W =

X 2HY I - Y21
IV1 - V 21
+ Z2,

-

(11)

where the X, Y, and Z signals may all be positive or negative,
but the difference V = VI - V 2 must be positive and in the
range + 10 mV to + 10 V. If a negative denominator voltage
must be used, simply ground the noninverting input of the op
amp. As previously noted, the X input must have a magnitude
of less than 1.25V.

70

u=~omv

50

..
50

'll

I

uJ_v

-

-r-..

~ 20 uJv

1.

"

--'~t-..

I

'30

r-

I
u=\.v

r--

I
10k

100.
1M
FREQUENCY - Hz

10M

Figure ". Three-Variable Multiplier/Divider Performance

The 2 MD. resistor is included to improve the accuracy of the
gain for small denominator voltages. At high gains, the X input
offset voltage can cause a significant output offset voltage. To
eliminate this problem, a low-pass feedback path can be used
from W to X2; see Figure 13 for details.
Where a numerator of 10 V is needed, to implement a twoquadrant divider with fixed scaling, the connections shown in
Figure 12 may be used. The reference voltage output appearing
between Pin 9 (ER) and Pin 8 (VN) is amplified and buffered
by the second op amp, to impose 10 V across the YlIY2 input.
Note that Y2 is connected to the negative supply in this application. This is permissable because the common-mode voltage is
still high enough to meet the internal requirements. The transfer
function is
W =

X2)

XI IOV ( VI _ V2.

(12)

+ Z2.

The ac performance of this circuit remains as shown in
Figure 11.

AD734

x- INPUT

w = (X , -

ru

H~+--"":':""

- : - -......

X2 hov + Z2
U,-U 2

LOAD

(U,

GROUND
t-o---+--'--~

U-INPUT

l U, ---=--o{~

nID+--1~--o--Z,
OPTIONAL

ru

V -INPUT - - -......

W ~':.~~G

z,

W ~~~~~~L
INPUT
:t10Y FS

:!:10V FS

Figure 10. Three-Variable Multiplier/Divider Using Direct
Denominator Control
8-28 SPECIAL FUNCTION VIDEO PRODUCTS

Figure 12. Two-Quadrant Divider with Fixed 10 V Scaling

REV. A

AD734
A PRECISION AGC LOOP
The variable denominator of the AD734 and its high gainbandwidth product make it an excellent choice for precise automatic gain control (AGC) applications. Figure 13 shows a
suggested method. The input signal, E IN , which may have a
peak amplitude of from 10 mV to 10 V at any frequency from
100 Hz to 10 MHz, is applied to the X input, and a fIxed positive voltage Ec to the Y input. Op amp A2 and capacitor C2
form an integrator having a current summing node at its inverting input. (The AD712 dual op amp is a suitable is a suitable
choice for this application.) In the absence of an input, the current in D2 and R2 causes the integrator output to ramp negative, clamped by diode D3, which is included to reduce the time
required for the loop to establish a stable, calibrated, output
level once the circuit has received an input signal. With no input to the denominator (VO and V2), the gain of the AD734 is
very high (about 70 dB), and thus even a small input causes a
substantial output.

The output amplitude tracks Ec over the range + I V to slightly
more than + 10 V.

+1

~,l

I -t---

m
I

~

1'-

V-- t;~ t3::::

'"

0

I/

a:

w

1

100Hi

~

II

IT
I

-2
l00mY
IV
INPUT AMPUTUDE - Yol18

10mV

lOY

Figure 14. AGC Amplifier Output Error vs. Input Voltage

1

E"

EOUT

10I--+-------++-J

WIDEBAND RMS-DC CONVERTER
USING U INTERFACE
The AD734 is well suited to such applications as implicit RMSDC conversion, where the AD734 implements the function

1

avg
VRMS

=

[V/N2l

(13)

VRMS

using its direct divide mode. Figure IS shows the circuit.

+10V

R2
1Mn

Rl
1MU

OP AMP

= AD712 DUAL

Figure 13. Precision AGC Loop

Diode D I and C I form a peak detector, which rectifIes the output and causes the integrator to ramp positive. When the cur·rent in RI balances the current in R2, the integrator output
holds the denominator output at a constant value. This occurs
when there is suffIcient gain to raise the amplitude of EIN to
that required to establish an output amplitude of Ec over the
range of + I V to + 10 V. The X input of the AD734, which has
fInite offset voltage, could be troublesome at the output at high
gains. The output offset is reduced to that of the X input (one
or two millivolts) by the offset loop comprising R3, C3, and
buffer AI. The low pass corner frequency of 0.16 Hz is transformed to a high-pass corner that is multiplied by the gain (for
example, 160 Hz at a gain of 1000).

V,N <>-1r------{j]

II
Figure 15. A 2-Chip, Wideband RMS-OC Converter

In applications not requiring operation down to low frequencies,
amplifIer Al can be eliminated, but the AD734's input resistance of 50 kO between XI and X2 will reduce the time constant and increase the input offset. Using a non-polar 20 ILF
tantalum capacitor for CI will result in the same unity-gain
high-pass corner; in this case, the offset gain increases to 20,
still very acceptable.

In this application, the AD734 and an AD708 dual op amp
serve as a 2-chip RMS-DC converter with a 10 MHz bandwidth.
Figure 16 shows the circuit's performance for square-, sine-, and
triangle-wave inputs. The circuit accepts signals as high as 10 V
p-p with a crest factor of I or I V p-p with a crest factor of 10.
The circuit's response is flat to 10 MHz with an input of 10 V,
flat to almost 5 MHz for an input of IV, and to almost I MHz
for inputs of 100 mY. For accurate measurements of input levels
below 100 m V, the AD734's output offset (Z interface) voltage,
which contributes a dc error, must be trimmed out.

Figure 14 shows the error in the output for sinusoidal inputs at
100 Hz, 100 kHz, and I MHz, with Ec set to + 10 V. The output error for any frequency between 300 Hz and 300 kHz is
similar to that for 100 kHz. At low signal frequencies and low
input amplitudes, the dynamics of the control loop determine
the gain error and distortion; at high frequencies, the 200 MHz
gain-bandwidth product of the AD734 limit the available gain.

In Figure IS's circuit, the AD734 squares the input signal, and
its output (VIN 2) is averaged by a low-pass fIlter that consists of
RI and CI and has a corner frequency of I Hz. Because of the
implicit feedback loop, this value is both the output value,
VRMS ' and the denominator in Equation (13). V2a and V2b, an
AD708 d'lRl dc precision op amp, serve as unity-gain buffers,
supplying both the output voltage and driving the V interface.

REV. A

SPECIAL FUNCTION VIDEO PRODUCTS 8-29

AD 734
100

=

10

~
6

100m

!;

10m

>

O~

SQUAREI~AV~ ••1.
!-SINEWAVE -,F=TRI-WAVE- - - -

-

- - ,- - . ...
.-. -... ~;
\

10k

.

,

,
\1

1m
100~

If the two XI inputs are at frequencies f1 and f2 and the frequency at the YI input is fo, then the two-tone third-order intermodulation products should appear at frequencies 2f1 - f2 ±
fo and 2f2 - f1 ± fo. Figures ,18 and 19 show the output spectra
of the AD.734 with f1 = 9.95 MHz, f2 = 10.05 MHz, and
fo = 9.00 MHz for a signa1level of f1 & f2 of 6 dBm and
fo of +24 dBm in Figure 18 and f1 & f2 of 0 dBm and
fo of + 24 dBlll in Figure 19. This performance is without external trimming of the AD734's X and Y input-offset voltages.

100k

1M

10M

INPUT FREQUENCY - Hz

Figure 16. RMS-DC Converter Performance

LOW DISTORTION MIXER
The AD734's low noise and distonion make it especially suitable
for use as a mixer, modulator, or demodulator. Although the
AD734's - 3 dB bandwidth is typically 10 MHz and is established by the output amplifier, the bandwidth of its X and Y
interfaces and the multiplier core are typically in excess of
40 MHz. Thus, provided that the desired output signal is less
than 10 MHz, as would typically be the case in demodulation,
the AD734 can be used with both its X and Y input signals as
high as 40 MHz. One test of mixer performance is to linearly
combine two closely spaced, equal-amplitude sinusoidal signals
and then mix them with a third signal to determine the mixer's
2-tone Third-Order Intermodulation Products.

The possible Two Tone Intermodulation Products are at 2 x
9.95 MHz - 10.05 MHz ± 9.00 MHz and 2 x 10.05 9.95 MHz ±9.00 MHz; of these only the third-order products at
0.850 MHz and 1.150 MHz are within the 10 MHz bandwidth
of the AD734; the desired output signals are at 0.950 MHz and
1.050 MHz. Note that the difference (Figure 18) between the
desired outputs and third-order products is approximately
78 dB, which corresponds to a computed third-order intercept
point of +46 dBm.

Figure 18. AD734 Third-Order Intermodulation Performance
for f, = 9.95 MHz, f2 = 10.05 MHz, and fo = 9.00 MHz and
for Signal Levels of f, & f2 of 6 dBm and fo of +24 dBm.
All Displayed Signal Levels Are Attenuated 20 dB by the
lOX Probe Used to Measure the Mixer's Output
Figure 17. AD734 Mixer Test Circuit
Figure 17 shows a test circuit for measuring the AD734's performance in this regard. In this test, two signals, at 10.05 MHz
and 9.95 MHz are summed and applied to the AD734's X interface. A second 9 MHz signal is applied to the AD734's Y interface. The voltage at the U interface is set to 2 V to use the full
dynamic range of the AD734. That is, by connecting the Wand
ZI pins together, grounding the Y2 and X2 pins, and setting
U = 2 V, the overall transfer function is
(14)
and W can be as high as 20 V p-p when Xl = 2 V p-p and
YI = 10 V p-p. The 2 V p-p signal level corresponds to
+ 10 dBm into a 50 n input termination resistor connected from
Xl or YI to ground.

Figure 19. AD734 Third-Order Intermodulation Performance
for f, = 9.95 MHz, f2 = 10.05 MHz, and fo = 9.00 MHz and
for Signal Levels of f, & f2 of a dBm aod fo of +24 dBm.
All Displayed Signal Levels Are Attenuated 20 dB by the
lOX Probe Used to Measure the Mixer's Output
8-30 SPECIAL FUNCTION VIDEO PRODUCTS

REV. A

Typical Characteristics - AD734

....
I

J•••(sv I

....

i

I

o.1

0."

i1-0JI2
1-0.04

....

is

VS=±15Y

0.31--f-+-++-f-X=1.4YRMS Y=lOY
0.21--f-+-++-f-RLOAD =5OCKlm 0.1
CLQAO =zapF

RLOAD=2kn
CI.OAI)=2OpF

I
IIt-....

om

-

.. I

v~.±;

I

RLOAD =2110:
CI.OAD=2OpF

~ o~~~~~~~~~t-~
-...~

I

l- / '

"""

~

rI-

-0.1

-0."

-2Y

2V

-2Y

2Y

SIGNAL AMPLITUDE

--+-+++--+-+-1<-[\+-1

-0.1 -

-0.21---t-+-+-t-1----t---t---t-1t-f
-0.31--f-+-++-I--+--+++j
-0.4 ---+-+-H--+--+--+-fH
1M
FREQUENCY - Hz

100k

SIGNAL AMPLITUDE

Figure 21. Differential Phase at
= 2 kfl

Figure 20. Differential Gain at
= 2 kfl

3.58 MHz and Ri..

3.58 MHz and RL

100

Figure 22. Gain Flatness, 300 kHz to
10 MHz, RL = 500 fl

100

---

COUMON-MODE

"GiLI=II·~ I

80

I

80

IN~UT~~~~L J ~~
7Y

.lJ

,(INPUT, X = lOY

YN

I"NJ

f'
t-...
20

20

o
1k

10k

100k
FFiEQUENCV - Hz

10M

1M

Figure 23. CMRR vs. Frequency

I
.isr~,!J,! =11v.l.J
I

jii'
I II
r
I III

-40

I

1k

I I

I II

-4D

~~II

10k

100k
FREQUENCY - Hz

I I

OTHER

r--

RLOAD= ;?2kil

10k

100k
FREQUENCY - Hz

-40

=

X INPUT

::;-

k:

~PUT

r---- ~.EL~lv =

1Mi

VP=15V

=2kn

I I
J.xI.PIIT·lv"~E::
.t.

-80

~I

YljPIIT. xi 'j i

-80

I

./
1M

10M

I
1k

10k

lOOk
FREQUENCY - Hz

10M

f - - f--VN=-15V
RLOAD

INPUT lOY DC

1M

Figure 25. Feedthrough vs. Frequency

f----

-80

Figure 26. THD vs. Frequency,
U=2V

REV. A

1k

INPUT .. 7Y RMS

i-'"
1k

o

10M

-20

-60

~

1M

I

r-

~

17

-100

I

YINPUT

-60

I.......

100k
FREQUENCY - Hz

I II

r--

2Y DC

XINPUT

-60

10k

x INPUT, Y NULLED

Figure 24. PSRR vs. Frequency

-20

Uz2V

OTHEr

o

0

I II

-20

I

...... VP

x INPUT, Y = 1~"

40

m

1'111
vi I• ~1.u~LE~
II'

-40

'-l'W

60

10M

1M

Figure 27. THO vs. Frequency,
U = 10V

10M

-10d8m
7O.7mV RMS

1Od8m

707mYRIIS
SIGNAL LEVEL

I

I

3Od8m
7VRIIS

Figure 28. THO vs. Signal Level,
f = 1 MHz

SPECIAL FUNCTION VIDEO PRODUCTS 8-31

•

AD734-Typical Characteristics
V.;"5V

1

1 1 11

X",1AVRMS
Y=10V
RLOAD =5000
CLOAD. 2OpF. 47pF, l00pF

!

-

Lo

1

Q

A.

~\

-3

100'

-90
Ys =±15Y

-150

t--- x = 1.4V RMS

-180

r---- CLOAD = soou
2OpF, 47pF, lOOpF
RLOAO '"

II

\\\

1M

l\\v

Y=10V

~\\

-4

........

-60

~ -120

1'\

-2

r---.

-30

I

~]\

c

-.

i
i

INCREASING
C....D

1

10M

lOOk

FREQUENCY - Hz

INCREAS1,
C LOAD

111
FREQUENCY - HiE

lDM

Figure 30. Phase vs. Frequency
CLOAD

Figure 29. Gain vs. Frequency vs.
CLOAD

20

l- I--

-10

I-- I--

I--

r-

-15

-20

""'IIii ~

-

1\ I\..

...- ...-

15

8

I

10

~

\ \

\

u=w\

~=2V

Xt FREQUENCY = Y,
FREQUENCY -1MHz

(e.g., Y, - X,

=1MHz

FOR ALL CURVES)

17

-30'0

18

30

U=10V

\

\

\

1\

\

'\

40
50
60
70
Y, FREQUENCY - MHz

80

90

100

Figure 33. Output Amplitude vs.
Input Frequency, When Used as
Demodulator

Figure 32. Output Swing vs. Supply
Voltage

40

20

\

'\=5Y

\ 1\

-- --

11 12 13 14 15
SUPPLY YO.LTAGE - ±Vs

Figure 31. Pulse Response VS.
CWAD< CLOAD = 0 pF, 47 pF,
100 pF, 200 pF

VS.

INPUT OFFSET VOLTAGE
DRIfT WILL TYPICALLY BE
WITHIN SHADED AREA

201..::+-+-t-+-+-t-+-+-+---I

-101"'--+-+-f---+-+-f---+-+-""1--I

-60I-+-+-t-+-+-+-+-+-+---I
_.L-~~~

105 125

TEMPEFIATURE _·c

Figure 34. Vos Drift, X Input

TEMPERATURE _ DC

Figure 35. Vos Drift, Z Input

8-32 SPECIAL FUNCTION VIDEO PRODUCTS

-55 -35 -15

__

~-L~

__L-~-L~

5
25 45 65 85
TEMPERATURE _ "'C

105 125

Figure 36. Vos Drift, Y Input

REV. A

-.ANALOG
WDEVICES
FEATURES
DC to >500MHz Operation
Differential :l:1V Full Scale Inputs
Differential :l:4mA Full Scale Output Current
Low Distortion (:50.05% for OdBm Input)
Supply Voltages from :l:4V to :l:9V
Low Power (280mW typical at Vs =:l:5V)
APPLICATIONS
High Speed Real Time Computation
Wideband Modulation and Gain Control
Signal Correlation and RF Power Measurement
Voltage Controlled Filters and Oscillators
Linear Keyers for High Resolution Television
Wideband True RMS

PRODUCT DESCRIPTION
The AD834 is a monolithic laser-trimmed four-quadrant analog
multiplier intended for use in high frequency applications,
having a transconductance bandwidth (RL =500) in excess of
SOOMHz from either of the differential voltage inputs. In multiplier modes, the typical total full scale error is 0.5%, dependent
on the application mode and the external circuitry. Performance
is relatively insensitive to temperature and supply variations,
due to the use of stable biasing based on a bandgap reference
generator and other design features.
To preserve the full bandwidth potential of the high speed
bipolar process used to fabricate the AD834, the outputs appear
as a differential pair of currents at open collectors. To provide a
single ended ground referenced voltage output, some form of
external current to voltage conversion is needed. This may take
the form of a wideband transformer, balun, or active circuitry
such as an op amp. In some applications (such as power measurement) the subsequent signal processing may not need to
have high bandwidth.
The transfer function is accurately trimmed such that when
X=Y=:l:lV, the differential output is ±4mA. This absolute
calibration allows the outputs of two or more AD834s to be
summed with precisely equal weighting, independent of the
accuracy of the load circuit.

500MHz Four-Quadrant Multiplier
AD834 I
FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS
I. The AD834 combines high static accuracy (low input and
output offsets and accurate scale factor) with very high bandwidth. As a four-quadrant multiplier or squarer, the response
extends from dc to an upper frequency limited mainly by
packaging and external board layout considerations. A large
signal bandwidth of over SOOMHz is attainable under optimum conditions.
2. The AD834 can be used in many high speed nonlinear operations, such as square rooting, analog division, vector addition
and rms-to-dc conversion. In these modes, the bandwidth is
limited by the external active components.
3. Special design techniques result in low distortion levels (better than -60dB on either input) at high frequencies and low
signal feedthrough (typically -6SdB up to 20MHz).
4. The AD834 exhibits low differential phase error over the input range-typically 0.08· at SMHz and 0.8· at SOMHz. The
large signal transient response is free from overshoot, and has
an intrinsic rise time of SOOps, typically settling to within 1%
in under Sns.
S. The nonloading, high impedance, differential inputs simplify
the application of the AD834.

The AD834J is specified for use over the commercial temperature range of 0 to + 70·C and is available in an 8-pin plastic DIP
package and an 8-pin plastic SOIC package. AD834A is available in cerdip for operation over the industrial temperature
range of -40·C to +8S·C. The AD834S/883B is specified for
operation over the military temperature range of -SS·C to
+ l2S·C and is available in the 8-pin cerdip package. S-Grade
chips are also available.

REV. A

SPECIAL FUNCTION VIDEO PRODUCTS 8-33

II'

AD834-SPECIFICATIONS (lA=+25°C and ±Vs=±5V. qnless otherwise noted; dBmllssumes 500 load.)
AD834A,S

AD834J
Model

Conditions

Min

Typ

Max

Min

Max

Units

±0.5
±1.5
0.1
±0.5

±2
±3
0.3
±1

%FS
%FS

0.2
0.1

0.3
0.2

Typ

MULTIPLIER PERFORMANCE
XY
W = (IVY x 4mA

Transfer Function
Total Error' (Figure 6)
VB. Temperature
vs. Supplier
Linearity'
Bandwidth4
Feedthrough, X
Feedthrough, Y
AC Feedthrough, X,
AC Feedthrough, ys

INPUTS (XI, X2, YI, Y2)
Full Scale Range
Clipping Level
Input Resistance
Offset Voltage
VB. Temperature
VB. Supplies2
Bias Current
Common Mode Rejection
Noulinearity, X
Nonlinearity, Y
Distortion, X

Distortion, Y

OUTPUTS (WI, W2)
Zero Signal Current
Differential Offset
vs. Temperature
Sca1ing Current
Output Compliance
Noise Spectral Density
POWER SUPPLIES
Operating Rauge
Quiescent Current"
+Vs
-Vs

-IVsX,Y<+IV
T_ toT....
±4Vto ±6V
See Figure 5
X=±IV, Y=Nulled
X=NulIed, Y=±IV
X=OdBm, Y=Nulled
f=lOMHz
f=IOOMHz
X=NulIed, Y=OdBm
f=IOMHz
f:;IOOMHz
Differential
Differential
Differential

±0.5

±2

0.1
±0.5

0.3
±1

0.2
0.1

0.3
0.2

500

±1.1

500

±4Vto ±6V

Each Output
X=O, Y=O
T_ to T ....

dB
dB

-70
-50

-70
-50

dB
dB

±I
±1.3
25
0.5
10

3

V
V
ill
mV

4
300

mV
",VN

0.5
0.3

dB
%FS
%FS

±I
±1.3
25
0.5

±1.1
3
4
300

100
45
70
0.2
0.1

0.5
0.3

tJ.A

-60
-44

dB
dB

-65
.-50

-65
-50

dB
dB

8.5
±20

±60

40

f=IOHz to IMHz
Outputs into 50n Load

",vrc

-60
-44

8.5
±20

3.96
4.75

%FS
MHz
%FS
%FS

-65
-50

100
45
70
0.2
0.1

fSIOOkHz; IV p-p
Y=IV;X=±IV
X=IV; Y=±IV
X=OdBm, Y=IV
f=IOMHz
f==IOOMHz
X=IV, Y=OdBM
f=IOMHz
f=IOOMHz

%FSN

-65
-50

10

T_ to Tmax

Differential

XY
W= (IVY x 4mA

4

40
4.04
9

3.96
4.75

16

4

±4

tJ.A

nArc
±60
4.04
9

16

±9

±4

mA
±60

tJ.A
mA
V
nVl'\l'lh

±9

V

14
35

mA
mA

T_ to Tmax

TEMPERATURE RANGE
Operating, Rated Performance
Commercia1 (0 to + 70'C)
Military ( - 55'C to + 125'C)
Industrial (-4O'C to +85'C)
PACKAGE OPTIONS7
8-Pin SOIC (R)
8-Pin Cerdip (Q)
8-Pin Plastic DIP (N)

11
28

14
35

11
28

AD834J
AD834S
AD834A
AD834JR
AD834JN

AD834AQ
AD834SQl883B

NOTES
'Error is defined as the maximum deviation from the ideal output, and expressed as a percentage of the full scale output.
2Both supplies taken simultaneOusly; sinusoidal input at f,,;; 10kHz.
'Linearity is defmed as residual error after compensating for input offset voltage, outpUt offset current and scaling current errors.
4Bandwidth is guaranteed when configured in squarer mode. See Figure 5.
'Sine input; relative to full scale output; zero input port nulled; represents feedthrough of the fundamental.
"Negative supply current is equal to the sum of positive supply current, the signal currents into each output, WI and W2, and the input bias currents.
7Por outline information see Package Information section.
Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgOiJ;>g quality levels.
Specifications subject to change without notice.

8-34 SPECIAL FUNCTION VIDEO PRODUCTS

REV. A

AD834
ABSOLUTE MAXIMUM RATINGS!
Supply Voltage (+Vs to -V s) . . . . . . . . . . . . . . . . . . . . 18V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 500mW
Input Voltages (Xl, X2, YI, Y2) . . . . . . . . . . . . . . . . . . +Vs
Operating Temperature Range
AD834J . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to + 70°C
AD834A . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
AD834S/883B . . . . . . . . . . . . . . . . . . . . - 55°C to + 125°C
Storage Temperature Range Q . . . . . . . . . . . -65°C to + 150°C
Storage Temperature Range R, N . . . . . . . . . -65°C to + 125°C
Lead Temperature, Soldering 60sec . . . . . . . . . . . . . . + 300°C
NOTE
'Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.

CONNECTION DIAGRAM
Small Outline (R) Package
Plastic DIP (N) Package
Cerdip (Q) Package
Y1

Y2

-Vs

•

AD834
TOP VIEW
(Notto Scalel

+Vs
W1

METALIZATION PHOTO
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).

THERMAL CHARACTERISTICS
8-Pin Cerdip Package (Q)
8-Pin Plastic SOIC (R)
8-Pin Plastic Mini-DIP (N)

30°CIW
45°CIW
50°CIW

110°CIW
165°CIW
99°CIW

ORDERING GUIDE
Model
AD834JN
AD834JQ
AD834JR
AD834AQ
AD834SQ/883B
AD834S Chips
*N

Temperature
Range

Package
Option*

o to +70°C
oto +70°C
o to +70°C

N-8
Q-8
R-8
Q-8
Q-8
Chips

-40OC to +85°C
- 55°C to + 125°C

•

= Plastic DIP; Q = Cerdip; R = Small Outline IC (SOlC) Package.

REV. A

SPECIAL FUNCTION VIDEO PRODUCTS 8-35

AD834-Typical Characteristics
1000

800
600

-10

400

!>~

~

200

~

....

-20

~ -'0

I -30

:r

"5-40

i:
i

1-20

z

o

!ll

100

!~

-------14"~-

(Xl- X2)(Yl- Y2)

W

(Ul-U2)

+Z

with a denominator range of about 100: 1. The denominator
input U = Ul-U2 must be positive and in the range lOOmV to
lOY; X, Y and Z inputs may have either polarity. Figure 16
shows a general configuration which may be simplified to suit a
particular application. This circuit accepts full scale input voltages of lOY, and delivers a full scale output voltage of lOY. The
optional offset trim at the output of the AD834 improves the
accuracy for small denominator values. It is adjusted by nulling
the output voltage when the X and Y inputs are zero and
U=+IOOmV.
The AD840 is internally compensated to be stable without the
use of any additional HF compensation. As the input U is
reduced, the bandwidth falls because the feedback around the
op amp is proportional to the input U.
This circuit may be modified in several ways. For example, if
the differential input feature is not needed, the unused input

8-40 SPECIAL FUNCTION VIDEO PRODUCTS

Figure 16. Wideband Three Signal Multiplier/Divider
can be connected to ground through a single resistor, equal to
the parallel sum of the resistors in the attenuator section. The
full scale input levels on X, Y and U can be adapted to any full
scale voltage down to ± 1V by altering the attenuator ratios.
Note,.however, that precautions must be taken if the attenuator
ratio from the output of A3 back to the second AD834 (A2) is
lowered. First, the HF compensation limit of the AD840 may
be exceeded if the negative feedback factor is too high. Second,
if the attenuated output at the AD834 exceeds its clipping level
of ± 1.3V, feedback control will be lost and the' output will suddenly jump to the supply rails. However, with these limitations
understood, it will be possible to adapt the circuit to smaller full
scale inputs and/or outputs, and for use with lower supply
voltages.

REV. A

4 x 1Wideband
Video Multiplexer

ANALOG
WDEVICES

11IIIIIIII

AD9300

I

FUNCTIONAL BLOCK DIAGRAM
(Based on Cerdip)

FEATURES
34MHz Full Power Bandwidth
±0.1dB Gain Flatness to 8MHz
72dB Crosstalk Rejection @ 10MHz
0.03°/0.01% Differential PhaselGain
Cascadable for Switch Matrices
MIL-STD-883 Compliant Versions Available
APP!-ICATIONS
Video Routing
Medical Imaging
Electro-Optics
ECM Systems
Radar Systems
Data Acquisition

GENERAL DESCRIPTION
The AD9300 is a monolithic high-speed video signal multiplexer
useable in a wide variety of applications.

BVPASS

~ 0.1._

Its four channels of video input signals can be randomly switched
at megahertz rates to the single output. In addition, multiple
devices can be configured in either parallel or cascade arrangements
to form switch matrices. This flexibility in using the AD9300 is
possible because the output of the device is in a high-impedance
state when the chip is not enabled; when the chip is enabled,
the unit acts as a buffer with a high input impedance and low
output impedance.

The AD9300K is available in a l6-pin ceramic DIP and a 20-pin
PLeC and is designed to operate over the commercial temperature
range of 0 to + 70°C. The AD9300TQ is a hermetic 16-pin
ceramic DIP for military temperature range ( - SSOC to + 12S°C)
applications. This part is also available processed to MIL-STD883. The AD9300 is available in Ii 20-pin LCC as the model
AD9300TE, which operates over a temperature range of - 55°C
to + l2S'C.

An advanced bipolar process provides fast, wideband switching
capabilities while maintaining crosstalk rejection of 72dB at
IOMHz. Full power bandwidth is a minimum 27MHz. The
device can be operated from ± IOV to ± ISV power supplies.

The AD9300 Video Multiplexer is available in versions compliant
with MIL-STD-883. Refer to the Analog Devices Mililary Products
Da/abook or current AD9300/883B data sheet for detailed
specifications.

PIN DESIGNATIONS
LeC and PLee

DIP

•

~

OUTPUT

3
BYPASS

+v.
AD9300
TOP VIEW
INot to Scale)

GROUND RETURN

ENABLE
A.
A,

z z
.. . .
c

c

::>
0

::>

t-

C

""
I

2

'

en

::> en
t- <
o.
::> >
0
20 19

.,

'"

tJ

GROUND 4

IN2 5

18

AD9300

GROUND 6

16 GROUND

TOP VIEW
INot to Scale)

GROUND 7

+Vs

17 GROUND RETURN

15 ENABLE

14 Ao

1N38

9

10 11

~ "i ~

i

"

~

12

f

13

250V/j.Ls.
9Measured at output between O.28Vdc and I.OVdc with VIN ~ 284mV p-p at 3.S8MHz and 4.43MHz.
IOThis specification is critically dependent on circuit layout. Value shown is measured with selected channel grounded and lOMHz 2V p-p signal
applied to remaining three channels. If selected channel is grounded through 7S!1, value is approximately 6dB higher.
"This specification is critically dependent on circuit layom. Value shown is measured with selected channel grounded and IOMHz 2V p-p signal
applied to one other channel. If selected channel is grounded through 7Sfl, value is approximately 6dB higher. Minimum specification in ( ) applies to DIPs.
12Consult system timing diagram.
13Measured from address change to 90% point of - 2V to + 2V output LOW~to-HIGH transition.
14Measured from address change to 90% point of + 2V to - 2V output HIGH~to-LOW transition.
ISMeasured from SO% transition point of ENABLE input to 90% transition of OV to - 2V and OV to + 2V output.
16Measured from SO% transition point of ENABLE inpm to 10% transition of + 2V to OV and - 2V to OV output.
17Measured while switching between two grounded channels.
18Maximum power dissipation is a package~dependent parameter related to the following typical thermal impedances:
16·Pin Ceramic alA ~ 87"CIW; a lC ~ 2S o CIW
20·Pin LCC
alA ~ 74°CIW; a lC ~ IO°CIW
20·Pin PLCC
alA ~ 71°CIW; aJC ~ 26°CIW
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS 1
Supply Voltages (±Vs) . . . . .
Analog Input Voltage Each Input
(IN 1 thru IN,) . . . . . . . .
Differential Voltage Between Any Two
Inputs (IN 1 thru IN,) . . . . . . .
Digital Input Voltages (Ao, AI> ENABLE)

±16V
±3.sV
. . . . . . . . SV
-O.5V to +s.sV

Output Current
Sinking . . .
Sourcing
...... .
Operating Temperature Range
AD9300KQ/KP . . . . .
Storage Temperature Range
Junction Temperature .
Lead Soldering (IOsec)

6.0rnA
6.0mA
O°C to +70°C
-65°C to + 150°C
+ 175°C
+ 300°C

ORDERING GUIDE

Device

Temperature
Range

AD9300KQ
Oto + 70°C
AD9300TE/883B 2 - 55°C to + 125°C
AD9300TQ/883B 2 - 55°C to + 125°C
AD9300KP
Oto + 70°C
NOTES
IE = CeramicLeadlessChipCarrier;P

Package
Option'

Description
l6-Pin Cerdip, Commercial
20-Pin LCC, Military Temperature
I6-Pin Cerdip, Military Temperature
20-Pin PLCC, Commercial

Q-16
E-20A
Q-16

P-ZOA

= Plastic LeadedChipCarrier;Q = Cerdip. Forourline

information see Package Information section.

'For specifications, refer to Analog DevicesMilitary Products Databook.

REV. A

SPECIAL FUNCTION VIDEO PRODUCTS 8-43

II

AD9300
AD9300 BURN·IN DIAGRAM

SUGGESTED LAYOUT OF AD9300
PeBOARD

D.
D,

S, _ _ _ _ _ _ _ _ _ _ _ -2.GY

D,
1kU
INPUT
RESISTORS

S,

ENABLE
GROUND
IN,

GROUND
S,

00

IN,

rI
r---, ___ +2.4V
-----1
LJ
L +O.4V
--l,00•• l-

n n n n

2kU
GROUND

S,

OUTPUT

.llma.

GROUND

S, _ _ _ _ _ _ _ _ _ _ _ +2.0V

~~

IN,

~

~

U

BYPASS

'Vs

---2.4V

L.~

S,
D, _ _ _ _- - '

OM'ION#1ISTATICIS,::: -2.0V;Sz = +2.0V
Do'" D, = +2.4V; 'lz = OV

OPTION #2 (DYNAMICI SEE WAVEFORMS

GROUND

A,

ALL RESISTORS ± 5"10
ALL CAPACITORS ±20%
ALL SUPPLY VOLTAGES :1::6%

-Vs

Suggested layout of AD9300 PC Board
(Bottom View_ Notto Seate,
ComponentSide Should be Ground Plane

METALIZATION PHOTOGRAPH
IN,

IN.

IN,

MECHANICAL INFORMATION

-Vs
BYPASS

+Vs

A,

Die Dimensions
Pad Dimensions
Metalization . .
Backing . . . .
Substrate Potential
Passivation
Die Attach
Bond Wire

84 x 104 x 18 (max) ~s
.. .. 4 x 4 (min) fu.ils
Aluminum
None
. . . -Vs
Oxynitride
Gold Eutectic
1.25 mil, Aluminum; Ultrasonic Bonding
or I mil, Gold; Gold Ball Bonding

ENABLE GROUND
RETURN

FUNCTIONAL DESCRIPTION

Ao

ENABLE

-Vs
+Vs
OUTPUT
BYPASS
GROUND
RETURN

Four analog input channels.
Analog input shielding grounds, not internally connected. Connect each to
externallow·impedance ground as close to device as possible.
One of two TTL decode control lines required for channel selection. See
Logic Truth Table.
One of two TTL decode control lines required for channel selection. See
Logic Truth Table.
TTL·compatible chip enable. In enabled mode (logic HIGH), output signal
tracks selected input channel; in disabled mode (logic LOW), output is high
impedance and no signal appears at output.
Negative supply voltage; nominally - lOY dc to ~ 15V dc.
Positive supply voltage; nominally + IOV dc to + 15V dc.
Analog output. Tracks selected input channel when enabled.
Bypass terminal for internal bias line; must be decoupled externally
to ground through O.I,..F capacitor.
Analog signal and power supply ground return.

8-44 SPECIAL FUNCTION VIDEO PRODUCTS

LOGIC TRUTH TABLE
ENABLE

Al

Ao

OUTPUT

0

X

X

HighZ

I

0

0

IN,

I

0

I

IN2

I

1

0

IN3

I

I

I

IN.

REV. A

AD9300
.....

ENABLE

A,

HIGH
LOW

.....

HIGH
LOW

HIGH
A,
LOW

OUTPUT

IN,

.....=

IN,
INa

',ow

to~

+2V
GND
-2V

to.

IN. '" -2VOLTS

= IN:.:z +2VOLTS
AD9300 Timing

THEORY OF OPERATION
Refer to the functional block diagram of the AD9300 ..
As shown on the drawing, this diagram is based on the pinouts
of the DIP packaging of the models AD9300KQ and AD9300TQ.
The AD9300KP and AD9300TE are packaged in 20-pin surface
mount packages. The extra pins are used for ground connections;
the theory of operation remains the same.

+V.

IN,

CHANNEL { __
Sl!LECTION
(AoANDA,)

__

The AD9300 Video Multiplexer allows the user to connect any
one of four analog input channels (IN I - IN.) to the output of
the device, and to switch between channels at megahertz rates.
The input channel which is connected to the output is determined
by a 2-bit TTL digital code applied to Ao and AI, The selected
input will not appear at the output unless a digital "I" is also
applied to the ENABLE input pin; unless the output is enabled,
it is a high impedance. Necessary combinations to accomplish
channel selection are shown in the Logic Truth Table.

+V.

+Vs

OUTPUT

Bipolar construction used in the AD9300 insures that the input
impedance of the device remains high, and will not vary·with
power supply voltages. This characteristic makes the AD9300,
in effect, a switchable-input buffer. An on-board bias network
makes the performance of the AD9300 independent of applied
supply voltages, which can have any nominal value from ± IOV
dc to ± ISV dc.
Although the primary application for the AD9300 is the routing
of video signals, the harmonic and dynamic attributes of the
device make it appropriate for other applications. The AD9300
has exceptional performance when switching video signals, but
can also be used for switching other analog signals requiring
greater dynamic range and/or precision than those in video.
As shown in Figure I, Input and Output Equivalent Circuits,
each analog input is connected to the base of a bipolar transistor.
If Channel I is selected, a current switch is closed and routes
current through the input transistor for Channel 1.
If Channel 2 is then selected by the digital inputs, the current
switch for Channel I is opened and the current switch for Channel
2 is closed. This causes current to be routed away from the
Channel I transistor and into the Channel 2 input transistor.
Whenever a channel's input device is carrying current, the
analog input applied to that channel is passed to the output
stage.
The operation of the output stage is similar to that of the input
stages. Whenever the output stage is enabled with a HIGH
digital "I" signal at the ENABLE pin, the output transistor will
carry current and pass the selected analog input.

REV. A

-v.
INPUT

D,

BIAS

-v.
DIGITAL

-v.
OUTPUT

Figure 1. Input and Output Equivalent Circuits

When the output stage is disabled (by virtue of the ENABLE
pin being driven LOW with a digital "0"), the output current
switch is opened. This routes the current to other circuits within
the AD9300 which keep the output transistor biased "off'.
These circuits require approximately 1,...A of bias current from
the load connected to the output of the multiplexer. In the
absence of a terminating load and the resulting dc bias, the
output of the AD9300 "floats" at - 2.SV.
In summary, when the AD9300 is enabled by the ENABLE pin
being driven HIGH with a digital "I", the selected analog input
channel acts as a buffer for the input; and the output of the
multiplexer is a low impedance. When the AD9300 is disabled
with a digital "0" LOW signal, the selected channel acts as an
open switch for the input; and the output of the unit becomes a
high impedance. This characteristic allows the user to wire-or
several AD9300 Analog Multiplexers together to form switch
matrices.
SPECIAL FUNCTION VIDEO PRODUCTS 8-45

II

AD9300
AD9300 APPLICATIONS
To ensure optimum performance from circuits using the AD9300,
it is imponant to follow a few basic rules which apply to all
high-speed devices.
A large, low-impedance ground plane under the AD9300 is
critical. Generally, GROUND and GROUND RETURN connections should be connected solidly to this plane. GROUND
pin connections are signal isolation grounds which are not connected internally; they can be left unconnected, but there may
be some degradation in crosstalk rejection. GROUND RETURN,
·on the other hand, serves as the internal ground reference for
the AD9300 and should be connected to the ground plane wilhout

exception.

The output stage of the unit is capable of driving a 2k011lOpF
load. Larger capacative loads may limit full power bandwidth
and increase topp (the interval between the 50% point of the
ENABLE high-to-Iow transition and the instant the output
becomes a high impedance.)
For applications such as driving cables (See Figure 2), output
buffers are recommended.
It is recommended that the AD9300 be soldered directly into
circuit boards, rather than using socket assemblies. lf sockets
must be used, individual pin soc.kets are the preferred choice,
rather than a socket assembly. A second requirement for proper
high-speed design involves decoupling the power supply and
interna1 bias supply lines from ground to improve noise immunity.
Chip capacitors are recommended for connectingO.ljl.F and
O.OIjl.F capacitors between ground and the ±Vs supplies
(Pins 9 and 14), and the BYPASS connection (Pin 15) .

.
Figure 2. 4x 1 AD9300 Multiplexer with Buffered Output
Driving 7512 Coaxial Cable

..

-40

-

-50

+20

r~
I=: --

..

-55

+'5

I

., +10

I

V

!--,-SECONO HARMONIC
RL =2kU 10pf

J

r-IN, =1Vp-pSINE WAVE

-70

;

/

~

.Y
~

.i

0

-00

-20

'0

'.0

OV _ _ _

~

Ii

-00
-55

10

_ _ _ _- - ,

ENABlE' _ _ _-,

ENABLE
GROUND

-'!

-as

~V

~

./1-"

/

-00

V
'0

1.0

'00

FREQUENCY-MHz

Figure 5. Crosstalkvs. Frequency

Figure 4. Outputvs. Frequency

OV_. _ _ _ _ _- - ,

~

2V pop SINE WAVE

-75

1GHz

'00
INPUT FREQUENCY -MHz

I
r-- ,",OsJTALL
INa INs = IN.. -

r-

-70

-00

100

FREQUENCY·MHz

Figure 3. Harmonic Distortion vs.
Frequency

i

\\

0-10

-'5

~

\

-s

-as

i

j[1

+5

~---------,
DV
_ _ _ _ _ _ _---,
5V _ _ _..,

ENABLE
GROUND

IN,
GROUND

Figure 6. Test Circuit for Harmonic Distortion, Pulse
Response, T-Step Response and Disable Characteristics

8-46 SPECIAL FUNCTION VIDED PRODUCTS

Figure 7. Crosstalk Rejection Test Circuit

REV. A

AD9300
200mV

SOOns

,
91

I

I

CROSSPOINT CIRCUIT APPLICATIONS
Four AD9300 multiplexers can be used to implement an 8 x 2
crosspoint, as shown in Figure II. The circuit is modular in
concept, with each pair of multiplexers (#1 and #2; #3 and
#4) forming an 8 x 1 crosspoint. When the inputs to all four
units are connected as shown, the result is an 8 x 2 crosspoint
circuit.

.

D
D
D

,
,

S

The truth table describes the relationships among the digital
inputs (Do - Ds) and the analog inputs (SI - S8); and which
signal input is selected at the outputs (OUTI and OUT2 ). The
number of crosspoint modules that can be connected in parallel
is limited by the drive capabilities of the input signal sources.
High input impedance (3M!}) and low input capacitance (2pF)
of the AD9300 help minimize this limitation.

8 x 2 Crosspoint Truth Table

....
....

I I

E A, A.
IN,
IN,
OUT
IN,
IN,
#1

,

S,
5,
S,

E
IN,
IN,
IN,
IN,

s,
S.

S;
S.
D,
D,
D.

Figure 10. EnabletoChannel
"Off" Response

Figure 9. T-Step Response

Figure 8. Pulse Response

"....

E
IN,
IN,

I I

A,

f-<> OUT,

A.

OUT

DI

Do

OUT1

or

or

or

Ds

D.

D3

OUT2

0
0
0
0
1
1
I
I

0
0
I
I
0
0
I
I

0
I
0
1
0
I
0
I

SI
S2
S3
S.
S5
S6
S7
S8

II

#2
Adding to the number of inputs applied to each crosspoint
module is simply a matter of adding AD9300 multiplexers in
parallel to the module. Eight devices connected in parallel result
in a 31 x I crosspoint which can be used with input signals
having 30MHz bandwidth and IV peak-to-peak aml?litude.
Even more AD9300 units can be added if input signal amplitude
and/or bandwidth are reduced; if they are not, distortion of the
output signals can result.

I I

A, A.

OUT

IN,

IN,

E
IN,
IN,
IN,
IN,

D2

or

#3

I A.I

f-o

A,

When an AD9300 is enabled, its low output impedance causes
the "off' isolation of disabled parallel devices to be greater than
the crosstalk rejection of a single unit.

OUT
#4

8 X2SIGNAL CROSSPOINT USING FOUR AD9300 MULTIPLEXERS

Figure 17. 8 x 2 Signal Crosspoint Using Four AD9300
Multiplexers

REV. A

SPECIAL FUNCTION VIDEO PRODUCTS

~7

8-48 SPECIAL FUNCTION VIDEO PRODUCTS

Quad 8-Bit Multiplying CMOS
D/A Converter with Memory
DAC-8408 I

r.ANALOG
WDEVICES
FEATURES

APPLICATIONS

• Four DACs in a 28 Pin, 0.6 Inch Wide DIP or 28 Pin JEDEC
Plastic Chip Carrier
• ±1/4 LSB End-Point Linearity
• Guaranteed Monotonic
• DACs Matched to Within 1%
• Microprocessor Compatible
• ReadlWrite Capability (with Memory)
• TTL/CMOS Compatible
• Four-Quadrant Multiplication
• Single-Supply Operation (+SV)
• Low Power Consumption
• Latch-Up Resistant
• Available In Ole Form

•
•
•
•
•
•
•

ORDERING INFORMATION t
PACKAGE
EXTENDED
COMMERCIAL
INDUSTRIAL
MILITARY·
TEMPERATURE TEMPERATURE TEMPERATURE
INL

DNL

DOC 10 .70'C

:l:1/4LSB
:l:1/2LSB
:l:lI2LSB
:l:1I2LSB
:l:1I2LSB

:l:1I2LSB
:l:1LSB
:1:1 LSB
:1:1 LSB
:l:1LSB

DAC8408GP

-40OC 10 .85'C -55'Clo .12S'C

DAC8408ET
DAC8408AT
DAC8408FT
DAC8408BT
DAC8408FPCtt
DAC8408FS
DAC8408FP
For devices processed in lOlal compliance 10 MIL-STD·883, add 1883 after part
number. Consult faC10ry for 883 data sheet.
t Bum·in is available on commercial and industrial temperature range parts in
CerDIP. plastic DIP, and TO-can packages.
It For availability and bum-in information on SO and PLCC packages, contact
your local sales offlce.

Voltage' Set Points in Automatic Test Equipment
Systems Requiring Data Access for Self-Diagnostics
Industrial Automation
Multi-Channel Microprocessor-Controlled Systems
Digitally Controlled Op Amp Offset Adjustment
Process Control
Digital Attenuators

GENERAL DESCRIPTION
The DAC-8408 is a monolithic quad 8-bit multiplying digital-toanalog CMOS converter. Each DAC has its own reference input,
feedback resistor, and on-board data latches that feature
read/write capability. The readback function serves as memory
for those systems requiring self-diagnostics.
A common 8-bit TTL/CMOS compatible input port is used to
load data into any of the four DAC data-latches. Control lines
DS1, DS2, and NB determine which DAC will accept data. Data
loading is similar to that of a RAM's write cycle. Data can be
read back onto the same data bus with control line Riw. The
DAC-8408 is bus compatible with most 8-bit microprocessors,
including the 6800, 8080, 8085, and Z80. The DAC-8408
operates on a single +5 volt supply and dissipates less than
20mW. The DAC-8408 is manufactured using PMl's highly
stable, thin-film resistors on an advanced oxidEHsolated,
silicon-gate, CMOS process. PMl's improved latch-Up resistant
design eliminates the need for external protective Schottky
diodes.

FUNCTIONAL DIAGRAM
v..

lOUT'.

IOUT1B

••

~w...----r-o"

I"""fAr-t"'''' ",.c
IOUT1C

AlB
R/ii

os;
Ds2

17

,.

..
19

IOUT2C1
IOUT2D

CONTROl.
LOGIC

'OUT10

DGND

REV. A

SPECIAL FUNCTION VIDEO PRODUCTS 8-49

•
:

DAC-8408
PIN CONNECTIONS

2B-PIN
HERMETIC DIP
(T-Suffix)
28-PIN
PLASTIC LEADED
CHIP CARRIER
(PC-Suffix)

28-PIN
EPOXY DIP
(P-Sufflx)
28-PIN SOL
(S-Sullix)

ABSOLUTE MAXIMUM RATINGS (TA - +25·C. unless
otherwise noted.)
Vo'o to lOUT 2A' lOUT 2B' lOUT 2C' lOUT 20 ••••••••••••..••••.•.••• O. +7V
Voo to OGNO ................................................................. O•. +7V

Storage Temperature .................................... -65'Cto +150·C
Lead Temperature (Soldering. 10 sec) ...••••.•.•...••••....•• +300'C

lOUT 1 A' lOUT 1B'
lOUT lC' lOUT 10 to DGNO ...................... -().3V to Voo + 0.3V
f\-BA• RFBB. RFBC. RFBO to lour ••••..••••••••••••••••• ,........... ±25V
lOUT 2A' lOUT 2B'
lOUT 2C' lOUT 2D to DGNO ....................... -().3V to VDD + 0.3V
OBO through OB7to OGNO ....................... -().3Vto Voo + 0.3V
Control Logic
Input Voltage to OGNO .......................... -o.3V + V00 + 0.3V
VRE~.VREFB. VREFC. VREFOto
lOUT 2A' lOUT 2B' lOUT 2C' lOUT 20··················· .. ···••••••·•••• ±25V
Operating Temperature Range
Commercial Grade (GP) .................................. O'C to +70'C
Industrial Grade (ET. FT. FP. FPC. FS) •••••• -40'C to +S5'C
Military Grade (AT. BT) •.....••.•.••..••••••.•.•.••.• -55'Cto +125'C
Junction Temperature .................................................. +150'C

28-Pln PlasIicDlP(P)
53
'Z1
"CHi
28-Pin SOl (S)
68
23
"CHi
28-Con1act PI.CC (PC)
66
29
"CHi
NOTE:
1. 8 1A is speclfoed for worst case mounting conditions. I•••• 8 jA Is speclfoed for
device In sock.t for CerOlP end P·DIP packages; ~A Is specified for device
soldered to printed circuit board lor SOl. end PLCC packeg•••
CAUTION:
1. Do not apply voltages higher than VDD +0.3V or less than-O.3V potential on
any terminal.xcept VREF and RF S'
2. The digital control inpula are dlode-protacted; however, permanent damage
may occur on unconnected inputs from high-energy .Iectrostatic n.lda. Keep
in conductive foam at all times until ready to use.
3. Use proper enti·static hendllng procedures.
4. Absolute Maximum Ratings apply 10 both packaged devices end DICE.
Stre...s above those listed under Absolute Maximum Ratings may cause
permanent damage to the device.

PACKAGE TYPE

UNITS

28-Pin Hermetic DIP (1)

65

10

"CHi

ELECTRICAL CHARACTERISTICS at Voo - +5V; VREF • ±10V; VouyA. B. C. 0 = OV; TA = -55'C to +125'C apply for DAC·
840SATIBT. TA--40'C to +S5'C apply for OAC-S40SETIFT/FPIFPCIFS; TA• O'C to +70'C apply for OAC·S40SGP. unless ot~erwise
noted. Specifications apply for OAC A. B. C. & D.
DAC-8408

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC ACCURACY
Resolution
Nonlin.arity
INotes 1, 21
Differential
Nonlinearity

INL

DAC·8408A1E/G
DAC·8408B/F/H

±1I4
±1I2

LSB

DNL

DAG-8408A1E1G

±1I2
±1

LSB

±1
±40

LSB
ppm/DC

0.001

%FSR/%

±30
±100

nA

Gain Error

Gain T.mpeo INotes 3, 61
Power Supply Rejection
I.lVOD

= ±10%1

lOUT lA. S. C. 0
L.akage Current
INote 131

Bits

8

N

DAC·8408B/F/H
I

Using Internal RFS I

TCOFS

±2

PSR
TA = +2S"C
TA = Full Temp. Range

8-50 SPECIAL FUNCTION VIDEO PRODUCTS

REV. A

OAC-840B
ELECTRICAL CHARACTERISTICS at Voo - +5V; V REF - ±10V; VourA, B, C, D. OV; TA - -S5·C to +125·C apply for DAC840SATIBT, T A - -40·C to +S5·C apply for DAC-S40SETIFT/FPIFPCIFS; T A - O·C to + 70·C apply for DAC-S40SGP, unless otherwise
noted. Specifications apply for DAC A, B, C, & D. Continued
PARAMETER

SYMBOL

CONDITIONS

MIN

CAe-S40B
TYP
MAX

UNITS

±20

V

±1

%

14

kn

0.8

V

REFERENCE INPUT
Inpul Vollage Range
Input Resistance Match
(Note 41
Input Resistance

RA, B. C, 0
6

R'N

10

DIGITAL INPUTS
Digital Input Low

V,L

Digital Input High

V,H

Input Current
(Note 51

liN

Input Capacitance
(Note 61

C'N

2.4
TA
TA

= +25"C
= Full Temp.

V
±0.01

Range

±1.0
±10.0

~A

pF

DATA BUS OUTPUTS
Digital Output low

VOL

1.6mA Sink

Digital Output High

VOH

400~A

ILKG

TA
TA

Output leakage
Current

0.4

Source

= +25"C
= Full Temp.

V
V

Range

±0.005
±0.075

±1.0
±10.0

~A

DAC OUTPUTS (Note 61
Propagation Delay
(Note 71

tpo

150

180

ns

Settling Time
(Notes II, 121

t,

190

250

ns

Output Capacitance

C OUT

DAC latches All "O's"
DAC latches All "I's"

30
50

pF

AC Feedthrough

FT

120Vp•p @ F = 100kHZI

54

dB

= +25"C
= Full Temp. Range

90
145

ns

TA = +25"C
TA = Full Temp. Range

150
175

ns

SWITCHING CHARACTERISTICS I Notes 6,101
Write to
Data Strobe Time

t051 or
t082

TA
TA

Data Valid to
Strobe Set·Up Time

tosu

Data Valid to
Strobe Hold Time

tOH

10

ns

DAC Select to
Strobe Set-Up Time

tAS

0

ns

DAC Select to
Strobe Hold Ti me

tAH

0

ns

Write Select to
Strobe Set-Up Time

t wsu

Write Select to
Strobe Hold Time

tWH

REV. A

ns

0

ns

SPECIAL FUNCTION VIDEO PRODUCTS 8-51

•

DAC~8408
ELECTRICAL CHARACTERISTICS at Voo" +5V; VREF - ±10V; Voul', B, C, D - OV; TA - -o5·Cta +125·C apply for DACB40BATIBT, TA - ..-40·C to +B5·C apply for DAC-840BETIFT/FPIFPCIFS; TA'. O·C to +70·C'apply for DAC·B40BGP, unless otherwise
noted. Specifications apply for DAC A, B, C,& D. Continued
.
DAC-8408
PARAMETER

CONDITIONS

MIN

Read to
Data Strobe Width

220

tROS

TA = +2SoC
TA = Full Temp. Range

Data Strobe to
Output Valid Time

TA = +2SoC
TA = Full Temp. Range

320

teo

tOTO

T A = +2SoC
TA, = Full Temp. Range

200
ZTO

ns

Output Data to

Deselect Time

TYP

MAX

SYMBOL

UNITS
ns

3S0

ns

430

Read Select to
Strobe Set-Up Time

tASU

0

ns

Read Select to
Strobe Hold Time

tRH

0

ns

POWER SUPPLY
Voltage Range

Voo

Supply Current
(Note B)

100

Supply Current
(Note 9)

100

4.S

TA = +2SoC
TA = Full Temp. Range

S.S

V

SO

I'A

1.0
1.S

mA

7. From Dig.ltal Input to 90% of final analog output current.

NOTES:

1. This is an end-point linearity specification.
2. Guaranteed to be monotonic over the full operating temperature range.
3. ppm/oC of FSR (FSR = Full Scale Range = V REF -1 LSB.)
4. Input Resistance Temperature Coefficient = +300ppm/oC.

5. Logic Inputs are MOS gates. Typical input current at +25°C is less than
10nA
6. Guaranteed by design.

B.
9.
10.
11.
12.

All Digital Inputs "0" or Voo.
All Digital Inputs V ,H or V ,L.
See Timing Diagram.
Digital Inputs = OV to Voo or Voo to OV.
Extrapolated: t, (1/2 LSB) = tpo + 6.2T where T = the measured first time
constant of the final RC decay.
.
13. All Digital Inputs = OV; VREF = +10V.

BURN-IN CIRCUIT
+.v

Yo.

+10Y
R1

le,

~4.7"F

1~1

1kl!

1 Voo
2
VREFA

L! RFaA

~O.01"F

R2
SkU

~7

"

IOUT1A

5

lOUT 2A/ioUT 2B

6

IOUT1B

7

RFBB

8 VREFB

---2.
,.....1!!.

.,

(LSB) DBO

DGND
VREFC

RFSe
IOUT1C

lOUT 2c1loUT 20
lOUT 10

RF8D
VREFD

oS2

DB'

Dii

.-l!

DB2

R/W

~

DB'

Alii

13 OB4

DB7(MSB}

~

DB'

DB•

l'

2.
27

t~,

28

2.
24

23
22
21

.

t

~'7

20

~
,

17

.!L~

R"

SkU

V

lOOk!!

~7

8-52 SPECIAL FUNCTION VIDEO PRODUCTS

REV. A

OAC-8408
DICE CHARACTERISTICS

1. Voo

2. VREFA
3. RFBA
4. IOUT1A
5. lOUT 2AIIOUT 2B
6. IOUTtB

7. RFBB
8. VREFB
9.DBO(LSB)

10. DBl
11. DB2

12. DB3
13. DB4
14. DB5

15. DB6
16. DB7 (MSB)
17.A/B
18. R/W
19. DSl
20. DS2
21. VREFD
22. RF8D
23. IOUT10
24. louT 2CllOUT 20
25. IOUTtC
26. RFBC
27. VAEFC
28. DGND

DIE SIZE 0.130 X 0.124 inch, 16,120 sq. mils
(3.30 X 3.15 mm, 10.4 sq. mm)

WAFER TEST LlMITSat VDD =+5V; VREF =±10V; VouTA, B, C, 0 =OV; TA =+25°C, unless otherwise noted. Specifications apply for
DAC A, B, C, & D.

DAC-S40SG
PARAMETER

SYMBOL

CONDITIONS

LIMITS

UNITS

±112

LSB MAX

STATIC ACCURACY
Resolution

N

Nonlinearity I Note 11

INL

Bit. MIN

Differential Nonlinearity

DNL

±1

LSB MAX

Gain Error

G FSE

Using Internal RFS

±1

LSB MAX

Power Supply Rejection
I~VDD = ±10%IINote 21

PSR

Using 'Internal RFB

0.001

%FSR/% MAX

lOUT lA, 8, C, 0 Leakage Current

'LKG

±30

nAMAX

All Digital Inputs = OV
VAEF = +10V

REFERENCE INPUT
Reference Input
Resi.tance I Note 31

R'N

6/14

kll MINIMAX

Input Resistance Match

R'N

±1

% MAX

Digital Input Low

V,L

0.8

V MAX

Digital Input High

V,H

2.4

VMIN

Input Current I Note 41

liN

±1.0

~AMAX

DIGITAL INPUTS

REV. A

SPECIAL FUNCTION VIDEO PRODUCTS ~53

•

DAC-8408
WAFER TEST LIMITS at VDD= +5V; VREF= ±10V; VOUTA, B, C, D = OV; r A= +25°C, unless otherwise noted. Specifications apply for
DAC A, B, C, & D. (Continued)
DAC-8408G
MRAMETER

CONDmONS

SYMBOL

UMITS

UNITS

0.4

V MAX

DATA BUS OUTPUTS
Digital Output Low

VOL

1.6mASlnk

Digital Output High

VOH

400ilA Source

Output Leakage Current

ILKG

4

VMIN

±1.0

"A MAX

POWER SUPPLY
Supply Current (Note 6)

100

50

I'AMAX

Supply Current (Note 6)

100

1".0

.mAMAX

NOTES:
1. This is an endpoint linearity specification.
2. FSR is Full Scale Range = VREF - 1 LSB..
3. Input Resistance Temperature Coefficient approximately equals
+300ppmI"C.

4. Logic inputs are MOS gates. Typical input currentat+2S'C is less than 10nA.
5. All Digital Inputs are either "0" or Voo
6. All Digital Inputs are either V,H or V,L.

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss. yield after packaging Is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

TYPICAL PERFORMANCE CHARACTERISTICS
ANALOG CROSSTALK
VI FREQUENCY

SUPPLY CURRENT
vs LOGIC LEVEL
4 .•

4..

,J'e

T•••

I

A

1\
\

...
••

i
~
"

-30

c

-70

0

"9cz

1.5

1.0

YiN ATYJtuA
YOUTATDAC 8
VA.,a GROUNDED
YiN = 4 Vp •p

-zo

3.5
3.0

Jb~b:

TA"'+25"C

-10

ALL DIGITAL INPUTS neD TOGETHER -

-40
-50

-eo
",.

-80

.......
~
Y,N (VOLTS)

8-54 SPECIAL FUNCTION VIDEO PRODUCTS

-80
-100

,.

r
10k

lOOk

1M

FREQUENCY ,Hz)

REV. A

DAC-8408
TIMING DIAGRAM

TIMING MEASUREMENT REFERENCE LEVEL IS VIH

~ VINL.

PARAMETER DEFINITIONS
RESOLUTION
Resolution is the number of states (2n) that the full-scale range
(FSR) of a DAC is divided (or resolved) into.

AC FEEDTHROUGH ERROR
This is the error caused by capacitance coupling from VREFtO
the DAC output with all switches off.

NONLINEARITY
Nonlinearity (Relative Accuracy) is a measure of the maximum
deviation from a straight line passing through the end-points of
the DAC transfer function. It is measured after adjusting for
ideal zero and full-scale and is expressed in LSB. %. or ppm of
full-scale range.

SETTLING TIME
Settling Time is the time required for the output function of the
DAC to settle to within 1/2 LSB for a given digital input signal.

DIFFERENTIAL NONLINEARITY
Differential Nonlinearity is the worst case deviation of any
adjacent analog outputs from the ideal 1LSB step size. A
specified differential nonlinearity of ±1 LSB maximum over the
operating temperature range ensures monotonicity.

GAIN ERROR
Gain Error (full-scale error) is a measure of the output error
between the ideal and actual DAC output. The ideal full-scale
output is VREF-1 LSB.

PROPAGATION DELAY
This is a measure ofthe internal delays of the DAC.lt is defined
as the time from a digital input change to the analog outputcurrent reaching 90% of its final value.
CHANNEL-TO-CHANNEL ISOLATION
This is the portion of input signal that appears at the output of a
DAC from another DAC's reference input. It is expressed as a
ratio in dB.
DIGITAL CROSSTALK
Digital Crosstalk is the glitch energy transferred to the output of
one DAC due to a change in digital input code from other
DACs. It is specified in nVs.

OUTPUT CAPACITANCE
Output Capacitance is that capacitance between lOUT 1A.
lOUT 180 lOUT 1C. or lOUT 10 and AGND.

REV. A

SPECIAL FUNCTION VIDEO PRODUCTS 8-55

II

OAC-840B
CIRCUIT INFORMATION

FIGURE 1: Simplified D/A Circuit of DAC-8408

The DAC-8408 combines four identical 8~bit CMOS DACs onto
a single monolithic chip. Each DAC has its own reference input,
feedback resistor, and on-board data latches. It also features a
read/write function that serves as an accessible memory
location for digital-input data words. The DAC's three-state
read back drivers place the data word back onto the data bus.
D/A CONVERTER SECTION
Each DAC contains a highly stable, silicon-chromium, thin-film,
R-2R resistor ladder network and eight pairs of current steering
switches. These switches are in series with each ladder resistor
and are single-pole, double-throw NMOS transistors; the gates
of these transistors are controlled by CMOS inverters. Figure 1
shows a simplified circuit of the R-2R resistor ladder section,
and Figure 2 shows an approximate equivalent switch circuit.
The current through each resistor leg is switched between lOUT 1
and lOUT 2. This maintains a constant current in each leg,
regardless of the digital input logic states.
Each transistor switch has a finite "ON" resistance that can
introduce errors to the DAC's specified performance. These
resistances must be accounted for by making the voltage drop
across each transistor equal to each other. This is done by
binarily-scaling the transistor's "ON" resistance from the most
significant bit (MSB) to the least significant bit (LSB). With 10
volts applied at the reference input, the current through the
MSB switch is O.SmA, the next bit is 0.2SmA, etc.; this maintains
a constant 10mV drop across each switch and the converter's
accuracy is maintained. It also results in a constant resistance
appearing at the DAC's reference input terminal; this allows the
DAC to be driven by a voltage or current source, AC or DC of
positive or negative polarity.
Shown in Figure 3 is an equivalent output circuit for DAC A. The
circuit is shown with all digital inputs high. The leakage current
source· is the combination of surface and junction leakages to
the substrate. The 1/2S6 current source represents the constant
l-bit current drain through the ladder terminating resistor. The
situation is reversed with all digital inputs low, as shown in
Figure 4. The output capacitance is code dependent, and
therefore, is modulated between the low and high values.

8-56 SPECIAL FUNCTION VIDEO PRODUCTS

OB7

DBl

086

080
(LSS)

FIGURE 2: N-Channel Current Steering Switch
TO LADDER

FROM~
0----1

INTERFACE
LOGIC

'OUT2

'OUT 1

FIGURE 3: Equivalent DAC Circuit (All digital inputs HIGH)
RFEEDBACK

.....----O 'OUT lA

O---oI""'--.----~----t-VREF

r------.-----o 'OUT 2A

REV. A

OAC-840B
FIGURE 4: Equivalent DAC Circuit (All digital inputs LOW)
RFEEDBACK

"",Okn
. . . - - - -.....--+----O'OUT1A

'REF
~

""10kG

o--'IIII'r-.....- - - - 1 r - - - - - - . - - - - - - - O IOUT2A

INTERFACE LOGIC SECTION
DAC Operating Modes
• All DACs in HOLD MODE.
• DAC A, B, C, or 0 individually .selected (WRITE MODE).
• DAC A, B, C, or 0 individually selected (READ MODE).
• DACs A and C simultaneously selected (WRITE MODE) .
• DACs Band 0 simultaneously selected (WRITE MODE).
DAC Selection: Control inputs, DS1, DS2, and AlB select which
DAC can accept data from the input port (see Mode Selection
Table).
Mode Selection: Control inputs OS and RtW control the
operating mode of the selected DAC.
WrIte Mode: When tt)e control inputs OS and R/W are both low,
the selected DAC is in the write mode. The input data latches of
the selected DAC are transparent, and its analog output
responds to activity on the data inputs DBO-DB7.

DIGITAL SECTION
Figure S shows the digital input/output structure for one bit.
The digital WR, WR, and RD controls shown in the figure are
internally generated from the external AlB, R/W, DS1, and DS2
signals. The combination of these signals decide which DAC is
selected. The digital inputs are CMOS inverters, designed such
that TTL input levels (2.4V and O.BV) are converted into CMOS
10gic·levels. When the digital input is in the region of 1.2 to 1.BV,
the input stages operate in their linear region and draw current
from the +SV supply (see Typical Supply Current vs Logic Level
curve on page 6). It is recommended that the digital input
voltages be as close to V DO and DGND as is practical in order to
minimize supply currents. This allows maximum savings in
power dissipation inherent with CMOS devices. The three-state
read back digital output drivers (in the active mode) provide
TTL-compatible digital outputs with a fan-out of one TTL load.
The three-state digital read back leakage-current is typically SnA.
FIGURE 5: Digital Input/Output Structure

...-------RD

...-----+_ SWITCH
TO 'OUT 2

Hold Mode: The selected DAC latch retains the data that was
present on the bus line just prior to OS or R/W going to a high
state. All analog outputs remain at the values corresponding to
the data in their respective latches.
Read Mode: When OS is low and R/W is high, the selected DAC
is in the read mode, and the data held in the appropriate latch is
put back' onto the data bus.
MODE SELECTION TABLE
CONTROL LOGIC
DS1
DS2
AlB
R/W
DAC
MODE
L
H
H
L
WRITE
A
L
H
L
WRITE
B
L
WRITE
H
L
H
C
L
H
L
L
L
WRITE
0
H
L
H
H
READ
A
L
H
L
H
READ
B
H
L
H
C
H
READ
H
H
L
L
READ
0
L
L
H
L
WRITE
A&C
L
L
L
L
WRITE
B&D
X
X
HOLD
AlB/C/O
H
H
L
L
H
H
HOLD
AlB/C/O
L
L
L
H
HOLD
AlB/C/O
L= LOW STATE H = HIGH STATE X = IRRELEVANT

WR

REV. A

SPECIAL FUNCTION VIDEO PRODUCTS 8-57

•

DAC-8408
BASIC APPLICATIONS
Some basic circuit configurations are shown in Figures 6 and 7.
Figure 6 shows th!3 DAc:-B408 connected in a unipolar configuration (2-Quadrant Multiplication), and Table I shows the Code
Table. Resistors R1, R2, R3, and R4 are used to trim full scale
output. Full-scaleoutputvoltage=VREF -1 LSB=VREF (1-z-il) or
VREF x (255/256) with ~II digital inputs high. Low temperature
coefficient (approximately 5Oppm/oC) resistors or trimmers
should be selected if used. Full scale can also be adjusted using
VREFvoltage. This will eliminate resistors R1, R2, R3, and R4.ln
many applications, R1 through R4 are not required, and the
maximum gain error will then be that of the DAC.

are used only if gain error adjustments are required and range
between 50 and 10000. Resistors R21. R22, R23, and R24 will
range betwen 50 and SOOO. If these resistors are used, it is
essential that resistor pairs R9-R13, R10-R14, Rll-R15,
R12-R16 are matched both in value and tempco. They should
be within 0.01%; wire wound or metalfoil types are preferred for
best temperature coefficient matching. The circuits of Figure 6
and 7 can either be used as a fixed reference DlA converter, or
as an attenuator with an AC input voltage.

TABLE I: Unipolar Binary Code Table (Refer to Figure 6.)
DAC DATA INPUT
MSB
LSB

Each DAC exhibits a variable output resistance that is codedependent. This produces a code-dependent, differential nonlinearity term at the amplifiQr's output which can have a
maximum value of 0.67 x the amplifier's offset voltage. This
differential nonlinearity term adds to the R-2R resistor ladder
differential-nonlinearity; the output may no longer be monotonic. To maintain monotonicity and minimize gain and linearity
errors, it is recommended that the op amp offset voltage be
adjusted to less than 10% of 1 LSB (1 LSB = ~ X VREF or
11256 X VREF ), or less than 3.9mVovertheoperating temperature
range. Zero-scale output voltage (with all digital inputs low)
may be adjusted using the op amp offset adjustment. Capacitors
C1, C2, C3, and C4 provide phase compensation and help prevent overshoot and ringing when using high speed op amps.

()

0 0

0 0

0

0 0 0

0 0

0

-VREF (129)
'256
0

-VREF

(128) -VIN
256 =-2-

-VREF (127)
256

0

Figure 7 shows the recommended circuit configuration for the
bipolar operation (4-quadrant multiplication), and Table II
shows the Code Table. Trimmer resistors Rl7, R18, R19, and R20

ANALOG OUTPUT

0 0 0 0

0 0

0

0 0 0 0

0 0

0

0

-VREF

(2~6)

-VREF

(2~6) =0

NOTE:
1
1 LSB = IZ-8) IVREF ) = 256 IVREF )

FIGURE 6: Quad DAC Unipolar Operation (2-Quadrant Multiplication)

1 y. .

Rl

v..

2· VAEFA
•

•

VOUTA

R....

VREF
DAC~8408

IOUT1A

5 lOUT ZAlloUT 2B
6 IOUT1B

7

RFaR

8 VAE,B

•

vo,""

10

11
I.

RF8C
IoUT1C

lOUT zc/IOUT 20

lOUT 10

..
R'

~

26

os
VourC

24
23

RFaD 22
VREF

1m

21

vo"",

20

DSI ,. } DIGITAL

Alii
AlB

18

;~~~~~L

17

I.

16

14

15

-AU AMPLIFIERS ARE OP-27s. 1/4 OP-42O&, OR 1/4 OP-4211.

~58 SPECIAL FUNCTION VIDEO PRODUCTS

REV. A

OAC-840B
FIGURE 7: Quad DAC Bipolar Operation (4-Quadrant Multiplication)

R5
R17

..

Voo

..

VRa=C 27

VREFA

AFBC

RFaA

IOUT1C

IOUT1A

2.

24
lOUT , .

IoUT1D

2.

R. . B

RFBD 22

v.....

VREFD 21
211

10

DAC-8408

11

,.
,.
,.

,. } DIGITAL
18

~~~~L

17
16
15

·AlL AMPLIFIERS ARE OP-27s, 1/4 OP-420s. OR 1/4 OP-421s.

TABLE II: Bipolar (Offset Binary) Code Table (Aeferto Figure 7.)
DAC DATA INPUT
MSB
LSB

0 0

0 0 0

0

0 0 0 0

0

0

ANALOG OUTPUT
(DAC A OR DAC B)
+VREF

( 127)
128

+VREF

(1~8)
0

0

0

-VREF

(1~8)

0 0 0

-VREF (127)
128

0 0 0 0 0

-VREF' (128)
128

0

0

0 0

0

0

0

APPLICATION HINTS
General Ground Management: AC or transient voltages between
AGND and DGND can appear as noise at the DAC-8408's •
analog output. Note that in Figures 5 and 6, lOUT 2A/loUT2Band
:
lOUT 2c1loUT 20 are connected to AGND. Therefore, it is
recommended that AGND and DGND be tied together at the
DAC-8408 socket. In systems'where AGND and DGND are tied
together on the backplane, two diodes (1N914 or equivalent)
should be connected in inverse parallel between AGND and
DGND.
Write Enable Timing: During the period when both OS and RiW
are. held low, the DAC latches are transparent and the analog
output responds directly to the digital data input. To prevent
unwanted variations of the analog output, the R/W should not
go low until the data bus is fully settled (DATA VALID).

NOTE:
1
1 LSB = 1Z- 71IVREF I = 128 IVREFI

REV. A

SPECIAL FUNCTION VIDEO PRODUCTS 8-59

DAC-8408
TABLE III: Single Supply Binary Code Table (Refer to
Figure 8)

SINGLE SUPPLY, VOLTAGE OUTPUT OPERATION
The DAC-8408 can be connected with a single +5V supply to
produce DAC output voltages from OV to +1.5V. In Figure 8.
the DAC-8408 R-2R ladder is inverted from its normal connection. A +1.500V reference is connected to the current
output pin 4 (lOUT 1A). and the normal VREFinput pin becomes
the DAC output. Instead ola normal current output. the R-2R
ladder outputs a voltage. The OP-490, consisting of four
precision low-power op amps that can operate its inputs and
outputs to zero volts. buffers" the DAC to produce a lowimpedance output voltage from OV to +1.5V full-scale. Table
III shows the code table.
"

DAC DATA INPUT
MSB
LSB

ANALOG OUTPUT

VREF (255)
256 • +1.4941V

With the supply and reference voltages as shown. better than

0 0

0 0 0 0

0 0

0 0 0 0

129)
VREF ( 256 • +0.7559V
0

VREF

VREF (127)
256 • +0.7441 V

0

1/2 LSB differential and integral nonlinearity can be ex-

pected. To maintain this performance level. the +5V supply
must not drop below 4.75V. Similarly. the reference voltage
must be no higher than 1.5V. This is because the CMOS
switches require a minimum level of bias in orderto maintain
the linearity performance.

( 128) +0.7500V
256 •

0 0

0 0 0

0 0

0 0

0 0 0

0 0 0

VREF
VREF

(2~6)'

+0.0059V

(2~6)'

O.OOOOV

FIGURE 8: Unipolar Supply. Voltage Output DAC Operation

+5V

DBG (LSB)

D81

,.

DB2 • • • • • • • • • DBS

11

15

087 (MSS)

,.
17
18

,.2.

LATCH + THREE·STATE BUFFER

R....

AlB

RIW
1!R

en
N.C.

+_V

VOUT
ovTO +1.5V

..

DGND

8-60 SPECIAL FUNCTION VIDEO PRODUCTS

1/4 DAC .....08

REV. A

0

[ _ _ _ _ _ _ _ _ _ _ _ _ _ _DAC-840
FIGURE 9: A Digitally Programmable Universal Active Filter

""

100kn
1%
1000pF
21

INPUT

+1SV

"8

100kO

1%

HIGH

",a

PASS

VREF

r----------+----------------::-BA:-"':NO
PASS

DIGITAL INPUT

CONTROLS

A DIGITALLY PROGRAMMABLE ACTIVE FILTER
A powerful D/A converter application is a programmable
active filter design as shown in Figure 9. The design is based
on the state-variable filter topology which offers stable and
repeatable filter characteristics. DAC Band DAC D can be
j1rogrammed in tandem with a single digital byte load which
sets the center frequency of the filter. DAC A sets. the Q of
the filter. DAC C sets the gain of the filter transfer function.
The unique feature of this design is that varying the gain of
filter does not affect the Q of the filter. Similarly, the reverse is
also true. This makes the programmability of the filter
extremely reliable and predictable. Note that low-pass, highpass, and bandpass outputs are available. This sophisticated
function is achieved in only two IC packages.
The network analyzer photo shown in Figure 10 superimposes five actual bandpass responses ranging from the lowest frequency of 75Hz (1 LSB ON) to a full-scale frequency of
19.132kHz (all bits ON), which is equivalent to a 256 to 1
dynamic range. The frequency is determined by fe = 1/21l"RC
where R is the ladder resistance (RIN) of the DAC -B40B, and
C is 1000pF. Note that from device to device, the resistance
RIN varies. Thus some tuning may be necessary.

REV. A

FIGURE 10: Programmable Active Filter Band-Pass Frequency
Response

II
THE CIRCUIT PROVIDES FULL B~BIT
(> 2 DECADE) DVNAMIC RANGE OF
FREQUENCV CONTROL

All components used are available off-the-shelf. Using low
drift thin-film resistors, the DAC-B40B exhibits very stable
performance over temperature. The wide bandwidth of the
OP-470 produces excellent high frequency and high Q
response. In addition, the OP-470's low input offset voltage
assures an unusually low DC offset at the filter output.

SPECIAL FUNCTION VIDEO PRODUCTS 8-61

OAC-840B
FIGURE 11: A Digitally Programmable, Low-Distortion Sinewave Oscillator

OUTPUT

1%

475q
1%

100kO
6.8kO

100kO

..t)lh>---'Vyy.-

!-=--+-~---'M,---

-15V

r--K~---' -2.7V

A LOW-DISTORTION, PROGRAMMABLE
SINEWAVE OSCILLATOR
By varying the previous state-variable filter topology slightly,
one can obtain a very low distortion sinewave oscillator with
programmable frequency feature as shown in Figure 11.
Again, DAC Band DAC D in tandem control the oscillating
frequency based on the relationship fc = 1/2rrRC. Positive
feedback is accomplished via the 82.5k!1 and the 20k!1 potentiometer. The Q of the oscillator is determined by the ratio of

~62

SPECIAL FUNCTION VIDEO PRODUCTS

10kll and 47511 in series with the FET transistor, which acts
as an automatic gain control variable resistor. The AGC
action maintains a very stable sinewave amplitude at any
frequency. Again, on,y two ICs accomplish a very useful
function.
At the highest frequency setting, the harmonic distortion
level measures 0.016%. As the frequencies drop, distortion
also drops to a low of 0.006%. At the lowest frequency setting,
distortion came back up to a worst case of 0.035%.

REV. A

1IIIIIIII ANALOG

Octal 8-Bit CMOS
O/A Converter
OAC-88DD I

WDEVICES
FEATURES

GENERAL DESCRIPTION

•
•
•
•
•
•
•
•

The DAC-8800 TrimDAC™ is designed to be a general purpose
digitally controlled voltage adjustment device. The output
voltage range can be independently set for each set of four D/A
converters. In addition, both unipolar and bipolar output voltage
ranges are easy to establish by external reference input high and
low terminals. The digitally-programmed output voltages are
ideal for op amp trimming, voltage-controlled amplifier gain
setting and any general purpose trimming tasks.

:t1/2 LSB Total Unadjusted Error
21!s Settling Time
Serial Data Input
:tFull·Scale Output Set by VREFH and VREFL
Unipolar and Bipolar Operation
TTL Input Compatible
20·Pin DIP or SOL Package
Low Cost

A three-wire serial digital interface loads the contents of eight
internal DAC registers which establish the output voltage levels.
An asynchronous Clear (ClR) input places all DACs in a zero
code output condition, very handy for system power-up. An
internal regulator provides TTL input compatibility over a wide
range of VD D supply Voltages. Single supply operation is
available by connecting Vss to GND.

APPLICATIONS
•
•
•
•

Voltage Set Point Control
Digital Offset & Gain Adjustment
Microprocessor Controlled Calibration
General Purpose Trimming Adjustments

FUNCTIONAL DIAGRAM

ORDERING INFORMATION I
PACKAGE
CERDIP
20-PIN
DAC8800BR*
DAC8800FR

PLASTIC
2D-PIN

DAC8800FP

so
20-PIN

DAC8800FS"

OPERATING
TEMPERATURE
RANGE
-55·C 10 + 125·C
-40·C 10 +85·C

For devices processed in lolal compliance 10 MIL·STD·883. add 1883 after part
number. Consult factory for 883 dala sheel.
Burn-in is available on commercial and industrial temperature range parts in
CerDIP and plastic DIP packages.
It For availability and burn-in informalion on SO package, conlaclyour local sales
office.

*
VOUTA
VOUTB

u;

••

VOUTC

VouTD

PIN CONNECTIONS

20·PIN CERDIP
(R·Suffix)
20·PINSOL
(S·Sufflx)
20·PIN EPOXY DIP
(P·Suffix)

REV. A

SPECIAL FUNCTION VIDEO PRODUCTS ~63

8

OAC-88UU
ELECTRICAL CHARACTERISTICS:

(Note 1) Unless otherwise noted, SINGLE SUPPLY: V 00 = + 12V, V 55 = OV, V REFH = +5V,

VRE~L,=OV; or DUAL SUPPLY: V OD = +12V, V55 =-5V, VREFH = +2.5V, V REF L=-2.5V; FGRADE: -40°Cs:TA s: +85°C; BGRADE:
-55°C s: TA s: +125°C.
DAC-8800
PARAMETER
STATIC ACCURACY

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

All specifications apply for DACs A, B. C, D, E, F, G, H

Resolution

N

Total Unadjusted Error
(Note 2)

TUE

~1/2

LSB

Differential Nonlinearity
(Note 3)

DNL

~1

LSB

Bits

8

Full Scale Error

GFSE '

~1/2

LSB

Zero Code Error

VZSE

~1/2

LSB

16

kg

DAe Output Resistance

DAC Output Resistance Match

8

ROUT

12
0.5

dRou.,!ROUT

%

REFERENCE INPUT
Voltage Range (Note 5)

Input Resistance
Input ReSistance Match
Reference Input
Capacitance (Note 4)

VREFH

Pins 2 & 19

VREFL

(VDD- 4)

VREFL

Pins 1 &20

Vss

VREFH

V
VREFH

Digital Inputs • 55H

dRREFH/RAE~

Digital Inputs • 55 H

CAEF

Digital Inputs All Zeros
Digital Inputs All Ones

2

kg

3

0.5
50
75

%
75
100

pF

DIGITAL INPUTS
Logic High

V,NH

Logic Low

V1NL

Input Current

liN

Input Capacitance (Note 4)

C'N

2.4

V
0.8

V

~1

I1A

8

pF

0.2

2
0.4

mA

0.01

0.2

mA

12
12

24
25

mW

0.001

0.01

%/%

0.8

2

I1S

V ,N • OV or +5V
4

BINARY

Input Coding
POWER SUPPLIES (Note 6)

TIL

Positive Supply Current

IDD

Dual Supply

Negative Supply Current

Iss

Dual Supply

PDISS

Single Supply Operation
Dual Supply Operation

PSRR

dVDD

Power Dissipation
DC Power Supply
Rejection Ratio

CMOS

.~5%

DYNAMIC PERFORMANCE (Note 4)
V OUT Settling Time

ts

~ 1/2

Channel-to-Channel
Crosstalk (Note 7)

cr

Measured Between Adjacent DAC Outputs

8-64 SPECIAL FUNCTION VIDEO PRODUCTS

LSB Error Band

80

nVs

REV.

A

OAC-88DD
ELECTRICAL CHARACTERISTICS: (Note 1) Unless otherwise noted, SINGLE SUPPLY: Voo m+12V, Vss =OV, VREFH '"' +SV,
VREFL = OV; or DUAL SUPPLY: Voo -+12V, Vss =-SV, VREFH '"' +2.SV, VREFL =-2.SV; FGRADE: -40'C:s TA:S +8S'C; B GRADE:
-SsoC :S T A :S + 12S'C. Continued
DAC-8800
PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SWITCHING CHARACTERISTICS (Notes 4, 8)
Input Clock Pulse Width

'cH'

'cL

60

Clock Level High or Low

ns

Data Setup Time

tos

30

ns

Data Hold Time

tOH

30

ns

DAC Register Load Pulse Width

t Lo

50

ns

Clear Pulse Width

tCLR

50

ns

Clock Edge to Load Time

'cKLO

50

ns

Load Edge to Next Clock
Edge Time

t LocK

50

ns

NOTES:
I. Tesling performed in SINGLE SUPPLY mode, except 100 , Iss' and PSRR
which are tested in DUAL SUPPLY mode.
2. Includes Full Scale Error, Relative Accuracy, and Zero Code Error.
3. All deyices guaranteed monotonic over the full operating temperature range.
4. Guaranteed by design and not subject to production test.
5. V DO - 4 volts is the maximum reference voltage for the above specifications.
Also VAEFH:I: VREFL.

6. Digital Input voltages VIN = V INL orVINH tor TTL condition; VIN =OVor +5V for
CMOS condition. DAC outputs unloaded. POISS is calculated from (100 x V0 oj
+ (Iss x Vss>'·
7. Measured atVouT pin where an adjacent VOUT pin is making a full-scale voltage change.
8. See timing diagram for location of measured values.

DETAILED DAC-8800 BLOCK DIAGRAM

•

+5V FOR INTERNAL LOGIC

LD~------~>-------------~~C=}------1~~~

YourS
VOUTC

YourO
YourE

VOUTF
YOUTG
YourH

D

CUi

NEGATIVE

SUPPLY

REV. A

SPECIAL FUNCTION VIDEO PRODUCTS 8-65

OAC-88DD
DICE CHARACTERISTICS

1.
2.
3.
4.
5.
8.
7.
8.
9.
10.

11.
12.
13.
14.
15.
16.
17.
18.
19.
20.

DIE SIZE 0.151 x 0.130 Inoh,19,830 aq. mila
(3.8354 x 3.3033 mm, 12.864 aq. mm)

WAFER TEST LIMITS at VDD - +12V. Vss = OV. VREFH = +5V, VREFL - OV; TA = +25°C unless otherwise noted.
DAC-8800G
PARAMETER

SYMBOL

Total Unadjusted Error

TUE

CONDITIONS

LIMIT

UNITS

±112

LSBMAX

Differential Nonlinearity

DNL

±1

LSBMAX

Full5cale Error

GFse

±1I2

LSBMAX

Zero Code Error

Vzse

±112

LSBMAX

RoUT

8
16

knMIN
knMAX

2

knMIN

DAC Output Resistance

Digital Inputs _ 55H

Reference Input Resistance

RREFH

Digital Inputs High

VINH

2.4

V MIN

DIgital Inputs Low

VINL

0.8

V MAX

Digital Input Current

liN

:1:1

JIA MAX

2
0.4

mAMAX

0.2

mAMAX

0.01

%1% MAX

Positive Supply Current

100

Vss=-5V

Negative Supply Current

Iss

Vss--5V

DC Power Supply
Rejection Ratio

PSRR

TTL
CMOS

NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging Is not guaranteed for
standard product dice. Consult factory to nsgotiate specifications based on dice lot qualifications through sample lot assembly and testing.

8-66 SPECIAL FUNCTION VIDEO PRODUCTS

REV. A

DAC-8800
ABSOLUTE MAXIMUM RATINGS (TA = +25·C,

unless

PACKAGE TYPE

UNITS

otherwise noted)
Voo to Vss ............................................................... OV, +20V

20-Pin Hermetic DIP (R)

76

11

'CIW

Voo to GND ................................................................ OV, +20V

20-Pin Plastic DIP (P)

69

27

'CIW

Vss to GND ................................................................ -20V, OV

20-Pin 50 (5)

88

25

'CIW

Digital Input Voltage to GND .•••••••...•• GND - 0.3V, Voo + 0.3V
VREFH to GND .••••••••••••••••••.••••••••••••••••••••••••••.•.••••••••• VREFL, Voo
VREFLtoGND .••••••••••••••••••••••••..••••••••••••••••.•••••••••••••• V ss ' VREFH
V OUT to GND ........................................................ VREFL, VREFH
Operating Temperature Range
Military, DAC-8800BR ••••••••••••••••••••••••••••••• -55·C to + 125·C
Extended Industrial, DAC-8800FR,FP,FS ••• -40·C to +85·C
Maximum Junction Temperature (Tj Max) ••••••••••••••••••• + 150·C
Storage Temperature •••••••••••••••••••••••••••••••••••• -65·Cto +150·C
Lead Temperature (Soldering, 10 sec) ........................ +300·C
Package Power Dissipation ••••••.•...••••••••••••••• (Tj Max - T A)/8 jA

TABLE 1: PIN
PIN

NOTE:
1. 8 iA is specified for worst case mounting conditions, i.e., 8 iA is specified for
devica in socket lor CerDIP, and P-DIP packages; 8' A is specified for device
soldered to printed circuit board lor SO package. J
CAUTION:
1. Do not apply voltages higherthan V DOor less than V ss potential on any terminal.
2. The digital COntrol inputs are zener-protected; however, permanent damage
may occur on unprotected units from high-energy electrostatic fields. Keep
units in conductive foam at all times until ready to use.

3. Do not insert this device into powered sockets; remove power before insertion
or removal.
4. Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to device.

Function Description

MNEMONIC

DESCRIPTION

VREFL,

External DAC voltage reference input shared by DAC A, B, C, D. VREFL, determines the lowest negative DAC output voltage.
VREFL, must be equal to or more positive than V's'

2

VREFH,

External DAC voltage reference input shared by DAC A, B, C, D. VREFH, determines the highest positive DAC output voltage.

3

VOU~

DAC A Output

VourB

DACBOutput

5

VOuP

DAC C Output

6

VouTD

DACDOutput

8

Voo

Positive supply, allowable input voltage range +4.SV to +16V.

SDI

Serial Data Input

9

CLK

Serial Clock Input, poSitive edge triggered

10

CLK

Clock Enable or Serial Clock Input, negative edge triggered

II

11

GND

Ground

12

CLR

Clear Input (Active Low), Asynchronous TTL compatible input that resets all DAC registers to zero code.

13

[5

Load DAC Register Strobe. TTL compatible input that transfers data bits from serial input register into the decoded DAC register.
See Table 2.

14

V••

Negative Supply, allowable input voltage range OV to -12V.

15

VOur'=

DACEOutput

16

VouTF

DAC FOutput

17

VOUTG

DACG Output

18

VouTH

DAC H Output

19

VREFH.

External DAC voltage reference input shared by DAC E, F, G, H. VREFH. determines the highest positive DAC output voltage.

20

VREFL.

External DAC VOltage reference input shared by DAC E, F, G, H. VREFLo determines the lowest negative DAC output voltage.
VREFL. must be equal toar more pOSitive than Vss'

REV,A

SPECIAL FUNCTION VIDEO PRODUCTS 8-67

DAC-8800
SOl

elK

\J

[JACREGISTER

lOADED

+BV

Vou,
OV

____x==

DETAIL SERIAL DATA INPUT TIMING (W ..01
SOl 1
(DATA IN) 0 - - - - -.....
1

elK

CLEAR OPERATION

_1--Q-a.·

CLR

o

Lo:-----------------------~=\]~·

.OV

You,.~----------------------

~~
------sb

VOUT 0 ±112 lSB ERRCR BAND

=-I-=:t;;;::=---

OY

±112 LIB ERROR BAND

elK INPUT (PIN 10) nMING IS EXACTLY INVERTED FRCM elK INPUT (PIN Q)

FIGURE 1:

Timing Diagrams

TABLE 2: Serial Input Decode Table

LSB

Ao

LSB
Do

0
0

0

0

0
0

1

0
0

0
0

0
0

1
0
0

0

0
0

0
0

0

0

0

0

DAC OUTPUT VOLTAGE
(K = VREFH - VREFLI

0
0
0

VREFL

0

(11256) x K + VRE~

0

0

(1271256) x K + VREFL
(1281256) x K + VREFL
(1291256) x K + VREFL

0
0

0
0

1
0

0
1
0

DACUPDATED
DACA
DACB
DACC
DACD
DACE
DACF
DACG
DACH

(2551256) x K + VREFL

TABLE 3: Logic Control Input Truth Table
elK

m

i

l

Shift Data

H

J.

Shift Data

l

X

No Operation

X

H

No Operation

INPUT SHIFT REGISTER OPERATON

8-68 SPECIAL FUNCTION VIDEO PRODUCTS

REV. A

OAC-88DD
TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT vs
TEMPERATURE

TOTAL UNADJUSTED ERROR
vs DIGITAL INPUT CODE

'.0 ,--,--,--,--,--,--,--,---,
YOD '" +t2Y

.1/2

1--t--t---t--t--t---t--t---1

V rNH ,,2.4V

!

r--f- DACsA, B. C, 0

SUPERIMPOSED

V~~~H, " +5V VIIHL, "CN

-f---

§

~

+112

1--t--t--t--t--t--+--+--1

g;

-+---1-+---1-+---1

1.6

ffi
-1i2

POWER SUPPLY REJECTION
RATIO vs FREQUENCY
120

ll00
0

~4--+--+-~--j--+-~-4

~~

Z

T A ", +25°C
VSS" -5V

Yco " +12V

t-...

80

r-~::t=:t==~=F==P==F~

0.8 ~-+-+--+-+--+-+--+--1

'\'

u

~

~

~-+-+--+-+--+-+--+--1

60

"

~

~

It

li

IJ. Voo=lVpp

r--.

g

1.2

0.4

t---

4'

ffi

~

~

20

o~~-~~-~~-~~~
_
_
_
0
~
~
n
_
_
128

194

256

lDO

TEMPERATURE (OC)

DIGITAL-INPUT CODE (DECIMAL)

EXPANDED OAC OUTPUT
SETTLING TIME POSITIVE
TRANSITION

DAC OUTPUT SETTLING TIME
POSITIVE & NEGATIVE
TRANSITIONS

UPPER TRACE: ILD INPUT (SV/DlY)
LOWER TRACE: VOUTA (2V/DIV)
CONDITIONS:
V DD = .12V, VREFH, = +SV,
VREFL, = av, Vss OV,
RL = 1 MQ, C L = 3,4pF

=

DAC OUTPUT CHANNEL-TOCHANNEL CROSSTALK BOTH
TRANSITIONS

1k

10k

tOOk

FREQUENCY (Hz)

EXPANDED DAC OUTPUT
SETTLING TIME NEGATIVE
TRANSITION

UPPER TRACE: ILD INPUT (SV/DIV)
LOWER TRACE: VOUTA (lV/DIY)
CONDITIONS:
V DD .12V, VREFH, +SV,
V REF L 1 = OV, Vss = OV,
RL lMQ, C L 3.4pF

UPPER TRACE: 'ILO INPUT (SV/Dly)
•
LOWER TRACE: VouTA (lV/DIY)
CONDITIONS:
V DD = +12V, VREFH, = +5V,
VREFL, OV, Vss OV,
R L lMQ, C L 3.4pF

EXPANDED DAC OUTPUT
CHANNEL-TO-CHANNEL CROSSTALK NEGATIVE TRANSITION
2V
- JOOtv
~ -

EXPANDED DAC OUTPUT
CHANNEL-TO-CHANNEL CROSSTALK POSITIVE TRANSITION

=
=

I

=

=

=

=

=

=

I

I

UPPER TRACE: VOUTA 0 TO .SV CHANGE
LOWER TRACE: VOUTB (lV/DIY)
CONDITIONS:
V DD .12V, VREFH, .SV,
VREFl, = av, Vss = av,
RL = 1MQ, C L = 3,4pF

=

REV. A

=

UPPER TRACE: V OUT A +SV TO OV CHANGE
LOWER TRACE: VouTB (100mV/DIy)
CONDITIONS:
V DD .12V, VREFH, +SV,
VREFL, = av, Vss = OV,
RL = 1 MQ, C L = 3.4pF

=

=

UPPER lRACE: VOUTA OTO +5V CHANGE
LOWER TRACE: VouTB (100mV/DIY)
CONDITIONS:
V OD = +12V, VREFH, = +5V,
V REF L , = OV, Vss = OV,
RL = lMQ, C L = 3.4pF

SPECIAL FUNCTION VIDEO PRODUCTS 8-69

•

DAC-8800
CIRCUIT OPERATION
The DAC-8800 provides a programmable voltage output adjustment capability. Changing the programmed output voltage of
each DAC is accomplished by clocking in an II-bit serial data
word into pin SOl (Serial Data Input). The format of this data
word is three address bits, MSBlirst, lollowed by 8 data bits,
MSB first. Table 2 provides the serial input decode table for data
loading. DAC outputs can be changed one at a time in random
sequence. The fast serial-data clocking of 6.6MHz makes it
possible to load all 8 DACs in as little time as 14 microseconds.
The exact timing requirements are provided in Figure 1.
A clear (CUi) input pin allows the circuit to be powered-up in the
all zero state or a system reset pulse connected to CLR can
asynchronously clear all data registers.

where 0 is a whole number binary digital input word loaded into
the DAC register. For example, when V R.E~ - +5V and VR~~­
OV unipolar output operation results With the following bmary
digital inputs:

255

4.98V

Full-Scale

128

2.50V

Half-Scale

0

O.02V

1 LSB

O.OOV

Zero-ScaJe also generated
When
Input Activated

ern

Bipolar output operation is achieved when V REFH = +2.5V and
VREFL. -2.5V, also note Vss must be equalto or more negative
than VREFL. Vss = ~V is a good choice for this example. The
following example lists the actual bipolar output voltages produced by the binary digital input which would now be considered
offset-binary coded:

-Flour
A

CONSTANT
INDEPENDENT

OF DIGITAL
INPUT CODE

DAC
AEGI~R

A

VREFLo---_ _- - - - - > / W ' - '

FIGURE 2: DAC-8800 TrimDAC™ Equivalent DAC Circuit
The output voltage range is determined by the external input
voltages applied to VREFH and V REFL. See Figure 2 for a simplified equivalent DAC circuit. II a negative supply is used on Vss
then VREFL may be set negative resulting in a programmable
bipolar output voltage swing.

255

2.48V

Positive FUll-Scale

129

O.02V

Positive 1 LSB

128

O.OOV

Bipolar Zero-Scale

127

-{).02V

Negative 1 LSB

0

.c.2.50V

Negative Full-Scale

REFERENCE INPUTS (VREFH,. VREFL,. VREFH2• VRE~2)
The external voltages connected to the VREF input pins determine the programmable output voltage ranges ofthetwo sets 01
lour DACs in the DAC-8800. Specifically, VREFH, and VREFL,
are connected to DACs, A, B, C, 0, and VRE II2 and VilEFL2
are connected to DACs E, F, G, H.
Inspection of the DAC-8800 equivalent DAC circuit (Figure 2)
shows the external VREFH and VREFL inputs connected to the
internal DAC switches. During updating, the DAC switches produce transient current flowing from V REFH to VREFL. It is recommended to place 0.01 J1F bypass capacitors across the VREFH
and V REFL inputs to minimize the voltage transients.

The actual output voltage, VOUT ' depends on VRlill and VREFL
as follows:
VouT(D) = 0 x (VREFH - VREF L)/256 + VREFL

8-70 SPECIAL FUNCTION VIDEO PRODUCTS

REV. A

DAC-8800
A wide range of external voltage references can be used subject
to the reference input voltage range boundary conditions. First
VREFH should always be more positive than VREFL. DC voltages
are recommended. VREFl can be equal to the negative power
supply Vss. This feature results in single supply operation when
Vss is at ground. VREFH should not be closer than four volts to
Vee. This is due to the DAC-8800 NMOS only DAC switches
which will no longer operate properly if VREFH is closer to Vee
than four volts. Total unadjusted error degrades when (VeeVREFH) is less than four volts as shown in Figure 3.

TA. +25"C

Vss·ov

~

The channel-to-channel crosstalk is due to the 0.15pF inter-pin
package capacitance. A FET probe with 3.4pF input capacitance was used to measure the DAC output channel-to-channel
crosstalk characteristics shown. In voltage transient sensitive
applications, minimization of crosstalk can be accomplished by
placing ground traces between adjacent DAC output pins. DAC
output bypass capacitors will also minimize voltage transients.

r-~

.,..

~ r-K•

... o~

V DCI - y .....H (VOLTS)

"

II

FIGURE 3: Effect on TUE Operating Beyond
(VDD - VRE,fIJ > 4V Limit
RECOMMENDED OPERATING POWER SUPPLY
VOLTAGE RANGES
Akhough the DAC-8800 is thoroughly specified for operation
with Vpe =+12Vand Vss =OVor-5V, it will still function with the
follOWing recommended boundary conditions:
• (Vee -V ss)< 18V
• 4.5V < Vee < 16V
• OV > Vss > -12V
In all cases the reference voltage boundary conditions still apply. The boundary conditions described here make it possible
to use DAC-8800 with a wide variety of readily available supply
voltages. Some choices include, but are not limited to:
Vee/Vss = + 15VtoV; + 12V/OV; + 12V/-5V; +5V/-5V; +5V/-12V

REV. A

The nominal DAC output capacitance measures three picofarads and has little variation with temperature.
One aspect of the nominal 12.5kO DAC output resistance is
channel-to-channel crosstalk. Under a worst case condition of
adjacent DAC outputs when DAC A makes a five volt output
voltage change DAC B exhibits a300mVvoitage transient. See
photograph in typical characteristics section of data sheet.

TOTAL UNADJUSTED ERROR
vs (VDe - VREFH)

-

DAC OUTPUTS (VOUT A, B, C, D, E, F, G, H)
The eight D/A converter voltage outputs have a constant output
resistance independent of digital input code. The distribution of
ROUT from DAC to DAC within the DAC-8800 typically matches
by 0.5%. Device to device ROUT matching is process-lot to process-lot dependent having a ±20% variation. The change in
ROUT with temperature is very small as a result of PMI's low
temperature coefficient SiCr thin-film resistor process.

Output settling time has adominant pole response as the photograph in the typical characteristics section shows. The output
settling time characteristic consists of an 80 nanosecond propagation delay followed by a single RC decay waveform determined by the nominal ROUT of 12.5kQ times COUT plus CLoAe
which includes the oscilloscope probe.
The digital feedthrough from the serial data inputs (ClK, and
501) to the DAC outputs measures less than 20mV.

DIGITAL INTERFACING
The DAC-8800 contains a standard three-wire serial input control interface. The three inputs are clock (ClK), load (LD), and
serial data input (501). A ClK input pin is available for negative
edge triggered data loading. The edge sensitive clock input pin
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic fan"lilies work well. If
mechanical switches are used for product evaluation they
should be debounced by a flip-flop or other suitable means.
The logic control input truth table (Table 3) defines operation of
the serial data input register.
The ClK input is used to place data in the serial data input register. The unused clock input (ClK or ClK) should be tied to the
active state (ClK = 1 or ClK - 0 for active). The load strobe ([5)
which must follow the eleventh active ClK edge transfers the

SPECIAL FUNCTION VIOEO PRODUCTS 8-71

•

DAC..8800
DA~

SERIAL DATA

~~

CLOCK~~
n

n

LOADSTHOBE

Lr

8

SD!

•

CLK

13

,.

~

Lii
CLi

Yoo

LE. CUi
GND

~
FIGURE 4: Three-Wire Serial Interface Connections

SOl

..:~
CLOCK~~

nL..-___

ClK

Lii

CAc-a800

'"

~ClK
cs,
DECODE

cs.

~CLi

lOADSTROSE
SD!

ClK

DAc.aaoo
«I

Lii

FIGURE Sa: Decoding Multiple DAC-8800s
data from the serial data input register to the OAC register decOded from the first three address bits clocked into the input register. Any extra ClK edges after the eleventh edge looses the
first bits shifted in. See Table 2 for a complete description. See
Figure 4 for an example using the ClK input pin to clock data
into the SOl.

8-72 SPECIAL FUNCTION VIDEO PRODUCTS

The unused clock input of Fig ure 4 can be used to provide a chip
select (CS) feature for applications using more than one OAC8800. Figure Sa shows the proper connection and timing of the
ClK inputs which assures that the CD< acting as a chip select
(CS) is taken to the active low state selecting the desired DAC8800.

REV. A

OAC-8800
Another method of decoding multiple DAC-8800s is shown in
Figure Sb. Here all the DAC serial input registers receive the
same input data; however, only one of DAC's LD input is activated to transfer its serial input register contents into the destination DAC register. In this circuit the LD timing generated by
the address decoder should follow the DAC-8800 standard timing requirements. Note the address decoder should not be activated by its WR input while the coded address inputs are changing.

C~CKo-------------+---~

DATA o>-------------+----t-~

CODED
ADDRESS

ADDRESS
DECODE

Va AUDIO

OUTPUT

.~]SIj
_15[]SJ
-1.2

0

+1.2

Vc(VOLTS)

EN

FIGURE 6: Digitally Programmable Amplifier
BUFFERING THE DAC-8800 OUTPUT

Wiio----'

FIGURE Sb: Decoding Multiple DAC-8800s Using the LD
Input Pin

APPLICATIONS
DIGITALLY PROGRAMMABLE AUDIO AMPLIFIER

The DAC-8800 is well suited to digitally control the gain or attenuation settings of eight voltage controlled amplifiers (VCAs).
In professional audio mixing consoles, music synthesizers and
other audio processor's VCAs, such as the SSM-2014, adjust
audio channel gain and attenuation from front panel potentiometers. The VCA provides a clean gain transition control of
audio level when the slew rate of the analog input control voltage (Vc) is properly chosen. Taking advantage of the 12.SkO
nominal output resistance of the DAC-8800 it is very easy to
control the slew rate of VOUT by appropriate selection of COUTo
Figure 6 shows one channel of a digitally programmable audio
amplifier.
The reference high (V REFH) and reference low (V REFL) input
voltages of the DAC-8800 provide a digitally programmable
output voltage of -1 .2V to +1.2V which is connected to the control voltage (Vc) input terminal of the SSM-2014 VCA. The gain
ofthe SSM-2014 is guaranteed to change from -1SdB to + 1SdB
for 1.2 to -1.2V input Vc voltage. A COUT of 0.1 J.lF provides a
control voltage transition time of 1.2ms which generates a click
free change in audio channel gain.

REV. A

External op amps can be used to buffer the output of the DAC8800's nominal 12.SkO output resistance. In Figure 7 a variety
of possibilities are shown. The quad low power OP-420 is used
as a simple buffer to reduce the output resistance of DAC A. The
OP-420 was chosen for its wide operating supply range, both
single and dual, low power consumption, and low cost.
The next two DACs, Band C, are configured in a summing arrangement where DAC C provides the course output voltage
setting and DAC B can be used for fine adjustment. The inser- •
tion of R1 in series with DAC B attenuates its contribution to the
:
voltage sum node at the DAC C output.
DAC D in Figure 7 is in a noninverting gain of two configuration
increasing the available output swing to 10V. Appropriate
choice of external op amp gain can achieve output voltage
swings beyond the range ofthe DAC-8800 ifthe external op amp
power supply voltages are sufficiently high. In addition, the op
amp feedback network termination could be a bias voltage
which would provide an offset to the output signal swing.
SETTING COMPARATOR TRIP POINTS

The DAC-8800 is ideal to provide setpOints for voltage input
comparators. In Figure 8 the very low power CMP-404 detects
whether input voltage (VIN) is higher or lower than the programmed limit values providing TIL compatible output signals.
The compactness of the DAC-8800 makes it ideal for high density testing applications found in pin head electronics.

SPECIAL FUNCTION VIDEO PRODUCTS 8-73

OAe-aaoo
.'IV
.'IV

v...
V~o-"""_-+.--0 OV TC IV

v.

"our

v.
v.

Vour B

4
OP-GO

II,

"our

v.
v.

V....C

SUMMER CIRCUIT WITH
FINE TRIM ADJUSTMENT

I

> .......,--0 OV TC IV
DAC-_

v.
v.

"

"our
INCREASE OUTPUT SWING

>..-.'--0

V..

11

OV TC 'OV

GND

'::"

DIGITAL INTERFACING OMITTED FOR CLARIlY.
II, ,OCIkO, Ro= '1IkO

=

FIGURE 7: Buffering the DAC-8800 Output

.'IV

Y,N

.'IV

VDD
VIE~
DACA

>--1-....-0 HIGH LIMIT

VIEFL,
OV

DAC-88OCI

....-O LOW LIMIT

~--1iDAC.

DACC

>-+---<'--0 VARIABLE LIMIT

FIGURE 8: Setting the Comparator Trip Points

8-74 SPECIAL FUNCTION VIDEO PRODUCTS

REV. A

DAC-8800
CURRENT SUMMING OUTPUT OPERATIONS
Since the DAC-8800 has a constant output resistance regardless of digital input code, it can be used in a current summing
application. Figure 9 depicts the DAC output connected to the
inverting input of an OP-20 low power consumption op amp. An
external feedback resistor sets the output signal swing according to the formula given. The gain accuracy of this circu~ has a
wide variation due to the 30% output tolerance of the DAC-8800
ROUT specification. A second DAC in the DAC-8800 could be
used with an external resistor summed into the OP-20 current
summing node to digitally adjust the full-scale swing.

.'2V

VO"

~ (~

X10V}-SV

WHERE 0 = OECIMAL CODE
INPut BETWEEN 0 AND 255

-sv

FIGURE 9: Current Summing Output Operation
OPTICALLY ISOLATED TWO-WIRE INTERFACE
Two-wire signal interfacing is often found in process control
applications where electrical isolation of hazardous environments and minimization of wiring is necessary. Isolation transformers or optocouplers provide the high voltage isolation.
Normally the DAC-8800 requires a three-wire interface to update the DAC contents. One technique which translates a twowire interface into the three-wire signal control required by the

DAC-8800 is shown in Figure 10. A single package CMOS-logic
dual-retriggerable one-shot MC14538 provides the solution. At
rest the optocouplers are both OFF allowing the pull-up resistors to sit at logic high. No undefined transients should occuron
the control input line Vc to avoid inadvertently clocking incorrect
data into the DAC-8800 serial input register. When it is time to
update one of the DAC-8800 DACs, the CONTROL line will go

l......-- HIGH VOLTAGE
I

ISOLATION

3'~ f r····-,~
I
I

.".

I

VOUT

3·WIRE
INTERFACE

SIGNAL

0;:,
1

il;(LD)

U
U

0

r-~

FIGURE 10: Iso/ated Two-Wire Signa/Interface for Seria/lnput DAC

REV. A

SPECIAL FUNCTION VIDEO PRODUCTS 8-75

•

OAC-88DD
low, triggering the first one-shot (Q1)' At this time valid data
should also be applied to the DATA input optocoupler. Sufficient
time must be allowed before the control (V c) input returns to
logic high to make sure the DAC-8800 input data is stabilized.
When Vc changes to logic high, the first DATA bit shifts into the
DAC-8800 serial data input register. The time constant of the
first one-shot established by R1 and C1 should be at least twice
as long as the basic CONTROL input clock period. This will
output from returning to the high state. The next
prevent the
control input negative edge retriggers the first one-shot and sets
up the DAC-8800 clock forthe next DATA bit. All eleven positive
clock edges will fill the DAC-8800serial input register and each
retrigger the first one shot. As soon as
negative clock edge
the CONi' ROL line returns to the passive state, the first one shot
will time out, triggering the second one shot (0;), which will producethe required load LD pulse for the DAC-8800totransfer its
serial input register contents to the internal DAC register completing the DAC update. The R1 C1 and R.2C~ times need to be
designed based on the system's CONTROL-input clock rate.
The optocoupler clocking rate must also be considered in setting the system clock rate.

BURN-IN CIRCUIT

••ovo--_--.....- ;

a;

will

8-76 SPECIAL FUNCTION VIDEO PRODUCTS

..11V

.0...

-IV

lID

• S ..
9 eLK

D,

"'"

10

ClK

OND 11

REV. A

8-Bit, Octal, 4-Quadrant
Multiplying, CMOS TrimDAC
DAC-8840 I

~ANALOG

WDEVICES
FEATURES
Replaces 8 Potentiometers
1 MHz 4-Quadrant Multiplying Bandwidth
No Signal Inversion
Low Zero Output Error
Eight Individual Channels
3-Wire Serial Input
500 kHz Update Data Loading Rate
±3 Volt Output Swing
Midscale Preset. Zero Volts Out
APPLICATIONS
Automatic Adjustment
Trimmer Replacement
Dynamic Level Adjustment
Special Waveform Generation and Modulation

FUNCTIONAL BLOCK DIAGRAM

DECODED
ADDRESS

LOAD

SDI

GND

GENERAL DESCRIPTION
The DAC-8840 provides eight general purpose digitally controlled voltage adjustment devices. The TrimDAC" capability
allows replacement of the mechanical trimmer function in new
designs. The DAC-8840 is ideal for ac or dc gain control of up
to I MHz bandwidth signals. The 4-quadrant multiplying capability is useful for signal inversion and modulation often found
in video convergence circuitry.

.-------OV'N A

vss

SDO PRESET

The DAC-8840 consumes only 190 mW from ±5 V power supplies. For single 5 V supply applications consult the DAC-8841.
The DAC-8840 is available in 24-pin plastic DIP, cerdip, and
SOIC-24 packages. A separate MIL-STD/883 data sheet for
-55°C to + 125°C operation is available on request.

Internally the DAC-8840 contains eight voltage output CMOS
digital-to-analog converters, each with separate reference inputs.
Each DAC has its own DAC register which holds its output
state. These DAC registers are updated from an internal serialto-parallel shift register which is loaded from a standard 3-wire
serial input digital interface. Twelve data bits make up the data
word clocked into the serial input register. This data word is
decoded where the first 4 bits determine the address of the DAC
register to be loaded with the last 8 bits of data. A serial data
output pin at the opposite end of the serial register allows simple daisy-chaining in multiple DAC applications without additional external decoding logic.

II

TrimDAC is a trademark of Analog Devices, Inc.

REV. A

SPECIAL FUNCTION VIDEO PRODUCTS 8-77

= +5 V. Vss = -5 V. ~II V1NX = +3 V. TA = -4O"C to +85°C apply
•PECIFICATIONS
DAC - 8840 - S
" I
for DAC-8840F. unless otherwise noted)
(VDD

Min

Typ

Symbol

Conditions

STATIC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Output Offset
Output Offset Drift

N
INL
DNL
VBZE
TCVBz

All Specifications Apply for DACs A, B, C, D, E, F, G, H
8
±1I4
All Devices Monotonic
PR = 0, Sets D = 80H
3
PR = 0, Sets D = 80H
10

REFERENCE INPUTS
Voltage Range
Input Resistance
Input Capacitance

IVR
RIN
CIN

Applies to All Inputs VINX
Note I
D = 2BH, Code Dependent
D = FFH, Code Dependent

±3
3

OVR
loUT
CL

Applies to All Outputs VOUTX
RL = 10 kO
aVOUT 

Figure 7. VOUT Slew Rate vs.
Temperature

1
INPUT C dB
OUTPUT D

i

l-+tttttt+-+t+t#ll;o:-+-t+ttltf-'N-tttttI -10 'll,
,-~ijjjtt-+t+l'l~

",
-2

'/

-4
-4

.... '7 ~ .......

V

"'

V

.,

0= FFH

O=COH

o =60H

r-.

O=40H

r.....

o =DOH

V IN - Volts

Figure 25. DAC Plus Amplifier Combine to Produce Four
Quadrant Multiplication

In order to simplify use with a controlling microprocessor, a
simple layout-efficient three-wire serial-data-interface was thosen. This interface can be easily adapted to almost aJI microcomputer and microprocessor systems. A clock (CLK), serial data
input (SOl) and a: load (LD) strobe pin make up the three-wire
interface. The 12-bit input data word used to change the value
of the internal DAC registers contains a 4-bit address and 8 bits
of data. Using this word combination any DAC register can be
changed at a given time without disturbing the other channels.
A serial data output SDO pin simplifies cascading multiple
DAC-8840s without adding address decoder chips to the system.

= 3 V)

Zero Output

Full Scale (FS)

Notice that the output polarity is the same as the input polarity
when the DAC register is loaded With 255 (in binary = aJI
ones). Also note that the output does not exactly equal the input
voltage. This is a result of the R-2R ladder DAC architecture
chosen. When the DAC register is loaded With 0, the output
polarity is inverted and exactly equals the magnitude of the
input voltage V,N. The actual voltage measured when setting up
a DAC in this example will vary within .the ± I LSB linearity
error specification of the DAC-8840. The calculated voltage
error would be ±0.023 V (= ±3 V/128).

If VIN is an ac signal such as a sine wave then we
tion 2 to describe circuit performance.

-2

Your =V1N (O/128-1), WHERE 0 =OTO 255

REV. A

(YIN

can. use equa-

V OUT (I,D) = (D1l28 - I) x A sin (we)

(2)

where w = 2 "f, A = sine wave amplitude, and D = decimal
input code.
This transfer characteristic Equation 2 lends itself to amplitude
and phase control of the incoming signal V'N~ When the DAC is
loaded with aJI zeros, the output sine wave is shifted by 180·
With respect to the input sine wave. This powerful multiplying.
capability can be used for a Wide variety of modulation, waveform adjustment and amplitude control..

SPECIAL FUNCTION VIDEO PRODUCTS 8-85

8

DAC-8840
REfERENCE INPUTS (VINA, B, C, D, E, F, G, H)
The eight independent VIN in~ts have a code dependent input
resistance whose worst case minimum value 3 kG is specified in

"Reference Input Current versus Code" shown in the typical

word. This needs to be done before the thirteenth positive clock
edge. The timing requirements are provided in the electrical
cbaracteristic table and in the Figure 1 timing diagram. After
twelve clock edges, data initia1ly loaded into the shift register at
SOl appears at the shift register output SOO.

performance cbaracteristics section displays the incremental
changes. Use a suitable amplifier capable of driving this input
resistance in parallel with·the specifIed 19 pF typical input
capacitance. These reference inputs are designed to receive not
only dc, but ac input voltages. This results from the incorporation of a true bilateral analog switcb in the DAC design (see
Figure 24). The DAC switcb operation has been designed to
operate in the break-before-make format to minimize traD,Sient
loading of the inputs. The reference input voltage range can
operate from near the negative supply (Vss) to within 2 V of the
positive supply (VDD)' That is, the operating input voltage
range is:

There is some digital feedthrough from the digital input pins.
Operating the clock only when the DAC registers require updating minimizes the effect of the digital feedthrough on the analog
signa1 cbannels. Measurements of DAC switcb feedthrough
shown in the electrical cbaracteristics table were accomplished
by grounding the VINX inputs and cycling the data codes
between all zeros and all ones. Under this condition 6 nVs of
feedthrough was measured on the outpUt of the switcbed DAC
cbannel. An adjacent cbannel measured less than 1 nVs of digital crosstalk. The digital feedthrough photographs shown in the
typical performance characteristics section displays these
cbaracteristics (Figures 14, IS, and 16).

the electrical characteristics table. The graph (Figure 5) titled

Vss + 0.5 V < VINK < (VDD-2 V)

(3)

DAC OUTPUTS (VourA, B, C, D, E, F, G, H)
The eight D/A converter outputs are fully buffered by the DAC8840's internal amplifier. This amplifier is designed to drive up
to I kO loads in parallel with 100 pF. However, in order to
minimize internal device power consumption, it is recommended
whenever possible to use 1arger values of load resistance. The
amplifier output stage can handle shorts to GND; however, care
should be taken to avoid continuous short circuit operation.
The low output 'impedance of the buffers minimizes crosstalk
between analog input cbanne1s. A graph (Figure 9) of analog
crosstalk between cbannels is provided in the typical performance cbaracteristics section. At I MHz, 72 dB of channel-tocbannel isolation exists. It is recommended to use good circuit
layout practice sucb as guard traces between analog channels
and power supply bypass capacitors. A 0.01 IIoF ceramic in parallel with a 1-10 IIoF tantulum capacitor provides a good power
supply bypass for most frequencies encountered.

Figure 26 shows a three-wire interface for a single DAC-884O
that easily cascades for multiple packages:
~C

PAO DATA
PAl ",C;;.;;L;.;;.OC;:;.;K.;......,
PA2 LD

r---~S~DI~O~AC~A~--~VmrrA
CLK

DAC-8840'1
LD
L..,..__-=SDO:r=-...:D:::;A;::C;.:.H:.J'--... VOUT H

SDI

DACA

CLK

DAC-8840ft
LD
SDO DACH

DIGITAL INTERFACING
The four digital input pins (CLK, SOl, LD, PR) of the DAC8840 were designed for TTL and 5 V CMOS logic compatibility. The SDO output pin offers good fanout in CMOS logic
applications and can easily drive several DAC-8840s.
The Logic Control input Truth Table II describes how to shift
data into the internal 12-bit serial input register. Note that the
CLK is a positive edge' sensitive input. If mechanical switcbes
are used for breadboarding product evaluation, they should be
debounced by a flipflop or other suitable means.
The required address plus data input format is defmed in the
serial input decode Table I. Note there are 8 address states that
result in no operation (NOP) or activity in the DAC-884O when
the active high load strobe LD is activated. This NOP can be
used in cascaded applications where only one DAC out of several packages needs updating. The packages not requiring data
cbanges would receive the NOP address, that is, all zeros. It
takes 12 clocks on the CLK pin to fully load the serial input
shift register. Data on the SOl input pin is subject to the timing
diagram (Figure 1) data serup and data hold time requirements.
After the twelfth clock pulse the processor needs to activate the
LD strobe to have the DAC-884O decode the serial register contents and update the target DAC register with the 8-bit data

lHJ6 SPECIAL FUNCTION VIDEO PRODUCTS

SOl

DACA

CLK

DAC-8840'3
LD
SDO DACH

Figure 26. Three-Wire Interface Updates Multiple
DAC-B840s

REV. A

8-Bit Octal, 2-Quadrant
Multiplying, CMOS TrimDAC
OAC-8841 I

r.ANALOG
WDEVICES
FEATURES
Repl_ 8 Potentiometers
Opal1lt.. From Single +5 V Suppiy
, MHz 2.Quadrant Multiplying Bandwidth
No Signal Inversion
Eight Individual Channels
3-W1ra Sariallnput
500 kHz Updete Dete Loading Rete
+3 Volt Output Swing
MIdIlClIe Preset
Low 95 mW Power Dissipation
APPUCATIONS
Trimmer Replacement
Dynamic Lavel Adjustment
Speciel Waveform Generation and Modulation
Programmable Gain Amplifiers

GENERAL DESCRIPTION
The DAC-8841 provides eight general purpose digitally controlled
voltage adjustment devices. The TrimDAC" capability replaces
the mechanical trimmer function in new designs. It is ideal for
Be or de pin control of up to 1 MHz bandwidth sigDals.
Intemally the DAC-8841 contains eight voltage output CMOS
digital-to-aoalog conveners, each with separate reference inputs.
Each DAC has its own DAC register which holds its output
state. These DAC registers are updated from an internal serialto-parallel shift register which is loaded from a standard 3-wire
serial input digital interface. Twelve data bits make up the data
word clocked into the serial input register. This data word is
decoded where the first 4 bits determine the address of the DAC
register to be loaded with the last 8 bits of data. A serial data
outpUt pin at the opposite end of the serial register allows simple daisy-chaining in multiple DAC applications without additional external decoding logic.

FUNCTIONAL BLOCK DIAGRAM

LOAO

SOl

GND

SDD PRESET

The DAC-8841 consumes only 95 mW from a +5 V power supply. For dual polsrity applications see the DAC-8840 which pr0vides full 4-quadrant-multiplying ± 3 V sigDal capability while
operating from ±5 V power supplies.
The DAC-8841 is available in 24-pin plastic DIP, cerdip, and
SOIC-24 packages. For MIL-STD/883 applications, contact
ADI sales for the DAC-8841BW/883 data sheet which specifies
operation over -55"C to + 125"C.

•

TrimDAC is • trademark of ADalog Devices, Ioc.

REV. A

SPECIAL FUNCTION VIDEO PRODUCTS 8-87

DAC-8841-SPECIFICATIONS
VDD = +5 V. All VI.x. = + 1.5 V. VREFL = DV. TA = -411"C to +85"1: apply for D~C" .
ELE'CTR' ICAL C' HARA'CTERISTICS
, 8841 F. unless otherwise noted.
,
Parameter

Symbol

STATIC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Half-Scale Output Voltage
Zero-Scale Output Voltage
Output Voltage Drift
SIGNAL INPUTS
Input Voltage Range
Input Resistance
Input Capacitance
REF Low Resistance
REF Low Capacitance
DACOUTPUTS
Voltage Range
Output Current
Capacitive Load
DYNAMIC PERFORMANCE
Multiplying Gain Bandwidth
Slew Rate

Tots! Harmonic Distortion
Spot Noise Voltage
Output Settling Time
Channel to Channel Crosstslk
Digital Feedthrough

DIGITAL OUTPUT
Logic High
Logic Low
TIMING SPECIFICATIONS
Input Clock Pulse Width
Dats Setup Time
Data Hold Time
CLK to SOO Propagation Delay
DAC Register Load Pulse Width
Preset Pulse Width
Qock Edge to Load Time
Load Edge to Next Clock Edge

Min

Typ

Mas

Units

:t1.5
:tl
1.475 1.500 1.525
20
100
10

Bits
LSB
LSB
V
mV
IJ-vrc

All Specifications Apply for DACs A, B, C,
D,E,F,G,H
N
INL
DNL
VHS
Vzs
TCVHs

S
Note I
All Devices Monotonic, Note I
PR = 0 V, Sets D = S~
Digits! Code = OOH
PR = 0 V,Sets D = S~

:t112

Applies to All Inputs VINX or VREpL
IVR
RIN
CIN
RREPL
~pL

D = 55H; Code Dependent
Code Dependent
D = ABH; Code Dependent
Code Dependent

OVR
loUT
CL

Applies to All Outputs VOUTX
RL = 10 kO
AVOUT < 25 mY, VINX = 1.375'.', PR = 0 V
No Oscillation

GBW
+SR
-SR
THD
eN
ts

Cr

Q

POWER SUPPLIES
Positive Supply Current
100
Power Dissipation
P DlSS
DC Power Supply Rejection Ratio PSRR
Power Supply Range
PSR
DIGITAL INPUTS
Logic High
Logic Low
Input Current
Input Capacitance
Input Coding

Conditions

Applies to All DACs
VINX = 100 mV p-p + 1.0 V de
Measured 10% to 90%
AVOUTX = +3 V
AVOUTX = -3 V
VINX = I Vp-p + 1.0 V dc, D = FFH, f = I kHz,
fLP = SO kHz
f=lkHz
:t I LSB Error Band, 8'0 to 255 10
Measured Between Adjacent Channels, f = 100 kHz
VREpL = +1.5 V, D = 0 to FFH

0
4
0.3

0
:t5

30
250
3

7
200

V
mA
pF

2.5

MHz

1.3

4.0
2.5
0.01

V/IJ-S

1.3

60

0.17
3.5
70
6
19
95

4.75

5.00

V/IJ-s
%

6

26
130
0.01
5,25

2.4,

VIH
VIL
IL
<:XL

V
kO
pF
kO
pF

I

PR= OV
PR= OV
Voo

1.5
10
19
0.75
190

O.S
:t10
S

IJ-V/v'Hz
IJ-S
dB
nVs
mA
mW

%1%
V
V
V

iJ.A
pF

Binary
,VOH
VOL

IOH = -0.4mA
IOL = 1.6 mA

tcH,tcL
tos
tOH
tpo
t LO
tPR
tcKLO
tLOCK

3.5
0.4
SO
40
20
120
70
50
30
60

V
V
ns
ns
ns
ns
ns
ns
DS

ns

NOTE
'INL and DNL tests do not include operation at cod.. 0 tbru 7 due to zero-teale outpUt voltage. For bias voltagea above 100 mV on VRE,.L. INL and DNL are
maintained over all codea.
Specifications subject to cban&e without notice.

8-88 SPECIAL FUNCTION VIDEO PRODUCTS

REV. A

DAC-8841
WAFER TEST LIMITS:

VDD

= +5 V, All V1NX = +1.5 V, VREFL = 0 V, TA = 25°C, unless otherwise noted.

Parameter

Symbol

Conditions

DAC-8841GBC
Limits

Units

Integral Nonlinearity

INL

Note 1

±1.5

LSB max

Differential Nonlinearity

DNL

All Devices Monotonic, Note 1

±1

LSBmax

Half-Scale Output Voltage

VHS

PR = 0 V, Sets D = 80H

1.475/1.525

V minimax

Input Resistance (VINX)
REF Low Resistance

RIN

D

= 55 H; Code Dependent
= AB H; Code Dependent
RL = 10 kG

4

kG min

D

0.3

kG min

3

V min

±5

rnA min

1.3
1.3
26

V/I1S min
V/I1S min
rnA max

DAC Output Voltage Range

RREFL
OVR

DAC Output Current

lOUT

Slew Rate
Positive
Negative
Positive Supply Current

SR+
SR100

AVOUT < 25 mV
Measured 10% to 90%
AVOUTX = +3 V
AVOUTX = -3 V
PR= OV

DC Power Supply Rejection Ratio

PSRR

PR

0.01

%/%max

Logic Input High

VIH

2.4

V min

Logic Input Low

VIL

0.8

V max

Logic Input Current
Logic Output High

IL
VOH

IOH = -0.4 rnA

±10
3.5

I1A max
V min

Logic Output Low

VOL

IOL

= 0 V,

=

AVoo

=

±5%

0.4

1.6 mA

V max
..

NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standsrd product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot.assembly and testing.

SDI

•

CLK

LD
VOUT

DAC REGISTER LOA~

1
0
FS

\..

a-------------------------------------------~

DETAIL SERIAL DATA INPUT nMING
(PR "1." V,N .1.5V. VR.. L OV)

=

=

SOl
(DATA IN)

1 --------~~~--------~J--~_=--~~----------------------------,.,_----------0 ________~X
... ,,______)I("1
....~Ax=O::.'=Dx=--,)I(I'_---------------------------'X"------------

los
SOO
(DATA OUT)

1
0

CLK

1
0

JIOH

I

X

~~------------------------~~

_

~ICH_I

~Ipo

r-I"

__________~~_-_-_-_._.:I.:==_I_C~__-_-_-_·1t~~~o--.:t·~~:_I-~~~_.~I_______
teL

LD

t

0

VoUT(FFH)
VOUT (08H) -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

~I\.I

I.
-

-

-

-

-

-

-

-

,.1LSBERRORBAND
-----.

PRESET nMING

h?~

~: : : : -~__--_--_-_--_--_-_--_--_...;._--~.1

LSB ERROR BAND

Figure 1. Timing Diagram

REV. A

SPECIAL FUNCTION VIDEO PROQUCTS

~89

DAC-8841
ABSOLUTE MAXIMUM RATINGS
+25'C, unless otherwise noted)
VOO to GND
. . . . . . . . . . . . . . . . . . . . . . -0.3 V, +7 V
VINXtoGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voo
VRBpL to GND .' . . . . . . . . . . . . . . . . . . . . . . . . . . Voo
VOVTX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . Voo
Short Circuit IoVTX to GND . . . . . . . . . . . . . . Continuous
Digital Input & Output Voltage to GND . . . . . . . . . . . Voo
Operating Temperature Range
Extended Industrial: DAC-884IF ....••• -4O"C to +85"C
Maximum Junction Temperature (TJ max) ..•..... + lSO"C
Storage Temperature ......••..•..•. -65"C to + 15O"C
Lead Temperature (Soldering, 10 sec) ...•.•.•••• +3OO"C
Package Power Dissipation .......... (TJ Max - T A)/alA
Thermal Resistance aJA
Cerdip ••....••....••....••••...•.•.• 64"CIW

PIN CONFIGURATIONS

(TA =

P-DIP •.••••.•...••....•••••..••...• 57"CIW
SOIC-24 •.•••••••••....••......•..... 70"C1W
DAC-8841 PIN DESCRIPTION
Pin

M ......onlc

o..rIptIon

1
2
3
4
1
8
7

V...,.c
V...,.a
V...,..A
V..B
V.,A
V.,L

DAC C Output
DAC B C)utput
DACAOutput
DAC B .......... Input
DAC A RefeN_ Input
DAC Input RefeN_ Low
...... Input. ActIve Low. All DAC Reg......

8
8
10

V ..E
V,..F
V.,...E
VovrF
V.,.,.o
VOUTH
V.,o
V.,H
LD

"

12
13
14
11
18

17
18
1.
20

21
22

23
24

PH

CLK
SDO
GND
SOl
V DD
v.,D
V..C
VourD

DICE CHARACTERISTICS
DIE SIZE 0.117 x 0.185 inch, 21,645 sq. mils
(2.9718 x 4.699 mm, 13.964 sq. mm)
The die backside is eIectric:aIly common to VDD •

=ao..

DACE ......... lnput
DAC F .......... Input
DACEOutput
DAC F Output
DACGOutput
DAC H Output
DAC G ......... Input
DACH~lnput

,1.cNId DAC Reg~ Strobe. ActIve HIgh Input
thR Tra"'" the om Bita from the Serlel
Input .......... Into the Decoded DAC
Reg...... See Teble I
....... Clock Input. PHItIve Edge TrItItIered
Serlel Dete Output. ActIve Totem Pole Output
Ground
Serlel Dm Input
PoeItIve 5 V ' - Supply
DAC D RefenInce Input
DAC C RefeNnce Input
DAC D Output

1. Vou.,c
2. Vou-rB
3.Vou.,A
4. VINB
5. VINA
8.ll-L
7.PR
8. VINE
9. VINF
10. VOUTE
11. Vou-rF
12. Vou-rG

13. VOUTH
14. VING
15. VINH
18. lD
17. elK
18. SDO
19. GND
20.SDI
21. V DD
22. VIND
23. VI"c
24.Vo~

CAUTION _______________________________________________
ESD (electrostatic discharge) sensitive device. The disital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-

static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destinstion socket before devices are inserted.

8-90 SPECIAL FUNCTION VIDEO PRODUCTS

WARNING!

l2J

~~EIJEVICf

REV. A

DAC-8841
ORDERING GUIDE
Model

Temperature Raage

DAC884IFP
DAC8841FW
DAC8841FS
DAC8841GBC

-40°C to +8S"C
-4O"C to +8S"C
-4O"C to +8S"C
-2S"C

Packaae OptiOD
Plastic DIP
Cerdip

SOIC
Dice

For dcvic:cs processed in total compliance to MIL·STO 883, contact
your local sa1es office for the OAC884IBW1883 data sheet.

Table I. Serial Input Decode Table
LAST

.. FIRST

1 LSBDO 1 DI

D2

03

04

D5

06

1 MSBD71 LSBAO 1 AI

---__~------------------------------r~
DATA

I

1 AZ

1 MSBAJ 1

/
ADDRESS
MSB
AJ

o
o
o
o
o
o
o
o
I
I

I

AZ

I

o

o
o
I
I

I
I

o
o

I

LSB
AO

DAC Updaled

o

o

I
I

o

I

o

No Operation
DACA
DACB
DACC
DACD
DACE
DACF
DACG
DACH
N~ Operallon

AI

o

o
o
I

o
o

I

I

o
I

I

o
I

I

NJOperalion

MSB

LSB

-1071061
0
0

D51041DJ

0
0

0
0

1 D21

DI

0
0

1

DO

o
I

0

I

I

I

I

I

I

I
I

0
0

0
0

0
0

0
0

0
0

0
0

DAC Oulpul Voltage
1
VOUT = D/1l8 (VIN - VREFL) + VREFL
VREFL
1/128 (VIN - VREFL) + VREFL
127/128 (VIN - VREFL) + VREFL
VIN (P.....I Valu.)
1l9/128 (VIN - VREFL) + VREFL

254/128 (VIN - VREFL) + VREFL
255/U8 (VIN - VREFL) + VREFL

Table D. Logic Control Input Truth Table
SDI CLK LD PR Input Shift Register Operation

X
X

L

L
L

H
H

X
X

X
L

L
H

L
H

No Operation
Shift One Bit In from SOl (Pin 20),
Shift One Bit* Out from SDO (Pin 18)
All DAC Registers = 80H
Load Seria1 Register Data into
DAC(X) Register

*Oata shifted into the SOl pin appears twelve clocks later at the SOO pin.

REV. A

SPECIAL FUNCTION VIDEO PRODUCTS 8-91

•

DAC-8841-.Typical Performance Characteristics
.0.5

I I I

+1/2

DAC. A, B, C, D SUPERIMPOSED

~

0

w

+1/2

~

0

5

~

i:I

li!

1 J J

.-

i

['

......\

128

192

256

2.0

1.6

r- Y,N =1.5V

VREF L = 2.SV

e

E
I

i

~

1.0
0.8

0.6

i,II

0.'

I/Mi1

'

I

Z

.r
,

..u. I~ ~

....,

J.,1

o

10

o

128

64

r-- IV.:a~~~VI

r

r--

1=
a:

~0

~ 1.496
1.495

192

1.493
-liD

256

~

I_-t::t::t::t::t::t:~~

I;
~21-

0.01

oL-...I--.l._.l-....L.......J_..L........L--I

0.001
10

100

lk

10k

tfl

,

1.0

VREFL =oV
DATA ALL ZEROS

./

-

I

o

iiii=DV

~ 0.6

o>~

0.'

\

S
I

c

..

V

VIN -Voltl

200
300
VOUTX-mV

400

500

,
~

o
100

Figure 9. Zero-Scale Output Detail

8-92 SPECIAL FUNCTION VIDEO PRODUCTS

0.2

•

o '/
o

Figure 8. Full-Scale Output to
Positive Saturation

VREFL=OV

I

-

TA=25'C

VDD +sv
TA = 25'C
0.8 _ V,. = 1.5V

~

L

./

LOAD = SmA _
e-- __ IVREFL=OV

I

~

~IN = +1.5V

I

I

=

VDD = 5V
TA =2S'C

}.
I

100 125

Figure 7. VOUT Slew Rate vs.
Temperature

Figure 6. Total Harmonic Distortion
vs. "Frequency

16

V OD =5V

-liD -25 0
25 50 75
TEMPERATURE -'C

-75

lOOk

FREQUENCY - Hz

, - ,- I
-_ .•I.'
,
"1
,

~~--r--+--+--+--+--+--4

~ 3r--r--t--+'S~R~_+--+--+--+--1

10

o

SR+

$a: •

0.1

32 64 96 128 150 192 22' 258
DIGITAL INPUT CODE - Decimal

,

100

r- Y,N = 1.5V

I

1.0

e

Figure 5. IREFL Input Current vs,
Digital Code

75

VREFL=OV
6r--r--T--+--+--+--~~--4

~

:z:

~

7

,.

z

..J

25
50
TEMPERATURE -'C

Voo= 5V

I I

VIN = 1Vpp + 1V
RL =2k(!
TA =25'C

a:

,

-25

Figure 4. Half Scale vs, Temperature

Y
0
:IE

0.2

o

100

0

1.2

""

Figure 3. Linearity Error vs, Digital
Code vs. Temperature

,.

Voo = sv

i.'

1.497

r;

DIGITAL INPUT CODE - Decimal

Figure 2, Linearity Error vs, Digital
Input Code

r-

[',t

1.498

I

1.494
-0.5

DIGITAL INPUT CODE - Decimal

1.8

~J

'r

~ -0.25

I I I
64

.... ....,..

iii

I

1,485 f-~X=1.5V
PR=DV

!

I

DAC. E, F, G, H SUPERIMPOSED

-1/2

+0.25

I

1.500 f - Voo =5V
VREF L= OV

VOD = 5V
V1NX = 1.SV
VREFL= 100mV

a:

Voo=5V
VIN X = 1.5V
VREF L = 100mV

a:

~

..

r

~T~=2~!C

g-112
I

1.501

T~ ~-li~' 25, ~85'cl

10

-,

-

lk
10k
FREQUENCY - Hz

100k

Figure 10. Voltage Noise Density vs.
Frequency

REV, A

DAC-8841

LD
(5V/DIV)

VIN
(O.5V/DIV)

VOUT
(1V/DIV)

VOUT
(1V/DIV)

DIGITAL CODE

Figure 11. Pulse Response

=255'" 8 ... 255

Figure 12. Settling Time

32
28

LD
(5V/DIV)

~I

24

~

20

o

16

0:
0:

VOUT
(50mV/DIV)

Q.

~

12

iilI

8

t- ~~N~ : ~

.!:

.I.VDD =6VJ
VDD =5V

'I

-

VDD =4V_

Jl
DIGITAL CODE

o

= 128 ... 127

-50

Figure 13. Worst Case 1 LSB Digital Step Change

40
80

T~ -25!C

.

PR =0

I
0-

j

0

~ SHORT CIRCUIT

-30 f -

I II I II
lk

10k

lOOk

1M

FREQUENCY - Hz

Figure 15. PSRR vs. Frequency

REV. A

178 PC SAMPLE
X+3a

Iii
Ie
~

1

~

..

-1

V

-40

CURRENT LIMITING
I I I
I

-1
VOUTX-Volta

Figure 16. DAC Output Current
vs. VourX

x

I\,

\

~-2

-40

VDD=+5V+O.1Vp--p

100

3

I

:!

-10

TA =25·C
100

SHORT
CIRCUIT
CURRENT
LIMITING

10

E

I"

o

~

I- ~EFL=OV

20

75

Figure 14. Supply Current vs. Temperature

30 t- VIN -= 1.5V

1\

25
50
TEMPERATURE - ·C

-25

X-3a
~

~-3
-4
-5

o

100 200 300 400 500 800
T =HOURS OF OPERATION AT 15O"C

Figure 17. Output Drift Delta
Accelerated by Burn-In

SPECIAL FUNCTION VIDEO PRODUCTS 8-93

II

OAC-8841
CIRCUIT OPERATION
The DAC-8841 is a general purpose multiple-channel ac or dc
signa1level adjustment device designed to replace potentiometers
used in the three-terminal connection mode. Eight independent
channels of programmable :signal level control are available in
this 24-pin package device. The outputs are completely buffered
providing up to 5 rnA of drive current to drive external loads.
The DAC and amplifier combination shown in Figure 18 produces two-quadrant mliltiplication of the signal inputs applied to
VIN times the digital input control word. In addition the DAC8841 provides a 1 MHz gain-bandwidth product in the twoquadrant mliltiplying channel. Operating from a 5 V power
supply, analog inputs to + 1.5 V which generate outputs to
+ 3 V are easily accommodated.

During system power up a logic low on the preset PR pin forces
all DAC registers to 80H which in turn forces all the buffer amplifier outputs to equal half-scale. The transfer equation (1)
shows that in the preset condition (80H ) that VOUT will equal
VIN' The asynchronous PR input pin can be activated at any
time to fOfce the DAC registerS to the half-scale· code 80H • This
is generally the most convenient place to start for general purpose adjustment applications.
ADJUSTING AC OR DC SIGNAL LEVELS
The two-quadrant multiplication operation of the DAC-8841 is
shown in Figure 18. For dc operation the equation describing
the relationship between VIN' digital inputs and VOUT is:
VouTID) = IDI128) x IVIN - VREFL)

+

VREFL

(1)

where D is a decimal number between 0 and 255.
The actual output voltages generated with a fixed 1.5 V dc input
on VIN and VREFL = 0 V are summarized in this table.

VOUT = 2

x

VOAC WHEN VREF L

v,.
xv,.

=OV

0

= 2 (D/25&) x
= (Dfl;zal

Decimal Input (D)

GENERAL CASE WHEN VR• F L ~ ov:
VOUT ~ (0/128) )( (YIN - VREF L) + VAEF L
DAC8841'NPUT.()UTPUTVOLTAGE RANGE
V DD

=+ 5V

VREFL=OV
4

2
127
128
129
254
255

VouT(D)
0.000 V*
0.012*
0.024*
1.488
1.500
1.512
2.976
2.988

Comments
(VIN
1.5 V, VREFL

=

= 0 V)

Zero Scale

Half Scale = VIN

Full Scale
(FS) == 2 x VIN

D=FFH

!

~D~CDH

I

82

hYD~80H

>

o

·See "Operation Near Ground."

e

. " , D~40H

.D=OOH

o

4

VIN-Volta
VOUT

=2 x V,. (DI25&). WHERE D =0 TO 255

Figure 18. DAC Plus Amplifier Combine to Produce TwoQuadrant Multiplication

In order to be easy to use with a controlling microprocessor, a
simple layout-efficient three-wire serial data interface was chosen. This interface can be easily adapted to almost all microcomputer and microprocessor systems. A clock (CLK), serial data
input (SDI) and a load (LD) strobe pin make up the three-wire
interface. The 12-bit input data word used to change the value
of the internal DAC registers contains a 4-bit address and 8-bits
of data. Using this combination; any DAC register can be
changed without disturbing the other devices. A serial data output (SDO) pin simplifies cascading multiple DAC-8841s without
adding address decoder chips to the system.

8-94 SPECIAL FUNCTION VIDEO PRODUCTS

Notice that the output polarity is the same as the input polarity
when the DAC register is loaded with 255 (in binary = all
ones). Also note that the output does not exactly equal two
times the input voltage. This is a reslilt of the R-2R ladder DAC
chosen. When the DAC register is loaded with 0, the output is
VREFL. The actual voltage measured when setting up a DAC in
this example will vary within the ± 1 LSB linearity error specification of the DAC-8841. The actual voltage error wolild be
±0.012 V.

Operation Near ground - The input stage of the internal buffer
amplifier functions down to ground, but the output stage cannot
pull lower than the internal ground voltage. When a DAC output tries to output a voltage at or below the internal ground potential, it saturates and appears like a 50 n resistor to ground.
The typical saturation voltage appearing at the output is 20 m V,
see Figure 9. The 100 mV worst case zero-scale voltage specification reflects this saturation effect, including the worst case
anticipated variation of the internal ground resistances, quiescent currents and buffer sinking current. Linearity is measured
between code 810 and code 255 10 to avoid this saturation effect.
In summary, the transfer function of each DAC will be a
straight line from code 8 to code 255 when VREFL = 0 V. For
input codes 0 to 7, some DAC outputs will be saturated in the
zero-scale output voltage region; therefore, changing digital code
o to 1 may not change the output voltage when VREFL = 0 V.

REV. A

OAC-8841
SIGNAL INPUTS (VINA, B, C, D, E, F, G, H)
The eight independent VIN inputs have a code dependent input
resistance whose worst case minimum value is specified in the
electrical characteristics table. Use a suitable amplifier capable of
driving this input resistance in parallel with the specified input
capacitance. These reference inputs are designed to receive not
only dc, but ac input voltages. This results from the incorporation of a true bilateral analog switch in the DAC design, see
Figure 19. The DAC switch operation has been designed to operate in the break-before-make format to minimize transient
loading of the inputs. The reference input voltage range can operate from ground (GND) to 1.5 V. That is, the operating input
voltage range, when VREFL = 0 V, is:

oV <

V/NK < 1.5 V

(2)
4

V REF L - Volts

v,.,

0-_--"
p-eH

Figure 20. DAC-8841 Input Voltage Operating Boundaries

N.cH

For example, biasing VREFL equal to one volt would accept a
I V p-p ac input signal on VIN' This input signal could then be
attenuated or given a gain-of-two depending on the DAC data
setting.

DAC
REGISTER

D,

DAC OUTPUTS (VouTA, B, C, D, E, F, G, H)
The eight D/A converter outputs are fully buffered by the DAC8841s internal amplifier. This amplifier is designed to drive up
to I kG loads in parallel with 200 pF. However in order to minimize internal device power consumption, it is recommended
whenever possible to use larger values of load resistance. The
amplifier output stage can handle shorts to GND; however, care
should be taken to avoid continuous short circuit operation. See
Figure 16 "DAC output current versus VOUTX" graph.

D.t--t--1I-.....-I.>.-,

2.

The amplifier output is guaranteed to operate to within 2 V of
V00 under all load conditions and temperature. Figure 8 shows
typical operation to positive output saturation with a 5 rnA load.

Figure 19. DAC-8841 TrimDAC Equivalent Circuit
(One Channel)
The reference inputs can withstand input voltages up to V 00;
however due to the internal amplifier's gain of two configuration, the output voltage of the circuit reaches its maximum specified value of 3 V when the input voltage equals 1.5 V and
VREFL = 0 V; see Figure 18.
The reference low input V REFL is the bottom end of the DAC
(see Figure 18). This input is normally tied to ground; however
it can be biased above ground. When VREFL is biased above
ground, its value and that of V INX should be chosen in agreement with Equation 3.
(3)

Also for the general case the headroom restriction to V 00 for
VINX and VREFL is given by Equation 4.
(4)

According to the above equations, the DAC-8841 can only be
operated under certain combinations of VINX and VREFL. The
shaded area in Figure 20 defines the theoretical allowable ranges
of operation. Note that VREFL can be biased higher than VINX,
Linearity will vary with the reference voltages and supply conditions. If a symmetrical output ac signal is desired, then the symmetrical ac input on VINX should be offset to VREFL. The
output signal will then be with respect to VREFL.

REV. A

The low output impedance of the buffers minimizes crosstalk
between analog input channels. At 100 kHz 70 dB of channelto-channel isolation exists. It is recommended to use good circuit layout practice such as guard traces between analog
channels and power supply bypass capacitors. A ·0.01 I'oF ceramic in parallel with a 1-10 I'oF tantulum capacitor provides a
goOd power supply bypass for most frequencies encountered.

DIGITAL INTERFACING
The four digital input pins (CLK, SOl, LD, PRj of the DAC8841 were designed for TTL and 5 V CMOS logic compatibility. The SDO output pin offers goOd fanout in CMOS logic
applications and can easily drive several DAC-884Is.
The Logic Control Input Truth Table II describes how to shift
data into the internal 12-bit serial input register. Note that the
CLK is a positive edge-sensitive input. If mechanical switches
are used for breadboard, product evaluation they should be debounced by a flipflop or other suitable means.
The required address plus data input format is defined in the
Serial Input Decode Table I. Note there are 8 address states
that result in no operation (NaP) or activity in the DAC-884I ,
when the active high load strobe LD is activated. This Nap can
be used in cascaded applications where only one DAC out of
several packages needs updating. It takes 12 clocks on the CLK

SPECIAL FUNCTION VIDEO PRODUCTS 8-95

•

DAC-8841
pin to fully load the serial input shift register. Data on the SOl
input pin is subject to the timing diagram (Figure 1) data setup
and data hold time requirements. After the twelfth clock pulse,
the processor needs to activate the LD strobe to have the DAC8841 decode the serial register contents and update the target
DAC register with the 8-bit data word. This needs to be done
before the thirteenth positive clock edge. The timing requirements are in the electrical characteristic table and in the Figure
1 timing diagram. After twelve clock edges data initially loaded
into the shift register at SDI appears at the shift register output
SOO.

.e
PAO
PAl
PA2

DATA
CLOCK

LD
SO,
eLK

....

DAC.aII41111
LD
SOO PACH

SOt
Cl.K

There is some digital feedthrough from the digital input pins.
Operating the clock only when the DAC registers require updating minimizes the effect oCthe digital feedthrough on the analog
signal channels.

....

•
•
•

DAC-8841 112
LO

Figure 21 shows a three-wire interface for a single DAC-8841
that easily cascades for multiple packages.

eLK

SDO

PACH

•0'

PAC •

DAC-8841 113
LD
SDO PACH

Figure 21. Three-Wire Interface

24

I'

12

:·:,aomV"

,="1.5\

o

,1;-36
-12

~-48
-60

-72

II

-84

I'-

-86

1k

10k

lOOk
111
FREQUENCY - Hz

1011

Figure 22. Gain (Vou-'/v/N) and Feedthrough vs. Frequency

8-96 SPECIAL FUNCTION VIDEO PRODUCTS

REV. A

Digital Signal Processing Products
Contents
Page

Digital Signal Processing Products - Section 9 .................................. 9-1
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-Z
ADDS-Z1OOA-ICE - In-Circuit Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
ADDS-ZIOI-EZ - EZ-Tools Hardware Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . 9-5
ADDS-ZIOI-ICE - In-Circuit Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
ADDS-21XX-SW - ADSP-Z1OO Family Development Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
ADDS-ZIOXX - SW-ADSP-Z1OOO Family Development Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
ADSP-ZIOO/2100A - lZ.5 MIPS DSP Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
ADSP-ZIOI - DSP Microcomputer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
ADSP-2tOS- DSP Microcomputer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-Z3
ADSP-Zl11 - DSP Microcomputer with Host Interface Pon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29
ADSP-ZIOZO - IEEE Floating-Point DSP Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33

II

DIGITAL SIGNAL PROCESSING PRODUCTS 9-1

~
tl

§

~

Selection Guide
Digital Signal Processing Products

r-

S!1
(;)

s;

DSP Processor Key Feature Summary

r-

]
Q
@
C/)

~

(;)

]
Q

tl

c:
C)

fil

Model

Instruction
Internal
Cycle
Off-Chip Program
Harvard Memory
Time
RAM
ns
Arch

ADSP2100A
ADSP-2101
ADSP-210S
ADSP-2111

80
60
100
60

Internal
Data
Memory
RAM

I

Internal
Program
Cache
Word

Program
Memory Serial Programmable
Boot
Ports Timer

16 x 24

\'

I

2K x 24 lK x 16
lK x 24 O.SK x 16
2K x 24 lK x 16

\'

\1
I

\

2
1
2

I

\'

\/
\1

Low
Ext
Power Pin
Interrupts .Modes Count

Page

4
3
3
3

100
68
68
100

9-13
9-17
9-23
9-29

4

223

9-33

3Z/40-Bit Floating Point
ADSP-21020

40

\

f

32 x 48

11IIIIIIII ANALOG
WDEVICES
FEATURES
Interfaces to IBM PC Host via RS-232 Interface. at up
to 57600 Baud
Emulates 80 ns ADSP-2100A at Full Speed
User Interface Similar to Simulators
Custom Window Configuration and Command Aliasing
Standalone Operation Allows Software Debugging
Before Hardware Prototype
Assembly and Disassembly of ADSP-2100A Instructions
Single-Step as Well as Full-Speed Operation
Overlay RAM Can Replace Target System Memory
Trace Buffer Stores Up to 8K Frames of ADSP-2100A
Activity
Supports Software Breakpoints and Break Expressions
Hardware Break and/or Trace Triggering on an Extensive Set of Bus Conditions
Static User Control of Selected ADSP-2100A Inputs
Software Support for Industry-Standard Mouse
Optional Logic Module Probes Allow Tracing of
Additional Signals
Optional Probe-to-Target Umbilical Cord Facilitates
Debug and Testing Work

GENERAL DESCRIPTION
The ADSP-2100A Emulator is a hardware development tool that
provides a controlled environment for observing, debugging,
and testing activities in a target system. The emulator provides
this control by replacing the target ADSP-2100A processor.
While running at full speed, the emulator behaves like the processor in the target system. The emulator can monitor and
record system behavior and lets you examine and alter memory
locations as well as processor registers. Hardware events can be
detected and used to trigger tracing.

The ADSP-2100A Emulator uses an emulator chassis manufactured by Microtek, Inc. The emulator consists of a control processor (CP) board, two real-time analyzer (RTAJ boards, an
ADSP-2100A personality board, and an ADSP-2100A in-circuit
probe.
The emulator is operated through an IBM PC host computer.
The interface software provided with the emulator is similar to
the simulator of the ADSP-2100 Family Development Software.

REV_A

In-Circuit Emulator
ADDS-21 DDA-ICE I

TRACE SAMPLING RATE
Trace sampling occurs at the ADSP-2100A instruction rate, up
to 12.5 MHz.
TRACE BUFFER SIZE
The trace memory buffer stores up to 8K x 144-bit frames of
ADSP-2100A activity. Buffer data may be window displayed or
written to a file.

OVERLAY RAM
Overlay RAM can replace program memory and/or data memory
in the target system. Data memory space may be overlaid in
lK-word blocks. Program memory space may be overlaid in 2Kword blocks.
Overlay RAM size is equal to the ADSP-2100A's memory space.
This includes 16K x 24-bit program memory and 16K x 16-bit
data memory.
HARDWARE EVENT DETECT (TRIGGER)
Hardware events may be detected and used to break execution,
start or stop tracing, or assert an instrumentation synchronization pulse. Break and/or trace triggering is possible on up to 8
bus condition sequences. Bus conditions and other signals may
be logically combined to create more complex events.

DIGITAL SIGNAL PROCESSING PRODUCTS 9-3

II

9-4 DIGITAL SIGNAL PROCESSING PRODUCTS

r.ANALOG
WDEVICES

EZ-Tools Hardware Development Tools
ADDS-2101-EZ I

FEATURES
EZ-Tools Support Prototyping. Development and
Debugging of ADSP-2101 and ADSP-2105 Systems
ADSP-2101 EZ-ICE'· IN-CIRCUIT EMULATOR
3.3" x 3.3" Surface-Mount Board with RS-232 Port
Plugs Directly into ADSP-2101 Socket on Target Board
Full Speed Emulation
Single Step Capability
Sixteen Breakpoints
Memory Upload/Download with a PC
Examine and Alter Registers. Program Memory and
Data Memory
8 K x 24-Bit High Speed Program/Data Overlay
Memory
12.288 MHz Oscillator. Socketed for Easy Change of
Clock Speed
Memory Map (MMAP) Pin Control
Standalone Operation for Software Debugging without
Target Board
Easy to Learn Menus and Displays
ADSP-2101 EZ-LAB'· DEMONSTRATION BOARD
12.5 MHz ADSP-2101 Microcomputer
64 K x 8-Bit Boot EPROM Preprogrammed with
Demonstrations
Voice I/O Port with Microphone Input Jack and
Speaker Output Jack
Four-Channel. 8-Bit Digital-to-Analog Converter (DAC)
Port
Bus Expansion Connector Allows Additional I/O and
Full Memory Expansion
Serial Port Expansion Available through SPORT
Connector
12.288 MHz Crystal. Replaceable with Different Speed
Crystals
Three Switches for User Control: Interrupt IRQ2. Flag
In and Reset
ADSP-2101 EZ-KIT STARTER PACKAGE
EZ-LAB Demonstration Board
Cross-Software (Assembler and Simulator)
DSP Textbook
Applications Handbook with Example Programs on
Disk
Training Workshop Discount Coupon

GENERAL DESCRIPTION
The ADSp·2101 EZ-Tools support the prototyping, development and debugging in hardware of applications based on the
ADSP-2101 or ADSP-2105 microcomputer.
EZ-ICE is a compact, easy-to-use in-circuit emulator for debugging code and testing ADSP-2101 or ADSP-2105 based systems.
EZ-ICE consists of a board and an RS-232 cable. It is operated
through a VT100-type terminal or through a PC running a terminal emulation program. The user interface is provided by an
on-board microcontroller-based monitor.
EZ-LAB is a low cost evaluation and demonstration board for
the ADSP-2101 DSP microcomputer. It allows you to test coded
digital signal processing applications on the ADSP-2101. EZLAB comes equipped with an EPROM device containing
prepared demonstrations, including speech and graphics applications. You can replace this EPROM with one containing your
own programs. Upon reset, the processor reads in the contents
of the EPROM, stores the code in its internal program memory,
and begins execution.
EZ-Kit is a starter package consisting of:
• an ADSP-2101 EZ-LAB demonstration board,
• ADSP-2101 software development tools for the IBM* PC,
including assembler and simulator,
• Digital Signal Processing in VLSI, a 575 page digital signal
processing textbook featuring the ADSP-2100 family,

• a book of example applications with source code provided on
disk, and
• a discount coupon for the ADSP-2100 processor family training workshop.

EZ-ICE and EZ-LAB are trademarks of Analog Devices, Inc.
"IBM is a registered trademark of International Business Machines Corp.

REV. A

DIGITAL SIGNAL PROCESSING PRODUCTS 9-5

II

9-6 DIGITAL SIGNAL PROCESSING PRODUCTS

1IIIIIIII ANALOG

WDEVICES

In-Circuit Emulator
ADDS-2101-ICE

FEATURES
Interfaces to IBM-PC Host via RS-232 Interface. at up
to 57600 Baud
Emulates 50 MHz ADSP-2101. with 12.5 MHz Instruction Rate
User Interface Similar to ADSP-2101 Simulator
Custom Window Configuration and Command Aliasing
Simulator Configuration Files May Be Used
Standalone Operation Allows Software Debugging
Before Hardware Prototype
Assembly and Disassembly of ADSP-2101 Instructions
Single-Step As Well As Full-Speed Operation
Overlay RAM Can Replace Target System Memory
Interface Board Prevents Bus Contention Between
Probe and Target
Trace Buffer Stores up to 8K Frames of ADSP-2101
Activity at Full Speed
Supports Software Breakpoints and Break Expressions
Hardware Break andlor Trace Triggering on an
Extensive Set of Bus Conditions
Static User Control of Selected ADSP-2101 Inputs
Software Support for Industry-Standard Mouse
Optional PGA-PLCC Adaptor
Optional Logic Module Probes Allow Tracing of
Additional Signals
Optional Probe-to-Target Umbilical Cord Facilitates
Debug and Testing Work

The ADSP-2101 Emulator user an emulator chassis manufactured by Microtek, Inc. The emulator consists of a VME-based
chassis, a control processor (CP) board, two real-time
analyzer (RTA) boards, an ADSP-2101 personality board, and
an ADSP-2101 in circuit probe.
The emulator is operated through an IBM PC host computer.
The interface software provided with the emulator is similar to
the sofrware simulator. If you are familiar with the simulator,
the emulator requires little additional learning.

GENERAL DESCRIPTION
The ADSP-2101 Emulator is a hardware development tool that
provides a controlled environment for observing, debugging,
and testing activities in a target system. The emulator provides
this control by replacing the target ADSP-2101 processor. While
running at full speed, the emulator behaves like the processor in
the target system. The emulator can monitor and record system
behavior, and lets you examine and alter memory locations as
well as processor registers. Hardware events can be detected and
used to trigger tracing.

REV. A

•

DIGITAL SIGNAL PROCESSING PRODUCTS 9-7

9-8 DIGITAL SIGNAL PROCESSING PRODUCTS

~ANALOG

WDEVICES

ADSP-2100 Family Development Software
ADDS-21 XX-SW I

FEATURES
DSP PROCESSORS SUPPORTED

ADSP-2100
ADSP-2101l2102
ADSP-2105/2106
ADSP-2111
ADSP-21 msp50
SYSTEM BUILDER
Architecture Description File Specifies Target
Hardware
ASSEMBLER
C Preprocessor Supports High Level Constructs
Supports Flexible Macro Processing
Encourages Modular Code Development
Provides a Full Range of Diagnostics
LINKER
User-Defined Library Support
Maps Assembler Output to System Memory
PROM SPLITTER
Formats ROM Memory Image for Uploading to PROM
Programmers
SIMULATORS
Reconfigurable Windowing Interface
Full Symbolic Disassembly
Simulates Hardware Configuration
Simulates Parallel and Serial Port I/O
Advanced Debugging Features
Profiling of Code Execution History
C COMPILER & RUNTIME LIBRARY
Allows Development of Applications Software in C
Language
Supports In-Line Assembly Code
Incorporates Optimizing Algorithms
Produces ROMabie Code
Floating-Point Emulation Support
Runtime Library with ANSI-Standard and DSP Library
Functions
Simplified Interrupt Handling via Library Functions

REV. A

GENERAL DESCRIPTION
The ADSP-2100 Family Development Software is a complete set
of software design tools which allow the programming of applications for this family of DSP microprocessors. The development system includes C and assembly language programming
tools as well as processor simulators to facilitate software design
and debug.

The software development system includes several programs:
System Builder, Assembler, Linker, PROM Splitter, Simulators
and C Compiler. Release 3.0 of the software development system runs on the IBM (or IBM-compatible) PC under DOS 3.x,
SUN3/SUN4 workstations, and VAX VMS.
The development process begins with the task of defining the
target system hardware with the use of the system b~ilder tool.
The system builder generates an architecture description file
which passes information about the target hardware to the
linker, simulator, and emulator (if used).
Code generation is accomplished by writing C and/or assembly
language source code modules. Each C and assembly module is
compiled and/or assembled separateiy. Several modules are then
linked together to form an executable program.
The simulator provides windows that display different portions
of the hardware environment. To replicate the target hardware,
the simulator configures memory according to the architecture
description file generated by the system builder, and simulates
1/0 ports according to user-entered commands. This simulation
allows the user to debug the system and analyze performance
before committing to a hardware prototype.

DIGITAL SIGNAL PROCESSING PRODUCTS 9-9

II
I

9-10 DIGITAL SIGNAL PROCESSING PRODUCTS

IIIIIIIIIII ANALOG

WDEVICES

ADSP-21 000 Family Development Software
ADDS-210XX-SW I

Supports the ADSP-21000 Family of Floating-Point DSP
Processors

PROM SPLITTER
Formats Executable File for Programming PROMs or
Loading Target from a Microcontroller
Supports Motorola S Record, Intel Extended Hex, etc.

ASSEMBLER
High Level Algebraic Syntax
Extensive Set of Directives
Supports Macros & Conditional Assembly
Generates COFF Object Flies

OPTIMIZING C COMPILER
ANSI C Compliant
C-Callable Library of ANSI-Standard and DSP Functions
Supports In-Line Assembly Code
Provides FRACT Data Type (1.31 Fixed-Point Format)

LINKER
Combines Object and Library Files
Generates COFF Executable Files
Maps Assembler Output to Target Hardware
Generates Memory Map Listing

GENERAL DESCRIPTION
The ADSP-21000 Family Development Software is a set of tools
for creating and debugging programs for the ADSP-21000 family of floating-point processors. These tools enable you to create,
test, and debug ADSP-21OXX programs.

ASSEMBLY LIBRARYILiBRARIAN
Powerful Set of Arithmetic and DSP Functions
Callable from Assembly Code
Can Incorporate User-Defined Routines

The ADSP-21000 Development Software consists of several
components described in the following sections.

SIMULATOR
Window-Based Interface
Pull-Down Menus
Point-and-Click Mouse Operation
Full Symbolic Disassembly and On-Line Assembly
Simulates Memory and Ports
Flags Illegal Operations
Breakpoint Capability

OPTIMIZING C COMPILER
The C Compiler reads source files written in ANSI-standard
C language. The compiler outputs ADSP-21OXX assembly
language files and comes with a standard library of C-callable
routines.

ADSP-21020 SIMULATOR

II
I

floating Point Attributes Menu

Preei s ion:
Rounding Mode:

Extended
Nearest

Display Format:
Fix Decimal Place::;:

Scientific
5

I Enter

Display Format

I

Accept Changes?
YES

I

REV. A

F'FTC

PX2:

NO

I

Program Memory

I

(Disassembled)

[OODOeD)

rl5'=rl5-r2, modHy(111,mlO);

[ OOOOcl)

AM

[ DOODe2]

AM

[OOOOc3)

FFDE5F5F AM

[OOOOc4]

f12=fO*(7, r6",dm(iO,mO);
fll=fl*f7, rT'''pm(lB,mB);
f14=fO*f6, fl2=fB+fl2;
LCNTR=r5, do END~GROUP until

[DODOeS]

LCNTR=r15,

PX Registers

PX: FFDE5F5FFFFC
PX1:

Scientific
Non-Scientific

M

do END BFLY until

".~

lce,"'j"

DIGITAL SIGNAL PROCESSING PRODUCTS 9-77

ADDS-210XX-SW
ASSEMBLER
The assembler inputs a file of ADSP-21OXX source code and
assembler directives and outputs a relocatable object file. The
assembler supports standard C preprocessor directives as well as
its own directives.

PROM SPLITTER
The PROM splitter translates an ADSP-210XX executable program into one of several formats (Motorola S2 and S3, Intel Hex
Record, etc.) that can be used to configure a PROM or be
downloaded to a target from a microcontroller.

LINKER
The linker processes separately assembled object and library
files to create a single executable program. It assigns memory
locations to code and data in accordance with a user-defined
architecture file, a text file that describes the memory configuration of the target system.

DEVELOPMENT PROCESS
Figure 1 shows the process of compiling, assembling, linking
and simulating a program, indicating the input and output of
each step. File name extensions (.asm, .obj, etc.) signify different types of files.

ASSEMBLY LIBRARYILIBRARIAN
The assembly library contains standard arithmetic and DSP routines that you can call from your program, saving development
time. You can add your own routines to this library using the
librarian function.
SIMULATOR
The simulator executes an ADSP-21OXX program in software in
the same way that an ADSP-21000 family processor would in
hardware. The simulator also simulates the memory and 110
devices specified in the architecture file. The window-based user
interface supports a powerful debug environment that allows the
developer to interactively observe and alter the data in the processor and in memory. Accurate simulation of chip functionality
is assured.

MINIMUM PC REQUIREMENTS
An IBM AT or 286/386-based PC (or compatible) and 640K of
memory are required. A color monitor, mouse, and at least 2
MB of extended memory are recommended.
ORDERING INFORMATION
Part Number

SOURCE CODE

~

.C FILES -

Description

ADDS-210XX-DSW-PC Assembler, Linker, Assembly Library/
Librarian. PROM Splitter, Simulator
ADDS-21OXX-BUN-PC Assembler, Linker, Assembly Library/
Librarian, PROM Splitter, Simulator,
Optimizing C Compiler & Runtime
Library
ADDS-21OXX-C-UP-PC Optimizing C Compiler & Runtime
Library (Upgrade for Owners of the
DSW Package)

SOURCE CODE

~

(c COMPILER) -.ASM FILES

CODING ENVIRONMENT

-

(ASSEMBLER)

_I

____

/
.OBJ FILES ---;/(LINKER) -

(SIMULATOR)

.EXE fLE ' "
HARDWARE
DEVELOPMENT
TOOLS
AFTER DEBUG

DEBUGGING ENVIRONMENT
(PROM SPLITTER)

+

PROM FORMATTED FILES

Figure 1. Program Development

9-12 DIGITAL SIGNAL PROCESSING PRODUCTS

REV. A

r-IIANALOG

WDEVICES
FEATURES
Pin- and Code-Compatible DSP Microprocessors
ADSP-2100, 6.144MHz and 8.192MHz
ADSP-2100A, 10.24MHz and 12.5MHz
Separate Program and Data Buses, Extended Off-Chip
Single-Cycle Direct Access to 16K x 16 of Data Memory
Single-Cycle Direct Access to 32K x 24 of Program
Memory
Dual Purpose Program Memory for Both Instruction
and Data Storage
Three Independent Computational Units: ALU,
MultiplierlAccumulator and Barrel Shifter
Two Independent Data Address Generators
Powerful Program Sequencer
Internal Instruction Cache
Provisions for Multiprecision Computation and
Saturation Logic
Single-Cycle Instruction Execution
Multifunction Instructions
Four External Interrupts
80ns Cycle Time (ADSP-2100A)
790mW Maximum Power Dissipation (ADSP-2100A,
J and K Grades)
100-Pin Grid Array, 100-Lead POFP (JEDEC Style),
100-Lead COFP
APPLICATIONS
Optimized for DSP Algorithms Including
Digital Filtering
Fast Fourier Transforms
Applications Include
Image ProceSSing
Radar, Sonar
Speech Processing
Telecommunications

GENERAL DESCRIPTION
The ADSP-2100 and ADSP-2100A are pin- and code-compatible
single-chip microprocessors optimized for digital signal processing
(DSP) and other high-speed numeric processing applications.
The ADSP-2100 and ADSP-2100A are both fabricated in a lowpower double-layer metal CMOS process. Together, they offer a
span of performance from 6MHz to 12.SMHz. All descriptions
of the ADSP-2100 in the text of this data sheet refer to both the
ADSP-2100A and the ADSP-2100 versions since they have
identical architectures and instruction sets. Timing and electrical
specifications differ as shown in those sections of the data sheet.
Both processors integrate computational units, data address
generators and a program sequencer in a single device. The
ADSP-2100 architecture makes efficient use of external memories
for program and data storage, freeing silicon area for increased

REV. A

12.5 MIPS DSP Microprocessors
ADSP-21 OO/ADSP-21 OOA I
FUNCTIONAL BLOCK DIAGRAM
DATA
ADDRESS
GENERATORS
IDAG li1 DAG

PROGRAM
SEQUENCER

ARITHMETIC
UNITS

I II II
ALU

21

MAC

SHIFTER

.

• •

) EXTERNAL

PROGRAM MEMORY ADDRESS

I

I
~

)

DATA MEMORY ADDRESS

~
PROGRAM MEMoaV DATA

(

>
>

~
DATA MEMORY DATA

(

ADDRESS
BUSES

EXTERNAL
DATA
BUSES

processor performance. The resulting processor combines the
functions and performance of a bit-slicefbuilding block system
with the ease of design and development support of a general
purpose microprocessor.
The ADSP-2100A (K grade) operates at 12.5MHz. Every instruction executes in a single 80ns cycle. The ADSP-2100A (J
and K grades) dissipates less than 790mW while the ADSP-2100
dissipates less than 47SmW.
The ADSP-2100's flexible architecture and comprehensive instruction set support a high degree of operational parallelism.
Because all instructions execute in a single cycle, MHz = MIPS.
In one cycle the ADSP-2100 can:
•
•
•
•
•

generate the next program address
fetch the next instruction
perform one or two data moves
update one or two data address pointers
perform a computational operation.

DEVELOPMENT SYSTEM
The ADSP-2100 and ADSP-2100A are supported by a complete
set of tools for software and hardware system development. The
Development-Software System provides a System Builder for
defining the architecture of simulated systems under development,
an Assembler, a Linker and a interactive Simulator. An ANSI
(draft) Standard C Compiler supports program development in
this widely used programming language, producing ADSP-2100
Assembly code which may be assembled, linked and simulated
with the other development system tools. A PROM Splitter
generates PROM burner compatible files. An In-Circuit Emulator
is available for hardware debugging.

DIGITAL SIGNAL PROCESSING PRODUCTS 9-13

II

ADSP-2100/ADSP-2100A
ADDITIONAL INFORMATION
For additional information on the architecture and instruction
set of the processor, refer to the ADSP-2100 User's Manual.
For more information about programming and the Development
System, refer to the ADSP-21OO Family Development Sofl'lJJare
Manual and the ADSP-2100 Emulator Manual. Manuals are
available only from your local Analog Devices sales office. There
is also a quarterly newsletter, DSPatch™, supporting Analog
Devices' digital signal processing customers.

ARCHITECTURE OVERVIEW
Figure I is an overall block diagram of the ADSP-2100. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the Shifter. The
computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs
a standard set of arithmetic and logic operations; division primitives
are also supported. The MAC performs single-cycle multiply,
multiply/add and multiply/subtract operations. The Shifter
performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations. The Shifter can be used
to efficiently implement any degree of numeric format control,
up to and including full floating point representations. The
computational units are arranged side-by-side instead of serially

for flexible operation sequencing. The internal result (R) bus
directly connects the computational units so that the output of
any unit may be the input of any unit on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units. The
program sequencer generates the next instruction address. To
minimize overhead cycles, the sequencer supports conditional
jumps, subroutine calls and returns in a single cycle. With
internal loop counters and loop stacks, the ADSP-2100 executes
looped code with zero overhead; no explicit jump instructions
are required to maintain the loop.
The data address generators (DAGs) handle address pointer
updates. Each DAG keeps track of up to four address pointers.
Whenever the pointer is used to access external data (indirect
addressing), it is modified by a prespecified value. A length
value may be associated with each pointer to implement automatic
modulo addressing for circular buffers. With two independent
DAGs, the processor can generate two addresses simultaneously
for dual operand fetches.
Efficient data transfer is achieved with the use of five internal
buses.
•
•
•
•
•

Program Memory Address (PMA) bus
Program Memory Data (PMD) bus
Data Memory Address (DMA) bus
Data Memory Data (DMD) bus
Result (R) bus

PMA

DMA

PMD BUS

24

PMD

DMD

Figure 1. ADSP-2100 Block Diagram
DSPatch is a trademark of Analog Devices, Inc.

9-14 DIGITAL SIGNAL PROCESSING PRODUCTS

REV. A

ADSP-21 DDIADSP-21 DDA
ADSP·2100A
Data Memory Read

Test
Code

AJGrade
Min
Max

AKGrade
Min
Max

AS Grade
Min
Max

AT Grade
Min
Max

AU Grade
Min
Max

Derating
Units Factor

SwitchingCharacuristics
67

DMRDWidth Low

A

36

28

45

36

28

os

4

68

DMA Valid to DMRD Low
DMRD High to DMA Invalid

A
A

6

4

14

6

4

os

3

8

6

\0

8

6

DMS Valid to DMRD Low
DMRD High to DMS Invalid

A
A

18

14

27

18

14

ns
ns

3

8

6

\0

8

6

ns

I

69
70
71

1

Timing Requirements
94
95

%
98

DMRD Low to DMD Input Valid
DMA Valid to DMD Input Valid

A
A

30

20

37

28

18

ns

4

48

32

59

46

32

7

DMS Valid to DMD Input Valid
DMRD High to DMD Input Invalid

A

52

45

67

50

35

ns
ns

A

0

0

0

0

0

7

ns

NOTE ON GENERATING WAIT STATES
See the application note "Wait State Generation on the ADSP·21001
2100A" for information on using DMACK to generate wait
states.

DMA

:

::

, i\----11_@----<·V
i i
..

f

.

i~i

~

DMACK

DMD

Figure 2. Data Memory Read

REV. A

DIGITAL SIGNAL PROCESSING PRODUCTS 9-15

II

ADS,P~21 OO/ADSP-:210QA
ADSP·2100A
Data Memory Write

Test

~Grade

Code

AJGrade
Min
Max

Min

Max

AS Grade
Min
Max

AT Grade
Min
Max

AU Grade
Min
Max

Derating
Units. factor

Switching Characreristics
78

DMWR Widlh Low

A

36

28

45

36

28

ns

4

79

DMA Valid 10DMWR Low

8

4

17

8

4

ns

3

80

DMWR Hiahlo DMA Invalid

8

6

10

8

6

ns

1

81

DMS Valid 10 DMWR Low

20

16

28

20

16

ns

3

6

4

8

6

4

ns

1

8

6

8

8

6

ns

1

82

DMWR High 10 DMS Invalid

87

DMWR Low 10 DMD OUI Enable

A
A
A
A
F

88

DMWR HiKb 10 DMD OUI Disable

D

32

29

38

32

29

ns

1

89

DMWRLowtoDMDOutValid

A

29

26

32

29

26

ns

1

90

DMWR Hillh to DMD Out Invalid

A

10

8

12

10

8

ns

1

91

DMD Out Valid to DMWRHigh

A

18

13

25

16

13

ns

3

DMA

\t, __ .~_ _

---------'1:::~-

't

"V-:,':,',

II

DMACK

DMD

Figure 3. Data Memory Write

9-16 DIGITAL SIGNAL PROCESSING PRODUCTS

REV. A

r-IIANALOG

WDEVICES
FEATURES
Complete DSP Microcomputer
80 ns Instruction Cycle Time from 12.5 MHz Crystal
ADSP-2100 Code & Function Compatible
2K Words of On·Chip Program Memory RAM
1K Word of On·Chip Data Memory RAM
Separate Program and Data Buses On·Chip
Dual Purpose Program Memory for Both Instruction
and Data Storage
Three Independent Computational Units: ALU, Multi·
plier/Accumulator and Barrel Shifter
Two Independent Data Address Generators
Powerful Program Sequencer
Zero Overhead Looping
Conditional Arithmetic Instruction Execution
Two Double·Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Programmable 16-Bit Interval Timer with Presealer
Programmable Wait Stete Generation
Automatic Booting of Internal Program Memory from
Byte·Wide External Memory, e.g., EPROM
Provisions for Multiprecision Computation and
Saturation Logic
Single·Cycle Instruction Execution
Single·Cycle Context Switch
Multifunction Instructions
Three Edge· or Level·Sensitive External Interrupts
80 mW Maximum Power Dissipation in Standby Mode
&S·Pin PGA, &S·Lead PLCC and 80·Lead POFP
MIL·STD-883 Compliant Versions Available

GENERAL DESCRIPTION
The ADSP-2101 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high-speed numeric
processing applications. Its instruction set is a fully compatible
superset of the ADSP-2100 instruction set. It combines the complete ADSP-2100 architecture (three computational units, data
address generators and a program sequencer) with two serial
ports, a programmable timer, extensive interrupt capabilities
and on-chip program and data memory RAM. The ADSP-2101
has IK words of (l6-bit) data memory RAM and 2K words of
(24-bit) program memory RAM on chip.
Fabricated in a high-speed 1.0 micron double-layer metal CMOS
process, the ADSP-210l operates at an 80 ns instruction cycle
time. Every instruction executes in a single cycle. Fabrication in
CMOS results in low power requirements. The ADSP-2101 dissipates less than I W under all conditions and no more than
80 mW under standby conditions.

DSP Microcomputer
ADSP-2101 I
FUNCTIONAL BLOCK DIAGRAM

The ADSP-2101's flexible architecture and comprehensive instruction set support a high degree of operational parallelism. In
one cycle the ADSP-2101 can:
•
•
•
•
•
•

generate the next program address
fetch the next instruction
perform one or two data moves
update one or two data address pointers
perform a computational operation
receive and transmit data via the two serial ports

Development System
The ADSP-2101 is supported by a complete set of tools for software and hardware system development. The Development
Software is a set of modules that supports all ADSP-2100 family •
processors. The System Builder provides a high-level method for
•
derming the architecture of systems under development. The
Assembler produces object code and the Linker combines object
modules and library calls into an executable file. The Simulator
provides an interactive instruction;level simulation with a reconfigurable user interface. A PROM Splitter generates PROM
burner compatible files. The C Compiler generates ADSP-2101
assembly source code.
Emulators aid in the hardware debugging of ADSP-2101 systems. The full featured emulator performs a full range of emulation functions including trace and triggering. EZ-Tools are low
cost, easy-to-use hardware tools. The EZ-ICE" emulator provides basic functions like changing register values and setting
breakpoints. The EZ-LAB'" demonstration board is a complete
ADSP-2101-based system that executes its own example programs. The EZ-Kit package is a starter kit that contains an
EZ-LAB board, development software, books and example
programs.
EZ-JCE and EZ-LAB are trademarks of Analog Devices, Inc.

REV.B

DIGITAL SIGNAL PROCESSING PRODUCTS 9-17

ADSP-2101

J I
.
DATA

ADDRESS
GEfERATOR

r>I~

~

I
G~a:R

PROGRAMS]
SEQU~CER

~

PROGRAM

DATA

BOOT

SRAII

2KX24

1KX16

ADDIIES8
GE_TOR

&RAM

~

DATA

,.
,.
24

PMABUSiL

~

=

MUX

-

lIMA BUS

.... BUS

............

' 7

;---

f-

BUS

16

E

7
~

INPUT REGS

. .UTAEGS

MAC

SHIFTER

ALU

OUTPUT REGS

~

N-

OUTPUT REGS ~
RBUS

~

ill
CONTROL
LOGIC

""-

{7

'---

RBUS

I

COMPANDING

7

Tran..... RoIg

_Rea

OUTPUT REOS V

16

I

ClRCUlTRV

EXTERN AL
DATA
BUS

~

]:/

DEBUS

It

E

INPUT REGS

MUX

ur-

~

/

=-.. . . .

I

I~ EXCHANGE~

-

EXTERN AL
ADDRESS
BUS

I

:!1~'{
_

TtMEA

Tran_ ....

...

SERIAL
PORTO

SERIAL

~

~

PORT 1

Figure 1. ADSP-2101 Block Diagram

Additional Information
This data sheet provides a general overview of ADSP-2101 functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-2IOI User's
Manual. For more information about the Development System
and ADSP-2101 programmer's reference information, refer to
the ADSP-2IOO Family Developmenl Software Manuals and the

ADSP-2IOI Emulalor Manual.
ARCHITECTURE OVERVIEW
Figure I is an overall block diagram of the ADSP-2101. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations. The
shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. The shifter can
be used to efficiently implement numeric format control including multiword floating-point representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.

9-18 DIGITAL SIGNAL PROCESSING PRODUCTS

A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units. The
sequencer suppons conditional jumps, subroutine calls and returns in a single cycle. With internal loop counters and loop
stacks, the ADSP-2101 executes looped code with zero overhead; no explicit jump instructions are required to maintain the
loop.
The data address generators (DAGs) handle address pointer updates. Each DAG maintains four address pointers. Whenever
the pointer is used 'to access data (indirect addressing), it is postmodified by the value of a specified modify register. A length
value may be associated with each pointer to implement automatic modulo addressing for circular buffers. With two data independent DAGs, the processor can generate two data addresses
simultaneously for dual operand fetches. The circular buffering
feature is also used by the serial pons for automatic data transfers; these are described in the section on serial pons.
Efficient data transfer is achieved with the use of five internal
buses.
•
•
•
•
•

Program Memory Address (PMA) Bus
Program Memory Data, (PMD) Bus
Data Memory Address CDMA) Bus
Data Memory Data CDMD) Bus
Result CR) Bus

REV. B

ADSP-2101
Min

Parameter

ADSp·2101·40
Max

Min

ADSp·2101·50
. Max

Unit

Memory Read
Timing Requirement:
tROD
tAA

RD Low to Data Valid

O.StcK - lS+w
0.75tcK - 20+w

AO-A13,P~S,D~S,B~Sto

Data Valid
Data Hold from RD High
tRDH
Switching Characteristic:

0

O.StcK - lS+w
0.7StcK - 20+w

ns
ns

0

tRP
teRD
t ASR

RD Pulse Width
CLKOUT High to RD Low

tRDA

AO-A13,D~S,P~S,B~S

0.2StcK - 10

0.2StCK - 10

tRWR

Hold after RD Deasserted
RD High to RD or WR Low

O.StCK - 5

O.StcK - 5

w = wait states x (tcK)

w= wait states x (tcK)

AO-A13,D~S,P~S,B~S

O.StCK - S+w
0.2StcK - 5
0.2StCK - 12

O.StcK - S+w
0.2StcK - 5
0.2StcK - 12

0.2StCK + 10

ns

0.2StcK + 10

Setup before RD Low

ns
ns
ns
ns
ns

CLKOUT

AO- A13

D

II
WR

Figure 2. Memory Read

REV.B

DIGITAL SIGNAL PROCESSING PRODUCTS 9-19

ADSP-2101
Parameter

ADSP·2101·40
MaX

Min

Min

ADSP·2101·50
Max

Unit

Memory Write
Switching Characteristic:
tow
tOH
twp
twoE
t ASW
tOOR
tcWR
tAW
tWRA
tWWR

Data Setup before WR High
Data Hold after WR High
WR Pulse Width
WR Low to Data Enabled
AD-AB, DMS, PMS Setup
before WR Low
Data Disable before WR or
RDLow
CLKOUT High to WR Low
AD-A l3 Setup before WR
Deasserted
AD-AB, DMS, PMS Hold
after WR Deasserted
WR High to RD or WR Low

O.StcK - 1O+w
0.25tcK - 10
O.StcK - 5+w
0
0.25tcK - 12

O.StCK - 10+w
0.2StcK - 10
0.5tCK - 5+w
0
0.25tcK - 12

0.25tcK - 10

0.25tCK - 10

ns
ns
ns
DS
DS

0.25tcK - 5
0.75tcK - 15+w

0.25tcK + 10

0.25tCK - 5
0.75tcK - 15+w

O.25tCK + 10

DS
DS
DS

0.25tcK - 10

0.25tcK - 10

0.5tCK - 5

0.5tcK - 5

W =

wait states x (tcK)

DS
DS

w = wait states x (tCK )

Figure 3. Memory Write

9-20 DIGITAL SIGNAL PROCESSING PRODUCTS

REV. B

ADSP-2101
Min

Parameter

ADSP-2IDl-40
Max

Min

ADSP-2IDl-SO
Max

Unit

Serial Ports
Timing Requirement:
tSCK
tscs
tSCH
tscp

97.6
10
10
38

SCLK Period

DRlTFS/RFS Setup before SCLK Low
DRlTFSIRFS Hold after SCLK Low
SCLKin Width

80
8
10
30

ns
ns
ns
ns

Switching Characteristic:

tee
tSCDE
tSCDV
tRH
tRD
tSCDH
tTDE

tTDV
tSCDD

tRDV

CLKOUT High to SCLKout
SCLK High to DT Enable
SCLK High to DT Valid
TFSIRFS out Hold after SCLK High
TFSIRFS out Delay from SCLK High
DT Hold after SCLK High
TFS in (alt) to DT Enable
TFS in (alt) to DT Valid
SCLK High to DT Disable
RFS in (multichannel, frame delay zero) to DT Valid

0.25tCK
0

0.25tCK + 15

0.25tcK
0

25

0.25tcK + 15
20

0

0
25

20
0
0

0
0
20

30
25

18
25
20

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

CLKOUT

SCLK

DR
RFSin
TFS'n

RFSout
TFSout

II

DT

TFS'n
alternate
lramemode

RFS'n
multichannel
mode, frame
delay 0 (MFD = 0)

Figure 4. Serial Ports

REV. B

DIGITAL SIGNAL PROCESSING PRODUCTS 9-21

9-22 DIGITAL SIGNAL PROCESSING PRODUCTS

ANALOG
WDEVICES

11IIIIIIII

FEATURES
Complete DSP Microcomputer
100 ns Instruction Cycle Time from 10 MHz Crystal
ADSP-2100 Code- & Function-Compatible
ADSP-2101 Pin-Compatible
1K Words of On-Chip Program Memory RAM
512 Words of On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Separate Program and Data Buses On-Chip
Three Computation Units: ALU, Multiplierl
Accumulator and Barrel Shifter
Two Independent Data Address Generators
Powerful Program Sequencer
Zero Overhead Looping
Conditional Arithmetic Instruction Execution
Double-Buffered Serial Port with Companding
Hardware and Automatic Data Buffering
Programmable 16-Bit Interval Timer with Prescaler
Programmable Wait State Generation
Automatic Boot of Internal Program Memory from
Byte-Wide External Memory, e.g., EPROM
Provisions for Multiprecision Computation and
Saturation Logic
Single-Cycle Instruction Execution
Single-Cycle Context Switch
Multifunction Instructions
Three .Edge- or Level-Sensitive External Interrupts
80 mW Maximum Power Dissipation in Standby Mode
68-Lead PLCC
GENERAL DESCRIPTION
The ADSP-2105 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high-speed numeric
processing applications. Its instruction set is a fully compatible
superset of the ADSP-2100 instruction set. It combines the complete ADSP-2100 architecture (three computational units, data
address generators and a program sequencer) with a serial port,
a programmable timer, extensive interrupt capabilities and onchip program and data memory RAM. The ADSP-2105 has 512
words of (l6-bit) data memory RAM and lK words of (24-bit)
program memory RAM on chip.
The ADSP-2105 is a pin-for-pin and code-compatible version
of Analog Devices' ADSP-2101 DSP Microcomputer. The
ADSP-2105 is the industry's leading cost/performance DSP. It
is an ideal choice in applications needing the performance advantages of a DSP processor at the cost of today's standard
microcontrollers.

REV. B

DSP Microcomputer
ADSP-2105 I
FUNCTIONAL BLOCK DIAGRAM

ADsp·2100 BASE
ARCHITECTURE

The ADSP-2105 offers a direct upgrade path to more highly
integrated and higher performance DSP processors. It is a subset of the ADSP-2101. Users selecting the ADSP-2105 will be
able to preserve their investment in ADSP-21XX tools in future
programs requiring the added features found on the ADSP-2101
and future members of the ADSP-2100 family.
The ADSP-2105 is feature- and instruction-set compatible with
the ADSP-2101. The only differences are the sizes of on-chip
memories (half the size of the ADSP-2101's), the number of
serial ports (one instead of two) and processor speed. The
ADSP-2105 serial port (SPORT) is identical to SPORT! of the
ADSP-2101. The specifics of these differences are documented
at the end of this data sheet.
Fabricated in a high-speed 1.0 micron double-layer metal CMOS
process, the ADSP-2105 operates with a 100 ns instruction cycle
time. Every instruction executes in a single cycle. Fabrication in
CMOS results in low power dissipation. The ADSP-2105 dissipates less than 1 W under all conditions and no more than
80 mW under standby conditions.
The ADSP-2105's flexible architecture and comprehensive instruction set support a high degree of operational parallelism. In
one cycle the ADSP-2105 can:
•
•
•
•
•
•

generate the next program address
fetch the next instruction
perform one or two data moves
update one or two data address pointers
perform a computational operation
receive or transmit data via the serial port

DIGITAL SIGNAL PROCESSING PRODUCTS 9-23

II

ADSP-2105

ig.

DATA

"

REGISTER

I

,.

.~

I

_,ADDRESS
DATA

ADORESS

GENERATOR

~ INSTRUCTION 1-,,-

~,~EN~~ATOR

PROGRAM

1Jj

~SEQ~~CER

~~

,.
,.

F-

I

2.

I~
-='...

--:::"

INPUT REGS

1~

j>-

-=

INPUT REGS

DMABUS

MUX

K

DMDBUS

ill

j>-

INPUT REGS

~

j\r-

,.

OUTPUT REGS ..r-

RBUS

{7

OUTPUT REGS

!'r-

{7

]:V

EXTERN AL
DATA

BUS

~

CIRCUITRY

CONTROL

A

~-~I
i:!1

~

V

=----~

BUS
EXCHANGE

LOGIC
OUTPUT REGS

ADORESS
BUS

MUX

=

,. ~

~ EXTERN At

-

~

PMDBUS

BOOT
ADDRESS
GENERATOR

J

=

PMABuslL

SHIFTER

MAC

AlU

DATA
SRAM
512X 16

r-

'---

~~

PROGRAM
SRAM
1KX24

TIMER

n.nomll Reg
Receive Reg

-

RBUS

SERIAL

'PORT
1

~
Figure 1. ADSP-2105 Block Diagram

Development System
The ADSP-210S is supported by a complete set of tools for
software and hardware system development. The development
software is a set 'of modules that supports all the ADSP-2100
family processors. The System Builder provides a high-level
method for defming the architecture of systems under development. The Assembler produces object code and the Linker combines object modules and library calls into an executable file.
The Simulator provides an interactive instruction-level simulation with a reconfigurable user interface. A PROM Splitter generates PROM burner compatible files. The C Compiler
generates ADSP-210S assembly source code.
Emulators aid in the hardware debugging of ADSP-2IOS systems. The full-featured emulator performs a full range of emulation functions including trace 'and triggering. EZ-Tools are low
cost, easy-to-use hardware tools. The EZ"ICE'" emulator provides basic functions like changing register values and setting
breakpoints. The EZ-LAB'" demonstration board is a complete
ADSP-2101-based system that executes its own example programs. The EZ-Kit package is a starter kit that contains an
EZ-LAB board, development software, books and example
programs.
Additional Information
Because the ADSP-210S is a subset of the ADSP-2101, the same
publications and development tools support both devices.
For additional information on the architecture and instruction
set of the processor, refer to the ADSP-2101 User's Manual.
For more information about the Development System and
ADSP-210S programmer's reference information, refer to the
ADSP-2100 Family Development Software Manuals and the
ADSP-2101 Emulator Manual.
EZ-ICE and EZ-LAB are trademarks of Analog Devices, Inc.

9-24 DIGITAL SIGNAL PROCESSING PRODUCTS

ARCHITECTURE OVERVIEW
Figure I is an overall block diagram of the ADSP-210S.
The processor contains three independent computational units:
the ALU, the multiplier/accumulator (MAC) and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs singlecycle multiply, multiply/add and multiply/subtract operations.
The shifter performs logical and arithmetic shifts, normalization,
denormalization, and derive exponent operations. The shifter
can be used to efficiently implement numeric format control including multiword floating-point representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units. The
sequencer supports conditional jumps, subroutine calls and returns in a single cycle. With internal loop counters and loop
stacks, the ADSP-210S executes looped code with zero overhead; no explicit jump instructions are required 'to maintain
the loop.
The data address generators (DAGs) handle address pointer updates. Each DAG maintains four address pointers. Whenever
the pointer is used to access data (indirect addressing), it is postmodified by the value of a specified modify register. A length
value may be associated with each pointer to implement automatic modulo addressing for circular buffers. With two
independent DAGs, the processor can generate two data addresses simultaneously for dual operand fetches. The circular
buffering feature is also used by the serial port for automatic
data transfers.

REV.S

ADSP-2105

·1

Efficient data transfer is achieved with the use of five internal
buses.
•
•
•
•
•

Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus.
Data Memory Data (DMD) Bus
Result (R) Bus

ADSP-2105-40
Parameter

Min

Max

Unit

0.5tcK - 15+w
0.75tcK - 20+w

ns
ns
ns

Memory Read
Timing Requirement:
tRDD
tAA
tRDH

RD Low to Data Valid
AO-A13, PMS, DMS, BMS to Data Valid
Data Hold from RD High

o

Switching Characteristic:
t RP

tcRD
t ASR

tRDA
t RwR

RD Pulse Width
CLKOUT High to RD Low
AO-A13, DMS, PMS, BMS Setup before RD Low
AO-A13, DMS, PMS, BMS Hold after RD Deasserted
RD High to RD or WR Low

0.5tcK - 5+w
0.25tcK - 5
0.Z5tcK - 12
0.25tcK - 10
0.5tcK - 5

0.25tcK + 10

ns
ns
ns
ns
ns

w = wait states x (tcK)

CLKOUT

AO-A13

DMS,PMS
BMS

II
D

Figure 2. Memory Read

REV.B

DIGITAL SIGNAL PROCESSING PRODUCTS 9-25

ADSP-2105
ADSP-21OS-40
Min

Parameter

Max

Unit

Memory Write
Switching Characteristic:
tow
tOR
twp
t WOE
tASW
tOOR
tcwR
tAW
tWRA
tWWR

Data Setup before WR High
Data Hold after WR High
WR Pulse Width
WR Low to Data Enabled
AQ--A13, OMS, PMS Setup before WR Low
Data Disable before WR or RD Low
CLKOUT High to WR Low
AQ--A13 Setup before WR Deassened
AQ--A13, OMS, PMS Hold after WR Deassened
WR High to RD or WR Low

0.5tcK - 10+w
0.25tcK - 10
0.5tcK - 5+w
0
0.25tcK - 12
0.25tcK - 10
0.25tCK - 5
0.75tcK - 15+w
0.25tcK - 10
0.5tCK - 5

0.25tcK + 10

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

w = wait states x (tCK)

Figure 3. Memory Write

9-26 DIGITAL SIGNAL PROCESSING PRODUCTS

REV.B

ADSP-2105
ADSP-2105-40
Parameter

Min

Max

Unit

Serial Port
Timing Requirement:
tscK
tscs
tSCH
tscp

SCLK Period
DRlTFS/RFS Setup before SCLK Low
DRlTFSIRFS Hold after SCLK Low
SCLK;n Width

97.6
10
10
38

ns
ns
nS
ns

Switching Characteristic:

tee
tSCDE
tSCDV
tRH
tRD
tSCDH
tTDE
tTDv
tSCDD

CLKOUT High to SCLKoUl
SCLK High to DT Enable
SCLK High to DT Valid
TFSIRFS ou, Hold after SCLK High
TFS/RFS ou, Delay from SCLK High
DT Hold after SCLK High
TFS;n (alt) to DT Enable
TFS;n (alt) to DT Valid
SCLK High to DT Disable

0.25tcK
0

0.25tcK + 15
25

0
25
0
0
20
30

ns
ns
ns
ns
ns
ns
ns
ns
ns

CLKOUT
tSCK

SCLK1

DR1
RFS11n
TFS11n

RFS10ui
TFS10ui
tSCDV
tSCDE

I+----I~

II

DT1

TFS11n
ALTERNATE
FRAME MODE

Figure 4. Serial Port

REV.B

DIGITAL SIGNAL PROCESSING PRODUCTS 9-27

9-28 DIGITAL SIGNAL PROCESSING PRODUCTS

DSP Microcomputer
with Host Interface Port
ADSP-2111 I

1IIIIIIII ANALOG

WDEVICES
FEATURES
Complete DSP Microcomputer
60 ns Instruction Cycle Time from 16.67 MHz Crystal
ADSP-21XX Family Code & Function Compatible
2K Words of On-Chip Program Memory RAM
1K Word of On-Chip Data Memory RAM
Host Interface Port Provides Simple Interface to 68000,
80C51, ADSP-2101 and Others
Separate Program and Data Buses On-Chip
Dual Purpose Program Memory for Both Instruction
and Data Storage
Three Independent Computational Units:
ALU, Multiplier/Accumulator and Barr
Two Independent Data Address Ge
Powerful Program Sequencer with
Zero Overhead L o o p i n g . ) . : ( ''',
Conditional Arithmetic Instruction ExecutiPn'~,.".f
Two Double-Buffered Serial Ports with Com~anding
Hardware and Automatic Data Buffering
Input and Output Flags
Programmable 16-Bit Interval Timer with Prescaler
Programmable Wait State Generation
Automatic Booting of Internal Program Memory from
Byte-Wide External Memory, e.g., EPROM
Automatic Booting of Internal Program Memory from
Host Port
Provisions for Multiprecision Computation and
Saturation Logic
Single-Cycle Instruction Execution
Single-Cycle Context Switch
Multifunction Instructions
Three Edge- or Level-Sensitive External Interrupts
Low Power Dissipation in Standby Mode
100-Pin PGA and 100-Lead POFP
MIL-STD-883 Compliant Version Available

GENERAL DESCRIPTION
The ADSP-2111 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high-speed numeric
processing applications. Its instruction set is a fully compatible
superset of the ADSP-2100 instruction set. It combines the complete ADSP-2100 architecture (three computational units, data
address generators and a program sequencer) with two serial
ports, a host interface port, a programmable timer, extensive
interrupt capabilities and on-chip program and data memory
RAM. The ADSP-2111 has IK words of (l6-bit) data memory
RAM and 2K words of (24-bit) program memory RAM on chip.

FUNCTIONAL BLOCK DIAGRAM

c::==:Ii::t:;~~1§;~~c==+:::j=+====r'

ADDRfSS
BUSES

~,";"""

Fabricated in a high-speed, 1.0 micron, double-layer metal
CMOS process, the ADSP-2111 operates with a 60 ns instruction cycle time. Every instruction executes in a single cycle.
Fabrication in CMOS results in low power operation.
The ADSP-211I's flexible architecture and comprehensive
instruction set support a high degree of operational parallelism.
In one cycle the ADSP-2111 can:
•
•
•
•
•
•
•

generate the next program address
fetch the next instruction
perform one or two data moves
update one or two data address pointers
perform a computational operation
receive and transmit data via the two serial ports
receive andlor transmit data via the host interface port

Development System
The ADSP-2111 is supported by a complete set of tools for software and hardware system development. The Development
Software is a set of modules that supports all ADSP-2100 family
processors. The System Builder provides a high-level method for
defming the architecture of systems under development. The
Assembler produces object code and the Linker combines object
modules and library calls into an executable fIle. The Simulator
provides an interactive instruction-level simulation with a reconfigurable user interface. A PROM Splitter generates PROM programmer compatible fIles. The C Compiler generates ADSP-211 I
assembly source code.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

REV. 0

DIGITAL SIGNAL PROCESSING PRODUCTS 9-29

II

ADSP-2111
Emulators aid in the hardware debugging of ADSP-Z111 systems. The full featured emulator performs a full range of
emulation functions including trace and triggering. EZ-Tools
are low cost, easy-to-use hardware tools. The EZ-ICE'" emulator provides basic ft!nctions like changing register values and
setting breakpoints. The EZ-LAB'" demonstration board
is a complete ADSP-Z111 system that executes EPROM-based
programs.
Additional Information
This data sheet provides a general overview of ADSP-Z111 functionality. For additional information on the .architecture and
instruction set of the processor, refer to the ADSP-ZIll User's
Manual. For more information about the Development System
and ADSP-Zl1l programmer's reference information, refer to
the ADSP-2100 Family Development Software Manuals and the
ADSP-2111 Emulator Manual.
ARCHITECTURE OVERVIEW
Figure I is an overall block diagram of the ADS
processor contains three independent co
ALD, the multiplier/accumulator (MAC)
computational units process 16-bit data d·
sions to support multiprecision computations. T
forms a standard set of arithmetic and logic opera
lSlon
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations. The
shifter performs logical and arithmetic shifts, normalization,
denormalization, and derive exponent operations. The shifter
can be used to efficiently implement numeric format control
including multiword floating-point representations.
EZ-ICE and EZ-LAB are trademarks of Analog Devices, Inc.

The internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units. The
sequencer supports conditional jumps, subroutine calls and
returns in a single cycle. With internal loop counters and loop
stacks, the ADSP-2111 executes looped code with zero overhead; no explicit jump instructions are required to maintain the
loop.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and program memory)
h DAG maintains and updates four address
e pointer is used to access data (indirect
-modified by the value of one of four possiers. A length value may be associated with each
automatic modulo addressing for circular
buffering feature is also used by the serial
atic data transfers;' these are described on the
erial Ports."
ansfer is achieved with the use of five internal
gram Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The two address buses (pMA and DMA) share a single external
address bus allowing memory to expanded off-chip, and the two
data buses (PMD and DMD) share a single external data bus.
The BMS, DMS and PMS signals indicate for which memory
space the external buses are being used.

Figure 1. ADSP-2111 Block Diagram
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

9-30 DIGITAL SIGNAL PROCESSING PRODUCTS

REV. 0

ADSP-2111
ADSP-2111-S2
Parameter

Min

Max

Unit

0.5teK - 15+w
0.75teK - 20+w

ns
ns
ns

Memory Read
Timing Requirement:
tRDD
tAA
tRDH

RD Low to Data Valid
AO-A13, PMS, DMS, BMS to Data Valid
Data Hold from RD High

0

Switching Characteristic:
tRP
teRD
tASR
tRDA
t RwR

RD Pulse Width
CLKOUT High to RD Low
AO-A13, DMS, PMS, BMS Setup before RD Low
AO-A13, DMS, PMS, BMS Hold after RD Deasserted
RD High to RD or WR Low

0.5tcK - 10+w
0.25teK - 10
0.25
IS
10
- 10

0.25teK + 10

ns
ns
ns
ns
ns

CLKOUT

AO-A13

D

II
WR

Figure 2. Memory Read

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

REV. 0

DIGITAL SIGNAL PROCESSING PRODUCTS 9-31

ADSP-2111
ADSP-2111-S2

Min

Parameter

Max

Unit

Memory Write
Switching Characteristic:
tDW
tDH
twp
tWDE
t ASW
tDDR
tcwR
tAW
tWRA
twwR

Data Setup before WR High
Data Hold after WR High
WR Pulse Width
WR Low to Data Enabled
AD-A13, DMS, PMS Setup before WR Low
Data Disable Jiefore WR or RD Low
CLKOUT High to WR Low
AD-A13 Setup before WR Deasserted
AD-A13, DMS, PMS Hold after WR Deasserted
WR High to RD or WR Low

0.5tcK - 20+w
0.25tcK - 10
0.5tcK - 10+w

o

0.25tcK + 10

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

CLKOUT

AO-A13

o

RD
Figure 3. Memory Write

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

9-32 DIGITAL SIGNAL PROCESSING PRODUCTS

REV. 0

r-III ANALOG

WDEVICES

IEEE Floating-Point DSP Microprocessor
ADSP-21020 I

FEATURES
20 MHz IEEE Floating-Point Processor
IEEE 32-Bit Single-Precision and 4O-Bit Extended
Single-Precision Floating-Point Formats
32-Bit Fixed-Point Formats. Integer and Fractional
Separate Program and Data Buses Extended Off-Chip
Dual Purpose Program Memory Contains Both
Instructions and Data
Three Independent Computation Units: ALU.
Multiplier. Shifter
Single-Cycle Parallel Operation of Multiplier and ALU
Two Independent Address Generators
Addressing Support for Page-Mode DRAMs
Powerful Program Sequencer
Zero Overhead Loops
Conditional Execution
32-Word. High-Performance Instruct. n C
Programmable Interval Timer
Programmable andlor Hardware-Controlled
Wait States
Alternate Register Sets for Single-Cycle Context
Switch
Large Instruction Set. Single-Cycle Instruction
Execution
Four Edge- or Level-Sensitive External Interrupts
Four InputlOutput Flags
50 ns Instruction Cycle Time
223-Pin PGA Package

2

GENERAL DESCRIPTION
The ADSP-ZlOZO is the first member of Analog Devices' family
of single-chip, programmable, IEEE floating-point processors
optimized for digital signal processing applications. Its architecture is similar to that of Analog Devices' ADSP-ZIOO family of
fixed-point DSP processors.
The ADSP-ZIOZO features:
• Independent Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier and shifter perform single-cycle instructions. The units are architecturally
arranged in parallel, maximizing computational throughput. A
single multifunction instruction executes parallel ALU and
multiplier operations. These computation units support IEEE
single-precision (32-bit) floating-point, extended 40-bit
floating-point and 32-bit fixed-point data formats.

SIMPLIFIED BLOCK DIAGRAM

ARITHMETIC UNITS

INSTRUCTION
CACHE
I ALU
PROGRAM
SEQUENCER

IIMULTlPLlERI~
REGISTER FILE

-liii+-t....:..:;======:::j-+--~ EXTERNAL
ADDRESS

......;-'t-+-:D::AT::-A::ME::M::O:::RY~A::D:::DR::ESS::::----l---l---'\.

BUSES

_t-_,;"PfI;;,:O:,;;G;,;;RA.::M;,;;M=EM:::O::;R,;"YD;;;A::;TA=---_-I-J......_..J EXTERNAL

::--.l---::D:::AT::A-:'M:::EM::::O:::RY~D::A~TA:----..J....,"""--,\

DATA
BUSES

e-Cycle Fetch of Instruction and Two Operands
The ADSP-21020 uses a modified Harvard architecture in
which data memory stores data and program memory stores
both instructions and data. Because of its separate program
and data memory buses and its high-performance instruction
cache, the processor can fetch an operand from data memory,
an operand from program memory, and an instruction from
the cache simultaneously.
• Hardware Circular Buffers
The ADSP-21020 provides hardware to implement circular
buffers in memory, which are common in digital ruters and
Fourier transform implementations. It handles address pointer
wraparound, reducing overhead (thereby increasing performance) and simplifying implementation. Circular buffers can
start and end at any location.
• Flexible Instruction Set
The ADSP-21020's 48-bit instruction word accommodates
a variety of parallel operations, for concise programming.
For example, the ADSP-21020 can conditionally execute a
computation, a data memory access and a branch in a single
instruction.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

REV. 0

DIGITAL SIGNAL PROCESSING PRODUCTS 9-33

II

ADSP-21 020
ARCHITECTURE OVERVIEW
Figure 1 is a block diagram of the ADSP-2l020. The processor
features:
• Three Computation Units-ALU, Multiplier and Shifter
- with a shared data register fIle
• Two Address Generators
• Program Seql):encer with Instruction Cache
• Timer
• Memory Buses and Interface
Computation Units
The ADSP-2l020 contains three independent computation units:
an ALU, a multiplier with fIxed-point accumulator and a
shifter. For meeting a wide variety of processing needs, the
computation units process data in three formats: 32-bit fIxedpoint, 32-bit floating-point and 4O-bit floating-point. The
floating-point operations are single-precision IEEE-compatible
(IEEE Standard 754/854). The 32-bit floating-point format is the
standard IEEE format, whereas the 40-bit IEEE extendedprecision format has eight more LSBs of mantissa for add' .
accuracy.
The multiplier performs floating-point
cation as well as fIxed-point multiply/ad
operations. Integer products are 64 bits w ,a
tor is 80 bits wide. The ALU performs 45 stan
gand logic operations, supporting both fIxed-point a
point formats. The shifter performs 19 operations; including
logical and arithmetic shifts, bit manipulation, fIeld deposit, and
extract and derive exponent operations, on 32-bit operands.
The computation units perform single-cycle operations; there is
no computation pipeline. The units are connected in parallel
rather than serially. The output of any unit may be the input of
any unit on the next cycle.

In a multifunction computation, the ALU and multiplier perform
independent simultaneous operations. A 10-port register fIle is
used for transferring data between the computation units and
the data buses, and for storing intermediate results. The register
fIle has two sets (primary and alternate) of sixteen 4O-bit registers each, for fast context switching. The primary or alternate
set of each half of the register fIle (top eight or bottom eight
registers) is selected independently.
Address Generators and Program Sequencer
Two dedicated address generators and a program sequencer supply addresses for memory accesses. Thus the computation units
never need to be used to calculate addresses. Because of its instruction cache, the ADSP-21020 can simultaneously fetch an
instruction and a ss data in both off-chip program memory
and off-chip
emory in a single cycle. If the instruction is
is no need to halt or wait for data.
in the
nerators (DAGs) provide memory addresses
ory data is transferred over the parallel meminternal registers. Dual data address generarocessor to output two simultaneous addresses
erand reads and writes. DAG 1 supplies 32-bit admemory. DAG2 supplies 24-bit addresses to profor program memory data accesses.
keeps track of up to eight address pointers, eight
'fIers, eight length values and eight base values. A pointer
used for indirect addressing can be modified by a value in a
specified register, either before (pre-modify) or after (postmodify) the access. To implement automatic modulo addressing
for circular buffers, the ADSP-2l020 provides length values that
can be associated with each pointer. Base values for pointers
allow relocatable data storage. Each DAG register has an alternate register that cm be activated for fast context switching.

24

32

DMDaus

PMDBUS

40
:J2.. OR 4O-BIT
DATA MEMORY

Figure 1. ADSP-21020 Block Diagram

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

9-34 DIGITAL SIGNAL PROCESSING PRODUCTS

REV. 0

ADSP-21 020
The program sequencer supplies instruction addresses to the
program memory. It controls loop iterations and evaluates conditional instructions. To execute looped code with zero overhead, the ADSP-21020 maintains an internal loop counter and
loop stack. No explicit jump instructions are required to loop or
to decrement and test the counter.
The ADSP-21020 derives its high clock rate from pipelined
fetch, decode and execUle cycles. External memories have more
time to complete an access than if there were no decode cycle;
consequently, ADSP-21020 systems can be built using slower
and therefore less expensive memories.
The program sequencer includes a high-performance instruction
cache. This 2-way, set associative cache holds 32 instructions.
Only the instructions whose fetches conflict with program memory data accesses are cached, so the ADSP-21020 can perform
a program memory data access and execute the corresponding
instruction in the same cycle. The program sequencer fet
the instruction from the cache instead of program
the ADSP-21020 can simultaneously access da .
memory.

Interrupts

The ADSP-21020 has four external hardware interrupts, nine
internally generated interrupts and eight software interrupts.
For the external user interrupts and the internal timer interrupt,
the ADSP-21020 automatically stacks the arithmetic status and
mode (MODEl) registers in parallel with servicing the interrupt, allowing four nesting levels of very fast service for these
interrupts.
An interrupt can occur at any time while the ADSP-21020 is
executing a program. Internal events that generate interrupts
include arithmetic exceptions, allowing fast trap handling and
recovery.
em
supponed with a complete set of software
pment tools. The ADSP-21020 Develops development software for software design
hardware debugging.

II

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

REV. 0

DIGITAL SIGNAL PROCESSING PRODUCTS ~35

ADSP-21 020
Max

Parameter

Min

Memory Read

20 MHz (50 ns)

15 MHz (66 ns)

Frequency Dependency
TcK = T ns; DT = T - 50 ns

11
0

17

0

11+3DT/8
0

Switching Characteristic
Address, Select valid to xRD
tDARL
xRD deasserted to Address, Select invalid
tDRHA
CLKIN rising edge to Address valid
t DCKA
t DAP
Address valid to xPAGE valid
CLKIN rising edge to xPAGE valid
t DCKP
CLKIN rising edge to xRD deasserted
tDCKR
Timing Requirement
Data Valid to CLKIN rising edge
tRDDV
CLKIN rising edge to Data invalid
tHRD
Address, Select valid to external Data valid
tDAD
xRD asserted to external Data valid
tDRLD.
tDRHDZ xRD deasserted to Data high impedance
xRD deasserted to Data invalid
tHDRH
Address valid to xACK valid
tDAAK
xRD asserted to xACK valid
tDRAK
xACK valid to CLKIN rising
tSAK
xACK invalid to CLKIN rising edge
tHAK

Min

Max

18

16

4

4

21
11

19
9

Min

Max

ns
ns

18-DT/8
4
21-DT/8
11-DT/8

4

4+DT/8
8-DT/8

8

36+DT

25+5DT/8
15+7DT/16

0
0

Unit

21+7DT/8
8+DT/2
11-DT/4

ns
ns
ns

ns

ns
ns
ns
ns

ns
ns
ns
ns

ns
2-DT/4

ns

x = PM or DM; Select = PMS1-O, DMS3-O

\'-------_.....A:

ClKlN
OAAK

:

!4------~..
~'
ADDRESS,
SELECT

-

tDCKA

ill

l

I

!

'
!
!

.:

DD

,PAGE

:

!
:
~

t DARL

t ......... K

"~4 ~

'

:

..I

,I

-----.! ~ tORtiA

i

----------~!--------~UL·.·::.:,------~!------------~i·----J~~"~re~~~-----!
'i
! Ii
I'
r i,"l·:.
1

I.
·
:

DATA

,I

'OAD

;.

:

ORLa

! '

________________________-rI___R_MW~~

i

INPlIT

!
:

:..

:

'/fRO

~,
Ii,'

~,'.
~M

\AAAN~----uu~+!-----+i~~~
: ~ ~tHDRH

!

xACK

.' :
----...i l..;

t
SAK

!!

~
l

:+-- tHAK

"i

------------------------~d_;____~~~--------

SELECT. PUS1-O, DMS3-0
._PMorDM

Figure 2. Memory Read Timing

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

9-36 DIGITAL SIGNAL PROCESSING PRODUCTS

REV. 0

ADSP-21 020
Parameter

Min

Memory Write

20 MHz (50 ns)

15 MHz (66 ns)

Frequency Dependency
tcK = T ns; DT = T - 50 ns

36
10
25
17

52
16
34
25

36+ 15DT/16
10+3DT/8
25+9DT/16
17+DT/2

Switching Characteristic
Address, Select valid to xWR deasserted
tDAWH
Address, Select valid to xWR asserted
t DAWL
xWR pulse width
tww
Data valid to xWR deasserted
tDDWH
CLKIN rising edge to Data valid
t wonv
CLKIN rising edge to Data low impedance
t DDZL
xWR deasserted to Address, Select invalid
t DWHA
xWR deasserted to Data high impedance
tnwHDZH*
CLKIN rising edge to Address valid
t DCKA
Address valid lO xPAGE valid
tDAP
CLKIN rising edge to xPAGE valid
t DCKP
CLKIN rising edge to xWR deasserted
tDCKW
Timing Requirement
Address valid to xACK valid
tDAAK
xWR valid to xACK vali
t DWAK
xACK enabled to CLKIN
tSAK
xACK disabled to CLKIN ns'
tHAK

Min

Max

38

Min

Max

Max

43

38+5DT/16

18

18+5DT116
2+DT/16
4+DT/16

2
4

35
16

15+DT/16
18-DT/8
4
21-DT/8
7-3DT/16
21 + 7DT/8
8+DT/2

11+DT/4
6

2+DT/4

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

x = PM or DM; Select = PMSI-O, DMS3-o. _ _
*tDWHDZH is the time from the rising edge of xWR to when the ADSP-21
stops driving the data bus, until the next write or read cycle. In between the two
memory accesses, the data output remains valid on the output bus for a time determined by the system's total bus capacitance and the total leakage current.

ClKIN

ADDRESS.
SELECT

•

~

S4-

,PAGE

:

:

i

i

i:!.••::

I
i.

:!, ....

i..
I
I

DATA
OUTPUT

I

1

DAWl

: - - -.....-::,

:

1...

i"

'

-II
..~l I DCKP

,..'..

DAP

DAWH

i "'1

!

'ww

!. . i
~

1

t

_

i

io--+jJ

t

~

__ I

t
:
DWAK .. :

~

,\.:..___-+1________

-

WODV
t

..

L.-!---,

-+1...../1.:.

.:i

~

---<~

_ _ _ _-+-1

I:.

)

'SAK

DWHD~

!

:

---1 ..;:t--~i..o---------+-~..
j

SELECT

I

!

i

.,i ,..'..o-_'..=D;:.DWH=_;--...-i;. .I. -....-i. ,

DDn

IDWHA

DCKW

:

i.

xACK

II

: :

tHAI(

------------~~~i------~~~---

=PMS1-O, DMsa-O

x_PUorDM

Figure 3. Memory Write Timing
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

REV. 0

DIGITAL SIGNAL PROCESSING PRODUCTS ~37

9-38 DIGITAL SIGNAL PROCESSING PRODUCTS

Other Products
Contents
Page

Other Products - Section 10 ....................................................

10-1

Analog-to-Digital Converters Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
Digital-to-Analog Converters Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
Operational Amplifiers Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16

II

OTHER PRODUCTS 10-1

~

Selection Guide

0

Analog-to-Digital Converters

~

~
~

0
tl

Sampling Converters

c:
C')
CiI
Model

Through- SHA
put Rate BW
Res kSPS
kHz
typl
Bits max

AD7821
AD7820
AD7569

8
8
8

AD7669

lOOO

Reference
Volt
IntIExt'

Bus Interface
Bits3

Package
Options4

8,,..P

Temp
Ranges

500
400

100
14
200

0-5 V, Ext
0-5 V, Ext
Int

8, fLP
8, ....p

2, 3, 4, 5, 6 I, M
2, 3, 4, 5, 6 I, M
2, 3, 4, 5, 6 C, I, M

8

400

200

Int

8, ....p

2,5,6

C,I,M

AD7769

8

400

200

Ext

8, ....p

2,5

C

AD7824
AD7828
AD7575
*AD7776

8
8
8
10

400
400
190
500

10
10
50
SO

0-5 V, Ext
0-5 V, Ext
1.23 V, Ext
2.0 V, IntlExt

8, ....p
8, ....P
8, fLP
10, ....p

2,3,6
2,3,4,5
2,3,4,5
2,6

C,I,M
C,I,M
C,I,M
C,I

*AD7777

10

500

SO

2.0 V, IntlExt

10, ,..P

2,6

C, I

*AD7778

10

500

SO

2.0 V, IntlExt

10, ....p

10

C, I

AD7579
AD7580
AD9003
*AD1671
*AD7886
AD678

10
10
12
12
12
12

50
50
1000
1250
750
200

25
25
10000
2000
1000
1000

2.5 V, Ext
2.5 V, Ext
Int
2.5 V, Int
5 V, Ext
5 V, Int

8, ....p
10, ,..P
12
12
12, ,..P
8112, ....p

2,3,4,5
2,3,4,5
8
1,2,4,5
2,3,5
1,2,14

C,I,M
C,I,M
C
C,I,M
C,I
C,I,M

*AD1341
*AD7893
*AD7892
AD1332

12
12
12
12

ISO
140
140
125

150
70
70
125

10 V, Int
2.5 V, Ext
2.5 V, Ext
-5 V, Int

16, ....p
Serial
81121SeriaI, ....P
12, ,..P

12
2,3,6
2, 3, 6
1

C,M
I,M
I,M
I,M

*AD7874

12

29

500

Int (+3 V), Ext

12, ....p

2,3,4,6

C,I,M

AD7870
*AD7875
*AD7876
AD7878
*AD1674

12
12
12
12
12

100
100
100
100
100

500
500
500
500
500

3 V, Int
3 V, Int
3 V, Int
3 V, Int
10 V, Int

8112/Serial,,..p
8112/Serial,,..p
81121SeriaI,,..p
12, ....p
8112, ....p

2,3,4,5
2,3,5
2,3,6
2,3,4,5
1,2,6

C,I,M
C,I,M
I,M
C,I,M
C,I,M

*AD7890
*AD7891

12
12

100
100

SO
50

2.5 V, Ext
2.5 V, Ext

Serial
12, ,..p

2,3,6
10

I,M
I,M

Page6

Comments

cn
ClI
Cn
cn
cn
cn
cn
ClI
cn
cn
cn
cn
cn
cn
ClI
cn
cn
cn
cn
cn

CMOS, Bipolar or Unipolar Operation
CMOS, 8-Bit Sampling ADC
CMOS, Complete 110 Port with DAC, ADC,
SHA, Amps and Reference
CMOS, Complete 110 Port with 2 DACs,
ADC, SHA, Amps and Reference
CMOS, Complete 2-Channel 110 Port with
Input/Output Signal Conditioning
CMOS, 4-Channel, 8-Bit Sampling ADC
CMOS, 8-Channel, 8-Bit Sampling ADC
CMOS, Low Cost
CMOS, Single Channel Complete Sampling ADC,
Single Supply, Twos Complement Outpot Code
CMOS, 

Selection Guide

~

Operational Amplifiers

3l

Low Cost, General Purpose Amplifiers

0

9.l
0
0

?i

Settling
Time

Cil
Model
OP-I77
AD707
AD705
AD704
AD706
*OP-497
OP-77

Vos
mV
max

VosTC
,..Vf'C
max

0.01~.06

0.1-1.2
0.1-1
0.6-2.0
0.6-1.5
1.G-1.5
0.5-1.5
0.3-1.2
0.6-2.5
0.6-2.5
0.6-2
1.5
1.5
0.9-2
2-20
5-20
5-20
8-10
IG-15
IG-15
8-20
8-20
8-20
10
10
20

0.01~.09

0.02~.09
0.~.10
0.~.10
0.0~.15

0.02~.1

ADOP~7

0.02~.15

OP~7

0.02~.15

OP-97
PM-I012
PM-I008
OP-05
AD548
AD542
AD544
OP-02
OP-ll
OP-09
OP-Ol
OP-04
OP-14
*OP-282
*OP-482
AD741

0.02~.2

0.03~.05

0.12
0.15-1.3
0.25-2
0.5-2
0.5-2
0.5-5
0.5-5
0.5-5
0.7-5
0.75-5
0.75-5
1.5
2.5
3-6

MHz

SR
V/,..s

0.01%

Noise
,..Vp-p
0.1-10 Hz

typ'

typ

typ

typ

0.6
0.9
0.8
0.8
0.8
0.5
0.6
0.6
0.6
0.9
0.5
0.5
0.6
1
I
2
1.3
3
3
2.5
1.3
1.3
4
4
1

0.3
0.15
0.15
0.15
0.15
0.15
0.3
0.17
0.3
0.2
0.2
0.2
0.3
1.8

IB

BW

nA

max
1.5-2.8
1-2.5
0.1~.15
0.1~.25
0.1~.25
0.1~.2

2-2.8
3-12
2-12
0.1~.15
0.1~.15

0.1
2-3
0.01~.02

0.025~.05
O.O25~.O5

3G-l00
30G-500
30G-500
3G-l00
5G-I00
5G-I00
0.1
0.1
2OG-500

3
13

0.5
1
1
18
0.5
0.5
9
9
0.5

,..S

8
8

0.35
0.23
0.5
0.5
0.5
0.3
0.35
0.3~.38

8

0.35
0.5
0.5
0.5
0.35
2
2
2
0.65
0.7
0.7
0.65
0.65
1.3
1.3

Package
Options2

Temp
Range'

2,3,6
2,3,6,7
2,3,6
2,3,6
2,3,6
2,3,4,6
2,3,4,6,7
2,3,6,7
2,3,4,6,7
2,3,4,6,7
2,3,6,7
2,3,7
2,3,7
2,3,6,7
7
7
2,3,7
2,3,4,6
3
2,3,7
3,7
2,3,6,7
2,3,6
2,3,6
2,7

I,M
C,I,M
C,I,M
C,I,M
C,I,M
I,M
C,I,M
C,M
C,I,M
I,M
I,M
C,M
C,M
C,I,M

e,M
e,M
C,M
C,I,M
C,M
C,M
I,M
I,M
I
I

e,.!, M

Page4

Comments

P
L
L
L
L
D
P
L
P
P
P
P
P
L
L
L
P
P
P
P
P
P
D
D
L

Highest Precision Perfonnance
Very High DC Precision
Low IB Precision Bipolar
QuadAD705
Dual AD705
Quad OP-97
Next Generation OP-07
Improved Industry Standard
Industry Standard Precision
Low Power, Low IB OP-07
Low Power, Low IB
Low Power Precision
Instrumentation Operational Amplifier
Low Power, High Perfonnance
High Performance BiFET
High Performance BiFET
Improved "741"
Improved Quad "741"
Improved "4136," Quad
Inverting, High Speed
Improved "747"
Improved "1458," Dual
Dual, High Speed, Low Power
Quad, High Speed, Low Power
Improved Second Source

Low PowerlMicropower Amplifiers
Model
OP-22
OP-32
OP-90
OP-290
OP-20
OP-490
OP-220
ADs48
OP-80
OP-420
OP-21
*OP-282
AD648

PM-lOOS
OP-97
AD70S
PM-IOl2
OP-221
OP-41
*OP-482
OP-43
AD706
*OP-297
OP-200
OP-421
AD704
*OP-497
OP-400

o

~

g]
~

~

ISY

Vos

IB

GBW

SR

max
rnA

max

max
nA

typ
MHz

typ

0.1~.7s

5-10
5-10
15-25
15-25
25-40
15-25
26-30

0.2~.2

0.01~.02

0.25
4.5
0.02
0.02
0.1
0.02
0.2
1.0
0.3
0.15
0.6
4
1.0
3.5
0.9
0.8
0.5
0.6
0.5
4
2.4
0.8
0.5
0.5
1.9
1.0
0.5
0.5

0.0002~.4

0.0005-2
0.02
0.04
0.08
0.08
0.17
0.2
0.325
0.36

mV
0.3-1
0.3-1
0.1~.4s
O.~.S

0.25-1
0.5-1

1.5
2.5-6

0.OOO2~.OOI

0.~.4

o.I~.S

0.5
0.4
0.6
0.6
0.6
0.6
0.8
I
1.0
1-1.2
1.2
1.25
1.45
1.8
2.4
2.5
2.9

2.0
0.4-2.0
0.12

20-40
106-150
0.1
0.005-.01
0.1

0.02~.07s

O.I~.ls

0.02~.09

O.I~.ls

0.03~.OS

O.I~.ls

o.I~.s

80-120

0.25-2
3.0
0.25-1.5

0.1

O.O~.I

0.1l~.2

0.OO~.02
0.OO~.02S

0.~.2

0.1~.2

0.07~.2

2-5
56-ISO
0.15-0.17

2.5-6
0.07~.ISO
O.O~.ls

0.1~.2

0.1~.3

3-7

V/p.s
0.08
1.5

0.05
0.05
1.8
0.4
0.05
0.25
9
1.8
0.2
0.2
0.15
0.2
0.3
1.3
9
6
0.15
0.15
0.15
0.5
0.15
0.15
0.15

Package
Options'
2,3,6,7
2,3
2,3,4,6
2,3,4,6
2,3,4,6
2,3,4,6
2,3,6,7
2,3,7
2,6,7
2,3,4,6
2,3,6,7
2,3,6
2,3,7
2,3,6,7
2,3,4,6,7
2,3,6
2,3,6,7
2,3,6,7
2,6,7
2,3,6
2,7
2,3,6
2,3,4,6
2,3,4,6
2,3,6
2,3,6
2,3,4,6
2,3,4,6

Temp
Range'
I,M
I,M
I,M
I,M
I,M
I,M
I,M
C,I,M
I,M
I,M
I,M
I
C,I,M
C,M
I,M
C,I,M
C,I,M
I,M
I,M
I
I,M
C,I,M
I,M
I,M
I,M
C,I,M
I,M
C,I,M

Page4
P
P
P
P
P
P
P
L
P
P
P
D
L
P
P
L
P
P
P
D
P
L
D
P
P
D
D
P

Comments
Programmable, Single Supply
Fast, Programmable AVCL'" 10, Single Supply
Micropower, Low Voltage Single Supply
Dual, Micropower, Low Voltage, Single Supply
Micropower, Single Supply, Low Cost
Quad, Micropower, Low Voltage, Single Supply
Dual, Low Cost, Micropower, Single Supply
Precision Low Power BiFET Op Amp
LowIB,CMOS
Quad, Low Cost, Micropower, Single Supply
Low Cost, Low Power, Single Supply
Dual, High Speed
Dual, Precision Low Power BiFET Op Amp
Low Power
Precision, Low IB
Picoampere Input Current Bipolar Op Amp
Precision, Low IB
Dual, Low Cost, Low Power, Single Supply
Low Power, Low IB
Quad, High Speed
Fast, Low Power, Low IB
Dual, Picoampere Input Current Bipolar Op Amp
Dual, Precision, Low IB
Dual, Precision
Quad, Low Cost, Low Power, Single Supply
Quad, Picoampere Input Current Bipolar Op Amp
Quad, Highest Precision, Low Power
Quad, Precision

IUnity gain small signal bandwidth.
'Package Options: I ~ Hermetic DIP, Ceramic or Metal; 2 ~ Plastic or Epoxy Sealed DIP; 3 ~ Cerdip; 4 ~ Cerantic Leadless Chip Carrier; 5 ~ Plastic Leaded Chip Carrier; 6 ~ Small Outline "SOIC" Package;
7 ~ Hermetic Metal Can; 8 ~ Hermetic Metal Can DIP; 9 ~ Ceramic Flatpack; 10 ~ Plastic Quad Flatpack; 11 ~ Single-In-Line "SIP" Package; 12 ~ Ceramic Leaded Chip Carrier; 13 ~ Nonbennetic Ceramid
Glass DIP; 14 ~ J-Leaded Cerantic Package; 15 ~ Ceramic Pin Grid Array; 16 ~ TO-92; 17 ~ Plastic Pin Grid Array.
'Temperature Ranges: C ~ Commercial, O"C to +7O"C; I ~ Industrial, -40°C to +85°C (Some older products -25"C to +85°C); M ~ Military, -55°C to + 125°C.
·C I ~ Data Converter Reference Manual, Volume I; C II ~ Data Converter Reference Manual, Volume II; D ~ Data sheet available, consult factory; L ~ Linear Products Databook; P ~ Precision Monolithics
Division Databook.
Boldface Type: Product recommended for new design.
*New product.

(jj

~

iii

?

Selection Guide

0

:i!

Operational Amplifiers

~

Low Input Current Amplifiers

I::l
!;:l

0
0

~
Model

IB
pA
max

AD549
AD515A
OP-80
AD546
AD645
AD545A
OP-41
AD548
OP-43
AD547
PM-155A
PM-156A
PM-157A
OP-15
OP-16
OP-17

0.06-0.25
0.075-0.3
0.25-1
0.5-1
1.5-3
1-2
5-20
10-20
5-25
25-50
50
50
50
50-200
50-200
50-200

Ci1

Input Impedance
Differential Common Mode
1lllpF
typ

f=l kHz
typ

1013111
10 1311l.6

1015110.8
10 15110.8

62
62

1013111
1013111
101311l.6

10'5110.8
1014113
10 15 110.8

62
94
62
98

10'2113

3 x 10'2113

CMRR
dB

0.25-1
1-3
1.5
1-2
0.25-0.5
0.25-1
0.25-2
0.25-2
0.25-1.5
0.25-1
2
2
2
0.5-3
0.5-3
0.5-3

90

10 12116

84

98
60
90
90
90

10 121113

Vos
mV
max

90
90
90

Vos
TC

. . vrc

max
5-20
15-50
20
1-5
3-25
5-10
2-20
5-10
1-5
5
5
5
5-15
5-15
5-15

BW
MHz
typ'

Package
Options2

Temp
Rangel

Page'

Comments

1
1
0.3
1
2
1
0.5
1
2.4
1
2.5
4.5
20
6
8
30

7
7
2,6,7
2
2,7
7
2,6,7
2,3,6,7
2,7
7
3,7
3,7
3,7
2,3,6,7
2,3,6,7
2,3,6,7

C,M
C
I,M
C
C,I,M
C
C,I,M
C,I,M
I,M
C,M
C,M
C,M
C,M
C,I,M
C,I,M
C,I,M

L
L
P
L
L
L
P
L
P
L
P
P
P
P
P
P

Monolithic, Lowest IB
Lower Cost AD515 Replacement
Low Cost CMOS
Precision Low Cost Electrometer
Low Noise, Precision BiFET
Lower Cost AD545 Replacement
High Stability JFET
Low Power, Low Cost
Low I B, Fast AVCL ;" 3
Low Drift
Improved Industry Standard
Improved Industry Standard
Improved Industry Standard
Precision BiFET
Precision BiFET
Fast, Precision BiFET

Quad Operational Amplifiers
Model
AD704
*OP-497
OP-400
OP-470
OP-490
OP-ll
*OP-482
PM-148/248

OP-421
OP-420

Vos
mV
max
0.05-0.10
0.05-0.15
0.15-0.3
0.4-1
0.5-1
0.5-5
3.0
2.5
2.5-6
2.5-6

Vos
TC

. . vrc

max
0.6-1.5
0.5-1.5
1.2-2.5
2-4
5
10-15
10
10-15
10-25

IB
pA
max

BW
MHz
typ'

150-250
150-200
3-7
25-60
15-25
300-500
0.1
75
50-150
20-40

0.8
0.5
0.5
6
0.02
3
4.0
0.8
1.9
0.15

Slew
Rate
V/ ....s
typ

Settling
Time 0.01%
to 0.01%
....styp

0.15
0.15
0.15
2
1
9
0.4
0.5
0.05

1.5

Package
Options2

Temp
Rangel

Page'

Comments

2,3,6
2,3,4,6
2,3,4,6
2,3,4,6
2,3,4,6
2,3,4,6
3,4,6
3
2,3,6
2,3,4,6

C,I,M
I,M
C,I,M
C,I,M
I,M
C,I,M
I
I,M
I,M
I,M

L
D
P
P
P
P
D
P
P
P

Quad AD705, Low IB Precision Bipolar
Low Power, Low IB Precision Bipolar
Quad Monolithic, Precision
Quad Monolithic, Low Noise
Micropower, Low Voltage, Single Supply
Improved Quad "741"
High Speed, Low Power
Improved Industry Standard
Low Power, Low Cost, Single Supply
Micropower, Low Cost, Single Supply

Dual Operational Amplifiers

Model

Vos
mV
max

Vos
TC
f.lV/oC
max

IB
nA
max

BW
MHz
typl

Slew
Rate
Vlf.ls
typ

AD70S

0.03-0.1

0.3-1.0

1-2.5

0.9

0.05-0.10
0.05-0.2
0.075-0.2
0.075-0.25
0.08-0.18
0.1-0.2
0.15-0.5
0.15-0.75
0.2-0.5
0.25-1
0.25-1
0.3-2
0.5
0.5-2
0.5-2
0.75-5
1-4
2.0

0.6-1.5
0.6-2
0.5-2
1-3
1-1.S
1.3-1.S
1.5-3
1.5-3
3-5
2.5-10
3-20
3-20
2-4.5

0.15-0.25
0.1-0.2
2-5
20-60
40-80

AD706
*OP·297
OP-200
OP-270
OP-227
OP-207
OP-221
OP-220
OP-290
AD647
AD746
AD648
OP-lO
AD642
AD644
OP-14
OP-215
*OP-282

8-20
10
10

3-7
80-120
20-30
15-25
0.035-0.075
0.15
0.01-0.02
3-7
0.035-0.075
0.035-0.075
50-100
0.1-0.3
0.1

Settling
Time
to 0.01%
f.ls
typ

Package
Options 2

Temp
Range'

Page 4

Comments

0.3

2,3,7

C,I,M

L

0.8
0.5
0.5
5
8
0.6
0.6
0.2
0.02

0.15
0.15
0.15
2.4
2.S
0.2
0.3
0.05

13

75
1.8
0.17

2,3,6
2,3,6
2,3,4,6
2,3,4,6
3
3
2,3,6,7
2,3,6,7
2,3,4,6
4, 7
2,3,7
2,3,7
3
7
7
2,3,6,7
2,3,4,6,7
3,4,6

C,I, M
I,M
I,M
I,M
I,M
C,M
C,I, M
C,I,M
I,M
C,M
C, I,M
C, I,M
C,M
C,M
C,M
I, M
C, I,M
I

L
D
P
P
P
P
P
P
P
L
L
L
P
L
L
P
P
D

Highest DC Precision; Excellent
Matching Between Amps, Dual AD707
Dual AD705, Low IB Precision Bipolar
Precision, Low Power, Low IB
Dual Monolithic, Precision
Dual Monolithic, Low Noise
Dual Matched, Low Noise
Dual Matched, Precision
Low Power, Single Supply
Micropower, Single Supply
Micropower, Low Voltage Single Supply
Dual AD547
Precision, Fast Settling, Dual AD744
Low Power, BiFET, Dual AD548
Dual Matched, Precision
Dual AD542
Dual AD544
General Purpose, Low Cost
High Speed, Precision
High Speed, Low Power

0.6
2

1.3
5.7
4.0

13
0.5
18
9

0.5
8

0.9-0.1
1.5

IUnity gain small signal bandwidth.
lPdckage Options: 1 = Hermetic DIP, Ceramic or Metal; 2 = Plastic or Epoxy Sealed DIP; 3 = Cerdip; 4 = Ceramic Leadless Chip Carrier; 5 = Plastic Leaded Chip Carrier; 6 = Small Outline "sole" Package;
7 = Hermetic Metal Can; 8 = Hermetic Metal Can DIP; 9 = Ceramic Flatpack; 10 = Plastic Quad Flatpack; 11 = Single-In-Line "SIP" Package; 12 = Ceramic Leaded Chip Carrier; 13 = Nonhermetic Ceramic!
Glass DIP; 14 = J-Leaded Ceramic Package; 15 = Ceramic Pin Grid Array; 16 = TO-92; 17 = Plastic Pin Grid Array.
3Temperature Ranges: C = Commercial, ODC to +70°C; I = Industrial, -40°C to +85°C (Some older products -25°C to +85°C); M = Military, -55°C to +125°C.
4C I = Data Converter Reference Manual, Volume I; C II = Data Converter Reference Manual, Volume II; D = Data sheet available, consult factory; L = Linear Products Databook; P = Precision Monolithics
Division Databook.
Boldface Type: Product recommended for new design.
*New product.

o

J!

9:l
]
oQ
c:
(")
i;l

~

II

~

Selection Guide

~

Operational Amplifiers

~
~

Unity Gain Buffers

~
Ci!

Model
AD9630
AD9620

-3 dB
BW
MHz
typ

750
600

Rise

SR
V/p.s
min

Settling
Time
to 0.02%
nstyp

Time
IV Step
nstyp

rnA

1800
2200

8
8

0.9
0.8

loUT

Iss
rnA

min

Vos
mV
typ

max

Package
Options l

Temp
Range2

Page'

Comments

50
40

3
2

26
48

2,3,6,12
I

I,M
I,M

L
L

High Performance, Wideband Buffer
High Performance, Low Harmonic Distortion Buffer

'Package Options: I = Hermetic DIP, Ceramic or Metal; 2 = Plastic or Epoxy Sealed DIP; 3 = Cerdip; 4 = Ceramic Leadless Chip Carrier; S = Plastic Leaded Chip Carrier; 6 = Small Outline "SOIC" Package;
7 = Hermetic Metal Can; 8 = Hermetic Metal Can DIP; 9 = Ceramic Flatpack; 10 = Plastic Quad Flatpack; II = Single-In-Line "SIP" Package; 12 = Cerantic Leaded Chip Carrier; 13 = Nonhermetic Ceramic!
Glass DIP; 14 = J-Leaded Ceramic Package; IS = Ceramic Pin Grid Array; 16 = T0-92; 17 = Plastic Pin Grid Array.
'Temperature Ranges: C = Commercial, O"C to + 70"C; I = Industrial, -4O"C to +8S"C (Some older products -2S"C to +8S"C); M = Military, -SS"C to + 12S"C.
I = Data Convener Reference Manual, Volume I; C II = Data Convener Reference Manual, Volume II; D = Data sheet available, consult factory; L = Linear Products Databook; P = Precision Monolitbics
Division Databook.
Boldface Type: Product recommended for new design.
"New product.

'c

Application Notes
Contents
Page

Application Notes - Section 11 .................................................. 11-1
AN-IS - Minimization of Noise in Operational Amplifier Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
AN-102 - Very Low Noise Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
AN-lOS - Applications of the MAT-04, A Monolithic Matched Quad Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
AN-lll - A Balanced Summing Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27
AN-112 - A Balanced Input High Level Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
AN-I 13 - An Unbalanced, Virtual Ground Summing Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31
AN-114 - A High Performance Transfonner - Coupled Microphone Preamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33
AN-llS - Balanced, Low Noise Microphone Preamplifier Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35
AN-1l6 - AGe Amplifier Design with Adjustable Attack and Release Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37
AN-121- High Performance Stereo Routing Switcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39
AN-122 - A Balanced Mute Circuit for Audio Mixing Consoles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43
AN-123 - A Constant Power "Pan" Control Circuit for Microphone Audio Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4S
AN-124 - Three High Accuracy RIAAlIEC MC and MM Phono Preamplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-47
AN-12S - A Two-Channel Dynamic Filter Noise Reduction System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1l-S3
AN-127 - An Unbalanced Mute Circuit for Audio Mixing Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ll-SS
AN-12S - A Two-Channel Noise Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-57
AN-129 - A Precision Sum and Difference (Audio Matrix) Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-59
AN-130 - A Two-Band Audio Compressor/Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-61
AN-13l - A Two-Channel VCA Level (Volume) Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-63
AN-133 - A High-Perfonnance Compandor for Wireless Audio Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-65
AN-134 - An Automatic Microphone Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-69
AN-13S - The Morgan Compressor/Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-73
AN-136 - An Ultralow Noise Preamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I1-Sl
AN-142 - Voltage Adjustment Applications of the DAC-SSOO TrimDAC", an Octal, S-Bit D/A Converter . . . . . . . . . . I1-S3
AN-20l - How to Test Basic Operational Amplifier Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-97
AN-202 - An I.C. Amplifier Users' Guide to Decoupling, Grounding, and Making Things Go Right for a Change ..... 11-101
AN-20S - Video Formats & Required Load Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-109
AN-206 - Analog Panning Circuit Provides Almost Constant Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-113
AN-207 - Interfacing Two 16-Bit ADlSS6 (AD18Sl) Audio DACs with the Philips SAA7220 Digital Filter . . . . . . . . . 11-117
AN-20S - Understanding LOGDACs'· . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-121
AN-209 - Sth Order Programmable Low Pass Analog Filter Using Dual12-Bit DACs . . . . . . . . . . . . . . . . . . . . . . . 11-125
AN-211 - The Alexander Current Feedback Audio Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-133

AN-21Z - Using the ADS34 in DC to 500 MHz Applications RMS-to-DC Conversion,
Voltage-Controlled Amplifiers and Video Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-149
AN-213 - Low-Cost, Two-Chip Voltage-Controlled Amplifier and Video Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-159
AN-2l4 -Ground Rules for High-Speed Circuit Layout and Wiring Are Critical in Video-Converter Circuits,
How to Keep Interference to a Minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-165
AN-2lSA - Designer's Guide to Flash-ADC Testing - Part 1, Flash ADCs Provide the Basis for
High Speed Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-169
AN-21SB - Designers' Guide to Flash-ADC Testing - Part 2, DSP Test TechIiiques Keep Flash ADCs in Check ..... 11-177
AN-2lSC - Designers' Guide to Flash-ADC Testing - Part 3, Measure Flash-ADC Performance

for Trouble-Free Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . l1-lS3

APPLICA TION NOTES 11-1

II

Page

AN-216 - Video VCAs and Keyers Using the AD834 and AD811 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-193
AN-217 - Audio Applications of the ADSP Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-201
AN-218 - DSP Multirate Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-205
AN-219 - Electronic Adjustment Made Easy with the TrimDAC" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-215

11-2 APPLICA TION NOTES

AN-15
APPLICATION NOTE

IIIIIIIIIII ANALOG

WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 617/329-4700

Minimization of Noise in Operational Amplifier Applications

INTRODUCTION

caused noise is repetitive rather than random and can be found
at a definite frequency. Noise effecis from external sources
must be reduced to insignificant levels to realize the full
performance available from a low noise op amp.

Since operational amplifier specifications such as Input Offset
Voltage and Input Bias Current have improved tremendously in
the past few years, noise is becoming an increasingly important
error consideration. To take advantage of today's high performance op amps, an understanding of the noise mechanisms
affecting op amps is required. This paper examines noise
contributions, both internal and external to an op amp, and
provides practical methods for minimizing their effects.

EXTERNAL NOISE SOURCES
Since noise is a composite signal, the individual sources must
be identified to minimize their effects. Forexample, 60Hz power
line pickup is a common interference noise appearing at an op
amp's output as a 16ms sine wave. In this and most other
situations, the basic tool for external noise source frequency
characterization is the oscilioscope sweep rate setting. Recognizing the oscilloscope's potential in this area, Tektronix®
manufactures an oscilloscope vertical amplifier with variable
upper and lower -3dB points, which allows quick noise source
frequency identification. Another basic identification tool is the
simple low pass filter as shown in Figure 2, where the bandpass
is calculated by:

BASIC NOISE PROPERTIES
Noise, for purposes of this discussion, is defined as any signal
appearing in an op amp's output that could not have been
predicted by DC and AC input error analysis. Noise can be
random or repetitive, internally or externally generated, current
or voltage type, narrowband or wideband, high frequency or
low frequency; whatever its nature, it can be minimized.
The first step in minimizing noise is source identification in
terms of bandwidth and location in the frequency spectrum;
some of the more common sources are shown in Figure 1, an
11-decade frequency spectrum chart. Some preliminary observations can be made: noise is present from DC to VHF from
sources which may be identified in terms of bandwidth and
frequency. Noise source bandwidths overlap, making noise a
composite quantity at any given frequency. Most externally

1
fa '" 2rr RC

(1 )

With such a filter, measurement bandpass can be changed from
10Hz to 100kHz (C = 4.71'F to 470pF), attenuating higher frequency components while passing frequencies of interest. Once
identified, noise from an external source may be minimized by the
methods outlined in Table 1-the external noise source chart.
Tektronix(ffl is a registered trademark of Tektronix, Inc., Oregon.

FIGURE 1: Frequency Spectrum of Noise Sources Affecting Operational Amplifier Performance

lH,

1300kHz

I

RADAR PULSE REPETITION FREQUENCY

I
DOMINANT REGION OF WHITE NOISE (JOHNSON & SCHOTTKY)

DOMINANT REGION IIF (FLICKER) NOISE - PINK NOISE

SWITCHING POWER
SUPPLY FREQUENCY
SCR SWITCHING
LARGE LOADS

MECHANICAL VIBRATION
DC TO DC

SUPPLY
INVERTING

POPCORN NOISE REGION
POWER

RADIO STATION

PICKUP

FREQUENCY

SUPPLY
RIPPLE 60Hz
PRINTED CIRCUIT BOARD

CONTAMINATION

I~~NE~

PICKUP

0.001

0.01

0.1

XFMR

EMI

I

10

I

I

60 100 120

Tl

RELAY & SWITCH
ARCING

CHOPPER AMP
COMMON MODE
CURRENT SPIKES
AT CHOPPING
FREQUENCY

180 1k

10k

lOOk

O.SSM 1M

10M

FREQUENCY IN Hz

APPLICA TION NOTES 11-3

II

TABLE 1: External Noise Source Chart
Nature

Source

Causes

Minimization Methods

Reorientation of power wiring. Shielded
transformers. Single pOint grounding.
Battery power.

60Hz

Repetitive Interference

Powerlines physically close to op amp
inputs. Poor CMRR at 60Hz. Power
transformer pri mary-to-secondary capacitive coupling.

120Hz Ripple

Repetitive

Full wave rectifier ripple on op amp's
supply terminals. Inadequate ripple
consideration. Poor PSRR at 120Hz.

Thorough design to minimize ripple.
RC decoupling at the op amp. Battery
power.

180Hz

Repetitive EMI

180Hz radiated from saturated 60Hz
transformers.

Physical reorientation of components.
Shielding. Battery power.

Radio Stations

Standard AM Broadcast
Through FM

Antenna action anyplace in system.

Shielding. Output filtering. Limited circuit bandwidth.

Relay and Switch Arcing

High Frequency Burst
At Switching Rate

Proximity to amplifier inputs, power
lines, compensation terminals, or nulling terminals.

Filtering of HF components. Shielding.
Avoidance of ground loops. Arc suppressors at switching source.

Printed Circuit Board
Contamination

Random Low Frequency

Dirty boards or sockets.

Thorough cleaning attime of soldering
followed by a bakeout and humidity
sealant.

Radar Transmitters

High Frequency Gated
At Radar Pu Ise
Repetition Rate

Radar transmitters from long range
surface search to short range navigational-especially near airports.

Shielding. Output filtering of frequencies ~ PRR.

Mechanical Vibration

Random < 100Hz

Loose connections, intermittent contact in mobile equipment.

Attention to connectors and cable
conditions. Shock mounting in severe
environments.

Chopper Frequency
Noise

Common Mode Input
Current At Chopping
Frequency

Abnormally high noise chopper amplifier in system.

Balanced source resistors. Use bipolar
input op amps instead. Use premium
low noise chopper.

Switching Power
Supply

Repetitive High Frequency
Glitches In Supply
And Ground

Improper ground return. Radiated noise
from switching circuit.

Analog ground return to AC return.
Shield power supply. Liberal power
supply bypass at the op amp.

FIGURE 2: Noise Frequency Analysis RC Low Pass Filter

FIGURE 3: PSRR vs Frequency (OP-77)

.

130

3.3kn

II+~ +2~!~

OSCILLOSCOPE
120

J

1\

4.7J,!F TO 470pF

10Hz TO 100kHz

110

~

'"

Power Supply Ripple
Power supply ripple at 120Hz is not usually thought of as a
noise, but it should be. In an actual op amp application, it is
quite possible to have a 120Hz noise component that is equal in
magnitude to all other noise sources combined, and, for this
reason, it deserves a special discussion.

~

100

1\

90
80

i\

70

60

0.1

1.0

10

100

FREQUENCY (Hz I

To be negligible, 120Hz ripple noise should be between 10nV
and 100nV referred to the input of an op amp. Achieving these
low levels requires consideration of three factors: the op amp's
120Hz power supply rejection ratio (PSRR). the regulator's ripple
rejection ratio, and finally, the regulator's input capacitor size.
PSRR at 120Hz for a given op amp may be found in the
manufacturer's data sheet curves of PSRR versus frequency as
shown in Figure 3. For the amplifier shown, 120Hz PSRR is

11-4 APPLICA TlON NOTES

1k

'''''

about 76dB, and to attain a goal of 100nV referred to the input,
ripple at the power terminals must be less than O.6mV. Today's
IC regulators provide about 60dB of ripple rejection; in this case
the regulator input capacitor must be made large enough to
limit input ripple to O.6V.

Externally-compensated low noise op amps can provide improved 120Hz PSRR in high closed-loop gain configurations.
The PSRR versus frequency curves of such an op amp are
shown in Figure 4. When compensated for a closed-loop gain of
1000. 120Hz PSRR is 115dB. PSRR is still excellent at much
higher frequencies allowing low ripple-noise operation in
exceptionally severe environments.
FIGURE 4: PSRR vs Frequency (OP-06)

Power Supply Regulation
Any change in power supply voltage will have a resultant effect
referred to an op amp's inputs. Forthe op amp of Figure 3. PSRR
at DC is 126dB (0.5!,V/V) which may be considered as a
potential low frequency noise source. Power supplies for low
noise op amp applications should. therefore. be both low in
ripple and well-regulated. Inadequate supply regulation is often
mistaken to be low frequency op amp noise.
When noise from external sources has been effectively minimized. further improvements in low noise performance are
obtained by specifying the right op amp and through careful
selection and application of the associated components.

100

80

OPERATIONAL AMPLIFIER INTERNAL NOISE

1-+++IIHll-h

0.1

0.01

1.0

10

100

FREQUENCY (kHz)

Power Supply Bypassing
Usually. 120Hz ripple is not the only power supply associated
noise. Series regulator output typically contain at least 150!'Vof
noise in the 100Hz to 100kHz range; switching types contain
even more. Unpredictable amounts of induced noise can also
be present on power leads from many sources. Since high
frequency PSRR decreases at 20dB/decade. these higher
frequency supply noise components must not be allowed to
reach the op amp~s power terminals. RC decoupling. as shown
in Figure 5. will adequately filter most wideband noise. Some
caution must be exercised with this type of decoupling. as load
current changes will modulate the voltage at the op amp's
supply pins.
FIGURE 5: RC Decoupling
v+
1000

J

+ 10IJF
g~~AMIC~ ELECTROLVTlC

-L O.1~F

Most completely specified low-noise op amp data sheets
specify current and voltage noises in a 1Hz bandwidth centered
on 10Hz. 100Hz. and 1kHz. as well as low frequency noise over a
range of 0.1 Hz to 10Hz. To minimize total noise. a knowledge of
the derivation of these specifications is useful. In this section.
the reader is provided with an explanation of basic op ampassociated random noise mechanisms and introduced to a
simplified method for calculating total input-referred noise in
typical applications.
Op amp-associated noise currents and voltages are random in
nature. They are aperiodic and uncorrelated to each other; and
typically have Gaussian amplitude distributions. with the highest noise amplitudes having the lowest probability. There is a
statistical relationship between the peak-to-peak value of
random noise and its rms value. Where the amplitude distribution is Gaussian. the rms value may be multiplied by six to
yield a peak-to-peak value that will not be exceeded 99.73% of
the time (this is a handy rule-of-thumb for noise calculations).
Noise Model of Op Amps
In the calculation of op amp circuit noise. it is customary to refer
all noise to the input. Figure 6 completely models the inputreferred noise sources. In the model. the internal white and
flicker noise sources are combined into three equivalent input
noise generators. En. In1 . and In2. The noise current generators
produce noise voltage drops across their respective source
resistors. RS1 and RS2. The source resistors themselves generate thermal noise voltages. En and Et 2. Total rms input-referred
voltage noise. over a given bandwidth. is the square root of the
sum of the squares of the five noise voltage generators over that
bandwidth.
FIGURE 6: Op Amp Noise Model

II

APPLICA TION NOTES 11-5

Mathematically, noise spectral density may be expressed as:
Equation 2 describes, in total, all noise sources of an op amp
circuit. It will be used throughout this application note.
Minimization of total noise requires an understanding of the
mechanisms involved in each of the five generators. First, the
white noise mechanisms, thermal and shot, are discussed,
followed by other low frequency noise mechanisms, flicker and
popcorn.
Noise Mechanisms of Op Amps
The two basic types of op amp-associated noises are white
noise and flicker noise (1If). White noise contains equal
amounts of power in each hertz of bandwidth. Flicker noise is
different in that it contains equal amounts of power in each
decade of bandwidth. This is best illustrated by spectral noise
density plots such as in Figures 7 and 8. Above a certain corner
frequency, white noise dominates; belowthatfrequency, flicker
(1/f) noise is dominant. Low noise corner frequencies in
conjunction with a low white noise magnitude distinguish low
noise op amps from general purpose devices.

Vs= ±15V
TA - 2SOC

~
>
~

Rs",on
100

= En 2
Af

10

"~

WHITE
NOISE
l/t CORNER

>

FREQUENCY, fee

0

1.0
0.01

En, In = Total rms voltage and current noise in a frequency band, respectively
Af

= Bandwidth of 1Hz

From Equation 3, the total rms noise in a frequency band from fl
to fH is then,
(4a)

En2 =

Jfrl

fH

III
0.10

1.0

10

fl = Lower frequency limit of interest
Equation 4 means that three things must be known to evaluate
total voltage noise (En) or current noise (In): fH' fl' and a
knowledge of noise behavior over freq·uency.

EnW = enw v'fH - fl

Inw = inw v'fH - fl

Enw = enw ~

(6b)

Inw = inw ~

Flicker Noise
Unlike white noise, flicker (1/f) noise is not constant with
respect to frequency, but has a power spectral density that is
inversely proportional (K e, Kj) to the frequency of interest as
described in Equation 7.
Vs= ±15V
TA =2SOC

(7a)

enF2(f)

2

K·2

Ke
=T

(7b)

inF2(f)

.j

(8b)

. f
Kj
InF! ) =

=+

or,

1.0

Ii!
0
z

(8a)

~'"

~

~

(5b)

1k

10

a:

(4b)

Where: fH = Upper frequency limit of interest

(6a)

I

100

FIGURE 8: OP-77 Noise Current

~

en2 df

When fH 2': 10 fl' the white noise expressions may be reduced to:

FREQUENCY (Hz)

~

(3b)

Where: en, in = Spectral noise density of voltage arid current,
respectively

(Sa)

...

0

w

2

1/f NOISE

Ii!
z

n

White noise contains many frequency components and is so
named in analogy to white light which is made up of many
colors. The important point to remember is that white noise has
equal noise power in each hertz of bandwidth. In other words,
the noise spectral density of white noise is constant with varying
frequency. Thus, Equation 4 may be rewritten to describe white
noise over a frequency band.

1000

~0

e

White Noise

FIGURE 7: OP-77 Noise Voltage

~

(3a)

0.1

""

endf)

=

.Jf

Where: Ke, Kj are constants of proportionality.

1/f CORNER

F~~IOUIEN~Ti ltd

I II

0.Q1

0.01

0.10

'.0

IIII
10

FREQUENCY (Hz)

11-6 APPLICA TION NOTES

100

1k

The constants of proportionality depend on a number of
parameters internal to the amplifier. It will be shown later that
the constants will drop out mathematically.
In orderto calculate total voltage and current noise, the concept
of corner frequency is useful. Referring to the graphs of en or in
versus frequency as in Figures 7 and 8, we can see that it is a
composite of a zero-slope line (white noise) summed with a line

of slope -1/2 (l/f noise, or flicker noise). The projected
intersection of these lines occurs where the two noise powers
are equal, at a frequency called the corner frequency. Therefore,
it follows that at the corner frequency, fee or fe;,
(9b)
rearranging,
(lOa)

The rms noise in a band is then:
En(fH, fLl =

(17)

In(fH,fLl=inwJfe;oln

inw = White noise current spectral density

K,,2 = enw2 ° fee

en F2 (f) = en w2

or,
(12a)

fee = Voltage noise corner frequency

enF(f) = enw

°

fee

T

J!i

fe; = Current noise corner frequency
(11 b)

(12b)

fH = Upper frequency limit of interest

inF 2(f) = inW2 °T
fe;

indf) = inw

~

We can find the rms flicker noise in a band as follows:
(13a)

(~) + (fH-fLl

Where: enw = White noise voltage spectral density

substituting in Equation 7,
(11 a)

enwJ""f-ee-o-ln-(-~-)-+-(-fH---fL-)

(16)

EnF2 = l:H enF2(f) df

fL = Lower frequency limit of interest
The two most important internally-generated noise minimization rules are derived from Equation 16 and 17: a) limit the circuit
bandwidth, and b) use operational amplifiers with low white
noise specifications in conjunction with low cornerfrequencies.
So far we have derived the nOise voltage (En) and noise current
(In) components (Equations 16 and 17) for the first three terms
of Equation 2, which is reproduced below.

=ew2of
n
ee oln(!tt)
fL
In the next section, the last two terms of the equation, which are
the thermal noise voltages generated by the external source
resistances, are derived.

Thermal Noise

Typical bipolar op amp corner frequencies for voltage noise are
in the range of 1 to 20Hz; and for current noise, 10to 1,000Hz. In
comparison, FET input op amps have voltage noise corner
frequencies in the range of 100Hz to 500Hz. Still higher are
CMOS op amps whose corner frequencies are typically on the
order of 1kHz.
Now that we have the mathematical expressions describing
white noise and flicker noise, we can sum (by root-sum-square
method) the two components to yield a total spectral density
expression.

Thermal (Johnson) noise is a white noise voltage generated by
random movement of thermally-charged carriers in a resistance; in op amp circuits, this is the type of noise produced by the
source resistances in series with each input. Its rms value over a
given bandwidth is calculated by:
(18)

Et = J4kTR ° (fH -fLl

Where: k = Boltzmann's constant = 1.38 x 10-23 joules/K
T = Absolute temperature, kelvin
R = Resistance in ohms
fH = Upper frequency limit in hertz
fL = Lower frequency limit in hertz

substituting from Equation 11,
(15a)

~

en =enwVl +1'-

(15b)

i n =i nW

V~
1 +f

Equation 15 is an expression frequently used to describe noise
(voltage and current) curves seen in op amp data sheets.

At room temperature, Equation 18 simplifies to:
(19)

Et = 1.28 x 10- 10 JR ° (fH -fLl

To minimize thermal noise (Ell and Et2 ) from RSI and RS2 , large
source resistors and excessive system bandwidth should be
avoided.

APPLICA TION NOTES 11-7

II

Thermal noise is also generated inside the op.amp. principally
from rbb'. the base-spreading resistances in the input stage
transistors. These noises are included in En. the total equivalent
input voltage noise generator.
All the component noise sources of Equation 2 have now been
derived. Total noise of an op amp circuit may be easily
calculated using the equation. In the next sections, examples
using several precision op amps will be calculated to illustrate
the noise minimization techniques as well as to contrast the
different noise performance of these devices.

3Hz. Lines projected from the horizontal (white noise) portion
and the sloped (flicker noise) portion intersect at 2Hz. the
voltage noise corner frequency (fee)' In the center curve,
excluding thermal noise from the source resistance, current
noise multiplied by 200kfl is plotted as a voltage noise. Lines
projected from the horizontal portion and sloped portions
intersect at 80Hz, the current noise corneF frequency (fei ).

FIGURE 9A: OP-77 Input Spot Noise Voltage vs Frequency
1000

EE;E

RS1 .. RS2 - 200k!l...
THERMAL NOISE OF ~~RCE

TOTAL NOISE CALCULATION

RESISTORSIII~fiLUD~DI

r:::::

With data sheet curves and specifications. and a knowledge of
source resistance values, total input-referred noise may be
calculated for a given application. To illustrate the method,
noise information from the Precision Monolithics OP-77A and
OP-27A data sheets are reproduced in Figure 9. The first step is
to determine the current and voltage noise corner frequencies
so that the En and In terms of Equation 2 may be calculated
using Equations 16 and 17.

EXCLUDED

RS"'O

s-

V
±15V
TA = +25°C

Corner Frequency Determination

1
1

In the input spot noise versus frequency curves of Figure 9, it
may be seen that voltage noise (Rs = 0) begins to rise at about

10

,.

100

FREQUENCY (Hz)

FIGURE 98: OP-77/0P-27 Ultra-Low Offset Voltage Op Amps

ELECTRICAL CHARACTERISTICS at Vs

= ±15V and TA = 25°C, unless otherwise noted.

SYMBOL

CONDITIONS

Input Noise Voltage

Bnp _p

0.1 Hz to 10Hz

0.35

Input NOise
Voltage Density

en

fo = 10Hz
fo = 100Hz
fo = 1000Hz

10.3
10.0
9.6

Input Noise Current

i np _p

0.1 Hz to 10Hz

Input Noise
Current Density

in

fo = 10Hz
fO = 100Hz
fo = 1000Hz

Input Offset Voltage

Vos

Input Offset Voltage
Drift

TCVos

Long Term Input Offset
Voltage Stability

Vos/Time

Input Offset Current

los

Input Bias Current

18

-55°C:5 TA :5 +125°C

MIN

OP-77A
TYP

PARAMETER

OP-27A
TYP

MAX

UNITS

0.6

0.08

0.18

I'Vp _p

18.0
13.0
11.0

3.5
3.1
3.0

5.5
4.5
3.8

nV/,fHZ

MAX

14

30

0.32
0.14
0.12

0.80
0.23
0.17

MIN

pAp _p
1.7'
1.0
0.4

4.0
2.3
0.6

pA/,fHZ

10

25

10

25

I'V

0.1

0.3

0.2

0.6

I'VioC

0.2

1.0

0.2

1.0

~V/Mo

0.3

1.5

35

nA

±1.2

±2.0

±10

±40

nA

INPUT NOISE VOLTAGE (e. p•p )

INPUT NOISE CURRENT (I.p _p )

The peak-te-peak noise voltage in a specified frequency band.

The peak-te-peak noise current in a specified frequency band.

INPUT NOISE VOLTAGE DENSITY(e.)

INPUT NOISE CURRENT DENSITY (I.)

The rms noise voltage in a·1 Hz band surrounding a specified value of

The rms noise current in a 1Hz band surrounding a specified value of
frequency.

frequency.

11-8 APPLICA TION NOTES

Equations 16 and 17 also require enw and inw for calculation of
En and In. To find enw and inW' use the data sheet specifications
a decade or more above the respective corner frequencies; in
the case of the OP-77A, enw is 9.6V1VHz (1,000Hzi, and inw is
0.12pA/VHz (1,000Hzi. At this time, it should be noted thatthe
noise current, 0.12pA/VHz, is a value that has been incorrectly
derived from the standardized, commonly-used test method on
virtually ALL commercially available op amps. The value is off
by a factor of J2. Therefore, in order to calculate the correct
total noise, the data sheet current noise value should be
multiplied by a correction factor of J2. Thus, for the noise
calculation ofthe OP-77 A, the value enw is 9.6nVl VHz (1 ,000Hz),
and inw should be 0.17pAlVHz (1,000Hz).

Next, calculate In using Equation 17:

OP-77 Bandwidth 01 Interest

In2 ' RS2 = 5.9pA· (10kn) = 0.059!,Vrms

To be summed correctly, each of the five noise quantities must
be expressed over the same bandwidth, fH to fL. For calculation
purposes, assume fH to be the highest frequency component
that must be amplified without distortion. Note that en, in, corner
frequencies are independent of actual circuit component
values. When dOing noise calculations for a large number of
circuits using the same op amp, these numbers only have to be
calculated once.

In=inVfc;'ln

= 0.17pA

vi

(~) +fH-fL

80 • In (100HZ)
0.0001 Hz + 100 - 0.0001

= 5.9pArms
and:
In1 • RS1 = 5.9pA . (900n) = 0.0053!,Vrms

Finally, En from Equation 16:
En=en Vfce·ln

= 9.6nV

vi

(~) +fH-fL

2 • In (100HZ)
0.0001 Hz + 100 - 0.0001

= 0.108!,Vrms

OP-77 Typical Application Example

Figure 10A shows a typical x10 gain stage with a 10kn source
resistance. In Figure 108, the circuit is redrawn to show five
noise voltage sources. To evaluate total input-referred noise,
the values of each of the five sources must be determined.
FIGURE 10A: Noise Analysis Circuit

Substituting in Equation 2:

(0.108!,V)2 + (0.0053!,V)2 + (0.059!,V)2 +
(0.04!,V)2 + (0.128!,V)2

R2

9."
>--4~--oEO

FIGURE 10B: Noise Analysis Equivalent Circuit

Total input-referred noise = 1.08!,V peak-to-peak (0.0001 Hz to
100Hz).
Notice that of the five terms in the equation, the first and the last
terms dominate. Since the first term is the total rms noise
voltage inherent of the amplifier, nothing can be done by the
system designer to lower its noise other than to choose a device
having inherently low noise characteristics. As can be seen in
Equation 16, two key parameters determine the total rms noise
of an amplifier-low white noise density and low noise corner
frequency.
Notice that the thermal noise voltage (last term) of Equation 2 is
determined by the 10k!} value selected for R3. Had the value
been reduced to 1kO, the thermal noise voltage would have
been 0.04!,Vrms instead of 0.128!,Vrms. As a result, total rms
noise voltage would have become 0.122!,V, a remarkable 32%
reduction in total noise.

Using Equation 19: Et = 1.28 x 10-10 .jR:-(fH - fLl
Et1 = 1.28 X 10-10 v(9000) (100Hz) - 0.04!,Vrms
Et2 = 1.28 X 10-10 V(10kO) (100Hz) = 0.128!,Vrms

Indeed, low noise design requires the system designer not only
to choose an amplifier with low noise characteristics, but also to
pay close attention in selecting appropriately low source
resistances in the input circuit.

APPLICATION NOTES

11-9

II

741 Calculation Example

FIGURE 11A: Input Noise Voltage as a Function Of Frequency

The preceding calculation determined total noise in a given
bandwidth using a low noise op amp. To place this level of
performance into perspective, a calculation using the industrystandard 741 op amp in the circuit of Figure 10 is useful. Once
again the starting point is corner frequency determination,
using the data sheet curves of Figure 11: fee = 200Hz; fei = 2kHz;
en = 20nVlVHZ; in = (J2). (0.5pAlVHZ) = 0.71pA/VHZ.

10-13 ,.--M'T'T""'r-1rTT"--T""'r-rrT""'T""'r-rr,..-,

Using these corner frequencies and noise magnitudes, En and
In are calculated to be 1.07p.Vrms and 118pArms, respectively.
Multiplying this noise current by the source resistance gives
terms 2 and 3 of Equation 2 as.shown below:

10

100

10k

"

lOOk

FREQUENCY 1Hz)

substituting in the equation:

,-------------------(1.07p.V)2 + (0. 106p.V)2 + (1.18p.V)2 +

FIGURE 118: Input Noise Current as a Function of Frequency

(0.04p.V)2 + (0.128p.V)2

= 1.6"Vrms

10-20

~

Total input-referred noise = 9.6p.V peak-to-peak (0.0001 Hz to
100Hz). This is more than 8 times that of the loW noise OP-77
example. Notice further in this example, the third term of the
equation becomes an additional dominant term. It is due to a
higher noise current flow in the 10k!} source resistance.

Vs;;; ±lSV

I-

TA =

ffi

a:

aa:

~

III

~
z
::l..

The calculation examples illustrate four rules for minimizing
noise in operational amplifier applications:
Rule 1. Use an op amp with low noise characteristics.

10-23

10-24

,~

10-26

"A741

Rule 2. Use an op amp with low noise corner frequencies.
100

10

Rule 3. Keep source resistances as low as practical.

lk

10k

FREQUENCY (Hz)

Rule 4. Limit circuit bandwidth to signal bandwidth.
FIGURE 12: OP-27, OP-37, and OP-227 Noise Voltage and Current as a Function of Frequency
(A) VOLTAGE NOISE DENSITY
vs FREQUENCY

(8) CURRENT NOISE DENSITY
vs FREQUENCY

10
9

10.0

•
7

TA'" 2!fc
Vs = ±15V

I\.

, ....
,

~

:---.

1/fCORNER
=2.7Hz

r-- 1

10

100

FREQUENCY (Hz)

11.;.10 APPLICATION NOTES

"

l/f CORNER
= 140Hz

11111111

0.1

1

2!/'e

10-22

10

100

I
lk

FREQUENCY 1Hz!

10'

lOOk

OP-27/0P-227/0P-37 Noise Optimization Design
In this example, a low noise, high speed op amp is examined.
Using the circuits in Figures 10A and 10B, and using the data
sheet curves of Figures 12A and 12B:
fee = 2.7Hz; fei = 140Hz; en = 3.0nVl,jHz;
in

= (J2) . (0.4pAl,jHz) = 0.57pA/,jHz

Using these corner frequencies and noise magnitudes, En and
In are calculated to be 0.035!,Vrmsand 25.7pArms, respectively.
Multiplying the noise currents by the source resistances yield
terms 2 and 3 of Equation 2 as shown below:

while in actual application the amplifier's bandwidth must be
considered.
In Figure 13, the OP-77 frequency response curves show a
rolloff of 20dB/decade; integration of the area under the curve
will show the effective circuit noise bandwidth to be 1.57 times
the 3dB bandwidth. In most closed-loop gain configurations,
the amplifier's bandwidth may be greater than required, and
output filtering, such as in Figure 14, could be used. As an
alternate to output filtering, an integrating capaCitor may be
connected across the feedback resistor. Bandwidth may also be
limited in some applications by overcompensating an externallycompensated low noise op amp, such as the OP-06.
FIGURE 13A: OP-77 Open-Loop Frequency Response
160

+ (0.023.uV)2 + (0.257 !,V)2 +
(0.04!,V)2 + (0.128pV)2
(0.035.uV)2

120

~
= 0.293!,Vrms

Vs'" ±15V
TA '" +25 C C

140

z

100

'"

80



1 f CORNER

f- ~R~~~IENCYi '0
1.0
0.01

0.1

1.0

10

100

1k

FREQUENCY (Hz)

FIGURE 16: OP-77 Low Frequency Noise

Where: 'sh = rms shot noise value in amps
q

= Charge of an electron = 1.602 x 10- 19 C

'DC = DC bias current in amps
fH = Upper frequency limit in hertz
fL = Lower frequency limit in hertz
At room temperature Equation 20 simplifies to:
(21)

Ish = 5.66 X 10- 10 JIDC (fH - fLl

Shot noise currents also flow in the input-stage emitter dynamic
resistances (re), producing input noise voltages. These voltages,
along with the rbb' thermal noise, make up the white noise
portion of En; the total equivalent input noise voltage generator.

FIGURE 17: Low Frequency Noise Test Circuit
250kU

lon

Shot noise can also be generated from external sources such as
PIN photodiodes, zener diodes, and other semiconductor
junction devices. Noise current from these sources may be
calculated using Equation 20 or 21.
In limited bandwidth, very low frequency applications, flicker
(1/f) noise is the most critical noise source. An op amp designer
minimizes flicker noise by keeping current noise components
in the input and second stages from contributing to input
voltage noise. Equation 22 illustrates this relationship:
(22)

in second stage -g;~st stage -

e
n input

Another critical factor is corner frequency. For minimum noise,
the current and voltage noise corner frequencies must be low;
this is crucial. As shown in Figure 15, low-noise corner
frequencies distinguish low-noise op amps from ordinary
industry-standard 741 types.
The photograph in Figure 16, taken using the test circuit of Figure
17, illustrates the flicker noise performance of the OP-77. This

11-12 APPLICATION NOTES

("'10Hz FilTER)
INPUT-REFERRED NOISE =

25~~O = ~:J:

= 200nV/em

Popcorn noise (burst noise) is a momentary change in input
bias current usually occurring below 100Hz, and is caused by
imperfect semiconductor surface conditions incurred during
wafer processing. Precision Monolithics minimizes this problem
through careful surface treatment, general cleanliness, and a
special three-step process known as "Triple Passivation."
To begin the process, a specially-treated thermal silicon dioxide
layer is grown. This protects the junctions and also attracts any
residual ionic impurities to the top surface of the oxide, where
they are held fixed. Next, a layer of silicon nitride is applied to
prevent the entry of any potential contamination or impurities.

The third step is the thick glass overcoat which leaves only the
bonding pads exposed. A cutaway view of a finished device is
shown in Figure 18.
FIGURE 18: Triple Passivated Integrated Circuit Process

EMITTER

BASE

COLLECTOR

CONCLUSION
Recent improvements in IC op amp DC specifications have
made noise an important error consideration. From data sheet
information and source resistance values, total input-referred
noise over a given bandwidth can be easily calculated. Total
noise can be minimized by a thorough understanding of the
various noise-generation mechanisms.

NOISE BIBLIOGRAPHY
1. "The OP-07 Ultra-Low Offset Voltage Op Amp-A Bipolar
Op Amp That Challenges Choppers, Eliminates Nulling," D.
Soderquist and G. Erdi, Precision Monolithics Inc., Application Note AN-13.
2. Low Noise Electronic Design, C.D. Motchenbacher and F.C.
Fitchen, John Wiley and Sons, 1973.

Op amp manufacturers face a difficult decision in dealing with
popcorn nOise. Through careful low noise processing, itcan be
eliminated from almost all devices; alternatively, the processing
may be relaxed, and finished devices must be individually tested
for this parameter. Special noise testing takes valuable labor
time, adds significant amounts to manufacturing cost, and
ultimately increases the price a customer has to pay. At Precision
Monolithics, the low noise process alternative is used to
manufacture high volumes of cost-effective low noise op amps.

3. "Low Frequency Noise Predicts When a Transistor Will Fail,"
A. Van der Ziel and H. Tong, Electronics, 39, November 28,
1966.
4. "Bistable NOise in Operational Amplifiers," S. Hsu, IEEE
Solid-State Circuit SC-6, December 1971.
5. "Low-Noise Transistor Amplifiers," E. Chenette, Solid State
Design, 5, February, 1964.
6. Electrical Noise, A. Bennett, McGraw-Hili, 1960.
7. Noise, A. Van der Ziel, Prentice-Hall, 1954.

SUMMARY
A summary of the major points to consider is as follows:
1. Minimize externally-generated noise.
2. Choose an amplifier with low noise characteristics and low
llf noise corner frequencies.
3. Limit the circuit bandwidth to signal bandwi.dth.
4. Eliminate excessive resistance in the input circuit.

II

APPLICATION NOTES 11-13

11-14 APPLICA TlON NOTES

~ANALOG

WDEVICES

AN·102
APPLICATION NOTE

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSEITS 02062-9106 • 617/329-4700

Very Low Noise Operational Amplifier

APPLICATIONS
• High Precision Instrumentation
• Microphone Preamplifier
• Tape-Head Preamplifier
• Strain-Gage Amplifier

r-----------~--------._--~v+

FEATURES

v-

• Very Low Voltage Noise ................ 500pV/JHZ
• High Gain-Bandwidth Product ............... 150MHz
• High Open-Loop Gain. . . . . . . . . . . . . . . . . . . . .. 3 x 107
• High CMRR ................................ 130dB
• Very Low Offset Voltage Drift .............. <0.1!,V/oC
GENERAL DESCRIPTION
In situations where low output, low-impedance transducers are
used, amplifiers must have very low voltage noise to maintain a
good signal-to-noise ratio. The design presented in this application note is an operational amplifier with only 500pVI VRZ of
broadband noise. The front end uses SSM-221 0 low-noise dual
transistors to achieve this exceptional performance. The op amp
has superb DC specifications compatible with high-precision
transducer requirements, and AC specifications suitable for
professional audio work.
PRINCIPLE OF OPERATION
The design configuration in Figure 1 uses an OP-27 op amp
(already a low-noise design) preceded by an amplifier consisting
of three parallel-connected SSM-2210 dual transistors. Base
spreading resistance (R bb ) generates thermal noise which is
reduced by a factor of -.f3 when the input transistors are parallel
connected. Schottky noise, the other major noise-generating
mechanism, is minimized by using a relatively high collector
current (1 mA per device). High current ensures a low dynamic
emitter resistance, but does increase the base current and its
associated current noise. Higher current noise is relatively
unimportant when low-impedance transducers are used.

v-

+INo-+-+-£

..l-+-+-<>-IN

v-

m

v-

Simplified Schematic for Very Low Noise Operational
Amplifier
Figure 1: Simplified Schematic

APPLICATION NOTES 11-15

CIRCUIT DESCRIPTION
The detailed circuit is shown in Figure 2. A total input-stage
emitter current of 6mA is provided by 04. The transistor acts as
a true current source to provide the highest possible commonmode rejection. R1 , R2 • and R3 ensure that this current splits
equally among the three input pairs. The constant current in 04
is set by using the forward voltage of a GaAsP light-emitting
diode as a reference. The difference between this voltage and
the base-emitter voltage of a silicon transistor is predictable and
constant (to within a few percent over the military temperature
range. The voltage difference. approximately 1V. is impressed
across the emitter resistor R12 which produces a temperaturestable emitter current.

Rs and C1 provide phase compensation for the amplifier and are
sufficient to ensure stability at gains of ten and above.
R7 is an input offset trim that provides approximately ±3001lV trim
range. The very low drift characteristics of the SSM-221 0 make
it possible to obtain drifts ofless than O.1IlV/oC when the offset
is nulled close to zero. If this trim is not required. the R4 • R7• and
Rs network should be omitted and Rs'Rg connected directly to
V+.

r-----~-----.--------------------------~~------------~~-o+15V

Ra
22U
NULL

Rg

R5

~100nF

1.5kU.O.l%

1.5kU.O.l%
RS. 150U Cl.

O.01~F

S

>------------+---i~ OUTPUT

+lNO-~"'-;~[

.1-.....-:--0 -IN

*

100nF

27kU

04

RED

LE~

/"
'--------<_------<_-0 -15V

Figure 2: Complete Amplifier Schematic

11-16 APPLICATION NOTES

AMPLIFIER PERFORMANCE
The measured performance of the op amp is summarized in
Table 1. Figure 3 shows the broadband noise spectrum which is
flat at about 500 pV/y'HZ. Figure 4 shows the low-frequency
spectrum which illustrates the low 1If noise corner at 1.5Hz. The
low-frequency characteristic in the time domain from 0.1 Hz to
10Hz is shown in Figure 5; peak-to-peak amplitude is less than
40nV.
Table 1: Measured Performance of the Op Amp
Input Noise
Voltage Density at 1kHz

SOOpV/VHZ

Input Noise
Voltage from 0.1 Hz to 10Hz

40nV p _p

Input Noise Current at 1kHz
GaincBandwidth

1.SpA/VHZ
G = 10
G= 100
G = 1000

Slew Rate

3MHz
600kHz
lS0kHz

Low frequency noise spectrum at a gain of 10,000
showing a low 1.SHz noise corner.
Figure 4: Spectrum Analyzer Display - Low Frequency

2V/IlS

Open-Loop Gain
Common-Mode Rejection

130dB

Input Bias Current

31lA

Supply Current

lOrnA

Nulled TCVos
T.H.D. at 1kHz

G = 1000

0.002%

Peak-to-peak noise from 0.1 to 10Hz.
Overall gain is 100,000.
Figure 5: Oscilloscope Display

Spectrum analyzer display of broadband noise with a
gain of 10,000.
Horizontal axis = 0 to 2.SkHz.
Normalized vertical axis = 830pV/VHZ R.T.I.
en = S07pVIVHZ at 1kHz.

CONCLUSION
Using SSM-2210 matched transistor pairs operating at a high
current level, it is possible to construct a high-performance, lownoise operational amplifier. The circuit uses a minimum of
components and achieves performance levels impractical with
monolithic amplifiers.
...

l1li

Figure 3: Spectrum Analyzer Display - Broadband

APPLICATION NOTES 11-17

11-18 APPLICATION NOTES

r'IIII ANALOG

AN·105
APPLICATION NOTE

WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 617/329-4700

Applications of the MAT-04
A Monolithic Matched Quad Transistor
The MAT-04 is a monolithic device containing four low-noise,
tightly matched transistors, which dramatically improves the
performance of many amplifier and analog computational
circuits, This note describes several of these designs which
capitalize on the superior characteristics and dynamic range
of the MAT-04. These applications include a low-distortion
voltage-controlled attenuator, a very low-noise (1.2nV IVHZ)
high-speed instrumentation amplifier, a 900pV/VHZ ultralow nOise audio preamplifier, a vector summing amplifier, a
squaring amplifier, and a square-root amplifier.

designed for high beta (400 minimum) and 40V minimum
breakdown. It exhibits a low O.4n bulk resistance, which is
important in logarithmic circuit applications. The MAT-04
uses a symmetrical quad transistor pinout (Figure 1) which
allows incorrect orientation of pin 1 without damage. The
base-emitter junctions are internally diode-protected against
reverse zener breakdown, which protects against degradation
of beta and matching characteristics.

Discrete circuit designers repeatedly run into the problem of
circuit component mismatches that limit performance. Passive component mismatching can be reduced by using tighter
tolerance components, but active components present a
more difficult problem. Discrete transistors exhibit poor beta
and VBE(ON) matching, even within single transistor families,
which severely degrade amplifier performance. Most available transistor arrays however, were developed to save board
space rather than to provide accurate parametric matching.
Only a few are designed to have tight matching tolerance.

A useful MAT-04 application is the Voltage-Controlled Attenuator (VCA) of Figure 2. This circuit, widely used in professional audio applications, is difficult to implement using discrete transistors due to distortion induced by transistor
mismatching. The MAT-04 offers excellent matching which

VOLTAGE-CONTROLLED ATTENUATOR

FIGURE 1: Pin Connections

The MAT -04 uses advanced layout and process techniques to
guarantee that the offset voltage between any two transistors
in the device will be no more than 200"V, and beta mismatch
will not exceed 2%. Additionally, the MAT-04 transistors are

FIGURE 2: Voltage-Controlled Attenuator
r-----~----------------------~------~---------------------ov+

A"

R3

3Ok!l

A6
lOkJI

30k!l

,-

A7
JOkn

R8
30k!l

v+

YOUT

MAT·04

I
I

8

III

03

10
C2
~ 100!,-F

R13
4.7kll

A1'
3301!

100pF
VCONTROL

v+
2N2222
05

A2

30kn

Rl0

R11

22kfl

10kH

R12

C4

10k!lr 100.F

2N2222

as

A5
30kU

~-----------------------------*--------------------~----o~

APPLICATION NOTES 11-19

diamatically ieduces distoition. The VCA piovides lowdistortion attenuation over a wide range of control voltages,
and can be used as a low-distortion gain control in an audio
amplifier.

differential pair (02 and 03) and converted to a single-ended
signal by op amp A 1 which has a stage gain of 1. The gain of
the overall circuit with the bases of the MAT-04 at ground
potential is:

The VCA design is based upon the amplifying characteristics
of a differential pair. Figure 3 shows the classic differential
pair. With zero volts between the inputs (V1N= OV), the current
in each side of the differential pair is equal and therefore the
output voltage equals zero. Small changes in VIN unbalance
the currents flowing in each side of the differential pair and
produce an amplified differential output. The total stage current (I) of the differential pair is constant regardless of the
input voltage. Matching of the transistors in a differential pair
is critical, as any device mismatch will cause DC errors and
upset linearity.

(3)

FIGURE 3: Classic Differential Pair
v.

+ R4 . R5)
(2R2' R5)

= V1N (R2' R6

VOUT

and since R2 = R4 = R5 = R6, = 1
V1N
When a positive control voltage is applied, most of the stage
current is diverted into transistors 02 and 03, resulting in an
increase in circuit gain. However, when a negative control
voltage is applied, most of the stage current is diverted
through transistors 01 and 04, with a subsequent decrease in
circuit gain.
The ideal transfer function for the Voltage-Controlled Attenuator is:

V OUT

(4)

2

VOUT

V1N

(-VCONTROU (

R14
)
R13 + R14

( k; )
where k = Boltzmann constant =

v-

In the Voltage-Controlled Attenuator, the input signal modulates the stage currents of the two differential amplifier stages.
Op amps A2 and A3, in conjunction with transistors 05 and
06, form two vOltage-to-current converters that transform a
single input voltage into differential currents, which form the
stage currents I Aand 18 (see Figure 2) of each differential pair.
The transfer function of the voltage-to-current converter is:

temperature in OK

T

=

= electronic charge = 1.602 x 10-19 C

From the transfer function, it can be seen that the maximum
gain of the circuit is 2 (6dB). Figure 4 shows the increase in
attenuation as the control voltage becomes more negative.
FIGURE 4: Voltage-Controlled Attenuator,
Attenuation vs Control Voltage at 1kHz, 25°C

1.

-1.
.I

~ -20

V1N
R5

Ii
i

-30

S

-40

Low-cost unmatched transistors can be used for 05 and 06,
since they are inside the feedback loop of op amps A2 and A3.
Their beta mismatch has minimal effect on output offset.
If all the bases of the MAT-04 are at ground potential, then the
stage currents of each differential pair split equally among
each transistor. The output is taken from one side of each

11-20 APPLICATION NOTES

1.38 X 10- 23 J

q

i
(2) 18=

]

-50

/

/

/

/'

...---

/

/

-60

-3

-2

-1

CONTROL VOLTAGE (VCONTROd

A LOW-NOISE, HIGH-SPEED INSTRUMENTATION
AMPLIFIER

The Voltage-Controlled Attenuator accepts a 3Vrms input
and easily handles the full 20Hz - 20kHz audio bandwidth as
indicated in Figure 5. Distortion typically runs under 0.03%
and the noise level is more than 110dB below maximum
output.

The circuit of Figure 6 has performance characteristics which
make it ideal for use in high precision transducer and professional audio applications. The circuit uses a high-speed op
amp, the OP-17, preceded by an input amplifier consisting of
a precision matched dual transistor, the MAT -02, and a MAT04. The arrangement of the MAT -04 is known as a "linearized
cross quad" and acts as a voltage-to-current converter to
provide feedback to the input stage. The OP-17 acts as an
overall nulling amplifier to complete the feedback loop. Resistor pair R1 and R2, and resistor pair R3 and R4 form voltage
dividers that attenuate the output feedback due to the limited
input range of the "cross quad" arrangement. Biasing for the
input stage is set by zener diode Zl. At low currents, the
effective zener voltage is about 3.3V due to the soft knee
characteristic of the zener diode. This results in a bias current
of 530l'A per side for the input stage.

To insure best performance, resistors R2 through R7 should
be 1% metal film resistors. Since capacitor C2 can see a small
amount of reverse bias when the control voltage is positive, a
nonpolarized tantalum capacitor or two polarized capacitors
connected back-to-back should be used.
FIGURE 5: Voltage-Controlled Attenuator,
Attenuation vs Frequency

5

•
ii
~
z

Jcl!ll~~ JvI
=

-5

The gain of the instrumentation amplifier, with the values
shown in Figure 6, is:

0

Iii

-10

"z

~ -15
-20
-25
10

VCONTROL -

1V

(5)

ill

II
100

III

IIII111

,.

VO UT _ 33,000
VIN

-R;-

IIII
100.

10k

FREQUENCY (Hz)

FIGURE 6: Low-Noise, High-Speed Instrumentation Amplifier

,-------......,_---------....,.-------------o+15v
R8

R5
S.8kU

I.SkU

Cl

"7

500pF

1.5kH

-15V

:....0

I

_+IN

R"
120H
R4

10k/!

110
110

.,

..IV
00....

=33k"
=,.31<"
=

Ro 330H
Ra = 33n

GAIN
GAIN

II

=1
=10

GAIN = 100
GAIN .. 1000

"111

AI
3.IIUl

L---~-------------~------------------------------------------o_~V

APPLICATION NOTES 11-21

TABLE 1
Input Noise
Voltage Density

G
G
G

~

G

~5oo

~
~

G~

Bandwidth

G~

1000
100
10

1.2nV/JHz
3.6nVlJHz
30nVlJHz
400kHz
lMHz
1.2MHz

100
10

Slew Rate

40V/,.s

Common-Mode
Rejection

G

Distortion

G ~ 100
f = 20Hz to 20kHz

Settling Time

G

~

~

1000

130dB

1000

0.03%
10,.s

Power
Consumption

350mW

FIGURE 7: Spot Noise of Discrete Instrumentation Amplifier
at Gain

~

1000 from 0 to 25kHz

NORMALIZED VERTICAL AXIS OR 2.6nV/v'Hz PER DIVISION
REFERENCED TO INPUT (R.I.I.I.
en AT 10kHz" 1.2nV/v'Hz

The performance of the amplifier is summarized in Table 1.
Figure 7 shows·the input-referred spot nOise to be flat at about
1.2nVIVHZ over the 0 - 25kHz bandwidth. Figure8 shows the
low frequency noise spectrum which highlights the low l/f
noise corner at 2Hz.
In situations where small output, low impedance transducers
are used, such as strain gages, amplifiers must have low
voltage noise to maintain a good signal-to-noise ratio. The
low voltage noise of 1.2nV/VHZ suits this instrumentation
amplifier for use in many low impedance transducer applications.

A LOW-NOISE HI-FI QUALITY PREAMPLIFIER
The AC-coupled preamplifier of Figure 9 exhibits an inputreferred noise voltage density of only 900pV/VHZ at a gain
of 200. Preamplifier noise is minimized by using a singleended input stage consisting of three transistors of a MAT -04
connected in parallel. This technique lowers the effective
base-spreading resistance, reducing thermal noise from this
source by a factor of .,[3. Tight matching of the three paralleled transistors is a critical requirement. If the matching is
poor, one transistor will steal most of the stage current, effectively removing the two other transistors from the circuit.
Noise reduction, achieved by paralleling the transistors,
would therefore be lost. Schottky nOise, or shot noise, is
minimized by using a relatively high stage current of 2mA.
The fourth transistor (01) of the MAT -04 is used to bias the
input stage. Op amp A 1 forces the voltages across Rl and R2
to be equal, setting the bias current at 2mA. Overall feedback
for the preamplifier is provided by resistors A7 and A8. Gain
for this circuit is:

FIGURE 8: Low Frequency Noise Spectrum Showing Low
2Hz Noise Corner; Gain

~

1000

The circuit is characterized with the gain of 200. Compensation components R3 and C2 may need to be optimized for
other values of gain. Open-loop gain of the preamplifier is
over 10 million.
Figure 10 ill:Jstrates the wide bandwidth of the preamplifier.
Figure 11 shows the broadband noise spectrum (0 - 25kHz) to
be flat at 900pV/VHZ. Distortion of the preamplifier is
0.035% at VOUT ~ 10Vp _p, f ~ 10kHz.

HORIZONTAL AXIS

11-22 APPLICA TION NOTES

= 0 TO 5Hz

FIGURE 9: Low-Noise AC Preamplifier

... 15V o-------..,------------------~------------o

. . 15V

+15V

R2

7.Skn
Rl
22HZ

R3

C2

lkn

l000pF

>-......- - 0 OUTPUT

-lSV

r-

-----1

MAT-04E

I

1
1

1
I

I
1
1
1
1
1

1

Q1

R5

R4

2

I
121

lkn

3kn

3

I

14

1
1

I

1

1

_ _ _ _ _ --11

L_

A8
RS

lkn

15n
A7

5n

Cl

INPUT

o-----=.j f ' + ' - - - - - - - - - - - - - - - - '
1000~F

FIGURE 10: Low-Noise AC Preamplifier,
Gain vs Frequency

FIGURE 11: Spot Noise of AC Preamplifier at Gain = 200
from 0 to 25kHz

50

45

'"

z
;;

\

I

iii

40

"
35

NORMALIZED VERTICAL AXIS = 260pW y'HiPER DIVISION

REFERENCED TO INPUT.

30
10

100

lk

10k

lOOk

en AT 10kHz'" 6OOpV/v'Hl

1M

II

FREQUENCV (Hod

NONLINEAR CIRCUIT APPLICATIONS
Another application area where precision matched transistors
are a powerful tool is in the generation of nonlinear functions.
These are based upon the transistor's logarithmic property
which has the following form:

(7)

VBE = Vr

In(~)

where: Vr = kT
q
IS = saturation current

APPLICA TION NOTES 11-23

The circuit of Figure 12 is a vector summing amplifier that has
the following generalized transfer function:
(8)

Op amp A3 forms a current-to-voltage converter giving
VOUT= 10' R2,

VOUT = k.JVA2 + VS2

(15)

where k is a scale factor

For the circuit of Figure 12, R1 = R3, and R2 =

The circuit (see Figure 12) consists of two log amplifiers each
using two transistors and an op amp. The voltage across the
series transistors 01 and 02 is equal to the voltage across 03
and the base-emitter of 04. Summing this voltage loop leads
to:
(9)

Vnln(-111)
Sl

+VT2ln(~) =VT3ln(~)
IS2

IS3

(16)

2InI1=lnIA+lnI0=ln(IA'10)

Exponentiating both sides yields:
(11)

112 = IA '10

122 = Is' 10

Summing the currents at the emitter of 04 gives:
(13)

10 = IA + Is

(17)

Solving equations (11) and (12) for IAand I s, and substituting
into equation (13) yields:
(14)

10 =

~ +!t
10

10

(~) .JVA2 + VS2

The MAT-04 can also be used to implement other nonlinear
functions such as the square and square-root circuits shown
in Figures 13 and 14 respectively. Similar to the vector summing amplifier, the analysis begins by summing the voltages
across transistors 01,02,03, and 04 of the squaring circuit
shown in Figure 13;

Similar analysis for transistors 07, 06, OS, and 04 leads to:
(12)

VOUT =

~,

A value of Rl/.J2 for resistor R2 builds in a scale factor of
1/.J2, which allows +10V to be applied to both inputs simultaneously without the danger of VOUT exceeding the output
range of op amp A3. The built-in protection diodes on the
MAT-04 allow the input voltages to go negative without damaging the MAT -04. Under this condition, the output voltage is
zero. The interconnections of the two MAT-04s in the circuit
reduce errors due to inherent mismatching and temperatureinduced differences between the two matched quad transistors. The accuracy of the vector summing amplifier is better
than 0.5% over an input range of 10mV to 10V.

+VT4In(IOUT)
IS4

All transistors are precisely matched and at the same temperature, therefore the Is and VT terms cancel. Equation 9 is
simplified to:
(10)

VOUT=R2v'(~)2+(~~)2

VT1InC~~) +VT2lnC~~)
10) + VT4 In
= VT3 In ( IS3

= .J1 12 + 122

(IREF)
I;-

FIGURE 12: Vector-Summing Amplifier
C3
l00pF
R2
23.3kll

~~~-----------------o~~

r--,

'---I
I
I

1
01

I

I
I

1

i

L_~~ ___ I

I
I
I
IL

-----,

I

Cl

v- /

L _____ J

/

8
06'1"<9H

_ _ _ _ _ _ _ _ _ _ _ - , MAT·04

Rl

v.O--..JYoI'r----<>-=-i
33kn

I
I
I

11-24 APPLICA TfON NOTES

~

10

I.
L __________

I

-+.?

,---~--~
I
I
C2 I
L ________ -'
1000PFI

'000pF
L_____________________
____
1

I
I

R3

I'--+-""",_-ov.
33kU

I
~

FIGURE 13: Squaring Amplifier
C2

'OOp'
A2

33kn

v+

>,'---+--oVOUT

r-----------..,

I

MAT-04EI

I

'0

I
I

I
IL ______ _
C,

'.....'

-,

IL

_________________ •

,.

I

I

,.

I

v+

I
I

IL _________ _
A3

5IJkn

A.

50kn

-lSV

FIGURE 14: Square-Root Amplifier
A2

33kn
C2

'OOp'
>,'--+---0 Your
'0

v+ v-

',N

r---

,-----MAH4E-----l

IREF

I

I
I

c,

I

II

I

1000pF

v+

I
I
I

IL __ _

,.O3F----.

A5

A3

2kn

5IJkn

A'

5IJkO

_15V

APPLICA TION NOTES 11-25

Once again. all the transistors are precisely matched and at
the same temperature. so the IS and VT terms cancel giving:
(18)

2 In liN = In 10 + In IREF = In(lo • IREF)

Exponentiating both sides of the equation leads to:
(19)

10 = (lIN)2

IREF
Op amp A2 forms a current-to-voltage converter which gives
VOUT= R2 '10. Substituting (VIN/R1) for IINand equation (19)
for 10 yields:
(20)

VOUT =

(I~:F) (~~) 2

A similar analysis made for the square-root circuit of Figure 14
leads to its transfer function:

operating range of the output op amp. Resistor R4 can be
changed to scale IREF. or R1 and R2 can be varied to keep the
output voltage within the usable range.
Unadjusted accuracy of the square-root circuit is better than
0.1% over an input voltage range of 100mV to 10V. For a
similar input voltage range. the accuracy of the squaring circuit is better than 0.5%.
In summary. the accuracy of nonlinear circuits depends heavily upon the logarithmic conformance of the transistors used
in the circuit. Extrinsic reSistances and the Early effect cause a
deviation from the ideal logarithmic transistor behavior. For
small values of Vce. the collector-base voltage. these effects
can be lumped together as an effective bulk resistance. reE.
The logarithmic transistor relationship of equation (7)
changes to:
(22)

(21)

V
= R2- / (VIN)(lREF)
OUT
"
R1

In these circuits. IREF is a function of the negative power
supply. To maintain accuracy. the negative supply should be
well regulated. For applications where very high accuracy is
required. a voltage reference may be used to set I REF. An
important consideration for the squaring circuit is that a sufficiently large input voltage can force the output beyond the

11-26 APPLICATION NOTES

VeE = VT In (~)

+ (Ic reEl

An obviOUS way to reduce reE- induced error in nonlinear
circuits is to reduce the maximum collector currents. but the
op amp offsets and leakage currents become a limiting factor
at low input levels. An operating range of 1OI'A to 1mA is
recommended. The MAT-04. which is specifically designed to
have a low bulk resistance of 0.4.0. further reduces reEinduced error in nonlinear circuits.

AN·111
APPLICATION NOTE

NANALOG

WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062·9106 • 6171329-4700

A Balanced Summing Amplifier

The summing amplifier circuit shown in Figure 1 represents an
excellent virtual ground summing amplifier using a balanced
differential design that includes extremely low noise and wide
bandwidth as featured by the SSM-2015. Any size audio mixing
system can benefit from balanced virtual node mixing (summing). The low cost and exceptional performance of this design
can be incorporated in any system with balanced or mixed
balanced and unbalanced input sources.
IC 2, the PMI OP-41 , serves as a DC servo-amplifier that is
referenced to signal ground. The circuit functions as an integrator with a long time constant that retains the integrity of low
frequency audio signals down to 5Hz, and keeps eOUT = OV DC'
(±1 OmV DC). The OP-41 is a FET input amplifier, with low input
offset voltage (Vos) and high input impedance. Although many
low performance JFET/CMOS operational amplifiers can be
employed, the summing output V DC is a function of the servo's
input offset voltage and its temperature coefficient (.1.V0s'.1.T),
which must be kept low for direct coupled summing applications.
In this design, the following facts predominate: es = 0, and is =
O. erN is the algebraic sum of the input(s) e'N1' e'N2' e'N3' e'Nn and
etc. eOUT = [e'N1 (R",R'Nl) +e'N2(R",R'N2) + e'N3(R",R'N3) + e'Nn(R",

R'Nn))' etc. The input impedance therefore equals R'Nl ' R'N2' R'N3'
R'Nn' etc. The overall gain of the circuit is set by RF, and the gain
of the individual channels can be adjusted independently by the
values of R'Nl' R'N2' R'N3' R'Nn' etc.
For individual source input(s), gain is Ao = R",R'N.
The circuit configuration produces linear signal mixing at the
summing nodes (IC l pins 10,11), whereas es = 0; therefore, no
interaction occurs between the source inputs. Owing to the fact
that the SSM-2015 is a bipolar transistor device, the noise is low
(1.3nV/-#iZ). The commonly used values of 1OkO for RFand R'N
are optimal for both minimum noise and previous stage loading,
eliminating the need for buffer amplifiers and their noise contribution.
The input common-mode rejection for the SSM-2015 is typically
1OOdS as a result of true differential input topology. The differential thermal noise and DC offset drift is nearly eliminated by
the common substrate construction employed. To exploit the
high CMR of the SSM-2015, all Signal resistors should be
matched resistor networks or should employ 0.5% or better
resistor tolerances.

RF

r-~10~~~----~------~------~~-----------o~~BU

1----<_--11-------+------_---<> GND

II
+---+---......--_---0 GND

FIGURE 1
APPLICA TION NOTES 11-27

The output circuit topology of the SSM-2015 is complementary
bipolar producing overall performance of 6V/fJ.s slew rate, and
is able to drive a 2kO unbalanced load. The circuit described
can be directly coupled, eliminating coloration and distortion
associated with coupling capacitors; The circuitry following this
amplifier could be AC (capacitor) coupled if the DC servo IC 2
offset voltage of :l:10mVoc is objectionable.

TABLE 1: Circuit Performance Specifications

TMD + Noise (@ +23dBu 20Hz to 20kHz)

0.008%

Audio performance challenges the best test equipment that
might be used to measure high performance analog designs.
For example: worst case THD for this circuit measures less than
0.008%, and IMD less than 0.02% over a band-width of 10Hz to
20kHz. See Table 1 for more performance details.

IMD (@ +23dBu SMPTE 60Hz & 4kHz, 4:1)

0.015%

Frequency Response (dB 20Hz to 20kHz)

SIN Ratio @ +23dBu

103dB

CMRR (60Hz)

100dB

Slew Rate

6V/fJ.s

Output Voltage (2kO load)

11-28 APPLICA TfON NOTES

:1:0.02

+23dBu or 11VRMS

1IIIIIIII ANALOG

AN·112
APPLICATION NOTE

WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 6171329-4700

A Balanced Input High Level Amplifier

The balanced amplifier in Figure 1 utilizing the SSM-2015 features adjustable gain and can accept nominal audio signals
from -27.5dBu to +OdBu with more than 30dB of headroom.
The input terminals can tolerate common-mode voltages of 30
volts peak-to-peak. Common-mode noise rejection is greater
than 1OOdB at 1,000Hz, while the EIN (Equivalent Input Noise)
is a low -124dBu.

input impedance. The output circuit topology is complementary
bipolar producing 6V/jJ.s slew rate, and is able to drive a 2kQ
unbalanced load. The circuit described can be directly coupled
eliminating the distortion associated with coupling capacitors.
Circuitry following this amplifier could be AC (capacitor)
coupled if input normal-mode DC voltages are expected at the
input of this circuit. Worst case THO measures less than
0.008%, and IMD less than 0.015%.

The IC. amplifier circuit is gain adjustable, and the design
utilizes a 12-position switch with 2.5dB steps. Other resistor
values can be calculated to accommodate custom gain requirements.

Input components C" C2, R., and R2 constitute a single pole
low-pass filter that limits the input voltage slew rate, curbs
interface transient intermodulation distortion, and keeps the
amplifier from slewing. The input network has little effect on
phase response within the pass band of 20Hz to 20kHz. To
maintain high frequency common-mode performance, capacitors C, and C2 should be matched for 1% tolerance.

IC, is PMI's SSM-2015 true differential input IC amplifier. Its
input circuit utilizes two identical low noise bipolar transistors,
with access to the emitters that provide the gain adjustment. RG
(R' 4 through R24 ) sets the amplifier's gain using the equation:
Gain

= 3.5 + (20~03)

for RB, R'B

For an output voltage of -10dBu, the balanced input amplifier
circuit has an input sensitivity range of O.OdBu to -27 .5dBu. The
common-mode voltage trim is included for maximizing application common-mode noise reduction and also allows the use of
low cost components.

=10.0kQ

The emitter feedback design exhibits both minimum noise and
maximum common-mode rejection while retaining a very high

R.

~~--~~--~----~------------o·~T

-1OdBu

1-..,,---1---_-------0 GND

••

r------~---#c.j---<>

II

ev

~~~---II-lllt"t..-,..2ft--T-~~,-o-·ev

GND

SW 1 GAIN SELECT

•

0

~

iii
ri:

! !
ri:

ri:

•

51

!

ri:

!

51

51

ri:

ri:

!

~

;:

;;

rr.

rr."

rr.

g

.

• ••

g

:;;
A

a

i:i
~

rr.

••
~

~

rr.

FIGURE 1

APPLICATION NOTES 11-29

SW

G dB

elN(dB}

RG

1

10.0

0

2

12.5

-2.5

3

15.0

-5.0

R14
R 15

VALUE(n)

R

ro

28.0k
9.53k

4

17.5

-7.5

R 16

4.99k

5

20.0

-10.0

R17

3.09k

6

22.5

-12.5

2.05k

7

25.0

-15.0

R1B
R 19

8

27.5

-17.5

R 20

1.00k

1.40k

9

30.0

-20.0

R2l

715

10

32.5

-22.5

511

11

35.0

-25.0

R22
R 23

12

37.5

-27.5

R24

280

374

Specific gain can be calculated from the equation:
GaindB = 20 log [3.5 + (20

~03)]

for Re, Rle = 10.0kn

TYPICAL APPLICATIONS
This design is ideal for use as the input amplifier in audio
distribution amplifiers, for balanced input audio routing switchers, as the input buffer ahead of the A-to-O codec in digital
recording and mixer equipment, or for the low noise high level
input of mixing consoles.

11-30 APPLICA TlON NOTES

TABLE 1: Circuit Performance Specifications

Frequency Response (dB 20Hz to 20kHz)

±O.1

SIN Ratio @ +23dBu

103dB

THO + Noise (20Hz to 20kHz) @ +23dBu

0.008%

IMO (SMPTE 60Hz & 4kHz, 4:1) @ +23dBu

0.015%

CMRR (60Hz)

100dB

Slew Rate

6V/IlS

Output Voltage (2kn load)

+23dBu or 11 VRMS

AN·113
APPLICATION NOTE

IIIIIIIIIII ANALOG

WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 617/329-4700

An Unbalanced, Virtual Ground Summing Amplifier

The summing amplifier circuit shown in Figure 1 represents a
splendid unbalanced virtual ground summing amplifier. The
design utilizes the SSM-2134, PMI's superior version of the
popular NE5534 bipolar operational amplifier. This low noise
amplifier can now be implemented where most equipment
manufacturers use FET input operational amplifiers. The circuit
described features reduction in noise, temperature, and input
impedance effects on static condition output voltages, and
elimination of unity gain instability.

OUT
t----~~~~--1-~R~,~__o e-10dBu

1000

The SSM-2134 helps reduce wide-band noise figures by 3dB to
10dB, while improving the frequency and phase response
performance. Only minimal value compensation (C 2) is required for the SSM-2134. In the feedback loop, C, improves
stability while keeping the slew rate at 10V/flS and bandwidth
greater than 100kHz.
In this circuit, note the following design facts: e OUT is the
algebraic sum of the input voltage(s) e ,N1 , e,N2 , e ,N3 , e'Nn and
etc. eOUT = (-) [e 'N1 (R F/R ,N1 ) + eIN2(RF/R,N2) + eIN3(RF/R,N3) +
eINn(RF/R,Nn)], etc. The individual input impedance therefore
equals R,N1 , R,N2 , R,N3 , R,Nn , etc. The overall gain of the circuit
is set by RF, and the gain of the individual channels can be
adjusted independently by the values of R,N1 , R,N2 , R,N3 , and
R,Nn ·
For individual source input(s), voltage gain = RF/R ,N .
The circuit configuration produces linear signal mixing at the
summing node (common tie pOint C RF, R,N1 , R,N2 , R,N3 , and
"
R,Nn), whereas e s = 0, there is no interaction between the
source inputs. Owing to the fact that SSM-2134 is a bipolar
device, noise is low (2.8nV/v'Hz). The commonly used values of
10kQ for RF and R'N are optimal for both minimum noise and
previous stage loading, eliminating the need for buffer amplifiers and their noise contribution.

R 4 1OO0

"---_+--1l1li'---0 +18V
Rs 1000

'-.-----t---N-I'----o -18V

FIGURE 1

TABLE 1: Circuit Performance Specifications
Frequency Response (20Hz to 20kHz)

SIN Ratio (@ +23dBu)

±0.02dB
104dB

THD + Noise (@ +23dBu, 20Hz to 20kHz)

0.007%

IMD (SMPTE 60Hz and 4kHz, 4:1)

0.015%

Slew Rate
Output Voltage (2kQ load)

10V/flS
+23.3dBu or 11.3VRMS

This design produces maximum amplifier bandwidth with unconditional circuit stability for both input and output impedance
(reactive or not) variations.

APPLICATION NOTES 11-31

II

11-32 APPLICA TION NOTES

11IIIIIIII

AN·114
APPLICATION NOTE

ANALOG

WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETIS 02062-9106 • 6171329-4700

A High Performance Transformer-Coupled Microphone Preamplifier

The SSM-2015 or SSM-2016 low noise differential amplifier is
utilized in a transformer-coupled microphone preamplifier. The
circuit shown in Figure 1 represents a microphone preamplifier
with high performance, wide dynamic range, and ultra low
noise. The design features a Jensen transformer-coupled
preamplifier circuit with balanced/floating input, 15000 input
loading, three step input attenuator, phantom microphone
powering, and twelve amplifier gain choices. Although the
design shown includes a twelve position gain selector, fixed
gain applications can utilize the component value calculations
and formula provided.
The design provides microphone input loading of 15000. Input
loading is capacitive reactive, and at higher input voltage
frequencies, the low-pass network and transformer characteristics help attenuate unwanted normal-mode RF and ultrasonic
voltages that might be present at the input terminals.
The input circuit contains a three-position input altenuator used
to optimize source levels versus amplifier headroom. As usual,
it's a compromise of headroom and preamplifier signal-tonoise. The attenuation is OdB, -10dB, and -20dB while maintaining an input impedance of 15000.

A phantom microphone powering circuit is included for condenser microphones that require 24 to 48 volts DC power.
The common-mode voltage range is limited only by the transformer's primary-to-shield breakdown voltage. Common-mode
rejection is a product of the primary-to-secondary isolation and
provides detachment of the microphone wiring environment.
Although the balanced single-pole low-pass filter at the input
terminals provides protection from radio frequency interference, this network, along with the capacitive effect of the
primary winding to the grounded shield, plus the phantom
powering resistors present a circuit path for external RF voltages to enter the preamplifier's circuit ground. A carefully
planned single point (power supply) grounding, and the true
balanced and differential input topology of the SSM-2015/2016
amplifierwill eliminate unwanted external noise signals.
The network composed of R4 and Cs at the transformer secondary serves two functions. It minimizes transformer riSing
secondary winding signal amplitude with rising input frequency
and deters secondary ringing, while helping to prevent amplifier
input slewing. The SSM-2015(2016 differential input improves
transformer performance substantially as compared with the
conventional unbalanced design.

R,.

"our

10""

C,
l000pF

-1OdBu

C.

R.

GND

10""

·'N

12

C,
l000pF

c.

11

150pF

10

+

+18V
-18V
R12

1Il00
GND

GND

.48V
PHANTOM

R13

MICRO POWER

1Il00
SW1 GAINADJ

8

10

11

12
39.65dB

FIGURE 1
APPLICATION NOTES 11-33

II

The circuit design incorporates a gain switch with twelve (12)
calculated gain settings. The Jensen transformer, model JE11 OK-HPC used in this application has a voltage gain of 17.9dB.
For an output voltage ..of -10dBu, the microphone amplifier
circuit has an input sensitivity range of -65dBu to -17.5dBu,
with a typical output headroom of 33dB. The preamplifier circuit
shown is gain adjustable from9.6dB to 39.6dB in 2.5dB steps.
PMl's SSM-2015/2016 input circuit utilizes two identical low
noise bipolar transistors, with access to the emitters, that
provide the gain adjUstment. The output circuit topology is
complementary bipolar producing 6V/I1s (2015) and 10V/I1s
(2016) slew rate into a 2ka unbalanced load.
RG (R 17 through R28 ) sets the amplifier gain uSing the equation:
VG = 3.5 + (20 ~03)
for R14' and R15 = 10.0ka.

SW

GdB

*eIN(dB)

1
2
3
4
5
6
7
8
9
10
11
12

9.6
12.1
14.6
17.1
19.6
22.1
24.6
27.1
29.6
32.1
34.6
39.6

-37.5
-40.0
-42.5
-45.0
-47.5
-50.0
-52.5
-55.0
-57.5
-60.0
-62.5
-65.0

RG

R17
R 18
R19
R 20
R2l
R22
R23
R24
R25
R26
R27
R28
"Input attenuator set to the OdB position.

VALUE (a)

100k
37.4k
10.7k
5.49k
3.32k
2.15k
1.47k
1.05k
750
549
402
215

Unspecified overall circuit gain can be calculated from the
equation:

Gla

= 20109[3.5

+(20~03)l

For ±36V DC power rails, although the headroom increases to
39.3dB, the SSM-2016 will dissipate 1.2 watts with no signal
applied, and 1.5 watts worst case signal conditions into 600a
load. Therefore, IC package cooling should be taken into
consideration. Please see the SSM-2016 data sheet for IC pinout connections and recommended compensation capacitor
values. All other circuit component values shown here apply.
The transformer-coupled microphone preamplifier circuit described above demonstrates robust, real-world usage refinements, along with most operational features required by equipment designers to deliver the highest performance. It will handle
the most hostile microphone environments without distress to'
either the circuit or the user.

TABLE 1: Circuit Performance Specifications

±O.15dB

Frequency Response
(20Hz to 20kHz, -60dBu, 50dB gain)
THO + Noise (20Hz to 20kHz, -60dBu, 50db gain)
IMO (+23dBu, SMPTE 60Hz and 4kHz, 4:1)

0.045%
0.05%

EIN (Equivalent Input Noise, 150Q source)

-127dB

Input Impedance (20Hz to 5kHz)

1500a

Source Impedance

150a

CMR at 1kHz (common-mode rejection at 1kHz)
CMVR (common-mode voltage range)

Output Voltage
SSM-2015 (±18VDC ' 2ka load)
SSM-2016 (±24VDC ' 2ka load)

120dB
±150VDC

Slew Rate (overall circuit)

6V/I1s

Gain Range (overall circuit)
+17.9

TYPICAL PERFORMANCE
Frequency response versus amplitude is ±0.2dB from 20 to
20,OOOHz, and THO + noise is better than 0.03% over gain and
frequency range described, with a typical EIN (Equivalent Input
Noise) of -127dBu. See Table 1 for detailed performance
specifications.

11-34 APPLICA TION NOTES

For applications where additional headroom is required, the
SSM-2016 should be used. The SSM-2016 can be powered
with up to ±36VDC rails and drive 600a loads. If ±24VDC rails are
used, headroom increases to 35.7dB (typically), while the /EIN
remains at -127dB. As a consequence of the increased power
supply voltage, the SSM-201'6 package power dissipation will
typically be 600mW with ±24VDC rails (no signal), and will rise
to 725mW with worst case signal conditions into 600a load.

17.5dB to 36dB
+23dBu or 11VRMS
+25.7dBu or 15VRMS

Output Headroom
(SSM-2015, 2ka load, -10dBu nominal)

33dB

AN·115
APPLICATION NOTE

ANALOG
WDEVICES

11IIIIIIII

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 6171329-4700

Balanced Low Noise Microphone Preamplifier Design
The SSM-2015 differential amplifier is utilized in a transformerless, active-balanced input amplifier. The circuit shown in
Figure 1 provides a microphone preamplifier design with excellent performance and low noise. The design features a transformerless preamplifier circuit with true-balanced input, 15000
input loading, phantom microphone powering. and high common-mode rejection. The design shown also includes a twelve
position gain selector, orforfixed gain usage, component value
calculations.

The circuit design incorporates a gain switch with twelve (12)
calculated gain settings. For an output voltage of-10dBu, the
microphone amplifier circuit has an input sensitivity range of
-65dBu to -27.5dBu, and an output headroom of 33dB. The
overall circuit gain is adjustable from 27.5dB to 55dB in 2.5dB
steps.

SW

The design includes microphone input loading of 15000, but
the load resistor can be changed to accommodate other applications. Input loading is capacitive reactive at higher frequencies to attenuate unwanted RF and ultrasonic voltages at the
input terminals.

G dB

eIN(dB)

RG

1

27.5

2
3
4

30
32.5
35
37.5
40
42.5
45
47.5

-37.5
-40
-42.5
-45
-47.5
-50
-52.5
-55
-57.5
-60
-62.5
-65

R'5
R'B
R'7
R'8

The phantom microphone powering circuit provides power for
condenser microphones that require 24 to 48 volts DC. The
zener diodes CR" CR 2, CR 3, and CR 4 protect the input transistors of the SSM-2015 when connecting the microphone to the
preamplifier circuit.

5
6
7
8

The common-mode voltage range is :t5.5 volts. Its cornmonmode rejection is optimized for most applications by the truebalanced and differential input topology of the SSM-2015. A
balanced Single pole low-pass filter at the input terminals
provides protection for the circuit from radio frequency interference and prevents slewing of the SSM-2015 amplifier. The
output circuit topology is complementary bipolar producing 6V/
!-Is slew rate, and able to drive a 2kO unbalanced load.

10

9

50
52.5
55

11
12

R22
R23
R24
R25
R2B

C,
e,.

1000PF,~
1000pF

LD

tA'1.87kn

TC'

GND

A,
6.81kO

C,

RS

'2 ~
5.6V

.....-!!

~ ~'

",

+

•

~3
'2 ~

13

7

~

-=-

~

Ii!

;::.

~

IE

IE

IE

~~~~+ ;:f~~~
GND
+.BV

),sw,

•

3

2

R ..
1000

150""

:::~~~
1

+lBV

- .BY

A..

114

rl

~ ~.

R..
1000

3

Vee /5

v,~7.

A

10ka

GND

.J,

~F

1

le,
SSM·2015

r1!!

10ka

~,

=.~1kO

OUT

12

331.lF sov

•

- 1QdBu

r,;~I~"F

10kO

33"F SOV

1.00k
715
511
374
280
205
154
115
86.6
63.4
47.5
35.7

R'9
R20
R2,

n.
HI

VALUE (0)

5

a. ~

IE

IE

6

Ii!
t

17

,.

31.6"" ......-..fV\t------+

lVF
10%

100""

-15V

14

TANTALUM

12 4.64kO

-=- QUTPUTLEVEL 5-4'01<_"_ _ _ _---'

RELE~~5-4'Ok1l-----./'N---=-----'

+

FAST

1.5ko.

U1

SSM-2013

U..

SS"'2134
SSM-2nD

Us

112 OP-215GP

U6

112 OP-215GP

u2 • U3

+
R..
15""

NOTE, u,. U3. U•• & OJ,;
POWER SUPPLY CONNECTIONS
AND BYPASSING ARE NOT SHOWN

-15V

-15V

FIGURE 1

APPLICA TlON NOTES 11-37

&I

The AGe attack and compression response is altered by
adjusting the integrator charging time constant or integrator
wave shape current. The three-position ATTACK switch allows
selection of fast, medium, and slow compression and AGC
response. When the slow position is selected, an insignificant
amount of compression will take place, while fast and medium
combine compression with the AGC action. The AGC release
rate is controlled by a constant current discharge of the integrator capacitor. The recovery time constant is linear and adjusted
by changing the integrator discharge current supplied by 01 and
regulated by the RELEASE rate control.
The SSM-2134 has been selected for its low noise and high
performance characteristics. The AGC circuit described is of
the feedback class, that is, the level detecting rectifier follows
the voltage controlled amplifier stage. This class of AGC circuit
combined with the complementary gain reduction compression,
driven by RMS level detection, and adjustable attack and
release AGC action, allows this circuit to be as unobtrusive or
as conspicuous as desired.
The flexibility and high performance of this design, along with
the simplicity and cost effectiveness, allows this design to be
suitable for incorporating in mixing console designs, or in standalone products.

11-38 APPLICATION NOTES

TABLE 1: Circuit Performance Specifications

Input Voltage Range
(Nominal for OdBu Out)

-26dBu to +10dBu
(6mV to 2.45\1 RMS)

Rectifier Type

RMS

AGC Amplifier Class

Feedback

Attack Time

20 to 200ms

Recovery Time (6dB)

3 to 32 SEC

VCA Feedthrough (Trimmed)

-100dB

Gain Limit Range (Gain Reduction 22)

-26dBu to -12dBu

Frequency Response (20Hz to 20kHz)

±0.2dB

SIN Ratio (@ ±10dB Gain)

106dB

THO + Noise (@ +23dBu, 20Hz to 20kHz)

0.01%

IMO (@ + 23dBu, SMPTE 60Hz & 4kHz, 4:1)

0.02%

Output Voltage Slew Rate
Output Voltage (2kn Load)

6V/IlS

+22dBu or 1OVRMS

AN-121
APPLICATION NOTE

11IIIIIIII ANALOG
WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 617/329-4700

High Performance Stereo Routing Switcher
The SSM-2402 Dual Audio Switch comprises the nucleus for
this 16 channels-to-one high performance stereo audio routing
switcher, which features negligible noise and low distortion over
the frequency range of 20Hz to 20kHz. This performance is
achieved even while driving 600Q loads at signal levels up to
+30dBu.
The SSM-2402 affords a much simplified electrical design and
printed circuit board layout, along with reduced manufacturing
cost, when compared with discrete JFET circuits of similar
performance. The electrical performance of the design described is vastly superior to CMOS switch designs, which are
more prone to failure resulting from electrical static discharge.
The switching control of the SSM-2402 may be activated by
conventional mechanical switches or 5 volt TTL or CMOS logic
circuits. The application shown utilizes a simple mechanical
control switch for illustration purposes only. Many diverse XfY
control schemes, destination control, or computer controlled
designs can be utilized.

The "T" configuralion of the SSM-2402 switch provides excellent ON-OFF isolation. The SSM-2402 also features 7ms ramped turn on and 4ms ramped turn off for click-free switching.
Additionally, the switch has a break-before-make switching
sequence. Both features become significant in large audio
switching systems where the audio path can pass through
multiple switching elements. Such controlled switching is very
important in large systems used in broadcast program switching
or in production work.
The application circuit design also employs the SSM-2015
balanced input amplifier (Figure 1). The input impedance is high
(~100kQ), balanced or unbalanced. The input circuit incorporates a single pole RFI filter with a cutoff frequency set at
145kHz. In addition, the input circuit attenuates the signal by
25dB and extends the common-mode input voltage range to
:t98 volts peak, with common-mode rejection greater than 70dB
from 20Hz to 20kHz. The SSM-2015 is set to produce a 15dB
gain. The signal drive level into the SSM-2402 switch is then

~

-

-

-

-

-

-

-10kQ -

-

-

-

-

-

-

-

:

5pF

I

I
33.20

r---,IVV~r<>

LO

GND

~GND
CR~~~T~~ll

ov - OFF

INPUT I
I

+5V . ON

III
t==

+18V

INPUT (RIGHT) :
(+2OdBu)

?

I

L---~~~'-00-"F~

lO o-'--+...,f\j'V'-~

25V

~+'r.'~OO~"~F'

I
U4 (PIN 7) I
Us (PIN 7) I
Us {PIN 7) I

:
I

I

25V

I
AUDIO INPUT AND CROSSPOINT SWITCHING CIRCUIT (TYP - 16)
~-------------------------

-18V

I
U 4 (PIN 4) I
Us (PIN 41 ,

~ ~u~o-"u..:P~~_CI~C~IT~!:...2) __ u~ (:IN_4)~

FIGURE 1: Switcher Schematic
APPLICA TION NOTES

11-39

I
I NO.1

HI <>--",W~..-j
INP.UT (LEFT) I
(+20dBu)
LO·<>--.--.W--'--OLO

:

- -

-

AUDIO OUTPUT

-

SSM-2134 I

I
>-t-~HI

I

I

o--,c-.t-'-~LO

L__:

+
~ ____ ...!N!!U!.&.9~~P.PI~T _____ I

LO

------------------

HI~I
_ SSM-2015
INPUT (LEFT) I

LO

:

r-------------------,

+

I

~

: NO.3

.

STEREO AUDIO CROSSPOINT SELECTOR

1

SM.2015

~
-

INPUT (RIGHT) :

I
I

0--++-''-_+-+-+-1---+

+
L ~ _ _ _ _ IN!U! &_Cf!.0!!..S~I~T _ _

LO

-

2

3

16

I

nnr"'!ft'

+5V~VV

V

:

_ _ _ I

.. CAN BE EXTENDED TO 16 INPUT & CROSSPOINT CKTS

.------------------ I

I NO. 16

HI o-,~IN'-.-t

I

INPUT (LEFT) I

I
LO 0-;--./\/11'-......-1 ~"'"
I
HI

SM.2015

~

INPUT (RIGHT)

_

:

+

LO

~ __ "_ _ JNfU!&_CFtOtll'P.9I!T _____ I

FIGURE 2: Switcher Functional Block Diagram
+10dBu with a +20dBu input level and +14dBu peak, well within
ideal operating range. Good signal-to-noise is maintained, with
generous head-room available by electing to use ±18VDC
power supply voltages.
The routing switcher bus carries high level unbalanced audio,
but is driven with low impedance sources. With the output impedance of the SSM-2015 at virtually 00 and the SSM-2402
switch ON, resistance is typically 600. Bus-to-bus crosstalk is
exceptionally low. For example, assuming 14pF coupling between buses and 20kHz signal, the crosstalk (isolation) exceeds 80dB. The 14pF would be representative for the 16 X 1
stereo design shown. Shielding of the buses with a printed
circuit board ground plane and physically isolating the input and
output circuits will reduce the crosstalk even further. The "T"
configuration of the SSM-2402 switch virtually eliminates
crosstalk between the various input signal sources.

11-'40 APPLICA TION NOTES

The output amplifier incorporates a buffer amplifier that provides 4dB of gain (nominally), with adjustable output level trim
control. The buffer also isolates the switching bus from the
balanced output amplifier circuit. The balanced output is designed to drive 6000 loads and utilizes two SSM-2134 IC
amplifiers. The differential design increases drive capability, yet
increases the heat dissipation surface area, and keeps Ie
package temperature well within safe operating limits, even
when driving 6000 loads. The SSM-2t 34 is recommended due
to its low noise, wide frequency response, and output drive
current capabilities.
Overall performance of the 16 X 1 stereo switcher is noteworthy.
Input-to-output frequency response is flat to within 1dB over a
10Hz to 50kHz band. Total harmonic distortion plus noise is less
than 0.03%, from 20Hz to 20kHz. SMPTE intermodulation distortion is less than 0.02%. The use of ±18VDC power supplies
produces a +30dBm clip level, even when driving 6000 loads.

TABLE 1: Circuit Performance Specifications
Max Input Level

+30dBu

Input Impedance, Unbalanced

100kQ

Input Impedance, Balanced

200kQ

Common-Mode Rejection (20Hz to 20kHz)
Common-Mode Voltage Limit
Max Output Level
Output Impedance
Gain Control Range
Output Voltage Slew Rate

>70dB
±98V Peak
+30dBu/dBm

670
±2dB

6V/IlS

Frequency Response (±0.05dB)

20Hz to 20kHz

Frequency Response (±0.5dB)

10Hz to 50kHz

THO + Noise (20Hz to 20kHz, +8dBu)

0.005%

THO + Noise (20Hz to 20kHz, +24dBu)

0.03%

IMO (SMPTE 60Hz & 4kHz, 4:1, +24dBu)

0.02%

Crosstalk (20Hz to 20kHz)

>80dB

SIN Ratio @ OdB Gain

135dB

III

APPLICA TION NOTES 11-41

11-42 APPLICA TlON NOTES

AN·122
APPLICATION NOTE

ANALOG
WDEVICES

11IIIIIIII

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 617/329-4700

A Balanced Mute Circuit for Audio Mixing Consoles
The SSM-2402 Dual Audio Switch enhances the performance
and simplifies the design of balanced high level switching
(Mute) circuits used in audio mixing consoles. The use of the
SSM-2402 and SSM-2134 creates a design that has negligible
transient noise (as a result of signal switching), and exceptionally low signal distortion over a wide dynamic range. The balanced high level voltage switch then drives a virtual ground
summing bus through 1OkQ resistors. Also included is a design
for a virtual ground summing amplifier.

The SSM-2402 is a monolithic dual audio switch that improves
electrical performance and eases printed circuit board layout
design. The design reduces manufacturing cost when com"
pared with discrete JFET designs of similar performance.
Electrical performance is measurably superior to CMOS switch
designs, and will be less prone to failure from electrical static
discharge.

R,

37.4kn

10kn
(-6dSm NOM.)

,pF

Rs

HI

I.""

V.

HI

"0

I.

INPUT

(LEFT)
LO

OUTPUT

(LEFT)

12
37.4kn

R,

BALANCED SIGNAL

tOka

SOURCE (LEFT)

10pF

SIDE 2

.pF
LO

SEE SSM PRODUCT GUIDE fOR CONNECTIONS

,.0

Rs
tOkQ

LEFT AUDIO BUS
(VIRTUAL GROUNDS)

ON

~
MUTE

~

CMOS OR TTL GATES

+S-(ON)
OV - MUTE (OFF)

RIGHT AUDIO BUS

MUTE (ON OFF)

CONTROL

R,
37.4kC

10pF

.

tOka

10"F

Rs

HI

I.""

l00kQ

'pF

,.g

V.

37.4kQ 14

OUTPUT

HI

U"

INPUT
(RIGHT)

SSM·2402

(RIGHT)

I.

37.4kQ 6

12

LO

R,

37.4kn
tOka

BALANCED SIGNAL

SOURCE (RIGHT)

SIDE2

10pF

LO

SEE SSM PRODUCT GUIDE FOR CONNECTIONS

"0

Rs
NOTES:

,pF

tOka

U1. U2- SSM·2122

u3_4. 5' 6< 7. e, 90 10- SSM·2134
U'l, 12 - SSM-2402

FIGURE 1: Audio Mixer Channel Mute (On/Off) Circuit, a Balanced Design with High Level Bus Switching
APPLICA TION NOTES 11-43

II

The "TN switch configuration of the SSM-2402 provides excellent ON-OFF isolation. The design shown further improves the
ON-OFF isolation and left/right channel crosstalk figures by
maintaining the common-mode rejection ratio of a fully balanced design. The switch features a 7ms ramped turn-on and
4ms ramped turn-off, and guaranteed break-before-make
switching sequence for transient-free audio switching. The
system performance is improved for large audio consoles that
have multiple switches in the audio signal path.

TABLE 1: Circuit Performance Specifications

The switch control ports are easily interfaced to conventional
5VDC TTL or CMOS digital control circuits, further simplifying
the control circuit design. Furthermore, product reliability and
serviceability are improved by the simplified design. The
application shown Lises an elementary control circuit to functionally illustrate control voltage requirements. Customized
logic gate control schemes or computer-controlled designs can
be easily implemented.

Frequency Response (±O.OSdBu)

20Hz to 20kHz

Frequency Response (±O.5dBu)

10Hz to 50kHz

The application circuit design employs dual audio switches
driven by U3 , U4' Us and Us inverting amplifiers. Their gain is
controlled by two dual voltage controlled amplifier (VCA) elements U, and U2 • A simplified signal path is shown for application clarity. For additional design information of the SSM-2122
dual VCA, consult the data sheet.
The design shown in Figure 1 is signal phase noninverting, and
incorporates a minimum number of components to minimize
noise. The input signal source should be balanced to maximize
separation and crosstalk isolation. PCB layout should also
utilize equal inductance in each side of the signal path wiring,
and include equal stray capacitance to ground and other signal
paths to obtain maximum performance. The SSM-2122 VCA
provides good gain tracking of the two audio channels, while
maintaining accuracy in the balanced signal path.

U" and U'2 are utilized as high level switches so that other postswitching functions can be employed. A nominal drive level of
OdBu balanced (-6dBu unbalanced) is applied to the switch.
This level is arbitrary, but will satisfy most signal-to-noise and
headroom compromises. The output of amplifiers U3 ' U4' Us' and
Us are AC coupled prior to the switches to further minimize the
switching transients caused by active component offset voltages. The balanced virtual ground mixing buses are current
driven by Rs of 10kQ. This value can affect overall system
performance, and should be modified to suit the size of the
mixing bus system. A greater number of input mixing channels
will warrant lower bus drive current. Although the individual
values of Rs and RF can be altered, their values must be the
same for a summing amplifier voltage gain of one (1).

11-44 APPLICA TION NOTES

Max Input Level
Input Impedence, Balanced
Common-Mode Rejection (20Hz to 20kHz)
Common-Mode Voltage Limit
Max Output Level
Output Voltage Slew Rate

+30dBu
75kQ
>70dB
±12V Peak
+3OdBu
12V/lls

THO + Noise (20Hz to 20kHz, +8dBu)

0.005%

THO + Noise (20Hz to 20kHz, +24dBu)

0.03%

IMO (SMPTE 60Hz & 4kHz, 4:1, +24dBu)

0.02%

ON/MUTE Isolation (20Hz to 20kHz)

>85dB

SIN Ratio @ OdB Gain

135dB

The active switches' ON resistances are typically 60Q and are
well matched. One should use 1% or better tolerance series
resistor Rs (10kQ) to minimize imbalance in the signal path. In
the OFF state, the "T" configuration of the switch virtually
eliminates leakage of the input source signal into the mixing
busIes). Greater than 100dB mute isolation at 1kHz can be
obtained with prudent printed circuit board design since the
SSM-2402 control inputs and switch terminals are separated by
ground guards.
The use of ±18VDC power supplies allows a +30dBu (balanced)
clipping level. All integrated circuit components mentioned will
operate reliably at ±18VDC' and noise contribution will be indiscernible, even in large mixing systems. The balanced input
to balanced output frequency response is typically greater than
10Hz to 50kHz, within 1dB. Total harmonic distortion plus noise
will measure less than 0.01%, from 20Hz to 20kHz at +30dBu,
with SMPTE intermodulation distortion less than 0.02% under
the same measurement conditions.

AN-123
APPLICATION NOTE

ANALOG
WDEVICES

11IIIIIIII

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 .6171329-4700

A Constant Power "Pan" Control Circuit for Microphone Audio Mixing
The SSM-2134 permits the design of a constant power, transient-free "PAN" control circuit suitable for installation in the
highest performance audio mixing consoles. The design incorporates unique and vital features. The PAN IN/OUT switch does
not introduce transient type noise or interruptions in the audio
when activated or deactivited, and when panning, an accurate
constant power output is maintained between the sum of the two
channels. The design allows "punching-in" and "punching-out"
of the PAN circuit while mixing down or on-the-air, without
transient clicks or holes in the mix.

in the center) forms an attenuator that has a 14dB loss. Rotating
the PAN control in either direction decreases the attenuation to
-lldB for one channel and maximum attenuation for the other.

The design utilizes conventional parts, e.g., a single SPST
switch and a linear 10kQ potentiometer. U, (SSM-2134) is used
as a unity gain, inverting buffer with an input impedance of
37.4kQ. The input source could be a VCA element or audio
directfrom the fader control. The values shown will allow a VCA,
for example, the SSM-2013, to be used with only minor additions. The overall application circuit is noninverting from input to
output.

Amplifier (U 2 & U3 ) gain is:

The 15kQ series input resistors Rs ' plus the inverting input
15kQ RI in parallel with 5kQ (1/2 of 1OkQ, with the PAN control

..1...=.1.+_1_
RL
RI
5kQ'

RL

= 3.75kQ

Attenuation is calculated as:
dBLoss = 2010g_R
= 20 log
3.75kQ
_LRL + Rs
3.75kQ + 15kQ

dBGAIN

-14dB

= 20 log RF = 20 log 75k!J = +14dB
At

15k!J

The frequency response is typically 10Hz to 50kHz, within
0.5dB. Total harmonic distortion plus noise will measure less
than 0.007% from 20Hz to 20kHz, and SMPTE intermodl,Jlation
distortion less than 0.01%. The amplifier clipping level is
+24dBu with :!:leVoc power supply rails. Headroom is nominally
30dB, and 27dB at full PAN for the operating channel.

PAN

J!!..I.....
OUT

15kg

75kQ

5pF

1=

10,..

PAN

10pF

AUDIO FROM A
VCAOR OTHER
SIGNAL SOURCE
(-6dBu NOM.)

15ka

r---It-+~ ~f:Q

6V

IL)OUT
(-6 dBu NOM.)
(-3 dBu TO -BOdBu)

1ookO

10l1F

15kD

1SkU

75kQ

SpF

1.:

10"F

6V

,.g

IR)OUT
(-6 dBu NOM.)
(-80 dBu TO -3dBu)

100kQ

FIGURE 1: Constant Power Type Control Circuit with Transient Free IN/OUT Switching
APPLICATION NOTES 11-45

II

TABLE 1: Circuit Performance Specifications
PAN Range, L -C- R (L Out)

+3dB -OdB- -BOdB

PAN Range, R .... C- L (R Out)

+3dB .... OdB- -BOdB

Max Input Level

+24dBu

Input Impedance, Balanced

37.4kO

Max Output Level (> 6000 ",18V DC PS)

+24dBu

Headroom
Output Voltage Slew Rate

30dB
<6V/lAs

Frequency Response (",0.05dB)

20 Hz to 20kHz

Frequency Response (",0.5dB)

10 Hz to 50kHz

THO + Noise (20Hz to 20kHz, +8dBu)

0.005%

THO + Noise (20Hz to 20kHz, +24dBu)

0.03%

IMO (SMPTE 60Hz & 4kHz, 4:1, +24dBu)

0.02%

SIN Ratio

130dB

11-46 APPLICA TlON NOTES

AN·124
APPLICATION NOTE

1IIIIIIII ANALOG

WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 6171329-4700

Three High Accuracy RIAA/IEC MC and MM Phono Preamplifiers
Although the digital compact disk is rapidly supplanting the vinyl
disk as the popular media method far professional and con·
sumer audio entertainment, the electro-mechanical recording
and reproduction of audio signals has many more years of life.
The group of phono preamplifier application designs below will
make the future years with vinyl more productive and pleasant.
The applications employ solid engineering concepts, and dismiss "golden ear" discussions.

One design includes an input scheme for both moving coil (MC)
and moving magnet (MM) - or variable reluctance - transducers. All designs employ extremely low noise circuit topologies,
high accuracy active and passive RIAA (Recording Industries
Association of America) equalization with selectable old RIAA
or RIAA/IEC (International Electro-Technical Commission)
curves. The applications incorporate both consumer and balanced output circuit configurations.
BALANCED OUTPUT

+44dB GAIN

GAIN TRIM

10ka

, - - - - M f ' - -....-O A

+4dB

A 0-----,

+14dB

a.19kQ

20'"

R,
9.76kQ

C2

MC'
PHONO

INPUT

(:.~d.::~

+-....._ .......---'

O.01~F

O.01tiF

1 % (SEE NOTES)

1% (SEE NOTES)

O.22"F
5%

ai.aka + 200Q

100"

316kO

R2

2kQ

RIAAlIEC

RIAA
10ka

37.4kD

HI

BALANCED
OUTPUT
(0 TO +1OdBul
37.4kQ

LO

INPUT LOADING SELECTOR

.9K

!!..

!!..

47K

50

200

+28dB GAIN

R,

10ka

3l.6Ke

,.---/lo/V'----..-oA

109

1O"

L-......-IVV'---.............., (-10dBu)

109

.,BV o----<~

MM~

PHONO

INPUT

-18Vo--.....h

'-.....--+--. R~rue~~:~
POWER

(-48dBu)
(3mVI

100"F
5V'

~

SUPPLY

OUTPUT
(CONSUMER)

V
EE

+ 100I1F

100"

35V

PSG

NOTES: U, - SSM-201S

u2. U3• U4• Us - SSM·2134
1% - POLYPROPYLENE OR POLYSTYRENE METALIZED FILM CAPACITORS
• MOVING COIL
**MOVI~G MAGNET

FIGURE 1: High Accuracy RIAAlIEC MC or MM Phono Preamplifier
APPLICA TION NOTES 11-47

•

+22.5dB

-O.17dB

+16.6dB
~--~

-17.67dB

+16.6dB

-3.35dB

QdBGAIN
-1OdBU

OUTPUT
(CONSUMER)

(-4SdBu)

_-l

INPUTo-.......

HI

",

7.95ms

53ka

NOTE: GAIN OR LOSS AT 1kHz (SINE WAVE)
SIMPLIFIED SCHEMATIC
BALANCED OUTPUT

+14dS

37.4IQ

'DOC

GAIN TRIM
+4dB

1.19k'"

31.me",

HI

'Dka

'oc

-lOdBu

BALANCED
OUTPUT
(GTO +lOdBu)

37.4kQ
OUTPUT
(CONSUMER)

LO

r
VEE Vee

INPUT LOADING SELECTOR

~

J!.

47K

50

.JL

16.6dS GAIN

22.5dBGAIN

16.6dBGAIN

'00

31.6kQ

22pF
'ka

3400
31.6ke

PHONO
INPUT

2.2nF

O.l"F

,% (SEE

,% (SEE

(-4BdBu)
MM TYPE

NOTES)

loDe

3.S7kC

24.3kn

NOTES)

VEE Vee

NOTES: U 1 - SSM·2015
U 2 - SSM-2134
1% - POLYPROPYLENE OR POLYSTYRENE METALIZED FILM CAPACITORS

FIGURE 2: Passive (Multi-Filter) RIANIEC Equalized Phono Preamplifier

A HIGH ACCURACY DESIGN
In the High Accuracy RIAA/IEC Phono Preamplifier shown in
Figure 1, both MC and MM transducer input configurations are
presented. Both utilize the PMI SSM-2015 differential amplifier
and take advantage of the high common-mode rejection it
provides. The overall circuit structure does not incorporate any
design compromises. It provides the lowest possible noise,
adjustable MM input loading, highest accuracy RIAA filtering,
and is completely devoid of transient and frequency dependent
gain errors. The wide bandwidth stages minimize in-band phase
shift, and provide exceptional phase and frequency response
accuracy. This allows the RIAA/IEC filter to render the exact
reciprocal of the recorded phase and frequency characteristics.

11-48 APPLICA TION NOTES

Referring to Figure 1, the Me input circuit has input loading (R L)
set at 1DOg. (Note: some Me transducers require 109 loading
for maximum reproduction accuracy. For these, replace RL with
a 109 metal film resistor.) The input circuit gain is 44dB, and
provides a -20dBu signal level at point A. 44dB gain should be
adequate for most Me cartridges available. If U 1 gain requires
adjusting, use the equation:
GdB

= 20109 (3.5

+ 20

~ 1(i)

Rs sets the U 1 bias value and contributes to symmetrical
amplifier slewing. The RIAA filter stage that follows U 1 stage(s)
all but eliminates noise produced by the input amplifier.

BALANCED OUTPUT
GAIN TRIM

+4dB

+14dB

10kQ
31.6kQ

37.4kO

"g

HI

10kg

BALANCED
OUTPUT
(0 TO +10dBu)

37.4kD

OUTPUT
(CONSUMER)

LO

INPUT LOADING SELECTOR
69K

.!.

...L

.!!..

47K

50

100

200

+3Od8 GAIN

+3OdB GAIN

-20<18

10kA

-O.17dB

31.6kn
O.15~F

1% (SEE
NOTES)

'''''
PHONO
INPUT

2B.7kD

(-48dBU)
MM TYPE

"lOg

O.06I1pF
1% (SEE
NOTES)

24.3kD

NOTES: U1 - SSM-2015
U 2 • 3. 4 - SSM-2134
1.% - POLYPROPYLENE OR POLYSTYRENE METAUZED FILM CAPACITORS

FIGURE 3: Passive RIAAlIEC Equalized Phono Preamplifier
The next stage contains the RIAA-RIAAlIEC equalization filter
and is built around U2, the SSM-2134 operational amplifier, and
is an active feedback type filter. The overall gain of this circuit
at 1,000Hz is -2.5dB. RIAA equalization requires a gain of
19.3dB at 20Hz, and attenuation of 19.6dB at 20,000Hz. The
open-loop gain of U2 is greater than 1OOdB at 20Hz, and 60dB
at 20,000Hz, ensuring exceptional equalization accuracy.
Three filters make up the RIAA reproduction curve. The time
constants are: 751-1s, 3181-1s, and 3180l-ls, and a fourth time
constant in the RIAAlIEC curve is 7960l-ls. The IEC filter was
Introduced to minimize warp and infrasonic signal interference
while maintaining flat frequency response down to 40Hz.
The 751-1s filter is formed by resistors R1 (9.76kO) and R2
(31.8kO) in parallel with capacitor C2 (0.01I-1F).
The 3181-1s pre-emphasis filter is formed by R2 (31.8kO) and
C2 (0.01I-1F).

Table 1 contains the complete RIAAand RIAAlIEC reproduction
equalization characteristics. RIAAlIEC switching allows selection of either reproduction response curves. For the "audio
purist," C5 can be eliminated for a direct coupled deSign, thus
reducing envelope and group delay distortions. All amplifier
feedback circuits are direct coupled, and are referenced to
circuit ground. The closed-loop gain is kept low to minimize
input offset voltage. Therefore, only very small DC voltages can
be expected at the output of the directly coupled version.
The high level amplifier, U5, provides +12.7dB gain and feeds
the unbalanced Consumer Output jack, with a nominal-1 OdBu
level. U5 is followed by balanced output buffer amplifier. The
nominal output level is continuously adjustable from O.OdBm to •
+10dBm at the balanced output terminals. The output source
impedance is 750, and will drive 6000 loads to a maximum
+30dBm clip point level. Table 2 shows circuit performance
specifications.

The 3180l-ls filter is formed by R3 (318kO) and C3 (0.01I-1F).
The fourth pole, IEC 7960l-ls, a high pass filter is formed by
R4 (31.6kO) and C4 (0.22I-1F), and provides 3dB attenuation
at 20Hz rolling off at -6dB/octave thereafter.

APPLICATION NOTES 11-49

TABLE 1: RIAAJlEC and RIM Playback Characierisiics

TABLE 2: High Accuracy Circuii Performance Specificaiions
MC Nominal Input Level

-64dBu (0.5mV)

Frequency
(Hz)

RIAA/IEC
Relative Level
(dB)

2.0

-0.2

2.5

+1.8

3.15

+3.7

Common-Mode Rejection (20Hz to 20kHz)

4.0

+5.7

Common-Mode Voltage limit

5.0

+7.6

Nominal Output Level, Balanced

6.3

+9.4

Max Output Level, Balanced

RIAA
Relative Level
(dB)

MC Input Impedance

1000

MM Nominal Input Level

-48dBu (3.0mV)

MM Input Impedance, Resistive

69kO or 47kO

MM Input Impedance, Capacitive

50pF to 350pF

8.0

+11.2

Output Impedance, Balanced

10.0

+12.8

Gain Control Range, Balanced

>50dB
±10V Peak
+8dBu/dBm
+30dBu/dBm
700

O.OdBu to 10dBu/dBm

12.5

+14.1

Nominal Output Level, Unbalanced

-10dBu

16.0

+15.4

Max Output Level, Unbalanced

+24dBu

20.0

+16.3

+19.3

Output Impedance, Unbalanced

1,0000

25.0

+16.8

+19.0

Output Voltage Slew Rate

>6V/

31.5

+17.0

+18.5

40.0

+16.8

+17.8

RIM Reproduction Characteristics
(20Hz to 20kHz)

±0.25dB

50.0

+16.3

+16.9

63.0

+15.4

+15.8

80.0

+14.2

+14.5

100

+12.9

+13.1

125

+11.5

+11.6

160

+9.7

+9.8

200

+8.2

+8.2

250

+6.7

+6.7

315

+5.2

+5.2

400

+3.8

+3.8

500

+2.6

+2.6
+0.8

630

+0.8

1,000

0.0

0.0

1,250

-0.8

-0.7
-1.6

1,600

-1.6

2,000

-2.6

-2.6

2,500

-3.7

-3.7

3,150

-5.0

-5.0

4,000

-6.6

-6.6

5,000

-8.2

-8.2

6,300

-10.0

-10.0

8,000

-11.9

-11.9

10,000

-13.7

-13.7

12,500

-15.6

-15.6

16,000

-17.7

-17.7

20,000

-19.6

-19.6

11-50 APPLICA TlON NOTES

RIAA/IEC Reproduction Characteristic
(2Hz to 20kHz)
Wideband Frequency Response (±1.0dB)

"'S

±1.0dB
O.OHz to 70kHz

Signal-to-Noise Ratio (20Hz to 20kHz)

>90dB

THO + Noise
(20Hz to 20kHz +8dBu, Any Output)

0.01%

IMO (SMPTE 60Hz & 4kHz, 4:1)

0.02%

A PASSIVE MULTI·FILTER DESIGN
The Passive Split Multi-Filter RIAA/IEC Preamplifier design,
shown in Figure 2, is intended for moving magnet (MM) input
phono transducers. The design has an extremely low noise
circuit topology, high accuracy passive RIAA/IEC equalization
filters, and both unbalanced consumer and balanced output
circuits. The input configuration utilizes the SSM-2015. It provides the lowest possible noise, adjustable resistive and capacitive input loading, and high accuracy passive RIM filtering
totally devoid oftransient and frequency dependent gain errors.
Referring to Figure 2, the following two stages contain the RIAARIAA/IEC passive equalization filters. All high pass and low
pass filters are passive. The signal is amplified by U2 and Ua
SSM-2134 op amps. The overall gain of the circuit at 1,OOOHz
is 38dB. RIAA equalization requires a gain of 19.3dB at 20Hz,
and attenuation of 19.6dB at 20,OOOHz. Open-loop gain of U2
and Ua is greater than 1OOdB at 20Hz, and 60dB at 20,OOOHz.
Closed-loop gain of U, is 22.5dB, and U2 , Ua is 16.6dB,
ensuring an extensive gain margin for phase accuracy. Refer to
Table 3 for complete circuit speCifications.

TABLE 3: Passive Multi-Filter Circuit Performance
Specifications

TABLE 4: Uncomplicated Passive Circuit Performance
Specifications

MM Nominal Input Level

MM Nominal Input Level

-48dBu (3.0mV)

MM Input Impedance, Resistive

69kO or 47kO

MM Input Impedance, Capacitive

50pF to 350pF

Common-Mode Rejection (20Hz to 20kHz)
Common-Mode Voltage Limit
Max Output Level, Balanced

+30dBu/dBm

Nominal Output Level, Balanced

+8dBu/dBm

Output Impedance, Balanced
Gain Control Range, Balanced

> 50 dB
±10V Peak

700
O.OdBu to 10dBu/dBm

-48dBu (3.0mV)

MM Input Impedance, Resistive

69kO or 47kO

MM Input Impedance, Capacitive

50pF to 350pF

Common-Mode Rejection (20Hz to 20kHz)
Commom-Mode Voltage Limit

> 50dB
±10V Peak

Max Output Level, Balanced

+30dBu/dBm

Nominal Output Level, Balanced

+8dBu/dBm

Output Impedance, Balanced

700

Gain Control Range, Balanced

O.OdBu to 10dBu/dBm

Nominal Output Level, Unbalanced

-10dBu

Nominal Output Level, Unbalanced

-10dBu

Max Output Level, Unbalanced

+24dBm

Max Output Level, Unbalanced

+24dBu

Output Impedance, Unbalanced

1,0000

Output Impedance, Unbalanced

1,0000

Output Voltage Slew Rate

>6V/tJ. s

Output Voltage Slew Rate

RIAA Reproduction Characteristic
(20Hz to 20kHz)
RIAAlIEC Reproduction Characteristic
(2Hz to 20kHz)
Wideband Frequency Response (±1.0dB)
Signal-to-Noise Ratio (20Hz to 20kHz)

±0.25dB
±0.5dB
O.OHz to 70kHz

RIAA Reproduction Characteristic
(20Hz to 20kHz)
RIAAlIEC Reproduction Characteristic
(2Hz to 20kHz)
Wide band Frequency Response (±1.0dB)

±O.5dB
±1.0dB
O.OHz to 70kHz

>90dB

Signal-to-Noise Ratio (20Hz to 20kHz)

>90dB

THO + Noise
(20Hz to 20kHz +8dBu, Any Output)

0.01%

THO + Noise
(20Hz to 20kHz, +8dBu, Any Output)

0.01%

IMO (SMPTE 60Hz & 4kHz, 4:1)

0.02%

IMO (SMPTE 60Hz & 4kHz, 4:1)

0.02%

AN ECONOMICAL APPROACH
An Uncomplicated Passive RIAAlIEC Preamplifier is shown in
Figure 3. It is a low cost, practical design for a passively
equalized RIAAlIEC phono preamplifier. The design shown is
for moving magnet (MM) input. It also is an extremely low noise
input circuit design, and includes both unbalanced consumer
and balanced output circuit configurations. The input circuit also
utilizes the SSM-2015, and provides adjustable resistive and
capacitive input loading. Wide bandwidth stages minimize inband phase shift, and provide exceptional phase and frequency
response accuracy. Table 4 details circuit performance data.
SUMMARY
For a phono transducer cartridge to deliver the performance as
intended, it should be loaded with proper resistance and capacitance. The MM input circuits have adjustable transducer loading. Most transducers currently available will be accommodated
with resistive loading of 69kO or 47kO, and capacitive loading
of a few pF (input wiring dependent) to 350pF, in 50pF steps.
If greater input common-mode noise rejection is required, it can
be obtained in all input designs by increasing the value of the
1000 resistor and 0.1 tJ.F capacitor connected between the input
RCA jack shield connection and the main circuit ground point.
The values shown satisfy most requirements for 1 meter cables
supplied with the newer tone arms.

All circuits described are signal noninverting, and constructed
with bipolar Ie amplifiers for lowest noise. They are compensated for widest bandwidth and circuit stability.
To achieve optimum trouble-free performance, a few construction and manufacturing tips should be observed. For grounding
to be truly effective, all grounded components must return to a
single point. This technique is effective in minimizing ground
current loops that can cause excessive noise, signal cross-talk,
AC power line noise, and circuit instability, and permit external
noise spikes to enter. The ground center should be as close to
the input amplifier (U l ) as possible. All grounded components
of U 2 , U 3 , U4 , Us' the output jack grounds, and the power supply
ground lead should be tied to the same U l ground point.
As long as the power supply leads are kept short, and adequately filtered and bypassed with polyester film capacitor at
the regulators, there is no need for individual decoupling capacitors at U 2 , U 3 , U 4 , and Us. The power supply voltages should be
regulated for ±18Voc .
All signal filter components should be ofthe highest quality, i.e.,
metalized polypropylene or polystyrene film, 1% tolerance capacitors (except for Cs' 5% tolerance is OK) and metal film
resistors, 1% or better tolerance.

APPLICA TION NOTES 11-51

II

11-52 APPLICA TlON NOTES

AN·125
APPLICATION NOTE

11IIIIIIII ANALOG
WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 6171329-4700

A Two-Channel Dynamic Filter Noise Reduction System
In this application, the SSM-2120 Dynamic Range Processor
and SSM-2134 op amp are utilized in a dual-channel dynamic
noise reduction circuit, where the input signal level and threshold control determine the corner frequency of a low-pass filter.
47pF

lOpF

The SSM-2120 contains two class A VCAs (Voltage Controlled
Amplifiers) that are used as the filter's control element, and two
wide dynamic range full-wave rectifiers with control amplifiers.
The VCA section or variable resistor is a current device con-

1Okf.1"

r-1f-----1I--lI---IW....,
10kU

35V

Vee
37,4kU

C"
FILTER THRESHOLD
-40_0dBu
10ku

'''''''

"

~

lOki!

2

3

46.4kU

~lrP_F-+__t-~.~n~'-+____~

100
U

22

21

20

19

220

kU

18

46.4k1!

v"

100

n

1

2.74k£2

17

16

,.

15

',~F

'-------l

1.SMU

U3

+

lkU

=
13

~ OUTPUT
lODkn

1

GND

22pF

12
2

5

3

U,

+
10k!l

4

10",F

Hrv-

10kU

SSM-2120

3

,

•

10ku

U,

2

6

10ku Vee Vee

T~:rr

1

,

5

-

5

6

7

100

220

100

U

kU

U

8

9

10

"

2.74ktl

,

•

•

-Ftt:
10kU

46.4ktl
lJlF

1.SMU

~NrT--t-----------~--~~-.

150
kll

F

,

3

46.4kU
10kll

101en

10kO

O.1).lF

50kU

10ku

>--If-<

fEEDTHRU

,.,",

22pF

INY

10kn

INPUT
NONINY

10kU

INPUT'r
10kO

GND

2

V"

t-_\~~;lrF~3'V·4~k!_'______________~~__+-~'~7<~,__2~~~
~v

5

"

10llF
10kU
I
8 6
3 J U2
>'---....------------ll--.t~------f_--.J

+4

7

35V

VEEVcc
U, THRU U6 ARE SSM-2134

FIGURE 1:

':'"

•

6

,

II

VEE Vee

lDk!J

FILTER THRESHOLD
--40_OdBu

"

+

'

~

2_2~F'6

3 +U4

,),"""'>-+-35~lv:--;

10ku VEE Vee

37.4ku

r-o

4

OUTPUT

100kU

t--------------~lr-----_OGND

Two-Channel Dynamic Filter Noise Reduction System
APPLICATION NOTES 11-53

trolled by the + Vc voltage control ports. The VCAs are employed
as variable resistor elements in a single-pole low-pass filter
operating in a virtual ground configuration. The level detecting
rectifier is a full-wave averaging type with more than 100dB
dynamic range, followed by a LOG amp converter. The part also
contains two operational amplifiers with PNP output transistors
used to drive the + Vc ports.
U1 and U2 (SSM-2134) are input amplifiers and source-load
isolating buffers. They provide a choice of non inverting, inverting, or balanced inputs. Unbalanced loading is 10kn and balanced loading is 20kn. U1 and U2 gain is set at OdB, with a 1OdBu nominal input signal recommended using ±18VDC power
supply rails. This configuration will provide an overall circuit
headroom of more than 30dB. In less critical applications, the
feedthrough trim controls and 220kn resistors can be eliminated.
DETAIL CIRCUIT DESCRIPTION FOR U7 (SSM-2120),
AND U3 and U4
The rectifier circuit is configured to provide a negative control
voltage referenced to ground. The LOG amplifier's bias is set by
the 1.5MO resistor. The 1.5MO resistor also provides the
discharge path for the 111F rectifier averaging capacitor. The
discharge time constant controls the low-pass filter's action
toward a lower corner frequency. The LOG amplifier provides a
constant current charging for the 111F averaging capacitor. It
results in an attack (return to flat response) time constant TcO of
approximately Sms, and a low-pass filter activation TCl of 350ms.
The internal op amp of U7 has the gain VG set at 47. The potentiometer at the inverting input provides the adjustable
threshold to activate the filter. The threshold adjustment ranges
from -40dBu to OdBu of input signalleve!. The output from the
op amp drive transistor supplies only a negative control voltage
to the VCA (+V ) control port(s). For example, with the filter
threshold control adjusted to OdB and a -1 OdBu signal applied
to the input, fCl is "'4kHz; or with -20dBu applied, fC2 is "'1.2kHz,
both rolling off at SdB/Octave. With the input signal level
exceeding the filter threshold setting (OV VCA control voltage
present), the overall circuit frequency response is 20Hz to
1SkHz, at±1dB.
The VCA audio input current is limited by the 37.4kO resistor.
The VCAs operate as current devices whose outputs feed the
virtual ground of an amplifier loop. The feedback capacitor
around the amplifier loop sets up a single-pole low-pass filter.

11-54 APPLICA TION NOTES

The SSM-2120 (U 7) inverts the signal current; therefore, Us and
Us are required to invert the output signal that is summed at the
input(s) of U7 •
The design is an effective single-ended noise reduction circuit
with low distortion and noise. When utilized on a noisy signal
source, it will attenuate high frequency noise with inconspicuous operation.

TABLE 1: Circuit Performance SpeCifications
Nominal Input Voltage (-10dBu Out)
Headroom (-1OdBu Out)
Input Voltage Range
Input Typellmpedance, Balanced
Input Typellmpedance, Unbalanced
Dynamic Noise Reduction Class
Filter Activate Time Constant (SdB)
Threshold Range (Level)
Filter Deactivate Time Constant
Signal Rectifier Type
Modulation Feedthrough, Trimmed
Frequency Response (20Hz to 1SkHz)
Filter Type, Low-Pass

-10dBu
+30dBu
-20dBu to +1 OdBu
20kO
10kn
Dynamic Low-Pass
350ms
-40dBu to OdBu
Sms
Full Wave Averaging
-100dB
±1dB
Single Pole, 6dB/Oct

Input 10dB Below Threshold Setting

fCl = 3,800Hz

Input 20dB Below Threshold Setting

fC2 = 1,400Hz

Dynamic Range
@ OdB Gain (Ref. +22dBu)

10SdB

THO + Noise (20Hz to 20kHz)

0.02%

IMD (SMPTE SOHz & 4kHz, 4:1)
Output Voltage (2kn Load)
Output Type
Power Supply

0.05%
+22dBu
Unbalanced
±18Voc Regulated

AN·127
APPLICATION NOTE

r.ANALOG
WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 617/329-4700

An Unbalanced Mute Circuit for Audio Mixing Channels
This application note describes a dual channel unbalanced
analog audio mute switch, for use in audio console mute
circuits. The SSM-2402 dual audio switch, when used in the
virtual ground configuration, truly enhances any audio mute
design. The application, as shown in Figure 1, incorporates
unbalanced stereo input buffers, dual stereo electronic virtual
ground switches (with simplified control circuit), and virtual
ground summing amplifiers.

37.4kD

37.4kO

THE AUDIO SWITCH AS IMPLEMENTED
The design utilizes the SSM-2402 (U 1 and U2 ) dual audio switch
in a virtual ground switching configuration. This method of
operation improves linearity over a wide dynamic range. The
SSM-2402 utilizes JFET switching, with internal wide bandwidth integrated amplifiers applied in a unique configuration.
The result is low transient intermodulation distortion, low THD,
and low IMD, while essentially eliminating all audio switching

".V"------..-,

1~F

T-::~~~~,~~~ o----NoI'------>NIi~--..-"+if--.._--..J,V
...

RF
10ke

5pF

100kD

CHANNEL A

(L)OUT

'''''

AUDIDFROM
VCAOR OTHER
SIGNAL SOURCE

(-6dBu NOM)

,.
12

37.4kQ

CHANNEL A (R) IN

37.4kQ

".

10~F

O---.!I./V'----.-..Jw---,..z.+If-..--o/V'oI'---+-+--'
10ke
100kQ
CHANNEL A

(R)OUT

AUDIO BUS A (l) -

,

AUDIO BUS A CR)

AUDIO BUS B (l)

A-SUS
ASSIGN
100kQ

AUDIO BUS B (R)

+5-(ON)

MUTe

~

CMOS OR TTL GATES
MurE (ON OFF)
CONTROL

ov - MUTE (OFF)
a·BUS
ASSIGN

(OFF)

100kO

".

CHANNEL B

(L)OUT

II

AUDIO FROM

veA OR OTHER
SIGNAL SOURCE

SSM.2402

10
12

RF

R.
37.4kn
37.4k{l
CHANNEL B CR) IN O----NIJ'------1,.....,Mr---..-:'-lf--e----.NIi~--+---'

VEE

10kO

u

FIGURE 1:

5pF

,.0

lOOk<>

U 1• U 2 - SSM·2402
3• U4• Us. U6. U7• U,.

10kQ

u9• UfO

CHANNELS

(R)OUT

-SSM·2134

Audio Mixer Channel Mute (On/Off) Circuit (Unbalanced Design with Virtual Ground Switching)
APPLICA TION NOTES 11-55

transients. The SSM-2402 switch closed (ON) resistance is
typically 60'1 in series with Rs (1 OkQ). As shown in this mixing
system; the tolerance of the 60'1 contributes to less channel
imbalance than the 1% resistor tolerance, thus eliminating the
need for level trim adjustments.
The SSM-2402 employs a "T" switching configuration that
yields superior ON-OFF signal isolation. In the OFF state, the
"T" configuration of the SSM-2402 virtually eliminates leakage
of the input signal (down more than 1OOdB at 1kHz with guard
pins 3, 5,10 and 12 grounded) onto the mixing bus(es). The part
also features a 7ms ramped turn ON and 4ms ramped turn OFF,
for transient free audio switching even with signal applied. The
switch also operates with a break-before-makeswitching sequence. These properties are significant when rnany remotely
controlled electronic switches are connected in series and
controlled by a single device, as in large audio systems managed by an automation computer.
CONTROL INTERFACE
In this application note, the bus assignment (selection) switches
are shown functionally for clarity. The control ports of the SSM2402 can easily be interfaced to conventional5V TTL or CMOS
logic control circuits. +5V DC (logic high) closes the switch (ON),
and OV DC (logic low) opens the switch (OFF). The common
interface levels improve the reliability and serviceability of any
products it's designed into. Diverse logic gate control designs or
computer controlled schemes can easily be implemented.
DRIVE REQUIREMENTS- THE INPUT CIRCUIT
The application employs two SSM-2402 dual audio switches in
a four-bus configuration (two stereo buses) driven by U3 , U4 and
Us' U6 bipolar amplifiers. The buffer amplifiers are signal inverting, with their gain set to OdB (Av = 1). The input amplifiers
also serve as source signal level clippers that prevent the input
signal from exceeding the input range of the switches, thus
preventing the switches from passing a distorted signal when
overdriven in the open (OFF) state. A nominal input drive level
of -1 OdBu is applied to the switch and will maximize the signalto-noise ratio, and optimize headroom. The output of U3 , U4' Us'
and U6 are AC coupled to further minimize the switching transient noise caused by signal path DC voltages from previous
origins.
The virtual ground mixing buses are current driven by Rs
(1 O.OkQ) resistors. Once again, this is a compromise value that
can be changed to accommodate the extent of the mixing bus
implemented. A greater number of input mixing channels will
warrant a lower bus drive current. Although other values can be
used, the resistance values of RB and RF should be the same.

11-56 APPLICATION NOTES

As shown (±18V DC power) Rs will apply approximately 1.7mA
peak current to the mixing bus. This is well within SSM-2402
switching capabilities, as well as the SSM-2134 drive capabilities. The signal current is low enough to keep return grounll
currents low enough to prevent crosstalk resulting from the
mechanical wiring constraints. Returning ground currents independently to the noninverting input of the summing amplifier is
advised.
THE OUTPUT SUMMING AMPLIFIER
The design utilizes the SSM-2134, the PMI version of the
popular NE5534 bipolar operational amplifier. The circuit features a significant reduction in summing amplifier noise, a
decrease in temperature and bus impedance effects on the
static output voltage as a result of using a bipolar amplifier. This
design also balances the input circuit reflected source impedance of the bipolar IC amplifier, alleviating the unity-gain instability and eliminating the unbalanced input topology for inverting
summing designs that could cause output offset.
The SSM-2134 has a noise voltage of 2.8nVI v"Hz, thus the
noise floor is reduced by 3 to 1OdB. Additionally, frequency and
phase response performance have been improved. Only minimal compensation is required in the feedback loop of the SSM2134 to maintain unconditional stability. The slew rate remains
greater than 10V/IlS, with baridwidth exceeding 50kHz.
SUMMARY
The design application shown in Figure 1 is signal non inverting,
and utilizes a minimum number of noise generating elements.
The circuit configuration produces linear signal mixing at the
virtual ground summing node (e s = OVAC); therefore, no reflected interaction occurs between the input sources. The signal
input to any output frequency response is typically 10Hz to
50kHz, ±0.5dB. Total harmonic distortion plus noise will measure less than 0.01%, from 20Hz to 20kHz. SMPTE intermodulation distortion is less than 0.02%. With prudent printed circuit
board design, a greater than 1OOdB mute isolation @ 1kHz can
be obtained.
The application shown employs ±18V DC power supplies to
produce a +24dBu audio output clip level. All SSM components
will operate with equal reliability at ±20VDC ' producing approximately a 1dB increase in clip level. If the extra headroom
is necessary, a ±20VDC power supply voltage is encouraged.
The noise increase will be indiscernible, even in large mixing
systems.

AN·128
APPLICATION NOTE

ANALOG
WDEVICES

11IIIIIIII

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 617/329-4700

A Two-Channel Noise Gate
This application applies the SSM-2120 as a dual-channel noise
gate or adjustable threshold downward expander. A noise gate
is a type of noise reduction system that fully attenuates a VCA
when no audio signal is present. The SSM-2120 contains two
class A VCAs (Voltage Controlled Amplifiers) and two wide

dynamic range full-wave rectifiers and control amplifiers. The
VCA section is a current amplifier device whose gain is controlled by two gain ports that have dBN scaling. The VCAs are
employed as wide bandwidth amplifiers with the current inputs
and outputs operating in a virtual ground configuration. The rec-

47pF

"
II

NONINV

10kn

~2:PF
~j;I

10kU

INPUT

7
8

10k1l

3 J U1

10kn

+,

Nt~:r
GND

6

3~.:

Vee Vcc

47pF

~----~+-----------------~~--~l~

v?

-=-

GATE THRESHOLD

~'I~'F__.l .__+_---FE~~N~V!!~R"---1--~~~----~1.~k!~l----~-++~1.~k~~l-BU____~10k!~'--~~37~_':PF. ~
46.4k11
3

+----,/W----....---------+_
I---lt~

1

U3

+

l~F

L...--,

1-0 OUTPUT

6

7
4

TAtlT

100k!!

VeE Vcc

r-~--~'~
•.'~k!~'--JL._J'~k!~'~----------~-------+-OGND

12

1

~

2

,

3

5

6

7

100
!!

220

100

•

9

,.

11

2.74kU

46.4kU

1,F

1.SMU

~~T

k!l

Il

vr

150
kll

0:-

46.4kU

"f

10kO

lOKU

10kn

.6

GATE THRESHOLD
-40_0dBu

FEEDTHRU

47pF

VEE

-f~

NONlNV

lOkU

INPUT
10k1!

'N~~r
10kU

OND

FIGURE 1:

2

31

5
U2

VEE

••

~;

:DIlF

35V

37.4kU

10llF

~

OUTPUT

47pF

22pF

OND

~~

50kn

470

37.4kU

'~~F

7

I!:
35V

VEE Vee

U1> U2. U3, U4 - 55M-2134

+,

10kU

2~PF

"

~
-

3

",

+4

.•
7

VEE Vee

Two-Channel Noise Gate
APPLICA TION NOTES 11-57

Il

tifiers are full-wave averaging type with 100dB dynamic range,
followed by LOG converters. The part also contains two operational amplifiers with PNP output transistors connected in a
common collector configuration.
Two SSM-2134s are used as input amplifiers, U 1 and U2 , to
provide non inverting, inverting, or balanced inputs. Unbalanced
loading is 1OkO and balanced loading 20kO. U, and U2 gain is
set at OdB, and with a-10dBu nominal input signal and ±18Voc
power, will provide overall circuit headroom of 30dB. The
VCA(s) could be DC coupled, although in this application they
are AC coupled to reduce the dependence on trimming the side
chain voltage modulation feedthrough.ln critical applications
the feedthrough trim controls and 220kO resistors should be
added.
The SSM-2120's internal rectifier produces a negative DC
voltage referenced to ground. The LOG amplifier bias is set by
the 1.5MO resistor. The 1.5MO resistor also provides the
discharge current path for the 1j.lF capacitor, that controls the
gate's downward expansion time constant. The LOG amplifier
provides a constant current capacitor charging value. It results
in an attack (return OdB gain) time constant T c of approximately
6ms, and a downward expansion T c of 350ms.
The internal op amp gain Ay is set at 47, with the inverting input
also providing the reference voltage. The reference voltage
range from the gate threshold control allows the gating to
activate at any source signal level from -40dBu to OdBu. The
output from the op amp drive transistor supplies a negative
control voltage to the VCA (+Vc) control port(s). The VeAls)
control ports have a sensitivity of 6mV/dB. As shown, the
voltage divider provides a 2:1 downward expansion slope.
Below the threshold level, the gain slope is 2dB G /dB 1N •
The VCAs are current output amplifiers that are designed to
operate with virtual ground configurations such as Ua and U4 •
The VCA input current is supplied by the 37.4kO resistor and
input voltage signal. The virtual ground amplifier feedback
resistors are 37.4kO. With no VCA control voltage, the overall

11-58 APPLICA TION NOTES

circuit voltage gain is 1 (OdB). Other non-gating gains can be
attained by changing the output amplifiers feedback resistor
value. The VCA input resistor should remain as shown for
maximizing the performance of the VCA(s).
TABLE 1: Circuit Performance Specifications

Nominal Input Voltage (-10dBu Out)
Headroom (-10dBu Out)
Input Type/Impedance, Balanced
Unbalanced
Downward Expander Class
Threshold Sense Time Constant (6dB)
Threshold Range (Level)
Gate Deactivate Time Constant
Signal Rectifier Type
Modulation Feedthrough, Trimmed
Gain Reduction Ratio,
Downward Expansion
Frequency Response (20Hz to 20kHz)

-10dBu
+30dB
20kO
10kO
Feedthrough
350ms
-40dBu to OdBu
6ms
Full-Wave Averaging
< -60dBV

1 to 2 (-2dB/dB)
±0.25dB

Dynamic Range

100dB

THO + Noise (20Hz to 20kHz)

0.02%

IMD (SMPTE 60Hz & 4kHz, 4:1)

0.05%

Output Voltage Slew Rate
Output Voltage (2kO Load)
Output Type
Power Supply

6V/j.ls
+22dBu
Unbalanced
± 18Voc Regulated

AN·129
APPLICATION NOTE

ANALOG
WDEVICES

11IIIIIIII

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETIS 02062-9106 • 617/329-4700

A Precision Sum and Difference (Audio Matrix) Circuit
When constructing an accurate sum and difference signal from
stereo left and right sources, amplitude and phase (delay)
errors can contribute substantial amounts of crosstalk in the reconstructed left and right audio channl9ls. A minor 1dB difference, or 6° phase error, will result in only 25dB stereo channel
separation. The design presented has essentially no phase or
group delay in the sum or difference outputs as measured over

the audio spectrum, 20Hz to 20kHz. This circuit utilizes matched
(laser trimmed) resistor networks combined with high open-loop
gain differential amplifiers to guarantee virtually no phase and
amplitude error in the sum and difference channels.
Amplifiers U3 and U4 (SSM-2134) are utilized as input signal
buffers that provide a low source impedance (00) to the 10kO
summing resistors that feed the virtual ground current summing

1000

11ea

10ka

'pF
INPUT SIGNAL SOURCES
NOMINAL LEVEL (-1OdSu)

Sl~::[o-_-l"O",'''''I'---..___-,'",O/V'''',--_-._~'OV·V'''''__'-____'''''>--_-Ii-'"'i.

SUM

y.-+----oll"~~UT

~~~F

'0....

t--+-I

+

OUTPUT
GND

35V
10ka-

'00II
VEE

10kO*

1mea-

1otcD*

sru~:~o---I'~--'---~~+-+-'--~V'--~

'00II

'00II
Vee

":'"

'00

'0....
'000

II

'pF

POWER SUPPLY

Vee

+18V~

-,ovo----,
6
VEE

~OOij"F

Vee

DIFF

:>"--+----N---o-1.Y
RON 50kll
O.1~F

(BAL) (-1De1Bu)
INY
INPUT

+~F

E

GND

2000pF

150
IUl

RF1
1DIUl

22pF

100
II

11

15

4711

243
1.

1"-4--I6~

AUDIO TO

~ODULATOR

10llF

1Dkn

veA CONTROL SIGNAL

Vee
15kn

COMPRESSOR

R,

CONTROL CIRCUIT

5.49kO

lDkn

UNUSED VCASSM-2120

6V

-V

2.21k!l
VEE

II
SSM-2120 POWER AND GND CONNECTIONS

O.1f.1F
VEE

0-----1.-11

J

.V 0!22
21

6'1

LIMITER CONTROL
CIRCUIT

u1, ~ -

SSM-2134

U3 - SSM-2120
Vee +9VDC

=

VEE =--9Voc

R,
11••"

10J.1F 15
6V

FIGURE 1: Compressor-Limiter Circuit for Transmitter
APPLICA TION NOTES 11-65

the transmitter and is expanded at the receiver by using a
telecommunications industry-standard compandor IC, which
has marginal audio performance as measured by professional
standards. This application'note <;lescribes a companding system
utilizing the SSM-2120 Dynamic Range Processor, which permits considerable improvement over other techniques in terms
of noise, distortion, feedthrough, and other key audio criteria.
Transmitters are battery powered and, hence, pose the most
severe constraints on supply voltages and current consumption. Receivers are often AC powered, so bipolar supplies are
more easily accommodated. Since the SSM-2120 requires split
supplies, a voltage doubler circuit is necessary for the transmitter. In some cases, this may be considered unfeasible. In this
event, however, the SSM-2120 is still very useful in the receiver
expander circuit to complement any compressed signal, and to
improve overall system performance. As a result, the compressor and expander sections of this application can be considered
independently.

THE TRANSMITTER COMPRESSOR AND LIMITER
CIRCUITS
COMPRESSOR
The design described is intended for ±9VDC battery operation,
and includes a third-order high-pass filter for the elimination of
subsonic noise and low frequency pops that would cause
compandDr overload or mistracking.

Figure 1 shows the connection of the SSM-2120 (U 3 ) VCA"
rectifier, and control amplifier as a compressor. The VCA is
connected in the feedback loop of the preamplifier U, to control
the gain. The compressor is designed for a 2:1 compression
characteristic. If the input rises 6dB, the output level will rise
only 3dB. The gain compression expression is:

G .

R2 ' R4

am reduction ratio = ~
,

3

as long asthe rectifier input currents are limited by R5 , Rs (1 OkO)
, and the rectifier has a ~1 OIlA reference current. The SSM2120 rectifier and VCA have a dynamic range in excess of
100dB, resulting in exceptional tracking of the expander/compressor in the compandor system. High quality capacitors and
resistors should be used to support the accuracy of the SSM2120 elements. The small-signal averaging time for a lOIlF
integration capacitor is 25ms. The attack time to 3dB of final
value is also about 26ms and is almost independent of signal
level increases for level changes in excess of + 1OdB. The decay
rate is 3ms per dB. The high-pass filter keeps frequencies below
90Hz from the input of the rectifier, reducing the low frequency
distortion caused by the VCA control circuit.
DC and high-frequency feedback are provided for U, without
sacrificing bandwidth or stability. The gain control is adjusted for
OdBu output with -50dBu applied to the microphone input
terminals. The VCA is Signal inverting. Its output current is
summed, along with the microphone signal current, at the
(virtual ground) noninverting input of preamplifier SSM-2134,
U,. The 10kO resistor at the input of the VCA limits the input

11-66 APPLICA TION NOTES

current, iswhile the 2200pF, 470 network provides frequency
compensation for the VCA, keeping it stable.
The 1OOkO resistor from Vec to pin 10 of U3 establishes the
operating current for the VCA. To minimize power supply
current, all pins of the unused VCA should be refurned to
ground. The FEEDTHROUGH trim control is optional, and it can
be used to minimize the VCA control voltage from feeding
through to the output.
PROTECTION LIMITER
The limiter, uses the second rectifier and control amplifier for
separate and independent attack and decay times, along with a
steeper gain reduction slope. The limiter threshold control sets
the predetermined gain limiting point for high input signal levels.
The gain reduction ratio is 4.6:1 as shown in Figure 1. Typically,
the onset of gain limiting should be set to + 1OdBu at the output.

As in the compressor control circuit, the rectifier input current is
limited by Rs' 10kO, and the rectifier referenced to ~1 OIlA as
well. Lower preCision capacitors and resistors can be used
here. Similar to the compressor, the attack time is much faster
than the decay.
The VCA/Preamplifierwas designed as a system. The VCA was
put in the signal feedback loop of the preamplifier principally to
prevent preamplifier overload, while keeping the overall noise
low, and minimizing component count.
POWER SUPPLY
The application circuit requires two power supply voltages,
±9VDC' The power consumption, for the circuit shown in Figure
1, is less than 15mA from each supply. The design described
will operate properly with good dynamic range as the battery
voltage begins to fall below the nominal9VDC' It is assumed that
two 9 volt batteries would be used, but for the smaller hand-held
wireless microphones, a single 9 volt battery would be required.
Figure 2 depicts a DC-to-DC converter that will supply the

-9V DC '

Vee (+9VDd

10n
1N4004

1kU

10V

33.2kU

1000~F

6

+ 330~F
10V

15V

1000pF

u1: 555 TIMER Ie
CKTGND

FIGURE 2: DC-to-DC Converter for +9Voc to -9Voc at
15mA

The converter circuit incorporates an astable oscillator running
at 25kHz. It is followed by a capacitor-coupled level shifter and
rectifier with a filter. A SE/NE555 timer is used in the "output
sink" mode for maximum efficiency, and longest battery life.

THE RECEIVER EXPANDER SECTION
EXPANDER CONTROL
In Figure 3, the control connection of the SSM-2120 (U 3 ) YeA,
rectifier, and control amplifier is shown. The control circuit
connection to the VeA produces a 1 :2 gain expansion curve. If
the input rises 3dB, the output level will rise 6dB. The gain
expansion ratio expression is:

G .
atnexpansion ratio

R2 ' R4
= ~
1

3

The rectifier input current is limited by a 10kQ resistor connected to pin 9 of U3 , and the rectifier is biased at 1O~A current
through a 1.5MQ resistor connected to VEE. The SSM-2120
rectifier and VeA each have a 1OOdB dynamic range, resulting
in accurate tracking of the compressor.
As with the compressor/limiter circuit, the small-signal averaging time for a 1O~F integration capacitor is 26ms. The attack
time to 3dB of final value is also about 26ms and is almost
independent of signal level increases for level changes in
excess of + 1OdB. The decay rate is 3ms per dB.

The control circuit gain values, as shown above, provide a
control voltage to the VeA section +Vc control port [U 3 , pin 5(19)],
which result in a 1:2 signal expansion characteristic. The
LEVEL control sets the initial overall gain value, and is adjustable from -10dB to +20dB.

EXPANDER AUDIO
Input amplifier U, is a buffer between the input signal source
(FM wireless receiver), the expander rectifier/control circuit,
and the VeA audio signal input. If the signal source output
impedance is below 100Q, U, can be omitted. The nominal
source signal level should be -10dBu. If signal gain or loss is
required, U, gain structure should be modified to provide 10dBu to the VeA input current limiting resistor. The 37.4kQ
resistor ahead of the VeA input [pin 8,(16)] limits peak signal
currents to avoid VeA distortion. The VeA signal input(s) are
virtual ground current inputs. The 150kQ resistor connected to
Vcc and pin 10 of U3 sets the VeA input/output current compliance range. A VeA input shunting capacitor shown from U3 pin
8(16) to ground minimizes signal distortion and keeps the VeA
stable by providing a high-frequency path to ground. The exact
value is determined empirically. The output of the VeA feeds a
virtual ground output amplifier, U2• The overall audio path is
signal non inverting, since the VeA is signal non inverting, and is
combined with two inverting amplifiers U and U2 .
"

l00pF
l00pF

37.4kn
22pF

100j.lF 100.0

(OdBu NOM)

6~AUDID

~DUTPUT

:--fH--1ii+~---'"

POWER & GROUND CONNEcnONS
FOR $SM-2120

11

-vo)------O

VEE

lkg
10V

BALANCED
OUTPUT

"::"

1aka

33.20'

HI
27pF

C"dB")
33.2Q

LO
(CHANNELS 2 THROUGH 7 ARE
OMITTED FOR SIMPLICITY)

Vee
15pF

(-10dBu) 10j.1.F

37.4kD

15V

UN.
14
J3kQ

VEE

243kQ

Vee

FEED·THRU

NULL

Vee

221Q

ON THRESHOLD
~)
0

~
5OkO

10kQ

VEE

4.54kO

VEE

Vee

~
Vee

10ka

L.-,.D"'.,"'' ' '--.....__--l
14

lkg
NOTES:

U, - U,

SSM·201S.'201S
U9 - U ,2 SSM·2120
U13 - U22 SSM·2134

15V

NOTE: SEE SSM HANDBOOK FOR PREAMP DETAILS

FIGURE 1: Automatic Channel Activation Microphone Mixer Diagram Illustrates Blnput Channels

11-70 APPLICA TION NOTES

TABLE 1: Circuit Performance Specifications
Input Voltage, without Preamplifier,
(for +4dBu Out)

-10dB

Input Impedance, Unbalanced

-lkQ

Headroom (Nominal for -10dBu In and Out)

32dB

Turn ON Time (to 3dB of Final Value)

30ms

Turn OFF Time (No Signal)

-3sec

Turn OFF Ramp Time

lOOms

Feedthrough (Trimmed)
ON/OFF Threshold Range (Nominal)
ON/OFF Gain Extent
Frequency Response for ",0.1 dB
SIN Ratio @ OdB Gain
THO + Noise (from 20Hz to 20kHz)

>lmV
OdBu to -40dBu
OdB to -90dB
20Hz to 20kHz
110dB
0.005%

IMO (SMPTE 60Hz and 4kHz, 4:1)

0.02%

Output Voltage Slew Rate

12V/lls

Rated Output Level (600Q Load)
Output Impedance
Output Type
Power Supply Requirements

+24dBu
68Q
Balanced
±15Vpc Regulated

III

APPLICATION NOTES 11-71

11-72 APPLICATION NOTES

AN·135
APPLICATION NOTE

11IIIIIIII ANALOG
WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 6171329-4700

The Morgan Compressor/Limiter

The following application was written by Michael Morgan, a
consultant to PMI with extensive experience in the design of
professional audio equipment, including high-performance
dynamic range processors. While currently a freelance consultant, Mr. Morgan spent nine years at Valley International as a
principal designer of their products.
This application note describes the configuration of a low cost,
high quality compressor with variable attack time and ratio
control using the SSM-2110 Level Detector and SSM-2014
VCA. The discussion begins with an overview of compressor/
limiter fundamentals, and is followed by a description of the
unique attributes of the integrated circuits and their implications
for the design engineer.
COMPRESSORILIMITER FUNDAMENTALS
The function of the audio compressor is, of course, to compress
the dynamic range of the processed audio signal by altering the
gain of its signal path in response to the relative level of the
signal as compared to an arbitrary setpoint called the threshold,
thus adding gain to low-level signals and reducing gain in the
presence of high-level signals.
An audio compressor consists primarily of two functional sections, one of which derives a control signal by measuring and
otherwise manipulating the audio signal to produce a voltage
suitable for the second functional section, which is the gain
control element. The gain control element is a device which can
alter its attenuation, gain, or resistance in response to an external signal, such as a voltage or current.

SHAPING THE RESPONSE
Figures 1a and 1b illustrate thetransferfunction of an ideal compressor as the ratio is varied with a fixed threshold, and as the
threshold is varied with a fixed ratio, respectively. Note that in
both cases, the rotation point is easily identified at OdB. Note
also that the compressor operates as a limiter when the threshold is equal to, or higher than, the rotation point. For this reason,
the device described in this application note may be considered
as a "compressor/limiter," but because it possesses a rotation
point, we shall refer to the device as a compressor.

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INPUT LEVEL (dB)

FIGURE 18: Output vs. Input Transfer Function of an Ideal
Compressor

The audio compressor differs from a similar device, called a
limiter, in that a compressor exhibits a rotation point which is
independent of its threshold setting. The rotation point is the
locus on a graph of the compressor's transfer function at which
the gain control element exhibits unity gain, and through which
all lines derived from data describing the device's output level
as a function of input level will pass. A limiter, in the purest
sense, adds no gain and has no rotation point.
The compressor's ratio is defined as the increase in input level,
in decibels, above the threshold which will result in an increase
of output level equal to 1dB, and is a function of control circuitry
gain. For example, each increase of 1dB in signal level above
the threshold may cause a corresponding decrease in gain
equal to 1dB, thus keeping the output level constant for a ratio
of infinity:1, or it may cause a 1/2 dB decrease in gain, thus
allowing the output level to rise at a ratio of 2:1. A compressor
may have a very high ratio, and conversely, a limiter may have
a very low ratio.

II
-40

-30

-20

-10

D

INPUT LEVEL (dB)

FIGURE 1b: Output vs. Input Transfer Function of an Ideal
Compressor Having a Fixed Ratio Showing the Effect of
Threshold

APPLICATION NOTES 11-73

Audio compressors use two types of circuit topologies. In a
feedback, or closed-loop configuration, the control signal is
derived by measuring the output level of the gain control element. In a fl1edforward, or open-loop configuration, the control
signal is derived by measuring the level of audio present at the
input of the gain control device. Each topology has its typical
advantages and· disadvantages. The most common type of
audio compressor uses the feedback topology. Among its
advantages are: low parts cost; ease of configuration; ability to
use simple, "linear" control circuitry and gain control elements.
The disadvantages of the feedback topology are numerous:
inability to realize continuously variable parameters accurately;
heavy dependence upon circuit trimming to assure consistency
in performance from unit to unit; tendency toward overshoot in
either control signal or processed signal; virtual inability to configure circuitry for performing arbitrary dynamic functions, such
as program control of release times, equalized sidechain functions, and interactive processing having more than one control
function per gain control element.
The feedforward topology has long been considered by equipment designers to be the more versatile method of configuring
audio dynamics processors. Among its advantages are: precise
control of dynamics; ability to accurately and continuously vary
processor parameters, such as ratio and attack-and-release
time constants; easy circuit trimming for unit-to-unit consistency; possibility to realize arbitrary types of dynamics alteration; ease in configuration of interactive processing schemes
using multiple control signals to operate a single gain control
element; and relative freedom from control and signal overshoot. The disadvantages of feedforward topology have traditionally been: dependence upon relatively expensive and little
understood logarithmic circuitry in configuration; difficulty in
sourcing high-quality, low cost logllinear multipliers (dBlvolt
yeAs); dependence upon expensive log/RMS detection
schemes to achieve the required accuracy for wide range of
control.
By using integrated building blocks, feedforward control technology can be realized by equipment designers by virtue oftheir
ease of application and low cost. These readily available integrated circuits deliver performance equal to or surpassing
complicated discrete circuits, and are more cost effective for
general use by equipment manufacturers.
THE SSM-2110 MONOLITHIC LEVEL DETECTOR
The SSM-211 0 level detector Ie represents a significant advancement in low cost, high quality converter circuitry. The
device greatly simplifies the design of feedforward dynamic
processors since it produces an accurate output that is proportional to the log of the absolute value of its input, and the log of
the rms value of its input, in addition to the corresponding linear
values. Such versatility is unique among detector/converter
configurations.
.

VARIABLE TIME INTEGRATOR
In this application, the SSM-211 0 is used in the design of a
feedforward compressor. The log of the absolute value of the
input signal is extracted,then integrated by a Ell x e circuit
which corresponds roughly to an RC network in the linear
domain (see Figure 2).

SSIl~2110

FIGURE 2: Simplified Schematic of a Variable Time Constant Log of Average Integrator Using the SSM-2110
The product ofthis operation is not, as one would expect, the average of the log of the absolute input value. During the integration process achieved by charging the integrator capacitor, e,
the charging current is proportional to the antilog of the voltage
appearing at the base of 0,. Since the voltage at the base of 0,
represents the log of the absolute value of the input, the log and
anti-log terms cancel, thus leaving C to charge as a linear integrator with a current proportional to the absolute value of the
input until the voltage across C approaches the voltage at the
emitter of 0,. In this manner, the order of the logging and
averaging operations are reversed. This is a very important
phenomenon which directly influences the audibility of the compression process, and will be discussed at length later.
The integration time of the circuit in Figure 2 is varied by changing the current through the collector of 03' This is accomplished
by means of the multiplier circuit consisting of the operational
amplifier, transistors 02 and 03' and their associated resistors.
Current IREF is forced to flow through the collector of 02' The
Vbe of 02 is thus made to be proportional to the log of IREF by
virtue of the silicon transistor's intrinsic logarithmic property,
idealized in the equation:
Vbe = kT/q x In(VI.) where
k = Boltzman's constant (1.:38 x 10-23J/K)
T = Temperature in Kelvins
q = Charge on an electron (1.60 x 10-' 9C)
Ie = Collector current
I. = Reverse saturation current (extrapolated as Vbe + 0)

11-74 APPLICATION NOTES

°

When transistors 02 and 03 are closely matched, Vbe of 2,
which appears also at 03'S emitter, causes a current equal to Ie
of 02 to flow through the collector of 03' This transistor collector
current, IREF' may be used to charge or discharge a capacitor,
to cause a voltage drop across a resistor, or may be converted
to a voltage at the output of an operational amplifier. The collector current of 03 may be varied by applying a voltage at the
bases of 02 or 3, or both bases simultaneously. As a rule of
thumb, at 25°C, each 60mV change in Vb will cause a corresponding ten-fold change in 03'S Ie' By using the "shorthand" log
relationship for gain in which a ten-fold change in vo~age (or
current) equals 20dB, we can say that the collector current of 0 3
can be made to vary antilogarithmically at a rate of 1 dB/3mV
(20dB/60mV). In effect, the circuit generates a voltage at the
emitter of 02 which corresponds to the log of the input current,
IREF' adds the control vo~age, then generates a current at the
collector of 03 which is proportional to the antilog of the sum.
Thus the portion of the circuit formed by the operational amplifier, 2 , 3 , and their associated passive components form a
two-quadrant multiplier whose output is a high compliance
current sink.

°

°°

A positive voltage applied to the base of 02 will cause a corresponding decrease in 03'S collector current, while a positive
voltage applied to the base of 03 has the opposite effect, causing an increase in Ie of 03' Both bases may be controlled by
bipolar voltages, but IREF must flow in the direction indicated by
conventional current flow through the transistors (must be
sourced from a voltage more positive than the non inverting input
of the operational amplifier for NPN transistors).
In operation, varying the current which discharges C also
causes a varying offset voltage at the collector of 03 which
equals the change in Vb' and must be compensated for in order
to derive a useful control voltage. Figure 3 shows the response
to a + 10 volt pulse input having a repetition frequency of approximately 4 pps and a duty cycle of 50%. Note that the X-axis
corresponds also to increasing integration time (decreasing Ie

of 03)' The illustration is a composite of several sampled waveforms, thus, scalar references in the X-axis are valid only for
each pulse.
As can be seen in Figure 3, in the log average detection mode.
the response of the device to large level changes is relatively
fast, while the last 50 to 1OOmVof change occurs althe characteristic integration time determined by the status of the charge
on the capacitor, C, as it is discharged by the collector current
of 03' As the vo~age across C approaches the voltage at the
emitter of 0" the transistor behaves less as an antilog element,
and more as a linear resistance proportional to VbiIREF'
These attributes determine the detector circuit's response to
complex waveforms, and directly affect the audibility of the compression process. Considerthe following explanation: Humans
respond to changes in audio signal level by perceiving volume
as being proportional to the log of the acoustic power emitted by
a source, thus the human listener perceives a source emitting
10 watts of "sound," (if the reader will permit such simplifications) to be roughly twice as loud as the same source emitting
only 1 watt. This implies that one should be able to control audio
levels logarithmically for a natural "sound" in the processed
output. That is generally the case, but the principle does not
extend, in a strict sense, to the control of a compressor.
If one accepts the premise that the most common uses of the
audio compressor are to enhance the "loudness" of the processed material, or to "level" the apparent volume of the processed material, one should be aware of the effect of waveform
complexity upon perceived loudness. A simple example is found
in the case of a musician playing an instrument: when called
upon to perform a solo, in order to "stand out" from the background music, the instrumentalist produces more complex
sounds, in addition to producing sounds at a higher relative
level. The increase in complexity provides a psychoacoustic
"cue" which translates to the human listener as increased perceived loudness.

20~V -------------P~--------------~c_--------------------~~------------~~~~-10~V ------------~--~~--------~~------~------------~-------------------------~ ------------~--------~----~------------~~------~-------------------------MAXIMUM ATTACK TIME

FIGURE 3: Output Voltage Response of the Variable Time Constant Log of Average Integrator to a LF Square Wave Input

APPLICA TION NOTES 11-75

II

During the compression process, if the detector circuitry produces a signal which calls for more gain reduction in response
to the added harmonics in a sound which cause an increase in
complexity, the gain control element will comply, thus making a
solo instrumental exitthe compressor at a lower level, foiling the
intent of the performer. This is precisely what happens when
using RMS detection - the detector circuit (correctly) assesses
the increased complexity as an increase in sound energy, and
calls for gain reduction.
.
The log averaging detector is relatively insensitive to increases
in waveform complexity, and "ignores" the loudness cue thus
provided. As a result, a complex waveform exits the compressor
at a slightly higher level than it would if under the control of an
rms detector. This rather unique "quirk" found in the log averaging process allows a solo instrumental or vocal to stand out in
the processed signal, thus preserving the intent of the performer.
As a log averaging detector, the SSM-211 0 exhibits remarkably
little departure from an idealized log curve representing its input
level throughout the entire range of the adjustable integration
time, and offers superior performance to the equipment designer in this type of application. In addition, at higher input
levels, the device does not compress the waveform at its output,
thus under-reading the input value. In fact, the detector exhibits
a gentle and quite predictable deviation from log conformity at
high input current levels which results in the addition of a linear
error term. This causes a slight over-reading of the input, and is
quite useful for aficionados of "soft knee" limiting. It is unlikely
that any real compressor design would require so wide a range
of operation that this deviation might pose a problem (> 60 dB),
but since the error term is so predictable and consistent, it can
easily be corrected elsewhere in the control circuitry if necessary.
THE COMPRESSOR CONTROL CIRCUIT
Figure 4 illustrates a compressor control circuit incorporating
the SSM-211 0 as the detector element. Because the temperature compensation characteristics of the log recovery amplifier
are not required in this application (control of a VCA having a
complementary control sensitivity temperature coefficient) and
to eliminate trimming of scale factor on a unit by unit basis, the
log recovery amplifier is disabled by connecting its inputs to the
IC's VREF output. This step is necessary for proper operation of
the IC when the log recovery amplifier is not used. The log
recovery transistor is not used since offset is not a real concern
in this circuit configuration.
The amplifier in the audio signal path, A" should be of a high
quality, low noise type such as the SSM-2134. The remaining
amplifiers may be general purpose types, preferably having
FET input stages to minimize the effects of input bias currents
on the accuracy of the multiplier circuits.

J

Amplifier A2 , and the SSM-221 0 matched transistor pair 0,
0, b form the voltage-controlled current sink for the variable log
averaging integrator. Amplifier A4 boosts the output of the integratorto a usable level by increasing the nominal6mV/dB scale
factor of the signal at pin 2 to 1V120dB, or 1V per decade. An

11-76 APPLICA TION NOTES

offset corresponding to the change in voltage at pin 2 which
results from varying the integration time is applied via R, 2'
Variable resistor VR2 allows the adjustment of the compressor's
rotation point, or that input level at which the output of A4 will
be OV.
A pair of matching two-quadrant multipliers, which are configured using amplifiers ~ and As along with a four-transistor
array O~ (MAT-04), allow adjustment of the compressor's ratio
and adds sufficient gain as a function of both the threshold
setting from VR4 and A 9, and the ratio, as determined by V~
and As' to maintain the compressor's rotation point. Amplifier A7
converts the current output of the ratio multiplier from 02b into
a voltage which charges the holding capacitor Cs via 03S to a
voltage corresponding to the amount of gain reduction required
of the VCA. Amplifier A'2 converts the current output of the
maintenance gain multiplier from 02e into a voltage corresponding to the quiescent gain required for the VCA to maintain the
compressor rotation point, and adds or reduces gain at the VCA
in response to the output gain control VR]"
The release current sink is formed by amplifier A, 0' and two
sections of monolithic transistor array 03' Compensation for
Vbe of 03S' and for the quiescent change of voltage across Ca
caused by varying the release current through 03e are applied
via R3 , to Ar
Amplifier A9 and diode 0 3 form a precision half-wave rectifier
whose output is a positive voltage equal to the gain reduction
signal. This point may also source a gain reduction indicator
with intrinsic scaling of + 1V -20dB. Since metering is a matter
of preference for the design engineer, no attempt has been
made to include a gain reduction indicator as part of this circuit
discussion.

=

As

Since it is possible for the inputs of both ~ and
to be negative voltages, it is wise to include germanium diodes 0, and O2
to prevent forward conduction of the internal baseto emitter protective diodes in the MAT-04, thus eliminating the possibility of
reverse leakage coupling between the multipliers. The existence of these diodes also prevents application of the MAT-04
as the charging transdiode 03a' since a voltage more negative
than that across Ca will frequently be present at the emitter of
°3S'
Amplifier A'3 outputs the algebraic sum of the various gain control signals for application to the compressor VCA section which
will be described next.
Selection of the internal scale factor at 1V/decade, and inclusion of the -7.SV "math rail" are arbitrary choices made by the
author in order to accommodate the use of the variable integrator, and to skew the control markings on the front panel controls,
ind icated by the enclosed names associated with those variable
resistor potentiometers. Placing the rotation point, as determined by R2, atthe nominal operating line level, e.g., +4dB, etc.,
minimizes the effects of errors caused by the uncompensated
temperature coefficient of the ratio multiplier, and any minor
deviations in log conformity inherent in the detector circuitry or
VCA sections of the compressor.

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NOTES:
ALL VARIABLE RESISTORS ARE TRIMS, EXCEPT PANEL
CONTROLS WHICH ARE INDICATED BY A FUNCTION BOX

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FIGURE 5: VGA, Math Rail Regulator and Line Driver Schematic

THE VCA SECTION
Figure 5 shows the VCA section of the compressor using the
SSM-2014. The device is configured as an "outboard OVCE" in
accordance with the literature supplied with the IC. Amplifiers
A'4' A'5' A'6' and A'7 should be high quality, low noise op amps
such as the SSM-2134. A'4 and A'5 provide the necessary
feedback and output buffers for this particular circuit. Resistive
voltage divider R45/R46 reduces the OVCE control port sensitivity to +1 V/20dB attenuation to match the scale factor of the

11-78 APPLICA [ION NOTES

control circuitry. Variable resistor VRs is adjusted for lowest
distortion products, preferrably at unity gain with a high level
input. VRg is adjusted by applying a low frequency «50Hz) signal
at about 2Vp·p to pin 11, and setting for least low frequency
output at A'5 under a no-input signal or shorted-input condition.
The stability of both these trims will be a welcomed surprise to
the designer used to dealing with log/antilog VCAs.
A "quasi-balanced" line driver, consisting of A'6' A'7' and their
associated passive components, completes the compressor

circuitry. The unit is capable of driving a soon load at a sustained output level of +21dBm, and has a maximum output of
+2SdBm.

the Attack, Release, and Output gain controls centered, the
maximum Ratio setting, fully clockwise, produces an output
level equal to or slightly greater than the rotation point.

The SSM-2014 provides the designer a degree of flexibility in
configuration which is not easily available using other VCA
topologies. Chief among its attributes is the ability to select the
operating bias current by applying currentto a single port on the
chip. This allows the user to select an operating point which is
optimized for best noise performance vs. distortion for a given
application.

When laying out circuitry using the SSM-2014 and SSM-211 0,
care should be taken to keep traces to virtual grounds as short
as possible, and a single point audio ground should be used.
The control ground should connect to the audio ground at one
point, pin 4 of the SSM-2110, and supply traces should be
heavily decoupled with high quality capacitors. Traces carrying
audio signal should be kept well away from control circuitry, and
the detector IC and VCA should be located away from heat
sources such as regulators or power supply transformers.

In considering the normal operation olthe compressor, the most
common scenario is that the unit is used to '1rack" instruments
or vocals. Of secondary, but no less important, concern is use
for compressing mixed program material to enhance apparent
loudness. In both applications, the trade-off between the residual noise floor and distortion at high-signal levels, both a function of operating bias, is somewhat arbitrary. Since it is likely
that the dynamic distortion inherent in the compression process
in normal operation would be at least equally as noticeable as
moderate distortion at high-signal levels, the "intermediate"bias
setting as described in the literature accompanying the device
was chosen. This places the device bias at approximately
300J.IA, with a value of 43kn for R44 • As a result, the noise floor
for the VCA circuit is -84dB (ref. 0.775VRMS ) in a 20 kHz bandwidth at OdB gain. The 1kHz THD+Noise measurements yielded
figures consistent with the published data, and SMPTE IMD
measurements disclosed worst-case distortion products in the
0.2% range, which is acceptable in all but the most critical applications. Should the designer wish to implement the sliding
bias scheme, as described SSM-2014 data sheet, the output of
the absolute value at pin 1 of the SSM-211 0 (see Figure 4), or
the rmscomputing loop (pin 5) may be used to drive a com parator with the appropriate time constants in orderto switch to class
A operation in the presence of high level inputs. In practice, this
makes little difference in the transparency of the compressor in
normal operation. Listening tests of the compressor demonstrated the smooth, precise control expected of the feedforward
circuit topology. As the attack time (integration time) control is
advanced from fast to slow settings, the low frequency content
in mixed material becomes more solid and better defined, but
the tendency to "squash" the lows is relatively absent at faster
attack times as compared to other compressors having adjustable attack times with comparable settings.

Since all parameter control is derived from DC levels produced
by the front panel controls, high quality potentiometers need not
be used. All the front panel control scales may be marked in
equal intervals, and follow the antilog law, i.e., equal spacing
per dB of gain or threshold setting, equal spacing per decade of
attack and release times, etc. The sole exception is the ratio
control, whose scale is skewed so that 2:1 appears near the
middle of the control, as one normally would expect of a traditional feedback compressor.
The compressor control circuit described in this application note
was configured using only four quad op amps in addition to the
SSM-2110 and three matched transistor arrays. By providing
the basic building blocks for an audio dynamic range processor
in monolithic form , the SSM audio chipset greatly simplifies the
implementation of an otherwise complex processor.

MEASURED PERFORMANCE:

The log averaging detector scheme really shines on vocals and
horns, bringing a soloist "up-front" with moderate attack times.
This is a noticeable difference when compared to any RMS-type
compressor used for comparison in the listening tests.

SMPTE IMD @ Unity Gain, OdBv in
0.009%
SMPTE IMD @ Unity Gain, +20dBv in
0.11%
0.06%
SMPTE IMD @ 20dB Gain Reduction, OdBv in
0.025%
SMPTE IMD @ 20dB Gain Reduction, +20dBv in
Residual Noise and Hum @ Unity Gain, 20kHz BW -84dBv
Maximum Output Level into soon, Balanced
+21dBm
+21dBv
Maximum Input Level Before Clipping
Usable Dynamic Range, Unweighted in 20kHz BW
103dB
-40 to +20dB
Threshold Range Ref. Rotation Point
Useful Range of Rotation on Point Adj.
-10to+4dBv
Nominal Attack (Integration) Time Range
0.02 to 200ms
1.3:1 to 20:1
Nominal Range of Ratio Adjustment
Range of Release Time Adjustment
0.05 to 5s/20dB
Range of Output Gain Adjustment
-20 to +20dB

ADJUSTING FOR BEST PERFORMANCE

NOTE: OdBv refers to 0.775 VRMS

As in any compressor or limiter whose ratio must be trimmed in
its initial setup (see Figure 4, VR s)' the unit is sensitive to incorrect adjustment. One of the most distressing sounds which can
be produced by a compressor is "over-compression," in which
the control circuitry causes too much gain reduction at high
ratios. For this reason, the compressor ratio trim should be set
with the Threshold control at OdB (OV at the wiper of VR4 ), and
with an input of +20dB, the trim should be adjusted so that with

APPLICA TION NOTES 11-79

m

11-80 APPLICA nON NOTES

AN·136
APPLICATION NOTE

r'IIIANALOG

WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062·9106 • 6171329-4700

An Ultra Low Noise Preamplifier
by M. Jachowski

Achieving the maximum usable dynamic range from low output
level transducers such as audio microphones, magnetic pickups, or low impedance strain gauges requires a preamplifier
with very low input-referred voltage noise. The circuit shown in
Figure 1 has extremely low noise, O.SnVlv"Hz, and can provide
a gain of 1000 over a 200kHz bandwidth.

at about 8MHz. This compensation ensures the preamplifier's
stability for gains from 100 to over 2000. Gain is set with
resistors Rs and R6 where AVCL = 1 + R/R 6. To limit the thermal
noise contributed by the feedback loop impedance, R6 should
be no more than 10(.1 (a 10(.1 resistor creates about 0.4nV/VHz
at +2S0C).

This amplifier's low noise characteristics are attributable to the
SSM-2220's matched PNP transistor pair. Operating with 2mA
collector current in each transistor, the SSM-2220 forms a
differential input stage with a DC gain of 38S, approximately
SOjiVof offset voltage, and only O.SnV/VHZ of broadband noise.
When multiplied by the stage gain of 38S, the input noise of the
SSM-2220 appears as 192.SnV/VHZ differentially at the inputs
of the OP-27. This makes the 3.8nV/v'HZ of the op amp an
insignifi-cant contribution to the overall noise of the circuit. In
this example, the input stage compensation, C 1 and R7 , optimizes noise performance over the audio frequency range by
allowing the differential pair to have a flat frequency response
to 20kHz before being rolled-off for stability criteria. Input stage
gain is reduced 20dB from 20kHz to 200kHz and then remains
constant until the SSM-2220's gain-bandwidth limit is reached

The input stage current, 4mA, is established by the current
source of 2 , R1 , and a GaAsP LED. The LED is used as a 1.6V
"zener" whose temperature coefficient is nearly identical to that
of 02'S base-emitter junction. This produces a temperature
stable 1V drop across Rl forcing 4mA to flow from 02'S collector.
The 4mA splits to 2mA in each side of the differential pair. With
hIe = 1S0 in the SSM-2220, input bias current will be about 13jiA.
Because the bias current is relatively large, the offset voltage
created as it flows through unbalanced source impedanpes will
quickly surpass the differential pair's offset, making necessary
the offset trim, Rs' Low source impedances will reduce the offset
drift as hIe changes over temperature.

°

A low source impedance is also critical to maintain a low overall
input noise. The O.SnVI v'Hz noise of the SSM-2220 input is
equivalent to the thermal noise of a 1S(.I resistor at +2SoC.

+ISV O-...._ _ _ _ _......_ _ _ _ _...._-l0.Oi~F

I.

LEO

ji

10~F

+~

II

Ion
R5

C2

10kn

33pF

~-+---+_----_oVOUT

R8

con

O.Q1~F

-ISVo-....- - - - - _ - - - - -....--f~.

FIGURE 1: This ultra low noise preamplifier shines new light on high-gain, low noise applications such as microphones,
thermocouples, strain gauges, and magnetic pick-ups.
APPLICATION NOTES 11-81

Therefore, any transducer with a sourcing impedance greater
than 1Sn will produce a noise which dominates that of the
preamplifier. Figure 2 shows the total output noise of the
preamplifier driven through a 10n source impedance. The
analyzer displays total RMS noise voltage measured in a
0.03Hz bandwidth. The average broadband measurement is
roughly 0.13~ V on the vertical scale. Divided by the amplifier's
closed-loop gain of 1000, this corresponds to 0.13nV at the
preamp input, oreXj)ressed in nVI Hz,
e =

0.13nV

=0.7SnV/VHz

n~

Taking into account the noise of two 10n source resistors, the
noise attributable to the SSM-2220 is then,
0.7SnV/v'Hz =-v1e sSM)2 + (0.4nVA/HZ)2 + (0.4nV/..,f"Hz)2
eSSM = 0.49nVA/Hz
The 11f noise corner frequency is also remarkably low, only
about 0.2SHz. In the 20kHz audio bandwidth, the total RMS
input-referred noise voltage contributed by the SSM-2220
differential pair is,
en = (O.SnVI VHz) fv'20kHz - 20Hz) = 70.SnVRMS
The thermal noise of a 10n source impedance in the same
bandwidth is,

v'(1 On) (20kHz -

et = 1.28 x 10-10

20Hz) = S7nVRMS

The total input referred noise of the preamplifier with 10n
source impedances on each input is,
elotal .. -/(70.SnV)2 + (S7nV)2 + (S7nV)2 + 106nVRMS
This is lower than the thermal noise of a single son resistor over
the same bandwidth, 126nVRMS .

11-82 APPLICA TION NOTES

FIGURE 2: The spectrum analyzer shows that, in a gain of 1000
with 100 source imJ}§dances, the SSM-2220 preamplifier has

less than 0.5nV ..fRZ broadband noise and a 11f noise corner
of about 0.25Hz. Total harmonic distortion is less than 0.005%
of a 1OVp-p Signal from 20Hz to 20kHz.

AN·142
APPLICATION NOTE

~ANALOG

WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 6171329-4700

Voltage Adjustment Applications of the DAC-8800 TrimDAC™
An Octal, 8-Bit D/A Converter
by Joe Buxton

The DAC-8800, a monolithicoctal8-bit digital-to-analog converter,
is a digitally-controlled voltage adjustment device. The DAC's
design makes it ideal for replacing trimming potentiometers in
many applications. Not only does it replace potentiometers, but
the DAC has many advantages over them, such as solid state
reliability, very low drift overtemperature and time, elimination of
shifts due to vibrations, and automating the adjustment process.
During manufacture of complex electrical systems, potentiometers must be manually adjusted taking considerable time and
cost for labor, or expensive robotic systems must be developed
forthesame purpose. However, the DAC-8800can automate the
system's voltage adjustments so that a computer can now control
the calibration.
This application note first describes the basic architecture and
operating modes of the DAC-8800, including the reference input
range limits, the load that the DAC places on the references, single
supply operation, and serial interfacing. The last half of this note
shows many basic circuits for using the DAC in a wide variety of
applications, such as two wire interfaces and stand-alone operation for systems not based on digital controllers. Also included

are techniques for adjusting the offset of operational amplifiers;
using two DAC outputs together for coarse and fine control of a
voltage; digitally changing the gain of a voltage-controlled
amplifier; and trimming voltage references.

BASIC ARCHITECTURE
As the functional diagram shows in Figure 1, the DAC-8800 has
eight individual DACs divided into two groups offour, each group
having its own high and low reference inputs. Each DAC's output
is independently controlled by a serial interface through which
the 8-bit data word and 3-bit address are loaded.
Each of the DACs contains an R-2R ladder connected between
the high and low reference inputs as shown in Figure2. The output
voltage is set by the position of the switches according to the
formula below:
VouT(D) = 0 x (VREFH - VREFL)/256 + VREFL
where 0 is the digital code.
As this equation shows, the output can varyfrom VREFL to VREFH
in 256 steps. It is significant that, while the output voltage can
varyoverthis range, the DAC-8800's output impedance isalways
equal to a constant ROUT, the characteristic resistance of the
ladder. ROUT is typically 12kQ but can vary between 8kQ and 16kQ
from device to device. The DAC's accuracy depends not on the
absolute value of the ladder resistors but rather on the relative
resistor matching. Thus, variations in output impedance do not
2R

2R

DAC
REGISTER

_ROUT
CONSTANT
R
INDEPENDENT
OF DIGITAL
INPUT CODE

R

2R

2R
-----"""'foIo-...J

VREFLo----......
·VOUT

= 2~ x [VREFH -

VREFLj + VREFL

FIGURE 2: DAC-8800 R-2R Ladder Network

FIGURE 1: DAC-8800 Block Diagram

TrimDAC is a trademark 01 Analog Devices, Inc.

APPLICA TION NOTES 11-83

m

affect the linearity ofthe DAC. To easily understand the DAC, each
output can be thought of as a Thevenin equivalent circuit of a
voltage source in series with ROUT as in Figure 3, where ROUT is
12kll. The digital code then varies the voltage source between
VREFL and VREFH.

400
350
300

~u.

250

w 200

.$

150
100
50
0

FIGURE 3: Thevenin equivalent of each DAC output. ROUT
is typically 12kQ.
REFERENCE INPUT LIMITS

The switches in the R-2R ladder are N-channel enhancement
MOSFETswith extremely low ON resistan~. To ensure the DAC's
linearity, the MOSFETs' gate-to-source voltage (VGS) needs to be
greater than the switches' intrinsic threshold voltage, which for
the DAC-8800 is 2.5V. When the voltage falls below 2.5V the
MOSFETs' ON resistance increases, which causes resistance
mismatching in the R-2R ladder. Any mismatching degrades the
precise R-2R ratios and thus decreases the linearity of the DAC.
. In the DAC-8800, the gate-to-source voltage is equivalent to the

voltage difference between Voo and VREFH, respectively. Figure 2 shows that VREFH is connected to the drain ofthe MOSFET
switches, and, when the switches are on, the drain voltage is
basically equivalent to the source voltage. The gate voltage is
driven by CMOS logic, and when the switch is on, the logic connects the gate to Voo. Thus, VREFH must be at least 2.5V below
Voo, as shown in Figure 3 ofthe DAC-8800's data sheet. However,
to guarantee the data sheet error specifications over -55°C to
+125°C, the gate-to-source voltage needs to be at least 4V. There
is no similar limitation between the reference input and the
negative supply, Vss. Thus, the reference inputs can go to Vss.
An important note: because of internal protection diodes in the
DAC, VREFL should not be allowed to go higher than VREFH.
Forward biasing these diodes allows large currents to flow between the two references, potentially resulting in permanent
damage to the DAC-8800.

11-84 APPLICA TlON NOTES

0

64

128

192

256

DIGITAL INPUT CODE

FIGURE 4: IREFH variation versus digital code. One of four
DACs connected to VREFH. The other 3 DACs are loaded
with zero code.
REFERENCE INPUT CURRENT CHANGES WITH DIGITAL
CODE

As the digital code changes, the resistance looking into the reference input changes significantly. Figure 4 shows the current
demand into the VREFH pin as a function of the digital code for
one of the four DACs referenced from that pin. This graph was
generated with the following conditions: Voo = +12V, Vss= OV,
VREFH = +5V, and VREFL = OV. As can be seen, the load on the
reference varies from zero to 4001lA. With all four DACs operating, the load current can go up to a maximum of 1.6mA. It is important to keep in mind that the current changes in abrupt steps.
Thus, in applications where speed is important, any device driving
the reference pin must be capable of handling these step current
changes. A fast recovery op amp (such as the OP-42) or reference is recommended.
THE DAC-8800 CANNOT BE USED AS A VARIABLE
RESISTOR

At first glance the DAC-8800 might appear to be ideal for use as
a variable resistor from its output to VREFL, where VREFL is tied
to ground and VREFH left floating. However, its internal structure
was not designed for this. The reason is twofold. First, the resistance from the DAC's output to VREFL does not vary linearly with

the digital code. Rather, it changes erratically, similarto the way
the reference current changes in Figure 4. These seemingly random changes are due to various switches connected to VREFH
turning on in binary fashion rather than sequentially and creating
alternate current paths from the output to VREFl.

10
FULLJALE

0

~
~

1/2 SCALE

iii" -10
:!!.

z

<
C)

-'"

-20

./

1116 SCALE

~

~,

-lIO

'\

-40

10M

100k
10k
1M
FREQUENCY (Hz)

1k

FIGURE 5: DAC-8800 Bandwidth Under Different Gains

0

/

-20

iii"
:!!.

z

-40

0

-60

~
........

-60

~

0

V
/

V
/

-100

/

-120
-140
1

10

100

1k

10k 100k

1M

10M

FREQUENCY (Hz)

FIGURE 6: DAC-8800 OFF Isolation

0

./

-20

iii"

-40

:!!.

~
'"

~

./
/~

.-60
-60

./

-100

V

./

~

V

./~

-120

Second, the NMOS switches are not bi-directional. In this variable resistor configuration, the switches connected to VREFH
would actually have current flowing in reverse direction from the
source to the drain. They maintain their low ON resistance only
when current is flowing normally from the VREFH side (the drain)
towards the output (the source). In backwards operation the
source voltage causes changes in the ON resistance. Thus, any
change of the voltage on the DAC's output will change the ON
resistance and ultimately change the resistance to ground, even
althe same digital code. Obviously, the DAC-8800 was designed
to work as a voltage attenuator, and not as a variable resistor.
AC MULTIPLYING MODE OPERATION
The DAC-8800 is designed primarily as a DC adjustment device.
However, it can also be used in multiplying mode by applying an
AC signalto the reference input. In such applications, bandwidth,
off-isolation, and crosstalk are important to the circuit's performance. The bandwidth of the DAC-8800 is limited by the ladder
resistance and the internal capacitance, which are both specified
in the data sheet. The typical resistance of 12kQ, combined with
the reference capacitance of 75pF,Iimits the bandwidth to 177kHz.
Figure 5 shows actual network analyzer measurements of the
-3dB bandwidth, which for this particular part occurs at 360kHz.
The fact that the measured bandwidth is twice the typical points
out how the bandwidth can vary due to varying capacitance and
resistance from device to device. The worst case bandwidth is
approximately 100kHz based on worst case resistor and capacitor
values of 16kn and 100pF, respectively. Remember, as mentioned in the reference input limits section, VREFH cannot go
below VREFl. Any AC signal into VREFH must be biased to avoid
this condition.
The off isolation of the DAC-8800, shown in Figure 6, was measured using an AC signal for VREFH and measuring an associated DAC output with all the bits off. The off isolation reveals how
much of the input signal will feed through to the output. An interesting correlation can be made between this graph and the
bandwidth graph of Figure 5, for the 1/16 scale measurement.
The 1/16 scale shows a 1OdB rise in the gain above 100kHz. This
is actually due to the capacitive feedthrough of the DAC-8800 .
The crosstalk versus frequency graph in Figure 7 was measured
as the crosstalk from one set of four DACs to the other set of
four DACs in the package. In other words, DACs A through D
were setto full scale, and a frequency dependent signal was injected into their VREFH input. The crosstalk was then measured
on the outputs of DACs E through H. The graph shows DC
crosstalkof-120dB rising upto-50dB at 100kHz, revealing excellent performance for DC and low frequency AC signals.

-140
1

10

100

1k

10k 100k 1M 10M

FREQUENCY (Hz)

FIGURE 7: DAC-8800 Crosstalk

APPLICATION NOTES 11-85

m

+5V
REF-43
TRIM

4

5

Vss=GNO

FIGURE 8: DAG-BBOO Single +5V Operation
OUTPUT NOISE
The DAC-8800 exhibits basic broadband white noise of typically
18nV/VHz.lts dominant noise source is the resistor ladder. Thus,
the noise does not exhibit any measurable 11t noise.
SINGLE +SV SUPPLY OPERAnON OF THE DAC-8800
The DAC-8800 is ideal for single supply applications because its
output range includes ground. In fact, the DAC-8800 can work
well with asingle+SVonly. Even with this lowof a supply voltage,
VREFH can' be connected to a 1.23V bandgap reference (Figure
8). Although the 1.23V bandgap reference violates the 4Vof
headroom requirement, the DAC is still within ±1/2 lSB of total
unadjusted error. The 4V below the positivesupply limit was set
with a safety margin of about O.SV to account for operation over
the full operating temperature range.
The 1.23V b,mdgap reference voltage is derived from the TRIM
pin of a precision 2.5V reference device, the REF-43. The buffer
amplifier is needed because the TRIM pin's impedance is SOkil.
The DAC-8800's reference inputs characteristically range from
12kn to 40kn depending on the digital code, which would load

SERIALOATA

the trim pin excessively. The OP-290's low offset voltage of 7SJ.l V
and low temperature drift characteristics maintain the reference's
accuracy. The OP-290 also has the ability for its output to operate to ground with the addition of a load resistor; 1Oknworks well.
The output amplifier is needed to buffer the DAC-8800's high
output impedance when the output is connected to a low impedance load.
SERIAL INTERFACING
The digital control ofthe DAC-8800 is a standard three-wire serial
interface with clock (ClK), load (ill), and serial data input (SDI)
(Figure 9). Additionally, an inverted ClK input pin is available for
negative edge triggered data loading. Either ClK or ClK can also
be used as a chip select pin. When loading data, 3 address bits
are loaded, MSB first, followed by 8 bits of data, again MSB first.
Thus 11 bits in all are loaded through the SDI pin to control each
DAC. The DAC-8800 can run on a clock as fast as 6.6MHz making
it possible to load all eight DACs in as little as 14 microseconds.
Furthermore, the DAC-8800 maintains TTL compatibility for
positive power supply voltages greater than or equal to +SV.

OAC-BBOO

~~_ _ __

CLOCK~l

8

nL-___

9

II

13

lOAD STROBE

10

l

SOl

ClK

Li5
CLK

VL
CLR
GNO

l
FIGURE 9: DAG-BBOO Serial Interfacing

"-B6 APPLICA TION NOTES

, _ HIGH VOLTAGE
ISOLATION

~I~
f
,
'

.".

r'"
SOl
3·W1RE
INTERFACE
SIGNAL

FIGURE 10: Isolated Two-Wire Serial Interface for the DAC-8800
TWO WIRE INTERFACES FOR PROCESS ENVIRONMENTS
High voltage isolation using opto-couplers is often necessary for
serial interfaces found in process control applications. In these
and other applications where minimizing the numberof data lines
is desirable, two-wire signal interfaces can be used (Figure 10).
This simple circuit translates the two-wire interface into the three
data lines required to load the DAC-8800. The LOAD signal is
generated using two retriggerable one-shots. The firstone-shot's
timeout should be set longer than the clock period. Each succeeding clock pulse will retrigger the one-shot until all11 bits are
loaded into the DAC. Then the clock must pause long enough to
allow the one-shot to time out. When the first one-shot's output

goes low, it triggers the second one'shot, which produces the
LOAD pulse, and finishes the loading cycle.
There are some common pitfalls when using one-shots. For example, the timeout set by the external resistor and capacitor can
vary over temperature and from part to part. Even more significant is the variation due to resistor and capacitor tolerances. A
typical capacitor can vary by ±1 0% which will cause an equivalent ±1 0% variation in the timing of the one-shot. To avoid the
problems of one-shots, a second method using a counter is
recommended (Figure 11 a). The counter keeps track of the
number of clock cycles and, when all the data has been input to
the DAC, the external logic creates the LOAD pulse.

II

6 0
7 ENP
8 GND

LOAD 9

12

DAC·8800

VOUT

FIGURE 11a: Isolated Two-Wire Serial Interface Using a Counter

APPLICA TION NOTES 11-87

ClK
QD-,~

__________________________

Qc __________________

~

~

LJ
FIGURE 11b: Isolated Two-wire Serial Interface Timing Diagram
Referring to the timing diagram (see Figure 11 b), the counter is
incremented on every rising edge of the clock. Additionally, the
data is loaded into the DAC-8800 on the falling edge of the clock
by using the ClK input instead of the ClK input. The reason for
using the ClK input becomes apparent after considering the lOAD
pulse. The timing diagram shows that after the eleventh bit has
been clocked, the output of the counter is binary 1010. On the
following rising ClK edge the output of the counter changes to
binary 1011, upon which NAND gate 'X' goes lowto generate the
lOAD pulse. The lOAD signal is connected to both the DAC's
lD and the counter's LOAD pins. Since the counter has a synchronous clear, the lOAD pulse remains low until the next ClK
pulse. NAND gates 'Y' and 'Z' prevent the twelfth falling ClK edge
(labelled 'lOAD' in the timing diagram) from clocking the DAC,
which would load false data into the DAC. Using the ClK input
allows sufficient time from the ClK edge to the lOAD edge, and
from the lOAD edge to the next ClK pulse, to satisfy the timing
requirements for loading the DAC-8800.
After loading one address of the DAC, the entire process can be
repeated to load another address. Ifthe loading is complete then
the ClK must stop after the twelfth pulse of the final load. The
ClK input will be pulled high and the counter reset to zero. The
timing requirements of the system are the same as for the DAC
alone, and can be found in the DAC-8800's data sheet. Another
feature of this circuit is the Rand C on the ClR pins of both the
DAC and the counter. This simple RCtiming circu~ will clear both
chips upon system power-up. The 74lS 161 was chosen because,
like the DAC-8800, it has an asynchronous clear. The RC time
constant should be set longer than the power supply turn-on time.
The values shown inthe circuit give a timeconstantof 1Oms, which
should be adequate for most systems. This same two-wire interface can be used for most three-input serial DACs.

11-88 APPLICA TION NOTES

STAND-ALONE OPERATION PROVIDING NONVOLATILE
SETTINGS
Whenever a system with a DAC-8800 is powered on, the DAC8800 needs to have all eight of its data words loaded to set the
proper DC output voltages. In a system with a microprocessor or
microcontroller, this is a straightforward operation. However, in
some systems the DAC-8800 may be the only part with a digital
interface. In this case, the circuit shown in Figure 12a will automatically load the DACon system power-up. The core olthe circu~
is a serial input/output EEPROM device (U2), preprogrammed
with the appropriate data for the DAC. The cou nter labelled U4
counts through 8 addresses, which are serially shHted into the
EEPROM by U3, a parallel to serial shift register. The EEPROM
shifts out a 16-bit word associated w~h each address. Only 11 of
the 16 bits are actually shifted into the DAC before the lOAD pulse
arrives.
The second counter, U7 , in combination with the flip-flop U6, counts
the loading of the bits into the EEPROM and into the DAC-8800.
When all the bits are loaded the logic sends a lOAD pulse which
loads the DAC and increments the address on U4 • The timing
diagram in Figure 12b gives a detailed description of the loading
of one address. The ClK INH logic inhibits the shift register during certain ClK pulses because 9 bits need to be loaded into the
EEPROM and only 8 bits are available in the register.
When the system is powered-up, R1 and C 1 create a PWRUP
pulse to asynchronously clear all of the counters and the DAC.
After the PWRUP pulse goes high, the free running clock begins
to load all 8 addresses. After the eighth address is loaded, the
clock is disabled to remove any digital switching noise in the analog circu~ry.

+5V

,

OA
Oc
OE
74lS04 x4

74LSOOx 3

~

OA~OA

SH!lo

3

OE

OB~Oe

11<.0

-----7

9l;

p::.-<....

9c

Oc~Oc

OE

Oo~Oii

lkn

LO.M>
00

OA

U.
74LS73A
lJ
lK

00

+5V

U7
74LS161

CLK

l00kn

=:::12:ru.~~l--...!-I>lCLK

+5V

Oc

U'O

ClK INH

,,1.::.4__::.3- 1000

51 IS CLOSED TO TEST 18+
52: IS CLOSED TO TEST IBBOTH CLOSED TO TEST Vas
BOTH OPEN TO TEST los

Vo

=(1+~) IVosl
+(l+~)(lB+RSI
-(1+~) 1I._Rsl

Figure 5. Bias/Offset Current Test Circuit
Open Loop Voltage Gain
Another op amp parameter which distinguishes a real
amplifier from an ideal amplifier is open-loop gain. In the
ideal op amp model, open loop gain is assumed to be infinite. The same assumption is also sometimes made when
dealing with real amplifiers.

Open-loop gain of an operational amplifier is an interesting parameter to attempt to measure. It is generally not
practical to measure open loop gain directly by applying
a signal at the input and observing the output change.
However, by using the device under test inside a feedback
loop, it is possible to measure the change in input voltage
required to produce a known change in outputvoltage.

Vc = -1DV TO +10V

EO

6EO = (1

Figure 6. Open Loop Gain Test Circuit
In this circuit, the control voltage, V c, is varied from -1 OV
to + 10V,causingthe D.U.T. output, V o , to vary from + 10V
to -10V. The D.U.T. output is varied by a change in V 1N
produced by the second amplifier. Since V 1N is attenuated
from Eo by the RF/1 oon voltage divider, Eo is easily measured, and open-loop gain can readily be computed.
Common-Mode Rejection Ratio

The ideal operational amplifier is a pure differential
amplifier and is insensitive to the absolute voltage on the
inputs with respect to ground. The real amplifier has several nonideal characteristics associated with input levels.
First, of course, is the allowable range of input voltage.
Most IC op amps will only operate when the voltage on
the inputterminal is within the range bounded by the supply voltages. The second, and perhaps more subtle, characteristic is the common-mode rejection ratio (CMRR).
CMRR is defined as the ratio of the change in common
mode to the resulting change in input offset voltage. It is
often convenientto specify this parameter logarithmically
in dB: CMR = 20 log (CMRR).
Common-mode rejection can be measured several ways.
One method uses four precision resistors to configure the
op amp as a subtractor amplifier. The disadvantage inherent in this circuit is that the ratio match of the resistors
also determines the subtractor's CMRR. A mismatch of
0.1% between resistor pairs will result in a CMR of only
60dB. Since most amplifiers exhibit CMR in excess of
SOdS (some as high as 120dSl. it is clear that this circuit
is only marginally useful.

+,:on

)LlVos

Figure 8. Common-Mode Rejection Test Circuit
Frequency Response
Open-loop gain versus frequency is another difficult-totest specification. Bandwidth is usually specified in terms
of gain-bandwidth product or unity-gain small signal
bandwidth. It is assumed that the amplifier undertest has
an open-loop gain versus frequency plot which decreases
with a - 20dB/decade slope. It is therefore possible to
measure the open-loop gain at some known frequency
and predict the frequency at which the open-loop gain will
be unity.

In the circuit shown, the D.U.T. dc output is held to OV by
Vc and the integrator amplifier. A low amplitude 10kHz ac
input signal is applied to the D.U.T. Since the integrator
has very low gain at 10kHz, the D.U.T. is effectively running open-loop for the ac signal. The ac output from the
D.U.T. can be measured and the gain at 10kHz can becomputed. For example, a 741-type amplifier has an open loop
gain of approximately 100 at 10kHz. Thus, an easily generated 100mV input at the D.U.T. input will produce an easily measured 10V output. This corresponds to a 1MHz
gain-bandwidth product.
Vc =ov

Va

R,

GBW= GI'OkHz X 10kHz
=

~

X 10kHz

R2

Figure 9. Gain-Bandwidth Product Test Circuit
V,N

+

VOUT'(1+l*)(~)

~RESISTORS MUST MATCH WITHIN lppm (O.OOO1%)
IN ORDER TO MEASURE CMR> l00dB

Figure 7. Simple CMR Test Circuit
A better circuit uses the same technique used for measuring offset voltage with one exception. Rather than applying a fixed zero volt input to the D.U.T. operating on ± 15V
supplies, the same input is applied to the D.U.T. with
asymmetrical power supplies, such as +5V and -25V.
The output of the amplifier is forced to remain centered
between the supplies and the input voltage to the D.U.T.
which forces this to occur is measured.
The change in Vos can be readily translated into CMR. If
this 10V change in CMV creates a 1mV change in Vos, the
CMRR is 10,000 and the CMR is SOdB.

In general, slew rate, settling time and noise measurements are performed on specialized test fixtures and the
parametric data is observed on an oscilloscope. Slew rate
can be measured in either the unity gain inverter or unity
gain follower circuits. Typically it's measured in the unity
gain follower circuit since this is usually the worst case
condition due to the amplifier's common-mode swing
limitation.

100pF

Figure 10. Slew Rate Test Circuit
APPLICA TION NOTES 11-99

II

The amplifier is driven by a high-frequency square wave
of sufficient magnitude in both directions in order to remove any rounded peaks from the measurement interval
as these portions are not slew rate limited. The slew rate
is found as the slope of the transition between the rated
output extremes. Frequently the positive and negative
swings will have different slew rates, and both have to be
monitored.

To effectively measure settling time, the test fixture
should be constructed with relatively low impedance
levels, minimum stray capacitance and no load capacitance. A full scale step input is used to determine settling
time and the step is usually unipolar. The settling time indicated is generally the longest time resulting from a step
of either polarity and is given as a percentage of the full
scale step transition.

;.:-:;.==::....:==__
4.991<

OV

~~~I~ERTICAl
VERROR

=

VIN; VOUT

4.991<

-9V

VOUT

-10V

NEGATIVE SLEW

POSmVESLEW
RATE
.lVo(+1

SRI + I ==

RATE

""lTI'+T

SR(-l '"

.l1f!f~l

Figure ". Slew Rate Test Output Waveform

Settling time is defined as the time elapsed from the application of a perfect step input to the time when the
amplifier output has entered and remained within a
specified error band symmetrical about the final value as
shown in the following figure. Settling time, therefore,includes the time required for the amplifier to slew from the
initial value, recover from slew rate limited overload, and
settle to a given error in the linear range.

Figure 13. Settling Time Test Circuit

Low frequency noise is difficult to measure, since very
long observation intervals are needed. In some cases, low
frequency noise is measured by direct observation on a
storage-type oscilloscope screen using very slow sweep
periods.

-

RECOVERY LINEAR SETTLING
SErnlNG TIME TO ::t ')'E
OR::t

~

-I

x 100%

Figure 12. Typical Amplifier Settling Characteristic

11-100 APPLICATION NOTES

Figure 14. Noise Test Circuit

AN·202
APPLICATION NOTE

~ANALOG

WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 6171329-4700

An I.C. Amplifier Users' Guide
To Decoupling, Grounding,
and Making Things
Go Right For a Change
by Paul Brokaw
"There once was a breathy baboon
Who always breathed down a bassoon,
For he said "It appears
that in billions of years
I shall certainly hit on a tune"
(Sir Arthur Eddington)
This quotation seemed a proper note with which to begin
on a subject which has made monkeys of most of us at one
time or another. The struggle to find a suitable configuration for system power, ground, and signal returns too frequently degenerates into a frustrating glitch hunt. While a
strictly experimental approach can be used to solve simple
problems, a little forethought can often prevent serious
problems and provide a plan of attack if some judicious
tinkering is later required.
The subject is so fragmented that a completely general
treatment is too difficult for me to tackle. Therefore, I'd
like to state one general principle and then look a bit more
narrowly at the subject of decoupling and grounding as it
relates to integrated circuit amplifiers .

concerned. Although the configuration of a system may
pose formidable problems of decoupling and signal returns,
some basic methods to handle many of these problems can
be developed from a look at op-amps.
OP AMPS HAVE FOUR TERMINALS

A casual look through almost any operational amplifier text
might leave the reader with the impression that an ideal
op-amp has three terminals: a pair of differential inputs and
an output as shown in Figure 1. A quick review of fundamentals, however, shows that this can't be the case. If the
amplifier has an output voltage it must be measured with
respect to some point ... a point to which the amplifier has
a reference. Since the ideal op-amp has infinite common
mode rejection, the inputs are ruled out as that reference so
that there must be a fOlJrth amplifier terminal. Another
way of looking at it is that if the amplifier is to supply output current to a load, that current must get into the amplifier somewhere. Ideally, no input current flows, so again
the conclusion is that a fourth terminal is required.

. . . Principle: Think-where the currents will flow.
I suppose this seems pretty obvious, but all of us tend to
think of the currents we're interested in as flowing "out" of
some place and "through" some other place but often neglect to worry how the current will find its way back to its
source. One tends to act as if all "ground" or "supply voltage" points are equivalent and neglect (for as long as·possible) the fact that they are parts of a network of conductors
through which currents flow and develop finite voltages.
In order to do some advance planning it's important to
consider where the currents originate and to where they
will return and to determine the effects of the resulting
voltage drops. This in turn requires some minimum amount
of understanding of what goes on inside the circuits being
decoupled and grounded. This information may be lacking
or difficult to interpret when integrated circuits are part of
the design_
Operational amplifiers are one of the most widely used linear I.e:s, and fortunately most of them fall into a few
classes, so far as the problems of power and grounding are

Figure 1. Conventional "Three Terminal" Op Amp

A common practice is to say, or indicate in a diagram, that
this fourth terminal is "ground." Well, without getting into
a discussion of what "ground" may be we can observe that
most integrated circuit op-amps (and a lot of the modular
ones as weill don't have a "ground" terminal. With these
circuits the fourth terminal is one or both of the power
supply terminals. There's a temptation here to lump together both supply voltages with the ubiquitous ground.
And, to the extent that the supply lines really do present a
low impedance at all frequencies within the amplifier bandWidth, this is probably reasonable. When the impedance
requirement isn't satisfied, however, the door is left open to
a variety of problems including noise, poor transient
response, and oscillation.
APPLICATION NOTES 11-101

II

DIFFERENTIAL TO SINGLE-ENDED CONVERSiON:

One fundamental requirement of a simple op-amp is that an
applied signal which is fully differential at the input must
be converted to a single-ended output. Single ended, that is,
with respect to the often neglected fourth terminal. To see
how this can lead to difficulties, take a look at Figure 2.
v.

-IN

"N

--+-+---'

Figure 2. Simplified "Real" Op Amp

The signal flow illustrated by Figure 2 is used in several
popular integrated circuit families. Details vary, but, the
basic signal path is the same as the 101, 741, 748, 777,
4136, 503,515, and other integrated circuit amplifiers. The
circuit first transforms a differential input voltage into a
differential current. This input stage function is represented
by. PNP transistors in Figure 2. The current is then con·
verted from differential to single-ended form by a current
mirror which is connected to the negative supply rail. The
output from the current mirror drives a voltage amplifier
and power output stage which is connected as an integrator.
The integrator controls the open-loop frequency response,
and its capacitor may be added externally, as in the 101, or
may be self-contained, as in the 741. Most descriptions of
this simplified model don't emphasize that the integrator
has, of course, a differential input. It's biased positive by a
couple of base emitter voltages, but, the non-inverting
integrator input is referred to the negative supply.
It should be apparent that most of the voltage difference
between the amplifier output and the negative supply
appears across the compensation capacitor. If the negative
supply voltage is changed abruptly the integrator ampl ifier
will force the output to follow the change. When the entire
amplifier is in a closed loop configuration the resulting
error signal at its input will tend to restore the output, but,
the recovery will be limited by the slew rate of the amplifier. As a result, an amplifier of this type may have outstanding low frequency power supply rejection, but, the
negative supply rejection is fundamentally limited at high
frequencies. Since it is the feedback signal to the input that
causes the output to be restored, the negative supply rejection will approach zero for signals at frequencies above the
closed loop bandwidth. This means that high-speed, high·
level circuits can "talk to" low-level circuits through the
common impedance of the negative supply line.
Note that the problem with these amplifiers is associated
with the negative supply terminal. Positive supply rejection
may also deteriorate with increasing frequency, but, the
effect is less severe. Typically, small trans.ients on the posi-

11-102 APPLICATION NOTES

tive supply have only a minor effect on the signal output.
The difference between these sensitivities can result in an
apparent asymmetry in the amplifier transient response. If
the amplifier is driven to produce a positive voltage swing
across its rated load it will draw a current pulse from the
positive supply. The pulse may result in a supply voltage
transient, but, the positive supply rejection will minimize
the effelrt on the amplifier output signal. In the opposite
case, a negative output signal will extract a current from the
negative supply. If this pulse results in a "glitch" on the
bus, the poor negative supply rejection will result in a
similar "glitch" at the amplifier output. While a positive
pulse test may give the amplifier transient response, a negative pulse test may actually give you a pretty good look at
your negative supply line transient response, instead of the
amplifier response I
Remember that the impulse response of the power supply
itself is not what is lik.~!y to appear at the amplifier. Thirty
or forty centimeters of wire can act like a high Q inductor
to add a high-frequency component to the normally over·
damped supply response. A decoupling capacitor near the
amplifier won't always cure the problem either, since the
supply must be decoupled to somewhere. If the decoupled
current flows through a long path, it can still produce an
. undesirable glitch.
Figure 3 illustrates three possible configurations for negative supply decoupling. In 3a the dotted line shows the
negative signal current path through the decoupling and
along the ground line. If the load "ground" and decoupled
"ground" actually join at the power supply the "glitch" on
the ground lines is similar to the "glitch" on the negative
supply bus. Depending upon how the feedback and signal
sources are "grounded" the effective disturbance caused by
the decoupling capacitor may be larger than the disturbance
which it was intended to prevent. Figure 3b shows how the
decoupling capacitor can be used to minimize disturbance
of V- and ground busses. The high·frequency component
of the load current is confined to a loop which doesn't
include any part of the ground path. If the capacitor is of
sufficient size and quality, it will minimize the glitch on the
negative supply without disturbing input or output signal
paths. When the load situation is more complex, as in 3c, a
little more thought is required. If the amplifier is driving a
load that goes to a virtual ground, the actual load current
does not return to ground. Rather, it must be supplied by
the amplifier creating the virtual ground as shown in the
figure. In this case, decoupling the negative supply of the
first amplifier to the positive supply of the second amplifier
closes the fast signal current loop without disturbing
ground or signal paths. O{ course, it's still important ·to
provide a low impedance path from "ground" to V- for
the second amplifier to avoid disturbing the input
reference.
The key to understanding decoupling circuits is to note
where the actual load and signal currents will flow. The key
to optimizing the circuit is to bypass these currents around
ground and other signal paths. Note, that as in figure 3a,
"single point grounding" may be an oversimplified solution
to a complex problem.

LOAD GRDUNO

L ____ ' ,
SIGNAL CURRENT LOOP
POWER
GROUND

Figure 3a.

",:)

v-

POWER
SUPPLY
TERMINAL

r--------------- J

Decoupling for Negative Supply Ineffective

v-

Figure 3b. Decoupling Negative Supply Optimized for
"Grounded" Load

Figure 4. Damping Parallel Decoupling Resonances

FREQUENCY STABILITY
There's a temptation to forget about decoupling the negative supply when the system is intended to handle only
low-frequency signals. Granted that decoupling may not be
required to handle low-frequency signals, but it may still be
required for frequency stability of the op-amps.

Figure 5 is a more-detailed version of Figure 2 showing the
output stage of the I.C. separated from the integrator (since
this is the usual arrangement) and showing the negative
power supply and wiring impedance lumped together as a
single constant. The amplifier is connected as a unity gain
follower. This makes a closed-loop path from the amplifier
output through the differential input to the integrator input. There is a second feedback path from the collector of
the output PNP transistor back to the other integrator input. The net input to the integrator is the difference of the
signals through these two paths. At low frequencies this is a
net, negative feedback. The high-frequency feedback depends upon both the load reactance and the reactance of
the V- supply.
v.------~~------------------~----

+ ------1----1----'

Figure 3c. Decoupling Negative Supply Optimized for
"Virtual Ground" Load

Figure 3b and 3c have been simplified for illustrative purposes. When an entire circuit is considered conflicts fre·
quently arise. For example, several amplifiers may be
powered from the same supply, and an individual decou·
piing capacitor is required for each. In a gross sense the
decoupling capacitors are all paralleled. In fact, however,
the inductance of the interconnecting power and ground
lines convert this harmless·looking arrangement into a com·
plex L-C network that often rings like the "Avon Lady". In
circuits handling fast signal wavefronts, decoupling net·
works paralleled by more than a few centimeters of wire
generally mean trouble. Figure 4 shows how small resistors
can be added to lower the Q of the undesired resonant
circuits. The resistors can generally be tolerated since they
convert a bad high-frequency jingle to a small damped signal at the op amp supply terminal. The residual has larger
low frequency components, but, these can be handled by
the op-amp supply rejection.

v-

Figure 5. Instability Can Result from Neglecting
Decoupling

When the supply lead reactance is inductive, it tends to
destabilize the integrator. This situation is aggravated by a
capacitive load on the amplifier. Although it's difficult to
predict under exactly what circumstances the circuit will
become unstable, it's generally wise to decouple the negative supply if there is any substantial lead inductance in the
V- lead or in the common return to the load and amplifier
input signal source. If the decoupling is to be effective, of
course, it must be with respect to the actual signal returns,
rather than to some vague "ground" connection.
POSITIVE SUPPLY DECOUPLING
Up to this point we haven't considered decoupling the positive supply line, and with amplifiers typified by Figures 2

APPLICATION NOTES 11-103

m

and 5 there may be no 'need to. On the other hand, there
are a number of integrated circuit amplifiers which refer the
compensating integrator to the positive supply. Among
these are the 108, 504, and 510 families. When these cir·
cuits are used, it's the positive supply which requires most
attention. The considerations and techniques described for
the class of circuits shown in Figure 2 apply equally to this
second class, but, should be applied to the positive supply
rather than the negative.
FEED-FORWARD
A technique which is most frequently used to improve
bandwidth is called feed-forward. Generally, feed-forward is
used to bypass an amplifier or level translator stage which
has poor high frequency response. Figure 6 illustrates how
this may be done. Each of the amplifiers shown is really a
subcircuit, usually a single stage, in the overall amplifier. In
the illustration, the input stage converts the differential input to a single-ended signal. The signal drives an intermediate stage (which in practice often includes level translator
circuitry) which has low-frequency gain, but, limited bandwidth. The output of this stage drives an integrator-amplifier and output stage. The overall compensation capacitor
feeds back to the input of the second stage and includes it
in the integrator loop. The compromises necessary to obtain gain and level translation in the intermediate stage
often limit its bandwidth and slow Clown the available integrator response. A feed-forward capacitor permits highfrequency signals to bypass this stage. As a result, the overall amplifier combines the low-frequency gain available
from 3 stages with the improved frequency response available from a 2-stage amplifier. The feed-forward capacitor
also feeds back to the non-inverting input of the intermediate stage. Note that the second stage is not an integrator, as
it may appear at first glance, but actually has a positive
feedback connection. Fed-forward amplifiers must be carefully designed to avoid internal oscillations resulting from
this connection. Improper decoupling can upset this plan
and permit this loop to oscillate.
COMPENSATING
CAPACITOR

FEEDFORWARD

CAPACITOR
INPUT
SECTION

Figure 6. Fast Fed-Forward Amplifier

Note that the internal input stages are shown as being
referred to separated reference points, Ideally, these will
be the same reference so far as signals are concerned,
although they may differ in bias level. In practice this
may not be the case. Examples of fed-forward amplifiers
are the AD518 and the AD707. In these amplifiers, signal
Reference 1 is the positive supply, while signal Reference 2 is the negative supply, Signals appearing be11-104 APPLICATION NOTES

tween the positive and negative supply terminals are
effectively inserted inside the integrator loopl
Obviously, while feed-forward is a valuable tool for the
high-speed amplifier designer, it poses special problems in
application. A thoughtful approach to decoupling is required to maximize bandwidth and minimize noise, error,
and the likelihood of oscillation.
Some fed-forward amplifiers have other arrangements,
which include the "ground" terminal in inverting only amplifiers. Almost without exception, however, signals between some combination of the supply terminals get "inside" the amplifier. It is vital to proper operation that the
involved supply terminals present a common low impedance at high frequencies. Many high-speed modular amplifiers include appropriate capacitive decoupling within the
amplifier, but, with I.C. op amps this is impossible. The
user must take care to provide a cleanly decoupled supply
for fed-forward amplifiers. Figure 7 shows a decoupling
method which may be applied to the AD518 as well as to
other fast fed-forward amplifiers such as the 118. One capacitor is used to provide a low-impedance path between
the supply terminals at high frequencies. The resistor in the
V+ lead insures that noise on the supply lines will be rejected and prevents the establishment of resonances with
other decoupling circuits. The second capacitor decouples
the low side of the integrator to the load.

v- SUPPLY

Figure 7. Decoupling for a Fed-Forward Amplifier

Alternatives include a resistor in both supply leads and/or
decoupling from V+ to the load. In principle, the positive
and negative supply should be tied in a "tight knot" with
the signal return. To the extent that this cannot be done.
there is a slight advantage to favoring the negative supply
due to the high frequency limitations of PNP transistors
used in junction-isolated I.C.'s.
OTHER COMPENSATION
While most integrated circuit amplifiers use one of the three
compensation schemes already described, a significant fraction use some other plan. The 725 type amplifiers combine
a V- referred integrator with a network which the manufacturers recommend to be connected from signal ground
to the integrator input. This makes the circuit extremely
liable to pick up noise between V- and ground. In many
circumstances it may be wiser to connect the external com·
pensation to the negative supply, rather than to signal
ground.
One more class of amplifiers is typified by the Analog Devices AD507 and AD509. In these circuits, a single capaci-

tor may be used to induce a dominant pole of response
without resorting to an integrator connection. The highfrequency response of the amplifier will appear with respect
to the "ground" end of the compensation capacitor. In
these amplifiers a small internal capacitance is connected
between V+ and the compensation point. Unity gain com·
pensation can be added in parallel and the pin-out is arranged to make this simple. The free end of the compensation capacitor can also be connected either to V-or signal
common. It is extremely important that the signal common
and the compensation connect directly or through a lowimpedance decoupling.
Although the main signal path of these amplifiers can be
compensated in a variety of ways, some care is required to
insure the stability of internal structures. It's always wise to
use extra care in decoupling wideband amplifiers to avoid
problems with the output stage and other subcircuits which
are similar to the main integrator problem illustrated by
Figure S. An effective compensation and decoupling circuit
for the ADS09 is shown in Figure 8. This arrangement is
similar to Figure 7, and one of these two circuits is likely to
be suitable for many types of wideband amplifier. Depending upon the power distribution, a small (lon to SOn)
resistor may be appropriate in both of the supply leads to
reduce power lead resonance and interference both to and
from circuits sharing the power supply.

represented by the load resistor. The load current comes
from the power supply and is controlled by the amplifier as
it amplifies the input Signal. This current must return to the
supply by some path; suppose that points A and Bare
alternative power supply "ground" connections. Assuming
that the figure represents the proper topology or ordering
of connections along the "ground" bus, connecting the supply at A will cause the load current to share a segment of
wire with the input signal connection. Fifteen centimeters
of number 22 wire in this path will present about 8 milliohms of resistance to the load current. With a 2k load, a
lO-volt output signal will result in about 40 microvolts between the points marked "t1 V." This signal acts in series
with the non-inverting input and can result in significant
errors. For example, the typical gain of an ADS10 amplifier
is 8 million so that only 1%/lV of input signal is required
to produce a 10 volt output. The 40/lV ground error signal
will result in a 32 times increase in the circuit gain error!
This degradation could easily be the most serious error in a
high-gain preciSion application. Moreover, the error represents positive feedback so that the circuit will latch up or
oscillate for large closed-loop gains with Rf/Ri greater than
about 2S0k.

OUTPUT SIGNAL

V+

OUTPUT

I

SIGNAL
COMMON

V-

Figure 8. Decoupling a Wideband Amplifier
GROUNDING ERRORS

Ground in most electronic equipment is not an actual connection to earth ground, but a common connection to
which signals and power are referred. It is frequently immaterial to the function of the equipment whether or not the
point actually connects to earth ground. I myself prefer
some distinguishing name or names for these common
points to emphasize that they must be made common. The
term "ground" too often seems to be associated with a sort
of cure-all concept, like snake oil, money or motherhood. If
you're one of those who regards ground with the same sort
of irrational reverence that you hold for your mother, remember that while you can always trust your mother, you
should never trust your "ground." Examine and think
about it.
It's important to have a look at the currents which flow in
the ground circuit. Allowing these currents to share a path
with a low-level signal may result in trouble. Figure 9 illustrates how careless grounding can degrade the performance
of a simple amplifier. The amplifier drives a load which is

Figure 9. Proper Choice of Power Connections Minimizes
Problems

Reconnecting the power supply to point B will correct the
problem by eliminating the common impedance feedback
connection. In a real system, the problem may be more
complex. The input signal source, which is represented as
fioating in Figure 9, may also produce a current which must
return to the power supply. With the supply at point B, any
current which flows in additional loads lother than Ri) may
interfere with the operation of the amplifier shown. Figure
10 illustrates how amplifiers can be cascaded and still drive
auxiliary loads without common impedance coupling. The

II
Figure 10. Minimizing Common Impedance Coupling

output currents flow through the auxiliary loads and back
to the power supply through power common. The currents
in the input and feedback resistors are supplied from
APPLICATION NOTES 11-105

the power supply by way of the amplifiers as previously
illustrated in Figure 3c. The only current flowing in signal
common is the amplifier's input current, and its effect
is generally negligibly small.
Having given an example of a simple "grounding error" and
its solution, I will now get back on my soap box and say
that grounding errors result from neglect based on the as·
sumption that a ground, is a ground, is a ground. Some
impedance will be present in any interconnection path, and
its effect should be considered in the overall design of a
system. Ouantitative approaches are quite useful in special·
ized applications: In fast TTL and Eel logic circuitry the
characteristic impedance of interconnections is controlled
so that proper terminations can reduce problems. In RF
circuitry the unavoidable impedances are taken into account and incorporated into the design of the circuit. With
op-amp circuitry, however, impedance levels do not lend
themselves to transmission line theory, and the power and
ground impedances are difficult to control or analyze. The
most expedient procedure, short of difficult and restrictive
quantitative analysis, seems to be to arrange the unavoid·
able impedances so as to minimize their effects and arrange
the circuitry to overcome the effects. Figures 9 and 10
illustrate the sort of simple considerations which can substantially reduce practical ground problems. Figure 11 iIIus·
trates how circuitry can be used to reduce the effect of
ground problems wh ich can't be corrected by topological
tricks.

SIGNAL

OUT

"GROUND NOise"

OUTPUT SIGNAL
COMMON

Figure ". Sub tractor Amplifier Rejects Common Mode
Noise

GETTING AROUND THE PROBLEM
In Figure 11 a subtractor circuit is used to amplify a normal
mode input signal and reject a ground noise signal which is
common to both sides of the input signal. This scheme uses
the common·mode rejection of the amplifier to reduce the
noise component while amplifying the desired signal. An
important aspect of this arrangement, which is often overlooked, is that the amplifier should be powered with respect to the output signal common. If its power pins are
exposed to the high-frequency noise of the input common,
the compensation capacitor will direct the noise right to the
output and defeat the purpose of the subtractor. It's just
this kind of effect which makes it important to use care in
grounding and decoupling. A subtractor or dynamic bridge,
like Figure 11, will be ineffective in correcting a grounding
problem if the amplifier itself is carelessly decoupled. In
general, an op-amp should be decoupled to the point which
is the reference for measuring or using its output signal. In
"single-ended" systems it should also be decoupled to the
11-106 APPLICATION NOTES

input signal return as well. When it is impossible to satisfy
both these requirements at once, there's a high probability
of either a noise or oscillation problem or both. Frequently
the difficulty can be resolved with a subtractor, like Figure
11, where a network like the single-ended feedback network (which needn't be all resistive) joins the input and
output signal reference points and provides a "clean" reference point for the non-inverting input of the amplifier.
A problem with the subtractor is that it uses a balanced
bridge to reject the common mode signal between the input
and output reference points. The arms of the network must
be carefully balanced, since to the extent they don't match,
the unwanted signal will be amplified. Although even a
poorly matched network will probably eliminate oscillation
problems, noise rejection will suffer in direct proportion to
any mismatches. An easier way to reject large "ground
noise" signals is to use a true instrumentation amplifier.
INSTRUMENTATION AMPLIFIERS
A true instrumentation amplifier has a very visible "fourth
terminal." The output signal is developed with respect to a
well defined reference point which is usually a "free" terminal that may be tied to the output signal common_ The
instrumentation amplifier also differs from an op amp in
that the gain is fixed and well defined, but there is no
feedback network coupling input and output circuits. Figure 12 shows how an instrumentation amplifier can be used
to translate a signal from one "ground reference" to another. The normal mode input signal is developed with respect to one reference point which may be common to its
generating circuits. The signal is to be used by a system
which has an interfering signal between its own common
and the signal source. The instrumentation amplifier has a
high impedance differential input to which the desired signal is applied. Its high common mode rejection eliminates
the unwanted signal and translates the desired signal to the
output reference point. Unlike the dynamic bridge circuit,
the gain and common mode rejection don't depend on a
network connecting the input and output circuits. The gain
is set, in Figure 12, by the ratio of a pair of resistors which
are connected inside the amplifier. The amplifier has a very
high input impedance, so that gain and common mode rejection are not greatly affected by variations or unbalance
in source impedance.
RS

NORMAL
MODE
SIGNAL

OUTPUT

COMMON

MODE
SIGNAL

Figure 12. Applying an In-Amp

Since instrumentation amplifiers have a reference or
"ground" terminal, they have the potential to be free of the
power supply sensitivities of op amps. In practice, however,
most instrumentation amplifiers have internal frequency

compensation which is referred to the power supply. In the
case of the AD521, the compensation integrator is referred
to the negative supply terminal. The decoupling of this ter·
minal is particularly important, and it should be decoupled
with respect to the output reference terminal, or actually to
the point to which this terminal refers. The AD520 instrumentation amplifier, on the other hand, has an internal
integrator which is referred to the positive supply terminal.
For best results both the V+ and V- terminals should be
decoupled to the output reference point.
THE "OTHER" INPUT
Most I.C. op-amps and in-amps include offset voltage
nulling terminals. These terminals generally have a small
voltage on them and by loading the terminals with a potentiometer the amplifier offset voltage can be adjusted. While
their impedance level is much lower than the normal input,
the null terminals can act as another differential input to
the amplifier. Although the null terminals aren't generally
looked at as inputs, most amplifiers are quite sensitive to
signals applied here. For example, in 741 family amplifiers
the output voltage gain from the null terminals is greater
than the gain from the normal input!

An illustration of the type of problems that can arise with
the "other" input is shown in Figure 13. The figure is an
op-amp circuit with some of the offset null detail shown.

-

case voltages developed along the "clothesline" will result
in a difference voltage at the Vas terminals. For instance,
suppose that a 10k null pot balances out the op amp offset
when it is set with 3k and 7k branches as shown in the
figure. In a 741 the internal resistors are about 1k so that
the difference signal at the Vas terminals will be about 1/8
Il V. The gain from these terminals is about twice the gain
from the normal input, so that the disturbance acts as if it
were an input signal of about 1/4 IlV. Using the same assumptions as in the discussion of Figure 9. the current 10 will result in a 10 microvolt input error signal. In this case,
however, the error will appear only when the amplifier load
current comes from the negative supply. When the load is
driven positive the error will disappear. As a result, the Vas
input signal will result in distortion rather than a simple
gain error!
An additional problem is created by If, a current returning
to the power supply from other circuits. The current from
other circuits is not generally related to the op amp signal,
and the voltage developed by it will manifest itself as noise.
This signal at the null terminals can easily be the dominant
noise in the system. A few milliamps of V- current through
a few centimeters of wire can result in interference which is
orders of magnitude larger than the inherent input noise of
the amplifier. The remedy is to make the connection from
the null pot wiper direct to the V- pin of the amplifier, as
shown in Figure 14. Some amplifiers such as the AD 504 and
AD510 refer to the null offset terminals to V+. Obviously,
the pot wiper should go to the V+ terminal of this type of
amplifier. It's important to connect the line directly to the
op amp terminal so as to minimize the common impedance
shared by the op amp current and the null pot connection.

"

Figure 13. Details of Vos Nulling - the "Other" Input

As it's drawn, the Vas null pot wiper connects to a point
along a V- "clothesline" which carries both the returh current from the amplifier and currents from other circuits
back to the power supply. These currents will develop a
small voltage, IlV, along the conductor between the amplifier V- terminal and the null pot wiper. If the null pot is
set on center, the equal halves will form a balanced bridge
with the resistors inside the amplifier. The effect of the
voltage generated along the wire is balanced at the Vas
terminals and will have little effect on the amplifier output.
On the other hand, if the null pot is unbalanced, to correct
an amplifier offset, the bridge will no longer balance. In this

Figure 14. Connecting the Null Pot for Trouble Free
Operation

The considerations for op-amp null pots also apply to the
similar trimmers on almost all types of integrated circuits.
For example, the AD521 In-Amp null terminals exhibit a
gain of about 30 to the output. Although this is much less
than in the case of most op-amps, it still warrants care in
controlling the null pot wiper return. Table I lists the integrated circuits manufactured by Analog Devices, including
some popular second-source families, and indicates how internal conversions from differential to single ended are referred. That is, the signals are made to appear with respect
to the terminal(s) listed.

APPLICATION NOTES 11-107

m

IntemaUntegrator
Referred to:
AD DP 071
27/37

V+,V-

AD380

V+

AD390

VVV-

AD3941AD395
AD396

lmarnallntegrator
Referred to:

Comment

Internal Feedforward Cap V+ to Vand Integrator V - to Output

AD507

A0689

AD707/AD708

V+,V-

AD711/AD7121
AD713

V-

and Integrator V - to Output

OF

AD518

V+,V-

Internal Feedforward Cap V .... to Vand Integrator V - to Output

AD521

VVVVVV-, V+

Output Amplifier Integrator

AD532/AD533
AD534/AD535
AD536A

Common

V-

Output Amplifier

AD843

V-,VV+,V-

External Integrator to V ..... Internal
Feedforward V - to Common

Output Amplifier and OAC Control
Loop Integrator Referred to Common

AD561

V-,

OAC Control Loop Integrator and
Ref, Amp Referred to Common and
Ref. Bias Amplifier Referred to V-

AD5471AD647
AD546IAD648

Common

Output and Reference Amplifier
Output Amplifier Referred to V - and
Reference Amp Referred to Common

Common

V-,V-

Common

AD546

AD767

External Integrator to VInternal Feedforward V - to Common

VVVV-,

AD840/AD841I
AD842

AD557/AD558

AD545A

AD766

V-,
Common

Multiplier Output Amplifier Integrator

Output Amplifier Integrator

AD549

AD5441AD644

AD744/AD746

Output Amplifier Integrator

Internal Amplifiers

AD5421AD642

AD7361
AD737
AD741

VVVVVVVV-

AD538

Output Amplifier

Output Amplifiers

AD517

AD526

Internal Feedforward Cap V+ to V-

Output Amplifiers

V..
V+

AD524

Output Amplifier

Output and Reference Amplifier

External Cap to Signal Common

Comm~nt

VVV+

AD704lAD7051
AD706

External Cap to Signal Common or V . . .

AD508
AD510

AD688

AD8441AD846
AD845
AD847/AD8481
AD849

VV-,V-

AD18561AD1860 V-

Output and Reference Amplifier

AD1864

V-

Output and Reference Amplifier

AD2700lAD2710

Common

Output Amplifier

AD2701

VV-,

Output Amplifier

AD27021
AD2712

Common

AD7224/AD7225

V-

Output Amplifiers
Output Amplifiers

AD7226IAD7228 V-

Output Amplifiers

V-,

AD72371
AD7247

Common

AD72451
1,\07248

Common

Reference Amplifier to Common
Output Amplifier to Both Vand Cornman

V-,

Reference Amplifier to VOutput Amplifier to Both Vand Common

AD565A/
AD566A

V-

OAC Control Loop Integrator Referred
to V -. Reference Input Common
to Control Loop Isolated from OAC
Output Common

AD7569/AD7669

V-

Ail Amplifiers

AD568

VVVVVVVVV-, V-,

Reference Amplifier

AD7769

Common

All Amplifiers

Output Amplifier

AD7770

Common

All Amplifiers

Output ~cmplifier

AD78371AD7647

Output Amplifier

AD7840

VV+,

AD580
AD581
AD582
AD584
AD5S6/AD587
AD588
AD6241AD625
AD636
AD637

Ail Amplifiers

Common

Output Amplifier

Output Amplifiers to VReference Amplifier to Common

Output Amplifier

AD7845

V-

Ail Amplifiers

Output Amplifier

AD7846

Ail Amplifiers

Output Amplifier Integrator

AD7848

VV-,

Common

External Integrator to V -, Internal
Feedforward V - to Common

V-,

Internal Feedforward V·- to Common

Common

Output Amplifier to VReference Amplifier to Common

Table I,

Common

AD645
AD650lAD652
AD662

vvCommon

This collection of examples won't solve all your potential
Internal Amplifier

grounding problems.

I hDpe that it will give you some

good ideas how to prevent some of them, and it should

OAC Control Loop Integrator and
Reference Amplifier Referred to
Common

you can put to work in very practical ways. There is no

also give you some of the "inside story" on I.C.'s which

AD664

v-

Output Amplifiers

general grounding method which will prevent all possi-

AD667

V-,
Common

Output Amplifier Referred to vand Reference Amplifier Referred
to Common

tion to detail, and remember that you can always trust

V+

Reference Amplifier

AD668

11-108 APPLICA TION NOTES

ble problems, The only generally applicable rule is attenyour mother, but, . , ,

1IIIIIIII ANALOG

AN·205
APPLICATION NOTE

WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 617/329-4700

Video Formats & Required Load Terminations
by Bill Slattery

A number of international standards exist for specifying
video levels used in television and video monitors. This
application note describes some of the more common
standards and compares their similarities. It also details
the required load terminations for Analog Devices video
RAM-DACs and explains how alternate video standards
can be implemented by altering the load termination.
VIDEO STANDARDS
The NTSC standard is the one most commonly used in
North America and Japan, while Europe uses PAL and
SECAM video standards. Figure 1 shows an RGB video
waveform, and Table I shows the associated current,
voltage and IRE relationships for the various video
standards.

....- - 7 r - - - - - - - - - . . . . , . . . - - - - W H I T E LEVEL

---+----1'--------- BLACK LEVEL
- f - - - - - - ' - - . - - . . . - - - ' - - - - - - - - B L A N K LEVEL

.....L_ _ _ _ _ _.L--'--_ _ _ _ _ _ _ _

SYNC LEVEL

Figure 1. RGB Video Waveform

Table I. Levels Associated with Various Video Formats
Video Output
Levels

IRE Units

Volts

Singly Terminated Line
mA (typl. 750 Monitor

Doubly Terminated Line
mA (typl. 750 Monitor

0.714 ±0.1
0.054 (typ)
0
-0.286 ±0.05

9.52
0.714
0
-3.81

19.04
1.43
0
-7.62

1.0 ±0.05
0.075 (typ)
0
-0.4 (typ)

13.33
1
0
-5.33

26.67
2
0
-10.67

0.714 (typ)
0
0
-0.307 (typ)

9.52
0
0
-4.09

19.04
0
0
-8.19

0.714 (typ)

9.52
0
0
-4.09

19.04
0
0
-8.19

NTSC
RS·343A

Blank to White
Blank to Black
Blank Level
Blank to Sync

100
7.5 ±5

NTSC
RS·170

Blank to White
Blank to Black
Blank Level
Blank to Sync

100
7.5 ±2.5

PAL

Blank to White
Blank to Black
Blank Level
Blank to Sync

100
0

SECAM

Blank
Blank
Blank
Blank

to White
to Black
Level
to Sync

40 (typ)

40 ±5

43 (typ)
100

o to 7

o to 0.049

43 (typ)

0
-0.307 (typ)

NOTE
This table indicates the Blank Level as being the zero reference level while the Sync Level is given·a negative value. In the case where composite sync is asserted
using the DAC, Analog Devices video RAM-DACs have the Sync Level as the zero reference level; the Blank, Black and White Levels are all offset positively by
the value of Sync Level. This will have no effect on the implementation of a particular standard as this is determined by the relative magnitude of the Blank Level
relative to the White Level. The Blank to White Level remains unchanged whether or not sync is being assened by the DAC.

APPLICATION NOTES 11-109

III

The composite video waveform illustrates the relationship between the white level and blank level (gray scale
or video portion) as well as the black and sync levels.
The amplitude level between the blank level and white
level is defined to be 100 IRE units. This corresponds to a
voltage level of either W or 0.714V. The newer international standards specify the lower voltage level of
0.714V. The RS-343A, PAL and SECAM standards all
specify a blank to white level of 0.714V, while RS-170
specifies a level of W. The blank to black level, also
known as the setup or pedestal, is used to ensure a
blacker than black beam level during retrace. The amplitude of the blank to black level vades between 0 and
approximately 7.5 IRE units, depending on the video
standard used. An additional 40 to 43 IRE units are required to drive the beam to the sync level. The sync
levels of 40 IRE units for NTSC and 43 IRE units for both
PAL and SECAM are close enough in tolerance to the 40
IRE levels of Analog Devices video RAM-DACs, thus enabling Analog Devices parts to output either NTSC, PAL
or SECAM video formats. Table I illustrates the various
amplitude levels and their tolerances for the video formats outlined above.

with the various video standards, for both 750 load
termination and 37.50 (doubly terminated 750) load
termination. Figures 2 and 3 show the electrical connections between the video RAM-DAC and monitor. Any of
thEl video standards listed in Table I can be implemented
using eith'er of these two terminations. Note that for
singly terminated loads, lOUT will have to be changed by
adjusting IREF'
IMPLEMENTATION OF RS-343A AND RS-170
Analog Devices video RAM-DACs can implement either
RS-343A or RS-170. This is achieved, in the case of a
doubly terminated configuration, by varying the value of
the source termination resistance Zs. Figures 4a to 4d
show the required terminations as well as the associated
RGB video waveforms for both RS-343A and RS-170
implementation when using the ADV478/ADV471. The
assertion or nonassertion of sync is also distinguished in
these diagrams. The advantage of using this technique
to implement the different video ,standards lies in the
fact that the output current level of the DAC need not be
altered. The relationship between DAC output current,
load termination resistance and voltage across the monitor is given by

The most common of the four video standards used in
computer graphics is RS-343A. The three RGB (red,
green and blue) signals are individually generated, each
one containing video, blanking and sync information. In
many cases however, sync information is only encoded
onto the green channel.

,1"O,-"u'=oT_'_Z-,S'=o-'_Z-=L
VL = - Zs + ZL
voltage developed across monitor
DAC output current
source termination resistance
cable/monitor impedance

LOAD TERMINATIONS
Analog Devices video RAM-DACs are capable of driving
750 monitors using either doubly terminated or singly
terminated loads. Table I shows the currents associated

Since the relevant video standard is determined by the
voltage developed across Zv altering the value of Zs is a
simple method of selecting any of the video standards,

Z, = 7511

(CABLE)

... tv,

'-----

Figure 2. Singly Terminated 75!! Load

Z, = 7511

(CABLE)

Figure 3. Doubly Terminated 75!l Load

11-110 APPLICATION NOTES

v
to'H

0.714

.----,...---------------------,....--'--WHITE LEVEL

0.054

~----------t_----~r_-------------BLACKLEVEL

0.000

~----------~----~-------------BLANKLEVEL

Z,,;::75H

1904mA

'-----.

tO.:"4V
(MAXI

VL = O.714V
= BLANK TO WHITE LEVEL (RS-343A)

Figure 4a. RS-343A Load Termination & RGB Video Waveform (SYNC Not Asserted)

v
tOUT

'0

- . - - - - ,___------------------,"'----WHITE LEVel

0075

+--------+------f------------ BLACK LEVEL

0000

- ' - - - - - - - - -.....------L------------BLANK LEVel

19.04mA

Zs=150H

'--_ _ _..

t 1~\'

(MAXI

VL = 1.0V

= BLANK TO WHITE LEVEL fRS-170)

Figure 4b. RS-170 Load Termination & RGB Video Waveform (SYNC Not Asserted)

V

1.000

.-----7.:--------------------7""~---

WHITE LEVEL

lOUT

26.67mA

' -______..

VL

=

=
=

1.0V
{O.714 + O.286lV
BLANK TO WHITE LEVel

t ~llv

(MAXI
0.340

~----------+_------f_-------------BLACKLEVEL

0.286

~----------~~~~L--------------BLANKLEVEL

0.000

~------------.....~-----------------SYNCLEVEL

+ SYNC LEVel (RS-343Al

Figure 4c. RS-343A Load Termination & RGB Video Waveform (SYNC Asserted)

II

V
lOUT

1.4

.,.-----..,..,--------------------,..------WHITE LEVEL

0.475

ir----------t-----~~-------------BLACKLEVEL

0.4

~----------~;r_r~'---------------BLANKLEVEL

26.67mA

' -______of
VL

t 1~V

(MAXI

= 1.4V
= fl.0 + O.4)V

=

BLANK TO WHITE LEVEL + SYNC LEVEL IRS-170)

0.000

~------------~-L-----------------SYNCLEVEL

Figure 4d RS-170 Load Termination & RGB Video Waveform (SYNC Asserted)

APPLICA T/ON NOTES

11-111

SELECTABLE TERMINATION
Figures 5a and 5b illustrate an interesting load termination technique which allows the user to select either
RS-343A or RS-170. If the switch is in the closed position,
RS-343A is implemented. If the switch is in the open
position, a blank to white voltage level of 1V is devel-

oped across the 75!l monitor load, corresponding to
RS-170. In the case where sync is not asserted by the
DAC, the termination is as shown in Figure 5a. When
sync is asserted by the DAC, the output must be terminated according to Figure 5b.

Zo=7SU

(CABLE)

ZS, = lS0n

ZL=7sn
(MONITOR)

Figure Sa. RS-343A & RS170 Selectable Termination (SYNC Not Asserted)

Zo=7SU

~--~----------~~
(CABLE)

ZS,=170U

ZS2= 13Sl!

r

ZL =7Sl!
(MONITOR)

SWITCH

Figure 5b. RS-343A & RS170 Selectable Termination (SYNC Asserted)

11-112 APPLICATION NOTES

AN·206
APPLICATION NOTE

1IIIIIIII ANALOG

WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062·9106 • 617/329-4700

Analog Panning Circuit Provides Almost Constant Output Power
by John Wynne

In audio recording and playback it is often required to split
or "pan" a single signal source into a two-channel signal
for stereo effects. To locate the signal source as desired
in the sound stage, the overall signal power is maintained
constant while the relative levels in the derived channels
are adjusted. This application note describes a circuit
which limits variations in the total output power to
±O.ldB.lt uses two CMOS Multiplying D/A Converters to
control the signal levels in the derived channels. CMOS
DACs are ideal in this application because of their low distortion. The DACs function as resistive attenuators using
thin-film resistors which have low noise and very low voltage coefficient. Converters which are especially suitable
for this application are Dual-DACs which contain two
CMOS DACs on a monolithic substrate. These are available from Analog Devices with 8-bit resolution (AD7528)
or 12-bit resolution (AD7537147149).
The simplest and most obvious circuit for panning is
shown in Figure 1. The digital data NB fed to DAC B is the
2's complement of the data NA fed to DAC A. For n-bit converters the digital input codes, NA & NB, can be represented by fractional values, DA & DB respectively, where
DA = NA/2" and DB = NB/2", with NA and NB in decimal
format. Because of the 2's complement arrangement between the DACs, the all O's code or full mute condition is
not allowed - in theory at least. The relationship between
the two fractional representations, DA & DB, is given as:
(1 )

The output voltage expressions for the two channels in
Figure 1 are as follows:
(2)

V ,N

Figure 1. SimplePowerSplitterCircuit

(3)

The performance of a 12-bit system is shown in Figure 2
where the total output power level is plotted versus N A.
The OdB output power level used as the reference level in
Figure 2 is the total output power available when DA = DB
= 0.5, the balanced condition. With this simple panning
circuit, the total output power level at either extreme of
the allowable input code range has increased by 3dB (a
doubling of the power) over the power output level at the
balanced condition. Load impedances, RLA & RLB, are assumed equal for both channels.

APPLICATION NOTES 11-113

II

I

A 1. A2

z!8

~5

~5
>0

+3

....
"0

3: u

5!~

+2

"'c
~OI

1\

1\

~~
O~

"'1"

~5
~~

+1

0001

200

'"

400

V

.........

600

I

= AD·0P07

I

/

../
600

coo

AOO

FFF

EOO

INPUT CODE. N•• IN HEXADECIMAL

Figure 2. Response ofFigure 1 Using 12-BitDACs

A circuit which avoids this doubling in output power level
is shown in Figure 3. The DACs are again driven with 2's
complementary data. The output voltage expressions for
the two channe.ls are as follows:
-DA'V IN

VOUTA = - - -

(4)

1 + DA

-DS'V IN

VOUTS = - - -

1

(5)

+ Os

Power splitter performance for this circuit when implemented with 12-bit DACs is shown in Figure 4. At the extremes of the input code range the total output power is
now only O.5d8 greater with respect to its level at the balanced condition. This amount of output variation would
be acceptable in many applications. Certain applications,
however, may demand better performance than this.

v"

Figure 3. Improved Power Splitter Circuit

I

z!8

0,.:
~::> +0.5

~5

....
>0

"0

3: U

+0.4

5!li

~~

+0.3

0 ..
... >

+0.2

~e

cl"

155
... ~
+0.1

1\
\
'\

-

/
II
i\.

200

"' I-400

600

v
1...---'
600

AOO

coo

INPUT CODE. N.. IN HEXADECIMAL

Figure4. Response ofFigure 3 Using 12-BitDACs

11-114 APPLICATION NOTES

I

:~~-R:~ ~0~~;~P07

+0.6

/

/
EOO

FFF

HIGHER PERFORMANCE POWER SPLmER
A higher performance power splitter circuit can be built by
adding some gain around the CMOS DACs of Figure 3.
The gain factor required is equal to v'2.
In order to provide a DAC output voltage which is v'2
times greater than normal, the effective value ofthe feedback resistor must be made equal to v'2 times the DAC
ladder impedance ROAC' Reference 1 outlines how additional gain can be added to the standard configuration
without requiring a large gain adjustment range or compromising the ciFcuit's temperature coefficient. The circuit configuration of Figure 5 provides the additional v'2
gain factor. Resistors R1, R2 and R3 should have similar
temperature coefficients, but they need not match the
temperature coefficient of the DAC. The three resistors
are precision (0.1%) metal film resistors with standard
EIAIMIL values. When both DAC circuits of Figure 3 are
changed to include the gain resistors of Figure 5, the output voltage expressions forthe two channels become:

(6)

(7)

R3
1.12k

>--+_--0

VOUT

Rl
1.58k
R2

3.83k
A

WHERE R3 = R1' R2

Rl + R2

Figure 5. Additional Resistors to Provide W Gain Factor

The performance of the revised circuit is shown in Figure
6. The total power output at either extreme of the input
code range is equal to the total power output at the balanced condition. The output power level remains constant within a ±0.1d8 error band. With the exception
of R1, R2 and R3, all resistors are metal film, 10kO, 1%
tolerance.

Or-----~----,-----_r--~~~--_.------r_----r_--__,

zig
Q,.:

~~
",I- -0.1
<:::l
>0

"'Q

ww
Oz

5;0

"'S

1-<
:::lID

5~

010

-0.2

.... 1!:


~

Figure 4. ANTILOG OIA Converter (Negative Exponent)

o

Features ofthe circuit of Figure4 include:
INCREASING N
DIGITAL INPUT. N

Figure 3. Expanded LOGOAC Transfer Function Illustrating the Concept of % of Reading Resolution
exhibits a continuously variable output voltage resolution
throughout its transfer function range. The LOGDAC's
voltage resolution is coarsest at or near full scale (OdB)
and finest at or near 0 scalp (mute). Table I shows the equivalent percent of reading resolution for various Analog
Devices LOGDACs.

1. It provides dB attenuation ofV ouT relative to V ,N as determined by the digital word N. (Le., output range is
OdBto -dB)
2. The circuit provides % of reading resolution.
3. The analog input can be voltage or current, ac or dc,
positive or negative polarity - Le., the circuit is basically a CMOS multiplying DAC.

ANTILOG DAC (Exponential with Positive Exponent)
The circuit of Figure 5 is analogous to a mUltiplying DAC
divider circuit. It provides signal gain of V OUT relative to
V ,N as determined by the equations:

dB Resolution
% of Reading Resolution
(~N = ± 1 Count) (~N= +1 Count) (~N = -1 Count)

Model

± 1.5dB

AD7118
AD7111
AD7115

"!"O.375dB
±O.1dB

-15.9%
-4.2%
-1.1%

+18.9%
+4.4%
+1.2%

EONS
and/or

Table I.

+IO.11512rNI

EON9

V OUT = -V'Ne

BASIC CIRCUIT CONFIGURATIONS

V,No-___-.

ANTILOG DAC (Exponential with Negative Exponent)
The circuit of Figure 4 generates output voltage levels as
determined by the equations:

VOUT

= -

V,N 10

EON6

'>-______.....-oV

and/or
-IO.11512rNI

V OUT = - V'Ne

AGND

Figure 5. ANTILOG DIA Converter (Positive Exponent)

WHERE:
LOGDAC resolution in dB
forAD7118:
r=1.5
for AD7111:
r=0.375
for AD7115:
r=0.1
N

EON7

OUT

= Integerequivalentofdigital input
forAD7118:
0:=;N:=;59
for AD7111:
0:=;N:=;239
0:=;N:=;199
forAD7115:
ac or dc input voltage
(nominal range ± 10V)

Basically, the analog input or reference voltage is applied
to the on chip feedback resistor (RFB) and the amplifier
output is connected to the V ,N terminal of the LOGDAC.
The LOGDAC then ends up in the amplifier's feedback
loop, thus the circuit provides dB gain of V OUT relative to
V ,N as determined by the digital input N (Le., VOUT range
is OdB to positive dB). As does the negative exponential
DAC of Figure 4, this circuit provides % of reading resolution.

APPLICATION NOTES 11-123

m

LOG OR LOG RATIO ADC

The circuit of Figure 6 provides an ADC function while performing a LOG compression. Its transferfunction is:

EON10

OR
EON11

V,No-------,
LOGDAC
VREI'-

o---II---'Y-+---i~

UPD

~
11 1274LS02

74LS244

o---.!L
~

16 12

~

~

5

~E14

3

~E13

~

~
A5 o---!.
A6 a---!.
A7

o-.-ll.

A8

o--.!!.

A9

~

AEN

8

j

74LS244

DO-D7

~

CS
UPD
WR
AO
Al AD7537*
DACl

I
I
I
I
V. V3 Vz V, VOl
I
74LS138
I
A
B C G ZA G,
G z•
I
I L-..:J
L--+ 5V
L
______

I

IBM PROTOTYPE CARD

-- ----,

18

2E2

16

2 E5

14

5

6

12
8
7

a---12-

.---I

i) E12

o----!?-

A4

13 9

11

7

~}C~'

A3

WR
AO
Al AD7537*
DAC2

11
3

1

2
4 . /6

9

~

74LS21

10~
8
12

r""",~ ~
..-"'-

4

V

f "F'~,:

"I

L..: 74LS21
10

"

74LS04

Ell

'-<> ""

1"'-. 2
74LS04

+5V
C2. C3. C4. 0.047.,.F CERAMIC
"ADDITIONAL CIRCUITRV OMMITED FOR CLARITV.

Figure 7. IBM PC A TIXT Digital Interface

APPLICATION NOTES 11-129

II

not the same as the overall filter cutoff frequency, as
wasthe case with the Butterworth filter. The remainder
of the design proceedure is the same as that outlined
for the Butterworth filter. An IBM Basic program for
this Chebychev filter is given in Table A2, Appendix 1.
This program tunes each individual stage to its particular cutoff frequency so that a specified overall filter
cutoff frequency is achieved.

This application note deals with the IBM PCAT/XTorcompatible as the digital controller for the analog filter. The filter could equally be controlled using any other microprocessor. Suggested microprocessor interfaces are given in
the AD7537, AD7547 and AD7549 data sheets.

ACKNOWLEDGEMENTS
To Mike Curtin for suggesting the original design idea.
To Sean Morley for his help in building and testing the
circuit.

3. Programmability over filter type (i.e., Butterworth,
Chebychev, Bessel, etc.) as well as cutoff frequency
can be achieved by replacing R1 and R2 of each stage
by an AD7537. This gives us total software control over
all the filter parameters.

REFERENCES
1. L.P. Huelsman and P.E. Allen, "Introduction to the
Theory and Design of Active Filters." McGraw-Hili Publication Number: ISBN 0-07-030854-3.

CONCLUSION
Filtering in the analog domain has many inherent advantages over filtering in the increasingly popular digital
domain. Analog filtering is a continuous time process
whereas digital filtering is a sampled data process. Digital
filters require extensive software routines to implement
such algorithms as FIR and IIR filters. The analog filter utilizes digital processing power to control the filter while
giving analog performance.

v

101 = 1.0210

~
= 9.255

STAGE 1

3. A.D. Delagrange, "An Active Filter Primer, Mod 1"
NSWC Publication Number: TR 82-552.
4. CMOS DAC Application Guide, Analog Devices Publication Number: G872a-15-4/86.

103 = 0.62310

102 = 0.87810

I-Q,

2. M.E. Van Valkenburg, "Analog Filter Design." HoltSaunders Publication Number: ISBN 4-8338-0091-3.

I-Q2

= 2.7962

STAGE 2

104 = 0.34310

Q3

= 1.326

STAGE 3

Q.

= 0.619

STAGE 4

Figure 8. Block Diagram of 8th Order Chebychev Filter

11-130 APPLICATION NOTES

V OUT

f-<>'

I--

APPENDIX 1
10 CLS
20 PRINT "8th-Order Low-Pass Butterworth Filter"
30 PRINT
40 INPUT"FO(kHz)(500Hz .... 48kHz)
50 FO=FO*1000
60 PRINT
70 INPUT"RDACIKohms)(14K TYPICALLY)
80 RDAC = RDAC*1000
90 PRINT
100 INPUT"RPADIKohms) 10 FOR DES.1, 100KFOR DES.2)
110 RPAD = RPAD*1000
120 PRINT
130 INPUT "ClpFarads) 1220pF FOR DES.1, 22pF FOR DES.2)
140 C=C*1E-12
150 REO= 1/2/22*7/FO/C
160 N = 4096*IRPAD + RDAC)/REO
170 PRINT
180 PRINT"CODE
190 N=INTIN)
200 N1 =INTIN/256)' MSB
210 N2=N-N1*256' LSB
220 AD DR = &H300
230 FORC=OT03
240 OUT ADDR,N2
2500UTADDR+1,N1
260 OUT ADDR + 2,N2
2700UTADDR+3,N1
280 ADDR = ADDR + 4
290 NEXTC
300 OUT&H310,0 'UPDATE DACS
310 END

= ";FO
=" ;RDAC

=" ;RPAD

= ";C

= ";HEX$IN);"H"

Table A 1. IBM Basic Program for8th Order Butterworth Filter
10 CLS
20 PRINT "8th-Order Low-Pass Chebychev Filter"
30 PRINT
40 INPUT"FO 1KHz)
50 FO=FO*1000
60 PRINT
70 INPUT "RDAC IKohms) 114K TYPICALLY)
80 RDAC = RDAC*1 000
90 PRINT
100 INPUT "RPADIKohms) 10 FOR DESIGN 1)
110 RPAD = RPAD*1000
120 PRINT
130 INPUT"C(pFarads) 1220pFFORDES.1)
140 C=C*1E-12
150 FOR I =OTO 3
160 READX
170 FC=X*FO
180 REO = 1/2/22*7/FC/C
190 N = 4096*IRPAD + RDAC)/REO
200 PRINT
210 PRINT"CODE" ;1;"
220 N = INTIN)
230 N1 = INTIN/256)' MSB
240 N2 = N-N ,.256' LSB
250 AD DR = &H300
260 AD DR = ADDR + 1*4
270 OUT ADDR,N2
2800UTADDR+1,N1
290 OUT ADDR + 2,N2
3000UTADDR+3,N1
310 NEXTI
320 OUT &H310,0'UPDATE DACS
330 END
340 DATA 1.02,.878,.623,.343

= ";FO
=" ;RDAC

=" ;RPAD

= ";C

= ";HEX$(N);"H"

Table A2. IBM Basic Program for 8th Order Chebychev Filter

APPLICATION NOTES 11-131

II

APPENDIX 2

REFLEVEL
OOOOdBm

IDiV
10000dB

REF LEVEL
OOOOdBm

IDIV
10000dB

~lf~~W

1\·
1\

1\
\
\

\
\

\

111\.11

1\

1\
10k
lOOk
STOP 1 000 OOO.OOOHz

1M

Figure A 1. Amplitude Response of Butterworth Filter for
Various CutoffFrequencies Using Design 1.

REF10.0dBm
10dB DIV

1\

..

\

\

lk

P4~kHZ

\

\

100
START 50.000Hz

K~rl

STOP 1 000 OOO.OOOHz

Figure A2. Amplitude Response of Butterworth Filter for
Various Cutoff Frequencies Using Design 2.

REFLEVEL
O.Odeg

MARKER 40 986.3Hz
- 54 8dBM
RANGE 10 OdBM

M

lk

100
START50.000Hz

IDIV
45.00Odeg

...........

........

.......

"'"
I

1.

START 50.000Hz
RBW100Hz

VBW300Hz

I

jJ

"'"

.......

01.

STOP 150 OOO.OHz
ST30.0SEC

Figure A3. Noise Spectrum ofFilter

11-132 APPLICATION NOTES

.I

fo =15kHz

START 50.000Hz

STOP30 OOO.OOOHz

Figure A4. Typical Phase Response of Butterworth Filter

AN·211
APPLICATION NOTE

r.ANALOG
WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 617/329-4700

The Alexander Current-Feedback Audio Power Amplifier*
by Mark Alexander

This application note was written by Mark Alexander,
who received his BSEE from the University of Toronto in
1981. As a consultant to Analog Devices, Mark describes
a unique power amplifier topology that is the result of
his long standing interest in audio power amplifier design and critical listening of audio systems.
The current-feedback approach presented here meets
the traditional audio requirements of power amplifiers,
but also adds the additional benefit of very high speed
and bandwidth (200 VII's slew rate, 1 MHz bandwidth)
that results in excellent dynamic performance, and
hence, sound quality.
INTRODUCTION
The subject of power amplifier design is one of those
controversial areas of audio engineering that continues
to receive intense debate, despite the fact that there are
literally dozens of papers available to guide the designer. Many different topologies have evolved from the
relatively modest beginnings of solid state power amplifier design in the late 1950s and early 1960s, and this has
lead to a few very unique and original designs. A substantial number of transistorized amplifiers that were
built during these early years were little more than redesigns of vacuum tube circuits with lower voltage supply
rails, and often had performance levels that left a great
deal to be desired. Quite a few of them sounded significantly worse than their thermionic predecessors. The
"real revolution" in audio power amplifier design actually occurred during the 1970s and introduced such new
innovations as direct coupling, fully complementary design, pseudo Class A biasing, and current dumping; not
to mention the discovery of the importance of dynamic
intermodulation distortion testing and its relationship to
slew rate. Unfortunately, the plethora of so called "new"
amplifier designs that have proliferated since this period
·Patent pending. The amplifier described herein is for informational
purposes only with restricted use and no licenses implied. Readers
are permitted to construct one stereo amplifier for their own
personal, noncommercial use. For other uses. contact Analog
Devices for licensing details.

are often variations of older circuits that originated during the 1970s, and generally feature only slight modifications to the input, output or gain stages.
Some designers have demonstrated rail-commutated
output stages, which allow them to improve the operating efficiency of a big amplifier to such an extent that the
huge amount of output transistor heat sinking usually
necessary is reduced to that of a much lower power
design. These can suffer from "switch over" distortion
caused by the output stage switching between different
supply rails, and can be quite objectionable. Certainly,
high output power should not be obtained at the expense of inferior operating specifications, but this is indeed the case with certain types of amplifiers. Some
clever design techniques do achieve quite impressive
performance, however, albeit at the expense of greatly
increased circuit complexity. Still other amplifiers dispense completely with the familiar principles of negative
feedback, and their creators claim that their circuitry
provides a sound more "open and lifelike," even though
the distortion performance is usually poor. On the
whole, though, most audio power amplifiers are essentially discrete copies of monolithic voltage feedback op
amps, such as the 4136, but are invariably simplified to
reduce the transistor count.
The purpose of this technical note is to introduce the . .
audio designer to a truly new power amplifier topology, . .
not an adaptation of an existing design, that offers exceptional performance on a par with the best of the
available solid state designs (voltage feedback or otherwise). This new topology completely dispenses with the
principles of global voltage feedback, so commonly
used in most amplifiers, in favor of a design based instead on the principles of current feedback. In addition,
this note addresses many of the important practical aspects of successfully getting a design off the ground,
aside from choosing the basic core amplifier design. In
almost all cases, having a good basic amplifier topology
is not enough to guarantee that the final piece of equipment will perform to the original design expectations.
Consequently, additional topics such as board layout,
APPLICATION NOTES 11-133

component selection, paralleling output devices, placement of high current wiring, and thermal design are
considered as well.

A LlTILE BACKGROUND ON FEEDBACK
Before dissecting the new audio amplifier circuit in detail, some background on the differences in operational
characteristics between voltage feedback and current
feedback amplifiers is appropriate. Since it is likely that
the reader may not have been previously exposed to the
latter, an overview of voltage feedback followed by a
look at the advantages of current feedback is necessary.
This discussion will allow one to understand why circuits that make use of this relatively new topology are so
important. Because the bandwidth of an audio amplifier
is usually one of the most important specifications, a
relatively simple equation for the upper -3 dB point is
essential. Simplifying the current feedback amplifier and
its attendant feedback network into a representative circuit model for nodal analysis provides the key to arriving
at a compact, but reasonably accurate, expression for
the frequency response. Appendix A has complete details of the circuit analysis.
The theoretical analysis of a voltage feedback circuit that
often accompanies its frequent criticism has been well
described in other works, 1 and thus will not be reiterated
here. Since the original impetus behind the development of this new power amplifier design was a general
dissatisfaction with the performance achievable by voltage feedback circuits, some discussion of their disadvantages is worthwhile. This will serve to set the stage
for the in-depth discussion of current feedback amplifier
analysis, in Appendix A. Although the analysis section
can be skipped without disrupting the continuity of this
note, the reader is encouraged to review it.
Constant gain bandwidth characteristics, resulting from
the application of voltage feedback, present a problem if
one requires reasonably high gain while simultaneously
achieving wide closed-loop bandwidth. Some very high
voltage power amplifiers may require gains as high as
50, for example, plus a bandwidth of several hundred
kilohertz which obviously means that a gain bandwidth
product in the range of 10 MHz to 20 MHz is needed. This
is not easy to achieve, especially in a high voltage design. An additional problem with voltage feedback amplifiers is that their slew rate is usually limited by the
transconductance stage which has a finite maximum
output current, normally equal to the tail current of the
differential input transistor pair, available to charge the
compensation capacitor. High slew rate is very desirable
in a large-signal audio power amplifier and mandates
the use of large input-stage tail currents and small compensation capacitor values. Unfortunately, in the interests of amplifier stability, reducing the value of the
compensation capacitor requires some degeneration of
the input stage (to reduce its transconductance) which
thus reduces the open-loop gain. This action reduces the
loop gain available in the audio band and causes an
increase in THD products, since it is the loop gain that

11-134 APPLICATION NOTES

serves to reduce the open-loop amplifier distortion,
most of which originates in the highly nonlinear output
stage. What all this boils down to is the fact that a
difficult trade-off has to be made between stability,
open-loop gain, and slew rate without compromising
the overall ac performance and transient response.
Clearly, a global voltage feedback scheme may not necessarily be the optimum choice for ultrahigh performance audio power amplifiers, and in some cases it will
not even be possible to meet all the design goals using
this topology.
Current feedback operational amplifiers were originally
introduced because they overcame the bandwidth variation, inversely proportional to closed-loop gain, exhibited by voltage feedback amplifiers. They still show a
slight variation of bandwidth, however, as the gain is
increased above unity, but it is much less significant
than with the latter. In fact, current feedback amplifiers
don't begin to behave like voltage feedback amplifiers
until the closed-loop gain is made quite large (-50). The
simplified model of a current feedback amplifier in Figure 1 shows that it uses a unity gain input buffer whose
output current is fed, via a bidirectional current mirror,
into a transimpedance gain stage. The voltage generated here is then buffered and fed to the output terminal.
Typical values for RT are quite high, usually several hundred kilohms or even a few megohms. R,NV is the output
resistance of the input buffer, and feedback resistors R,
and R2 set the input-to-output voltage gain in a fashion
somewhat similar to that of a conventional op amp.
Here, however, it is an error current 1, that sustains the
output voltage and not an error voltage.

Vo
(OUTPUT)

V,N
(INPUT)

Xl
BUFFER

INPUT
BUFFER

R 1NV

-

Nl

R2

-..
~

Figure 1. The Model of a Current Feedback Amplifier
Shows that an Error Current, I" Determines the Overall
Output Voltage.
The concept of a finite gain bandwidth product can also
be applied to a current feedback amplifier as a measure
of its performance, although it is only meaningful at
high gains. Arguably, the most important attribute of
this topology is that the amount of current available to
charge the compensation capacitor during output slewing is proportional to the difference between the actual
and final output voltages, just like a simple RC circuit. As
such, there is theoretically no slew rate limit with this
topology, which makes it very attractive for an audio
power amplifier. Practical circuit limitations inevitably

impose a restriction on the maximum current level that
can be handled in the gain stage of a current feedback
amplifier, however, and it is this limiting that gives rise
to a finite slew rate. Still, the slew rates achievable with
these types of circuits are often higher by as much as a
factor of 5 (or greater) than their voltage feedback counterparts, for a given quiescent supply current. Current
feedback represents a much more logical choice for a
power amplifier than voltage feedback, and this will be
demonstrated.

POWER AMPLIFIER CIRCUIT TOPOLOGY
Prior to looking at the actual amplifier circuit, the simplified block diagram of Figure 2 will be considered to help
understand how the overall design works on a system
level. This will make the final amplifier circuit easier to
follow. As may be gathered from Figure 2, this is a rather
unconventional design, in which there are two op amp
input stages feeding a single gain stage and power output buffer. By considering this design one block at a
time, however, it is becomes easier to grasp the way in
which each of the major sections interacts with one
another.
The Input Stage
The input buffer used in this power amplifier is simply a
conventional voltage feedback op amp chosen for its
excellent audio characteristics, and reasonably high output current capability. This ensures that the limiting factor in terms of overall amplifier performance will be the
current feedback gain block and not the input stage. The
output current from input amplifier A, is taken from its
power supply pins and fed to the emitters of a pair of
common base cascode transistors that provide regulated dc voltages for the op amps. At first glance this
might appear to be a very strange connection, because

the power supply pins of A, are used as outputs and its
output is used as an input. However, this is in accordance with the model shown in Figure 1 since the output
current from. the input buffer must be fed, via the bidirectional current mirror, into the transimpedance gain
stage. It is here that the high output voltage is ultimately
generated, prior to buffering by the unity gain output
stage. The half-wave rectification action of A,'s output
current, due to its class AB output stage, causes the two
current mirrors to receive complementary input currents. When A, is sourcing output current, it causes a
corresponding increase in the current of the upper mirror and a decrease in that of the lower mirror. This
forces the voltage at the output of the transimpedance
stage to swing positive. For cases where A, is sinking
current, exactly the opposite is true. A current mode
gain stage arrangement such as this is fully complementary and truly push-pull, which means it should exhibit
low even-order distortion. Note that the quiescent supply current of A, conveniently serves to bias the two
current mirrors that sit referenced to each power supply
rail, thus providing an appropriate operating point for
the transimpedance stage and bias voltage generator.
In most commercially available current feedback amplifiers, the input buffer stage has a gain of unity and is
generally of an open-loop design. Here, an op amp is
being used as the input stage instead and thus can be
configured to provide some gain. This is extremely easy
to do since it only involves tapping the shunt resistor to
ground at the output of A,. The overall amplifier midband gain is therefore:

+ -Rs- -)
R6 + R7

(1 )

..-----,.........- - -.....---ov.

V REF1

>-----[.

m
~--~~~--~~--o~

Figure 2. A Simplified Block Diagram of the Amplifier Shows that the Input Amplifiers, A, and A 2 , Feed a Common Gain
Stage and Output Buffer.

APPLICATION NOTES 11-135

The Gain Stage and Frequency Compensation
The outputs of the two current mirrors that are connected to each supply rail feed an adjustable voltage bias
generator which provides the necessary bias for class AB
operation of the complementary MOS-IGBT (MetalOxide-Semiconductor Insulated-Gate-Bipolar-Transistor)
output stage. The bias generator is designed to have
very low output impedance over the operating frequency range of· the amplifier. Compensation is provided by CC1 and CC2; two capacitors are used instead of
one to keep the structure of the gain stage symmetrical.
Unlike the simplified current feedback model shown in
Figure 1, this design has the compensation capacitors
returned to the feedback summing node instead of
ground. This alternate connection has a very beneficial
effect on the amplifier step response when it is loaded
by a fairly low value impedance such as a loudspeaker.
An IGBT emitter follower output stage, such as the one
used in this amplifier, has a transfer function that contains two poles and a real zero plus the usual dc gain
term of slightly less than unity. When the amplifier
drives high values of load impedance, such as the feedback resistors alone, the two output stage poles are
quite high in frequency (usually above 20 MHz), and
contribute little excess phase shift within the amplifier's
passband. Quite a different situation arises when a load
is connected to the output of the amplifier. The two
poles in the output stage now split apart, and the dominant one becomes sufficiently low in frequency that it
contributes excess phase shift at lower frequencies
within the amplifiers' passband. This can cause a considerable problem if the compensation scheme in Figure 1
is used since it may result in undesirable ringing on the
edges of a square wave. The compensation scheme of
Figure 2 overcomes this problem by inserting a high
frequency closed-loop zero that tends to make the amplifier more stable. Also, this compensation arrangement allows the use of smaller capacitors than with the
original scheme. Appendix A shows the complete response of the amplifier when this alternate compensation scheme is used. If we assume that the small signal
transresistance, RT , is quite high and also that the output
buffer gain is near unity, then the closed-loop pole and
zero will occur at frequencies given by:

be demonstrated that the mathematical theory and actual measurements made on the circuit do indeed correlate very well with each other.
Driver and Output Stages
This part of the power amplifier design is quite conventional, relatively speaking, and no attempt was made to
use error correction or pseudo class A biasing schemes
to lower the output stage crossover distortion. Since the
primary design objective for this amplifier was wide
bandwidth and high slew rate, it was felt that any additional circuitry following the transimpedance gain stage
might degrade the closed-loop stability. Besides, low
crossover distortion can be achieved by running the
output transistors at a sufficiently (but not excessively)
high idling current. A simple double emitter follower
driver stage, therefore, was chosen to buffer the voltage
generated by the gain stage and feed it to the gates of
the power IGBTs. This driver stage is capable of providing several hundred milliamps of charging current for
the IGBT gate capacitances while the output is slewing,
and is mandatory in a high speed design such as this.
DC Control Amplifier
The purpose of this additional input stage is to provide
an accurate, low drift, dc gain path to the main output
that is independent of the ac gain path and its poor dc
characteristics. In the original version of this amplifier,
expensive precision matched NPN and PNP dual transistors were used in the two current mirrors, but no dc
control amplifier was used. It was incorrectly assumed
that precise matching of the transistors in each mirror
would result in very low output offset voltage, as long as
the input buffer had reasonably low input offset voltage
as well. As it happens, this is not the case with a current
feedback amplifier. Any mismatch between the two current mirrors results in a finite amount of bias current
appearing at the output terminal of the input buffer,
which must flow through feedback resistor Rs to the
output. It cannot flow through Rs and R7 to ground,
because the current in these resistors is set only by the
voltage appearing at the output of the input buffer. The
output offset voltage, without the dc control amplifier is
thus:

Voos
fPOLE

~

(

2 'Tr 2Rs

~

)

+ R6 : R7 R/NV Cm

(2)

and

_
fZERO

-

(1 +R6-Ra)
-+ R7
4'Tr Ra CC12

(3)

where CC12 is the sum of CC1 and CC2' Notice that the
frequency at which the zero occurs is approximately
equal to the closed-loop bandwidth multiplied by the
gain of the current feedback loop, if R,NV is fairly small in
value. These equations, plus Equation (1), are the necessary design formulas needed to determine the gain and
small signal bandwidth of this amplifier. Later on it will

11-136 APPLICATION NOTES

= V/OSIA1I

(1 +~) (1 + ~ +
R6

R7)

IS/ASRS

(4)

Normally, V ,DS (A, ) can be made quite small by using a
low offset op amp. Unfortunately, the output terminal
bias current, IBIAS ' can be as large as 100 I1A under static
conditions and even larger if a thermal gradient exists
between the two mirrors on the power amplifier driver
board. This can easily lead to an output offset in excess
of 100 mV, which changes as the amplifier warms up. A
large offset like this is likely to cause an audible click
when the relay that connects the loudspeakers to the
amplifier is energized, and is generally undesirable.
The solution to these problems is a low frequency servoloop that controls the dc output voltage, independently
of any low frequency current or voltage fluctuations in

the main current feedback gain path. This is facilitated
by the use of a second low power precision op amp, A 2,
that is configured as an integrator with very low crossover frequency (less than 5 Hz). The low crossover frequency ensures that the integrator will not have any
effect on the performance of the overall amplifier in the
audio band. Voltage feedback is applied from the main
output back to the input of the integrator through resistors R10 and R", which set the closed-loop dc gain. This
gain is made equal to that given by equation (1). Since
A2 drives a resistor connected to ground, as shown in
Figure 2, it behaves as an operational transconductance
amplifier with the output current taken from its power
supply terminals. This compensating output current is
then fed to the two common-base regulator transistors
where it is summed with the signal current from the
power supply terminals of A,. The output current of A2 is
thus forced to cancel IBIAS almost exactly because the dc
gain of the integrator, coupled with the additional gain
produced by the transimpedance stage, is very high.
Consequently, the integrating control loop completely
overrides the current feedback loop at dc and the output
offset is reduced from that given by Equation (4) to:
VOOS

=

VIOSIA21

(1 + ~::)

(5)

This means that it can be made arbitrarily small through
the choice of a low offset amplifier for A 2. Here the cost
of an additional op amp is more than offset by not
having to use expensive matched NPN and PNP dual
transistors in the current mirrors.

AMPLIFIER CIRCUIT DESIGN
The complete circuit diagram for one channel of the
amplifier is shown in Figure 3, and an accompanying
parts list is included in Appendix B. This design utilizes
2 IC op amps, 17 bipolar transistors in the gain and
driver stages, and at least 2 complementary IGBT power
transistors from Toshiba in the output stage. These recently introduced devices are essentially similar to
power MOSFETs in that they have a very high impedance input terminal (the gate) and square-law transfer
characteristics, but are manufactured using a slightly
modified double diffused MOS process. Unlike power
MOSFETs, however, they feature consistently higher
current handling capability for N- and P-channel transistors of a given die size. This allows one to get by with
a smaller die size IGBT output stage than one using
MOSFETs, thus providing a fairly substantial cost savings (especially on the P-channel transistors). The driver
stage in this amplifier can easily accommodate multiple
pairs of power devices in the output stage, because of
its high peak current drive capability, but just a single
pair of 250 V, 20 A IGBTs was used in the version that
was characterized here. Power supply voltages for the
driver board and output stage may range from ±20 V to
±75 V. Most of the components that mount on the compact driver board, the layout of which is shown in Figure
4, are quite readily available and inexpensive.

An input filter with a cutoff frequency of approximately
2 MHz precedes the input stage. It was included to reduce the potential for RF interference problems, and to
eliminate the possibility of the amplifier oscillating on
power-up with the input left floating (something that
was noticed during the original development of this topology). The filter is formed by the 100 n input resistor
and 750 pF shunt capacitor. A 100 kn resistor is connected to ground at the input of A" and provides the
necessary dc bias current path to ground if the input is
inadvertently left open. The overall amplifier gain is set
by R6, R7 , and RB, and substituting the values of these
resistors into equation (1) yields a figure of 24.087 or
27.64 dB. If more gain from the circuit is desired, the
values of R6 and R7 should be changed, but their sum
should be kept approximately equal to 50 n so that the
gain of the current feedback section stays constant (at
about a factor of 16). By simply swapping the 16.5 nand
33.2 n resistors, for example, the gain of the input stage
becomes approximately equal to 3, and the gain of the
overall amplifier increases to a factor of 48.47 or 33.7 dB.
In fact, the gain of the input stage can be made as large
as 20 dB before its bandwidth drops below that of the
rest of the amplifier.
The references for the two common-base regulator transistors (a, and O2), which provide stable supply voltages for the op amps, are actually two pairs of standard
NPN bipolar transistors (2N3904s) used as Zener diodes
(Q'4 through 0,7)' They are connected in series (with
their collector leads clipped off) to obtain a net breakdown voltage of around 15 V for the pair. There really is
a good reason for using such an arrangement since it
would obviously be easier to use a 15 V "Zener" diode,
as opposed to this seemingly more complicated approach. In reality, the connection of two bipolar transistors in this manner exhibits significantly less low
frequency noise than the 15 V "avalanche" diodes, as
they are more appropriately called, and is actually more
cost effective. The composite Zeners are bypassed with
10 ""F 25 V tantalum capacitors, used mainly for reasons
of economy and size, which filter out residual noise from
the diodes as well as the power supply rails. Two resistors marked RBIAS on the circuit diagram (R, and R2),
which are connected to each supply, serve to bias Zener
connected transistors 0'4 through 017 and should be
chosen such that with nominal power supply operating
voltages (anywhere from 50 to 70 volts) about 1 mA of
current will flow through them.
The two Wilson current mirrors connected to each rail,
and fed from the collectors of
and O2, are formed
from a low voltage transistor, a diode and a high voltage
transistor (2N5551 or 2N5401). They are degenerated
somewhat with 100 n 1% resistors to improve matching.
Anti-saturation diodes (02 through 0 5 ) have been included to prevent storage time problems with the cascode transistors (04 and 0.) in either of the two mirrors
during clipping, and this results in extremely rapid recovery from overdrive. It should be noted that the onset
of clipping in the transimpedance stage will occur at

a,

APPLICATION NOTES 11-137

II

...

I

~

e12

V"F

:to

POLY
l00v

...n:g

v.

~

r

:::!

~
~

..,

..--...

~

:!oD101.V

I

~NNELI

+,.....

J ,1

MOUNTED

ON

_TllIHK

'r

I r_., ,

t t.

-+

0+

1

rl

OUTPUT

1

Ql.

=~I

1

'GBT

1110

..L 1 e17 t
F :E ::c 10~F
133O!.a
100v
V100v
el •

D13

lN01.

1
1
L

V

1

I

018
MR022

.J
v-

e13

::r: 2JlF
V

"2V~
~
'.

L

MOlE,
1. ALL RESISTORS,% 114 W METAL FILM. UNLESS OTHERWtsE

POLY
1110V

NOTED, VAWES ARE IN C.

GND

*UOUNTED ON HEATSINK

Figure 3, The Complete Amplifier Circuit Diagram Shows that Inexpensive Small-Signal Silicon Is Used Throughout to
Minimize Overall Cost.

3

Dl.

1N01'

about 2 V from either power supply rail for very small
overdrive conditions, but hard clipping in this stage will
actually be dependent on the current limit of the input
amplifier A,. This occurs because, during hard clipping,
the current summing network connected to the output of
A, is no longer balanced and significant current can flow
in its output stage. Consequently, the current in the mirrors increases very rapidly up to the value of A,'s maximum output capability (usually 30 mA to 40 mAl,
causing a corresponding voltage drop across the aforementioned 100 0 resistors. The effect of this excessive
current in the mirrors is such that it causes the clipped
signal to "pull in" slightly from the rails, as the amplifier
is driven harder and harder into its overload region. It is
very important not to let the circuit stay in this condition
for any significant period of time, since the power dissipation in a, and O2 will increase far beyond their nominally rated value of a few hundred milliwatts. Peak
dissipation in these transistors can reach as much as
1.5 W to 2 W, with typical rail voltages of 50 to 70 volts;
therefore, very large dc input signals or low frequency
square waves should be avoided. If these operating conditions are anticipated, however, clip-on heat sinks for
and O2 are mandatory.

a,

Frequency compensation in this particular design is provided by two 47 pF compensation capacitors that are
connected to the feedback summing node (C 6 and C7 ), as
mentioned previously. This results in a total value of 94
pF. The reason such a large value of capacitance was
chosen is quite simple: it completely swamps out any
nonlinear voltage dependent capacitances that are
present at the high impedance gain node, resulting in
constant amplifier bandwidth as the supply voltage is
varied. Concerns about too Iowa slew rate, with such
large compensation capacitors, are usually justified in a
voltage feedback amplifiers, but here there is as much as
30 mA of current available to charge them and slew rate
limiting will not normally be encountered.
A calculation of the expected frequency response of the
amplifier is now in order, and can be accomplished quite
easily by substituting the value of 94 pF for CC'2. and the
values of 750 0 for Rs, 16.50 for R7 , and 33.2 0 for Rs
into Equation (2). The value for R1NV is a little more
difficult to determine since we must know a priori what
the value of the closed-loop output resistance of A, is, at
the overall -3 dB point of the amplifier. The solution to
this problem actually involves a little bit of circular reasoning, but the motive behind it is rather easy to see. If
Equation (2) is evaluated initially without considering
the effect of R1NV, a closed-loop bandwidth of 1.12 MHz
is calculated. Since the effect of a finite R1NV is to lower
the bandwidth somewhat, a prediction of the final amplifier closed-loop bandwidth will allow an initial guess
for this parameter to be made. In this case a prediction
of a final closed-loop bandwidth of 1 MHz is made. If we
now take the open-loop output resistance of A, from its
data sheet (about 70 0) and divide it by one plus the
value of its loop gain at the predicted -3 dB point of 1
MHz (about 7.68), a value of 9.11 0 is obtained. When

this estimate for R1NV is included in Equation (2), an
overall closed-loop bandwidth of 1.034 MHz is the final
result. This is really very close to the original guess of 1
MHz, and it seems that no further iteration will be necessary to get closer to an acceptable answer. It should
now be plainly apparent that extraordinarily wide
closed-loop bandwidth seems rather easy to come by in
a current feedback power amplifier, even when the compensation capacitors are quite large. For this reason,
careful board layout and wiring techniques are of tantamount importance in actually getting a design such as
this to work properly without oscillating.
The output stage bias voltage generator, connected between the collectors of 0 4 and 0 6, is formed from a
programmable shunt regulator (07 ), with an NPN
emitter-follower buffer (05) driving its control input. This
buffer is not normally required in most applications because the control input bias current of 0 7 (a TL431) is
only a few microamps, but it is included here for thermal
compensation of the output stage idling current. A common problem with biasing output stages that use vertical OM OS devices (MOSFETs and IGBTs) is that at
moderately low current levels, the decrease in VTH of
approximately 3 mVrC causes the collector current to
increase for a fixed gate-to-emitter bias voltage. If transistor 0 5 is securely mounted on the same heat sink as
the power IGBT output stage, its V BE will decrease as the
output transistors heat up. This decrease in V BE of about
2 mVrC, which is multiplied up in the bias generator by
approximately a factor of three, thus helps to stabilize
the quiescent current in the IGBT output stage. A form-C
relay can also be included across the 50 kO bias adjustment pot (VR,), as shown, to allow the amplifier to be
powered up with zero bias voltage on the output transistors. This feature, when used in conjunction with resistive surge protection schemes for the main filter
capacitors (and bridge rectifiers) during power up, will
prevent any static voltage drop across the current limiting resistor due to the amplifier class AB idling current.
Some means must be provided, as well, to protect the
output transistors from any condition that could cause
their gate-to-emitter voltages to exceed the maximum
allowed value of ±20 V. Thus, Zener diodes 0 9 and 0'0
are connected from either side of the bias generator to
the main output, and prevent the voltage seen between
the gain stage and the emitters of the IGBTs from exceeding more than about 12 V.
The IGBT output stage is operated in a complementary
emitter-follower configuration running at an idling current of about 100 mA, and series gate resistors R23 and
R26 are included to limit the frequency response. This
mitigates any tendency, in the fairly wideband output
stage, towards parasitic oscillation. Current in the output
stage is sensed across two low value resistors, R24 and
R25 , connected in series with the emitters of the IGBTs.
As the voltage drop across either of these two resistors
increases towards 0.7 V, 0'2 or 0'3 will begin to conduct
current away from the gain stage and thus limit the

APPLICATION NOTES 11-139

III

output voltage. This is a convenient way to limit the
current in the output stage to a safe value. Emitter degeneration resistors (10 0. ) must be used in conjunction
with the two limiter transistors, 0'2 and 0'3' because
this circuit has quite a bit of gain when active and tends
to oscillate slightly at high frequencies. Since these transistors must sink or source all the current from the transimpedance stage (up to the current limit of A,) when
the output current is being limited, the voltage across
the 100. resistors will increase slightly as the amplifier is
driven into hard limiting. This causes a corresponding
increase in the actual value of limited current, resulting
in a somewhat "soft" limiting curve.
Of course, current limiting alone is not enough to guarantee power transistor integrity if short circuits to
ground at the output are anticipated. This results from
the fact that excessive power dissipation in the output
stage will still occur if the current limit is set fairly high
(actually a very desirable attribute in a modern amplifier). Fusing the power supply feed to the output stage
will usually be necessary for protection of the power
transistors.

Power supply busses travel along the top and bottom
edges of the board, thus providing a convenient means
of picking off power for the various stages. The two
polyfilm bypass capacitors on the board actually have
their own ground return paths that are independently
isolated from the signal ground bus near the input stage.
This may seem a like a subtle refinement, but on the
original layout the bypass capacitors shared the same
ground bus as the input stage, and strange low level
oscillations were noticed on the first prototypes. It
turned out that the oscillation was occurring as a result
of the discharging of the bypass capacitors into the
driver transistors (and ultimately the gates of the output

11-140 APPLICATION NOTES

0

(I

a. Topside Silkscreening
0

0

0

0

0
0

PRACTICAL CIRCUIT CONSIDERATIONS
It is often mistakenly assumed that once a respectable
topology has been chosen for a power amplifier, it is a
simple task to construct a completed unit that meets all
the original design goals. In fact, getting the physical
details of an amplifier's construction properly sorted out
can be just as time consuming as the actual design of
the driver electronics themselves.
Circuit Board Layout
This is probably one of the most critical elements for a
wide bandwidth audio power amplifier. The key to good
board layout for this design is to keep trace lengths to an
absolute minimum wherever possible, and to keep the
overall layout very small in physical size. Figure 4 shows
the layout of the board used to characterize this new
topology, and as can be seen, the component packing
density is reasonably high-it measures less than 9 cm
on a side. The layout of the driver board actually follows
the amplifier circuit diagram fairly closely in orientation,
since it was begun on the left hand side where the input
stage resides, and finished on the right where the output
stage drivers are located.

JRG

0

_ . ._ _ii~--o

0

0

0

0

00

0

ooo~

000

00

000 0

~

o

o

o

o
0

o

o

JRG

o

b. Topside Layout

c. Bottomside Layout
Figure 4. A Compact Driver Board Contains All Amplifier
Circuitry Except the IGBT Output Stage.

transistors) due to an initial perturbation in the circuit.
This initial disturbance eventually lead to a self sustaining relaxation oscillation (of a few hundred hertz) because the ground bus surge, as the capacitors were
discharging, was sufficiently large so as to be coupled
back into the input stage of the amplifier. The improved
layout of Figure 4 does not exhibit this anomaly.
Critical Component Selection
Some of the resistors in this design require great care in
their selection, since the wrong type of resistive element
will lead to unexpectedly poor performance. In particular, the 750 n feedback resistor Ra should be an oversized completely noninductive metal film power resistor
with a dissipation rating of at least 2 W (remember that
the peak current in this component may be as high as 75
mAl. Failure to use a resistor with a high enough power
rating will very likely lead to thermal modulation of the
actual resistance value and a corresponding increase in
overall amplifier intermodulation distortion when large
low frequency input signal components are present. Additionally, a low temperature coefficient of resistance is
very desirable for this part. The current sensing resistors
in the output stage (R 24 and R25 ) should also be of the
low or noninductive variety. Since the short rise time of
the amplifier (approximately 350 ns) means that a large
di/dt in the load, and hence these resistors, can occur,
any excessive inductance will cause the voltage across
them to increase during fast edge transitions thus causing premature current limiting.
Input amplifier A, plays a significant role in the overall
performance of the amplifier. It must possess all the
desirable characteristics of a good line level audio op
amp (namely low distortion, high slew rate and wide
gain bandwidth product), plus it must have good output
current capability as well. The SSM2131 BiFET audio op
amp with a GBW of 10 MHz and slew rate of 40 V/."s
more than meets the requirements for this design. Also,
amplifier A2 in the integrating dc control stage must
have very low input offset current in addition to low
offset voltage. This is because 1 Mn resistors are used,
in series with its input pins, to obtain the long time
constant needed in this stage. Too large an input offset
current would cause a sufficiently large differential dc
error to appear across these resistors (many mV) and it
would render a low input offset voltage op amp totally
useless. The OP-97 adequately satisfies these requirements with an input offset current of only 30 pA and
offset voltage of 30 ."V.
Paralleling Output Transistors
This is an extremely important topic because most amplifiers will use more than one pair of output transistors
per channel, so that low impedance loads can be accommodated without the output stage self-destructing.
Since the maximum power dissipation in the output
stage increases with decreasing load impedance, it is
desirable to ensure adequate static and dynamic current
sharing amongst all the output transistors. This will minimize the junction-to-case temperature rise in anyone

output device. Power MOSFET output stages can be
effectively made to share current by means of tight thermal coupling between all transistors, and through the
inclusion of appropriately valued series sourceballasting resistors. There is no reason to believe that
power IGBT output stages, with their very similar square
law transfer characteristics, will behave any differently if
the same techniques are employed.
Typically for best current sharing in a MOSFET output
stage, the value of the source resistors should be
»1/gm of each transistor over its desired drain current
range. Since the transconductance is lowest at the output stage quiescent point, using this value of gm should
guarantee sharing over the full output current range.
Unfortunately, in practice this may lead to rather large
resistance values and correspondingly large voltage
drops when high values of load current are being delivered. A better solution is to do a limited amount of
prescreening on the N- and P-channellGBTs to eliminate
any devices with larger than average characteristic deviations in VTH and gm (at the idling point). Once this is
done, it becomes feasible to use series emitter resistors
in the range of 0.2/gm to 0.5/gm, which will help to
minimize the voltage drop. For the Toshiba IGBT output
devices used in this design, the typical gm at an emitter
current of around 100 mA is close to 1S. For example, if
an eight transistor output stage is needed that must
have a total idling current of 400 mA. series emitter
resistors in the range of 0.2 n to 0.5 n are acceptable
along with some limited screening of the output transistors prior to installation.
Wiring Techniques
Some amplifier designers relegate power supply and
output terminal wiring to the lowest level of the design
phase. However, since these wires may carry large pulsating currents with a harmonic content well above the
audio band, it pays to devote some attention to this task.
Wiring is probably one of the most critical things that
must be accomplished successfully, if the final design is
to get anywhere close to the performance measured on
a prototype breadboard (where the wires are normally
quite short). Usually the layout of the power supply
wiring is not particularly well controlled, but some very
simple rules should be observed that will maximize the
likelihood of success at first power up.
One of the most important rules in wiring layout is to
use twisted pairs for the forward and return currents
paths in any loop. This minimizes the series inductance
of the conductors, since inductance increases with cross
sectional loop area. Thus all power supply wires from
the filter capacitors to the amplifier output stage{s) (and
driver boards) should be twisted together, as shown in
the system connection diagram of Figure 5. Fuses are
placed in series with the power rails to protect the output stage in the event that an accidental short circuit in
the load occurs. They should be of the fast blow type,
and must be rated appropriately so that they will not

APPLICATION NOTES 11-141

II

C14

V+ FUSE
(FAST BLOW)

33O.F10OV
C16

R23

10.F1ODV

RELAY
DRIVE

LOUDSPEAKER
TERMINALS

"

TWIST OUTPUT
WIRES TOGETHER

INPUT
CABLE

C17

KEEP THIS GROUND
CONNECTION AS SHORT AS
POSSIBLE

10.F100v
C15

+

33O.F 100v

,

BRAID POWER
SUPPLY WIRES
TOGETHER
NOTE:
KEEP CONNECTIONS BETWEEN
DRIVER BOARD AND OUTPUT STAGE
AS SHORT AS POSSIBLE

V-FUSE
(FAST BLOW)

Figure 5. A Power Wiring Scheme Requires Proper Attention to Detail If Low Distortion Is to Be Achieved.

open up under peak output power levels. The wires that
run from the output stage to the loudspeaker connectors
should also be twisted together, as shown, to minimize
their inductance. All interconnections between the driver
boards and their respective output stages should be kept
very short, in the interests of closed-loop stability. The
series gate resistors for the IGBTs should be connected
directly at the package terminals of these devices.
These tips are all a definite step in the right direction, but
there is something else to consider that is decidedly not
obvious. Since the positive and negative supply leads
which feed the output stage(s) have half-wave rectified
current waveforms, as shown in Figure 6, the harmonic
current (occurring at even multiples of the fundamental
output frequency) circulates in the loop formed between
the power supply capacitors and the output transistors 2 •
If there is any mutual inductance between these power
supply leads and the output terminal loop, after the
point at which negative feedback has been extracted,
even order distortion components can be induced in the
output that cannot be attenuated by the feedback action
of the amplifier. For a typical amplifier with RL = 8 nand
sinusoidal excitation, then at an output frequency f =
10 kHz, the induced second harmonic component in the
output loop will be approximately 0.33% per ,..H of mutual inductance. It should be noted that the magnitude of
the induced distortion components is proportional to the
output frequency (i.e., they get larger as the frequency
goes up), which can be minimized by keeping the power
input and speaker wiring runs perpendicular to each
other. Thus the output transistors should be physically
11-142 APPLICATION NOTES

connected to the power supply feed and output terminal
cabling as shown in Figure 7. This approach minimizes
the mutual coupling between the power input and output paths of the amplifier.
Heatsinking and Thermal Considerations
Heatsink selection should never be underestimated because it is one of those critical areas that, if neglected,
will inevitably result in damage to the output transistors
from excessive junction temperature. In most class AB
power amplifiers, the total dissipation in the output
stage is split equally between the two banks of output
transistors (the N-channel units and the P-channel units).
An equation that relates the power supply rail voltage
and load impedance to the total maximum output stage
power dissipation, under sinusoidal excitation, is given
by:

PD/55

(max) =

2

'IT

Vel

21ZLIcos6

(6)

where 6 is the phase angle of the load. As an example,
consider the case of an amplifier with a two transistor
output stage powered by ±60 V rails, and loaded by an
impedance of 8 n with a phase angle of +30°. Under
these conditions the maximum dissipated power will be
105.3 W. The Toshiba N- and P-channellGBTs are rated
for 180 W dissipation at a Tc of 25°C, but this is derated
to zero at aTe of 150°C. The junction-to-case thermal
resistance (R.Jcl for these transistors is calculated by
dividing the total difference in case temperature change
(125°C) by that of the total change in power dissipation

I'~t

V.

I

,,,

-L..
CIRCULATING
lV\QC: t

I

,

,,

r--,~

'I,

KP .
LOAD

RL

U
, I.

-L..
V-

1·UL.t

Figure 6. Harmonic Currents in a Power Amplifier Circulate Between the Supplies and the Class AB Output Stage.
BIAS COMPENSATION
TRANSISTOR

~

FROM
POWER
SUPPLY
N·CHANNEL
GATE DRIVE
FEEDBACK

TO
P·CHANNEL
LOAD
GATE
DRIVE

IOENSE-

Figure 7. The Preferred Output Stage Layout and Component Placement
(180 W). This results in a figure of 0.694°CIW. Since the
total power dissipated in the output stage is split equally
between the two transistors, the effective ReJC is equal
to 0.694/2 or 0.34JOCIW. To ensure that the output stage
transistors do not reach their maximum allowed junction temperature of 150°C, the total thermal resistance
from junction-to-ambient (assuming TA = 25°C) must
not be greater than 125°C/105.3 W or 1.19°CIW. When
the junction-to-case thermal resistance of the total output stage is subtracted from this number, we are left
with the net allowed case-to-ambient thermal resistance
(R ecA ) of 0.843°CIW. This value includes any thermal
resistance due to the insulating washers that must be
used to prevent the transistors from making electrical
contact with the heat sink (often as much as 0.3°CIW per
insulator). Thus in reality, some allowance for the interface materials must be made in the choice of the final
extrusion which will provide heatsinking for the power
transistors. In the example here, a large finned heatsink
with a sink-to-ambient thermal resistance (ResA) of
around 0.69°CIW is required. Of course, had two pairs of
transistors been used in the output stage, the net ReJc

would have been lower by a factor of two and a smaller
extrusion could have been used for the heatsink. Thus
there is a limited trade-off that can be made between the
number of transistors and the size of the output stage
heatsink, for a given power supply rail voltage and load
impedance.

MEASURED PERFORMANCE
Table I provides a synopsis ofthe overall performance of
the current feedback power amplifier using the new
complementary IGBT output devices. Although this design does not achieve astoundingly low distortion levels
typical of more complex topologies that employ linearization schemes in the output stage, the measurements
made show that the THD and IMD generated by this
circuit are still respectably low. Figure 8 shows that the
overall harmonic distortion at 50 W output into an 8 n
load is a minimal 0.001% at 1 kHz, rising to just under
0.009% at 20 kHz. This is a particularly good result considering that only one pair of output transistors has
been used. Also, no low-pass LR isolation network has
been used in series with the output that would tend to

APPLICATION NOTES 11-143

II

attenuate the high frequency harmonics. This would artificially improve the amplifier performance in the vicinity of 20 kHz, and was deliberately excluded. SMPTE
intermodulation distortion for 60 Hz and 7 kHz mixed 4:1
is plotted in Figure 9 as a function of the rms input level
and, as the curve indicates, it is extremely low being just
0.0004% at 41.7 W into 8 n (0.92 V rms input). The
absence of any significant upward slope in the curve of
Figure 9, except where the amplifier is entering its overload region at about 0.95 V rms input, indicates a lack
of thermal modulation effects on the 750 n feedback
resistor.
aJJIIIDtr-1'BBIIIMCIr: MPLJrIER

n.... CxJ

.... PJIBIICHB)

81 .JIll 91 16:12:15

8.818

I;;,~
..........................

~

..... · · · . . 17 .....
V

. . . .1..

.....

. ......................

~~'*-I.J..l.lIot=-~==1

~.................." ......... "I"...............,
••••••••••••••••••.•••••..•

r

... ··..·1···
.....................................................

28

118

..

...

28k

Figure 8. Amplifier THD Is Below 0.009% Throughout the
Audio Band When Delivering 50 W to An 8 Load.

n

aJIIIIIII'I-~

MlPLIFIBR SltPUOd . .

M'II'L(~)

8.818 ::::.: ........

Table 1. Summary of Amplifier Performance
(VSUPPLV
±40 V, Current Limited to 2.5 A Average
Per Rail, RL = 8 ill

=

Sine Wave Power Output
(Voltage Limited)
Total Harmonic Distortion at 1 kHz
Total Harmonic Distortion at 20 kHz
(Depends Strongly on Idling
Current Level in Output Stage)
SMPTE Intermodulation Distortion
Dynamic Intermodulation Distortion
(DIM-100)
Frequency Response (-3 dB)
Slew Rate
Rise Time (Input Filter in Circuit)
Total Quiescent Supply Current

70W
0.001% at 50 W

0.009% at 50 W
0.0004% at41.7W
0.0012% at 50 W
DC to 1 MHz
>200 V/JLs
400 ns
130-150 mA

Static distortion measurements aside, what does put the
current feedback topology into a class of its own is the
dynamic performance. High slew rate is always critical in
any large signal amplifier design, but proper waveform
control during the reproduction of a square wave is just
as important. Because of the nature of the gain stage
arrangement in this amplifier, slew rate limiting occurs
at a very large rate of change (typically 250 V/JLs). Most
normal program material is unlikely ever to cause slew
limiting in this amplifier, even with large output swings.
Consequently, the value measured for the DIM-100 dynamic intermodulation distortion test is a very low
0.0012% at 50 W output into 8 n, as shown in Figure 10.

81 JUN 91 16:32:28

;iF]

81 .J", 91 16:47:36

aJJIIII!It!-FEIDlIACK MlPLIFIER Dlftb:J ... MlPLcu....)

.............................................................................. ·1

................................................................................................................···················1

....................................................................... ····1

.....
;;"1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .j
............................ :::::.::::: :::::::::::::::::::::.. . ............................................ :::::::::::::::.: :::·:1

. . . . . . . .• j
···········.1

..... ..... ..........................................................................::

. . . .:. .•. ········:····················1

...

.a.s ... .

Figure 9. SMPTE Intermodulation Distortion (60 Hz17 kHz
4: t 40 W into 8
Is Exceptionally Low, Reaching
Almost 0.0002% Before Rising as the Amplifier Enters its
Overload Region.

m

11-144 APPLICATION NOTES

Figure 10. Low DIM-100 Transient Intermodulation Distortion (3.15 kHz/15 kHz 4.1,50 W into 8
Results from
the Clean Transient Response.

m

This is the lowest value of DIM-100 distortion that the
author has ever seen reported for a solid-state power
amplifier. In numerous listening tests, the "fast" sound
of this amplifier and its tight LF performance have been
commented upon. The large signal step response of the
amplifier into an 8 {), load at 100 kHz is shown in Figure
11, and the no load response with an 80 V p-p squarewave at the output is shown in Figure 12. Either photograph reveals that the amplifier is inherently stable and
exhibits no trace of overshoot on fast edges.

+30
+25

r\

+20

!g

+15

~

I

z

~w

+10
+5

"

0

g

-6

~

-10

-15

-20
10

100

10k
100k
FREQUENCY - Hz

1k

1M

10M

Figure 13. The Small-Signal Frequency Response Does
Indeed Extend All the Way Out to 1 MHz, as Predicted by
the Calculations.

Figure ". The Amplifier Exhibits Minimal Overshoot
When Driving a High Frequency Square Wave into an
8JJ Load.

Finally the frequency response, as shown in Figure 13,
does indeed verify the somewhat overbearing calculations done earlier and proves that the closed-loop bandwidth extends all the way out to 1 MHz. Such a wide
frequency response is definitely overkill for any audio
power amplifier (200 kHz-300 kHz is probably more than
adequate), but it does show what is achievable with a
modern design.

CONCLUSION
Once in a while a new design comes along that offers a
different way of doing an old job. The amplifier that has
been presented here offers an evolutionary approach to
the task of driving a loudspeaker. When proper attention
is paid to all the details (and some of them are nontrivial
indeed), current feedback amplifiers can offer superior
sonic performance to all known topologies.
REFERENCES
'Mark Alexander, "A Current Feedback Audio Power
Amplifier," 88th Convention of the Audio Eng. Soc.,
reprint #2902, March 1990.
2Edward M. Cherry, "A New Distortion Mechanism in
Class B Amplifiers," Journal of the Audio Eng. Soc., Vol
29, No.5, pp. 327-32 8, May 1981.

II
Figure 12. A Large Signal Square Wave at 100 kHz
Shows that the IGBT Output Stage Is Inherently Stable
Even Without a Load.

APPLICATION NOTES 11-145

APPENDIX A: FREQUENCY RESPONSE OF CURRENT
FEEDBACK AMPLIFIERS
To derive the. input-to-output transfer function of a current feedback amplifier, the representative model shown
in Figure 14 must be analyzed. Instead of a differential
input stage, this topology utilizes a unity gain input
buffer, driving a low impedance current summing node,
which forces the inverting terminal to be at the same
potential as the noninverting input. A nonzero input
buffer output resistance, R,NV' is shown in series with
the inverting terminal and must be included in the analysis of closed-loop gain versus frequency. Neglecting
this resistance is a common oversight in simplified analyses, and leads to a transfer function that will not show
any bandwidth variation with gain at all. Feedback is
applied from the main amplifier output back to the inverting terminal through the current summing network
that comprise of R, and R2.
"TRANSIMPEDANCE
STAGE"

Vo
(OUTPU1)

resistors, therefore presents a very light effective load
on the output of the input buffer. To derive a transfer
function for this amplifier, nodal equations must be written for nodes 1 and 2, and then combined in an appropriate way to obtain the final result:

1+~
R,

Va

This relationship is actually very similar to that of a
voltage feedback amplifier, and it can be seen that the dc
closed-loop gain is nearly equal to 1 + R,tR, (assuming
that the product RTA BUF is also rel,lsonably large). The
low frequency gain term is something with which most
users of IC op amps should already be familiar. At a first
glance the frequency dependent term might seem to be
quite similar to that ofa voltage feedback amplifier, but
it is in fact very different. This can· be seen more easily if
the expression for the closed-loop pole frequency is
written down:

AsuF

s_
'POLE

=

21T( R2 +

Figure 14.

The action of the input buffer is to force a finite current
to flow through R, that must be balanced by an almost
exactly equal but opposite current in R2 . Any difference
between these two currents is an error current that flows
into or out of the low impedance inverting terminal. This
error current (as opposed to an error voltage in a conventional operational amplifier) is then mirrored and fed
into a transimpedance stage, consisting of RT and Cc,
where current-to-voltage conversion takes place. The
voltage generated here is buffered by another unity gain
stage and is fed to the main amplifier output. Because
the value of the small signal transresistance, RT, is very
high (normally several megohms) only minute error currents are needed to change the voltage at node 2 by
several volts. Consequently, the amount of current that
must flow into or out of the inverting terminal under
steady state conditions is extremely small. The feedback
network, even though it consists of fairly low value

11-146 APPLICATION NOTES

.

(1 + t,)R/NV)C

(8)

c

Interestingly, this result shows that the pole frequency
now depends predominantly on the value of feedback
resistor R2 and the input buffer output resistance R,NV
multiplied by the closed-loop gain. Normally the value of
R,NV is made as low as possible to minimize the change
in pole frequency with gain, and is typically less than
one tenth that of the minimum recommended feedback
resistor value. At high gains, as mentioned before, the
closed-loop bandwidth starts to become inversely proportional to the gain because the term in the denominator of Equation (8) due to R,NV starts to become
dominant. The gain bandwidth product is thus:

GBW =

AsuF

R'NV

(9)

2 1T
Cc
The gain of the output buffer, A BUF , also plays its part in
determining the closed-loop pole frequency. As the
main amplifier output is loaded, this gain drops well
below unity, and causes a reduction in closed-loop
bandwidth as dictated by Equation (8). This actually
tends to make the amplifier more stable since the high
frequency nondominant poles contribute less additional
phase shift at the lower closed-loop -3 dB point. In fact,
many commercial current feedback amplifiers show significant gain peaking with light loads, and don't begin to
behave acceptably until loaded fairly heavily. Another
thing to remember is that the minimum recommended

value for feedback resistor R2 must be strictly adhered
because too Iowa value will result in an excessively high
closed-loop pole frequency. This can result in severe
gain peaking due to the higher order poles becoming
more dominant, and is especially a problem at low gains
when the multiplicative effect of R'NV on the closed-loop
pole time constant is minimal.
During early development of the current feedback power
amplifier it was noticed that instability appeared on the
edges of square waves, using the ground referenced
compensation scheme. Some experimentation revealed
that connecting the compensation capacitors to the
feedback summing node made the instability disappear.
An analysis of the amplifier response using this new
arrangement was undertaken, since something must
have changed to make it more stable. Indeed, when the
compensation capacitors are returned to the feedback
summing node instead of ground, the transfer function
of the circuit changes quite significantly. This modified
compensation arrangement also allows one to get by
with smaller capacitors than before, but without compromising closed-loop stability. To see this, the current
feedback model must be analyzed again but this time

the compensation capacitor Cc is returned to the summing node instead of ground:

The major difference between Equations (7) and (10) is
the appearance of a zero in the numerator determined
by the parallel combination of R, and R2 , and some
additional terms in the denominator. The zero tends to
partially cancel the second pole of the amplifier due to
the IGBT output stage, resulting in greatly improved
stability. Probably the most interesting thing to notice
about Equation (10) however, is that the R2 CC time constant is now multiplied by a factor oftwo instead of unity
as before. Since it is this time constant that predominantly determines the closed-loop pole frequency, the
original compensation capacitor value can thus be
scaled down by a factor of one half.

II

APPLICATION NOTES 11-147

APPENDIX B: AMPLIFIER COMPONENT LIST FOR A SINGLE CHANNEL
Quantity

Designator

Integrated Circuits
SSM-2131 P BiFET Audio Op Amp
OP-97FP Precision DC Op Amp
TL431CP Programmable Shunt Regulator
Transistors
2N3904 NPN. 40 V (4 Are Used as Zener diodes)
2N3906 PNP. 40 V
2N5401 PNP. 150 V (or 2SC2682 from NEC)
2N5551 NPN. 160 V
MPS-U10 NPN. 300 V '
MPS-U60 PNP. 300 V2
GT20D101-Y N-CHAN IGBT 250 V. 20 A (Toshiba)
GT20D201-Y P-CHAN IGBT 250 V. 20 A (Toshiba)
Diodes
1N914 100 V. 100 mA Small Signal Diode
1N5242B 12 V. 500 mW Zener Diode
1N4938 200 V. 100 mA Low tRR Diode
MR822 200 V. 5 A Low tRR Rectifier

A,
A2

07
7
2
3
3
1
1

9
2
2
2

0 " O2 , 0 5 , 0 6 , 0 8 , 0 11 , 0 ,2 , 0 ,3 , 0 '4
0 9 .0 10
0 3 .04
0 ,5, 0 '6

Resistors
(All Values Are in Ohms. and Are 1/4W 1% Metal Film Unless Otherwise Specified)
0.05 !l. 3 W. 5% Noninductive (Shallcross LO-3 Series)
2
R24 • R25
1QO
2
R,9• R20

1aS

1

R7

33.2
100 (2 Are Used as Gate Resistors for the IGBTs)
249
499
750.2-5 W. 1% Noninductive Metal Film
4.k
10.0 k
11.5 k
16.9 k
24.9 k
100 k
1.00 M
RB1AS (49.9 k with ±65 V Power Rails)
50 k!l Multiturn Trimpot (Helitrim 68WR503 or Equivalent)

1
7
1
1
1
1
1
1
1
1
1
2
2
1

Rs
R3 • R,3-R ,6• R23 • R26
R22
R'0

Capacitors
47 pF 5% Silvered Mica (or Ceramic) 200 V
750 pF 5% Silvered Mica (or Ceramic) 200 V
0.1 f.LF 10% Ceramic or Mylar 63 V
1 f.LF 10% Ceramic 100 V
2 f.LF 10% Polyfilm 100 V (Electrocube 230B1 B205K)
10 f.LF 10% Tantalum Electrolytic 25 V
2 to 10 f.LF 10% Polyfilm 100 V
220 or 330f.LF 10% Aluminum Electrolytic 100 V

2
1
4
1
2
3
2
2

Miscellaneous:
Form-C Reed Relay (Coto 2211-12-300)
Thermalloy 6100B Heatsink for the Driver Transistors
Extra Large Finned Heatsink for the IGBT Output Stage
Insulating Pads for the IGBTs
5-Pin Molex Header 0.156 Inch Pin Spacing
7-Pin Molex Header 0.156 Inch Pin Spacing
3-Pin Molex Header 0.100 Inch Pin Spacing
Right Angle RCA Jack
Amplifier evaluation PC Board 3

R8

R'2

R21
R11

R'7
R'8
R4

R5 • R9
R, • R2
VR ,

C6 • C7

C3
C4 • C5 • Ca. ClO

C11
C,2 • C'3
C, • C2 • C9

C,6• C'7
C,4• C'5
K,

2
1
2
1
1
1

'First choice substitution is NEC 2SC2682; second choice Toshiba 2SC2238B. Note correct pinouts.
2First choice substitution is NEC 2SA1142; second choice Toshiba 2SA968B. Note correct pinouts.
'Available to qualified OEMs. Contact local ADI sales office for details.

11-148 APPLICATION NOTES

AN·212
APPLICATION NOTE

r'IIII ANALOG

WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 617/329-4700

Using the AD834
in DC to 500 MHz Applications:
RMS-to-DC Conversion, Voltage-Controlled
Amplifiers, and Video Switches
by Mark Elbert and Barrie Gilbert
INTRODUCTION
The AD834 is the fastest four quadrant multiplier available, having a useful bandwidth of 800 MHz, compared
to the 60 MHz bandwidth of the AD539 two-quadrant
multiplier, the 10 MHz bandwidth of the AD734 fourquadrant multiplier, or the 1 MHz bandwidth of the
industry-standard AD534 four-quadrant multiplier. Its
monolithic construction and high speed makes the
AD834 a candidate for such HF applications as balanced
modulation-demodulation, power measurement, gain
control, and video switching, at frequencies that were
previously beyond the scope of analog multipliers.

OVERVIEW OF THE AD834
The AD834, shown in block schematic form in Figure 1,
is the outcome of Analog Devices' continuing dedication
to high-accuracy analog signal processing. In particular,

The AD834 does not sacrifice accuracy to achieve its
speed. In common with all of the Analog Devices multipliers, laser trimming is used during manufacture to null
input and output offsets and to establish precise scaling.
In typical applications the total static error can be held to
less than ±0.5%.
It is available in 8-pin plastic DIP, SOIC, and ceramic
packages for the commercial, industrial, and military
temperature ranges and operates from ±5 V supplies.
The main challenge in using the AD834 arises from its
current-mode output stage. In order to maintain the
highest possible bandwidth, the AD834's outputs are in
the form of a pair of differential currents from open
collectors. This is an inconvenience when a more conventional ground-referenced voltage output is needed.
Thus, this application note discusses methods for the
accurate conversion of these currents to a single-sided
ground-referenced voltage.
These applications include a wideband mean-square detector, an rms-to-dc converter, two wideband voltagecontrolled amplifiers, a high-speed video switch, and
transformer-coupled output circuits. These applications
provide the user with a complete and proven solution, in
many cases including recommended sources for critical
components.

Figure 1. AD834 Block Diagram

it incorporates the experience gained in twenty years of
manufacturing analog multipliers. The part is constructed on a 3 GHz epitaxial bipolar transistor process
using laser-trimmed thin-film resistors. Attention to
many subtle details has resulted in unusually low distortion and noise. Figure 2 shows a more detailed, but still
simplified, circuit schematic.
The X- and V-inputs are applied to high-speed voltageto-current (VII) converters, having a transresistance of
2850 and a small-signal input resistance of about 25 kO.
The full-scale input voltage is ±1 V for both inputs. The
input bias currents are typically 45 .,A. Therefore, the dc
resistance seen by both inputs of a differential pair must
be equal to minimize offset voltages, just as for an op
amp. Resistors at the inputs also minimize the risk of

APPLICATION NOTES 11-149

III

WI

W2

is customarily controlled by adjustment of the bias currents in the VII converter used on the X-input, which.also
determines the currents in the diode-connected transistors, 01 and 02.
In classical voltage-output multipliers, the range of adjustment needed to absorb the inevitable resistor mismatches is small, and this method of trimming the
scaling factor is acceptable. In the AD834, however, the
transfer function involves the two input VOltages Vx and
Vy , the scaling voltage (generated in the band-gap reference circuit, and trimmed to an accurate value which is
assumed here to be 1 V) and the output current, Iw:
. VxVy .I

Iw

Figure 2. Simplified AD834 Schematic

high frequency oscillations. The VII converters have a
common-mode range of ±1.2V, using the recommended supply voltages. Within that range, the differential inputs exhibit a common-mode rejection of 70 dB,
conservatively specified for f < 100 kHz. Even-order distortion in the VII converters is inherently low, while distortion cancellation circuitry is included to reduce odd
order nonlinearity to typically ±0.05%.
The multiplier core is a well-known translinear circuit.
The translinear principle [Ref. 1] exploits the precise logarithmic relationship between the base-emitter voltage
(V BE) and collector current (ld of a bipolar transistor. The
input and output signals of translinear circuits are always in current form. Voltage swings at the internal
nodes are very small, so that parasitic junction capacitances do not have to be charged and discharged, a
common cause for bandwidth reduction and slew-rate
limiting. Thus, translinear multiplier cells are inherently
fast; they are also readily implemented in monolithic
form. However, they can introduce distortion if not carefully designed.
This distortion is due primarily to emitter area mismatches and ohmic resistances in the core transistors
(Ref. 2). Using the traditional convention in naming the
channels, as shown in Figure 2, the X channel is susceptible to these effects, while the Y signal-path is essentially linear (the four output devices, 03 through 06,
behaving in many respects like common-base stages, or
cascodes). Therefore, the signal requiring the lowest
possible distortion should always be handled by the Y
channel. For example, in a balanced modulator application, the carrier (local oscillator voltage) should be applied to the X input and the baseband signal to the Y
input.
The output from the core is in the form of a pair of
differential currents. Now, the scaling of these currents

11-150 APPLICATION NOTES

= w'li

(1 )

In this expression, the value of a resistance, R, determines the calibration of the output current. As fabricated, thin-film resistors have an initial uncertainty
which can be as large as ±20%, and the customary
methods of trimming the scale factor would result in
other compromises (for example, erosion of the available signal range in the X-input VII converter).
Therefore, the AD834 uses a "Gilbert gain-cell" [Reference 3] after the core to provide the needed adjustment
of the effective value of R, which, in fact, is achieved by
varying the current gain of this cell through trimming
the current IG. R, after the IG trim, has an effective value
of 250 n, resulting in a full-scale output current of
±4 mA when both inputs are at their full-scale value of
± 1 V. The typical current-gain is 1.6, and because this
type of amplifier is very fast and buffers the core outputs, the overall bandwidth of the multiplier is actually
enhanced over that which would be obtained using the
core outputs directly.
The bias currents from the core, and the gain-setting
current IG' result in a fairly large standing current-typically 8.5 mA-which flows into the outputs W1 and W2
(Pins 4 and 5). Only the differential output is precisely
specified to be ±4 mA.
The output currents can be converted back to voltages in
a variety of ways. In the simplest case, load resistors
connected to the positive supply might be used, but
these do not convert the (two) differential outputs to a
single-sided Voltage.
For the AD834 to operate properly, the output Pins (4
and 5) must be pulled above V+ to avoid saturation of
07-010. To avoid using a separate supply to do this,
several of the circuits included here use a voltagedropping resistor in series with the positive supply Pin
(6) of the AD834; this is a higher value than necessary
for decoupling purposes.
This dropping resistor lowers the voltage at Pin 6 to
provide an extra margin of bias for the output transistors. For example, in the mean-square circuit in Figure 3,
11 mA of quiescent current across the 169 n dropping
resistor creates 1.86 V of headroom. The decoupling re-

r-------------~--------------------~-----------------o+6V
,69!l

'Ok!l

49.9"

O.'~F

49.9"
'Oldl

'0"
~--------------------------------------~~--------___o~v

Figure 3. A DC to 500 MHz Mean Square Circuit

sistor in series with the negative supply to Pin 3 is only
lOn, since it is included just to decouple the supplies.
Much of this application note, however, is concerned
with more effective ways of loading the outputs. For
example, because they are fully calibrated, the outputs
of two or more ADS34's can be accurately summed by
simply connecting them in parallel, as is done in the rms
application discussed later in this application note.
MEAN-SQUARED DETECTOR

We will begin with a discussion of a mean square detector (Figure 3), whose output is a dc voltage proportional
to the input power. This circuit is useful in that it requires only a calibrated signal generator and a dc voltmeter to demonstrate the very high speed of the ADS34.
The input signal is applied to the X- and V-inputs connected in parallel. The instantaneous output current is
thus proportional to the square of the input voltage. The
square of a sinusoidal input voltage of amplitude A is an
offset cosine at twice the frequency:

A (sin",t)2 = A2 (1 -cos 2 ",t)/2

(2)

If the input to the ADS34 has this sinusoidal form, then
the instantaneous output current (using Equation 1) is
simply
Iw

7'

2A2 (1 - cos2",t) mA

(3)

the average value of which is just 2 mA for the maximum 1 V amplitude sinusoid.
The full-scale differential voltage which would be measured across Pins 4 and 5 of the ADS34 is, therefore,
2 mA x (50 n + 50 0), or 200 mY. This average is extracted by the low-pass filter formed by the 4.7 .... F 22 .... F
(AVX part #SR505E475MMAA and #SR505a223JAA) capacitors in conjunction with the 50 n collector load resistors, having a -3 dB frequency of about 650 Hz.
Two capacitors are used in parallel since the 4.7 .... F capacitor uses the compact but lossy Z5U dielectric material while the 22 .... F capacitor uses a high Q NPO

dielectric which ensures good filtering at the highest
frequencies. Note that the 4.7 .... F capacitors have a
-20% to +SO% tolerance, so their -3 dB frequency is
not accurate, nor does it usually need to be. Further
filtering is performed by the capacitors in shunt with the
feedback resistors of the AD711 operational amplifier,
configured to have a -3 dB frequency of 65 Hz.
Due to finite averaging Of the circuit, there will be some
ripple for low frequency inputs. For the circuit shown, a
1 kHz input will produce the mean-square plus a
-42 dB 2 kHz ripple; for 100 kHz input, the ripple will be
only -so dB. Since the output is band limited, we can
use a generic low speed op amp with ample commonmode range, obviating the need for level shifting. The
differential gain of the amplifier can be chosen to provide a convenient scale factor.
The full-scale gain of the circuit in Figure 3 is calculated
as follows. The average output current is ±2 mA for 1 V
(peak) sinusoidal input, which creates ±100 mV across
each 50 n output load resistor or 200 mV differential.
The amplifier is configured for a differential gain of 2.5
(feedback resistance over source resistance), yielding a
circuit gain of 0.5 V dc output for 1 V rms input.
The bandwidth of this circuit is limited by package capacitance and inductance. In the S-pin cerdip, the multiplier's response normally starts to rise at 500 MHz due to
package resonance and peaks at SOO MHz before rolling
off. A 24.9 n resistor at the input dampens the resonance yielding an essentially flat response out to
SOO MHz. (The package inductance will be different for a
surface mount ADS34.) Figure 4 shows the results over
frequency for three different power levels using the test
configuration shown in Figure 5.
Neglecting the 24.9 n in series with the high impedance
inputs, the input resistance to the mean square circuit in
Figure 3 is 50 n. Since the full-scale input range is ± 1 V,
the maximum measurable power with a 50 n input load
is 10 mW (20 dBm), assuming a sinusoidal input.

APPLICATION NOTES 11-151

II

ADJUSTED POWER LEVEL: +5clBm

3

ffi!lI2

~~
5l1i!
.11:
ZW

~

___________

Q,A··F~~

____________'

1

0

1\

:331
::Ew

;! z-l

~~ -2
-3

1M

10M

100M

lG

FREQUENCY - Hz

Figure 5. Test Configuration

ADJUSTED POWER LEVEL· OdBm

RMS-TO-DC CONVERTER
The root mean square (rms) circuit (Figure 6) is little
more than the mean square detector circuit described
above followed by a square root circuit. The frequency
response is determined by the front end squarer and
output filter. From the mean-square discussion, the
squarer functions well past 500 MHz, while the lower
-3 dB frequency response is 340 Hz (1000 and 4.7 ILF).
Note that a resistor divider network at the input determines the full-scale input voltage to be ±2 V peak.

3

1\

10M

lG

100M

FREQUENCY - Hz

ADJUSTED POWER LEVEL: -ScIBm

3

\

-3

1M

10M

100M

lG

FREQUENCY - Hz

Figure 4. Frequency Response of Mean Square Circuit
for Input Power Levels of -5 dBm, 0 dBm, and +5 dBm
For greater input ranges, a voltage divider with a series
resistance of 50 0 at the input will scale down the voltage seen by the AD834 while maintaining a proper termination resistance. For example, if the input signal is
applied to a 450 resistor in series with a 50 resistor to
ground, then taking the AD834's input from the middle
node of the voltage divider provides 20 dB attenuation
of the input signal, while maintaining a termination resistance of 500 (45 0 + 5 0).
Detection of low power signals is limited by dc offsets
and the common-mode rejection of the op amp. For
example, a -20 dBm signal, corresponding to 22.4 mV
rms across 500, would result in a 4.5% error in the
presence of only 1 mV of offset in the op amp. A 10%
error can occur if the AD834's X channel offset is just
2mV.

11-152 APPLICA TION NOTES

The square root function is performed by a squaring
AD834 in the feedback loop of an AD711 operational
amplifier. The 2N3904 transistor functions as a buffer.
The resistive divider network (two 100 0) between the
buffered output and the X and Y channel inputs of the
AD834 used in the square root section determines the
output scaling to be ±2 V full scale.
The outputs of the two AD834s are current-differenced.
Accurate output differencing and summing is possible
owing to the precision of the laser trimmed AD834 output signal current scaling. The AD711 forces the difference between the two AD834 signal current to zero. Any
error in the nulling generates a voltage across the two
1000 pull-up resistors.
After additional filtering and level shifting by the 15 k~,
85 k~, and 0.1 ILF network, the residual error is amplified
by the full AD711 open loop gain. The amplified error
signal forces the AD834 in the feedback loop to match its
output to the mean-squaring AD834's output. The error
is nulled when the rms circuit's output is equal to the
square-root of the circuit's input mean-squared, hence
the rms function.
The accuracy of the circuit at small signal levels is limited by inevitable offset voltages. While a nominal 0 V
input with a 1 mV error to a mean-square function generates a 1 ILV output error, the same input error generates a 31.6 mV output error through a square root
circuit.

~~~-------------1~-----1~----------~------------~-o+6V

1011

INPUT
±2VFS

100ll
10kll
100ll

501l

1Skll

OUTPUT
.2YFS

1Skll

e

0.1~F

. . 85kll

~~==~~l-----------------------~~~V

Figure 6. DC to 500 MHz RMS-to-DC Converter

DC COUPLED VCA APPLICATIONS

Where the dc response of the AD834 cannot be discarded, some form of level shifting, either passive or
active must be employed, since high speed op amps
often have inadequate common-mode range. The following applications show the use of active and passive
level shifting circuits in the implementation of wideband
voltage-controlled amplifiers.

A DC TO 60 MHz VOLTAGE-CONTROLLED AMPLIFIER
USING PASSIVE LEVEL SHIFTING

Figure 7 shows the schematic of a circuit employing a
passive network as a level shifter. The op amp chosen
here is the AD5539.
The AD5539 is built on the same process as the AD834
and provides a 2 GHz gain-bandwidth product at high
closed-loop gain. Unlike most op amps, the AD5539

~------~----------------------------~----------~+6V

OUTPUT
XV/(1V)

INTO
SOIl

:lIE

*

DIRECT CONNECTION TO GROUND PLANE
OPTIONAL TERMINATION

Figure 7. DC to 60 MHz Voltage-Controlled Amplifier Using Passive Level Shifting

APPLICATION NOTES 11-153

II

....--_ __1>---_-----0-110

INVERTING
INPUT

+Vs

1

'----!-...(12 FREQUENCY
COMPENSATION

GROUND

7' H--4--4.....----J

• '5

TP

Figure 8. AD5539 Operational Amplifier Simplified
Schematic
features a ground pin and an all-NPN output stage which
operates in "Class A" to achieve the part's high speed
(see Figure 8). Closer examination shows that there is a
limited amount of "headroom" between the output
node and the inputs, and between these voltages and
ground. This, its high speed, and other unusual attributes of the AD5539 require special care in its use.
First, consider the consequences of its Class A output
stage. In most op amps, the output can both "pull up"
and "pull down" on the load, but the NPN emitterfollower output stage can only pull up. The AD5539 has
an internal pull-down resistor (R11) of 2 kn. which can
only supply two or three milliamps. A general-purpose
high-speed multiplier must be able to swing to at least
±1 V while driving the minimum likely load resistance of
50 n. At this output level, the load current will be
±20 mA, which must therefore be supplied by an external pull-down resistor. In fact, the pull-down current
must be considerably more than this, and requires careful consideration.
Figure 9 shows how the calculation is done. The 425 mV
voltage sources are just "lsRc," that is, the standing
current of 8.5 mA at the AD834 multiplied by the load
resistor Rc, which we have here set to 50 n. The 200 mV
sources in Figure 9 (a) are the "lwRc" generators when
the full-scale output current is +4 mA. From here, we
calculate V1 - 5.375 V and V2 - 5.775 V.

Next, we calculate the voitageat W2. Because the input
current to an ideal op amp is zero, there is no loading at
W2 and the voltage is simply V2 multiplied by the attenuation ratio 125/(125 + 50), o"r 4.125 V. Because the input
voltage to an ideal op amp is zero, W1 is at the same
voltage, so we can now calculate the current in the
upper 50 n resistor as (5.375-4.125)/50 mA or 25 mA.
Again, there is essentially no current at the input of the
op amp, so the 25 mA all flows in the feedback resistor
of 125 n, resulting in a voltage drop across it of3.125 V.
Finally, we calculate the output as the voltage at W1
(4.125 V) minus this drop; that is, the output is at +1 V .
Notice a somewhat surprising result at this point: although a current of 20 mA flows into the load, a larger
current, 25 mA, flows in the feedback resistor! This unusual state of affairs is due to the very low value of the
feedback resistor needed to reduce the scaling factor to
the desired value, and the relatively large voltage
needed at the output of the AD834 to ensure proper
biasing of its outputs W1 and W2. Thus, even though the
load needs to be sourced 20 mA, we still need to provide
at least 5 mA in the pull-down resistor Rp to bias the
output emitter-follower in the AD5539. The situation
gets more severe when the output current of the AD834
is reversed, because we now need to sink 20 mA in the
50 n load and the voltage across the feedback resistor is
now even higher.
This situation is shown in Figure 9(b). The calculation is
exactly as before, and we discover that the current in the
feedback resistor is now 39.7 mA. So Rp needs to provide the load current of 20 mA and an additional 40 mA
or so in the feedback path, while the voltage across it is
5 V. This would require Rp = 83 n. In practice, it should
be slightly lower to prevent slew rate limiting the filII
time. Also, the feedback resistor will be raised from
125 n to 133 n to make up for the finite gain of the
AD5539 under these heavily-loaded conditions. If we
take the parallel sum of the 50 n load, the 70 n pulldown and about 150 n effective feedback resistance, the
actual load on the amplifier is only 24 n!
The AD5539 is stable for uncompensated gains of
greater than 5, and the AD5539 in this circuit is operating
at a gain of just over 3. The 0.01 ,...F and 10 n network
compensates by throwing away enough open loop gain
to be stable when driving a 50 n load. For higher impedance loads, the 10 n compensation resistor may need to
be reduced.

+6V

+6V

Rp

a.

b.

Figure 9. Equivalent Circuits for Calculating the Value of the Pull-Down Resistor
11-154 APPLICATION NOTES

A level-shifting network is included between the nodes
Wl and W2, whose average voltage is about +4 V, to the
input of the AD5539 which must be close to ground.
With the values shown, the op amp inputs are set
slightly below ground (about -460 mV). This network
halves the low frequency open-loop gain, which has
some effect on the dc accuracy in the presence of offset
voltages at the input to the AD5539. If output offset is
important, a 500 n potentiometer should be inserted in
series with the 3.74 kn resistors and its slider taken to
-6 V. It is then adjusted for zero output with both X and
Y inputs set to zero.

A DC TO 480 MHz VOLTAGE-CONTROLLED AMPLIFIER
USING ACTIVE LEVEL SHIFTING
Figure 12 (a) shows an active level shifter, using a PNP
transistor as a common base stage or cascode. Here, the
AD834 is modeled by three ideal current sources, two for
the 8.5 mA bias currents and one for the ±4 mA differential signal current. The transistors' bases are tied to
+5 V, setting the emitter potential stays at 5.7 V resulting in a voltage of 3.3 V across the resistors Rl and R2 in
the absence of signal. Figure 12 (b) shows an equivalent
circuit.
+9V

Note also that the "inner" Pins Xl and Y2 on the AD834
are grounded to minimize HF feedthrough; the resulting
phase-reversal at the X input is corrected by swapping
Wl and W2.

R1

+9V
1690

R1

±4mA

B.5mA •

Figure 10 shows the pulse response with the input pulse
applied to the X input and the ¥ input set to +1 V,
indicating a rise time of 6 ns.
-5V

-5V

-5V

a.

-5V

b.

Figure 12. An AD834 Output Stage Using Active Level
Shifting
The equivalent dc bias current of 7.17 mA is found by
solving for the current flowing into the emitter when the
signal current generator is zero. In the ac domain, the
signal current generator sees Rl and R2 both tied to low
impedance nodes. By inspection, the original signal current has been scaled by:
Figure 10. Pulse Response of the DC to 60 MHz VOltageControlled Amplifier
Figure 11 shows a set of frequency responses taken on
an HP8753B network analyzer for Y inputs of + 1 V,
316 mV, +100 mV, and 0 V. In the case of 0 V, the Y input
is adjusted to null the input offsets. Note that the high
frequency feedthrough is less than -65 dB of full scale
(f < 3 MHz).
pH1 521 &M log MAG

10dBi REF OdB

1:-2.991dB
66.162 843 MHz

..........
..........

'-

..rr

,./

,;It'

,
START

.~
I\'tV I'

.Ii

0.:100 OOOMHz

STOP

Rl
± 2.6mA = ±4 mA x Rl + R2

(4)

Since AD834's outputs have very high output impedances, the equivalent series resistance can be ignored.
The entire 7.17 mA flowing into the cascade's emitter
flows out the cascade's collector, assuming a good "',
and across R3. The voltage across R3 is:
4.65 V = 7.17 mA x 649

n

(5)

The operational amplifier's inputs are 350 mV below
ground and are within the common-mode range of a
wideband amplifier.
The bandwidth of a transistor configured as a cascode is
the unity gain frequency (fT ) of the transistor, provided
that the user does not create any spurious poles. Choosing an Rl and R2 such that their parallel sum is too large
for the transistor's parasitic emitter-base capacitance or
an R3 too large for the transistor's parasitic collectorbase capacitance will create unwanted poles that lower
the frequency response of the circuit.

200.000 OOOMHz

Figure ". Frequency Response of the DC to 60 MHz
Voltage-Controlled Amplifier

APPLICATION NOTES

11-155

II

r---------~--~~------------------~-----------------o+5V

X INPUT
±1VFS

6490

('!jl

lpF

OUTPUT
. . XY/{lV)

4020

6490
YINPUT
±lVFS

4020

100

~--------------~----------------------~~----------_o~V

Figure 13. A DC to 480 MHz Voltage-Controlled Amplifier
Using Active Level Shifting
Another potential pitfall when using the active PNP level
shifter is oscillations at the cascode's emitter. The input
impedance of a bipolar junction transistor's emitter is
inductive at frequencies approaching its gain-bandwidth
product (fT ), while the ADS34's output is capacitive. Due
to the high bandwidth of the system, these impedances
can lead to oscillation.

or 1.04 V after the reverse termination resistor. The actual circuit shows a full-scale gain closer to unity.
Figure 14 shows the full-scale step response (-1 V to
+1 V) applied to the X input and theY input set to +1 V
demonstrating the circuit's capabilities with a rise time
of under 2 ns while exhibiting some overshoot, but no
ringing. Note that the output slews at over 500 V/",s.

To prevent such oscillations, the emitter in Figure 12 has
been isolated from the ADS34's output by R2. This prevents oscillations while providing signal attenuation
(gain control) as related in Equation 4. The 2N3906s
provide wideband level shifting without resonance or
oscillation. Care must be taken when using alternative
transistors.
The signal current at the cascodes' collectors is now fed
to a wideband amplifier in a differential current to voltage converter configuration as shown in Figure 13. This
configuration is similar to an op amp driven current-tovoltage converter which typically follows a current output multiplying digital-to-analog converter.
The AD9617 makes an excellent choice to drive the current to voltage converter. The AD9617 is a secondgeneration transimpedance amplifier (also known as a
current feedback or TZ amplifier) with a fully complementary output stage (unlike the AD5539), and optimized for use with a 400 n feedback resistor.
The AD9617 inputs are tied directly to the collectors of
the cascodes. The op amp creates a virtual short between the input nodes, forcing all the signal current to
flow in the feedback paths. The differential transresistance of the convertor is 400 n. The desired scaling can
be attained by means of the R1 and R2 attenuation network described above. The full-scale gain of the circuit
(X = Y = 1 V) at the AD9617's output is calculated as;
2 x 2.6 mA x 400 n = 2.0S V

11-156 APPLICATION NOTES

(6)

Figure 14. Step Response of the Wideband VCA
Figure 15 shows a set of frequency responses taken on
the HPS753B network analyzer for Y inputs of +1 V,
316 mV, +100 mV, and 0 V. The Y input is actually adjusted to null the input offsets. Note that the circuit has a
small-signal bandwidth of 500 MHz (at an input power
level of 0 dBm). This bandwidth is possible with the two
1 pF capacitors at the inverting node. The high frequency feedthrough is less than -SO dB of full-scale
(f < 2 MHz).

CH1 S" 'M log MAG

1:-3.013<18

10c1BI REF OdB

S00.658 268 MHz

1

/"

Figure 17 shows a scope photograph of a 1.5 ns risetime pulse gating a 200 MHz signal. The resulting envelope rise time is 2.7 ns; it has a fall time of 3.0 ns.
Although the switched signal may be much slower, the
output stage from the AD834 should have a bandwidth
greater than 100 MHz in order to maintain an envelope
rise time of 3.5 ns.

/
II-

I"V'
START

1.000 OOOMHz

STOP 1,000.000 OOOMHz

Figure 15. Frequency Response of the Wideband VCA
THE AD834 AS A VIDEO SWITCH
With 0 V or + 1 V applied to the X channel as gate control
and the video signal to the Y channel, the AD834 becomes a high-speed video switch. Figure 16 illustrates
this idea with a high speed current switching circuit
centered around an ECl switch. The current flows
through either 01 or 02, depending on the input voltage. Current switching ensures fast and clean switching
to determined levels (+1 V and ground), and allows the
user to over- or under-drive the gate input.
.5V
• 5V
GATE INPUT
OTO+5V

AC OUTPUT-COUPLING METHODS
In many applications, the dc component at the output
can be discarded. In such cases, a wideband buffer can
easily ac couple to the AD834 output. The circuits below
show the use of simple transformers and baluns for
passive, ac coupled output circuits .
TRANSFORMER-COUPLED OUTPUT
Figure 18 shows the use of a center-tapped output transformer, which provides the necessary dc load condition
at the outputs W1 and W2, and is designed to match into
the desired load impedance by appropriate choice of
turns ratio. The specific choice of the transformer design
will depend entirely on the application. Transformers
may also be used at the inputs. Center-tapped transformers can reduce high frequency distortion and lower
HF feedthrough by driving the inputs with balanced signals. Suitable center-tapped transformers include the
Coilcraft WB2010PC, which the manufacturer specifies
for 0.04 MHz to 250 MHz operation.

~

OPllONAL
TERMINATION

Figure 17. Rise Time of the Video Switch

4.7!l
r--------1r---------<~v

-5V

Figure 16. The AD834 as a High-Speed Video Switch

X INPUT

±1VFS

The AD834 switches on as the gate input rises from +1 V
through +2 V at the gate circuit input. Below 1 V, 01
absorbs almost all ofthe current from the 216 n resistor;
the 2N3906 transistor is turned off. In this state, the
100 n resistor from the X2 input to ground accurately
shuts the Y channel off, with Y channel feedthrough to
the output measured at -50 dB. With the base of 02
held at 1.6 V, the transistor's emitter potential is 2.35 V.
A steady 10.2 mA (minus base current) from the 261 n
resistor generates + 1 V across the 100 n resistor at the
X2 input independent of the exact high level of the gate
input.

V INPUT

±1VFS

L-----____________-<-5V

Figure 18. The AD834 with Transformer-Coupled Output
APPLICATION NOTES 11-157

III

BALUN-COUPLED OUTPUT
Figure 19 shows a circui~ which. uses blocking capaci~ors
~o elimina~e ~he dc offse~, and a balun, a particularly
effec~ive ~ype of ~ransformer, ~o convert ~he differen~ial
(or balanced) signal ~o a single-sided (or unbalanced)
ou~pu~. A balun consis~s of a short leng~h of ~ransmis­
sion line wound on ~o a ~oroidal ferri~e core, which converts ~he 'bal'anced ou~pu~ ~o an 'un'-balanced one
(hence ~he use of ~he term).
r - - -......---......,.-<+5V
1.5R C
X INPUT

±lVFS

YINPUT

±1VFS

Figure 19. The AD834 with Balun-Coupled Output
Although the symbol used is identical to that for a transformer, the mode of operation is quite different. In the
first place, the load should now be equal to the characteristic impedance of the line, although this will usually
not be critical for short line lengths. The collector load
resistors Rc may also be chosen to reverse-terminate the
line, but again this will only be necessary when an electrically long line is used. In most cases, Rc will be made
as large as the dc conditions allow, to minimize power
loss to the load. The line may be a miniature coaxial
cable or a twisted pair.
It is important to note that the upper bandwidth limit of
the balun is determined only by the quality of the trans-

11-158 APPLICATION NOTES

mission line; hence, it will usually exceed that of the
multiplier. This is unlike.a conventional transformer,
where the signal is conveyed as a flux in a rnagnetic
core, and is limited by core losses and leakage inductance. The lower limit on bandwidth is determined by
the series inductance of the line, taken as a whole, and
the load resistance (if the blocking capacitors C are sufficiently large). In practice, a balun can provide excellent
differential-to-single-sided conversion over much wider
bandwidths than a transformer.
IMPLEMENTATION
Building these circuits requires good high frequency
techniques. The circuit schematics suggest suitable layout. Ground plane is essential for all of the circuits
described in this applications brief. It should cover as
much of the component side of the PCB as possible, but
not directly underneath the IC orencirciing any individual pins. Sockets add to the pin capacitance and inductance, and should be avoided. If sockets are necessary,
use individual pin sockets such as AMP pIn 6-330808-3.
They contribute far less stray reactance than the molded
socket assemblies. Each power trace should be decoupled at the IC with a 0.1 fLF low inductance ceramic
capacitor, in addition to the main decoupling capacitor.
All lead lengths should be kept as short as possible. For
lead lengths longer than an inch, stripline techniques
should be used.
REFERENCES
[Ref. 1]Gilbert, Barrie, "Translinear Circuits: A Proposed
Classification," Electronic Letters, Vol. 11, No.6, pp. 126127.
[Ref. 2] Gilbert, Barrie, "A Precise Four-Quadrant Multiplier with Subnanosecond Response," Journal of SolidState Circuits, Vol. SC-3, No.4, pp. 365-373.
[Ref. 3] Gilbert, Barrie, "A New Wideband Amplifier
Technique," Journal of Solid-State Circuits, Vol. SC-3,
No.4, pp. 353-365.

11IIIIIIII ANALOG
WDEVICES

AN-213
APPLICATION NOTE

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 6171329-4700

Low-Cost, Two-Chip Voltage-Controlled
Amplifier and Video Switch
by Charles Kitchin, Andrew Wheeler, and Ken Weigel

INTRODUCTION
Historically, it has been very difficult to build wide
bandwidth, high quality, voltage-controlled amplifiers.
Discrete designs have required a great deal of design effort while monolithic or hybrid integrated circuit approaches to VCAs have been expensive, or they have suffered from poor performance.
With the introduction of the AD539JN, a 60MHz analog
multiplier in a plastic package, wideband gain-control is
now practical at low cost. Used in conjunction with the
5539N wideband op-amp available from either Analog
Devices or Signetics Corp. (also in a plastic package), the
two devices can be connected together to create a highspeed voltage-controlled amplifier (VCA) or Video Switch
with outstanding performance. In addition to providing a
50MHz bandwidth, this combination also satisfies even
the most stringent differential phase and differential gain
requirements. The AD539/5539 VCA is able to drive a 75!l
terminated coaxial cable directly.

A REVIEW OF SOME BASICS
Before describing the complete circuit, some basic principles of analog multiplication, as well as the main features
of the AD539, will be reviewed. Monolithic multipliers
have been commercially available since 1970, following
the discovery of an important circuit design technique
based on the logarithmic relationship between the baseemitter voltage of a bipolar transistor and its collector current. AIlIC multipliers now use this concept, known as the
translinear principle.
One-quadrant multipliers accept input voltages at Vx and
Vy of only one polarity; accordingly, their operation is
confined to quadrant 1 of a 4-quadrant X, Y coordinate
system. Thistypeofmultiplier is of most use in high-accuracy computational roles.
Two-quadrant multipliers can accept voltages of either
polarity at one of their input ports, but they can accept
only a Single polarity voltage at the other input. In gaincontrol applications, the bipolar input is considered the
"signal" input and the single polarity input is referred to
as the "control" input; therefore, when Vx is restricted to

positive values, multiplier operation is confined to Quadrants 1 and 4.
Four-quadrant multipliers allow operation in all four
quadrants with any combination of input polarity. Since
this variety always preserves the correct sign at the output, it may atfirst seem thatthe four-quadranttype would
a/ways be the most useful variety of multiplier. However,
this is not the case.
Until recently, the main emphasis in improving multiplier
performance was directed toward higher precision, and
four-quadrant operation was standard. However, the introduction ofthe AD539 two-quadrant multiplier deviates
from this trend, by providing a 50MHz low distortion device optimized for gain control applications.

SOME ADVANTAGES OF TWO-QUADRANT
MULTIPLIERS OVER OTHER TYPES
Four-quadrant analog multipliers have often been used in
fast computational applications, in correcting the distortion of wide-angle CRT deflection systems, and in performing modulation and demodulation operations. However, in gain-control applications a two-quadrant multiplier is the better choice because this device is optimized
for AC signals. This type of multiplier is often used for precision AGC, for implementing voltage-controlled amplifiers, and for creating various types of programmable
filters.
Two-quadrant multipliers such as the AD539 have important advantages in gain-control applications, where there
is no need (and it is undesirable) to respond to a bipolar
control input voltage. Therefore, one functional advantage of the two quadrant multiplier is that the control
channel can be fully blocked for all values of Vx below
zero. As a practical matter, the offset voltage ofthe control
channel can be made to be about one-tenth that of a general-purpose four-quadrant multiplier; this also provides
improved low level gain accuracy.
Other advantages relate to improvements made possible
in the design of the IC when the four-quadrant requirement is removed. In the AD539, these result in higher

APPLICATION NOTES 11-159

m

bandwidth (60MHz versus 1MHz for a general-purpose
device) with much smaller signal feedthrough at low
gains. better phase response. lower signal-path distortion
(the AD539 will generate less than 0.05% THD at full output in most applications). higher control-channel linearity. and lower noise (particularly at low gains).

TWO-SIGNAL CHANNELS WITH COMMON CONTROL
A unique feature of the AD539 is its own separate signal
input channels. VY1 and Vy2• each with a nominal full-scale
voltage range of ± 2V and each simultaneously controlled
by a common input. Vx . Vx has a range ofzero to + 3V FS.
All inputs are referred to a common (input) ground
connection.
The two-signal channels may be used in many different
ways. First. of course. they can be used to control the
magnitude of a pair of separate input signals. The excellent gain-tracking and high separation between channels
of the AD539 proves to be valuable in this application; in
fact. the bandwidth. crosstalk and other limitations occurring at high frequencies are caused more by the PC board
layoutthan by the IC itself.
In applications where only a single channel is involved.
the signal inputs and outputs may be connected in parallel. When driving grounded resistive loads. this configuration has the advantage of increasing the load power by a
factor of four. Alternatively. the two-signal channels may
be driven from complementary (phase and antiphase)
signals. to achieve distortion figures as low as 0.01%; this
mode is generally of more utility in low-speed applications (those with less than 1MHz bandwidth).
The two-signal channels may also be connected in series.
thus providing a VX 2 Vy function. This results in a circuit
which has higher gain with twice the gain-control range
(up to 100dB is practical) or instead. to provide a circuit
with a more constant bandwidth over a reduced control
voltage range. With the constant bandwidth circuit. the
gain now varies as the square of the control voltage.
which in some applications is advantageous.

V'

A50MHz VOLTAGE-CONTROLLED AMPLIFIER
Figure 1 is a circuit for a 50MHz voltage-controlled amplifier (VCA) suitable for use in high-quality-video-speed applications. The outputs from the two-signal channels of
the AD539 (see "Inside the AD539" for a more complete
circuit analysis) are applied to the op-amp in a subtracting
configuration. This connection has two main advantages:
first. it results in better rejection of the control voltage.
particularly when overdriven (Vx3.3V). Secondly. it provides a choice of either non inverting or inverting responses. using either inputs VY1 or Vy2• respectively.
In this circuit. the output ofthe op amp will equal:
V 0
VOUT -- VX(VY1-VY2)f
2V
or x>
Hence. the gain is unity at Vx = +2V. Since Vx can overrange to + 3.3V. the maximum gain in this configuration
is about 4.3dB. (Note: If pin 9 of the AD539 is grounded.
rather than connected to the output of the 5539N. the
maximum gain becomes 10dB.)
The bandwidth of this circuit is over 50MHz at full gain.
and is not substantially affected at lower gains. Of course.
when Vx is zero (or slightly negative. to override the residual input offset) there is still a small amount of capacitive feedthrough at high frequencies; therefore. extreme
care is needed in laying out the PC board to minimize this
effect. Also. for small values ofVx • the combination ofthis
feedthrough with the multiplier output can cause a dip in
the response where they are out of phase. Figure 2 shows
the AC response from the non-inverting input. with the response from the inverting input, Vy2• essentially identical.
Test conditions: VY1 =0.5V rms for values of Vx from
+ 10mV to + 3.16V; this is with a 750 load on the output.
Thefeedthrough atVx = -10mVisalsoshown.
The transient response of the signal channel atVx = + 2V,
Vy=VOUT = + or -1V is shown in Figure 3; with the VCA
driving a 750 load. The rise and fall times are both approximately7ns.

01: THOMPSON·CSF BAR-100R SIMILAR SCHOTTKY DIODE
SHORT, DIRECT CONNECTION rOGROUND PLANE.

2.7U

~O.47IJ.F

-,v

Figure 1. A Wide Bandwidth Voltage-Controlled Amplifier
11-160 APPLICATION NOTES

10

0.1 . - - - - - - - , - - - - - . - - - - - . . - - - - - - ,

Vx = +3.162V

.........

1'\

Vx = +1V

""

-10
V x = +O.316V

........

-20
Vx

= +O.1V

0.05

f-----+-----+-----+-----l

I\.
I':~

........

-30
Vx

-40

--

Vx = +O.D1V

~

-50

I

V,= - •. u"

-60
1

I'\:

= +O.032V

....

".

I:?"""
-0.1 L...._ _ _--L_ _ _ _...l..-_ _ _ _.l...._ _ _--I

10

100

Figure 2. AC Response of the VCA at Different Gains
Vy =O.5V RMS

W

-1V

FREQUENCY - MHz

1V

BIAS VOLTAGE ON SIGNAL INPUT

Figure 4. Differential Gain of the Voltage-Controlled
Amplifier

t--- t--

r--- ~

-

V--

~

V,:;V-

-1

-1V

OV

1V

BIAS VOLTAGE ON SIGNAL INPUT

Figure 3. Transient Response of the Voltage-Controlled
Amplifier Vx = +2 Volts, Vy = ± 1 Volt

In video applications, it is important that the gain and
phase of the signal channels remain constant over the
full-signal window. These aspects of the response are
known as the differential-gain and differential-phase
characteristics respectively, and are measured by
superimposing a small AC signal at the subcarrier frequency (about 3.58MHz for NTSC systems) on top of a
bias signal that modulates the channel over its nominal
range, usually 0 to + lV. Figure 4 shows the variation in
gain for Vy = -lV to + lV at a frequency of 3.58MHz, for
three values of Vx . Figure 5 shows the phase variation
under the same conditions. In most respects. this performance is similar to that which may be achieved using
more expensive custom circuitry, although the control
channel of the AD539 can be more easily overloaded by
a rapidly changing step input.

Figure 5. Differential Phase of the Voltage-Controlled
Amplifier

A few final circuit details: in general. the control amplifier
compensation capacitor for pin 2. Cc• must have a minimum value of3000pF (3nF) to provide both circuit stability
and maximum control bandwidth. However. if the
maximum control bandwidth is not needed, then it is advisable to use a larger value of Cc• with typical values between 0.01 and 0.1 f.LF. like many aspects of design. the
value of Cc will be a tradeoff: higher values of Cc will
lower the high frequency distortion, reduce the high frequency crosstalk. and improve the signal channel phase
response. Conversely. lower values of Cc will provide a
higher control channel bandwidth at the expense of degraded linearity in the output response when amplitude
modulating a carrier signal. The control channel
bandwidth will vary in inverse proportion to the value of
Cc• providing a typical bandwidth of 2MHz with a Cc of
0.01 f.LF and a Vxvoltage of + 1.7 volts.

APPLICATION NOTES 11-161

II

Both the bandwidth and pulse response of the control
channel can be further increased by using a feedforward
capacitor, Ctt, with a value between 5 and 20 percent of Cc.
Ctt should be carefully adjusted to give the best pulse response for a particular step input applied to the control
channel. Note that since Ctt is connected between a linear
control input (pin 1) and a logarithmic node, the settling
time of the control channel with a pulse input will vary
with different control input step levels.

response shows the output being fully switched in about
50ns. Note that the output is ON when the control input
is zero (or more negative) and OFF for a control input of
+ 1V or more. There is very little control-signal breakthrough.

Diode 01 clamps the logarithmic control node at pin 2 of
the AD539, (preventing this point from going too negative); this diode helps decrease the circuit recovery time
when the control input goes below ground potential.

THE AD53915539 COMBINATION AS A FAST, LOW FEEDTHROUGH, VIDEO SWITCH
Figure 6 shows how the AD539/5539 combination can be
used to create a fast video speed switch suitable for many
high frequency applications including color key switching.ltfeatures both inverting and noninverting inputs and
can provide an output of ± 1V into a reverse-terminated
750 load (or ± 2V into 1500). An optional output offset adjustment is provided. The input range of the video switch
is the same as the output range: ± 1V at either input generates ± 1V (noninverting) or + 1V (inverting) across the
750 load. The circuit provides a dimensionless gain of
about 1,when "ON," or zero when "OFF."

Figure 7. The Control Response of the Video Switcher

2
~~

~

~L

.. . .... .... ..

• I ••
. . . .I . . .

I

~

The differential configuration uses both channels of the
AD539 not only to provide alternative input phases, but
also to eliminate the switching pedestal due to stepchanges in the output current as the AD539 is gated on or
off.
The waveforms shown in Figures 7 and 8 were taken
across a 750 termination; in both photos, the signal of 0
to + 1V (in this case, an offset sine wave at 1MHz) was applied to the noninverting input. In Figure 7, the envelope

R

T

1-

•

I I

~-

Figure 8. The Signal Response of the Video Switcher

n
DENOTES SHORT.
DIRECT CONNECTION
TO GROUND PLANE

..J

+1VIOFF)

LoloNI

·VAlUE WILL VARY SLIGHTLY

-.v

WITH COMPONENT LAYOUT

Figure 6. An Analog Multiplier Video Switch
11-162 APPLICATION NOTES

.,

••

.,)-.:,.........--+---1

.q

II

.. . , . . . I. . .

~
-.

470n

:~~.wING

I

I I

'+9Vo-_....-l

NON·

."

Figure 8 shows the response to a pulse of OV to + 1V on
the signal channel. With the control input held at zero, the
rise-time is under 10ns. The response from the inverting
input is similar.

Correspondingly, the same fraction ofthe signal and biascurrents that is supplied to the common emitter nodes of
controlled cascodes 03-04 and 05-0S is conveyed to the
two outputs.

The differential-gain and differential-phase characteristics of this switch are compatible with video applications.
The incremental gain changes less than 0.05dB over a signal window of OV to + 1V, with a phase variation of less
than 0.5 degree at the subcarrier frequency of 3.58MHz.
The noise level of this circuit measured at the 750 load is
typically 200,...V in a 0 to 5MHz bandwidth or approximately 100nV per root hertz. The noise spectral density is
essentially flat to 4OMHz.

Now consider the signals paths. The voltages VY1 and VY2
are converted to currents by V-I converters which have a
transresistance of 1.74kO. At full-scale input of ± 2V, the
signal current supplied to the cascodes is ± 1.15mA; this
is superimposed on a bias current of 2.75mA. Thus, when
Vx = +3V, the collector currents of either 03 or OS will
consist of a signal component of ± 1mA (0.873 x 1.15mA)
and a DC component of 2.4mA. both of these currents
being proportionally less for other values of Vx . The DC
component is removed by resistors RXI and RX2 , driven directlyfrom Vx . Thefinal output isthus a current of value:

INSIDE THEAD539
Figure 9 is a simplified schematic outlining the main design features of the AD539 multiplier. 01 through OS,
which form the translinear core of the multiplier, are
multi-emitter NPN transistors having a very low base resistance, to minimize noise and distortion; emitter area
scaling is also used in optimizing this crucial section ofthe
circuit. Each of the pairs 01-02, 03-04, and 05-0S form
what is called a "controlled cascode" circuit; this is basically a grounded-base transistor to which has been added
another device which removes some of the signal from
the emitter. This alters the gain of the cascode, from almost unity (when no current is removed) to zero (when al/
the signal is removed). The "controlled cascode" configuration has very desirable characteristics for use in twoquadrant multiplication.
:mre~~'Q---~--------~---------R"

2.5.

A.,

__--,

1.2SkU

Vx
VY
IW =1V x SkO
Notethatthe peak value ofVycan be ±4.2V (using a -Vs
supply of at least - 7.5V) and Vx can overrange by 10% to
+ 3.3V, so the peak output current of each channel can be
slightly morethan ± 2mA, for a maximum of ± 4mA when
the channels are used in parallel. These currents may be
delivered directly to grounded load resistors or to terminated coaxial cables. With coaxial cables, the full SOMHz
bandwidth of the AD539 can be realized, but the peak signal amplitude will be quite limited (to only ± 330mV using
a 750 load). Clearly, some additional gain is needed.
Unfortunately, the amplifiers necessary for additional
gain could not be included on the AD539, due mainly to
power dissipation considerations. Also, gain errors (of up
to ± 1.5dB) will occur using a simple load resistor, because ofthe 20 percenttolerance ofthe thin-film resistors.
Fortunately, by using external op amps, the output currents may be converted to much larger voltages, using
on-chip applications resistors Rw and Rz provided for this
purpose. These resistors have a nominal value of6kO, but
they are laser-trimmed during manufacture so as to result
in high gain accuracy when used as the feedback resistors
around an inverting op amp. When using just Rw (RW1 for
CH1, RW2 for CH2), the transfer characteristic becomes:
Vx
Vy
VXVYf
Vw = Iw x Rw = 1V x SkO x SkO = 1V orVx>O

Figure 9. A Simplified Schematic of the A0539 Analog
Multiplier
A stable 1.375mA reference current (which determines
the multiplier scaling) is supplied to the common emitters
ofthe controlled-cascode 01-02, whose bases are biased
by the control amplifier (a high speed op amp). When the
control input Vx is zero, 02 is biased off. This bias voltage
is conveyed to 03 and OS, which are likewise turned off;
signal transmission to the outputs is thus blocked. As Vx
increases, the current through Rx (Ix) is forced to flow in
the collector of 02; this current only represents a fractional part of the 1.375mA reference current. When
Vx =3V (its nominal full-scale value), 1.2mA flows in Rx
and 02; this is 0.873 (or 87.3%) of the reference current.

When Rw and Rz are used in parallel, the gain is halved,
that is:
Vw = VxVy
2V
The bandwidth is now largely determined by the op amp.
For wideband applications, the 5539N is an ideal low-cost
complement to the AD539; this combination is capable of
providing ± 1V into a 750 load with only a very small degradation ofthe 60MHz bandwidth achieved by the AD539
alone.

APPLICATION NOTES 11-163

II

LAYOUT OFVIDEO-BANDWlQTH CIRCUITRY
Careful component layout, adequate power supply
bypassing, and proper coaxial cable termination are all
very important in the implementation of video-bandwidth
circuits in general. Unfortunately, even when these precautions are taken, some added difficulties can still arise
in the case of voltage-controlled amplifiers. This can happen when leakage ofthe input signal to the output occurs
when the gain should be zero. This feedthrough will cause
ghost images which are generated by the high-frequency
components ofthe unwanted signal.

should be measured first (since this property of the resistor may vary with each manufacturer). Avoid using wirewound resistors fortermination !
The VCA described in this application note was designed
to operate directly into a 750 load; therefore, "back-termination" (i.e., a series resistor which halves the load voltage) was not used. In most cases, the weak reflection from
a short (up to 6 feet) directly driven cable will not cause
any visible effects. However, when using very long cables, it may be necessary to insert a 750 resistor in series
with the output ofthe 5539N to absorb these reflections.

A good ground plane is essential! To help assure this, it
is recommended that part of this ground be run between
the rows of the pins of both chips, on both the upper and
lower surfaces of the PC board. The ground plane for a
typical AD539/5539 layout is shown in Figure 10. In addition, all decoupling capacitors must have minimum lead
lengths to this ground plane. Also, the input and output
connections must be kept short, and should be physically
separated as far as possible from each other. Separate
power supply decoupling for the AD539JN and 5539N is
also recommended.
Proper cable termination is also essential for adequate
high-frequency performance. One-quarter-watt carbon
resistors are well suited for this function since they are
non inductive and quite inexpensive; one-percent-metal
film resistors may also be used, although their inductance

11-164 APPLICATION NOTES

Figure 10. Layout of a Typical AD53915539 Ground
Plane

AN·214
APPLICATION NOTE

1IIIIIIII ANALOG

WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 617/329-4700

Ground Rules for High-Speed Circuits
Layout and Wiring Are Critical in Video-Converter Circuits
How to Keep Interference to a Minimum
by Don Brockman and Amold Williams

In recent issues, Analog Dialogue has dealt extensively
with topics in shielding and grounding," 2 emphasizing
the techniques needed to protect the integrity and precision of analog signals in the dc and audio-frequency
domain from interfering signals, whether at line frequency or at much higher frequencies. To complement
those articles, we suggest here the elements of good
practice for high-resolution "video speed" converters,
i.e., converters of 1O-bit or greater resolution, operating
at word rates above 1 MHz.
Electronics may be frustrating for designers who cross
the threshold from low-resolution-Iow-speed to highresolution-high-speed designs, or from digital to analogsignal-conditioning circuits. For them, it often seems the
"ground rules" have changed.
Experienced designers can readily attest to the difficulty
of obtaining consistent grounds. They can relate stories
about the ground that wasn't where they thought it was,
or the ground that wasn't there at all, despite a conviction that "it has to be." On printed-circuit (p-c) boards,
wires andlor runs that seemed to be perfectly good
grounds are transformed into inductors or worse in
high-speed or high-frequency circuits.
At ADI's Computer Labs Division, where high-speed circuits are its bread and butter, applications engineers
have found that grounding is the focus of a large percentage of questions from designers making their initial
foray into high-speed circuits. In most cases, the designers encountered difficulties as the result of being unaware of-or ignoring-certain basic ground rules.

BASIC PC-CARD RULES
Knowledgeable high-speed circuit designers have
learned that every square inch of a printed-circuit board
'Alan Rich, "Understanding Interference-Type Noise," Analog Dialogue 16-3, 1982, pages 16-19.
2Alan Rich, "Shielding and Guarding: Analog Dialogue 17-1, 1983,
pages 8-13.

REV. A

which doesn't contain circuits or conducting runs should
be ground plane. Violating that simple rule invites disaster. But sometimes, strict adherence to the rule is still no
guarantee of success if circuit density is too high; then
one must reduce the density and create more "real estate" for the ground plane.
Our applications engineers strongly recommend that all
bread-board designs be done on double-sided copperclad boards. Although this is not a sure cure for ground
problems, it improves the designer's chances.
Another basic rule for working with high-speed andlor
high-frequency printed-circuit-board designs is to connect analog ground and digital ground together within
the PC board. This technique is used, for example, in
Analog Devices card-level high-speed aId converters
(e.g., MOD-1005, MOD-1020, MOD-1205, CAV-0920, and
CAV-1210). Connecting the two grounds enhances the
performance of the converters when they are operated
either by themselves or as tightly knit subsystems. However, it can raise some system-level problems, to be
discussed below.
Another rule for printed-circuit-board designs containing
analog and digital circuitry is to use every available
spare pin for making ground connections, and to use
those pins to separate the analog and digital signals
entering or leaving the board.
Avoid using purely insulating (e.g., "Vector") breadboards and small-diameter hookup wire (e.g., #24) for
connections, including supply voltages and grounds.
The approach will create ground and noise problems if
the circuit is intended to operate at 1 MHz or more (it will
probably lead to problems at even slower speeds).
To summarize: Use double-sided copper-clad boards
with maximum ground area and heavy, well-located
power-supply and ground-return leads. Tie rounds together locally.

APPLICATION NOTES 11-165

II

GENERAL CIRCUIT PRACTICE
Any subsystem or circuit layout operating at high
speeds with both analog and digital signals needs to
have those signals physically separated as much as possible to prevent possible crosstalk between the two. Digital signals leaving or entering the layout should use
runs that have minimum length. The shorter the digital
runs, the lower the likelihood of coupling to the analog
circuits.

Analog signals should be routed as far from digital signals as size constraints allow; and the two, ideally
should never closely parallel one another's paths. If they
must cross, they should do so at right angles to minimize interference. Coaxial cables may be necessary for
analog inputs or outputs-a demanding condition mechanically, but sometimes the only solution electrically.
When combining track-and-hold and aid-converter hybrids or modules on the same board, keep them as close
together as is practical. All grounds need to be connected to the single, low-impedance ground plane: and
the connections should be made right at the units themselves (another argument for having large amounts of
good, solid ground plane available all over the p-c
board).
A suggested practical approach for accomplishing this is
illustrated in Figure 1, which shows a flow-chart layout,
as the preferred method for combining high-speed analog and digital circuits on a p-c board.
If one assumes a 10-volt input range on the 12-bit aid
converter, the least-significant bit (LSB) of the ADC will
have a value of 2.5 mV (10 V/4,096). Assume that a single
pin of the p-c connector, which is used for ground, has a
resistance of 0.05 ohm-and that the p-c card draws a
total of 1.5 amperes.
The voltage drop at the ground pin could be 75 millivolts
in these circumstances. If only digital logic were used,
this voltage drop would be minuscule, hardly worth considering. However, the hypothetical real-world situation
being considered here is a mixture of both analog and
digital circuits, and the 75 mV can have a significant
impact on the subsystem's performance.
In this example, the digital circuits are TTL. Since TTL is
a saturated logic, ground currents vary widely, and varying current flowing through the ground often produces
noise signals which modulate the ground plane. This
noise, created by digital switching, can couple into the
analog portion of the circuit and have an important effect on performance, even at low digital levels. For example, if only 10% of the 75-millivolt I-R drop cited here
couples into the analog signal, that would represent 3
LSBs.
The result? The circuit intended for operation as a 12-bit
system is now reduced to a system of 10 to 11 bits,
because of noise masking the 2.5-millivolt level of the
desired 12-bit LSB. The recommended solution? Assign
multiple pins for ground connections, to reduce the total
contact resistance. As Figure 1 shows, those pins are

11-166 APPLICATION NOTES

also used to separate the analog and digitai signals.

MEMORY 8SYSTEM

INTERFACE

TIMING

GENERATOR

Figure 1. "Flow Chart" Layout for Logical Separation of
Functions.
This design approach may seem unnecessarily rigorous
and time-consuming but can prove rewarding when the
p-c board is installed in its final system location.
Locate the timing circuits near the center of the board
(Figure 1) because the timing is at the heart of the circuit,
being connected to all of the major circuit components
of the board. A central location helps assure minimum
paths for the digital signals.
Variations of this theme may not use the exact same
components or functions, but the same basic techniques
should be applied in any design containing analog and
digital circuits. For cards with all connections at one end,
avoid configurations which have analog circuits near the
p-c connector, and digital signals at the opposite end of
the card-or vice versa; either situation will cause analog and digital paths to pass in close proximity to one
another.
SYSTEM GROUNDING
Although local ties for analog and digital grounds help
the performance of a card, they can cause problems for
the system designer using ADCs and DACs. In systems,
data converters should be considered as analog (not
digital) components; the system design must be assigned to experienced and capable analog engineers,
who are used to defending millivolt signals against
interference.

Place ADCs and DACs (like other analog devices) near
other parts of the analog section, because: (1) reflections
make it hard to transmit analog signals more than a
short distance without loss of bandwidth and amplitude;
and (2) noise generated by the digital section can couple
into the analog through the ground plane or power supplies, or radiate to nearby analog components.
Each card in the system should be returned directly to
the power supply common, using heavy wire. Where it
is mandatory that a card's analog and digital grounds be
separated, each should be separately returned to the
power supply; don't connect the two grounds and return
a single ground line to the power supply.
REV. A

POWER SUPPLIES

ABOUT Ie DESIGNS

Besides ground rules, designers of high-speed circuits
must also consider the rules about power supplies to
obtain best results.

There is often a difference in implementing designs
using high-precision IC circuits vis-a-vis p-c card designs
using modules or hybrids. Some ICs are specifically designed to keep analog and digital grounds separated
within the device, because they would be unable to perform their functions properly without the separation.

Every power-supply line leading into a high-speed p-c
card or data-acquisition circuit must be carefully
bypassed to its ground return to prevent noise from
entering the card. Ceramic capacitors, ranging in value
from 0.01 to 0.1 fLF, should be used generously in the
layout, mounted as closely as possible to the device or
circuit being bypassed; and at least one good-quality
tantalum capacitor of 3 to 20 fLF should be assigned to
each power-supply voltage, mounted as near as possible to the incoming power pins to keep potentially high
levels of low-frequency ripple off the card.
To some extent, the p-c's power-supply connector pins
can introduce noise problems. If their contact resistance
is sufficiently high, and a varying current is flowing, the
varying IR drop which results is noise and can be coupled into parts of the card. This caution applies especially to +5-volt supplies used to power TTL systems,
but the problem can be alleviated with a variation of the
rule about multiple pins for making ground connections.
Parallel the I-R drops by also using multiple pins for
power connections.

Recognizing this, IC manufacturers are generally very
careful in detailing how to obtain optimum performance
from their devices. Those details of the application notes
frequently instruct the user to connect analog and digital
grounds for the device together externally; when they
do, the connection needs to be made as closely as possible to the device. In other, much rarer, instances, the
characteristics of an individual device-or system-may
require some remote connection of the grounds.
The best approach for getting optimum performance
from any device is to follow diligently the recommendations of the manufacturer. If the recommendations are
missing or vague, ask for them.
Logical signal flow generates logical treatment of
ground paths and ground connections- a logical way to
prevent potential problems.

Low-noise, low-ripple temperature-stable linear power
supplies are the preferred choices for high-speed circuits. Switching power supplies often seem to meet
those criteria, including ripple specifications. But ripple
specs are generalJy expressed in terms of rms-and the
spikes generated in switchers may often produce hardto-filter, uncontrollable noise peaks with amplitudes of
several hundred millivolts. Their high-frequency components may be extremely difficult to keep out of the
ground system.
If switchers cannot be avoided for high-speed designs,
they should be carefully shielded and located as far
away from the "action" as possible, and their outputs
should be filtered heavily.

•
APPLICATION NOTES 11-167

11-168 APPLICATION NOTES

AN·215A
APPLICATION NOTE

11IIIIIIII ANALOG
WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062·9106 • 6171329-4700

Designer's Guide to Flash·ADC Testing
Part 1
Flash ADCs Provide the Basis for High Speed Conversion
by Walt Kester

Building high-performance circuits that take advantage of the high sampling rates offlash ADCs requires
a krwwledge of these converters' many intricacies. Part
1 of this 3-part series discusses the pitfalls of designing
with flash ADCs, how to evaluate certain data-sheet
specifications, and how to choose external components
that complerrumt your particular converter. Parts 2
and 3 will explore test and measurement methods that
you can use to verify a converter's performance in
your system.

Walt Kester, Computer Labs Div,
Analog Devices
To digitize analog signals whose bandwidths exceed 1
MHz, you'll probably need flash ADCs. Many flash
converters with 4 to 10 bits of resolution are now available, thanks to recent advances in VLSI process technology and design techniques. However, to use these
converters successfully at the high sampling rates that
they provide, you must take into account and compensate for a variety of flash-converter characteristics.
The basic features of most flash converters are
shown in Fig 1. A flash ADC simultaneously applies
an analog-input signal to 2N - 1 latched comparators,
where N is the number of the converter's output bits.
A resistive voltage divider generates each comparator's reference voltage and sets each reference level 1

LSB higher than the level of the comparator immediately below it. Comparators that have a reference voltage below the input-signal level will assume a logic 1.
The comparators with a reference voltage above the
level of the input signal will produce a logic O. A secondary logic stage decodes the thermometer code that
results from the 2N - 1 comparisons. An optional output
register latches the decoding stage's digital output for
one clock cycle.
Timing is everything
One of the first difficulties you'll encounter when
using flash converters is removing valid data from the
converter. In practice, the comparator bank has two
states controlled by a conversion-command signal.
Various converters call this command the convert, the
encode, or simply the clock command. When this signal
is in its convert-command state, the comparators track
the analog-input signal, and during this time the output
data is invalid. When the command line changes state,
it latches the comparator outputs. Valid output data
is now available for transfer to an external register.
You'll find most flash converters somewhat sensitive
to the duty cycle and frequency of this command pulse.
In other words, the performance of the converter, specifically its differential and integral nonlinearity performance, is related to the clock's duty cycle and frequency. Performance degradation is especially pronounced when you run the device at or near its maximum sampling rate.

Reprinted from EDN, January 4, 1990.

APPLICATION NOTES 11-169

III

Because of recent advances in VLSI processing and design techniques many.flash converters that have from 4 to 10 bits ofresolutum are available.
J

output directly to a backplane data bus through a cardedge connector, signal coupling between the digitaloutput signals and analog input will degrade the SIN
ratio and harmonic performance.
In many high-speed data-acquisition designs, you'll
need a large and fast buffer memory to store the output
data. A 500M-sample/sec converter can fill 1M byte of
memory in 2 msec. To reduce the required speed-and
thus the cost-of the memory, you can demultiplex the
high-speed data stream (Fig 2), which slows it to frequencies compatible with cost-efficient CMOS RAMs.
Fig 2's circuit clocks the two output registers at half
the sample rate, and it latches data in each register
180x out of phase from the other. Some flash converters
that operate in excess of 200 MHz have onboard demultiplexing for added convenience.

The way you handle the binary output depends on
whether the converter has an internal output latch.
Without a latch, the data will be invalid for a period
equal to the sampling clock's pulse width. At high sample rates, the data-invalid time will impinge on the
data-valid time, making it difficult for you to strobe
the flash converter's output into an external register.
For instance, if you operate a flash converter at 100M
samples/sec with a 5O%-duty-cycle sampling clock, the
output data will be valid for only 5 nsec. When you
consider the finite rise and fall time of the output binary bits, this short time doesn't leave you much leeway, even if you use the fastest external logic. In fact,
you may ultimately lose data. The addition of an internal output latch simplifies clocking of the output data,
because the output data is valid for approximately the
entire clock cycle. In return for a longer data-valid
time, you'll have to accept an inherent 1-cycle or more
pipeline delay-an acceptable compromise in most systems applications.
Try to place an appropriate buffer register next to
the flash converter. If you route the converter's digital

All that sparkles isn't gold
So far, these timing difficulties refer to how you
deal with the converter's output data. But flash converters can have internal problems as well. Low input
frequencies can cause comparator metastability, and

o

·: .
•

•

I
I •

II •
I

DECODE
LOGIC

v,

OUTPUT
N

~=

N

BINARY
OUTPUT

v,
Fig l-FllIIlh converters contain a bank of
tN -1 comparators, 'Where N u. the number
of output bits. Decoding logic transforms the
comparator outputs into the appropriate Nbit result. Timing and input characteristics
of the converter, such as mismatched comparator detays, mismatched ladder resistors,
and rnmlinear input capacitances, are just
a few sources of converter errors.

11-170 APPLICATION NOTES

V,

,VREF

SAMPLING CLOCK

NOTE: WHEN Va < ANALOG INPUT < Vo. THE
COMPARAlOR OUTPUTS WILL BE AS SHOWN.

when t:s;O. T equals the regeneration-time constant,
and t is the time after the application of a latch command. The probability of a metastable state, Pm, for a
regenerative comparator bank driving decoding logic is

high input frequencies can lead to errors caused by
slew-rate and delay mismatches. All of these errors
may manifest themselves as sparkle codes in a poorly
designed flash converter.
Sparkle codes are random errors whose magnitude
may approach the full-scale range of the converter.
The term refers to the white dots or "sparkles" that
appear against a gray background when the ADC output drives a video display. There are two sources of
sparkle codes: comparator metastable states and thermometer-code bubbles.
A comparator metastable state occurs if the comparator output falls between the logic-O and logic-l
threshold of the digital decoding logic. If the threshold
uncertainty region has a width of AVL and the comparator has a gain of A, then the error probability Pm is a
uniformly distributed value that's equal to

P =AVLe-U<
m

.

The magnitude of the sparkle code depends on the
location of the metastable comparator in the comparator bank and on the logic-decoding scheme. For instance, the 128th comparator determines the MSB of
an 8-bit flash converter with straight binary decoding
logic. If this comparator's output is in a metastable
state, the decoding logic may mistakenly convert the
input voltage whose correct binary representation is
01111111 to 11111111, producing a full-scale error. If
the comparator bank's thermometer-code output is first
decoded into Gray code, latched, and then converted
into binary code, the metastable error is reduced to 1
LSB, regardless of the comparator in error. Flash converters, however, rarely use this scheme because of
the ripple-through time and the increased logic density
of the Gray-to-binary circuitry. Instead, converter designers often use "pseudo-Gray" decoding techniques
to eliminate the delay time associated with traditional
Gray-to-binary circuits.
Note that the probability of a metastable-state error
increases as the time-after-latch, t, decreases (assum-

P =AVL
m

Aoq

Aq'

where q is the weight of the LSB.
A latched comparator in a flash converter has a regenerative gain of

when t>O, and
A=Ao

REGISTER I

ANALOO
INPUT

FLASH
IW

CONVERTER

II

HIGH-SPEED
REGISTER

I,

REGISTER 2

Fig 2-FlGsh converters can opemte at extrlJmely high sample rates. Thus, you must
have an output regi8ter that can handle this
fast data. By demultiplexing the converter's
outputs, you can slaw the data to a rate that's
compatible with standard CMOS memory.

APPLICATION NOTES 11-171

One of the first difficulties you~ll encounter
when using flash converters is removing
valid data from the converter.

ing a constant value of T). This implies that the flash
converter is more apt to produce metastable-state errors as you increase the sampling rate, because t must
decrease correspondingly. Most manufacturers reduce
metastable comparator states by minimizing the regeneration-time constant, T. Lower regeneration-time constants result in higher power dissipation, which is one
reason why many high-speed flash converters are
power-hungry devices.
Thermometer-eode bubbles are another potential
source of sparkle codes. A well-behaved flash converter's comparator bank produces a specific sequence
of ones up to a certain point in the input range of the
converter, and it produces a sequence of zeros beyond
that point. The decoding logic then assigns a binary
number to the thermometer code. For low-frequency
inputs, most flash converters' comparator banks are
well behaved. At high speeds, however, delay mismatches among comparators may produce out-of-sequence ones and zeros in the thermometer code. The
decoding logic then assigns an error binary code to
these out-of-sequence points, or bubbles, which also
result in sparkle codes. Again, proper comparator design and more sophisticated decoding-logic circuitry
16

,.

98

~A09617tSTORTION (dB)
86

I"'-

7.

12

10

"'f'

A09060

NUMBER

OF BITS

62

I'

rAOJ:t--

EFFECT1VE

50

AO~OO6

1"\1"- 1\
~

f'

SIN RATIO
(dB)

...

26

"
100

1000

INPUT fREQUENCY (MHz)

(BI]]l)

MAXIMUM
SAMPLING RATE
(M SAMPLESISEC)

TEST
SAMPLING RATE
(M SAMPLESISEC)

'0
8
6

75
300

60
250

500

400

RESOLUTION

FVSHADC
A09060
AD9028

AIl9OO6

Fig ;J-TheoretkaU,I. II Ikuh con"erter should maintain ibJ perf'ormanee acros. the full Nyquist bandwidth. But a. the curve. in

this figure illustrate, the SIN ratio .tart, to degrade well belCYW each
/Uviee', marimum sampling rate. (Note that theBe curves are based
on test sampling rates that a,.. somewhat lower than each device's
marimum possible rate.)

11-172 APPLICATION NOTES

SIN ratio=6.02N+1.76 dB.

However, as shown in a typical plot of SIN ratio
versus input frequency for actual flash converters (Fig
3), the SIN ratio degrades as the input frequency increases. This degradation starts well below these converters' maximum sampling rates. The left vertical axis
of Fig 3 shows the SIN ratio in another term: effective
number of bits. The effective number of bits is simply
the value of N when you solve the above equation using
a specific value for the SIN ratio. Aperture jitter (sample-to-sample variations in the effective-sampling instant) can also cause degradation in the overall SIN
ratio for high-slew-rate inputs. Jitter can be internal
or external to the converter. Part 3 of this series will
cover this topic in more detail. To minimize externally
produced jitter components, you should always practice
proper grounding, power-supply-decoupling, and pCe
board-layout techniques.

38

2

10

within the ADC itself can reduce these errors to acceptable levels.
These comparator-timing errors degrade both the
differential and integral linearity of a flash ADC as the
input slew rate increases. In addition to static errors,
such as missing codes and sparkle-eode errors, slewrate limitations manifest themselves as dynamic errors,
such as increased harmonic distortion and degradation
in the SIN ratio. Ideally, a flash converter should maintain its static performance specifications across the full
Nyquist bandwidth, and certain applications demand
full performance beyond the Nyquist bandwidth. The
theoretical, rms SIN ratio for an N-bit ADC is given
by the well-known equation

Watch for dangerous data-sheet territory
Most of the timing difficulties and error soorces discussed so far are common to all flash converters. However, each converter features its own unique design
and specifications; thus the data sheets require scrutiny. Don't be fooled into believing that sampling rate
and input bandwidth are interchangeable; they're different specifications. It wasn't until recently that you'd
even find input bandwidth specified for an ADC. Even
now. no accepted industry-wide definition exists for a
flash converter's full-power-bandwidth specification.
Scrutinize the data sheet carefully and make sure you
understand the manufacturer's definition and test
method. The full-power bandwidth of a traditional op
amp is the maximum frequency at which the amplifier

can produce the specified p-p output voltage at a specified level of distortion. Another commonly used definition calculates the full-power bandwidth by dividing
the amplifier's slew rate by 2'1rV o, where the outputvoltage range of the amplifier is ± Vo.
When you apply traditional analog-bandwidth definitions to flash converters, the results can be misleading.
The dynamic-error sources previously discussed may
become predominant long before the comparator front
end approaches its maximum bandwidth. If you use a
common definition of full-power bandwidth as the frequency at which the p-p reconstructed-sine-wave output is reduced by 3 dB for a full-scale input, then the
effective number of bits (SIN ratio) at this input frequency may render the flash converter useless in your
system. Thus, to get a true idea of a converter's performance, you must consider both the full-power bandwidth and the effective number of bits (SIN ratio) at
a specific sampling rate.
Another definition you'll encounter occasionally for
full-power bandwidth is the maximum, full-scale input
signal at a specified sampling rate that produces no
missing codes. Using this definition always gives the
most pessimistic number, so specifications based on
this definition appear on only a few data sheets. The
following is a recently proposed definition for fullpower bandwidth (courtesy Chris Manglesdorf, a senior scientist at Analog Devices): the frequency at which
the fundamental component of the reconstructed FFT
output-excluding harmonics-is reduced by 3 dB from
full scale.
Just when you think you've mastered the intricacies
of flash ADCs, you'll realize that you have another
component to worry about: the input buffer amplifier.

Fortunately (or unfortunately depending upon your
perspective), the flash converter-not the amplifierusually limits the converter's dynamic performance.
A flash converter typically digitizes a signal from a
50, 75, or 930 bipolar or unipolar source. If the input
range of the flash converter is incompatible with the
signal, then you'll clearly need a wideband op amp to
generate the required gain and offset (Fig 4). In addition, the input capacitance of some flash converters
may vary as a function of the analog input's signal
amplitude. Therefore, so that the nonlinear capacitance
doesn't produce undesirable harmonics in the digitized
signal, you'll need to use a buffer amplifier for isolation.
For certain flash converters, the input capacitance is
so high that a buffer amplifier is needed just to preserve the signal bandwidth.
A good choice for the buffer is a high-speed transimpedance amplifier. These amplifiers have high bandwidths and flat frequency responses over a broad range
of input frequencies. Also, many transimpedance amplifiers exhibit extremely low distortion. Pairing the
right amplifier with your converter is important. For
instance, Fig 3 shows the SIN ratio of various converters plotted along with the harmonic distortion of the
AD9617. Since the THD of the amplifier is better than
the SIN ratio of the converters, the amplifier won't
degrade the flash converters' performance over the
major portion of their usable bandwidth.
Another factor to consider when driving the input
of flash converters is the input-signal polarity. Positive
input signals, which forward bias the substrate diode,
can damage a converter that has a unipolar, negative
input-voltage range. Installing an external Schottky
diode provides effective protection.

II

OFFSET ADJUST

+v

·v

A,

Fig 4-1f the voltage mnge of the alllJlDg
Bignal and the input range of the ADC aren't
compatible, you'll have to adjust the gain
using R, and R, and also adjust the input
signal's offset. Because of the substantial
value and the often nonlinear nature of a
flash converter's input capacitance, you
must choose an aP'fJ1"01Yl"iate drive amplifier
and value for Rs.

FLASH CONVERTER

I
APPLICATION NOTES 11-173

Ideally, a flash converter should maintain
its static-performance specifu:ations across
the full Nyquist bandwidth, but in reality
ADCs fall far short of this ideal.
The flash converter's input capacitance and the drive
amplifier's isolation resistor, Rs, form a lowpass filter.
Typical series-resistor and input-capacitance values of
100 and 20 pF create a single-pole lowpass filter that
has a bandwidth of 800 MHz. However, if the input
capacitance changes from 20 to 15 pF over the input
range of the converter, then an attenuation error of
1.4% occurs for a 50-MHz input signal. This 1.4% nonlinearity will produce 37 dBc of harmonics. (The unit
dBc refers to the number of dB between ,the signal
you're measuring and the carrier frequency). If you
minimize the value of Rs and still maintain op-amp
stability, you can reduce the attenuation error caused
by these lowpass filtering effects. The signal dependence of input capacitance is rarely specified, but as
converters move toward higher bandwidths, you can
expect to see this parameter on more data sheets.
Few, if any, flash converters contain an internal voltage reference, so in addition to an external drive amplifier, you must also design your own voltage-reference
generator. Fig 5 illustrates a typical -2V, unipolar
reference-voltage circuit for a flash converter. A buffer
transistor is necessary because the resistance of the
converter's ladder string is usually fairly low. The total
reference-ladder resistance of a flash converter depends heavily on the fabrication process and may vary
considerably from device to device. Also, the ladder's
resistance may exhibit a large temperature coefficient.

If the flash converter allows bipolar operation, then
you'll have to generate two reference voltages. The
circuit in Fig 6 allows great flexibility in setting both
the gain and the offset of a bipolar flash converter,
and it operates on ± 5V power supplies. A few flash
converters provide a sense pin for the voltage reference. You can use this pin to compensate for the voltage drop caused by the package's pin and bond-wire
resistances, as shown in the bipolar-reference circuit
in Fig 6. In addition, some ADCs give you access to
one or more taps along the internal, reference-ladder
resistor string. To achieve better integral linearity,
you can drive these taps from low-impedance sources.
Improve dynamics with TIH amplifiers
As previously discussed, the effective-sample timedelay variations among the latched comparators degrade the SIN ratio and the harmonic performance.
You can visualize the individual comparators within
an array as having variable delay lines in series with
their latch-strobe inputs. To understand the effect of
this delay on performance, consider an 8-bit, l00Msample/sec flash converter that's digitizing a full-scale,
50-MHz sine-wave input. You can express the sine
wave as
v(t)= VpSin21Tft.

FLASH
ND CONVERTER

GAIN
ADJUST

2.7k
1k

10
5V

2,5V

REFERENCE
LADDER

3,9k

220
2N-3906

33pF
AD580

I

10

-5,2V

Fig S-FIDBh converiera don't have inte17llJ1 refererree.,
-l!V reference for a unipolar converter,

11-174 APPLICATION NOTES

80

yoo must design them externally, This particular circuit provides a stable

To improve flash-converter performance at
sampling rates as high as 25 MHz, you
can use front-end T/H amplifters to implement a "track-and-slow-down" approach.
be digitizing a dc input. In actual practice, T/H amplifiers aren't ideal, especially at high speeds. The signal
presented to the flash converter is still changing, although at a slower rate. Nevertheless, this "track-andslow-down" approach can improve the flash-converter
performance at sampling rates as high as approximately 25 MHz. At sampiing rates above 25 MHz, the
T/H circuit needs to be mounted on the same substrate
as the flash converter in a suitable hybrid package.
Monolithic T/H amplifiers in hybrid packages with 8-bit
flash converters have successfully achieved 7 effective
bits at Nyquist inputs and at sampling rates of 250
MHz. These hybrid packages exact a penalty of higher
cost and power consumption, however.
You'll find it difficult to select an appropriate discrete T/H amplifier, because the interaction between
the T/H amplifier and the flash ADC is hard to predict.
You should evaluate key T/H amplifier specifications
such as acquisition time, full-power bandwidth, slew
rate, and harmonic distortion. Harmonic-distortion
specifications typically are provided for the track mode.
The T/H amplifier's performance may be considerably

The maximum rate-of-change of this signal occurs at
the zero-crossing point and is equal to
dvl
=27TfY =avl
dt max
. P at max.
By solving this equation for atma" you obtain

If the input-voltage range of the flash converter is 2V,
or VP = 1V, then the LSB weight is 8 mV for an 8-bit
ADC. For the flash converter's error to be less than
1 LSB, atmax must equal 25 psec. The effective-sample
delay mismatch between comparators can't exceed this
value. If the mismatch is greater, a 50-MHz, full-scale
sine-wave input will produce missing codes in the converter's output.
Placing an ideal track-and-hold (T/H) amplifier ahead
of the flash converter theoretically would eliminate this
problem, because the flash converter basically would

sv

sv
sv

10

V REF

ADJUST
Sk>-O----i

220
2N·3904

2.SV

-5.2V

SENSE

3.9k

-=

FLASH ADC

10
REFERENCE
LADDER

ADSBO
SENSE

-=
-=-

SV
10

3.9k

Rs

220

SV

2N·3906
Sk

V REF
ADJUST
·2.SV

-=-

·S.2V

·S.2V

10

-=sv

Fig 6-Thill referenu generator frY/' a IJipolar flash converter uses the sense pins provi.ckd by the resistor ladder to compensate frY/' the
voltage drops in the package's pin and bond-wire resistances.

APPLICATION NOTES 11-175

II

worse than the stated specifications when the amplifier
is in the hold mode and actually driving a flash converter. Also, the loading effects of the converter may
degrade the T/H amplifier's performance. In addition,
obtaining the optimum relationship between the various timing pulses that drive the T/H amplifier and the
flash converter may require considerable experimentation.
Because of these many difficulties, the current goal
of many ADC manufacturers is either to provide flash
converters whose dynamic performance. is acceptable
without a TIH function, or to integrate the T/H function
and converter on the same chip. In either case, manufacturers can fully specify the ADC for dynamic performance and spare you the somewhat difficult design
problems associated with interfacing the TIH amplifier
to the converter.

11-176 APPLICATION NOTES

The knowledge of internal ADG features and the
requirements these ADCs place on external circuits
should guide your initial design efforts. But once you
finish the design and build your circuit, you'll want to
ensure that the combined performance of your converter and its support circuits meets your requirements. Part 2 will discuss various DSP-based test
methods that are particularly effective in flash-converter testing.
EDII

Reference
1. Sheingold, Dan, Analog-Digiml Conversion Handbook
3rd ed, Prentice-Hall, Englewood Cliffs, NJ, 1986.
'

AN·2158
APPLICATION NOTE

11IIIIIIII ANALOG
WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 6171329-4700

Designer's Guide to Flash-ADC Testing

Part 2
DSP Test Techniques Keep Flash ADCs in Check
by Walt Kester

By testing your flash AID converter, you can ensure
that it's faithful to all the specifications listed on its
data sheet. Part 2 of this 3-part series presents a number of methods, including sine-wave curve fitting and
the FFT, that you can use to test flash converters.
Readily available benchtop instruments or personal
computers are the only equipment that you'll need to
use these methods.

Walt Kester, Computer Labs Div,
Analog Devices
It's important to know how your flash AID converter
will perform in real-world applications. Therefore, you
may want to perform anyone of a variety of tests on
your converter to determine its deviation from ideal
performance. As Part 1 of this series discussed, flash
ADCs exhibit errors due to static and dynamic nonlinearities, and these errors increase as the input signal's slew rate increases. Thus, the actual SIN ratio
will fall short of the converter's theoretical value. Even
if you don't apply these tests yourself, becoming familiar with them will help you evaluate data-sheet specifications more accurately, because many manufacturers
use these same methods.
Another reason you may want to test your flash
converter is to gain information that the manufacturer
doesn't provide. Specifications such as SIN ratio and
its related effective number of bits are key in all applications and are normally specified, but other specifications that are more important for your particular application may not be included on the data sheet. For
Reprinted from EON, January 18, 1990.

example, video designs typically require that you know
a converter's differential phase and gain (Ref 1). Communications systems may even depend on esoteric
specifications such as the spurious-free dynamic range,
which isn't available on many data sheets.
For a full-scale sine-wave input, the theoretical rmssignal to rms-quantization noise ratio is
SIN RATIO=6.02N+1.76 dB,

where N equals the number of bits (Ref 2). The rms
quantization-noise voltage for an ideal ADC within the
Nyquist bandwidth is qlV12, where q is the weight
of the LSB expressed in volts.
The most popular method for extracting a flash converter's SIN ratio And effective number of bits is
through discrete Fourier transforms (DFTs). Today,
you can perform sophisticated DSP tests with PCbased test systems and standard software packages.
The test system in Fig 1, for example, can execute a
l024-point FFT in less than one second. Most of the
hardware you'll need is available as plug-in boards for
the PC. However, you'll have to do a fair amount of
work before you can begin to use a PC-based test
system. First, you'll need to design a high-speed
buffer-memory board to capture the data from the flash
ADC. Typically, you'll need to use high-speed static
CMOS or ECL RAMs. Second, plan to design an appropriate logic interface to connect this buffer memory
to the digital I/O rard of the PC.
Another hardware feature you might consider is an
evaluation board, which certain manufacturers of
video-speed ADCs supply to ease design testing. Many
evaluation boards contain reference voltages, powersupply decoupling, timing circuits, output registers,
and connectors. The evaluation boards usually have a
APPLICATION NOTES 11-177

II

DSP test techniques determine your converter's deviation from ideal performance,
and they even tell you certain speclfu;ations
that the ADC's data sheet doesn't.
matching reconstruction DAC. In most cases, the
manufacturer has optimized the design of these boards
so that your ADC test won't be corrupted by faulty
or poorly designed support circuits.
Your software must include a program to capture
the data and then load it into the memory of the PC.
If you plan to use FFT analysis, you must link a stan:~
dard FFT software package to your test program. You
may also have to generate a look-up table to store any
special. weighting functions required by your particular
sampling scheme. Also, adding a coprocessor card will
speed up the thousands of multiplications that FFTbased analysis requires.
If you don't have the time or the energy to build
your own test system, consider one of the benchtop
instruments available from a number of instrumentation manufacturers. These turnkey systems typically
utilize a high-speed logic analyzer to capture data. Because menu-driven software allows you to select from
a variety of tests, you incur practically no hardware
or software development time.
To test a flash ADC using Fourier analysis, you
must apply a spectrally pure sine wave to the converter
and store a number of contiguous output data samples.
Then, using DFT techniques, your test program calculates the rms-signal and rms-noise content and determines the ratio of the two. Noise calculations using
DFT techniques include not only the converter's quantization noise but also the harmonics of the input sine
wave. In addition, harmonics that fall outside the

Nyquist bandwidth are aliased back into the Nyquist
bandwidth because of the sampling process. Thus, to
achieve accurate and repeatable results, the purity of
the sampling clock and the input sine wave is critical.
You can use either coherent or noncoherent sampling
to evaluate the ADC performance. Coherent sampling
simply means that your record of samples contains an
integer number of sine-wave input cycles. Alternatively, noncoherent sampling produces a record that
contains noninteger multiples of the input. You must
choose between these sampling schemes based on the
type of input data you expect. Coherent testing is more
suited to a laboratory environment when you know
the precise frequency content of an input signal, and
it requires careful attention in the selection of the input
and sampling frequencies. Noncoherent testing yields
a better representation of ADC performance in a realworld application such as spectral analysis, because
the precise frequency content of the signal being digitized is a mystery.
However, whenever the number of time samples
doesn't contain an integer number of input cycles (noncoherent testing), you'll have to time-weight the samples to reduce frequency side lobes. Without weighting, discontinuities will cause the main lobe's energythe fundamental-to leak into many other frequency
bins. The term "bins" refers to the spaces between
spectral lines or spectral peaks. The number of bins
for a particular spectrum equals the sampling fre-

r-----------------------------------------------,

Fig I-This nsp test system for a flash
ADC can execute a 1021"point FFT in less
than one ...cond, but the system requires a
significant design effm- Hardware require·
ments include a high·speed buffer memory
and logic interface between th.is memory and
you.r PC. Software requirements include a
program to capture the data and load it into
the mer/wry of the PC, as well as a link
between your test program and a standard
FFT .•q(f:ware package_

11-178 APPLICATION NOTES

.--

PROGRAMMABLE

--

SAMPLING-CLOCK

ANALOO-SIGNAL
SOURCE

t-------o

f------>

AID
CONVERTER

r----

BUFFER
MEMORY

Is
PROGRAMMABLE
GENERATOR

,
NOTE: TEST-SYSTEM HARDWARE
AND SOFTWARE CONSISTS OF:
AT&T PC-6300 PC
8087 COPROCESSOR.
20M BYTE STORAGE
METROBYTE PIQ-12, 24·81T
PARALLEL INTERFACE CARD
MICROSOFT QUICKBASIC
OPERATING SOFTWARE
MICROWAY 87 FFT SOFTWARE

PRINTER
DISPLAY

PLOTTER

~wI-

INTERFACE
CARD
(PARALLEL)

INTERFACE
CARD
(IEEE-488)

PERSONAL
COMPUTER

DSP
SOFTWARE.

quency divided by the record length, or fs/M. The leakage of the signal from the central bin to side-lobe bins
makes accurate spectral measurements impossibleyou simply can't distinguish the frequency bins that
contain actual signal information from those that contain noise. Another reason to time-weight the samples
is that the end user of your AID-conversion system
may be interested in the performance of the ADC using
an identical or similar window.
Noncoherent sampling involves fewer input- and
sampling-frequency restrictions than coherent sampling does, but it requires careful attention in the selection and use of the weighting function. Also, to prevent
masking out harmonics of the fundamental, avoid using
inputs that are integer submultiples of the sampling
frequency. If your input frequency is an integer
submultiple of the sampling frequency, the quantization noise, qlV12, will be concentrated in the harmonics of the input frequency rather than uniformly distrib-

Wn",OS-O.5cos

(a)

CONTINUOUS
FOURIER
TRANSFORMATION

[¥lJ

M.>t

BINS FROM

SIDE-LOBE

F.~NJ?~MENTM

ATT~I:'J~~-r:19NJ9J3J

2.5
5.0
10.0
20.0

50
68
86

32

(b)

Fig 2-When the record of samples doesn't contain an integer
number of input cgcles-that is, when you're using noncoherent
sampling-you must precondition the data with a weighting function. The Hanning window shown here in the time domain (a) and
the sampled-frequency domain (b) is a popular weighting function.

uted across the Nyquist bandwidth. Ultimately, this
condition leads to incorrect harmonic-distortion test results.
One popular weighting function is the Hanning window (Ref 3), which is described by the equation
27Tn) '
Wn =0.5-0.5 cos ( M

where Wn is the weighting coefficient for the nth data
sample, and M is the total number of samples. Fig 2
graphically depicts the Hanning window in both the
time and the frequency domains.
To calculate the SIN ratio, you have to decide the
number of frequency bins to include in the fundamental
and the number of bins to consider as noise. As Fig 2
shows, you can correlate the amount of side-lobe attenuation with the lobe's distance, in terms of bins,
from the fundamental bin. Fig 2b includes a table that
lists some of these values. You'll have to make your
decision based on the theoretical SIN ratio of the converter you're testing.
For example, an 8-bit converter has a theoretical,
maximum SIN ratio of approximately 50 dB. In order
to ensure that the side-lobe energy doesn't cause an
artificially high noise measurement (and hence an artificially low SIN-ratio measurement), you should include
at least 10 frequency bins on either side of the fundamental when calculating the signal level. (Simply take
the square root of the sum of the squares of all 21 bins
as your signal level.) Now, any side-lobe energy outside this region will be at least 68 dB below the fundamental signal level (18 dB below the theoretical, 8-bit
quantization noise floor of 50 dB), and side-lobe leakage
won't significantly affect the accuracy of your SIN-ratio
measurement.
Other weighting functions may better suit your ap- . . . .
plication. For example, Fig 3 compares the popular . .
Hanning window's spectral representation with the
more sophisticated, minimum 4-term, Blackman-Harris
type. For the same record length, the Blackman-Harris
window provides better spectral resolution than the
Hanning window, making it more suitable for critical
spectral analysis, such as measuring 2-tone, third-order
intermodulation-distortion products. The extra computations for the Blackman-Harris window don't lengthen
processing time, because you calculate them only once
and store them in a look-up table.
As previously stated, you can use coherent sampling
if you know the characteristics of your input signal and
if you choose the sampling rate accordingly. Coherent
APPLICATION NOTES 11-179

Today, you can perform sophisticated DSP
tests with PC-based test systems and standard software packages.
sampling eliminates leakage and the need for windowing (Ref 4); the spectral result of a coherently sampled
signal is simply a single-frequency peak. Certain restrictions apply to the choice of the sampling rate and
the sine-wave frequency, however. First, you must
observe the following ratio:

fi. Me

fs=1f'

Me equals the number of integer cycles of the sine
wave during the record period. For a whole number
of cycles, Me must be an integer. To ensure that you
don't take repetitive data, Me should also be a prime
number: 1, 3, 5, 7, 11, 13, 17, etc. By using prime
numbers, you ensure that all samples during the record
period are unique. When using coherent sampling, it's
mandatory that the ratio MdM be constant. This requirement implies that you derive fs and fin from two
locked frequency synthesizers.
HANNING WlNDO\N
M..,1024
Wft=0.5-0.5cos

r~nj

Calculate the DFT
After selecting the record length and determining
the weighting function (for noncoherent sampling), you
must write your DFT test program. Your program
must find the DFT of the sequence of weighted data
samples for M/2 frequencies (the Nyquist frequency).
Thus, the program should solve the following two equations for the kth frequency:

-1. ~ W••
D cos [21Tk(n-1)]
Ak-M.t:J
M
n=1

=1. ~ Wnn
D sm
. [21Tk(n-1)]
BkM.t:J
M
.
n=1

In these equations, Ak and Bk represent the magnitudes of the cosine and sine parts of the kth spectral
line; n is the number of time samples; Wn is the weighting function; Dn is the amplitude of the time-function
data point; and k is the number of a spectral line. The
total magnitUde of the kth spectral line is

~

~ -ro~-------------------

~
~

-1401.-_______. .
256

-256
FREQUENCY BINS (n)
(a)

MINIMUM 4-TERM
BLACKMAN·HARRIS WINDOW
M ..1Q24
Wn=ao-8,COS

r~~J

+

a~os P~~~l-a,cos r?-1!~~~

i
~

-92

1

1--------------------:
80=0.35875
a, =0.48829

~

82=0.14128

83=OD1168

-129
(h)

128

256

FAEaUENCV BINS (n)

Fig ~The Blackman-Harrill windowing function (II) resolves
closer peaks in a frequency spectrum than does the Hanning window
(a). The mathematical expre8sionfor the Blackman-Harris window
is more complex, but you only need to calculate the term8 once and
then store them in a look-up table.

11-180 APPLICATION NOTES

The program's results yield M/2 components, which
are the frequency-domain representation of the M time
samples. The resolution or spacing between the spectral lines, af, equals fslM and is the bin size or bin
width.
Typically, you should select the number of time samples (M) to be between 256 and 4096, depending on
the desired resolution and the size of the buffer memory. M must be equal to an integer that's a power of
two. If you're using noncoherent sampling, you can
compress leakage around the main lobe by' using a
larger record length, thereby leaving a larger percentage of the Nyquist spectrum uncontaminated. For example, the Hanning weighting leakage is ± 10 bins
from the fundamental for 68-dB side-lobe suppression.
If the record length is 256, then the leaky fundamental
occupies 20 bins out of 128 spectral components, or 16%
of the digital spectrum. When M equals 1024, the percentage reduces to 20/512, or 4%.
In practice, you can use one of the many FFT algorithms to simplify and speed the DFT calculations (Ref
5). An FFT algorithm will produce the same results
as the DFT equations above, and the computation time
is much faster.

The discrete Fourier transform is the most
popular method for determining a converter's true SjN ratio and effective number of bits.
Verify the FFT
Consider the noise floor when verifying the FFT.
Assuming that the round-off error contributed by the
DSP-noise calculation (the error caused by using a finite number of bits in the FFT multiplications and
additions) is negligible, the rms-signal to rms-noise
level in a single frequency bin of width .if is
SIN RATIOFFT =6.02N+1.76 dB+I0 LOG lo

(~).

This equation represents the FFT noise floor. You
should choose M so that any spurious components you
want to resolve lie at least 10 dB above this floor.
Basic software can easily.generate an ideal N-bit
sine wave by using the Integer (lNT) function to truncate the value to the proper resolution. For instance,
an input signal of frequency fin is equal to

where n is the nth time sample for an ADC that has
infinite resolution. You can calculate the corresponding
quantized value using

2'7T£)
( Vo Si~ fa
,

where q = 2VoI2N. Substituting this expression for q
in the above equation yields
Vq(n)=INT [2N- 1 sin (2'7:fin )

EFFECTIVE _
(~)
NUMBER OF BITS - N - LOG2 QT '
where QT is the theoretical rms quantization error,

q/V12. This measurement includes errors due to differ-

. (21Tllfin)
Vq= Vosm
T'

Vq(n)=INT

lates the best-fit, ideal N-bit sine wave to match the
data points, based on the sine wave's amplitude, offset,
frequency, and phase required to minimize the rms
error between the actual and the ideal sine wave (Refs
6 and 7). This method also requires that the input
sine-wave frequency contains no subharmonics of the
sampling rate. If you know the precise sine-wave frequency, the curve-fit algorithm is much simpler than
the FFT method, and the probability that the algorithm will converge is higher.
After the software computes the rms error, ~, between the ideal sine wave and the actual sine wave,
you can calculate the effective number of bits by using

J.

The INT function simply truncates the fractional portion of Vq(n).
To check the dynamic range of the FFT, calculate
the SIN ratio by using 6.02N + 1. 76 dB for increasing
values of N and observing the point at which the SIN
ratio no longer increases by 6.02 dBlbit. The sine-wave
input to the weighting function and the FFT are more
ideal as N approaches infinity. By making N arbitrarily
large, you can greatly reduce quantization-error effects
and analyze the true noise floor of the FFT. You can
also examine the characteristics of the weighting function.
Match the sine wave to a curve
Another test method to use with flash ADCs is sinewave curve fitting. You perform this test after the
ADC digitizes the sine wave and after your test system
stores the data in its memory. A record length of 1024
samples is usually sufficient. The software then calcu-

ential nonlinearity, integral nonlinearity, missing
codes, aperture jitter, and noise, in addition to the
quantization noise.
The effective number of bits that you calculate using
the sine-wave curve-fitting method correlates with the
value of the full-scale, FFT SIN-ratio measurement
obtained using the equation
EFFECTIVE
SIN RATIOACTUAL -1. 76 dB
NUMBER OF BITS
6.02
However, if you measure the effective bits of a sinewave input signal whose amplitude is less than full
scale, you must include the following correction factor
in the above equation to achieve correlation between
the two methods:
EFFECTIVE SIN RATIOACTUAL -1. 76 dB
NUMBER
OF BITS
6.02
+ LEVEL OF SIGNAL BELOW FULL SCALE (dB)
6.02
One useful method for reducing the effects of the
D/A converter in making gross back-to-back measure-

ments on an ADC is the beat-frequency method. Fig
4 illustrates a basic test setup. This test method
stresses the converter with a near-Nyquist signal and
drives the converter at its maximum sampling rate.
Thus, the analog-input sine wave should be slightly
lower in frequency than half the sampling frequency.
The test system updates the registers that drive the
DAC at an even submultiple of the sampling rate, fslN,
APPLICATION NOTES 11-181

II

Coherent testing is more suited to a laboratory environment; noncoherent testing more
closely represents ADC performance in the
real world.
where N is a power of 2. (N is not the ADC's resolution.) The resulting signal from the DAC is a l~w­
frequency sine wave whose exact frequency equals the
difference between half the sampling rate and the analog-input frequencl'. As Fig 4 shows, you should clock
the DAC at a much lower rate, fslN-known as the
decimation rate-thereby reducing the effects of
glitches and other dynamic errors.
You can use the beat-frequency method to make
signal-to-noise measurements over the Nyquist bandwidth, fsl2N. You also can examine the low-frequency
beat on an oscilloscope for missing codes and other
nonlinearities. To measure the harmonic content of the
beat frequency, you can use a low-frequency spectrum
analyzer. The harmonics of the low-frequency beat are
directly related to the harmonics of the analog-input
frequency. A beat frequency of a few hundred kilohertz
works well. To prevent jitter on the low-frequency
beat signal, you must derive both the analog-input sine
wave and the sampling frequency from frequency synthesizers or crystal oscillators.
This beat-frequency test is also effective in measuring the flash converter's performance for input signals
near the sampling frequency. The performance under
these conditions is useful for radar in-phase and quadrature-phase systems and in IF -to-digital conversion.
To perform this test, set the ADC's analog-input frequency to slightly less than the sampling rate. The
circuit generates a low-frequency beat even if the DAC
updates at the sampling rate. However, updating the
DAC at fslN reduces the effects of DAC dynamic errors
on the measurements.
You can use DSP techniques and FFTs to analyze
Fig 4's decimated data for a wide range of input fre-

quencies. You do have to remember the rules of aliasing, however, to know where to expect the fundamental signal to show up in the FFT output spectrum.
You may think your FFT is sampling your signal at a
rate of fslN, but the converter is actually sampling at
a rate of fs.
Once you understand how to use these various techniques, you can start to probe your particular converter
to measure its real performance. Part 3 will discuss
how you apply these techniques to actually test an
ADC in your system and determine a number of static
ErIN
and dynamic specifications.

References
1. Kester, W A, "PCM Signal Codecs for Video Applications," SMPTE Journal, No. 88, November 1979, pg 770.
2. Bennett, W R, "Spectra of Quantized Signals," Bell
System Technical Journal, No. 27, July 1948, pg 446.
3. Harris, Frederic J, "On the use of windows for harmonic
analysis with the discrete Fourier transform," IEEE Proceedings, Vol 66, No.1, January 1978, pg 51.
4. Coleman, Brendan,.Pat Meehan, John Reidy, and Pat
Weeks, "Coherent sampling helps when specifying DSP AJD
converters," EDN, October 15, 1987, pg 145.
5. Ramirez, Robert W, The FFT: Fundamentals and Concepts, Prentice Hall, Englewood Cliffs, NJ, 1985.
6. Peetz, B E, AS Muto, and J M Neil, "Measuring Waveform Recorder Performance," HP Journal, Vol 33, No. 11,
November 1982, pg 21.
7. Frohring, B J, B E Peetz, M A Unkrich, and S C Bird,
"Waveform Recorder Design for Dynamic Performance," HP
Journal, Vol 39, February 1988, pg 39.
8. "Dynamic performance testing of A to D converters,"
HP Product Note 5180A-2, 1982.

ANALOG
INPUT

,~-.1f
Fig 4-The beat..frequency test stresses the
converter with a near-Nyquist input signal,
and it drives the converter at its maximum
sampling rate. You can then examine the
low-frequency beat on an oscilloscope and
search for missing codes and other nonlinearities.

11-182 APPLICATION NOTES

~vaUIST BANDWIDTH ... ~

AN·215C
APPLICATION NOTE

ANALOG
WDEVICES

11IIIIIIII

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETIS 02062·9106 • 617/329·4700

Designer's Guide to Flash-ADC Testing

Part 3
Measure Flash-ADC Performance for Trouble-Free Operation
by Walt Kester

The first two parts of this series described
the subtleties offlash A/D converters and
the test methods used to evaluate these devices. Part 3 concludes the series with a
discussion ofthe actual measurements you'll
need to fully characterize flash A/D converters.
Walt Kester, Analog Devices
Although manufacturers have expanded the number
of guaranteed specifications they put on their data
sheets, the test conditions often won't match those of
your system design. You can use the methods described in Part 2 of this series to test a flash AID
converter, but the measurements you need to perform
depend on the converter's primary application. This
final part of the series provides information on important measurements you'll need to characterize your
converter's performance, including total harmonic distortion (THD), differential and integral nonlinearity,
and noise power ratio. You'll probably want to start
with the SIN ratio, a measurement that's common to
most AID converter applications.
The SIN ratio is the ratio of the rms fundamental
to the rms quantization noise. As described in Part 2,

you can measure this parameter by digitizing a pure
sine wave and performing Fourier transformations on
the data. The rms energy contained in the fundamental
sine wave is equal to the square root of the sum of the
squares of the peak value and the values of the appropriate number of samples, or bins, located on either
side of the peak. The converter's resolution and its
side-lobe roll-off characteristics determine the number
of samples you'll need. For a detailed explanation of
sampling requirements, see Part 2.
The rms energy in the remaining frequency bins
represents the noise due to theoretical quantization,
the converter's harmonic distortion and excess noise,
and the FFT round-off error. Take the square root of
the sum of the squares of the remaining samples (excluding the dc components) to determine the rms energy. The overall SIN ratio of the AID converter is
SIN ratio = 20 log(rms signalleveVrms noise level).
You can measure harmonic distortion in a similar
manner. The test program (described in Part 2) examines the FFT frequency spectrum for the proper location of the desired harmonic (harmonics above fsl2 will
be aliased into the baseband) and determines the rms
energy in that harmonic. The following equation calculates the harmonic distortion:
Harmonic distortion = 20 log(rms signalleveVrms
harmonic level).

Reprinted from EDN, February 1, 1990.

APPLICATION NOTES 11-183

II

The SjN ratio and harmonic distortion lire
key specifications in evaluating the performanceofJlj2)conp~er~
.

The total harmonic distortion (THD) is the root-sumsquare of the first five harmonics of the fundamental.
Use this number in place of the rms harmonic level in
the above formula.

component. For an ideal AJD converter, this ratio occurs for a full-scale input sinusoid. In a practical AID
converter, however, spurious content is a function of
slew rate. Therefore, the maximum spurious-free dynamic range for a given input frequency will probably
occur at a level somewhat below full scale. Because
the spurious-free dynamic range is slew-rate dependent, it's a function of input frequency and amplitude.
Fig 1 is a plot of the typical maximum spurious level
vs input signal level. Also shown is a plot of the corresponding spurious-free dynamic range. The plot demonstrates ~hat the maximum spurious-free dynamic
range of 38 dB occurs for an input signal that's about
3 dB below full scale.
The data you need to generate these plots is readily
available from the family of FFTs calculated for the
different input amplitudes. By knowing the input signal
level that gives the highest spurious-free dynamic
range at frequencies close to the Nyquist frequency,
it's possible to set the gain of the system to take maximum advantage of the AJD converter's spectral characteristics.

Two-tone intermodulation tests using FFTs
In many applications, you don't have the simple case
of a single input freQ,uency. For example, in communication applications that multiplex several frequencies
onto a single carrier, you need to measure intermodulation products. You determine this parameter by applying two sine waves of different frequencies (fl and fJ
to an AJD converter. You then measure the amplitudes
of the third-order intermodulation products, which 0ccur at frequencies 2f1 +f2' 2f1 -f2, 2f2+fh and 2fz-fl •
Although it's possible to filter out most intermodulation distortion if the two tones are of similar frequencies, the third-order products will be very close to the
fundamental frequencies and thus difficult to remove.
To avoid clipping-induced distortion, the amplitudes
of the individual tones should be at least 6 dB below
the full-scale range of the flash converter. In addition,
the frequency separation of the two tones should be
consistent with the resolution of the FFT. As discussed
in Part 2, the spectral resolution of the FFT is a function of record length M, coherence vs noncoherence,
and the properties of the windowing function that you
choose.
In receiver applications, you often want to know the
maximum ratio between the amplitude of a single-tone
input signal and the amplitude of its maximum spurious

Histograms are helpful
Differential and integral nonlinearity are also important measurements of converter performance. Try a
histogram test to obtain these measurements. To make
a histogram analysis, digitize a known periodic input
at a rate that's asynchronous relative to the input signal. To gather the sample data for the histogram, you'll
need a buffer memory and a test system, as described
POWER LEVEL
OF MAXIMUM
SPURIOUS
COMPONENT

SPURIOUS·FREE
DYNAMIC RANGE
60

Fig I-Thae tignmnic-MltfI6 pWta shaw the
plJWer levels of If[llJ:riO'U8 frequencieB and the
'11lIliI:imum BfJUrious-free dynamic range. In
this nample, the '11lIliI:imum spurious-jree
dynamic range occurs at an input signal
level that'8 9 dB belmn full seale.

11-184 APPLICATION NOTES

-20

40

-40

20

~~----~r------r------;

-10

MAXIMUM SPURIOUS-FREE
DYNAMIC RANGE

O~-A~-r-------r--~--,

~

~O

INPUT SIGNAL LEVEL (dB)

~

o

in Part 2. The buffer memory will probably be too
small to hold a statistically significant number of samples from a single run (several hundred thousand are
usually required). For this reason, run several tests
to acquire the data and load the contents of the buffer
into the main memory of your test system after each,
run. Benchtop test systems from Hewlett Packard and
Tektronix also provide histogram test capability.
After the test system accumulates a statistically significant number of samples, it can determine the relative number of occurrences of each digital code (the
code density). This test routine then normalizes the
data based upon the input signal and analyzes the results for linearity errors.
For an ideal AID converter with a full-scale triangular-wave input, you'd expect an equal number of codes
in each bin. The number of counts in the nth bin, H(n),
divided by the total number of samples taken, M, is
the" bin width as a fraction of full scale. The ratio of
the actual bin width to the ideal bin width, P(n), is the
differential linearity . Ideally, this ratio should be unity.
Subtracting 1 LSB gives you the differential nonlinearity.
You can determine integral nonlinearity with a cumulative histogram; the cumulative bin widths are the
transition levels. However, the cumulative effects of
errors can make the integral-nonlinearity measurement
inaccurate. Histograms are used more often in evaluating differential nonlinearity.
High-speed, high-accuracy triangular waves are difficult to generate, so use a sine wave. All codes aren't

equally probable with a sine-wave input," however, and
you should normalize the histogram data using the
probability density function for a sine wave, as shown
in Fig 2.
To obtain accurate results, you need to take a large
number of samples. For example, to determine the
differential nonlinearity for an 8-bit flash converter to
within 0.1 bit with 99-percent confidence, you'll need
268,000 samples. You can use hardware to count these
samples, thus speeding up the software processing
time. For high-speed sampling, decimate the output
data to clock rates that are compatible with a slowerspeed memory.
Using noise-power-ratio tests
You can use noise-power-ratio (NPR) tests to measure the transmission characteristics of frequency-division-multiplexed (FDM) communications links. In a
typical FDM system, 4-kHz-wide voice channels are
"stacked" in frequency for transmission over coaxial,
microwave, or satellite equipment. At the receiving
end, the FDM equipment demultiplexes the data and
returns it to individual, 4-kHz baseband channels. In
an FDM system that has 100 channels or more, Gaussian noise with the appropriate bandwidth approximates
the FDM signal.
The test setup of Fig 3 measures an individual4-kHz
channel for quietness by using a narrow-band notch
(bandstop) filter and a tuned receiver (Ref 4), both of
which measure the noise power inside this 4-kHz notch.
The NPR measurements are straightforward. With the

V(t) _ A.sin (2)<1,)

i

1

P(Y) -

a

~
~
U'i

y;r:Y'
A'.v'

LARGE
DIFFERENTIAL
NONLINEARITY

a:

~+1

'"zw

0

~
z

w

a:
a:

..J

~
zW

::>

8

ffi-1

LL

0

LL
LL

a:

w
CD
::ii
::>

z

V.-A

0

V_A

-FS

"'"

5

III
0

I

MISSING

CODES

a:

+FS

!i1

_w.

FitJ Z-HiMogranu are often "-' to pW differentilJl IIDIIlilU1Gritg. Shown kere i8 a C'UrrJe fen the probability demity function of a sine
wh.iA:k i8 ttBed to lOOrIIIalize h.istogram data to produce a plot of differenti4l nonlinearity.

APPLICATION NOTES 11-185

II

Where multiple frequencies exist on a single
carrier) you need to measure intermodulation distortion as well as harmonic distortion.

notch filter out, the receiver detennines the rms noise
power of the signal inside the notch. The notch filter
is then switched in, and the receiver detennines the
residual noise inside the 4-kHz slot. The ratio of the
two readings, expressed in dB, is the NPR. You should
test several slot frequencies across the noise bandwidth-low, midband, and high.
The NPR is usually plotted on an NPR curve as a
function of rms noise level referred to the peak range
of the system. For very low noise levels, the undesired
noise is primarily thermal noise and is independent of
the input noise level. Over this region of the curve, a
I-dB increase in the noise level causes a I-dB increase
in the NPR. As the noise level increases, the amplifiers
in the system begin to overload, creating intermodulation products that cause the noise floor of the system
to rise. As the input noise increases further, the effects
of overload noise predominate, reducing the NPR dramatically. FDM systems are usually operated at a
noise-loading level a few decibels below the point of
maximum NPR.
In a digital system containing an AJD converter, the
noise within the slot is primarily quantizing noise when
low values of noise input signals are applied. The NPR
curve is linear in this region. As the noise input level
increases, the hard-limiting action of the converter
causes clipping noise to dominate.

In a practical AJD converter, any dc or ac nonlinearities cause a departure from the theoretical NPR. Although the peak value of NPR occurs at a fairly low
input noise level (rms noise = 1/4 V0, where ± V0 is
the range of the AJD converter), the broadband nature
of the noise signal stresses the device, and the test
provides a good indication of its dynamic performance.
Theoretically, NPR readings should be independent
of any particular slot frequency. However, because of
increased nonlinearities for the higher input frequencies, the NPR readings in the higher slots tend to be
lower.
NPR testing using DSP techniques
Using FFT analysis techniques, you'll find NPR
measurements a real challenge. Consider the case
where the record length is 1024 and the sampling rate
is 20 MHz. The FFT of 1024 contiguous time samples
would place a spectral component every 19.53 kHz (20
MHzlI024). Because the notch-filter slot width is approximately 4 kHz, the probability of a spectral component falling within the notch is very low.
To achieve reasonable data stability in the FFT NPR
analysis, a number of samples must fall within the
notch. If ten samples are within the 4-kHz notch, then
the resolution of the FFT would need to be 400 Hz,
necessitating a record length of 50,000 for a sampling

-.

o

NOISE
GENERATOR

-

LOWPASS
FILTER

-I

~

NOTCH
FILTER
(BANDSTOP)

f----< ~

AID
CONVERTER

I

DIA CONVERTER

>

WITH
DEGLITCHER

I--

NOISE RECEIVER
WITH BANDPASS
FILTER

TRUE rms
VOLTMETER
rms

~

~

Fig 3-You can use thbl test setup to measure noble power ratio (NPR). With the rwtch filter out, the receiver determines the rwise power
of the signal inside the rwtch. With the notch filter switched in, the receiver measures the residual noise inside the typical 4-kHz slot. The
ratio of the two readings (in decibels) is the NPR.

11-186 APPLICATION NOTES

rate of 20 MHz. To avoid an extremely large buffer
memory (and hence more demands on the FFT processor), you need to make the notch filter wider. For
20-MHz sampling and a 1024-word buffer memory, a
notch filter that has a width of 200 kHz will provide
ten frequency bins inside the notch. Even under these
conditions, however, you should average the NPR calculations for several records to provide reasonable data
stability.
Transient-response testing
The response of a flash converter to a transient input
such as a square wave is often critical in radar applications. The major difficulty in implementing this test
is obtaining a flat pulse that's commensurate with the
converter's resolution.
A test setup for measuring the transient response
of an AID converter is shown in Fig 4. If you mount
the Schottky-diode flat-pulse generator as close as possible to the analog input of the AID converter, you can
apply a signal to the AID converter that's flat to at
least 10-bit accuracy a few nanoseconds after it reverse
biases the Schottky diodes.
You can use the same test setup to measure overvoltage recovery time. The amount of overvoltage is generally specified as a percentage of the AID converter's
range. For a converter with a 2V input range, 50%
overvoltage corresponds to IV above or below the
nominal 2V input range. You make the starting point
of the flat pulse correspond to the desired overvoltage
condition. The actual recovery time is referenced to
the time the input signal re-enters the AID-converter

input range. As in the transient-response test, you
must consider the sampling (aperture) time delay when
making this measurement.
The aperture-time and -jitter specifications of video
AID converters have probably been the least understood and most misused specifications in the entire
field. The original concept of aperture time is centered
around the classic SIH circuit of Fig 5. In an ideal SIH
circuit, the switch has zero resistance when closed and
opens instantly on receipt of an encode command. In
practice, the sampling switch changes from a low to a
high resistance over a certain finite time interval. An
error occurs because the circuit tends to average the
input signal over the finite time interval required to
open the switch. As a result, the sampled voltage varies from the voltage at the instant the switch starts
to open. The time required to open the switch is -the
aperture time. The error is determined by E.=t,. dVI
dt, where E. is the aperture error, t. is the aperture
time, and dV/dt is the rate at which the input signal
changes.
A simple first-order analysis, which neglects nonlinear effects, shows that no real error exists for such
a switch. As long as the switch opens in a repeatable
fashion, there is an effective sampling time that will
cause an ideal SlH amplifier to produce the same hold
voltage. The difference between this effective sampling
point and the leading edge of the sampling clock is a
fixed delay, which doesn't constitute an error. This
effective aperture delay is the period from the leading
edge of the sampling clock to the instant when the
input signal equals the hold value. This specification

BUFFER
MEMORY

II

SAMPLING
CLOCK.f,

A VOLTAGE
BVOLTAGE

\

OV

~

Fig 4-Thill test setup melJllures the tran·
sient response of an AID converter. The
Schottky-diode network, located between
points A and B in the circuit, generates a
flat pulse for th~ input of the converter.

APPLICATION NOTES 11-187

In a practical A/D converter, the spuriousfree dynamic range is a function of the
converter's slew rate and can occur at a
level below full scale.

ANALOG

~

DIGITAL

~
SAMPLING
CLOCK

SWITCH
DRIVER

VOLTAGE
ON HOLD
CAPACITOR

sine wave can produce the same effect as jitter on the
sampling clock. The resulting error is called aperture
jitter. The corresponding rms voltage error caused by
the rms aperture jitter qualifies as a valid aperture
error.
The aperture-jitter specification is sometimes interpreted as a measure of the converter's ability to accurately digitize rapidly changing input signals. An AID
converter with an impressive aperture-jitter specification still may lose effective bits when digitizing a sine
wave that has a maximum slew rate calculated from
the aperture formula E. =t. dVIdt.
For example, assume that a 20-MHz, 8-bit flash converter has a bipolar input range of ± Vo (2V0 p-p) and
an aperture jitter specification of 20 psec rms. To calculate the maximum aperture-jitter error, convert the
rms aperture jitter into a maximum value. If you consider that aperture jitter follows a Gaussian distribution similar to white noise, the rms aperture jitter, t ..
corresponds to the sigma (a) of the distribution. The
2a point on the distribution is a good place to set the
maximum value, and the maximum aperture jitter becomes is 2t..
If the corresponding maximum voltage error (11V)
at the zero crossing of a full-scale sine wave is set to
l,-l! LSB
LSB = 2VoI2N + \ where N equals the resolution of the AID converter), then you can calculate the
maximum full-scale sine-wave frequency, fmax, which
will produce the l,-l! LSB aperture error, by using the
following equations:

eh

Fig 5-The

C6ncf1pt

01 aperture time centers around the SIB cir-

cuit. In practice, the sampling switch generates an enw because of
input·signal averaging aver the finite time interval needed to open
the switch. The aperture time is the time needed to open the switch.

is important because it helps you determine when to
apply the sampling clock with respect to the input
signal timing.
The variation in effective aperture delay is important
in simultaneous S/H applications. For example, in both
I (in·phase) and Q (quadrature) radar receivers you
may have to provide adjustable delays in the sampling
clock to match the effective aperture delay times of
several AID converters. You should also consider delay-time tracking over a range of temperatures, especially in military systems where the specified operating
temperature ranges from - 55 to + 125°C.
True aperture errors, however, do result from variable time delays. In a practical AID converter, the
sampling clock is often phase-modulated by some unwanted source; the source can be wideband random
noise, PQwer-line frequency, or digital noise due to
poor grounding techniques. Phase jitter on the input
11-188 APPLICATION NOTES

V(t) = V0 • sin (21Tft ),
dV =
dt

2'ITfV0 • cos (21Tft),

dVI max =
dt
f.

I1V
2t. = 21TVofmax I, and

- ~ - 2-'"

max -

41TVot. -

N 1
-"".' 2 + .

For t. = 20 psec rms and N = 8, fmax is 16 MHz. These
calculations imply that a 20-MHz flash converter can
accurately digitize a full-scale sine wave of 16 MHz.
In actual practice, however, the device may begin to
suffer from skipped codes, decreased effective bits and
SIN ratio, and ac nonlinearities at much lower frequencies.
You can calculate the effects of aperture jitter on

Histograms are useful in epaluating the
differential nonlinearity of an AjD converter.

the full-scale sine-wave SIN ratio as follows:
V(t)
dV
dt

= Vo . sin (2m,),

= 21TfV0

•

cos (21rl't), and

90
14

80

dV

21TfVo

f!!
iii

Ttnns = v'2'

12

!Ii

10

!!I::>

II:
W

For an nns error voltage, !J..Vrma, and an nns aperture
jitter of 1;.,

z

8

~

b

!J..V.... = 21TfVO and

v'2 '

t.

6 ~

:t;

30

4

20

!J..V

...

= 21TfVot.

v'2'

The nns-signal to nns-noise ratio, expressed in decibels, is

.

SIN ratio

=

20 log

== 20 log

[V;,V1v'....2]
[2~tJ dB.

The SIN ratio that's due exclusively to aperture jitter
in the above equation is plotted in Fig 6 as a function
of the full-scale input-sine-wave frequency for various
values of aperture jitter.
Consider an 8-bit, 20-MHz AJD converter with an
nns aperture jitter of 20 psec. For an 8-MHz full-scale
input, the SIN ratio due only to aperture jitter is 60
dB, as calculated from the equation. The theoretical
SIN ratio due to quantizing noise in an 8-bit flash converter is 50 dB. When you combine the SIN ratio of
60 dB with the SIN ratio of 50 dB, you obtain a theoretical SIN ratio of 49.6 dB, which encompasses both the
ideal quantizing noise and the noise due to aperture
jitter. A practical8-bit device that has an nns aperturejitter specification of 20 psec may, however, only
achieve an SIN ratio of 40 dB under these conditions.
Therefore, to accurately evaluate the AID converter's dynamic perfonnance, you must carefully examine the SIN ratio, effective number of bits, and aperture-jitter specifications.
Try measuring the aperture jitter of an AJD converter using the test setup shown in Fig 7. The low-

10

2

3

5

7 10

20

30

50

70

100

FULL-SCALE SINE·WAVE INPUT (MHz)

Fig 6-TlaiB plot compare. tile SIN ratio to the full·scale aine-wave
input.frequ.mcy fX

SAMPLING
CLOCK

B

Fig 8--The effective aperture dewg is the
time difference between the leading edge of
the sampling-clock pnlse and the actnal zero
crossing of the sine-wave inpnt.

In a similar manner, you can measure dynamic errors
caused by fast input signals by using the beat-frequency approach. You choose the low-frequency beat
frequency to give the proper number of samples per
code level, and then you examine the decimated digital
outputs for adjacent sample differences that exceed
the allowable error amplitude.
In summary, determining appropriate error-rate criteria for an AID converter depends upon both the application and the characteristics of the converter under
consideration. Flash converters that use straight binary decoding with no additional correction logic are
most subject to large metastable errors at midscale.
For this situation, a low-amplitude dither signal centered on the midscale code transition might be an appropriate stimulus. In a more well-behaved flash converter, a full-scale signal that exercises all codes might
be desirable.
If you plan to digitize composite video signals, you'll
need to measure the differential-gain and -phase performance of the flash AID converter. Differential gain
is the percentage difference between the digitized amplitudes of two signals. Likewise, differential phase is
the phase difference between the digitized values of
the same two input signals. The input signals are typically a high-frequency low-level sine wave representing
the color subcarrier frequency, superimposed on a lowfrequency sine wave. Distortion-free processing of the
color signal requires that the flash converter alters
neither the amplitude nor the phase of the chrominance
signal as a function of the luminance-signal level.

The best method for performing composite video
tests is to use an AID converter back-to-back with a
D/A converter. Connect a TV test signal to the AID
converter and use the output of the D/A converter to
drive a vectorscope. To ensure that the test accurately
measures the AID converter's performance, use a lowglitch D/A converter followed by a track-and-hold
deglitcher. In addition, the dc accuracy of the D/A
converter should exceed that of the AID converter.
When testing an 8-bit flash converter, use a D/A converter with at least 10 bits of accuracy.
EDN

References
1. Andrews, James R, Barry A Bell, Noms S Nahman,
and Eugene E Baldwin, "Reference Waveform Flat Pulse
Generator," IEEE Transactions on Instrumentation and
Measurerrwnt, Vol IM-32, No.1, March 1983, pg 27.
2. Schoenwetter, Howard K, "A Programmable Voltage
Step Generator for Testing Waveform Recorders," IEEE
Transactions on Instrumentation and Measurerrwnt, Vol
IM-33, No.3, September 1984, pg 196.
3. Gray, G A, and G W Zeoli, "Quantization and Saturation
Noise Due to Analog-Digital Conversion," IEEE Transactions on Aerospace and Electronic Systems, January 1971,
pg 222.
4. Tant, M J, The White Noise Book, Marconi Instruments,
July 1974.

APPLICATION NOTES 11-191

II

11-192 APPLICATION NOTES

AN·216
APPLICATION NOTE

~ANALOG

WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 6171329-4700

Video VCAs and Keyers Using the AD834 and AD811
by Eberhard Brunner, Bob Clarke, and Barrie Gilbert

A VIDEO-QUALITY VCA
The VCA is shown in Figure 1. The AD834 multiplies the
signal input by the control voltage. Its outputs are in the
form of differential currents from a pair of open collectors, ensuring that the full bandwidth of the multiplier
(which exceeds 500 MHz) is available for certain applications. In this case, more moderate bandwidth is obtained
using current-to-voltage conversion, provided by the
AD811 op amp, to realize a practical amplifier with a
single-sided ground-referenced output. Using feedback
resistors R8 and R9 of 511 n the overall gain ranges
from -70 dB for VG -0 to +12 dB (a numerical gain of
four) when VG = +1 V.

INTRODUCTION

Voltage-controlled amplifiers (VCAs) built from analog
multipliers take one of two forms. In the first, the multiplier acts as a voltage-controlled attenuator ahead of a
fixed-gain amplifier. This type of VCA is used in applications where only a moderate maximum gain, but a fairly
high maximum loss, are needed. In the second, the variable attenuation is placed in the feedback path around
an op amp, which, in fact, implements an analog divider,
more suitable for applications requiring high gains.
This application note describes practical circuits in
which the wide bandwidth of the Analog Devices AD834
Four-Quadrant Multiplier and the AD811 CurrentFeedback Op Amp are exploited to provide a videoquality VCAwith a maximum gain of 12 dB (x4) or 20 dB
(x 10), based on the first of the above methods. A
slightly modified form of this VCA, using two multipliers
whose outputs are summed, provides the first of two
video keyer designs; a second design uses global negative feedback around the multipliers to achieve improved accuracy and some simplification.

The -3 dB bandwidth is 90 MHz (Figure 2) and is essentially independent of gain. The response can be maintained flat to within ±0.1 dB from dc to 40 MHz at full
gain (Figure 3) with the addition of an optional capacitor
of about 0.3 pF across the feedback resistor R8. The
circuit produces a full-scale output of ±4 V for a ±1 V
input, and can drive a reverse-terminated load of 50 n or
75 n to ±2 V. Figure 4 shows the typical pulse response.

Rl
lOO1l

FB
+12V

+o---'III/'v----,

RB"

Vo

II

Cl

R4
18211
R6
294!l

VOUT

R5

182!l

V,N 0 - - - - - - '

R7
294!l

FB

-12V
• RB = R9= 511 FOR X4 GAIN
=1.27k FOR Xl0 GAIN

Figure 1. Complete VCA Provides Up to 20 dB of Gain (G = BW = 25 MHz)
and a Bandwidth of Over 90 MHz (G = 12 dB)

APPLICATION NOTES 11-193

The gain can be increased to 20 dB (x10) by raising Ra
and R9 to 1.27 kO, with a reduction of the -3 dB bandwidth to about 25 MHz (also shown in Figure 2) and a
maximum output voltage of ±9 V using the ±12 V supplies. It is not necessary to alter R6 and R7 for the high
gain version of the amplifier, although an optimized design would raise these slightly to restore the commonmode voltage at the input of the ADa1 1 to +5 V.

Figure 4. Full-Output Pulse Response for the 12 dB
Amplifier

+20dB

l-

I-

t

I-OUTPUT
(2dBPER
DIVISION)

I-

R,= 1.27kQ

II

,--

JI

I

"'r-..

I

\

I I

R F=51Hl

+12dB

"

10k

lOOk

1M

10M

100M

Figure 2. Small-Signal Response of the VCA Shows a
-3 dB Bandwidth of 90 MHz for the 12 dB Version and
25 MHz for the 20 dB Version

12.1dB
12dB

~'rJf'

11.9dB

II-

10k

~~:u:ER
DIVISION)

lOOk

1M

10M

Figure 3. AC Response Can Be Held Flat to Within
±0.1 dB from DC to 40 MHz by Addition of a 0.1 pF
Capacitor Across R8

11-194 APPLICATION NOTES

The gain-control input may be a positive or negative
ground-referenced voltage, or fully differential, depending on the user's choice of connections at Pins 7 and a.
As shown, a positive value of VG results in an overall
noninverting response. Reversing the sign of VG simply
causes the sign of the overall response to invert. In fact,
although we have called this a voltage-controlled amplifier, it can just as well be used as a general-purpose
four-quadrant multiplier with good load-driving capabilities and fully symmetrical responses from X- and
V-inputs.
We have used the V-input of the multiplier for the signal,
since this port is slightly more linear than the X-input,
and have shown X2 and Y2 grounded. These inputs each
draw about 45 fLA of bias current, so the grounded (unused) inputs should be terminated preferably in the
same resistance as the source, in each case, to minimize
offset voltages. The resistance of the signal source may
in some cases be essentially zero (as in the case of a
transformer-coupled input, or certain signal generators);
note that a doubly terminated cable line of impedance
Zo will present a dc resistance of Zo/2 at the input.
Resistors R1 and R2 have been included in Figure 1 to
minimize the likelihood of small aberrations arising in
the signal path in those cases where VG is derived from
a source having poor HF characteristics; they may be
omitted in the four-quadrant multiplier application.
High-frequency circuits such as those described herein
are sensitive to component layout, stray capacitance,
and lead lengths. Use a ground plane and make short,
direct connections to ground. Bypass the power-supply
connections- inductance in the power-supply leads can
form resonant circuits that produce response peaking or
even sustained oscillations.

sure proper operation of the AD811's input stage, the
common-mode voltage at W1 and W2 must be within
the common-mode range of these inputs. There are several ways to do this. We can use separate supplies of
±5 V for the AD834 and 2: ±9 V for the AD811. Here, we
have chosen to show how the VCA can be biased from
one dual supply of nominally ±12 V. Figure 5 also helps
to understand the dc biasing design.

Circuit Analysis
To understand the operation of the VCA, we need first to
consider the scaling properties of the AD834, which is
actually an accurate nonlinear (two-input) voltagecontrolled current source. Figure 5 shows a simplified
schematic of the whole VCA.
The exact transfer function for the AD834 would show
that the differential voltage inputs at X1, X2 and Y1, Y2
are first multiplied together, divided by the scaling voltage of 1 V (determined by the on-chip bandgap reference) and the resulting voltage is then divided by an
accurate 250 0 resistor to generate the output current. A
simplified form of this transfer function is

We begin by deciding to place the AD834's outputs at
about +5 V (a little higher than they operate in the other
published applications of this product). Under dc conditions, the high open-loop gain of the op amp forces W1
and W2 to assume the same potential. We calculate the
values of RA to introduce the required 7 V drop, by considering the components of the total current in each of
these resistors for the zero-signal condition.

(1 )

where Iw is the differential current output from W1 to
W2 and it is understood that the inputs X" X 2 , Y" and Y2
are expressed in volts. Thus, when both differential inputs are 1 V, Iw is 4 mA; this current is laser-calibrated to
close tolerance, which simplifies the use of the AD834 in
many applications. Note carefully the direction of this
current in determining the correct polarity of the output
connections.

First, when VOUT = 0, the current in resistors RF must be
10 mA (5 VI 5000 ). Second, the standing current into
W1 and W2, due to the AD834's internal biasing, is
8.5 mA per side. Third, in this application we provide the
positive supply voltage for the AD834 (at Pin 6) via resistors Rs which each carry one-half of the total supply
current of 11 mA. Thus, the total current in resistors RA
is 24 mA (10 + 8.5 + 5.5 mAl and a value of 2940 is
chosen (the closest standard value to 7 V/24 rnA) for
these resistors. Finally, we choose Rs to set the voltage
at Pin 6 to +4 V, which is high enough to ensure accurate operation of the AD834 over the full signal and
temperature ranges; the nearest standard resistor value
is 1820 (1 VI 5.5 mAl.

It is easy to show that the output of the AD811 is
VOUT = 2 x Iw

X RF

(2)

where RF is the feedback resistor. For RF = 500 0 (499 0
is the nearest standard resistor value), the overall transfer function of the VCA becomes
(3)

which reduces to VOUT = 4 VG V1N using the labeling
conventions shown in Figure 1. As noted, the phase of
the output reverses when VG is negative. A slightly
higher value of RF is used to compensate for the finite
gain of the AD811.

The presence of these resistors (whose parallel sum is
1120 on each side) at the input of the op amp causes it
to operate at a "noise gain" of 4.45 (4990/112 0), but
this neither has any significant effect on the dc scaling of
the system, nor does it lower the closed-loop bandwidth
(as would be the case for a conventional voltagefeedback op amp).

Both the AD811 and the AD834 can operate individually
from power-supply voltages of ±5 V. However, to en-

11mA

+12V

RA
RF

II

R.
+4V

R.
RF

RA
-5V
+12V

Figure 5. Simplified Schematic of the VCA for Analysis Purposes

APPLICATION NOTES 11-195

to be unity at the load, when it is driven from a reverseterminated 75 n line. This means that the "dual VCA"
has to operate at a maximum gain of x2,.rather than x4
as in Figure 1. However, this cannot be achieved by
lowering the feedback resistor, since below a critical
value (not much less that 5000) the AD8' 1 will become
unstable. This is because the dominant pole in the
closed-loop ac response of a current-feedback amplifier
is controlled by this feedback resistor. It would be possible to operate at a gain of x4 and then attenuate the
signal at the output. Instead, we have chosen to attenuate the signals by 6 dB at the input to the AD81'; this is
the function of R8 through Rll.

A VIDEO KEVER BASED ON THE VeA
Using two AD834s and adding a 1 V dc source, a special
form of a two-input VCA called a video keyer (Figure 6)
can be assembled. Keying is the term used in reference
to blending two or more video sources under the control
of a further signal or signals to create such special effects as dissolves and overlays. The circuit described
here is a two-input keyer, with video inputs VA and VB'
and a control input V G' The output at the load is given by

VOUT = GVA

+

(4)

(1 - G)Vs

where G is a dimensionless variable (actually, just the
gain of the "A" signal path) that ranges from 0 when
VG = 0, to 1 when VG = +1 V. Thus, V OUT varies continuously between VA and VB as G varies from 0 to 1.

The -3dB bandwidth is about 85 MHz and the gain is flat
within ±O.' dB to 30 MHz (Figure 7). Output noise and
signal isolation with either channel fully off and the
other fully on is about -60 dB to 20 MHz. The feedthrough at 100 MHz is limited primarily by board layout.

The operation is straightforward. Consider first the signal path through Ul, which handles video input VA' Its
gain is clearly zero when VG = 0 and the scaling we have
chosen ensures that it is unity when VG = +1 V; this
takes care of the first term in Equation 4. On the other
hand, the VG input to U2 is taken to the inverting input
X2 while Xl is biased at an accurate +1 V. Thus, when
VG = 0, the response to video input VB is already at its
full-scale value of unity, whereas when VG = +1 V, the
differential input X, - X 2 is zero. This generates the
second term in Equation 4.

OdB

I'-....

"

I-- OUTPUT
' - (1OdBPER
DIVISION)

To generate the 1 V dc needed for the "l-G" term, an
AD589 reference supplies 1.225 V ±25 mV to a voltage
divider consisting of resistors R2 through R4. Potentiometer R3 should be adjusted to provide exactly + 1 V at the
X, input.

, III IlllL

-SOdB

rlll'!'

"1 II" !19IU'

11" )'

R6

IYIlI 'ri '

10M

+5V
R12
511n

VG
OTO+1V
Rl
1.87k

+12V

R2
174n
+5V
C1
R3
100n

~~~~tL~~-o%~
±1VFS

~O.'~F

R10
49.9n

VB
±1VFS

NOTE: IN THIS CASE,
Vo~ TAKEN AT LOAO

o-------....J
R11
49.9ll

R13
51111

Figure 6. A Two-Input Video Keyer Based on the VCA

11:"'196 APPLICATION NOTES

100M

Figure 7. AC Response of the Video Keyer, at VG = Zero
and + 1 V; Feedthrough Is About -60 dB

R8
49.9n

VA
±1VFS

~

'I' "1 I

1M

In this case, we have shown an alternative arrangement
using dual supplies of ±5 V for the AD834 and ±12 V for
the AD811. Also, the overall gain in this case is arranged

,11, liJIIIJ n

,d,.H.

A FEEDBACK KEVER
The gain accuracy of the "VCA-based" keyer is dependent on the feedback resistor, RF • Also, any nonlinearity
in the multipliers will show up as a differential gain
error. Using an alternative technique, in which the feedback is routed back to unused signal inputs on the
AD834s, we can eliminate the feedback resistor and
achieve higher accuracy. In the design shown here, we
have also used a level-shifting network between the
AD834 and the AD811 that eliminates the need for separate power supplies for the two ICs. (In fact, this technique can also be used in the VCAs.)

Xl

X2
':'

yA-+----I Yl

+

(1-G)(Vs-Vour) -> 0

VOUT
+lV

+

X2

W
(1-G) (lle-VOUT)

Figure 8. Elements of a Feedback Keyer
are identical to those used previously. The bias currents
required at the output of the multipliers are provided by
R8 and R9. A dc-level-shifting network comprising
R10/R12 and R11/R13 ensures that the input nodes ofthe
AD811 are positioned within an acceptable commonmode range for this IC. At high frequencies, C1 and C2
bypass R10 and R11, respectively.
R14 is included to lower the HF loop gain, and is needed
because the voltage-to-current conversion in the
AD834s, via the Y2 inputs, results in an effective value of
the feedback resistance of 250 a (see Figure 5); this is
only half the minimum value of 500 a required for HF
stability of the AD811. (Note that this resistance is unaffected by G: when G = 1, all the feedback is via U1,
while when G = 0 it is all via U2.) Resistor R14 reduces
the fractional amount of output current from the multipliers into the current-summing inverting input of the
AD811, by sharing it with R8. This resistor can be used to
adjust the bandwidth and damping factor to best suit the
application.

(6)

exactly as required for a two-input keyer. The summation of the differential current-mode outputs of the two
AD834s is simply achieved by connecting together their
respective W1 and W2 nodes. The resulting signalessentially the loop error represented by the left-hand
side of Equation 5 - is forced to zero by the high gain of
an AD811 op amp.
Figure 9 provides a practical embodiment of these ideas.
The gain-control details to provide G and (1-G) terms
R14
SEE TEXT

+5V

M2

Y2

(5)

(1-G)Vs

Xl

1Ie---+--l Yl

which requires that
Vour = GVA

G (YA-YoUT)

Y2

The basic idea is shown in Figure 8. Note first that VOUT
is returned to the inverting inputs Y2 of the multipliers
and that their outputs are added. The sum is forced to
zero by the assumed high open-loop gain of the op amp.
Multiplier M1 produces an output G(VA-VOUT), while M2
produces an output (1-G)(V B-VOUT)' where G is Vo /(1 V)
and ranges from 0 to 1. Therefore, the complete system
is described by the limiting condition
G(VA-Vour )

M1 w

SETUP FOR DRIVING
REVERSE-TERMINATED LOAD

TO PIN

spzo
200n zo

"",VOUT

AD811
RIO

""

OTO+1V

TOY2
+5Y

200n
INSET

R12

1.B7k

6.98k

R2
174n
VA
±1VFS

II

-SY

R3

loon

R13

6.98k
LOAD
GND

-SV

Va o--------ll--'
±lVFS

Rll

Figure 9. A Practical Embodiment of a Feedback Keyer. The Inset Shows the Feedback Configuration
(Gain of x2) for Driving a Reverse-Terminated Load.

APPLICATION NOTES 11-197

Figure 10 shows the small-signal ac response of this
system of the "A" channel at unity gain and zero gain;
as is inevitably the case, there is a small amount of
feedthrough at the highest frequencies. Two representative values of R14 are shown; using 4020, the pulse
response is considerably overdamped, resulting in a
-3 dB bandwidth of 15 MHz, while a value of 1070
provides a maximally flat response with a -3 dB bandwidth of 70 MHz.

RI4=I071l
RILl!;' ~
a.

~

J""'IIf'II
10k

... 1.tIo"

1M
lOOk

1M

10M

100M

Figure 10. AC Response of the Feedback Keyer. For VG =
+ 1 V, the -3 dB Bandwidth Is 15 MHz Using R14 = 402 G
and 70 MHz with R14 = 107 G. For These Measurements,
RL = 500
Figure 11 shows the pulse response at unity gain: in (a)
R14 = 4020, while in (b) R14 = 107 O. The frequency
and pulse responses of the "B" channel, and of the
gain-control input are the same, being limited by the
output amplifier rather than the AD834s. Likewise, the
differential gain and phase behavior will be determined
primarily by the AD811; the data sheet should be consulted for more information. The feedthrough at 1 MHz
is about -80 dB and -64 dB at 10 MHz and, as before, is
eventually limited by board layout. All of these results
used a 50 0 load at the output.

11-198 APPLICATION NOTES

b.

Figure 11. Pulse Response of the Feedback Keyer.ln (a),
R14 = 402 G While in (b), R14 = 107 G. For These
Measurements, RL. = 50 G

Unlike Figure 6's circuit, this keyer provides unity-gain
operation. In applications where a reverse-terminated
line (50+500 or 75+ 750) is to be driven, the gain can
be doubled by the inclusion of a resistive divider between VOUT and the Y2 pins; equal resistors of 2000 can
be used (see the inset in Figure 9). This halving of the
feedback voltage also lowers the bandwidth, which can
now be restored by reducing, or even eliminating, R14.
Figures 12 and 13 show the modified circuit's performance when driving a 500 reverse-terminated line.

RI4=49.9n..,
R1LlJC >-.

a.

",,'"

i-"

~
"".'r"

~It...
10k

lOOk

1M

10M

100M

Figure 12. AC Response of the Feedback Keyer, Now
Configured for a Gain of x2. For VG = + 1 V, the -3 dB
Bandwidth Is 15 MHz Using R14 = 137 nand 70 MHz
with R14 = 49.9 n. For These Measurements, RL = 50 n

b.
Figure 13. Pulse Response of the Feedback Keyer Now
Configured for a Gain of x2. In (a), R14 = 137 n While in
For These Measurements, RL = 50
(b), R14 = 49.9

n.

n

II

APPLICATION NOTES 11-199

11-200 APPLfCA TION NOTES

AN·217
APPLICATION NOTE

1IIIIIIII ANALOG

WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 6171329-4700

Audio Applications of the ADSP Family
(IIR Filters)

INFINITE IMPULSE RESPONSE (IIR) FILTERS
Compared to the FIR filter, an IIR filter can often be much
more efficient in terms of attaining certain performance
characteristics with a given filter order. This is because
the IIR filter incorporates feedback and is capable of
realizing both poles and zeros of a system transfer function, whereas the FIR filter is only capable of realizing
the zeros (although the FIR filter is still more desirable in
many applications, because of features such as stability
and the ability to realize exactly linear phase responses).

followed by the sum-of-products of the b values and the
delay line values.
.MODULE diriir_sub;

Direct Form II IIR Filter Subroutine
Calling Parameters

MRl = Input sample Ix[n))
MRO = 0
10 - Delay line buffer current location Ix[n-1])
LO = Filter length
15 - Feedback coefficients la[1]. a[2], ... a[N))
L5 = Filter length - 1
16 - Feedlorward coefficients Ib[O], b[1], ... b[N))
L6 = Filter length
MO = 0
Ml,M4= 1
CNTR = Filter length - 2
AXO = Filter length - 1

Direct Form IIR Filter
The IIR filter can realize both the poles and zeros of a
system because it has a rational transfer function, described by polynomials in z in both the numerator and
the denominator:
M

Return Values

~>kZ-k

MR1 = output sample Iy[n))
10 - delay line current location Ix[n-1))
15 ---+ feedback coefficients
16 ---+ feedforward coefficients

H(z) = __
k_=_O _ __
N

-L

ak z - k

Altered Registers

k =1

MXO,MYO,MR

The difference equation for such a system is described
by the following:
M

yin) =

L
k=O

N

bkx(n-k)

+

L

Computation Time

liN - 2) + IN - 1)) + 10 + 4 cycles IN = M = Filter order)
All coefficients and data values are assumed to be in 1.15 format.

aky(n-k)

'k= 1

In most applications, the order of the two polynomials M
and N are the same.
The roots of the denominator determine the pole locations of the filter, and the roots of the numerator determine the zero locations. There are, of course, several
means of implementing the above transfer function with
an IIR filter structure. The "direct form" structure presented in Listing 1 implements the difference equation
above.
Note that there is a single delay line buffer for the recursive and nonrecursive portions of the filter (Oppenheim
and Schafer's Direct Form II). The sum-of-products ofthe
a values and the delay line values are first computed,

.ENTRY diriir;
diriir:

MXO=DMIIO,M1), MYO=PMII5,M4);
DO poleloop UNTIL CE;
poleloop: MR=MR+MXO*MYOISS), MXO=DMIIO,Ml), MYO=PMII5,M4);
MR=MR+MXO*MYOIRND);
CNTR=AXO;
DMIIO,MO)=MRl ;
MR=O, MXO=DMIIO,Ml), MYO=PMII6,M4);
DO zeroloop UNTIL CE;
zeroloop: MR=MR+MXO*MYOISS), MXO=DMIIO,Ml), MYO=PMII6,M4);
MR=MR+MXO*MYOIRND);
MODIFY 1I0,M2);
RTS;
.ENDMOD;

Listing 1. Direct Form IIR Filter

APPLICA TION NOTES 11-201

III

Cascaded Biquad IIR Filter
A second-order biquad IIR filter section is shown on
Figure 1. Its transfer function in the z-domain is:
H(z) = Y(z)/X(z) = (Bo+B,z-'

+ Bzz- z)/(1 +A,z-' +Azz-z)

where A" A 2, Bo, B, and B2. are coefficients that determine the desired impulse response of the system H(z).
Furthermore, the corresponding difference equation for
a biquad section is:
Y(n) = BoX(n)+B,X(n-1)+ BzX(n-2)- A, Y(n-1 )-AzY(n -2)
SCALE
FACTOR

x --- Y ;
RTI;
RTI;
RTI;
JUMP sample;

{decimate by factor of M}

{interrupt
{interrupt
{interrupt
{interrupt

O}
1}
2}
3= input sample rate}

{disable all interrupts}
{edge sensitive interrupts}
{set decimation counter to M}
{for first input data sample}
{setup a circular buffer in PM}

IMASK=b#OOOO;
ICNTL= b#Ollll ;
SI=M;
DM(counter)= SI;
14=-coef;
L4=%coef;
M4=1;
IO=-data;
LO=%data;
MO=l;
IMASK=b#1000;
JUMP waitjnterrupt;

{modifier for coef is 1}
{setup a circular buffer in DM}
{modifier for data is 1}
{enable interrupt 3}
{infinite wait loop}

' -_ _ _ Decimator, code executed at the sample rate _ _ _ _ _ _-----J
sample:
AYO=DM(adc);
DM(lO,MO)=AYO;
{update delay line with newest}
AYO=DM(counter);
AR=AYO-l;
{decrement and update counter}
DM(counter)=AR;
IF NE RTI;
{test and return if not M times}
code below executed at 11M times the sample rate
}
AR=M;
{reset the counter to M}
DM(counter)=AR;
CNTR=N - 1;
MR=O, MXO=DM(lO,MO), MYO=PM(l4,M4);
DO taploop UNTIL CE;
{N-l taps of FIR}
MR=MR+ MXO*MYO(SS), MXO=DM(lO,MO), MYO=PM(l4,M4);
taploop:
MR=MR+MXO*MYO(RND);
{last tap with round}
IF MV SAT MR;
{saturate result if overflow}
DM(dac)=MR1;
{output data sample}
RTI;
.ENDMOD;

m

Listing 1. Decimation Filter

The routine uses two circular buffers, one for data samples and one for coefficients, that are each N locations
long. The coefbuffer is located in program memory and
stores the filter coefficients. Each time an output is calculated, the decimator accesses all these coefficients in
sequence, starting with the first location in coef. The 14
index register, which points to the coefficient buffer, is
modified by one (from modify register MO) each time it
is accessed. Therefore, 14 is always modified back to the
beginning of the coefficient buffer after the calculation is
complete.

The FIR filter equation starts the convolution with the
most recent data sample and accesses the oldest data
sample last. Delay lines implemented with circular buffers, however, access data in the opposite order. The
oldest data sample is fetched first from the buffer and
the newest data sample is fetched last. Therefore, to
keep the data/coefficient pairs together, the coefficients
must be stored in memory in reverse order.

APPLICA TION NOTES 11-207

The relationship between the address and the contents
of the two circular buffers (after N inputs have occurred)
is shown in the table below. The data buffer is located in
data memory and contains the last N data samples input
to the filter. Each pass of the filter accesses the locations
of both buffers sequentially (the pointer is modified by
one), but the first address accessed is not always the
first location in the buffer, because the decimation filter
inputs M samples into the delay line before starting each
filter pass. For each pass, the first fetch from the data
buffer is from an address M greater than for the previous
pass. The data delay line moves forward M samples for
every output calculated.

Data
OM(O)
OM(1)
OM(2)

DM(N-3)
OM(N-2)
OM(N-1)

= x(n-(N-1))
= x(n-(N-2))
= x(n-(N-3))

oldest

••
•= x(n-2)

= x(n-1)
= x(n-O)

newest

Coefficient
PM(O)
PM(l)
PM(2)

PM(N-3)
PM(N-2)
PM(N-1)

=
=
=

h(N-1)
h(N-2)
h(N-3)

=
=
=

h(2)
h(l)
h(O)

••
•

A variable in data memory is used to store the decimation counter. One of the processor's registers could have
been used for this counter, but using a memory location
allows for expansion to multiple stages of decimation.
The number of cycles required for the decimation filter
routine is shown below. The AOSP-2100 takes one cycle
to calculate each tap (multiply and accumulate), so only
18+N cycles are necessary to calculate one output sample of an N-tap decimator. The 18 cycles of overhead for
each pass is just six cycles greater than the overhead of
a non-multirate FIR filter.

A More Efficient Decimator
The routine in Listing 1 requires that the 18+N cycles
needed to calculate an output occur during the first of
the M input sample intervals. No calculations are done
in the remaining M-1 intervals. This limits the number
of filter taps that can be calculated in real time to:
.
1
N=---18

Fs tCLK

where tCLK is the instruction cycle time of the processor.
An increase in this limit by a factor of M occurs if the
program is modified so that the M data inputs overlap
the filter calculations. This more efficient version of the
program is shown in Listing 2.
In this example, a circular buffer inpuCbuf stores the M
input samples. The code for loading inpuCbufis placed
in an interrupt routine to allow the input of data and the
FIR filter calculations to occur simultaneously.
A loop waits until the input buffer is filled with M samples before the filter output is calculated. Instead of
counting input samples, this program determines that M
samples have been input when the input buffer's index
register 10 is modified back to the buffer's starting address. This strategy saves a few cycles in the interrupt
routine.
After M samples have been input, a second loop transfers the data from inpucbufto the data buffer. An output
sample is calculated. Then the program checks that at
least one sample has been placed in inpuCbuf. This
check prevents a false output if the output calculation
occurs in less than one sample interval. Then the program jumps back to wait until the next M samples have
been input.

Interrupt Response
Fetch Input
Write Input to Data Buffer
Decrement and Test Counter
Reload Counter with M
FIR Filter Pass
Return from Interrupt

2 Cycles
I Cycle
I Cycle
4 Cycles
2 Cycles
7+N Cycles
I Cycle

This more efficient decimation filter spreads the calculations over the output sample interval1/Fs ' instead of the
input interval 1/Fs . The number of taps that can be calculated in real time is:

Maximum Total

18+ N Cycles/Output

which is approximately M times greater than for the first
routine.

11-208 APPLICA TION NOTES

M

N = - - -20 - 2M - 6IM-l)

Fs

tCLK

{DEC_EFF.dsp
Real time Direct Form FIR Filter, N taps, decimates by M for a decrease of 11M times the input sample rate. This version
uses an input buffer to allow the filter computations to occur in parallel with inputs. This allows larger order filter for a
given input sample rate. To save time, an index register is used for the input buffer as well as for a decimation counter.
INPUT: adc
OUTPUT: dac
.MODULE/RAM/ABS=O
.CONST
.CONST
.VAR/PM/RAM/CIRC
.VAR/DM/RAM/CIRC
.VAR/DM/RAM/CIRC
.PORT
.PORT
.INIT
RTI;
RTI;
RTI;
JUMP sample;

eff_decimate;
N=300;
M=4;
coef[N);
data[N];
input_buf[M];
adc;
dac;
coef: ;
{interrupt O}
{interrupt 1}
{interrupt 2}
{interrupt 3= input sample rate}

initialize:

IMASK=b#OOOO;
ICNTL= b#01111;
14="coef;
L4=%coef;
M4=1;
IO="data;
LO=%data;
MO=1;
11 ="input_buf;
L1=%input_buf;
IMASK=b#1000;

{decimate by factor of M}

{disable all interrupts}
{edge sensitive interrupts}
{setup a circular buffer in PM}
{modifier for coef is 1}
{setup a circular buffer in OM}
{modifier for data is 1}
{setup a circular buffer in OM}
{enable interrupt 3}

AXO=11;
{wait for M inputs}
AYO="inpuCbuf;
AR=AXO-AYO;
{test if pointer is at start}
IF NE JUMP wait_M;
L--_ _ _ _ _ code below executed at 11M times the sample rate _ _ _ _-'
CNTR=M;
DO load_data UNTIL CE;
AR=DM(11,MO);
load_data:
DM(lO,MO)=AR;
fir:

taploop:

CNTR=N -1;
MR=O, MXO=DM(lO,MO), MYO=PM(l4,M4);
DO taploop UNTIL CE;
{N-1 taps of FIR}
MR=MR+MXO*MYO(SS), MXO=DM(lO,MO), MYO=PM(l4,M4);
{last tap with round}
MR=MR+MXO*MYO(RND);
IF MV SAT MR;
{saturate result if overflow}
DM(dac)=MR1;
{output data sample}

waicagain:

AXO=11;
AYO="inpuCbuf;
AR=AXO-AYO;
IF EQ JUMP wait_again;
JUMPwaiCM;
L----:_ _ _ _ sample input, code executed at the sample rate _ _ _ _-'
sample:
ENA SEC_REG;
AYO=DM(adc);
DM(l1,MO)=AYO;
RTI;

{test and wait if i1 still}
{points to start of input_but}

{so no registers will get lost}
{get input sample}
{load in M long buffer}

.ENDMOD;
Listing 2. Efficient Decimation Filter

APPLICA TION NOTES 11-209

II

X(I)

y(I')

Figure 3, Decimator Hardware
Decimator Hardware Configuration
Both decimation filter programs assume an ADSP'2100
system with the 110 hardware configuration shown in
Figure 3, The processor is interrupted by an interval
timer at a frequency equal to the input sample rate Fs
and responds by inputting a data value from the AID
converter, The track/hold (sampler) and the AID converter (quantizer) are also clocked at this frequency, The
D/A converter on the filter output is clocked at a rate of
FslM, which is generated by dividing the interval timer
frequency by M,

To keep the output signal jitter-free, it is important to
derive the D/A converter's clock from the interval timer
and not from the ADSP-2100, The sample period of the
analog output should be disassociated from writes to
the D/A converter. If an instruction-derived clock is used,
any conditional instructions in the program could
branch to different length program paths, causing the
output samples to be spaced unequally in time, The D/A
converter must be double-buffered to accommodate the
interval-time-derived clock. The ADSP-2100 outputs data
to one latch. Data from this latch is fed to a second latch
that is controlled by an interval-timer-derived clock.
Interpolation
The process of recreating a continuous-time signal from
its discrete-time representation is called reconstruction.
Interpolation can be thought of as the reconstruction of
a discrete-time signal from another discrete-time signal,
just as decimation is equivalent to sampling the samples
of a signal. Continuous-time (analog) signal reconstruction and discrete-time (digital) signal reconstruction are
analogous.
Interpolation Filter Structure
Figure 4a shows a block diagram of an interpolation
filter. The two major differences from the decimation
filter are that the interpolator uses a sample rate expander instead of the sample rate compressor and that
the interpolator's low-pass filter is placed after the rate
expander instead of before the rate compressor. The
rate expander, which is the block labeled with an uparrow and L, inserts L-1 zero-valued samples after each
input sample. The resulting w(m) is low-pass filtered to

11-210 APPLICA TION NOTES

x(n)

y(m)

a.
h(O)

y(m)

x(n)
.-1

h(1)
••1

h(2)

•.1

h(3)

I
I

• -1

t

I
I

h(N-1)
~

b.

•

Figure 4. Interpolation Filter Block Diagram
produce y(m), a smoothed, anti-imaged version of w(m).
The transfer function of the interpolator H(k) incorporates a gain of 1/L because the L-1 zeros inserted by the
rate expander cause the energy of each input to be
spread over L output samples.
The low-pass filter of the interpolator uses an FIR filter
structure for the same reasons that an FIR filter is used
in the decimator, notably computational efficiency. The
convolution equation for this filter is
N-l

y(m) = ~ h(k) w(m-k)
k~O

N-1 is the number of filter coefficients (taps) in h(k),
w(m-k) is the rate expanded version of the input x(n),
and w(m-k) is related to x(n) by
w(m-k) = { ~((m-k)IL)

for m-k = 0, ±L, ±2L, ...
otherwise

The signal flowgraph that represents the interpolation
filter is shown in Figure 4b. A delay line of length N is
loaded with an input sample followed by L-1 zeros,

then the next input sample and L-1 zeros, and so on.
The output is the sum of the N products of each sample
from the delay line and its corresponding filter coefficient. The filter calculates an output for every sample,
zero or data, loaded into the delay line.
An example of the interpolator operation is shown in the
signal flowgraph in Figure 5. The contents of the delay
line for three consecutive passes of the filter are highlighted. In this example, the interpolation factor L is 3.
The delay line is N locations long, where N is the number of coefficients of the filter; N=9 in this example.
There are NIL or 3 data samples in the delay line during
each pass. The data samples x(1), x(2), and x(3) in the
first pass are separated by L -1 or 2 zeros inserted by the
rate expander. The zero-valued samples contribute
(L -1 )N/L or 6 zero-valued products to the output result.
These (L-1)N/L multiplications are unnecessary and
waste processor capacity and execution time.
A more efficient interpolation method is to access the
coefficients and the data in a way that eliminates wasted
calculations. This method is accomplished by removing
the rate expander to eliminate the storage of the zerovalued samples and shortening the data delay line from
N to NIL locations. In this implementation, the data delay
line is updated only after L outputs are calculated. The
same NIL (three) data samples are accessed for each set
of L output calculations. Each output calculation accesses every Lth (third) coefficient, skipping the coefficients that correspond to zero-valued data samples.
1ST 2ND 3RD
PASS PASS PASS

x(n)

z·1
z·1
z·1
Z·1

I,0"II 0 II
, ,x(3),I

,IX(2) "I I

Z·1

0

h(2)

0

h(3)

"

"

I IX(2) I I 0

,

"

"

I

I

I I

I I

I

,I

0

0

II 0

0

I 0 I I 0 I IX(2) I 0

h(5)

IX(1)1 I 0 I I 0 I x(2) 0

h(6)

'I

I I

AT L X ('NPUT SAMPLE RATE)

h(4)

0

,
Z·1

0

,I x(3)
,I x(3)

"

Figure 6 shows a flowchart of the interpolation algorithm. The processor waits in a loop and is interrupted at
the output sample rate (L times the input sample rate). In
the interrupt routine, the coefficient address pointer is
decremented by one location so that a new set of interleaved coefficients will be accessed in the next filter
pass. A counter tracks the occurrence of every Lth output; on the Lth output, an input sample is taken and the
coefficient address pointer is set forward L locations,
back to the first set of interleaved coefficients. The output is then calculated with the coefficient address
pointer incremented by L locations to fetch every Lth
coefficient. One restriction in this algorithm is that the
number of filter taps must be an integral multiple of the
interpolation factor; NIL must be an integer.

NO

:~i;;~ (~.,\ (~.,~ x(4) 0 h(O)
t L .......-f,...;..;-f,-i,f--i,-+,-,f-..;...-....;....;........~y(m)
z·1
I 0 I IX(3) I I 0 I 0 x(4) h(1)
z·1

ADSP-2100 Interpolation Algorithm
A circular buffer of length NIL located in data memory
forms the data delay line. Although the convolution
equation accesses the newest data sample first and the
oldest data sample last, the ADSP-2100 fetches data
samples from the circular buffer in the opposite order:
oldest data first, newest data last. To keep the data/coefficient pairs together, the coefficients are stored in program memory in reverse order, e.g., h(N-1) in PM(O)
and h(O) in PM(N-1).

m

I

I 0 I IX(1)1 I 0 I 0 x(2) h(7)
I I I
I 0 II
I I 0 I IX(1lt
, ....' " --......'" ........',
I

0

0

h(8)

~

Figure 5. Example Interpolator Flowgraph
Crochiere and Rabiner refer to this efficient interpolation
filtering method as polyphase filtering, because a different phase of the filter function h(k) (equivalent to a set of
interleaved coefficients) is used to calculate each output
sample.

Figure 6. Interpolation Flowchart

APPLICATION NOTES 11-211

Listing 3 is an ADSP-2100 program that implements this
interpolation algorithm. The ADSP-2100 is capable of
calculating each filter pass in ((N/L)+17) processor instruction cycles. Each pass must be calculated within the
period between output samples, equal to 1/FsL. Thus the
maximum number of taps that can be calculated in real
time is:
1
N=---17L
Fs tCLK

where tCLK is the processor cycle time and Fs is the input
sampling rate.
The interpolation filter has a gain of 1/L in the passband.

11-212 APPLICATION NOTES

One method to attain unity gain is to premultiply
(offline) all the filter coefficients by L. This method requires the maximum coefficient amplitude to be less
than 1/L, otherwise the multiplication overflows the 16bit coefficient word length. If the maximum coefficient
amplitude is not less than 1/L, then you must multiply
each output result by 1/L instead. The code in Listing 4
performs the 16-by-32 bit multiplication needed for this
gain correction. The MY1 register should be initialized to
L at the start of the routine, and the last multiply/accumulate of the filter should be performed with (SS) format, not the rounding option. This code multiplies a
filter output sample in 1.31 format by the gain L, in 16.0
format, and produces in a 1.15 format corrected output
in the SRO register.

{INTERPOLATE.dsp
Real time Direct Form FIR Filter, N taps, uses an efficient algorithm to interpolate
by L for an increase of L times the input sample rate. A restriction on the number
of taps is that NIL be an integer.
INPUT: adc
OUTPUT: dac
.MODULE/RAM/ABS=O interpolate;
.CONST
N=30;
.CONST
L=4;
.CONST
NoverL=75;
.VAR/PM/RAM/CIRC
coef[N);
.VAR/DM/RAM/CIRC
data [NoverL);
.VAR/DM/RAM
counter;
.PORT
adc;
.PORT
dac;
.INIT
coef:;
RTI;
RTI;
RTI;
JUMP sample;

{interpolate by factor of L}

{interrupt
{interrupt
{interrupt
{interrupt

O}
1}
1}
3 at (L *input rate)}

IMASK=b#OOOO;
{disable all interrupts}
ICNTL= b#Ollll;
{edge sensitive interrupts}
SI=l;
{set interpolate counter to 1}
DM(counter)=SI;
{for first data sample}
14="coef;
{setup a circular buffer in PM}
L4=%coef;
M4=L;
{modifier for coef is L}
M5=-1;
{modifier to shift coef back -1}
IO="data;
{setup a circular buffer in OM}
LO=%data;
MO=l;
IMASK=b#1000;
{enable interrupt 3}
{infinite wait loop}
waiUnterrupt:
JUMP waiUnterrupt;
L -_ _ _ _ _ _ _ _ _ Interpolate_ _ _ _ _ _ _ _ _ _ _ _ __
initialize:

sample:

MODIFY(l4,M5);
AYO=DM(counter);
AR=AYO-l;
DM(counter)=AR;
IF NE JUMP do_fir;

{shifts coef pointer back by -1}
{decrement and update counter}
{test and input if L times}

'--_ _ _ _ input data sample, code executed at the sample rate
do_input:

AYO=DM(adc);
DM(lO,MO)=AYO;
MODIFY(l4,M4);
DM(counter)=M4;
'--_ _ _ _filter pass, occurs at L times the input
do_fir:

taploop:

}

{input data sample}
{update delay line with newest}
{shifts coef pointer up by L}
{reset counter to L}
sample rate _ _ _ _.J

CNTR=NoverL - 1;
{N/L-l since round on last tap}
MR=O, MXO=DM(lO,MO), MYO=PM(l4,M4);
DO taploop UNTIL CE;
{N/L-l taps of FIR}
MR=MR+MXO*MYO(SS), MXO=DM(lO,MO), MYO=PM(l4,M4);
MR=MR+MXO*MYO(RND); {last tap with round}
IF MV SAT MR;
{saturate result if overflowed}
DM(dac)=MR1;
{output sample}
RTI;

.ENDMOD;
Listing 3. Efficient Interpolation Filter

APPLICATION NOTES 11-213

II

l'v1X1= rV1R1;
MR= MRO*MY1 (UU);
MRO= MR1;
MR1= MR2;
MR= MR+MX1*MY1 (SU);
SR= LSHIFT MRO BY -1 (LO);
SR= SR OR ASHIFTMR1 BY -1 (HI);
Listing 4. Extended Precision Multiply

Interpolator Hardware Configuration
The 110 hardware required for the interpolation filter is
the same as that for the decimation filter with the exception that the interval timer clocks the output D/A converter, and the input AID converter is clocked by the
interval counter signal divided by L. The interval timer
interrupts the ADSP-21 00 at the output sample rate. This
configuration is shown in Figure 7.

X(I)

y(t')

Figure 7. Interpolation Filter Hardware

11-214 APPLICATION NOTES

AN-219
APPLICATION NOTE

r'IIIANALOG

WDEVICES

ONE TECHNOLOGY WAY. P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062·9106 • 617/329-4700

Electronic Adjustment Made Easy with the TrimDAC™
by Walter Heinzer and Joe Buxton

The TrimDAC" is a multi-channel d/a converter designed specifically for adjusting gains and dc levels in
electronic circuits digitally and without moving parts. It
combines many of the properties of the adjusting
pot(entiometer) with the prospect of hands-off automatic adjustment and high reliability. The highly desirable attributes of TrimDACs include small package size,
many devices per package, serial interface (reduces pin
count) and low power dissipation. TrimDACs in electronic adjustment reduce cost in two ways: the higher
speed of adjustment under software control saves time
and capital investment; and the device itself is quite
cheap.
Most designers of new circuit designs would like to
avoid the once-ubiquitous variable resistor because of
its mechanical sensitivity, relatively wide absolute tolerances, and high labor cost. But there is generally a need
for factory adjustments and calibrations in electronic
equipment. Even digital products need a power supply
adjusted or calibrated to a specified tolerance. And
many electronic systems are connected to real world
sensors or output devices in systems that need calibration. A key issue facing engineers who design such systems is cost reduction of factory calibration and field
maintenance.

individually adjusted, especially for high-resolution
displays. Since the convergence adjustment of CRT display systems with resolutions of more than 1,000 lines
requires that 6 to 8 variable-resistor adjustments be
made in high-volume production-currently by robotcontrolled screwdrivers - displays are ideal candidates
for electronically controlled adjustment devices. The
TrimDAC" offers an attractive alternative to this
mechanical adjustment approach. Previously a labor(human or robot) intensive process taking minutes, the
operation now can be done in seconds.
VOLTAGE ADJUSTMENT, THE FIRST GENERATION
The first TrimDAC, the DAC-8800, is a monolithic CMOS
IC with all the ingredients necessary for general-purpose
dc voltage setting. It contains eight unbuffered voltageoutput d/a converters in a 20-pin skinny DIP package
(Figure 1). The output voltage range, unipolar or bipolar,
can be independently set for each group of four DACs.
Output voltage ranges are established by the choice of
high- and low- external-reference inputs. The 8-bit DACs
provide 256 voltage levels within each range.

II

Electronic factory-calibration of chips by semiconductor
manufacturers is already widely used; calibration and
adjustment problems are solved on (and with) integrated circuits by autozero, self-calibration, Zener-zap,
fuse link, EPROM and laser trim. Something akin to this
in larger-scale real-world systems is highly desirable.
Recognizing this problem, we sought to design products
to fill the need for digitally adjustable electronic devices
to automate, speed up, and eliminate manual and mechanical adjustments.
For example, consider the CRT display; curvature aberrations in the manufacturing of glass tubes require that
the elements of focus (convergence & color purity) be
TrimDAC is a trademark of Analog Devices. Inc.

Figure 1. DAC-8800 Block Diagram. Shared References
Determine Output Voltage Range.
APPLICATION NOTES 11-215

A TTL-compatible 3-wire serial interface loads the contents of the eight internal DAC registers. These can all be
set to zero by an asynchronous Clear (CLR) input, very
handy for system power-up. An internal regulator provides TTL compatibility over a wide range of VDD supply
voltages. Single-supply operation is available by connecting Vss to GND. The device achieves its performance and flexibility with a low 24 mW of dissipation.
The output voltage of each DAC is changed by clocking
an 11-bit word (3 address bits, 8 data bits) into the serial
shift register. The internal logic decodes the three address bits to establish which internal DAC register will
receive the 8 bits of data from the serial register during
the Load (LD) strobe. One DAC is updated with each LD
strobe. At the maximum clock rate of 6.6 MHz, all eight
dla converters can be loaded in as little as 14 microseconds.
The output voltage range is determined by the external
input voltages applied to VREFH and VREFL (Figure 2). If
Vss is negative, VREFL may be set to a negative value;
this results in a programmable bipolar range of output
voltages. The relationship between Vour. and VREFH,
VREFV and the digital input, 0 (a base-10 integer between
o and 255), is:
Vouy(D)

= (0/256)(VREFH -

VREFL )

Second-generation TrimDACs, such as the DAC-8840
and DAC-8841, solve the problem of replacing variable
resistors for adjusting ac or varying dc voltages-for
example, in audio volume control. Other common applications where ac signals must be .attenuated include
some circuits found in video displays, projection-TV
displays, instrumentation, oscilloscopes, medical gear,
modulation circuits, modems, and so on.
The DAC-8840 contains a multiplying DAC structure with
four-quadrant multiplying capability. Figure 3 shows the
connection of one of the eight independent channels of
the DAC-8840. This multiplying channel has a 1-MHz

VOUTX

D,

DAC
REGISTER

Dsl--+---t-.....-t:>-.

+ VREFL

The DAC-8800 is tested for operation with Voo = 12 V
and Vss = 0 V or -5 V. However, it was designed to
operate from a wide variety of available supply-voltage
combinations. Here are some typical pairings: VOll'
Vss = +15 V, 0 V; +12 V, 0 V; +12 V, -5 V; +5 V,-5 V;
+5 V, -12 V; +5 V, 0 V.
The primary application of the DAC-8800 is with fixed
reference inputs for dc voltage setting. Outputs may be
applied directly to high-impedance circuits-or to external op amps for buffering.

:r---....S)Iw--4p-<)

Vour*

~ROUT

R

DAC
REGISTER

ADDING GAIN: THE SECOND GENERATION

D.I-++-.....-I

CONSTANT
INDEPENDENT
OF DIGITAL
INPUT CODE

R

DO

GNDo---4-------~~-J

Figure 3. One Channel of the Four-Quadrant Multiplying
DAC-8840.

bandwidth for ±3-V input signal levels while operating
from ±5-V supplies. A typical signal channel has 0.01%
total harmonic distortion and can slew at 2.5 V/fJ-s. Because the output amplifier is connected in a differencing
(push-pull) configuration, the gain for signals applied to
V,N can range from full-scale positive to full-scale negative, depending on the applied digital (offset binary)
word. The magnitude of the binary word corresponds to
the wiper position of a pot, with zero output at halfscale; a Preset control input sets all DACs to this "zero"
position. Figure 4 describes this serial input CMOS octal
D/A converter in greater detail.
The gain transfer function of a DAC-8840 channel is:
Vour(D)

VREFL

o - - - -......-------'W.......

Figure 2. Simplified Equivalent Voltage-Switching DAC
Circuit. The Output Resistance Remains Constant at a
Nominal 11 kfl.

11-216 APPLICATION NOTES

= (0/128-1)

V'N

where 0 is the value of the binary input, a decimal
integer
between
0
and
255.
At
full-scale,
Vour = 1271128 x V'N; when D = 128 (also the Preset
condition), V our equals zero volts; and when D = zero,
Vour = - V'N·
In the DAC-8840, eight DAC registers store the output
state; they are updated from an internal serial-to-parallel
shift register loaded from a standard 3-wire serial-input

width. AC signals applied to the V'N terminal can be
attenuated to zero or amplified by a factor of up to two,
with 256 possible level settings from zero to 2 x
(255/256) VIN :

DAC-8840

DECODED ADDRESS

Vou.,./D) = 2 x (01256)

8X8

DAC

LOAD

X (VIN -

VREFL )

+ VREFL

•
••

REGISTERS

vour

SD'

J

CLK~~~~~~:::t~=-________________
GND

Vss

SOC

PRESET

Figure 4. DAC-8840 Block Diagram. Note the 3-Wire
Input and Serial Data Output Pin (500) for DaisyChaining Additional Packages.

digital interface. The data word clocked into the serialinput register (SOl) consists of 12 bits; the first four
determine the address of the OAC register to be loaded
with the 8 data-bits. A serial data output pin at the other
end of the shift register (SOO) allows simple daisychaining in multiple OAC applications without additional
external decoding logic (Figure 5). The fourth address
bit, which decodes as a NOP for the package, makes it
possible to select a single OAC in one of the packages to
be updated when all the packages receive the common
LO OAC strobe signal.

,C
PAD

DATA

CLOCK
PAl

LD
PA'

SD'

DACA

CLK

DAC-8840#1
LD
SDO

DACH

SD,

DACA

•
•

•

CLK

DAC-8840#2
LD
SOC

DACH

SDI • DACA

CLK

DAC-8840 tI3
LO
SDO

DACH

Figure 5. DAC-8840s in a Serial Daisy Chain Minimize
Chip Decoders.

The OAC-8841, a mask option of the OAC-8840, offers an
ideal octal OAC for +5-V single-supply applications. The
OAC and amplifier of each channel are configured as
shown in Figure 6, with the amplifier connected for a
non-inverting gain of two. This configuration is a
2-quadrant multiplying arrangement with a 1-MHz band-

Figure 6. Internal Connections of the +5-V-only DAC-

8841.
VARIABLE RESISTORS VERSUS TRIMDACS
From the above overview of the OAC-8800 and OAC8840/41 TrimOACs, we can compare them to mechanically variable resistors (pots), reviewing the strengths
and weaknesses of each.
Advantages of TrimDACs over Potentiometers: Better
mechanical stability, improved product life, improved
temperature coefficients, smaller size; computer control
can eliminate technician costs; remote operation, constant output resistance, and low output resistance with
low power dissipation.
Advantages of Potentiometers over TrimDACs: Voltage
range usually much greater, no separate power supply
required, simple human interface, no memory required,
no "zipper noise" (the sound heard when using a OAC to
adjust audio levels).
Another useful advantage of the potentiometer at
present is a nonvolatile memory. That is, in a vibrationfree environment, the wiper of the potentiometer stays
where it was last set, even with the power off. The
TrimOAC'" devices described here do not contain nonvolatile memory; for them, the required memory is generally supplied by system E2 PROM. Since in many of
today's systems a low-cost high-density E2 PROM holds
system set points for current time, date, mode, parameters and so on, it is an easy matter to share this nonvolatile memory with the TrimOAC calibration set points;
they are reloaded at system powerup.
TYPICAL APPLICATIONS
In professional audio equipment, voltage-controlled amplifiers (VCA) are used to set gain, fade, pan and mix
signals. The dc control inputs of these VCAs are ideally
controlled by the OAC-8800 (Figure 7). The addition of
the capacitor at the VCA voltage control port, VC, helps
to limit the slew rate, reducing the clicking to a subaudible level. One OAC-8800 can control 8 channels of logarithmically set gain and attenuation levels.

APPLICATION NOTES 11-217

II

GAIN-ct8vs.Vc

..
~·"rn·
•

,t

-"-1.2

0

+1.2

For video convergence and deflection control, especially
in multi-sync displays, the DAC-8840 can be used to
adjust the sawtooth waveform amplitudes, their reference bias voltages, and the parabolic waveforms used to
linearize them as they are summed together to drive the
CRT deflection. Figure 9 shows a block diagram of a
typical arrangement.

Vc -Va'"
SERIAl

CONTROL

Figure 7. Setting Gain of a Voltage,Controlled Amplifier
in Professional Audio Equipment. One DAC-8800 Can
Serve 8 Channels. The Damping Capacitor at the Voltage C
Control Point Minimizes Zipper Noise by Slowing Rates
of Gain Change to Subaudio Frequencies.
Figure 8 shows a selection of output configurations of a
DAC-8800, including simple buffers, summing circuits
with coarse/fine control, and adding gain for increased
output swing. A DAC-8800 can be used in system offset
nulling by connecting its output to the summing node of
any convenient op amp, using an appropriate value of
summing resistance or aT-network.

Figure 9. DAC-8840's Four-Quadrant Multiplying Capability Simplifies Amplitude Adjustment of Waveform
Components in Video Deflection.
Availability
The 20-pin DAC-8800, and the 24-pin DAC-8840 and
DAC-8841 are ayailable for two temperature ranges-extended industrial (-40°C to +85°C) and military (-55°C
to +125°C). Packaging includes plastic and ceramic DIPs
and SOL surface-mount packages.
The DAC-8800 was designed by Patrick Copley, who
also-with Jim Brubaker-designed the DAC-8840 &
DAC-8841 at the Precision Monolithics Division of Analog Devices, Santa Clara, CA.

DIGITAL INTERFACING ownED FOR CLARITY.
R, =,oo~u. R2 ;: 10kU

",

Figure 8. Some Ways of Buffering the DAC-8800 Output.

11-218 APPLICA TlON NOTES

Package Information
Contents
ADI Letter
Designator

MIL-M38510
Applicable
ConfJgUration

PMI Letter
Designator

Package
Description

P
P
P
P
P
P
P
P
P
P
P

8-Lead
14-Lead
16-Lead
18-Lead
20-Lead
22-Lead
24-Lead (Narrow Body)
28-Lead
28-Lead
4O-Lead
48-Lead

12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-10
12-11
12-12
12-13

S
S
S
S

8-Lead (Narrow Body)
8-Lead (Narrow Body)
14-Lead (Narrow Body)
16-Lead (Wide Body)
16-Lead (Narrow Body)
20-Lead (Wide Body)
24-Lead (Wide Body)
28-Lead (Wide Body)

12-14
12-15
12-16
12-17
12-18
12-19
12-20
12-21

Z
Y
Q
R
W
T

8-Lead
14-Lead
16-Lead
20-Lead
24-Lead (Narrow Body)
28-Lead

Page

Plastic DIP
N-8
N-14
N-16
N-18
N-20
N-24
N-28
N-28A
N-40A
Small Outline (SOlC)
R-8
R-14
R-16
R-I6A
R-20
R-24
R-28

S
S

Cerdip
Q-8
Q-14
Q-16
Q-20
Q-24
Q-28

0401

Dl-l
02-1
D8-1
03-1

DlO-l

12-22
12-23
12-24
12-25
12-26
12-27

Metal Can
8-Lead (TO-99)
12-Lead (TO-8)

H-08A
H-12A

12-28
12-29

Leadless Chip Carrier (Ceramic)
E-20A
E-28A
E-68A

RC
TC

20-Terminal
28-Terminal
68-Terminal

C-2
C-4
C-7

12-30
12-31
12-32

Leaded Chip Carrier (Gull Wing)
Z-68

68-Lead Leaded Chip Carrier (Ceramic)

12-33

20-Lead
28-Lead
44-Lead
68-Lead

12-34
12-35
12-36
12-37

Plastic Leaded Chip Carrier
(pLCC)
P-20A
P-28A
P-44A
P-68A

PC
PC

PACKAGE INFORMATION 12-1

m

ADI Letter
Designator

PMI Letter
Designator

Package
Description

MIL-M38510
Applicable
ConfJgll1'lltion

Page

J-Leaded Chip Carrier
J-28

28-Lead

12-38

28-Lead

12-39

68-Lead
l00-Lead
223-Lead

12-40
12-41
12-42

IOO-Lead

12-43

100-Lead

12-44

223-Lead

12-45

Side Brazed DIP (Ceramic)
D-28A

Pin Grid Array
o.68A
G-l00A
0.223
Plastic Quad Flat Pack
P-I00
Ceramic Quad Flat Pack
Z-I00
Plastic Pin Grid Array
223

12-2 PACKAGE INFORMATION

Package Outline Dimensions
N-8
8-Lead Plastic DIP

b

SYMBOL
A
A2
b
b,
c
0
E
E,

e
L
L,
Q

e

INCHES
MIN
MAX

MILLIMETERS
MIN
MAX

0.210
0.115
0.195
0.014
0.022
0.045
0.070
0.008
0.015
0.348
0.430
0.300
0.325
0.240
0.280
0.100BSC
0.125
0.200
0.150
0.015
0.060

5.33
4.95
2.93
0.356
0.558
1.15
1.77
0.204
0.381
8.84
10.92
8.25
7.62
6.10
7.11
2.54BSC
3.18
5.05
3.81
0.38
1.52

b,

NOTES

NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold flash or
protrusions.

2
2

PACKAGE INFORMATION 12-3

N-14
14-Lead Plastic DIP

T

SEE
NOTE 1

"

E,

7-.l
. .' - r r. .

~TO~rr

~

~D~

T~Q
J-......
t'
~
1111
+

SEATING
•
PLANE - - - . -

b

SYMBOL
A
Az
b
b,
c
D
E

E,
e
L
L,

a

-

..j \--

-

-

-

-

-l e ~ ~ ~ b,

INCHES
MIN
MAX

MILLIMETERS
MAX
MIN

0.210
0.115
0.195
0.014
0.022
0.045
0.070
0.008
0.015
0.725
0.795
0.300
0.325
0.240
0.280
0.100 BSC
0.125
0.200
0.150
0.015
0.060

5.33
4.95
2.93
0.558
0.356
1.77
1.15
0.381
0.204
20.19
18.42
8.25
7.62
7.11
6.10
2.54BSC
5.05
3.18
3.81
1.52
0.38

12-4 PACKAGE INFORMATION

-

NOTES

NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold flash or
protrusions.

2
2

N-16
16-Lead Plastic DIP

SYMBOL
A
A2
b
b,
c
0
E
E,

e
L
L,
Q

INCHES
MIN
MAX

MILLIMETERS
MIN
MAX

0.210
0.115
0.195
0.014
0.022
0.045
0.070
0.008
0.015
0.745
0.840
0.300
0.325
0.240
0.280
0.100BSC
0.125
0.200
0.150
0.015
0.060

5.33
4.95
2.93
0.356
0.558
1.77
1.15
0.204
0.381
21.33
18.93
7.62
8.25
7.11
6.10
2.54BSC
3.18
5.05
3.81
0.38
1.52

NOTES

NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold fla$h or
protrusions.

2
2

PACKAGE INFORMATION 12-5

IS-Lead Epoxy DIP
(P) Suffix

T

~::::::::II
~
D

(

1 ~-!-r
IIII TL

SEATING
E

PLAN---.-

~j.-b

INCHES
SYMBOL

b
b,
c
D

E
E,

e

MAX

0.014
0.045

0.210
0.022
0.070

0.356
1.15

0.008
0.845
0.240
0.300

0.015
0.925
0.280
0.325

0.20
21.46
6.10
7.62

MIN

MAX

0.38
23.49
7.11
8.25

0.100 BSC
0.115 0.160

2.54 BSC
2.92
4.06
3.30

L,

0.130
0.015

a

0-

0.38
15°

12-6 PACKAGE INFORMATION

0-

NOTES

5.33
0.558
1.77

L
Q

E,

I
c

i-{J

MILLIMETERS

MIN

A

:"H:~

-I. fo-

1',= :::,1

15°

3
3
2

NOTES
1. Minor changes in dimensions may occur without
advance notice.
2. Dimensions "E," to center of leads when formed
parallel.
3. D and E dimensions do not include mold flash or
protrusion.

N-20
20-Lead Plastic DIP

SYMBOL

A
A.
b
b,

c
D

E
E,

e
L
L,
Q

INCHES
MIN
MAX

MILLIMETERS
MIN
MAX

0.210
0.115
0.195
0.014
0.022
0.045
0.070
0.008
0.015
0.925
1.060
0.300
0.325
0.240
0.280
0.100BSC
0.125
0.200
0.150
0.015
0.060

5.33
2.93
4.95
0.356
0.558
1.77
1.15
0.204
0.381
23.50
26.90
7.62
8.25
6.10
7.11
2.54BSC
5.05
3.18
3.81
0.38
1.52

NOTES

NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold flash or
protrusions.

2
2

PACKAGE INFORMATION 12-7

22-Pin Plastic DIP

INCHES
SYMBOL

MIN

MAX

MILLIMETERS
MIN

0.210

A

MAX

5.33

A2

0.115

0.195

2.93

4.95

b

0.014

0.022

0.356

0.558

b,

0.045

0.070

1.15

1.77

C

0.008

0.015

0.204

0.381

0

1.020

1.080

E

0.300

0.325

7.62

8.25

E,

0.240

0.280

6.10

7.11

e

0.100 BSC

L

0.115

Q

0.015

0.160

12-8 PACKAGE INFORMATION

2.54 BSC
2.93
0.38

4.06

NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.

2. The dimension does not include mold flash or
protrusions.

N-24
24-Lead Plastic DIP

SYMBOL

A
A.
b
b,

c
D

E
E,

e
L
L,
Q

INCHES
MIN
MAX

MILLIMETERS
MIN
MAX

0.210
0.115
0.195
0.014
0.022
0.045
0.070
0.008
0.015
1.125
1.275
0.300
0.325
0.240
0.280
0.100BSC
0.200
0.125
0.150
0.015
0.060

5.33
2.93
4.95
0.558
0.356
1.77
1.15
0.204
0.381
32.30
28.60
7.62
8.25
7.11
6.10
2.S4BSC
3.18
5.05
3.81
0.38
1.52

NOTES

NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold flash or
protrusions.

2
2

PACKAGE INFORMATION 12-9

N-28
28-Lead Plastic DIP

SEATING
PLANE

SYMBOL
A
A2
b
b,

c
D

E
E,
e
L
L,
Q

INCHES
MIN
MAX

MILLIMETERS
MAX
MIN

0.250
0.195
0.022
0.070
0.008
0.015
1.565
1.380
0.600
0.625
0.485
0.580
0.100BSC
0.125
0.200
0.150
0.015
0.060

6.35
4.95
0.558
1.77
0.381
0.204
35.10
39.70
15.24
15.87
12.32
14.73
2.54BSC
3.18
5.05
3.81
1.52
0.38

0.125
0.014

12-10 PACKAGE INFORMATION

NOTES

NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. This dimension does not include mold flash or
protrusions.

3.18
0.356

2
2

N-28A
28-Pin Plastic DIP

28

"

14

~

SYMBOL
A
b
c
D
E
E,
e
L
Q
(I

1
1
E

SEE
NOTE 1

INCHES
MIN
MAX
0.015
0.008
1.440
0.530
0.594
0.096
0.120
0.020
0°

·1

D

0.200
0.020
0.012
1.450
0.550
0.606
0.105
0.175
0.060
15°

MILLIMETERS
MIN
MAX
0.381
0.203
35.580
13.470
15.090
2.420
3.050
0.560
0°

5.080
0.508
0.305
36.830
13.970
15.400
2.670
4.450
1.580
15°

NOTES
3
3

2
4

NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. Lead center when .. is 0°. E, shall be measured at the
centerline of the leads.
3. All leads - increase maximum limit by 0.003" (0.08mml
measured at the center of the flat. when hot solder
dip lead finish is applied.
4. Twenty-six spaces.

PACKAGE INFORMATION 12-11

N-40A
40-Pin Plastic DIP

40

21

20

~

~

-~-tL=1
-.l • \.b-.j~

r.

~

-I

E

tr-"~

- - - l o t . ..J.,'fr
NOTE:
LEADS ARE SOLDER-PLATED KOVAR OR ALLOY 42

SYMBOL
A
b
b,

c
D
E
E1

•L

L1
Q

S
S1
II

12-12 PACKAGE INFORMATION

INCHES
MIN
MAX

MILLIMETERS
MIN
MAX

-

-

0.200
0.025
0.060
0.015
2.08
0.550
0.550
0.580
0.620
0.100BSC
0.120
0.175
0.140
0.015
0.060
0.110
0.015
0.040
0.008

-

-

-

O.DOS
0-

15°

5.08
0.64
1.52
0.38
52.83
13.46
13.97
14.73
15.75
2.54BSC
4.45
3.05
3.56
0.38
1.52
2.79
0.13
015°
0.38
1.02
0.20

-

-

-

b,

48-Pin Plastic DIP

~

~

D

T~
- - - - - -- - - - - -- - - -- -- -- - - -T
A

~

.

s~:~-t-

~~

~.~

t

INCHES
SYMBOL

JLb'

E----t

MIN

A

MAX

MILLIMETERS
MIN

0.25

b

0.014

b.
C

MAX
6.35

0.022

0.36

0.59

0.030

0.070

0.77

1.77

0.008

0.015

0.20

0.38

D

2.385

2.480

60.7

63.1

E

0.485

0.580

12.32

14.73

E,

0.590

0.630

15.0

16.0

•

2.54 BSC

0.100 BSC

L

0.115

0.200

2.93

Q

0.015

0.39

S,

0.005

0.13

II

0"

15°

0"

5.08

15°

PACKAGE INFORMATION 12-13

R-8
8-Lead Small Outline (SOIC)

SYMBOL
A
B
C
D

F
G
J
K

L
P

12-14 PACKAGE INFORMATION

INCHES
MIN
MAX

MILUMETERS
MIN
MAX

0.188
0.198
0.150
0.158
0.089
0.107
0.014
0.022
0.018
0.034
0.050BSC
0.007
0.015
0.011
0.005
0.195
0.205
0.224
0.248

4.77
5.03
3.81
4.01
2.26
2.72
0.36
0.56
0.46
0.86
1.27BSC
0.18
0.38
0.125
0.275
4.95
5.21
6.29
5.69

SO-8
8-Lead Narrow-Body SO
(S-Suffix)

PLANE

SYMBOL

MIN

INCHES
MAX

MILLIMETERS
MIN
MAX

A

0.0532

0.0688

1.35

1.75

b

0.0138

0.0192

0.35

0.49

c

0.0075

0.0098

0.19

0.25
5.00

0

0.1890

0.1968

4.80

E

0.1497

0.1574

3.80

4.00

H

0.2284

0.2440

5.80

6.20

0.0500 BSC

e

NOTES

NOTES
1. Package dimensions conform to JEDEC specification
MS-012-AA (Issue A. June 1985).
2. Index area; a dimple or lead one identification mark is
located adjacent to lead one and is within the shaded
area shown.

1.27 BSC

h

0.0099

0.0196

0.25

0.50

L

0.0160

0.0500

0.41

1.27

a

0.0040

0.0098

0.10

0.25

0<

0°

8°

0°

8°

PACKAGE INFORMATION 12-15

80-14
14-Lead Narrow-Body SO
(S-Suff1x)

SEE
NOTE 2

F14~~.~
nI
E H

'~.~!J
aLtU U0 UU0 oII
r-..je~

SYMBOL

MIN

INCHES
MAX

MILLIMETERS
MIN
MAX

.A

0.0532

0.0688

1.35

1.75

b

0.0138

0.0192

0.35

0.49

c

0.0075

0.0098

0.19

0.25

0

0.3367

0.3444

8.55

8.75

E

0.1497

0.1574

3.80

4.00

H

0.2284

0.2440

5.80

6.20

0.0500 BSC

e

1.27 BSC

h

0.0099

0.0196

0.25

0.50

L

0.0160

0.0500

0.41

1.27

Q

0.0040

0.0098

0.10

0.25

0<

0°

8°

o·

So

12-16 PACKAGE INFORMATION

SEATING
PLANE

NOTES

ctJr=t\
f

-..j~,\
b

h x 45"

"11-

ISEE DETAIL
ABOVE

NOTES
1. Package dimensions conform to JEDEC specification
MS·012·AB (Issue A, June 19851.
2. Index area; a dimple or lead one identification mark is
located adjacent to lead one and is within the shaded
area shown.

R-16 (S-Suffix)
16-Lead Wide-Body SO
(SOL-16)

hx45°

1;-1-"---~

c.tJ (
SEATING
PLANE

SYMBOL

MIN

INCHES
MAX

MILLIMETERS
MIN
MAX

A

0:0926

0.1043

2.35

2.65

b

0.0138

0.0192

0.35

0.49

c

0.0091

0.0125

0.23

0.32

0

0.3977

0.4133

10.10

10.50

E

0.2914

0.2992

7.40

7.60

H

0.3937

0.4193

10.00

10.65

0.0500 BSC

e

NOTES

)~.../~14-

SEE DETAIL
ABOVE

NOTES
1. Package dimensions conform to JEDEC specification
MS-013-AA (Issue A. June 19851.
2. Index area; a dimple or lead one identification mark is
located adjacent to lead one and is within the shaded
area shown.

1.27 BSC

h

0.0098

0.0291

0.25

0.74

L

0.0157

0.0500

0.40

1.27

Q

0.0040

0.0118

0.10

0.30

IX

0°

8°

0°

8°

II

PACKAGE INFORMATION 12-17

R·16A (S·Suffix)
16·Lead Narrow Body 50
(50·16)

SYMBOL

MIN

INCHES
MAX

MILLIMETERS
MIN
MAX

A

0.0532

0.0688

1.35

1.75

b

0.0138

0.0192

0.35

0.49

c

0.0075

0.0099

0.19

0.25

D

0.3859

0.3937

9.80

10.00

E

0.1497

0.1574

3.80

4.00

H

0.2284

0.2440

5.80

6.20

0.0500 BSC

e
h

0.0099

0.0196

1.27 BSC
0.25

0.50

L

0.0160

0.0500

0.41

1.27

a

0.0040

0.0098

0.10

0.25

Ot

0"

8"

0"

8"

12-18 PACKAGE INFORMATION

NOTES

NOTES
1. Package dimensions conform to JEDEC specification
MS-012-AC (Issue A. June 1985).
2. Index area; a dimple or lead one identification mark is
located adjacent to lead one and is within the shaded
area shown.

R-20 (S-Suffix)
20-Lead Wide-Body SO
(SOL-20)

rr=F=======f=;)t
-.I!4SEATING
PLANE

SYMBOL

MIN

INCHES
MAX

MILLIMETERS
MIN
MAX

A

0.0926

0.1043

2.35

2.65

b

0.0138

0.0192

0.35

0.49

c

0.0091

0.0125

0.23

0.32
13.00

0

0.4961

0.5118

12.60

E

0.2914

0.2992

7.40

7.60

H

0.3937

0.4193

10.00

10.65

e

0.0500 BSC

NOTES

SEE DETAIL
ABOVE

NOTES
1. Package dimensions conform to JEDEC specification
MS-013-AC (Issue A. June 19851.
2. Index area; a dimple or lead one identification mark is
located adjacent to lead one and is within the shaded
area shown.

1.27 BSC

h

0.0098

0.0291

0.25

0.74

L

0.0157

0.0500

0.40

1.27

Q

0.0040

0.0118

0.10

0.30

III

0°

8°

0°

SO

PACKAGE INFORMATION 12-19

R-24 (S-Sufflx)
24-Lead Wide-Body SO
(SOL-24)

"m \1\
=-!/ - - - .........

E

~

b

MIN

INCHES
MAX

MILLIMETERS
MIN
MAX

A

0.0926

0.1043

2.35

2.65

b

0.0138

0.0192

0.35

0.49

c

0.0091

0.0125

0.23

0.32

0

0.5985

0.6141

15.20

15.60

E

0.2914

0.2992

7.40

7.60

H

0.3937

0.4193

10.00

10.65

0.0500 BSC

e

1.27 BSC

h

0.0098

0.0291

0.25

0.74

L

0.0157

0.0500

0.40

1.27

a

0.0040

0.0118

0.10

0.30

00

80

00

80

..

12-20 PACKAGE INFORMA TlON

\

SEATING
PLANE

NOTES

\

L~/

J

'--_/

h x 45 0

11'--

c.iJ (

Q

SYMBOL

I

H

h~~

--114-

SEE DETAIL
ABOVE

NOTES
1. Package dimensions conform to JEDEC specification
MS-013-AD (Issue A. June 1985).
2. Index area; a dimple or lead one identification mark is
located adjacent to lead one and is within the shaded
area shown.

R-28 (S-Suffix)
28-Lead Wide-Body SO
(SOL-28)

"m
~~~,,~
I·
,---------It
1;--~----,
QiJb uu
Wl i) (
)~

~

EH

.-

~

UZlLU 0
eUt-- [QJ ~lLD
t-b

SYMBOL

MIN

INCHES
MAX

MILLIMETERS
MIN
MAX

A

0.0926

0.1043

2.35

b

0.0138

0.0192

0.35

0.49

c

0.0091

0.0125

0.23

0.32
18.10

2.65

0

0.6969

0.7125

17.70

E

0.2914

0.2992

7.40

7.60

H

0.3937

0.4193

10.00

10.65

0.0500 BSC

e

\

c.

SEATING
PLANE

NOTES

...jlh.j4-

SEE DETAIL
ABOVE

NOTES
1. Package dimensions conform to JEDEC specification
MS-013-AE (Issue A. June 1985).
2. Index area; a dimple or lead one identification mark is
located adjacent to lead one and is within the shaded
area shown.

1.27 BSC

h

0.0098

0.0291

0.25

0.74

L

0.0157

0.0500

0.40

1.27

Q

0.0040

0.0118

0.10

0.30

Ot

0°

8°

0°

8°

PACKAGE INFORMATION 12-21

Q-8
8-Lead Cerdip

1~S'
4

SYMBOL

A
b
b,
c
D
E
E,
e
L
L,
Q

S
S,
II

MIN

INCHES
MAX

MIWMETERS
MIN
MAX

0.200
0.023
0.070
0.015
0.405
0.310
0.320
0.110
0.200

5.08
0.58
1.78
0.38
10.29
7.87
8.13
2.79
5.08

0.014
0.030
0.008
0.220
0.290
0.090
0.125
0.150
0.015
0.005
0"

0.060
0.055
15°

0. •
0.76
0.20
5.5'
7.37
2.2'
3.18
3.81
0.38
0.13
0"

12-22 PACKAGE INFORMA TION

1.52
1.35
15°

NOTES
7
2.7
7
4
4
6
8

3
5
5

NOTES
1. Index area; a notch or a lead one identificalion mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.5Bmml for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid. meniscus
and glass overrun.
5. Applies to all four corners.
6. Lead center when II is 0·. E, shall be measured at the
centerline of the leads.
7. All leads - increase maximum limit by 0.003"(0.OBmml
measured at the center of the flat. when hot solder
dip lead finish is applied.
B. Six spaces.

Q-14
14-Lead Cerdip

SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q

MIN

INCHES
MAX

MILUMETERS
MIN
MAX

0._
0.023
0.070
0.015
0.785
0.310
0.320
0.110
0._

5.08
0.58
1.71
0.38
19.94.
7.87
8.13
2.79
5.08

0.014
0.030
0.008
0.220
0.290
0.090
0.125
0.150
0.015

S
S,

0.005

a

0"

0.060
0.098

0••
0.76
0.20
5.59
7.37
2.29
3.18
3.81
0.38

1.52
2.49

0.13
15°

0"

NOTES
7
2.7
7
4
4
6

8

3
5
5

NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(O.58mml for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the bese plane.
4. This dimension allows for off-center lid. meniscus
and glass overrun.
5. Applies to all four corners.
6. Lead center when a Is 0". E, shall be measured at the
centerline of the leads.
7. All leads - increase maximum limit by 0.003" (0.08mml
measured at the center of the flat. when hot solder
dip lead finish is applied.
8. Twelve spaces.

15°

PACKAGE INFORMATION 12-23

Q-16
16-Lead Cerdip

11-- s,

-.j

r-

S

~i:I. :::::::J.1
'MW:
SfA~-P~-h- t -1
~~
~ JL.. ~.
D

I

L

'

.

I

E,

-01.

.-01-

SEE
NOTE 7

SYMBOL

MIN

INCHES
MAX

MIWMETERS
MIN
MAX

0.200
0.023
0.070
0.015
0.840
0.310
0.320
0.110
0.200

5.08
0.58
1.71
0.38
21.34
7.•7
•. 13
2.79
5.08

A

b
b,
c
D
E
E,
e
L
L,

0.014
0.030
0.008

Q

0.220
0.290
0.090
0.125
0.150
0.015

S
S,
ex

0.005
0"

0._
0._
15°

12-24 PACKAGE INFORMATION

0.38
0.71
0.20
5.59
7.37
2.29
3.1.
3•• '
0.38
0.13
0"

1.52
2.03
15°

NOTES

7
2.7
7
4
4
6

•
3
5
5

NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(O.58mml for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid. meniscus
and gla$s overrun.
5. Applies to all four corners.
6. Lead center when ex is 0". E, shall be measured at the
centerline of the leads.
7. All leads - increase maximum limit by.0.003"(0.08mml
measured at the center of the flat. when hot solder
dip lead finish is applied.
8. Fourteen spaces.

Q-20
20·Lead Cerdip

.,

~S,

-.j

r-S

~4:I. :::::::::l-I
D

r-~--------------~

NOTE 7

INCHES .
SYMBOL

MIN

A
b
b,

0.014
0.030

c

D• •

D
E
E,

•L
L,
Q

0.220
0.290
0._
0.125
0.150
0.015

S
S,

O.OOS

II

0"

MAX
O.ZOO
0. •
0.070
0.015
1• •
0.310
0.320
0.110
0.200

0• •
0._

MIWMETERS
MIN
MAX
0.38
0.78
0.20

5.08
0.58
1.78
0.38
21.12

5.58
7.37
2.21
3.18
3.81
.0.38

7.87
8.13
2.71
5.08
1.52
2.41

0.13
15·

0"

NOTES
7
2,7
7
4
4
8
8

3
5
5

NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to leed one.
2. The minimum limit for dimension b, may be 0.023"
10.58mml for all four comer leeds only.
3. Dimension Q shall be measured from the seating plane
to the bese plane.
4. This dimension allows for off·center lid, meniscus
and glall overrun.
5. Applies to all four corners.
8. Lead center when II is 0". E, shall be measuradat the
centerline of the leads.
7. All leeds - increase maximum limit by O.OO3"IO.Olmm)
measurad at the center of the flat, when hot solder
dip leed finish is appliad.
8. Eighteen spaces.

15°

PACKAGE INFORMA nON 12-25

Q-24
24-Lead.Cerdip

-11-- s,

r-

-t

~i:::::::::::
:1
ID.

t···

PlANE

SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q

MIN

0.014
0.030
0.008
0.220
0.290
0.090
0.125
0.150
0.015

S
S,

0.005

CI

0-

0.200
0.023
0.070
0.015
1.260
0.310
0.320
0.110
0.200
·0.060
0.098

-l • IMIWMETERS
MIN
MAX
0.36
0.71
0.20
5.59
7.37
2.29
3.18
3.81
0.38

5.08
0.58
1.78
0.38
32.51
7.87
8.13
2.79
5.08
1.52
2 ....

0.13
15°

12-26 PACKAGE INFORMA TION

.

I

tb-1IINCHES
MAX

~

S

0-

15°

NOTES
7

2,7
7
4
4
I

8

3
5
5

JLb'

~.

I

E,

,..\\0-

SEE
NOTE 7

NOTES
1. Index area; a notch or a leild one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(O.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid, meniscus
and glasS· overrun.
5. Applies to all four corners.
I. Lead center when CI is 0°. E, shall be measured at the
centerline of the leads.
.
7. All leads - increase maximum limit by 0.003"(0.08mm)
measured at the center of the flat, when hot solder
dip lead finish is applied.
8. Twenty-two spaces.

Q-28
28-Lead Cerdip

11- s,
28

SYMBOL
A
b
b,
c
D
E
E,
e
L
L,
Q

MIN

INCHES
MAX

MILLIMETERS
MIN
MAX

0.225
0.026
0.070
0.018
1.490
0.610
0.620
0.110
0.200

5.72
0.66
1.78
0.46
37.85
15.49
15.75
2.79
5.08

0.014
0.030
0.008
0.500
0.590
0.090
0.125
0.150
0.015

0.36
0.76
0.20
12.70
14.99
2.29
3.18
3.81
0.38

0.100

S
S,

0.005

ex

cr

15°

2.54
0.13
0°

NOTES
7
2,7
7
4
4

6
8

3
5
5

NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(O.58mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid, meniscus
and glass overrun.
5. Applies to all four corners.
6. Lead center when u is 0°. E, shall be measured at the
centerline of the leads.
7. All leads - increase maximum limit by 0.003"(0.08mm)
measured at the center of the flat, when hot solder
dip lead finish is applied.
8. Twenty-six spaces.

15°

PACKAGE INFORMATION 12-27

H-OSA
8-Lead Metal Can (TO-99)

SYMBOL
A
+b
b,
D
D,
+D2
e
e,
F

k
k,
L
L,
L2
Q

a

INCHES
MAX

MILLIMETERS
MIN
MAX

0.166
0.185
0;016
0.019
0.016
0.021
0.335
0.370
0.305
0.335
0.110
0.160
0.200.BSC
0.100BSC
0.040
0.027
0.034
0.027
0.045
0.500
0.750
0.050
0.250
0.010
0.045
45°BSC

4.19
4.70
0.41
0.48
0.41
0.53
8.51
9.40
7.75
8.51
2.79
4.06
5.08BSC

MIN

12-28 PACKAGE INFORMATION

2.~BSC

0:69
0.69
12•.70

NOTES
1,4
1,4

3
3

1.02
0.86
1.14
19.05
1.27

6.35
0.25
1.14
45°BSC

3

NOTES
1. (All leads) b applies between L, and L2. b, applies
between L2 and 0.500" (12.70mm) from the reference
plane. Diameter is uncontrolled in L, and beyond 0.500"
(12.70mm) from the reference plane.
2. Measured from the maximum diameter of the
product.
3. Leads having a maximum diameter 0.019" (O.48mm)
measued in gauging plane 0.054" (1.37mm) + 0.001"
(0.03mm) - 0.000" (O.OOmm) below the base plane of
the product are within 0.007" (0.18mm) of their true
position relative to the maximum width tab.
4. All leads - increase maximum limit 0.003" (0.08mm)·
when hot solder dip finish is applied.

H-12A
12-Lead Metal Can (TO-S Style)

SYMBOL
A
+b
+b,
+D
+D,
e
e,
8z
F
k
k,
L
L,
Q

MIN

INCHES
MAX

0.148
0.181
0.018
0.019
0.018
0.021
0.592
0.810
0.545
0.555
O.400BSC
O.200BSC
0.100BSC
0.040
0.028
0.038
0.028
0.038
0.375
0.050
0.010
0.046

MIWMETERS
MIN
MAX
3.76
0.41
0.41
15.04
13.84

4.60
0.48
0.53
15.44
14.10

NOTES
1
1

3
3
3
0.88
0.88
9.50
G.25

1.02
0.91
0.91
1.27
1.14

NOTES
1. (All leads) +b applies between Land L,. +b, applies
between L, and 0.375" (9.50mm) from the reference
plane. Diameter is uncontrolled in L, and beyond 0.375"
(9.50mm) from the reference plane.
2. Measured from the maximum diameter of the
product.
3. Leads having a maximum diameter 0.019" (O.48mm)
measued in gauging plane 0.054" (1.37mm) + 0.001"
(O.03mm) - 0.000" (O.OOmm) below the base plane of
the product is within 0.007" (0.18mm) of their true
position relative to the maximum width tab.

2
1
1

PACKAGE INFORMATION 12-29

E-20A
20·Terminal Leadless Ceramic Chip Carrier

BOTTOM VIEW

Ihx45°'
3PLACES

L

-1.
TTl'

I

T"T
~D

Iix450 '

•

I IH HHHHill
SYMBOL
A
B,

D
D,
e
j
h
L

MIN

INCHES
MAX

0.064
0.100
0.022
0.028
0.358
0.342
0.075 REF
O.05OBSC
0.020 REF
O.D4DREF
0.045
0.055

12-30 PACKAGE INFORMATION

MILUMETERS
MIN
MAX
1.63
0.56

2.54
0.71
8.69
9.09
1.91 REF
1.27BSC
0.51
1.02
1.40
1.14

NOTES
1
2

NOTES

•

1. Dimension A con1rols the overall package thlckne...
2. Applies to all 4 sides.
3. All terminals are gold plated.

E-28A
28-Terminal Leadless Ceramic Chip Carrier

--1

fB,

.L

......

e

NO.1 PIN INDEX

r
(hX45o)L
3 PLACES

BOTTOM VIEW

.....l

I

P
I

'f

D

Ii x 45°)

IIHHHHHHHlli

SYMBOL
A
B,
D
D,

e
j
h
L

INCHES
MAX

MILLIMETERS
MIN
MAX

0.064
0.100
0.028
0.022
0.442
0.458
0.075 REF
O.050BSC
0.020 REF
0.040 REF
0.045 I 0.055

2.54
1.63
0.71
0.56
11.23
11.63
1.91 REF
1.27BSC
0.51
1.02
1.14
I 1.40

MIN

NOTES
1
2

NOTES

1. Dimension A controls the overall package thickness.
2. Applies to all 4 sides.
3. All terminals are gold plated.

II

PACKAGE INFORMA TION

72-37

E-68A
68-Tenninal Leaclless Chip Carrier

"

e

NO.1 PIN INDEX

t

BOTTOM
VIEW

IhX450l
3PLACES

L
f .~

....l
pli

D

IIMMM'MMMMMMMMHtlM'MMM
SYMBOL
A,
B
D

e
h

i
L2

MIN

INCHES·
MAX

0.065
0.103
0.020
0.030
0.940
0.965
0.045
0.055
O.04OTYP
0.020TYP
0.055
0.045

MILUMETERS
MIN
MAX
1.65
0.51

2.62
0.76
23.88
24.51
1.14
1.40
1.02TYP
0.51TYP
1.14
1.40

12-32 PACKAGE INFORMATION

NOTES
1
2

NOTES

X450

I

III

1. Dimension controls the overall package thickness.
2. Applies to all 4 sides.
3. All terminals are gold plated.

Z-68
68-Lead Leaded Chip Carrier (Ceramic)

t--E
I DDDDDDI

"PIN1

1

F

8.

T=~

TOP VIEW

SYMBOL
A
b
D
8

E
F

G
K

L

INCHES
MIN
MAX
0.092 0.118
0.016 0.020
0.841 0.859
0.050BSC
0.940 0.960
0.040
0.695 0.705
0.025
1.200 1.220

MILLIMETERS
MIN
MAX
2.337
2.997
0.452
0.462
21.361 21.819
1.27 BSC
23.876 24.384
1.016
17.653 17.907
0.625
30.476 30.984

PACKAGE INFORMATION 12-33

P-20A
20-Lead Plastic Leaded Chip Carrier (PLCC)

SYMBOL
A
B
C
0

E
F
G
H
J
K

R
U

V
W

X
Y

12-34 PACKAGE INFORMA TION

INCHES
MIN
MAX

MIWMETERS
MIN
MAX

0.395
0.385
0.385
0.395
0.165
0.180
0.025
0.040
0.085
0.110
0.013
0.021
O.05OBSC
0.026
0.032
0.015
0.025
0.290
0.330
0.350
0.356
0.356
0.350
0.042
0.048
0.042
0.048
0.056
0.042
0.020

9.78
10.02
9.78
10.02
4.19
4.57
0.64
1.01
2.16
2.79
0.33
0.53
1.27BSC
0.66
0.81
0.38
0.63
7.37
8.38
8.89
9.04
9.04
8.89
1.07
1.21
1.07
1.21
1.42
1.07
0.50

P-28A
28·Lead Plastic Leaded Chip Carrier (PLCC)
YR

PIN 1
IDENTIFIER

o

PIN 1
IDENTIFIER
TOP
VIEW

BOTTOM
VIEW

SYMBOL
A
B
C
0
E

F
G

H
J
K

R
U

V
W
X
Y

INCHES
MIN
MAX

MILLIMETERS
MIN
MAX

0.495
0.485
0.485
0.495
0.165
0.180
0.025
0.040
0.085
0.110
0.013
0.021
0.050BSC
0.032
0.026
0.015
0.025
0.390
0.430
0.456
0.450
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
0.020

12.32
12.57
12.32
12.57
4.19
4.57
0.64
1.01
2.16
2.79
0.33
0.53
1.27BSC
0.66
0.81
0.63
0.38
9.91
10.92
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
0.50

PACKAGE INFORMATION 12-35

P-44A
44-Lead Plastic Leaded Chip Carrier (PLCC)

YR
PIN 1
IDENTIFIER

TOP
VIEW

SYMBOL
A
B
C
0
E

F
G
H
J
K
R
U
V
W
X
Y

12-36 PACKAGE INFORMATION

INCHES
MIN
MAX
0.685 0.695
0.685 0.695
0.165 0.180
0.025 0.040
0.085 0.110
0.013 0.021
0.050 BSC
0.026 0.032
0.015 0.025
0.650 0.656
0.650 0.656
0.650 0.656
0.042 0.048
0.042 0.048
0.042 0.056
0.020

MILLIMETERS
MIN
MAX
17.40 17.65
17.40 17.65
4.19
4.57
1.01
0.64
2.16
2.79
0.33
0.53
1.27 BSC
0.66
0.81
0.38
0.63
16.51 16.66
16.51 16.66
16.51 16.66
1.21
1.07
1.21
1.07
1.07
1.42
0.50

P-68A
68-Lead Plastic Leaded Chip Carrier

61

9

PIN 1 IDENTIFIER
PIN 1 IDENTIFIER

IJ

00000

DC

TOP

BOTTOM

VIEW

VIEW

:::JDDOODDO

~.----------------D,------------~
~·---------------D----------------~

SYMBOL

A
A,
b
b,

D
D,
D,
e

INCHES
MAX
MIN
0.169 0.175
0.104 TYP
0.017 0.019
0.027 0.029
0.885 0.995
0.950 0.954
0.895 0.925
0.050 TYP

MILLIMETERS
MIN
MAX
4.29
4.45
2.64 TYP
0.43
0.48
0.69
0.74
22.48 25.27
24.13 24.23
22.73 23.50
1.27 TYP

PACKAGE INFORMATION 12-37

J-28
28-Lead J-Leaded Chip Carrier

SYMBOL

INCHES
MAX
MIN

A

0.125

B

0.013

B,

0.017

0.021

3.175
0.330

0.534

0.432

0

0.489

0.491

12.196

12.704

0,

0.440

0.460

11.176

11.684

04

0.428

0.432

10.412

11.428

e
G

12-38 PACKAGE INFORMATION

MILLIMETERS
MAX
MIN

0.050 BSC
0.280

0.310

1.27 BSC
2.366

2.874

D-28A
28-Lead Side Brazed Ceramic DIP (Single Width)

SYMBOL
A

b
b,
c
D
E
E,

INCHES
MAX
MIN
0.200
0.014 0.023
0.030 0.070

0.008
0.220
0.290

0.38

0.310
0.320

5.59
7.37

37.59
7.87
8.13

2.29
3.18
3.81

2.79
5.08

7

0.38

1.52
2.49

3

0.090

0.110

0.125
0.150

0.200

Q

0.015

0.060
0.098

0.005

6
2,6

0.20

L
L,

S,

NOTES

0.015
1.480

e

S

MILLIMETERS
MIN
MAX
5.08
0.36
0.58
0.76
1.78

0.13

6
4
4

NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one.
2. The minimum limit for dimension b, may be 0.023"
(0.58 mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating plane
to the base plane.
4. This dimension allows for off-center lid, meniscus and
glass overrun.
5. Applies to all four corners.
6. All leads-increase maximum limit by 0.003" (0.08 mm)
measured at the center of the flat, when hot solder dip
lead finish is applied.
7. Twenty-six spaces.

5

PACKAGE INFORMATION 12-39

G-68A
68-Pin Grid Array

SEE NOTE1

"
a

-r--

17

,. @),.
0

0

0

0

•
0

• 0•

0

7

5

3

0

0

0

0

4

2

0

1

0

0

64

25

24

0

0

27

26

0

0

2.

2.

28

0

0

31

3.

0

0

0

..l!...-

0

0
62

0
6.

TOP VIEW

0
58

0

32

@)

3.

41

43

45

47

4'

MIN

MAX

A
A,

0.123
0.035

0.164
0.055

MIN
3.12
0.89

4.17
1.40

cf>b

0.016

0.021

0.41

0.53

cf>b,
D

0.045
1.080

0.060

1.14

1.52

2

1.110

27.43

28.19

6

e,

0.988

1.012

25.10

25.70

5

e.
e

0.788

0.812
0.105

20.02
2.41

20.62
2.67

5
4

0.190

3.68

4.83

MAX

NOTES
3
3

0

.3

0

.,

.
0

0

57

52

0

0

0

0

0

0

0

@)

38

4.

42

44

50

51

0

0

0

0

4'

48

0

0

0

0

NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead A 1.
2. The minimum limit for dimension cf>b, may be 0.023"
(0.58 mm) for all four corner leads only.
3. Dimension shall be measured from the seating plane
to the base plane.
4. The basic pin spacing is 0.100" (2.54 mm) between
centerlines.
5. Lead center when", is 0°; e, shall be measured at the
centerline of the leads.
6. All four sides.

0

0

3.

0

'7
'5

0
0
37

••0

56
54

0

35

@)

MILLIMETERS

SYMBOL

12-40 PACKAGE INFORMA TlON

0

I.

0

0

0.095
0.145

11

22

34

L.

0

tl

0

33

INCHES

0

23

r
1

e, e2

14

15

..

0

21

D

12

16

0

55

0
53

0

G-IOOA
lOO-Pin Grid Array

::
r
l

SEE NOTE1

'\

r---@

D

0

o

0

o

0

-11
0

0

0

ooo

0

0

0

:::

0

o

0

0

0

@

0

0

0

0

2

10

0

0

3

GUIDE
PIN
ONLY

0

0

4

0

0

5

0

0

0

6

0

0

0

7

0

0

8

0

0

9
10

000

D

e, e.

I..

-I

D

•
SEATING

A

0

0

0
0

0

0

o
o
o

0

0

o

0

TOP VIEW

0

0

000
0

0

0

0

000

0

0

0

0

11

0

12

0

0

0

'---@OOOOOOOOO

0

O@ 13

C

B

NMLKJHGFED

A

A,

I

I,

PLANE~~-~ ~-~-~-~ ~-~-~-~ ~-~-~~
--II-- Ij>b

SYMBOL

e

J..-

Ij>b,

INCHES
MAX
MIN

MILLIMETERS
MIN
MAX

0.169
0.055

0.64

4.29
1.40

0.020

0.41

0.51

1.02

1.40

A
A,

0.025

cl>b

0.016
0.040
1.308

0.055
1.332

e,

1.188

1.212

e.
e

0.988
0.095

L.

0.165

cl>b,
D

-./

NOTES
3
3

~k

NOTES
1. Index area; a notch or a lead one identification mark
is located adjacent to lead A 1.
2. The minimum limit for dimension cl>b, may be 0.023"
(0.58 mm) for all four corner leads only.

2

33.22

33.83

6

3. Dimension shall be measured from the seating plane
to the base plane.

1.024
0.105

30.18
25.10
2.41

30.78
26.01

5
5
4

4. The basic pin spacing is 0.100" (2.54 mm) between
centerlines.

0.190

4.19

4.83

2.67

5. Lead center when II is 0°; e, shall be measured at the
centerline of the leads.
6. All four sides.
7. Gold plating a minimum of 50,.. inches over 100,.. inches
ref. Thickness of nickel.

PACKAGE INFORMATION 12-41

II

223-Pin Ceramic Pin Grid Array

I

rr
l

ioII
-f----- .. -----~I

~@~~~~~~~~~~~~~~@~ :~16

000000000000000000
o0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0000
0000
0000
0000
0000
0000
0000
0000

l~

D

1"

I-

.1...1-

~

D

TOP VIEW

00000000000000000

At

ABC D E F G H J

~~tr~u~~~~~~~~~~i~tr~~
_11_
IT

..j

•

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

A

0.073

0.089

1.86

2.26

A,

0.045

0.055

1.14

1.40

ct>b
ct>b,
0

0.018 TYP
0.050 TYP
1.844

1.876

MIN

MAX

0.46 TYP
0.27 TYP

46.84

47.64

e,

1.700 TYP

43.18 TYP

e

0.100 TYP

2.54 TYP

L,
h

;,
;2

0.174

0.186

0.020 TYP

4.42

4.72

0.500TYP

1.209

1.225

30.71

31.91

1.134

1.150

28.80

29.20

NOTE
When socketing the CPGA Package, use of a
low insertion force socket is recommended.

12-42 PACKAGE INFORMATION

~~~~

r

0000
00007
0000
0000 6
0000
0000
000000000000000000

~@~~~~~~~~~~~~~~@~

-I

12

I

~~~~

15
14
13
12
11

K L M N P R STU

P-IOO
IOO-Lead Plastic Quad Flat Pack

e

SYMBOL

A
A,
b

c
E
E,
E2

e
L
Q
Q

MIN

INCHES
MAX

0.160
0.020
0.010
0.006
0.875
0.897
0.747
0.020
0.020
0.065

0.180
0.040
0.013
0.008
0.885
0.903
0.753
0.030
0.030
0.075
0.008

MILLIMETERS
MIN
MAX
4.06
0.51
0.25
0.15
22.23
22.78
18.97
0.51
0.51
1.65

4.57
1.02
0.33
0.20
22.48
22.94
19.13
0.76
0.76
1.91
0.20

PACKAGE INFORMATION 12-43

Z-IOO
IOO-Lead Ceramic Quad Flat Pack
.PIN

13~

-r---

-1 r- e

SYMBOL
A
A,
b

c
E
E,
e
L
Q

c

12-44 PACKAGE INFORMATION

INCHES
MAX
MIN
0.114 0.174
0.020 0.040
0.008 0.013
0.004 0.006
0.875 0.885
0.660 0.700
0.023 0.027
0.020 0.030
0.055 0.075
0.008

MILLIMETERS
MIN
MAX
2.91
4.41
0.51
1.02
0.20
0.33
0.10
0.15
22.23 22.48
16.76 17.78
0.58
0.69
0.51
0.76
1.40
1.91
0.20

223-Pin Plastic Pin Grid Array

1-1-----·, -----I-I
o 00 0

.,

0 0 0 0 0 0 0 0 00 0 0 0 0 18
O@O 0 0 0 00 00 0 0 0 0 0 O@O 17
000000000000000000 18
o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15
0000
0000 14
0000
0000 13
0000
0000 12
0000
000011
0000
0000 10
0000
TOP VIEW
0000 •
0000
0000 8
0000
00007
0000
0000 8
0000
0000 5
000000000000000000 4
000000000000000000 3
O@OOOOOOOOOOOOOO@O 2
00000000000000000 1
ABCDEFGHJ KLMNPRSTU

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

A

0.065

0.089

1.65

2.25

A,

0.077

",b

0.065
0.0164

1.65
0.42

0.50

",b,

0.046

0.054

1.17

1.37

D

1.856

1.864

47.14

47.34

43.48
2.84

0.0196

MIN

e,

1.688

1.712

42.88

e

0.088

0.112

2.24

L3

0.197 TYP

MAX

1.95

5.0TYP

h

0.012

0.020

0.3

0.5

j

0.803

0.811

20.4

20.6

NOTE

When socketing the PPGA package. use of a
low insertion force socket is recommended.

PACKAGE INFORMA TlON 12-45

12-46 PACKAGE INFORMATION

Appendix
Contents
Page

Appendix - Section 13 ......................................................... 13-1
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Technical Publications . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Worldwide Sales Directory . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . • . . . 13-8

lEI
APPENDIX 13-1

Ordering Guide
INTRODUCTION
This Ordering Guide should make it easy to order Analog Devices products, whether you're buying one Ie op amp, a multi-option
subsystem, or 1000 each of 15 different items. It will help you:

1. Find the correct part number for the options you want.
2. Get a price quotation and place an order with us.
3. Know our warranty for components and subsystems.
For answers to further questions, call the nearest sales office (listed at the back of the book) or our main office in Norwood, Mass.
U.S.A. (617-329-4700).

MODEL NUMBERING
In this reference manual many of the data sheets for products having a number of standard options contain an Ordering Guide. Use it
to specify the correct part number for the exact combination of options you want. Two model numbering schemes are used by Analog
Devices. The fIrst model numbering scheme is used for designating standard Analog Devices monolithic and hybrid products. The
second scheme is used by our Precision Monolithics Division (formerly PMI) as designators for its product line.
Figure 1 shows the form of model number used for our proprietary standard monolithic les and many of our hybrids. It consists of
an "AD" (Analog Devices) prefIx, a 3-to-s-digit number, * an alphabetic performance/temperature-range designator and a package
designator. One or two additional letters may immediately follow the digits ("A" for second-generation redesigned les, "DI" for
dielectrica1ly isolated CMOS switches, e.g., ADs36AJH, AD7s12DIKD).
Figure 2 shows a different numbering scheme used by our Precision Monolithics Division. This numbering scheme starts with a
prefIx which designates the device type and model number. It is then followed by a suffix consisting of alphabetic designators (as
applicable) to indicate additional functional designations or options and packaging options.

[NANN]
x~

~

ANALOG
DEVICES
PREFIX

L-

THREE-T().FIVE
DIGIT NUMBERS ~

1 OR 2 LETTERS PROVIDE
ADDITIONAL GENERAL INFORMATION
A: SECOND GENERATION
DI: DIELECTRJCALLY ISOLATED
Z: OPERATION ON ±12V SUPPLIES
PERFORMANCE-TEMPERATURE
RANGE DESIGNATOR'

D"CTO."/1)OC

(~M

t

BEST OVERALL
PERFORMANCE

1
-25"C OR -40"C
TO.85"C

{:

INCREASING
PARAMETRIC
PERFORMANCE

,

INCREASING
PERFORMANCE

BEST OVERALL
PERFORMANCE

1

PACKAGE OPTIONS:
D
E
F
G
H
J
M
N
P
Q

R
S
T
W
Y

Z

HERMETIC DIP, CERAMIC OR METAL
CERAMIC LEADLESS CHIP CARRIER
CERAMIC FLATPACK
CERAMIC PIN GRID ARRAY
HERMETIC METAL CAN
J-LEADED CERAMIC
HERMETIC METAL CAN DIP
PLASTIC OR EPOXY SEALED DIP
PLASTIC LEADED CHIP CARRIER
CERDIP
SMALL OUTLINE ''SO" PACKAGE
PLASTIC QUAD FLATPACK
TM2 STYLE PACKAGE
NON HERMETIC CERAMICIGLASS DIP
SlNGLE-IN-L1NE "SIP" PACKAGE
CERAMIC LEADED CHIP CARRIER

EXAMPLES:
AD521KCHIPS
AD7524AD
AD536ASHi883B
AD7512DIKD

INCREASING
PERFORMANCE

'MONOLITHIC CMOS CHIPS IN THE AD75XX SERIES
WERE FORMERLY DESIGNATED AD75XXlCOMICHIPS
AND AD75XXlMIUCHIPS AND MAY APPEAR ON PRICE
LISTS WITH THOSE DESIGNATIONS. CONSULT ANALOG
1-_ _ _ _ _ _ _ _ _ _ _ _--1 DEVICES FOR CURRENT PRICING OF AD75XX CHIPS.
,

BEST OVERALL
PERFORMANCE

Figure 1. Model-Number Designations for Standard Analog Devices Monolithic and Hybrid Ie Products. S, T and U
Grades have the Added Suffix, /8838 for Devices that Qualify to the Latest Revision of MIL-STD-883, Level 8.
·For some models, the combination [digitIletter] [two or three digits] is used instead of ADXXXX, e.g., 2580.
\

13-2 APPENDIX

DA -XX B1
MIL-ST0-883, CLASS B, REVISION C OPTION

DEVICE TYPE AND MODEL NUMBER
DEVICE TYPE:
ADC
AMP
BUF
CMP
DAC
JAN
LlU
MAT
MUX
OP
PKD
PM
REF
RPT
SMP
SW
SSM
TMP

-

ANALOG-TO-DIGITAL CONVERTER
INSTRUMENTATION AMPLIFIER
BUFFER (VOLTAGE FOLLOWER)
COMPARATOR
DIGITAL-TO-ANALOG CONVERTER
MIL-M-38510 SLASH SHEET
HIGH SPEED SERIAL DATA RECEIVER
MATCHED TRANSISTOR
MULTIPLEXER
PROPRIETARY OPERATIONAL AMPLIFIER
PEAK DETECTOR
SECOND-SOURCE, INDUSTRY SPECIFICATIONS
VOLT AGE REFERENCE
PCM LINE REPEATER
SAMPLE-AND-HOLD AMPLIFIER
ANALOG SWITCH
SOLID STATE MUSIC PRODUCT
TEMPERATURE SENSOR

DEVICE SPECIFlCAnoNS.

PACKAGE SUFFIX
PACKAGE TYPE:
H
J
K

BURN-IN OPTION

::~:::~:="~~B~:D:~=:NAT~EE
MODEL NUMBER AND THE ELECTRICAL GRADE. FOR

I

ELECTRICAL GRADE

r-

+_

6-LEAD TO-78 CAN
II-LEAD T0-99 CAN
10-LEAD TO-l00 CAN

o

NOT USED

P
PC

EPOXY DIP
PLASTIC LEADED CHIP CARRIER
16-LEAD CERAMIC DIP
20-LEAD CERAMIC DIP
2Q-POSITION LCC'
SMALL OUTLINE PACKAGE
28-LEAD CERAMIC DIP
28-POSITION LCC'
NOT USED
24-LEAD CERAMIC DIP
III-LEAD CERAMIC DIP
14-LEAD CERAMIC DIP
II-LEAD CERAMIC DIP

Q

PMI OFFERS MOST O"noDc, -25°'+85°C AND -4O"/+85~C

EXAMPLE, TO ORDER DACo08EQ WITH BURN-IN, THE
PART NUMBER IS DAc-oaSIEQ.

PMI-55°C TO +125°C DEVICES ARE AVAILABLE
WITH MlL·STD-883, CLASS B SCREENING AS
STANDARD PRODUCTS. TO ORDER AN 883 PART,
SIMPLY ADD THE DEstGNAnON 1883 TO THE PART
NUIIBER. FOR EXAMPLE, THE DAc.oeAQ, SCREENED
TO THE 883 REQUIREMENTS WOULD BE ORDERED
AS A DACOBAQl8B3. CONTACT FACTORY FOR 883

R
RC
S
T
TC
U
V
X
Y
Z

*AYAILABLE WITH IIIL"ST~ PROCESSING

ONLY.

SELECT ELECTRICAL GRADE
FROM DATA SHEET.

Figure 2. Precision Monolithics Division's Product Designations

ORDERING FROM ANALOG DEVICES
When placing an order, please provide specific information regarding model type, number, option designations, quantity, ship-to and
bill-to address. Prices quoted are list; they do not include applicable taxes, customs, or shipping charges. All shipments are F .O.B.
factory. Please specify if air shipment is required.
Place your orders with our local sales office or representative, or directly with our customer service group located in the Norwood
facility. Orders and requests for quotations may be telephoned, sent via fax or telex, or mailed. Orders will be acknowledged when
received; billing and delivery information is included.
Payments for new accounts, where open-account credit has not yet been established, will be C.O.D. or prepaid. Analog Devices' minimum order value is two hundred fifty dollars ($250.00).
When prepaid, orders should include $2.50 additional for packaging and postage (and a 5% sales tax on the price of the goods if you
are ordering for delivery to a destination in Massachusetts).
You may also order Analog Devices parts through distributors. For information on distributors, please see pages 13-8 and 13-9 at the
back of this volume.
WARRANTY AND REPAIR CHARGE POLICIES
All Analog Devices, Inc., products are warranted against defects in workmanship and materials under normal use and service for one
year from the date of their shipment by Analog Devices, Inc., except that components obtained from others are warranted only to the
extent of the original manufacturers' warranties, if any, except for component test systems, which have a ISO-day warranty, and
f1MAC and MACSYM systems, which have a 90-day warranty. This warranty does not extend to any products which have been subjected to misuse, neglect, accident, or improper installation or application, or which have been repaired or altered by others. Analog
Devices' sole liability and the Purchaser's sole remedy under this warranty is limited to repairing or replacing defective products.
(The repair or replacement of defective products does not extend the warranty period. This warranty does not apply to components
which are normally consumed in operation or which have a normal life inherently shorter than one year.) Analog Devices, Inc., shall
not be liable for consequential damages under any circumstances.
THE FOREGOING WARRANTY AND REMEDY ARE IN LIEU OF ALL OTHER REMEDIES AND ALL OTHER
WARRANTIES, WRITTEN OR ORAL, STATUTORY, EXPRESS, OR IMPLIED, INCLUDING ANY WARRANTY
OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
APPENDIX 13-3

II

Technical Publications
Analog Devices provides a wide array of FREE technical publications. These include Data Sheets, Catalogs, Application Notes
and Guides and four serial publications: Anawg Productwg, a
digest of new-production information; DSPatch·N , a newsletter
about digital signal-processing (applications); Anawg Briejings1385 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

Model

Page

_ADl671 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2, 10-6
-A01674 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
_A01851 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
A01856 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
A01860 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
-A01861 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
-A01862 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
_AOI864 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
-A01865 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55
_A01866 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5~5
-A01868 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5~7
-A01876 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
_A01878 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
_A01879 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
A01885 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
A05200 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
A05210 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
A05240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
A05539 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-153
A07111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
A07118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
A07224 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10,:.11
A07225 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
A07226 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
A07228 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
-A07228A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
-A07233 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
A07237 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
_A07242 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
-A07243 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
_A07244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
A07245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
-A07245A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
A07247 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
A07248 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
-A07248A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
A07524 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
A07528 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
A07533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
A07534 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
A07535 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
A07536 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
A07537 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
A07538 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
A07541A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
AD7542 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
A07543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
A07545 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
A07545A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
A07547 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
A07548 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
A07549 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
-A07564 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
_A07568 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
A07569 . . . . . . . . . . . . . • . . . . . . . . . . . . . 10-2, 10-11

Model

Page

A07572 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
-A07572A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
A07574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
A07575 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
A07576 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
1\.07578 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
A07579 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
A07580 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
A07581 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4, 10-8
A07582 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4, 10-8
-A07586 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
A07628 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
A07669 . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2, 10-13
A07672 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
-A07701 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
-A07703 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
-A07710 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
-A07711 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
-A07712 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
-A07713 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
-A07716 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
A07769 . . . . . . . . . . . . . . . . . . . . . . . 10-2, 10-8, 10-13
-A07776 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
-A07777 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
-A07778 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
A07820 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
A07821 ., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
A07824 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2; 10-8
A07828 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2, 10-8
-A07837 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
A07840 . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . 10-11
A07845 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
A07846 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
-A07847 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
A07848 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
A07850 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
-A07868 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
-A07869 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
A07870 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
A07871 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
A07872 . . . . . . . . . . . . . . . . • . . . . . . . . . . . • . . . 10-3
-A07874 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2, 10-8
-A07875 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
-A07876 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
A07878 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
-A07880 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
_A07884 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
-A07885 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
-A07886 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2, 10-6
-A07890 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2, 10-8
-A07891 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2,10-8
-A07892 . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . 10-2
_A07893 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
A09000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
A09002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

eNew product since publication of the most recent Databooks.

INDEX 14-5

II

Model

. Page

AD9003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2, 10-6
eAD9005A . . . . . . • . . . . . . . . . . . . . . . • . . . . . . . . 10-6
AD9006 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
AD9012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . 10-6
eAD9014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
AD9016 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
eAD9020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
AD9028 . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . 10-6
eAD9032 . . . . . . . . . . . • • . . . . . . . . . . . . . . . . . . . 10-6
eAD9034 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
AD9038 . . . . . . . . . . . . '.' . . . . . . . . . . . . . . . . . . 10-6
eAD9040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
AD9048 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
eAD9058 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
eAD9060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
AD9300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41
AD9610 . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16, 10-17
AD9617 . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16, 10-17
AD9618 . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16, 10-17
AD%20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
AD%30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
AD9701 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
AD9712 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • 10-9
eAD9712A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
AD9713 . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . 10-9
eAD9713A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
eAD9720 . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
eAD9nl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
AD9768 . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
AD75004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
eAD75069 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
AD ADC71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
AD ADCn .............................. 10-5
AD ADC80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
AD ADC84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
AD ADC85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
eADC-170 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
ADC-908 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
ADC-910 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
ADC-912 . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . 10-4
eADC-912A . . . . . . . . . . . . . . . • . . . . . . . . . . . . . • 10-4
ADC1140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
AD DAC71 . . . . . . . . . . . . . . . . . . . . . . . . 10-10, 10-11
AD DACn ........................ 10-10, 10-11
AD DAC80 . . . . . . . . . . . . . . . . . . . . . . . . 10-10, 10-11
AD DAC85 . . . . . . . . . . . . . . . . . . . . . . . . 10-10, 10-11
AD DAC87 . . . . . . . . . . . . . . . . . . . . . . . . 10-10, 10-11
eADDS-21XX-SW . . . . . . . . . . . . . . . . . . . . . . . . • . 9-9
eADDS-210XX . . . . . . . . . . . . . . . . . . . . . . . . . • . . 9-11
eADDS-2100A-ICE . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
eADDS-2101-EZ . . . . . . . . . . . . . . . . . . . . . . . . . • . . 9-5
ADDS-2101-ICE . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
AD OP-07 . . . . . . . . . . . . . . . . . . . . . . . . . 10-18, 10-20
AD OP-27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
AD OP-37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
eNew product since publication of the mQst recent Databooks.

14-6 INDEX

Model

Page

ADSP-2100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
ADSP-2100A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
ADSP-2101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
eADSP-2105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-23
eADSP-2111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29
eADSP-21020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33
eADVI01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
ADV453 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
ADV471 . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . 6-19
eADV473 . . . . . . . . . . . . . . . . . . . . . . . . . . . , ... 10-12
eADV475 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
ADV476 . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . 6-9
eADV477 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
ADV478 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
eADV7120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
eADV7121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37
eADV7122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37
eADV7141 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49
eADV7146 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49
eADV7148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49
eADV7150 . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . 10-12
eADV7151 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
eADV7152 .. , . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
DAC-02/03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
DAC-05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
DAC-06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
DAC-08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
DAC-I0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
eDAC-16 . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
DAC-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
DAC-86 . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
DAC-88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
DAC-89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
DAC-I00 . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . 10-9
DAC-21O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
DAC-312 . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . 10-10
DAC-888 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
DACI136 . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . 10-12
DACI138 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
DAC-I408A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
DAC-1508A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
DAC-8012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
DAC-8043 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
DAC-8143 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
DAC-8212 . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . 10-15
DAC-8221 . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . 10-15
DAC-8222 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
DAC-8228 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
DAC-8229 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
DAC-8248 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
DAC-8408 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-49
DAC-8412 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
eDAC-8413 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
DAC-8426 . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . 10-13
DAC-8800 . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . 8-63

Model

Page

DAC-SS40 ......... . . . . . . . . . . . . . . . . . . . . . S-77
eDAC-SS41
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-S7
DAS1152
DASI153 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
DAS1157 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
DAS115S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
DAS1159 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
MAT-04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
OP-OI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
OP-02
., . . . . . . . . . . . . . . . . . . . . . . . . 10-17, 10-20
OP-04 ...... :: . . . . . . . . . . . . . . . . . . . . . . . . 10-20
OP-05
. . . . . . . . . . . . . . . . . . . . . . . . 10-20
OP-07 ::::: . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
OP-09.
. . . . . . . . . . . . . . . . . . . . .. 1001S, 10-20
Op-to

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20

OP-11 . '. '. '. '. '. '. '. . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
OP-14 . . . . . . . . : : : : : : : . . . . . . . . . . . . . 10-20, 10-22
OP-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20, 10-23
01>-16 . . . . . . . . . . .
. . . . . . . . . . . . . 10-17, 10-22
OP-17
. . . . . . . . . . . . . . . . . 10-17, 10-22
OP-20 : : : : : : : : . . . . . . . . . . . . . . . . . . . . 10-17, 10-22
OP-21 . . . . . .. . . . . . . . . . . . . . . . . . . . . 10-19, 10-21
OP-22 . . . . . . . : . . . . . . . . . . . . . . . . . . . . 1001S, 10-21
OP-27 . . . . . . . ::::::: . . . . . . . . . . . . . 10-19, 10-21
. . . . . . . . . . . . . . . . . . 2-169
OP-32
OP-37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19 10-21
OP-41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : 2-lSI
OP-42
. . . . . . . . . . . . . . . . . . . . . 10-19, 10-21 10-22
OP-43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . :. 10-17
OP-44 ........................... 10-19, 10-21, 10-22
. . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
OP-50 . . . ..
OP-61
. . . . . . . . . . . . . . . . . . . . . . . 10-16, 100iS
OP-64 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-193
OP-77
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-211
OP-SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . Io-IS 10-20
OP-90 ........... . . . . . . . . . . . . . . . . . 10-20 ' 10-22
OP-97 '. '. '. '. '. '. '. '. . . . . . . . . . . . . . . . . . . . . Io-IS: 10-21
. . . . . . . . . . . . . . . Io-IS, 10-20, 10-21
OP-I60 . . . .
OP-I77
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-225
OP-200 . . . . . . . . . . . . . . . . . . . . . . . . . . . Io-IS 10-20
OP-207 . . . . . . . . . . . . . . . . . . . . . . 1001S, 10-21' 10-23
OP-215 . . . . . . . . . . . . . . . . . . . . . . . . . . . 100lS: 10-23
OP-220 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
OP-22 I . . . . . . . . . . . . . . . . . . . . . Io-IS, 10-21 10-23
OP-227 :::::: . . . . . . . . . . . . . . . . Io-IS, 10-21: 10-23
OP-249
. . . . . . . . . . . . . . . . 10-16, 10-18 10-23
OP-260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : 2-249
OP-270 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-267
OP-271 ............................ 10-16, 1001S, 10-23
OP-275
. . . . . . . . . . . . . . . . . . . . . . . . . . 2-2S7
eOP-2S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-297
OP-290 : . . . . . . . . . . . . . . . . 10-17, 10-20, 10-21 10-23
OP-297 . . . . . . . . . . . . . . . . . . . . . 100lS, 10-21' 10-23
OP-400 ::::::: . . . . . . . . . . . . . . . 1001S, 10-21: 10-23
OP-420
. . . . . . . . . . . . . . . 1001S, 10-21 10-22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : 10-22

Model
OP-42 I
Page
OP-470 . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 10-22
OP-471 ............................... 10-16, 10-19: 10-22
. . . . . . . . . . . . . . . . . . . . . . . 2-299
eOP-482
OP-490 ......................... 10-17, 10-20, 10-21, 10-22
OP-497
. . . . . . . . . . . . . . . . . . . 10-21, 10-22
PKD-OI . . . . . . . . . . . . . . . . . 1001S, 10-20, 10-21 10-22
PM-14S/248 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' . 7-33
PM-155A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
PM-156A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
PM-157A . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 10-22
PM-IOOS ............................... 10-17: 10-22
PM-I0l2
. . . . . . . . . . . . . . . . 10-18, 10-20 10-21
ePM-6012 : : : : : : : : : : : . . . . . .. . .. 10-18, 10-20: 10-21
PM-7224
. . . . . . . . . . . . . . . . . . . . 10-10
PM-7226A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
PM-7524 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
PM-7528 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
PM-7533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
PM-7541A' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
PM-7542 . : : : : . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
. . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
PM-7543
PM-7545 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
PM-754S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
PM-7574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
PM-762S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
PM-7645 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
SSM-20B' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
SSM-2014 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51
SSM-2015
. . . . . . . . . . . . . . . . . . . . . . . 7-57
SSM-2016 '.' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-59
SSM-2017 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-65
SSM-20IS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-73
SSM-2024 ........ . . . . . . . . . . . . . . . . . . . . . . . 7-S1
SSM-2110 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-93
SSM-2120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-99
SSM-2122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-111
SSM-2125 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-111
SSM-2126 . : : : . . . . . . . . . . . . . . . . . . . . . . . . . . 7-123
SSM-2131
. . . . . . . . . . . . . . . . . . . . . . . . . . 7-123
SSM-2B4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-315
SSM-2B9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-327
SSM-2141 . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . 2-333
SSM-2142 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-133
SSM-2143 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-139
SSM-221O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-145
SSM-2220 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-147
SSM-2402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-159
eSSM-2404 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-167
SSM-2412 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-177
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-167

II

eNewproduct since
.
publication of the most recent Datab00k s.

INDEX 14-7

PUBLICATION TEAM
Project Leader: Dan Parks
Production Coordinator: Marie Etchells
Cover Design: Foster Design Group
Production Team: Marie Barlow, Lea Cook, Joan Costa,
Elinor Fagone, Kathy Hurd, Ernie Lehtonen, Carol Libbey,
Kristin Nelson, Peter Sanfa~on,
Technical Contributors: Don Brockman, Joe Buxton,
Bob Clarke, Paul Errico, David Fair, Bob Fine,
Walt Heinzer, Arman Naghavi, Dan Parks, Rene Sierra,
Steve Sockolov, Jerry Whitmore

r.ANALOG
a...OEVICES
WORLDWIDE HEADQUARTERS
One Technology Way, P.O. Box 9106, Norwood, MA 02062 - 9106, U.S.A.
Tel: (617) 329 - 4700, Fax: (617) 326 - 8703, Telex: 924491
Complete Worldwide Sales Office Directory Can Be Found On Pages 13 - 8 And 13 - 9.
PRINTED IN U.S.A.
G1591a - 16 - 5/92
$12.95



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